diff --git a/COPYING b/COPYING index ae47afc7cac37d3caa90445c0be39eab9b7d0003..62662be709ba2df3c42004783f0d3ac573681be3 100644 --- a/COPYING +++ b/COPYING @@ -14,7 +14,7 @@ individual files will vary): /************************************************************************* * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without diff --git a/ChangeLog b/ChangeLog index 3bceb86d3bf3795ceaebe67465ed8db2e192c72e..055d540aeafde0c8c9216b0883fea13828185dc2 100755 --- a/ChangeLog +++ b/ChangeLog @@ -14350,7 +14350,7 @@ * drivers/lcd/st7565.c: Use ST7565_POWERCTRL_INT instead of ST7565_POWERCTRL_BRF. From Masayuki Ishikawa (2017-03-21). * SMP Kconfig: Change the minimum SMP_NCPUS to 1. From Masayuki - Ishikawa (2017-03-xx). + Ishikawa (2017-03-21). * SMP: Setting CONFIG_SMP_NCPUS=1 should only be permitted in a debug configuration (2017-03-22). * Clicker2-STM32: Create src/, kernel/, and scripts/ directories @@ -14457,7 +14457,7 @@ Assis (2017-03-27). * AT86RF23x: Clean-up, standardize lower half interface. Take advantage of new OS features for interrupt parameter passing - (2017-03-xx). + (2017-03-27). * MRF24J40: Take advantage of new OS features for interrupt parameter passing (2017-03-27). * lcd/: PCF8574 backpack logic needs to include poll.h @@ -14781,7 +14781,7 @@ * STM32F0: Add basic support for STM32F07x family (2017-04-17). * STM32F0: Move enabling of GPIO peripherals form UART setup to clockconfig. This is not a UART function. It is needed by all - peripherals (2017-04-xx). + peripherals (2017-04-17). * STM32F0: Add logic to enable other USARTs. No UART4/5. Rather USART4/5 (2017-04-17). * STM32F7: Warn if no DMA2 configured when using ADC with DMA. Also @@ -14960,7 +14960,7 @@ * Nucleo-F072RB: Add support for the I2C driver used by I2C tools (2017-04-20). * drivers/i2c: Fix compile issus if CONFIG_DISABLE_PSEUDOFS_OPERATIONS - is enabled (2017-04-xx). + is enabled (2017-04-30). * STM32F0 I2C: Update driver to use the standard interrupt parameter passing logic (2017-04-30). * STM32F0 I2C: Pin definitions should specify open drain (and probably @@ -15601,7 +15601,7 @@ a rejected association response frame. From Anthony Merlino (2017-06-15). * Rename configs/mrf24j40-radio to mrf24j40-mac (2017-06-15). - * clicker2-stm32: Add a configuratino that will, eventually, be used + * clicker2-stm32: Add a configuration that will, eventually, be used for 6loWPAN testing (2017-06-15). * Fix a typo. And typo in Kconfig file is reflect in all defconfig files (2017-06-15). @@ -16728,4 +16728,1434 @@ was not freeing resources when a wait was completed. From Boris Astardzhiev (2017-09-04). -7.23 2017-xx-xx Gregory Nutt +7.23 2017-12-04 Gregory Nutt + + * STM32L4: ADC, Kconfig small changes: + - STM32L4 ADC: port analog watchdog ioctls from the Motorola MDK + - STM32L4: Kconfig: add some L486 and L496 chips, remove duplicates + From Juha Niskanen (2017-09-06). + * 6LoWPAN: Correct an error in uncompressing multicast address + (2017-09-08). + * sem_open() should return SEM_FAILED on any failures. This is change + in the POSIX specification since the original sem_open() was written + so many years ago (2017-09-08). + * STM32: Add logic for enabling wakeup pins. From Oleg Evseev + (2017-09-08). + * Update/fix last commit: On some STM32's, the CSR regiser is 18 vs. 16 + bits wide. Need to use 32-bit register accesses (2017-09-08). + * 6LoWPAN: I believe, based on RFC review, that with the last multicast + change, the NuttX 6LoWPAN is now compliant with RFC 6282 (2017-09-08). + * arch/arm/Kconfig: Add more classic ARM11 architecture selections + (2017-09-09). + * 6LoWPAN/Radio: Rename radio property sp_pktlen to sp_framelen. Add + 6LoWPAN utility to get the max frame length (not yet hooked in) + (2017-09-10). + * 6LoWPAN: Remove the option to disable fragmentation support. Two + reasons: (1) First fragementation is always required because IPv6 + requires an MTU of 1280 bytes. The is no application use case that can + work without fragmentation support. And (2) it greatly reduces the + complexity of the code (2017-09-10). + * net/sixlowpan: Remove CONFIG_NET_6LOWPAN_FRAMELEN. In this case where + multiple radios are supported, this may not be a constant. 6LoWPAN now + always queries the driver to get the maximum frame length (2017-09-10). + * drivers/smps.c: fix error messages. From Mateusz Szafoni (2017-09-10). + * configs/stm32f334-disco: beginning of lower half driver for high power + LED (powerled). From Mateusz Szafoni (2017-09-10). + * Misc STM32 fixes + - stm32f33xxx_hrtim.h: fix definition + - stm32_hrtim: fix pclk calculation + - stm32_hrtim.c: cosmetics + - add upper-half driver for high power LED driver (powerled) + From Mateusz Szafoni (2017-09-10). + * drivers/video/fb.c: Add framebuffer character device (2017-09-11). + * drivers/video/fb.c: Add support for LCD drivers that use a simulated + framebuffer and must receive explicit notification when there is an + update to a region in the framebuffer (2017-09-11). + * configs/lc823450-xgevk: Enable ADC and watchdog driver. From Masayuki + Ishikawa (2017-09-12). + * arch/arm/src/lc823450: Conform to the NuttX coding style, merge the + latest fix in lc823450_rtc.c, add ADC driver, add watchdog driver. From + Masayuki Ishikawa (2017-09-12). + * net/sock: recvfrom: Fix double leave_cancellation_point on error + path. From Jussi Kivilinna (2017-09-12). + * net/socket: Do not enter cancellation point in psock_send() as this + is already done in send(). From Jussi Kivilinna (2017-09-12). + * net/socket: send: verify that sockfd is valid, fixes assert when using + send on closed socket. From Jussi Kivilinna (2017-09-12). + * drivers/video/fb.c and include/nuttx/video.fb.h: Some improvements + and fixes from early testing sith the sim/fb cnofiguration (2017-09-12). + * sim/configs/fb: Add a configuration for non-graphical testing of the + frambuffer character driver using apps/example/fb (2017-09-12). + * Rename CONFIG_VIDEO_DEVICES to CONFIG_DRIVERS_VIDEO to conform better + to the evolving configuration naming standard (2017-09-12). + * Rename CONFIG_AUDIO_DEVICES to CONFIG_DRIVERS_AUDIO to conform better + to the evolving configuration naming standard (2017-09-12). + * stm32: stm32 alt I2C ensure proper error handling. Injecting data + errors would cause the driver to continually reenter the isr with BERR + an RxNE. This fix allows the error to be cleared and propagated to the + waiting task. From David Sidrane (2017-09-12). + * stm32x i2c fixes, stm32: Fix coding standard error, stm32f7 I2C: fixed + typo in comment. From David Sidrane (2017-09-13). + * STM32 Tickless: Fixes compilation error when timer info/debug messages + are enabled. From Rajan Gill (2017-09-13). + * net/: Fix some errors found by Coverity. + * STM32/STM32 F7: Fix some errors found by Coverity (2017-09-13). + * drivers/video/fb.c: File offset is in units of bytes, not pixels + (2017-09-14). + * drivers/lis3dsh.c: Added the argument parameter (FAR void *arg) to + the interrupt handler provided by the LIS3DSH driver to fit the + definition for ISRs in xcpt_t. Changed the check for working queue + availability in lis3dsh interrupt handler to use work_available() and + not crash in case of an overrun. From Florian Olbrich (2017-09-14). + * configs/stm32f4discover: Added initialization code and Kconfig entries + to set up the LIS3DSH accelerometer driver on STM32F4Discovery rev. C + boards and attach the associated interrupt callback. From Florian + Olbrich (2017-09-14). + * Added initialization code and Kconfig entries for LIS3DSH + accelerometer on STM32F4Discovery + associated changes to LIS3DSH + driver. From Florian Olbrich (2017-09-14). + * LPC31xx: Change naming of some global variables to match coding + standard (2017-09-14). + * wireless/ieee802154/: Moves MAC802154IOC from ieee802154_ioctl.h and + renames ieee802154_ioctl.h to ieee802154_device.h since it only contains + types relevant to the MAC char device now. From Anthony Merlino + (2017-09-15). + * wireless/ieee802154: Adds support for receiving MAC events via IOCTL + through socket interface. Other small fixes and cleanup. From Anthony + Merlino (2017-09-15). + * drivers/wireless: Adds XBee S2C (802.15.4 firmware) support. XBee + driver emulates mac802154 interface. From Anthony Merlino (2017-09-15). + * sched/waitpid.c: Eliminate a warning detected by GCC 6 (2017-09-15). + * drivers/xbee: Fixes a few warnings + - drivers/xbee: Fixes a few warnings + - configs/clicker2-stm32: Updates sections about i8sak usage in the + README + From Anthony Merlino (2017-09-15). + * STM32 Tickless: The attached patch removes the restriction to 16bit + counts when a 32bit timer is used for the new tickless on the stm32. As + it is now, the restriction is very limiting, especially if one wants + high granularity and large achievable intervals and has the hardware + (namely the 32bit timers) available. From Rajan Gill (2017-09-16). + * configs/open1788: Initialization now follows the pattern of other + boards. Add initialization of fb driver. Add a configuration for + testing the framebuffer driver (2017-09-16). + * drivers/video: fb driver now clears framebuffer initially. Eliminates + (or minimizes) initial garbage on the display (2017-09-16). + * SAMV71-XULT: Add support for fb_driver (2017-09-17). + * drivers/lcd: Add suppose for a generic front-end that will convert + any LCD driver into a framebuffer driver (2017-09-17). + * SAMv71-XULT: Add a configuration to test the LCD framebuffer driver. + Not quite yet working properly (2017-09-17). + * configs/stm3210e-eval: Rename stm32_appinit.c to stm32_bringup.c so + that the start up logic is compatible with other, new boards. Bring in + new stm32_appinit.c, add board_initialize(), add support for FB + character driver (2017-09-17). + * configs/stm3240g-eval: Rename stm32_appinit.c to stm32_bringup.c to + better match other architectures. Replace the old-style stm32_appinit.c + with tne new one from the STM32F4-Discovery. Add a configuration for + testing the FB character driver at drivers/video/fb.c using the LCD + frame driver front end at drivers/lcd/lcd_framebuffer.c. Appears to be + fully functional (2017-09-17). + * netinet/in.h: Add missing IN6_IS_ADDR_V4COMPAT macro (2017-09-18). + * configs/stm32f4discovery: Update README. Add summary of differences + with the newest STM32F407G-DISC1 part. Remove a lot of old discussion + that is really no longer helpful (2017-09-18). + * Networking: sockgetname() files need to include udp/udp.h and + tcp/tcp.h or otherwise NET_UDP_HAVE_STACK and NET_TCP_HAVE_STACK are + undefined and the logic is never compiled. Noted by Anthony Merlino + (2017-09-18). + * Add driver for APA102 LED controller. These LEDs are used on LED + Strips and are controlled over SPI (2017-09-18). + * configs/stm32f103-minimum: Add board support for APA102 driver. From + Alan Carvalho de Assis (2017-09-18). + * sched/env_dup.c: Fix an error in the duplication of the child tasks + environment in the special case where the parent's environment was + created, but then all of the variables were unset. In that case, there + is still an allocation in place but the size of the allocation is zero. + This case was not being handled correctly when a child task attempts to + create its environment and inherit the zero-size partent environment. + Noted by Anthony Merlino (2017-09-18). + * STM32L4 DFSDM: add peripheral, DAC, TIM: small changes + - STM32L4 DAC: do not configure output pin if it is not used + - STM32L4 TIM: fix compilation of timers with complementary outputs + when not PWM_MULTICHAN + - STM32L4 DFSDM: peripheral for digital filters for sigma-delta ADCs + Initial version. Timer trigger support is not completed and there is + some issue with DMA. + From Juha Niskanen (2017-09-19). + * stm3240g-eval: Remove some bad conditional compilation (2017-09-19). + * Networking: IPv4 getsockname(): Fix a typo that can cause a compile + error (2017-09-19). + * viewtool-stm32f107: Enable NSH arch-specific initialization. Rename + stm32_appinit.c to stm32_bringup.c for consistency with other boards. + Replace old stm32_appinit.c (now stm32_bringup.c) with 'standard' + stm32_appinit.c from the STM32F4-Discovery. Add CONFIG_BOARD_INITIALIZE + logic to stm32_boot.c. Add support to auto-mount the procfs file system + (2017-09-19). + * Networking: Add implementation of logic for SIOCGIFCONF and + SIOCGLIFCOF IOCTL commnds (2017-09-19). + * Networking: drivers/net/loopback.c: Eliminate a warning. + net/netdev/netdev_ifconfig.c: Was not returning all of the address info + (2017-09-19). + * STM32L4 ADC, DFSDM: add routing of ADC data to DFSDM filters. From + Juha Niskanen + - configs/nucleo-l496zg: add DFSDM initialization + - STM32L4 ADC: add option for routing ADC data to DFSDM, fix DFSDM + DMA (2017-09-20). + * SIOCGIFCONF and SIOCGLIFCONF IOCTL commands should only report on + network adatpors in the UP state (2017-09-20). + * In some cases, packets are still not sent behind the router. I found + that NuttX sends the ARP requests not to the router but to the target. + Mistake in file net/route/netdev_router.c. From Aleksandr Kazantsev + (2017-09-20). + * stm32: stm32f40xxx I2C ensure proper isr handling. Injecting data + errors that causes a STOP to be perceived by the driver, will + continually re-enter the isr with SB not set and BTF + and RxNE set. This changes allows the interrupts to be cleared and + propagates a I2C_SR1_TIMEOUT to the waiting task. From David Sidrane + (2017-09-21). + * include/nuttx/net/net.h: Add missing semicolon in prototype. Fixes + error in certain combinations of configuration options. From Pavel Pisa + (2017-09-21). + * drivers/pipes: pipe_common: Fix writing large buffers not triggering + POLLIN for reader poll. From Jussi Kivilinna (2017-09-21). + * drivers/usbdev: Add support for RX flow control to the CDC/ACM driver + (2017-09-22). + * STM32 Serial: Fix some incorrect conditional compilation (2017-09-23). + * drivers/usbdev: Add support for flow control TERMIOs in CDC/ACM + driver (2017-09-23). + * drivers/usbdev: CDC/ACM should reset all 'irregular' notifications to + zero after sending the SerialState packet (2017-09-23). + * drivers/usbdev: Fix some bad conditional logic (2017-09-23). + * Fixes several errors preventing icmpv6_radvertise.c from being + compiled. Fixes conversions to network byte order (namely vlifetime, + plifetime, mtu). IPv6 source address is set to link-local IP address + instead of the address in the netdev structure. This is in compliance to + RFC 4861. RA didn't work on Linux before this change. Finally, router + prefix and prefix length are derived from the IPv6 address and netmask + in the netdev structure. This seems to make more sense than using a + predefined, separate prefix from the config. From Sakari Kapanen + (2017-09-24). + * drivers/usbdev/usbdev: Add RNDIS-over-USB driver. From Sakari Kapanen + (2017-09-24). + * net/igmp/igmp_send.c: Fix incoming IGMP checksum calculation. From + Louis Mayencourt (2017-09-25). + * Fixes for problems found by Coverity in the nuttx repository: + - net/socket/recvfrom.c: Check fromlen integrity before using it. + - net/socket/net_sockets.c: Always check for valid psock before using. + - net/tcp/tcp_send_unbuffered.c: Avoid using psock beforing + checking its integrity. + - sched/timer/timer_create.c: Fix watchdog resource leak if cannot + allocate a new timer. + From Bruno Herrera (2017-09-25). + * drivers/usbdev/Kconfig: Add comments in regard to RNDIS selection + (2017-09-25). + * configs/nucleo-f410rb: Add support for the nucleo-F410RB board. From + Gwenhael Goavec-Merou (2017-09-25). + * STM32 L4: Add SDMMC driver. From Miha Vrhovnik (2017-09-26). + * Nucleo-L496ZG: Add support for SDMMC driver. From Miha Vrhovnik + (2017-09-26). + * drivers/usbdev/cdcacm.c: Avoid using priv before checking its + validity. From Juha Niskanen (2017-09-26). + * drivers/usbdev/cdcacm.c: Change design for queuing RX packets that + cannot be processed. Previous design had a logic problem that could + cause data loss (2017-09-26). + * drivers/usbdev/cdcacm.c: Add a failsafe time to assure that the RX + pending queue cannot stall indefinitely. I can imagine a corner case + where the serial driver's RX buffer is full and it stops accepting data + and where all of the read requests are queued and there is not event to + restart RX processing. I am not sure that that scenario can really + happen, but the failsafe timer gives me peace of mind (2017-09-26). + * Build break fix: define PWM_TIM2_CH1CFG for channel 1 PWM. From + Tomasz Wozniak (2017-09-26). + * Fixed directory unlocking in tmpfs_opendir. From Dmitriy Linikov + (2017-09-27). + * drivers/usbdev/cdcacm.c: Add some missing logic when flow control is + disabled. Also make sure that the flowcontrol and rxint can handle + being re-entered when cdcacm_release_rxpending() is called (2017-09-27). + * drivers/usbdev/cdcacm.c: Fix confusion between flow control being + enabled and being active. Different things (2017-09-27). + * drivers/usbdev/cdcacm.c: Change ordering of some operations to avoid + races; Add missing uppder watermark logic that is normally in + serial_io.c but must be duplicated in cdcacm.c (2017-09-27). + * net/route: Permit IPv4 and IPv6 routing tables to be of different + sizes (2017-09-27). + * ROMFS for STM32F4 Discovery board. From Tomasz Wozniak (2017-09-28). + * STM32 PWR: Adds stm32_pwr_getsbf and stm32_pwr_getwuf functions that + return the standby flag and the wakeup flag PWR power control/status + register. From Oleg Evseev (2017-09-28). + * net/arp/arp_out.c: Fix IGMP Ethernet address computation. From Louis + Mayencourt (2017-09-28). + * net/route: Adds support for read-only routing tables. Prior to this + change, routing tables were only support in RAM and had to be + initialized with explicit logic to add the necessary routes to the + routing table. With this change, routes may be defined in the + pre-initialized, read-only routing table provided by the board-specific + logic + + This would be particularly useful, for example, in the case where + there is only a single network adaptor and you want all output packets + to go to the single adaptor in all cases. So for that behavior you + could add a read-only routing table to the board-specific long that + contains a single entry, the default route: 0.0.0.0/0 (2017-09-28). + * fs/vfs: file_seek() is an internal OS interface and should not errors + via the errno (2017-09-28). + * fs/vfs: file_read() is an internal OS interface and should not errors + via the errno (2017-09-28). + * fs/vfs: file_write() and file_pwrite() are internal OS interfaces and + should not report errors via the errno (2017-09-28). + * STM32L4 FLASH, DFSDM: option bytes, JEXTSEL bits, ADC1 output to DFSDM + chips change + - STM32L4 FLASH: add function for modifying device option bytes + - STM32L4 DFSDM: add JEXTSEL bits, ADC1 output to DFSDM chips change + ST's documentation hints that ADC output can be routed to DFSDM on + some STM32L4X3 chips, but I got confirmation from tech support that + this is just a documentation error so remove this from Kconfig + From Juha Niskanen (2017-09-29). + * This commit adds support for routing tables in files in a file + system. This might be useful for customized, per-unit routing tables. + There are two issues with it however: + 1. Reading from file system on a per packet basis could be slow. I + think it probably should have a small, in-memory cache of most + frequently used routes for good problem. + 2. Currently the delroute logic is disabled due to a problem with + the design. NuttX does not currently support truncate(). + Therefore, it is not possible to delete entries from the routing + table file. + In this current implementation, that leaves the last entry intact at + the end of the file. An alternative design might include a tag on + each record to indicate if the record is valid or not. That would + work but would add complexity to the other routing table functions + (2017-09-29). + * net/route: Add support for an in-memory routing table cache in order + to improve performance when the routing table is retained in a file. + The cache holds the most recently used routing table entries and so can + eliminate some file access. Flush the in-memory cache when any entry is + deleted from the routing table. When a router matching an IP address is + found, add the routing table entry to the cache (2017-09-29). + * fs/vfs: null check for path on open and buf on write. Null path + check is depend on CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_ASSERTIONS, + added null checking so it's always performed Added null checking on buf + for write(). From Xiao Qin (2017-09-29). + * net/route: File read/write logic should be able to handle short reads + and writes (2017-09-29). + * drivers/syslog: syslog internal functions should not set the errno + variable: ramlog_putc(), syslog_dev_putc(), syslog_dev_write(), + syslog_force() (2017-09-29). + * net/sockets: psock_sendto() is an internal OS interface an should not + set the errno variable (2017-09-29). + * net/sockets: psock_send() is an internal OS interface an should not + set the errno variable (2017-09-29). + * psock_send() no longer sets errno, so send() must now set it + (2017-09-30). + * net/: Versions of psock_send() and pock_sendto() should not set + errno. That is taken care of at a higher level in the send()/sendto() + implementation as appropriate (2017-09-30). + * net/: psock_accept() is an internal interface and should not set the + errno (2017-09-30). + * net/: psock_bind() is an internal interface and should not set the + errno (2017-09-30). + * net/: psock_connect() is an internal interface and should not set the + errno nor should it be a cancellation point (2017-09-30). + * net/: psock_listen() is an internal interface and should not set the + errno (2017-09-30). + * net/: psock_getsockopt() is an internal interface and should not set + the errno (2017-09-30). + * net/: psock_getsockopt() and psock_socket() are an internal interfaces + and should not set the errno (2017-09-30). + * net/: psock_accept() is not a cancellation point (2017-09-30). + * net/: psock_recvfrom() is an internal interface and should not set the + errno nor should it be a cancellation point (2017-09-30). + * net/ and fs/: net_vfcntl(), file_fcntl(), file_dup(), and file_dup2() + are all internal OS interfaces and should not modify the errno value + (2017-09-30). + * net_dupsd() and net_dupsd2() are internal OS functions and should not + set the errno variable (2017-09-30). + * psock_ioctl() and netdev_ioctl() are internal OS functions and should + not set the errno variable (2017-09-30). + * psock_close() and net_close() are internal OS functions and should not + set the errno variable (2017-09-30). + * SAMv7, STM32, STM32 L4: DAC and ADC drivers are not permitted to set + the errno (2017-09-30). + * SIM LPC31xx: Serial and console drivers are not permitted to set the + errno (2017-09-30). + * STM32, STM32 F7: LTDC and DMA2D drivers are not permitted to set the + errno (2017-09-30). + * drivers/serial: 16550 UART driver IOCTL method must not set errno; it + must return a negated errno value (2017-09-30). + * drivers/lcd: ILI9341 initialize method not permitted to set errno + (2017-09-30). + * drivers/sensors: LIS331DL driver not permitted to set errno + (2017-09-30). + * drivers/wireless: CC1101 driver not permitted to set errno + (2017-09-30). + * configs/z80sim and xtrs: Serial driver lower halfs ioctl methods + should return a negated errno value, not set the errno variable + (2017-10-30). + * compiler.h, limits.h, types.h: Update SDCC/z80 files to include + support for long long, inline, __FILE__, and __func__ (2017-10-01). + * z80 Make.defs: Fixes dependency generation with newest SDCC compiler + (2017-10-01). + * include/: Add stdnoreturn.h (2017-10-01). + * tools/configure.sh: Add special support so that you can start with a + windows native configuration and install on a different host (and vice + versa). (2017-10-01). + * stm32_hrtim: add support for capture, chopper, deadtime and dump + registers. From Mateusz Szafoni (2017-10-01). + * tools/configure.c: Duplicate new functionaity added to configure.sh + (2017-10-01). + * tools/configure.sh: Another fix for the script. The last change only + worked for Windows Cygwin; for Linux, it needed to remove some + additional things from the defconfig file (2017-10-01). + * configs/z80sim: convert other configurations to default to Linux + (2017-10-01). + * tools/: configure.sh and configure.c should redirect stdout to + /dev/null but should not suppress stderr output (2017-10-01). + * stdnoreturn.h: Add definitions for the C11 noreturn keyword. Also + Remove C++11 dependency. Applies to C too (2017-10-02). + * net/route: Add logic to mark a route as most-recently-used in the + route cache (2017-10-02). + * commit b2ea300b6fb7672cdb682a0957b5dd2cff63804d broke the STM32L4 port + for people not using the L496xx or L4A6xx. That was because + stm32l4_sdmmc.h is included from the stm32l4.h global header, and this + header fires an #error for other chips. I see that ALL stm32l4 have the + same SDMMC except the stm32l4x2, which has none. From Sebastien Lorquet + (2017-10-02). + * net/route: Fix an error in cache list management (2017-10-02). + * Add support for Micron MT25Q series MT25Q128. From Sebastien Lorquet + (2017-10-02). + * binfmt/: Don't schedule starthook if there are no constructors + (2017-10-02). + * binfmt/: exec_module(), load_module(), unload_module(), and + schedule_unload() are internal OS functions and must not alter the errno + variable (2017-10-02). + * stm32f103-minimum: Add ADC support on stm32f103-minimum board. From + Alan Carvalho de Assis (2017-10-02). + * syscall/: The non-standard interface exec() is now enshrined as a + official NuttX API. I really dislike doing this but I think that this + is probably the only want to load programs in the protected mode. It is + currently used by some example code under apps/ that generate their own + symbol tables for linking. Other file execution APIs relay on a symbol + table provided by the OS. In the protected mode, the OS cannot provide + any meaning symbol table for execution of code in the user-space blob so + that is they exec() is really needed in that build case. And, finally, + the interface is completely useless and will not be supported in the + KERNEL build mode where the contrary is true: An application process + cannot provide any meaning symbolic information for use in linking a + different process (2017-10-03). + * STM32L4 RTC, PM: small fixes to subseconds handling, ADC + power-management hooks + - STM32L4 ADC: add PM hooks from Motorola MDK + - STM32L4 RTC: add up_rtc_getdatetime_with_subseconds + - STM32 RTC: workaround for potential subseconds race condition. In + all recent STM32 chips reading either RTC_SSR or RTC_TR is supposed + to lock the values in the higher-order calendar shadow registers + until RTC_DR is read. However many old chips have in their errata + this silicon bug (at least F401xB/C, F42xx, F43xx, L15xxE, L15xVD + and likely others): "When reading the calendar registers with + BYPSHAD=0, the RTC_TR and RTC_DR registers may not be locked after + reading the RTC_SSR register. This happens if the read operation is + initiated one APB clock period before the shadow registers are + updated. This can result in a non-consistency of the three + registers. Similarly, RTC_DR register can be updated after reading + the RTC_TR register instead of being locked." + - STM32L4 RTC: correct RTC_SSR and RTC_TR read ordering. In all + recent STM32 chips reading either RTC_SSR or RTC_TR is supposed to + lock the values in the higher-order calendar shadow registers until + RTC_DR is read. Change the register read ordering to match this and + don't keep a workaround for a hypothetical race condition (not in + any L4 errata, lets for once assume ST's silicon works as it is + documented...) + - STM32L4 PM: remove useless #ifdefs and old non-L4 STM32 code + From Juha Niskanen (2017-10-03). + * sched/semaphore: Rename sem_reset() to nxsem_reset() so that it is + clear this is an internal OS function (2017-10-03). + * sched/semaphore: Rename sem_tickwait() to nxsem_tickwait() so that it + is clear this is an internal OS function (2017-10-03). + * libc/semaphore: Add nxsem_init() which is identical to sem_init() + except that it never modifies the errno variable. Changed all + references to sem_init in the OS to nxsem_init() (2017-10-03). + * sched/semaphore: Rename all internal private functions from sem_xyz + to nxsem_xyz. The sem_ prefix is (will be) reserved only for the + application semaphore interfaces (2017-10-03). + * libc/semaphore: Add nxsem_getvalue() which is identical to + sem_getvalue() except that it never modifies the errno variable. + Changed all references to sem_getvalue in the OS to nxsem_getvalue() + (2017-10-03). + * libc/semaphore and sched/semaphore: Add nxsem_getprotocol() and + nxsem_setprotocola which are identical to sem_getprotocol() and + set_setprotocol() except that they never modifies the errno variable. + Changed all references to sem_setprotocol in the OS to + nxsem_setprotocol(). sem_getprotocol() was not used in the OS + (2017-10-03). + * sched/semaphore: Add nxsem_destroy() which is identical to + sem_destroy() except that it never modifies the errno variable. Changed + all references to sem_destroy() in the OS to nxsem_destroy() (2017-10-03). + * sched/semaphore: Add nxsem_post() which is identical to sem_post() + except that it never modifies the errno variable. Changed all + references to sem_post in the OS to nxsem_post() (2017-10-03). + * sched/semaphore: Add the function nxsem_wait(). This is a new + internal OS interface. It is functionally equivalent to sem_wait() + except that (1) it is not a cancellation point, and (2) it does not set + the per-thread errno value on return. In all OS functions (not + libraries), change sem_wait() to nxsem_wait(). This will prevent the OS + from creating bogus cancellation points and from modifying the per-task + errno variable. This commit also backs out most of commit + b4747286b19d3b15193b2a5e8a0fe48fa0a8638c. That change was added because + sem_wait() would sometimes cause cancellation points inappropriately. + But with these recent changes, nxsem_wait() is used instead and it is + not a cancellation point (2017-10-04). + * sched/semaphore: sem_timedwait() is a cancellation point and, hence, + cannot be called from within the OS. Created nxsem_timedwait() that is + equivalent but does not modify the errno and does not cause + cancellation. All calls to sem_timedwait() change to calls to + nxsem_timedwait() in the OS (2017-10-05). + * sched/semaphore: sem_trywait() modifies the errno value and, hence, + should not be used within the OS. Use nxsem_trywait() instead + (2017-10-05). + * This change renames all internal, private NuttX signal-related + functions to use the prefix nxsig_ so that they cannot be confused with + application interfaces that begin, primarily, with sig_. This is + analogous to similar renaming that was done previously for semaphores + (2017-10-05). + * drivers/input/cypress_mbr3108: Add missing variable for nxsem_wait + return value. From Jussi Kivilinna (2017-10-06). + * fs/vfs and net/socket: fcntl() is not return success fail for + F_SETFL. Reported by Jussi Kivilinna (2017-10-06). + * This commit adds internal versions of the signal interfaces: + - sigtimedwait() -> nxsig_timedwait() + - sigwaitinfo() -> nxsig_waitinfo() + - nanosleep() -> nxsig_nanosleep() + Replace all usage of sigwaitinfo(), sigtimedwait(), and nanosleep() + with the OS internal counterparts nxsig_waitinfo(), nxsig_timedwait(), + and nxsig_nanosleep(). The internal OS versions differ from the + standard application interfaces in that they do not create + cancellation points and they do not modify the application's errno + variable (2017-10-06). + * Adds new OS internal functions nxsig_sleep() and nxsig_usleep. These + differ from the standard sleep() and usleep() in that (1) they don't + cause cancellation points, and (2) don't set the errno variable (if + applicable). All calls to sleep() and usleep() changed to calls to + nxsig_sleep() and nxsig_usleep() (2017-10-06). + * drivers/serial/tcdrain: tcdrain() was recently added to the NuttX C + library. But there is a problem. The specification of tcdrain() + requires that it be a cancellation point. In order to do this, tcdrain + was moved from the C library into the OS and the addition cancellation + point hooks were added. In non-FLAT builds, access via system calls is + also now supported (2017-10-06). + * net/Kconfig: Remove improper use of comma in syntax (2017-10-06). + * mm/: Heap semaphore logic needs to use nxsem_* interfaces when + available, but the standard semaphores only when implementing a + user-space heap. Not this does introduce and issue: the memory + management functions them become cancellation points because of the use + of sem_wait (2017-10-07). + * syscall/: Fix some backward conditional compilation (2017-10-07). + * sched/signal: Add nxsig_kill() which is functionally equivalent to + kill() except that it does not modify the errno variable. Replace all + usage kill() in the OS proper with nxsig_kill() (2017-10-07). + * graphics/vnc/server: Fix an error in the VNC server introduced with + recent big set of changes (2017-10-07). + * sched/signal: Add nxsig_queue() which is functionally equivalent to + sigqueue() except that it does not modify the errno variable. Replace + all calls to sigqueue() in the OS proper with calls to nxsig_queue() to + avoid accessing the errno variable (2017-10-07). + * sched/signal: Add internal OS interface nxsig_procmask(). This + internal interface is equivalent to the standard sigprocmask() used by + applications except that it does not modify the errno value. Also fixes + a problem in that the original sigprocmask() was not setting the errno. + Replace all calls to sigprocmask() in the OS proper with calls to + nxsig_procmask(). (2017-10-07). + * sama5d4-ek: Remove a really old defconfig example file that is so far + out of date that it can only be misleading (2017-10-07). + * Fix some build problems after recent separation of internal OS from + application interfaces. The build problem only occurs in the PROTECTED + and KERNEL builds where separate libraries are built for the + applications and for use within the OS. In these cases, the correct + interfaces must be used. This commit fixes a few of these, so I can get + through build testing, but there are many more that need fixin' + (2017-10-08). + * SDCC Fixes: Change some prototypes and some assumptions about the + size of unsigned int to get to a clean SDCC compile (2017-10-08). + * Fix some problems in the previous commits: Forgot to update sigset() + after change to prototype. Also there was a stray semicolon in the + change signal() (2017-10-08). + * libc/stdio: Build the lib_noflush() and lib_snoflush() stubs even if + CONFIG_FILE_DESCRIPTORS=0. They may still be needed (2017-10-08). + * configs/z80sim: Fix a naming problem. Also, don't try to build the + serial driver if CONFIG_NFILE_DESCRIPTOR=0 (2017-10-08). + * libc and libnx: When the libraries are built into two libraries, a + user space library and a OS space library (as in the PROTECTED and + KERNEL build). Then the user space library must not use the OS internal + interfaces; similarly, the OS must avoid using the userspace interfaces + so that it does not muck the errno value or create spurious cancellation + points (2017-10-08). + * Misc STM32 Fixes + - stm32_hrtim.c: fix burst mode prescaler update + - stm32f334-disco: add flash mode support for powerled driver + + cosmetics + From Mateusz Szafoni (2017-10-08). + * powerled.h: Add fault field to state structure. From Mateusz Szafoni + (2017-10-08). + * libc/termios: Adds tcflow() (2017-10-09). + * RNDIS: Use CONFIG_USBDEV_MAXPOWER instead of hardcoded value. Use + LPWORK for network operations by default. From Sakari Kapanen + (2017-10-09). + * sched/mqueue: Rename all OS internal functions declared in + sched/mqueue/mqueue.h to begin with nxmq_ vs. mq_. The mq_ prefix is + reserved for standard application interfaces. Rename all private static + functions for use the nxmq_ vs. mq_ naming (2017-10-09). + * task: Add new cancellation point interface, + check_cancellation_point() (2017-10-09). + * STM32, STM32L4 serial changes: + - stm32: serial: add interface to get uart_dev_t by USART number, + stm32_serial_get_uart + - stm32: serial: do not stop processing input in SW flow-control mode + - stm32l4: serial: do not stop processing input in SW flow-control + mode + - stm32l4: serial: suspend serial for Stop mode + From Juha Niskanen (2017-10-09). + * Misc STM32 Fixes + - stm32_powerled.c: cosmetics + - stm32_hrtim.c: cosmetics + - stm32/Kconfig: add HRTIM configuration and add DAC external + trigger configuration + - stm32f334-disco: Add powerled example configuration. From Mateusz + Szafoni (2017-10-09). + * drivers/power: Add powerled to Kconfig. From Mateusz Szafoni + (2017-10-09). + * BCM2708: Add enough infrastructrue (more stubs) to get a clean + compilation of the Pi Zero configuration (with many undefined things at + link time). This includes several register definition header files + (some from Alan Carvalho de Assis), basic interrupt handling logic, + boot-up files, GPIO support, build and configuration logic, basic board + support at configs/pizero (2017-10-09). + * sched/mqueue: Add internal function nxmq_send() and nxmq_timedsend() + that are equivalent to mq_send() and mq_timedsend() except that they do + not create cancellation points and do to not modify the errno variable. + Change all calls to mq_send() and mq_timedsend() in the OS to calls to + nxmq_send() and nxmq_timedsend(), making appropriate changes for + differences in return values (2017-10-10). + * sched/mqueue: Add nxmq_receive() and mxmq_timedreceive() which are + functionally equivalent to the standard mq_receive and mq_timedreceive() + except that (1) they do not create cancellation points, and (2) the do + not modify the application's errno variable. Change all calls to + mq_receive() and mq_timedreceive() in the OS to calls to nxmq_receive() + and nxmq_timedreceive(), making appropriate changes for differences in + return values (2017-10-10). + * Fix a few places where there was a semicolon following the 'if' + condition, making the following logic unconditional (2017-10-10). + * The INA219 is a combined voltage and current sensor that can measure + up to 26 volts and a current that depends on an external shunt + resistor. Connection happens via i2c/smbus and the chip features a + power supply rail that is independent from the measured voltage, so it + can measure low voltages. + + This commit adds a driver for this chip. Right now it measures bus + voltage and current, and does not use the internal calibrated current + reading, nor the available power measurement. From Sebastien Lorquet + (2017-10-10). + * configs/clicker2-stm32: Adds SD card, automount, and syslog file + support and fixes a few minor issues + - Moves defines for xbee from clicker2-stm32.h to stm32_xbee.h + - Adds support for uSD click boards and automount support + - Fixes minor guard clause + - Bring-up automounter before MMCSD + - MRF24J40 interrupt should only fire on falling edge. + - Adds file syslog support for logging to file on SD card + From Anthony Merlino (2017-10-11). + * Z80: Makefile fix for use with current SDCC (2017-10-11). + * fs/vfs: Change the return value of internal function fs_getfilep(). + It no longer sets the errno variable but, rather, returns errors in the + same manner as other internal OS functions (2017-10-11). + * Adds OS internal functions nx_send(), ns_recv(), and nx_recvfrom() + which are functionally equivalent to send(), recv(), and recvfrom() + except that they do not set the errno variable and do not cause + cancellation points (2017-10-11). + * Adds OS internal function nx_write() which is functionally equivalent + to write() except that it does not set the errno variable and do not + cause cancellation points (2017-10-11). + * sched/task: task_exithook.c fails to link if signals are disabled + because was unconditionally trying to send the SIGCHLD signal to the + parent in certain configurations. Noted by Jeongchan Kim (2017-10-11). + * arch/arm/src/samv7: Correct an error in RX DMA setup. From Manish + Kumar Sharma (2017-10-11). + * net/socket: psock_send/psock_sendto: remove assert check for null + psock and buf input pointers. Removes check as 'psock == NULL' + altogether because that checked for later in psock_send and + psock_sendto. Change null check for 'buf' so that it is handled same as + in recvfrom.c (return -EINVAL instead of assert). From Jussi Kivilinna + (2017-10-11). + * fs/vfs: Add new internal OS interface nx_read(). nx_read() is + functionally equivalent to read() except that it does not modify the + errno variable and it is not a cancellation point. Changed all + references to read() in the OS to nx_read() (2017-10-11). + * sched/signal: Add logic to wake up a thread that is waiting on a + signal if it is canceled (2017-10-12). + * nxsig_timedwait: Add logic to suppress the wait if there is a pending + cancellation (2017-10-12). + * stm32 SPI: Add missing include required when CONFIG_SPI_CALLBACK is + enabled. From Anthony Merlino (2017-10-12). + * STM32L4 RTC fixes: + - STM32L4 RTC: init mode was never exited because nested locking in + rtc_synchwait() disabled backup domain access + - STM32L4 RTC: Use backup register magic value instead of INITS + bit. The INITS (bit 4) of RTC_ISR register cannot be used to + reliably detect backup domain reset. This is because we can operate + our device without ever initializing the year field in the RTC + calendar if our application does not care about correct date being + set. Hardware also clears the bit when RTC date is set back to year + 2000. + - STM32L4 RTC: put back the SSR race condition workaround. ST has + confirmed that the issue has not been fixed, and that it applies to + STM32L4 too (was not in errata sheets due to documentation bug) See + discussion: https://community.st.com/thread/43710-issue-with-rtc-maximum-time-resolution + - STM32F4, STM32L4, STM32F7 RTC: add more CONFIG_RTC_NALARMS > 1 to + reduce code size + - STM32L4: rename stm32l4_rtcc.c to stm32l4_rtc.c to better match + STM32F7 + - STM32, STM32L4, STM32F7 RTC: stray comment and typos in + chip/stm32_rtcc.h + - STM32L4 RTC: change maximum alarm time from 24h to one month + From Juha Niskanen (2017-10-13). + * TCP Networking: When CONFIG_NET_TCP_WRITE_BUFF=y there is a situation + where a NULL pointer may be dereferenced. In this configuration, the + TCP connection's 'semi-permanent' callback, s_sndcb was nullified in + tcp_close_disconnect. However, other logic in tcp_lost_connection() + attempt to use that callback reference after it was nullifed. Fixed in + tcp_lost_connectino() by adding a NULL pointer change before the + access. This was reported by Dmitriy Linikov in Bitbucket Issue 72 + (2017-10-13). + * stm32f7 BBSRAM: stm32_bbsram: avoid assert in stm32_bbsram_savepanic. + If panic happens before stm32_bbsram is initialized, + stm32_bbsram_savepanic caused additional assert panic. Function has null + pointer check, so drop DEBUGASSERT. From Jussi Kivilinna (2017-10-13). + * FS FAT: Fix hard-fault when listing contents of FAT root. From Jussi + Kivilinna (2017-10-13). + * configs/stm32f4discovery: Add a USB MSC configuration. From Alan + Carvalho de Assis (2017-10-13). + * 6LoWPAN: Correct a bug in handling uncompressed frames (IPv6 + dispatch) (2017-10-13). + * 6LoWPAN: Fix a whole in the logic of the previous commit. It turns + out that g_uncomp_hdrlen has other usages so it cannot be modified as I + was doing. Instead, I needed to add a separate localt variable, + protosize, to keep track of the two usages of g_uncomp_hdrlen + (2017-10-13). + * configs/: The nx and nxtext examples no longer supports single user + mode (2017-10-14). + * The lcdrw example has been removed because it violates the portable OS + interface (2017-10-14). + * All configurations that use NXIMAGE or NXHELLO must select + NX_MULTIUSER. All configuratinos that use examples/nxterm must enable + CONFIG_LIB_BOARDCTL (2017-10-14). + * configs/stm32f103-minimum: Add support for LM75 in the + stm32f103-minimum board. From Alan Carvalho de Assis (2017-10-14). + * configs/: All configurations that use NXLINES must select + NX_MULTIUSER. All configurations that use the NX server need to have + larger POSIX messages (2017-10-14). + * boardctl(): Remove the BOARDIOC_GRAPHICS_SETUP command (2017-10-15). + * Initial ADC support for the STM32F33XX + - stm32_adc.h: add JEXTSEL definitions and hrtim trigger configuration + - stm32_adc.c: move STM32F33 ADC logic to a separate file + From Mateusz Szafoni (2017-10-15). + * configs/sim: Update touchscreen driver initialization to use only + multiple-user NX server logic (2017-10-15). + * configs/sim: Convert the traveler configuration so that it uses the + framebuffer driver (2017-10-16). + * task_delete(): Do not permit user applications to delete kernel + threads (2017-10-16). + * kthread_create(): Rename kernel_thread() to kthread_create() for + better naming consistency with task_create() and kthread_delete() + (2017-10-16). + * All other STM32: SHIFTR_SUBFS_MASK was correct in STM32F0 only + - STM32L1: use correct EXTI line definitions (2017-10-17). + * STM32 RTC fixes: + - RTC: canceling an alarm marks it as inactive + - STM32L4, STM32F4, STM32F7 RTC: fix reading alarm value that is + more than 24h in future + - STM32F0 RTC: fix backup register count in stm32_rtcc.h + From Juha Niskanen (2017-10-17) + * BCM2708: Add system timer register definitions and a partial + implementation of the tickless mode timer (2017-10-17). + * BCM2708: Add support for AUX interrupts. Add some build configuration + and support logic for low-level serial output (2017-10-17). + * drivers/usbdev: Correct input flow control logic when watermarks are + not enabled. Problem noedt by and change based on suggestion by Juha + Niskanen (2017-10-18). + * BCM2708: Add hooks to support both Mini- and PL011 UARTs (2017-10-18). + * BCM2708: Fleshes out GPIO interrupt logic (2017-10-18). + * fs/vfs: Fix after recent changes. write() was return negative values + in errno. Noted by Jussi Kivilinna (2017-10-18). + * drivers/usbdev: Move test for NULL pointer before the pointer is + deferences. Noted by Juha Niskanen (2017-10-18). + * net/: Fix some build issues noted when both IPv4 and IPv6 are + enabled. From Anthony Merlino (2017-10-18). + * photon: Support SPI1 and SPI3. From Anthony Merlino (2017-10-18). + * BCM2708: Allow pass parameters with AUX interrupts; Add mini-UART + break capability. BCM2708: Add Mini-UART logic. Still missing UART + configuration logic (2017-10-18). + * Alexey T, Bitbuck Issue 73: Lower part of STM32 CAN driver + arch/arm/src/stm32/stm32_can.c uses all three hw tx mailboxes and clears + TXFP bit in the CAN_MCR register (it means transmission order is defined + by identifier and mailbox number). + + This creates situation when order frames are put in upper part of CAN + driver (via can_write) and order frames are sent on bus can be + different (and I experience this in wild). Since CAN driver API + pretends to be "file like" I expect data to be read from fd the same + order it is written. So I consider described behaviour to be a bug. + + I propose either to set TXFP bit in the CAN_MCR register (FIFO + transmit order) or to use only one mailbox (2017-10-19). + * The timer frequencies (BOARD_TIMx_FREQUENCY) are incorrectly defined + in configs/stm3240g-eval/include/board.h. Since the APB prescalers are + set to divide by 4 and 2 respectively, the frequencies should be + "2xAPBx" as said in the comment.  The correct frequencies are already + defined but as STM32_APBx_TIMx_CLKIN. From Mattias Edlund (2017-10-19). + * drivers/ioexpander: The IRQ subsystem now supports passing a void * + parameter to IRQ handlers. Use that method to support multiple pc9555 + devices, by passing a pointer to the device to the board defined irq + handler. Now the CONFIG_ for multiple PCA devices just allocates device + structures dynamically instead of statically when not enabled. + + The same interrupt handler is entered with the device structure + parameter in all situations, multiple or single PCA. One should still + be careful if multiple PCA devices share the same IRQ. From Sebastien + Lorquet (2017-10-19). + * libc/match: Use of exp() vs expf() in logf() caused function to be + slow. From Alan Carvalho de Assis (2017-10-19). + * drivrs/mtd/filemtd.c: add block device MTD interface. Block MTD + interface allows using block device directly as MTD instead of having to + use file-system in between. NOTE that this provides the opposite + capability of FTL which will let you use an MTD interface directly as a + block device. From Jussi Kivilinna (2017-10-19). + * There was a reference counting problem in the TPC logic of + net_clone(). net_clone() which is the common logic underlying dup() and + dup2() for sockets. When net_clone() calls net_start_monitor() and + net_start_monitor() returns a failure (because the underlying TCP + connection) then net_clone() must back out the reference count on the + structure. Problem noted by Pascal Speck and this implementation of the + solution is based on his suggestion (2017-10-19). + * There was a possible recursion that could eventually overflow the + stack. The error occurred when closing the socket with inet_close() + while a socket callback was still queued. When the socket callback was + executed by devif_conn_event(), this resulted in a call to + psock_send_eventhandler() with TCP_CLOSE flag set which then called + tcp_lost_connection(). tcp_shutdown_monitor() then called + tcp_callback() again, which again called psock_send_eventhandler(), and + so on.... Noted by Pascal Speck. Solution is also similar to a + solution proposed by Pascal Speck (2017-10-19). + * nucleo-f334r8/adc: change serial console to USART2 (STLINK COM). From + Mateusz Szafoni (2017-10-19). + * stm32f33xxx_adc.c: fix some warnings and compilation error when extsel + not in use. From Mateusz Szafoni (2017-10-19). + * net/tcp: Same change to tcp_send_buffered.c probably also applies to + tcp_send_unbuffered.c (2017-10-19). + * net/tcp: Same change to tcp_send_buffered.c probably also applies to + tcp_sendfile.c (2017-10-19). + * tcp_lost_connection() is called from two places in tcp_sendfile.c + (2017-10-19). + * net/tcp: Same change to tcp_send_buffered.c probably also applies to + sixlowpan_tcpsend.c and inet_recvfrom.c (2017-10-19). + * drivers/sensor: Add driver for the APDS-9960 gesture sensor. From + Alan Carvalho de Assis (2017-10-20). + * include/nuttx/sensors/ioctl: deduplicate SNIOC_CFGR. From Jussi + Kivilinna (2017-10-20). + * drivers/sensors/hts221: power-on sensor for loading calibration data. + From Jussi Kivilinna (2017-10-20). + * arch/arm/src/stm32f7/i2c: fix I2C_M_NORESTART handling. From Jussi + Kivilinna (2017-10-20). + * drivers/sensors/apds9960.c: Use work_queue to read/process data when + receive an IRQ. From Alan Carvalho de Assis (2017-10-20). + * STM32L1, STM32L4 RTC: add periodic interrupts, update L1 RTC + implementation + - STM32L4 RTC: add support experimental CONFIG_RTC_PERIODIC + - STM32 RTC: separate STM32L1 RTC into a separate file + STM32L1 RTC is very close to F4 or L4 versions, with two alarms and + periodic wakeup support so backported L4 peripheral to L1. + - RTC: Add periodic alarms to upper and lower halves + From Juha Niskanen (2017-10-20). + * stm32_adc.c: clear pending interrupts. From Mateusz Szafoni + (2017-10-20). + * drivers/bch: The character driver to block device access now supports + an IOCTL to get the geomtry of the underlying block device (2017-10-20). + * fs/fat: Remove mkfatfs from the OS. This is a user-space application + and belongs in apps, not in the OS (2017-10-20). + * configs/nucleo-f334r8: add logic for zero latency high priority + interrupts example. From Mateusz Szafoni (2017-10-22). + * Misc STM32 chagnes + - STM32 HRTIM: Fix warnings related with RCC + - STM32F33xxx ADC: Add some publicly visable interfaces and some + code to support injected channels + - STM32F33xxx DMA: Add public interface to handle with DMA interrupts + From Mateusz Szafoni (2017-10-22). + * stm32f103-minimum: Add an ADPS-9960 example configuration. From Alan + Carvalho de Assis (2017-10-23). + * net/icmp: This change adds support for semi-standard IPPROTO_ICMP + AF_INET datagram sockets. This replaces the old ad hoc, nonstandard way + of implementing ping with a more standard, socket interface (2017-10-23). + * net/inet: Add check for protocol before handing out TCP and UDP + sockets (2017-10-23). + * arch/arm/common/up_checkstack: fix assert panic when both TLS and + interrupt stack are enable. From Jussi Kivilinna (2017-10-23). + * net/icmp: Correct some comments, typings, spacing problems from last + big ICMP socket change (2017-10-23). + * configs/: All defconfig filess that include + CONFIG_NET_ICMPv6_SOCKET=y need to select CONFIG_SYSTEM_PING6=y and + deselect CONFIG_DISABLE_POLL (2017-10-24). + * net/icmpv6: This commit adds support for semi-standard IPPROTO_ICMP6 + sockets. This is a replacement for the non-standard ICMPv6 ping support + that violated the portable POSIX OS interface (2017-10-24). + * mm/mm-heap: memalign: fix heap corruption caused by using unaligned + chuck size. Unaligned nodes generated by memalign later cause heap + corruptions when nodes are shrink further (for example, 24 bytes -> 8 + bytes, when alignment is 16 bytes). From Jussi Kivilinna (2017-10-24). + * lm3s8962: NX configuration needs CONFIG_NXSTART_EXTERNINIT=y + (2017-10-24). + * sched/: move POSIX thread specific data from pthread TCB to common + TCB structure. This change allows using + pthread_getspecific/pthread_setspecific from main thread. Patch also + enables using pthread data with config option CONFIG_DISABLE_PTHREAD=y. + From Jussi Kivilinna (2017-10-25). + * net/local: fix typo in config macro name. From Juha Niskanen + (2017-10-25). + * Olimex stm32-h407 serial support for the on-board UEXT connector + (fixed style & defconfig). Add USART6 for UEXT connector. Add + nsh_uext configuration and README update. From Jan Pobříslo (2017-10-26). + * configs/nucleo-l496zg/nsh: enable I2C4 bus with i2ctool. From Jussi + Kivilinna (2017-10-26). + * arch/arm/stm32f7: i2c: restore bus frequency after I2C reset. Copy + frequency restoration fix from STM32L4 I2C driver to STM32F7 I2C + driver. From Jussi Kivilinna (2017-10-26). + * arch/stm32l4: port STM32F7 I2C driver to STM32L4. STM32L4 I2C driver + is in work-in-progress state (plentiful of TODOs and #warnings) and lags + many features found in more up-to-date STM32 I2C drivers. The peripheral + on STM32F7 and STM32L4 are identical except for L4's 'wakeup from stop + mode' flag and STM32F7's I2C driver is in more 'ready to use' state. + + Commit ports the STM32F7 I2C driver to STM32L4. The I2C clock + configuration is kept the same as before (I2CCLK = PCLK1 80 Mhz) + instead of switching to STM32F7 arch default that is I2CCLK=HSI. + Further work would be to add configuration option for choosing I2C + clock source instead of current hard-coded default. From Jussi + Kivilinna (2017-10-26). + * drivers/sensors/lis2dh: fixes for self-test. From Jussi Kivilinna + (2017-10-26). + * include/nuttx/fs/: Move prototype of foreach_mountpoint out of + include/nuttx/fs/fs.h to fs/mount/mount.h (2017-10-26). + * fs/mount: Implements procfs /proc/fs/blocks and /proc/fs/usage files, + replacing the NSH df command. Also implements procfs /proc/fs/mount + file, replacing the NSH mount command when there are no arguments + (2017-10-26). + * Correct a problem that was causing an apparent directory to be + reported as a file instead of a directory by opendir. This happened + after adding these three new procfs entries: fs/block, fs/mount, and + fs/usage. Of course, there is no directory fs in this case, only three + files that have fs/ in their relative pathnames. The logic was + detecting that fs was the name of the enty to report, but it was then + declaring that fs was a file (because fs/block is of type file). This + was fixed by adding a check for matching lenghts. i.e., if strlen(fs) + != strlen(fs/block), then report fs as a directory instead of a file + (2017-10-26). + * fs/procfs: Missing some conditional logic for cases where mountpoint + procfd entries excluded (2017-10-27). + * drivers/can/mcp2515.c: Fix the MCP2515 Bit Rate Prescale + calculation. Fix BRP for SET_BITTIMING ioctl as well. From Alan + Carvalho de Assis (2017-10-27). + * sensors/lis2dh: Fix use of obsolete dbg macro. From Jussi Kivilinna + (2017-10-27). + * nucleo-f334r8: Add highpri example configuration. From Mateusz + Szafoni (2017-10-28). + * STM32 F33xx: Add ADC DMA support to STM32F33 configuration. From + Mateusz Szafoni (2017-10-28). + * drivers/net: Remove the old, unfinished Crystal LAN driver. I don't + even have the hardware that it goes with anymore (2017-10-28). + * configs/mx1ads: This commit removes board support for the mx1ads + board. That board support was never completed and I no longer even have + the hardware. The unfinished board support is still available in the + Obsoleted repository if anyone would ever like to resurrect it + (2017-10-28). + * STM32 ADC: Added support for ADC's IO_ENABLE_TEMPER_VOLT_CH ioctl on + STM32F10XX and STM32F20XX. From Dmitriy Linikov (2017-10-30). + * STM32 F2: Fixed build for STM32F20XX platforms when + CONFIG_STM32_DMACAPABLE is enabled. From Dmitriy Linikov (2017-10-30). + * fs/userfs: This completes coding of the UserFS client and of the + UserFS feature in general. This feature is being merged to main now + because I believe it is innocuous. It is, however, untesed. The next + step will be to develop a test case to verify the feature. Uses Unix + domain local sockets instead of message queues. Easier to transfer big + data in local sockets than message queues (2017-10-30). + * Fix DEBUGASSERT() issues with nxhello on lc823450-xgevk + - sched/task: Remove DEBUGASSERT in task_exitstatus() and + task_groupexit() + - graphics: Change DEBUGASSERT condition in nx_runinstance() + From Masayuki Ishikawa (2017-10-31). + * Fix GPIO operation of STMPE811 driver. + 1. STMPE811_GPIO_DIR was defined for register name and later was + redefined to be the pin direction mask for `stmpe811_gpioconfig`. I + decided to change register name to be STMPE811_GPIO_DIR_REG, and keep + pin direction mask STMPE811_GPIO_DIR, so that any external code that + already use this driver will be unchanged. + 2. The STMPE811 register GPIO_DIR uses bit value 1 for output and 0 + for input, but `stmpe811_gpioconfig` set the opposite. + 3. The call to `stmpe811_gpiowrite` from inside of + `stmpe811_gpioconfig` leaded to deadlock. + From Dmitriy Linikov (2017-10-31). + * sim/userfs: Add a configuration for testing the UserFS using + apps/examples/userfs (2017-10-31). + * Fixes a memory leak that is caused because the client message queue is + not unlinked after the client disconnects from the NX server. From + Masayuki Ishikawa (2017-10-31). + * drivers/wireless/ieee80211: Fix typos and spelling errors as needed + for Photon build. From Anthony Merlino (2017-11-01). + * net/icmpv6: Add some header file necessary for correct build. From + Anthony Merlinoo (2017-11-01). + * libc/userfs: Correct return value from dispatchers. Should return + zero on success, not the number of bytes sent (2017-11-01). + * net/ipforward: Fixes typo that caused build error when IP forwarding + was enabled with CONFIG_NET_ICMPv6_NEIGHBOR enabled as well. From + Anthony Merlino (2017-11-01). + * ieee802154: Simplifies notify() and rxframe() calls to a single + notify() call. dataind's and all other "notifs" are now "primitives" + which aligns with standard terminology From Anthony Merlino (2017-11-01). + * fs/userfs: Correct check for response type (2017-11-01). + * net/local: This commit modifies the Unix domain local socket design. + Local sockets are built on top of pipes. The Local socket + implementation maintained file descriptors to interrupt with the pipes. + File descriptors have the bad property that they are valid only while + running on the thread within the task that created the local socket. + + As a policy, all internal OS implementations must use "detached" files + which are valid in any context and do not depend on the validity of a + file descriptor at any point in time. This commit converts the usage + of file descriptors to detached files throughout the local socket + implementation (2017-11-02). + * fs/userfs: There are some deadlock issues that make the UserFS + un-usable at the current time. Added to the TODO list; also feature is + now marked EXPERIMENTAL (2017-11-02). + * drivers/serial/serial.c: Optimize wait time in tcdram() for buffer + emptying. According to the specification, the close function must wait + until all data has been written before it closes the file (except + O_NONBLOCK is set). The maximum waiting time for this is not specified. + + To be able to edit the file list of the process, the close function + has to lock the file list semaphore. After that the close function of + the serial driver is called. + + Waiting for the complete transmission of all data is done in the + serial driver. This causes the semaphore to remain locked until all + data has been sent. However, no other thread of the process can edit + the file list for that time (open, close, dup2, etc.). This is not + optimal in a multithreaded environment. Therefore, we have to keep + the waiting time within the driver as short as possible. From Frank + Benkert (2017-11-02). + * drivers/loop: Don't use file descriptors... Use the internal file + system interfaces so that the loop device can be shared across threads + (2017-11-02). + * drivers/mtd/filemtd.c: Don't use file descriptors... Use the internal + file system interfaces so that the loop device can be shared across + threads (2017-11-02). + * mac802154: Fixes a warning for unused variable and returns -1 from + macnet_notify() if event is not used. From Anthony Merlino (2017-11-03). + * drivers/lcd/max7219.c: Add support to MAX7219 LED Matrix as LCD + interface. From Alan Carvalho de Assis (2017-11-04). + * configs/stm32f103-minimum: Add board support for MAX7219 LED Matrix + controller. From Alan Carvalho de Assis (2017-11-04). + * stm32f334-disco, nucleo-f334r8: add missing ram_vectors configuration + in linker script. From Mateusz Szafoni (2017-11-04). + * Kconfigs: Add CONFIG_LCD_UPDATE that works like CONFIG_NX_UPDATE but + can be enabled without enabling the graphics subsystem (2017-11-04). + * SAMv71-XULT: Remove non-functional framebuffer configuration + (2017-11-05). + * stm32f103-minimum: Remove warning when selecting MMCSD support, Add + board_usbmsc_initialize to stm32f103-minimum. From Alan Carvalho de + Assis (2017-11-05). + * nucleo-f334r8/highpri: missing ADC trigger configuration. From + Mateusz Szafoni (2017-11-05). + * stm32f334-Disco: beginning of lower-half driver for SMPS (buck-boost + onboard converter). From Mateusz Szafoni + * Misc. STM32 Fixes: + - STM32 HRTIM: add helper macros + - STM32F33xxx ADC: injected channels support, fix some definitions, + add interface to disable interrupts + From Mateusz Szafoni (2017-11-05). + * fs/userfs: This commit converts the underlying IPC used by the + UserFS from Unix domain local sockets to UDP LocalHost loopback + sockets. The problem with the local sockets is that they do require + operations on the top level psuedo-file system inode tree. That tree + must be locked during certain traversals such as enumerate mountpoints + or enumerating directory entries. + + This conversion is unfortunate in the sense that Unix local domain + sockets are relatively lightweight. LocalHost UDP sockets are much + heavier weight since they rely on the full UDP stack. If anyone is + up for a complete redesign, then using some shared memory and a POSIX + message queue would be lightweight again. + + This commit also fixes several bugs that were not testable before the + inode tree deadlock. I cannot say that the logic is 100% stable but + it does not have basic functionality (2017-11-05). + * fs/userfs: Fix return value from dup method. In order to return a + pointer, the parameter must be a pointer to a pointer (2017-11-06). + * configs/stm32f429i-disco/ltdc: This configuration has been deleted + because it violated the portable POSIX OS interface. It used + apps/examples/ltdc and include ltdc.h and dma2d.h which were also + removed for the same reason (2017-11-06). + * arch/arm/include/stm32 and stm32f7: Remove ltdc.h and dma2d.h. + Those header files in that location permitted inclusion into + application space logic and, hence, facilitated and encouraged calling + into the OS and violating the portable POSIX OS interface. The + definitions in those header files were move the appropriate location in + the counterpart, architecture specific files at arch/arm/src/stm32 and + stm32f7 dma2d.h and ltdc.h (2017-11-06). + * lpc43xx Ethernet: Fix some backward logic setting full-duplex and + 100mbps when autoconfiguration is disabled. Noted by Anonymous in + Issue #76 (2017-11-06). + * sched/sched/sched_cpuselect.c: For SMP, In order to find the cpu + with the lowest priority thread, we have to remember the already found + lowest priority. Noted by Anonymous in Issue #75 (2017-11-06). + * Add IPL2 support for LC823450 + - arch/arm/src/lc823450: Add IPL2 support + - configs/lc823450-xgevk: Add IPL2 support + From Masayuki Ishikawa (2017-11-07). + * drivers/audio: Add WM8774 support. From Masayuki Ishikawa + (2017-11-08). + * lc823450-xgevk audio support + - arch/arm/src/lc823450: Add IPL2 support + - configs/lc823450-xgevk: Add IPL2 support + - libc/audio: Fix compilation error in lib_buffer.c + - arch/arm/src/lc823450: Add I2S support + - configs/lc823450-xgevk: Add WM8774 support + From Masayuki Ishikawa (2017-11-08). + * drivers/usbdev/rndis.c: fix packet receiving logic. The logic didn't + take single-byte termination frames in account. From Sakari Kapanen + (2017-11-08). + * net/icmpv6/icmpv6_radvertise.c: Add option to manually specify router + prefix. From Sakari Kapanen (2017-11-08). + * net/icmpv6/icmpv6_radvertise.c: set the prefix length to + preconfigured value (2017-11-08). + * STM32 L4 RCC: restore backup-registers after backup-domain reset. + From Jussi Kivilinna (2017-11-08). + * STM32 L4: Build stm32l4_idle.c only if CONFIG_ARCH_IDLE_CUSTOM is + not enabled. From Jussi Kivilinna (2017-11-08). + * drivers/power/bq2429x.c: Add BATIO_OPRTN_SYSON for enabling BATFET + after SYSOFF. From Jussi Kivilinna (2017-11-08). + * lc823450 auto LED support + - arch/arm/src/lc823450: Add auto LED for CPU activity + - configs/lc823450-xgevk: Add auto LED support + From Masayuki Ishikawa (2017-11-09). + * tools/configure.sh: This commit adds a -m option for macOS. For + anyone not aware, Apple renamed OSX to macOS recently; thus the 'm' + instead of 'o'. This does not change the other uses of *_OSX to macOS. + From jeditekunum (2017-11-09). + * tools/configure.c: Update functionality to match last change to + tools/configure.sh (2017-11-10). + * STM32L4 serial PM interface improvements: Check rx/tx buffers for + pending data in pmprepare. Remove adhoc PM interfaces and move serial + suspend functionality behind CONFIG_PM. From Jussi Kivilinna + (2017-11-10). + * procfs: Fix uptime being clse to maximum 32-bit value in certain + config. From Juha Niskanen (2017-11-10). + * libc: Add support for readv() and write(). Also includes some + cosmetic changes to some unrelated files (2017-11-11). + * libc/signal: Add support for sigwait() (2017-11-11). + * sched/signal/sig_nanosleep.c and libc/time/lib_nanosleep.c: + Implement clock_nanosleep(). nanosleep() is now reduced to a libc + wrapper around clock_nanosleep() (2017-11-11). + * Changes from review of clock_nanosleep(): Misplaced right bracket, + but return value in one failure case (2017-11-11). + * include/netinet/tcp.h: Add trivial standard tcp.h header file + (2017-11-12). + * Trivial re-ordering of socket option bit numbers to match order + presented on OpenGroup.org (2017-11-12). + * arch/arm/src/stm32/stm32f33xx_adc.c: Eliminate warnings about + cj_channels and j_chanlist being set but not used (2017-11-12). + * configs/stm32l476-mdk: Add support for the on-board LEDs (2017-11-12). + * include/netinet/tcp.h: Add trivial standard tcp.h header file + (2017-11-12). + * configs/stm32l476-mdk: Repartition bring-up logic so that it is more + like other board directories. Add support for USERLED driver. Add + bring-up initialization logic for the USERLED driver (2017-11-12). + * drivers/usbdev/rndis.c: Fix some issues in rndis.c Introduce + rndis_transmit() and change rndis_rxdispatch() to avoid packet + corruption. Introduce max packet size for dual speed whichis mainly + used for high speed mode. Fix adjusting MTU warning on Linux host. Fix + data corruption if a packet size excceds MTU. NOTE: Max packet size is + not configured dynamically. This should be fixed in the future + version. Change HPWORK to ETHWORK. NOTE: In the commit 07b98ccbb5, + max packet size of bulkout was assumed to be 64. In this commit, + priv->epbulkout->maxpacket is used instead. From Masayuki Ishikawa + (2017-11-13). + * configs/stm32f4discovery: RNDIS support on STM32F4Discovery + - Add rndis configuration. NOTE: STM32F4Discovery + DM-STF4BB + - Add stm32_netinit.c to avoid a compilation error + - Add rndis initialization in stm32_bringup.c + NOTE: MAC address for the host side starts 0xaa. This assignment + scheme should be fixed later. From Masayuki Ishikawa (2017-11-13). + * configs/: apps/system/free has been deleted because it violates the + portable POSIX OS interface. Remove CONFIG_SYSTEM_FREE=y from all + defconfig files (2017-11-13). + * fs/procfs/fs_procfsprogrem: Add /proc/progmem. This is an + alternative way to get the information that was previoulsy available in + apps/system/free. apps/system/free was removed beause it made illegal + calls into the OS violating the portable interface. This new procfs + entry provides the same information with no such violation (2017-11-13). + * Nucleo-F746ZG: Use the serial console over /dev/ttyACM0 by default. + The Nucleo-F746ZG doesn't come with Arduio RS-232 shield, then it is + better to use the serial over the /dev/ttyACM0 that is created + automatically when the board is plugged in the computer. From Alan + Carvalho de Assis (2017-11-13). + * SAMA5/SAMv7: It is necessary to disable pre-emption and interrupts + around a loop that copies TX data into the hardware in order to avoid a + TX data underrun condition. From Anthony Merlino (2017-11-13). + * fs/profcs: Add file to show user space heap. This replaces the NSH + free command (2017-11-13). + * fs/procfs: Optimization of previous commits. /proc/umm and + proc/progmem are deleted. /proc/kmm is renamed /proc/meminfo and + contains the output that was in all three files previously (2017-11-13). + * configs/stm32f439i-disco: Add an fb configuration (2017-11-13). + * configs/stm32f429i-disco/fb: Fix a compile issue. Disable all NX + features in the fb configuration. NX is not needed (2017-11-13). + * configs/stm32f429i-disco/fb: Refactor initialization logic so that + it is a little more like other boards. Remove double initialization of + framebuffer or LCD drivers (whichever is enabled) (2017-11-13). + * configs/stm32f429i-disco: Add logic to auto-mount procfs. Enable + procfs in all configurations that use NSH (2017-11-13). + * configs/stm32f429-disco/fb: Enable support for the STMPE811 + touchscreen controller and also for the apps/exmaples/touchscreen test + (2017-11-14). + * Remove CONFIG_GRAN_SINGLE. It adds no technical benefit (other than + some minor reduction in the number of interface arguments) but adds a + lot of code complexity. Better without it (2017-11-14). + * mm/mm_gran: Add a function to get information about the state of the + granuale allocator (2017-11-14). + * fs/procfs: Add logic to show the state of the page allocator in + /proc/meminfo (2017-11-14). + * mm/mm_gran: Fix some issues found during test of the new gran_info() + interface (2017-11-14). + * configs/stm32429i-disco/src: Fix a compile error when + CONFIG_BOARD_INITIALIZE is defined (2017-11-14). + * configs/lc823450-xgevk: Fix compilation errors on Cygwin. From + Masayuki Ishikawa (2017-11-15). + * mm/mm_gran: Combine some common logic into a function (also fixes a + subtle bug) (2017-11-15). + * Build system: Fix CONFIG_BUILD_KERNEL logic directories that have + ubin and kbin subdirectories. Conditional logic was fine for + CONFIG_BUILD_FLAT and CONFIG_BUILD_PROTECTED but generated useless + dependencies if CONFIG_BUILD_KERNEL (2017-11-15). + * arch/arm/src/lpc43: Add LPC43xx CAN driver. From Alexander Vasiljev + (2017-11-15). + * arch/arm/src/lpc43: UART_RX pins should be configured with input + buffers enabled. Otherwise it cannot be read. From Alexander Vasiljev + (2017-11-15). + * STM32F429i-Disco: Convert NxWM configuration to use LTDC framebuffer + driver instead of SPI serial. Also reduce number of layers from 4 to 1 + in fb configuration. Only one layer is used (2017-11-15). + * configs/stm32f429i-disco/ide: Remove the uVision IDE setup that goes + along with the ltdc configuration that was removed on 2017-10-28 + (2017-11-16). + * configs/stm3220g-eval/ide: Remove the uVision IDE setup. This has + not been used for years and it a maintenance problem for me (2017-11-16). + * arch/arm/src/xmc4: Fix XMC4xxx USIC UART sginal to be high level when + in idle. From Alan Carvalho de Assis (2017-11-16). + * arch/arm/src/xmc4: Kconfig was not selecting XMC4_USIC for USIC1. + From Alan Carvalho de Assis (2017-11-16). + * configs/xmc4500-relax: Add config for UART3 on RXD P0.0 and TXD P0.1 + pins. From Alan Carvalho de Assis (2017-11-16). + * STM32 F72xx and F73xx: Add register definition header files and + clocking logic. From Bob Feretich (2017-11-17). + * STM32F7: Fix typos in two RCC register definition header files. + From Bob Feretich (2017-11-17). + * STM32F7: Completes architecture support for the STM32 F72x and F73x + families. Adds support for the Nucleo-144 boards with STM32F722. From + Bob Feretich (2017-11-18). + * configs/sim: Disable NX graphics support in the fb configuration. + * libnx: Changes to allow the font subsystem to be built without + enabling the entire graphics system (CONFIG_NX). Adds CONFIG_NXFONTS + and CONFIG_NXGLIB. NX and NXFONTS are still pretty heavily entangled. + Needed to duplicate some Kconfig setting for NXFONTs if it can be + configured and built independently of NX. Also includes some + build-related fixes (2017-11-18). + * configs/mcb1700: Add support for Keil MCB1700 board. From Alan + Carvalho de Assis (2017-11-18). + * configs/open1788/pdcurses: Add a configuration for testing pdcurses + (2017-11-19). + * C library: Fix sscanf character conversion (%c): do not add '\0' at + the end as for strings, cause, for example, parsing one character will + fill two bytes: character itself and zero one '\0' after it, so will + overflow one byte variable argument and corrupt memory for variables + allocated after it. From Oleg Evseev (2017-11-19). + * arch/arm/src/xmc4:xmc4_uart_configure() expects the channel# not + uartbase as an input parameter. From Alan Carvalho de Assis + (2017-11-20). + * configs/open1788: Add support for the discrete joystick driver. + Update the pdcurses configuration to use apps/examples/djoystick + (2017-11-20). + * net/icmpv6: icmpv6_input() needs to set d_len to 0 after consuming + echo reply, otherwise, garbage will get sent out. From Anthony Merlino + (2017-11-20). + * configs/open1788: Enable discrete joystick input. This is + sufficient to get through all menuing that does not require text input + (2017-11-20). + * net/sixlowpan: Fix an endian-ness problem in 6LoWPAN address + decompression. From Anthony Merlino (2017-11-20). + * net/sixlowpan: The logic that extracts interface identifier from the + IP address needs to be generalized to handle cases where the address is + not a link local address. From Anthony Merlino (2017-11-20). + * arch/arm/src/xmc4 UART: Enable RX/TX status and small fixes. From + Alan Carvalho de Assis (2017-11-21). + * Various fixes for errors ound while debugging OTG on L496 + - STM32, STM32 L4, and STM32 M4: USB OTGFS DMA trace output fix + - STM32: Add dump buffer feature to stm32 F4 series + - STM32 and STM32 L4: Fix bad USB OTGFS register address + - STM32 L4: Fix typo in USB OTGFS register usage + - STM32 L4: Add check in USB OTGFS driver to assure that SYSCFG is + enabled + - Nucleo-L496ZG: Make HSE on Nucleo-L496ZG default to enable USB + From Miha Vrhovnik (2017-11-21). + * Two changes for STM32F7. + 1) The first enables building with CONFIG_ARCH_IDLE_CUSTOM enabled. + 2) The second allows changing voltage output scaling setting and + prevents enabling over-drive mode for low frequencies (STM32 F74xx, + 75xx, 76xx, 77xx) + From Jussi Kivilinna (2017-11-21). + * Replicate Jussi Kivilinna's change for the newly added STM32F2xx and + F3xx family members. This change allows selecting voltage output scale + mode and enable over-drive only when needed (2017-11-21). + * mm: Add a debug assertion to check for integer overflow in malloc + (2017-11-21). + * net/icmpv6: Fix an error in the poll logic. It was assume that the + input parmeter pvconn was valid. It was not. Instead, the poll logic + must work like the sendto() and recvfrom() logic: It must keep a copy + of the conn structure in the private data (2017-11-21). + * net/icmpv6: Remove the 'list' field from struct icmpv6_conn_s. It + is not used (2017-11-21). + * net/icmp: Ports the changes in ICMPv6 of commits + 4629cf9461e5ac6f5f01ef8c9bee3ec9a60ce081 and + 74a633ea94bc308cd2eca0ec6c2be798d5794e72 to ICMP. ICMP and ICMPv6 + sockets are nearly identical, bug-for-bug (2017-11-21). + * net/sixlowpan: Add htohs() in arguments to debug statements that + print IP addresses so that they are all shown in friendlier host + order. From Anthony Merlino (2017-11-21). + * stm32f33xxx_rcc: Fix CAN clock enable. From Mateusz Szafoni + (2017-11-22). + * drivers/lcd_framebuffer.c: If BPP is less then 8, then we need to + byte-align the update region (2017-11-22). + * configs/stm32f103-minimum: Add framebuffer driver initialization for + stm32f103-minimum board. From Alan Carvalho de Assis (2017-11-22). + * mm: Fix a typo in a debug assertion (2017-11-22). + * net/icmp and icmpv6: Fix some errors in debug assertions introduced + with last changes in this area. Also updates a REAME.txt file + (2017-11-22). + * net/: Fix some issues with regard to UDP broadcast handling. This + is Bitbucket Issue #77. This commit tentatively closes the issues, + subject to verification (2017-11-22). + * sixlowpan: Support sending to a router that is on-link and may be + able to forward the packet for us if the destination is not reachable + directly. From Anthony Merlino (2017-11-22). + * Pass header-payload offset to application for use when the MAC layer + is in promiscuous mode + - mac802154_device: When in promiscuous mode, the char driver sends + the entire frame, including the MAC header. This change adds an + offset field indicating the header-payload boundary. It is set to 0 + when not in promiscuous mode as the header is not passed to the + application + - mac802154: Adds support for getting promiscuous mode state + From Anthony Merlino (2017-11-22). + * USB RNDIS - Fixes minor build error while using USB RNDIS with USB + debugging information enabled. From Anthony Merlino (2017-11-22). + * clicker2-stm32: Adds support for USB RNDIS device. From Anthony + Merlino (2017-11-22). + * STM32 L4 USB OTGFS: Remove dumpbuffer feature added in the last + commit. I don't want in features that cannot be controlled be via + Kconfig files and I do not accept debug code in the upstream GIT. My + mistake for merging it in the first place (2017-11-22). + * include/nuttx/video/fb.h: Add definition for a Y2 color format. I + don't know if this standard but I do have 2-bit greyscale hardware so + the definition is needed (2017-11-22). + * sixlowpan: Fixes build error introduced by recent PR when routing + table is enabled. From Anthony Merlino (2017-11-22). + * sixlowpan: Fixes build error introduced by recent PR when routing + table is enabled. From Anthony Merlino (2017-11-22). + * net/netdev: Add support for the SIOCGIFBRDADDR ioctl() command + (2017-11-22). + * include/nuttx/audio: Remove CONFIG_SCHED_WORKQUEUE check in pcm.h. + From Masayuki Ishikawa (2017-11-23). + * sched/semaphore/spinlock.c: Disable local interrupts in spin_setbit() + and spin_clrbit() in order to avoid a deadlock condition. From + Masayuki Ishikawa (2017-11-23). + * configs/stm32f4disovery: Add support for JLX12864G display on STM32F4 + Discovery board. From Alan Carvalho de Assis (2017-11-23). + * configs: All NX configuration... Because of recent changes to + libnx/nxfonts, Supported bit per pixel must be separated specified for + NXFONTs too and need to match the select BPP for NX (2017-11-24). + * fs/procfs: Correct ordering of procfs entries. For consistency, use + alphabetical ordering (2017-11-24). + * configs/xmc4500-relax: Setup max. freq. 120MHz and setup pull-up to + UART RXD pin. From Alan Carvalho de Assis (2017-11-24). + * arch/arm/src/xmc4: Do not run at 144MHz unless BOARD_FCPU_144MHZ is + selected in the board.h header file. From Alan Carvalho de Assis + (2017-11-24). + * configs/xtrs: Removed the XTRS configuration This was an unverified + port of NuttX to a TRS-80 simulator. It was removed because (1) it is, + as I said, unverified as well as unsupported, and (2) the TRS-80 + simulation is a sub-optimal platform. That platform includes a 16-bit + ROM image and only a 48Kb RAM space (2017-11-24). + * arch/arm/src/xmc4: Remove hard-coded values in clock configuration. + USB will be fixed later. From Alan Carvalho de Assis (2017-11-25). + * drivers/lcd: Add support for external LCD initialization required by + some board logic. configs/zpa214xpa: Tried to get the LCD working + again unsuccessfully. Too much bit rot I suppose (2017-11-25). + * STM32F4 Discovery: Fix some errors due to missing inclusion of + stm32_gpio.h (2017-11-25). + * XMC4 Serial: The Alternative Receive Interrupt was not being + configured (2017-11-25). + * drivers/lcd: Make LCD driver configuration indepently selected from + NX graphics configuration. This makes things awkward and loses some + error checking but is a necessary step in order to make LCD drivers + usable when the NX graphics system is disabled (2017-11-25). + * STM3240G-EVAL: Mount procfs if enabled (2017-11-25). + * arm/src/xmc4: Include Alt. Interrupt Enable to RX_EVENTS and rename + serial GPIO configurations. From Alan Carvalho de Assis (2017-11-25). + * configs/: CONFIG_QENCODER was renamed to CONFIG_SENSORS_QENCODER: + update occurrences in several Kconfig files (2017-11-25). + * configs/stm3240g-eval: Add support for pdcurses and the pdcurses + demo programs in the 'fb' configuration (2017-11-26). + * arch/arm/src/stm32: Fix compile error when trace is enabled. + I2CEVENT_ERROR was used but never defined (2017-11-26). + * configs/lc823450-xgevk: Enable CONFIG_SMP for audio.Update README.txt + regarding SMP audio. From Masayuki Ishikawa (2017-11-27). + * lc823450 smp audio + - arch/arm/src/lc823450: Remove a workaround in up_cpu_paused(). + Introduce g_gpio_lock to improve write performance in SMP mode. + NOTE: This is a tentative solution and should be replaced with more + generic one. Add a workaround in up_txready() to avoid data + corruption. From Masayuki Ishikawa (2017-11-27). + * arch/arm/src/lpc43xx: lpc43_adc.c was being selected by the build + system wehn DAC was selected (2017-11-27). + * configs/lc823450-xgevk: Add rndis configuration. From Masayuki + Ishikawa (2017-11-28). + * drivers/input/nunchuck.c: Add Nintendo Wii Nunchuck driver. From + Alan Carvalho de Assis (2017-11-28). + * configs/stm32f4discovery/include/board.h: Remove only I2C pin config, + we can use PB6 and PB9. From Alan Carvalho de Assis (2017-11-28). + * configs/stm32f4discovery/src: Add stm32f4discovery board support for + Nunchuck joystick. From Alan Carvalho de Assis (2017-11-28). + * net/devif: Do not add link layer header size to d_len inside + devif_forward(). From Anthony Merlino (2017-11-29). + * Framebuffer Driver: Small modification convention for multi-planar + displays (of which there are none) (2017-11-29). + * configs/stm32f103-minimum: Add Nunchuck board support for + stm32f103-minimum board. From Alan Carvalho de Assis (2017-11-29). + * drivers/mtd: Add a driver for Macronix MX35LFxGE4AB serial NAND + flash. From Ekaterina Kovylova (2017-11-29). + * net/pkt: Eliminate a compile error due to missing include and also a + warning (2017-11-29). + * sched/task/task_exithook.c: Clear atexit() function pointer before + calling it. On most archs, up_assert() calls exit() so without this + change, if atexit() function triggers an assertion we are in endless + loop. From Juha Niskanen (2017-11-30). + * arch/arm/src/xmc4/Kconfig: Define user friendly SPI, I2C, LIN, and + I2S aliases to follow other arch names. From Alan Carvalho de Assis + (2017-11-30). + +7.24 2018-xx-xx Gregory Nutt diff --git a/Directories.mk b/Directories.mk index 2e55b91a94007f210ad4b6ab58700092a32e3bb3..cabca719ab17967c37fff1796c0d5601f7c0407c 100644 --- a/Directories.mk +++ b/Directories.mk @@ -1,7 +1,8 @@ ############################################################################ # Directories.mk # -# Copyright (C) 2007-2012, 2014, 2016 Gregory Nutt. All rights reserved. +# Copyright (C) 2007-2012, 2014, 2016-2017 Gregory Nutt. All rights +# reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -121,6 +122,10 @@ endif ifeq ($(CONFIG_NX),y) NONFSDIRS += graphics libnx CONTEXTDIRS += graphics libnx +else ifeq ($(CONFIG_NXFONTS),y) +NONFSDIRS += libnx +CONTEXTDIRS += libnx +OTHERDIRS += graphics else OTHERDIRS += graphics libnx endif @@ -131,7 +136,7 @@ else OTHERDIRS += audio endif -ifeq ($(CONFIG_DRIVERS_WIRELESS),y) +ifeq ($(CONFIG_WIRELESS),y) NONFSDIRS += wireless else OTHERDIRS += wireless diff --git a/Documentation/NuttShell.html b/Documentation/NuttShell.html index a4056e6d66231fa1eb8ce6736e09e09aa6938d29..c23950484cd83895c4f1a664914846070a2625fd 100644 --- a/Documentation/NuttShell.html +++ b/Documentation/NuttShell.html @@ -8,7 +8,7 @@

NuttShell (NSH)

-

Last Updated: October 24, 2017

+

Last Updated: January 10, 2018

@@ -443,61 +443,67 @@
- 2.60 Unmount a File System (umount) + 2.60 Set the Size of a File (truncate)
- 2.61 Print system information (uname) + 2.61 Unmount a File System (umount)
- 2.62 Unset an Environment Variable (unset) + 2.62 Print system information (uname)
- 2.63 URL Decode (urldecode) + 2.63 Unset an Environment Variable (unset)
- 2.64 URL Encode (urlencode) + 2.64 URL Decode (urldecode)
- 2.65 Add a New User (useradd) + 2.65 URL Encode (urlencode)
- 2.66 Delete a user (userdel) + 2.66 Add a New User (useradd)
- 2.67 Wait for Microseconds (usleep) + 2.67 Delete a user (userdel)
- 2.68 Get File Via HTTP (wget) + 2.68 Wait for Microseconds (usleep)
- 2.69 Hexadecimal Dump of Memory (xd) + 2.69 Get File Via HTTP (wget) + + + +
+ + 2.70 Hexadecimal Dump of Memory (xd) @@ -1593,13 +1599,16 @@ dirname <path>

Command Syntax:

    -echo [<string|$name> [<string|$name>...]]
+echo [-n] [<string|$name> [<string|$name>...]]

Synopsis. Copy the sequence of strings and expanded environment variables to console output (or to a file if the output is re-directed).

+

+ The -n option suppresses the trailing newline character. +

@@ -2977,7 +2986,35 @@ nsh>
+ +
-

2.60 Unmount a File System (umount)

 +

2.60 Set the Size of a File (truncate)

 +
+ +

Command Syntax:

+
    +truncate -s <length> <file-path>
+
+

+ Synopsis. + Shrink or extend the size of the regular file at <file-path> to the + specified<length>. +

+

+ A <file-path> argument that does not exist is created. The <length> + option is NOT optional. +

+

+ If a <file-path> is larger than the specified size, the extra data is + lost. If a <file-path> is shorter, it is extended and the extended part + reads as zero bytes. +

+ + + + +
+

2.61 Unmount a File System (umount)
@@ -3007,7 +3044,7 @@ nsh>
-

2.61 Print system information (uname)

 +

2.62 Print system information (uname)
@@ -3074,7 +3111,7 @@ uname [-a | -imnoprsv]
-

2.62 Unset an Environment Variable (unset)

 +

2.63 Unset an Environment Variable (unset)
@@ -3100,7 +3137,7 @@ nsh>
-

2.63 URL Decode (urldecode)

 +

2.64 URL Decode (urldecode)
@@ -3117,7 +3154,7 @@ urldecode [-f] <string or filepath>
-

2.64 URL Encode (urlencode)

 +

2.65 URL Encode (urlencode)
@@ -3134,7 +3171,7 @@ urlencode [-f] <string or filepath>
-

2.65 Add a New User (useradd)

 +

2.66 Add a New User (useradd)
@@ -3151,7 +3188,7 @@ useradd <username> <password>
-

2.66 Delete a user (userdel)

 +

2.67 Delete a user (userdel)
@@ -3168,7 +3205,7 @@ userdel <username>
-

2.67 Wait for Microseconds (usleep)

 +

2.68 Wait for Microseconds (usleep)
@@ -3185,7 +3222,7 @@ usleep <usec>
-

2.68 Get File Via HTTP (wget)

 +

2.69 Get File Via HTTP (wget)
@@ -3212,7 +3249,7 @@ wget [-o <local-path>] <url>
-

2.69 Hexadecimal Dump of Memory (xd)

 +

2.70 Hexadecimal Dump of Memory (xd)
@@ -3639,6 +3676,11 @@ nsh>   CONFIG_NSH_DISABLE_TIME + + truncate + !CONFIG_DISABLE_MOUNTPOINT && CONFIG_NFILE_DESCRIPTORS > 0 + CONFIG_NSH_DISABLE_TRUNCATE + umount !CONFIG_DISABLE_MOUNTPOINT && CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_FS_READABLE3 @@ -5443,10 +5485,10 @@ xxd -i romfs_img >nsh_romfsimg.h
  • CONFIG_NSH_ARCHROMFS
  • CONFIG_NSH_ROMFSMOUNTPT
  • CONFIG_NSH_ROMFSSECTSIZE
    • +
  • CONFIG_NSH_STRERROR
      • -
    • nfsmount
      • -
    • nice
    • NSH library (nshlib)
    • NSH library (nshlib)
    • nsh_consolemain()
      • @@ -5565,6 +5607,7 @@ xxd -i romfs_img >nsh_romfsimg.h
    • telnetd
    • test
    • time
      • +
    • truncate
    • umount
    • uname
    • unset
      • diff --git a/Documentation/NuttX.html b/Documentation/NuttX.html index f4f506deff15bc64863280cad4a3e7729e29d3c2..78b47792639e57e65ba202fd2b20a89104f819e6 100644 --- a/Documentation/NuttX.html +++ b/Documentation/NuttX.html @@ -8,7 +8,7 @@

      NuttX RTOS

      -

      Last Updated: October 28, 2017

      +

      Last Updated: December 4, 2017

      @@ -556,6 +556,14 @@

      + +
      + +

      +

    • UserFS - User application file system.
      • +

      + +
      @@ -808,7 +816,7 @@

      -

    • Special INET protocol sockets: Raw ICMP and ICMPv6 protocol ping sockets (IPPROTO_ICMP).
      • +
    • Special INET protocol sockets: Raw ICMP and ICMPv6 protocol ping sockets (IPPROTO_ICMP/IPPROTO_ICMP6).

      • @@ -1073,7 +1081,7 @@

      -

    • Device-dependent USB class drivers available for USB serial (CDC/ACM and a PL2303 emulation), for USB mass storage, and for a dynamically configurable, composite USB devices.
      • +
    • Device-dependent USB class drivers available for USB serial (CDC/ACM and a PL2303 emulation), for USB mass storage, for RNDIS networking, and for a dynamically configurable, composite USB devices.

      • @@ -1417,11 +1425,11 @@

      Released Versions

      In addition to the ever-changing GIT repository, there are frozen released versions of NuttX available. - The current release is NuttX 7.22. - NuttX 7.22 is the 122nd release of NuttX. - It was released on September 6, 2017, and is available for download from the + The current release is NuttX 7.23. + NuttX 7.23 is the 123rd release of NuttX. + It was released on December 4, 2017, and is available for download from the Bitbucket.org website. - Note that the release consists of two tarballs: nuttx-7.22.tar.gz and apps-7.22.tar.gz. + Note that the release consists of two tarballs: nuttx-7.23.tar.gz and apps-7.23.tar.gz. Both may be needed (see the top-level nuttx/README.txt file for build information).

      @@ -1430,7 +1438,7 @@
      • nuttx.

          - Release notes for NuttX 7.22 are available here. + Release notes for NuttX 7.23 are available here. Release notes for all released versions on NuttX are available in the Bitbucket GIT. The ChangeLog for all releases of NuttX is available in the ChangeLog file that can viewed in the Bitbucket GIT. The ChangeLog for the current release is at the bottom of that file. @@ -1438,7 +1446,7 @@

      • apps.
      • Atmel AVR
        • +
      • Broadcom + +
      • Expressif @@ -5005,6 +5053,29 @@ Mem: 29232 5920 23312 23312 Also refer to the NuttX board README file for further information.

        + + +
        +
        + + +
        + +

        + STMicro STM32 F72x/F73x. + Support for the F72x/F73x family was provided by Bob Feretich in NuttX-7.23. + A single board is supported in this family: +

        +
          +

          + Nucleo F722ZE. + This is a member of the common board support for the common Nucleo-144 boards, this one featuring the STM32F722ZE. + This port was also provided by Bob Feretich in NuttX-7.23. + See the board README.txt file for further information. +

          +
        + +
        @@ -5936,10 +6007,16 @@ BFD_ASSERT (*plt_offset != (bfd_vma) -1);

          STATUS: - Basically the same as for the Z80 instruction set simulator. - This port was contributed by Jacques Pelletier. - Refer to the NuttX board README file for further information. + Basically the same as for the Z80 instruction set simulator. + This port was contributed by Jacques Pelletier. + Refer to the NuttX board README file for further information.

          +

          + NOTE: + This port was removed from the NuttX source tree on 2017-11-24. + It was removed because (1) it is unfinished, unverified, and unsupported, and (2) the TRS-80 simulation is a sub-optimal platform.i + That platform includes a 16-bit ROM image and only a 48Kb RAM space for NuttX. + The removed board support is still available in the Obsoleted repository if anyone would ever like to resurrect it.

            diff --git a/Documentation/NxWidgets.html b/Documentation/NxWidgets.html index 2d88d2bf48652bf3203914405ab65e1976378ed4..69344dc918c1e4b31d3b21ac6674e2161637484a 100644 --- a/Documentation/NxWidgets.html +++ b/Documentation/NxWidgets.html @@ -8,11 +8,11 @@

            NxWidgets

            -

            Last Updated: March 27, 2012

            +

            Last Updated: November 7, 2017

            -

            NXWidgets

            +

            NxWidgets

            In order to better support NuttX based platforms, a special graphical userinterface has been created called NXWidgets. NXWidgets is written in C++ and integrates seamlessly with the NuttX NX graphics subsystem in order to provide graphic objects, or "widgets," in the NX Graphics Subsystem @@ -61,10 +61,10 @@

            • - NxWidgets-1.15: - Documentation, - Release notes, and - Downloads + NxWidgets-1.18: + Documentation, + Release notes, and + Downloads

              • diff --git a/Documentation/README.html b/Documentation/README.html index ad6e4ac1ab74bcfcb2fad863ea95f3aa7974156d..bad25c87e1afddb02e2188b5da4fc9889137bd08 100644 --- a/Documentation/README.html +++ b/Documentation/README.html @@ -8,7 +8,7 @@

              NuttX README Files

              -

              Last Updated: October 7, 2017

              +

              Last Updated: January 8, 2018

              @@ -103,6 +103,10 @@ nuttx/ | | `- README.txt | |- fire-stm32v2/ | | `- README.txt + | |- flipnclick-pic32mz/ + | | `- README.txt + | |- flipnclick-sam3x/ + | | `- README.txt | |- freedom-k64f/ | | `- README.txt | |- freedom-k66f/ @@ -114,6 +118,8 @@ nuttx/ | |- hymini-stm32v/ | | |- RIDE/README.txt | | `- README.txt + | |- indium-f7/ + | | `- README.txt | |- kwikstik-k40/ | | `- README.txt | |- launchxl-tms57004/ @@ -138,10 +144,14 @@ nuttx/ | | `- README.txt | |- lpcxpresso-lpc1768/ | | `- README.txt + | |- lpcxpresso-lpc54628/ + | | `- README.txt | |- maple/ | | `- README.txt | |- mbed/ | | `- README.txt + | |- mcb1700/ + | | `- README.txt | |- mcu123-lpc214x/ | | `- README.txt | |- micropendous3/ @@ -285,8 +295,8 @@ nuttx/ | |- stm32f411e-disco/ | | `- README.txt | |- stm32f429i-disco/ + | | |- fb/README.txt | | |- ide/ltcd/uvision/README.txt - | | |- ltdc/README.txt | | `- README.txt | |- stm32f746g-disco/ | | `- README.txt @@ -326,12 +336,10 @@ nuttx/ | | `- README.txt | |- xmc4500-relax/ | | `- README.txt - | |- xtrs/ - | | `- README.txt | |- z16f2800100zcog/ - | | |- ostest/README.txt - | | |- pashello/README.txt - | | `- README.txt + | | |- ostest/README.txt + | | |- pashello/README.txt + | | `- README.txt | |- z80sim/ | | `- README.txt | |- z8encore000zco/ @@ -379,6 +387,7 @@ nuttx/ | |- zoneinfo/README.txt | `- README.txt |- libnx/ + | |- libnx/README.txt | `- README.txt |- libxx/ | `- README.txt diff --git a/FlatLibs.mk b/FlatLibs.mk index 0a05e84c4934c8fa7fd6501b71fb241667f77f29..ad29c24272ad0c6760ad764e011aa8920e8c6457 100644 --- a/FlatLibs.mk +++ b/FlatLibs.mk @@ -1,7 +1,8 @@ ############################################################################ # FlatLibs.mk # -# Copyright (C) 2007-2012, 2014, 2016 Gregory Nutt. All rights reserved. +# Copyright (C) 2007-2012, 2014, 2016-2017 Gregory Nutt. All rights +# reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -104,6 +105,8 @@ endif ifeq ($(CONFIG_NX),y) NUTTXLIBS += lib$(DELIM)libgraphics$(LIBEXT) NUTTXLIBS += lib$(DELIM)libnx$(LIBEXT) +else ifeq ($(CONFIG_NXFONTS),y) +NUTTXLIBS += lib$(DELIM)libnx$(LIBEXT) endif # Add libraries for the Audio sub-system diff --git a/Kconfig b/Kconfig index d5f4209c5d0472da5c490995c6f5c491b1965047..584db78620cfdc513e80cbb3b08256be46bc1dbf 100644 --- a/Kconfig +++ b/Kconfig @@ -1662,6 +1662,7 @@ endmenu menu "Graphics Support" source graphics/Kconfig +source libnx/Kconfig endmenu menu "Memory Management" diff --git a/KernelLibs.mk b/KernelLibs.mk index b1da6dbd0b9fd17feec4e93500621ef29dff09f7..b5ea4768aa29fd60e0bff81f3b49ab848aa83c27 100644 --- a/KernelLibs.mk +++ b/KernelLibs.mk @@ -99,6 +99,9 @@ ifeq ($(CONFIG_NX),y) NUTTXLIBS += lib$(DELIM)libgraphics$(LIBEXT) NUTTXLIBS += lib$(DELIM)libknx$(LIBEXT) USERLIBS += lib$(DELIM)libunx$(LIBEXT) +else ifeq ($(CONFIG_NXFONTS),y) +NUTTXLIBS += lib$(DELIM)libknx$(LIBEXT) +USERLIBS += lib$(DELIM)libunx$(LIBEXT) endif # Add libraries for the Audio sub-system diff --git a/LibTargets.mk b/LibTargets.mk old mode 100755 new mode 100644 diff --git a/Makefile.unix b/Makefile.unix index fbbb258afb593951ca5ed211ded3dd8f29c71b7e..ffe8d7ed6308ed8d4516ae6e00668303d9126bf0 100644 --- a/Makefile.unix +++ b/Makefile.unix @@ -568,7 +568,6 @@ clean: subdir_clean $(call DELFILE, _SAVED_APPS_config) $(call DELFILE, nuttx-export*) $(call DELFILE, nuttx_user*) - $(call DELFILE, .gdbinit) $(call DELFILE, .cproject) $(call DELFILE, .project) $(call CLEAN) @@ -587,6 +586,7 @@ endif $(call DELFILE, Make.defs) $(call DELFILE, .config) $(call DELFILE, .config.old) + $(call DELFILE, .gdbinit) # Application housekeeping targets. The APPDIR variable refers to the user # application directory. A sample apps/ directory is included with NuttX, diff --git a/ProtectedLibs.mk b/ProtectedLibs.mk index 5dd45a6fab8ffe1d5fdf62417f71987e5fc23e51..df3edddadb0449d682c9153590ff5b1a12cb3a4b 100644 --- a/ProtectedLibs.mk +++ b/ProtectedLibs.mk @@ -1,7 +1,8 @@ ############################################################################ # ProtectedLibs.mk # -# Copyright (C) 2007-2012, 2014, 2016 Gregory Nutt. All rights reserved. +# Copyright (C) 2007-2012, 2014, 2016-2017 Gregory Nutt. All rights +# reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -103,12 +104,11 @@ endif ifeq ($(CONFIG_NX),y) NUTTXLIBS += lib$(DELIM)libgraphics$(LIBEXT) -ifeq ($(CONFIG_BUILD_PROTECTED),y) NUTTXLIBS += lib$(DELIM)libknx$(LIBEXT) USERLIBS += lib$(DELIM)libunx$(LIBEXT) -else -NUTTXLIBS += lib$(DELIM)libnx$(LIBEXT) -endif +else ifeq ($(CONFIG_NXFONTS),y) +NUTTXLIBS += lib$(DELIM)libknx$(LIBEXT) +USERLIBS += lib$(DELIM)libunx$(LIBEXT) endif # Add libraries for the Audio sub-system diff --git a/README.txt b/README.txt index 0ab435362f1111073d240c488bbcc49d1fbb3fb5..adfead108410b4af248e67e7279135c3dfcb0157 100644 --- a/README.txt +++ b/README.txt @@ -1647,6 +1647,10 @@ nuttx/ | | `- README.txt | |- fire-stm32v2/ | | `- README.txt + | |- flipnclick-pic32mz/ + | | `- README.txt + | |- flipnclick-sam3x/ + | | `- README.txt | |- freedom-k64f/ | | `- README.txt | |- freedom-k66f/ @@ -1657,6 +1661,8 @@ nuttx/ | | `- README.txt | |- hymini-stm32v/ | | `- README.txt + | |- indium-f7 + | | `- README.txt | |- kwikstik-k40/ | | `- README.txt | |- launchxl-tms57004/ @@ -1681,10 +1687,14 @@ nuttx/ | | `- README.txt | |- lpcxpresso-lpc1768/ | | `- README.txt + | |- lpcxpresso-lpc54628/ + | | `- README.txt | |- maple/ | | `- README.txt | |- mbed/ | | `- README.txt + | |- mcb1700/ + | | `- README.txt | |- mcu123-lpc214x/ | | `- README.txt | |- micropendous3/ @@ -1827,8 +1837,8 @@ nuttx/ | |- stm32f411e-disco/ | | `- README.txt | |- stm32f429i-disco/ + | | |- fb/README.txt | | |- ide/ltcd/uvision/README.txt - | | |- ltdc/README.txt | | `- README.txt | |- stm32f746g-disco/ | | `- README.txt @@ -1868,8 +1878,6 @@ nuttx/ | | `- README.txt | |- xmc5400-relax/ | | `- README.txt - | |- xtrs/ - | | `- README.txt | |- z16f2800100zcog/ | | |- ostest/README.txt | | |- pashello/README.txt @@ -1922,6 +1930,8 @@ nuttx/ | | `- README.txt | `- README.txt |- libnx/ + | |- nxfongs + | | `- README.txt | `- README.txt |- libxx/ | `- README.txt diff --git a/ReleaseNotes b/ReleaseNotes index bf2a4cef9a7ed20e156e5cb763c2b90c80da73fa..d3302c654ece99e39973764ebd62d9a0a5c59cbd 100644 --- a/ReleaseNotes +++ b/ReleaseNotes @@ -15601,3 +15601,1107 @@ detailed bugfix information): use forward slashes for kconfig-frontends. interpreters/ficl - Reorder some targets that causes GNUwin32 make to behave badly. From Jeff. + +NuttX-7.23 Release Notes +------------------------ + +The 123rd release of NuttX, Version 7.23, was made on December 4, 2017, +and is available for download from the Bitbucket.org website. Note +that release consists of two tarballs: nuttx-7.23.tar.gz and +apps-7.23.tar.gz. These are available from: + + https://bitbucket.org/nuttx/nuttx/downloads + https://bitbucket.org/nuttx/apps/downloads + +Both may be needed (see the top-level nuttx/README.txt file for build +information). + +Additional new features and extended functionality: + + * Core OS: + + - sem_open() should return SEM_FAILED on any failures. This is change + in the POSIX specification since the original sem_open() was written + so many years ago. + - exec(): The non-standard interface exec() is now enshrined as a + official NuttX API. I really dislike doing this but I think that + this is probably the only want to load programs in the protected + mode. It is currently used by some example code under apps/ that + generate their own symbol tables for linking. Other file execution + APIs relay on a symbol table provided by the OS. In the protected + mode, the OS cannot provide any meaning symbol table for execution + of code in the user-space blob so that is they exec() is really + needed in that build case. And, finally, the interface is + completely useless and will not be supported in the KERNEL build + mode where the contrary is true: An application process cannot + provide any meaning symbolic information for use in linking a + different process. + - OS Internal Functions: Rename many OS internal functions so it is + clear that they are not part of the application interface. All + internal functions with the sem_* prefix became nxsem_*, sig* become + nxsig_*, mq_* become nxmq_*, etc. + - Cancellation Points: Add new cancellation point interface, + check_cancellation_point(). + - Signals: Add logic to wake up a thread that is waiting on a signal + if it is canceled. + - sigtimedwait(): Add logic to suppress the wait if there is a + pending cancellation. + - clock_nanosleep(): Implement clock_nanosleep(). nanosleep() is now + reduced to a libc wrapper around clock_nanosleep(). + - task_delete(): Do not permit user applications to delete kernel + threads. + - kthread_create(): Rename kernel_thread() to kthread_create() for + better naming consistency with task_create() and kthread_delete(). + - boardctl(): Remove the BOARDIOC_GRAPHICS_SETUP command. + - TCB: Move POSIX thread specific data from pthread TCB to common TCB + structure. This change allows using pthread_getspecific and + pthread_setspecific from main thread. Patch also enables using + pthread data with config option CONFIG_DISABLE_PTHREAD=y. From Jussi + Kivilinna. + - mm: Remove the CONFIG_GRAN_SINGLE configuration option. It adds no + technical benefit (other than some minor reduction in the number of + interface arguments) but adds a lot of code complexity. Better + without it. + - mm: Add a function to get information about the state of the + granule allocator. This is the moral equivalent of mallinfo(). + + * File Systems/Block and MTD Drivers + + - MT25Q Serial FLASH: Add support for Micron MT25Q series MT25Q128. + From Sebastien Lorquet. + - MX35LFxGE4AB: Add an MTD driver for Macronix MX35LFxGE4AB serial + NAND flash. From Ekaterina Kovylova. + - FileMTD: Add block device MTD interface. Block MTD interface + allows using block device directly as MTD instead of having to use + file-system in between. NOTE that this provides the opposite + capability of FTL which will let you use an MTD interface directly + as a block device. From Jussi Kivilinna. + - BCH: The character driver to block device access now supports an + IOCTL to get the geomtry of the underlying block device. + - mkfatfs: Remove mkfatfs from the OS. This is a user-space + application and belongs in apps, not in the OS. + - procfs: Implements procfs /proc/fs/blocks and /proc/fs/usage files, + replacing the NSH df command. Also implements procfs /proc/fs/mount + file, replacing the NSH mount command when there are no arguments. + - procfs: Add /proc/meminfo. This is an alternative way to get the + information that was previoulsy available in apps/system/free. + apps/system/free was removed beause it made illegal calls into the + OS violating the portable interface. This new procfs entry provides + the same information with no such violation. it also provides + information about the kernel heap (formerly /proc/kmm), about the + use of program memory(formerly /proc/progmem). And also information + for the page table usage in the KERNEL build. + - UserFS: Adds the UserFS client and of the UserFS feature in + general. Initially used Unix domain local sockets instead of + message queues. Easier to transfer big data in local sockets than + message queues. However, that lead to certain inescapable deadlock + conditions So the IPC was converted to UDP LocalHost loopback + sockets. The problem with the local sockets is that they do require + operations on the top level psuedo-file system inode tree. That + tree must be locked during certain traversals such as enumerate + mountpoints or enumerating directory entries. This conversion is + unfortunate in the sense that Unix local domain sockets are + relatively lightweight. LocalHost UDP sockets are much heavier + weight since they rely on the full UDP stack. + + * Graphics/Display Drivers: + + - Framebufer character driver: Add framebuffer character device driver. + - LCD Framebuffer: Add support for a generic front-end that will + convert any LCD driver into a framebuffer driver. + - Framebufer character driver: Include support for LCD drivers that + use a simulated framebuffer and must receive explicit notification + when there is an update to a region in the framebuffer. + - LCD: Make LCD driver configuration indepently selected from NX + graphics configuration. This makes things awkward and loses some + error checking but is a necessary step in order to make LCD drivers + usable when the NX graphics system is disabled. + + * Networking/Network Drivers: + + - Networking: Add implementation of logic for SIOCGIFCONF and + SIOCGLIFCOF IOCTL commnds. + - Network IOCTLs: Add support for the SIOCGIFBRDADDR ioctl() command. + - Routing Tables: Permit IPv4 and IPv6 routing tables to be of + different sizes. + - Routing Tables: Adds support for read-only routing tables. Prior + to this change, routing tables were only support in RAM and had to + be initialized with explicit logic to add the necessary routes to + the routing table. With this change, routes may be defined in the + pre-initialized, read-only routing table provided by the + board-specific logic. + This would be particularly useful, for example, in the case where + there is only a single network adaptor and you want all output + packets to go to the single adaptor in all cases. So for that + behavior you could add a read-only routing table to the + board-specific long that contains a single entry, the default route: + 0.0.0.0/0. + - Routing Tables. Added support for routing tables in files in a file + system. This might be useful for customized, per-unit routing + tables. There are two issues with it however: + 1. Reading from file system on a per packet basis could be slow. I + think it probably should have a small, in-memory cache of most + frequently used routes for good problem. + 2. Currently the delroute logic is disabled due to a problem with + the design. NuttX does not currently support truncate(). + Therefore, it is not possible to delete entries from the routing + table file. In this current implementation, that leaves the last + entry intact at the end of the file. An alternative design + might include a tag on each record to indicate if the record is + valid or not. That would work but would add complexity to the + other routing table functions. + - Routing Tables: Add support for an in-memory routing table cache in + order to improve performance when the routing table is retained in a + file. The cache holds the most recently used routing table entries + and so can eliminate some file access. Flush the in-memory cache + when any entry is deleted from the routing table. When a router + matching an IP address is found, add the routing table entry to the + cache. + - Routing Tables: Add logic to mark a route as most-recently-used in + the route cache. + - ICMP: This change adds support for semi-standard IPPROTO_ICMP + AF_INET datagram sockets. This replaces the old ad hoc, nonstandard + way of implementing ping with a more standard, socket interface. + - ICMPV6: This commit adds support for semi-standard IPPROTO_ICMP6 + sockets. This is a replacement for the non-standard ICMPv6 ping + support that violated the portable POSIX OS interface. + - ICMPv6: Add option to manually specify router prefix in router + advertisement message. From Sakari Kapanen. + - Local Sockets: This commit modifies the Unix domain local socket + design. Local sockets are built on top of pipes. The Local socket + implementation maintained file descriptors to interrupt with the + pipes. File descriptors have the bad property that they are valid + only while running on the thread within the task that created the + local socket. + As a policy, all internal OS implementations must use "detached" + files which are valid in any context and do not depend on the + validity of a file descriptor at any point in time. This commit + converts the usage of file descriptors to detached files throughout + the local socket implementation. + + * Wireless Networking/Wireless Drivers: + + - IEEE-802154: Adds support for receiving MAC events via IOCTL through + socket interface. From Anthony Merlino. + - IEEE-802154: Simplifies notify() and rxframe() calls to a single + notify() call. dataind's and all other "notifs" are now "primitives" + which aligns with standard terminology From Anthony Merlino. + - MAC802154: Add support for getting promiscuous mode state From + Anthony Merlino. + - MAC802154 Character Driver: When in promiscuous mode, the char + driver sends the entire frame, including the MAC header. This + change adds an offset field indicating the header-payload boundary. + It is set to 0 when not in promiscuous mode as the header is not + passed to the application + - 6LoWPAN: Remove CONFIG_NET_6LOWPAN_FRAMELEN. In this case where + multiple radios are supported, this may not be a constant. 6LoWPAN + now always queries the driver to get the maximum frame length. + - 6LoWPAN: Support sending to a router that is on-link and may be + able to forward the packet for us if the destination is not + reachable directly. From Anthony Merlino. + - XBee: Adds XBee S2C (802.15.4 firmware) support. XBee driver + emulates mac802154 interface. From Anthony Merlino. + + * Other Common Device Drivers: + + - PowerLED: Add upper-half driver for high power LED driver (powerled) + From Mateusz Szafoni. + - RTC Driver: Add periodic alarms to upper and lower halves. From + Juha Niskanen. + - Pipes: Fix writing large buffers not triggering POLLIN for reader + poll. From Jussi Kivilinna. + - USB CDC/ACM Device: Add support for RX flow control to the CDC/ACM + driver. + - USB CDC/ACM Device: Add support for flow control TERMIOs in CDC/ACM + driver. + - USB RNDIS Device: Add RNDIS-over-USB driver. From Sakari Kapanen + with added Hi-Speed support from Masayuki Ishikawa. + - Loop Driver: Don't use file descriptors... Use the internal file + system interfaces so that the loop device can be shared across + threads. + - APA102 LED controller: Add driver for APA102 LED controller. These + LEDs are used on LED Strips and are controlled over SPI. + - INA219. Add INA219 Driver. The INA219 is a combined voltage and + current sensor that can measure up to 26 volts and a current that + depends on an external shunt resistor. Connection happens via + i2c/smbus and the chip features a power supply rail that is + independent from the measured voltage, so it can measure low + voltages. Right now it measures bus voltage and current, and does + not use the internal calibrated current reading, nor the available + power measurement. From Sebastien Lorquet. + - PCA9555: The IRQ subsystem now supports passing a void * parameter + to IRQ handlers. Use that method to support multiple PCA9555 + devices, by passing a pointer to the device to the board defined irq + handler. Now the CONFIG_ for multiple PCA devices just allocates + device structures dynamically instead of statically when not enabled. + The same interrupt handler is entered with the device structure + parameter in all situations, multiple or single PCA. One should + still be careful if multiple PCA devices share the same IRQ. From + Sebastien Lorquet. + - APDS-9960: Add driver for the APDS-9960 gesture sensor. From Alan + Carvalho de Assis. + - MAX7219: Add support to MAX7219 LED Matrix as LCD interface. From + Alan Carvalho de Assis. + - WM8774: Add WM8774 audio DAC support. From Masayuki Ishikawa. + - Nunchuck: Add Nintendo Wii Nunchuck driver. From Alan Carvalho de + Assis. + + * Simulation + + - Simulation: Add a configuration for non-graphical testing of the + frambuffer character driver using apps/example/fb. + - Simulation: Add a configuration for testing the UserFS using + apps/examples/userfs. + + * Broadcom BCM2708: + + - BCM2708: Add enough infrastructrue (more stubs) to get a clean + compilation of the Pi Zero configuration (with many undefined things + at link time). This includes several register definition header + files (some from Alan Carvalho de Assis), basic interrupt handling + logic, boot-up files, GPIO support, tickless timer, build and + configuration logic + + * Broadcom BCM2708 Boards: + + - Raspberry Pi Zero. Basic board support at configs/pizero. Untested + in this release and still some remaining issues. + + * Infineon XMC4xxx Boards: + + - XMC4500-Relax: Add config for UART3 on RXD P0.0 and TXD P0.1 pins. + From Alan Carvalho de Assis. + + * NXP Freescale LPC17xx Boards: + + - Open1788: Add initialization of Framebuffer driver. Add + configuration for testing the framebuffer driver. + + * NXP Freescale LPC43xx Drivers: + + - LPC43xx: Add LPC43xx CAN driver. From Alexander Vasiljev. + + * NXP Freescale LPC43xx Boards: + + - MCB1700: Add support for Keil MCB1700 board. From Alan Carvalho de + Assis. + - Open1788: Add support for the discrete joystick driver. + - Open1788: Add a configuration for testing pdcurses with discrete + joystick. + + * On Semiconductor LC823450 + + - LC823450: Add ADC driver and watchdog drivers. From Masayuki + Ishikawa. + - LC823450: Add IPL2 support. From Masayuki Ishikawa. + - LC823450: Add I2S support. From Masayuki Ishikawa. + - LC823450: Add auto LED for CPU activity. From Masayuki Ishikawa. + + * On Semiconductor LC823450 Boards + + - LC823450-XGEVK: Enable ADC and watchdog driver. From Masayuki + Ishikawa. + - LC823450-XGEVK: Add IPL2 support. From Masayuki Ishikawa. + - LC823450-XGEVK: Add WM8774 support. From Masayuki Ishikawa. + - LC823450-XGEVK: Add auto LED support. From Masayuki Ishikawa. + - LC823450-XGEVK: Enable CONFIG_SMP for audio. From Masayuki Ishikawa. + - LC823450-XGEVK: Add rndis configuration. From Masayuki Ishikawa. + + * STMicro STM32: + + - ARM Kconfig: Add support for classic ARM11 architecture selections. + - STM32 Tickless: Removes the restriction to 16-bit counts when a + 32-bit timer is used for tickless operation on the stm32. As it + was, the restriction is very limiting, especially if one wants high + granularity and large achievable intervals and has the hardware + (namely the 32bit timers) available. From Rajan Gill. + - STM32 L4 Kconfig: Add some L486 and L496 chips. From Juha Niskanen + - STM32 F7: Adds architecture support for the STM32 F72x and F73x + families. From Bob Feretich. + - STM32 F7: Allow changing voltage output scaling setting and + prevents enabling over-drive mode for low frequencies (STM32 F74xx, + 75xx, 76xx, 77xx). From Jussi Kivilinna. Changes replicated for + the 72xx and 73xx families. + + * STMicro STM32 Drivers: + + - STM32 ADC: Added support for ADC's IO_ENABLE_TEMPER_VOLT_CH ioctl + on STM32F10XX and STM32F20XX. From Dmitriy Linikov. + - STM32 Wakeup: Add logic for enabling wakeup pins. From Oleg Evseev. + - STM32 PWR: Adds stm32_pwr_getsbf and stm32_pwr_getwuf functions + that return the standby flag and the wakeup flag PWR power + control/status register. From Oleg Evseev. + - STM32 HRTIM: Sdd support for capture, chopper, deadtime and dump + registers. From Mateusz Szafoni. + - STM32 RTC: Canceling an alarm marks it as inactive. From Juha + Niskanen + - STM32 Serial: Add interface to get uart_dev_t by USART number, + stm32_serial_get_uart(). From Juha Niskanen. + - STM32 F33xx ADC: Initial ADC support for the STM32F33XX. From + Mateusz Szafoni. + - STM32 F33xx ADC: Add ADC DMA support to STM32F33 configuration. From + Mateusz Szafoni. + - STM32 L4 ADC: Port analog watchdog ioctl commands from the Motorola + MDK. From Juha Niskanen + - STM32 L4 ADC: Add option for routing ADC data to DFSDM, fix DFSDM + DMA. From Juha Niskanen + - STM32 L4 ADC: Add PM hooks from Motorola MDK + - STM32 L4 FLASH: Add function for modifying device option bytes, + From Juha Niskanen. + - STM32 L4 DFSDM: Add peripheral support for digital filters for + sigma-delta ADCs. Initial version. Timer trigger support is not + completed and there is some issue with DMA. From Juha Niskanen. + - STM32 L4 I2C: Port then STM32 F7 I2C driver to STM32 L4. STM32L4 I2C + driver is in work-in-progress state (plentiful of TODOs and + #warnings) and lags many features found in more up-to-date STM32 I2C + drivers. The peripheral on STM32F7 and STM32L4 are identical except + for L4's 'wakeup from stop mode' flag and STM32F7's I2C driver is in + more 'ready to use' state. The I2C clock configuration is kept the + same as before (I2CCLK = PCLK1 80 Mhz) instead of switching to + STM32F7 arch default that is I2CCLK=HSI. Further work would be to + add configuration option for choosing I2C clock source instead of + current hard-coded default. From Jussi Kivilinna. + - STM32 L4 RTC: Add up_rtc_getdatetime_with_subseconds + - STM32 L4 RTC: Change maximum alarm time from 24h to one month. From + Juha Niskanen. + - STM32 L4 RTC: Add support for periodic interrupts with + (experimental) CONFIG_RTC_PERIODIC. From Juha Niskanen. + - STM32 L4 SDMMC: Add support for an SDMMC driver. From Miha Vrhovnik. + - STM32 L4 Serial: Suspend serial for Stop mode. From Juha Niskanen. + - STM32 L4 Serial/PM: STM32L4 serial PM interface improvements: + Check rx/tx buffers for pending data in pmprepare. Remove adhoc PM + interfaces and move serial suspend functionality behind CONFIG_PM. + From Jussi Kivilinna. + + * STMicro STM32 Boards: + + - STM32F103-Minimum: Add board support for APA102 driver. From Alan + Carvalho de Assis. + - STM32F103-Minimum: Add ADC support on stm32f103-minimum board. + From Alan Carvalho de Assis. + - STM32F103-Minimum: Add support for LM75 in the stm32f103-minimum + board. From Alan Carvalho de Assis. + - STM32F103-Minimum: Add an ADPS-9960 example configuration. From + Alan Carvalho de Assis. + - STM32F103-Minimum: Add board support for MAX7219 LED Matrix + controller. From Alan Carvalho de Assis. + - STM32F103-Minimum: Add USB MSC device initialzation to + stm32f103-minimum. From Alan Carvalho de Assis. + - STM32F103-Minimum: Add framebuffer driver initialization for + stm32f103-minimum board. From Alan Carvalho de Assis. + - STM32F103-Minimum: Add Nunchuck board support for + stm32f103-minimum board. From Alan Carvalho de Assis. + - STM32F4 Discovery: Add support for JLX12864G display on STM32F4 + Discovery board. From Alan Carvalho de Assis. + - Viewtool-STM32F107: Add support to auto-mount the procfs file system. + - Photon: Support SPI1 and SPI3. From Anthony Merlino. + - STM32F334-DISCO: Add lower half driver for high power LED + (powerled). From Mateusz Szafoni. + - STM32F334-DISCO: Add flash mode support for powerled driver. From + Mateusz Szafoni. + - STM32F334-DISCO: Add powerled example configuration. From Mateusz + Szafoni. + - STM32F334-DISCO: Add lower-half driver for SMPS (buck-boost onboard + converter). From Mateusz Szafoni + - Nucleo-F334R8: Add logic for zero latency high priority interrupts + example. From Mateusz Szafoni. + - Nucleo-F334R8: Add highpri example configuration. From Mateusz + Szafoni. + - STM32 F4 Discovery: Added support for the LIS3DSH accelerometer on + the STM32F4 Discovery rev. C boards. From Florian Olbrich. + - STM32 F4 Discovery: ROMFS for STM32F4 Discovery board. From Tomasz + Wozniak. + - STM32 F4 Discovery: Add a USB MSC configuration. From Alan Carvalho + de Assis. + - STM32 F4 Discovery: RNDIS support on STM32F4Discovery + DM-STF4BB. + NOTE: MAC address for the host side starts 0xaa. This assignment + scheme should be fixed later. From Masayuki Ishikawa. + - STM32 F4 Discovery: Add STM32F4 Discovery board support for + Nunchuck joystick. From Alan Carvalho de Assis. + - STM3240G-EVAL: Add a configuration for testing the Framebuffer + character driver using the LCD framebuffer front. + - STM3240G-EVAL: Mount procfs if enabled. + - STM3240G-EVAL: Add support for pdcurses and the pdcurses demo + programs in the 'fb' configuration. + - Clicker2-STM32: Adds SD card, automount, and syslog file + support and fixes a few minor issues. From Anthony Merlino. + - Clicker2-STM32: Adds support for USB RNDIS device. From Anthony + Merlino. + - Olimex STM32-H407: Add serial support on the on-board UEXT + connector. Add USART6 for UEXT connector. Add nsh_uext + configuration and README update. From Jan Pobríslo. + - Nucleo-F410RB: Add support for the nucleo-F410RB board. From + Gwenhael Goavec-Merou. + - STM32F429i-DISCO: Add framebuffer driver initialization. Add a + framebuffer (fb) configuration. + - STM32F429i-DISCO: Add logic to auto-mount procfs. Enable procfs in + all configurations that use NSH. + - STM32F429i-DISCO: Enable support for the STMPE811 touchscreen + controller. Enable touchscreen and also the touchscreen testa at + apps/examples/touchscreen in the fb configuration. + - STM32F429i-DISCO: Convert NxWM configuration to use LTDC + framebuffer driver instead of SPI serial. Also reduce number of + layers from 4 to 1 in fb configuration. Only one layer is used. + - STM32L476-MDK: Add support for the on-board LEDs. + - Nucleo-L496ZG: Add DFSDM initialization. From Juha Niskanen + - Nucleo-L496ZG: Add support for SDMMC driver. From Miha Vrhovnik. + - Nucleo-L496ZG: Enable I2C4 bus with i2ctool in NSH configuration. + From Jussi Kivilinna. + - Nucleo-L496ZG: Make HSE on Nucleo-L496ZG default to enable USB. + From Miha Vrhovnik. + - Nucleo-F746ZG: Use the serial console over /dev/ttyACM0 by default. + The Nucleo-F746ZG doesn't come with Arduio RS-232 shield, then it is + better to use the serial over the /dev/ttyACM0 that is created + automatically when the board is plugged in the computer. From Alan + Carvalho de Assis. + - Nucleo-144: Adds support for the Nucleo-144 boards with + STM32F722ZE. From Bob Feretich. + + * ZiLOG Z80 + + - z80/include: compiler.h, limits.h, types.h: Update SDCC/z80 files + to include support for long long, inline, __FILE__, and __func__. + + * C Library/Header Files: + + - include/: Add stdnoreturn.h. Holds definitions for the C11 + noreturn keyword. Applies to C too. + - include/netinet/tcp.h: Add trivial standard tcp.h header file. + - libc: Add support for readv() and writev(). + - libc: Adds tcflow(). + - libc: Add support for sigwait(). + - libnx: Changes to allow the font subsystem to be built without + enabling the entire graphics system (CONFIG_NX). Adds + CONFIG_NXFONTS and CONFIG_NXGLIB. Needed to duplicate some Kconfig + setting for NXFONTs if it can be configured and built independently + of NX. + + * Tools: + + - tools/configure.sh: Add special support so that you can start with a + windows native configuration and install on a different host (and + vice versa). + - tools/configure.c: Duplicate new functionaity added to configure.sh. + - tools/configure.sh: This commit adds a -m option for macOS. For + anyone not aware, Apple renamed OSX to macOS recently; thus the 'm' + instead of 'o'. This does not change the other uses of *_OSX to + macOS. From jeditekunum. + - tools/configure.c: Update functionality to match last change to + tools/configure.sh. + + * NSH: apps/nshlib: + + - apps/nshlib: mount command no long uses the non-standard OS + interface foreach_mountpoint(). Now simply cats /proc/fs/mount + when there are no arguments to the mount command. + - apps/nshlib: df command no long uses the non-standard OS interface + foreach_mountpoint(). Now simply cats /proc/fs/blocks or + /proc/fs/usage. + - apps/nshlib: The free commands no longer used mallinfo() to get + the state of the use heap. Two reasons: That is not useful + information in the kernel build. And (2) there are other memory + resources of interest in other configurations such as the Kernel + heap in PROTECTED and KERNEL builds, and the prog mem uses when + FLASH is used to hold modifiable data. The free command has been + extended to just dump the content of procfs entries and to include + all of these other memory resources of the procfs entries are + available. + + * Examples/Tests: apps/examples: + + - apps/examples/fb: Add a simple test for the framebuffer character + driver.. + - apps/examples/ostest: sem_open() now returns SEM_FAILED in the + event of a failure. + - examples/ostest: Extend cancellation test to make sure that + cancelable threads waiting on a message queue or on a signal can be + canceled. + - Added a simple reader example for the LIS3DSH acceleration sensor + on STM32F4Discovery. From Florian Olbrich. + - apps/examples/apa102: Add a Rainbow example for APA102 LED Strip. + From Alan Carvalho de Assis. + - apps/examples/flowc: Add a simple test of serial hardware flow + control. + - Add powerled driver example. From Mateusz Szafoni. + - apps/examples/ina219: A simple infinite loop that polls the INA219 + sensor and displays the measurements. From Sebastien Lorquet. + - apps/examples/alarm: Add options for reading alarm value and + canceling it. From Juha Niskanen. + - Add -n samples to lm75 app and replace Centigrade with Celsius. + From Alan Carvalho de Assis. + - apps/examples/adps9960: Add ADPS-9960 example. From Alan Carvalho + de Assis. + - apps/examples/obd2: Add OBD2 example application. From Alan + Carvalho de Assis. + - apps/examples/userfs: Add a test case for verifying UserFS. + - apps/examples/smps: add SMPS driver example. From Mateusz Szafoni. + - apps/examples/pdcurses: Bring in pdcurses demos and make them + conform to the NuttX coding style. + - apps/examples/pdcurses: Add a very simple example that just shows + the entire character set (7-bit only). It adapts to the size of + the framebuffer and, hence, can be used with very tiny displays. + In fact it looks really dumb on big displays. + - apps/examples/nunchuck: Add Nunchuck example application. From + Alan Carvalho de Assis. + + * File System Utilies: apps/fsutils: + + - apps/fsutils/mkfatfs: Move mkfatfs from the OS to here. + + * Network Utilities: apps/netutils: + + - apps/netutils/netlib: Add netlib_ipv6adaptor() and + netlib_ipv4adaptor(). + - apps/netutils/netlib: Add helpers for reading the routing table: + netlib_read_ipv4route() and netlib_read_ipv6route(). + - apps/netutils/netlib: Add new utilities netlib_ipv[4|6]router() + that can be used to determine the IP address of a router that would + be used some some destination IP address that is not locally + accessible. + - apps/netutils/ftpc: Adds support for IPv6 and fixes various + transfer issues. From Anthony Merlino. + + * CANUtilities: apps/canutils: + + - apps/canutils/libobd2: Add libobd2 for NuttX. From Alan Carvalho + de Assis. + + * Graphics: apps/graphics: + + - graphics/traveler: Convert to use the framebuffer driver. + - apps/graphics/pdcurs34: This commit brings the public domain + pdcurses library into NuttX. NuttX graphics support based on the + framebuffer character drivers has been integrated. Input is + currently limited to a discrete joystick driver. + + * Wireless Utilities: apps/wireless: + + - apps/wireless/ieee802154/i8sak: Adds socket interface support. You + can now use both socket or char driver to control the MAC layer. + From Anthony Merlino. + - apps/wireless/ieee802154/i8sak: Adds sniffer port option and a few + other get/set parameters. From Anthony Merlino. + - apps/wireless/ieee802154/i8sak: Changes 'notif' to 'primitive' + corresponding to the changes in the Kernel. From Anthony Merlino. + - apps/wireless/ieee802154/i8sak: Channel setting is now saved + locally, so when performing a startpan or assoc, the channel + previously set is still used, even though the MAC layer gets reset. + From Anthony Merlino. + - apps/wireless/ieee802154/i8sak: Adds ability to get/set rxonidle + setting for MAC layer. From Anthony Merlino. + - apps/wireless/ieee802154/i8shark: Adds i8shark, a sniffer "adapter" + that captures all 802.15.4 traffic, packages it into a Wireshark ZEP + packet, and sends it to a host running Wireshark From Anthony + Merlino. + + * System Utilities (apps/system) + + - apps/system/ping and ping6: This commit removes the ping and ping6 + commands from NSH and replaces then with the apps/system/ping and + apps/system/ping6 built-in commands. The NSH ping[6] commands had + to be removed because they violated the portable POSIX OS interface. + The apps/system/png and ping6 command uses the sem-standard + IPPROTO_ICMP and IPPROTO_ICMP6 socket interfaces. + + * Platform-Specific Support (apps/platform) + +Bugfixes. Only the most critical bugfixes are listed here (see the +ChangeLog for the complete list of bugfixes and for additional, more +detailed bugfix information): + + * Core OS: + + - Task Environment Creation: Fix an error in the duplication of the + child tasks environment in the special case where the parent's + environment was created, but then all of the variables were unset. + In that case, there is still an allocation in place but the size of + the allocation is zero. This case was not being handled correctly + when a child task attempts to create its environment and inherit the + zero-size partent environment. Noted by Anthony Merlino. + - timer_create(): Fix watchdog resource leak if cannot allocate a new + timer. From Bruno Herrera. + - OS Internal Functions: Internal OS functions should not return error + information via the user errno variable: This includes functions + like file_seek(), file_read(), file_write(), etc. The complete list + is too long to duplicate here (please refer to the ChangeLog for + details). + - OS Internal Functions: Not only should internal OS functions not + modify the errno variable, they should never introduce cancellation + points: psock_connect(), psock_listen(), psock_getsockopt(), etc. + The list is too long to duplicate here (please refer to the + ChangeLog for details). + - OS Internal Functions: Create OS internal versions of many + applications functions that were used by the OS. The new versions + differ from the application interfaces in that (1) they do not + return error information via the errno variable, and (2) they never + create cancellation points. This includes new internal interfaces + like nxsem_init() that is like sem_init(), etc. There are too many + to list here (see the ChangeLog for details). + - Task Exit: task_exithook.c fails to link if signals are disabled + because was unconditionally trying to send the SIGCHLD signal to the + parent in certain configurations. Noted by Jeongchan Kim. + - memalign(): Fix heap corruption caused by using unaligned chunk + size. Unaligned nodes generated by memalign later cause heap + corruptions when nodes are shrink further (for example, 24 bytes -> + 8 bytes, when alignment is 16 bytes). From Jussi Kivilinna. + - SMP: In sched/sched/sched_cpuselect.c, in order to find the cpu + with the lowest priority thread, we have to remember the already + found lowest priority. Noted by Anonymous in Issue #75. + - spinlocks: Disable local interrupts in spin_setbit() and + spin_clrbit() in order to avoid a deadlock condition. From Masayuki + Ishikawa. + - atexit()/on_exit(): Clear atexit()/on_exit() function pointer + before calling it. On most archs, up_assert() calls exit() so + without this change, if atexit() function triggers an assertion we + are in endless loop. From Juha Niskanen. + + * File System/Block and MTD Drivers: + + - tmpfs: Fixed directory unlocking in tmpfs_opendir. From Dmitriy + Linikov. + - fcntl(): fcntl() did not return success fail for F_SETFL. Reported + by Jussi Kivilinna. + - tcdrain(): tcdrain() was recently added to the NuttX C library. + But there is a problem. The specification of tcdrain() requires + that it be a cancellation point. In order to do this, tcdrain was + moved from the C library into the OS and the addition cancellation + point hooks were added. In non-FLAT builds, access via system calls + is also now supported. + - FS FAT: Fix hard-fault when listing contents of FAT root. From + Jussi Kivilinna. + - procfs: Correct a problem that was causing an apparent directory to + be reported as a file instead of a directory by opendir. This + happened after adding these three new procfs entries: fs/block, + fs/mount, and fs/usage. Of course, there is no directory fs in this + case, only three files that have fs/ in their relative pathnames. + The logic was detecting that fs was the name of the enty to report, + but it was then declaring that fs was a file (because fs/block is of + type file). This was fixed by adding a check for matching lenghts. + i.e., if strlen(fs) != strlen(fs/block), then report fs as a + directory instead of a file. + - procfs: Fix uptime being clse to maximum 32-bit value in certain + config. From Juha Niskanen. + + * Binary Loader: + + - binfmt/: Don't schedule starthook if there are no constructors. + + * Graphics/Display Drivers: + + - LCD: ILI9341 initialize method not permitted to set errno. + + * Networking/Network Drivers: + + - Networking: net/netdev/netdev_ifconfig.c: Was not returning all of + the address info. + - Networking: In some cases, packets are still not sent behind the + router. I found that NuttX sends the ARP requests not to the router + but to the target. Mistake in file net/route/netdev_router.c. From + Aleksandr Kazantsev. + - SIOCGIFCONF and SIOCGLIFCONF IOCTL commands should only report on + network adatpors in the UP state. + - recvfrom(): Fix double leave_cancellation_point on error path. + From Jussi Kivilinna. + - send(): Verify that sock descriptor is valid. Fixes assertion when + using send on closed socket. From Jussi Kivilinna. + - sendto(): Remove assert check for null psock and buf input + pointers. Removes check as 'psock == NULL' altogether because that + checked for later in psock_send and psock_sendto. Change null check + for 'buf' so that it is handled same as in recvfrom.c (return + -EINVAL instead of assert). From Jussi Kivilinna. + - sockgetname() files need to include udp/udp.h and tcp/tcp.h or + otherwise NET_UDP_HAVE_STACK and NET_TCP_HAVE_STACK are undefined + and the logic is never compiled. Noted by Anthony Merlino. + - dup()/dup2(): There was a reference counting problem in the TPC + logic of net_clone(). net_clone() which is the common logic + underlying dup() and dup2() for sockets. When net_clone() calls + net_start_monitor() and net_start_monitor() returns a failure + (because the underlying TCP connection) then net_clone() must back + out the reference count on the structure. Problem noted by Pascal + Speck and this implementation of the solution is based on his + suggestion. + - close(): There was a possible recursion that could eventually + overflow the stack. The error occurred when closing the socket with + inet_close() while a socket callback was still queued. When the + socket callback was executed by devif_conn_event(), this resulted in + a call to psock_send_eventhandler() with TCP_CLOSE flag set which + then called tcp_lost_connection(). tcp_shutdown_monitor() then + called tcp_callback() again, which again called + psock_send_eventhandler(), and so on.... Noted by Pascal Speck. + Solution is also similar to a solution proposed by Pascal Speck. + - inet: Add check for protocol before handing out TCP and UDP sockets. + - IP Forwarding: Fixes typo that caused build error when IP + forwarding was enabled with CONFIG_NET_ICMPv6_NEIGHBOR enabled as + well. From Anthony Merlino. + - IP Forwarding: Do not add link layer header size to d_len inside + devif_forward(). From Anthony Merlino. + - TCP Networking: When CONFIG_NET_TCP_WRITE_BUFF=y there is a + situation where a NULL pointer may be dereferenced. In this + configuration, the TCP connection's 'semi-permanent' callback, + s_sndcb was nullified in tcp_close_disconnect. However, other logic + in tcp_lost_connection() attempt to use that callback reference + after it was nullifed. Fixed in tcp_lost_connectino() by adding a + NULL pointer change before the access. This was reported by Dmitriy + Linikov in Bitbucket Issue 72. + - UDP Broadcat: Fix some issues with regard to UDP broadcast + handling. This is Bitbucket Issue #77. + - ICMP: Fix an error in the poll logic. It was assumed that the + input parmeter pvconn was valid. It was not. Instead, the poll + logic must work like the sendto() and recvfrom() logic: It must + keep a copy of the conn structure in the private data. + - ICMPv6: Fixes several errors preventing icmpv6_radvertise.c from + being compiled. Fixes conversions to network byte order (namely + vlifetime, plifetime, mtu). IPv6 source address is set to + link-local IP address instead of the address in the netdev + structure. This is in compliance to RFC 4861. RA didn't work on + Linux before this change. Finally, router prefix and prefix length + are derived from the IPv6 address and netmask in the netdev + structure. This seems to make more sense than using a predefined, + separate prefix from the config. From Sakari Kapanen. + - ICMPV6: icmpv6_input() needs to set d_len to 0 after consuming echo + reply, otherwise, garbage will get sent out. From Anthony Merlino. + - ICMPV6: Fix an error in the poll logic. It was assumed that the + input parmeter pvconn was valid. It was not. Instead, the poll + logic must work like the sendto() and recvfrom() logic: It must + keep a copy of the conn structure in the private data. + - IGMPv2 Send: Fix incoming IGMP checksum calculation. From Louis + Mayencourt. + - ARP: Fix IGMP Ethernet address computation. From Louis Mayencourt. + + * Wireless/Wireless Drivers: + + - CC1101: CC1101 driver not permitted to set errno. + - 6LoWPAN: Correct an error in uncompressing multicast address. + - 6LoWPAN: Correct a bug in handling uncompressed frames (IPv6 + dispatch). Adds a separate local variable, protosize, to keep track + of the size of thep protocol header. + - 6LoWPAN: Fix an endian-ness problem in 6LoWPAN address + decompression. From Anthony Merlino. + - 6LoWPAN: The logic that extracts interface identifier from the IP + address needs to be generalized to handle cases where the address is + not a link local address. From Anthony Merlino. + + * Common Drivers: + + - Serial: 16550 UART driver IOCTL method must not set errno; it must + return a negated errno value. + - LIS3DSH: Added the argument parameter (FAR void *arg) to the + interrupt handler provided by the LIS3DSH driver to fit the + definition for ISRs in xcpt_t. Changed the check for working queue + availability in lis3dsh interrupt handler to use work_available() + and not crash in case of an overrun. From Florian Olbrich. + - LIS2DH: Fixes for self-test. From Jussi Kivilinna. + - LIS2DH: Fix use of obsolete dbg macro. From Jussi Kivilinna. + - LIS331DL: LIS331DL driver not permitted to set errno. + - HTS221: Power-on sensor for loading calibration data. From Jussi + Kivilinna. + - MCP2515: Fix the MCP2515 Bit Rate Prescale calculation. Fix BRP + for SET_BITTIMING ioctl as well. From Alan Carvalho de Assis. + - STMPE811: Fix GPIO operation of STMPE811 driver. + 1. STMPE811_GPIO_DIR was defined for register name and later was + redefined to be the pin direction mask for `stmpe811_gpioconfig`. + I decided to change register name to be STMPE811_GPIO_DIR_REG, and + keep pin direction mask STMPE811_GPIO_DIR, so that any external + code that already use this driver will be unchanged. + 2. The STMPE811 register GPIO_DIR uses bit value 1 for output and 0 + for input, but `stmpe811_gpioconfig` set the opposite. + 3. The call to `stmpe811_gpiowrite` from inside of + `stmpe811_gpioconfig` leaded to deadlock. + From Dmitriy Linikov. + - BQ2429X: Add BATIO_OPRTN_SYSON for enabling BATFET after SYSOFF. + From Jussi Kivilinna. + + * Simulation: + + - Simulation: Serial and console drivers are not permitted to set + the errno. + + * ARMv7-M: + + - ARM Stack Check: Fix assert panic when both TLS and interrupt stack + are enable. From Jussi Kivilinna. + + * Expressif ESP32: + + * Infineon XMC4xxx Drivers: + + - XMC4 USIC: Kconfig was not selecting XMC4_USIC for USIC1. From Alan + Carvalho de Assis. + - XMC4 UART: Fix XMC4xxx USIC UART sginal to be high level when in idle. + From Alan Carvalho de Assis. + - XMC4 UART:xmc4_uart_configure() expects the channel# not uartbase as + an input parameter. From Alan Carvalho de Assis. + - XMC4 UART: Enable RX/TX status. From Alan Carvalho de Assis. + - XMC4 UART: The Alternative Receive Interrupt was not being + configured. + + * Infineon XMC4xxx Boards: + + - XMC4500-Relax: Setup max. freq. 120MHz and setup pull-up to UART + RXD pin. From Alan Carvalho de Assis. + + * Microchip/Atmel SAMv7 Drivers: + + - SAMv7: DAC and ADC drivers are not permitted to set the errno. + - SAMv7: Correct an error in RX DMA setup. From Manish Kumar Sharma. + - SAMv7 USB: It is necessary to disable pre-emption and interrupts + around a loop that copies TX data into the hardware in order to + avoid a TX data underrun condition. From Anthony Merlino. + + * NXP/Freescale LPC31xx Drivers: + + - LPC31xx: Serial and console drivers are not permitted to set + the errno. + + * NXP/Freescale LPC43xx: + + - lpc43xx: lpc43_adc.c was being selected by the build system wehn + DAC was selected. + + * NXP/Freescale LPC43xx Drivers: + + - LPC43xx Ethernet: Fix some backward logic setting full-duplex and + 100mbps when autoconfiguration is disabled. Noted by Anonymous in + Issue #76. + - lpc43xx: UART_RX pins should be configured with input buffers + enabled. Otherwise it cannot be read. From Alexander Vasiljev. + + * STMicro STM32: + + - STM32 F2: Fixed build for STM32F20XX platforms when + CONFIG_STM32_DMACAPABLE is enabled. From Dmitriy Linikov. + - STM32 F4: Remove ltdc.h and dma2d.h. Those header files in that + location permitted inclusion into application space logic and, + hence, facilitated and encouraged calling into the OS and violating + the portable POSIX OS interface. The definitions in those header + files were move the appropriate location in the counterpart, + architecture specific files at arch/arm/src/stm32/dma2d.h and ltdc.h. + - STM32 L4: Build stm32l4_idle.c only if CONFIG_ARCH_IDLE_CUSTOM is + not enabled. From Jussi Kivilinna. + - STM32 F7: Remove ltdc.h and dma2d.h. Those header files in that + location permitted inclusion into application space logic and, + hence, facilitated and encouraged calling into the OS and violating + the portable POSIX OS interface. The definitions in those header + files were move the appropriate location in the counterpart, + architecture specific files at arch/arm/src/stm32f7/dma2d.h and + ltdc.h. + + * STMicro STM32 Drivers: + + - STM32: DAC and ADC drivers are not permitted to set the errno. + - STM32 ADC: Clear pending interrupts. From Mateusz Szafoni. + - STM32 CAN: Lower part of STM32 CAN driver + arch/arm/src/stm32/stm32_can.c uses all three hw tx mailboxes and + clears TXFP bit in the CAN_MCR register (it means transmission order + is defined by identifier and mailbox number). + This creates situation when order frames are put in upper part of + CAN driver (via can_write) and order frames are sent on bus can be + different (and I experience this in wild). Since CAN driver API + pretends to be "file like" I expect data to be read from fd the same + order it is written. So I consider described behaviour to be a bug. + Fixed by settin the TXFP bit in the CAN_MCR register (FIFO + transmit order). From comments by Alexey T, in Bitbucket Issue 73. + - STM32 HRTIM: Fix pclk calculation. From Mateusz Szafoni. + - STM32 HRTIM: Fix burst mode prescaler update. From Mateusz Szafoni. + - STM32 (alt) I2C: Ensure proper error handling. Injecting data + errors would cause the driver to continually reenter the isr with + BERR an RxNE. This fix allows the error to be cleared and + propagated to the waiting task. From David Sidrane. + - STM32: LTDC and DMA2D drivers are not permitted to set the errno. + - STM32 RTC: Workaround for potential subseconds race condition. In + all recent STM32 chips reading either RTC_SSR or RTC_TR is supposed + to lock the values in the higher-order calendar shadow registers + until RTC_DR is read. However many old chips have in their errata + this silicon bug (at least F401xB/C, F42xx, F43xx, L15xxE, L15xVD + and likely others): "When reading the calendar registers with + BYPSHAD=0, the RTC_TR and RTC_DR registers may not be locked after + reading the RTC_SSR register. This happens if the read operation is + initiated one APB clock period before the shadow registers are + updated. This can result in a non-consistency of the three + registers. Similarly, RTC_DR register can be updated after reading + the RTC_TR register instead of being locked." + - STM32 Serial: Do not stop processing input in SW flow-control + mode. From Juha Niskanen. + - STM32F33xxx ADC: Add some publicly visable interfaces and some + code to support injected channels. From Mateusz Szafoni. + - STM32F33xxx DMA: Add public interface to handle with DMA + interrupts. From Mateusz Szafoni. + - STM32F33xxx RCC: Fix CAN clock enable. From Mateusz Szafoni. + - stm32 F4 I2C: Ensure proper interrupt handling. Injecting data + errors that causes a STOP to be perceived by the driver, will + continually re-enter the isr with SB not set and BTF and RxNE set. + This changes allows the interrupts to be cleared and propagates a + I2C_SR1_TIMEOUT to the waiting task. From David Sidrane. + - STM32 L4 Serial: Do not stop processing input in SW flow-control + mode. From Juha Niskanen. + - STM32 F7: LTDC and DMA2D drivers are not permitted to set the errno. + - STM32 L4: DAC and ADC drivers are not permitted to set the errno. + - STM32 L4 DAC: Do not configure output pin if it is not used. From + Juha Niskanen. + - STM32 L4 RTC, PM: Small fixes to subseconds handling, ADC + power-management hooks + - STM32 F4 RTC: Fix reading alarm value that is more than 24h in + future. From Juha Niskanen + - STM32 L4 RTC: Fix reading alarm value that is more than 24h in + future. From Juha Niskanen + - STM32 L4 TIM: Fix compilation of timers with complementary outputs + when not PWM_MULTICHAN. From Juha Niskanen. + - STM32 L4 RCC: Restore backup-registers after backup-domain reset. + From Jussi Kivilinna. + - STM32 L4 RTC: Correct RTC_SSR and RTC_TR read ordering. In all + recent STM32 chips reading either RTC_SSR or RTC_TR is supposed to + lock the values in the higher-order calendar shadow registers until + RTC_DR is read. Change the register read ordering to match this and + don't keep a workaround for a hypothetical race condition (not in + any L4 errata, lets for once assume ST's silicon works as it is + documented...) + - STM32 L4 RTC: Init mode was never exited because nested locking in + rtc_synchwait() disabled backup domain access. From Juha Niskanen. + - STM32 L4 RTC: Use backup register magic value instead of INITS + bit. The INITS (bit 4) of RTC_ISR register cannot be used to + reliably detect backup domain reset. This is because we can operate + our device without ever initializing the year field in the RTC + calendar if our application does not care about correct date being + set. Hardware also clears the bit when RTC date is set back to year + 2000. From Juha Niskanen. + - STM32 L4 RTC: Put back the SSR race condition workaround. ST has + confirmed that the issue has not been fixed, and that it applies to + STM32 L4 too (was not in errata sheets due to documentation bug) See + discussion: https://community.st.com/thread/43710-issue-with-rtc-maximum-time-resolution . + From Juha Niskanen. + - STM32 F7 BBSRAM: Avoid assert in stm32_bbsram_savepanic. If panic + happens before stm32_bbsram is initialized, stm32_bbsram_savepanic + caused additional assert panic. Function has null pointer check, so + drop DEBUGASSERT. From Jussi Kivilinna. + - STM32 F7 I2C: fix I2C_M_NORESTART handling. From Jussi Kivilinna. + - STM32 F7 I2C: Restore bus frequency after I2C reset. Copy + frequency restoration fix from STM32L4 I2C driver to STM32F7 I2C + driver. From Jussi Kivilinna. + - STM32 F7 RTC: Fix reading alarm value that is more than 24h in + future. From Juha Niskanen + + * STMicro STM32 Boards: + + - STM32F334-DISCO: Add missing ram_vectors configuration in linker + script. From Mateusz Szafoni. + - Nucleo-F334R8: Add missing ram_vectors configuration in linker + script. From Mateusz Szafoni. + - Nucleo-F334R8: Add Missing ADC trigger configuration tot he highpri + configuration. From Mateusz Szafoni. + - STM3240G-EVAL: The timer frequencies (BOARD_TIMx_FREQUENCY) are + incorrectly defined in board.h. Since the APB prescalers are set to + divide by 4 and 2 respectively, the frequencies should be "2xAPBx" + as said in the comment.  The correct frequencies are already defined + but as STM32_APBx_TIMx_CLKIN. From Mattias Edlund. + - STM32F429i-DISCO: The ltdc configuration has been deleted because + it violated the portable POSIX OS interface. It used + apps/examples/ltdc and include ltdc.h and dma2d.h which were also + removed for the same reason. + + * ZiLOG Z80 + + - configs/z80sim and xtrs: Serial driver lower halfs ioctl methods + should return a negated errno value, not set the errno variable. + - z80 Make.defs: Fixes dependency generation with newest SDCC + compiler. + - configs/z80sim: Fix a naming problem. Also, don't try to build the + serial driver if CONFIG_NFILE_DESCRIPTOR=0. + - Z80: Makefile fix for use with current SDCC. + + * Build System + + - configs/: All defconfig filess that include + CONFIG_NET_ICMPv6_SOCKET=y need to select CONFIG_SYSTEM_PING6=y and + deselect CONFIG_DISABLE_POLL. + - configs/: All NX configuration... Because of recent changes to + libnx/nxfonts, Supported bit per pixel must be separated specified + for NXFONTs too and need to match the select BPP for NX. + - Build system: Fix CONFIG_BUILD_KERNEL logic directories that have + ubin and kbin subdirectories. Conditional logic was fine for + CONFIG_BUILD_FLAT and CONFIG_BUILD_PROTECTED but generated useless + dependencies if CONFIG_BUILD_KERNEL. + + * C Library/Header Files: + + - libc/stdio: Build the lib_noflush() and lib_snoflush() stubs even + if CONFIG_FILE_DESCRIPTORS=0. They may still be needed. + - libc and libnx: When the libraries are built into two libraries, a + user space library and a OS space library (as in the PROTECTED and + KERNEL build). Then the user space library must not use the OS + internal interfaces; similarly, the OS must avoid using the + userspace interfaces so that it does not muck the errno value or + create spurious cancellation points. + - libc/match: Use of exp() vs expf() in logf() caused function to be + slow. From Alan Carvalho de Assis. + - libnx: Fixes a memory leak that is caused because the client message + queue is not unlinked after the client disconnects from the NX + server. From Masayuki Ishikawa. + - sscanf(): Fix sscanf() character conversion (%c): do not add '\0' at + the end as for strings, cause, for example, parsing one character + will fill two bytes: character itself and zero one '\0' after it, so + will overflow one byte variable argument and corrupt memory for + variables allocated after it. From Oleg Evseev. + + * Tools + + - tools/: configure.sh and configure.c should redirect stdout to + /dev/null but should not suppress stderr output. + + * NSH: apps/nshlib: + + - apps/nshlib/: Avoid truncating the strcmp result in the parser + into a unsigned char variable. nshlib/nsh_netcmds.c: Check for + valid hostip before using it. From Bruno Herrera. + - apps/nshlib/: Fix resouce leak in 'dd' commenad when 'if=' or + 'of=' params are repeated in the command line. For example: + dd if=/dev/null if=/dev/zero of=/dev/null or + dd if=/dev/zero of=/dev/zero of=/dev/null. From Bruno Herrera. + - apps/nshlib: This commit eliminates the ping and ping6 commands + from NSH and replaces them with 'built-in' commands at + apps/system/ping and ping6. The original NSH version of ping[6] + commands violated the portable POSIX interface and, hence, had to + be removed. The new system/ping and ping6 built-in commands uses + the new IPPROTO_ICMP AF_INET and IPPROTO_ICMP6 AF_INET6 datagram + sockets to implement ping. + - apps/nshlib: Fix parsing of empty strings when CONFIG_NSH_CMDPARMS + is not defined. Problem noted by Juha Niskanen. + + * Examples/Tests: apps/examples: + + - All configurations that use NXIMAGE or NXHELLO must select + NX_MULTIUSER. All configuratinos that use examples/nxterm must + enable CONFIG_LIB_BOARDCTL. + - All configurations that use NXLINES must select NX_MULTIUSER. All + configurations that use the NX server need to have larger POSIX + messages. + - apps/examples/adc: Fix g_adcstate.count initialization. From + Masayuki Ishikawa. + - apps/examples/elf: Remove low-level interfaces and replace with + call to exec(). + - apps/examples/nxflat: Remove low-level interfaces and replace with + call to exec(). + - examples/ostest: Works around a bug in printf() when cancellation + points are enabled. printf() is a cancellation point because it + calls write(). This is correct according to OpenGroup.org. + However, printf holds the stdio library semaphore when it is + canceled and this leaves the semaphore in a bad state. No fix for + the printf bug yet. + - apps/examples/nx: The NX example no longer supports single user + mode. + - apps/examples/nxtext: The nxtext example no longer supports single + user mode. + - apps/examples/nxhello now supports only multiuser mode. + - apps/examples/nximage now supports only multiuser mode. + - examples/nxlines: Now supports only multiuser mode. + + * Network Utilies: apps/netutils: + + - apps/netutils/ftpc: Fix some crazy comparisons to determine is a + file is an absolute path. Noted by Anthony Merlino. + + * System Unitilities (apps/system) + + - apps/system/i2ctool: Fixed i2ctool write operation in `no restart` + mode (flag `-n`). It seems that I2C driver has changed a bit since + i2ctool was written, so now i2ctool sends repeated start even if + `no restart` flag (-n) was passed to it. From Dmitriy Linikov. \ No newline at end of file diff --git a/TODO b/TODO index 25fffb9b872f9243e843ad22c1c7c771dcf58780..3d92fd7ee2cc84745d03d4b523cd06576d4728fd 100644 --- a/TODO +++ b/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated October 25, 2017) +NuttX TODO List (Last updated January 3, 2018) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -14,18 +14,18 @@ nuttx/: (1) Memory Management (mm/) (0) Power Management (drivers/pm) (3) Signals (sched/signal, arch/) - (3) pthreads (sched/pthread) + (2) pthreads (sched/pthread) (0) Message Queues (sched/mqueue) (8) Kernel/Protected Build (3) C++ Support (6) Binary loaders (binfmt/) - (16) Network (net/, drivers/net) + (17) Network (net/, drivers/net) (4) USB (drivers/usbdev, drivers/usbhost) (0) Other drivers (drivers/) (12) Libraries (libc/, libm/) (10) File system/Generic drivers (fs/, drivers/) - (9) Graphics Subsystem (graphics/) - (3) Build system / Toolchains + (10) Graphics Subsystem (graphics/) + (1) Build system / Toolchains (3) Linux/Cywgin simulation (arch/sim) (4) ARM (arch/arm/) @@ -300,12 +300,13 @@ o Task/Scheduler (sched/) ./risc-v/src/common/up_internal.h:EXTERN uint32_t g_idle_topstack; ./x86/src/common/up_internal.h:extern uint32_t g_idle_topstack; - That omits there architectures: sh1, sim, xtensa, z16, z80, + That omits these architectures: sh1, sim, xtensa, z16, z80, ez80, and z8. All would have to support this common globlal variable. Also, the stack itself may be 8-, 16-, or 32-bits wide, - depending upon the architecture. + depending upon the architecture and do have differing + alignment requirements. 2. Another problem is colorizing that stack to use with stack usage monitoring logic. There is logic in some @@ -551,49 +552,10 @@ o pthreads (sched/pthreads) solution. So I discarded a few hours of programming. Not a big loss from the experience I gained." - Title: ISSUES WITH CANCELLATION POINTS - Description: According to POSIX cancellation points must occur when a - thread is executing the following functions. There are some - exceptions as noted: - - accept() mq_timedsend() NA putpmsg() sigtimedwait() - 04 aio_suspend() NA msgrcv() pwrite() NA sigwait() - NA clock_nanosleep() NA msgsnd() read() sigwaitinfo() - close() NA msync() NA readv() 01 sleep() - connect() nanosleep() recv() 02 system() - -- creat() open() recvfrom() tcdrain() - fcntl() pause() NA recvmsg() 01 usleep() - NA fdatasync() poll() select() -- wait() - fsync() pread() sem_timedwait() waitid() - NA getmsg() NA pselect() sem_wait() waitpid() - NA getpmsg() pthread_cond_timedwait() send() write() - NA lockf() pthread_cond_wait() NA sendmsg() NA writev() - mq_receive() pthread_join() sendto() - mq_send() pthread_testcancel() 03 sigpause() - mq_timedreceive() NA putmsg() sigsuspend() - - NA Not supported - -- Doesn't need instrumentation. Handled by lower level calls. - nn See note nn - - NOTE 01: sleep() and usleep() are user-space functions in the C library and cannot - serve as cancellation points. They are, however, simple wrappers around nanosleep - which is a true cancellation point. - NOTE 02: system() is actually implemented in apps/ as part of NSH. It cannot be - a cancellation point. - NOTE 03: sigpause() is a user-space function in the C library and cannot serve as - cancellation points. It is, however, a simple wrapper around sigsuspend() - which is a true cancellation point. - NOTE 04: aio_suspend() is a user-space function in the C library and cannot serve as - cancellation points. It does call around sigtimedwait() which is a true cancellation - point. - Status: Not really open. This is just the way it is. - Priority: Nothing additional is planned. - Title: INAPPROPRIATE USE OF sched_lock() BY pthreads Description: In implementation of standard pthread functions, the non- standard, NuttX function sched_lock() is used. This is very - strong sense it disables pre-emption for all threads in all + strong since it disables pre-emption for all threads in all task groups. I believe it is only really necessary in most cases to lock threads in the task group with a new non- standard interface, say pthread_lock(). @@ -608,7 +570,7 @@ o pthreads (sched/pthreads) This is an easy change: pthread_lock() and pthread_unlock() would simply operate on a semaphore retained in the task group structure. I am, however, hesitant to make this change: - I the flat build model, there is nothing that prevents people + In the FLAT build model, there is nothing that prevents people from accessing the inter-thread controls from threads in differnt task groups. Making this change, while correct, might introduce subtle bugs in code by people who are not @@ -651,11 +613,9 @@ o Kernel/Protected Build These functions still call directly into operating system functions: - - cdcacm_classobject - Called from apps/system/composite. - usbmsc_configure - Called from apps/system/usbmsc and apps/system/composite - - usbmsc_bindlun - Called from apps/system/usbmsc and - apps/system/composite + - usbmsc_bindlun - Called from apps/system/usbmsc - usbmsc_exportluns - Called from apps/system/usbmsc. Status: Open @@ -1341,12 +1301,24 @@ o Network (net/, drivers/net) connect() most likely has this same issue. A work-around might be to raise the priority of the thread - that calls accept(). + that calls accept(). accept() might also need to check the + tcpstateflags in the connection structure before returning + in order to assure that the socket truly is connected. Status: Open Priority: Medium. I have never heard of this problem being reported before, so I suspect it might not be so prevalent as one might expect. + Title: LOCAL DATAGRAM RECVFROM RETURNS WRONG SENDER ADDRESS + Description: The recvfrom logic for local datagram sockets returns the + incorrect sender "from" address. Instead, it returns the + receiver's "to" address. This means that returning a reply + to the "from" address receiver sending a packet to itself. + Status: Open + Priority: Medium High. This makes using local datagram sockets in + anything but a well-known point-to-point configuration + impossible. + o USB (drivers/usbdev, drivers/usbhost) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1787,14 +1759,10 @@ o File system / Generic drivers (fs/, drivers/) intended for deeply embedded environments where there are not multiple users with varying levels of trust. - truncate - The standard way of setting a fixed file size. - Often used with random access, data base files. There is no - simple way of doing that now (other than just writing data - to the file). - link, unlink, softlink, readlink - For symbolic links. Only the ROMFS file system currently supports hard and soft links, - so this is not too important. + so this is not too important. The top-level, psuedo-file + system supports soft links. File locking @@ -1807,6 +1775,8 @@ o File system / Generic drivers (fs/, drivers/) True inodes - Standard Unix inodes. Currently only supported by ROMFs. + File times, for example as set by utimes(). + The primary obstacle to all these is that each would require changes to all existing file systems. That number is pretty large. The number of file system implementations that would @@ -2042,6 +2012,27 @@ o Graphics Subsystem (graphics/) Status: Open Priority: Low for many, but I imagine higher in countries that use wide fonts + Title: LOW-RES FRAMEBUFFER RENDERERING + Description: There are obvious issues in the low-res, < 8 BPP, implemenation of + the framebuffer rendereing logic of graphics/nxglib/fb. I see two + obvious problems in reviewing nxglib_copyrectangle(): + + 1. The masking logic might work 1 BPP, but is insufficient for other + resolutions like 2-BPP and 4-BPP. + 2. The use of lnlen will not handle multiple bits per pixel. It + would need to be converted to a byte count. + + The function PDC_copy_glyph() in the file apps/graphics/pdcurs34/nuttx/pdcdisp.c + derives from nxglib_copyrectangle() and all of those issues have been + resolved in that file. + + Other frambuffer rendering functions probably have similary issues. + Status: Open + Priority: Low. It is not surprising that there would be bugs in this logic: + I have never encountered a hardware framebuffer with sub-byte pixel + depth. If such a beast ever shows up, then this priority would be + higher. + o Build system ^^^^^^^^^^^^ @@ -2058,109 +2049,6 @@ o Build system Status: Open Priority: Low. - Title: CONTROL-C CAN BREAK DEPENDENCIES - Description: If you control C out of a make, then there are things that can go - wrong. For one, you can break the dependencies in this scenario: - - - The build in a given directory begins with all of the compilations. - On terminal, this the long phase with CC: on each line. As each - .o file is created, it is timestamped with the current time. - - - The dependencies on each .o are such that the C file will be re- - compile if the .o file is OLDER that the corresponding .a archive - file. - - - The compilation phase is followed by a single, relatively short - AR: phase that adds each of the file to the .a archive file. As - each file is added to archive, the timestamp of the of archive is - updated to the current time. After the first .o file has been - added, then archive file will have a newer timestamp than any of - the newly compiled .o file. - - - If the user aborts with control-C during this AR: phase, then we - are left with: (1) not all of the files have bee added to the - archive, and (2) the archive file has a newer timestamp than any - of the .o file. - - So when the make is restarted after a control, the dependencies will - see that the .a archive file has the newer time stamp and those .o - file will never be added to the archive until the directory is cleaned - or some other dependency changes. - - NOTE: This may not really be an issue because the the timestamp on - libapps.a is not really used but rather the timestamp on an empty - file: - - .built: $(OBJS) - $(call ARCHIVE, $(BIN), $(OBJS)) - $(Q) touch $@ - - UPDATE: But there is another way that Control-C can break dependencies: - If you control-c out of the make during the apps/ part of the build, - the archive at apps/libapps.a is deleted (but all of the .built files - remain in place). You can see this in the make outout, for example: - - CC: ieee802154_getsaddr.c - make[2]: *** [Makefile:104: ieee802154_getsaddr.o] Interrupt - make: *** Deleting file '../apps/libapps.a' - - When you rebuild the system, the first file archived will recreate - libapps.a and set the timestamp to the current time. Then, none of - the other object files will be added to the archive because they are - all older.. or, more correctly, none of the other object files will - be addred because .built files remained and say that there is no - need to update the libapps.a file. - - The typical symptom of such an issue is a link time error like: - - LD: nuttx libsched.a(os_bringup.o): In function `os_bringup': - os_bringup.c:(.text+0x34): undefined reference to `nsh_main' - - This is becuase the libapps.a file was deleted and an new empty - libapps.a file was created (which the object containing nsh_main()). - The object containing nsh_main() will not be added because the - .built file exists and says that there is not need to add the - nsh_main() object to libapps.a. - - The work-around for now is: - - $ make apps_distclean - - One solution to this might be to making the special target - .PRECIOUS depend on apps/libapps.a. Then if make receives a - signal, it will not delete apps/libapps.a. This would have to - be done in all Makefiles. - - Status Open - Priority: Medium-High. It is a rare event that control-C happens at just the - point in time. However, when it does occur the resulting code may - have binary incompatiblies in the code taken from the out-of-sync - archives and cost a lot of debug time before you realize the issue. - - The first stated problem is not really an issue: There is already - the spurious .built file that should handle the described case: - If you control-C out of the build then the timestamp on the .built - file will not be updated and the archiving should be okay on the - next build. - - A work-around for the second stated problem is to do 'make clean' - if you ever decide to control-C out of a make and see that the - libapps.a file was deleted. - - UPDATE: This is a potential fix for the second problem in place - in in all Makefiles under apps/. This fix adds - - .PRECIOUS: $(BIN) - - to all Makefiles. It has not yet been confirmed that this fix - eliminates the dependency issue or not. - - Title: DEPENDENCIES OBJECT SUB-DIRECTORIES - Descripton: Dependencies do not work in directories that keep binaries in - a sub-directory like bin, ubin, kbin. - Status: Open - Priority: Medium-Low. Definitely a build issue once in awhile. - o Other drivers (drivers/) ^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/arch/Kconfig b/arch/Kconfig index a621f6f163519263e39d5eb097520abcb5ef47b4..1efa5d52c2a4bd2ebeb961dcd9466204f56665e4 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -194,6 +194,10 @@ config ARCH_HAVE_POWEROFF bool default n +config ARCH_HAVE_PROGMEM + bool + default n + config ARCH_HAVE_RESET bool default n diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f87e9148d69799c8539f71d3e8a59288e9e24813..63ca64635c4beb812ee091ff5b1490fdc14886c2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -171,6 +171,17 @@ config ARCH_CHIP_LPC43XX ---help--- NPX LPC43XX architectures (ARM Cortex-M4). +config ARCH_CHIP_LPC54XX + bool "NXP LPC54XX" + select ARCH_CORTEXM4 + select ARCH_HAVE_CMNVECTOR + select ARMV7M_CMNVECTOR + select ARCH_HAVE_MPU + select ARM_HAVE_MPU_UNIFIED + select ARCH_HAVE_FPU + ---help--- + NPX LPC54XX architectures (ARM Cortex-M4). + config ARCH_CHIP_MOXART bool "MoxART" select ARCH_ARM7TDMI @@ -244,9 +255,10 @@ config ARCH_CHIP_STM32 select ARCH_HAVE_MPU select ARCH_HAVE_I2CRESET select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_PROGMEM + select ARCH_HAVE_SPI_BITORDER select ARCH_HAVE_TICKLESS select ARCH_HAVE_TIMEKEEPING - select ARCH_HAVE_SPI_BITORDER select ARM_HAVE_MPU_UNIFIED select ARMV7M_HAVE_STACKCHECK ---help--- @@ -275,13 +287,14 @@ config ARCH_CHIP_STM32F7 config ARCH_CHIP_STM32L4 bool "STMicro STM32 L4" - select ARCH_HAVE_CMNVECTOR select ARCH_CORTEXM4 - select ARCH_HAVE_MPU + select ARCH_HAVE_CMNVECTOR select ARCH_HAVE_I2CRESET select ARCH_HAVE_HEAPCHECK - select ARCH_HAVE_TICKLESS + select ARCH_HAVE_MPU + select ARCH_HAVE_PROGMEM select ARCH_HAVE_SPI_BITORDER + select ARCH_HAVE_TICKLESS select ARM_HAVE_MPU_UNIFIED select ARMV7M_CMNVECTOR select ARMV7M_HAVE_STACKCHECK @@ -520,6 +533,7 @@ config ARCH_CHIP default "lpc2378" if ARCH_CHIP_LPC2378 default "lpc31xx" if ARCH_CHIP_LPC31XX default "lpc43xx" if ARCH_CHIP_LPC43XX + default "lpc54xx" if ARCH_CHIP_LPC54XX default "moxart" if ARCH_CHIP_MOXART default "nuc1xx" if ARCH_CHIP_NUC1XX default "sama5" if ARCH_CHIP_SAMA5 @@ -761,6 +775,9 @@ endif if ARCH_CHIP_LPC43XX source arch/arm/src/lpc43xx/Kconfig endif +if ARCH_CHIP_LPC54XX +source arch/arm/src/lpc54xx/Kconfig +endif if ARCH_CHIP_MOXART source arch/arm/src/moxart/Kconfig endif diff --git a/arch/arm/include/lpc54xx/chip.h b/arch/arm/include/lpc54xx/chip.h new file mode 100644 index 0000000000000000000000000000000000000000..962dc0300f990fdb74c64aec2a839d7939d0cb65 --- /dev/null +++ b/arch/arm/include/lpc54xx/chip.h @@ -0,0 +1,134 @@ +/************************************************************************************ + * arch/arm/include/lpc54xx/chip.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_LPC54XX_CHIP_H +#define __ARCH_ARM_INCLUDE_LPC54XX_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + *********************************************************************************** +/* LPC546xx Family Options. + * + * Family CPU Flash SRAM FS HS Ether- CAN CAN LCD Package + * MHz (Kb) (Kb) USB USB net 2.0 FD + * LPC54628 220 512 200 X X X X X X BGA180 + * LPC54618 180 <=512 <=200 X X X X X X BGA180, LQFP208 + * LPC54616 180 <=512 <=200 X X X X X BGA100, BGA180, LQFP100, LQFP208 + * LPC54608 180 512 200 X X X X X BGA180, LQFP208 + * LPC54607 180 <=512 <=200 X X X BGA180, LQFP208 + * LPC54606 180 <=512 <=200 X X X X BGA100, BGA180, LQFP100, LQFP208 + * LPC54605 180 <=512 <=200 X X BGA180 + */ + +/* NVIC priority levels *************************************************************/ +/* Each priority field holds a priority value, 0-31. The lower the value, the greater + * the priority of the corresponding interrupt. + * + * The Cortex-M4 core supports 8 programmable interrupt priority levels. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x20 /* Steps between priorities */ + +/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled + * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most + * interrupts will not have execution priority. SVCall must have execution + * priority in all cases. + * + * In the normal cases, interrupts are not nest-able and all interrupts run + * at an execution priority between NVIC_SYSH_PRIORITY_MIN and + * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). + * + * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special + * high priority interrupts are supported. These are not "nested" in the + * normal sense of the word. These high priority interrupts can interrupt + * normal processing but execute outside of OS (although they can "get back + * into the game" via a PendSV interrupt). + * + * In the normal course of things, interrupts must occasionally be disabled + * using the up_irq_save() inline function to prevent contention in use of + * resources that may be shared between interrupt level and non-interrupt + * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, + * do we disable all interrupts (except SVCall), or do we only disable the + * "normal" interrupts. Since the high priority interrupts cannot interact + * with the OS, you may want to permit the high priority interrupts even if + * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be + * used to select either behavior: + * + * ----------------------------+--------------+---------------------------- + * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES + * ----------------------------+--------------+--------------+------------- + * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO + * ----------------------------+--------------+--------------+------------- + * | | | SVCall + * | SVCall | SVCall | HIGH + * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL + * | | MAXNORMAL | + * ----------------------------+--------------+--------------+------------- + */ + +#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) +# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY +# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX +#else +# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX +# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY +# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_LPC43XX_CHIP_H */ diff --git a/arch/arm/include/lpc54xx/irq.h b/arch/arm/include/lpc54xx/irq.h new file mode 100644 index 0000000000000000000000000000000000000000..2be395af162aecc3a8f03e671abe5385456312a0 --- /dev/null +++ b/arch/arm/include/lpc54xx/irq.h @@ -0,0 +1,112 @@ +/******************************************************************************************** + * arch/arm/include/lpc54xxx/irq.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +/* This file should never be included directed but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_LPC54XX_IRQ_H +#define __ARCH_ARM_INCLUDE_LPC54XX_IRQ_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in + * the NVIC. This does, however, waste several words of memory in the IRQ to handle mapping + * tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define LPC54_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define LPC54_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define LPC54_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define LPC54_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define LPC54_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define LPC54_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define LPC54_IRQ_SIGNVALUE (7) /* Vector 7: Sign value */ +#define LPC54_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define LPC54_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define LPC54_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define LPC54_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define LPC54_IRQ_EXTINT (16) /* Vector 16: Vector number of the first external interrupt */ + +/* Cortex-M4 External interrupts (vectors >= 16) */ + +#if defined(CONFIG_ARCH_FAMILY_LPC546XX) +# include +#else +# error "Unsupported LPC54 MCU" +#endif + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +#ifndef __ASSEMBLY__ +typedef void (*vic_vector_t)(uint32_t *regs); + +/******************************************************************************************** + * Public Function Prototypes + ********************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_LPC54XX_IRQ_H */ + diff --git a/arch/arm/include/lpc54xx/lpc546x_irq.h b/arch/arm/include/lpc54xx/lpc546x_irq.h new file mode 100644 index 0000000000000000000000000000000000000000..964b56f0027fba18116eb087e0b09af8703def5b --- /dev/null +++ b/arch/arm/include/lpc54xx/lpc546x_irq.h @@ -0,0 +1,115 @@ +/**************************************************************************************************** + * arch/arm/include/lpc54xxx/lpc546x_irq.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_LPC54XX_LPC543X_IRQ_H +#define __ARCH_ARM_INCLUDE_LPC54XX_LPC543X_IRQ_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Cortex-M4 External interrupts (vectors >= 16) */ + +#define LPC54_IRQ_WDT (LPC54_IRQ_EXTINT+0) /* VOD Windowed watchdog timer, Brownout detect */ +#define LPC54_IRQ_DMA (LPC54_IRQ_EXTINT+1) /* DMA controller */ +#define LPC54_IRQ_GINT0 (LPC54_IRQ_EXTINT+2) /* GPIO group 0 */ +#define LPC54_IRQ_GINT1 (LPC54_IRQ_EXTINT+3) /* GPIO group 1 */ +#define LPC54_IRQ_PININT0 (LPC54_IRQ_EXTINT+4) /* Pin interrupt 0 or pattern match engine slice 0 */ +#define LPC54_IRQ_PININT1 (LPC54_IRQ_EXTINT+5) /* Pin interrupt 1 or pattern match engine slice 1 */ +#define LPC54_IRQ_PININT2 (LPC54_IRQ_EXTINT+6) /* Pin interrupt 2 or pattern match engine slice 2 */ +#define LPC54_IRQ_PININT3 (LPC54_IRQ_EXTINT+7) /* Pin interrupt 3 or pattern match engine slice 3 */ +#define LPC54_IRQ_UTICK (LPC54_IRQ_EXTINT+8) /* Micro-tick Timer */ +#define LPC54_IRQ_MRT (LPC54_IRQ_EXTINT+9) /* Multi-rate timer */ +#define LPC54_IRQ_CTIMER0 (LPC54_IRQ_EXTINT+10) /* Standard counter/timer CTIMER0 */ +#define LPC54_IRQ_CTIMER1 (LPC54_IRQ_EXTINT+11) /* Standard counter/timer CTIMER1 */ +#define LPC54_IRQ_SCTIMER (LPC54_IRQ_EXTINT+12) /* SCTimer/PWM0 */ +#define LPC54_IRQ_PWM0 (LPC54_IRQ_EXTINT+12) /* SCTimer/PWM0 */ +#define LPC54_IRQ_CTIMER3 (LPC54_IRQ_EXTINT+13) /* CTIMER3 Standard counter/timer CTIMER3 */ +#define LPC54_IRQ_FLEXCOMM0 (LPC54_IRQ_EXTINT+14) /* Flexcomm Interface 0 (USART, SPI, I2C) */ +#define LPC54_IRQ_FLEXCOMM1 (LPC54_IRQ_EXTINT+15) /* Flexcomm Interface 1 (USART, SPI, I2C) */ +#define LPC54_IRQ_FLEXCOMM2 (LPC54_IRQ_EXTINT+16) /* Flexcomm Interface 2 (USART, SPI, I2C) */ +#define LPC54_IRQ_FLEXCOMM3 (LPC54_IRQ_EXTINT+17) /* Flexcomm Interface 3 (USART, SPI, I2C) */ +#define LPC54_IRQ_FLEXCOMM4 (LPC54_IRQ_EXTINT+18) /* Flexcomm Interface 4 (USART, SPI, I2C) */ +#define LPC54_IRQ_FLEXCOMM5 (LPC54_IRQ_EXTINT+19) /* Flexcomm Interface 5 (USART, SPI, I2C) */ +#define LPC54_IRQ_FLEXCOMM6 (LPC54_IRQ_EXTINT+20) /* Flexcomm Interface 6 (USART, SPI, I2C, I2S) */ +#define LPC54_IRQ_FLEXCOMM7 (LPC54_IRQ_EXTINT+21) /* Flexcomm Interface 7 (USART, SPI, I2C, I2S) */ +#define LPC54_IRQ_ADC0SEQA (LPC54_IRQ_EXTINT+22) /* ADC0 sequence A completion */ +#define LPC54_IRQ_ADC0SEQB (LPC54_IRQ_EXTINT+23) /* ADC0 sequence B completion */ +#define LPC54_IRQ_ADC0THCMP (LPC54_IRQ_EXTINT+24) /* ADC0 threshold compare and error */ +#define LPC54_IRQ_DMIC (LPC54_IRQ_EXTINT+25) /* Digital microphone and audio subsystem */ +#define LPC54_IRQ_HWVAD (LPC54_IRQ_EXTINT+26) /* Hardware Voice Activity Detection */ +#define LPC54_IRQ_USB0NEEDCLK (LPC54_IRQ_EXTINT+27) /* USB0 Activity Interrupt */ +#define LPC54_IRQ_USB0 (LPC54_IRQ_EXTINT+28) /* USB0 host and device */ +#define LPC54_IRQ_RTC (LPC54_IRQ_EXTINT+29) /* RTC alarm and wake-up interrupts */ + /* 30-31 Reserved */ +#define LPC54_IRQ_PININT4 (LPC54_IRQ_EXTINT+32) /* Pin interrupt 4 or pattern match engine slice 4 */ +#define LPC54_IRQ_PININT5 (LPC54_IRQ_EXTINT+33) /* Pin interrupt 5 or pattern match engine slice 5 */ +#define LPC54_IRQ_PININT6 (LPC54_IRQ_EXTINT+34) /* Pin interrupt 6 or pattern match engine slice 6 */ +#define LPC54_IRQ_PININT7 (LPC54_IRQ_EXTINT+35) /* Pin interrupt 7 or pattern match engine slice 7 */ +#define LPC54_IRQ_CTIMER2 (LPC54_IRQ_EXTINT+36) /* Standard counter/timer CTIMER2 */ +#define LPC54_IRQ_CTIMER4 (LPC54_IRQ_EXTINT+37) /* Standard counter/timer CTIMER4 */ +#define LPC54_IRQ_RIT (LPC54_IRQ_EXTINT+38) /* Repetitive Interrupt Timer */ +#define LPC54_IRQ_SPIFI (LPC54_IRQ_EXTINT+39) /* SPI flash interface */ +#define LPC54_IRQ_FLEXCOMM8 (LPC54_IRQ_EXTINT+40) /* Flexcomm Interface 8 (USART, SPI, I2C) */ +#define LPC54_IRQ_FLEXCOMM9 (LPC54_IRQ_EXTINT+41) /* Flexcomm Interface 9 (USART, SPI, I2C) */ +#define LPC54_IRQ_SDMMC (LPC54_IRQ_EXTINT+42) /* SD/MMC interrupt */ +#define LPC54_IRQ_CAN0IRQ0 (LPC54_IRQ_EXTINT+43) /* CAN0 interrupt 0 */ +#define LPC54_IRQ_CAN0IRQ1 (LPC54_IRQ_EXTINT+44) /* CAN0 interrupt 1 */ +#define LPC54_IRQ_CAN1IRQ0 (LPC54_IRQ_EXTINT+45) /* CAN1 interrupt 0 */ +#define LPC54_IRQ_CAN1IRQ1 (LPC54_IRQ_EXTINT+46) /* CAN1 interrupt 1 */ +#define LPC54_IRQ_USB1 (LPC54_IRQ_EXTINT+47) /* USB1 interrupt */ +#define LPC54_IRQ_USB1NEEDCLK (LPC54_IRQ_EXTINT+48) /* USB1 activity */ +#define LPC54_IRQ_ETHERNET (LPC54_IRQ_EXTINT+49) /* Ethernet */ +#define LPC54_IRQ_ETHERNETPMT (LPC54_IRQ_EXTINT+50) /* Ethernet power management interrupt */ +#define LPC54_IRQ_ETHERNETMACLP (LPC54_IRQ_EXTINT+51) /* Ethernet MAC interrupt */ +#define LPC54_IRQ_EEPROM (LPC54_IRQ_EXTINT+52) /* EEPROM interrupt */ +#define LPC54_IRQ_LCD (LPC54_IRQ_EXTINT+53) /* LCD interrupt */ +#define LPC54_IRQ_SHA (LPC54_IRQ_EXTINT+54) /* SHA interrupt */ +#define LPC54_IRQ_SMARTCARD0 (LPC54_IRQ_EXTINT+55) /* Smart card 0 interrupt */ +#define LPC54_IRQ_SMARTCARD1 (LPC54_IRQ_EXTINT+56) /* Smart card 1 interrupt */ + +#define LPC54_IRQ_NEXTINT (57) +#define LPC54_IRQ_NIRQS (LPC54_IRQ_EXTINT+LPC54_IRQ_NEXTINT) + +/* Total number of IRQ numbers */ + +#define NR_VECTORS LPC54_IRQ_NIRQS +#define NR_IRQS LPC54_IRQ_NIRQS + +#endif /* __ARCH_ARM_INCLUDE_LPC54XX_LPC543X_IRQ_H */ diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h index d8de19a4419235dc3bb19b295bb36aa58d68338f..0c197549c99a592ddf523a5b767c017939dc7784 100644 --- a/arch/arm/include/stm32/chip.h +++ b/arch/arm/include/stm32/chip.h @@ -1689,21 +1689,21 @@ * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ # define STM32_NGTIMNDMA 0 /* All timers have DMA */ # define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (2) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (3) SPI1 */ -# define STM32_NI2S 0 /* (0) I2S1 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S1 */ # define STM32_NUSART 2 /* (2) USART1-2 */ -# define STM32_NI2C 1 /* (2) I2C1 */ +# define STM32_NI2C 1 /* (1) I2C1 */ # define STM32_NCAN 1 /* (1) CAN1 */ # define STM32_NSDIO 0 /* (0) No SDIO */ # define STM32_NLCD 0 /* (0) No LCD */ # define STM32_NUSBOTG 0 /* (0) No USB */ # define STM32_NGPIO 25 /* GPIOA-F */ -# define STM32_NADC 2 /* (3) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (2) 12-bit DAC1 CH1/CH2 and DAC2 CH1 */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1 CH1/CH2 and DAC2 CH1 */ # define STM32_NCMP 2 /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */ # define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 14 /* (14) No capacitive sensing channels */ +# define STM32_NCAPSENSE 14 /* (14) Capacitive sensing channels */ # define STM32_NCRC 1 /* (1) CRC calculation unit */ # define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ # define STM32_NRNG 0 /* (0) No random number generator (RNG) */ @@ -1733,21 +1733,21 @@ * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ # define STM32_NGTIMNDMA 0 /* All timers have DMA */ # define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (2) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (3) SPI1 */ -# define STM32_NI2S 0 /* (0) I2S1 */ -# define STM32_NUSART 3 /* (2) USART1-3 */ -# define STM32_NI2C 1 /* (2) I2C1 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S1 */ +# define STM32_NUSART 3 /* (3) USART1-3 */ +# define STM32_NI2C 1 /* (1) I2C1 */ # define STM32_NCAN 1 /* (1) CAN1 */ # define STM32_NSDIO 0 /* (0) No SDIO */ # define STM32_NLCD 0 /* (0) No LCD */ # define STM32_NUSBOTG 0 /* (0) No USB */ # define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */ -# define STM32_NDAC 3 /* (2) 12-bit DAC1 CH1/CH2 and DAC2 CH1 */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1 CH1/CH2 and DAC2 CH1 */ # define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ # define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 17 /* (17) No capacitive sensing channels */ +# define STM32_NCAPSENSE 17 /* (17) Capacitive sensing channels */ # define STM32_NCRC 1 /* (1) CRC calculation unit */ # define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ # define STM32_NRNG 0 /* (0) No random number generator (RNG) */ @@ -1777,21 +1777,21 @@ * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ # define STM32_NGTIMNDMA 0 /* All timers have DMA */ # define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (2) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (3) SPI1 */ -# define STM32_NI2S 0 /* (0) I2S1 */ -# define STM32_NUSART 3 /* (2) USART1-3 */ -# define STM32_NI2C 1 /* (2) I2C1 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S1 */ +# define STM32_NUSART 3 /* (3) USART1-3 */ +# define STM32_NI2C 1 /* (1) I2C1 */ # define STM32_NCAN 1 /* (1) CAN1 */ # define STM32_NSDIO 0 /* (0) No SDIO */ # define STM32_NLCD 0 /* (0) No LCD */ # define STM32_NUSBOTG 0 /* (0) No USB */ # define STM32_NGPIO 51 /* GPIOA-F */ -# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */ -# define STM32_NDAC 3 /* (2) 12-bit DAC1 CH1/CH2 and DAC2 CH1 */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1 CH1/CH2 and DAC2 CH1 */ # define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ # define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 18 /* (18) No capacitive sensing channels */ +# define STM32_NCAPSENSE 18 /* (18) Capacitive sensing channels */ # define STM32_NCRC 1 /* (1) CRC calculation unit */ # define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ # define STM32_NRNG 0 /* (0) No random number generator (RNG) */ diff --git a/arch/arm/include/stm32/dma2d.h b/arch/arm/include/stm32/dma2d.h deleted file mode 100644 index be807de31dca8b917cad700529c7d6da46568c57..0000000000000000000000000000000000000000 --- a/arch/arm/include/stm32/dma2d.h +++ /dev/null @@ -1,415 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/dma2d.h - * - * Copyright (C) 2015 Marco Krahl. All rights reserved. - * Author: Marco Krahl - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_STM32_DMA2D_H -#define __ARCH_ARM_INCLUDE_STM32_DMA2D_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -struct ltdc_area_s; /* see arch/chip/ltdc.h */ - -/* Blend mode definitions */ - -enum dma2d_blend_e -{ - DMA2D_BLEND_NONE = 0, /* Disable all blend operation */ - DMA2D_BLEND_ALPHA = 0x1, /* Enable alpha blending */ - DMA2D_BLEND_PIXELALPHA = 0x2, /* Enable alpha blending from pixel color */ -}; - -/* The layer is controlled through the following structure */ - -struct dma2d_layer_s -{ - /* Name: getvideoinfo - * - * Description: - * Get video information about the layer - * - * Parameter: - * layer - Reference to the layer control structure - * vinfo - Reference to the video info structure - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getvideoinfo)(FAR struct dma2d_layer_s *layer, - FAR struct fb_videoinfo_s *vinfo); - - /* Name: getplaneinfo - * - * Description: - * Get plane information about the layer - * - * Parameter: - * layer - Reference to the layer control structure - * planeno - Number of the plane - * pinfo - Reference to the plane info structure - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getplaneinfo)(FAR struct dma2d_layer_s *layer, int planeno, - FAR struct fb_planeinfo_s *pinfo); - - /* Name: getlid - * - * Description: - * Get a specific layer identifier. - * - * Parameter: - * layer - Reference to the layer structure - * lid - Reference to store the layer id - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getlid)(FAR struct dma2d_layer_s *layer, int *lid); - -#ifdef CONFIG_STM32_DMA2D_L8 - /* Name: setclut - * - * Description: - * Configure layer clut (color lookup table). - * Non clut is defined during initializing. - * - * Parameter: - * layer - Reference to the layer structure - * cmap - color lookup table with up the 256 entries - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*setclut)(FAR struct dma2d_layer_s *layer, - const FAR struct fb_cmap_s *cmap); - - /* Name: getclut - * - * Description: - * Get configured layer clut (color lookup table). - * - * Parameter: - * layer - Reference to the layer structure - * cmap - Reference to valid color lookup table accept up the 256 color - * entries - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getclut)(FAR struct dma2d_layer_s *layer, FAR struct fb_cmap_s *cmap); -#endif - - /* Name: setalpha - * - * Description: - * Configure layer alpha value factor into blend operation. - * During the layer blend operation the source alpha value is multiplied - * with this alpha value. If the source color format doesn't support alpha - * channel (e.g. non ARGB8888) this alpha value will be used as constant - * alpha value for blend operation. - * Default value during initializing: 0xff - * - * Parameter: - * layer - Reference to the layer structure - * alpha - Alpha value - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*setalpha)(FAR struct dma2d_layer_s *layer, uint8_t alpha); - - /* Name: getalpha - * - * Description: - * Get configured layer alpha value factor for blend operation. - * - * Parameter: - * layer - Reference to the layer structure - * alpha - Reference to store the alpha value - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getalpha)(FAR struct dma2d_layer_s *layer, uint8_t *alpha); - - /* Name: setblendmode - * - * Description: - * Configure blend mode of the layer. - * Default mode during initializing: DMA2D_BLEND_NONE - * Blendmode is active after next update. - * - * Parameter: - * layer - Reference to the layer structure - * mode - Blend mode (see DMA2D_BLEND_*) - * - * Return: - * On success - OK - * On error - -EINVAL - * - * Procedure information: - * DMA2D_BLEND_NONE: - * Informs the driver to disable all blend operation for the given layer. - * That means the layer is opaque. - * - * DMA2D_BLEND_ALPHA: - * Informs the driver to enable alpha blending for the given layer. - * - * DMA2D_BLEND_PIXELALPHA: - * Informs the driver to use the pixel alpha value of the layer instead - * the constant alpha value. This is only useful for ARGB8888 - * color format. - */ - - int (*setblendmode)(FAR struct dma2d_layer_s *layer, uint32_t mode); - - /* Name: getblendmode - * - * Description: - * Get configured blend mode of the layer. - * - * Parameter: - * layer - Reference to the layer structure - * mode - Reference to store the blend mode - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getblendmode)(FAR struct dma2d_layer_s *layer, uint32_t *mode); - - /* Name: blit - * - * Description: - * Copy selected area from a source layer to selected position of the - * destination layer. - * - * Parameter: - * dest - Reference to the destination layer - * destxpos - Selected x target position of the destination layer - * destypos - Selected y target position of the destination layer - * src - Reference to the source layer - * srcarea - Reference to the selected area of the source layer - * - * Return: - * OK - On success - * -EINVAL - If one of the parameter invalid or if the size of the - * selected source area outside the visible area of the - * destination layer. (The visible area usually represents the - * display size) - * -ECANCELED - Operation cancelled, something goes wrong. - */ - - int (*blit)(FAR struct dma2d_layer_s *dest, - fb_coord_t destxpos, fb_coord_t destypos, - FAR const struct dma2d_layer_s *src, - FAR const struct ltdc_area_s *srcarea); - - /* Name: blend - * - * Description: - * Blends the selected area from a background layer with selected position - * of the foreground layer. Copies the result to the selected position of - * the destination layer. Note! The content of the foreground and background - * layer keeps unchanged as long destination layer is unequal to the - * foreground and background layer. - * - * Parameter: - * dest - Reference to the destination layer - * fore - Reference to the foreground layer - * forexpos - Selected x target position of the foreground layer - * foreypos - Selected y target position of the foreground layer - * back - Reference to the background layer - * backarea - Reference to the selected area of the background layer - * - * Return: - * OK - On success - * -EINVAL - If one of the parameter invalid or if the size of the - * selected source area outside the visible area of the - * destination layer. (The visible area usually represents the - * display size) - * -ECANCELED - Operation cancelled, something goes wrong. - */ - - int (*blend)(FAR struct dma2d_layer_s *dest, - fb_coord_t destxpos, fb_coord_t destypos, - FAR const struct dma2d_layer_s *fore, - fb_coord_t forexpos, fb_coord_t foreypos, - FAR const struct dma2d_layer_s *back, - FAR const struct ltdc_area_s *backarea); - - /* Name: fillarea - * - * Description: - * Fill the selected area of the whole layer with a specific color. - * - * Parameter: - * layer - Reference to the layer structure - * area - Reference to the valid area structure select the area - * color - Color to fill the selected area. Color must be formatted - * according to the layer pixel format. - * - * Return: - * OK - On success - * -EINVAL - If one of the parameter invalid or if the size of the - * selected area outside the visible area of the layer. - * -ECANCELED - Operation cancelled, something goes wrong. - */ - - int (*fillarea)(FAR struct dma2d_layer_s *layer, - FAR const struct ltdc_area_s *area, - uint32_t color); -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_dma2dgetlayer - * - * Description: - * Get a dma2d layer structure by the layer identifier - * - * Parameter: - * lid - Layer identifier - * - * Return: - * Reference to the dma2d layer control structure on success or Null if no - * related exist. - * - ****************************************************************************/ - -FAR struct dma2d_layer_s *up_dma2dgetlayer(int lid); - -/**************************************************************************** - * Name: up_dma2dcreatelayer - * - * Description: - * Create a new dma2d layer object to interact with the dma2d controller - * - * Parameter: - * width - Layer width - * height - Layer height - * fmt - Pixel format of the layer - * - * Return: - * On success - A valid dma2d layer reference - * On error - NULL and errno is set to - * -EINVAL if one of the parameter is invalid - * -ENOMEM if no memory available or exceeds - * CONFIG_STM32_DMA2D_NLAYERS - * - ****************************************************************************/ - -FAR struct dma2d_layer_s *up_dma2dcreatelayer(fb_coord_t width, - fb_coord_t height, - uint8_t fmt); - -/**************************************************************************** - * Name: up_dma2dremovelayer - * - * Description: - * Remove and deallocate the dma2d layer - * - * Parameter: - * layer - Reference to the layer to remove - * - * Return: - * On success - OK - * On error - -EINVAL - * - ****************************************************************************/ - -int up_dma2dremovelayer(FAR struct dma2d_layer_s *layer); - -/**************************************************************************** - * Name: up_dma2dinitialize - * - * Description: - * Initialize the dma2d controller - * - * Return: - * OK - On success - * An error if initializing failed. - * - ****************************************************************************/ - -int up_dma2dinitialize(void); - -/**************************************************************************** - * Name: up_dma2duninitialize - * - * Description: - * Uninitialize the dma2d controller - * - ****************************************************************************/ - -void up_dma2duninitialize(void); - -#endif /* __ARCH_ARM_INCLUDE_STM32_DMA2D_H */ diff --git a/arch/arm/include/stm32/ltdc.h b/arch/arm/include/stm32/ltdc.h deleted file mode 100644 index c561c680cd6262e5c8c24ea0841c5fc3e2037072..0000000000000000000000000000000000000000 --- a/arch/arm/include/stm32/ltdc.h +++ /dev/null @@ -1,592 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/ltdc.h - * - * Copyright (C) 2014-2015 Marco Krahl. All rights reserved. - * Author: Marco Krahl - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_STM32_LTDC_H -#define __ARCH_ARM_INCLUDE_STM32_LTDC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#ifdef CONFIG_STM32_LTDC -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -struct dma2d_layer_s; /* see arch/chip/dma2d.h */ - -/* Blend mode definitions */ - -enum ltdc_blend_e -{ - LTDC_BLEND_NONE = 0, /* Disable all blend operation */ - LTDC_BLEND_ALPHA = 0x1, /* Enable alpha blending */ - LTDC_BLEND_PIXELALPHA = 0x2, /* Enable alpha blending from pixel color */ - LTDC_BLEND_COLORKEY = 0x4, /* Enable colorkey */ - LTDC_BLEND_ALPHAINV = 0x8, /* Inverse alpha blending of source */ - LTDC_BLEND_PIXELALPHAINV = 0x10 /* Invers pixel alpha blending of source */ -}; - -/* layer control definitions */ - -enum ltdc_layer_e -{ - LTDC_LAYER_OWN = 0, /* The given layer */ - LTDC_LAYER_TOP = 0x1, /* The initialized top layer */ - LTDC_LAYER_BOTTOM = 0x2, /* the initialized bottom layer */ - LTDC_LAYER_ACTIVE = 0x4, /* The current visible flip layer */ - LTDC_LAYER_INACTIVE = 0x8 /* The current invisible flip layer */ -#ifdef CONFIG_STM32_DMA2D - ,LTDC_LAYER_DMA2D = 0x10 /* The dma2d interface layer id */ -#endif -}; - -/* Update operation flag */ - -enum ltdc_update_e -{ - LTDC_UPDATE_NONE = 0, /* Update given layer only */ - LTDC_UPDATE_SIM = 0x1, /* Update both layer simultaneous */ - LTDC_UPDATE_FLIP = 0x2, /* Perform flip operation */ - LTDC_UPDATE_ACTIVATE = 0x4 /* Set the given layer to the active layer */ -}; - -/* sync mode definitions */ - -enum ltdc_sync_e -{ - LTDC_SYNC_NONE = 0, /* Immediately */ - LTDC_SYNC_VBLANK = 0x100, /* Upon vertical sync */ - LTDC_SYNC_WAIT = 0x200 /* Waits upon vertical sync */ -}; - -/* Definition of the visible layer position and size */ - -struct ltdc_area_s -{ - fb_coord_t xpos; /* X position in pixel */ - fb_coord_t ypos; /* Y position in pixel */ - fb_coord_t xres; /* X resolution in pixel */ - fb_coord_t yres; /* Y resolution in pixel */ -}; - -/* The layer is controlled through the following structure */ - -struct ltdc_layer_s -{ - - /* - * Name: getvideoinfo - * - * Description: - * Get video information about the layer - * - * Parameter: - * layer - Reference to the layer control structure - * vinfo - Reference to the video info structure - * - * Return: - * On success - OK - * On error - -EINVAL - * - */ - int (*getvideoinfo)(FAR struct ltdc_layer_s *layer, - FAR struct fb_videoinfo_s *vinfo); - - /* - * Name: getplaneinfo - * - * Description: - * Get plane information about the layer - * - * Parameter: - * layer - Reference to the layer control structure - * planeno - Number of the plane - * pinfo - Reference to the plane info structure - * - * Return: - * On success - OK - * On error - -EINVAL - * - */ - int (*getplaneinfo)(FAR struct ltdc_layer_s *layer, int planeno, - FAR struct fb_planeinfo_s *pinfo); - - /* - * Name: getlid - * - * Description: - * Get a specific layer identifier. - * - * Parameter: - * layer - Reference to the layer structure - * lid - Reference to store the layer id - * flag - Operation flag describe the layer identifier - * e.g. get the current active or inactive layer. - * See LTDC_LAYER_* for possible values - * - * Return: - * On success - OK - * On error - -EINVAL - * - */ - int (*getlid)(FAR struct ltdc_layer_s *layer, int *lid, uint32_t flag); - -#ifdef CONFIG_FB_CMAP - /* - * Name: setclut - * - * Description: - * Configure layer clut (color lookup table). - * Non clut is defined during initializing. - * Clut is active during next vertical blank period. Do not need an update. - * - * Parameter: - * layer - Reference to the layer structure - * cmap - color lookup table with up the 256 entries - * enable - Enable or disable clut support (if false cmap is ignored and can - * be NULL) - * - * Return: - * On success - OK - * On error - -EINVAL - * - */ - int (*setclut)(FAR struct ltdc_layer_s *layer, - const FAR struct fb_cmap_s *cmap); - - /* - * Name: getclut - * - * Description: - * Get configured layer clut (color lookup table). - * - * Parameter: - * layer - Reference to the layer structure - * cmap - Reference to valid color lookup table accept up the 256 color - * entries - * - * Return: - * On success - OK - * On error - -EINVAL - * - */ - int (*getclut)(FAR struct ltdc_layer_s *layer, FAR struct fb_cmap_s *cmap); -#endif - - /* - * Name: setcolor - * - * Description: - * Configure layer color for the non active layer area. - * Default value during initializing: 0x00000000 - * Color is active after next update. - * - * Parameter: - * layer - Reference to the layer structure - * argb - ARGB8888 color value - * - * Return: - * On success - OK - * On error - -EINVAL - * - */ - int (*setcolor)(FAR struct ltdc_layer_s *layer, uint32_t argb); - - /* - * Name: getcolor - * - * Description: - * Get configured layer color for the non active layer area. - * - * Parameter: - * layer - Reference to the layer structure - * argb - Reference to store the ARGB8888 color value - * - * Return: - * On success - OK - * On error - -EINVAL - * - */ - int (*getcolor)(FAR struct ltdc_layer_s *layer, uint32_t *argb); - - /* - * Name: setcolorkey - * - * Description: - * Configure the layer color key (chromakey) for transparence. - * Default value during initializing: 0x00000000 - * Colorkey is active after next update. - * - * Parameter: - * layer - Reference to the layer structure - * rgb - RGB888 color key - * - * Return: - * On success - OK - * On error - -EINVAL - * - */ - int (*setcolorkey)(FAR struct ltdc_layer_s *layer, uint32_t rgb); - - /* - * Name: getcolorkey - * - * Description: - * Get the configured layer color key (chromakey) for transparence. - * - * Parameter: - * layer - Reference to the layer structure - * rgb - Reference to store the RGB888 color key - * - * Return: - * On success - OK - * On error - -EINVAL - * - */ - int (*getcolorkey)(FAR struct ltdc_layer_s *layer, uint32_t *rgb); - - /* - * Name: setalpha - * - * Description: - * Configure layer alpha value factor into blend operation. - * During the layer blend operation the source alpha value is multiplied - * with this alpha value. If the source color format doesn't support alpha - * channel (e.g. non ARGB8888) this alpha value will be used as constant - * alpha value for blend operation. - * Default value during initializing: 0xff - * Alpha is active after next update. - * - * Parameter: - * layer - Reference to the layer structure - * alpha - Alpha value - * - * Return: - * On success - OK - * On error - -EINVAL - * - */ - int (*setalpha)(FAR struct ltdc_layer_s *layer, uint8_t alpha); - - /* - * Name: getalpha - * - * Description: - * Get configured layer alpha value factor for blend operation. - * - * Parameter: - * layer - Reference to the layer structure - * alpha - Reference to store the alpha value - * - * Return: - * On success - OK - * On error - -EINVAL - * - */ - int (*getalpha)(FAR struct ltdc_layer_s *layer, uint8_t *alpha); - - /* - * Name: setblendmode - * - * Description: - * Configure blend mode of the layer. - * Default mode during initializing: LTDC_BLEND_NONE - * Blendmode is active after next update. - * - * Parameter: - * layer - Reference to the layer structure - * mode - Blend mode (see LTDC_BLEND_*) - * - * Return: - * On success - OK - * On error - -EINVAL - * - * Procedure information: - * LTDC_BLEND_NONE: - * Informs the driver to disable all blend operation for the given layer. - * That means the layer is opaque. Note this has no effect on the - * colorkey settings. - * - * LTDC_BLEND_ALPHA: - * Informs the driver to enable alpha blending for the given layer. - * - * LTDC_BLEND_COLORKEY: - * Informs the driver to enable colorkeying for the given layer. - * - * LTDC_BLEND_SRCPIXELALPHA: - * Informs the driver to use the pixel alpha value of the layer instead - * the constant alpha value. This is only useful for ARGB8888 - * color format. - * - * LTDC_BLEND_DESTPIXELALPHA: - * Informs the driver to use the pixel alpha value of the subjacent layer - * instead the constant alpha value. This is only useful for ARGB8888 - * color format. - * - */ - int (*setblendmode)(FAR struct ltdc_layer_s *layer, uint32_t mode); - - /* - * Name: getblendmode - * - * Description: - * Get configured blend mode of the layer. - * - * Parameter: - * layer - Reference to the layer structure - * mode - Reference to store the blend mode - * - * Return: - * On success - OK - * On error - -EINVAL - * - */ - int (*getblendmode)(FAR struct ltdc_layer_s *layer, uint32_t *mode); - - /* - * Name: setarea - * - * Description: - * Configure visible layer area and the reference position of the first - * pixel of the whole layer which is the first visible top left pixel in - * the active area. - * Default value during initializing: - * xpos = 0 - * ypos = 0 - * xres = display x resolution - * yres = display y resolution - * - * Area is active after next update. - * - * Parameter: - * layer - Reference to the layer control structure - * area - Reference to the valid area structure for the new active area - * srcxpos - x position of the visible pixel of the whole layer - * srcypos - y position of the visible pixel of the whole layer - * - * Return: - * On success - OK - * On error - -EINVAL - * - * Procedure Information: - * If the srcxpos and srcypos unequal the xpos and ypos of the coord - * structure this acts like moving the visible area to another position on - * the screen during the next update operation. - * - */ - int (*setarea)(FAR struct ltdc_layer_s *layer, - FAR const struct ltdc_area_s *area, - fb_coord_t srcxpos, - fb_coord_t srcypos); - - /* - * Name: getarea - * - * Description: - * Get configured visible layer area. - * - * Parameter: - * layer - Reference to the layer control structure - * area - Reference to the area structure to store the active area - * srcxpos - Reference to store the referenced x position of the whole layer - * srcypos - Reference to store the reterenced y position of the whole layer - * - * Return: - * On success - OK - * On error - -EINVAL - * - */ - int (*getarea)(FAR struct ltdc_layer_s *layer, - FAR struct ltdc_area_s *area, - fb_coord_t *srcxpos, - fb_coord_t *srcypos); - - /* - * Name: update - * - * Description: - * Update current layer settings and make changes visible. - * - * Parameter: - * layer - Reference to the layer structure - * mode - operation mode (see LTDC_UPDATE_*) - * - * Return: - * OK - On success - * -EINVAL - If one of the parameter invalid - * -ECANCELED - Operation cancelled, something goes wrong - * - * Procedure information: - * LTDC_UPDATE_SIM: - * Informs the driver to update both ltdc layers simultaneously. Otherwise - * update the given layer only. - * - * LTDC_UPDATE_FLIP: - * Informs the driver to perform a flip operation. - * This only effects the ltdc layer 1 and 2 and can be useful for double - * buffering. Each flip operation changed the active layer ot the inactive - * and vice versa. In the context of the ltdc that means, the inactive layer - * is complete disabled. So the subjacent layer is the background layer - * (background color). To reactivate both layer and their settings perform - * an update without LTDC_UPDATE_FLIP flag. - * - * LTDC_UPDATE_ACTIVATE: - * Informs the driver that the given layer should be the active layer when - * the operation is complete. - * - * LTDC_SYNC_VBLANK: - * Informs the driver to update the layer upon vertical blank. Otherwise - * immediately. - * - */ - int (*update)(FAR struct ltdc_layer_s *layer, uint32_t mode); - -#ifdef CONFIG_STM32_DMA2D - /* - * Name: blit - * - * Description: - * Copy selected area from a source layer to selected position of the - * destination layer. - * - * Parameter: - * dest - Reference to the destination layer - * destxpos - Selected x position of the destination layer - * destypos - Selected y position of the destination layer - * src - Reference to the source layer - * srcarea - Reference to the selected area of the source layer - * - * Return: - * OK - On success - * -EINVAL - If one of the parameter invalid or if the size of the selected - * source area outside the visible area of the destination layer. - * (The visible area usually represents the display size) - * - */ - int (*blit)(FAR struct ltdc_layer_s *dest, - fb_coord_t destxpos, fb_coord_t destypos, - FAR const struct dma2d_layer_s *src, - FAR const struct ltdc_area_s *srcarea); - /* - * - * Name: blend - * - * Description: - * Blends the selected area from a foreground layer with selected position - * of the background layer. Copy the result to the destination layer. Note! - * The content of the foreground and background layer is not changed. - * - * Parameter: - * dest - Reference to the destination layer - * destxpos - Selected x position of the destination layer - * destypos - Selected y position of the destination layer - * fore - Reference to the foreground layer - * forexpos - Selected x position of the foreground layer - * foreypos - Selected y position of the foreground layer - * back - Reference to the background layer - * backarea - Reference to the selected area of the background layer - * - * Return: - * OK - On success - * -EINVAL - If one of the parameter invalid or if the size of the selected - * source area outside the visible area of the destination layer. - * (The visible area usually represents the display size) - * - */ - int (*blend)(FAR struct ltdc_layer_s *dest, - fb_coord_t destxpos, fb_coord_t destypos, - FAR const struct dma2d_layer_s *fore, - fb_coord_t forexpos, fb_coord_t foreypos, - FAR const struct dma2d_layer_s *back, - FAR const struct ltdc_area_s *backarea); - - /* - * Name: fillarea - * - * Description: - * Fill the selected area of the whole layer with a specific color. - * - * Parameter: - * layer - Reference to the layer structure - * area - Reference to the valid area structure select the area - * color - Color to fill the selected area. Color must be formatted - * according to the layer pixel format. - * - * Return: - * OK - On success - * -EINVAL - If one of the parameter invalid or if the size of the selected - * area outside the visible area of the layer. - * - */ - int (*fillarea)(FAR struct ltdc_layer_s *layer, - FAR const struct ltdc_area_s *area, - uint32_t color); -#endif -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_ltdcgetlayer - * - * Description: - * Get the ltdc layer structure to perform hardware layer operation - * - * Parameter: - * lid - Layer identifier - * - * Return: - * Reference to the layer control structure on success or Null if parameter - * invalid. - * - ****************************************************************************/ -FAR struct ltdc_layer_s *up_ltdcgetlayer(int lid); -#endif /* CONFIG_STM32_LTDC */ -#endif /* __ARCH_ARM_INCLUDE_STM32_LTDC_H */ diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h index 7246cb2a2d5d8e59ea4dde1e7e67f4768b41462d..5735683959451f8cad4e6afde803bdaca20ee8f3 100644 --- a/arch/arm/include/stm32f7/chip.h +++ b/arch/arm/include/stm32f7/chip.h @@ -1,9 +1,10 @@ /************************************************************************************ * arch/arm/include/stm32f7/chip.h * - * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane + * Bob Feretich * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -46,13 +47,23 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* STM32F745xx, STM32F746xx, STM32F756xx, STM32F765xx, STM32F767xx, STM32F768xx, +/* STM32F722xx, STM32F723xx, + * STM32F745xx, STM32F746xx, STM32F756xx, STM32F765xx, STM32F767xx, STM32F768xx, * STM32F769xx, STM32F777xx and STM32F779xx Differences between family members: * * ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------ * SPI ADC LCD * PART PACKAGE GPIOs I2S CHAN TFT MIPI JPEG CAN ETH DFSDM CRYPTO FPU RAM L1 * ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------ + * STM32F722Rx LQFP64 50 3/3 16 No No No 1 No No No SFPU (176+16+64) 8+8 + * STM32F722Vx LQFP100 82 4/3 16 No No No 1 No No No SFPU (176+16+64) 8+8 + * STM32F722Zx LQFP144 114 5/3 24 No No No 1 No No No SFPU (176+16+64) 8+8 + * STM32F722Ix UFBGA176/LQFP176 140 5/3 24 No No No 1 No No No SFPU (176+16+64) 8+8 + * + * STM32F723Vx WLCSP100 79 4/3 16 No No No 1 No No No SFPU (176+16+64) 8+8 + * STM32F723Zx UFBGA144/LQFP144 112 5/3 24 No No No 1 No No No SFPU (176+16+64) 8+8 + * STM32F723Ix UFBGA176/LQFP176 138 5/3 24 No No No 1 No No No SFPU (176+16+64) 8+8 + * * STM32F745Vx LQFP100 82 4/3 16 No No No 2 Yes No No SFPU (240+16+64) 4+4 * STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4 * STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4 @@ -108,6 +119,8 @@ * STM32F779Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16 * ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------ * + * Parts STM32F72xxC & STM32F73xxC have 256Kb of FLASH + * Parts STM32F72xxE & STM32F73xxE have 512Kb of FLASH * Parts STM32F74xxE have 512Kb of FLASH * Parts STM32F74xxG have 1024Kb of FLASH * Parts STM32F74xxI have 2048Kb of FLASH @@ -116,7 +129,23 @@ * with CONFIG_STM32F7_FLASH_OVERRIDE_x * */ -#if defined(CONFIG_ARCH_CHIP_STM32F745VG) || \ +#if defined(CONFIG_ARCH_CHIP_STM32F722RC) || \ + defined(CONFIG_ARCH_CHIP_STM32F722RE) || \ + defined(CONFIG_ARCH_CHIP_STM32F722VC) || \ + defined(CONFIG_ARCH_CHIP_STM32F722VE) || \ + defined(CONFIG_ARCH_CHIP_STM32F722ZC) || \ + defined(CONFIG_ARCH_CHIP_STM32F722ZE) || \ + defined(CONFIG_ARCH_CHIP_STM32F722IC) || \ + defined(CONFIG_ARCH_CHIP_STM32F722IE) || \ + defined(CONFIG_ARCH_CHIP_STM32F723RC) || \ + defined(CONFIG_ARCH_CHIP_STM32F723RE) || \ + defined(CONFIG_ARCH_CHIP_STM32F723VC) || \ + defined(CONFIG_ARCH_CHIP_STM32F723VE) || \ + defined(CONFIG_ARCH_CHIP_STM32F723ZC) || \ + defined(CONFIG_ARCH_CHIP_STM32F723ZE) || \ + defined(CONFIG_ARCH_CHIP_STM32F723IC) || \ + defined(CONFIG_ARCH_CHIP_STM32F723IE) || \ + defined(CONFIG_ARCH_CHIP_STM32F745VG) || \ defined(CONFIG_ARCH_CHIP_STM32F745VE) || \ defined(CONFIG_ARCH_CHIP_STM32F745IG) || \ defined(CONFIG_ARCH_CHIP_STM32F745IE) || \ @@ -179,7 +208,20 @@ /* Size SRAM */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# define STM32F7_SRAM1_SIZE (176*1024) /* 176Kb SRAM1 on AHB bus Matrix */ +# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +# if defined(CONFIG_ARMV7M_HAVE_DTCM) +# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ +# else +# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# endif +# if defined(CONFIG_ARMV7M_HAVE_ITCM) +# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# else +# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# endif +#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ # define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) @@ -209,6 +251,18 @@ # error STM32 F7 chip Family not identified #endif +/* Common to all Advanced (vs Foundation) Family members */ + +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# define STM32F7_NSPDIFRX 0 /* Not supported */ +# define STM32F7_NGPIO 9 /* 9 GPIO ports, GPIOA-I */ +# define STM32F7_NI2C 3 /* I2C1-3 */ +#else +# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */ +# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */ +# define STM32F7_NI2C 4 /* I2C1-4 */ +#endif + /* Common to all Family members */ # define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -219,14 +273,11 @@ # define STM32F7_NUART 4 /* UART 4-5 and 7-8 */ # define STM32F7_NUSART 4 /* USART1-3 and 6 */ # define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */ -# define STM32F7_NI2C 4 /* I2C1-4 */ # define STM32F7_NUSBOTGFS 1 /* USB OTG FS */ # define STM32F7_NUSBOTGHS 1 /* USB OTG HS */ # define STM32F7_NSAI 2 /* SAI1-2 */ -# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */ # define STM32F7_NDMA 2 /* DMA1-2 */ -# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */ -# define STM32F7_NADC 3 /* 12-bit ADC1-3, 24 channels *except V series) */ +# define STM32F7_NADC 3 /* 12-bit ADC1-3, number of channels vary */ # define STM32F7_NDAC 2 /* 12-bit DAC1-2 */ # define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */ # define STM32F7_NCRC 1 /* CRC */ @@ -258,11 +309,17 @@ #else # define STM32F7_NRNG 0 /* No Random number generator (RNG) */ #endif + #if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6) -# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */ -#else +# define STM32F7_NSPI 6 /* SPI1-6 (Advanced Family Except V series) */ +#elif defined(CONFIG_STM32F7_HAVE_SPI5) +# define STM32F7_NSPI 5 /* SPI1-5 (Foundation Family Except V & R series) */ +#elif defined(CONFIG_STM32F7_HAVE_SPI4) # define STM32F7_NSPI 4 /* SPI1-4 V series */ +#else +# define STM32F7_NSPI 3 /* SPI1-3 R series */ #endif + #if defined(CONFIG_STM32F7_HAVE_SDMMC2) # define STM32F7_NSDMMC 2 /* 2 SDMMC interfaces */ #else @@ -270,8 +327,10 @@ #endif #if defined(CONFIG_STM32F7_HAVE_CAN3) # define STM32F7_NCAN 3 /* CAN1-3 */ -#else +#elif defined(CONFIG_STM32F7_HAVE_CAN2) # define STM32F7_NCAN 2 /* CAN1-2 */ +#else +# define STM32F7_NCAN 1 /* CAN1 only */ #endif #if defined(CONFIG_STM32F7_HAVE_DCMI) # define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */ @@ -288,10 +347,10 @@ #else # define STM32F7_NLCDTFT 0 /* No LCD-TFT */ #endif -#if defined(CONFIG_STM32F7_HAVE_DMA2D) -# define STM32F7_NDMA2D 0 /* No DChrom-ART Acceleratorâ„¢ (DMA2D) */ -#else +#if defined(CONFIG_STM32F7_HAVE_DMA2D) /* bf20171107 Swapped defines they were reversed. */ # define STM32F7_NDMA2D 1 /* DChrom-ART Acceleratorâ„¢ (DMA2D) */ +#else +# define STM32F7_NDMA2D 0 /* No DChrom-ART Acceleratorâ„¢ (DMA2D) */ #endif #if defined(CONFIG_STM32F7_HAVE_JPEG) #define STM32F7_NJPEG 1 /* One JPEG Converter */ diff --git a/arch/arm/include/stm32f7/dma2d.h b/arch/arm/include/stm32f7/dma2d.h deleted file mode 100755 index 0ebffb05f500b42aa6b179caac82318a8e42a51e..0000000000000000000000000000000000000000 --- a/arch/arm/include/stm32f7/dma2d.h +++ /dev/null @@ -1,415 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/dma2d.h - * - * Copyright (C) 2015 Marco Krahl. All rights reserved. - * Author: Marco Krahl - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_STM32F7_DMA2D_H -#define __ARCH_ARM_INCLUDE_STM32F7_DMA2D_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -struct ltdc_area_s; /* see arch/chip/ltdc.h */ - -/* Blend mode definitions */ - -enum dma2d_blend_e -{ - DMA2D_BLEND_NONE = 0, /* Disable all blend operation */ - DMA2D_BLEND_ALPHA = 0x1, /* Enable alpha blending */ - DMA2D_BLEND_PIXELALPHA = 0x2, /* Enable alpha blending from pixel color */ -}; - -/* The layer is controlled through the following structure */ - -struct dma2d_layer_s -{ - /* Name: getvideoinfo - * - * Description: - * Get video information about the layer - * - * Parameter: - * layer - Reference to the layer control structure - * vinfo - Reference to the video info structure - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getvideoinfo)(FAR struct dma2d_layer_s *layer, - FAR struct fb_videoinfo_s *vinfo); - - /* Name: getplaneinfo - * - * Description: - * Get plane information about the layer - * - * Parameter: - * layer - Reference to the layer control structure - * planeno - Number of the plane - * pinfo - Reference to the plane info structure - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getplaneinfo)(FAR struct dma2d_layer_s *layer, int planeno, - FAR struct fb_planeinfo_s *pinfo); - - /* Name: getlid - * - * Description: - * Get a specific layer identifier. - * - * Parameter: - * layer - Reference to the layer structure - * lid - Reference to store the layer id - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getlid)(FAR struct dma2d_layer_s *layer, int *lid); - -#ifdef CONFIG_STM32F7_DMA2D_L8 - /* Name: setclut - * - * Description: - * Configure layer clut (color lookup table). - * Non clut is defined during initializing. - * - * Parameter: - * layer - Reference to the layer structure - * cmap - color lookup table with up the 256 entries - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*setclut)(FAR struct dma2d_layer_s *layer, - const FAR struct fb_cmap_s *cmap); - - /* Name: getclut - * - * Description: - * Get configured layer clut (color lookup table). - * - * Parameter: - * layer - Reference to the layer structure - * cmap - Reference to valid color lookup table accept up the 256 color - * entries - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getclut)(FAR struct dma2d_layer_s *layer, FAR struct fb_cmap_s *cmap); -#endif - - /* Name: setalpha - * - * Description: - * Configure layer alpha value factor into blend operation. - * During the layer blend operation the source alpha value is multiplied - * with this alpha value. If the source color format doesn't support alpha - * channel (e.g. non ARGB8888) this alpha value will be used as constant - * alpha value for blend operation. - * Default value during initializing: 0xff - * - * Parameter: - * layer - Reference to the layer structure - * alpha - Alpha value - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*setalpha)(FAR struct dma2d_layer_s *layer, uint8_t alpha); - - /* Name: getalpha - * - * Description: - * Get configured layer alpha value factor for blend operation. - * - * Parameter: - * layer - Reference to the layer structure - * alpha - Reference to store the alpha value - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getalpha)(FAR struct dma2d_layer_s *layer, uint8_t *alpha); - - /* Name: setblendmode - * - * Description: - * Configure blend mode of the layer. - * Default mode during initializing: DMA2D_BLEND_NONE - * Blendmode is active after next update. - * - * Parameter: - * layer - Reference to the layer structure - * mode - Blend mode (see DMA2D_BLEND_*) - * - * Return: - * On success - OK - * On error - -EINVAL - * - * Procedure information: - * DMA2D_BLEND_NONE: - * Informs the driver to disable all blend operation for the given layer. - * That means the layer is opaque. - * - * DMA2D_BLEND_ALPHA: - * Informs the driver to enable alpha blending for the given layer. - * - * DMA2D_BLEND_PIXELALPHA: - * Informs the driver to use the pixel alpha value of the layer instead - * the constant alpha value. This is only useful for ARGB8888 - * color format. - */ - - int (*setblendmode)(FAR struct dma2d_layer_s *layer, uint32_t mode); - - /* Name: getblendmode - * - * Description: - * Get configured blend mode of the layer. - * - * Parameter: - * layer - Reference to the layer structure - * mode - Reference to store the blend mode - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getblendmode)(FAR struct dma2d_layer_s *layer, uint32_t *mode); - - /* Name: blit - * - * Description: - * Copy selected area from a source layer to selected position of the - * destination layer. - * - * Parameter: - * dest - Reference to the destination layer - * destxpos - Selected x target position of the destination layer - * destypos - Selected y target position of the destination layer - * src - Reference to the source layer - * srcarea - Reference to the selected area of the source layer - * - * Return: - * OK - On success - * -EINVAL - If one of the parameter invalid or if the size of the - * selected source area outside the visible area of the - * destination layer. (The visible area usually represents the - * display size) - * -ECANCELED - Operation cancelled, something goes wrong. - */ - - int (*blit)(FAR struct dma2d_layer_s *dest, - fb_coord_t destxpos, fb_coord_t destypos, - FAR const struct dma2d_layer_s *src, - FAR const struct ltdc_area_s *srcarea); - - /* Name: blend - * - * Description: - * Blends the selected area from a background layer with selected position - * of the foreground layer. Copies the result to the selected position of - * the destination layer. Note! The content of the foreground and background - * layer keeps unchanged as long destination layer is unequal to the - * foreground and background layer. - * - * Parameter: - * dest - Reference to the destination layer - * fore - Reference to the foreground layer - * forexpos - Selected x target position of the foreground layer - * foreypos - Selected y target position of the foreground layer - * back - Reference to the background layer - * backarea - Reference to the selected area of the background layer - * - * Return: - * OK - On success - * -EINVAL - If one of the parameter invalid or if the size of the - * selected source area outside the visible area of the - * destination layer. (The visible area usually represents the - * display size) - * -ECANCELED - Operation cancelled, something goes wrong. - */ - - int (*blend)(FAR struct dma2d_layer_s *dest, - fb_coord_t destxpos, fb_coord_t destypos, - FAR const struct dma2d_layer_s *fore, - fb_coord_t forexpos, fb_coord_t foreypos, - FAR const struct dma2d_layer_s *back, - FAR const struct ltdc_area_s *backarea); - - /* Name: fillarea - * - * Description: - * Fill the selected area of the whole layer with a specific color. - * - * Parameter: - * layer - Reference to the layer structure - * area - Reference to the valid area structure select the area - * color - Color to fill the selected area. Color must be formatted - * according to the layer pixel format. - * - * Return: - * OK - On success - * -EINVAL - If one of the parameter invalid or if the size of the - * selected area outside the visible area of the layer. - * -ECANCELED - Operation cancelled, something goes wrong. - */ - - int (*fillarea)(FAR struct dma2d_layer_s *layer, - FAR const struct ltdc_area_s *area, - uint32_t color); -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_dma2dgetlayer - * - * Description: - * Get a dma2d layer structure by the layer identifier - * - * Parameter: - * lid - Layer identifier - * - * Return: - * Reference to the dma2d layer control structure on success or Null if no - * related exist. - * - ****************************************************************************/ - -FAR struct dma2d_layer_s *up_dma2dgetlayer(int lid); - -/**************************************************************************** - * Name: up_dma2dcreatelayer - * - * Description: - * Create a new dma2d layer object to interact with the dma2d controller - * - * Parameter: - * width - Layer width - * height - Layer height - * fmt - Pixel format of the layer - * - * Return: - * On success - A valid dma2d layer reference - * On error - NULL and errno is set to - * -EINVAL if one of the parameter is invalid - * -ENOMEM if no memory available or exceeds - * CONFIG_STM32F7_DMA2D_NLAYERS - * - ****************************************************************************/ - -FAR struct dma2d_layer_s *up_dma2dcreatelayer(fb_coord_t width, - fb_coord_t height, - uint8_t fmt); - -/**************************************************************************** - * Name: up_dma2dremovelayer - * - * Description: - * Remove and deallocate the dma2d layer - * - * Parameter: - * layer - Reference to the layer to remove - * - * Return: - * On success - OK - * On error - -EINVAL - * - ****************************************************************************/ - -int up_dma2dremovelayer(FAR struct dma2d_layer_s *layer); - -/**************************************************************************** - * Name: up_dma2dinitialize - * - * Description: - * Initialize the dma2d controller - * - * Return: - * OK - On success - * An error if initializing failed. - * - ****************************************************************************/ - -int up_dma2dinitialize(void); - -/**************************************************************************** - * Name: up_dma2duninitialize - * - * Description: - * Uninitialize the dma2d controller - * - ****************************************************************************/ - -void up_dma2duninitialize(void); - -#endif /* __ARCH_ARM_INCLUDE_STM32F7_DMA2D_H */ diff --git a/arch/arm/include/stm32f7/irq.h b/arch/arm/include/stm32f7/irq.h index f09659190b74a2f4078b0c0df1f5f31cbcfe2389..19e2596f7d76b9aa5c4ae33a608342f066e3e6cd 100644 --- a/arch/arm/include/stm32f7/irq.h +++ b/arch/arm/include/stm32f7/irq.h @@ -1,8 +1,9 @@ /************************************************************************************ * arch/arm/include/stm32f7/irq.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt + * Bob Feretich * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -76,7 +77,9 @@ #define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# include +#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) # include diff --git a/arch/arm/include/stm32f7/ltdc.h b/arch/arm/include/stm32f7/ltdc.h deleted file mode 100755 index 0b1e509916b9a2b355a18e18d56f76845eab788a..0000000000000000000000000000000000000000 --- a/arch/arm/include/stm32f7/ltdc.h +++ /dev/null @@ -1,575 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/ltdc.h - * - * Copyright (C) 2014-2015 Marco Krahl. All rights reserved. - * Author: Marco Krahl - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_STM32F7_LTDC_H -#define __ARCH_ARM_INCLUDE_STM32F7_LTDC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#ifdef CONFIG_STM32F7_LTDC -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -struct dma2d_layer_s; /* see arch/chip/dma2d.h */ - -/* Blend mode definitions */ - -enum ltdc_blend_e -{ - LTDC_BLEND_NONE = 0, /* Disable all blend operation */ - LTDC_BLEND_ALPHA = 0x1, /* Enable alpha blending */ - LTDC_BLEND_PIXELALPHA = 0x2, /* Enable alpha blending from pixel color */ - LTDC_BLEND_COLORKEY = 0x4, /* Enable colorkey */ - LTDC_BLEND_ALPHAINV = 0x8, /* Inverse alpha blending of source */ - LTDC_BLEND_PIXELALPHAINV = 0x10 /* Invers pixel alpha blending of source */ -}; - -/* layer control definitions */ - -enum ltdc_layer_e -{ - LTDC_LAYER_OWN = 0, /* The given layer */ - LTDC_LAYER_TOP = 0x1, /* The initialized top layer */ - LTDC_LAYER_BOTTOM = 0x2, /* the initialized bottom layer */ - LTDC_LAYER_ACTIVE = 0x4, /* The current visible flip layer */ - LTDC_LAYER_INACTIVE = 0x8 /* The current invisible flip layer */ -#ifdef CONFIG_STM32F7_DMA2D - ,LTDC_LAYER_DMA2D = 0x10 /* The dma2d interface layer id */ -#endif -}; - -/* Update operation flag */ - -enum ltdc_update_e -{ - LTDC_UPDATE_NONE = 0, /* Update given layer only */ - LTDC_UPDATE_SIM = 0x1, /* Update both layer simultaneous */ - LTDC_UPDATE_FLIP = 0x2, /* Perform flip operation */ - LTDC_UPDATE_ACTIVATE = 0x4 /* Set the given layer to the active layer */ -}; - -/* sync mode definitions */ - -enum ltdc_sync_e -{ - LTDC_SYNC_NONE = 0, /* Immediately */ - LTDC_SYNC_VBLANK = 0x100, /* Upon vertical sync */ - LTDC_SYNC_WAIT = 0x200 /* Waits upon vertical sync */ -}; - -/* Definition of the visible layer position and size */ - -struct ltdc_area_s -{ - fb_coord_t xpos; /* X position in pixel */ - fb_coord_t ypos; /* Y position in pixel */ - fb_coord_t xres; /* X resolution in pixel */ - fb_coord_t yres; /* Y resolution in pixel */ -}; - -/* The layer is controlled through the following structure */ - -struct ltdc_layer_s -{ - /* Name: getvideoinfo - * - * Description: - * Get video information about the layer - * - * Parameter: - * layer - Reference to the layer control structure - * vinfo - Reference to the video info structure - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getvideoinfo)(FAR struct ltdc_layer_s *layer, - FAR struct fb_videoinfo_s *vinfo); - - /* Name: getplaneinfo - * - * Description: - * Get plane information about the layer - * - * Parameter: - * layer - Reference to the layer control structure - * planeno - Number of the plane - * pinfo - Reference to the plane info structure - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getplaneinfo)(FAR struct ltdc_layer_s *layer, int planeno, - FAR struct fb_planeinfo_s *pinfo); - - /* Name: getlid - * - * Description: - * Get a specific layer identifier. - * - * Parameter: - * layer - Reference to the layer structure - * lid - Reference to store the layer id - * flag - Operation flag describe the layer identifier - * e.g. get the current active or inactive layer. - * See LTDC_LAYER_* for possible values - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getlid)(FAR struct ltdc_layer_s *layer, int *lid, uint32_t flag); - -#ifdef CONFIG_FB_CMAP - /* Name: setclut - * - * Description: - * Configure layer clut (color lookup table). - * Non clut is defined during initializing. - * Clut is active during next vertical blank period. Do not need an update. - * - * Parameter: - * layer - Reference to the layer structure - * cmap - color lookup table with up the 256 entries - * enable - Enable or disable clut support (if false cmap is ignored and can - * be NULL) - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*setclut)(FAR struct ltdc_layer_s *layer, - const FAR struct fb_cmap_s *cmap); - - /* Name: getclut - * - * Description: - * Get configured layer clut (color lookup table). - * - * Parameter: - * layer - Reference to the layer structure - * cmap - Reference to valid color lookup table accept up the 256 color - * entries - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getclut)(FAR struct ltdc_layer_s *layer, FAR struct fb_cmap_s *cmap); -#endif - - /* Name: setcolor - * - * Description: - * Configure layer color for the non active layer area. - * Default value during initializing: 0x00000000 - * Color is active after next update. - * - * Parameter: - * layer - Reference to the layer structure - * argb - ARGB8888 color value - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*setcolor)(FAR struct ltdc_layer_s *layer, uint32_t argb); - - /* Name: getcolor - * - * Description: - * Get configured layer color for the non active layer area. - * - * Parameter: - * layer - Reference to the layer structure - * argb - Reference to store the ARGB8888 color value - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getcolor)(FAR struct ltdc_layer_s *layer, uint32_t *argb); - - /* Name: setcolorkey - * - * Description: - * Configure the layer color key (chromakey) for transparence. - * Default value during initializing: 0x00000000 - * Colorkey is active after next update. - * - * Parameter: - * layer - Reference to the layer structure - * rgb - RGB888 color key - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*setcolorkey)(FAR struct ltdc_layer_s *layer, uint32_t rgb); - - /* Name: getcolorkey - * - * Description: - * Get the configured layer color key (chromakey) for transparence. - * - * Parameter: - * layer - Reference to the layer structure - * rgb - Reference to store the RGB888 color key - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getcolorkey)(FAR struct ltdc_layer_s *layer, uint32_t *rgb); - - /* Name: setalpha - * - * Description: - * Configure layer alpha value factor into blend operation. - * During the layer blend operation the source alpha value is multiplied - * with this alpha value. If the source color format doesn't support alpha - * channel (e.g. non ARGB8888) this alpha value will be used as constant - * alpha value for blend operation. - * Default value during initializing: 0xff - * Alpha is active after next update. - * - * Parameter: - * layer - Reference to the layer structure - * alpha - Alpha value - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*setalpha)(FAR struct ltdc_layer_s *layer, uint8_t alpha); - - /* Name: getalpha - * - * Description: - * Get configured layer alpha value factor for blend operation. - * - * Parameter: - * layer - Reference to the layer structure - * alpha - Reference to store the alpha value - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getalpha)(FAR struct ltdc_layer_s *layer, uint8_t *alpha); - - /* Name: setblendmode - * - * Description: - * Configure blend mode of the layer. - * Default mode during initializing: LTDC_BLEND_NONE - * Blendmode is active after next update. - * - * Parameter: - * layer - Reference to the layer structure - * mode - Blend mode (see LTDC_BLEND_*) - * - * Return: - * On success - OK - * On error - -EINVAL - * - * Procedure information: - * LTDC_BLEND_NONE: - * Informs the driver to disable all blend operation for the given layer. - * That means the layer is opaque. Note this has no effect on the - * colorkey settings. - * - * LTDC_BLEND_ALPHA: - * Informs the driver to enable alpha blending for the given layer. - * - * LTDC_BLEND_COLORKEY: - * Informs the driver to enable colorkeying for the given layer. - * - * LTDC_BLEND_SRCPIXELALPHA: - * Informs the driver to use the pixel alpha value of the layer instead - * the constant alpha value. This is only useful for ARGB8888 - * color format. - * - * LTDC_BLEND_DESTPIXELALPHA: - * Informs the driver to use the pixel alpha value of the subjacent layer - * instead the constant alpha value. This is only useful for ARGB8888 - * color format. - */ - - int (*setblendmode)(FAR struct ltdc_layer_s *layer, uint32_t mode); - - /* Name: getblendmode - * - * Description: - * Get configured blend mode of the layer. - * - * Parameter: - * layer - Reference to the layer structure - * mode - Reference to store the blend mode - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getblendmode)(FAR struct ltdc_layer_s *layer, uint32_t *mode); - - /* Name: setarea - * - * Description: - * Configure visible layer area and the reference position of the first - * pixel of the whole layer which is the first visible top left pixel in - * the active area. - * Default value during initializing: - * xpos = 0 - * ypos = 0 - * xres = display x resolution - * yres = display y resolution - * - * Area is active after next update. - * - * Parameter: - * layer - Reference to the layer control structure - * area - Reference to the valid area structure for the new active area - * srcxpos - x position of the visible pixel of the whole layer - * srcypos - y position of the visible pixel of the whole layer - * - * Return: - * On success - OK - * On error - -EINVAL - * - * Procedure Information: - * If the srcxpos and srcypos unequal the xpos and ypos of the coord - * structure this acts like moving the visible area to another position on - * the screen during the next update operation. - */ - - int (*setarea)(FAR struct ltdc_layer_s *layer, - FAR const struct ltdc_area_s *area, - fb_coord_t srcxpos, - fb_coord_t srcypos); - - /* Name: getarea - * - * Description: - * Get configured visible layer area. - * - * Parameter: - * layer - Reference to the layer control structure - * area - Reference to the area structure to store the active area - * srcxpos - Reference to store the referenced x position of the whole layer - * srcypos - Reference to store the reterenced y position of the whole layer - * - * Return: - * On success - OK - * On error - -EINVAL - */ - - int (*getarea)(FAR struct ltdc_layer_s *layer, - FAR struct ltdc_area_s *area, - fb_coord_t *srcxpos, - fb_coord_t *srcypos); - - /* Name: update - * - * Description: - * Update current layer settings and make changes visible. - * - * Parameter: - * layer - Reference to the layer structure - * mode - operation mode (see LTDC_UPDATE_*) - * - * Return: - * OK - On success - * -EINVAL - If one of the parameter invalid - * -ECANCELED - Operation cancelled, something goes wrong - * - * Procedure information: - * LTDC_UPDATE_SIM: - * Informs the driver to update both ltdc layers simultaneously. Otherwise - * update the given layer only. - * - * LTDC_UPDATE_FLIP: - * Informs the driver to perform a flip operation. - * This only effects the ltdc layer 1 and 2 and can be useful for double - * buffering. Each flip operation changed the active layer ot the inactive - * and vice versa. In the context of the ltdc that means, the inactive layer - * is complete disabled. So the subjacent layer is the background layer - * (background color). To reactivate both layer and their settings perform - * an update without LTDC_UPDATE_FLIP flag. - * - * LTDC_UPDATE_ACTIVATE: - * Informs the driver that the given layer should be the active layer when - * the operation is complete. - * - * LTDC_SYNC_VBLANK: - * Informs the driver to update the layer upon vertical blank. Otherwise - * immediately. - */ - - int (*update)(FAR struct ltdc_layer_s *layer, uint32_t mode); - -#ifdef CONFIG_STM32F7_DMA2D - /* Name: blit - * - * Description: - * Copy selected area from a source layer to selected position of the - * destination layer. - * - * Parameter: - * dest - Reference to the destination layer - * destxpos - Selected x position of the destination layer - * destypos - Selected y position of the destination layer - * src - Reference to the source layer - * srcarea - Reference to the selected area of the source layer - * - * Return: - * OK - On success - * -EINVAL - If one of the parameter invalid or if the size of the selected - * source area outside the visible area of the destination layer. - * (The visible area usually represents the display size) - */ - - int (*blit)(FAR struct ltdc_layer_s *dest, - fb_coord_t destxpos, fb_coord_t destypos, - FAR const struct dma2d_layer_s *src, - FAR const struct ltdc_area_s *srcarea); - - /* Name: blend - * - * Description: - * Blends the selected area from a foreground layer with selected position - * of the background layer. Copy the result to the destination layer. Note! - * The content of the foreground and background layer is not changed. - * - * Parameter: - * dest - Reference to the destination layer - * destxpos - Selected x position of the destination layer - * destypos - Selected y position of the destination layer - * fore - Reference to the foreground layer - * forexpos - Selected x position of the foreground layer - * foreypos - Selected y position of the foreground layer - * back - Reference to the background layer - * backarea - Reference to the selected area of the background layer - * - * Return: - * OK - On success - * -EINVAL - If one of the parameter invalid or if the size of the selected - * source area outside the visible area of the destination layer. - * (The visible area usually represents the display size) - */ - - int (*blend)(FAR struct ltdc_layer_s *dest, - fb_coord_t destxpos, fb_coord_t destypos, - FAR const struct dma2d_layer_s *fore, - fb_coord_t forexpos, fb_coord_t foreypos, - FAR const struct dma2d_layer_s *back, - FAR const struct ltdc_area_s *backarea); - - /* Name: fillarea - * - * Description: - * Fill the selected area of the whole layer with a specific color. - * - * Parameter: - * layer - Reference to the layer structure - * area - Reference to the valid area structure select the area - * color - Color to fill the selected area. Color must be formatted - * according to the layer pixel format. - * - * Return: - * OK - On success - * -EINVAL - If one of the parameter invalid or if the size of the selected - * area outside the visible area of the layer. - */ - - int (*fillarea)(FAR struct ltdc_layer_s *layer, - FAR const struct ltdc_area_s *area, - uint32_t color); -#endif -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_ltdcgetlayer - * - * Description: - * Get the ltdc layer structure to perform hardware layer operation - * - * Parameter: - * lid - Layer identifier - * - * Return: - * Reference to the layer control structure on success or Null if parameter - * invalid. - * - ****************************************************************************/ - -FAR struct ltdc_layer_s *up_ltdcgetlayer(int lid); - -#endif /* CONFIG_STM32F7_LTDC */ -#endif /* __ARCH_ARM_INCLUDE_STM32F7_LTDC_H */ - diff --git a/arch/arm/include/stm32f7/stm32f72xx73xx_irq.h b/arch/arm/include/stm32f7/stm32f72xx73xx_irq.h new file mode 100644 index 0000000000000000000000000000000000000000..f1ff50d49e8aab132920fd7fb7a3926eed34aa6d --- /dev/null +++ b/arch/arm/include/stm32f7/stm32f72xx73xx_irq.h @@ -0,0 +1,198 @@ +/**************************************************************************************************** + * arch/arm/include/stm32f7/stm32f72xx73xx_irq.h.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *Change Record: + * bf20171107 Created file. It's identical to stm32f74xx75xx_irq except for the + * exclusions noted by this tag, and the addition of the last IRQ + * for SDMMC2 (IRQ103). + ****************************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through arch/irq.h */ + +#ifndef __ARCH_ARM_INCLUDE_STM32F7_STM32F72XX73XX_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F7_STM32F72XX73XX_IRQ_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in the + * NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables. + * + * Processor Exceptions (vectors 0-15). These common definitions can be found in the file + * nuttx/arch/arm/include/stm32f7/irq.h which includes this file + * + * External interrupts (vectors >= 16) + */ + +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */ +#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */ +#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */ +#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */ +#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */ +#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */ +#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */ +#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */ +#define STM32_IRQ_FMC (STM32_IRQ_FIRST+48) /* 48: FMC global interrupt */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */ +#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */ +#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */ +#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */ +#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */ + +#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */ +#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */ +#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */ +#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */ +#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */ +#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */ +#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */ +#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */ + +#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */ +#define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 global interrupt */ +#define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 global interrupt */ +#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */ +#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 global interrupt */ + +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 global interrupt */ + +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 global interrupt */ +#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI global interrupt */ +#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST+93) /* 93: LP Timer1 global interrupt */ + +#define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST+103) /* 103: SDMMC2 global interrupt */ +#define NR_INTERRUPTS 103 + +#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS) + +/* EXTI interrupts (Do not use IRQ numbers) */ + +#define NR_IRQS NR_VECTORS + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************************************** + * Public Functions + ****************************************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_STM32F7_STM32F72XX73XX_IRQ_H */ + diff --git a/arch/arm/include/xmc4/xmc4500_irq.h b/arch/arm/include/xmc4/xmc4500_irq.h index b35a1b3f8a2c0fa7ce9d9b95c8e6c9a1fd20af40..556af564224f099e361560407e83adc2cab1e077 100644 --- a/arch/arm/include/xmc4/xmc4500_irq.h +++ b/arch/arm/include/xmc4/xmc4500_irq.h @@ -171,12 +171,12 @@ #define XMC4_IRQ_USIC1_SR3 (XMC4_IRQ_FIRST+93) /* 93: USIC1 Channel, SR3 */ #define XMC4_IRQ_USIC1_SR4 (XMC4_IRQ_FIRST+94) /* 94: USIC1 Channel, SR4 */ #define XMC4_IRQ_USIC1_SR5 (XMC4_IRQ_FIRST+95) /* 95: USIC1 Channel, SR5 */ -#define XMC4_IRQ_USIC2_SR0 (XMC4_IRQ_FIRST+96) /* 96: USIC1 Channel, SR0 */ -#define XMC4_IRQ_USIC2_SR1 (XMC4_IRQ_FIRST+97) /* 97: USIC1 Channel, SR1 */ -#define XMC4_IRQ_USIC2_SR2 (XMC4_IRQ_FIRST+98) /* 98: USIC1 Channel, SR2 */ -#define XMC4_IRQ_USIC2_SR3 (XMC4_IRQ_FIRST+99) /* 99: USIC1 Channel, SR3 */ -#define XMC4_IRQ_USIC2_SR4 (XMC4_IRQ_FIRST+100) /* 100: USIC1 Channel, SR4 */ -#define XMC4_IRQ_USIC2_SR5 (XMC4_IRQ_FIRST+101) /* 101: USIC1 Channel, SR5 */ +#define XMC4_IRQ_USIC2_SR0 (XMC4_IRQ_FIRST+96) /* 96: USIC2 Channel, SR0 */ +#define XMC4_IRQ_USIC2_SR1 (XMC4_IRQ_FIRST+97) /* 97: USIC2 Channel, SR1 */ +#define XMC4_IRQ_USIC2_SR2 (XMC4_IRQ_FIRST+98) /* 98: USIC2 Channel, SR2 */ +#define XMC4_IRQ_USIC2_SR3 (XMC4_IRQ_FIRST+99) /* 99: USIC2 Channel, SR3 */ +#define XMC4_IRQ_USIC2_SR4 (XMC4_IRQ_FIRST+100) /* 100: USIC2 Channel, SR4 */ +#define XMC4_IRQ_USIC2_SR5 (XMC4_IRQ_FIRST+101) /* 101: USIC2 Channel, SR5 */ #define XMC4_IRQ_LEDTS0_SR0 (XMC4_IRQ_FIRST+102) /* 102: LEDTS0, SR0 */ #define XMC4_IRQ_RESVD103 (XMC4_IRQ_FIRST+103) /* 103: Reserved */ #define XMC4_IRQ_FCR_SR0 (XMC4_IRQ_FIRST+104) /* 102: FCE, SR0 */ diff --git a/arch/arm/src/a1x/a1x_boot.c b/arch/arm/src/a1x/a1x_boot.c index b7ceee33f74412dcdfa95520c6b0ec03db999e15..1dc27fd636520bc0cc3214c363b84cd3b64907c9 100644 --- a/arch/arm/src/a1x/a1x_boot.c +++ b/arch/arm/src/a1x/a1x_boot.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/a1x/a1x_boot.c * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -46,8 +46,6 @@ # include #endif -#include - #include "chip.h" #include "arm.h" #include "mmu.h" @@ -56,6 +54,7 @@ #include "up_arch.h" #include "a1x_lowputc.h" +#include "a1x_boot.h" /**************************************************************************** * Pre-processor Definitions @@ -76,10 +75,6 @@ # error High vector remap cannot be performed if we are using a ROM page table #endif -/**************************************************************************** - * Private Types - ****************************************************************************/ - /**************************************************************************** * Public Data ****************************************************************************/ diff --git a/arch/arm/src/a1x/a1x_boot.h b/arch/arm/src/a1x/a1x_boot.h new file mode 100644 index 0000000000000000000000000000000000000000..49b226eec970991eeae8c3190ad4843c2e2be356 --- /dev/null +++ b/arch/arm/src/a1x/a1x_boot.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/a1x/a1x_boot.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_A1X_A1X_BOOT_H +#define __ARCH_ARM_SRC_A1X_A1X_BOOT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: a1x_boardinitialize + * + * Description: + * All A1x architectures must provide the following entry point. This entry + * point is called early in the initialization -- after clocking and memory have + * been configured but before caches have been enabled and before any devices have + * been initialized. + * + ************************************************************************************/ + +void a1x_boardinitialize(void); + +#endif /* __ARCH_ARM_SRC_A1X_A1X_BOOT_H */ diff --git a/arch/arm/src/arm/up_cache.S b/arch/arm/src/arm/up_cache.S index e03099ce04fc38676b3557295c37bbefe7da81d3..564df7553423d9224ea8d085e867a4ef0c0d5e4c 100644 --- a/arch/arm/src/arm/up_cache.S +++ b/arch/arm/src/arm/up_cache.S @@ -154,12 +154,12 @@ cp15_invalidate_icache: cp15_invalidate_dcache: bic r0, r0, #CACHE_DLINESIZE - 1 - mcr p15, 0, r0, c7, c6, 1 /* Invalidate D entry */ +1: mcr p15, 0, r0, c7, c6, 1 /* Invalidate D entry */ add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b mov pc, lr - .size cp15_flush_idcache, .-cp15_flush_idcache + .size cp15_invalidate_dcache, .-cp15_invalidate_dcache #if 0 /* Not used */ /* Invalidate Dcache */ diff --git a/arch/arm/src/common/up_modifyreg16.c b/arch/arm/src/common/up_modifyreg16.c index 8871d7f60c0581a2ca8db6a14053df14ac1aa0b0..796732093e3982865634aa899ee5770ccbf37103 100644 --- a/arch/arm/src/common/up_modifyreg16.c +++ b/arch/arm/src/common/up_modifyreg16.c @@ -64,10 +64,10 @@ void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits) irqstate_t flags; uint16_t regval; - flags = enter_critical_section(); + flags = spin_lock_irqsave(); regval = getreg16(addr); regval &= ~clearbits; regval |= setbits; putreg16(regval, addr); - leave_critical_section(flags); + spin_unlock_irqrestore(flags); } diff --git a/arch/arm/src/common/up_modifyreg32.c b/arch/arm/src/common/up_modifyreg32.c index 0a1619592b5953dee261b1bdda91cd53f1ad3ec1..c49cdfa425a6a93b2021ccb8e944c5f1475ab4a1 100644 --- a/arch/arm/src/common/up_modifyreg32.c +++ b/arch/arm/src/common/up_modifyreg32.c @@ -64,10 +64,10 @@ void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) irqstate_t flags; uint32_t regval; - flags = enter_critical_section(); + flags = spin_lock_irqsave(); regval = getreg32(addr); regval &= ~clearbits; regval |= setbits; putreg32(regval, addr); - leave_critical_section(flags); + spin_unlock_irqrestore(flags); } diff --git a/arch/arm/src/common/up_modifyreg8.c b/arch/arm/src/common/up_modifyreg8.c index abc4b60885c29a58f58f4df382f4469c821aed32..b67cbdc028cae0a3bdbaa734687650c30dcc1b64 100644 --- a/arch/arm/src/common/up_modifyreg8.c +++ b/arch/arm/src/common/up_modifyreg8.c @@ -64,10 +64,10 @@ void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) irqstate_t flags; uint8_t regval; - flags = enter_critical_section(); + flags = spin_lock_irqsave(); regval = getreg8(addr); regval &= ~clearbits; regval |= setbits; putreg8(regval, addr); - leave_critical_section(flags); + spin_unlock_irqrestore(flags); } diff --git a/arch/arm/src/efm32/Kconfig b/arch/arm/src/efm32/Kconfig index 877cca10740d2309d6d0830c87e6d79f490e2eb9..8cfba344fcf1fea02729ce43fab3f70961a83fce 100644 --- a/arch/arm/src/efm32/Kconfig +++ b/arch/arm/src/efm32/Kconfig @@ -135,6 +135,7 @@ config EFM32_RMU config EFM32_FLASHPROG bool "Enable Erase/Write flash function (MSC) " default n + select ARCH_HAVE_PROGMEM select ARCH_HAVE_RAMFUNCS config EFM32_RMU_DEBUG diff --git a/arch/arm/src/kinetis/kinetis_start.c b/arch/arm/src/kinetis/kinetis_start.c index 41df37aa4dc74d8de1f855719eb6ddc7b9159424..3c094ca3020c6edf55798b78edfaf17fa23829a6 100644 --- a/arch/arm/src/kinetis/kinetis_start.c +++ b/arch/arm/src/kinetis/kinetis_start.c @@ -44,7 +44,6 @@ #include #include -#include #include "up_arch.h" #include "up_internal.h" @@ -58,6 +57,8 @@ # include "nvic.h" #endif +#include "kinetis_start.h" + /**************************************************************************** * Private Function prototypes ****************************************************************************/ diff --git a/arch/arm/src/kinetis/kinetis_start.h b/arch/arm/src/kinetis/kinetis_start.h new file mode 100644 index 0000000000000000000000000000000000000000..850fbd4341411549415f26fc07ed93b1c05c4cad --- /dev/null +++ b/arch/arm/src/kinetis/kinetis_start.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/kinetis/kinetis_start.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_START_H +#define __ARCH_ARM_SRC_KINETIS_KINETIS_START_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: kinetis_boardinitialize + * + * Description: + * All Kinetis architectures must provide the following entry point. This entry + * point is called early in the initialization -- after clocking and memory have + * been configured but before caches have been enabled and before any devices have + * been initialized. + * + ************************************************************************************/ + +void kinetis_boardinitialize(void); + +#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_START_H */ diff --git a/arch/arm/src/kl/kl_start.c b/arch/arm/src/kl/kl_start.c index 6e9970517f57854eb7cc18986237dccbd6bd50b7..5244365a2aae86aa1a0bc047819a9a820c11f5bf 100644 --- a/arch/arm/src/kl/kl_start.c +++ b/arch/arm/src/kl/kl_start.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/kl/kl_start.c * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -44,7 +44,6 @@ #include #include -#include #include "up_arch.h" #include "up_internal.h" @@ -56,6 +55,7 @@ #include "kl_lowputc.h" #include "kl_userspace.h" #include "kl_clockconfig.h" +#include "kl_start.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/kl/kl_start.h b/arch/arm/src/kl/kl_start.h new file mode 100644 index 0000000000000000000000000000000000000000..fb26e5b3222f13b3de28b150923e057c0881618c --- /dev/null +++ b/arch/arm/src/kl/kl_start.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/kl/kl_start.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KL_KL_START_H +#define __ARCH_ARM_SRC_KL_KL_START_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: kl_boardinitialize + * + * Description: + * All Kinetis L architectures must provide the following entry point. This entry + * point is called early in the initialization -- after clocking and memory have + * been configured but before caches have been enabled and before any devices have + * been initialized. + * + ************************************************************************************/ + +void kl_boardinitialize(void); + +#endif /* __ARCH_ARM_SRC_KL_KL_START_H */ diff --git a/arch/arm/src/lc823450/Kconfig b/arch/arm/src/lc823450/Kconfig index 7866de57f69dbb489746980c8d3590e251c3435b..f616cbdfca9dcbe81c8f265ea9f815638b6cb5fa 100644 --- a/arch/arm/src/lc823450/Kconfig +++ b/arch/arm/src/lc823450/Kconfig @@ -7,6 +7,10 @@ comment "LC823450 Configuration Options" menu "LC823450 Peripheral Support" +config LC823450_IPL2 + bool "IPL2" + default n + config LC823450_UART0 bool "UART0" select UART0_SERIALDRIVER @@ -125,6 +129,14 @@ config MTD_CONFIG_DEVPATH string "Device path for config" default "/dev/mtdblock0p2" +config MTD_RECOVERY_DEVPATH + string "Device path for recovery" + default "/dev/mtdblock0p3" + +config MTD_KERNEL_DEVPATH + string "Device path for kernel" + default "/dev/mtdblock0p4" + config MTD_ETC_DEVPATH string "Device path for etc" default "/dev/mtdblock0p5" @@ -173,6 +185,11 @@ config LC823450_I2C1 default n depends on I2C +config LC823450_I2S0 + bool "I2S0" + default n + depends on I2S + config LC823450_SPI_DMA bool "DMA for SPI" default n @@ -213,7 +230,7 @@ config LC823450_USBDEV_CUSTOM_HSDSEL_10 endchoice config LC823450_LSISTBY - bool "LIS Standby" + bool "LSI Standby" default n config LC823450_MTM0_TICK @@ -229,4 +246,8 @@ config HRT_TIMER bool "High resolution timer" default n +config DVFS + bool "Dynamic Voltage and Frequencey Scaling" + default n + endmenu diff --git a/arch/arm/src/lc823450/Make.defs b/arch/arm/src/lc823450/Make.defs index dca20b04c0a1af817cc9bda20e6f554f47cb7745..58905083caa22af5e3fb295336180ec8b7124ee2 100644 --- a/arch/arm/src/lc823450/Make.defs +++ b/arch/arm/src/lc823450/Make.defs @@ -137,8 +137,8 @@ ifeq ($(CONFIG_ADC),y) CHIP_CSRCS += lc823450_adc.c endif -ifeq ($(CONFIG_IPL2),y) -ifeq ($(CONFIG_SPIFLASH_BOOT),y) +ifeq ($(CONFIG_LC823450_IPL2),y) +ifeq ($(CONFIG_LC823450_SPIFLASH_BOOT),y) CHIP_CSRCS += lc823450_spif_ipl2.c else CHIP_CSRCS += lc823450_ipl2.c @@ -146,7 +146,8 @@ endif endif ifeq ($(CONFIG_DVFS),y) -CHIP_CSRCS += lc823450_dvfs.c +CHIP_CSRCS += lc823450_dvfs2.c +CHIP_CSRCS += lc823450_procfs_dvfs.c endif ifeq ($(CONFIG_PM),y) @@ -181,3 +182,7 @@ ifeq ($(CONFIG_LC823450_MTD),y) CHIP_CSRCS += lc823450_mtd.c CHIP_CSRCS += lc823450_mmcl.c endif + +ifeq ($(CONFIG_LC823450_I2S0),y) +CHIP_CSRCS += lc823450_i2s.c +endif diff --git a/arch/arm/src/lc823450/lc823450_clockconfig.c b/arch/arm/src/lc823450/lc823450_clockconfig.c index 916eac8627cd7b515b6cb0270f89a4e5daeb6a6b..e2c0d8b6b5f37f2369d8a111831b38bc7b1336d4 100644 --- a/arch/arm/src/lc823450/lc823450_clockconfig.c +++ b/arch/arm/src/lc823450/lc823450_clockconfig.c @@ -141,7 +141,7 @@ void lc823450_clockconfig() val |= OSCCNT_SCKSEL_MAIN; putreg32(val, OSCCNT); -#ifdef CONFIG_IPL2 +#ifdef CONFIG_LC823450_IPL2 /* set the common PLL values */ /* XTAL / XT1OSC_CLK = 1MHz */ diff --git a/arch/arm/src/lc823450/lc823450_cpupause.c b/arch/arm/src/lc823450/lc823450_cpupause.c index a8f663e6d886cc44aed8b35738908a90365d9ce0..10b4a0baf25dfd39feda25de376d5a2a87136862 100644 --- a/arch/arm/src/lc823450/lc823450_cpupause.c +++ b/arch/arm/src/lc823450/lc823450_cpupause.c @@ -185,9 +185,6 @@ int up_cpu_paused(int cpu) up_restorestate(tcb->xcp.regs); - /* FIXME */ - up_udelay(500); - spin_unlock(&g_cpu_wait[cpu]); return OK; diff --git a/arch/arm/src/lc823450/lc823450_dma.c b/arch/arm/src/lc823450/lc823450_dma.c index 104c1d2ac6d3a19d7da2090671d49dc5e7f34893..b228f706d54f25f36316fef077f60119a90fd41d 100644 --- a/arch/arm/src/lc823450/lc823450_dma.c +++ b/arch/arm/src/lc823450/lc823450_dma.c @@ -150,9 +150,11 @@ static int dma_interrupt_core(void *context) struct lc823450_phydmach_s *pdmach; struct lc823450_dmach_s *dmach; sq_entry_t *q_ent; + irqstate_t flags; pdmach = (struct lc823450_phydmach_s *)context; + flags = spin_lock_irqsave(); q_ent = pdmach->req_q.tail; DEBUGASSERT(q_ent); dmach = (struct lc823450_dmach_s *)q_ent; @@ -160,11 +162,17 @@ static int dma_interrupt_core(void *context) if (dmach->nxfrs == 0) { /* finish one transfer */ + sq_remlast(&pdmach->req_q); + spin_unlock_irqrestore(flags); if (dmach->callback) dmach->callback((DMA_HANDLE)dmach, dmach->arg, 0); } + else + { + spin_unlock_irqrestore(flags); + } up_disable_clk(LC823450_CLOCK_DMA); phydmastart(pdmach); @@ -218,14 +226,14 @@ static int phydmastart(struct lc823450_phydmach_s *pdmach) struct lc823450_dmach_s *dmach; sq_entry_t *q_ent; - flags = enter_critical_section(); + flags = spin_lock_irqsave(); q_ent = pdmach->req_q.tail; if (!q_ent) { pdmach->inprogress = 0; - leave_critical_section(flags); + spin_unlock_irqrestore(flags); return 0; } @@ -288,7 +296,7 @@ static int phydmastart(struct lc823450_phydmach_s *pdmach) modifyreg32(DMACCFG(dmach->chn), 0, DMACCFG_ITC | DMACCFG_E); - leave_critical_section(flags); + spin_unlock_irqrestore(flags); return 0; } @@ -614,7 +622,7 @@ int lc823450_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg) /* select physical channel */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(); sq_addfirst(&dmach->q_ent, &g_dma.phydmach[dmach->chn].req_q); @@ -628,7 +636,7 @@ int lc823450_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg) phydmastart(&g_dma.phydmach[dmach->chn]); } - leave_critical_section(flags); + spin_unlock_irqrestore(flags); return OK; } @@ -645,7 +653,7 @@ void lc823450_dmastop(DMA_HANDLE handle) DEBUGASSERT(dmach); - flags = enter_critical_section(); + flags = spin_lock_irqsave(); modifyreg32(DMACCFG(dmach->chn), DMACCFG_ITC | DMACCFG_E, 0); @@ -660,6 +668,6 @@ void lc823450_dmastop(DMA_HANDLE handle) sq_rem(&dmach->q_ent, &pdmach->req_q); } - leave_critical_section(flags); + spin_unlock_irqrestore(flags); return; } diff --git a/arch/arm/src/lc823450/lc823450_dvfs2.c b/arch/arm/src/lc823450/lc823450_dvfs2.c new file mode 100644 index 0000000000000000000000000000000000000000..2bc8855f516fc2c8a13cb11171cce262dd9b133f --- /dev/null +++ b/arch/arm/src/lc823450/lc823450_dvfs2.c @@ -0,0 +1,429 @@ +/**************************************************************************** + * arch/arm/src/lc823450/lc823450_dvfs2.c + * + * Copyright (C) 2015-2017 Sony Corporation. All rights reserved. + * Author: Masayuki Ishikawa + * Author: Masatoshi Tateishi + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "up_arch.h" + +#include "lc823450_clockconfig.h" +#include "lc823450_syscontrol.h" +#include "lc823450_intc.h" +#include "lc823450_sdc.h" +#include "lc823450_dvfs2.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define FREQ_160 0 +#define FREQ_080 1 +#define FREQ_040 2 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +typedef struct freq_entry +{ + uint16_t freq; + uint16_t pll1; + uint16_t mdiv; + uint16_t hdiv; +} t_freq_entry; + +static struct freq_entry _dvfs_act_tbl[3] = +{ + { 160, OSCCNT_MCSEL, OSCCNT_MAINDIV_1, 3}, /* PLL1 */ + { 80, OSCCNT_MCSEL, OSCCNT_MAINDIV_2, 1}, /* PLL1 */ + { 40, OSCCNT_MCSEL, OSCCNT_MAINDIV_4, 0}, /* PLL1 */ +}; + +static struct freq_entry _dvfs_idl_tbl[3] = +{ + { 24, 0, OSCCNT_MAINDIV_1, 0}, /* XT1 */ + { 12, 0, OSCCNT_MAINDIV_2, 0}, /* XT1 */ + { 6, 0, OSCCNT_MAINDIV_4, 0}, /* XT1 */ +}; + +static uint16_t _dvfs_cur_idx = 0; /* current speed index */ +static uint16_t _dvfs_cur_hdiv = 3; +static uint16_t _dvfs_cur_mdiv = OSCCNT_MAINDIV_1; + +#if 0 +static uint16_t _dvfs_init_timeout = (5 * 100); /* in ticks */ +#endif + +#if defined(CONFIG_SMP) && (CONFIG_SMP_NCPUS == 2) +static uint8_t _dvfs_cpu_is_active[CONFIG_SMP_NCPUS]; +#endif + +static void lc823450_dvfs_set_div(int idx, int tbl); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +int8_t g_dvfs_enabled = 0; +uint16_t g_dvfs_cur_freq = 160; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lc823450_dvfs_update_lpm + ****************************************************************************/ + +static void lc823450_dvfs_update_lpm(int freq) +{ + /* TODO */ +} + +#if defined(CONFIG_SMP) && (CONFIG_SMP_NCPUS == 2) +static int _dvfs_another_cpu_state(int me) +{ + if (0 == me) + { + return _dvfs_cpu_is_active[1]; + } + else + { + return _dvfs_cpu_is_active[0]; + } +} +#endif + +/**************************************************************************** + * Name: lc823450_dvfs_set_div + * Set dividers in the OSC block + * target tbl: 0=active, 1=idle + ****************************************************************************/ + +static void lc823450_dvfs_set_div(int idx, int tbl) +{ + uint32_t target; + uint32_t t_hdiv; + uint32_t t_mdiv; + + if (0 == tbl) + { + target = _dvfs_act_tbl[idx].freq; + t_hdiv = _dvfs_act_tbl[idx].hdiv; + t_mdiv = _dvfs_act_tbl[idx].mdiv; + } + else + { + target = _dvfs_idl_tbl[idx].freq; + t_hdiv = _dvfs_idl_tbl[idx].hdiv; + t_mdiv = _dvfs_idl_tbl[idx].mdiv; + } + + if (100 < target) + { + /* Set ROM wait cycle (CPU=1wait) */ + + modifyreg32(MEMEN4, 0, MEMEN4_HWAIT); + } + + /* adjust AHB */ + + if (t_hdiv > _dvfs_cur_hdiv) + { + uint32_t pclkdiv = t_hdiv; +#ifdef CONFIG_LC823450_SDRAM + pclkdiv += (t_hdiv << 16); +#endif + putreg32(pclkdiv, PERICLKDIV); + } + + uint32_t regval = getreg32(OSCCNT); + + /* NOTE: In LC823450, MCSEL is reflected first then MAINDIV */ + /* To avoid spec violation, 2-step clock change is needed */ + + /* step 1 : change MAINDIV if needed */ + + if (t_mdiv > _dvfs_cur_mdiv) + { + regval &= ~OSCCNT_MAINDIV_MASK; + regval |= t_mdiv; + + /* change the MAINDIV first */ + + putreg32(regval, OSCCNT); + } + + /* step 2 : change MCSEL and MAINDIV */ + + regval = getreg32(OSCCNT); + regval &= ~(OSCCNT_MCSEL | OSCCNT_MAINDIV_MASK); + + if (0 == tbl) + { + regval |= _dvfs_act_tbl[idx].pll1; + } + else + { + regval |= _dvfs_idl_tbl[idx].pll1; + } + + regval |= t_mdiv; + + /* set MCSEL and MAINDIV again */ + + putreg32(regval, OSCCNT); + + /* update loops_per_msec for up_udelay(), up_mdelay() */ + + if (0 == tbl) + { + lc823450_dvfs_update_lpm(_dvfs_act_tbl[idx].freq); + } + else + { + lc823450_dvfs_update_lpm(_dvfs_idl_tbl[idx].freq); + } + + /* adjust AHB */ + + if (t_hdiv < _dvfs_cur_hdiv) + { + uint32_t pclkdiv = t_hdiv; +#ifdef CONFIG_LC823450_SDRAM + pclkdiv += (t_hdiv << 16); +#endif + putreg32(pclkdiv, PERICLKDIV); + } + + _dvfs_cur_idx = idx; + _dvfs_cur_hdiv = t_hdiv; + _dvfs_cur_mdiv = t_mdiv; + g_dvfs_cur_freq = target; + + if (100 > target) + { + /* Clear ROM wait cycle (CPU=0wait) */ + + modifyreg32(MEMEN4, MEMEN4_HWAIT, 0); + } + +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lc823450_get_apb + * Assumption: CPU=APB + ****************************************************************************/ + +uint32_t lc823450_get_apb(void) +{ + return g_dvfs_cur_freq * 1000000; +} + +/**************************************************************************** + * Name: lc823450_dvfs_tick_callback + * This callback is called in the timer interupt + ****************************************************************************/ + +void lc823450_dvfs_tick_callback(void) +{ +#if 0 + if (_dvfs_init_timeout) + { + _dvfs_init_timeout--; + + if (0 == _dvfs_init_timeout) + { + g_dvfs_enabled = 1; + } + } +#endif +} + +/**************************************************************************** + * Name: lc823450_dvfs_enter_idle + ****************************************************************************/ + +void lc823450_dvfs_enter_idle(void) +{ + irqstate_t flags = spin_lock_irqsave(); + + if (0 == g_dvfs_enabled) + { + goto exit_with_error; + } + +#if defined(CONFIG_SMP) && (CONFIG_SMP_NCPUS == 2) + int me = up_cpu_index(); + + /* Update my state first : 0 (idle) */ + + _dvfs_cpu_is_active[me] = 0; + + /* check if another core is still active */ + + if (_dvfs_another_cpu_state(me)) + { + /* do not change to idle clock */ + + goto exit_with_error; + } + +#endif + +#ifdef CONFIG_DVFS_CHECK_SDC + if (lc823450_sdc_locked()) + { + goto exit_with_error; + } +#endif + + /* NOTE: set idle freq : idx=same, change:tbl */ + + lc823450_dvfs_set_div(_dvfs_cur_idx, 1); + +exit_with_error: + spin_unlock_irqrestore(flags); +} + +/**************************************************************************** + * Name: lc823450_dvfs_exit_idle + * This API is called in up_ack_irq() (i.e. interrupt context) + ****************************************************************************/ + +void lc823450_dvfs_exit_idle(int irq) +{ + irqstate_t flags = spin_lock_irqsave(); + + if (0 == g_dvfs_enabled) + { + goto exit_with_error; + } + +#if defined(CONFIG_SMP) && (CONFIG_SMP_NCPUS == 2) + int me = up_cpu_index(); + + /* Update my state first: 1 (active) */ + + _dvfs_cpu_is_active[me] = 1; + + /* Check if another core is already active */ + + if (_dvfs_another_cpu_state(me)) + { + /* do nothing */ + + goto exit_with_error; + } +#endif + + /* NOTE: set active freq : idx=same, change:tbl */ + + lc823450_dvfs_set_div(_dvfs_cur_idx, 0); + +exit_with_error: + spin_unlock_irqrestore(flags); +} + +/**************************************************************************** + * Name: lc823450_dvfs_boost + * boost the sytem clock to MAX (i.e. 160M) + * timeout in msec + ****************************************************************************/ + +int lc823450_dvfs_boost(int timeout) +{ + /* TODO */ + return 0; +} + +/**************************************************************************** + * Name: lc823450_dvfs_set_freq + * NOTE: should be called from dvfs command only + ****************************************************************************/ + +int lc823450_dvfs_set_freq(int freq) +{ + int ret = 0; + int idx; + irqstate_t flags; + + if (0 == g_dvfs_enabled) + { + return -1; + } + + flags = spin_lock_irqsave(); + + switch (freq) + { + case 160: + idx = FREQ_160; + break; + + case 80: + idx = FREQ_080; + break; + + case 40: + idx = FREQ_040; + break; + + default: + ret = -1; + break; + } + + if (0 == ret) + { + lc823450_dvfs_set_div(idx, 0); + } + + spin_unlock_irqrestore(flags); + return ret; +} diff --git a/arch/arm/src/lc823450/lc823450_dvfs2.h b/arch/arm/src/lc823450/lc823450_dvfs2.h new file mode 100644 index 0000000000000000000000000000000000000000..a4423d65e065c5e191bc490969cc2d75c4a1e7dc --- /dev/null +++ b/arch/arm/src/lc823450/lc823450_dvfs2.h @@ -0,0 +1,75 @@ +/**************************************************************************** + * arch/arm/src/lc823450/lc823450_dvfs2.h + * + * Copyright (C) 2015-2017 Sony Corporation. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LC823450_LC823450_DVFS2_H +#define __ARCH_ARM_SRC_LC823450_LC823450_DVFS2_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void lc823450_dvfs_set_min(uint8_t id, uint16_t mhz); +void lc823450_dvfs_enter_idle(void); +void lc823450_dvfs_exit_idle(int irq); +int lc823450_dvfs_set_freq(int freq); +void lc823450_dvfs_tick_callback(void); + +int dvfs_procfs_register(void); + +#if defined(__cplusplus) +} +#endif +#undef EXTERN +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LC823450_LC823450_DVFS2_H */ diff --git a/arch/arm/src/lc823450/lc823450_gpio.c b/arch/arm/src/lc823450/lc823450_gpio.c index a9c6d06b50c9940600e87c51e38f96b9d2fbf43c..bb8aab5d3cb25821bd29ef713f93ed80ce4c741a 100644 --- a/arch/arm/src/lc823450/lc823450_gpio.c +++ b/arch/arm/src/lc823450/lc823450_gpio.c @@ -239,12 +239,12 @@ int lc823450_gpio_mux(uint16_t gpiocfg) if (port <= (GPIO_PORT5 >> GPIO_PORT_SHIFT)) { - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(); val = getreg32(PMDCNT0 + (port * 4)); val &= ~(3 << (2 * pin)); val |= (mux << (2 *pin)); putreg32(val, PMDCNT0 + (port * 4)); - leave_critical_section(flags); + spin_unlock_irqrestore(flags); } else { @@ -287,7 +287,7 @@ int lc823450_gpio_config(uint16_t gpiocfg) /* Handle the GPIO configuration by the basic mode of the pin */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(); /* pull up/down specified */ @@ -312,7 +312,7 @@ int lc823450_gpio_config(uint16_t gpiocfg) break; } - leave_critical_section(flags); + spin_unlock_irqrestore(flags); } #ifdef CONFIG_IOEX else if (port <= (GPIO_PORTEX >> GPIO_PORT_SHIFT)) @@ -400,24 +400,24 @@ void lc823450_gpio_write(uint16_t gpiocfg, bool value) regaddr = lc823450_get_gpio_data(port); - flags = enter_critical_section(); + flags = spin_lock_irqsave(); /* Write the value (0 or 1). To the data register */ regval = getreg32(regaddr); - if (value) - { - regval |= (1 << pin); - } - else - { - regval &= ~(1 << pin); - } + if (value) + { + regval |= (1 << pin); + } + else + { + regval &= ~(1 << pin); + } - putreg32(regval, regaddr); + putreg32(regval, regaddr); - leave_critical_section(flags); + spin_unlock_irqrestore(flags); } #ifdef CONFIG_IOEX else if (port <= (GPIO_PORTEX >> GPIO_PORT_SHIFT)) diff --git a/arch/arm/src/lc823450/lc823450_i2c.c b/arch/arm/src/lc823450/lc823450_i2c.c index 4b9c26451e570e735d9b192c3657131e2a76ed36..5b49856ee4b27a068c9386ec27bda8946de1f183 100644 --- a/arch/arm/src/lc823450/lc823450_i2c.c +++ b/arch/arm/src/lc823450/lc823450_i2c.c @@ -765,12 +765,12 @@ static int lc823450_i2c_poll(FAR struct lc823450_i2c_priv_s *priv) i2cinfo("re-START condition\n"); +#ifdef CONFIG_I2C_RESET /* Reset I2C bus by softreset. There is not description of the reset, * but in order to recover I2C bus busy, it must be done. * Please refer to macaron's code. */ -#ifdef CONFIG_I2C_RESET lc823450_i2c_reset((FAR struct i2c_master_s *)priv); #endif @@ -778,6 +778,7 @@ static int lc823450_i2c_poll(FAR struct lc823450_i2c_priv_s *priv) /* We have to enable interrupt again, because all registers are reset by * lc823450_i2c_reset(). */ + lc823450_i2c_enableirq(priv); #endif @@ -1053,7 +1054,7 @@ static int lc823450_i2c_transfer(FAR struct i2c_master_s *dev, leave_critical_section(irqs); } -#ifndef CONFIG_IPL2 +#ifndef CONFIG_LC823450_IPL2 i2cerr("ERROR: I2C timed out (dev=%xh)\n", msgs->addr); #endif } diff --git a/arch/arm/src/lc823450/lc823450_i2s.c b/arch/arm/src/lc823450/lc823450_i2s.c new file mode 100644 index 0000000000000000000000000000000000000000..3eced5cb4f246d282cf4b122b2ac7adf91330c6e --- /dev/null +++ b/arch/arm/src/lc823450/lc823450_i2s.c @@ -0,0 +1,472 @@ +/**************************************************************************** + * arch/arm/src/lc823450/lc823450_i2s.c + * + * Copyright (C) 2017 Sony Corporation. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "up_arch.h" +#include "lc823450_dma.h" +#include "lc823450_i2s.h" +#include "lc823450_syscontrol.h" +#include "lc823450_clockconfig.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LC823450_AUDIO_REGBASE 0x40060000 + +#define ABUF_REGBASE (LC823450_AUDIO_REGBASE + 0x0000) +#define BEEP_REGBASE (LC823450_AUDIO_REGBASE + 0x1200) +#define PCKGEN_REGBASE (LC823450_AUDIO_REGBASE + 0x1600) +#define AUDCTL_REGBASE (LC823450_AUDIO_REGBASE + 0x4000) + +#define ABUFCLR (ABUF_REGBASE + 0x0000) + +#define ABUFACCEN (ABUF_REGBASE + 0x0004) +#define ABUFACCEN_CDCFEN (1 << 5) + +#define ABUFIRQEN0 (ABUF_REGBASE + 0x0008) +#define ABUFIRQEN0_BFULIRQEN (1 << 5) + +#define ABUFSTS1 (ABUF_REGBASE + 0x0034) + +#define BUF_F_BASE (ABUF_REGBASE + 0x00c0 + (0x4 * 5)) +#define BUF_F_SIZE (ABUF_REGBASE + 0x0100 + (0x4 * 5)) +#define BUF_F_ULVL (ABUF_REGBASE + 0x0140 + (0x4 * 5)) +#define BUF_F_DTCAP (ABUF_REGBASE + 0x01c0 + (0x4 * 5)) +#define BUF_F_ACCESS (ABUF_REGBASE + 0x0300 + (0x4 * 5)) + +#define CLOCKEN (AUDCTL_REGBASE + 0x0000) +#define CLOCKEN_FCE_PCKGEN (1 << 28) +#define CLOCKEN_FCE_PCMPS0 (1 << 17) +#define CLOCKEN_FCE_BEEP (1 << 16) +#define CLOCKEN_FCE_VOLPS0 (1 << 13) + +#define AUDSEL (AUDCTL_REGBASE + 0x001c) +#define AUDSEL_PCM0_MODE (1 << 17) +#define AUDSEL_PCM0_MODEM (1 << 16) + +#define PSCTL (AUDCTL_REGBASE + 0x0110) + +#define PCMOUTEN (AUDCTL_REGBASE + 0x0500) +#define PCMOUTEN_DOUT0EN (1 << 3) +#define PCMOUTEN_LRCK0EN (1 << 2) +#define PCMOUTEN_MCLK0EN (1 << 1) +#define PCMOUTEN_BCK0EN (1 << 0) + +#define PCMCTL (AUDCTL_REGBASE + 0x0504) + +#define BEEP_CTL (BEEP_REGBASE + 0x0000) +#define BEEP_BYPASS (BEEP_REGBASE + 0x0004) +#define BEEP_COEFF (BEEP_REGBASE + 0x0008) +#define BEEP_TIME (BEEP_REGBASE + 0x000c) + +/* Audio PLL */ + +#define AUDIOPLL_REGBASE (LC823450_OSCSYS_REGBASE + 0x2000) +#define AUDPLLCNT (AUDIOPLL_REGBASE + 0x00) +#define AUDPLLMDIV (AUDIOPLL_REGBASE + 0x04) +#define AUDPLLNDIV (AUDIOPLL_REGBASE + 0x08) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* The state of the one I2S peripheral */ + +struct lc823450_i2s_s +{ + struct i2s_dev_s dev; /* Externally visible I2S interface */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static uint32_t lc823450_i2s_txsamplerate(struct i2s_dev_s *dev, uint32_t rate); +static uint32_t lc823450_i2s_txdatawidth(struct i2s_dev_s *dev, int bits); +static int lc823450_i2s_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, + i2s_callback_t callback, void *arg, + uint32_t timeout); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* I2S device operations */ + +static const struct i2s_ops_s g_i2sops = +{ + /* Transmitter methods */ + + .i2s_txsamplerate = lc823450_i2s_txsamplerate, + .i2s_txdatawidth = lc823450_i2s_txdatawidth, + .i2s_send = lc823450_i2s_send, +}; + +static DMA_HANDLE _htxdma; +static sem_t _sem_txdma; +static sem_t _sem_buf_under; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern unsigned int XT1OSC_CLK; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _setup_audio_pll + ****************************************************************************/ + +static void _setup_audio_pll(uint32_t freq) +{ + ASSERT(24000000 == XT1OSC_CLK); + + uint32_t m; + uint32_t n; + + switch (freq) + { + case 44100: + m = 625; + n = 3528; + break; + + case 48000: + m = 125; + n = 768; + break; + + default: + ASSERT(false); + } + + /* Set divider */ + + putreg32(n, AUDPLLNDIV); + putreg32(m, AUDPLLMDIV); + + /* Audio PLL standby=off, Audio PLL unreset */ + + putreg32(0x0503, AUDPLLCNT); + + /* TODO: Wait */ + + usleep(50 * 1000); + + /* Switch to the PLL */ + + modifyreg32(AUDCLKCNT, + 0x0, + 0x03 /* AUDCLKSEL=Audio PLL */ + ); + + /* TODO: Clock divider settings */ + + modifyreg32(AUDCLKCNT, + 0x0, + 0x0200 /* AUDDIV=2 */ + ); +} + +/**************************************************************************** + * Name: _i2s_txdma_callback + ****************************************************************************/ + +static void _i2s_txdma_callback(DMA_HANDLE hdma, void *arg, int result) +{ + sem_t *waitsem = (sem_t *)arg; + nxsem_post(waitsem); +} + +/**************************************************************************** + * Name: _i2s_semtake + ****************************************************************************/ + +static void _i2s_semtake(FAR sem_t *sem) +{ + int ret; + + do + { + /* Take the semaphore (perhaps waiting) */ + + ret = nxsem_wait(sem); + + /* The only case that an error should occur here is if the wait was + * awakened by a signal. + */ + + DEBUGASSERT(ret == OK || ret == -EINTR); + } + while (ret == -EINTR); +} + +/**************************************************************************** + * Name: lc823450_i2s_txsamplerate + ****************************************************************************/ + +static uint32_t lc823450_i2s_txsamplerate(struct i2s_dev_s *dev, uint32_t rate) +{ + /* TODO */ + return 0; +} + +/**************************************************************************** + * Name: lc823450_i2s_txdatawidth + ****************************************************************************/ + +static uint32_t lc823450_i2s_txdatawidth(struct i2s_dev_s *dev, int bits) +{ + /* TODO */ + return 0; +} + +/**************************************************************************** + * Name: _i2s_isr + ****************************************************************************/ + +static int _i2s_isr(int irq, FAR void *context, FAR void *arg) +{ + /* Disable Buffer F Under Level IRQ */ + + putreg32(0, ABUFIRQEN0); + + /* post semaphore for the waiter */ + + nxsem_post(&_sem_buf_under); + return 0; +} + +/**************************************************************************** + * Name: lc823450_i2s_send + ****************************************************************************/ + +static int lc823450_i2s_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, + i2s_callback_t callback, void *arg, + uint32_t timeout) +{ + /* Enable Buffer F Under Level IRQ */ + + putreg32(ABUFIRQEN0_BFULIRQEN, ABUFIRQEN0); + + /* Wait for Audio Buffer */ + + _i2s_semtake(&_sem_buf_under); + + volatile uint32_t *ptr = (uint32_t *)&apb->samp[apb->curbyte]; + uint32_t n = apb->nbytes; + + /* Setup and start DMA for I2S */ + + lc823450_dmasetup(_htxdma, + LC823450_DMA_SRCINC | + LC823450_DMA_SRCWIDTH_WORD | + LC823450_DMA_DSTWIDTH_WORD, + (uint32_t)ptr, (uint32_t)BUF_F_ACCESS, n / 4); + + lc823450_dmastart(_htxdma, + _i2s_txdma_callback, + &_sem_txdma); + + _i2s_semtake(&_sem_txdma); + + /* Invoke the callback handler */ + + callback(dev, apb, arg, 0); + return OK; +} + +/**************************************************************************** + * Name: lc823450_i2s_beeptest + ****************************************************************************/ + +#ifdef BEEP_TEST +static void lc823450_i2s_beeptest(void) +{ + /* Set BEEP params */ + + putreg32(0x0, BEEP_BYPASS); + putreg32(0x123ca6, BEEP_COEFF); /* 1kHz@fs=44.1k */ + putreg32(0xffff, BEEP_TIME); + + /* Start */ + + putreg32(0x3, BEEP_CTL); +} +#endif + +/**************************************************************************** + * Name: lc823450_i2s_configure + ****************************************************************************/ + +static int lc823450_i2s_configure(void) +{ + _setup_audio_pll(44100); + + /* Unreset Audio Buffer */ + + putreg32(MRSTCNTEXT3_AUDIOBUF_RSTB, + MRSTCNTEXT3); + + /* Enable clock to Audio Buffer */ + + putreg32(MCLKCNTEXT3_AUDIOBUF_CLKEN, + MCLKCNTEXT3); + + /* F Buffer = 32KB */ + + putreg32(4096 * 8, BUF_F_SIZE); + + /* Buffer Under Level = 1KB */ + + putreg32(1024, BUF_F_ULVL); + + /* Clear Audio Buffer */ + + putreg32(0xffff, ABUFCLR); + + /* Access Enable */ + + putreg32(ABUFACCEN_CDCFEN, ABUFACCEN); + + /* PCM0: BCK0/LRCK0=master, MCLK0=master */ + + putreg32(AUDSEL_PCM0_MODE | + AUDSEL_PCM0_MODEM, + AUDSEL); + + /* LRCK0/BCK0: 1/1fs, BCK0:64fs, BCK1:64fs */ + + putreg32(0x00001010, + PCMCTL); + + /* Enable DOUT0/LRCK0/MCL0/BCK0 */ + + putreg32(PCMOUTEN_DOUT0EN | + PCMOUTEN_LRCK0EN | + PCMOUTEN_MCLK0EN | + PCMOUTEN_BCK0EN, + PCMOUTEN); + + /* Stereo, PCMDLY=1, LRCK active low, + * MSB first and left justified, 32bit + */ + + putreg32(0x64, PSCTL); + + /* Enable PCMPS0 */ + + putreg32(CLOCKEN_FCE_PCKGEN | + CLOCKEN_FCE_BEEP | + CLOCKEN_FCE_PCMPS0 | + CLOCKEN_FCE_VOLPS0, + CLOCKEN); + + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lc823450_i2sdev_initialize + ****************************************************************************/ + +FAR struct i2s_dev_s *lc823450_i2sdev_initialize(void) +{ + FAR struct lc823450_i2s_s *priv = NULL; + + /* The support STM32 parts have only a single I2S port */ + + i2sinfo("port: %d\n", port); + + /* Allocate a new state structure for this chip select. NOTE that there + * is no protection if the same chip select is used in two different + * chip select structures. + */ + + priv = (struct lc823450_i2s_s *)zalloc(sizeof(struct lc823450_i2s_s)); + if (!priv) + { + i2serr("ERROR: Failed to allocate a chip select structure\n"); + return NULL; + } + + /* Initialize the common parts for the I2S device structure */ + + priv->dev.ops = &g_i2sops; + + (void)lc823450_i2s_configure(); + +#ifdef BEEP_TEST + lc823450_i2s_beeptest(); +#endif + + _htxdma = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL); + nxsem_init(&_sem_txdma, 0, 0); + nxsem_init(&_sem_buf_under, 0, 0); + + irq_attach(LC823450_IRQ_AUDIOBUF0, _i2s_isr, NULL); + + /* Enable IRQ for Audio Buffer */ + + up_enable_irq(LC823450_IRQ_AUDIOBUF0); + + /* Success exit */ + + return &priv->dev; +} diff --git a/drivers/wireless/ieee802154/xbee/xbee_dataind.h b/arch/arm/src/lc823450/lc823450_i2s.h similarity index 69% rename from drivers/wireless/ieee802154/xbee/xbee_dataind.h rename to arch/arm/src/lc823450/lc823450_i2s.h index 074f646f760b9bd3b8f4528151c0c3a42c28057c..82e64be60dcf0f947afaa322e727ac8eb4ec092b 100644 --- a/drivers/wireless/ieee802154/xbee/xbee_dataind.h +++ b/arch/arm/src/lc823450/lc823450_i2s.h @@ -1,9 +1,8 @@ /**************************************************************************** - * drivers/wireless/ieee802154/xbee/xbee_dataind.h + * arch/arm/src/lc823450/lc823450_i2s.h * - * Copyright (C) 2017 Verge Inc. All rights reserved. - * - * Author: Anthony Merlino + * Copyright (C) 2017 Sony Corporation. All rights reserved. + * Author: Masayuki Ishikawa * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -34,44 +33,43 @@ * ****************************************************************************/ -#ifndef __DRIVERS_WIRELESS_IEEE802154_XBEE_DATAIND_H -#define __DRIVERS_WIRELESS_IEEE802154_XBEE_DATAIND_H +#ifndef __ARCH_ARM_SRC_LC823450_LC823450_I2S_H +#define __ARCH_ARM_SRC_LC823450_LC823450_I2S_H /**************************************************************************** * Included Files ****************************************************************************/ #include +#include -#include -#include +#include "chip.h" -#include +#ifndef __ASSEMBLY__ /**************************************************************************** - * Private Types + * Public Data ****************************************************************************/ -/* Extend the public ieee802154_data_ind_s to include a private forward link to - * support a list to handle allocation - */ - -struct xbee_dataind_s +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { - struct ieee802154_data_ind_s pub; /* Publically visible structure */ - FAR struct xbee_dataind_s *flink; /* Supports a singly linked list */ -}; +#else +#define EXTERN extern +#endif /**************************************************************************** - * Function Prototypes + * Public Function Prototypes ****************************************************************************/ -struct xbee_priv_s; /* Forward Reference */ - -void xbee_dataindpool_init(FAR struct xbee_priv_s *priv); +FAR struct i2s_dev_s *lc823450_i2sdev_initialize(void); -int xbee_dataind_alloc(FAR struct xbee_priv_s *priv, - FAR struct ieee802154_data_ind_s **dataind, - bool allow_interrupt); +#undef EXTERN +#if defined(__cplusplus) +} +#endif -#endif /* __DRIVERS_WIRELESS_IEEE802154_XBEE_DATAIND_H */ \ No newline at end of file +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LC823450_LC823450_I2S_H */ diff --git a/arch/arm/src/lc823450/lc823450_idle.c b/arch/arm/src/lc823450/lc823450_idle.c index b9caac0dfef51b1878b25ea7188d8982453a921a..f4ced8826d5339e40514720efb61329c96489e13 100644 --- a/arch/arm/src/lc823450/lc823450_idle.c +++ b/arch/arm/src/lc823450/lc823450_idle.c @@ -42,13 +42,15 @@ #include #include +#include +#include #include "nvic.h" #include "up_internal.h" #include "up_arch.h" #ifdef CONFIG_DVFS -# include "lc823450_dvfs.h" +# include "lc823450_dvfs2.h" #endif /**************************************************************************** @@ -60,6 +62,8 @@ static int32_t g_in_sleep; static uint64_t g_sleep_t0; #endif /* CONFIG_LC823450_SLEEP_MODE */ +static uint32_t g_idle_counter[2]; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -122,16 +126,21 @@ void up_idle(void) regval &= ~NVIC_SYSCON_SLEEPDEEP; putreg32(regval, NVIC_SYSCON); + leave_critical_section(flags); +#endif /* CONFIG_LC823450_SLEEP_MODE */ + #ifdef CONFIG_DVFS lc823450_dvfs_enter_idle(); #endif - leave_critical_section(flags); -#endif /* CONFIG_LC823450_SLEEP_MODE */ + board_autoled_off(LED_CPU0 + up_cpu_index()); /* Sleep until an interrupt occurs to save power */ asm("WFI"); + + g_idle_counter[up_cpu_index()]++; + #endif } diff --git a/arch/arm/src/lc823450/lc823450_ipl2.c b/arch/arm/src/lc823450/lc823450_ipl2.c new file mode 100644 index 0000000000000000000000000000000000000000..beabbc4a5f580445a1dace86476c23a7722c1bb1 --- /dev/null +++ b/arch/arm/src/lc823450/lc823450_ipl2.c @@ -0,0 +1,758 @@ +/**************************************************************************** + * arch/arm/src/lc823450/lc823450_ipl2.c + * + * Copyright (C) 2015-2017 Sony Corporation. All rights reserved. + * Author: Masatoshi Tateishi + * Author: Nobutaka Toyoshima + * Author: Yasuhiro Osaki + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#ifdef CONFIG_FS_EVFAT +# include +#endif + +#include +#include +#include + +#ifdef CONFIG_I2C +# include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_LASTKMSG +# include +#endif /* CONFIG_LASTKMSG */ + +#include + +#include + +#include "up_internal.h" +#include "up_arch.h" + +#ifdef CONFIG_ADC +# include "lc823450_adc.h" +#endif + +#include "lc823450_syscontrol.h" +#include "lc823450_mtd.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IPL2_DEVPATH "/dev/mtdblock0" +#define IPL2_IMAGE "LC8234xx_17S_start_data.boot_bin" + +#define LASTMSG_LOGPATH "/log/lastkmsg" + +#define R2A20056BM_ADDR 0x1B +#define R2A20056BM_SCL 375000 + +#ifdef CONFIG_CHARGER +# define FORCE_USBBOOT_CHARGER +#endif + +#pragma GCC optimize ("O0") + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +static struct +{ + uint32_t sig; + uint32_t chunknum; + struct + { + char fname[32]; + char csum[32]; + uint32_t size; + uint32_t enc; + uint32_t offset; + } chunk[10]; +} upg_image; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static char copybuf[512]; +static void *tmp; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef CONFIG_USBMSC +static void sysreset(void); +static int set_config(int num, char *buf); +#endif + +/**************************************************************************** + * Name: blk_read() + ****************************************************************************/ + +static int blk_read(void *buf, int len, const char *path, int offset) +{ + void *handle; + int ret; + + ret = bchlib_setup(path, true, &handle); + + if (ret) + { + return ret; + } + + ret = bchlib_read(handle, buf, offset, len); + + bchlib_teardown(handle); + + return ret; +} + +/**************************************************************************** + * Name: blk_write() + ****************************************************************************/ + +#ifdef CONFIG_USBMSC +static int blk_write(const void *buf, int len, const char *path, int offset) +{ + void *handle; + int ret; + + ret = bchlib_setup(path, true, &handle); + + if (ret) + { + return ret; + } + + ret = bchlib_write(handle, buf, offset, len); + + bchlib_teardown(handle); + + return ret; +} +#endif + +/**************************************************************************** + * Name: install_recovery() + ****************************************************************************/ + +static int install_recovery(const char *srcpath) +{ + int rfd, i, len, rem; + int ret = 0; + void *handle = NULL; + + if (bchlib_setup(CONFIG_MTD_RECOVERY_DEVPATH, false, &handle)) + { + return -1; + } + + rfd = open(srcpath, O_RDONLY, 0444); + + if (read(rfd, &upg_image, sizeof(upg_image)) != sizeof(upg_image)) + { + _info("read head"); + ret = -EIO; + goto err; + } + +#ifdef IMG_SIGNATURE + if (upg_image.sig != IMG_SIGNATURE) + { + _info("image signature missmatch. IPL2=%u, UPG=%u\n", + IMG_SIGNATURE, upg_image.sig); + _info("go normal boot\n"); + + memset(copybuf, 0, sizeof(copybuf)); + snprintf(copybuf, sizeof(copybuf), "normal"); + set_config(1, copybuf); + sysreset(); + + /* NOT REACHED */ + + } +#endif + + for (i = 0; i < upg_image.chunknum; i++) + { + if (!strcmp(basename(upg_image.chunk[i].fname), "recovery")) + { + break; + } + } + + if (i == upg_image.chunknum) + { + _info("recovery not found\n"); + ret = -ENOENT; + goto err; + } + + lseek(rfd, upg_image.chunk[i].offset + + ((void *)&upg_image.chunk[upg_image.chunknum] - (void *)&upg_image), + SEEK_SET); + + rem = upg_image.chunk[i].size; + + while (rem > 0) + { + len = read(rfd, copybuf, rem > 512 ? 512 : rem); + + if (len < 0) + { + _info("read image"); + ret = -EIO; + goto err; + } + + bchlib_write(handle, copybuf, upg_image.chunk[i].size - rem, len); + rem -= len; + } + +err: + if (handle) + { + bchlib_teardown(handle); + } + + close(rfd); + _info("DONE\n"); + return ret; +} + +/**************************************************************************** + * Name: load_kernel() + ****************************************************************************/ + +static void load_kernel(const char *name, const char *devname) +{ + int i; + + tmp = (void *)0x02040000; + + (void)blk_read(tmp, 512 * 1024, devname, 0); + + /* disable all IRQ */ + for (i = LC823450_IRQ_NMI + 1; i < NR_IRQS; i++) + { + up_disable_irq(i); + } + + /* clear pending IRQ */ + putreg32(0xffffffff, NVIC_IRQ0_31_CLRPEND); + putreg32(0xffffffff, NVIC_IRQ32_63_CLRPEND); + putreg32(0xffffffff, NVIC_IRQ64_95_CLRPEND); + + _info("start %s\n", name); + + __asm__ __volatile__ + ( + "ldr r0, =tmp\n" + "ldr r1, [r0, #0]\n" /* r1 = 0x02040000 */ + "ldr sp, [r1, #0]\n" /* set sp */ + "ldr pc, [r1, #4]" /* set pc, start nuttx */ + ); + +} + +/**************************************************************************** + * Name: check_diskformat() + ****************************************************************************/ + +#ifdef CONFIG_USBMSC +static int check_diskformat(void) +{ + int ret; + +#ifdef CONFIG_FS_EVFAT + struct evfat_format_s fmt = EVFAT_FORMAT_INITIALIZER; + + /* load MBR */ + + ret = blk_read(copybuf, sizeof(copybuf), "/dev/mtdblock0p2", 0); + + if (ret < 0) + { + return 0; + } + + /* If part2 has MBR signature, this eMMC was formated by PC. + * This means the set is just after writing IPL2. + */ + + if (copybuf[510] != 0x55 || copybuf[511] != 0xaa) + { + return 0; + } + + ret = mkevfatfs(CONFIG_MTD_CP_DEVPATH, &fmt); +#endif + + _info("FORMAT content partition : %d\n", ret); + + memset(copybuf, 0, sizeof(copybuf)); + ret = blk_write(copybuf, 512, CONFIG_MTD_ETC_DEVPATH, 0); + _info("clear /etc : %d\n", ret); + ret = blk_write(copybuf, 512, CONFIG_MTD_SYSTEM_DEVPATH, 0); + _info("clear /system : %d\n", ret); + ret = blk_write(copybuf, 512, CONFIG_MTD_CACHE_DEVPATH, 0); + _info("clear /cache : %d\n", ret); + + return 1; +} +#endif + +/**************************************************************************** + * Name: check_forceusbboot() + ****************************************************************************/ + +#ifdef CONFIG_ADC +static int check_forceusbboot(void) +{ + uint32_t val; + uint32_t val1; + + /* enable clock & unreset */ + + modifyreg32(MCLKCNTAPB, 0, MCLKCNTAPB_ADC_CLKEN); + modifyreg32(MRSTCNTAPB, 0, MRSTCNTAPB_ADC_RSTB); + + usleep(10000); + + /* start ADC0,1 */ + + putreg32(rADCCTL_fADCNVCK_DIV32 | rADCCTL_fADACT | rADCCTL_fADCHSCN | + 1 /* 0,1 ch */, rADCCTL); + + putreg32(53, rADCSMPL); + + /* wait for adc done */ + + while ((getreg32(rADCSTS) & rADCSTS_fADCMPL) == 0) + ; + + val = getreg32(rADC0DT); + val1 = getreg32(rADC1DT); + + _info("val = %d, val1 = %d\n", val, val1); + + /* disable clock & reset */ + + modifyreg32(MCLKCNTAPB, MCLKCNTAPB_ADC_CLKEN, 0); + modifyreg32(MRSTCNTAPB, MRSTCNTAPB_ADC_RSTB, 0); + + /* check KEY0_AD_D key pressed */ + + if (val >= (0x3A << 2) && val < (0x57 << 2)) + { + return 1; + } + + /* check KEY0_AD_B key pressed */ + + if (val >= (0x0B << 2) && val < (0x20 << 2)) + { + return 1; + } + + /* check KEY1_AD_B key pressed */ + + if (val1 >= (0x0B << 2) && val1 < (0x20 << 2)) + { + return 1; + } + + return 0; +} +#endif + +#ifdef CONFIG_USBMSC + +/**************************************************************************** + * Name: sysreset() + ****************************************************************************/ + +static void sysreset(void) +{ + /* workaround to flush eMMC cache */ + + usleep(100000); + + up_systemreset(); +} + +/**************************************************************************** + * Name: get_config() + ****************************************************************************/ + +static int get_config(int num, char *buf) +{ + int ret; + ret = blk_read(buf, 512, CONFIG_MTD_CONFIG_DEVPATH, num * 512); + return ret; +} + +/**************************************************************************** + * Name: set_config() + ****************************************************************************/ + +static int set_config(int num, char *buf) +{ + int ret; + ret = blk_write(buf, 512, CONFIG_MTD_CONFIG_DEVPATH, num * 512); + return ret; +} + +#endif /* CONFIG_USBMSC */ + +extern volatile int g_update_flag; + +/**************************************************************************** + * Name: chg_disable() + ****************************************************************************/ + +#ifdef CONFIG_CHARGER +static void chg_disable(void) +{ + FAR struct i2c_dev_s *i2c; + int ret; + uint32_t freq; + + const uint8_t addr = 0x01; + const uint8_t data = 0x83; + + struct i2c_msg_s msg[2] = + { + { + .addr = R2A20056BM_ADDR, + .flags = 0, + .buffer = (uint8_t *)&addr, + .length = 1, + }, + { + .addr = R2A20056BM_ADDR, + .flags = I2C_M_NORESTART, + .buffer = (uint8_t *)&data, + .length = 1, + } + }; + + /* I2C pinmux */ + + modifyreg32(PMDCNT0, 0x0003C000, 0x00014000); + + /* I2C drv : 4mA */ + + modifyreg32(PTDRVCNT0, 0x0003C000, 0x0003C000); + + /* Enable I2C controller */ + + modifyreg32(MCLKCNTAPB, 0, MCLKCNTAPB_I2C0_CLKEN); + modifyreg32(MRSTCNTAPB, 0, MRSTCNTAPB_I2C0_RSTB); + + /* I2C SCL: push pull */ + + modifyreg32(I2CMODE, 0, I2CMODE0); + + /* Disable charge */ + + i2c = up_i2cinitialize(1); + + if (i2c) + { + /* Set slave address */ + + ret = I2C_SETADDRESS(i2c, R2A20056BM_ADDR, 7); + + /* Set frequency */ + + freq = I2C_SETFREQUENCY(i2c, R2A20056BM_SCL); + + /* Charge disable */ + + if (ret == OK && freq == R2A20056BM_SCL) + { + ret = I2C_TRANSFER(i2c, msg, sizeof(msg) / sizeof(msg[0])); + + if (ret != OK) + { + _info("no vbus (%d)\n", ret); + } + else + { + usleep(20); + } + } + + up_i2cuninitialize(i2c); + } + else + { + _info("Failed to i2c initialize\n"); + } +} +#endif + +/**************************************************************************** + * Name: msc_enable() + ****************************************************************************/ + +#ifdef CONFIG_USBMSC +static int msc_enable(int forced) +{ + int ret; + void *handle; + + usbmsc_configure(1, &handle); + usbmsc_bindlun(handle, CONFIG_MTD_CP_DEVPATH, 0, 0, 0, false); + usbmsc_exportluns(handle); + +#ifdef FORCE_USBBOOT_CHARGER + if (!forced && !usbdev_is_usbcharger()) + { + /* If not USBCharger, go normal boot */ + + usbmsc_uninitialize(handle); + return 0; + } + + /* wait for SCSI command */ + + while (g_update_flag == 0) + { + /* If key released, go normal boot */ + + if (!forced && !check_forceusbboot()) + { + usbmsc_uninitialize(handle); + return 0; + } + usleep(10000); + } + +#else + /* wait for SCSI command */ + + while (g_update_flag == 0) + { + usleep(10000); + } +#endif + + usbmsc_uninitialize(handle); + + /* check recovery kernel update */ + + mount(CONFIG_MTD_CP_DEVPATH, "/mnt/sd0", "evfat", 0, NULL); + usleep(10000); + + /* recovery kernel install from UPG.img */ + + ret = install_recovery("/mnt/sd0/UPG.IMG"); + + if (ret == 0) + { + _info("Install recovery\n"); + + /* clear old MBR */ + memset(copybuf, 0, sizeof(copybuf)); + set_config(0, copybuf); + } + + /* set bootmode to recovery */ + + memset(copybuf, 0, sizeof(copybuf)); + snprintf(copybuf, sizeof(copybuf), "recovery"); + set_config(1, copybuf); + + sysreset(); + + /* not reached */ + return 0; +} +#endif + +#ifdef CONFIG_LASTKMSG + +/**************************************************************************** + * Name: check_lastkmsg() + ****************************************************************************/ + +void check_lastkmsg(void) +{ + int ret; + FILE *fp; + + if (g_lastksg_buf.sig != LASTKMSG_SIG) + { + return; + } + + ret = mount(CONFIG_MTD_LOG_DEVPATH, "/log", "vfat", 0, NULL); + + if (ret) + { + _info("mount: ret = %d\n", ret); + return; + } + + /* log rotate */ + + (void)unlink(LASTMSG_LOGPATH ".4"); + (void)rename(LASTMSG_LOGPATH ".3", LASTMSG_LOGPATH ".4"); + (void)rename(LASTMSG_LOGPATH ".2", LASTMSG_LOGPATH ".3"); + (void)rename(LASTMSG_LOGPATH ".1", LASTMSG_LOGPATH ".2"); + (void)rename(LASTMSG_LOGPATH ".0", LASTMSG_LOGPATH ".1"); + + fp = fopen(LASTMSG_LOGPATH ".0", "w"); + + if (fp) + { + lastkmsg_output(fp); + fflush(fp); + fclose(fp); + } + + umount("/log"); + + /* XXX: workaround for logfile size = 0 */ + + usleep(100000); +} +#endif /* CONFIG_LASTKMSG */ + +/**************************************************************************** + * Name: ipl2_main() + ****************************************************************************/ + +int ipl2_main(int argc, char *argv[]) +{ + int ret; + + UNUSED(ret); /* Not used in all configurations */ + + _info("start: %s\n", CONFIG_CURRENT_REVISION); + _info("imgsig: %u\n", IMG_SIGNATURE); + +#ifdef CONFIG_CHARGER + /* NOTE: + * chg_disable() must be done before CMIC_FWAKE L->H. + * Please refer to PDFW15IS-2494 for more information + */ + + chg_disable(); +#endif + + lc823450_mtd_initialize(0); + +#ifdef CONFIG_ADC + ret = check_forceusbboot(); +#endif + +#ifdef CONFIG_USBMSC + if (ret) + { + msc_enable(0); + } + + ret = check_diskformat(); + + if (ret) + { + msc_enable(1); + } + + memset(copybuf, 0, sizeof(copybuf)); + get_config(1, copybuf); + + /* for "reboot usb" */ + + if (!strncmp("usb", copybuf, 3)) + { + /* remove boot flag for next boot */ + + memset(copybuf, 0, sizeof(copybuf)); + set_config(1, copybuf); + msc_enable(1); + } +#endif + +#ifdef CONFIG_LASTKMSG + check_lastkmsg(); +#endif /* CONFIG_LASTKMSG */ + + if (!strncmp("recovery", copybuf, 8)) + { + /* check recovery kernel update */ + + mount(CONFIG_MTD_CP_DEVPATH, "/mnt/sd0", "evfat", 0, NULL); + usleep(10000); + + /* recovery kernel install from UPG.img */ + + install_recovery("/mnt/sd0/UPG.IMG"); + load_kernel("recovery", CONFIG_MTD_RECOVERY_DEVPATH); + + } + else + { + load_kernel("nuttx", CONFIG_MTD_KERNEL_DEVPATH); + } + + /* not reached */ + + return -1; +} + diff --git a/arch/arm/src/lc823450/lc823450_irq.c b/arch/arm/src/lc823450/lc823450_irq.c index e36b26b8bddbf983797f0769c81edced9174eba0..9339f7cd632a291821f2668b6d3b1ab27d707cbc 100644 --- a/arch/arm/src/lc823450/lc823450_irq.c +++ b/arch/arm/src/lc823450/lc823450_irq.c @@ -47,6 +47,8 @@ #include #include #include +#include +#include #include "nvic.h" #include "ram_vectors.h" @@ -56,7 +58,7 @@ #include "lc823450_intc.h" #ifdef CONFIG_DVFS -# include "lc823450_dvfs.h" +# include "lc823450_dvfs2.h" #endif /**************************************************************************** @@ -630,6 +632,7 @@ void up_enable_irq(int irq) uintptr_t regaddr; uint32_t regval; uint32_t bit; + irqstate_t flags; #ifdef CONFIG_LC823450_VIRQ if (irq >= LC823450_IRQ_VIRTUAL && @@ -655,6 +658,8 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ + flags = spin_lock_irqsave(); + if (irq >= LC823450_IRQ_NIRQS) { /* Clear already asserted IRQ */ @@ -675,6 +680,8 @@ void up_enable_irq(int irq) regval |= bit; putreg32(regval, regaddr); } + + spin_unlock_irqrestore(flags); } /* lc823450_dumpnvic("enable", irq); */ @@ -690,10 +697,24 @@ void up_enable_irq(int irq) void up_ack_irq(int irq) { + if (irq < LC823450_IRQ_SYSTICK) + { + return; + } + #ifdef CONFIG_DVFS lc823450_dvfs_exit_idle(irq); #endif + board_autoled_on(LED_CPU0 + up_cpu_index()); + +#ifdef CONFIG_SMP + if (irq > LC823450_IRQ_LPDSP0 && 1 == up_cpu_index()) + { + irqwarn("*** warning irq(%d) handled on CPU1."); + } +#endif + #ifdef CONFIG_LC823450_SLEEP_MODE extern void up_update_idle_time(void); up_update_idle_time(); @@ -789,7 +810,7 @@ int lc823450_irq_srctype(int irq, enum lc823450_srctype_e srctype) port = (irq & 0x70) >> 4; gpio = irq & 0xf; - flags = enter_critical_section(); + flags = spin_lock_irqsave(); regaddr = INTC_REG(EXTINTnCND_BASE, port); regval = getreg32(regaddr); @@ -799,7 +820,7 @@ int lc823450_irq_srctype(int irq, enum lc823450_srctype_e srctype) putreg32(regval, regaddr); - leave_critical_section(flags); + spin_unlock_irqrestore(flags); return OK; } diff --git a/arch/arm/src/lc823450/lc823450_procfs_dvfs.c b/arch/arm/src/lc823450/lc823450_procfs_dvfs.c new file mode 100644 index 0000000000000000000000000000000000000000..fa69b0a3ca3a0dd34c22cb2d162b4988b6a89a84 --- /dev/null +++ b/arch/arm/src/lc823450/lc823450_procfs_dvfs.c @@ -0,0 +1,354 @@ +/**************************************************************************** + * arch/arm/src/lc823450/lc823450_procfs_dvfs.c + * + * Copyright (C) 2018 Sony Corporation. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "lc823450_dvfs2.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DVFS_LINELEN 64 + +#ifndef MIN +# define MIN(a,b) (a < b ? a : b) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct dvfs_file_s +{ + struct procfs_file_s base; /* Base open file structure */ + unsigned int linesize; /* Number of valid characters in line[] */ + char line[DVFS_LINELEN]; /* Pre-allocated buffer for formatted lines */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int dvfs_open(FAR struct file *filep, FAR const char *relpath, + int oflags, mode_t mode); +static int dvfs_close(FAR struct file *filep); +static ssize_t dvfs_read(FAR struct file *filep, FAR char *buffer, + size_t buflen); +static ssize_t dvfs_write(FAR struct file *filep, FAR const char *buffer, + size_t buflen); +static int dvfs_dup(FAR const struct file *oldp, + FAR struct file *newp); +static int dvfs_stat(FAR const char *relpath, FAR struct stat *buf); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct procfs_operations dvfs_procfsoperations = +{ + dvfs_open, /* open */ + dvfs_close, /* close */ + dvfs_read, /* read */ + dvfs_write, /* write */ + dvfs_dup, /* dup */ + NULL, /* opendir */ + NULL, /* closedir */ + NULL, /* readdir */ + NULL, /* rewinddir */ + dvfs_stat /* stat */ +}; + +static const struct procfs_entry_s g_procfs_dvfs = +{ + "dvfs", + &dvfs_procfsoperations +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern int8_t g_dvfs_enabled; +extern uint16_t g_dvfs_cur_freq; + + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: dvfs_open + ****************************************************************************/ + +static int dvfs_open(FAR struct file *filep, FAR const char *relpath, + int oflags, mode_t mode) +{ + FAR struct dvfs_file_s *priv; + + finfo("Open '%s'\n", relpath); + + /* "dvfs" is the only acceptable value for the relpath */ + + if (strcmp(relpath, "dvfs") != 0) + { + ferr("ERROR: relpath is '%s'\n", relpath); + return -ENOENT; + } + + /* Allocate a container to hold the task and attribute selection */ + + priv = (FAR struct dvfs_file_s *)kmm_zalloc(sizeof(struct dvfs_file_s)); + if (!priv) + { + ferr("ERROR: Failed to allocate file attributes\n"); + return -ENOMEM; + } + + /* Save the index as the open-specific state in filep->f_priv */ + + filep->f_priv = (FAR void *)priv; + return OK; +} + +/**************************************************************************** + * Name: dvfs_close + ****************************************************************************/ + +static int dvfs_close(FAR struct file *filep) +{ + FAR struct dvfs_file_s *priv; + + /* Recover our private data from the struct file instance */ + + priv = (FAR struct dvfs_file_s *)filep->f_priv; + DEBUGASSERT(priv); + + /* Release the file attributes structure */ + + kmm_free(priv); + filep->f_priv = NULL; + return OK; +} + +/**************************************************************************** + * Name: dvfs_read + ****************************************************************************/ + +static ssize_t dvfs_read(FAR struct file *filep, FAR char *buffer, + size_t buflen) +{ + FAR struct dvfs_file_s *priv; + size_t linesize; + size_t copysize; + size_t remaining; + size_t totalsize; + off_t offset = filep->f_pos; + + finfo("buffer=%p buflen=%d\n", buffer, (int)buflen); + + priv = (FAR struct dvfs_file_s *)filep->f_priv; + DEBUGASSERT(priv); + + remaining = buflen; + totalsize = 0; + + linesize = snprintf(priv->line, + DVFS_LINELEN, + "cur_freq %d \n", g_dvfs_cur_freq); + copysize = procfs_memcpy(priv->line, linesize, buffer, remaining, &offset); + totalsize += copysize; + buffer += copysize; + remaining -= copysize; + + if (totalsize >= buflen) + { + return totalsize; + } + + linesize = snprintf(priv->line, + DVFS_LINELEN, + "enable %d \n", g_dvfs_enabled); + copysize = procfs_memcpy(priv->line, linesize, buffer, remaining, &offset); + totalsize += copysize; + + /* Update the file offset */ + + if (totalsize > 0) + { + filep->f_pos += totalsize; + } + + return totalsize; +} + +/**************************************************************************** + * Name: procfs_write + ****************************************************************************/ + +static ssize_t dvfs_write(FAR struct file *filep, FAR const char *buffer, + size_t buflen) +{ + char line[DVFS_LINELEN]; + char cmd[16]; + int n; + int freq; + int enable; + + n = MIN(buflen, DVFS_LINELEN - 1); + strncpy(line, buffer, n); + line[n] = '\0'; + + n = MIN(strcspn(line, " "), sizeof(cmd) - 1); + strncpy(cmd, line, n); + cmd[n] = '\0'; + + if (0 == strcmp(cmd, "cur_freq")) + { + freq = atoi(line + (n + 1)); + (void)lc823450_dvfs_set_freq(freq); + } + else if (0 == strcmp(cmd, "enable")) + { + enable = atoi(line + (n + 1)); + g_dvfs_enabled = enable; + } + else + { + printf("%s not supported.\n", cmd); + } + + return buflen; +} + +/**************************************************************************** + * Name: dvfs_dup + ****************************************************************************/ + +static int dvfs_dup(FAR const struct file *oldp, FAR struct file *newp) +{ + FAR struct dvfs_file_s *oldpriv; + FAR struct dvfs_file_s *newpriv; + + finfo("Dup %p->%p\n", oldp, newp); + + /* Recover our private data from the old struct file instance */ + + oldpriv = (FAR struct dvfs_file_s *)oldp->f_priv; + DEBUGASSERT(oldpriv); + + /* Allocate a new container to hold the task and attribute selection */ + + newpriv = (FAR struct dvfs_file_s *)kmm_zalloc(sizeof(struct dvfs_file_s)); + if (!newpriv) + { + ferr("ERROR: Failed to allocate file attributes\n"); + return -ENOMEM; + } + + /* The copy the file attributes from the old attributes to the new */ + + memcpy(newpriv, oldpriv, sizeof(struct dvfs_file_s)); + + /* Save the new attributes in the new file structure */ + + newp->f_priv = (FAR void *)newpriv; + return OK; +} + +/**************************************************************************** + * Name: dvfs_stat + ****************************************************************************/ + +static int dvfs_stat(const char *relpath, struct stat *buf) +{ + if (strcmp(relpath, "dvfs") != 0) + { + ferr("ERROR: relpath is '%s'\n", relpath); + return -ENOENT; + } + + buf->st_mode = + S_IFREG | + S_IROTH | S_IWOTH | + S_IRGRP | S_IWGRP | + S_IRUSR | S_IWUSR; + + buf->st_size = 0; + buf->st_blksize = 0; + buf->st_blocks = 0; + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: dvfs_procfs_register + ****************************************************************************/ + +int dvfs_procfs_register(void) +{ + return procfs_register(&g_procfs_dvfs); +} diff --git a/arch/arm/src/lc823450/lc823450_pwm.h b/arch/arm/src/lc823450/lc823450_pwm.h new file mode 100644 index 0000000000000000000000000000000000000000..1c364f86e255a38c15df1a2028e08ed749101589 --- /dev/null +++ b/arch/arm/src/lc823450/lc823450_pwm.h @@ -0,0 +1,115 @@ +/**************************************************************************** + * arch/arm/src/lc823450/lc823450_pwm.h + * + * Copyright (C) 2014-2017 Sony Corporation. All rights reserved. + * Author: Nobutaka Toyoshima + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LC823450_LC823450_PWM_H +#define __ARCH_ARM_SRC_LC823450_LC823450_PWM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Addresses *******************************************************/ + +#define LC823450_MTM0_REGBASE 0x40043000 +#define LC823450_MTM1_REGBASE 0x40044000 + +#define LC823450_MTM_OPR 0x00 +#define LC823450_MTM_SYNC 0x04 +#define LC823450_MTM_PWM 0x08 +#define LC823450_MTM_FCTL 0x0c + +#define LC823450_MTM_0CTL 0x40 +#define LC823450_MTM_0IOCL 0x44 +#define LC823450_MTM_0STS 0x4C +#define LC823450_MTM_0CNT 0x50 +#define LC823450_MTM_0A 0x54 +#define LC823450_MTM_0B 0x58 +#define LC823450_MTM_0SOL 0x5C +#define LC823450_MTM_0BA 0x60 +#define LC823450_MTM_0BB 0x64 +#define LC823450_MTM_0PSCL 0x68 +#define LC823450_MTM_0TIER 0x6C +#define LC823450_MTM_0TISR 0x70 + +#define LC823450_MTM_1CTL 0x80 +#define LC823450_MTM_1IOCL 0x84 +#define LC823450_MTM_1STS 0x8C +#define LC823450_MTM_1CNT 0x90 +#define LC823450_MTM_1A 0x94 +#define LC823450_MTM_1B 0x98 +#define LC823450_MTM_1SOL 0x9C +#define LC823450_MTM_1BA 0xA0 +#define LC823450_MTM_1BB 0xA4 +#define LC823450_MTM_1PSCL 0xA8 +#define LC823450_MTM_1TIER 0xAC +#define LC823450_MTM_1TISR 0xB0 + +/* PWM Identifier ***********************************************************/ + +#define LC823450_PWMTIMER0_CH0 0 +#define LC823450_PWMTIMER0_CH1 1 +#define LC823450_PWMTIMER1_CH0 2 +#define LC823450_PWMTIMER1_CH1 3 + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +EXTERN FAR struct pwm_lowerhalf_s *lc823450_pwminitialize(int timer); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_LC823450_LC823450_PWM_H */ diff --git a/arch/arm/src/lc823450/lc823450_serial.c b/arch/arm/src/lc823450/lc823450_serial.c index eba588f38ba8a2c1ac9570be19b35814e9cce8fb..5ddeb324dfeffe618828137bbee40b611fdbf644 100644 --- a/arch/arm/src/lc823450/lc823450_serial.c +++ b/arch/arm/src/lc823450/lc823450_serial.c @@ -1007,7 +1007,11 @@ static bool up_txready(struct uart_dev_s *dev) } #endif /* CONFIG_DEV_CONSOLE_SWITCH */ +#ifndef CONFIG_SMP return ((up_serialin(priv, UART_USR) & UART_USR_TXFULL) == 0); +#else + return (UART_USFS_TXFF_LV(up_serialin(priv, UART_USFS)) <= 1); +#endif } /**************************************************************************** diff --git a/arch/arm/src/lc823450/lc823450_start.c b/arch/arm/src/lc823450/lc823450_start.c index a52bf2cf1fbb877c050a46d22d512de3cf2dbb1f..089f21eaee6da39d618d8aff12105103ccf768f8 100644 --- a/arch/arm/src/lc823450/lc823450_start.c +++ b/arch/arm/src/lc823450/lc823450_start.c @@ -251,17 +251,20 @@ void __start(void) #else /* CONFIG_SPIFLASH_BOOT */ /* vector offset */ -#ifdef CONFIG_IPL2 +#ifdef CONFIG_LC823450_IPL2 putreg32(0x02000e00, 0xe000ed08); putreg32(0x0, 0x40080008); /* XXX: remap disable */ -#else /* CONFIG_IPL2 */ +#else /* CONFIG_LC823450_IPL2 */ putreg32(0x02040000, 0xe000ed08); -#endif /* CONFIG_IPL2 */ -#endif /* CONFIG_SPIFLASH_BOOT */ +#endif /* CONFIG_LC823450_IPL2 */ +#endif /* CONFIG_LC823450_SPIFLASH_BOOT */ - /* Mutex enable */ + /* Enable Mutex */ + /* NOTE: modyfyreg32() can not be used because it might use spin_lock */ - modifyreg32(MRSTCNTBASIC, 0, MRSTCNTBASIC_MUTEX_RSTB); + uint32_t val = getreg32(MRSTCNTBASIC); + val |= MRSTCNTBASIC_MUTEX_RSTB; + putreg32(val, MRSTCNTBASIC); /* Configure the uart so that we can get debug output as soon as possible */ @@ -273,7 +276,7 @@ void __start(void) /* IPL2 don't change mux */ -#ifdef CONFIG_IPL2 +#ifdef CONFIG_LC823450_IPL2 /* GPIO2F out High in IPL2 */ modifyreg32(MCLKCNTAPB, 0, MCLKCNTAPB_PORT2_CLKEN); @@ -286,9 +289,9 @@ void __start(void) modifyreg32(PMDCNT5, 0, 3 << 14); #endif /* CONFIG_DEBUG */ -#else /* CONFIG_IPL2 */ +#else /* CONFIG_LC823450_IPL2 */ up_init_default_mux(); -#endif /* CONFIG_IPL2 */ +#endif /* CONFIG_LC823450_IPL2 */ showprogress('B'); @@ -326,9 +329,9 @@ void __start(void) showprogress('F'); -#ifndef CONFIG_IPL2 +#ifndef CONFIG_LC823450_IPL2 sinfo("icx_boot_reason = 0x%x\n", icx_boot_reason); -#endif /* CONFIG_IPL2 */ +#endif /* CONFIG_LC823450_IPL2 */ #ifdef CONFIG_POWERBUTTON_LDOWN if (icx_boot_reason & ICX_BOOT_REASON_POWERBUTTON) diff --git a/arch/arm/src/lc823450/lc823450_syscontrol.c b/arch/arm/src/lc823450/lc823450_syscontrol.c index 35d18b2a2a6c38a3a70772fbddd49cfda0d56f64..82e6c2ee01885489de549b52033781fe0b4087d2 100644 --- a/arch/arm/src/lc823450/lc823450_syscontrol.c +++ b/arch/arm/src/lc823450/lc823450_syscontrol.c @@ -144,7 +144,7 @@ void mod_stby_regs(uint32_t enabits, uint32_t disbits) void up_enable_clk(enum clock_e clk) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(); ASSERT(clk < LC823450_CLOCK_NUM); @@ -154,7 +154,7 @@ void up_enable_clk(enum clock_e clk) 0, lc823450_clocks[clk].regmask); } - leave_critical_section(flags); + spin_unlock_irqrestore(flags); } /**************************************************************************** @@ -164,7 +164,7 @@ void up_enable_clk(enum clock_e clk) void up_disable_clk(enum clock_e clk) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(); ASSERT(clk < LC823450_CLOCK_NUM); @@ -181,7 +181,7 @@ void up_disable_clk(enum clock_e clk) lc823450_clocks[clk].count = 0; } - leave_critical_section(flags); + spin_unlock_irqrestore(flags); } /**************************************************************************** diff --git a/arch/arm/src/lc823450/lc823450_syscontrol.h b/arch/arm/src/lc823450/lc823450_syscontrol.h index 509f2c3b9f278c3eec59944e0b1d60f82ed5b53f..d31edf4eda6337e4c947224f89c3ae1ca979864d 100644 --- a/arch/arm/src/lc823450/lc823450_syscontrol.h +++ b/arch/arm/src/lc823450/lc823450_syscontrol.h @@ -108,6 +108,9 @@ #define MCLKCNTEXT1_PTM1C_CLKEN (1 << 29) #define MCLKCNTEXT1_PTM2C_CLKEN (1 << 30) +#define MCLKCNTEXT3 (LC823450_SYSCONTROL_REGBASE + 0x0108) +#define MCLKCNTEXT3_AUDIOBUF_CLKEN (1 << 0) + #define MCLKCNTEXT4 (LC823450_SYSCONTROL_REGBASE + 0x010c) #define MCLKCNTEXT4_SDRAMC_CLKEN0 (1 << 0) #define MCLKCNTEXT4_SDRAMC_CLKEN1 (1 << 1) @@ -156,6 +159,9 @@ #define MRSTCNTEXT1_SDIF2_RSTB (1 << 10) #define MRSTCNTEXT1_MSIF_RSTB (1 << 11) +#define MRSTCNTEXT3 (LC823450_SYSCONTROL_REGBASE + 0x011c) +#define MRSTCNTEXT3_AUDIOBUF_RSTB (1 << 0) + #define MRSTCNTEXT4 (LC823450_SYSCONTROL_REGBASE + 0x0120) #define MRSTCNTEXT4_SDRAMC_RSTB (1 << 0) diff --git a/arch/arm/src/lc823450/lc823450_testset.c b/arch/arm/src/lc823450/lc823450_testset.c index 2093b42f404e37852247d50b733cfb250ff88f5e..826150285ef80d289e1ab15d53679a028e8e7f0f 100644 --- a/arch/arm/src/lc823450/lc823450_testset.c +++ b/arch/arm/src/lc823450/lc823450_testset.c @@ -95,12 +95,15 @@ spinlock_t up_testset(volatile FAR spinlock_t *lock) } while (getreg32(MUTEX_REG_MUTEX0) != val); + SP_DMB(); + ret = *lock; if (ret == SP_UNLOCKED) { *lock = SP_LOCKED; } + SP_DMB(); val = (up_cpu_index() << 16) | 0x0; putreg32(val, MUTEX_REG_MUTEX0); diff --git a/arch/arm/src/lc823450/lc823450_timerisr.c b/arch/arm/src/lc823450/lc823450_timerisr.c index 1357219b262c5389c9c42bd1ca100680d928f406..1e89f795273220c8062050a3d3c17ec0b88b9cc1 100644 --- a/arch/arm/src/lc823450/lc823450_timerisr.c +++ b/arch/arm/src/lc823450/lc823450_timerisr.c @@ -62,6 +62,13 @@ #include "lc823450_clockconfig.h" #include "lc823450_serial.h" +#ifdef CONFIG_DVFS +# include "lc823450_dvfs2.h" +#endif + +#if !defined(CONFIG_LC823450_MTM0_TICK) && defined (CONFIG_DVFS) +# error "Use CONFIG_LC823450_MTM0_TICK=y" +#endif /**************************************************************************** * Pre-processor Definitions @@ -109,6 +116,11 @@ # define rMT30CNT (LC823450_MTM3_REGBASE + LC823450_MTM_0CNT) #endif /* CONFIG_PROFILE */ +#ifndef container_of +# define container_of(ptr, type, member) \ + ((type *)((void *)(ptr) - offsetof(type, member))) +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -175,7 +187,7 @@ static void hrt_queue_refresh(void) struct hrt_s *tmp; irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(); elapsed = (uint64_t)getreg32(rMT20CNT) * (1000 * 1000) * 10 / XT1OSC_CLK; for (pent = hrt_timer_queue.head; pent; pent = dq_next(pent)) @@ -193,7 +205,9 @@ cont: if (tmp->usec <= 0) { dq_rem(pent, &hrt_timer_queue); + spin_unlock_irqrestore(flags); nxsem_post(&tmp->sem); + flags = spin_lock_irqsave(); goto cont; } else @@ -202,12 +216,12 @@ cont: } } - leave_critical_section(flags); + spin_unlock_irqrestore(flags); } #endif /**************************************************************************** - * Name: hrt_queue_refresh + * Name: hrt_usleep_setup ****************************************************************************/ #ifdef CONFIG_HRT_TIMER @@ -217,7 +231,7 @@ static void hrt_usleep_setup(void) struct hrt_s *head; irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(); head = container_of(hrt_timer_queue.head, struct hrt_s, ent); if (head == NULL) { @@ -225,7 +239,7 @@ static void hrt_usleep_setup(void) modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2C_CLKEN, 0x0); modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2_CLKEN, 0x0); - leave_critical_section(flags); + spin_unlock_irqrestore(flags); return; } @@ -244,12 +258,10 @@ static void hrt_usleep_setup(void) putreg32(0, rMT20CNT); /* counter */ putreg32(count, rMT20A); /* AEVT counter */ - up_enable_irq(LC823450_IRQ_MTIMER20); - /* Enable MTM2-Ch0 */ putreg32(1, rMT2OPR); - leave_critical_section(flags); + spin_unlock_irqrestore(flags); } #endif @@ -273,6 +285,10 @@ static int hrt_interrupt(int irq, FAR void *context, FAR void *arg) return OK; } +/**************************************************************************** + * Name: hrt_usleep_add + ****************************************************************************/ + static void hrt_usleep_add(struct hrt_s *phrt) { dq_entry_t *pent; @@ -284,7 +300,7 @@ static void hrt_usleep_add(struct hrt_s *phrt) hrt_queue_refresh(); - flags = enter_critical_section(); + flags = spin_lock_irqsave(); /* add phrt to hrt_timer_queue */ @@ -305,7 +321,7 @@ static void hrt_usleep_add(struct hrt_s *phrt) dq_addlast(&phrt->ent, &hrt_timer_queue); } - leave_critical_section(flags); + spin_unlock_irqrestore(flags); hrt_usleep_setup(); } @@ -350,21 +366,20 @@ int up_timerisr(int irq, uint32_t *regs, FAR void *arg) /* Process timer interrupt */ #ifdef CONFIG_DVFS - extern void lc823450_dvfs_tick_callback(void); - lc823450_dvfs_tick_callback(); + lc823450_dvfs_tick_callback(); #endif #ifdef CONFIG_LC823450_MTM0_TICK - /* Clear the interrupt (BEVT) */ + /* Clear the interrupt (BEVT) */ - putreg32(1 << 1, rMT00STS); + putreg32(1 << 1, rMT00STS); #endif - sched_process_timer(); + sched_process_timer(); #ifdef CONFIG_LCA_SOUNDSKIP_CHECK - extern void lca_check_soundskip(void); - lca_check_soundskip(); + extern void lca_check_soundskip(void); + lca_check_soundskip(); #endif #ifdef CHECK_INTERVAL @@ -375,7 +390,7 @@ int up_timerisr(int irq, uint32_t *regs, FAR void *arg) hsuart_wdtimer(); #endif /* CONFIG_HSUART */ - return 0; + return 0; } /**************************************************************************** @@ -474,6 +489,8 @@ void arm_timer_initialize(void) modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2_CLKEN, 0); (void)irq_attach(LC823450_IRQ_MTIMER20, (xcpt_t)hrt_interrupt, NULL); + up_enable_irq(LC823450_IRQ_MTIMER20); + #endif /* CONFIG_HRT_TIMER */ #ifdef CONFIG_PROFILE @@ -619,7 +636,7 @@ int up_hr_gettime(FAR struct timespec *tp) irqstate_t flags; uint64_t f; - flags = enter_critical_section(); + flags = spin_lock_irqsave(); /* Get the elapsed time */ @@ -630,7 +647,7 @@ int up_hr_gettime(FAR struct timespec *tp) f = up_get_timer_fraction(); elapsed += f; - leave_critical_section(flags); + spin_unlock_irqrestore(flags); tmrinfo("elapsed = %lld \n", elapsed); diff --git a/arch/arm/src/lc823450/lc823450_usbdev.c b/arch/arm/src/lc823450/lc823450_usbdev.c index f8c0a09787c91ba72470597e5a4e9b7bb188e408..27e804fb9714b7a928d4f94d2b180001ae60a388 100644 --- a/arch/arm/src/lc823450/lc823450_usbdev.c +++ b/arch/arm/src/lc823450/lc823450_usbdev.c @@ -487,7 +487,7 @@ static int lc823450_epclearreq(struct usbdev_ep_s *ep) struct lc823450_ep_s *privep = (struct lc823450_ep_s *)ep; irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(); while (privep->req_q.tail) { struct usbdev_req_s *req; @@ -504,7 +504,7 @@ static int lc823450_epclearreq(struct usbdev_ep_s *ep) req->callback(ep, req); } - leave_critical_section(flags); + spin_unlock_irqrestore(flags); return 0; } @@ -666,27 +666,27 @@ static int lc823450_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if (privep->epphy == 0) { - flags = enter_critical_section(); + flags = spin_lock_irqsave(); req->xfrd = epbuf_write(privep->epphy, req->buf, req->len); - leave_critical_section(flags); + spin_unlock_irqrestore(flags); req->callback(ep, req); } else if (privep->in) { /* Send packet requst from function driver */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(); if ((getreg32(USB_EPCOUNT(privep->epphy * 2)) & USB_EPCOUNT_PHYCNT_MASK) >> USB_EPCOUNT_PHYCNT_SHIFT || privep->req_q.tail) { sq_addfirst(&privreq->q_ent, &privep->req_q); /* non block */ - leave_critical_section(flags); + spin_unlock_irqrestore(flags); } else { - leave_critical_section(flags); + spin_unlock_irqrestore(flags); req->xfrd = epbuf_write(privep->epphy, req->buf, req->len); req->callback(ep, req); } @@ -695,9 +695,9 @@ static int lc823450_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { /* receive packet buffer from function driver */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(); sq_addfirst(&privreq->q_ent, &privep->req_q); /* non block */ - leave_critical_section(flags); + spin_unlock_irqrestore(flags); lc823450_epack(privep->epphy, 1); } @@ -716,10 +716,13 @@ static int lc823450_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { struct lc823450_req_s *privreq = (struct lc823450_req_s *)req; struct lc823450_ep_s *privep = (struct lc823450_ep_s *)ep; + irqstate_t flags; /* remove request from req_queue */ + flags = spin_lock_irqsave(); sq_remafter(&privreq->q_ent, &privep->req_q); + spin_unlock_irqrestore(flags); return 0; } @@ -738,7 +741,7 @@ static int lc823450_epstall(struct usbdev_ep_s *ep, bool resume) /* STALL or RESUME the endpoint */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(); usbtrace(resume ? TRACE_EPRESUME : TRACE_EPSTALL, privep->epphy); if (resume) @@ -752,7 +755,7 @@ static int lc823450_epstall(struct usbdev_ep_s *ep, bool resume) epcmd_write(privep->epphy, USB_EPCMD_STALL_SET | USB_EPCMD_TGL_SET); } - leave_critical_section(flags); + spin_unlock_irqrestore(flags); return OK; } @@ -761,11 +764,11 @@ void up_epignore_clear_stall(struct usbdev_ep_s *ep, bool ignore) { struct lc823450_ep_s *privep = (struct lc823450_ep_s *)ep; irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(); privep->ignore_clear_stall = ignore; - leave_critical_section(flags); + spin_unlock_irqrestore(flags); } #endif /* CONFIG_USBMSC_IGNORE_CLEAR_STALL */ @@ -922,7 +925,7 @@ static void usb_suspend_work_func(void *arg) } #endif - flags = enter_critical_section(); + flags = spin_lock_irqsave(); if (getreg32(USB_DEVS) & USB_DEVS_SUSPEND) { uinfo("USB BUS SUSPEND\n"); @@ -936,7 +939,7 @@ static void usb_suspend_work_func(void *arg) g_usbsuspend = 1; wake_unlock(&priv->wlock); } - leave_critical_section(flags); + spin_unlock_irqrestore(flags); } #endif @@ -1251,6 +1254,9 @@ static void subintr_epin(uint8_t epnum, struct lc823450_ep_s *privep) { /* Send packet done */ + irqstate_t flags; + flags = spin_lock_irqsave(); + if (privep->req_q.tail) { struct usbdev_req_s *req; @@ -1259,6 +1265,9 @@ static void subintr_epin(uint8_t epnum, struct lc823450_ep_s *privep) /* Dequeue from TXQ */ q_ent = sq_remlast(&privep->req_q); + + spin_unlock_irqrestore(flags); + req = &container_of(q_ent, struct lc823450_req_s, q_ent)->req; /* Write to TX FIFO */ @@ -1272,6 +1281,7 @@ static void subintr_epin(uint8_t epnum, struct lc823450_ep_s *privep) } else { + spin_unlock_irqrestore(flags); epcmd_write(epnum, USB_EPCMD_EMPTY_CLR); } } @@ -1288,6 +1298,9 @@ static void subintr_epout(uint8_t epnum, struct lc823450_ep_s *privep) { /* Packet receive from host */ + irqstate_t flags; + flags = spin_lock_irqsave(); + if (privep->req_q.tail) { struct usbdev_req_s *req; @@ -1296,6 +1309,7 @@ static void subintr_epout(uint8_t epnum, struct lc823450_ep_s *privep) /* Dequeue from Reqbuf poll */ q_ent = sq_remlast(&privep->req_q); + req = &container_of(q_ent, struct lc823450_req_s, q_ent)->req; if (privep->req_q.tail == NULL) { @@ -1304,6 +1318,8 @@ static void subintr_epout(uint8_t epnum, struct lc823450_ep_s *privep) lc823450_epack(epnum, 0); } + spin_unlock_irqrestore(flags); + /* PIO */ epcmd_write(epnum, USB_EPCMD_READY_CLR); @@ -1315,6 +1331,7 @@ static void subintr_epout(uint8_t epnum, struct lc823450_ep_s *privep) } else { + spin_unlock_irqrestore(flags); uinfo("REQ Buffer Exhault\n"); epcmd_write(epnum, USB_EPCMD_READY_CLR); } @@ -1630,7 +1647,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) * canceled while the class driver is still bound. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(); #ifdef CONFIG_WAKELOCK /* cancel USB suspend work */ @@ -1666,7 +1683,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) pm_unregister(&pm_cb); #endif /* CONFIG_PM */ - leave_critical_section(flags); + spin_unlock_irqrestore(flags); #ifdef CONFIG_LC823450_LSISTBY /* disable USB */ @@ -1915,7 +1932,7 @@ static void usbdev_pmnotify(struct pm_callback_s *cb, enum pm_state_e pmstate) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(); switch (pmstate) { @@ -1936,6 +1953,6 @@ static void usbdev_pmnotify(struct pm_callback_s *cb, enum pm_state_e pmstate) default: break; } - leave_critical_section(flags); + spin_unlock_irqrestore(flags); } #endif diff --git a/arch/arm/src/lpc11xx/lpc11_start.c b/arch/arm/src/lpc11xx/lpc11_start.c index 917cdeae275e6a5ef705a3e14e67293309b684c6..51dac5d00bf21e54159142dc6ebb371a25ea027f 100644 --- a/arch/arm/src/lpc11xx/lpc11_start.c +++ b/arch/arm/src/lpc11xx/lpc11_start.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc11xx/lpc11_start.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -44,7 +44,6 @@ #include #include -#include #include "up_arch.h" #include "up_internal.h" @@ -57,6 +56,8 @@ # include "nvic.h" #endif +#include "lpc11_start.h" + /**************************************************************************** * Private Definitions ****************************************************************************/ diff --git a/arch/arm/src/lpc11xx/lpc11_start.h b/arch/arm/src/lpc11xx/lpc11_start.h new file mode 100644 index 0000000000000000000000000000000000000000..ebace6f72c8546ede93d7ad3653d0ec15a624ded --- /dev/null +++ b/arch/arm/src/lpc11xx/lpc11_start.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/lpc11xx/lpc11_start.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_START_H +#define __ARCH_ARM_SRC_LPC11XX_LPC11_START_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc11_boardinitialize + * + * Description: + * All LPC11xx architectures must provide the following entry point. This entry + * point is called early in the initialization -- after clocking and memory have + * been configured but before caches have been enabled and before any devices have + * been initialized. + * + ************************************************************************************/ + +void lpc11_boardinitialize(void); + +#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_START_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.c b/arch/arm/src/lpc17xx/lpc17_gpdma.c index 7825f2ce0d0765db2fa2628e2dfb4134dfe54106..a9ae9443190bbd6526aa9d4e225300722154c127 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpdma.c +++ b/arch/arm/src/lpc17xx/lpc17_gpdma.c @@ -272,10 +272,11 @@ static int gpdma_interrupt(int irq, FAR void *context, FAR void *arg) * Name: up_dmainitialize * * Description: - * Initialize the GPDMA subsystem. + * Initialize the GPDMA subsystem. Called from up_initialize() early in the + * boot-up sequence. Prototyped in up_internal.h. * * Returned Value: - * Zero on success; A negated errno value on failure. + * None * ****************************************************************************/ diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.h b/arch/arm/src/lpc17xx/lpc17_gpdma.h index a7c0d7009ccbdef0d522665bd9540cf6e3f25091..7953bda182aa255310edeb5e0bf5972553de6f4a 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpdma.h +++ b/arch/arm/src/lpc17xx/lpc17_gpdma.h @@ -140,19 +140,6 @@ EXTERN volatile uint8_t g_dma_inprogress; * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: up_dmainitialize - * - * Description: - * Initialize the GPDMA subsystem (also prototyped in up_internal.h). - * - * Returned Value: - * Zero on success; A negated errno value on failure. - * - ****************************************************************************/ - -void weak_function up_dmainitialize(void); - /**************************************************************************** * Name: lpc17_dmaconfigure * diff --git a/arch/arm/src/lpc17xx/lpc17_lcd.c b/arch/arm/src/lpc17xx/lpc17_lcd.c index dde2d50ae039f2d7292a1f3a2f64ad54f9ae00f8..90332fc12e9d072bde96e8e135d4deea28650b12 100644 --- a/arch/arm/src/lpc17xx/lpc17_lcd.c +++ b/arch/arm/src/lpc17xx/lpc17_lcd.c @@ -483,7 +483,10 @@ int up_fbinitialize(int display) putreg32(regval, LPC17_SYSCON_MATRIXARB); /* Configure pins */ - /* Video data */ + /* Video data: + * + * REVISIT: The conditional logic is not correct here. See arch/arm/src/lpc54xx/lpc454_lcd.c + */ lcdinfo("Configuring pins\n"); diff --git a/arch/arm/src/lpc17xx/lpc17_start.c b/arch/arm/src/lpc17xx/lpc17_start.c index 3a0ae1d70554331623ad0447b8a4df2949941ed5..88b4f8d69e9f7073a5acdfa390ebebefc9772a8c 100644 --- a/arch/arm/src/lpc17xx/lpc17_start.c +++ b/arch/arm/src/lpc17xx/lpc17_start.c @@ -45,7 +45,6 @@ #include #include -#include #include "up_arch.h" #include "up_internal.h" @@ -58,17 +57,7 @@ # include "nvic.h" #endif -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ +#include "lpc17_start.h" /**************************************************************************** * Private Functions diff --git a/arch/arm/src/lpc17xx/lpc17_start.h b/arch/arm/src/lpc17xx/lpc17_start.h new file mode 100644 index 0000000000000000000000000000000000000000..9b038be3738ceb7a257cc49ac26defb0728d4cec --- /dev/null +++ b/arch/arm/src/lpc17xx/lpc17_start.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_start.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_START_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_START_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc17_boardinitialize + * + * Description: + * All LPC17xx architectures must provide the following entry point. This entry + * point is called early in the initialization -- after clocking and memory have + * been configured but before caches have been enabled and before any devices have + * been initialized. + * + ************************************************************************************/ + +void lpc17_boardinitialize(void); + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_START_H */ diff --git a/arch/arm/src/lpc31xx/lpc31_boot.c b/arch/arm/src/lpc31xx/lpc31_boot.c index 5c106ae34d8aa70271797fd0352379c74bea4377..8578cef04f9f10457fa400f7afe36c7b8dc418e8 100644 --- a/arch/arm/src/lpc31xx/lpc31_boot.c +++ b/arch/arm/src/lpc31xx/lpc31_boot.c @@ -40,25 +40,20 @@ #include #include -#include - #include "chip.h" #include "arm.h" #include "up_internal.h" #include "up_arch.h" -#include "lpc31_syscreg.h" -#include "lpc31_cgudrvr.h" -#include "lpc31.h" - #ifdef CONFIG_PAGING # include # include "pg_macros.h" #endif -/************************************************************************************ - * Private Types - ************************************************************************************/ +#include "lpc31_syscreg.h" +#include "lpc31_cgudrvr.h" +#include "lpc31.h" +#include "lpc31_boot.h" /************************************************************************************ * Private Types diff --git a/arch/arm/src/lpc31xx/lpc31_boot.h b/arch/arm/src/lpc31xx/lpc31_boot.h new file mode 100644 index 0000000000000000000000000000000000000000..cfa096d9b094470dab8f36db602eeec09dab472c --- /dev/null +++ b/arch/arm/src/lpc31xx/lpc31_boot.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/lpc31xx/lpc31_boot.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_BOOT_H +#define __ARCH_ARM_SRC_LPC31XX_LPC31_BOOT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc31_boardinitialize + * + * Description: + * All LPC31xx architectures must provide the following entry point. This entry + * point is called early in the initialization -- after clocking and memory have + * been configured but before caches have been enabled and before any devices have + * been initialized. + * + ************************************************************************************/ + +void lpc31_boardinitialize(void); + +#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_BOOT_H */ diff --git a/arch/arm/src/lpc43xx/Kconfig b/arch/arm/src/lpc43xx/Kconfig index db16b30626ab41c2ac25027fe47e645344c36db0..59c927604b43975e88f97bd4ad0acdd8425ce854 100644 --- a/arch/arm/src/lpc43xx/Kconfig +++ b/arch/arm/src/lpc43xx/Kconfig @@ -142,7 +142,7 @@ config LPC43_BOOT_FLASHA bool "Running in internal FLASHA" config LPC43_BOOT_FLASHB - bool "Running in internal FLASHA" + bool "Running in internal FLASHB" config LPC43_BOOT_CS0FLASH bool "Running in external FLASH CS0" @@ -172,11 +172,11 @@ config LPC43_ATIMER bool "Alarm timer" default n -config LPC43_CAN1 - bool "C_CAN1" +config LPC43_CAN0 + bool "C_CAN0" default n -config LPC43_CAN2 +config LPC43_CAN1 bool "C_CAN1" default n @@ -254,6 +254,8 @@ config LPC43_SCT config LPC43_SDMMC bool "SD/MMC" default n + select ARCH_HAVE_SDIO + depends on EXPERIMENTAL config LPC43_SPI bool "SPI" @@ -338,19 +340,6 @@ config LPC43_WWDT endmenu # LPC43xx Peripheral Support -menu "ADC driver options" - depends on LPC43_ADC0 || LPC43_ADC1 - -config ADC0_MASK - hex "ADC0 mask" - default 0x01 - -config ADC0_FREQ - int "ADC0 frequency" - default 4500000 - -endmenu # ADC driver options - config LPC43_GPIO_IRQ bool "GPIO interrupt support" default n @@ -509,6 +498,32 @@ endif # LCP43_EXTSDRAM3 endmenu # External Memory Configuration +menu "SD/MMC Configuration" + depends on LPC43_SDMMC + +config LPC43_SDMMC_PWRCTRL + bool "Power-enable pin" + default n + ---help--- + Select if the board supports a power-enable pin that must be selected + to provide power to the SD card. + +config LPC43_SDMMC_DMA + bool "Support DMA data transfers" + default y + select SDIO_DMA + ---help--- + Support DMA data transfers. + +config LPC43_SDMMC_REGDEBUG + bool "Register level debug" + default n + depends on DEBUG_MEMCARD_INFO + ---help--- + Output detailed register-level SD/MMC debug information. + +endmenu # SD/MMC Configuration + menu "Ethernet MAC configuration" depends on LPC43_ETHERNET @@ -672,6 +687,19 @@ config LPC43_ETHERNET_REGDEBUG endmenu # Ethernet MAC configuration +menu "ADC driver options" + depends on LPC43_ADC0 || LPC43_ADC1 + +config ADC0_MASK + hex "ADC0 mask" + default 0x01 + +config ADC0_FREQ + int "ADC0 frequency" + default 4500000 + +endmenu # ADC driver options + menu "RS-485 Configuration" if LPC43_USART0 diff --git a/arch/arm/src/lpc43xx/Make.defs b/arch/arm/src/lpc43xx/Make.defs index d68a19635b31dea6de0fe4bfdb26dddbf2ebfc30..d5bd89123723dec372537e7e7dadd7e137ee7731 100644 --- a/arch/arm/src/lpc43xx/Make.defs +++ b/arch/arm/src/lpc43xx/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # arch/arm/src/lpc43xx/Make.defs # -# Copyright (C) 2012-2015 Gregory Nutt. All rights reserved. +# Copyright (C) 2012-2015, 2017 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -112,6 +112,14 @@ ifeq ($(CONFIG_LPC43_GPIO_IRQ),y) CHIP_CSRCS += lpc43_gpioint.c endif +ifeq ($(CONFIG_LPC43_WWDT),y) +CHIP_CSRCS += lpc43_wwdt.c +endif + +ifeq ($(CONFIG_LPC43_SDMMC),y) +CHIP_CSRCS += lpc43_sdmmc.c +endif + ifeq ($(CONFIG_LPC43_ETHERNET),y) CHIP_CSRCS += lpc43_ethernet.c endif @@ -122,15 +130,11 @@ endif ifeq ($(CONFIG_LPC43_SPI),y) CHIP_CSRCS += lpc43_spi.c -else -ifeq ($(CONFIG_LPC43_SSP0),y) +else ifeq ($(CONFIG_LPC43_SSP0),y) CHIP_CSRCS += lpc43_spi.c -else -ifeq ($(CONFIG_LPC43_SSP1),y) +else ifeq ($(CONFIG_LPC43_SSP1),y) CHIP_CSRCS += lpc43_spi.c endif -endif -endif ifeq ($(CONFIG_LPC43_SPIFI),y) CHIP_CSRCS += lpc43_spifi.c @@ -138,11 +142,9 @@ endif ifeq ($(CONFIG_LPC43_SSP0),y) CHIP_CSRCS += lpc43_ssp.c -else -ifeq ($(CONFIG_LPC43_SSP1),y) +else ifeq ($(CONFIG_LPC43_SSP1),y) CHIP_CSRCS += lpc43_ssp.c endif -endif ifeq ($(CONFIG_LPC43_TIMER),y) CHIP_CSRCS += lpc43_timer.c @@ -152,28 +154,30 @@ ifeq ($(CONFIG_LPC43_RIT),y) CHIP_CSRCS += lpc43_rit.c endif +ifeq ($(CONFIG_LPC43_RTC),y) +CHIP_CSRCS += lpc43_rtc.c +endif + ifeq ($(CONFIG_LPC43_I2C0),y) CHIP_CSRCS += lpc43_i2c.c -else -ifeq ($(CONFIG_LPC43_I2C1),y) +else ifeq ($(CONFIG_LPC43_I2C1),y) CHIP_CSRCS += lpc43_i2c.c endif + +ifeq ($(CONFIG_LPC43_CAN0),y) +CHIP_CSRCS += lpc43_can.c +else ifeq ($(CONFIG_LPC43_CAN1),y) +CHIP_CSRCS += lpc43_can.c endif ifeq ($(CONFIG_LPC43_ADC0),y) CHIP_CSRCS += lpc43_adc.c -else -ifeq ($(CONFIG_LPC43_ADC1),y) +else ifeq ($(CONFIG_LPC43_ADC1),y) CHIP_CSRCS += lpc43_adc.c endif -endif ifeq ($(CONFIG_LPC43_DAC),y) -CHIP_CSRCS += lpc43_adc.c -else -ifeq ($(CONFIG_LPC43_DAC),y) -CHIP_CSRCS += lpc43_adc.c -endif +CHIP_CSRCS += lpc43_dac.c endif ifeq ($(CONFIG_LPC43_USBOTG),y) diff --git a/arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h b/arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h index 38a951e5e6319b81222027ca3175e511fd1d3708..db66b779adfe9337b2e7e6c3b114dfee53d3136e 100644 --- a/arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h +++ b/arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h @@ -41,6 +41,7 @@ ****************************************************************************************************/ #include +#include "lpc43_pinconfig.h" /**************************************************************************************************** * Pre-processor Definitions @@ -89,14 +90,14 @@ #define PINCONF_ADCTRIG1_1 (PINCONF_FUNC2|PINCONF_PINSE|PINCONF_PIN_3) #define PINCONF_ADCTRIG1_2 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_5) -#define PINCONF_CAN0_RD_1 (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_2) -#define PINCONF_CAN0_RD_2 (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_1) +#define PINCONF_CAN0_RD_1 (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_2) +#define PINCONF_CAN0_RD_2 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_1) #define PINCONF_CAN0_TD_1 (PINCONF_FUNC1|PINCONF_PINSE|PINCONF_PIN_3) #define PINCONF_CAN0_TD_2 (PINCONF_FUNC2|PINCONF_PINS3|PINCONF_PIN_2) -#define PINCONF_CAN1_RD_1 (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_18) -#define PINCONF_CAN1_RD_2 (PINCONF_FUNC5|PINCONF_PINSE|PINCONF_PIN_1) -#define PINCONF_CAN1_RD_3 (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_9) +#define PINCONF_CAN1_RD_1 (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_18) +#define PINCONF_CAN1_RD_2 (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_PINSE|PINCONF_PIN_1) +#define PINCONF_CAN1_RD_3 (PINCONF_FUNC6|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_9) #define PINCONF_CAN1_TD_1 (PINCONF_FUNC5|PINCONF_PINS1|PINCONF_PIN_17) #define PINCONF_CAN1_TD_2 (PINCONF_FUNC5|PINCONF_PINSE|PINCONF_PIN_0) #define PINCONF_CAN1_TD_3 (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_8) @@ -862,12 +863,12 @@ #define PINCONF_U1_TXD_4 (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS3|PINCONF_PIN_4) #define PINCONF_U1_TXD_5 (PINCONF_FUNC4|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS5|PINCONF_PIN_6) -#define PINCONF_U2_DIR_1 (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_18) -#define PINCONF_U2_DIR_2 (PINCONF_FUNC7|PINCONF_PINS2|PINCONF_PIN_13) -#define PINCONF_U2_RXD_1 (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_16) -#define PINCONF_U2_RXD_2 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_11) -#define PINCONF_U2_RXD_3 (PINCONF_FUNC3|PINCONF_PINSA|PINCONF_PIN_2) -#define PINCONF_U2_RXD_4 (PINCONF_FUNC6|PINCONF_PINS7|PINCONF_PIN_2) +#define PINCONF_U2_DIR_1 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_18) +#define PINCONF_U2_DIR_2 (PINCONF_FUNC7|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_13) +#define PINCONF_U2_RXD_1 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS1|PINCONF_PIN_16) +#define PINCONF_U2_RXD_2 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_11) +#define PINCONF_U2_RXD_3 (PINCONF_FUNC3|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSA|PINCONF_PIN_2) +#define PINCONF_U2_RXD_4 (PINCONF_FUNC6|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS7|PINCONF_PIN_2) #define PINCONF_U2_TXD_1 (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_15) #define PINCONF_U2_TXD_2 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_10) #define PINCONF_U2_TXD_3 (PINCONF_FUNC3|PINCONF_PINSA|PINCONF_PIN_1) @@ -875,16 +876,16 @@ #define PINCONF_U2_UCLK_1 (PINCONF_FUNC1|PINCONF_PINS1|PINCONF_PIN_17) #define PINCONF_U2_UCLK_2 (PINCONF_FUNC7|PINCONF_PINS2|PINCONF_PIN_12) -#define PINCONF_U3_BAUD_1 (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_7) -#define PINCONF_U3_BAUD_2 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_9) -#define PINCONF_U3_BAUD_3 (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_3) -#define PINCONF_U3_DIR_1 (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_6) -#define PINCONF_U3_DIR_2 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_8) -#define PINCONF_U3_DIR_3 (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_4) -#define PINCONF_U3_RXD_1 (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_3) -#define PINCONF_U3_RXD_2 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_4) -#define PINCONF_U3_RXD_3 (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_2) -#define PINCONF_U3_RXD_4 (PINCONF_FUNC7|PINCONF_PINS9|PINCONF_PIN_4) +#define PINCONF_U3_BAUD_1 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_7) +#define PINCONF_U3_BAUD_2 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_9) +#define PINCONF_U3_BAUD_3 (PINCONF_FUNC6|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_3) +#define PINCONF_U3_DIR_1 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_6) +#define PINCONF_U3_DIR_2 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_8) +#define PINCONF_U3_DIR_3 (PINCONF_FUNC6|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_4) +#define PINCONF_U3_RXD_1 (PINCONF_FUNC1|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINSF|PINCONF_PIN_3) +#define PINCONF_U3_RXD_2 (PINCONF_FUNC2|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS2|PINCONF_PIN_4) +#define PINCONF_U3_RXD_3 (PINCONF_FUNC6|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS4|PINCONF_PIN_2) +#define PINCONF_U3_RXD_4 (PINCONF_FUNC7|PINCONF_PULLUP|PINCONF_INBUFFER|PINCONF_PINS9|PINCONF_PIN_4) #define PINCONF_U3_TXD_1 (PINCONF_FUNC1|PINCONF_PINSF|PINCONF_PIN_2) #define PINCONF_U3_TXD_2 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_3) #define PINCONF_U3_TXD_3 (PINCONF_FUNC6|PINCONF_PINS4|PINCONF_PIN_1) diff --git a/arch/arm/src/lpc43xx/chip/lpc43_can.h b/arch/arm/src/lpc43xx/chip/lpc43_can.h index cebeaccd8ce4e1f35003f285243d0514e19c37f8..c03ceab04bd617e58972f29b2bfe33abb7efc4a6 100644 --- a/arch/arm/src/lpc43xx/chip/lpc43_can.h +++ b/arch/arm/src/lpc43xx/chip/lpc43_can.h @@ -93,6 +93,50 @@ /* Register Addresses ***************************************************************/ +#define LPC43_CAN0_CNTL (LPC43_CAN0_BASE+LPC43_CAN_CNTL_OFFSET) +#define LPC43_CAN0_STAT (LPC43_CAN0_BASE+LPC43_CAN_STAT_OFFSET) +#define LPC43_CAN0_EC (LPC43_CAN0_BASE+LPC43_CAN_EC_OFFSET) +#define LPC43_CAN0_BT (LPC43_CAN0_BASE+LPC43_CAN_BT_OFFSET) +#define LPC43_CAN0_INT (LPC43_CAN0_BASE+LPC43_CAN_INT_OFFSET) +#define LPC43_CAN0_TEST (LPC43_CAN0_BASE+LPC43_CAN_TEST_OFFSET) +#define LPC43_CAN0_BRPE (LPC43_CAN0_BASE+LPC43_CAN_BRPE_OFFSET) + +#define LPC43_CAN0_IF1_CMDREQ (LPC43_CAN0_BASE+LPC43_CAN_IF1_CMDREQ_OFFSET) +#define LPC43_CAN0_IF1_CMDMSKW (LPC43_CAN0_BASE+LPC43_CAN_IF1_CMDMSKW_OFFSET) +#define LPC43_CAN0_IF1_CMDMSKR (LPC43_CAN0_BASE+LPC43_CAN_IF1_CMDMSKR_OFFSET) +#define LPC43_CAN0_IF1_MSK1 (LPC43_CAN0_BASE+LPC43_CAN_IF1_MSK1_OFFSET) +#define LPC43_CAN0_IF1_MSK2 (LPC43_CAN0_BASE+LPC43_CAN_IF1_MSK2_OFFSET) +#define LPC43_CAN0_IF1_ARB1 (LPC43_CAN0_BASE+LPC43_CAN_IF1_ARB1_OFFSET) +#define LPC43_CAN0_IF1_ARB2 (LPC43_CAN0_BASE+LPC43_CAN_IF1_ARB2_OFFSET) +#define LPC43_CAN0_IF1_MCTRL (LPC43_CAN0_BASE+LPC43_CAN_IF1_MCTRL_OFFSET) +#define LPC43_CAN0_IF1_DA1 (LPC43_CAN0_BASE+LPC43_CAN_IF1_DA1_OFFSET) +#define LPC43_CAN0_IF1_DA2 (LPC43_CAN0_BASE+LPC43_CAN_IF1_DA2_OFFSET) +#define LPC43_CAN0_IF1_DB1 (LPC43_CAN0_BASE+LPC43_CAN_IF1_DB1_OFFSET) +#define LPC43_CAN0_IF1_DB2 (LPC43_CAN0_BASE+LPC43_CAN_IF1_DB2_OFFSET) + +#define LPC43_CAN0_IF2_CMDREQ (LPC43_CAN0_BASE+LPC43_CAN_IF2_CMDREQ_OFFSET) +#define LPC43_CAN0_IF2_CMDMSKW (LPC43_CAN0_BASE+LPC43_CAN_IF2_CMDMSKW_OFFSET) +#define LPC43_CAN0_IF2_CMDMSKR (LPC43_CAN0_BASE+LPC43_CAN_IF2_CMDMSKR_OFFSET) +#define LPC43_CAN0_IF2_MSK1 (LPC43_CAN0_BASE+LPC43_CAN_IF2_MSK1_OFFSET) +#define LPC43_CAN0_IF2_MSK2 (LPC43_CAN0_BASE+LPC43_CAN_IF2_MSK2_OFFSET) +#define LPC43_CAN0_IF2_ARB1 (LPC43_CAN0_BASE+LPC43_CAN_IF2_ARB1_OFFSET) +#define LPC43_CAN0_IF2_ARB2 (LPC43_CAN0_BASE+LPC43_CAN_IF2_ARB2_OFFSET) +#define LPC43_CAN0_IF2_MCTRL (LPC43_CAN0_BASE+LPC43_CAN_IF2_MCTRL_OFFSET) +#define LPC43_CAN0_IF2_DA1 (LPC43_CAN0_BASE+LPC43_CAN_IF2_DA1_OFFSET) +#define LPC43_CAN0_IF2_DA2 (LPC43_CAN0_BASE+LPC43_CAN_IF2_DA2_OFFSET) +#define LPC43_CAN0_IF2_DB1 (LPC43_CAN0_BASE+LPC43_CAN_IF2_DB1_OFFSET) +#define LPC43_CAN0_IF2_DB2 (LPC43_CAN0_BASE+LPC43_CAN_IF2_DB2_OFFSET) + +#define LPC43_CAN0_TXREQ1 (LPC43_CAN0_BASE+LPC43_CAN_TXREQ1_OFFSET) +#define LPC43_CAN0_TXREQ2 (LPC43_CAN0_BASE+LPC43_CAN_TXREQ2_OFFSET) +#define LPC43_CAN0_ND1 (LPC43_CAN0_BASE+LPC43_CAN_ND1_OFFSET) +#define LPC43_CAN0_ND2 (LPC43_CAN0_BASE+LPC43_CAN_ND2_OFFSET) +#define LPC43_CAN0_IR1 (LPC43_CAN0_BASE+LPC43_CAN_IR1_OFFSET) +#define LPC43_CAN0_IR2 (LPC43_CAN0_BASE+LPC43_CAN_IR2_OFFSET) +#define LPC43_CAN0_MSGV1 (LPC43_CAN0_BASE+LPC43_CAN_MSGV1_OFFSET) +#define LPC43_CAN0_MSGV2 (LPC43_CAN0_BASE+LPC43_CAN_MSGV2_OFFSET) +#define LPC43_CAN0_CLKDIV (LPC43_CAN0_BASE+LPC43_CAN_CLKDIV_OFFSET) + #define LPC43_CAN1_CNTL (LPC43_CAN1_BASE+LPC43_CAN_CNTL_OFFSET) #define LPC43_CAN1_STAT (LPC43_CAN1_BASE+LPC43_CAN_STAT_OFFSET) #define LPC43_CAN1_EC (LPC43_CAN1_BASE+LPC43_CAN_EC_OFFSET) @@ -137,50 +181,6 @@ #define LPC43_CAN1_MSGV2 (LPC43_CAN1_BASE+LPC43_CAN_MSGV2_OFFSET) #define LPC43_CAN1_CLKDIV (LPC43_CAN1_BASE+LPC43_CAN_CLKDIV_OFFSET) -#define LPC43_CAN2_CNTL (LPC43_CAN2_BASE+LPC43_CAN_CNTL_OFFSET) -#define LPC43_CAN2_STAT (LPC43_CAN2_BASE+LPC43_CAN_STAT_OFFSET) -#define LPC43_CAN2_EC (LPC43_CAN2_BASE+LPC43_CAN_EC_OFFSET) -#define LPC43_CAN2_BT (LPC43_CAN2_BASE+LPC43_CAN_BT_OFFSET) -#define LPC43_CAN2_INT (LPC43_CAN2_BASE+LPC43_CAN_INT_OFFSET) -#define LPC43_CAN2_TEST (LPC43_CAN2_BASE+LPC43_CAN_TEST_OFFSET) -#define LPC43_CAN2_BRPE (LPC43_CAN2_BASE+LPC43_CAN_BRPE_OFFSET) - -#define LPC43_CAN2_IF1_CMDREQ (LPC43_CAN2_BASE+LPC43_CAN_IF1_CMDREQ_OFFSET) -#define LPC43_CAN2_IF1_CMDMSKW (LPC43_CAN2_BASE+LPC43_CAN_IF1_CMDMSKW_OFFSET) -#define LPC43_CAN2_IF1_CMDMSKR (LPC43_CAN2_BASE+LPC43_CAN_IF1_CMDMSKR_OFFSET) -#define LPC43_CAN2_IF1_MSK1 (LPC43_CAN2_BASE+LPC43_CAN_IF1_MSK1_OFFSET) -#define LPC43_CAN2_IF1_MSK2 (LPC43_CAN2_BASE+LPC43_CAN_IF1_MSK2_OFFSET) -#define LPC43_CAN2_IF1_ARB1 (LPC43_CAN2_BASE+LPC43_CAN_IF1_ARB1_OFFSET) -#define LPC43_CAN2_IF1_ARB2 (LPC43_CAN2_BASE+LPC43_CAN_IF1_ARB2_OFFSET) -#define LPC43_CAN2_IF1_MCTRL (LPC43_CAN2_BASE+LPC43_CAN_IF1_MCTRL_OFFSET) -#define LPC43_CAN2_IF1_DA1 (LPC43_CAN2_BASE+LPC43_CAN_IF1_DA1_OFFSET) -#define LPC43_CAN2_IF1_DA2 (LPC43_CAN2_BASE+LPC43_CAN_IF1_DA2_OFFSET) -#define LPC43_CAN2_IF1_DB1 (LPC43_CAN2_BASE+LPC43_CAN_IF1_DB1_OFFSET) -#define LPC43_CAN2_IF1_DB2 (LPC43_CAN2_BASE+LPC43_CAN_IF1_DB2_OFFSET) - -#define LPC43_CAN2_IF2_CMDREQ (LPC43_CAN2_BASE+LPC43_CAN_IF2_CMDREQ_OFFSET) -#define LPC43_CAN2_IF2_CMDMSKW (LPC43_CAN2_BASE+LPC43_CAN_IF2_CMDMSKW_OFFSET) -#define LPC43_CAN2_IF2_CMDMSKR (LPC43_CAN2_BASE+LPC43_CAN_IF2_CMDMSKR_OFFSET) -#define LPC43_CAN2_IF2_MSK1 (LPC43_CAN2_BASE+LPC43_CAN_IF2_MSK1_OFFSET) -#define LPC43_CAN2_IF2_MSK2 (LPC43_CAN2_BASE+LPC43_CAN_IF2_MSK2_OFFSET) -#define LPC43_CAN2_IF2_ARB1 (LPC43_CAN2_BASE+LPC43_CAN_IF2_ARB1_OFFSET) -#define LPC43_CAN2_IF2_ARB2 (LPC43_CAN2_BASE+LPC43_CAN_IF2_ARB2_OFFSET) -#define LPC43_CAN2_IF2_MCTRL (LPC43_CAN2_BASE+LPC43_CAN_IF2_MCTRL_OFFSET) -#define LPC43_CAN2_IF2_DA1 (LPC43_CAN2_BASE+LPC43_CAN_IF2_DA1_OFFSET) -#define LPC43_CAN2_IF2_DA2 (LPC43_CAN2_BASE+LPC43_CAN_IF2_DA2_OFFSET) -#define LPC43_CAN2_IF2_DB1 (LPC43_CAN2_BASE+LPC43_CAN_IF2_DB1_OFFSET) -#define LPC43_CAN2_IF2_DB2 (LPC43_CAN2_BASE+LPC43_CAN_IF2_DB2_OFFSET) - -#define LPC43_CAN2_TXREQ1 (LPC43_CAN2_BASE+LPC43_CAN_TXREQ1_OFFSET) -#define LPC43_CAN2_TXREQ2 (LPC43_CAN2_BASE+LPC43_CAN_TXREQ2_OFFSET) -#define LPC43_CAN2_ND1 (LPC43_CAN2_BASE+LPC43_CAN_ND1_OFFSET) -#define LPC43_CAN2_ND2 (LPC43_CAN2_BASE+LPC43_CAN_ND2_OFFSET) -#define LPC43_CAN2_IR1 (LPC43_CAN2_BASE+LPC43_CAN_IR1_OFFSET) -#define LPC43_CAN2_IR2 (LPC43_CAN2_BASE+LPC43_CAN_IR2_OFFSET) -#define LPC43_CAN2_MSGV1 (LPC43_CAN2_BASE+LPC43_CAN_MSGV1_OFFSET) -#define LPC43_CAN2_MSGV2 (LPC43_CAN2_BASE+LPC43_CAN_MSGV2_OFFSET) -#define LPC43_CAN2_CLKDIV (LPC43_CAN2_BASE+LPC43_CAN_CLKDIV_OFFSET) - /* Register Bit Definitions *********************************************************/ /* CAN control register */ @@ -267,7 +267,7 @@ # define CAN_INT_MSG30 (30 << CAN_INT_SHIFT) /* Message 30 */ # define CAN_INT_MSG31 (31 << CAN_INT_SHIFT) /* Message 31 */ # define CAN_INT_MSG32 (32 << CAN_INT_SHIFT) /* Message 32 */ -# define CAN_INT_MSG32 (0x8000 << CAN_INT_SHIFT) /* Status interrupt */ +# define CAN_INT_STAT (0x8000 << CAN_INT_SHIFT) /* Status interrupt */ /* Bits 16-31: Reserved */ /* Test register */ /* Bits 0-1: Reserved */ diff --git a/arch/arm/src/lpc43xx/chip/lpc43_cgu.h b/arch/arm/src/lpc43xx/chip/lpc43_cgu.h index bd9682c8fd444d076e52da49a6ba2d40202fd162..7f60f38836fa3db2108cc76e31b7e050ecde6174 100644 --- a/arch/arm/src/lpc43xx/chip/lpc43_cgu.h +++ b/arch/arm/src/lpc43xx/chip/lpc43_cgu.h @@ -643,6 +643,31 @@ # define BASE_VADC_CLKSEL_IDIVD (15 << BASE_VADC_CLK_CLKSEL_SHIFT) /* IDIVD */ # define BASE_VADC_CLKSEL_IDIVE (16 << BASE_VADC_CLK_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ + +/* Output stage 13 control register (BASE_SDIO_CLK) */ +/* NOTE: Clocks 4-19 are identical */ + +#define BASE_SDIO_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_SDIO_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_SDIO_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_SDIO_CLK_CLKSEL_MASK (31 << BASE_SDIO_CLK_CLKSEL_SHIFT) +# define BASE_SDIO_CLKSEL_32KHZOSC (0 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_SDIO_CLKSEL_IRC (1 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_SDIO_CLKSEL_ENET_RXCLK (2 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_SDIO_CLKSEL_ENET_TXCLK (3 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_SDIO_CLKSEL_GPCLKIN (4 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_SDIO_CLKSEL_XTAL (6 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_SDIO_CLKSEL_PLL0AUDIO (8 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_SDIO_CLKSEL_PLL1 (9 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_SDIO_CLKSEL_IDIVA (12 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_SDIO_CLKSEL_IDIVB (13 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_SDIO_CLKSEL_IDIVC (14 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_SDIO_CLKSEL_IDIVD (15 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_SDIO_CLKSEL_IDIVE (16 << BASE_SDIO_CLK_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ + /* Output stage 14 control register (BASE_SSP0_CLK) */ /* NOTE: Clocks 4-19 are identical */ diff --git a/arch/arm/src/lpc43xx/chip/lpc43_sdmmc.h b/arch/arm/src/lpc43xx/chip/lpc43_sdmmc.h index 05a51178fb24852294c8290ea145ac081cef7b82..a61c254894cb2e8bd44f09358875519f0715d416 100644 --- a/arch/arm/src/lpc43xx/chip/lpc43_sdmmc.h +++ b/arch/arm/src/lpc43xx/chip/lpc43_sdmmc.h @@ -46,6 +46,11 @@ * Pre-processor Definitions ************************************************************************************************/ +#define LPC43_TXFIFO_DEPTH 32 +#define LPC43_TXFIFO_WIDTH 4 +#define LPC43_RXFIFO_DEPTH 32 +#define LPC43_RXFIFO_WIDTH 4 + /* MCI register offsets (with respect to the MCI base) ******************************************/ #define LPC43_SDMMC_CTRL_OFFSET 0x0000 /* Control register */ @@ -114,7 +119,6 @@ #define LPC43_SDMMC_TBBCNT (LPC43_SDMMC_BASE+LPC43_SDMMC_TBBCNT_OFFSET) #define LPC43_SDMMC_TBBCNT (LPC43_SDMMC_BASE+LPC43_SDMMC_TBBCNT_OFFSET) #define LPC43_SDMMC_DEBNCE (LPC43_SDMMC_BASE+LPC43_SDMMC_DEBNCE_OFFSET) -#define LPC43_SDMMC_DEBNCE (LPC43_SDMMC_BASE+LPC43_SDMMC_DEBNCE_OFFSET) #define LPC43_SDMMC_RSTN (LPC43_SDMMC_BASE+LPC43_SDMMC_RSTN_OFFSET) #define LPC43_SDMMC_BMOD (LPC43_SDMMC_BASE+LPC43_SDMMC_BMOD_OFFSET) #define LPC43_SDMMC_PLDMND (LPC43_SDMMC_BASE+LPC43_SDMMC_PLDMND_OFFSET) @@ -157,12 +161,16 @@ #define SDMMC_CLKDIV0_SHIFT (0) /* Bits 0-7: Clock divider 0 value */ #define SDMMC_CLKDIV0_MASK (255 << SDMMC_CLKDIV0_SHIFT) +# define SDMMC_CLKDIV0(n) ((((n) + 1) >> 1) << SDMMC_CLKDIV0_SHIFT) #define SDMMC_CLKDIV1_SHIFT (8) /* Bits 8-15: Clock divider 1 value */ #define SDMMC_CLKDIV1_MASK (255 << SDMMC_CLKDIV1_SHIFT) +# define SDMMC_CLKDIV1(n) ((((n) + 1) >> 1) << SDMMC_CLKDIV1_SHIFT) #define SDMMC_CLKDIV2_SHIFT (16) /* Bits 16-23: Clock divider 2 value */ #define SDMMC_CLKDIV2_MASK (255 << SDMMC_CLKDIV2_SHIFT) +# define SDMMC_CLKDIV2(n) ((((n) + 1) >> 1) << SDMMC_CLKDIV2_SHIFT) #define SDMMC_CLKDIV3_SHIFT (24) /* Bits 24-31: Clock divider 3 value */ #define SDMMC_CLKDIV3_MASK (255 << SDMMC_CLKDIV3_SHIFT) +# define SDMMC_CLKDIV3(n) ((((n) + 1) >> 1) << SDMMC_CLKDIV3_SHIFT) /* Clock source register CLKSRC */ @@ -175,7 +183,7 @@ /* Bits 2-31: Reserved */ /* Clock enable register CLKENA */ -#define SDMMC_CLKENA_EMABLE (1 << 0) /* Bit 0: Clock enable */ +#define SDMMC_CLKENA_ENABLE (1 << 0) /* Bit 0: Clock enable */ /* Bits 1-15: Reserved */ #define SDMMC_CLKENA_LOWPOWER (1 << 16) /* Bit 16: Low-power mode */ /* Bits 17-31: Reserved */ @@ -188,6 +196,7 @@ /* Card type register CTYPE */ +#define SDMMC_CTYPE_WIDTH1 (0) /* 1-bit mode */ #define SDMMC_CTYPE_WIDTH4 (1 << 0) /* Bit 0: 4-bit mode */ /* Bits 1-15: Reserved */ #define SDMMC_CTYPE_WIDTH8 (1 << 16) /* Bit 16: 8-bit mode */ @@ -218,7 +227,7 @@ #define SDMMC_INT_SBE (1 << 13) /* Bit 13: Start-bit error */ #define SDMMC_INT_ACD (1 << 14) /* Bit 14: Auto command done */ #define SDMMC_INT_EBE (1 << 15) /* Bit 15: End-bit error (read)/Write no CRC */ -#define SDMMC_INT_SDIO (1 << 16) /* Bit 16: Mask SDIO interrupt */ +#define SDMMC_INT_SDIO (1 << 16) /* Bit 16: SDIO interrupt */ /* Bits 17-31: Reserved */ #define SDMMC_INT_ALL (0x1ffff) @@ -228,6 +237,11 @@ #define SDMMC_CMD_CMDINDEX_MASK (63 << SDMMC_CMD_CMDINDEX_SHIFT) #define SDMMC_CMD_RESPONSE (1 << 6) /* Bit 6: Response expected from card */ #define SDMMC_CMD_LONGRESP (1 << 7) /* Bit 7: Long response expected from card */ +#define SDMMC_CMD_WAITRESP_SHIFT (6) /* Bits 6-7: Response expected */ +#define SDMMC_CMD_WAITRESP_MASK (3 << SDMMC_CMD_WAITRESP_SHIFT) +# define SDMMC_CMD_NORESPONSE (0 << SDMMC_CMD_WAITRESP_SHIFT) /* x0: No response */ +# define SDMMC_CMD_SHORTRESPONSE (1 << SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response */ +# define SDMMC_CMD_LONGRESPONSE (3 << SDMMC_CMD_WAITRESP_SHIFT) /* 11: Long response */ #define SDMMC_CMD_RESPCRC (1 << 8) /* Bit 8: Check response CRC */ #define SDMMC_CMD_DATAXFREXPTD (1 << 9) /* Bit 9: Data transfer expected (read/write) */ #define SDMMC_CMD_WRITE (1 << 10) /* Bit 10: Write to card */ @@ -286,9 +300,11 @@ #define SDMMC_FIFOTH_TXWMARK_SHIFT (0) /* Bits 0-11: FIFO threshold level when transmitting */ #define SDMMC_FIFOTH_TXWMARK_MASK (0xfff << SDMMC_FIFOTH_TXWMARK_SHIFT) +# define SDMMC_FIFOTH_TXWMARK(n) ((uint32_t)(n) << SDMMC_FIFOTH_TXWMARK_SHIFT) /* Bits 12-15: Reserved */ #define SDMMC_FIFOTH_RXWMARK_SHIFT (16) /* Bits 16-27: FIFO threshold level when receiving */ #define SDMMC_FIFOTH_RXWMARK_MASK (0xfff << SDMMC_FIFOTH_RXWMARK_SHIFT) +# define SDMMC_FIFOTH_RXWMARK(n) ((uint32_t)(n) << SDMMC_FIFOTH_RXWMARK_SHIFT) #define SDMMC_FIFOTH_DMABURST_SHIFT (28) /* Bits 28-30: Burst size for multiple transaction */ #define SDMMC_FIFOTH_DMABURST_MASK (7 << SDMMC_FIFOTH_DMABURST_SHIFT) # define SDMMC_FIFOTH_DMABURST_1XFR (0 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 1 transfer */ @@ -324,6 +340,7 @@ #define SDMMC_BMOD_FB (1 << 1) /* Bit 1: Fixed Burst */ #define SDMMC_BMOD_DSL_SHIFT (2) /* Bits 2-6: Descriptor Skip Length */ #define SDMMC_BMOD_DSL_MASK (31 << SDMMC_BMOD_DSL_SHIFT) +# define SDMMC_BMOD_DSL(n) ((uint32_t)(n) << SDMMC_BMOD_DSL_SHIFT) #define SDMMC_BMOD_DE (1 << 7) /* Bit 7: SD/MMC DMA Enable */ #define SDMMC_BMOD_PBL_SHIFT (8) /* Bits 8-10: Programmable Burst Length */ #define SDMMC_BMOD_PBL_MASK (7 << SDMMC_BMOD_PBL_SHIFT) @@ -365,7 +382,6 @@ /* Bits 17-31: Reserved */ /* Internal DMAC Interrupt Enable Register */ -#define SDMMC_IDINTEN_ #define SDMMC_IDINTEN_TI (1 << 0) /* Bit 0: Transmit Interrupt */ #define SDMMC_IDINTEN_RI (1 << 1) /* Bit 1: Receive Interrupt */ #define SDMMC_IDINTEN_FBE (1 << 2) /* Bit 2: Fatal Bus Error Interrupt */ @@ -376,6 +392,7 @@ #define SDMMC_IDINTEN_NIS (1 << 8) /* Bit 8: Normal Interrupt Summary */ #define SDMMC_IDINTEN_AIS (1 << 9) /* Bit 9: Abnormal Interrupt Summary */ /* Bits 10-31: Reserved */ +#define SDMMC_IDINTEN_ALL 0x00000333 /************************************************************************************************ * Public Types diff --git a/arch/arm/src/lpc43xx/chip/lpc43_usb0.h b/arch/arm/src/lpc43xx/chip/lpc43_usb0.h index caa4c86cc2faaa6618ac3b193dbb0101b39aaf22..15e009a2467a7bdc7ae5d0adf055e9f658e8166e 100644 --- a/arch/arm/src/lpc43xx/chip/lpc43_usb0.h +++ b/arch/arm/src/lpc43xx/chip/lpc43_usb0.h @@ -58,6 +58,7 @@ #define LPC43_USBDEV_DCCPARAMS_OFFSET 0x0124 /* Device controller capability parameters */ /* Device/host/OTG operational registers */ + #define LPC43_USBOTG_HCOR_OFFSET 0x0140 /* Offset to EHCI Host Controller Operational Registers */ #define LPC43_USBOTG_USBCMD_OFFSET 0x0140 /* USB command (both) */ #define LPC43_USBOTG_USBSTS_OFFSET 0x0144 /* USB status (both) */ diff --git a/arch/arm/src/lpc43xx/lpc43_can.c b/arch/arm/src/lpc43xx/lpc43_can.c new file mode 100644 index 0000000000000000000000000000000000000000..415a7b28efd163130bac8e6079c611b681dd0643 --- /dev/null +++ b/arch/arm/src/lpc43xx/lpc43_can.c @@ -0,0 +1,1279 @@ +/**************************************************************************** + * arch/arm/src/lpc43xx/lpc43_can.c + * + * Copyright(C) 2017 Gregory Nutt. All rights reserved. + * + * Created on: 2 May 2017 + * Author: katherine + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "up_internal.h" +#include "up_arch.h" +#include "cache.h" + +#include "chip.h" +#include "lpc43_gpio.h" +#include "chip/lpc43_can.h" +#include "chip/lpc43_rgu.h" +#include "lpc43_ccu.h" +#include "lpc43_cgu.h" + +#if defined(CONFIG_LPC43_CAN0) || defined(CONFIG_LPC43_CAN1) + +#define CAN_MSG_OBJECTS_NUM 0x20 +#define CAN_RX_OBJ_NUM 0x10 +#define CAN_TX_OBJ_NUM 0x10 + +#define CAN_RX_OBJ_FIRST 0x01 +#define CAN_RX_OBJ_LAST (CAN_RX_OBJ_FIRST + CAN_RX_OBJ_NUM - 0x01) + +#define CAN_TX_OBJ_FIRST (CAN_RX_OBJ_LAST + 0x01) +#define CAN_TX_OBJ_LAST (CAN_TX_OBJ_FIRST + CAN_TX_OBJ_NUM - 0x01) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifdef CONFIG_LPC43_CAN0 + +/* A CAN bit rate must be provided */ + +# ifndef CONFIG_CAN0_BAUD +# define CONFIG_CAN0_BAUD 1000000 +# endif +#endif + +#ifdef CONFIG_LPC43_CAN1 + +/* A CAN bit rate must be provided */ + +# ifndef CONFIG_CAN1_BAUD +# define CONFIG_CAN1_BAUD 1000000 +# endif +#endif + +/* User-defined TSEG1 and TSEG2 settings may be used. + * + * CONFIG_CAN_TSEG1 = the number of CAN time quanta in segment 1 + * CONFIG_CAN_TSEG2 = the number of CAN time quanta in segment 2 + * CAN_BIT_QUANTA = The number of CAN time quanta in on bit time + */ + +#ifndef CONFIG_CAN_TSEG1 +# define CONFIG_CAN_TSEG1 12 +#endif + +#ifndef CONFIG_CAN_TSEG2 +# define CONFIG_CAN_TSEG2 4 +#endif + +#define CAN_BIT_QUANTA (CONFIG_CAN_TSEG1 + CONFIG_CAN_TSEG2 + 1) + +/* Timing *******************************************************************/ + +/* CAN clock source is defined in board.h */ + +#define CAN_CLOCK_FREQUENCY(c) ((uint32_t)LPC43_CCLK / ((uint32_t)(c))) + +/* CAN module clock must be less then 50 MHz */ + +#define CAN_CLKDIVVAL 0x05 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + uint8_t port; /* CAN port number */ + uint8_t clkdiv; /* CLKDIV register */ + uint32_t baud; /* Configured baud */ + uint32_t base; /* CAN register base address */ + uint8_t irq; /* IRQ associated with this CAN */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ +/* CAN Register access */ + +#ifdef CONFIG_CAN_REGDEBUG +static void can_printreg(uint32_t addr, uint32_t value); +#endif + +static uint32_t can_getreg(struct up_dev_s *priv, int offset); +static void can_putreg(struct up_dev_s *priv, int offset, uint32_t value); + +#ifdef CONFIG_CAN_REGDEBUG +static uint32_t can_getcommon(uint32_t addr); +static void can_putcommon(uint32_t addr, uint32_t value); +#else +# define can_getcommon(addr) getreg32(addr) +# define can_putcommon(addr, value) putreg32(value, addr) +#endif + +/* CAN methods */ + +static void can_reset(FAR struct can_dev_s *dev); +static int can_setup(FAR struct can_dev_s *dev); +static void can_shutdown(FAR struct can_dev_s *dev); +static void can_rxint(FAR struct can_dev_s *dev, bool enable); +static void can_txint(FAR struct can_dev_s *dev, bool enable); +static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg); +static int can_remoterequest(FAR struct can_dev_s *dev, uint16_t id); +static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg); +static bool candev_txready(FAR struct can_dev_s *dev); +static bool candev_txempty(FAR struct can_dev_s *dev); + +/* CAN interrupts */ + +#ifdef CONFIG_LPC43_CAN0 +static int can0_interrupt(int irq, void *context, FAR void *arg); +#endif +#ifdef CONFIG_LPC43_CAN1 +static int can1_interrupt(int irq, void *context, FAR void *arg); +#endif +static void can_interrupt(FAR struct can_dev_s *dev); + +/* Message Processing */ + +static void can_savemsg(struct up_dev_s *priv, struct can_hdr_s *hdr, + uint32_t *data); +static void can_readobj(struct up_dev_s *priv, uint32_t index); +static void can_invalobj(struct up_dev_s *priv, uint32_t index); +static void can_setuprxobj(struct up_dev_s *priv); + +/* Initialization */ + +static int can_bittiming(struct up_dev_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct can_ops_s g_canops = +{ + .co_reset = can_reset, + .co_setup = can_setup, + .co_shutdown = can_shutdown, + .co_rxint = can_rxint, + .co_txint = can_txint, + .co_ioctl = can_ioctl, + .co_remoterequest = can_remoterequest, + .co_send = can_send, + .co_txready = candev_txready, + .co_txempty = candev_txempty, +}; + +#ifdef CONFIG_LPC43_CAN0 +static struct up_dev_s g_can0priv = +{ + .port = 0, + .clkdiv = CAN_CLKDIVVAL + 1, + .baud = CONFIG_CAN0_BAUD, + .base = LPC43_CAN0_BASE, + .irq = LPC43M4_IRQ_CAN0, +}; + +static struct can_dev_s g_can0dev = +{ + .cd_ops = &g_canops, + .cd_priv = &g_can0priv, +}; +#endif + +#ifdef CONFIG_LPC43_CAN1 +static struct up_dev_s g_can1priv = +{ + .port = 1, + .clkdiv = CAN_CLKDIVVAL + 1, + .baud = CONFIG_CAN1_BAUD, + .base = LPC43_CAN1_BASE, + .irq = LPC43M4_IRQ_CAN1, +}; + +static struct can_dev_s g_can1dev = +{ + .cd_ops = &g_canops, + .cd_priv = &g_can1priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: can_printreg + * + * Description: + * Print the value read from a register. + * + * Input Parameters: + * addr - The register address + * value - The register value + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_REGDEBUG +static void can_printreg(uint32_t addr, uint32_t value) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && value == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + caninfo("...\n"); + } + + return; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + caninfo("[repeats %d more times]\n", count-3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = value; + count = 1; + } + + /* Show the register value read */ + + caninfo("%08x->%08x\n", addr, value); +} +#endif /* CONFIG_CAN_REGDEBUG */ + +/**************************************************************************** + * Name: can_getreg + * + * Description: + * Read the value of an CAN1/2 register. + * + * Input Parameters: + * priv - A reference to the CAN block status + * offset - The offset to the register to read + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_REGDEBUG +static uint32_t can_getreg(struct up_dev_s *priv, int offset) +{ + uint32_t addr; + uint32_t value; + + /* Read the value from the register */ + + addr = priv->base + offset; + value = getreg32(addr); + can_printreg(addr, value); + return value; +} +#else +static uint32_t can_getreg(struct up_dev_s *priv, int offset) +{ + return getreg32(priv->base + offset); +} +#endif /* CONFIG_CAN_REGDEBUG */ + +/**************************************************************************** + * Name: can_putreg + * + * Description: + * Set the value of an CAN1/2 register. + * + * Input Parameters: + * priv - A reference to the CAN block status + * offset - The offset to the register to write + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_REGDEBUG +static void can_putreg(struct up_dev_s *priv, int offset, uint32_t value) +{ + uint32_t addr = priv->base + offset; + + /* Show the register value being written */ + + caninfo("%08x<-%08x\n", addr, value); + + /* Write the value */ + + putreg32(value, addr); +} +#else +static void can_putreg(struct up_dev_s *priv, int offset, uint32_t value) +{ + putreg32(value, priv->base + offset); +} +#endif /* CONFIG_CAN_REGDEBUG */ + +/**************************************************************************** + * Name: can_getcommon + * + * Description: + * Get the value of common register. + * + * Input Parameters: + * addr - The address of the register to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_REGDEBUG +static uint32_t can_getcommon(uint32_t addr) +{ + uint32_t value; + + /* Read the value from the register */ + + value = getreg32(addr); + can_printreg(addr, value); + return value; +} +#endif /* CONFIG_CAN_REGDEBUG */ + +/**************************************************************************** + * Name: can_putcommon + * + * Description: + * Set the value of common register. + * + * Input Parameters: + * addr - The address of the register to write + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_REGDEBUG +static void can_putcommon(uint32_t addr, uint32_t value) +{ + /* Show the register value being written */ + + caninfo("%08x<-%08x\n", addr, value); + + /* Write the value */ + + putreg32(value, addr); +} +#endif /* CONFIG_CAN_REGDEBUG */ + +/**************************************************************************** + * Name: can_reset + * + * Description: + * Reset the CAN device. Called early to initialize the hardware. This + * function is called, before can_setup() and on error conditions. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void can_reset(FAR struct can_dev_s *dev) +{ + FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->cd_priv; + uint32_t regval; + + caninfo("CAN%d reset\n", priv->port); + +#ifdef CONFIG_LPC43_CAN0 + if (priv->port == 0) + { + regval = ~(getreg32(LPC43_RGU_ACTIVE1)); + regval |= RGU_CTRL1_CAN0_RST; + putreg32(regval, LPC43_RGU_CTRL1); + } +#endif /* CONFIG_LPC43_CAN0 */ + +#ifdef CONFIG_LPC43_CAN1 + if (priv->port == 1) + { + regval = ~(getreg32(LPC43_RGU_ACTIVE1)); + regval |= RGU_CTRL1_CAN1_RST; + putreg32(regval, LPC43_RGU_CTRL1); + } +#endif /* CONFIG_LPC43_CAN1 */ +} + +/**************************************************************************** + * Name: can_setup + * + * Description: + * Configure the CAN. This method is called the first time that the CAN + * device is opened. This will occur when the port is first opened. + * This setup includes configuring and attaching CAN interrupts. + * All CAN interrupts are disabled upon return. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int can_setup(FAR struct can_dev_s *dev) +{ + FAR struct up_dev_s *priv = (FAR struct up_dev_s *) dev->cd_priv; + uint32_t regval; + uint8_t i; + int ret = ERROR; + + caninfo("CAN%d setup\n", priv->port); + + can_bittiming(priv); + + /* Clock must be divided by the CAN clock divider CLKDIV to be less than + * 50 MHz. + */ + + can_putreg(priv, LPC43_CAN_CLKDIV_OFFSET, CAN_CLKDIVVAL); + + /* Invalidate all message objects */ + + for (i = 1; i <= CAN_MSG_OBJECTS_NUM; ++i) + { + can_invalobj(priv, i); + } + + /* Initialization finished, normal operation now. */ + + regval = can_getreg(priv, LPC43_CAN_CNTL_OFFSET); + regval &= ~CAN_CNTL_INIT; + can_putreg(priv, LPC43_CAN_CNTL_OFFSET, regval); + + while (can_getreg(priv, LPC43_CAN_CNTL_OFFSET) & CAN_CNTL_INIT); + +#ifdef CONFIG_LPC43_CAN0 + if (priv->irq == LPC43M4_IRQ_CAN0) + { + ret = irq_attach(priv->irq, can0_interrupt, 0); + } +#endif + +#ifdef CONFIG_LPC43_CAN1 + if (priv->irq == LPC43M4_IRQ_CAN1) + { + ret = irq_attach(priv->irq, can1_interrupt, 0); + } +#endif + + if (ret == OK) + { + up_enable_irq(priv->irq); + + /* Enable CAN interrupts within CAN module */ + + regval = can_getreg(priv, LPC43_CAN_CNTL_OFFSET); + regval |= (CAN_CNTL_IE | CAN_CNTL_SIE | CAN_CNTL_EIE); + can_putreg(priv, LPC43_CAN_CNTL_OFFSET, regval); + } + + return ret; +} + +/**************************************************************************** + * Name: can_shutdown + * + * Description: + * Disable the CAN. This method is called when the CAN device is closed. + * This method reverses the operation the setup method. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void can_shutdown(FAR struct can_dev_s *dev) +{ + FAR struct up_dev_s *priv = (FAR struct up_dev_s *) dev->cd_priv; + uint32_t regval; + + caninfo("CAN%d\n", priv->port); + + /* Stop operation mode */ + + regval = can_getreg(priv, LPC43_CAN_CNTL_OFFSET); + regval |= CAN_CNTL_INIT; + can_putreg(priv, LPC43_CAN_CNTL_OFFSET, regval); + + /* Disable CAN interrupts */ + + regval = can_getreg(priv, LPC43_CAN_CNTL_OFFSET); + regval &= ~(CAN_CNTL_IE | CAN_CNTL_SIE | CAN_CNTL_EIE); + can_putreg(priv, LPC43_CAN_CNTL_OFFSET, regval); + + up_disable_irq(priv->irq); + + /* Then detach the CAN interrupt handler. */ + + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: can_rxint + * + * Description: + * Call to enable or disable RX interrupts. + * This function is called two times: from can_open and can_close. Therefore + * this function enables and disables not only RX interrupts but all message + * objects. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void can_rxint(FAR struct can_dev_s *dev, bool enable) +{ + FAR struct up_dev_s *priv = (FAR struct up_dev_s *) dev->cd_priv; + + if (enable == true) + { + can_setuprxobj(priv); + } + else + { + uint8_t i = 0; + for (i = CAN_RX_OBJ_FIRST; i <= CAN_RX_OBJ_LAST; ++i) + { + can_invalobj(priv, i); + } + } +} + +/**************************************************************************** + * Name: can_txint + * + * Description: + * Call to enable or disable TX interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void can_txint(FAR struct can_dev_s *dev, bool enable) +{ + /* The TX interrupt is automatically enabled in can_send within a + * message object. + */ +} + +/**************************************************************************** + * Name: can_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg) +{ + caninfo("Fix me:Not Implemented\n"); + return 0; +} + +/**************************************************************************** + * Name: can_remoterequest + * + * Description: + * Send a remote request + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int can_remoterequest(FAR struct can_dev_s *dev, uint16_t id) +{ + caninfo("Fix me:Not Implemented\n"); + return 0; +} + +/**************************************************************************** + * Name: can_send + * + * Description: + * Send one can message. + * + * One CAN-message consists of a maximum of 10 bytes. A message is + * composed of at least the first 2 bytes (when there are no data bytes). + * + * Byte 0: Bits 0-7: Bits 3-10 of the 11-bit CAN identifier + * Byte 1: Bits 5-7: Bits 0-2 of the 11-bit CAN identifier + * Bit 4: Remote Tranmission Request (RTR) + * Bits 0-3: Data Length Code (DLC) + * Bytes 2-10: CAN data + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) +{ + FAR struct up_dev_s *priv = (FAR struct up_dev_s *) dev->cd_priv; + uint32_t regval; + uint32_t clz; + uint32_t id; + uint32_t dlc; + uint8_t txobj; + + if(msg == NULL) + { + return ERROR; + } + + regval = (can_getreg(priv, LPC43_CAN_MSGV2_OFFSET) & 0xFFFF); + clz = arm_clz(regval); + + if (clz == 0x10) + { + return ERROR; + } + + txobj = CAN_TX_OBJ_LAST - clz + CAN_TX_OBJ_FIRST; + DEBUGASSERT((txobj >= CAN_TX_OBJ_FIRST) && (txobj <= CAN_TX_OBJ_LAST)); + + id = (uint32_t) msg->cm_hdr.ch_id; + dlc = (uint32_t) msg->cm_hdr.ch_dlc; + + caninfo("CAN%d ID: %d DLC: %d\n", + priv->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc); + + can_putreg(priv, LPC43_CAN_IF1_MSK1_OFFSET, 0xFFFF); + can_putreg(priv, LPC43_CAN_IF1_MSK2_OFFSET, 0xFFFF); + + regval = ((dlc & CAN_MCTRL_DLC_MASK) | CAN_MCTRL_EOB | CAN_MCTRL_TXRQST + | CAN_MCTRL_TXIE ); + can_putreg(priv, LPC43_CAN_IF1_MCTRL_OFFSET, regval); + + /* Write data to IF1 data registers */ + + regval = msg->cm_data[0] + (msg->cm_data[1] << 8); + can_putreg(priv, LPC43_CAN_IF1_DA1_OFFSET, regval); + + regval = msg->cm_data[2] + (msg->cm_data[3] << 8); + can_putreg(priv, LPC43_CAN_IF1_DA2_OFFSET, regval); + + regval = msg->cm_data[4] + (msg->cm_data[5] << 8); + can_putreg(priv, LPC43_CAN_IF1_DB1_OFFSET, regval); + + regval = msg->cm_data[6] + (msg->cm_data[7] << 8); + can_putreg(priv, LPC43_CAN_IF1_DB2_OFFSET, regval); + +#ifdef CONFIG_CAN_EXTID + can_putreg(priv, LPC43_CAN_IF1_ARB1_OFFSET, id & 0x0000FFFF); + can_putreg(priv, LPC43_CAN_IF1_ARB2_OFFSET, CAN_MSK2_DIR | CAN_MSK2_XTD + | CAN_MSK2_MSGVAL | id >> 16); +#else + can_putreg(priv, LPC43_CAN_IF1_ARB1_OFFSET, 0x0000); + can_putreg(priv, LPC43_CAN_IF1_ARB2_OFFSET, CAN_MSK2_DIR | CAN_MSK2_MSGVAL + | id << 2); +#endif + + regval = (CAN_CMDMSKW_WRRD | CAN_CMDMSKW_MASK | CAN_CMDMSKW_ARB + | CAN_CMDMSKW_CTRL | CAN_CMDMSKW_CLRINTPND | CAN_CMDMSKW_TXRQST + | CAN_CMDMSKW_DATAA | CAN_CMDMSKW_DATAB); + can_putreg(priv, LPC43_CAN_IF1_CMDMSKW_OFFSET, regval); + + /* Write to Message RAM */ + + can_putreg(priv, LPC43_CAN_IF1_CMDREQ_OFFSET, txobj); + +#ifdef CONFIG_CAN_TXREADY + can_txdone(dev); +#endif + + return OK; +} + +/**************************************************************************** + * Name: candev_txready + * + * Description: + * Return true if the CAN hardware can accept another TX message. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * True if the CAN hardware is ready to accept another TX message. + * + ****************************************************************************/ + +static bool candev_txready(FAR struct can_dev_s *dev) +{ + FAR struct up_dev_s *priv = (FAR struct up_dev_s *) dev->cd_priv; + + if (can_getreg(priv, LPC43_CAN_MSGV2_OFFSET) & 0x8000) + { + return false; + } + + if (can_getreg(priv, LPC43_CAN_IF1_CMDREQ_OFFSET) & CAN_CMDREQ_BUSY) + { + return false; + } + + return true; +} + +/**************************************************************************** + * Name: candev_txempty + * + * Description: + * Return true if all message have been sent. If for example, the CAN + * hardware implements FIFOs, then this would mean the transmit FIFO is + * empty. This method is called when the driver needs to make sure that + * all characters are "drained" from the TX hardware before calling + * co_shutdown(). + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * True if there are no pending TX transfers in the CAN hardware. + * + ****************************************************************************/ + +static bool candev_txempty(FAR struct can_dev_s *dev) +{ + FAR struct up_dev_s *priv = (FAR struct up_dev_s *) dev->cd_priv; + return (!((can_getreg(priv, LPC43_CAN_MSGV2_OFFSET)) & 0xFFFF)); +} + +/**************************************************************************** + * Name: can0/1_interrupt + * + * Description: + * CAN interrupt handler for CAN0 and CAN1. + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + + +#ifdef CONFIG_LPC43_CAN0 +static int can0_interrupt(int irq, void *context, FAR void *arg) +{ + can_interrupt(&g_can0dev); + return OK; +} +#endif + +#ifdef CONFIG_LPC43_CAN1 +static int can1_interrupt(int irq, void *context, FAR void *arg) +{ + can_interrupt(&g_can1dev); + return OK; +} +#endif + +/**************************************************************************** + * Name: can_interrupt + * + * Description: + * CAN interrupt handler. There is a single interrupt for both CAN0 and + * CAN1. + * + ****************************************************************************/ + +static void can_interrupt(FAR struct can_dev_s *dev) +{ + FAR struct up_dev_s *priv = (FAR struct up_dev_s *) dev->cd_priv; + uint32_t regval = 0; + + uint32_t msgindex = 0; + + /* Read CAN interrupt register */ + + uint32_t interrupt = can_getreg(priv, LPC43_CAN_INT_OFFSET); + + /* Read CAN status register */ + + uint32_t stat = can_getreg(priv, LPC43_CAN_STAT_OFFSET); + + if ( interrupt & CAN_INT_STAT ) + { + /* Clear all warning/error states except RXOK/TXOK */ + + regval = can_getreg(priv, LPC43_CAN_STAT_OFFSET); + regval &= CAN_STAT_RXOK | CAN_STAT_TXOK; + can_putreg(priv, LPC43_CAN_STAT_OFFSET, regval); + } + else + { + msgindex = interrupt & 0x7FFF; + + /* if no error detected */ + + if (((stat & CAN_STAT_LEC_MASK) == 0) || + ((stat & CAN_STAT_LEC_MASK) == CAN_STAT_LEC_MASK)) + { + if (msgindex <= CAN_RX_OBJ_LAST) + { + struct can_hdr_s hdr; + uint32_t data[2]; + + regval = can_getreg(priv, LPC43_CAN_STAT_OFFSET); + regval &= ~CAN_STAT_RXOK; + can_putreg(priv, LPC43_CAN_STAT_OFFSET, regval); + + can_readobj(priv, msgindex); + can_savemsg(priv, &hdr, data); + can_invalobj(priv, msgindex); + can_receive(dev, &hdr, (uint8_t *)data); + } + else + { + regval = can_getreg(priv, LPC43_CAN_STAT_OFFSET); + regval &= ~CAN_STAT_TXOK; + can_putreg(priv, LPC43_CAN_STAT_OFFSET, regval); + + can_invalobj(priv, msgindex); +#ifdef CONFIG_CAN_TXREADY + can_txready(dev); +#else + can_txdone(dev); +#endif + } + } + else + { + can_invalobj(priv, msgindex); + } + + can_putreg(priv, LPC43_CAN_STAT_OFFSET, 0); + + if (msgindex == CAN_RX_OBJ_LAST) + { + can_setuprxobj(priv); + } + } +} + +/**************************************************************************** + * Name: can_savemsg + * + * Description: + * Save received message. + * + * Input Parameters: + * priv - A reference to the CAN block status + * hdr - A reference to the message header + * data - A reference to the data block + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void can_savemsg(struct up_dev_s *priv, struct can_hdr_s *hdr, + uint32_t *data) +{ +#ifdef CONFIG_CAN_EXTID + hdr->ch_id = (can_getreg(priv, LPC43_CAN_IF2_ARB1_OFFSET) & 0xFFFF) | + (can_getreg(priv, LPC43_CAN_IF2_ARB2_OFFSET) & 0x0FFF) << 16; + hdr->ch_extid = 1; +#else + hdr->ch_id = (can_getreg(priv, LPC43_CAN_IF2_ARB2_OFFSET) & 0x1FFF) >> 2; +#endif + hdr->ch_dlc = can_getreg(priv, LPC43_CAN_IF2_MCTRL_OFFSET) & 0x000F; + hdr->ch_rtr = 0; + + data[0] = can_getreg(priv, LPC43_CAN_IF2_DA2_OFFSET) << 16 | + can_getreg(priv, LPC43_CAN_IF2_DA1_OFFSET); + data[1] = can_getreg(priv, LPC43_CAN_IF2_DB2_OFFSET) << 16 | + can_getreg(priv, LPC43_CAN_IF2_DB1_OFFSET); +} + +/**************************************************************************** + * Name: can_readobj + * + * Description: + * Transfer Message Object into IF registers. + * + * Input Parameters: + * priv - A reference to the CAN block status + * index - Message Object number + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void can_readobj(struct up_dev_s *priv, uint32_t index) +{ + uint32_t regval; + + while (can_getreg(priv, LPC43_CAN_IF2_CMDREQ_OFFSET) & CAN_CMDREQ_BUSY); + + regval = (CAN_CMDMSKR_MASK | CAN_CMDMSKR_ARB | CAN_CMDMSKR_CTRL | + CAN_CMDMSKR_CLRINTPND | CAN_CMDMSKR_DATAA | CAN_CMDMSKR_DATAB); + can_putreg(priv, LPC43_CAN_IF2_CMDMSKR_OFFSET, regval); + can_putreg(priv, LPC43_CAN_IF2_CMDREQ_OFFSET, index); +} + +/**************************************************************************** + * Name: can_invalobj + * + * Description: + * Invalidate Message Object. + * + * Input Parameters: + * priv - A reference to the CAN block status + * index - Message Object number + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void can_invalobj(struct up_dev_s *priv, uint32_t index) +{ + while (can_getreg(priv, LPC43_CAN_IF2_CMDREQ_OFFSET) & CAN_CMDREQ_BUSY); + + can_putreg(priv, LPC43_CAN_IF2_ARB1_OFFSET, 0x0000); + can_putreg(priv, LPC43_CAN_IF2_ARB2_OFFSET, 0x0000); + + /* Disable reception and transmission interrupts, clear transmit request */ + + can_putreg(priv, LPC43_CAN_IF2_MCTRL_OFFSET, CAN_MCTRL_EOB); + can_putreg(priv, LPC43_CAN_IF2_CMDMSKW_OFFSET, CAN_CMDMSKW_WRRD + | CAN_CMDMSKW_CLRINTPND | CAN_CMDMSKW_CTRL | CAN_CMDMSKW_ARB); + can_putreg(priv, LPC43_CAN_IF2_CMDREQ_OFFSET, index); +} + +/**************************************************************************** + * Name: can_setuprxobj + * + * Description: + * Setup Message Object as buffer for received messages. + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void can_setuprxobj(struct up_dev_s *priv) +{ + uint32_t regval; + uint8_t i; + + while (can_getreg(priv, LPC43_CAN_IF2_CMDREQ_OFFSET) & CAN_CMDREQ_BUSY); + + can_putreg(priv, LPC43_CAN_IF2_MSK1_OFFSET, 0x0000); + regval = (CAN_MSK2_MXTD | CAN_MSK2_MDIR); + can_putreg(priv, LPC43_CAN_IF2_MSK2_OFFSET, regval); + + regval = (CAN_MCTRL_DLC_MASK | CAN_MCTRL_EOB | CAN_MCTRL_RXIE | + CAN_MCTRL_UMASK); + can_putreg(priv, LPC43_CAN_IF2_MCTRL_OFFSET, regval); + + can_putreg(priv, LPC43_CAN_IF2_ARB1_OFFSET, 0x0000); +#ifdef CONFIG_CAN_EXTID + can_putreg(priv, LPC43_CAN_IF2_ARB2_OFFSET, CAN_MSK2_MSGVAL | CAN_MSK2_XTD); +#else + can_putreg(priv, LPC43_CAN_IF2_ARB2_OFFSET, CAN_MSK2_MSGVAL); +#endif + + regval = (CAN_CMDMSKR_WRRD | CAN_CMDMSKR_MASK | CAN_CMDMSKR_ARB | + CAN_CMDMSKR_CTRL | CAN_CMDMSKR_CLRINTPND | CAN_CMDMSKR_DATAA | + CAN_CMDMSKR_DATAB); + can_putreg(priv, LPC43_CAN_IF2_CMDMSKR_OFFSET, regval); + + for (i = CAN_RX_OBJ_FIRST; i <= CAN_RX_OBJ_LAST; ++i) + { + while (can_getreg(priv, LPC43_CAN_IF2_CMDREQ_OFFSET) & CAN_CMDREQ_BUSY); + can_putreg(priv, LPC43_CAN_IF2_CMDREQ_OFFSET, i); + } +} + +/**************************************************************************** + * Name: can_bittiming + * + * Description: + * Set the CAN bit timing register (BTR) based on the configured BAUD. + * + * The bit timing logic monitors the serial bus-line and performs sampling + * and adjustment of the sample point by synchronizing on the start-bit edge + * and resynchronizing on the following edges. + * + * Its operation may be explained simply by splitting nominal bit time into + * three segments as follows: + * + * 1. Synchronization segment (SYNC_SEG): a bit change is expected to occur + * within this time segment. It has a fixed length of one time quantum + * (1 x tCAN). + * 2. Bit segment 1 (BS1): defines the location of the sample point. It + * includes the PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration + * is programmable between 1 and 16 time quanta but may be automatically + * lengthened to compensate for positive phase drifts due to differences + * in the frequency of the various nodes of the network. + * 3. Bit segment 2 (BS2): defines the location of the transmit point. It + * represents the PHASE_SEG2 of the CAN standard. Its duration is + * programmable between 1 and 8 time quanta but may also be automatically + * shortened to compensate for negative phase drifts. + * + * Pictorially: + * + * |<----------------- NOMINAL BIT TIME ----------------->| + * |<- SYNC_SEG ->|<------ BS1 ------>|<------ BS2 ------>| + * |<---- Tq ---->|<----- Tbs1 ------>|<----- Tbs2 ------>| + * + * Where + * Tbs1 is the duration of the BS1 segment + * Tbs2 is the duration of the BS2 segment + * Tq is the "Time Quantum" + * + * Relationships: + * + * baud = 1 / bit_time + * bit_time = Tq + Tbs1 + Tbs2 + * Tbs1 = Tq * ts1 + * Tbs2 = Tq * ts2 + * Tq = brp * Tcan + * + * Where: + * Tcan is the period of the APB clock (PCLK = CCLK / CONFIG_CAN1_DIVISOR). + * + * Input Parameter: + * priv - A reference to the CAN block status + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int can_bittiming(struct up_dev_s *priv) +{ + uint32_t ts1 = CONFIG_CAN_TSEG1; + uint32_t ts2 = CONFIG_CAN_TSEG2; + uint32_t sjw = 1; + uint32_t brp = CAN_CLOCK_FREQUENCY(priv->clkdiv) / + (priv->baud * CAN_BIT_QUANTA); + + uint32_t regval; + + canllvdbg("CAN%d PCLK: %d baud: %d\n", + priv->port, CAN_CLOCK_FREQUENCY(priv->clkdiv), priv->baud); + canllvdbg("TS1: %d TS2: %d BRP: %d SJW= %d\n", ts1, ts2, brp, sjw); + + /* Start configuring bit timing */ + + regval = can_getreg(priv, LPC43_CAN_CNTL_OFFSET); + regval |= CAN_CNTL_CCE; + can_putreg(priv, LPC43_CAN_CNTL_OFFSET, regval); + + regval = (((brp - 1) << CAN_BT_BRP_SHIFT) + | ((ts1 - 1) << CAN_BT_TSEG1_SHIFT) + | ((ts2 - 1) << CAN_BT_TSEG2_SHIFT) + | ((sjw - 1) << CAN_BT_SJW_SHIFT)); + + canllvdbg("Setting CANxBTR= 0x%08x\n", regval); + + /* Set bit timing */ + + can_putreg(priv, LPC43_CAN_BT_OFFSET, regval); + + /* Stop configuring bit timing */ + + regval = can_getreg(priv, LPC43_CAN_CNTL_OFFSET); + regval &= ~CAN_CNTL_CCE; + can_putreg(priv, LPC43_CAN_CNTL_OFFSET, regval); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc43_caninitialize + * + * Description: + * Initialize the selected can port + * + * Input Parameter: + * Port number (for hardware that has mutiple can interfaces) + * + * Returned Value: + * Valid can device structure reference on succcess; a NULL on failure + * + ****************************************************************************/ + +FAR struct can_dev_s *lpc43_caninitialize(int port) +{ + FAR struct can_dev_s *candev; + irqstate_t flags; + uint32_t regval; + + canllvdbg("CAN%d\n", port); + + flags = enter_critical_section(); + +#ifdef CONFIG_LPC43_CAN0 + if (port == 0) + { + /* Enable clock */ + + regval = getreg32(LPC43_CCU1_APB3_CAN0_CFG); + regval |= CCU_CLK_CFG_RUN; + putreg32(regval, LPC43_CCU1_APB3_CAN0_CFG); + + /* Configure CAN GPIO pins */ + + lpc43_pin_config(PINCONF_CAN0_RD); + lpc43_pin_config(PINCONF_CAN0_TD); + + candev = &g_can0dev; + } + else +#endif /* CONFIG_LPC43_CAN0 */ + +#ifdef CONFIG_LPC43_CAN1 + if (port == 1) + { + /* Enable clock */ + + regval = getreg32(LPC43_CCU1_APB1_CAN1_CFG); + regval |= CCU_CLK_CFG_RUN; + putreg32(regval, LPC43_CCU1_APB1_CAN1_CFG); + + /* Configure CAN GPIO pins */ + + lpc43_pin_config(PINCONF_CAN1_RD); + lpc43_pin_config(PINCONF_CAN1_TD); + + candev = &g_can1dev; + } + else +#endif /* CONFIG_LPC43_CAN1 */ + { + canerr("Unsupported port: %d\n", port); + + leave_critical_section(flags); + return NULL; + } + + leave_critical_section(flags); + + return candev; +} +#endif diff --git a/arch/arm/src/lpc43xx/lpc43_can.h b/arch/arm/src/lpc43xx/lpc43_can.h new file mode 100644 index 0000000000000000000000000000000000000000..f321c9b72fa087ce403f8e48a75e92847a90b28d --- /dev/null +++ b/arch/arm/src/lpc43xx/lpc43_can.h @@ -0,0 +1,85 @@ +/**************************************************************************** + * arch/arm/src/lpc43xx/lpc43_can.h + * + * Copyright(C) 2017 Gregory Nutt. All rights reserved. + * + * Created on: 2 May 2017 + * Author: katherine + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_CAN_H_ +#define __ARCH_ARM_SRC_LPC43XX_LPC43_CAN_H_ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip/lpc43_can.h" + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * Name: lpc43_caninitialize + * + * Description: + * Initialize the selected can port + * + * Input Parameter: + * Port number (for hardware that has mutiple can interfaces) + * + * Returned Value: + * Valid can device structure reference on succcess; a NULL on failure + * + ****************************************************************************/ + +#if defined(CONFIG_CAN) && (defined(CONFIG_LPC43_CAN0) || defined(CONFIG_LPC43_CAN1)) +struct can_dev_s; +FAR struct can_dev_s *lpc43_caninitialize(int port); +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_CAN_H_ */ diff --git a/arch/arm/src/lpc43xx/lpc43_clrpend.c b/arch/arm/src/lpc43xx/lpc43_clrpend.c index cb3ce5f095e1798f1550e77436457d426f6c234b..4363923e77dc1ae4f1ccdc8027af724ecf9fed14 100644 --- a/arch/arm/src/lpc43xx/lpc43_clrpend.c +++ b/arch/arm/src/lpc43xx/lpc43_clrpend.c @@ -1,6 +1,5 @@ /**************************************************************************** * arch/arm/src/lpc43/lpc43_clrpend.c - * arch/arm/src/chip/lpc43_clrpend.c * * Copyright (C) 2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c index 955c30684e147e8b048bb8e71f431bac3c23b2a6..f5a9cb1e580215f2988447e8a629e9d314fafcf4 100644 --- a/arch/arm/src/lpc43xx/lpc43_ethernet.c +++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c @@ -3210,11 +3210,11 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv) #else /* Auto-negotion not selected */ #ifdef CONFIG_LPC43_ETHFD - priv->mbps100 = 1; + priv->fduplex = 1; #endif #ifdef CONFIG_LPC43_ETH100MBPS - priv->fduplex = 1; + priv->mbps100 = 1; #endif phyval = 0; @@ -3238,11 +3238,14 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv) up_mdelay(PHY_CONFIG_DELAY); - /* Remember the selected speed and duplex modes */ + /* Remember the selected speed and duplex modes + * REVISIT: Isn't this redundant? + */ #ifdef CONFIG_LPC43_ETHFD priv->fduplex = 1; #endif + #ifdef CONFIG_LPC43_ETH100MBPS priv->mbps100 = 1; #endif diff --git a/arch/arm/src/lpc43xx/lpc43_gpdma.c b/arch/arm/src/lpc43xx/lpc43_gpdma.c index d2c0f3bace5f1ce62c39a40f6076918ee0d8ec0e..f68577e1311aa059373ddd7a069ace4b60ee2340 100644 --- a/arch/arm/src/lpc43xx/lpc43_gpdma.c +++ b/arch/arm/src/lpc43xx/lpc43_gpdma.c @@ -269,13 +269,14 @@ static int gpdma_interrupt(int irq, FAR void *context, FAR void *arg) ****************************************************************************/ /**************************************************************************** - * Name: lpc43_dmainitialize + * Name: up_dmainitialize * * Description: - * Initialize the GPDMA subsystem. + * Initialize the GPDMA subsystem. Called from up_initialize() early in the + * boot-up sequence. Prototyped in up_internal.h. * * Returned Value: - * Zero on success; A negated errno value on failure. + * None * ****************************************************************************/ @@ -628,7 +629,7 @@ void lpc43_dmastop(DMA_HANDLE handle) DEBUGASSERT(dmach && dmach->inuse); /* Disable this channel and mask any further interrupts from the channel. - * this channel. The channel is disabled by clearning the channel + * this channel. The channel is disabled by clearing the channel * enable bit. Any outstanding data in the FIFOs is lost. */ diff --git a/arch/arm/src/lpc43xx/lpc43_gpdma.h b/arch/arm/src/lpc43xx/lpc43_gpdma.h index ecf35f0834f771e5e947a53e3f131099188547d7..db304c801af2fe31dbb5b263eb23fa89d2def8c3 100644 --- a/arch/arm/src/lpc43xx/lpc43_gpdma.h +++ b/arch/arm/src/lpc43xx/lpc43_gpdma.h @@ -119,19 +119,6 @@ extern "C" * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: lpc43_dmainitialize - * - * Description: - * Initialize the GPDMA subsystem. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void lpc43_dmainitilaize(void); - /**************************************************************************** * Name: lpc43_dmachannel * diff --git a/arch/arm/src/lpc43xx/lpc43_mpuinit.c b/arch/arm/src/lpc43xx/lpc43_mpuinit.c index 3ed8d8a8c740f23bb6f86337f18a8b7e918a6466..e1ad602ab313a4877d8a48f0bb137800e8ac93d8 100644 --- a/arch/arm/src/lpc43xx/lpc43_mpuinit.c +++ b/arch/arm/src/lpc43xx/lpc43_mpuinit.c @@ -60,14 +60,6 @@ # define MIN(a,b) a < b ? a : b #endif -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/arm/src/lpc43xx/lpc43_mpuinit.h b/arch/arm/src/lpc43xx/lpc43_mpuinit.h index f4c6c59ca3479599330ca9f0a000d589b026ca0a..8b09dabad6c83c6b1a1526d66e3f1dcadc64a2a7 100644 --- a/arch/arm/src/lpc43xx/lpc43_mpuinit.h +++ b/arch/arm/src/lpc43xx/lpc43_mpuinit.h @@ -43,19 +43,7 @@ #include /************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions + * Public Function Prototypes ************************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/lpc43xx/lpc43_rtc.c b/arch/arm/src/lpc43xx/lpc43_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..9afc1529779cd72dd3d941b69828b59075ca2c1e --- /dev/null +++ b/arch/arm/src/lpc43xx/lpc43_rtc.c @@ -0,0 +1,404 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/lpc43_rtc.c + * + * Copyright (C) 2014, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Adapted for the LPC43xx by Gintaras Drukteinis from the similar LCP176x RTC driver. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" +#include "chip.h" +#include "chip/lpc43_creg.h" +#include "chip/lpc43_rtc.h" +#include "lpc43_rtc.h" + +#ifdef CONFIG_RTC + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration ********************************************************************/ +/* This RTC implementation supports only date/time RTC hardware */ + +#ifndef CONFIG_RTC_DATETIME +# error "CONFIG_RTC_DATETIME must be set to use this driver" +#endif + +#ifdef CONFIG_RTC_HIRES +# error "CONFIG_RTC_HIRES must NOT be set with this driver" +#endif + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +/* Callback to use when the alarm expires */ + +#ifdef CONFIG_RTC_ALARM +static alarmcb_t g_alarmcb; +#endif + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/* g_rtc_enabled is set true after the RTC has successfully initialized */ + +volatile bool g_rtc_enabled = false; + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: rtc_dumpregs + * + * Description: + * Disable RTC write protection + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ************************************************************************************/ + +#ifdef CONFIG_DEBUG_RTC_INFO +static void rtc_dumpregs(FAR const char *msg) +{ + rtcinfo("%s:\n", msg); + rtcinfo(" DOM : %08x\n", (getreg32(LPC43_RTC_DOM) & RTC_DOM_MASK)); + rtcinfo(" DOW : %08x\n", (getreg32(LPC43_RTC_DOW) & RTC_DOW_MASK)); +} +#else +# define rtc_dumpregs(msg) +#endif + +/************************************************************************************ + * Name: rtc_dumptime + * + * Description: + * Disable RTC write protection + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ************************************************************************************/ + +#ifdef CONFIG_DEBUG_RTC_INFO +static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg) +{ + rtcinfo("%s:\n", msg); + rtcinfo(" tm_sec: %08x\n", tp->tm_sec); + rtcinfo(" tm_min: %08x\n", tp->tm_min); + rtcinfo(" tm_hour: %08x\n", tp->tm_hour); + rtcinfo(" tm_mday: %08x\n", tp->tm_mday); + rtcinfo(" tm_mon: %08x\n", tp->tm_mon); + rtcinfo(" tm_year: %08x\n", tp->tm_year); +} +#else +# define rtc_dumptime(tp, msg) +#endif + +/************************************************************************************ + * Name: rtc_setup + * + * Description: + * Performs first time configuration of the RTC. A special value written into + * back-up register 0 will prevent this function from being called on sub-sequent + * resets or power up. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ************************************************************************************/ + +static int rtc_setup(void) +{ + uint32_t regval; + + /* Enable RTC Clock */ + + regval = getreg32(LPC43_CREG0); + regval &= ~(CREG0_RESET32KHZ | CREG0_PD32KHZ); /* Reset 32Khz oscillator */ + putreg32(regval, LPC43_CREG0); + + regval = getreg32(LPC43_CREG0); + regval |= (CREG0_EN1KHZ | CREG0_EN32KHZ); /* Enable 32 kHz & 1 kHz on osc32k and release reset */ + putreg32(regval, LPC43_CREG0); + + /* Clear all register to be default */ + + putreg32((uint32_t)0x00, LPC43_RTC_ILR); + putreg32((uint32_t)0x00, LPC43_RTC_CCR); + putreg32((uint32_t)0x00, LPC43_RTC_CIIR); + putreg32((uint32_t)0xff, LPC43_RTC_AMR); + putreg32((uint32_t)0x00, LPC43_RTC_CALIB); + + /* Enable counters */ + + putreg32((uint32_t)0x01, LPC43_RTC_CCR); + return OK; +} + +/************************************************************************************ + * Name: rtc_interrupt + * + * Description: + * RTC interrupt service routine + * + * Input Parameters: + * irq - The IRQ number that generated the interrupt + * context - Architecture specific register save information. + * + * Returned Value: + * Zero (OK) on success; A negated errno value on failure. + * + ************************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtc_interrupt(int irq, void *context) +{ +#warning "Missing logic" + return OK; +} +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: up_rtc_initialize + * + * Description: + * Initialize the hardware RTC per the selected configuration. This function is + * called once during the OS initialization sequence + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ************************************************************************************/ + +int up_rtc_initialize(void) +{ + int ret; + + rtc_dumpregs("On reset"); + +#ifdef CONFIG_RTC_ALARM + /* Attach the RTC interrupt handler */ + + ret = irq_attach(LPC43M4_IRQ_RTC, rtc_interrupt); + if (ret == OK) + { + up_enable_irq(LPC43M4_IRQ_RTC); + } +#endif /* CONFIG_RTC_ALARM */ + + /* Perform the one-time setup of the RTC */ + + ret = rtc_setup(); + + /* Configure RTC interrupt to catch alarm interrupts. All RTC interrupts are + * connected to the EXTI controller. To enable the RTC Alarm interrupt, the + * following sequence is required: + * + * 1. Configure and enable the EXTI Line 17 in interrupt mode and select the + * rising edge sensitivity. + * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC. + * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). + */ + + g_rtc_enabled = true; + rtc_dumpregs("After Initialization"); + return ret; +} + +/************************************************************************************ + * Name: up_rtc_getdatetime + * + * Description: + * Get the current date and time from the date/time RTC. This interface + * is only supported by the date/time RTC hardware implementation. + * It is used to replace the system timer. It is only used by the RTOS during + * initialization to set up the system time when CONFIG_RTC and CONFIG_RTC_DATETIME + * are selected (and CONFIG_RTC_HIRES is not). + * + * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. That + * sub-second accuracy is lost in this interface. However, since the system time + * is reinitialized on each power-up/reset, there will be no timing inaccuracy in + * the long run. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ************************************************************************************/ + +int up_rtc_getdatetime(FAR struct tm *tp) +{ + rtc_dumpregs("Reading Time"); + + /* Convert the RTC time to fields in struct tm format.*/ + + tp->tm_sec = ((getreg32(LPC43_RTC_SEC) & RTC_SEC_MASK)); + tp->tm_min = ((getreg32(LPC43_RTC_MIN) & RTC_MIN_MASK)); + tp->tm_hour = ((getreg32(LPC43_RTC_HOUR) & RTC_HOUR_MASK)); + + /* Now convert the RTC date to fields in struct tm format*/ + + tp->tm_mday = ((getreg32(LPC43_RTC_DOM) & RTC_DOM_MASK)); + tp->tm_mon = ((getreg32(LPC43_RTC_MONTH) & RTC_MONTH_MASK)) - 1; + tp->tm_year = ((getreg32(LPC43_RTC_YEAR) & RTC_YEAR_MASK)-1900); + +#if defined(CONFIG_LIBC_LOCALTIME) || defined(CONFIG_TIME_EXTENDED) + tp->tm_wday = ((getreg32(LPC43_RTC_DOW) & RTC_DOW_MASK)); + tp->tm_yday = ((getreg32(LPC43_RTC_DOY) & RTC_DOY_MASK)); +#endif + + rtc_dumptime(tp, "Returning"); + return OK; +} + +/************************************************************************************ + * Name: up_rtc_settime + * + * Description: + * Set the RTC to the provided time. All RTC implementations must be able to + * set their time based on a standard timespec. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ************************************************************************************/ + +int up_rtc_settime(FAR const struct timespec *tp) +{ + FAR struct tm newtime; + + /* Break out the time values (not that the time is set only to units of seconds) */ + + (void)gmtime_r(&tp->tv_sec, &newtime); + rtc_dumptime(&newtime, "Setting time"); + + /* Then write the broken out values to the RTC */ + + putreg32(((newtime.tm_sec) & RTC_SEC_MASK), LPC43_RTC_SEC); + putreg32(((newtime.tm_min) & RTC_MIN_MASK), LPC43_RTC_MIN); + putreg32(((newtime.tm_hour) & RTC_HOUR_MASK), LPC43_RTC_HOUR); + putreg32(((newtime.tm_mday) & RTC_DOM_MASK), LPC43_RTC_DOM); + putreg32((((newtime.tm_mon)+1) & RTC_MONTH_MASK), LPC43_RTC_MONTH); + putreg32(((newtime.tm_year) & RTC_YEAR_MASK)+1900, LPC43_RTC_YEAR); + +#if defined(CONFIG_LIBC_LOCALTIME) || defined(CONFIG_TIME_EXTENDED) + putreg32(((newtime.tm_wday) & RTC_DOW_MASK), LPC43_RTC_DOW); + putreg32(((newtime.tm_yday) & RTC_DOY_MASK), LPC43_RTC_DOY); +#endif + + return OK; +} + +/************************************************************************************ + * Name: lpc43_rtc_setalarm + * + * Description: + * Set up an alarm. Up to two alarms can be supported (ALARM A and ALARM B). + * + * Input Parameters: + * tp - the time to set the alarm + * callback - the function to call when the alarm expires. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ************************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int lpc43_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) +{ + int ret = -EBUSY; + + /* Is there already something waiting on the ALARM? */ + + if (g_alarmcb == NULL) + { + /* No.. Save the callback function pointer */ + + g_alarmcb = callback; + + /* Break out the time values */ +#warning "Missing logic" + + /* The set the alarm */ +#warning "Missing logic" + + ret = OK; + } + return ret; +} +#endif + +#endif /* CONFIG_RTC */ diff --git a/arch/arm/src/lpc43xx/lpc43_rtc.h b/arch/arm/src/lpc43xx/lpc43_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..11daa161d5c95e44187337d2f574525aeaa16230 --- /dev/null +++ b/arch/arm/src/lpc43xx/lpc43_rtc.h @@ -0,0 +1,51 @@ +/**************************************************************************** + * arch/arm/src/lpc43xx/lpc43_rtc.h + * + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. + * Author: Brandon Warhurst + * + * Adapted from the similar LCP17xx RTC by Gintaras Drukteinis. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H +#define __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H */ \ No newline at end of file diff --git a/arch/arm/src/lpc43xx/lpc43_sdmmc.c b/arch/arm/src/lpc43xx/lpc43_sdmmc.c new file mode 100644 index 0000000000000000000000000000000000000000..5d4df400b3f00723a24d9da7dc3e03ff33cce892 --- /dev/null +++ b/arch/arm/src/lpc43xx/lpc43_sdmmc.c @@ -0,0 +1,2792 @@ +/**************************************************************************** + * arch/arm/src/lpc43xx/lpc43_sdmmc.c + * + * Copyright (C) 2017 Alan Carvalho de Assis. All rights reserved. + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Alan Carvalho de Assis + * + * This code is based on arch/arm/src/lpc17xx/lpc17_sdcard.c: + * + * Copyright (C) 2013-2014, 2016-2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "up_arch.h" + +#include "chip/lpc43_pinconfig.h" +#include "lpc43_cgu.h" +#include "lpc43_ccu.h" +#include "lpc43_gpio.h" +#include "lpc43_sdmmc.h" + +#include + +#ifdef CONFIG_LPC43_SDMMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MCI_DMADES0_OWN (1UL << 31) +#define MCI_DMADES0_CH (1 << 4) +#define MCI_DMADES0_FS (1 << 3) +#define MCI_DMADES0_LD (1 << 2) +#define MCI_DMADES0_DIC (1 << 1) +#define MCI_DMADES1_MAXTR 4096 +#define MCI_DMADES1_BS1(x) (x) + +/* Configuration ************************************************************/ +/* Required system configuration options in the sched/Kconfig: + * + * CONFIG_SCHED_WORKQUEUE -- Callback support requires work queue support. + * + * Driver-specific configuration options in the drivers/mmcd Kdonfig: + * + * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking + * APIs to manage concurrent accesses on the SD card bus. This is not + * needed for the simple case of a single SD card slot, for example. + * CONFIG_SDIO_WIDTH_D1_ONLY - This may be selected to force the driver + * operate with only a single data line (the default is to use all + * 4 SD data lines). + * CONFIG_MMCSD_HAVE_CARDDETECT - Select if the SD slot supports a card + * detect pin. + * CONFIG_MMCSD_HAVE_WRITEPROTECT - Select if the SD slots supports a + * write protected pin. + * + * Driver-specific configuration options in the arch/arm/src/lpc43xx/Kconfig + * + * CONFIG_LPC43_SDMMC_PWRCTRL - Select if the board supports an output + * pin to enable power to the SD slot. + * CONFIG_LPC43_SDMMC_DMA - Enable SD card DMA. This is a marginally + * optional. For most usages, SD accesses will cause data overruns if + * used without DMA. This will also select CONFIG_SDIO_DMA. + * CONFIG_LPC43_SDMMC_REGDEBUG - Enables some very low-level debug output + * This also requires CONFIG_DEBUG_MEMCARD_INFO + */ + +#ifndef CONFIG_SCHED_WORKQUEUE +# error "Callback support requires CONFIG_SCHED_WORKQUEUE" +#endif + +/* Timing */ + +#define SDCARD_CMDTIMEOUT (10000) +#define SDCARD_LONGTIMEOUT (0x7fffffff) + +/* Type of Card Bus Size */ + +#define SDCARD_BUS_D1 0 +#define SDCARD_BUS_D4 1 +#define SDCARD_BUS_D8 0x100 + +/* FIFO size in bytes */ + +#define LPC43_TXFIFO_SIZE (LPC43_TXFIFO_DEPTH | LPC43_TXFIFO_WIDTH) +#define LPC43_RXFIFO_SIZE (LPC43_RXFIFO_DEPTH | LPC43_RXFIFO_WIDTH) + +/* Data transfer interrupt mask bits */ + +#define SDCARD_RECV_MASK (SDMMC_INT_DTO | SDMMC_INT_DCRC | SDMMC_INT_DRTO | \ + SDMMC_INT_EBE | SDMMC_INT_RXDR | SDMMC_INT_SBE) +#define SDCARD_SEND_MASK (SDMMC_INT_DTO | SDMMC_INT_DCRC | SDMMC_INT_DRTO | \ + SDMMC_INT_EBE | SDMMC_INT_TXDR | SDMMC_INT_SBE) + +#define SDCARD_DMARECV_MASK (SDMMC_INT_DTO | SDMMC_INT_DCRC | SDMMC_INT_DRTO | \ + SDMMC_INT_SBE | SDMMC_INT_EBE) +#define SDCARD_DMASEND_MASK (SDMMC_INT_DTO | SDMMC_INT_DCRC | SDMMC_INT_DRTO | \ + SDMMC_INT_EBE) + +#define SDCARD_DMAERROR_MASK (SDMMC_IDINTEN_FBE | SDMMC_IDINTEN_DU | \ + SDMMC_IDINTEN_AIS) + +#define SDCARD_TRANSFER_ALL (SDMMC_INT_DTO | SDMMC_INT_DCRC | SDMMC_INT_DRTO | \ + SDMMC_INT_EBE | SDMMC_INT_TXDR | SDMMC_INT_RXDR | \ + SDMMC_INT_SBE) + +/* Event waiting interrupt mask bits */ + +#define SDCARD_INT_RESPERR (SDMMC_INT_RE | SDMMC_INT_RCRC | SDMMC_INT_RTO) + +#ifdef CONFIG_MMCSD_HAVE_CARDDETECT +# define SDCARD_INT_CDET SDMMC_INT_CDET +#else +# define SDCARD_INT_CDET 0 +#endif + +#define SDCARD_CMDDONE_STA (SDMMC_INT_CDONE) +#define SDCARD_RESPDONE_STA (0) + +#define SDCARD_CMDDONE_MASK (SDMMC_INT_CDONE) +#define SDCARD_RESPDONE_MASK (SDMMC_INT_CDONE | SDCARD_INT_RESPERR) +#define SDCARD_XFRDONE_MASK (0) /* Handled by transfer masks */ + +#define SDCARD_CMDDONE_CLEAR (SDMMC_INT_CDONE) +#define SDCARD_RESPDONE_CLEAR (SDMMC_INT_CDONE | SDCARD_INT_RESPERR) + +#define SDCARD_XFRDONE_CLEAR (SDCARD_TRANSFER_ALL) + +#define SDCARD_WAITALL_CLEAR (SDCARD_CMDDONE_CLEAR | SDCARD_RESPDONE_CLEAR | \ + SDCARD_XFRDONE_CLEAR) + +/* Let's wait until we have both SD card transfer complete and DMA complete. */ + +#define SDCARD_XFRDONE_FLAG (1) +#define SDCARD_DMADONE_FLAG (2) +#define SDCARD_ALLDONE (3) + +/* Card debounce time. Number of host clocks (SD_CLK) used by debounce + * filter logic for card detect. typical debounce time is 5-25 ms. + * + * Eg. Fsd = 44MHz, ticks = 660,000 + */ + +#define DEBOUNCE_TICKS (15 * BOARD_SDMMC_FREQUENCY / 1000) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct sdmmc_dma_s +{ + volatile uint32_t des0; /* Control and status */ + volatile uint32_t des1; /* Buffer size(s) */ + volatile uint32_t des2; /* Buffer address pointer 1 */ + volatile uint32_t des3; /* Buffer address pointer 2 */ +}; + +/* This structure defines the state of the LPC43XX SD card interface */ + +struct lpc43_dev_s +{ + struct sdio_dev_s dev; /* Standard, base SD card interface */ + + /* LPC43XX-specific extensions */ + /* Event support */ + + sem_t waitsem; /* Implements event waiting */ + sdio_eventset_t waitevents; /* Set of events to be waited for */ + uint32_t waitmask; /* Interrupt enables for event waiting */ + volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */ + WDOG_ID waitwdog; /* Watchdog that handles event timeouts */ + + /* Callback support */ + + sdio_statset_t cdstatus; /* Card status */ + sdio_eventset_t cbevents; /* Set of events to be cause callbacks */ + worker_t callback; /* Registered callback function */ + void *cbarg; /* Registered callback argument */ + struct work_s cbwork; /* Callback work queue structure */ + + /* Interrupt mode data transfer support */ + + uint32_t *buffer; /* Address of current R/W buffer */ + uint32_t xfrmask; /* Interrupt enables for data transfer */ +#ifdef CONFIG_LPC43_SDMMC_DMA + uint32_t dmamask; /* Interrupt enables for DMA transfer */ +#endif + ssize_t remaining; /* Number of bytes remaining in the transfer */ + bool wrdir; /* True: Writing False: Reading */ + + /* DMA data transfer support */ + + bool widebus; /* Required for DMA support */ +#ifdef CONFIG_LPC43_SDMMC_DMA + bool dmamode; /* true: DMA mode transfer */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_LPC43_SDMMC_REGDEBUG +static uint32_t lpc43_getreg(uint32_t addr); +static void lpc43_putreg(uint32_t val, uint32_t addr); +#else +# define lpc43_getreg(addr) getreg32(addr) +# define lpc43_putreg(val,addr) putreg32(val,addr) +#endif + +/* Low-level helpers ********************************************************/ + +static void lpc43_takesem(struct lpc43_dev_s *priv); +#define lpc43_givesem(priv) (sem_post(&priv->waitsem)) +static inline void lpc43_setclock(uint32_t clkdiv); +static inline void lpc43_sdcard_clock(bool enable); +static int lpc43_ciu_sendcmd(uint32_t cmd, uint32_t arg); +static void lpc43_enable_ints(struct lpc43_dev_s *priv); +static void lpc43_disable_allints(struct lpc43_dev_s *priv); +static void lpc43_config_waitints(struct lpc43_dev_s *priv, uint32_t waitmask, + sdio_eventset_t waitevents, sdio_eventset_t wkupevents); +static void lpc43_config_xfrints(struct lpc43_dev_s *priv, uint32_t xfrmask); +#ifdef CONFIG_LPC43_SDMMC_DMA +static void lpc43_config_dmaints(struct lpc43_dev_s *priv, uint32_t xfrmask, + uint32_t dmamask); +#endif + +/* Data Transfer Helpers ****************************************************/ + +static void lpc43_eventtimeout(int argc, uint32_t arg); +static void lpc43_endwait(struct lpc43_dev_s *priv, sdio_eventset_t wkupevent); +static void lpc43_endtransfer(struct lpc43_dev_s *priv, sdio_eventset_t wkupevent); + +/* Interrupt Handling *******************************************************/ + +static int lpc43_sdmmc_interrupt(int irq, void *context, FAR void *arg); + +/* SD Card Interface Methods ************************************************/ + +/* Mutual exclusion */ + +#ifdef CONFIG_SDIO_MUXBUS +static int lpc43_lock(FAR struct sdio_dev_s *dev, bool lock); +#endif + +/* Initialization/setup */ + +static void lpc43_reset(FAR struct sdio_dev_s *dev); +static sdio_capset_t lpc43_capabilities(FAR struct sdio_dev_s *dev); +static uint8_t lpc43_status(FAR struct sdio_dev_s *dev); +static void lpc43_widebus(FAR struct sdio_dev_s *dev, bool enable); +static void lpc43_clock(FAR struct sdio_dev_s *dev, + enum sdio_clock_e rate); +static int lpc43_attach(FAR struct sdio_dev_s *dev); + +/* Command/Status/Data Transfer */ + +static int lpc43_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t arg); +static int lpc43_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, + size_t nbytes); +static int lpc43_sendsetup(FAR struct sdio_dev_s *dev, + FAR const uint8_t *buffer, uint32_t nbytes); +static int lpc43_cancel(FAR struct sdio_dev_s *dev); + +static int lpc43_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd); +static int lpc43_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort); +static int lpc43_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t rlong[4]); +static int lpc43_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort); +static int lpc43_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rnotimpl); + +/* EVENT handler */ + +static void lpc43_waitenable(FAR struct sdio_dev_s *dev, + sdio_eventset_t eventset); +static sdio_eventset_t + lpc43_eventwait(FAR struct sdio_dev_s *dev, uint32_t timeout); +static void lpc43_callbackenable(FAR struct sdio_dev_s *dev, + sdio_eventset_t eventset); +static void lpc43_callback(struct lpc43_dev_s *priv); +static int lpc43_registercallback(FAR struct sdio_dev_s *dev, + worker_t callback, void *arg); + +#ifdef CONFIG_LPC43_SDMMC_DMA +/* DMA */ + +static int lpc43_dmarecvsetup(FAR struct sdio_dev_s *dev, + FAR uint8_t *buffer, size_t buflen); +static int lpc43_dmasendsetup(FAR struct sdio_dev_s *dev, + FAR const uint8_t *buffer, size_t buflen); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct lpc43_dev_s g_scard_dev = +{ + .dev = + { +#ifdef CONFIG_SDIO_MUXBUS + .lock = lpc43_lock, +#endif + .reset = lpc43_reset, + .capabilities = lpc43_capabilities, + .status = lpc43_status, + .widebus = lpc43_widebus, + .clock = lpc43_clock, + .attach = lpc43_attach, + .sendcmd = lpc43_sendcmd, + .recvsetup = lpc43_recvsetup, + .sendsetup = lpc43_sendsetup, + .cancel = lpc43_cancel, + .waitresponse = lpc43_waitresponse, + .recvR1 = lpc43_recvshortcrc, + .recvR2 = lpc43_recvlong, + .recvR3 = lpc43_recvshort, + .recvR4 = lpc43_recvnotimpl, + .recvR5 = lpc43_recvnotimpl, + .recvR6 = lpc43_recvshortcrc, + .recvR7 = lpc43_recvshort, + .waitenable = lpc43_waitenable, + .eventwait = lpc43_eventwait, + .callbackenable = lpc43_callbackenable, + .registercallback = lpc43_registercallback, +#ifdef CONFIG_LPC43_SDMMC_DMA + .dmarecvsetup = lpc43_dmarecvsetup, + .dmasendsetup = lpc43_dmasendsetup, +#endif + }, +}; + +#ifdef CONFIG_LPC43_SDMMC_DMA +static struct sdmmc_dma_s g_sdmmc_dmadd[1 + (0x10000 / MCI_DMADES1_MAXTR)]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc43_getreg + * + * Description: + * This function may to used to intercept an monitor all register accesses. + * Clearly this is nothing you would want to do unless you are debugging + * this driver. + * + * Input Parameters: + * addr - The register address to read + * + * Returned Value: + * The value read from the register + * + ****************************************************************************/ + +#ifdef CONFIG_LPC43_SDMMC_REGDEBUG +static uint32_t lpc43_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + + /* Read the value from the register */ + + uint32_t val = getreg32(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + mcinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + mcinfo("[repeats %d more times]\n", count-3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + mcinfo("%08x->%08x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: lpc43_putreg + * + * Description: + * This function may to used to intercept an monitor all register accesses. + * Clearly this is nothing you would want to do unless you are debugging + * this driver. + * + * Input Parameters: + * val - The value to write to the register + * addr - The register address to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_LPC43_SDMMC_REGDEBUG +static void lpc43_putreg(uint32_t val, uint32_t addr) +{ + /* Show the register value being written */ + + mcinfo("%08x<-%08x\n", addr, val); + + /* Write the value */ + + putreg32(val, addr); +} +#endif + +/**************************************************************************** + * Name: lpc43_takesem + * + * Description: + * Take the wait semaphore (handling false alarm wakeups due to the receipt + * of signals). + * + * Input Parameters: + * dev - Instance of the SD card device driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc43_takesem(struct lpc43_dev_s *priv) +{ + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(&priv->waitsem) != 0) + { + /* The only case that an error should occr here is if the wait was + * awakened by a signal. + */ + + DEBUGASSERT(errno == EINTR); + } +} + +/**************************************************************************** + * Name: lpc43_setclock + * + * Description: + * Define the new clock frequency + * + * Input Parameters: + * clkdiv - A new division value to generate the needed frequency. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void lpc43_setclock(uint32_t clkdiv) +{ + mcinfo("clkdiv=%08lx\n", (unsigned long)clkdiv); + + /* Disable the clock before setting frequency */ + + lpc43_sdcard_clock(false); + + /* Use the Divider0 */ + + lpc43_putreg(SDMMC_CLKSRC_CLKDIV0, LPC43_SDMMC_CLKSRC); + + /* Inform CIU */ + + lpc43_ciu_sendcmd(SDMMC_CMD_UPDCLOCK | SDMMC_CMD_WAITPREV, 0); + + /* Set Divider0 to desired value */ + + lpc43_putreg(clkdiv, LPC43_SDMMC_CLKDIV); + + /* Inform CIU */ + + lpc43_ciu_sendcmd(SDMMC_CMD_UPDCLOCK | SDMMC_CMD_WAITPREV, 0); + + /* Enable the clock */ + + lpc43_sdcard_clock(true); + + /* Inform CIU */ + + lpc43_ciu_sendcmd(SDMMC_CMD_UPDCLOCK | SDMMC_CMD_WAITPREV, 0); +} + +/**************************************************************************** + * Name: lpc43_sdcard_clock + * + * Description: Enable/Disable the SDCard clock + * + * Input Parameters: + * enable - False = clock disabled; True = clock enabled. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void lpc43_sdcard_clock(bool enable) +{ + if (enable) + { + lpc43_putreg(SDMMC_CLKENA_ENABLE, LPC43_SDMMC_CLKENA); + } + else + { + lpc43_putreg(0, LPC43_SDMMC_CLKENA); + } +} + +/**************************************************************************** + * Name: lpc43_ciu_sendcmd + * + * Description: + * Function to send command to Card interface unit (CIU) + * + * Input Parameters: + * cmd - The command to be executed + * arg - The argument to use with the command. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int lpc43_ciu_sendcmd(uint32_t cmd, uint32_t arg) +{ + volatile int32_t tmo = SDCARD_CMDTIMEOUT; + + mcinfo("cmd=%04lx arg=%04lx\n", (unsigned long)cmd, (unsigned long)arg); + + /* Set command arg reg */ + + lpc43_putreg(arg, LPC43_SDMMC_CMDARG); + lpc43_putreg(SDMMC_CMD_STARTCMD | cmd, LPC43_SDMMC_CMD); + + /* Poll until command is accepted by the CIU */ + + while (--tmo > 0 && (lpc43_getreg(LPC43_SDMMC_CMD) & SDMMC_CMD_STARTCMD) != 0) + { + } + + return (tmo < 1) ? 1 : 0; +} + +/**************************************************************************** + * Name: lpc43_enable_ints + * + * Description: + * Enable/disable SD card interrupts per functional settings. + * + * Input Parameters: + * priv - A reference to the SD card device state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc43_enable_ints(struct lpc43_dev_s *priv) +{ + uint32_t regval; + +#ifdef CONFIG_LPC43_SDMMC_DMA + mcinfo("waitmask=%04lx xfrmask=%04lx dmamask=%04lx RINTSTS=%08lx\n", + (unsigned long)priv->waitmask, (unsigned long)priv->xfrmask, + (unsigned long)priv->dmamask, + (unsigned long)lpc43_getreg(LPC43_SDMMC_RINTSTS)); + + /* Enable DMA-related interrupts */ + + lpc43_putreg(priv->dmamask, LPC43_SDMMC_IDINTEN); + +#else + mcinfo("waitmask=%04lx xfrmask=%04lx RINTSTS=%08lx\n", + (unsigned long)priv->waitmask, (unsigned long)priv->xfrmask, + (unsigned long)lpc43_getreg(LPC43_SDMMC_RINTSTS)); +#endif + + /* Enable SDMMC interrupts */ + + regval = priv->xfrmask | priv->waitmask | SDCARD_INT_CDET; + lpc43_putreg(regval, LPC43_SDMMC_INTMASK); +} + +/**************************************************************************** + * Name: lpc43_disable_allints + * + * Description: + * Disable all SD card interrupts. + * + * Input Parameters: + * priv - A reference to the SD card device state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc43_disable_allints(struct lpc43_dev_s *priv) +{ +#ifdef CONFIG_LPC43_SDMMC_DMA + /* Disable DMA-related interrupts */ + + lpc43_putreg(0, LPC43_SDMMC_IDINTEN); + priv->dmamask = 0; +#endif + + /* Disable all SDMMC interrupts (except card detect) */ + + lpc43_putreg(SDCARD_INT_CDET, LPC43_SDMMC_INTMASK); + priv->waitmask = 0; + priv->xfrmask = 0; +} + +/**************************************************************************** + * Name: lpc43_config_waitints + * + * Description: + * Enable/disable SD card interrupts needed to suport the wait function + * + * Input Parameters: + * priv - A reference to the SD card device state structure + * waitmask - The set of bits in the SD card INTMASK register to set + * waitevents - Waited for events + * wkupevent - Wake-up events + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc43_config_waitints(struct lpc43_dev_s *priv, uint32_t waitmask, + sdio_eventset_t waitevents, + sdio_eventset_t wkupevent) +{ + irqstate_t flags; + + mcinfo("waitevents=%04x wkupevent=%04x\n", + (unsigned)waitevents, (unsigned)wkupevent); + + /* Save all of the data and set the new interrupt mask in one, atomic + * operation. + */ + + flags = enter_critical_section(); + priv->waitevents = waitevents; + priv->wkupevent = wkupevent; + priv->waitmask = waitmask; + + lpc43_enable_ints(priv); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: lpc43_config_xfrints + * + * Description: + * Enable SD card interrupts needed to support the data transfer event + * + * Input Parameters: + * priv - A reference to the SD card device state structure + * xfrmask - The set of bits in the SD card MASK register to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc43_config_xfrints(struct lpc43_dev_s *priv, uint32_t xfrmask) +{ + irqstate_t flags; + flags = enter_critical_section(); + + priv->xfrmask = xfrmask; + lpc43_enable_ints(priv); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: lpc43_config_dmaints + * + * Description: + * Enable DMA transfer interrupts + * + * Input Parameters: + * priv - A reference to the SD card device state structure + * dmamask - The set of bits in the SD card MASK register to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_LPC43_SDMMC_DMA +static void lpc43_config_dmaints(struct lpc43_dev_s *priv, uint32_t xfrmask, + uint32_t dmamask) +{ + irqstate_t flags; + flags = enter_critical_section(); + + priv->xfrmask = xfrmask; + priv->dmamask = dmamask; + lpc43_enable_ints(priv); + + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: lpc43_eventtimeout + * + * Description: + * The watchdog timeout setup when the event wait start has expired without + * any other waited-for event occurring. + * + * Input Parameters: + * argc - The number of arguments (should be 1) + * arg - The argument (state structure reference cast to uint32_t) + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +static void lpc43_eventtimeout(int argc, uint32_t arg) +{ + struct lpc43_dev_s *priv = (struct lpc43_dev_s *)arg; + + mcinfo("argc=%d, arg=%08lx\n", argc, (unsigned long)arg); + + /* There is always race conditions with timer expirations. */ + + DEBUGASSERT((priv->waitevents & SDIOWAIT_TIMEOUT) != 0 || priv->wkupevent != 0); + + /* Is a data transfer complete event expected? */ + + if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0) + { + /* Yes.. wake up any waiting threads */ + + lpc43_endwait(priv, SDIOWAIT_TIMEOUT); + mcerr("ERROR: Timeout: remaining: %d\n", priv->remaining); + } +} + +/**************************************************************************** + * Name: lpc43_endwait + * + * Description: + * Wake up a waiting thread if the waited-for event has occurred. + * + * Input Parameters: + * priv - An instance of the SD card device interface + * wkupevent - The event that caused the wait to end + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +static void lpc43_endwait(struct lpc43_dev_s *priv, sdio_eventset_t wkupevent) +{ + mcinfo("wkupevent=%04x\n", (unsigned)wkupevent); + + /* Cancel the watchdog timeout */ + + (void)wd_cancel(priv->waitwdog); + + /* Disable event-related interrupts */ + + lpc43_config_waitints(priv, 0, 0, wkupevent); + + /* Wake up the waiting thread */ + + lpc43_givesem(priv); +} + +/**************************************************************************** + * Name: lpc43_endtransfer + * + * Description: + * Terminate a transfer with the provided status. This function is called + * only from the SD card interrupt handler when end-of-transfer conditions + * are detected. + * + * Input Parameters: + * priv - An instance of the SD card device interface + * wkupevent - The event that caused the transfer to end + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +static void lpc43_endtransfer(struct lpc43_dev_s *priv, sdio_eventset_t wkupevent) +{ + mcinfo("wkupevent=%04x\n", (unsigned)wkupevent); + + /* Disable all transfer related interrupts */ + + lpc43_config_xfrints(priv, 0); + + /* Clearing pending interrupt status on all transfer related interrupts */ + + lpc43_putreg(priv->waitmask, LPC43_SDMMC_RINTSTS); + + /* Mark the transfer finished */ + + priv->remaining = 0; + + /* Is a thread wait for these data transfer complete events? */ + + if ((priv->waitevents & wkupevent) != 0) + { + /* Yes.. wake up any waiting threads */ + + lpc43_endwait(priv, wkupevent); + } +} + +/**************************************************************************** + * Name: lpc43_sdmmc_interrupt + * + * Description: + * SD card interrupt handler + * + * Input Parameters: + * dev - An instance of the SD card device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int lpc43_sdmmc_interrupt(int irq, void *context, FAR void *arg) +{ + struct lpc43_dev_s *priv = &g_scard_dev; + uint32_t enabled; + uint32_t pending; + + /* Loop while there are pending interrupts. Check the SD card status + * register. Mask out all bits that don't correspond to enabled + * interrupts. (This depends on the fact that bits are ordered + * the same in both the STA and MASK register). If there are non-zero + * bits remaining, then we have work to do here. + */ + + while ((enabled = lpc43_getreg(LPC43_SDMMC_MINTSTS)) != 0) + { + /* Clear pending status */ + + lpc43_putreg(enabled, LPC43_SDMMC_RINTSTS); + +#ifdef CONFIG_MMCSD_HAVE_CARDDETECT + /* Handle in card detection events ************************************/ + + if ((enabled & SDMMC_INT_CDET) != 0) + { + sdio_statset_t cdstatus; + + /* Update card status */ + + cdstatus = priv->cdstatus; + if ((lpc43_getreg(LPC43_SDMMC_CDETECT) & SDMMC_CDETECT_NOTPRESENT) == 0) + { + priv->cdstatus |= SDIO_STATUS_PRESENT; + +#ifdef CONFIG_MMCSD_HAVE_WRITEPROTECT + if ((lpc43_getreg(LPC43_SDMMC_WRTPRT) & SDMMC_WRTPRT_PROTECTED) != 0) + { + priv->cdstatus |= SDIO_STATUS_WRPROTECTED; + } + else +#endif + { + priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED; + } + +#ifdef CONFIG_LPC43_SDMMC_PWRCTRL + /* Enable/ power to the SD card */ + + lpc43_putreg(SDMMC_PWREN, LPC43_SDMMC_PWREN); +#endif + + } + else + { + priv->cdstatus &= ~(SDIO_STATUS_PRESENT | SDIO_STATUS_WRPROTECTED); + +#ifdef CONFIG_LPC43_SDMMC_PWRCTRL + /* Disable power to the SD card */ + + lpc43_putreg(0, LPC43_SDMMC_PWREN); +#endif + } + + mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); + + /* Perform any requested callback if the status has changed */ + + if (cdstatus != priv->cdstatus) + { + lpc43_callback(priv); + } + } +#endif + + /* Handle idata transfer events ***************************************/ + + pending = enabled & priv->xfrmask; + if (pending != 0) + { + /* Handle data request events */ + + if ((pending & SDMMC_INT_TXDR) != 0) + { + uint32_t status; + + /* Transfer data to the TX FIFO */ + + mcinfo("Write FIFO\n"); + DEBUGASSERT(priv->wrdir); + + for (status = lpc43_getreg(LPC43_SDMMC_STATUS); + (status & SDMMC_STATUS_FIFOFULL) == 0 && + priv->remaining > 0; + status = lpc43_getreg(LPC43_SDMMC_STATUS)) + { + lpc43_putreg(*priv->buffer, LPC43_SDMMC_DATA); + priv->buffer++; + priv->remaining -= 4; + } + + /* If all of the data has been transferred to the FIFO, then + * disable further TX data requests and wait for the data end + * event. + */ + + if (priv->remaining <= 0) + { + uint32_t intmask = lpc43_getreg(LPC43_SDMMC_INTMASK); + intmask &= ~SDMMC_INT_TXDR; + lpc43_putreg(intmask, LPC43_SDMMC_INTMASK); + + priv->xfrmask &= ~SDMMC_INT_TXDR; + } + } + else if ((pending & SDMMC_INT_RXDR) != 0) + { + uint32_t status; + + /* Transfer data from the RX FIFO */ + + mcinfo("Read from FIFO\n"); + DEBUGASSERT(!priv->wrdir); + + for (status = lpc43_getreg(LPC43_SDMMC_STATUS); + (status & SDMMC_STATUS_FIFOEMPTY) == 0 && + priv->remaining > 0; + status = lpc43_getreg(LPC43_SDMMC_STATUS)) + { + *priv->buffer = lpc43_getreg(LPC43_SDMMC_DATA); + priv->buffer++; + priv->remaining -= 4; + } + + /* If all of the data has been transferred to the FIFO, then + * just force DTO event processing (the DTO interrupt is not + * actually even enabled in this use case). + */ + + if (priv->remaining <= 0) + { + /* Force the DTO event */ + + pending |= SDMMC_INT_DTO; + } + } + + /* Check for transfer errors */ + /* Handle data block send/receive CRC failure */ + + if ((pending & SDMMC_INT_DCRC) != 0) + { + /* Terminate the transfer with an error */ + + mcerr("ERROR: Data CRC failure, pending=%08x remaining: %d\n", + pending, priv->remaining); + lpc43_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } + + /* Handle data timeout error */ + + else if ((pending & SDMMC_INT_DRTO) != 0) + { + /* Terminate the transfer with an error */ + + mcerr("ERROR: Data timeout, pending=%08x remaining: %d\n", + pending, priv->remaining); + lpc43_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT); + } + + /* Handle RX FIFO overrun error */ + + else if ((pending & SDMMC_INT_FRUN) != 0) + { + /* Terminate the transfer with an error */ + + mcerr("ERROR: RX FIFO overrun, pending=%08x remaining: %d\n", + pending, priv->remaining); + lpc43_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } + + /* Handle TX FIFO underrun error */ + + else if ((pending & SDMMC_INT_FRUN) != 0) + { + /* Terminate the transfer with an error */ + + mcerr("ERROR: TX FIFO underrun, pending=%08x remaining: %d\n", + pending, priv->remaining); + lpc43_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } + + /* Handle start bit error */ + + else if ((pending & SDMMC_INT_SBE) != 0) + { + /* Terminate the transfer with an error */ + + mcerr("ERROR: Start bit, pending=%08x remaining: %d\n", + pending, priv->remaining); + lpc43_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } + + /* Handle data end events. Note that RXDR may accompany DTO, DTO + * will be set on received while there is still data in the FIFO. + * So for the case of receiving, we don't actually even enable the + * DTO interrupt. + */ + + else if ((pending & SDMMC_INT_DTO) != 0) + { + /* Finish the transfer */ + + lpc43_endtransfer(priv, SDIOWAIT_TRANSFERDONE); + } + } + + /* Handle wait events *************************************************/ + + pending = enabled & priv->waitmask; + if (pending != 0) + { + /* Is this a response error event? */ + + if ((pending & SDCARD_INT_RESPERR) != 0) + { + /* If response errors are enabled, then we must certainly be + * waiting for a response. + */ + + DEBUGASSERT((priv->waitevents & SDIOWAIT_RESPONSEDONE) != 0); + + /* Wake the thread up */ + + mcerr("ERROR: Response error, pending=%08x\n", pending); + lpc43_endwait(priv, SDIOWAIT_RESPONSEDONE | SDIOWAIT_ERROR); + } + + /* Is this a command (plus response) completion event? */ + + else if ((pending & SDMMC_INT_CDONE) != 0) + { + /* Yes.. Is their a thread waiting for response done? */ + + if ((priv->waitevents & SDIOWAIT_RESPONSEDONE) != 0) + { + /* Yes.. wake the thread up */ + + lpc43_endwait(priv, SDIOWAIT_RESPONSEDONE); + } + + /* NO.. Is their a thread waiting for command done? */ + + else if ((priv->waitevents & SDIOWAIT_CMDDONE) != 0) + { + /* Yes.. wake the thread up */ + + lpc43_endwait(priv, SDIOWAIT_CMDDONE); + } + } + } + } + +#ifdef CONFIG_LPC43_SDMMC_DMA + /* DMA error events *******************************************************/ + + pending = lpc43_getreg(LPC43_SDMMC_IDSTS); + if ((pending & priv->dmamask) != 0) + { + mcerr("ERROR: IDTS=%08lx\n", (unsigned long)pending); + + /* Clear the pending interrupts */ + + lpc43_putreg(pending, LPC43_SDMMC_IDSTS); + + /* Abort the transfer */ + + lpc43_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: lpc43_lock + * + * Description: + * Locks the bus. Function calls low-level multiplexed bus routines to + * resolve bus requests and acknowledgment issues. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * lock - TRUE to lock, FALSE to unlock. + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_MUXBUS +static int lpc43_lock(FAR struct sdio_dev_s *dev, bool lock) +{ + /* Single SD card instance so there is only one possibility. The multiplex + * bus is part of board support package. + */ + + lpc43_muxbus_sdio_lock(lock); + return OK; +} +#endif + +/**************************************************************************** + * Name: lpc43_reset + * + * Description: + * Reset the SD card controller. Undo all setup and initialization. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc43_reset(FAR struct sdio_dev_s *dev) +{ + FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev; + irqstate_t flags; + uint32_t regval; + + mcinfo("Resetting...\n"); + + flags = enter_critical_section(); + + /* Reset DMA controller internal registers. */ + + lpc43_putreg(SDMMC_BMOD_SWR, LPC43_SDMMC_BMOD); + + /* Reset all blocks */ + + lpc43_putreg(SDMMC_CTRL_CNTLRRESET | SDMMC_CTRL_FIFORESET | + SDMMC_CTRL_DMARESET, LPC43_SDMMC_CTRL); + + while ((lpc43_getreg(LPC43_SDMMC_CTRL) & + (SDMMC_CTRL_CNTLRRESET | SDMMC_CTRL_FIFORESET | SDMMC_CTRL_DMARESET)) != 0) + { + } + + /* Reset data */ + + priv->waitevents = 0; /* Set of events to be waited for */ + priv->waitmask = 0; /* Interrupt enables for event waiting */ + priv->wkupevent = 0; /* The event that caused the wakeup */ + + wd_cancel(priv->waitwdog); /* Cancel any timeouts */ + + /* Interrupt mode data transfer support */ + + priv->buffer = 0; /* Address of current R/W buffer */ + priv->remaining = 0; /* Number of bytes remaining in the transfer */ + priv->xfrmask = 0; /* Interrupt enables for data transfer */ +#ifdef CONFIG_LPC43_SDMMC_DMA + priv->dmamask = 0; /* Interrupt enables for DMA transfer */ +#endif + + /* DMA data transfer support */ + + priv->widebus = true; /* Required for DMA support */ + priv->cdstatus = 0; /* Card status is unknown */ + +#ifdef CONFIG_LPC43_SDMMC_DMA + priv->dmamode = false; /* true: DMA mode transfer */ +#endif + + /* Select 1-bit wide bus */ + + lpc43_putreg(SDMMC_CTYPE_WIDTH1, LPC43_SDMMC_CTYPE); + + /* Enable interrupts */ + + regval = lpc43_getreg(LPC43_SDMMC_CTRL); + regval |= SDMMC_CTRL_INTENABLE; + lpc43_putreg(regval, LPC43_SDMMC_CTRL); + + /* Disable Interrupts except for card detection. */ + + lpc43_putreg(SDCARD_INT_CDET, LPC43_SDMMC_INTMASK); + +#ifdef CONFIG_MMCSD_HAVE_CARDDETECT + /* Set the card debounce time. Number of host clocks (SD_CLK) used by + * debounce filter logic for card detect. typical debounce time is 5-25 + * ms. + */ + + lpc43_putreg(DEBOUNCE_TICKS, LPC43_SDMMC_DEBNCE); +#endif + + /* Clear to Interrupts */ + + lpc43_putreg(0xffffffff, LPC43_SDMMC_RINTSTS); + + /* Define MAX Timeout */ + + lpc43_putreg(SDCARD_LONGTIMEOUT, LPC43_SDMMC_TMOUT); + + /* Disable clock to CIU (needs latch) */ + + lpc43_putreg(0, LPC43_SDMMC_CLKENA); + leave_critical_section(flags); + +#if defined(CONFIG_LPC43_SDMMC_PWRCTRL) && !defined(CONFIG_MMCSD_HAVE_CARDDETECT) + /* Enable power to the SD card */ + + lpc43_putreg(SDMMC_PWREN, LPC43_SDMMC_PWREN); +#endif +} + +/**************************************************************************** + * Name: lpc43_capabilities + * + * Description: + * Get capabilities (and limitations) of the SDIO driver (optional) + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Returns a bitset of status values (see SDIO_CAPS_* defines) + * + ****************************************************************************/ + +static sdio_capset_t lpc43_capabilities(FAR struct sdio_dev_s *dev) +{ + sdio_capset_t caps = 0; + + caps |= SDIO_CAPS_DMABEFOREWRITE; + +#ifdef CONFIG_SDIO_WIDTH_D1_ONLY + caps |= SDIO_CAPS_1BIT_ONLY; +#endif +#ifdef CONFIG_LPC43_SDMMC_DMA + caps |= SDIO_CAPS_DMASUPPORTED; +#endif + + return caps; +} + +/**************************************************************************** + * Name: lpc43_status + * + * Description: + * Get SD card status. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Returns a bitset of status values (see lpc43_status_* defines) + * + ****************************************************************************/ + +static sdio_statset_t lpc43_status(FAR struct sdio_dev_s *dev) +{ + struct lpc43_dev_s *priv = (struct lpc43_dev_s *)dev; + + mcinfo("cdstatus=%02x\n", priv->cdstatus); + + return priv->cdstatus; +} + +/**************************************************************************** + * Name: lpc43_widebus + * + * Description: + * Called after change in Bus width has been selected (via ACMD6). Most + * controllers will need to perform some special operations to work + * correctly in the new bus mode. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * wide - true: wide bus (4-bit) bus mode enabled + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc43_widebus(FAR struct sdio_dev_s *dev, bool wide) +{ + mcinfo("wide=%d\n", wide); +} + +/**************************************************************************** + * Name: lpc43_clock + * + * Description: + * Enable/disable SD card clocking + * + * Input Parameters: + * dev - An instance of the SD card device interface + * rate - Specifies the clocking to use (see enum sdio_clock_e) + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc43_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) +{ + struct lpc43_dev_s *priv = (struct lpc43_dev_s *)dev; + uint8_t clkdiv; + uint8_t ctype; + bool enabled = false; + bool widebus = false; + + switch (rate) + { + /* Disable clocking (with default ID mode divisor) */ + + default: + case CLOCK_SDIO_DISABLED: + clkdiv = SDMMC_CLKDIV0(BOARD_CLKDIV_INIT); + ctype = SDCARD_BUS_D1; + enabled = false; + widebus = false; + return; + break; + + /* Enable in initial ID mode clocking (<400KHz) */ + + case CLOCK_IDMODE: + clkdiv = SDMMC_CLKDIV0(BOARD_CLKDIV_INIT); + ctype = SDCARD_BUS_D1; + enabled = true; + widebus = false; + break; + + /* Enable in MMC normal operation clocking */ + + case CLOCK_MMC_TRANSFER: + clkdiv = SDMMC_CLKDIV0(BOARD_CLKDIV_MMCXFR); + ctype = SDCARD_BUS_D1; + enabled = true; + widebus = false; + break; + + /* SD normal operation clocking (wide 4-bit mode) */ + + case CLOCK_SD_TRANSFER_4BIT: +#ifndef CONFIG_SDIO_WIDTH_D1_ONLY + clkdiv = SDMMC_CLKDIV0(BOARD_CLKDIV_SDWIDEXFR); + ctype = SDCARD_BUS_D4; + enabled = true; + widebus = true; + break; +#endif + + /* SD normal operation clocking (narrow 1-bit mode) */ + + case CLOCK_SD_TRANSFER_1BIT: + clkdiv = SDMMC_CLKDIV0(BOARD_CLKDIV_SDXFR); + ctype = SDCARD_BUS_D1; + enabled = true; + widebus = false; + break; + } + + /* Setup the card bus width */ + + mcinfo("widebus=%d\n", widebus); + + priv->widebus = widebus; + lpc43_putreg(ctype, LPC43_SDMMC_CTYPE); + + /* Set the new clock frequency division */ + + lpc43_setclock(clkdiv); + + /* Enable the new clock */ + + lpc43_sdcard_clock(enabled); +} + +/**************************************************************************** + * Name: lpc43_attach + * + * Description: + * Attach and prepare interrupts + * + * Input Parameters: + * dev - An instance of the SD card device interface + * + * Returned Value: + * OK on success; A negated errno on failure. + * + ****************************************************************************/ + +static int lpc43_attach(FAR struct sdio_dev_s *dev) +{ + int ret; + uint32_t regval; + + mcinfo("Attaching..\n"); + + /* Attach the SD card interrupt handler */ + + ret = irq_attach(LPC43M4_IRQ_SDIO, lpc43_sdmmc_interrupt, NULL); + if (ret == OK) + { + /* Disable all interrupts at the SD card controller and clear static + * interrupt flags + */ + + lpc43_putreg(0, LPC43_SDMMC_INTMASK); + lpc43_putreg(SDMMC_INT_ALL, LPC43_SDMMC_RINTSTS); + + /* Enable Interrupts to happen when the INTMASK is activated */ + + regval = lpc43_getreg(LPC43_SDMMC_CTRL); + regval |= SDMMC_CTRL_INTENABLE; + lpc43_putreg(regval, LPC43_SDMMC_CTRL); + + /* Enable card detection interrupts */ + + lpc43_putreg(SDCARD_INT_CDET, LPC43_SDMMC_INTMASK); + + /* Enable SD card interrupts at the NVIC. They can now be enabled at + * the SD card controller as needed. + */ + + up_enable_irq(LPC43M4_IRQ_SDIO); + } + + return ret; +} + +/**************************************************************************** + * Name: lpc43_sendcmd + * + * Description: + * Send the SD card command + * + * Input Parameters: + * dev - An instance of the SD card device interface + * cmd - The command to send (32-bits, encoded) + * arg - 32-bit argument required with some commands + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int lpc43_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t arg) +{ + uint32_t regval = 0; + uint32_t cmdidx; + + mcinfo("cmd=%04x arg=%04x\n", cmd, arg); + + /* The CMD0 needs the SENDINIT CMD */ + + if (cmd == 0) + { + regval |= SDMMC_CMD_SENDINIT; + } + + /* Is this a Read/Write Transfer Command ? */ + + if ((cmd & MMCSD_WRDATAXFR) == MMCSD_WRDATAXFR) + { + regval |= SDMMC_CMD_DATAXFREXPTD | SDMMC_CMD_WRITE | SDMMC_CMD_WAITPREV; + } + else if ((cmd & MMCSD_RDDATAXFR) == MMCSD_RDDATAXFR) + { + regval |= SDMMC_CMD_DATAXFREXPTD | SDMMC_CMD_WAITPREV; + } + + /* Set WAITRESP bits */ + + switch (cmd & MMCSD_RESPONSE_MASK) + { + case MMCSD_NO_RESPONSE: + regval |= SDMMC_CMD_NORESPONSE; + break; + + case MMCSD_R1B_RESPONSE: + regval |= SDMMC_CMD_WAITPREV; + case MMCSD_R1_RESPONSE: + case MMCSD_R3_RESPONSE: + case MMCSD_R4_RESPONSE: + case MMCSD_R5_RESPONSE: + case MMCSD_R6_RESPONSE: + case MMCSD_R7_RESPONSE: + regval |= SDMMC_CMD_SHORTRESPONSE; + break; + + case MMCSD_R2_RESPONSE: + regval |= SDMMC_CMD_LONGRESPONSE; + break; + } + + /* Set the command index */ + + cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT; + regval |= cmdidx; + + mcinfo("cmd: %04x arg: %04x regval: %08x\n", cmd, arg, regval); + + /* Write the SD card CMD */ + + lpc43_putreg(SDCARD_RESPDONE_CLEAR | SDCARD_CMDDONE_CLEAR, + LPC43_SDMMC_RINTSTS); + lpc43_ciu_sendcmd(regval, arg); + + return OK; +} + +/**************************************************************************** + * Name: lpc43_recvsetup + * + * Description: + * Setup hardware in preparation for data transfer from the card in non-DMA + * (interrupt driven mode). This method will do whatever controller setup + * is necessary. This would be called for SD memory just BEFORE sending + * CMD13 (SEND_STATUS), CMD17 (READ_SINGLE_BLOCK), CMD18 + * (READ_MULTIPLE_BLOCKS), ACMD51 (SEND_SCR), etc. Normally, SDCARD_WAITEVENT + * will be called to receive the indication that the transfer is complete. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * buffer - Address of the buffer in which to receive the data + * nbytes - The number of bytes in the transfer + * + * Returned Value: + * Number of bytes sent on success; a negated errno on failure + * + ****************************************************************************/ + +static int lpc43_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, + size_t nbytes) +{ + struct lpc43_dev_s *priv = (struct lpc43_dev_s *)dev; + uint32_t blocksize; + uint32_t bytecnt; +#ifdef CONFIG_LPC43_SDMMC_DMA + uint32_t regval; +#endif + + mcinfo("nbytes=%ld\n", (long) nbytes); + + DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0); + DEBUGASSERT(((uint32_t)buffer & 3) == 0); + + /* Save the destination buffer information for use by the interrupt handler */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = nbytes; + priv->wrdir = false; +#ifdef CONFIG_LPC43_SDMMC_DMA + priv->dmamode = false; +#endif + + /* Then set up the SD card data path */ + + if (nbytes < 64) + { + blocksize = nbytes; + bytecnt = nbytes; + } + else + { + blocksize = 64; + bytecnt = nbytes; + DEBUGASSERT((nbytes & 0x3f) == 0); + } + + lpc43_putreg(blocksize, LPC43_SDMMC_BLKSIZ); + lpc43_putreg(bytecnt, LPC43_SDMMC_BYTCNT); + + /* Configure the FIFO so that we will receive the RXDR interrupt whenever + * there are more than 1 words (at least 8 bytes) in the RX FIFO. + */ + + lpc43_putreg(SDMMC_FIFOTH_RXWMARK(1), LPC43_SDMMC_FIFOTH); + +#ifdef CONFIG_LPC43_SDMMC_DMA + /* Make sure that internal DMA is disabled */ + + lpc43_putreg(0, LPC43_SDMMC_BMOD); + + regval = lpc43_getreg(LPC43_SDMMC_CTRL); + regval &= ~SDMMC_CTRL_INTDMA; + lpc43_putreg(regval, LPC43_SDMMC_CTRL); +#endif + + /* Configure the transfer interrupts */ + + lpc43_config_xfrints(priv, SDCARD_RECV_MASK); + return OK; +} + +/**************************************************************************** + * Name: lpc43_sendsetup + * + * Description: + * Setup hardware in preparation for data transfer from the card. This + * method will do whatever controller setup is necessary. This would be + * called for SD memory just AFTER sending CMD24 (WRITE_BLOCK), CMD25 + * (WRITE_MULTIPLE_BLOCK), ... and before SDCARD_SENDDATA is called. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * buffer - Address of the buffer containing the data to send + * nbytes - The number of bytes in the transfer + * + * Returned Value: + * Number of bytes sent on success; a negated errno on failure + * + ****************************************************************************/ + +static int lpc43_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, + size_t nbytes) +{ + struct lpc43_dev_s *priv = (struct lpc43_dev_s *)dev; +#ifdef CONFIG_LPC43_SDMMC_DMA + uint32_t regval; +#endif + + mcinfo("nbytes=%ld\n", (long)nbytes); + + DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0); + DEBUGASSERT(((uint32_t)buffer & 3) == 0); + + /* Save the source buffer information for use by the interrupt handler */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = nbytes; + priv->wrdir = true; +#ifdef CONFIG_LPC43_SDMMC_DMA + priv->dmamode = false; +#endif + + /* Configure the FIFO so that we will receive the TXDR interrupt whenever + * there the TX FIFO is at least half empty. + */ + + lpc43_putreg(SDMMC_FIFOTH_TXWMARK(LPC43_TXFIFO_DEPTH / 2), + LPC43_SDMMC_FIFOTH); + +#ifdef CONFIG_LPC43_SDMMC_DMA + /* Make sure that internal DMA is disabled */ + + lpc43_putreg(0, LPC43_SDMMC_BMOD); + + regval = lpc43_getreg(LPC43_SDMMC_CTRL); + regval &= ~SDMMC_CTRL_INTDMA; + lpc43_putreg(regval, LPC43_SDMMC_CTRL); +#endif + + /* Configure the transfer interrupts */ + + lpc43_config_xfrints(priv, SDCARD_SEND_MASK); + return OK; +} + +/**************************************************************************** + * Name: lpc43_cancel + * + * Description: + * Cancel the data transfer setup of SDCARD_RECVSETUP, SDCARD_SENDSETUP, + * SDCARD_DMARECVSETUP or SDCARD_DMASENDSETUP. This must be called to cancel + * the data transfer setup if, for some reason, you cannot perform the + * transfer. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * + * Returned Value: + * OK is success; a negated errno on failure + * + ****************************************************************************/ + +static int lpc43_cancel(FAR struct sdio_dev_s *dev) +{ + struct lpc43_dev_s *priv = (struct lpc43_dev_s *)dev; + + mcinfo("Cancelling..\n"); + + /* Disable all transfer- and event- related interrupts */ + + lpc43_disable_allints(priv); + + /* Clearing pending interrupt status on all transfer- and event- related + * interrupts + */ + + lpc43_putreg(SDCARD_WAITALL_CLEAR, LPC43_SDMMC_RINTSTS); + + /* Cancel any watchdog timeout */ + + (void)wd_cancel(priv->waitwdog); + + /* Mark no transfer in progress */ + + priv->remaining = 0; + return OK; +} + +/**************************************************************************** + * Name: lpc43_waitresponse + * + * Description: + * Poll-wait for the response to the last command to be ready. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * cmd - The command that was sent. See 32-bit command definitions above. + * + * Returned Value: + * OK is success; a negated errno on failure + * + ****************************************************************************/ + +static int lpc43_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) +{ + volatile int32_t timeout; + uint32_t events; + + mcinfo("cmd=%04x\n", cmd); + + switch (cmd & MMCSD_RESPONSE_MASK) + { + case MMCSD_NO_RESPONSE: + events = SDCARD_CMDDONE_STA; + timeout = SDCARD_CMDTIMEOUT; + break; + + case MMCSD_R1_RESPONSE: + case MMCSD_R1B_RESPONSE: + case MMCSD_R2_RESPONSE: + case MMCSD_R6_RESPONSE: + events = (SDCARD_CMDDONE_STA | SDCARD_RESPDONE_STA); + timeout = SDCARD_LONGTIMEOUT; + break; + + case MMCSD_R4_RESPONSE: + case MMCSD_R5_RESPONSE: + return -ENOSYS; + + case MMCSD_R3_RESPONSE: + case MMCSD_R7_RESPONSE: + events = (SDCARD_CMDDONE_STA | SDCARD_RESPDONE_STA); + timeout = SDCARD_CMDTIMEOUT; + break; + + default: + return -EINVAL; + } + + mcinfo("cmd: %04x events: %04x STATUS: %08x RINTSTS: %08x\n", + cmd, events, lpc43_getreg(LPC43_SDMMC_STATUS), + lpc43_getreg(LPC43_SDMMC_RINTSTS)); + + /* Then wait for the response (or timeout or error) */ + + while ((lpc43_getreg(LPC43_SDMMC_RINTSTS) & events) != events) + { + if (--timeout <= 0) + { + mcerr("ERROR: Timeout cmd: %04x events: %04x STA: %08x RINTSTS: %08x\n", + cmd, events, lpc43_getreg(LPC43_SDMMC_STATUS), + lpc43_getreg(LPC43_SDMMC_RINTSTS)); + return -ETIMEDOUT; + } + else if ((lpc43_getreg(LPC43_SDMMC_RINTSTS) & SDCARD_INT_RESPERR) != 0) + { + mcerr("ERROR: SDMMC failure cmd: %04x events: %04x STA: %08x RINTSTS: %08x\n", + cmd, events, lpc43_getreg(LPC43_SDMMC_STATUS), + lpc43_getreg(LPC43_SDMMC_RINTSTS)); + return -EIO; + } + } + + lpc43_putreg(SDCARD_CMDDONE_CLEAR, LPC43_SDMMC_RINTSTS); + return OK; +} + +/**************************************************************************** + * Name: lpc43_recvRx + * + * Description: + * Receive response to SD card command. Only the critical payload is + * returned -- that is 32 bits for 48 bit status and 128 bits for 136 bit + * status. The driver implementation should verify the correctness of + * the remaining, non-returned bits (CRCs, CMD index, etc.). + * + * Input Parameters: + * dev - An instance of the SD card device interface + * Rx - Buffer in which to receive the response + * + * Returned Value: + * Number of bytes sent on success; a negated errno on failure. Here a + * failure means only a faiure to obtain the requested reponse (due to + * transport problem -- timeout, CRC, etc.). The implementation only + * assures that the response is returned intacta and does not check errors + * within the response itself. + * + ****************************************************************************/ + +static int lpc43_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort) +{ + uint32_t regval; + + int ret = OK; + + mcinfo("cmd=%04x\n", cmd); + + /* R1 Command response (48-bit) + * 47 0 Start bit + * 46 0 Transmission bit (0=from card) + * 45:40 bit5 - bit0 Command index (0-63) + * 39:8 bit31 - bit0 32-bit card status + * 7:1 bit6 - bit0 CRC7 + * 0 1 End bit + * + * R1b Identical to R1 with the additional busy signaling via the data + * line. + * + * R6 Published RCA Response (48-bit, SD card only) + * 47 0 Start bit + * 46 0 Transmission bit (0=from card) + * 45:40 bit5 - bit0 Command index (0-63) + * 39:8 bit31 - bit0 32-bit Argument Field, consisting of: + * [31:16] New published RCA of card + * [15:0] Card status bits {23,22,19,12:0} + * 7:1 bit6 - bit0 CRC7 + * 0 1 End bit + */ + + +#ifdef CONFIG_DEBUG_FEATURES + if (!rshort) + { + mcerr("ERROR: rshort=NULL\n"); + ret = -EINVAL; + } + + /* Check that this is the correct response to this command */ + + else if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE) + { + mcerr("ERROR: Wrong response CMD=%04x\n", cmd); + ret = -EINVAL; + } + else +#endif + { + /* Check if a timeout or CRC error occurred */ + + regval = lpc43_getreg(LPC43_SDMMC_RINTSTS); + if ((regval & SDMMC_INT_RTO) != 0) + { + mcerr("ERROR: Command timeout: %08x\n", regval); + ret = -ETIMEDOUT; + } + else if ((regval & SDMMC_INT_RCRC) != 0) + { + mcerr("ERROR: CRC failure: %08x\n", regval); + ret = -EIO; + } + } + + /* Clear all pending message completion events and return the R1/R6 + * response. + */ + + lpc43_putreg(SDCARD_RESPDONE_CLEAR | SDCARD_CMDDONE_CLEAR, + LPC43_SDMMC_RINTSTS); + *rshort = lpc43_getreg(LPC43_SDMMC_RESP0); + mcinfo("CRC=%04x\n", *rshort); + + return ret; +} + +static int lpc43_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t rlong[4]) +{ + uint32_t regval; + int ret = OK; + + mcinfo("cmd=%04x\n", cmd); + + /* R2 CID, CSD register (136-bit) + * 135 0 Start bit + * 134 0 Transmission bit (0=from card) + * 133:128 bit5 - bit0 Reserved + * 127:1 bit127 - bit1 127-bit CID or CSD register + * (including internal CRC) + * 0 1 End bit + */ + +#ifdef CONFIG_DEBUG_FEATURES + /* Check that R1 is the correct response to this command */ + + if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE) + { + mcerr("ERROR: Wrong response CMD=%04x\n", cmd); + ret = -EINVAL; + } + else +#endif + { + /* Check if a timeout or CRC error occurred */ + + regval = lpc43_getreg(LPC43_SDMMC_RINTSTS); + if (regval & SDMMC_INT_RTO) + { + mcerr("ERROR: Timeout STA: %08x\n", regval); + ret = -ETIMEDOUT; + } + else if (regval & SDMMC_INT_RCRC) + { + mcerr("ERROR: CRC fail STA: %08x\n", regval); + ret = -EIO; + } + } + + /* Return the long response */ + + lpc43_putreg(SDCARD_RESPDONE_CLEAR | SDCARD_CMDDONE_CLEAR, + LPC43_SDMMC_RINTSTS); + if (rlong) + { + rlong[0] = lpc43_getreg(LPC43_SDMMC_RESP3); + rlong[1] = lpc43_getreg(LPC43_SDMMC_RESP2); + rlong[2] = lpc43_getreg(LPC43_SDMMC_RESP1); + rlong[3] = lpc43_getreg(LPC43_SDMMC_RESP0); + } + + return ret; +} + +static int lpc43_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort) +{ + uint32_t regval; + int ret = OK; + + mcinfo("cmd=%04x\n", cmd); + + /* R3 OCR (48-bit) + * 47 0 Start bit + * 46 0 Transmission bit (0=from card) + * 45:40 bit5 - bit0 Reserved + * 39:8 bit31 - bit0 32-bit OCR register + * 7:1 bit6 - bit0 Reserved + * 0 1 End bit + */ + + /* Check that this is the correct response to this command */ + +#ifdef CONFIG_DEBUG_FEATURES + if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE) + { + mcerr("ERROR: Wrong response CMD=%04x\n", cmd); + ret = -EINVAL; + } + else +#endif + { + /* Check if a timeout occurred (Apparently a CRC error can terminate + * a good response) + */ + + regval = lpc43_getreg(LPC43_SDMMC_RINTSTS); + if (regval & SDMMC_INT_RTO) + { + mcerr("ERROR: Timeout STA: %08x\n", regval); + ret = -ETIMEDOUT; + } + } + + lpc43_putreg(SDCARD_RESPDONE_CLEAR | SDCARD_CMDDONE_CLEAR, + LPC43_SDMMC_RINTSTS); + if (rshort) + { + *rshort = lpc43_getreg(LPC43_SDMMC_RESP0); + } + + return ret; +} + +/* MMC responses not supported */ + +static int lpc43_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rnotimpl) +{ + mcinfo("cmd=%04x\n", cmd); + + lpc43_putreg(SDCARD_RESPDONE_CLEAR | SDCARD_CMDDONE_CLEAR, + LPC43_SDMMC_RINTSTS); + return -ENOSYS; +} + +/**************************************************************************** + * Name: lpc43_waitenable + * + * Description: + * Enable/disable of a set of SD card wait events. This is part of the + * the SDCARD_WAITEVENT sequence. The set of to-be-waited-for events is + * configured before calling lpc43_eventwait. This is done in this way + * to help the driver to eliminate race conditions between the command + * setup and the subsequent events. + * + * The enabled events persist until either (1) SDCARD_WAITENABLE is called + * again specifying a different set of wait events, or (2) SDCARD_EVENTWAIT + * returns. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * eventset - A bitset of events to enable or disable (see SDIOWAIT_* + * definitions). 0=disable; 1=enable. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc43_waitenable(FAR struct sdio_dev_s *dev, + sdio_eventset_t eventset) +{ + struct lpc43_dev_s *priv = (struct lpc43_dev_s *)dev; + uint32_t waitmask; + + mcinfo("eventset=%04x\n", (unsigned int)eventset); + DEBUGASSERT(priv != NULL); + + /* Disable event-related interrupts */ + + lpc43_config_waitints(priv, 0, 0, 0); + + /* Select the interrupt mask that will give us the appropriate wakeup + * interrupts. + */ + + waitmask = 0; + if ((eventset & SDIOWAIT_CMDDONE) != 0) + { + waitmask |= SDCARD_CMDDONE_MASK; + } + + if ((eventset & SDIOWAIT_RESPONSEDONE) != 0) + { + waitmask |= SDCARD_RESPDONE_MASK; + } + + if ((eventset & SDIOWAIT_TRANSFERDONE) != 0) + { + waitmask |= SDCARD_XFRDONE_MASK; + } + + /* Enable event-related interrupts */ + + lpc43_config_waitints(priv, waitmask, eventset, 0); +} + +/**************************************************************************** + * Name: lpc43_eventwait + * + * Description: + * Wait for one of the enabled events to occur (or a timeout). Note that + * all events enabled by SDCARD_WAITEVENTS are disabled when lpc43_eventwait + * returns. SDCARD_WAITEVENTS must be called again before lpc43_eventwait + * can be used again. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * timeout - Maximum time in milliseconds to wait. Zero means immediate + * timeout with no wait. The timeout value is ignored if + * SDIOWAIT_TIMEOUT is not included in the waited-for eventset. + * + * Returned Value: + * Event set containing the event(s) that ended the wait. Should always + * be non-zero. All events are disabled after the wait concludes. + * + ****************************************************************************/ + +static sdio_eventset_t lpc43_eventwait(FAR struct sdio_dev_s *dev, + uint32_t timeout) +{ + struct lpc43_dev_s *priv = (struct lpc43_dev_s *)dev; + sdio_eventset_t wkupevent = 0; + irqstate_t flags; + int ret; + + mcinfo("timeout=%lu\n", (unsigned long)timeout); + + /* There is a race condition here... the event may have completed before + * we get here. In this case waitevents will be zero, but wkupevents will + * be non-zero (and, hopefully, the semaphore count will also be non-zero. + */ + + flags = enter_critical_section(); + DEBUGASSERT(priv->waitevents != 0 || priv->wkupevent != 0); + + /* Check if the timeout event is specified in the event set */ + + if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0) + { + int delay; + + /* Yes.. Handle a cornercase: The user request a timeout event but + * with timeout == 0? + */ + + if (!timeout) + { + /* Then just tell the caller that we already timed out */ + + wkupevent = SDIOWAIT_TIMEOUT; + goto errout; + } + + /* Start the watchdog timer */ + + delay = MSEC2TICK(timeout); + ret = wd_start(priv->waitwdog, delay, (wdentry_t)lpc43_eventtimeout, + 1, (uint32_t)priv); + if (ret != OK) + { + mcerr("ERROR: wd_start failed: %d\n", ret); + } + } + + /* Loop until the event (or the timeout occurs). Race conditions are avoided + * by calling lpc43_waitenable prior to triggering the logic that will cause + * the wait to terminate. Under certain race conditions, the waited-for + * may have already occurred before this function was called! + */ + + for (; ; ) + { + /* Wait for an event in event set to occur. If this the event has already + * occurred, then the semaphore will already have been incremented and + * there will be no wait. + */ + + lpc43_takesem(priv); + wkupevent = priv->wkupevent; + + /* Check if the event has occurred. When the event has occurred, then + * evenset will be set to 0 and wkupevent will be set to a nonzero value. + */ + + if (wkupevent != 0) + { + /* Yes... break out of the loop with wkupevent non-zero */ + + break; + } + } + + /* Disable all transfer- and event- related interrupts */ + + lpc43_disable_allints(priv); + +errout: + leave_critical_section(flags); + mcinfo("wkupevent=%04x\n", wkupevent); + return wkupevent; +} + +/**************************************************************************** + * Name: lpc43_callbackenable + * + * Description: + * Enable/disable of a set of SD card callback events. This is part of the + * the SD card callback sequence. The set of events is configured to enabled + * callbacks to the function provided in lpc43_registercallback. + * + * Events are automatically disabled once the callback is performed and no + * further callback events will occur until they are again enabled by + * calling this methos. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * eventset - A bitset of events to enable or disable (see SDIOMEDIA_* + * definitions). 0=disable; 1=enable. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc43_callbackenable(FAR struct sdio_dev_s *dev, + sdio_eventset_t eventset) +{ + struct lpc43_dev_s *priv = (struct lpc43_dev_s *)dev; + + mcinfo("eventset: %02x\n", eventset); + DEBUGASSERT(priv != NULL); + + priv->cbevents = eventset; + lpc43_callback(priv); +} + +/**************************************************************************** + * Name: lpc43_registercallback + * + * Description: + * Register a callback that that will be invoked on any media status + * change. Callbacks should not be made from interrupt handlers, rather + * interrupt level events should be handled by calling back on the work + * thread. + * + * When this method is called, all callbacks should be disabled until they + * are enabled via a call to SDCARD_CALLBACKENABLE + * + * Input Parameters: + * dev - Device-specific state data + * callback - The funtion to call on the media change + * arg - A caller provided value to return with the callback + * + * Returned Value: + * 0 on success; negated errno on failure. + * + ****************************************************************************/ + +static int lpc43_registercallback(FAR struct sdio_dev_s *dev, + worker_t callback, void *arg) +{ + struct lpc43_dev_s *priv = (struct lpc43_dev_s *)dev; + + mcinfo("callback=%p arg=%p\n", callback, arg); + + /* Disable callbacks and register this callback and its argument */ + + mcinfo("Register %p(%p)\n", callback, arg); + DEBUGASSERT(priv != NULL); + + priv->cbevents = 0; + priv->cbarg = arg; + priv->callback = callback; + return OK; +} + +/**************************************************************************** + * Name: lpc43_dmarecvsetup + * + * Description: + * Setup to perform a read DMA. If the processor supports a data cache, + * then this method will also make sure that the contents of the DMA memory + * and the data cache are coherent. For read transfers this may mean + * invalidating the data cache. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * buffer - The memory to DMA from + * buflen - The size of the DMA transfer in bytes + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_LPC43_SDMMC_DMA +static int lpc43_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, + size_t buflen) +{ + struct lpc43_dev_s *priv = (struct lpc43_dev_s *)dev; + uint32_t regval; + uint32_t ctrl; + uint32_t maxs; + int i; + + /* Don't bother with DMA if the entire transfer will fit in the RX FIFO or + * if we do not have a 4-bit wide bus. + */ + + DEBUGASSERT(priv != NULL); + + if (buflen <= LPC43_RXFIFO_SIZE || !priv->widebus) + { + return lpc43_recvsetup(dev, buffer, buflen); + } + + mcinfo("buflen=%lu\n", (unsigned long)buflen); + DEBUGASSERT(buffer != NULL && buflen > 0 && ((uint32_t)buffer & 3) == 0); + + /* Reset DMA controller internal registers. The SWR bit automatically + * clears in one clock cycle. + */ + + lpc43_putreg(SDMMC_BMOD_SWR, LPC43_SDMMC_BMOD); + + /* Save the destination buffer information for use by the interrupt handler */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = buflen; + priv->wrdir = false; + priv->dmamode = true; + + /* Reset the FIFO and DMA */ + + regval = lpc43_getreg(LPC43_SDMMC_CTRL); + regval |= SDMMC_CTRL_FIFORESET | SDMMC_CTRL_DMARESET; + lpc43_putreg(regval, LPC43_SDMMC_CTRL); + + while ((lpc43_getreg(LPC43_SDMMC_CTRL) & SDMMC_CTRL_DMARESET) != 0) + { + } + + /* Configure the FIFO so that we will receive the DMA/FIFO requests whenever + * there more than than (FIFO_DEPTH/2) - 1 words in the FIFO. + */ + + regval = SDMMC_FIFOTH_RXWMARK(LPC43_RXFIFO_DEPTH / 2 - 1) | + SDMMC_FIFOTH_DMABURST_4XFRS; + lpc43_putreg(regval, LPC43_SDMMC_FIFOTH); + + /* Setup DMA list */ + + i = 0; + while (buflen > 0) + { + /* Limit size of the transfer to maximum buffer size */ + + maxs = buflen; + + if (maxs > MCI_DMADES1_MAXTR) + { + maxs = MCI_DMADES1_MAXTR; + } + + buflen -= maxs; + + /* Set buffer size */ + + g_sdmmc_dmadd[i].des1 = MCI_DMADES1_BS1(maxs); + + /* Setup buffer address (chained) */ + + g_sdmmc_dmadd[i].des2 = (uint32_t)priv->buffer + (i * MCI_DMADES1_MAXTR); + + /* Setup basic control */ + + ctrl = MCI_DMADES0_OWN | MCI_DMADES0_CH; + + if (i == 0) + { + ctrl |= MCI_DMADES0_FS; /* First DMA buffer */ + } + + /* No more data? Then this is the last descriptor */ + + if (buflen == 0) + { + ctrl |= MCI_DMADES0_LD; + } + else + { + ctrl |= MCI_DMADES0_DIC; + } + + /* Another descriptor is needed */ + + g_sdmmc_dmadd[i].des0 = ctrl; + g_sdmmc_dmadd[i].des3 = (uint32_t) &g_sdmmc_dmadd[i + 1]; + i++; + } + + lpc43_putreg((uint32_t)&g_sdmmc_dmadd[0], LPC43_SDMMC_DBADDR); + + /* Enable internal DMA, burst size of 4, fixed burst */ + + regval = lpc43_getreg(LPC43_SDMMC_CTRL); + regval |= SDMMC_CTRL_INTDMA; + lpc43_putreg(regval, LPC43_SDMMC_CTRL); + + regval = SDMMC_BMOD_DE | SDMMC_BMOD_PBL_4XFRS | SDMMC_BMOD_DSL(4); + lpc43_putreg(regval, LPC43_SDMMC_BMOD); + + /* Setup DMA error interrupts */ + + lpc43_config_dmaints(priv, SDCARD_DMARECV_MASK, SDCARD_DMAERROR_MASK); + return OK; +} +#endif + +/**************************************************************************** + * Name: lpc43_dmasendsetup + * + * Description: + * Setup to perform a write DMA. If the processor supports a data cache, + * then this method will also make sure that the contents of the DMA memory + * and the data cache are coherent. For write transfers, this may mean + * flushing the data cache. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * buffer - The memory to DMA into + * buflen - The size of the DMA transfer in bytes + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_LPC43_SDMMC_DMA +static int lpc43_dmasendsetup(FAR struct sdio_dev_s *dev, + FAR const uint8_t *buffer, size_t buflen) +{ + struct lpc43_dev_s *priv = (struct lpc43_dev_s *)dev; + uint32_t regval; + + /* Don't bother with DMA if the entire transfer will fit in the TX FIFO or + * if we do not have a 4-bit wide bus. + */ + + DEBUGASSERT(priv != NULL); + + if (buflen <= LPC43_TXFIFO_SIZE || !priv->widebus) + { + return lpc43_sendsetup(dev, buffer, buflen); + } + + mcinfo("buflen=%lu\n", (unsigned long)buflen); + DEBUGASSERT(buffer != NULL && buflen > 0 && ((uint32_t)buffer & 3) == 0); + + /* Reset DMA controller internal registers. The SWR bit automatically + * clears in one clock cycle. + */ + + lpc43_putreg(SDMMC_BMOD_SWR, LPC43_SDMMC_BMOD); + + /* Save the destination buffer information for use by the interrupt + * handler. + */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = buflen; + priv->wrdir = true; + priv->dmamode = true; + + /* Reset the FIFO and DMA */ + + regval = lpc43_getreg(LPC43_SDMMC_CTRL); + regval |= SDMMC_CTRL_FIFORESET | SDMMC_CTRL_DMARESET; + lpc43_putreg(regval, LPC43_SDMMC_CTRL); + + while ((lpc43_getreg(LPC43_SDMMC_CTRL) & SDMMC_CTRL_DMARESET) != 0) + { + } + + /* Configure the FIFO so that we will receive the DMA/FIFO requests whenever + * there are FIFO_DEPTH/2 or fewer words in the FIFO. + */ + + regval = SDMMC_FIFOTH_TXWMARK(LPC43_TXFIFO_DEPTH / 2) | + SDMMC_FIFOTH_DMABURST_4XFRS; + lpc43_putreg(regval, LPC43_SDMMC_FIFOTH); + + /* Setup DMA descriptor list */ + + g_sdmmc_dmadd[0].des0 = MCI_DMADES0_OWN | MCI_DMADES0_CH | MCI_DMADES0_LD; + g_sdmmc_dmadd[0].des1 = 512; + g_sdmmc_dmadd[0].des2 = (uint32_t)priv->buffer; + g_sdmmc_dmadd[0].des3 = (uint32_t)&g_sdmmc_dmadd[1]; + + lpc43_putreg((uint32_t) &g_sdmmc_dmadd[0], LPC43_SDMMC_DBADDR); + + /* Enable internal DMA, burst size of 4, fixed burst */ + + regval = lpc43_getreg(LPC43_SDMMC_CTRL); + regval |= SDMMC_CTRL_INTDMA; + lpc43_putreg(regval, LPC43_SDMMC_CTRL); + + regval = SDMMC_BMOD_DE | SDMMC_BMOD_PBL_4XFRS | SDMMC_BMOD_DSL(4); + lpc43_putreg(regval, LPC43_SDMMC_BMOD); + + /* Setup DMA error interrupts */ + + lpc43_config_dmaints(priv, SDCARD_DMASEND_MASK, SDCARD_DMAERROR_MASK); + return OK; +} +#endif + +/**************************************************************************** + * Name: lpc43_callback + * + * Description: + * Perform callback. + * + * Assumptions: + * This function does not execute in the context of an interrupt handler. + * It may be invoked on any user thread or scheduled on the work thread + * from an interrupt handler. + * + ****************************************************************************/ + +static void lpc43_callback(struct lpc43_dev_s *priv) +{ + /* Is a callback registered? */ + + mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", + priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus); + + if (priv->callback) + { + /* Yes.. Check for enabled callback events */ + + if ((priv->cdstatus & SDIO_STATUS_PRESENT) != 0) + { + /* Media is present. Is the media inserted event enabled? */ + + if ((priv->cbevents & SDIOMEDIA_INSERTED) == 0) + { + /* No... return without performing the callback */ + + return; + } + } + else + { + /* Media is not present. Is the media eject event enabled? */ + + if ((priv->cbevents & SDIOMEDIA_EJECTED) == 0) + { + /* No... return without performing the callback */ + + return; + } + } + + /* Perform the callback, disabling further callbacks. Of course, the + * the callback can (and probably should) re-enable callbacks. + */ + + priv->cbevents = 0; + + /* Callbacks cannot be performed in the context of an interrupt handler. + * If we are in an interrupt handler, then queue the callback to be + * performed later on the work thread. + */ + + if (up_interrupt_context()) + { + /* Yes.. queue it */ + + mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); + (void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0); + } + else + { + /* No.. then just call the callback here */ + + mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg); + priv->callback(priv->cbarg); + } + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc43_sdmmc_initialize + * + * Description: + * Initialize the SD/MMC peripheral for normal operation. + * + * Input Parameters: + * slotno - Not used. + * + * Returned Values: + * A reference to an SD card interface structure. NULL is returned on failures. + * + ****************************************************************************/ + +FAR struct sdio_dev_s *lpc43_sdmmc_initialize(int slotno) +{ + struct lpc43_dev_s *priv = &g_scard_dev; + irqstate_t flags; + uint32_t regval; + + mcinfo("slotno=%d\n", slotno); + flags = enter_critical_section(); + + /* Set up the clock source */ + + regval = getreg32(LPC43_BASE_SDIO_CLK); + regval &= ~BASE_SDIO_CLK_CLKSEL_MASK; + regval |= (BOARD_SDIO_CLKSRC | BASE_SDIO_CLK_AUTOBLOCK); + putreg32(regval, LPC43_BASE_SDIO_CLK); + + /* Enable clocking to the SD/MMC peripheral */ + + regval = lpc43_getreg(LPC43_CCU1_M4_SDIO_CFG); + regval |= CCU_CLK_CFG_RUN; + regval |= CCU_CLK_CFG_AUTO; + regval |= CCU_CLK_CFG_WAKEUP; + lpc43_putreg(regval, LPC43_CCU1_M4_SDIO_CFG); + + /* Initialize semaphores */ + + sem_init(&priv->waitsem, 0, 0); + + /* The waitsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + + /* Create a watchdog timer */ + + priv->waitwdog = wd_create(); + DEBUGASSERT(priv->waitwdog != NULL); + + /* Configure GPIOs for 4-bit, wide-bus operation */ + + lpc43_pin_config(GPIO_SD_D0); +#ifndef CONFIG_SDIO_WIDTH_D1_ONLY + lpc43_pin_config(GPIO_SD_D1); + lpc43_pin_config(GPIO_SD_D2); + lpc43_pin_config(GPIO_SD_D3); +#endif +#ifdef CONFIG_MMCSD_HAVE_CARDDETECT + lpc43_pin_config(GPIO_SD_CARD_DET_N); +#endif + lpc43_pin_config(GPIO_SD_CLK); + lpc43_pin_config(GPIO_SD_CMD); +#ifdef CONFIG_LPC43_SDMMC_PWRCTRL + lpc43_pin_config(GPIO_SD_POW_EN); +#endif +#ifdef CONFIG_MMCSD_HAVE_WRITEPROTECT + lpc43_pin_config(GPIO_SD_WR_PRT); +#endif + + regval = getreg32(LPC43_SCU_SFSCLK2); + regval |= (2 << 3); /* Disable pull-down and pull-up resistor */ + regval |= (1 << 6); /* Enable Input buffer */ + regval |= (4); /* Selects pin function 4 */ + putreg32(regval, LPC43_SCU_SFSCLK2); + + /* Reset the card and assure that it is in the initial, unconfigured + * state. + */ + + lpc43_reset(&priv->dev); + + leave_critical_section(flags); + return &g_scard_dev.dev; +} + +#endif /* CONFIG_LPC43_SDMMC */ diff --git a/arch/arm/src/lpc43xx/lpc43_sdmmc.h b/arch/arm/src/lpc43xx/lpc43_sdmmc.h new file mode 100644 index 0000000000000000000000000000000000000000..7a27088415cf16f294218165fe6fc3f73b2d846d --- /dev/null +++ b/arch/arm/src/lpc43xx/lpc43_sdmmc.h @@ -0,0 +1,88 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/lpc43_sdmmc.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_SDMMC_H +#define __ARCH_ARM_SRC_LPC43XX_LPC43_SDMMC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include + +#include "chip.h" +#include "chip/lpc43_sdmmc.h" + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: lpc43_sdmmc_initialize + * + * Description: + * Initialize the SD/MMC peripheral for normal operation. + * + * Input Parameters: + * slotno - Not used. + * + * Returned Values: + * A reference to an SDIO interface structure. NULL is returned on failures. + * + ****************************************************************************/ + +struct lpc43_sdmmc_dev_s; /* See include/nuttx/sdio.h */ +FAR struct sdio_dev_s *lpc43_sdmmc_initialize(int slotno); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_SDMMC_H */ diff --git a/arch/arm/src/lpc43xx/lpc43_start.c b/arch/arm/src/lpc43xx/lpc43_start.c index e3fe5c552e8b37ff2f652875cd35027fdac61b51..5b3103197d26e2aaa0f805cd6345c1212ef36c54 100644 --- a/arch/arm/src/lpc43xx/lpc43_start.c +++ b/arch/arm/src/lpc43xx/lpc43_start.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc43xx/lpc43_start.c * - * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -60,7 +60,6 @@ #include #include -#include #include #include "up_arch.h" @@ -74,6 +73,7 @@ #include "lpc43_emc.h" #include "lpc43_uart.h" #include "lpc43_userspace.h" +#include "lpc43_start.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/lpc43xx/lpc43_start.h b/arch/arm/src/lpc43xx/lpc43_start.h new file mode 100644 index 0000000000000000000000000000000000000000..27e4e754ae84d00828beb3b1271b702b3d844fa2 --- /dev/null +++ b/arch/arm/src/lpc43xx/lpc43_start.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/lpc43_start.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_START_H +#define __ARCH_ARM_SRC_LPC43XX_LPC43_START_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc43_boardinitialize + * + * Description: + * All LPC43xx architectures must provide the following entry point. This entry + * point is called early in the initialization -- after clocking and memory have + * been configured but before caches have been enabled and before any devices have + * been initialized. + * + ************************************************************************************/ + +void lpc43_boardinitialize(void); + +#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_START_H */ diff --git a/arch/arm/src/lpc43xx/lpc43_tickless_rit.c b/arch/arm/src/lpc43xx/lpc43_tickless_rit.c index cacfb47c91b0a6a3c955dda7b7cc0c7f34b09968..6ffaac8f80f387490abfb2cf940013db4a044920 100644 --- a/arch/arm/src/lpc43xx/lpc43_tickless_rit.c +++ b/arch/arm/src/lpc43xx/lpc43_tickless_rit.c @@ -197,7 +197,7 @@ static inline bool lpc43_tl_get_interrupt(void) /* Converters */ -static uint32_t commonDev(uint32_t a, uint32_t b) +static uint32_t common_dev(uint32_t a, uint32_t b) { while (b != 0) { @@ -449,17 +449,17 @@ static void lpc43_tl_looped_forced_set_compare(void) static bool lpc43_tl_set_calc_arm(uint32_t curr, uint32_t to_set, bool arm) { - uint32_t calcTime; + uint32_t calc_time; if (curr < TO_RESET_NEXT) { - calcTime = min(TO_RESET_NEXT, to_set); + calc_time = min(TO_RESET_NEXT, to_set); } else { if (curr < TO_END) { - calcTime = min(curr + RESET_TICKS, to_set); + calc_time = min(curr + RESET_TICKS, to_set); } else { @@ -468,9 +468,9 @@ static bool lpc43_tl_set_calc_arm(uint32_t curr, uint32_t to_set, bool arm) } } - bool set = lpc43_tl_set_safe_compare(calcTime); + bool set = lpc43_tl_set_safe_compare(calc_time); - if (arm && set && (calcTime == to_set)) + if (arm && set && (calc_time == to_set)) { armed = true; } @@ -557,17 +557,17 @@ static int lpc43_tl_isr(int irq, FAR void *context, FAR void *arg) { if (alarm_time_set) /* need to set alarm time */ { - uint32_t toSet = lpc43_tl_calc_to_set(); + uint32_t toset = lpc43_tl_calc_to_set(); - if (toSet > curr) + if (toset > curr) { - if (toSet > TO_END) + if (toset > TO_END) { lpc43_tl_set_default_compare(curr); } else { - bool set = lpc43_tl_set_calc_arm(curr, toSet, true); + bool set = lpc43_tl_set_calc_arm(curr, toset, true); if (!set) { lpc43_tl_alarm(curr); @@ -605,7 +605,7 @@ void arm_timer_initialize(void) mask_cache = getreg32(LPC43_RIT_MASK); compare_cache = getreg32(LPC43_RIT_COMPVAL); - COMMON_DEV = commonDev(NSEC_PER_SEC, LPC43_CCLK); + COMMON_DEV = common_dev(NSEC_PER_SEC, LPC43_CCLK); MIN_TICKS = LPC43_CCLK/COMMON_DEV; MIN_NSEC = NSEC_PER_SEC/COMMON_DEV; @@ -651,16 +651,16 @@ int up_timer_gettime(FAR struct timespec *ts) if (lpc43_tl_get_reset_on_match()) { - bool resetAfter = lpc43_tl_get_interrupt(); + bool reset_after = lpc43_tl_get_interrupt(); /* Was a reset during processing? get new counter */ - if (reset != resetAfter) + if (reset != reset_after) { count = lpc43_tl_get_counter(); } - if (resetAfter) + if (reset_after) { /* Count should be smaller then UINT32_MAX-TO_END -> no overflow */ @@ -710,19 +710,19 @@ int up_alarm_start(FAR const struct timespec *ts) alarm_time_ts.tv_sec = ts->tv_sec; alarm_time_ts.tv_nsec = ts->tv_nsec; - uint32_t toSet = lpc43_tl_calc_to_set(); + uint32_t toset = lpc43_tl_calc_to_set(); uint32_t curr = lpc43_tl_get_counter(); - if (toSet > curr) + if (toset > curr) { - if (toSet > TO_END) /* Future set */ + if (toset > TO_END) /* Future set */ { lpc43_tl_set_default_compare(curr); } else { - bool set = lpc43_tl_set_calc_arm(curr, toSet, true); + bool set = lpc43_tl_set_calc_arm(curr, toset, true); if (!set) /* Signal call, force interrupt handler */ { call = true; diff --git a/arch/arm/src/lpc43xx/lpc43_userspace.c b/arch/arm/src/lpc43xx/lpc43_userspace.c index 43ded6b4abeb24b0593121058351594e5dbd0042..c884e3c77bf094a721866d81fb3509c698c0f40c 100644 --- a/arch/arm/src/lpc43xx/lpc43_userspace.c +++ b/arch/arm/src/lpc43xx/lpc43_userspace.c @@ -49,18 +49,6 @@ #ifdef CONFIG_BUILD_PROTECTED -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/arm/src/lpc43xx/lpc43_userspace.h b/arch/arm/src/lpc43xx/lpc43_userspace.h index 77b6d1e609225a5c72cf34b173ef6ef995384ac0..46d16637a9473cb76dda9702bdf8385a261525de 100644 --- a/arch/arm/src/lpc43xx/lpc43_userspace.h +++ b/arch/arm/src/lpc43xx/lpc43_userspace.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/lpc43xx/lpc43_qei.h + * arch/arm/src/lpc43xx/lpc43_userspace.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -43,19 +43,7 @@ #include /************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions + * Public Function Prototypes ************************************************************************************/ /**************************************************************************** diff --git a/arch/arm/src/lpc43xx/lpc43_wdt.h b/arch/arm/src/lpc43xx/lpc43_wdt.h new file mode 100644 index 0000000000000000000000000000000000000000..af427504e4dc53fa8c75031ea4d12165852756f7 --- /dev/null +++ b/arch/arm/src/lpc43xx/lpc43_wdt.h @@ -0,0 +1,97 @@ +/**************************************************************************** + * arch/arm/src/lpc43xx/lpc43_wdt.h + * + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_WDT_H +#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_WDT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc43_wdt.h" + +#ifdef CONFIG_WATCHDOG + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc43_wwtginitialize + * + * Description: + * Initialize the WWDG watchdog time. The watchdog timer is initializeed and + * registers as 'devpath. The initial state of the watchdog time is + * disabled. + * + * Input Parameters: + * devpath - The full path to the watchdog. This should be of the form + * /dev/watchdog0 + * + * Returned Values: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_LPC43_WWDT +void lpc43_wwdtinitialize(FAR const char *devpath); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_WATCHDOG */ +#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_WDT_H */ diff --git a/arch/arm/src/lpc43xx/lpc43_wwdt.c b/arch/arm/src/lpc43xx/lpc43_wwdt.c new file mode 100644 index 0000000000000000000000000000000000000000..872e8d5f3f5b063c11f0b129cabf09bc0ccd397c --- /dev/null +++ b/arch/arm/src/lpc43xx/lpc43_wwdt.c @@ -0,0 +1,662 @@ +/**************************************************************************** + * arch/arm/src/lpc43xx/lpc43_wwdt.c + * + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "lpc43_wdt.h" +#include "chip/lpc43_wwdt.h" + +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_LPC43_WWDT) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Clocking *****************************************************************/ + +#define WWDT_FREQ 3000000 /* Watchdog clock is IRC 12MHz, but + * it has fixed divider by 4 */ +#define LPC43_MAX_WWDT_TC 0xFFFFFF /* 24-bit counter max value */ +#define LPC43_MIN_WWDT_TC 0xFF /* 8-bit counter min value */ +#define LPC43_MAX_WWDT_WINDOW 0xFFFFFF /* 24-bit max value */ +#define LPC43_MIN_WWDT_WINDOW 0x100 /* Minimum window value allowed */ +#define WWDT_WARNINT_VALUE 0x3FF /* 10-bit max value */ +#define WWDT_MAXTIMEOUT 5592 /* Max timeout value in miliseconds */ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_LPC43_WWDT_DEFTIMOUT +# define CONFIG_LPC43_WWDT_DEFTIMOUT WWDT_MAXTIMEOUT +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * well-known watchdog_lowerhalf_s structure. + */ + +struct lpc43_lowerhalf_wwdt_s +{ + FAR const struct watchdog_ops_s *ops; /* Lower half operations */ + xcpt_t handler; /* Current watchdog interrupt handler */ + uint32_t timeout; /* The actual timeout value */ + bool started; /* The timer has been started */ + uint32_t reload; /* The 24-bit reload field reset value */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void lpc43_setwindow(uint32_t window); +static void lpc43_setwarning(uint32_t warning); + +/* Interrupt hanlding *******************************************************/ + +static int lpc43_interrupt(int irq, FAR void *context); + +/* "Lower half" driver methods **********************************************/ + +static int lpc43_start(FAR struct watchdog_lowerhalf_s *lower); +static int lpc43_stop(FAR struct watchdog_lowerhalf_s *lower); +static int lpc43_keepalive(FAR struct watchdog_lowerhalf_s *lower); +static int lpc43_getstatus(FAR struct watchdog_lowerhalf_s *lower, + FAR struct watchdog_status_s *status); +static int lpc43_settimeout(FAR struct watchdog_lowerhalf_s *lower, + uint32_t timeout); +static xcpt_t lpc43_capture(FAR struct watchdog_lowerhalf_s *lower, + xcpt_t handler); +static int lpc43_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static const struct watchdog_ops_s g_wdgops = +{ + .start = lpc43_start, + .stop = lpc43_stop, + .keepalive = lpc43_keepalive, + .getstatus = lpc43_getstatus, + .settimeout = lpc43_settimeout, + .capture = lpc43_capture, + .ioctl = lpc43_ioctl, +}; + +/* "Lower half" driver state */ + +static struct lpc43_lowerhalf_wwdt_s g_wdgdev; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc43_setwindow + * + * Description: + * The window register determines the highest timeout value allowed when a + * watchdog feed is performed. If a feed valid sequence completes prior to + * timeout value reaching the value in window, a watchdog event will occur. + * + * window resets to the maximum possible timeout value, so windowing is not + * in effect. Values of window below 0x100 will make it impossible to ever + * feed the watchdog successfully + * + ****************************************************************************/ + +static void lpc43_setwindow(uint32_t window) +{ + /* WWDT window minimum value limiting */ + + if (window < 0x100) + { + window = 0x100; + } + + putreg32(window, LPC43_WWDT_WINDOW); +} + +/**************************************************************************** + * Name: lpc43_setwarning + * + * Description: + * The WDWARNINT register determines the watchdog timer counter value that + * will generate a watchdog interrupt. When the watchdog timer counter + * matches the value defined by WDWARNINT, an interrupt will be generated + * after the subsequent WDCLK. A match of the watchdog timer counter to + * WDWARNINT occurs when the bottom 10 bits of the counter have the same + * value as the 10 bits of WARNINT, and the remaining upper bits of the + * counter are all 0. This gives a maximum time of 1,023 watchdog timer + * counts (4,096 watchdog clocks) for the interrupt to occur prior to a + * watchdog event. If WDWARNINT is set to 0, the interrupt will occur at + * the same time as the watchdog event. + * + ****************************************************************************/ + +static void lpc43_setwarning(uint32_t warning) +{ + /* WWDT warning maximum value limiting */ + + if (warning > 0x3FF) + { + warning = 0x3FF; + } + + putreg32(warning, LPC43_WWDT_WARNINT); +} + +/**************************************************************************** + * Name: lpc43_interrupt + * + * Description: + * WWDT warning interrupt + * + * Input Parameters: + * Usual interrupt handler arguments. + * + * Returned Values: + * Always returns OK. + * + ****************************************************************************/ + +static int lpc43_interrupt(int irq, FAR void *context) +{ + FAR struct lpc43_lowerhalf_wwdt_s *priv = &g_wdgdev; + uint32_t regval; + + /* Check if the watchdog warning interrupt is really pending */ + + regval = getreg32(LPC43_WWDT_MOD); + if ((regval & WWDT_MOD_WDINT) != 0) + { + /* Is there a registered handler? */ + + if (priv->handler) + { + /* Yes... NOTE: This interrupt service routine (ISR) must reload + * the WWDT counter to prevent the reset. Otherwise, we will + * reset upon return. + */ + + priv->handler(irq, context); + } + + /* The watchdog interrupt flag is cleared by writing '1' to the WDINT + * bit in the WDMOD register. + */ + + regval |= WWDT_MOD_WDINT; + putreg32(regval, LPC43_WWDT_MOD); + } + + return OK; +} + +/**************************************************************************** + * Name: lpc43_start + * + * Description: + * Start the watchdog timer, resetting the time to the current timeout, + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc43_start(FAR struct watchdog_lowerhalf_s *lower) +{ + FAR struct lpc43_lowerhalf_wwdt_s *priv = + (FAR struct lpc43_lowerhalf_wwdt_s *)lower; + + wdinfo("Entry\n"); + DEBUGASSERT(priv); + + /* The watchdog is always disabled after a reset. It is enabled by setting + * the WDEN bit in the WDMOD register, then it cannot be disabled again + * except by a reset. + * + * Watchdog is enabled and will reset the chip + */ + + putreg32(WWDT_MOD_WDEN | WWDT_MOD_WDRESET , LPC43_WWDT_MOD); + + /* Feed the watchdog to enable it */ + + putreg32(0xAA, LPC43_WWDT_FEED); + putreg32(0x55, LPC43_WWDT_FEED); + + priv->started = true; + return OK; +} + +/**************************************************************************** + * Name: lpc43_stop + * + * Description: + * Stop the watchdog timer + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc43_stop(FAR struct watchdog_lowerhalf_s *lower) +{ + + /* The watchdog is always disabled after a reset. It is enabled by setting + * the WDEN bit in the WDMOD register, then it cannot be disabled again + * except by a reset. + */ + + wdinfo("Entry\n"); + return -ENOSYS; +} + +/**************************************************************************** + * Name: lpc43_keepalive + * + * Description: + * Reset the watchdog timer to the current timeout value, prevent any + * imminent watchdog timeouts. This is sometimes referred as "pinging" + * the watchdog timer or "feeding the dog". + * + * The application program must write in the FEED register at regular + * intervals during normal operation to prevent an MCU reset. This operation + * must occur only when the counter value is lower than the window register + * value. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc43_keepalive(FAR struct watchdog_lowerhalf_s *lower) +{ + FAR struct lpc43_lowerhalf_wwdt_s *priv = + (FAR struct lpc43_lowerhalf_wwdt_s *)lower; + + wdinfo("Entry\n"); + DEBUGASSERT(priv); + + /* Feed the watchdog */ + + putreg32(0xAA, LPC43_WWDT_FEED); + putreg32(0x55, LPC43_WWDT_FEED); + + return OK; +} + +/**************************************************************************** + * Name: lpc43_getstatus + * + * Description: + * Get the current watchdog timer status + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * status - The location to return the watchdog status information. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc43_getstatus(FAR struct watchdog_lowerhalf_s *lower, + FAR struct watchdog_status_s *status) +{ + FAR struct lpc43_lowerhalf_wwdt_s *priv = + (FAR struct lpc43_lowerhalf_wwdt_s *)lower; + uint32_t elapsed; + uint32_t reload; + + wdinfo("Entry\n"); + DEBUGASSERT(priv); + + /* Return the status bit */ + + status->flags = WDFLAGS_RESET; + if (priv->started) + { + status->flags |= WDFLAGS_ACTIVE; + } + + if (priv->handler) + { + status->flags |= WDFLAGS_CAPTURE; + } + + /* Return the actual timeout is milliseconds */ + + status->timeout = priv->timeout; + + /* Get the time remaining until the watchdog expires (in milliseconds) */ + + + reload = getreg32(LPC43_WWDT_TC); + elapsed = priv->reload - reload; + status->timeleft = (priv->timeout * elapsed) / (priv->reload + 1); + + wdinfo("Status :\n"); + wdinfo(" flags : %08x\n", status->flags); + wdinfo(" timeout : %d\n", status->timeout); + wdinfo(" timeleft : %d\n", status->flags); + return OK; +} + +/**************************************************************************** + * Name: lpc43_settimeout + * + * Description: + * Set a new timeout value (and reset the watchdog timer) + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * timeout - The new timeout value in milliseconds. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc43_settimeout(FAR struct watchdog_lowerhalf_s *lower, + uint32_t timeout) +{ + FAR struct lpc43_lowerhalf_wwdt_s *priv = + (FAR struct lpc43_lowerhalf_wwdt_s *)lower; + uint32_t reload; + uint32_t regval; + + DEBUGASSERT(priv); + wdinfo("Entry: timeout=%d\n", timeout); + + /* Can this timeout be represented? */ + + if (timeout < 1 || timeout > WWDT_MAXTIMEOUT) + { + wderr("ERROR: Cannot represent timeout=%d > %d\n", + timeout, WWDT_MAXTIMEOUT_MS); + return -ERANGE; + } + + /* Determine timeout value */ + + reload = WWDT_FREQ/1000; + reload = timeout * reload; + + /* Make sure that the final reload value is within range */ + + if (reload > LPC43_MAX_WWDT_TC) + { + reload = LPC43_MAX_WWDT_TC; + } + + /* Save the actual timeout value in milliseconds*/ + + priv->timeout = timeout; + + /* Remember the selected values */ + + priv->reload = reload; + wdinfo("reload=%d timout=%d\n", reload, priv->timeout); + regval = reload; + putreg32(regval, LPC43_WWDT_TC); + + /* Reset the t window value to the maximum value.. essentially disabling + * the lower limit of the watchdog reset time. + */ + + lpc43_setwindow(LPC43_MAX_WWDT_WINDOW); + + /* Set the warning interrupt register value */ + + lpc43_setwarning(WWDT_WARNINT_VALUE); + return OK; +} + +/**************************************************************************** + * Name: lpc43_capture + * + * Description: + * Don't reset on watchdog timer timeout; instead, call this user provider + * timeout handler. NOTE: Providing handler==NULL will restore the reset + * behavior. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * newhandler - The new watchdog expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored, + * + * Returned Values: + * The previous watchdog expiration function pointer or NULL is there was + * no previous function pointer, i.e., if the previous behavior was + * reset-on-expiration (NULL is also returned if an error occurs). + * + ****************************************************************************/ + +static xcpt_t lpc43_capture(FAR struct watchdog_lowerhalf_s *lower, + xcpt_t handler) +{ + FAR struct lpc43_lowerhalf_wwdt_s *priv = + (FAR struct lpc43_lowerhalf_wwdt_s *)lower; + irqstate_t flags; + xcpt_t oldhandler; + uint16_t regval; + + DEBUGASSERT(priv); + wdinfo("Entry: handler=%p\n", handler); + + /* Get the old handler return value */ + + flags = enter_critical_section(); + oldhandler = priv->handler; + + /* Save the new handler */ + + priv->handler = handler; + + /* Are we attaching or detaching the handler? */ + + regval = getreg32(LPC43_WWDT_MOD); + if (handler) + { + /* Attaching... Enable the watchdog interrupt */ + + regval |= WWDT_MOD_WDINT; + putreg32(regval, LPC43_WWDT_MOD); + + up_enable_irq(LPC43M4_IRQ_WWDT); + } + else + { + /* Detaching... Disable the EWI interrupt */ + + regval &= ~WWDT_MOD_WDINT; + putreg32(regval, LPC43_WWDT_MOD); + + up_disable_irq(LPC43M4_IRQ_WWDT); + } + + leave_critical_section(flags); + return oldhandler; +} + +/**************************************************************************** + * Name: lp43_ioctl + * + * Description: + * Any ioctl commands that are not recognized by the "upper-half" driver + * are forwarded to the lower half driver through this method. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * cmd - The ioctl command value + * arg - The optional argument that accompanies the 'cmd'. The + * interpretation of this argument depends on the particular + * command. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc43_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd, + unsigned long arg) +{ + FAR struct lpc43_lowerhalf_wwdt_s *priv = + (FAR struct lpc43_lowerhalf_wwdt_s *)lower; + int ret = -ENOTTY; + + DEBUGASSERT(priv); + wdinfo("Entry: cmd=%d arg=%ld\n", cmd, arg); + + /* WDIOC_MINTIME: Set the minimum ping time. If two keepalive ioctls + * are received within this time, a reset event will be generated. + * Argument: A 32-bit time value in milliseconds. + */ + + if (cmd == WDIOC_MINTIME) + { + uint32_t mintime = (uint32_t)arg; + + /* The minimum time should be strictly less than the total delay + * which, in turn, will be less than or equal to LPC43_MAX_WWDT_TC + */ + + ret = -EINVAL; + if (mintime < priv->timeout) + { + uint32_t window = mintime*WWDT_FREQ/1000; + DEBUGASSERT(window < priv->reload); + lpc43_setwindow( window ); + ret = OK; + } + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc43_wwdginitialize + * + * Description: + * Initialize the WWDT watchdog time. The watchdog timer is initialized and + * registers as 'devpath. The initial state of the watchdog time is + * disabled. + * + * Input Parameters: + * devpath - The full path to the watchdog. This should be of the form + * /dev/watchdog0 + * + * Returned Values: + * None + * + ****************************************************************************/ + +void lpc43_wwdginitialize(FAR const char *devpath) +{ + FAR struct lpc43_lowerhalf_wwdt_s *priv = &g_wdgdev; + + wdinfo("Entry: devpath=%s\n", devpath); + + /* Initialize the driver state structure. Here we assume: (1) the state + * structure lies in .bss and was zeroed at reset time. (2) This function + * is only called once so it is never necessary to re-zero the structure. + */ + + priv->ops = &g_wdgops; + + /* Set watchdog mode register to zero */ + + putreg32(0, LPC43_WWDT_MOD); + + /* Attach our watchdog interrupt handler (But don't enable it yet) */ + + (void)irq_attach(LPC43M4_IRQ_WWDT, lpc43_interrupt); + + /* Select an arbitrary initial timeout value. But don't start the watchdog + * yet. NOTE: If the "Hardware watchdog" feature is enabled through the + * device option bits, the watchdog is automatically enabled at power-on. + */ + + lpc43_settimeout((FAR struct watchdog_lowerhalf_s *)priv, + CONFIG_LPC43_WWDT_DEFTIMOUT); + + /* Register the watchdog driver as /dev/watchdog0 */ + + (void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv); +} + +#endif /* CONFIG_WATCHDOG && CONFIG_LPC43_WWDT */ diff --git a/arch/arm/src/lpc54xx/Kconfig b/arch/arm/src/lpc54xx/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..bc77fb071992cfa6024976919edebd97e1ddb5e3 --- /dev/null +++ b/arch/arm/src/lpc54xx/Kconfig @@ -0,0 +1,1043 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "LPC54xx Configuration Options" + +choice + prompt "LPC54XX Chip Selection" + default ARCH_CHIP_LPC54628 + depends on ARCH_CHIP_LPC54XX + +config ARCH_CHIP_LPC54628 + bool "LPC54628" + select ARCH_FAMILY_LPC546XX + select ARCH_LPC54_HAVE_FSUSB + select ARCH_LPC54_HAVE_HSUSB + select ARCH_LPC54_HAVE_ETHERNET + select ARCH_LPC54_HAVE_CAN20 + select ARCH_LPC54_HAVE_CANFD + select ARCH_LPC54_HAVE_LCD + select ARCH_LPC54_HAVE_SHA + +config ARCH_CHIP_LPC54618 + bool "LPC54618" + select ARCH_FAMILY_LPC546XX + select ARCH_LPC54_HAVE_FSUSB + select ARCH_LPC54_HAVE_HSUSB + select ARCH_LPC54_HAVE_ETHERNET + select ARCH_LPC54_HAVE_CAN20 + select ARCH_LPC54_HAVE_CANFD + select ARCH_LPC54_HAVE_LCD + +config ARCH_CHIP_LPC54616 + bool "LPC54616" + select ARCH_FAMILY_LPC546XX + select ARCH_LPC54_HAVE_FSUSB + select ARCH_LPC54_HAVE_HSUSB + select ARCH_LPC54_HAVE_ETHERNET + select ARCH_LPC54_HAVE_CAN20 + select ARCH_LPC54_HAVE_CANFD + +config ARCH_CHIP_LPC54608 + bool "LPC54608" + select ARCH_FAMILY_LPC546XX + select ARCH_LPC54_HAVE_FSUSB + select ARCH_LPC54_HAVE_ETHERNET + select ARCH_LPC54_HAVE_CAN20 + select ARCH_LPC54_HAVE_LCD + +config ARCH_CHIP_LPC54607 + bool "LPC54607" + select ARCH_FAMILY_LPC546XX + select ARCH_LPC54_HAVE_FSUSB + select ARCH_LPC54_HAVE_HSUSB + select ARCH_LPC54_HAVE_ETHERNET + +config ARCH_CHIP_LPC54606 + bool "LPC54606" + select ARCH_FAMILY_LPC546XX + select ARCH_LPC54_HAVE_FSUSB + select ARCH_LPC54_HAVE_HSUSB + select ARCH_LPC54_HAVE_ETHERNET + select ARCH_LPC54_HAVE_CAN20 + +config ARCH_CHIP_LPC54605 + bool "LPC54605" + select ARCH_FAMILY_LPC546XX + select ARCH_LPC54_HAVE_FSUSB + select ARCH_LPC54_HAVE_HSUSB + +endchoice # LPC54XX Chip Selection + +# LPC54xx Families + +config ARCH_FAMILY_LPC546XX + bool + default n + +# Peripheral support + +config ARCH_LPC54_HAVE_FSUSB + bool + default n + +config ARCH_LPC54_HAVE_HSUSB + bool + default n + +config ARCH_LPC54_HAVE_ETHERNET + bool + default n + +config ARCH_LPC54_HAVE_CAN20 + bool + default n + +config ARCH_LPC54_HAVE_CANFD + bool + default n + +config ARCH_LPC54_HAVE_LCD + bool + default n + +config ARCH_LPC54_HAVE_SHA + bool + default n + +# Peripheral Selection + +config LPC54_HAVE_I2C_MASTER + bool + default n + +config LPC54_HAVE_FLEXCOMM + bool + default n + +config LPC54_FLEXCOMM0 + bool + default n + select LPC54_HAVE_FLEXCOMM + +config LPC54_FLEXCOMM1 + bool + default n + select LPC54_HAVE_FLEXCOMM + +config LPC54_FLEXCOMM2 + bool + default n + select LPC54_HAVE_FLEXCOMM + +config LPC54_FLEXCOMM3 + bool + default n + select LPC54_HAVE_FLEXCOMM + +config LPC54_FLEXCOMM4 + bool + default n + select LPC54_HAVE_FLEXCOMM + +config LPC54_FLEXCOMM5 + bool + default n + select LPC54_HAVE_FLEXCOMM + +config LPC54_FLEXCOMM6 + bool + default n + select LPC54_HAVE_FLEXCOMM + +config LPC54_FLEXCOMM7 + bool + default n + select LPC54_HAVE_FLEXCOMM + +config LPC54_FLEXCOMM8 + bool + default n + select LPC54_HAVE_FLEXCOMM + +config LPC54_FLEXCOMM9 + bool + default n + select LPC54_HAVE_FLEXCOMM + +config LPC54_HAVE_SPI_MASTER + bool + default n + +config LPC54_HAVE_USART + bool + default n + +menu "LPC54xx Peripheral Selection" + +config LPC54_DMA + bool "DMA" + default n + select ARCH_DMA + depends on EXPERIMENTAL + +menu "Flexcomm Peripherals" + +config LPC54_I2C0_MASTER + bool "I2C0 Master" + default n + select LPC54_FLEXCOMM0 + select LPC54_HAVE_I2C_MASTER + +config LPC54_I2C1_MASTER + bool "I2C1 Master" + default n + select LPC54_FLEXCOMM1 + select LPC54_HAVE_I2C_MASTER + +config LPC54_I2C2_MASTER + bool "I2C2 Master" + default n + select LPC54_FLEXCOMM2 + select LPC54_HAVE_I2C_MASTER + +config LPC54_I2C3_MASTER + bool "I2C3 Master" + default n + select LPC54_FLEXCOMM3 + select LPC54_HAVE_I2C_MASTER + +config LPC54_I2C4_MASTER + bool "I2C4 Master" + default n + select LPC54_FLEXCOMM4 + select LPC54_HAVE_I2C_MASTER + +config LPC54_I2C5_MASTER + bool "I2C5 Master" + default n + select LPC54_FLEXCOMM5 + select LPC54_HAVE_I2C_MASTER + +config LPC54_I2C6_MASTER + bool "I2C6 Master" + default n + select LPC54_FLEXCOMM6 + select LPC54_HAVE_I2C_MASTER + +config LPC54_I2C7_MASTER + bool "I2C7 Master" + default n + select LPC54_FLEXCOMM7 + select LPC54_HAVE_I2C_MASTER + +config LPC54_I2C8_MASTER + bool "I2C8 Master" + default n + select LPC54_FLEXCOMM8 + select LPC54_HAVE_I2C_MASTER + +config LPC54_I2C9_MASTER + bool "I2C9 Master" + default n + select LPC54_FLEXCOMM9 + select LPC54_HAVE_I2C_MASTER + +config LPC54_SPI0_MASTER + bool "SPI0 Master" + default n + depends on !LPC54_I2C0_MASTER && EXPERIMENTAL + select LPC54_FLEXCOMM0 + select LPC54_HAVE_SPI_MASTER + +config LPC54_SPI1_MASTER + bool "SPI1 Master" + default n + depends on !LPC54_I2C1_MASTER && EXPERIMENTAL + select LPC54_FLEXCOMM1 + select LPC54_HAVE_SPI_MASTER + +config LPC54_SPI2_MASTER + bool "SPI2 Master" + default n + depends on !LPC54_I2C2_MASTER && EXPERIMENTAL + select LPC54_FLEXCOMM2 + select LPC54_HAVE_SPI_MASTER + +config LPC54_SPI3_MASTER + bool "SPI3 Master" + default n + depends on !LPC54_I2C3_MASTER && EXPERIMENTAL + select LPC54_FLEXCOMM3 + select LPC54_HAVE_SPI_MASTER + +config LPC54_SPI4_MASTER + bool "SPI4 Master" + default n + depends on !LPC54_I2C4_MASTER && EXPERIMENTAL + select LPC54_FLEXCOMM4 + select LPC54_HAVE_SPI_MASTER + +config LPC54_SPI5_MASTER + bool "SPI5 Master" + default n + depends on !LPC54_I2C5_MASTER && EXPERIMENTAL + select LPC54_FLEXCOMM5 + select LPC54_HAVE_SPI_MASTER + +config LPC54_SPI6_MASTER + bool "SPI6 Master" + default n + depends on !LPC54_I2C6_MASTER && EXPERIMENTAL + select LPC54_FLEXCOMM6 + select LPC54_HAVE_SPI_MASTER + +config LPC54_SPI7_MASTER + bool "SPI7 Master" + default n + depends on !LPC54_I2C7_MASTER && EXPERIMENTAL + select LPC54_FLEXCOMM7 + select LPC54_HAVE_SPI_MASTER + +config LPC54_SPI8_MASTER + bool "SPI8 Master" + default n + depends on !LPC54_I2C8_MASTER && EXPERIMENTAL + select LPC54_FLEXCOMM8 + select LPC54_HAVE_SPI_MASTER + +config LPC54_SPI9_MASTER + bool "SPI9 Master" + default n + depends on !LPC54_I2C9_MASTER && EXPERIMENTAL + select LPC54_FLEXCOMM9 + select LPC54_HAVE_SPI_MASTER + +config LPC54_USART0 + bool "USART0" + default n + depends on !LPC54_I2C0_MASTER && !LPC54_SPI0_MASTER + select LPC54_FLEXCOMM0 + select USART0_SERIALDRIVER + select LPC54_HAVE_USART + +config LPC54_USART1 + bool "USART1" + default n + depends on !LPC54_I2C1_MASTER && !LPC54_SPI1_MASTER + select LPC54_FLEXCOMM1 + select USART1_SERIALDRIVER + select LPC54_HAVE_USART + +config LPC54_USART2 + bool "USART2" + default n + depends on !LPC54_I2C2_MASTER && !LPC54_SPI2_MASTER + select LPC54_FLEXCOMM2 + select USART2_SERIALDRIVER + select LPC54_HAVE_USART + +config LPC54_USART3 + bool "USART3" + default n + depends on !LPC54_I2C3_MASTER && !LPC54_SPI3_MASTER + select LPC54_FLEXCOMM3 + select USART3_SERIALDRIVER + select LPC54_HAVE_USART + +config LPC54_USART4 + bool "USART4" + default n + depends on !LPC54_I2C4_MASTER && !LPC54_SPI4_MASTER + select LPC54_FLEXCOMM4 + select USART4_SERIALDRIVER + select LPC54_HAVE_USART + +config LPC54_USART5 + bool "USART5" + default n + depends on !LPC54_I2C5_MASTER && !LPC54_SPI5_MASTER + select LPC54_FLEXCOMM5 + select USART5_SERIALDRIVER + select LPC54_HAVE_USART + +config LPC54_USART6 + bool "USART6" + default n + depends on !LPC54_I2C6_MASTER && !LPC54_SPI6_MASTER + select LPC54_FLEXCOMM6 + select USART6_SERIALDRIVER + select LPC54_HAVE_USART + +config LPC54_USART7 + bool "USART7" + default n + depends on !LPC54_I2C7_MASTER && !LPC54_SPI7_MASTER + select LPC54_FLEXCOMM7 + select USART7_SERIALDRIVER + select LPC54_HAVE_USART + +config LPC54_USART8 + bool "USART8" + default n + depends on !LPC54_I2C8_MASTER && !LPC54_SPI8_MASTER + select LPC54_FLEXCOMM8 + select USART8_SERIALDRIVER + select LPC54_HAVE_USART + +config LPC54_USART9 + bool "USART9" + default n + depends on !LPC54_I2C9_MASTER && !LPC54_SPI9_MASTER + select LPC54_FLEXCOMM9 + select USART9_SERIALDRIVER + select LPC54_HAVE_USART + +endmenu # Flexcomm Peripherals + +config LPC54_EMC + bool "External Memory Controller (EMC)" + default n + +config LPC54_ETHERNET + bool "Ethernet" + default n + select NETDEVICES + select ARCH_HAVE_PHY + +config LPC54_LCD + bool "LCD controller" + default n + depends on ARCH_LPC54_HAVE_LCD + +config LPC54_RNG + bool "Random Number Generator (RNG)" + default n + select ARCH_HAVE_RNG + +config LPC54_RTC + bool "Real Time Clock (RTC)" + default n + select RTC + +config LPC54_SDMMC + bool "SD/MMC" + default n + select ARCH_HAVE_SDIO + depends on EXPERIMENTAL + +config LPC54_WWDT + bool "Windowing Watchdog Timer (WWDT)" + default n + depends on EXPERIMENTAL + +endmenu # LPC54xx Peripheral Selection + +menu "GPIO Interrupt Configuration" + +config LPC54_GPIOIRQ + bool "Support GPIO Interrupts" + default n + +config LPC54_GPIOIRQ_GROUPS + bool "Support GPIO Interrupt groups" + default n + depends on LPC54_GPIOIRQ && EXPERIMENTAL + +endmenu # GPIO Interrupt Configuration + +menu "EMC Configuration" +depends on LPC54_EMC + +config LPC54_EMC_STATIC + bool "EMC static memory support" + default n + +if LPC54_EMC_STATIC + +config LPC54_EMC_STATIC_CS0 + bool "SRAM on CS0" + default n + +if LPC54_EMC_STATIC_CS0 + +config LPC54_EMC_STATIC_CS0_OFFSET + hex "Heap offset" + default 0x0 + ---help--- + May be used to reserve memory at the beginning of SRAM for other + usage. + +config LPC54_EMC_STATIC_CS0_SIZE + hex "SRAM size" + default 0x0 + ---help--- + Total amount of RAM (after the heap offset) that will be added to + the heap. The may be zero, in which case none of the SRAM will be + added to heap, it may be less than the size of heap if memory of + reserved at the beginning or end of the SRAM form other purpose, or + it may be the full SRAM size to add the entire SRAM to the heap + +endif # LPC54_EMC_STATIC_CS0 + +config LPC54_EMC_STATIC_CS1 + bool "SRAM on CS1" + default n + +if LPC54_EMC_STATIC_CS1 + +config LPC54_EMC_STATIC_CS1_OFFSET + hex "Heap offset" + default 0x0 + ---help--- + May be used to reserve memory at the beginning of SRAM for other + usage. + +config LPC54_EMC_STATIC_CS1_SIZE + hex "Heap size" + default 0x0 + ---help--- + Total amount of RAM (after the heap offset) that will be added to + the heap. The may be zero, in which case none of the SRAM will be + added to heap, it may be less than the size of heap if memory of + reserved at the beginning or end of the SRAM form other purpose, or + it may be the full SRAM size to add the entire SRAM to the heap + +endif # LPC54_EMC_STATIC_CS1 + +config LPC54_EMC_STATIC_CS2 + bool "SRAM on CS2" + default n + +if LPC54_EMC_STATIC_CS2 + +config LPC54_EMC_STATIC_CS2_OFFSET + hex "Heap offset" + default 0x0 + ---help--- + May be used to reserve memory at the beginning of SRAM for other + usage. + +config LPC54_EMC_STATIC_CS2_SIZE + hex "Heap size" + default 0x0 + ---help--- + Total amount of RAM (after the heap offset) that will be added to + the heap. The may be zero, in which case none of the SRAM will be + added to heap, it may be less than the size of heap if memory of + reserved at the beginning or end of the SRAM form other purpose, or + it may be the full SRAM size to add the entire SRAM to the heap + +endif # LPC54_EMC_STATIC_CS2 + +config LPC54_EMC_STATIC_CS3 + bool "SRAM on CS3" + default n + +if LPC54_EMC_STATIC_CS3 + +config LPC54_EMC_STATIC_CS3_OFFSET + hex "Heap offset" + default 0x0 + ---help--- + May be used to reserve memory at the beginning of SRAM for other + usage. + +config LPC54_EMC_STATIC_CS3_SIZE + hex "Heap size" + default 0x0 + ---help--- + Total amount of RAM (after the heap offset) that will be added to + the heap. The may be zero, in which case none of the SRAM will be + added to heap, it may be less than the size of heap if memory of + reserved at the beginning or end of the SRAM form other purpose, or + it may be the full SRAM size to add the entire SRAM to the heap + +endif # LPC54_EMC_STATIC_CS3 +endif # LPC54_EMC_STATIC + +config LPC54_EMC_DYNAMIC + bool "EMC dynamic memory support" + default y + +if LPC54_EMC_DYNAMIC + +config LPC54_EMC_DYNAMIC_CS0 + bool "SDRAM on CS0" + default n + +if LPC54_EMC_DYNAMIC_CS0 + +config LPC54_EMC_DYNAMIC_CS0_OFFSET + hex "Heap offset" + default 0x0 + ---help--- + May be used to reserve memory at the beginning of SDRAM for other + usage. + +config LPC54_EMC_DYNAMIC_CS0_SIZE + hex "Heap size" + default 0x0 + ---help--- + Total amount of RAM (after the heap offset) that will be added to + the heap. The may be zero, in which case none of the SDRAM will be + added to heap, it may be less than the size of heap if memory of + reserved at the beginning or end of the SDRAM form other purpose, or + it may be the full SDRAM size to add the entire SDRAM to the heap + +endif # LPC54_EMC_DYNAMIC_CS0 + +config LPC54_EMC_DYNAMIC_CS1 + bool "SDRAM on CS1" + default n + +if LPC54_EMC_DYNAMIC_CS1 + +config LPC54_EMC_DYNAMIC_CS1_OFFSET + hex "Heap offset" + default 0x0 + ---help--- + May be used to reserve memory at the beginning of SDRAM for other + usage. + +config LPC54_EMC_DYNAMIC_CS1_SIZE + hex "Heap size" + default 0x0 + ---help--- + Total amount of RAM (after the heap offset) that will be added to + the heap. The may be zero, in which case none of the SDRAM will be + added to heap, it may be less than the size of heap if memory of + reserved at the beginning or end of the SDRAM form other purpose, or + it may be the full SDRAM size to add the entire SDRAM to the heap + +endif # LPC54_EMC_DYNAMIC_CS1 + +config LPC54_EMC_DYNAMIC_CS2 + bool "SDRAM on CS2" + default n + +if LPC54_EMC_DYNAMIC_CS2 + +config LPC54_EMC_DYNAMIC_CS2_OFFSET + hex "Heap offset" + default 0x0 + ---help--- + May be used to reserve memory at the beginning of SDRAM for other + usage. + +config LPC54_EMC_DYNAMIC_CS2_SIZE + hex "Heap size" + default 0x0 + ---help--- + Total amount of RAM (after the heap offset) that will be added to + the heap. The may be zero, in which case none of the SDRAM will be + added to heap, it may be less than the size of heap if memory of + reserved at the beginning or end of the SDRAM form other purpose, or + it may be the full SDRAM size to add the entire SDRAM to the heap + +endif # LPC54_EMC_DYNAMIC_CS2 + +config LPC54_EMC_DYNAMIC_CS3 + bool "SDRAM on CS3" + default n + +if LPC54_EMC_DYNAMIC_CS3 + +config LPC54_EMC_DYNAMIC_CS3_OFFSET + hex "Heap offset" + default 0x0 + ---help--- + May be used to reserve memory at the beginning of SDRAM for other + usage. + +config LPC54_EMC_DYNAMIC_CS3_SIZE + hex "Heap size" + default 0x0 + ---help--- + Total amount of RAM (after the heap offset) that will be added to + the heap. The may be zero, in which case none of the SDRAM will be + added to heap, it may be less than the size of heap if memory of + reserved at the beginning or end of the SDRAM form other purpose, or + it may be the full SDRAM size to add the entire SDRAM to the heap + +endif # LPC54_EMC_DYNAMIC_CS3 +endif # LPC54_EMC_DYNAMIC + +endmenu # EMC Configuration + +menu "Ethernet configuration" + depends on LPC54_ETHERNET + +config LPC54_ETH_PHYADDR + int "PHY address" + default 1 + ---help--- + The 5-bit address of the PHY on the board. Default: 1 + +config LPC54_ETH_MII + bool "Use MII interface" + default n + ---help--- + Support Ethernet MII interface. Default: Use RMII interface. + +config LPC54_ETH_MULTIQUEUE + bool "IEEE 802.1q VLAN AVBTP support" + default n + depends on EXPERIMENTAL + ---help--- + Enables software drivers for the special hardware support of + IEEE 802.1q VLAN Audio/Visual Bridge Types (AVBTP). In this + configuration two queues are available: One for normal traffic + and one dedicated to the AVBTP traffic. + +if LPC54_ETH_MULTIQUEUE + +config LPC54_ETH_BURSTLEN + int "DMA Tx burst length" + default 1 + range 1 256 + ---help--- + Transmit programmable burst length. These bits indicate the maximum + number of beats to be transferred in one DMA data transfer. This is + the maximum value that is used in a single block read or write. The + DMA always attempts to burst as specified in PBL each time it starts + a burst transfer on the application bus. You can program PBL with + any of the following values: 1, 2, 4, 8, 16, 32, 64, 128, or 256. + Any other value results in undefined behavior. + +config LPC54_ETH_TXRR + bool "Tx round robin" + default y + ---help--- + Selects round-robin Tx scheduling. The alternative is strict + priority scheduling. + +config LPC54_ETH_RXRR + bool "Rx round robin" + default y + ---help--- + Selects round-robin Rx scheduling. The alternative is strict + priority scheduling. + +config LPC54_ETH_DYNAMICMAP + bool "Dynamic Rx queue mapping" + default n + ---help--- + If selected, the received frame in in Rx Qn, n=0..1, maps to the DMA + channel m, m=0..1 related with the same MAC. Otherwise, static + mapping is used: The received fame in Rx Qn, n=0..1 maps directly + to DMA channel n. + +config LPC54_ETH_RXQ0WEIGHT + int "Rx queue 0 weight" + default 0 + range 0 7 + +config LPC54_ETH_RXQ1WEIGHT + int "Rx queue 1 weight" + default 0 + range 0 7 + +config LPC54_ETH_TXQ0WEIGHT + int "Tx queue 0 weight" + default 0 + range 0 2097151 + +config LPC54_ETH_TXQ1WEIGHT + int "Tx queue 1 weight" + default 0 + range 0 2097151 + +endif # LPC54_ETH_MULTIQUEUE + +config LPC54_ETH_TX_STRFWD + bool "Tx store and forward" + default n + ---help--- + Transmission starts when a full packet resides in the MTL Tx Queue. + This disables the default Tx threshold controls. + +config LPC54_ETH_RX_STRFWD + bool "Rx store and forward" + default n + ---help--- + Read packets from the Rx Queue only after the complete packet has + been written to it. By default, the Rx Queue operates in the + threshold (cut-through) mode. + +config LPC54_ETH_RX_PROMISCUOUS + bool "Enable Rx promiscuous mode" + default n + ---help--- + If selected, the address filter module accepts all incoming frames + regardless of its destination or source address. + +config LPC54_ETH_RX_BROADCAST + bool "Enable Rx broadcast" + default y + ---help--- + If selected, all received frames with a broadcast destination + address are accepted. + +config LPC54_ETH_RX_ALLMULTICAST + bool "Accept all multicast packets" + default y if NET_BROADCAST + default n if !NET_BROADCAST + ---help--- + If selected, all received frames with a multicast destination + address (first bit in the destination address field is '1') are + accepted. + + This feature will will be selected automatically if ICMPv6 or + IGMP are enabled. Unlike other Ethernet hardware, the LPC54xx + does not seem to support explicit Multicast address filtering + as needed for ICMPv6 and for IGMP. In these cases, I am simpl + accepting all multicast packets. + +config LPC54_ETH_FLOWCONTROL + bool "Enable flow control" + default n + ---help--- + Enable TX and RX flow control. + +config LPC54_ETH_TX_PAUSETIME + int "Tx pause time" + default 0 + range 0 65535 + depends on LPC54_ETH_FLOWCONTROL + ---help--- + Value to be used in the pause time field in the transmit control + frame. + +config LPC54_ETH_8023AS2K + bool "Enable 8023as support for 2K packets" + default n + +config LPC54_ETH_NRXDESC0 + int "Number of Rx DMA descriptors (ch0)" + default 8 + range 4 1024 + ---help--- + The number of Rx DMA descriptors to configure for Rx Channel 0. The + minimum is 4; the upper limit is 1024. + + NOTE: Each Rx descriptor will require a receive buffer at the size + of the configured MTU. + +config LPC54_ETH_NRXDESC1 + int "Number of Rx DMA descriptors (ch1)" + default 8 + range 4 1024 + depends on LPC54_ETH_MULTIQUEUE + ---help--- + The number of Rx DMA descriptors to configure for Rx Channel 1. The + minimum is 4; the upper limit is 1024. + + NOTE: Each Rx descriptor will require a receive buffer at the size + of the configured MTU. + +config LPC54_ETH_NTXDESC0 + int "Number of Tx DMA descriptors (ch0)" + default 8 + range 4 1024 + ---help--- + The number of Tx DMA descriptors to configure for Rx Channel 0. The + minimum is 4; the upper limit is 1024. + + NOTE: Each Rx descriptor will require a transmit buffer at the size + of the configured MTU. + +config LPC54_ETH_NTXDESC1 + int "Number of Tx DMA descriptors (ch1)" + default 8 + range 4 1024 + depends on LPC54_ETH_MULTIQUEUE + ---help--- + The number of Tx DMA descriptors to configure for Rx Channel 1. The + minimum is 4; the upper limit is 1024. + + NOTE: Each Rx descriptor will require a transmit buffer at the size + of the configured MTU. + +config LPC54_ETH_REGDEBUG + bool "Register level debug" + default n + depends on DEBUG_NET_INFO + ---help--- + Output detailed register-level Ethernet debug information. + +endmenu # Ethernet configuration + +menu "SD/MMC Configuration" + depends on LPC54_SDMMC + +config LPC54_SDMMC_PWRCTRL + bool "Power-enable pin" + default n + ---help--- + Select if the board supports a power-enable pin that must be selected + to provide power to the SD card. + +config LPC54_SDMMC_DMA + bool "Support DMA data transfers" + default y + select SDIO_DMA + ---help--- + Support DMA data transfers. + +config LPC54_SDMMC_REGDEBUG + bool "Register level debug" + default n + depends on DEBUG_MEMCARD_INFO + ---help--- + Output detailed register-level SD/MMC debug information. + +endmenu # SD/MMC Configuration + +menu "LCD Configuration" + depends on LPC54_LCD + +config LPC54_LCD_VRAMBASE + hex "Video RAM base address" + default 0xa0010000 + ---help--- + Base address of the video RAM frame buffer. The default is + (LPC54_EXTDRAM_CS0 + 0x00010000) + +config LPC54_LCD_USE_CLKIN + bool "Use optional input clock" + default n + +config LPC54_LCD_CLKIN_FREQUENCY + int "Input clock frequency" + default 0 + depends on LPC54_LCD_USE_CLKIN + +config LPC54_LCD_REFRESH_FREQ + int "LCD refesh rate (Hz)" + default 50 + ---help--- + LCD refesh rate (Hz) + +config LPC54_LCD_BACKLIGHT + bool "Enable backlight" + default y + ---help--- + Enable backlight support. If LPC54_LCD_BACKLIGHT is selected, then + the board-specific logic must provide this lpc54_backlight() + interface so that the LCD driver can turn the backlight on and off + as necessary. You should select this option and implement + lpc54_backlight() if your board provides GPIO control over the + backlight. This interface provides only ON/OFF control of the + backlight. If you want finer control over the backlight level (for + example, using PWM), then this interface would need to be extended. + +config LPC54_LCD_TFTPANEL + bool "TFT Panel" + default y + ---help--- + TFT Panel vs. STN display. STN display panels require algorithmic + pixel pattern generation to provide pseudo gray scaling on + monochrome displays, or color creation on color displays. TFT + display panels require the digital color value of each pixel to be + applied to the display data inputs. + +config LPC54_LCD_MONOCHROME + bool "Monochrome LCD" + default n + depends on !LPC54_LCD_TFTPANEL + ---help--- + STN LCD monochrome/color selection. Selects monochrome LCD. This + selection has no meaning for a TFT panel. + +choice + prompt "Bits per pixel" + default LPC54_LCD_BPP24 if LPC54_LCD_TFTPANEL + default LPC54_LCD_BPP16_565 if !LPC54_LCD_TFTPANEL + +config LPC54_LCD_BPP1 + bool "1 BPP" + depends on LPC54_LCD_MONOCHROME + +config LPC54_LCD_BPP2 + bool "2 BPP" + depends on LPC54_LCD_MONOCHROME + +config LPC54_LCD_BPP4 + bool "4 BPP" + depends on LPC54_LCD_MONOCHROME + +config LPC54_LCD_BPP8 + bool "8 BPP" + depends on LPC54_LCD_MONOCHROME + +config LPC54_LCD_BPP12_444 + bool "12 bpp, 4:4:4 mode" + depends on !LPC54_LCD_MONOCHROME + +config LPC54_LCD_BPP16 + bool "16 BPP" + depends on LPC54_LCD_MONOCHROME + +config LPC54_LCD_BPP16_565 + bool "16 BPP, 5:6:5 mode" + depends on !LPC54_LCD_MONOCHROME + +config LPC54_LCD_BPP24 + bool "24 BPP, 8:8:8 mode" + depends on LPC54_LCD_TFTPANEL + +endchoice + +config LPC54_LCD_BGR + bool "Blue-Green-Red color order" + default n + depends on !LPC54_LCD_MONOCHROME + ---help--- + This option selects BGR color order vs. default RGB + +config LPC54_LCD_BACKCOLOR + hex "Initial background color" + default 0x0 + ---help--- + Initial background color + +config LPC54_LCD_HWIDTH + int "Display width (pixels)" + default 480 + ---help--- + Horizontal width the display in pixels + +config LPC54_LCD_HPULSE + int "Horizontal pulse" + default 2 + +config LPC54_LCD_HFRONTPORCH + int "Horizontal front porch" + default 5 + +config LPC54_LCD_HBACKPORCH + int "Horizontal back porch" + default 40 + +config LPC54_LCD_VHEIGHT + int "Display height (rows)" + default 272 + ---help--- + Vertical height of the display in rows + +config LPC54_LCD_VPULSE + int "Vertical pulse" + default 2 + +config LPC54_LCD_VFRONTPORCH + int "Vertical front porch" + default 8 + +config LPC54_LCD_VBACKPORCH + int "Vertical back porch" + default 8 + +endmenu # LCD Configuration diff --git a/arch/arm/src/lpc54xx/Make.defs b/arch/arm/src/lpc54xx/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..4ba8c0d6f8f3d21e02bbf01d3157ac8ee755a4a5 --- /dev/null +++ b/arch/arm/src/lpc54xx/Make.defs @@ -0,0 +1,149 @@ +############################################################################ +# arch/arm/src/lpc54xx/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +HEAD_ASRC = + +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S +CMN_ASRCS += up_testset.S vfork.S + +CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c +CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c +CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c +CMN_CSRCS += up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c +CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c +CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_stackframe.c +CMN_CSRCS += up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c +CMN_CSRCS += up_svcall.c up_vfork.c + +ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) +CMN_ASRCS += up_lazyexception.S +else +CMN_ASRCS += up_exception.S +endif +CMN_CSRCS += up_vectors.c + +ifeq ($(CONFIG_ARCH_RAMVECTORS),y) +CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c +ifneq ($(CONFIG_DISABLE_SIGNALS),y) +CMN_CSRCS += up_signal_dispatch.c +CMN_UASRCS += up_signal_handler.S +endif +endif + +ifeq ($(CONFIG_STACK_COLORATION),y) +CMN_CSRCS += up_checkstack.c +endif + +ifeq ($(CONFIG_ARCH_FPU),y) +CMN_ASRCS += up_fpu.S +ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y) +CMN_CSRCS += up_copyarmstate.c +else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) +CMN_CSRCS += up_copyarmstate.c +endif +endif + +CHIP_ASRCS = +CHIP_CSRCS = lpc54_start.c lpc54_clockconfig.c lpc54_irq.c lpc54_clrpend.c +CHIP_CSRCS += lpc54_allocateheap.c lpc54_lowputc.c lpc54_gpio.c lpc54_reset.c + +ifneq ($(CONFIG_SCHED_TICKLESS),y) +CHIP_CSRCS += lpc54_timerisr.c +else +CHIP_CSRCS += lpc54_tickless.c +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += lpc54_userspace.c lpc54_mpuinit.c +endif + +ifeq ($(CONFIG_LPC54_DMA),y) +CHIP_CSRCS += lpc54_dma.c +endif + +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CHIP_CSRCS += lpc54_idle.c +endif + +ifeq ($(CONFIG_LPC54_GPIOIRQ),y) +CHIP_CSRCS += lpc54_gpioirq.c +endif + +ifeq ($(CONFIG_RTC),y) +CHIP_CSRCS += lpc54_rtc.c +ifeq ($(CONFIG_RTC_DRIVER),y) +CHIP_CSRCS += lpc54_rtc_lowerhalf.c +endif +endif + +ifeq ($(CONFIG_LPC54_WWDT),y) +CHIP_CSRCS += lpc54_wwdt.c +endif + +ifeq ($(CONFIG_LPC54_RNG),y) +CHIP_CSRCS += lpc54_rng.c +endif + +ifeq ($(CONFIG_LPC54_HAVE_USART),y) +CHIP_CSRCS += lpc54_serial.c +endif + +ifeq ($(CONFIG_LPC54_HAVE_I2C_MASTER),y) +CHIP_CSRCS += lpc54_i2c_master.c +endif + +ifeq ($(CONFIG_LPC54_HAVE_SPI_MASTER),y) +CHIP_CSRCS += lpc54_spi_master.c +endif + +ifeq ($(CONFIG_LPC54_EMC),y) +CHIP_CSRCS += lpc54_emc.c +endif + +ifeq ($(CONFIG_LPC54_ETHERNET),y) +CHIP_CSRCS += lpc54_ethernet.c +endif +ifeq ($(CONFIG_LPC54_LCD),y) +CHIP_CSRCS += lpc54_lcd.c +endif + +ifeq ($(CONFIG_LPC54_SDMMC),y) +CHIP_CSRCS += lpc54_sdmmc.c +endif + diff --git a/arch/arm/src/lpc54xx/chip.h b/arch/arm/src/lpc54xx/chip.h new file mode 100644 index 0000000000000000000000000000000000000000..2d906c01ab5fcf5a0c00ae866e3e1a77139044f6 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip.h @@ -0,0 +1,77 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/chip.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* Include the memory map and the chip definitions file. Other chip hardware files + * should then include this file for the proper setup. + */ + +#include +#include +#include "chip/lpc54_memorymap.h" + +/* If the common ARMv7-M vector handling logic is used, then it expects the + * following definition in this file that provides the number of supported external + * interrupts which, for this architecture, is provided in the arch/lpc54xx/chip.h + * header file. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS LPC54_IRQ_NEXTINT + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc546x_memorymap.h b/arch/arm/src/lpc54xx/chip/lpc546x_memorymap.h new file mode 100644 index 0000000000000000000000000000000000000000..c6878580f8c3f89f9caf69846de62483e8dc33b5 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc546x_memorymap.h @@ -0,0 +1,145 @@ +/**************************************************************************************************** + * arch/arm/src/lpc54xx/chip/lpc546x_memorymap.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC546X_MEMORYMAP_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC546X_MEMORYMAP_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Memory Map */ + +#define LPC54_FLASH_BASE 0x00000000 /* Flash memory (512 KB) */ +#define LPC54_BOOTROM_BASE 0x03000000 /* Boot ROM with flash services in a 64 KB space. */ +#define LPC54_SRAMX_BASE 0x04000000 /* I&D SRAM bank (32 KB) */ +#define LPC54_SPIFLASH_BASE 0x10000000 /* SPIFI memory mapped access space (128 MB). */ +#define LPC54_SRAM_BASE 0x20000000 /* SRAM banks (160 KB) */ +#define LPC54_SRAMBB_BASE 0x22000000 /* SRAM bit band alias addressing (32 MB) */ +#define LPC54_APB0_BASE 0x40000000 /* APB slave group 0 (128 KB) */ +#define LPC54_APB1_BASE 0x40020000 /* APB slave group 1 (128 KB) */ +#define LPC54_APB2_BASE 0x40040000 /* APB slave group 2 (128 KB) */ +#define LPC54_AHB_BASE 0x40080000 /* AHB peripherals (256 KB) */ +#define LPC54_USBSRAM_BASE 0x40100000 /* USB SRAM (8 KB) */ +#define LPC54_PERIPHBB_BASE 0x42000000 /* Peripheral bit band alias addressing (32 MB) */ +#define LPC54_SRAMCS0_BASE 0x80000000 /* Static memory chip select 0 (<=64MB) */ +#define LPC54_SRAMCS1_BASE 0x88000000 /* Static memory chip select 1 (<=64MB) */ +#define LPC54_SRAMCS2_BASE 0x90000000 /* Static memory chip select 2 (<=64MB) */ +#define LPC54_SRAMCS3_BASE 0x98000000 /* Static memory chip select 3 (<=64MB) */ +#define LPC54_DRAMCS0_BASE 0xa0000000 /* Dynamic memory chip select 0 (<=256MB) */ +#define LPC54_DRAMCS1_BASE 0xa8000000 /* Dynamic memory chip select 1 (<=256MB) */ +#define LPC54_DRAMCS2_BASE 0xb0000000 /* Dynamic memory chip select 2 (<=256MB) */ +#define LPC54_DRAMCS3_BASE 0xb8000000 /* Dynamic memory chip select 3 (<=256MB) */ +#define LPC54_CORTEXM4_BASE 0xe0000000 /* Cortex-M4 Private Peripheral Bus */ + +/* ROM Driver Table */ + +#define LPC54_ROM_DRIVERTAB 0x03000200 /* Beginning of the ROM driver table */ + +/* AHB Peripherals */ + +#define LPC54_SPIFI_BASE 0x40080000 /* SPIFI registers */ +#define LPC54_EMC_BASE 0x40081000 /* EMC registers */ +#define LPC54_DMA_BASE 0x40082000 /* DMA registers */ +#define LPC54_LCD_BASE 0x40083000 /* LCD registers */ +#define LPC54_FSUSB_BASE 0x40084000 /* FS USB device registers */ +#define LPC54_SCTPWM_BASE 0x40085000 /* SC Timer / PWM */ +#define LPC54_FLEXCOMM0_BASE 0x40086000 /* Flexcomm 0 */ +#define LPC54_FLEXCOMM1_BASE 0x40087000 /* Flexcomm 1 */ +#define LPC54_FLEXCOMM2_BASE 0x40088000 /* Flexcomm 2 */ +#define LPC54_FLEXCOMM3_BASE 0x40089000 /* Flexcomm 3 */ +#define LPC54_FLEXCOMM4_BASE 0x4008a000 /* Flexcomm 4 */ +#define LPC54_GPIO_BASE 0x4008c000 /* High Speed GPIO */ +#define LPC54_DMIC_BASE 0x40090000 /* D-Mic interface */ +#define LPC54_ETHERNET_BASE 0x40092000 /* Ethernet */ +#define LPC54_HSUSB_BASE 0x40094000 /* HS USB device */ +#define LPC54_CRC_BASE 0x40095000 /* CRC engine */ +#define LPC54_FLEXCOMM5_BASE 0x40096000 /* Flexcomm 5 */ +#define LPC54_FLEXCOMM6_BASE 0x40097000 /* Flexcomm 6 */ +#define LPC54_FLEXCOMM7_BASE 0x40098000 /* Flexcomm 7 */ +#define LPC54_FLEXCOMM8_BASE 0x40099000 /* Flexcomm 8 */ +#define LPC54_FLEXCOMM9_BASE 0x4009a000 /* Flexcomm 9 */ +#define LPC54_SDMMC_BASE 0x4009b000 /* SD/MMC */ +#define LPC54_ISPAP_BASE 0x4009c000 /* ISP-AP interface */ +#define LPC54_CAN0_BASE 0x4009d000 /* CAN 0 */ +#define LPC54_CAN1_BASE 0x4009e000 /* CAN 1 */ +#define LPC54_ADC_BASE 0x400a0000 /* ADC */ +#define LPC54_SHA_BASE 0x400a1000 /* SHA registers */ +#define LPC54_FSUSBHOST_BASE 0x400a2000 /* FS USB host registers */ +#define LPC54_HSUSBHOST_BASE 0x400a3000 /* HS USB host registers */ +#define LPC54_USBSRAM_BASE 0x40100000 /* USB SRAM (8 kB) */ +#define LPC54_EPROM_BASE 0x40108000 /* EPROM (16 kB) */ + +/* APB Bridge 0 */ + +#define LPC54_SYSCON_BASE 0x40000000 /* Syscon */ +#define LPC54_IOCON_BASE 0x40001000 /* IOCON */ +#define LPC54_GINT0_BASE 0x40002000 /* GINT0 */ +#define LPC54_GINT1_BASE 0x40003000 /* GINT1 */ +#define LPC54_PINT_BASE 0x40004000 /* Pin Interrupts (PINT) */ +#define LPC54_MUX_BASE 0x40005000 /* Input muxes */ +#define LPC54_CTIMER0_BASE 0x40008000 /* CTIMER0 */ +#define LPC54_CTIMER1_BASE 0x40009000 /* CTIMER1 */ +#define LPC54_WWDT_BASE 0x4000c000 /* WDT */ +#define LPC54_MRT_BASE 0x4000d000 /* MRT */ +#define LPC54_MTICK_BASE 0x4000e000 /* Micro-Tick */ +#define LPC54_EEPROMC_BASE 0x40014000 /* EEPROM controller */ +#define LPC54_OTP_BASE 0x40016000 /* OTP controller */ + +/* APB Bridge 1 */ + +#define LPC54_OSYSCON_BASE 0x40020000 /* Other system registers */ +#define LPC54_CTIMER2_BASE 0x40028000 /* CTIMER2 */ +#define LPC54_RTC_BASE 0x4002c000 /* RTC */ +#define LPC54_RIT_BASE 0x4002d000 /* RIT */ +#define LPC54_FLASHC_BASE 0x40034000 /* Flash controller */ +#define LPC54_SMARCARD0_BASE 0x40036000 /* Smart card 0 */ +#define LPC54_SMARCARD1_BASE 0x40037000 /* Smart card 1 */ +#define LPC54_RNG_BASE 0x4003a000 /* RNG */ + +/* Asynchronous APB bridge */ + +#define LPC54_ASYSCON_BASE 0x40040000 /* Asynchronous Syscon */ +#define LPC54_CTIMER3_BASE 0x40048000 /* CTIMER3 */ +#define LPC54_CTIMER4_BASE 0x40049000 /* CTIMER4 */ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC546X_MEMORYMAP_H */ + diff --git a/arch/arm/src/lpc54xx/chip/lpc546x_pinmux.h b/arch/arm/src/lpc54xx/chip/lpc546x_pinmux.h new file mode 100644 index 0000000000000000000000000000000000000000..c4e6d39b57c95d53c135d12d22dabb35b8aec338 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc546x_pinmux.h @@ -0,0 +1,907 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/chip/lpc546x_pinmux.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC546X_PINMUX_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC546X_PINMUX_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Alternate Pin Functions. + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. + * Drivers, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. For example, if + * CAN0 RX connects vis P0.4 on some board, then the following definitions should + * appear in the board.h header file for that board: + * + * #define GPIO_CAN0_RD GPIO_CAN0_RD_1 + * + * The driver will then automatically configre P0.4 as the CAN0 RX pin. + * + * All pins are Type D unless otherwise noted. + */ + +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as frequency, + * open-drain/push-pull, and pull-up/down! Just the basics are defined for most + * pins in this file. + */ + + /* Analog-to-Digital Conversion (ADC) */ + +#define GPIO_ADC0_0 (GPIO_INPUT | GPIO_MODE_ANALOG | GPIO_PORT0 | GPIO_PIN10) /* Type A */ +#define GPIO_ADC0_1 (GPIO_INPUT | GPIO_MODE_ANALOG | GPIO_PORT0 | GPIO_PIN11) /* Type A */ +#define GPIO_ADC0_2 (GPIO_INPUT | GPIO_MODE_ANALOG | GPIO_PORT0 | GPIO_PIN12) /* Type A */ +#define GPIO_ADC0_3 (GPIO_INPUT | GPIO_MODE_ANALOG | GPIO_PORT0 | GPIO_PIN15) /* Type A */ +#define GPIO_ADC0_4 (GPIO_INPUT | GPIO_MODE_ANALOG | GPIO_PORT0 | GPIO_PIN16) /* Type A */ +#define GPIO_ADC0_5 (GPIO_INPUT | GPIO_MODE_ANALOG | GPIO_PORT0 | GPIO_PIN31) /* Type A */ +#define GPIO_ADC0_6 (GPIO_INPUT | GPIO_MODE_ANALOG | GPIO_PORT1 | GPIO_PIN0) /* Type A */ +#define GPIO_ADC0_7 (GPIO_INPUT | GPIO_MODE_ANALOG | GPIO_PORT2 | GPIO_PIN0) /* Type A */ +#define GPIO_ADC0_8 (GPIO_INPUT | GPIO_MODE_ANALOG | GPIO_PORT2 | GPIO_PIN1) /* Type A */ +#define GPIO_ADC0_9 (GPIO_INPUT | GPIO_MODE_ANALOG | GPIO_PORT3 | GPIO_PIN21) /* Type A */ +#define GPIO_ADC0_10 (GPIO_INPUT | GPIO_MODE_ANALOG | GPIO_PORT3 | GPIO_PIN22) /* Type A */ +#define GPIO_ADC0_11 (GPIO_INPUT | GPIO_MODE_ANALOG | GPIO_PORT0 | GPIO_PIN23) /* Type A */ + +/* Controller Area Network (CAN) */ + +#define GPIO_CAN0_RD_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_CAN0_RD_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_CAN0_RD_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN19) +#define GPIO_CAN0_TD_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_CAN0_TD_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_CAN0_TD_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN18) + +#define GPIO_CAN1_RD_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_CAN1_RD_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN18) +#define GPIO_CAN1_RD_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN18) +#define GPIO_CAN1_TD_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_CAN1_TD_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN17) +#define GPIO_CAN1_TD_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN17) + +/* CLKOUT */ + +#define GPIO_CLKOUT_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN16) /* Type A */ +#define GPIO_CLKOUT_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN26) +#define GPIO_CLKOUT_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN20) +#define GPIO_CLKOUT_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN27) +#define GPIO_CLKOUT_5 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN29) +#define GPIO_CLKOUT_6 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN12) + +/* Standard counter/timer (CTIMER) */ + +#define GPIO_CTIMER0_CAP0_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_CTIMER0_CAP0_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN13) /* Type D+I */ +#define GPIO_CTIMER0_CAP0_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_CTIMER0_CAP1_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_CTIMER0_CAP1_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN14) /* Type D+I */ +#define GPIO_CTIMER0_CAP1_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN7) +#define GPIO_CTIMER0_CAP2_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN0) /* Type A */ +#define GPIO_CTIMER0_CAP2_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN28) +#define GPIO_CTIMER0_CAP2_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN9) +#define GPIO_CTIMER0_CAP3_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_CTIMER0_CAP3_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN26) +#define GPIO_CTIMER0_CAP3_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN3) +#define GPIO_CTIMER0_MAT0_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_CTIMER0_MAT0_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN30) +#define GPIO_CTIMER0_MAT0_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_CTIMER0_MAT1_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN3) +#define GPIO_CTIMER0_MAT1_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN31) /* Type A */ +#define GPIO_CTIMER0_MAT1_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_CTIMER0_MAT2_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN19) +#define GPIO_CTIMER0_MAT2_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN31) +#define GPIO_CTIMER0_MAT2_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_CTIMER0_MAT3_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_CTIMER0_MAT3_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN27) +#define GPIO_CTIMER0_MAT3_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN15) + +#define GPIO_CTIMER1_CAP0_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN16) /* Type A */ +#define GPIO_CTIMER1_CAP0_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_CTIMER1_CAP0_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN0) /* Type A */ +#define GPIO_CTIMER1_CAP0_4 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN27) +#define GPIO_CTIMER1_CAP1_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN11) +#define GPIO_CTIMER1_CAP1_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN17) +#define GPIO_CTIMER1_CAP1_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_CTIMER1_CAP2_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN13) +#define GPIO_CTIMER1_CAP2_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN17) +#define GPIO_CTIMER1_CAP2_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_CTIMER1_CAP3_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN15) +#define GPIO_CTIMER1_CAP3_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN18) +#define GPIO_CTIMER1_CAP3_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN30) +#define GPIO_CTIMER1_MAT0_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN18) +#define GPIO_CTIMER1_MAT0_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN10) +#define GPIO_CTIMER1_MAT0_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN1) /* Type A */ +#define GPIO_CTIMER1_MAT0_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN0) +#define GPIO_CTIMER1_MAT0_5 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN23) +#define GPIO_CTIMER1_MAT1_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN20) +#define GPIO_CTIMER1_MAT1_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN12) +#define GPIO_CTIMER1_MAT1_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_CTIMER1_MAT1_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN1) +#define GPIO_CTIMER1_MAT1_5 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN24) +#define GPIO_CTIMER1_MAT2_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN23) /* Type A */ +#define GPIO_CTIMER1_MAT2_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN14) +#define GPIO_CTIMER1_MAT2_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_CTIMER1_MAT2_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN2) +#define GPIO_CTIMER1_MAT2_5 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN25) +#define GPIO_CTIMER1_MAT3_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN16) +#define GPIO_CTIMER1_MAT3_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN16) +#define GPIO_CTIMER1_MAT3_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN22) +#define GPIO_CTIMER1_MAT3_4 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN26) + +#define GPIO_CTIMER2_CAP0_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN24) +#define GPIO_CTIMER2_CAP0_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN22) +#define GPIO_CTIMER2_CAP1_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN25) +#define GPIO_CTIMER2_CAP1_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN26) +#define GPIO_CTIMER2_CAP2_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN10) /* Type A */ +#define GPIO_CTIMER2_CAP2_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN28) +#define GPIO_CTIMER2_CAP3_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN28) +#define GPIO_CTIMER2_CAP3_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN29) +#define GPIO_CTIMER2_MAT0_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN10) /* Type A */ +#define GPIO_CTIMER2_MAT0_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_CTIMER2_MAT0_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_CTIMER2_MAT1_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_CTIMER2_MAT1_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_CTIMER2_MAT1_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_CTIMER2_MAT2_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN11) /* Type A */ +#define GPIO_CTIMER2_MAT2_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_CTIMER2_MAT2_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN30) +#define GPIO_CTIMER2_MAT3_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN29) +#define GPIO_CTIMER2_MAT3_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_CTIMER2_MAT3_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN21) + +#define GPIO_CTIMER3_CAP0_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_CTIMER3_CAP0_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN12) +#define GPIO_CTIMER3_CAP0_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN2) +#define GPIO_CTIMER3_CAP1_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_CTIMER3_CAP1_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN13) +#define GPIO_CTIMER3_CAP1_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN3) +#define GPIO_CTIMER3_CAP2_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN26) +#define GPIO_CTIMER3_CAP2_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN20) +#define GPIO_CTIMER3_CAP2_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_CTIMER3_CAP3_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN20) +#define GPIO_CTIMER3_CAP3_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN22) +#define GPIO_CTIMER3_CAP3_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN5) +#define GPIO_CTIMER3_MAT0_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_CTIMER3_MAT0_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN10) +#define GPIO_CTIMER3_MAT0_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN30) +#define GPIO_CTIMER3_MAT0_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN18) +#define GPIO_CTIMER3_MAT1_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN19) +#define GPIO_CTIMER3_MAT1_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN14) +#define GPIO_CTIMER3_MAT1_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN31) +#define GPIO_CTIMER3_MAT1_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN19) +#define GPIO_CTIMER3_MAT2_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN27) +#define GPIO_CTIMER3_MAT2_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN21) +#define GPIO_CTIMER3_MAT2_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_CTIMER3_MAT2_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN20) +#define GPIO_CTIMER3_MAT3_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN21) +#define GPIO_CTIMER3_MAT3_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN23) /* Type A */ +#define GPIO_CTIMER3_MAT3_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_CTIMER3_MAT3_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN21) + +#define GPIO_CTIMER4_CAP0_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN24) /* Type D+I */ +#define GPIO_CTIMER4_CAP0_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN15) /* Type A */ +#define GPIO_CTIMER4_CAP0_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN20) +#define GPIO_CTIMER4_CAP1_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN0) +#define GPIO_CTIMER4_CAP1_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN4) +#define GPIO_CTIMER4_CAP2_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN25) +#define GPIO_CTIMER4_CAP2_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN7) +#define GPIO_CTIMER4_CAP2_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN19) +#define GPIO_CTIMER4_CAP3_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN7) +#define GPIO_CTIMER4_CAP3_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN8) +#define GPIO_CTIMER4_CAP3_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN20) +#define GPIO_CTIMER4_MAT0_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN13) +#define GPIO_CTIMER4_MAT0_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_CTIMER4_MAT0_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN18) +#define GPIO_CTIMER4_MAT1_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN14) +#define GPIO_CTIMER4_MAT1_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN19) +#define GPIO_CTIMER4_MAT1_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN5) +#define GPIO_CTIMER4_MAT2_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN15) +#define GPIO_CTIMER4_MAT2_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN31) +#define GPIO_CTIMER4_MAT2_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN6) +#define GPIO_CTIMER4_MAT3_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN16) +#define GPIO_CTIMER4_MAT3_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN21) /* Type A */ +#define GPIO_CTIMER4_MAT3_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN5) + +/* External Memory Controller (EMC) */ + +#define GPIO_EMC_A0 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN18) +#define GPIO_EMC_A1 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN19) +#define GPIO_EMC_A2 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN20) +#define GPIO_EMC_A3 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN21) +#define GPIO_EMC_A4 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_EMC_A5 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_EMC_A6 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_EMC_A7 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_EMC_A8 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN26) +#define GPIO_EMC_A9 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN27) +#define GPIO_EMC_A10 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN16) +#define GPIO_EMC_A11 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN23) +#define GPIO_EMC_A12 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN24) +#define GPIO_EMC_A13 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN25) +#define GPIO_EMC_A14 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT3 | GPIO_PIN25) +#define GPIO_EMC_A15 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT3 | GPIO_PIN26) +#define GPIO_EMC_A16 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT3 | GPIO_PIN27) +#define GPIO_EMC_A17 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT3 | GPIO_PIN28) +#define GPIO_EMC_A18 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT3 | GPIO_PIN29) +#define GPIO_EMC_A19 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT3 | GPIO_PIN30) +#define GPIO_EMC_A20 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT3 | GPIO_PIN31) +#define GPIO_EMC_A21 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT5 | GPIO_PIN5) +#define GPIO_EMC_A22 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT5 | GPIO_PIN6) +#define GPIO_EMC_A23 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT5 | GPIO_PIN7) +#define GPIO_EMC_A24 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT5 | GPIO_PIN8) +#define GPIO_EMC_A25 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT5 | GPIO_PIN9) +#define GPIO_EMC_BLSN0 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN17) +#define GPIO_EMC_BLSN1 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN18) +#define GPIO_EMC_BLSN2 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN17) +#define GPIO_EMC_BLSN3 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN18) +#define GPIO_EMC_CASN (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_EMC_CKE0 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN15) +#define GPIO_EMC_CKE1 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_EMC_CKE2 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN5) +#define GPIO_EMC_CKE3 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN6) +#define GPIO_EMC_CLK0 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN11) +#define GPIO_EMC_CLK1 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT3 | GPIO_PIN12) +#define GPIO_EMC_CSN0 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT0 | GPIO_PIN16) /* Type A */ +#define GPIO_EMC_CSN1 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN0) +#define GPIO_EMC_CSN2 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN1) +#define GPIO_EMC_CSN3 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN2) +#define GPIO_EMC_D0 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_EMC_D1 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN3) +#define GPIO_EMC_D2 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_EMC_D3 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_EMC_D4 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_EMC_D5 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_EMC_D6 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_EMC_D7 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_EMC_D8 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN19) +#define GPIO_EMC_D9 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN20) +#define GPIO_EMC_D10 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN21) +#define GPIO_EMC_D11 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_EMC_D12 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN28) +#define GPIO_EMC_D13 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_EMC_D14 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN30) +#define GPIO_EMC_D15 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN31) +#define GPIO_EMC_D16 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN21) +#define GPIO_EMC_D17 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN22) +#define GPIO_EMC_D18 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN23) +#define GPIO_EMC_D19 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN24) +#define GPIO_EMC_D20 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN25) +#define GPIO_EMC_D21 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN26) +#define GPIO_EMC_D22 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN27) +#define GPIO_EMC_D23 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_EMC_D24 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_EMC_D25 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN30) +#define GPIO_EMC_D26 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN31) +#define GPIO_EMC_D27 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_EMC_D28 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_EMC_D29 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT5 | GPIO_PIN2) +#define GPIO_EMC_D30 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT5 | GPIO_PIN3) +#define GPIO_EMC_D31 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_EMC_DQM0 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN13) +#define GPIO_EMC_DQM1 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN14) +#define GPIO_EMC_DQM2 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN19) +#define GPIO_EMC_DQM3 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN20) +#define GPIO_EMC_DYCSN0 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN12) +#define GPIO_EMC_DYCSN1 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT3 | GPIO_PIN10) +#define GPIO_EMC_DYCSN2 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN3) +#define GPIO_EMC_DYCSN3 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT4 | GPIO_PIN4) +#define GPIO_EMC_FBCK (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT3 | GPIO_PIN13) +#define GPIO_EMC_OEN (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT0 | GPIO_PIN17) +#define GPIO_EMC_RASN (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_SLEW_FAST | GPIO_PORT1 | GPIO_PIN10) +#define GPIO_EMC_WEN (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT0 | GPIO_PIN15) /* Type A */ + +/* Ethernet (ENET) */ + +#define GPIO_ENET_COL_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN7) +#define GPIO_ENET_COL_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN2) +#define GPIO_ENET_CRS_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_ENET_CRS_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_ENET_MDC_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN16) +#define GPIO_ENET_MDC_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN15) +#define GPIO_ENET_MDC_3 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN3) +#define GPIO_ENET_MDC_4 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_ENET_MDIO_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN17) +#define GPIO_ENET_MDIO_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN16) +#define GPIO_ENET_MDIO_3 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_ENET_MDIO_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN23) +#define GPIO_ENET_MDIO_5 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_ENET_RX_CLK_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN15) +#define GPIO_ENET_RX_CLK_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN14) +#define GPIO_ENET_RX_CLK_3 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN31) +#define GPIO_ENET_RX_CLK_4 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_ENET_RX_DV_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN14) +#define GPIO_ENET_RX_DV_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN10) +#define GPIO_ENET_RX_DV_3 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_ENET_RX_DV_4 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_ENET_RX_ER_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN10) +#define GPIO_ENET_RX_ER_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_ENET_RXD0_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN12) +#define GPIO_ENET_RXD0_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN11) +#define GPIO_ENET_RXD0_3 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN23) +#define GPIO_ENET_RXD0_4 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN13) /* Type D+I */ +#define GPIO_ENET_RXD1_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN13) +#define GPIO_ENET_RXD1_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN12) +#define GPIO_ENET_RXD1_3 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN24) +#define GPIO_ENET_RXD1_4 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN14) /* Type D+I */ +#define GPIO_ENET_RXD2_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_ENET_RXD2_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN25) +#define GPIO_ENET_RXD3_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_ENET_RXD3_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN26) +#define GPIO_ENET_TX_CLK_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_ENET_TX_CLK_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN30) +#define GPIO_ENET_TX_EN_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN11) +#define GPIO_ENET_TX_EN_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN13) +#define GPIO_ENET_TX_EN_3 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN27) +#define GPIO_ENET_TX_EN_4 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN15) /* Type A */ +#define GPIO_ENET_TX_ER_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_ENET_TX_ER_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_ENET_TXD0_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_ENET_TXD0_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN19) +#define GPIO_ENET_TXD0_3 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN8) +#define GPIO_ENET_TXD0_4 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN16) /* Type A */ +#define GPIO_ENET_TXD1_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN10) +#define GPIO_ENET_TXD1_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN20) +#define GPIO_ENET_TXD1_3 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN9) +#define GPIO_ENET_TXD1_4 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN17) +#define GPIO_ENET_TXD2_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_ENET_TXD2_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN21) +#define GPIO_ENET_TXD3_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_ENET_TXD3_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN22) + +/* Flexcomm (FC) + * + * Pins used for I2C should add GPIO_FILTER_OFF in your board. h head file. + * For standard mode I2C, add GPIO_I2C_FILTER_OFF + * For fast speed mode plaseI2C, also add GPIO_I2CDRIVE_HIGH + * For high speed slave add both GPIO_I2C_FILTER_OFF and GPIO_I2CDRIVE_HIGH + */ + +#define GPIO_FC0_CTS_SDA_SSEL0_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN31) /* Type A */ +#define GPIO_FC0_CTS_SDA_SSEL0_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_FC0_CTS_SDA_SSEL0_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN5) +#define GPIO_FC0_RTS_SCL_SSEL1_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN0) /* Type A */ +#define GPIO_FC0_RTS_SCL_SSEL1_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_FC0_RTS_SCL_SSEL1_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN4) +#define GPIO_FC0_RXD_SDA_MOSI_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN24) +#define GPIO_FC0_RXD_SDA_MOSI_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN29) +#define GPIO_FC0_RXD_SDA_MOSI_3 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_FC0_RXD_SDA_MOSI_4 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN0) /* Type A */ +#define GPIO_FC0_SCK_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN28) +#define GPIO_FC0_SCK_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_FC0_SCK_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN11) +#define GPIO_FC0_TXD_SCL_MISO_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN25) +#define GPIO_FC0_TXD_SCL_MISO_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN30) +#define GPIO_FC0_TXD_SCL_MISO_3 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_FC0_TXD_SCL_MISO_4 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN1) /* Type A */ + +#define GPIO_FC1_CTS_SDA_SSEL0_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN13) /* Type D+I */ +#define GPIO_FC1_CTS_SDA_SSEL0_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_FC1_RTS_SCL_SSEL1_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN14) /* Type D+I */ +#define GPIO_FC1_RTS_SCL_SSEL1_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_FC1_RTS_SCL_SSEL1_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN30) +#define GPIO_FC1_RXD_SDA_MOSI_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN10) +#define GPIO_FC1_RXD_SDA_MOSI_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_FC1_RXD_SDA_MOSI_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_FC1_SCK_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_FC1_SCK_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN11) +#define GPIO_FC1_SCK_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_FC1_SCK_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN27) +#define GPIO_FC1_TXD_SCL_MISO_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN11) +#define GPIO_FC1_TXD_SCL_MISO_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_FC1_TXD_SCL_MISO_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN10) /* Type A */ +#define GPIO_FC1_TXD_SCL_MISO_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN29) + +#define GPIO_FC2_CTS_SDA_SSEL0_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN26) +#define GPIO_FC2_CTS_SDA_SSEL0_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN23) /* Type D+I */ +#define GPIO_FC2_CTS_SDA_SSEL0_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN11) +#define GPIO_FC2_CTS_SDA_SSEL0_4 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN23) +#define GPIO_FC2_RTS_SCL_SSEL1_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN27) +#define GPIO_FC2_RTS_SCL_SSEL1_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN24) /* Type D+I */ +#define GPIO_FC2_RTS_SCL_SSEL1_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN12) +#define GPIO_FC2_RTS_SCL_SSEL1_4 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN22) +#define GPIO_FC2_RXD_SDA_MOSI_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN26) +#define GPIO_FC2_RXD_SDA_MOSI_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN24) +#define GPIO_FC2_RXD_SDA_MOSI_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN9) +#define GPIO_FC2_RXD_SDA_MOSI_4 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN20) +#define GPIO_FC2_SCK_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN23) +#define GPIO_FC2_SCK_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN8) +#define GPIO_FC2_SCK_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN19) +#define GPIO_FC2_TXD_SCL_MISO_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN27) +#define GPIO_FC2_TXD_SCL_MISO_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN25) +#define GPIO_FC2_TXD_SCL_MISO_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN10) +#define GPIO_FC2_TXD_SCL_MISO_4 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN21) + +#define GPIO_FC3_CTS_SDA_SSEL0_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN20) +#define GPIO_FC3_CTS_SDA_SSEL0_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_FC3_CTS_SDA_SSEL0_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN21) +#define GPIO_FC3_RTS_SCL_SSEL1_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN21) +#define GPIO_FC3_RTS_SCL_SSEL1_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_FC3_RTS_SCL_SSEL1_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN20) +#define GPIO_FC3_RXD_SDA_MOSI_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN3) +#define GPIO_FC3_RXD_SDA_MOSI_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_FC3_RXD_SDA_MOSI_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN18) +#define GPIO_FC3_SCK_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_FC3_SCK_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_FC3_SCK_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN26) +#define GPIO_FC3_SSEL2_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_FC3_SSEL2_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN27) +#define GPIO_FC3_SSEL2_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN23) +#define GPIO_FC3_SSEL3_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_FC3_SSEL3_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_FC3_SSEL3_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN24) +#define GPIO_FC3_TXD_SCL_MISO_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN12) /* Type A */ +#define GPIO_FC3_TXD_SCL_MISO_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_FC3_TXD_SCL_MISO_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN19) + +#define GPIO_FC4_CTS_SDA_SSEL0_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN18) +#define GPIO_FC4_CTS_SDA_SSEL0_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN28) +#define GPIO_FC4_CTS_SDA_SSEL0_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN2) +#define GPIO_FC4_CTS_SDA_SSEL0_4 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_FC4_RTS_SCL_SSEL1_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN19) +#define GPIO_FC4_RTS_SCL_SSEL1_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN29) +#define GPIO_FC4_RTS_SCL_SSEL1_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN3) +#define GPIO_FC4_RTS_SCL_SSEL1_4 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN15) +#define GPIO_FC4_RXD_SDA_MOSI_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_FC4_RXD_SDA_MOSI_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN26) +#define GPIO_FC4_RXD_SDA_MOSI_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_FC4_RXD_SDA_MOSI_4 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN21) +#define GPIO_FC4_SCK_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_FC4_SCK_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN25) +#define GPIO_FC4_SCK_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN31) +#define GPIO_FC4_SCK_4 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN19) +#define GPIO_FC4_SSEL2_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN17) +#define GPIO_FC4_SSEL2_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN30) +#define GPIO_FC4_SSEL2_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_FC4_SSEL2_4 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_FC4_SSEL3_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN4) +#define GPIO_FC4_SSEL3_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN5) +#define GPIO_FC4_SSEL3_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_FC4_TXD_SCL_MISO_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN16) /* Type A */ +#define GPIO_FC4_TXD_SCL_MISO_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN27) +#define GPIO_FC4_TXD_SCL_MISO_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_FC4_TXD_SCL_MISO_4 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN20) + +#define GPIO_FC5_CTS_SDA_SSEL0_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN9) +#define GPIO_FC5_CTS_SDA_SSEL0_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN14) +#define GPIO_FC5_CTS_SDA_SSEL0_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_FC5_RTS_SCL_SSEL1_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN10) +#define GPIO_FC5_RTS_SCL_SSEL1_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN15) +#define GPIO_FC5_RTS_SCL_SSEL1_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_FC5_RXD_SDA_MOSI_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_FC5_RXD_SDA_MOSI_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN7) +#define GPIO_FC5_RXD_SDA_MOSI_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_FC5_SCK_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_FC5_SCK_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN6) +#define GPIO_FC5_SCK_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN11) +#define GPIO_FC5_TXD_SCL_MISO_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_FC5_TXD_SCL_MISO_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN8) +#define GPIO_FC5_TXD_SCL_MISO_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_FC6_CTS_SDA_SSEL0_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN15) /* Type A */ + +#define GPIO_FC6_CTS_SDA_SSEL0_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN0) +#define GPIO_FC6_RXD_SDA_MOSI_DATA_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN11) /* Type A */ +#define GPIO_FC6_RXD_SDA_MOSI_DATA_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN13) +#define GPIO_FC6_RXD_SDA_MOSI_DATA_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN2) +#define GPIO_FC6_SCK_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN10) /* Type A */ +#define GPIO_FC6_SCK_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN12) +#define GPIO_FC6_SCK_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN1) +#define GPIO_FC6_TXD_SCL_MISO (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN22) +#define GPIO_FC6_TXD_SCL_MISO_WS_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN16) +#define GPIO_FC6_TXD_SCL_MISO_WS_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN3) + +#define GPIO_FC7_CTS_SDA_SSEL0_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN21) +#define GPIO_FC7_CTS_SDA_SSEL0_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN28) +#define GPIO_FC7_CTS_SDA_SSEL0_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN25) +#define GPIO_FC7_RTS_SCL_SSEL1_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN20) +#define GPIO_FC7_RTS_SCL_SSEL1_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN29) +#define GPIO_FC7_RTS_SCL_SSEL1_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN24) +#define GPIO_FC7_RXD_SDA_MOSI (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN20) +#define GPIO_FC7_RXD_SDA_MOSI_DATA_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_FC7_RXD_SDA_MOSI_DATA_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN19) +#define GPIO_FC7_SCK_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN28) +#define GPIO_FC7_SCK_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN18) +#define GPIO_FC7_SCK_3 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN21) +#define GPIO_FC7_TXD_SCL_MISO (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN19) +#define GPIO_FC7_TXD_SCL_MISO_WS_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN30) +#define GPIO_FC7_TXD_SCL_MISO_WS_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN20) + +#define GPIO_FC8_CTS_SDA_SSEL0_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN18) +#define GPIO_FC8_CTS_SDA_SSEL0_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN4) +#define GPIO_FC8_CTS_SDA_SSEL0_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN31) +#define GPIO_FC8_RTS_SCL_SSEL1_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_FC8_RTS_SCL_SSEL1_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN19) +#define GPIO_FC8_RTS_SCL_SSEL1_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN5) +#define GPIO_FC8_RXD_SDA_MOSI_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN16) +#define GPIO_FC8_RXD_SDA_MOSI_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN17) +#define GPIO_FC8_RXD_SDA_MOSI_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN17) +#define GPIO_FC8_SCK_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN19) +#define GPIO_FC8_SCK_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN15) +#define GPIO_FC8_SCK_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN16) +#define GPIO_FC8_TXD_SCL_MISO_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN17) +#define GPIO_FC8_TXD_SCL_MISO_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN18) +#define GPIO_FC8_TXD_SCL_MISO_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN29) + +#define GPIO_FC9_CTS_SDA_SSEL0_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN30) +#define GPIO_FC9_CTS_SDA_SSEL0_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN13) +#define GPIO_FC9_CTS_SDA_SSEL0_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN5) +#define GPIO_FC9_RTS_SCL_SSEL1_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN31) +#define GPIO_FC9_RTS_SCL_SSEL1_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN14) +#define GPIO_FC9_RTS_SCL_SSEL1_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN6) +#define GPIO_FC9_RXD_SDA_MOSI_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN21) /* Type A */ +#define GPIO_FC9_RXD_SDA_MOSI_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN2) +#define GPIO_FC9_RXD_SDA_MOSI_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN15) +#define GPIO_FC9_SCK_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN20) +#define GPIO_FC9_SCK_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN27) +#define GPIO_FC9_SCK_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN14) +#define GPIO_FC9_TXD_SCL_MISO_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN22) /* Type A */ +#define GPIO_FC9_TXD_SCL_MISO_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN3) +#define GPIO_FC9_TXD_SCL_MISO_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN16) + +/* Frequency Measurement (FREQME) */ + +#define GPIO_FREQME_GPIO_CLK_A_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN11) /* Type A */ +#define GPIO_FREQME_GPIO_CLK_A_2 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_FREQME_GPIO_CLK_B_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN12) /* Type A */ +#define GPIO_FREQME_GPIO_CLK_B_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN7) + +/* LCD */ + +#define GPIO_LCD_AC (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_LCD_CLKIN (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN17) +#define GPIO_LCD_DCLK (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_LCD_FP (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_LCD_LE (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_LCD_LP (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN16) +#define GPIO_LCD_PWR (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN11) +#define GPIO_LCD_VD0_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN18) +#define GPIO_LCD_VD0_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN6) +#define GPIO_LCD_VD1_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN19) +#define GPIO_LCD_VD1_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN7) +#define GPIO_LCD_VD2_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN20) +#define GPIO_LCD_VD2_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN8) +#define GPIO_LCD_VD3_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN21) +#define GPIO_LCD_VD3_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN9) +#define GPIO_LCD_VD4 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN22) +#define GPIO_LCD_VD5 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN23) +#define GPIO_LCD_VD6 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN24) +#define GPIO_LCD_VD7 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN25) +#define GPIO_LCD_VD8 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN26) +#define GPIO_LCD_VD9 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN27) +#define GPIO_LCD_VD10 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN28) +#define GPIO_LCD_VD11 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN29) +#define GPIO_LCD_VD12 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN30) +#define GPIO_LCD_VD13 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN31) +#define GPIO_LCD_VD14 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN0) +#define GPIO_LCD_VD15 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN1) +#define GPIO_LCD_VD16 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN2) +#define GPIO_LCD_VD17 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN3) +#define GPIO_LCD_VD18 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN4) +#define GPIO_LCD_VD19 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN5) +#define GPIO_LCD_VD20 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN6) +#define GPIO_LCD_VD21 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN7) +#define GPIO_LCD_VD22 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN8) +#define GPIO_LCD_VD23 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN9) + +/* MCLK */ + +#define GPIO_MCLK_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN23) /* Type A */ +#define GPIO_MCLK_2 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN31) +#define GPIO_MCLK_3 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN11) +#define GPIO_MCLK_4 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN7) +#define GPIO_MCLK_5 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN21) + +/* Microphone (PDM) */ + +#define GPIO_PDM0_CLK_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN0) +#define GPIO_PDM0_CLK_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN8) +#define GPIO_PDM0_CLK_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_PDM0_CLK_4 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN26) +#define GPIO_PDM0_DATA_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN1) +#define GPIO_PDM0_DATA_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN9) +#define GPIO_PDM0_DATA_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_PDM0_DATA_4 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN27) + +#define GPIO_PDM1_CLK_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN5) +#define GPIO_PDM1_CLK_2 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_PDM1_CLK_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_PDM1_DATA_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN6) +#define GPIO_PDM1_DATA_2 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_PDM1_DATA_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN3) + +/* SmartCard Interface (SCI) */ + +#define GPIO_SCI0_IO (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN20) +#define GPIO_SCI0_SCLK (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN21) + +#define GPIO_SCI1_IO (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_SCI1_SCLK (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN18) + +/* SCTimer */ + +#define GPIO_SCT0_GPI0_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN5) +#define GPIO_SCT0_GPI0_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN0) +#define GPIO_SCT0_GPI0_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN13) /* Type D+I */ +#define GPIO_SCT0_GPI0_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN24) +#define GPIO_SCT0_GPI0_5 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_SCT0_GPI0_6 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN31) +#define GPIO_SCT0_GPI0_7 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN7) +#define GPIO_SCT0_GPI1_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN6) +#define GPIO_SCT0_GPI1_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_SCT0_GPI1_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN14) /* Type D+I */ +#define GPIO_SCT0_GPI1_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN25) +#define GPIO_SCT0_GPI1_5 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN0) +#define GPIO_SCT0_GPI1_7 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN8) +#define GPIO_SCT0_GPI2_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN7) +#define GPIO_SCT0_GPI2_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_SCT0_GPI2_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN20) +#define GPIO_SCT0_GPI2_4 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN1) +#define GPIO_SCT0_GPI2_5 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN9) +#define GPIO_SCT0_GPI3_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN8) +#define GPIO_SCT0_GPI3_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN21) +#define GPIO_SCT0_GPI3_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN3) +#define GPIO_SCT0_GPI3_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_SCT0_GPI3_5 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN10) +#define GPIO_SCT0_GPI3_6 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN2) +#define GPIO_SCT0_GPI4_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN9) +#define GPIO_SCT0_GPI4_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_SCT0_GPI4_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN0) /* Type A */ +#define GPIO_SCT0_GPI4_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_SCT0_GPI4_5 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN11) +#define GPIO_SCT0_GPI4_6 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN3) +#define GPIO_SCT0_GPI5_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN10) +#define GPIO_SCT0_GPI5_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_SCT0_GPI5_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_SCT0_GPI5_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_SCT0_GPI5_5 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN12) +#define GPIO_SCT0_GPI5_6 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN4) +#define GPIO_SCT0_GPI6_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_SCT0_GPI6_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_SCT0_GPI6_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN2) +#define GPIO_SCT0_GPI6_4 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN13) +#define GPIO_SCT0_GPI6_5 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN5) +#define GPIO_SCT0_GPI7_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN17) +#define GPIO_SCT0_GPI7_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN30) +#define GPIO_SCT0_GPI7_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN12) /* Type A */ +#define GPIO_SCT0_GPI7_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN19) +#define GPIO_SCT0_GPI7_5 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN14) +#define GPIO_SCT0_GPI7_6 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN6) +#define GPIO_SCT0_OUT0_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN23) +#define GPIO_SCT0_OUT0_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN26) +#define GPIO_SCT0_OUT0_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN2) +#define GPIO_SCT0_OUT0_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN17) +#define GPIO_SCT0_OUT0_5 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_SCT0_OUT1_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN24) +#define GPIO_SCT0_OUT1_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN27) +#define GPIO_SCT0_OUT1_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN3) +#define GPIO_SCT0_OUT1_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN18) +#define GPIO_SCT0_OUT1_5 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_SCT0_OUT2_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN25) +#define GPIO_SCT0_OUT2_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN28) +#define GPIO_SCT0_OUT2_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN15) /* Type A */ +#define GPIO_SCT0_OUT2_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN19) +#define GPIO_SCT0_OUT2_5 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_SCT0_OUT3_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN10) +#define GPIO_SCT0_OUT3_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN26) +#define GPIO_SCT0_OUT3_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN29) +#define GPIO_SCT0_OUT3_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN22) +#define GPIO_SCT0_OUT3_5 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN31) /* Type A */ +#define GPIO_SCT0_OUT3_6 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN10) +#define GPIO_SCT0_OUT4_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN14) +#define GPIO_SCT0_OUT4_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN30) +#define GPIO_SCT0_OUT4_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN23) /* Type A */ +#define GPIO_SCT0_OUT4_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN17) +#define GPIO_SCT0_OUT4_5 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_SCT0_OUT5_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN31) +#define GPIO_SCT0_OUT5_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN26) +#define GPIO_SCT0_OUT5_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN18) +#define GPIO_SCT0_OUT5_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN6) +#define GPIO_SCT0_OUT5_5 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN18) +#define GPIO_SCT0_OUT6_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN2) +#define GPIO_SCT0_OUT6_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN27) +#define GPIO_SCT0_OUT6_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN31) +#define GPIO_SCT0_OUT6_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN7) +#define GPIO_SCT0_OUT6_5 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN19) +#define GPIO_SCT0_OUT7_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN19) +#define GPIO_SCT0_OUT7_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN22) +#define GPIO_SCT0_OUT7_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN28) +#define GPIO_SCT0_OUT7_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN8) +#define GPIO_SCT0_OUT7_5 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN20) +#define GPIO_SCT0_OUT8_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN12) +#define GPIO_SCT0_OUT8_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN23) +#define GPIO_SCT0_OUT8_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN29) +#define GPIO_SCT0_OUT8_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN9) +#define GPIO_SCT0_OUT9_1 (GPIO_ALT1 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN13) +#define GPIO_SCT0_OUT9_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN24) +#define GPIO_SCT0_OUT9_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN30) +#define GPIO_SCT0_OUT9_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN10) + +/* SD card */ + +#define GPIO_SD_BACKEND_PWR_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN21) /* Type A */ +#define GPIO_SD_BACKEND_PWR_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_SD_CARD_DET_N_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN17) +#define GPIO_SD_CARD_DET_N_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN10) +#define GPIO_SD_CARD_DET_N_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN22) +#define GPIO_SD_CARD_INT_N_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN20) +#define GPIO_SD_CARD_INT_N_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT4 | GPIO_PIN24) +#define GPIO_SD_CLK_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT0 | GPIO_PIN7) +#define GPIO_SD_CLK_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT1 | GPIO_PIN8) +#define GPIO_SD_CLK_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN3) +#define GPIO_SD_CLK_4 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT4 | GPIO_PIN19) +#define GPIO_SD_CMD_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_SD_CMD_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT1 | GPIO_PIN22) +#define GPIO_SD_CMD_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN4) +#define GPIO_SD_CMD_4 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT4 | GPIO_PIN20) +#define GPIO_SD_CMD_5 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT1 | GPIO_PIN16) +#define GPIO_SD_D0_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT0 | GPIO_PIN24) +#define GPIO_SD_D0_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_SD_D0_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_SD_D0_4 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT4 | GPIO_PIN25) +#define GPIO_SD_D1_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT0 | GPIO_PIN25) +#define GPIO_SD_D1_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT1 | GPIO_PIN7) +#define GPIO_SD_D1_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN7) +#define GPIO_SD_D1_4 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT4 | GPIO_PIN26) +#define GPIO_SD_D2_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT0 | GPIO_PIN31) /* Type A */ +#define GPIO_SD_D2_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_SD_D2_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN8) +#define GPIO_SD_D2_4 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT4 | GPIO_PIN27) +#define GPIO_SD_D3_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PORT1 | GPIO_PIN0) /* Type A */ +#define GPIO_SD_D3_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT1 | GPIO_PIN6) +#define GPIO_SD_D3_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT2 | GPIO_PIN9) +#define GPIO_SD_D3_4 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT4 | GPIO_PIN28) +#define GPIO_SD_D4_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT1 | GPIO_PIN27) +#define GPIO_SD_D4_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN16) +#define GPIO_SD_D4_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT4 | GPIO_PIN29) +#define GPIO_SD_D5_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT1 | GPIO_PIN28) +#define GPIO_SD_D5_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN17) +#define GPIO_SD_D5_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT4 | GPIO_PIN30) +#define GPIO_SD_D6_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_SD_D6_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN18) +#define GPIO_SD_D6_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT4 | GPIO_PIN31) +#define GPIO_SD_D7_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT1 | GPIO_PIN30) +#define GPIO_SD_D7_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT3 | GPIO_PIN19) +#define GPIO_SD_D7_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_SLEW_FAST | GPIO_FILTER_OFF | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_SD_POW_EN_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_SD_POW_EN_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN5) +#define GPIO_SD_POW_EN_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN21) +#define GPIO_SD_VOLT0_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN11) +#define GPIO_SD_VOLT0_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_SD_VOLT1_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_SD_VOLT1_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN2) +#define GPIO_SD_VOLT2_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN13) +#define GPIO_SD_VOLT2_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN3) +#define GPIO_SD_WR_PRT_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN18) +#define GPIO_SD_WR_PRT_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN15) +#define GPIO_SD_WR_PRT_3 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN23) + +/* SPIFI */ + +#define GPIO_SPIFI_CLK (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN26) +#define GPIO_SPIFI_CSN (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN23) /* Type A */ +#define GPIO_SPIFI_IO0 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN24) +#define GPIO_SPIFI_IO1 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN25) +#define GPIO_SPIFI_IO2 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN28) +#define GPIO_SPIFI_IO3 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN27) +#define GPIO_SWCLK (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN11) /* Type A */ + +/* SWD */ + +#define GPIO_SWDIO (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN12) /* Type A */ +#define GPIO_SWO_1 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN8) +#define GPIO_SWO_2 (GPIO_ALT6 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN10) /* Type A */ + +/* Trace */ + +#define GPIO_TRACECLK_1 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN0) /* Type A */ +#define GPIO_TRACECLK_2 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN5) +#define GPIO_TRACECLK_3 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN12) +#define GPIO_TRACEDATA0_1 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN31) /* Type A */ +#define GPIO_TRACEDATA0_2 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN6) +#define GPIO_TRACEDATA0_3 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN10) +#define GPIO_TRACEDATA1_1 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN30) +#define GPIO_TRACEDATA1_2 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN7) +#define GPIO_TRACEDATA1_3 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN13) +#define GPIO_TRACEDATA2_1 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN29) +#define GPIO_TRACEDATA2_2 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN8) +#define GPIO_TRACEDATA2_3 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN14) +#define GPIO_TRACEDATA3_1 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN28) +#define GPIO_TRACEDATA3_2 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN9) +#define GPIO_TRACEDATA3_3 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN11) + +/* USBG */ + +#define GPIO_USB0_FRAME_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_USB0_FRAME_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN7) +#define GPIO_USB0_FRAME_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN13) +#define GPIO_USB0_IDVALUE_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN12) +#define GPIO_USB0_IDVALUE_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN11) +#define GPIO_USB0_IDVALUE_3 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN26) +#define GPIO_USB0_LEDN_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_USB0_LEDN_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN8) +#define GPIO_USB0_LEDN_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN14) +#define GPIO_USB0_OVERCURRENTN_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN15) +#define GPIO_USB0_OVERCURRENTN_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN8) +#define GPIO_USB0_OVERCURRENTN_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN13) +#define GPIO_USB0_OVERCURRENTN_4 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN28) +#define GPIO_USB0_PORTPWRN_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN14) +#define GPIO_USB0_PORTPWRN_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN7) +#define GPIO_USB0_PORTPWRN_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN12) +#define GPIO_USB0_PORTPWRN_4 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN3) +#define GPIO_USB0_VBUS_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN25) +#define GPIO_USB0_VBUS_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN24) /* Type D+I */ +#define GPIO_USB0_VBUS_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN11) +#define GPIO_USB0_VBUS_4 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN22) + +#define GPIO_USB1_FRAME_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN16) +#define GPIO_USB1_FRAME_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN9) +#define GPIO_USB1_FRAME_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_USB1_LEDN_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN17) +#define GPIO_USB1_LEDN_2 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN10) +#define GPIO_USB1_LEDN_3 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN30) +#define GPIO_USB1_OVERCURRENTN_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN17) +#define GPIO_USB1_OVERCURRENTN_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN10) +#define GPIO_USB1_OVERCURRENTN_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN30) +#define GPIO_USB1_OVERCURRENTN_4 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_USB1_PORTPWRN_1 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN16) +#define GPIO_USB1_PORTPWRN_2 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN9) +#define GPIO_USB1_PORTPWRN_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN29) +#define GPIO_USB1_PORTPWRN_4 (GPIO_ALT7 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN2) + +/* Micro-tick Timer (UTICK) */ + +#define GPIO_UTICK_CAP0_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN13) /* Type D+I */ +#define GPIO_UTICK_CAP0_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN19) +#define GPIO_UTICK_CAP0_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN25) +#define GPIO_UTICK_CAP0_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN17) +#define GPIO_UTICK_CAP1_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN14) /* Type D+I */ +#define GPIO_UTICK_CAP1_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN22) +#define GPIO_UTICK_CAP1_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN26) +#define GPIO_UTICK_CAP1_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN18) +#define GPIO_UTICK_CAP2_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN15) /* Type A */ +#define GPIO_UTICK_CAP2_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN14) +#define GPIO_UTICK_CAP2_3 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN21) /* Type A */ +#define GPIO_UTICK_CAP2_4 (GPIO_ALT4 | GPIO_MODE_DIGITAL | GPIO_PORT4 | GPIO_PIN26) +#define GPIO_UTICK_CAP3_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT0 | GPIO_PIN21) +#define GPIO_UTICK_CAP3_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT1 | GPIO_PIN15) +#define GPIO_UTICK_CAP3_3 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN23) /* Type D+I */ +#define GPIO_UTICK_CAP3_5 (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN10) + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC546X_PINMUX_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_dma.h b/arch/arm/src/lpc54xx/chip/lpc54_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..f79b531f881b590961ef4546f57a5d28e79da49c --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_dma.h @@ -0,0 +1,278 @@ +/******************************************************************************************** + * arch/arm/src/lpc54xx/lpc54_dma.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_DMA_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_DMA_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +#define LPC54_DMA_NCHANNELS 30 /* Channels 0..29 */ +#define LPC54_DMA_MAXXFRS 1024 /* Maximum number of transfers per DMA */ + +/* Register offsets *************************************************************************/ + +/* Global control and status registers */ + +#define LPC54_DMA_CTRL_OFFSET 0x0000 /* DMA control */ +#define LPC54_DMA_INTSTAT_OFFSET 0x0004 /* Interrupt status */ +#define LPC54_DMA_SRAMBASE_OFFSET 0x0008 /* SRAM address of the channel configuration table */ + +/* Shared registers */ + +#define LPC54_DMA_ENABLESET0_OFFSET 0x0020 /* Channel enable read and Set for all DMA channels */ +#define LPC54_DMA_ENABLECLR0_OFFSET 0x0028 /* Channel enable clear for all DMA channels */ +#define LPC54_DMA_ACTIVE0_OFFSET 0x0030 /* Channel active status for all DMA channels */ +#define LPC54_DMA_BUSY0_OFFSET 0x0038 /* Channel busy status for all DMA channels */ +#define LPC54_DMA_ERRINT0_OFFSET 0x0040 /* Error interrupt status for all DMA channels */ +#define LPC54_DMA_INTENSET0_OFFSET 0x0048 /* Interrupt enable read and Set for all DMA channels */ +#define LPC54_DMA_INTENCLR0_OFFSET 0x0050 /* Interrupt enable clear for all DMA channels */ +#define LPC54_DMA_INTA0_OFFSET 0x0058 /* Interrupt A status for all DMA channels */ +#define LPC54_DMA_INTB0_OFFSET 0x0060 /* Interrupt B status for all DMA channels */ +#define LPC54_DMA_SETVALID0_OFFSET 0x0068 /* Set ValidPending control bits for all DMA channels */ +#define LPC54_DMA_SETTRIG0_OFFSET 0x0070 /* Set trigger control bits for all DMA channels */ +#define LPC54_DMA_ABORT0_OFFSET 0x0078 /* Channel abort control for all DMA channels */ + +/* Channel registers */ + +#define LPC54_DMA_CHAN_OFFSET(n) (0x0400 + ((n) << 4)) +#define LPC54_DMA_CFG_OFFSET 0x0000 /* Configuration register for DMA channel n */ +#define LPC54_DMA_CTLSTAT_OFFSET 0x0004 /* Control and status register for DMA channel n */ +#define LPC54_DMA_XFERCFG_OFFSET 0x0008 /* Transfer configuration register for DMA channel n */ + +/* Register addresses ***********************************************************************/ + +/* Global control and status registers */ + +#define LPC54_DMA_CTRL (LPC54_DMA_BASE + LPC54_DMA_CTRL_OFFSET) +#define LPC54_DMA_INTSTAT (LPC54_DMA_BASE + LPC54_DMA_INTSTAT_OFFSET) +#define LPC54_DMA_SRAMBASE (LPC54_DMA_BASE + LPC54_DMA_SRAMBASE_OFFSET) + +/* Shared registers */ + +#define LPC54_DMA_ENABLESET0 (LPC54_DMA_BASE + LPC54_DMA_ENABLESET0_OFFSET) +#define LPC54_DMA_ENABLECLR0 (LPC54_DMA_BASE + LPC54_DMA_ENABLECLR0_OFFSET) +#define LPC54_DMA_ACTIVE0 (LPC54_DMA_BASE + LPC54_DMA_ACTIVE0_OFFSET) +#define LPC54_DMA_BUSY0 (LPC54_DMA_BASE + LPC54_DMA_BUSY0_OFFSET) +#define LPC54_DMA_ERRINT0 (LPC54_DMA_BASE + LPC54_DMA_ERRINT0_OFFSET) +#define LPC54_DMA_INTENSET0 (LPC54_DMA_BASE + LPC54_DMA_INTENSET0_OFFSET) +#define LPC54_DMA_INTENCLR0 (LPC54_DMA_BASE + LPC54_DMA_INTENCLR0_OFFSET) +#define LPC54_DMA_INTA0 (LPC54_DMA_BASE + LPC54_DMA_INTA0_OFFSET) +#define LPC54_DMA_INTB0 (LPC54_DMA_BASE + LPC54_DMA_INTB0_OFFSET) +#define LPC54_DMA_SETVALID0 (LPC54_DMA_BASE + LPC54_DMA_SETVALID0_OFFSET) +#define LPC54_DMA_SETTRIG0 (LPC54_DMA_BASE + LPC54_DMA_SETTRIG0_OFFSET) +#define LPC54_DMA_ABORT0 (LPC54_DMA_BASE + LPC54_DMA_ABORT0_OFFSET) + +/* Channel registers */ + +#define LPC54_DMA_CHAN_BASE(n) (LPC54_DMA_BASE + LPC54_DMA_CHAN_OFFSET(n)) +#define LPC54_DMA_CFG(n) (LPC54_DMA_CHAN_BASE(n) + LPC54_DMA_CFG_OFFSET) +#define LPC54_DMA_CTLSTAT(n) (LPC54_DMA_CHAN_BASE(n) + LPC54_DMA_CTLSTAT_OFFSET) +#define LPC54_DMA_XFERCFG(n) (LPC54_DMA_CHAN_BASE(n) + LPC54_DMA_XFERCFG_OFFSET) + +/* Register bit definitions *****************************************************************/ + +/* DMA control */ + +#define DMA_CTRL_ENABLE (1 << 0) /* Bit 0: DMA controller master enable */ + +/* Interrupt status */ + +#define DMA_INTSTAT_ACTIVEINT (1 << 1) /* Bit 1: Summarizes pending enabled interrupts */ +#define DMA_INTSTAT_ACTIVEERRINT (1 << 2) /* Bit 2: Summarizes pending error interrupts */ + +/* SRAM address of the channel configuration table */ + +#define DMA_SRAMBASE_MASK 0xfffffe00 + +/* The remaining shared registers are all 32 bit encoded fieldss with bit n corresponding to + * Channel n. + */ + +#define DMA_CHANNEL(n) (1 << (n)) +#define DMA_ALL_CHANNELS 0x3fffffff + +/* Channel registers */ + +/* Configuration register for DMA channel n */ + +#define DMA_CFG_PERIPHREQEN (1 << 0) /* Bit 0: Peripheral request Enable */ +#define DMA_CFG_HWTRIGEN (1 << 1) /* Bit 1: Hardware Triggering Enable */ +#define DMA_CFG_TRIGPOL (1 << 4) /* Bit 4: Trigger Polarity */ +# define DMA_CFG_ACTIVE_LOW (0) +# define DMA_CFG_FALLING_EDGE (0) +# define DMA_CFG_ACTIVE_HIGH DMA_CFG_TRIGPOL +# define DMA_CFG_RISING_EDGE DMA_CFG_TRIGPOL +#define DMA_CFG_TRIGTYPE (1 << 5) /* Bit 5: Trigger Type */ +# define DMA_CFG_EDGE_TRIGGER (0) +# define DMA_CFG_LEVEL_TRIGGER DMA_CFG_TRIGTYPE +#define DMA_CFG_TRIGBURST (1 << 6) /* Bit 6: Trigger Burst */ +#define DMA_CFG_BURSTPOWER_SHIFT (8) /* Bits 8-11: Burst Power */ +#define DMA_CFG_BURSTPOWER_MASK (15 << DMA_CFG_BURSTPOWER_SHIFT) +# define DMA_CFG_BURSTPOWER_1 (0 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 1 (2^0) */ +# define DMA_CFG_BURSTPOWER_2 (1 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 2 (2^1) */ +# define DMA_CFG_BURSTPOWER_3 (2 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 4 (2^2) */ +# define DMA_CFG_BURSTPOWER_8 (3 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 8 (2^2) */ +# define DMA_CFG_BURSTPOWER_16 (4 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 16 (2^2) */ +# define DMA_CFG_BURSTPOWER_32 (5 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 32 (2^2) */ +# define DMA_CFG_BURSTPOWER_64 (6 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 64 (2^2) */ +# define DMA_CFG_BURSTPOWER_128 (7 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 128 (2^2) */ +# define DMA_CFG_BURSTPOWER_256 (8 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 256 (2^2) */ +# define DMA_CFG_BURSTPOWER_512 (9 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 256 (2^2) */ +# define DMA_CFG_BURSTPOWER_1024 (10 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 1024 (2^10) */ +#define DMA_CFG_SRCBURSTWRAP (1 << 14) /* Bit 14: Source Burst Wrap */ +#define DMA_CFG_DSTBURSTWRAP (1 << 15) /* Bit 15: Destination Burst Wrap */ +#define DMA_CFG_CHPRIORITY_SHIFT (16) /* Bits 16-18: Priority of this channel */ +#define DMA_CFG_CHPRIORITY_MASK (7 << DMA_CFG_CHPRIORITY_SHIFT) +# define DMA_CFG_CHPRIORITY(n) ((uint32_t)(n) << DMA_CFG_CHPRIORITY_SHIFT) +# define DMA_CFG_CHPRIORITY_HIGH (0 << DMA_CFG_CHPRIORITY_SHIFT) /* Highest priority */ +# define DMA_CFG_CHPRIORITY_LOW (7 << DMA_CFG_CHPRIORITY_SHIFT) /* Lowest priority */ + +/* Control and status register for DMA channel n */ + +#define DMA_CTLSTAT_VALIDPENDING (1 << 0) /* Bit 0: Valid pending flag */ +#define DMA_CTLSTAT_TRIG (1 << 2) /* Bit 2: Trigger flag */ + +/* Transfer configuration register for DMA channel n */ + +#define DMA_XFERCFG_CFGVALID (1 << 0) /* Bit 0: Configuration Valid flag */ +#define DMA_XFERCFG_RELOAD (1 << 1) /* Bit 1: Reload channel’s control structure */ +#define DMA_XFERCFG_SWTRIG (1 << 2) /* Bit 2: Software Trigger */ +#define DMA_XFERCFG_CLRTRIG (1 << 3) /* Bit 3: Clear Trigger */ +#define DMA_XFERCFG_SETINTA (1 << 4) /* Bit 4: Set Interrupt flag A */ +#define DMA_XFERCFG_SETINTB (1 << 5) /* Bit 5: Set Interrupt flag B */ +#define DMA_XFERCFG_WIDTH_SHIFT (8) /* Bits 8-9: Transfer width */ +#define DMA_XFERCFG_WIDTH_MASK (3 << DMA_XFERCFG_WIDTH_SHIFT) +# define DMA_XFERCFG_WIDTH_8BIT (0 << DMA_XFERCFG_WIDTH_SHIFT) /* 8-bit transfers */ +# define DMA_XFERCFG_WIDTH_16BIT (1 << DMA_XFERCFG_WIDTH_SHIFT) /* 16-bit transfers */ +# define DMA_XFERCFG_WIDTH_32BIT (2 << DMA_XFERCFG_WIDTH_SHIFT) /* 32-bit transfers */ +#define DMA_XFERCFG_SRCINC_SHIFT (12) /* Bits 12-13: Source address increment */ +#define DMA_XFERCFG_SRCINC_MASK (3 << DMA_XFERCFG_SRCINC_SHIFT) +# define DMA_XFERCFG_SRCINC_NONE (0 << DMA_XFERCFG_SRCINC_SHIFT) /* No increment */ +# define DMA_XFERCFG_SRCINC_1X (1 << DMA_XFERCFG_SRCINC_SHIFT) /* 1 x width */ +# define DMA_XFERCFG_SRCINC_2X (2 << DMA_XFERCFG_SRCINC_SHIFT) /* 2 x width */ +# define DMA_XFERCFG_SRCINC_4X (3 << DMA_XFERCFG_SRCINC_SHIFT) /* 4 x width */ +#define DMA_XFERCFG_DSTINC_SHIFT (14) /* Bits 14-15: Destination address increment */ +#define DMA_XFERCFG_DSTINC_MASK (3 << DMA_XFERCFG_DSTINC_SHIFT) +# define DMA_XFERCFG_DSTINC_NONE (0 << DMA_XFERCFG_DSTINC_SHIFT) /* No increment */ +# define DMA_XFERCFG_DSTINC_1X (1 << DMA_XFERCFG_DSTINC_SHIFT) /* 1 x width */ +# define DMA_XFERCFG_DSTINC_2X (2 << DMA_XFERCFG_DSTINC_SHIFT) /* 2 x width */ +# define DMA_XFERCFG_DSTINC_4X (3 << DMA_XFERCFG_DSTINC_SHIFT) /* 4 x width */ +#define DMA_XFERCFG_XFERCOUNT_SHIFT (16) /* Bits 16-25: Total number of transfers to be performed */ +#define DMA_XFERCFG_XFERCOUNT_MASK (0x3ff << DMA_XFERCFG_XFERCOUNT_SHIFT) +# define DMA_XFERCFG_XFERCOUNT(n) ((uint32_t)((n)-1) << DMA_XFERCFG_XFERCOUNT_SHIFT) + +/* DMA requests *****************************************************************************/ +/* DMA requests are directly connected to the peripherals. Each channel supports one DMA + * request line and one trigger input. Some DMA requests allow a selection of requests + * sources. DMA triggers are selected from many possible input sources. + */ + +/* Peripheral request inputs to DMA channel. For DMA channel 'n', the corresponding DMA + * trigger input is provided by the setting of the INPUT MUX register DMA_ITRIG_INMUXn + */ + +#define FLEXCOMM0_RX_DMACHAN (0) /* Flexcomm Interface 0 RX */ +#define FLEXCOMM0_I2CSLAVE_DMACHAN (0) /* Flexcomm Interface 0 I2C Slave */ +#define FLEXCOMM0_TX_DMACHAN (1) /* Flexcomm Interface 0 TX */ +#define FLEXCOMM0_I2CMASTER_DMACHAN (1) /* Flexcomm Interface 0 I2C Master */ +#define FLEXCOMM1_RX_DMACHAN (2) /* Flexcomm Interface 1 RX */ +#define FLEXCOMM1_I2CSLAVE_DMACHAN (2) /* Flexcomm Interface 1 I2C Slave */ +#define FLEXCOMM1_TX_DMACHAN (3) /* Flexcomm Interface 1 TX */ +#define FLEXCOMM1_I2CMASTER_DMACHAN (3) /* Flexcomm Interface 1 I2C Master */ +#define FLEXCOMM2_RX_DMACHAN (4) /* Flexcomm Interface 2 RX */ +#define FLEXCOMM2_I2CSLAVE_DMACHAN (4) /* Flexcomm Interface 2 I2C Slave */ +#define FLEXCOMM2_TX_DMACHAN (5) /* Flexcomm Interface 2 TX */ +#define FLEXCOMM2_I2CMASTER_DMACHAN (5) /* Flexcomm Interface 2 I2C Master */ +#define FLEXCOMM3_RX_DMACHAN (6) /* Flexcomm Interface 3 RX */ +#define FLEXCOMM3_I2CSLAVE_DMACHAN (6) /* Flexcomm Interface 3 I2C Slave */ +#define FLEXCOMM3_TX_DMACHAN (7) /* Flexcomm Interface 3 TX */ +#define FLEXCOMM3_I2CMASTER_DMACHAN (7) /* Flexcomm Interface 3 I2C Master */ +#define FLEXCOMM4_RX_DMACHAN (8) /* Flexcomm Interface 4 RX */ +#define FLEXCOMM4_I2CSLAVE_DMACHAN (8) /* Flexcomm Interface 4 I2C Slave */ +#define FLEXCOMM4_TX_DMACHAN (9) /* Flexcomm Interface 4 TX */ +#define FLEXCOMM4_I2CMASTER_DMACHAN (9) /* Flexcomm Interface 4 I2C Master */ +#define FLEXCOMM5_RX_DMACHAN (10) /* Flexcomm Interface 5 RX */ +#define FLEXCOMM5_I2CSLAVE_DMACHAN (10) /* Flexcomm Interface 5 I2C Slave */ +#define FLEXCOMM5_TX_DMACHAN (11) /* Flexcomm Interface 5 TX */ +#define FLEXCOMM5_I2CMASTER_DMACHAN (11) /* Flexcomm Interface 5 I2C Master */ +#define FLEXCOMM6_RX_DMACHAN (12) /* Flexcomm Interface 6 RX */ +#define FLEXCOMM6_I2CSLAVE_DMACHAN (12) /* Flexcomm Interface 6 I2C Slave */ +#define FLEXCOMM6_TX_DMACHAN (13) /* Flexcomm Interface 6 TX */ +#define FLEXCOMM6_I2CMASTER_DMACHAN (13) /* Flexcomm Interface 6 I2C Master */ +#define FLEXCOMM7_RX_DMACHAN (14) /* Flexcomm Interface 7 RX */ +#define FLEXCOMM7_I2CSLAVE_DMACHAN (14) /* Flexcomm Interface 7 I2C Slave */ +#define FLEXCOMM7_TX_DMACHAN (15) /* Flexcomm Interface 7 TX */ +#define FLEXCOMM7_I2CMASTER_DMACHAN (15) /* Flexcomm Interface 7 I2C Master */ +#define DMIC0_DMACHAN (16) /* DMIC0 */ +#define DMIC1_DMACHAN (17) /* DMIC1 */ +#define SPIFI_DMACHAN (18) /* SPIFI */ +#define SHA_DMACHAN (19) /* SHA */ +#define FLEXCOMM8_RX_DMACHAN (20) /* Flexcomm Interface 8 RX */ +#define FLEXCOMM8_I2CSLAVE_DMACHAN (20) /* Flexcomm Interface 8 I2C Slave */ +#define FLEXCOMM8_TX_DMACHAN (21) /* Flexcomm Interface 8 TX */ +#define FLEXCOMM8_I2CMASTER_DMACHAN (21) /* Flexcomm Interface 8 I2C Slave (?) */ +#define FLEXCOMM9_RX_DMACHAN (22) /* Flexcomm Interface 9 RX */ +#define FLEXCOMM9_I2CSLAVE_DMACHAN (22) /* Flexcomm Interface 9 I2C Slave */ +#define FLEXCOMM9_TX_DMACHAN (23) /* Flexcomm Interface 9 TX */ +#define FLEXCOMM9_I2CMASTER_DMACHAN (23) /* Flexcomm Interface 9 I2C Slave (?) */ +#define SMARTCARD0_RX_DMACHAN (24) /* SMARTCARD0_RX */ +#define SMARTCARD0_TX_DMACHAN (25) /* SMARTCARD0_TX */ +#define SMARTCARD1_RX_DMACHAN (26) /* SMARTCARD1_RX */ +#define SMARTCARD1_TX_DMACHAN (27) /* SMARTCARD1_TX */ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/* DMA channel descriptor */ + +struct lpc54_dmachan_desc_s +{ + uint32_t reserved; + uint32_t srcend; /* Source data end address */ + uint32_t dstend; /* Destination end address */ + uint32_t link; /* Link to next descriptor */ +}; + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_DMA_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_emc.h b/arch/arm/src/lpc54xx/chip/lpc54_emc.h new file mode 100644 index 0000000000000000000000000000000000000000..9a722b86b2db0eda4ee9b23754477c2c2d09fedb --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_emc.h @@ -0,0 +1,343 @@ +/**************************************************************************************************** + * arch/arm/src/lpc54xx/lpc54_emc.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_EMC_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_EMC_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +#define LPC54_EMC_CS0 0 +#define LPC54_EMC_CS1 1 +#define LPC54_EMC_CS2 2 +#define LPC54_EMC_CS3 3 +#define LPC54_EMC_NCS 4 + +/* Register offsets *********************************************************************************/ + +#define LPC54_EMC_CONTROL_OFFSET 0x0000 /* Controls operation of the memory controller */ +#define LPC54_EMC_STATUS_OFFSET 0x0004 /* Provides EMC status information */ +#define LPC54_EMC_CONFIG_OFFSET 0x0008 /* Configures operation of the memory controller */ +#define LPC54_EMC_DYNCONTROL_OFFSET 0x0020 /* Controls dynamic memory operation */ +#define LPC54_EMC_DYNREFRESH_OFFSET 0x0024 /* Configures dynamic memory refresh */ +#define LPC54_EMC_DYNREADCONFIG_OFFSET 0x0028 /* Configures dynamic memory read strategy */ +#define LPC54_EMC_DYNRP_OFFSET 0x0030 /* Precharge command period */ +#define LPC54_EMC_DYNRAS_OFFSET 0x0034 /* Active to precharge command period */ +#define LPC54_EMC_DYNSREX_OFFSET 0x0038 /* Self-refresh exit time */ +#define LPC54_EMC_DYNAPR_OFFSET 0x003c /* Last-data-out to active command time */ +#define LPC54_EMC_DYNDAL_OFFSET 0x0040 /* Data-in to active command time */ +#define LPC54_EMC_DYNWR_OFFSET 0x0044 /* Write recovery time */ +#define LPC54_EMC_DYNRC_OFFSET 0x0048 /* Selects the active to active command period */ +#define LPC54_EMC_DYNRFC_OFFSET 0x004c /* Selects the auto-refresh period */ +#define LPC54_EMC_DYNXSR_OFFSET 0x0050 /* Time for exit self-refresh to active command */ +#define LPC54_EMC_DYNRRD_OFFSET 0x0054 /* Latency for active bank A to active bank B */ +#define LPC54_EMC_DYNMRD_OFFSET 0x0058 /* Time for load mode register to active command */ +#define LPC54_EMC_STATEXTWAIT_OFFSET 0x0080 /* Time for long static memory read and write transfers */ + +/* Per-chip select dynamic memory registers */ + +#define LPC54_EMC_DYNCS_OFFSET(n) (0x0100 + ((uintptr_t)(n) << 5)) +#define LPC54_EMC_DYNCONFIG_OFFSET 0x0000 /* Configuration information for CSn */ +#define LPC54_EMC_DYNRASCAS_OFFSET 0x0004 /* RAS and CAS latencies for CSn */ + +#define LPC54_EMC_DYNCONFIGn_OFFSET(n) (0x0100 + ((uintptr_t)(n) << 5)) +#define LPC54_EMC_DYNRASCASn_OFFSET(n) (0x0104 + ((uintptr_t)(n) << 5)) + +/* Per-chip select static memory registers */ + +#define LPC54_EMC_STATCS_OFFSET(n) (0x0200 + ((uintptr_t)(n) << 5)) +#define LPC54_EMC_STATCONFIG_OFFSET 0x0000 /* Configuration for CSn */ +#define LPC54_EMC_STATWAITWEN_OFFSET 0x0004 /* Delay to write enable */ +#define LPC54_EMC_STATWAITOEN_OFFSET 0x0008 /* Delay to output enable */ +#define LPC54_EMC_STATWAITRD_OFFSET 0x000c /* Delay to read access */ +#define LPC54_EMC_STATWAITPAGE_OFFSET 0x0010 /* Delay for asynchronous page mode accesses */ +#define LPC54_EMC_STATWAITWR_OFFSET 0x0014 /* Delay from EMC_CS0 to a write access */ +#define LPC54_EMC_STATWAITTURN_OFFSET 0x0018 /* Number of bus turnaround cycles */ + +#define LPC54_EMC_STATCONFIGn_OFFSET(n) (0x0200 + ((uintptr_t)(n) << 5)) +#define LPC54_EMC_STATWAITWENn_OFFSET(n) (0x0204 + ((uintptr_t)(n) << 5)) +#define LPC54_EMC_STATWAITOENn_OFFSET(n) (0x0208 + ((uintptr_t)(n) << 5)) +#define LPC54_EMC_STATWAITRDn_OFFSET(n) (0x020c + ((uintptr_t)(n) << 5)) +#define LPC54_EMC_STATWAITPAGEn_OFFSET(n) (0x0210 + ((uintptr_t)(n) << 5)) +#define LPC54_EMC_STATWAITWRn_OFFSET(n) (0x0214 + ((uintptr_t)(n) << 5)) +#define LPC54_EMC_STATWAITTURNn_OFFSET(n) (0x0218 + ((uintptr_t)(n) << 5)) + +/* Register addresses *******************************************************************************/ + +#define LPC54_EMC_CONTROL (LPC54_EMC_BASE + LPC54_EMC_CONTROL_OFFSET) +#define LPC54_EMC_STATUS (LPC54_EMC_BASE + LPC54_EMC_STATUS_OFFSET) +#define LPC54_EMC_CONFIG (LPC54_EMC_BASE + LPC54_EMC_CONFIG_OFFSET) +#define LPC54_EMC_DYNCONTROL (LPC54_EMC_BASE + LPC54_EMC_DYNCONTROL_OFFSET) +#define LPC54_EMC_DYNREFRESH (LPC54_EMC_BASE + LPC54_EMC_DYNREFRESH_OFFSET) +#define LPC54_EMC_DYNREADCONFIG (LPC54_EMC_BASE + LPC54_EMC_DYNREADCONFIG_OFFSET) +#define LPC54_EMC_DYNRP (LPC54_EMC_BASE + LPC54_EMC_DYNRP_OFFSET) +#define LPC54_EMC_DYNRAS (LPC54_EMC_BASE + LPC54_EMC_DYNRAS_OFFSET) +#define LPC54_EMC_DYNSREX (LPC54_EMC_BASE + LPC54_EMC_DYNSREX_OFFSET) +#define LPC54_EMC_DYNAPR (LPC54_EMC_BASE + LPC54_EMC_DYNAPR_OFFSET) +#define LPC54_EMC_DYNDAL (LPC54_EMC_BASE + LPC54_EMC_DYNDAL_OFFSET) +#define LPC54_EMC_DYNWR (LPC54_EMC_BASE + LPC54_EMC_DYNWR_OFFSET) +#define LPC54_EMC_DYNRC (LPC54_EMC_BASE + LPC54_EMC_DYNRC_OFFSET) +#define LPC54_EMC_DYNRFC (LPC54_EMC_BASE + LPC54_EMC_DYNRFC_OFFSET) +#define LPC54_EMC_DYNXSR (LPC54_EMC_BASE + LPC54_EMC_DYNXSR_OFFSET) +#define LPC54_EMC_DYNRRD (LPC54_EMC_BASE + LPC54_EMC_DYNRRD_OFFSET) +#define LPC54_EMC_DYNMRD (LPC54_EMC_BASE + LPC54_EMC_DYNMRD_OFFSET) +#define LPC54_EMC_STATEXTWAIT (LPC54_EMC_BASE + LPC54_EMC_STATEXTWAIT_OFFSET) + +/* Per-chip select dynamic memory registers */ + +#define LPC54_EMC_DYNCS_BASE(n) (LPC54_EMC_BASE + LPC54_EMC_DYNCS_OFFSET(n)) +#define LPC54_EMC_DYNCONFIG(n) (LPC54_EMC_DYNCS_BASE(n) + LPC54_EMC_DYNCONFIG_OFFSET) +#define LPC54_EMC_DYNRASCAS(n) (LPC54_EMC_DYNCS_BASE(n) + LPC54_EMC_DYNRASCAS_OFFSET) + +/* Per-chip select static memory registers */ + +#define LPC54_EMC_STATCS_BASE(n) (LPC54_EMC_BASE + LPC54_EMC_STATCS_OFFSET(n)) +#define LPC54_EMC_STATCONFIG(n) (LPC54_EMC_STATCS_BASE(n) + LPC54_EMC_STATCONFIG_OFFSET) +#define LPC54_EMC_STATWAITWEN(n) (LPC54_EMC_STATCS_BASE(n) + LPC54_EMC_STATWAITWEN_OFFSET) +#define LPC54_EMC_STATWAITOEN(n) (LPC54_EMC_STATCS_BASE(n) + LPC54_EMC_STATWAITOEN_OFFSET) +#define LPC54_EMC_STATWAITRD(n) (LPC54_EMC_STATCS_BASE(n) + LPC54_EMC_STATWAITRD_OFFSET) +#define LPC54_EMC_STATWAITPAGE(n) (LPC54_EMC_STATCS_BASE(n) + LPC54_EMC_STATWAITPAGE_OFFSET) +#define LPC54_EMC_STATWAITWR(n) (LPC54_EMC_STATCS_BASE(n) + LPC54_EMC_STATWAITWR_OFFSET) +#define LPC54_EMC_STATWAITTURN(n) (LPC54_EMC_STATCS_BASE(n) + LPC54_EMC_STATWAITTURN_OFFSET) + +/* Register bit definitions *************************************************************************/ + +/* Controls operation of the memory controller */ + +#define EMC_CONTROL_E (1 << 0) /* Bit 0: EMC Enable */ +#define EMC_CONTROL_M (1 << 1) /* Bit 1: Address mirror */ +#define EMC_CONTROL_L (1 << 2) /* Bit 2: Low-power mode */ + +/* Provides EMC status information */ + +#define EMC_STATUS_B (1 << 0) /* Bit 0: Busy */ +#define EMC_STATUS_S (1 << 1) /* Bit 1: Write buffer status */ +#define EMC_STATUS_SA (1 << 2) /* Bit 2: Self-refresh acknowledge */ + +/* Configures operation of the memory controller */ + +#define EMC_CONFIG_EM (1 << 0) /* Bit 0: EM Endian mode */ +#define EMC_CONFIG_CLKR (1 << 8) /* Bit 8: Must be zero */ + +/* Controls dynamic memory operation */ + +#define EMC_DYNCONTROL_CE (1 << 0) /* Bit 0: Dynamic memory clock enable */ +#define EMC_DYNCONTROL_CS (1 << 1) /* Bit 1: Dynamic memory clock control */ +#define EMC_DYNCONTROL_SR (1 << 2) /* Bit 2: Self-refresh request, EMCSREFREQ */ +#define EMC_DYNCONTROL_MMC (1 << 5) /* Bit 5: Memory clock control */ +#define EMC_DYNCONTROL_I_SHIFT (7) /* Bit 7-8: SDRAM initialization */ +#define EMC_DYNCONTROL_I_MASK (3 << EMC_DYNCONTROL_I_SHIFT) +# define EMC_DYNCONTROL_I_NORMAL (0 << EMC_DYNCONTROL_I_SHIFT) /* Issue SDRAM NORMAL operation command */ +# define EMC_DYNCONTROL_I_MODE (1 << EMC_DYNCONTROL_I_SHIFT) /* Issue SDRAM MODE command */ +# define EMC_DYNCONTROL_I_PALL (2 << EMC_DYNCONTROL_I_SHIFT) /* Issue SDRAM PALL (precharge all) command */ +# define EMC_DYNCONTROL_I_NOP (3 << EMC_DYNCONTROL_I_SHIFT) /* Issue SDRAM NOP (no operation) command */ + +/* Configures dynamic memory refresh */ + +#define EMC_DYNREFRESH_SHIFT (0) /* Bits 0-10: Refresh timer */ +#define EMC_DYNREFRESH_MASK (0x7ff << EMC_DYNREFRESH_SHIFT) +# define EMC_DYNREFRESH_DISABLE(n) (0 << EMC_DYNREFRESH_SHIFT) +# define EMC_DYNREFRESH(n) ((uint32_t)((n) >> 4) << EMC_DYNREFRESH_SHIFT) + +/* Configures dynamic memory read strategy */ + +#define EMC_DYNREADCONFIG_SHIFT (0) /* Bits 0-1: Read data strategy */ +#define EMC_DYNREADCONFIG_MASK (3 << EMC_DYNREADCONFIG_SHIFT) +# define EMC_DYNREADCONFIG(n) ((uint32_t)(n) << EMC_DYNREADCONFIG_SHIFT) +# define EMC_DYNREADCONFIG_PLUS0 (1 << EMC_DYNREADCONFIG_SHIFT) /* Using EMCCLKDELAY */ +# define EMC_DYNREADCONFIG_PLUS1 (2 << EMC_DYNREADCONFIG_SHIFT) /* Plus one clock cycle using EMCCLKDELAY */ +# define EMC_DYNREADCONFIG_PLUS2 (3 << EMC_DYNREADCONFIG_SHIFT) /* Plus two clock cycles using EMCCLKDELAY */ + +/* Precharge command period */ + +#define EMC_DYNRP_SHIFT (0) /* Bits 0-3: Precharge command period */ +#define EMC_DYNRP_MASK (15 << EMC_DYNRP_SHIFT) +# define EMC_DYNRP(n) ((uint32_t)((n)-1) << EMC_DYNRP_SHIFT) + +/* Active to precharge command period */ + +#define EMC_DYNRAS_SHIFT (0) /* Bits 0-3: Active to precharge command period */ +#define EMC_DYNRAS_MASK (15 << EMC_DYNRAS_SHIFT) +# define EMC_DYNRAS(n) ((uint32_t)((n)-1) << EMC_DYNRAS_SHIFT) + +/* Self-refresh exit time */ + +#define EMC_DYNSREX_SHIFT (0) /* Bits 0-3: Self-refresh exit time */ +#define EMC_DYNSREX_MASK (15 << EMC_DYNSREX_SHIFT) +# define EMC_DYNSREX(n) ((uint32_t)((n)-1) << EMC_DYNSREX_SHIFT) + +/* Last-data-out to active command time */ + +#define EMC_DYNAPR_SHIFT (0) /* Bits 0-3: Self-refresh exit time */ +#define EMC_DYNAPR_MASK (15 << EMC_DYNAPR_SHIFT) +# define EMC_DYNAPR(n) ((uint32_t)((n)-1) << EMC_DYNAPR_SHIFT) + +/* Data-in to active command time */ + +#define EMC_DYNDAL_SHIFT (0) /* Bits 0-3: Data-in to active command */ +#define EMC_DYNDAL_MASK (15 << EMC_DYNDAL_SHIFT) +# define EMC_DYNDAL(n) ((uint32_t)(n) << EMC_DYNDAL_SHIFT) + +/* Write recovery time */ + +#define EMC_DYNWR_SHIFT (0) /* Bits 0-3: Data-in to active command */ +#define EMC_DYNWR_MASK (15 << EMC_DYNWR_SHIFT) +# define EMC_DYNWR(n) ((uint32_t)((n)-1) << EMC_DYNWR_SHIFT) + +/* Selects the active to active command period */ + +#define EMC_DYNRC_SHIFT (0) /* Bits 0-4: Data-in to active command */ +#define EMC_DYNRC_MASK (31 << EMC_DYNRC_SHIFT) +# define EMC_DYNRC(n) ((uint32_t)((n)-1) << EMC_DYNRC_SHIFT) + +/* Selects the auto-refresh period */ + +#define EMC_DYNRFC_SHIFT (0) /* Bits 0-4: Auto-refresh period and auto-refresh to active command period */ +#define EMC_DYNRFC_MASK (31 << EMC_DYNRFC_SHIFT) +# define EMC_DYNRFC(n) ((uint32_t)((n)-1) << EMC_DYNRFC_SHIFT) + +/* Time for exit self-refresh to active command */ + +#define EMC_DYNXSR_SHIFT (0) /* Bits 0-4: Exit self-refresh to active command time */ +#define EMC_DYNXSR_MASK (31 << EMC_DYNXSR_SHIFT) +# define EMC_DYNXSR(n) ((uint32_t)((n)-1) << EMC_DYNXSR_SHIFT) + +/* Latency for active bank A to active bank B */ + +#define EMC_DYNRRD_SHIFT (0) /* Bits 0-3: Active bank A to active bank B latency */ +#define EMC_DYNRRD_MASK (15 << EMC_DYNRRD_SHIFT) +# define EMC_DYNRRD(n) ((uint32_t)((n)-1) << EMC_DYNRRD_SHIFT) + +/* Time for load mode register to active command */ + +#define EMC_DYNMRD_SHIFT (0) /* Bits 0-3: Load mode register to active command time */ +#define EMC_DYNMRD_MASK (15 << EMC_DYNMRD_SHIFT) +# define EMC_DYNMRD(n) ((uint32_t)((n)-1) << EMC_DYNMRD_SHIFT) + +/* Time for long static memory read and write transfers */ + +#define EMC_STATEXTWAIT_SHIFT (0) /* Bits 0-9: Extended wait time out */ +#define EMC_STATEXTWAIT_MASK (0x3ff << EMC_STATEXTWAIT_SHIFT) +# define EMC_STATEXTWAIT(n) ((uint32_t)((n)-1) << EMC_STATEXTWAIT_SHIFT) + +/* Per-chip select dynamic memory registers */ +/* Dynamic Memory Configuration registers */ +#define EMC_DYNCONFIG_ +#define EMC_DYNCONFIG_MD_SHIFT (3) /* Bits 3-4: Memory device */ +#define EMC_DYNCONFIG_MD_MASK (3 << EMC_DYNCONFIG_MD_SHIFT) +# define EMC_DYNCONFIG_MD(n) ((uint32_t)(n) << EMC_DYNCONFIG_MD_SHIFT) +# define EMC_DYNCONFIG_MD_SDRAM (0 << EMC_DYNCONFIG_MD_SHIFT) /* SDRAM */ +# define EMC_DYNCONFIG_MD_LPDRAM (1 << EMC_DYNCONFIG_MD_SHIFT) /* Low-power SDRAM */ +#define EMC_DYNCONFIG_AM0_SHIFT (7) /* Bits 7-12: See Table 656 in User Manual */ +#define EMC_DYNCONFIG_AM0_MASK (0x3f << EMC_DYNCONFIG_AM0_SHIFT) +# define EMC_DYNCONFIG_AM0(n) ((uint32_t)(n) << EMC_DYNCONFIG_AM0_SHIFT) +#define EMC_DYNCONFIG_AM1 (1 << 14) /* Bit 14: See Table 656 in User Manual */ +#define EMC_DYNCONFIG_B (1 << 19) /* Bit 19: Buffer enable */ +#define EMC_DYNCONFIG_P (1 << 20) /* Bit 20: Write protect */ + +#define EMC_DYNCONFIG_ADDRMAP_SHIFT EMC_DYNCONFIG_AM0_SHIFT +#define EMC_DYNCONFIG_ADDRMAP_MASK (EMC_DYNCONFIG_AM0_MASK | EMC_DYNCONFIG_AM1) +# define EMC_DYNCONFIG_ADDRMAP(n) ((uint32_t)(n) << EMC_DYNCONFIG_ADDRMAP_SHIFT) + +/* Dynamic Memory RAS and CAS Delay registers */ + +#define EMC_DYNRASCAS_RAS_SHIFT (0) /* Bits 0-1: RAS latency */ +#define EMC_DYNRASCAS_RAS_MASK (3 << EMC_DYNRASCAS_RAS_SHIFT) +# define EMC_DYNRASCAS_RAS(n) ((uint32_t)(n) << EMC_DYNRASCAS_RAS_SHIFT) +#define EMC_DYNRASCAS_CAS_SHIFT (8) /* Bits 8-9: CAS latency */ +#define EMC_DYNRASCAS_CAS_MASK (3 << EMC_DYNRASCAS_CAS_SHIFT) +# define EMC_DYNRASCAS_CAS(n) ((uint32_t)(n) << EMC_DYNRASCAS_CAS_SHIFT) + +/* Per-chip select static memory registers */ +/* Static Memory Configuration registers */ + +#define EMC_STATCONFIG_MW_SHIFT (0) /* Bits 0-1: Memory width */ +#define EMC_STATCONFIG_MW_MASK (3 << EMC_STATCONFIG_MW_SHIFT) +# define EMC_STATCONFIG_MW_8BIT (0 << EMC_STATCONFIG_MW_SHIFT) /* 8 bit */ +# define EMC_STATCONFIG_MW_16BIT (1 << EMC_STATCONFIG_MW_SHIFT) /* 16 bit */ +# define EMC_STATCONFIG_MW_32BIT (2 << EMC_STATCONFIG_MW_SHIFT) /* 32 bit */ +#define EMC_STATCONFIG_PM (1 << 3) /* Bit 3: Page mode */ +#define EMC_STATCONFIG_PC (1 << 6) /* Bit 6: Chip select polarity */ +#define EMC_STATCONFIG_PB (1 << 7) /* Bit 7: Byte lane state */ +#define EMC_STATCONFIG_EW (1 << 8) /* Bit 8: Extended wait */ +#define EMC_STATCONFIG_B (1 << 19) /* Bit 19: Buffer enable */ +#define EMC_STATCONFIG_P (1 << 20) /* Bit 20: Write protect */ + +/* Static Memory Write Enable Delay registers */ + +#define EMC_STATWAITWEN_SHIFT (0) /* Bits 0-3: Wait write enable */ +#define EMC_STATWAITWEN_MASK (15 << EMC_STATWAITWEN_SHIFT) +# define EMC_STATWAITWEN(n) ((uint32_t)((n)-1) << EMC_STATWAITWEN_SHIFT) + +/* Static Memory Output Enable delay registers */ + +#define EMC_STATWAITOEN_SHIFT (0) /* Bits 0-3: Wait output enable */ +#define EMC_STATWAITOEN_MASK (15 << EMC_STATWAITOEN_SHIFT) +# define EMC_STATWAITOEN_NONE (0 << EMC_STATWAITOEN_SHIFT) +# define EMC_STATWAITOEN(n) ((uint32_t)(n) << EMC_STATWAITOEN_SHIFT) + +/* Static Memory Read Delay registers */ + +#define EMC_STATWAITRD_SHIFT (0) /* Bits 0-4: Non-page mode read wait states */ +#define EMC_STATWAITRD_MASK (31 << EMC_STATWAITRD_SHIFT) +# define EMC_STATWAITRD(n) ((uint32_t)((n)-1) << EMC_STATWAITRD_SHIFT) + +/* Static Memory Page Mode Read Delay registers */ + +#define EMC_STATWAITPAGE_SHIFT (0) /* Bits 0-4: Page mode erad wait states */ +#define EMC_STATWAITPAGE_MASK (31 << EMC_STATWAITPAGE_SHIFT) +# define EMC_STATWAITPAGE(n) ((uint32_t)((n)-1) << EMC_STATWAITPAGE_SHIFT) + +/* Static Memory Write Delay registers */ + +#define EMC_STATWAITWR_SHIFT (0) /* Bits 0-4: Write wait states */ +#define EMC_STATWAITWR_MASK (31 << EMC_STATWAITWR_SHIFT) +# define EMC_STATWAITWR(n) ((uint32_t)((n)-2) << EMC_STATWAITWR_SHIFT) + +/* Static Memory Turn-around Delay registers */ + +#define EMC_STATWAITTURN_SHIFT (0) /* Bits 0-3: Bus turn-around cycles */ +#define EMC_STATWAITTURN_MASK (15 << EMC_STATWAITTURN_SHIFT) +# define EMC_STATWAITTURN(n) ((uint32_t)((n)-1) << EMC_STATWAITTURN_SHIFT) + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_EMC_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_ethernet.h b/arch/arm/src/lpc54xx/chip/lpc54_ethernet.h new file mode 100644 index 0000000000000000000000000000000000000000..12b282ea4a3df2b38010c65784aba341dd26bd53 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_ethernet.h @@ -0,0 +1,865 @@ +/************************************************************************************************************ + * arch/arm/src/lpc54xx/lpc54_ethernet.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_ETHERNET_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_ETHERNET_H + +/************************************************************************************************************ + * Included Files + ************************************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/************************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************************/ + +/* Register offsets *****************************************************************************************/ + +#define LPC54_ETH_MAC_CONFIG_OFFSET 0x0000 /* MAC configuration */ +#define LPC54_ETH_MAC_EXT_CONFIG_OFFSET 0x0004 /* MAC extended configuration */ +#define LPC54_ETH_MAC_FRAME_FILTER_OFFSET 0x0008 /* MAC frame filter */ +#define LPC54_ETH_MAC_WD_TIMEROUT_OFFSET 0x000c /* MAC watchdog timeout */ +#define LPC54_ETH_MAC_VLAN_TAG_OFFSET 0x0050 /* VLAN tag */ +#define LPC54_ETH_MAC_TX_FLOW_CTRL_Q0_OFFSET 0x0070 /* Transmit flow control 0 */ +#define LPC54_ETH_MAC_TX_FLOW_CTRL_Q1_OFFSET 0x0074 /* Transmit flow control 1 */ +#define LPC54_ETH_MAC_RX_FLOW_CTRL_OFFSET 0x0090 /* Receive flow control */ +#define LPC54_ETH_MAC_TXQ_PRIO_MAP_OFFSET 0x0098 /* Transmit Queue priority mapping */ +#define LPC54_ETH_MAC_RXQ_CTRL0_OFFSET 0x00a0 /* Receive Queue control 0 */ +#define LPC54_ETH_MAC_RXQ_CTRL1_OFFSET 0x00a4 /* Receive Queue control 1 */ +#define LPC54_ETH_MAC_RXQ_CTRL2_OFFSET 0x00a8 /* Receive Queue control 2 */ +#define LPC54_ETH_MAC_INTR_STAT_OFFSET 0x00b0 /* Interrupt status */ +#define LPC54_ETH_MAC_INTR_EN_OFFSET 0x00b4 /* Interrupt enable */ +#define LPC54_ETH_MAC_RXTX_STAT_OFFSET 0x00b8 /* Receive transmit status */ +#define LPC54_ETH_MAC_PMT_CRTL_STAT_OFFSET 0x00c0 /* MAC PMT control and status */ +#define LPC54_ETH_MAC_RWK_PKT_FLT_OFFSET 0x00c4 /* Wake-up packet filter */ +#define LPC54_ETH_MAC_LPI_CTRL_STAT_OFFSET 0x00d0 /* LPI control and status */ +#define LPC54_ETH_MAC_LPI_TIMER_CTRL_OFFSET 0x00d4 /* LPI timers control */ +#define LPC54_ETH_MAC_LPI_ENTR_TIMR_OFFSET 0x00d8 /* LPI entry timer */ +#define LPC54_ETH_MAC_1US_TIC_COUNTR_OFFSET 0x00dc /* MAC 1 usec tick counter */ +#define LPC54_ETH_MAC_VERSION_OFFSET 0x0110 /* MAC version */ +#define LPC54_ETH_MAC_DBG_OFFSET 0x0114 /* MAC debug */ +#define LPC54_ETH_MAC_HW_FEAT0_OFFSET 0x011c /* MAC hardware feature 0 */ +#define LPC54_ETH_MAC_HW_FEAT1_OFFSET 0x0120 /* MAC hardware feature 1 */ +#define LPC54_ETH_MAC_HW_FEAT2_OFFSET 0x0124 /* MAC hardware feature 2 */ + +#define LPC54_ETH_MAC_MDIO_ADDR_OFFSET 0x0200 /* MIDO address */ +#define LPC54_ETH_MAC_MDIO_DATA_OFFSET 0x0204 /* MDIO data */ +#define LPC54_ETH_MAC_ADDR_HIGH_OFFSET 0x0300 /* MAC address0 high */ +#define LPC54_ETH_MAC_ADDR_LOW_OFFSET 0x0304 /* MAC address0 low */ + +#define LPC54_ETH_MAC_TIMESTAMP_CTRL_OFFSET 0x0b00 /* Timestamp control */ +#define LPC54_ETH_MAC_SUB_SCND_INCR_OFFSET 0x0b04 /* Sub-second increment */ +#define LPC54_ETH_MAC_SYS_TIME_SCND_OFFSET 0x0b08 /* System time seconds */ +#define LPC54_ETH_MAC_SYS_TIME_NSCND_OFFSET 0x0b0c /* System time nanoseconds */ +#define LPC54_ETH_MAC_SYS_TIME_SCND_UPD_OFFSET 0x0b10 /* System time seconds update */ +#define LPC54_ETH_MAC_SYS_TIME_NSCND_UPD_OFFSET 0x0b14 /* System time nanoseconds update */ +#define LPC54_ETH_MAC_SYS_TIMESTMP_ADDEND_OFFSET 0x0b18 /* Timestamp addend */ +#define LPC54_ETH_MAC_SYS_TIME_HWORD_SCND_OFFSET 0x0b1c /* System time-higher word seconds */ +#define LPC54_ETH_MAC_SYS_TIMESTMP_STAT_OFFSET 0x0b20 /* Timestamp status */ +#define LPC54_ETH_MAC_Tx_TIMESTAMP_STATUS_NSECS_OFFSET 0x0b30 /* Tx timestamp status nanoseconds */ +#define LPC54_ETH_MAC_Tx_TIMESTAMP_STATUS_SECS_OFFSET 0x0b34 /* Tx timestamp status seconds */ +#define LPC54_ETH_MAC_TIMESTAMP_INGRESS_CORR_NSEC_OFFSET 0x0b58 /* Timestamp ingress correction */ +#define LPC54_ETH_MAC_TIMESTAMP_EGRESS_CORR_NSEC_OFFSET 0x0b5c /* Timestamp egress correction */ + +#define LPC54_ETH_MTL_OP_MODE_OFFSET 0x0c00 /* MTL operation mode */ +#define LPC54_ETH_MTL_INTR_STAT_OFFSET 0x0c20 /* MTL interrupt status */ +#define LPC54_ETH_MTL_RXQ_DMA_MAP_OFFSET 0x0c30 /* MTL Rx Queue and DMA channel mapping */ + +#define LPC54_ETH_MTL_Qn_OFFSET(n) (0x0d00 + ((n) << 6)) + +#define LPC54_ETH_MTL_TXQ_OP_MODE_OFFSET 0x0000 /* MTL TxQn operation mode */ +#define LPC54_ETH_MTL_TXQ_UNDRFLW_OFFSET 0x0004 /* MTL TxQn underflow */ +#define LPC54_ETH_MTL_TXQ_DBG_OFFSET 0x0008 /* MTL TxQn debug */ +#define LPC54_ETH_MTL_TXQ_ETS_CTRL_OFFSET 0x0010 /* MTL TxQ1 (only) ETS control */ +#define LPC54_ETH_MTL_TXQ_ETS_STAT_OFFSET 0x0014 /* MTL TxQn ETS status */ +#define LPC54_ETH_MTL_TXQ_QNTM_WGHT_OFFSET 0x0018 /* MTL TxQn idleSlopeCredit, quantum or weights */ +#define LPC54_ETH_MTL_TXQ_SNDSLP_CRDT_OFFSET 0x001c /* MTL TxQ1 (only) SendSlopCredit */ +#define LPC54_ETH_MTL_TXQ_HI_CRDT_OFFSET 0x0020 /* MTL TxQ1 (only) hiCredit */ +#define LPC54_ETH_MTL_TXQ_LO_CRDT_OFFSET 0x0024 /* MTL TxQ1 (only) loCredit */ +#define LPC54_ETH_MTL_TXQ_INTCTRL_STAT_OFFSET 0x002c /* MTL TxQn interrupt control status */ +#define LPC54_ETH_MTL_RXQ_OP_MODE_OFFSET 0x0030 /* MTL RxQn operation mode */ +#define LPC54_ETH_MTL_RXQ_MISSPKT_OVRFLW_CNT_OFFSET 0x0034 /* MTL RxQn missed packet overflow counter */ +#define LPC54_ETH_MTL_RXQ_DBG_OFFSET 0x0038 /* MTL RxQn debug */ +#define LPC54_ETH_MTL_RXQ_CTRL_OFFSET 0x003c /* MTL RxQn control */ + +#define LPC54_ETH_DMA_MODE_OFFSET 0x1000 /* DMA mode */ +#define LPC54_ETH_DMA_SYSBUS_MODE_OFFSET 0x1004 /* DMA system bus mode */ +#define LPC54_ETH_DMA_INTR_STAT_OFFSET 0x1008 /* DMA interrupt status */ +#define LPC54_ETH_DMA_DBG_STAT_OFFSET 0x100c /* DMA debug status */ + +#define LPC54_ETH_DMACH_OFFSET(n) (0x1100 + ((n) << 7)) + +#define LPC54_ETH_DMACH_CTRL_OFFSET 0x0000 /* DMA channel n control */ +#define LPC54_ETH_DMACH_TX_CTRL_OFFSET 0x0004 /* DMA channel n transmit control */ +#define LPC54_ETH_DMACH_RX_CTRL_OFFSET 0x0008 /* DMA channel n receive control */ +#define LPC54_ETH_DMACH_TXDESC_LIST_ADDR_OFFSET 0x0014 /* DMA channel n Tx descriptor list address */ +#define LPC54_ETH_DMACH_RXDESC_LIST_ADDR_OFFSET 0x001c /* DMA channel n Rx descriptor list address */ +#define LPC54_ETH_DMACH_TXDESC_TAIL_PTR_OFFSET 0x0020 /* DMA channel n Tx descriptor tail pointer */ +#define LPC54_ETH_DMACH_RXDESC_TAIL_PTR_OFFSET 0x0028 /* DMA channel n Rx descriptor tail pointer */ +#define LPC54_ETH_DMACH_TXDESC_RING_LENGTH_OFFSET 0x002c /* DMA channel n Tx descriptor ring length */ +#define LPC54_ETH_DMACH_RXDESC_RING_LENGTH_OFFSET 0x0030 /* DMA channel n Rx descriptor ring length */ +#define LPC54_ETH_DMACH_INT_EN_OFFSET 0x0034 /* DMA channel n interrupt enable */ +#define LPC54_ETH_DMACH_RX_INT_WDTIMER_OFFSET 0x0038 /* DMA channel n receive interrupt watchdog timer */ +#define LPC54_ETH_DMACH_SLOT_FUNC_CTRL_STAT_OFFSET 0x003c /* DMA channel n slot function control and status */ +#define LPC54_ETH_DMACH_CUR_HST_TXDESC_OFFSET 0x0044 /* DMA channel n current host transmit descriptor */ +#define LPC54_ETH_DMACH_CUR_HST_RXDESC_OFFSET 0x004c /* DMA channel n current host receive descriptor */ +#define LPC54_ETH_DMACH_CUR_HST_TXBUF_OFFSET 0x0054 /* DMA channel n current host transmit buffer address */ +#define LPC54_ETH_DMACH_CUR_HST_RXBUF_OFFSET 0x005c /* DMA channel n current application receive buffer address */ +#define LPC54_ETH_DMACH_STAT_OFFSET 0x0060 /* DMA channel n DMA status */ +#define LPC54_ETH_DMACH_MISS_FRAME_CNT_OFFSET 0x006c /* DMA channel n missed frame count */ + +/* Register addresses ***************************************************************************************/ + +#define LPC54_ETH_MAC_CONFIG (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_CONFIG_OFFSET) +#define LPC54_ETH_MAC_EXT_CONFIG (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_EXT_CONFIG_OFFSET) +#define LPC54_ETH_MAC_FRAME_FILTER (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_FRAME_FILTER_OFFSET) +#define LPC54_ETH_MAC_WD_TIMEROUT (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_WD_TIMEROUT_OFFSET) +#define LPC54_ETH_MAC_VLAN_TAG (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_VLAN_TAG_OFFSET) +#define LPC54_ETH_MAC_TX_FLOW_CTRL_Q0 (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_TX_FLOW_CTRL_Q0_OFFSET) +#define LPC54_ETH_MAC_TX_FLOW_CTRL_Q1 (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_TX_FLOW_CTRL_Q1_OFFSET) +#define LPC54_ETH_MAC_RX_FLOW_CTRL (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_RX_FLOW_CTRL_OFFSET) +#define LPC54_ETH_MAC_TXQ_PRIO_MAP (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_TXQ_PRIO_MAP_OFFSET) +#define LPC54_ETH_MAC_RXQ_CTRL0 (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_RXQ_CTRL0_OFFSET) +#define LPC54_ETH_MAC_RXQ_CTRL1 (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_RXQ_CTRL1_OFFSET) +#define LPC54_ETH_MAC_RXQ_CTRL2 (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_RXQ_CTRL2_OFFSET) +#define LPC54_ETH_MAC_INTR_STAT (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_INTR_STAT_OFFSET) +#define LPC54_ETH_MAC_INTR_EN (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_INTR_EN_OFFSET) +#define LPC54_ETH_MAC_RXTX_STAT (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_RXTX_STAT_OFFSET) +#define LPC54_ETH_MAC_PMT_CRTL_STAT (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_PMT_CRTL_STAT_OFFSET) +#define LPC54_ETH_MAC_RWK_PKT_FLT (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_RWK_PKT_FLT_OFFSET) +#define LPC54_ETH_MAC_LPI_CTRL_STAT (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_LPI_CTRL_STAT_OFFSET) +#define LPC54_ETH_MAC_LPI_TIMER_CTRL (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_LPI_TIMER_CTRL_OFFSET) +#define LPC54_ETH_MAC_LPI_ENTR_TIMR (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_LPI_ENTR_TIMR_OFFSET) +#define LPC54_ETH_MAC_1US_TIC_COUNTR (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_1US_TIC_COUNTR_OFFSET) +#define LPC54_ETH_MAC_VERSION (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_VERSION_OFFSET) +#define LPC54_ETH_MAC_DBG (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_DBG_OFFSET) +#define LPC54_ETH_MAC_HW_FEAT0 (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_HW_FEAT0_OFFSET) +#define LPC54_ETH_MAC_HW_FEAT1 (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_HW_FEAT1_OFFSET) +#define LPC54_ETH_MAC_HW_FEAT2 (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_HW_FEAT2_OFFSET) + +#define LPC54_ETH_MAC_MDIO_ADDR (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_MDIO_ADDR_OFFSET) +#define LPC54_ETH_MAC_MDIO_DATA (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_MDIO_DATA_OFFSET) +#define LPC54_ETH_MAC_ADDR_HIGH (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_ADDR_HIGH_OFFSET) +#define LPC54_ETH_MAC_ADDR_LOW (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_ADDR_LOW_OFFSET) + +#define LPC54_ETH_MAC_TIMESTAMP_CTRL (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_TIMESTAMP_CTRL_OFFSET) +#define LPC54_ETH_MAC_SUB_SCND_INCR (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_SUB_SCND_INCR_OFFSET) +#define LPC54_ETH_MAC_SYS_TIME_SCND (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_SYS_TIME_SCND_OFFSET) +#define LPC54_ETH_MAC_SYS_TIME_NSCND (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_SYS_TIME_NSCND_OFFSET) +#define LPC54_ETH_MAC_SYS_TIME_SCND_UPD (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_SYS_TIME_SCND_UPD_OFFSET) +#define LPC54_ETH_MAC_SYS_TIME_NSCND_UPD (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_SYS_TIME_NSCND_UPD_OFFSET) +#define LPC54_ETH_MAC_SYS_TIMESTMP_ADDEND (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_SYS_TIMESTMP_ADDEND_OFFSET) +#define LPC54_ETH_MAC_SYS_TIME_HWORD_SCND (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_SYS_TIME_HWORD_SCND_OFFSET) +#define LPC54_ETH_MAC_SYS_TIMESTMP_STAT (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_SYS_TIMESTMP_STAT_OFFSET) +#define LPC54_ETH_MAC_Tx_TIMESTAMP_STATUS_NSECS (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_Tx_TIMESTAMP_STATUS_NSECS_OFFSET) +#define LPC54_ETH_MAC_Tx_TIMESTAMP_STATUS_SECS (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_Tx_TIMESTAMP_STATUS_SECS_OFFSET) +#define LPC54_ETH_MAC_TIMESTAMP_INGRESS_CORR_NSEC (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_TIMESTAMP_INGRESS_CORR_NSEC_OFFSET) +#define LPC54_ETH_MAC_TIMESTAMP_EGRESS_CORR_NSEC (LPC54_ETHERNET_BASE + LPC54_ETH_MAC_TIMESTAMP_EGRESS_CORR_NSEC_OFFSET) + +#define LPC54_ETH_MTL_OP_MODE (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_OP_MODE_OFFSET) +#define LPC54_ETH_MTL_INTR_STAT (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_INTR_STAT_OFFSET) +#define LPC54_ETH_MTL_RXQ_DMA_MAP (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_RXQ_DMA_MAP_OFFSET) + +#define LPC54_ETH_MTL_Q_BASE(n) (LPC54_ETHERNET_BASE + LPC54_ETH_MTL_Qn_OFFSET(n)) + +#define LPC54_ETH_MTL_TXQ_OP_MODE(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_OP_MODE_OFFSET) +#define LPC54_ETH_MTL_TXQ_UNDRFLW(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_UNDRFLW_OFFSET) +#define LPC54_ETH_MTL_TXQ_DBG(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_DBG_OFFSET) +#define LPC54_ETH_MTL_TXQ_ETS_CTRL(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_ETS_CTRL_OFFSET) +#define LPC54_ETH_MTL_TXQ_ETS_STAT(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_ETS_STAT_OFFSET) +#define LPC54_ETH_MTL_TXQ_QNTM_WGHT(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_QNTM_WGHT_OFFSET) +#define LPC54_ETH_MTL_TXQ_SNDSLP_CRDT(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_SNDSLP_CRDT_OFFSET) +#define LPC54_ETH_MTL_TXQ_HI_CRDT(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_HI_CRDT_OFFSET) +#define LPC54_ETH_MTL_TXQ_LO_CRDT(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_LO_CRDT_OFFSET) +#define LPC54_ETH_MTL_TXQ_INTCTRL_STAT(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_TXQ_INTCTRL_STAT_OFFSET) +#define LPC54_ETH_MTL_RXQ_OP_MODE(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_RXQ_OP_MODE_OFFSET) +#define LPC54_ETH_MTL_RXQ_MISSPKT_OVRFLW_CNT(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_RXQ_MISSPKT_OVRFLW_CNT_OFFSET) +#define LPC54_ETH_MTL_RXQ_DBG(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_RXQ_DBG_OFFSET) +#define LPC54_ETH_MTL_RXQ_CTRL(n) (LPC54_ETH_MTL_Q_BASE(n) + LPC54_ETH_MTL_RXQ_CTRL_OFFSET) + +#define LPC54_ETH_DMA_MODE (LPC54_ETHERNET_BASE + LPC54_ETH_DMA_MODE_OFFSET) +#define LPC54_ETH_DMA_SYSBUS_MODE (LPC54_ETHERNET_BASE + LPC54_ETH_DMA_SYSBUS_MODE_OFFSET) +#define LPC54_ETH_DMA_INTR_STAT (LPC54_ETHERNET_BASE + LPC54_ETH_DMA_INTR_STAT_OFFSET) +#define LPC54_ETH_DMA_DBG_STAT (LPC54_ETHERNET_BASE + LPC54_ETH_DMA_DBG_STAT_OFFSET) + +#define LPC54_ETH_DMACH_BASE(n) (LPC54_ETHERNET_BASE + LPC54_ETH_DMACH_OFFSET(n)) + +#define LPC54_ETH_DMACH_CTRL(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_CTRL_OFFSET) +#define LPC54_ETH_DMACH_TX_CTRL(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_TX_CTRL_OFFSET) +#define LPC54_ETH_DMACH_RX_CTRL(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_RX_CTRL_OFFSET) +#define LPC54_ETH_DMACH_TXDESC_LIST_ADDR(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_TXDESC_LIST_ADDR_OFFSET) +#define LPC54_ETH_DMACH_RXDESC_LIST_ADDR(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_RXDESC_LIST_ADDR_OFFSET) +#define LPC54_ETH_DMACH_TXDESC_TAIL_PTR(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_TXDESC_TAIL_PTR_OFFSET) +#define LPC54_ETH_DMACH_RXDESC_TAIL_PTR(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_RXDESC_TAIL_PTR_OFFSET) +#define LPC54_ETH_DMACH_TXDESC_RING_LENGTH(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_TXDESC_RING_LENGTH_OFFSET) +#define LPC54_ETH_DMACH_RXDESC_RING_LENGTH(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_RXDESC_RING_LENGTH_OFFSET) +#define LPC54_ETH_DMACH_INT_EN(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_INT_EN_OFFSET) +#define LPC54_ETH_DMACH_RX_INT_WDTIMER(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_RX_INT_WDTIMER_OFFSET) +#define LPC54_ETH_DMACH_SLOT_FUNC_CTRL_STAT(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_SLOT_FUNC_CTRL_STAT_OFFSET) +#define LPC54_ETH_DMACH_CUR_HST_TXDESC(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_CUR_HST_TXDESC_OFFSET) +#define LPC54_ETH_DMACH_CUR_HST_RXDESC(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_CUR_HST_RXDESC_OFFSET) +#define LPC54_ETH_DMACH_CUR_HST_TXBUF(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_CUR_HST_TXBUF_OFFSET) +#define LPC54_ETH_DMACH_CUR_HST_RXBUF(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_CUR_HST_RXBUF_OFFSET) +#define LPC54_ETH_DMACH_STAT(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_STAT_OFFSET) +#define LPC54_ETH_DMACH_MISS_FRAME_CNT(n) (LPC54_ETH_DMACH_BASE(n) + LPC54_ETH_DMACH_MISS_FRAME_CNT_OFFSET) + +/* Register bit definitions *********************************************************************************/ + +/* MAC configuration */ + +#define ETH_MAC_CONFIG_RE (1 << 0) /* Bit 0: Receiver enable */ +#define ETH_MAC_CONFIG_TE (1 << 1) /* Bit 1: Transmitter enable */ +#define ETH_MAC_CONFIG_PRELEN_SHIFT (2) /* Bits 2-3: Preamble length for transmit packets */ +#define ETH_MAC_CONFIG_PRELEN_MASK (3 << ETH_MAC_CONFIG_PRELEN_SHIFT) +# define ETH_MAC_CONFIG_PRELEN_7 (0 << ETH_MAC_CONFIG_PRELEN_SHIFT) /* 7 bytes of preamble */ +# define ETH_MAC_CONFIG_PRELEN_5 (1 << ETH_MAC_CONFIG_PRELEN_SHIFT) /* 5 bytes of preamble */ +# define ETH_MAC_CONFIG_PRELEN_3 (2 << ETH_MAC_CONFIG_PRELEN_SHIFT) /* 3 bytes of preamble */ +#define ETH_MAC_CONFIG_DC (1 << 4) /* Bit 4: Deferral check */ +#define ETH_MAC_CONFIG_BL_SHIFT (5) /* Bits 5-6: Back-off limit */ +#define ETH_MAC_CONFIG_BL_MASK (3 << ETH_MAC_CONFIG_BL_SHIFT) +# define ETH_MAC_CONFIG_BL_10 (0 << ETH_MAC_CONFIG_BL_SHIFT) /* k = min (n, 10) */ +# define ETH_MAC_CONFIG_BL_8 (1 << ETH_MAC_CONFIG_BL_SHIFT) /* k = min (n, 8) */ +# define ETH_MAC_CONFIG_BL_4 (2 << ETH_MAC_CONFIG_BL_SHIFT) /* k = min (n, 4) */ +# define ETH_MAC_CONFIG_BL_1 (3 << ETH_MAC_CONFIG_BL_SHIFT) /* k = min (n, 1) */ +#define ETH_MAC_CONFIG_DR (1 << 8) /* Bit 8: Disable retry */ +#define ETH_MAC_CONFIG_DCRS (1 << 9) /* Bit 9: Disable carrier sense during transmission */ +#define ETH_MAC_CONFIG_DO (1 << 10) /* Bit 10: Disable receive own */ +#define ETH_MAC_CONFIG_ECRSFD (1 << 11) /* Bit 11: Enable carrier sense full-duplex mode before transmission */ +#define ETH_MAC_CONFIG_LM (1 << 12) /* Bit 12: Loopback mode */ +#define ETH_MAC_CONFIG_DM (1 << 13) /* Bit 13: Duplex mode */ +#define ETH_MAC_CONFIG_FES (1 << 14) /* Bit 14: Speed */ +#define ETH_MAC_CONFIG_PS (1 << 15) /* Bit 15: Port select */ +#define ETH_MAC_CONFIG_JE (1 << 16) /* Bit 16: Jumbo frame enable */ +#define ETH_MAC_CONFIG_JD (1 << 17) /* Bit 17: Jabber disable */ +#define ETH_MAC_CONFIG_BE (1 << 18) /* Bit 18: Packet burst enable */ +#define ETH_MAC_CONFIG_WD (1 << 19) /* Bit 19: Watchdog disable */ +#define ETH_MAC_CONFIG_ACS (1 << 20) /* Bit 20: Automatic pad or CRC stripping */ +#define ETH_MAC_CONFIG_CST (1 << 21) /* Bit 21: CRC stripping for type packets */ +#define ETH_MAC_CONFIG_S2KP (1 << 22) /* Bit 22: IEEE 802.3as support for 2K packets */ +#define ETH_MAC_CONFIG_GPSLCE (1 << 23) /* Bit 23: Giant packet size limit control enable */ +#define ETH_MAC_CONFIG_IPG_SHIFT (24) /* Bits 24-26: Inter-packet gap */ +#define ETH_MAC_CONFIG_IPG_MASK (7 << ETH_MAC_CONFIG_IPG_SHIFT) +# define ETH_MAC_CONFIG_IPG_96 (0 << ETH_MAC_CONFIG_IPG_SHIFT) /* 96 bit times */ +# define ETH_MAC_CONFIG_IPG_88 (1 << ETH_MAC_CONFIG_IPG_SHIFT) /* 88 bit times */ +# define ETH_MAC_CONFIG_IPG_80 (2 << ETH_MAC_CONFIG_IPG_SHIFT) /* 80 bit times */ +# define ETH_MAC_CONFIG_IPG_72 (3 << ETH_MAC_CONFIG_IPG_SHIFT) /* 72 bit times */ +# define ETH_MAC_CONFIG_IPG_64 (4 << ETH_MAC_CONFIG_IPG_SHIFT) /* 64 bit times */ +# define ETH_MAC_CONFIG_IPG_56 (5 << ETH_MAC_CONFIG_IPG_SHIFT) /* 56 bit times */ +# define ETH_MAC_CONFIG_IPG_48 (6 << ETH_MAC_CONFIG_IPG_SHIFT) /* 48 bit times */ +# define ETH_MAC_CONFIG_IPG_40 (7 << ETH_MAC_CONFIG_IPG_SHIFT) /* 40 bit times */ +#define ETH_MAC_CONFIG_IPC (1 << 27) /* Bit 27: Checksum offload */ + +/* MAC extended configuration */ +#define ETH_MAC_EXT_CONFIG_ + +/* MAC frame filter */ + +#define ETH_MAC_FRAME_FILTER_PR (1 << 0) /* Bit 0: Promiscuous mode */ +#define ETH_MAC_FRAME_FILTER_DAIF (1 << 3) /* Bit 3: DA inverse filtering */ +#define ETH_MAC_FRAME_FILTER_PM (1 << 4) /* Bit 4: Pass all multicast */ +#define ETH_MAC_FRAME_FILTER_DBF (1 << 5) /* Bit 5: Disable broadcast frames */ +#define ETH_MAC_FRAME_FILTER_PCF_SHIFT (6) /* Bits 6-7: Pass control frames */ +#define ETH_MAC_FRAME_FILTER_PCF_MASK (3 << ETH_MAC_FRAME_FILTER_PCF_SHIFT) +# define ETH_MAC_FRAME_FILTER_PCF_NONE (0 << ETH_MAC_FRAME_FILTER_PCF_SHIFT) /* All control frames filtered */ +# define ETH_MAC_FRAME_FILTER_PCF_PAUSE (1 << ETH_MAC_FRAME_FILTER_PCF_SHIFT) /* All but pause control frames accepted */ +# define ETH_MAC_FRAME_FILTER_PCF_ALL (2 << ETH_MAC_FRAME_FILTER_PCF_SHIFT) /* All control frames accepted */ +# define ETH_MAC_FRAME_FILTER_PCF_FILTERED (3 << ETH_MAC_FRAME_FILTER_PCF_SHIFT) /* Control frames accepted if pass the address filter */ +#define ETH_MAC_FRAME_FILTER_SAIF (1 << 8) /* Bit 8: SA inverse filtering */ +#define ETH_MAC_FRAME_FILTER_SAF (1 << 9) /* Bit 9: Source address filter enable */ +#define ETH_MAC_FRAME_FILTER_RA (1 << 31) /* Bit 31: Receive all */ + +/* MAC watchdog timeout */ +#define ETH_MAC_WD_TIMEROUT_ +/* VLAN tag */ +#define ETH_MAC_VLAN_TAG_ + +/* Transmit flow control 0/1 */ + +#define ETH_MAC_TX_FLOW_CTRL_Q_FCB (1 << 0) /* Bit 0: Flow control busy/backpressure activate */ +#define ETH_MAC_TX_FLOW_CTRL_Q_TFE (1 << 1) /* Bit 1: Transmit flow control enable */ +#define ETH_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4) /* Bits 4-6: Pause low threshold */ +#define ETH_MAC_TX_FLOW_CTRL_Q_PLT_MASK (7 << ETH_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT) +# define ETH_MAC_TX_FLOW_CTRL_Q_PLT(n) ((uint32_t)(n) << ETH_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT) +#define ETH_MAC_TX_FLOW_CTRL_Q_DZPQ (1 << 7) /* Bit 7: Disable zero-quanta pause */ +#define ETH_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16) /* Bits 16-31: Pause time */ +#define ETH_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xffff << ETH_MAC_TX_FLOW_CTRL_Q_PT_SHIFT) +# define ETH_MAC_TX_FLOW_CTRL_Q_PT(n) ((uint32_t)(n) << ETH_MAC_TX_FLOW_CTRL_Q_PT_SHIFT) + +/* Receive flow control */ + +#define ETH_MAC_RX_FLOW_CTRL_RFE (1 << 0) /* Bit 0: Receive flow control enable */ +#define ETH_MAC_RX_FLOW_CTRL_UP (1 << 1) /* Bit 1: Unicast pause packet detect */ + +/* Transmit Queue priority mapping */ + +#define ETH_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT (0) /* Bits 0-7: Priorities selected in Tx Queue 0 */ +#define ETH_MAC_TXQ_PRIO_MAP_PSTQ0_MASK (0xff << ETH_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT) +# define ETH_MAC_TXQ_PRIO_MAP_PSTQ0(n) ((uint32_t)(n) << ETH_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT) +#define ETH_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT (8) /* Bits 8-15: Priorities selected in Tx Queue 1 */ +#define ETH_MAC_TXQ_PRIO_MAP_PSTQ1_MASK (0xff << ETH_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT) +# define ETH_MAC_TXQ_PRIO_MAP_PSTQ1(n) ((uint32_t)(n) << ETH_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT) + +/* Receive Queue control 0 */ + +#define ETH_MAC_RXQ_CTRL0_RXQ0EN_SHIFT (0) /* Bits 0-1: Rx Queue 0 enable */ +#define ETH_MAC_RXQ_CTRL0_RXQ0EN_MASK (3 << ETH_MAC_RXQ_CTRL0_RXQ0EN_SHIFT) +# define ETH_MAC_RXQ_CTRL0_RXQ0EN_DISABLE (0 << ETH_MAC_RXQ_CTRL0_RXQ0EN_SHIFT) /* Disable */ +# define ETH_MAC_RXQ_CTRL0_RXQ0EN_ENABLE (1 << ETH_MAC_RXQ_CTRL0_RXQ0EN_SHIFT) /* Queue 0 enabled for AV */ +#define ETH_MAC_RXQ_CTRL0_RXQ1EN_SHIFT (2) /* Bits 2-3: Rx Queue 1 enable */ +#define ETH_MAC_RXQ_CTRL0_RXQ1EN_MASK (3 << ETH_MAC_RXQ_CTRL0_RXQ1EN_SHIFT) +# define ETH_MAC_RXQ_CTRL0_RXQ1EN_DISABLE (0 << ETH_MAC_RXQ_CTRL0_RXQ1EN_SHIFT) /* Disable */ +# define ETH_MAC_RXQ_CTRL0_RXQ1EN_ENABLE (1 << ETH_MAC_RXQ_CTRL0_RXQ1EN_SHIFT) /* Queue 1 enabled for AV */ + +/* Receive Queue control 1 */ + +#define ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT (0) /* Bits 0-2: AV untagged control packets queue */ +#define ETH_MAC_RXQ_CTRL1_AVCPQ_MASK (7 < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT) +# define ETH_MAC_RXQ_CTRL1_AVCPQ(n) ((uint32_t)(n) < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT) /* Rx Queue n, n=0..1 */ +#define ETH_MAC_RXQ_CTRL1_AVPTPQ_SHIFT (4) /* Bits 4-6: AV PTP packets queue */ +#define ETH_MAC_RXQ_CTRL1_AVPTPQ_MASK (7 < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT) +# define ETH_MAC_RXQ_CTRL1_AVPTPQ(n) ((uint32_t)(n) < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT) /* Rx Queue n, n=0..1 */ +#define ETH_MAC_RXQ_CTRL1_UPQ_SHIFT (12) /* Bits 12-14: Untagged packet queue */ +#define ETH_MAC_RXQ_CTRL1_UPQ_MASK (7 < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT) +# define ETH_MAC_RXQ_CTRL1_UPQ(n) ((uint32_t)(n) < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT) /* Rx Queue n, n=0..1 */ +#define ETH_MAC_RXQ_CTRL1_MCBCQ_SHIFT (16) /* Bits 16-18: Multicast and broadcast queue */ +#define ETH_MAC_RXQ_CTRL1_MCBCQ_MASK (7 < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT) +# define ETH_MAC_RXQ_CTRL1_MCBCQ(n) ((uint32_t)(n) < ETH_MAC_RXQ_CTRL1_AVCPQ_SHIFT) /* Rx Queue n, n=0..1 */ +#define ETH_MAC_RXQ_CTRL1_MCBCQEN (1 << 20) /* Bit 20: Multicast and broadcast queue enable */ + +/* Receive Queue control 2 */ + +#define ETH_MAC_RXQ_CTRL2_PSRQ0_SHIFT (0) /* Bits 0-7: Priorities selected in the Rx Queue 0 */ +#define ETH_MAC_RXQ_CTRL2_PSRQ0_MASK (0xff << ETH_MAC_RXQ_CTRL2_PSRQ0_SHIFT) +# define ETH_MAC_RXQ_CTRL2_PSRQ0(n) ((uint32_t)(n) << ETH_MAC_RXQ_CTRL2_PSRQ0_SHIFT) +#define ETH_MAC_RXQ_CTRL2_PSRQ1_SHIFT (8) /* Bits 8-15: Priorities selected in the Rx Queue 1 */ +#define ETH_MAC_RXQ_CTRL2_PSRQ1_MASK (0xff << ETH_MAC_RXQ_CTRL2_PSRQ1_SHIFT) +# define ETH_MAC_RXQ_CTRL2_PSRQ1(n) ((uint32_t)(n) << ETH_MAC_RXQ_CTRL2_PSRQ1_SHIFT) +#define ETH_MAC_RXQ_CTRL2_PSRQ2_SHIFT (16) /* Bits 16-23: Priorities selected in the Rx Queue 2 */ +#define ETH_MAC_RXQ_CTRL2_PSRQ2_MASK (0xff << ETH_MAC_RXQ_CTRL2_PSRQ2_SHIFT) +# define ETH_MAC_RXQ_CTRL2_PSRQ2(n) ((uint32_t)(n) << ETH_MAC_RXQ_CTRL2_PSRQ2_SHIFT) +#define ETH_MAC_RXQ_CTRL2_PSRQ3_SHIFT (24) /* Bits 24-31: Priorities selected in the Rx Queue 3 */ +#define ETH_MAC_RXQ_CTRL2_PSRQ3_MASK (0xff << ETH_MAC_RXQ_CTRL2_PSRQ3_SHIFT) +# define ETH_MAC_RXQ_CTRL2_PSRQ3(n) ((uint32_t)(n) << ETH_MAC_RXQ_CTRL2_PSRQ3_SHIFT) + +/* Interrupt enable and interrupt status */ + +#define ETH_MAC_INTR_PHYI (1 << 3) /* Bit 3: PHY interrupt */ +#define ETH_MAC_INTR_PMTI (1 << 4) /* Bit 4: PMT interrupt */ +#define ETH_MAC_INTR_LPII (1 << 5) /* Bit 5: LPI interrupt */ +#define ETH_MAC_INTR_TSI (1 << 12) /* Bit 12: Timestamp interrupt */ +#define ETH_MAC_INTR_TXSTSI (1 << 13) /* Bit 13: Transmit status interrupt */ +#define ETH_MAC_INTR_RXSTSI (1 << 14) /* Bit 14: Receive status interrupt */ + +/* Receive transmit status */ +#define ETH_MAC_RXTX_STAT_ +/* MAC PMT control and status */ +#define ETH_MAC_PMT_CRTL_STAT_ +/* Wake-up packet filter */ +#define ETH_MAC_RWK_PKT_FLT_ +/* LPI control and status */ +#define ETH_MAC_LPI_CTRL_STAT_ +/* LPI timers control */ +#define ETH_MAC_LPI_TIMER_CTRL_ +/* LPI entry timer */ +#define ETH_MAC_LPI_ENTR_TIMR_ + +/* MAC 1 usec tick counter */ + +#define ETH_MAC_1US_TIC_COUNTR_SHIFT (0) /* Bits 0-11: 1uS TIC counter */ +#define ETH_MAC_1US_TIC_COUNTR_MASK (0xfff << ETH_MAC_1US_TIC_COUNTR_SHIFT) +# define ETH_MAC_1US_TIC_COUNTR(n) ((uint32_t)((n)-1) << ETH_MAC_1US_TIC_COUNTR_SHIFT) + +/* MAC version */ +#define ETH_MAC_VERSION_ +/* MAC debug */ +#define ETH_MAC_DBG_ +/* MAC hardware feature 0 */ +#define ETH_MAC_HW_FEAT0_ +/* MAC hardware feature 1 */ +#define ETH_MAC_HW_FEAT1_ +/* MAC hardware feature 2 */ +#define ETH_MAC_HW_FEAT2_ + +/* MIDO address */ + +#define ETH_MAC_MDIO_ADDR_MB (1 << 0) /* Bit 0 MII busy */ +#define ETH_MAC_MDIO_ADDR_MOC_SHIFT (2) /* Bits 2-3: MII operation command */ +#define ETH_MAC_MDIO_ADDR_MOC_MASK (3 << ETH_MAC_MDIO_ADDR_MOC_SHIFT) +# define ETH_MAC_MDIO_ADDR_MOC_WRITE (1 << ETH_MAC_MDIO_ADDR_MOC_SHIFT) /* Write */ +# define ETH_MAC_MDIO_ADDR_MOC_READ (3 << ETH_MAC_MDIO_ADDR_MOC_SHIFT) /* Read */ +#define ETH_MAC_MDIO_ADDR_CR_SHIFT (8) /* Bits 8-11: CSR clock range */ +#define ETH_MAC_MDIO_ADDR_CR_MASK (15 << ETH_MAC_MDIO_ADDR_CR_SHIFT) +# define ETH_MAC_MDIO_ADDR_CR_DIV42 (0 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=60-100 MHz; MDC=CSR/42 */ +# define ETH_MAC_MDIO_ADDR_CR_DIV62 (1 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=100-150 MHz; MDC=CSR/62 */ +# define ETH_MAC_MDIO_ADDR_CR_DIV16 (2 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=20-35 MHz; MDC=CSR/16 */ +# define ETH_MAC_MDIO_ADDR_CR_DIV26 (3 << ETH_MAC_MDIO_ADDR_CR_SHIFT) /* CSR=35-60 MHz; MDC=CSR/26 */ +#define ETH_MAC_MDIO_ADDR_NTC_SHIFT (12) /* Bits 12-14: Number of training clocks */ +#define ETH_MAC_MDIO_ADDR_NTC_MASK (7 << ETH_MAC_MDIO_ADDR_NTC_SHIFT) +# define ETH_MAC_MDIO_ADDR_NTC(n) ((uint32_t)(n) << ETH_MAC_MDIO_ADDR_NTC_SHIFT) +#define ETH_MAC_MDIO_ADDR_RDA_SHIFT (16) /* Bits 16-20: Register/device address */ +#define ETH_MAC_MDIO_ADDR_RDA_MASK (31 << ETH_MAC_MDIO_ADDR_RDA_SHIFT) +# define ETH_MAC_MDIO_ADDR_RDA(n) ((uint32_t)(n) << ETH_MAC_MDIO_ADDR_RDA_SHIFT) +#define ETH_MAC_MDIO_ADDR_PA_SHIFT (21) /* Bits 21-25: Physical layer address */ +#define ETH_MAC_MDIO_ADDR_PA_MASK (31 << ETH_MAC_MDIO_ADDR_PA_SHIFT) +# define ETH_MAC_MDIO_ADDR_PA(n) ((uint32_t)(n) << ETH_MAC_MDIO_ADDR_PA_SHIFT) +#define ETH_MAC_MDIO_ADDR_BTB (1 << 26) /* Bit 26 Back to back transactions */ +#define ETH_MAC_MDIO_ADDR_PSE (1 << 27) /* Bit 27 Preamble suppression enable */ + +/* MDIO data */ + +#define ETH_MAC_MDIO_DATA_MASK 0xffff /* Bits 0-15: 16 bit PHY data */ + +/* MAC address0 high */ + +#define ETH_MAC_ADDR_HIGH_A32_47_SHIFT (0) /* Bits 9-15: MAC address 32-47 */ +#define ETH_MAC_ADDR_HIGH_A32_47_MASK (0xffff << ETH_MAC_ADDR_HIGH_A32_47_SHIFT) +# define ETH_MAC_ADDR_HIGH_A32_47(n) ((uint32_t)(n) << ETH_MAC_ADDR_HIGH_A32_47_SHIFT) +#define ETH_MAC_ADDR_HIGH_DCS (1 << 16) /* Bit 16: DMA channel select */ + +/* MAC address0 low (32-bit MAC address 0-31) */ + +/* Timestamp control */ +#define ETH_MAC_TIMESTAMP_CTRL_ +/* Sub-second increment */ +#define ETH_MAC_SUB_SCND_INCR_ +/* System time seconds */ +#define ETH_MAC_SYS_TIME_SCND_ +/* System time nanoseconds */ +#define ETH_MAC_SYS_TIME_NSCND_ +/* System time seconds update */ +#define ETH_MAC_SYS_TIME_SCND_UPD_ +/* System time nanoseconds update */ +#define ETH_MAC_SYS_TIME_NSCND_UPD_ +/* Timestamp addend */ +#define ETH_MAC_SYS_TIMESTMP_ADDEND_ +/* System time-higher word seconds */ +#define ETH_MAC_SYS_TIME_HWORD_SCND_ +/* Timestamp status */ +#define ETH_MAC_SYS_TIMESTMP_STAT_ +/* Tx timestamp status nanoseconds */ +#define ETH_MAC_Tx_TIMESTAMP_STATUS_NSECS_ +/* Tx timestamp status seconds */ +#define ETH_MAC_Tx_TIMESTAMP_STATUS_SECS_ +/* Timestamp ingress correction */ +#define ETH_MAC_TIMESTAMP_INGRESS_CORR_NSEC_ +/* Timestamp egress correction */ +#define ETH_MAC_TIMESTAMP_EGRESS_CORR_NSEC_ + +/* MTL operation mode */ + +#define ETH_MTL_OP_MODE_DTXSTS (1 << 1) /* Bit 1: Drop transmit status */ +#define ETH_MTL_OP_MODE_RAA (1 << 1) /* Bit 2: Receive arbitration algorithm */ +# define ETH_MTL_OP_MODE_RAA_SP (0) /* Strict priority */ +# define ETH_MTL_OP_MODE_RAA_WSP (1 << 1) /* Weighted Strict Priority */ +#define ETH_MTL_OP_MODE_SHALG_SHIFT (5) /* Bits 5-6: Tx Scheduling Algorithm */ +#define ETH_MTL_OP_MODE_SHALG_MASK (3 << ETH_MTL_OP_MODE_SHALG_SHIFT) +# define ETH_MTL_OP_MODE_SHALG_SP (0 << ETH_MTL_OP_MODE_SHALG_SHIFT) /* Strict priority */ +# define ETH_MTL_OP_MODE_SHALG_WSP (3 << ETH_MTL_OP_MODE_SHALG_SHIFT) /* Weighted Strict */ + +/* MTL interrupt status */ +#define ETH_MTL_INTR_STAT_ + +/* MTL Rx Queue and DMA channel mapping */ + +#define ETH_MTL_RXQ_DMA_MAP_Q0MDMACH (1 << 0) /* Bit 0: Queue 0 mapped to DMA channel 1 */ +#define ETH_MTL_RXQ_DMA_MAP_Q0DDMACH (1 << 4) /* Bit 4: Queue 0 enabled for DA-based DMA channel selection */ +#define ETH_MTL_RXQ_DMA_MAP_Q1MDMACH (1 << 8) /* Bit 8: Queue 1 mapped to DMA channel 1 */ +#define ETH_MTL_RXQ_DMA_MAP_Q1DDMACH (1 << 12) /* Bit 12: Queue 1 enabled for DA-based DMA channel selection */ + +/* MTL TxQn operation mode */ + +#define ETH_MTL_TXQ_OP_MODE_FTQ (1 << 0) /* Bit 0: Flush Tx Queue */ +#define ETH_MTL_TXQ_OP_MODE_TSF (1 << 1) /* Bit 1: Transmit store and forward */ +#define ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT (2) /* Bits 2-3: Tx Queue enable */ +#define ETH_MTL_TXQ_OP_MODE_TXQEN_MASK (3 << ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT) +# define ETH_MTL_TXQ_OP_MODE_TXQEN_DISABLE (0 << ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT) /* Not enabled */ +# define ETH_MTL_TXQ_OP_MODE_TXQEN_ENABLE (2 << ETH_MTL_TXQ_OP_MODE_TXQEN_SHIFT) /* Enabled */ +#define ETH_MTL_TXQ_OP_MODE_TTC_SHIFT (4) /* Bits 4-6: Transmit threshold control */ +#define ETH_MTL_TXQ_OP_MODE_TTC_MASK (7 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT) +# define ETH_MTL_TXQ_OP_MODE_TTC_32 (0 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT) +# define ETH_MTL_TXQ_OP_MODE_TTC_64 (1 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT) +# define ETH_MTL_TXQ_OP_MODE_TTC_96 (2 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT) +# define ETH_MTL_TXQ_OP_MODE_TTC_128 (3 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT) +# define ETH_MTL_TXQ_OP_MODE_TTC_192 (4 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT) +# define ETH_MTL_TXQ_OP_MODE_TTC_256 (5 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT) +# define ETH_MTL_TXQ_OP_MODE_TTC_384 (6 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT) +# define ETH_MTL_TXQ_OP_MODE_TTC_512 (7 << ETH_MTL_TXQ_OP_MODE_TTC_SHIFT) +#define ETH_MTL_TXQ_OP_MODE_TQS_SHIFT (16) /* Bits 16-18: Tx Queue size (x256) */ +#define ETH_MTL_TXQ_OP_MODE_TQS_MASK (7 << ETH_MTL_TXQ_OP_MODE_TQS_SHIFT) +# define ETH_MTL_TXQ_OP_MODE_TQS(n) ((uint32_t)((n)-1) << ETH_MTL_TXQ_OP_MODE_TQS_SHIFT) + +/* MTL TxQn underflow */ +#define ETH_MTL_TXQ_UNDRFLW_ +/* MTL TxQn debug */ +#define ETH_MTL_TXQ_DBG_ +/* MTL TxQ1 (only) ETS control */ +#define ETH_MTL_TXQ1_ETS_CTRL_ +/* MTL TxQn ETS status */ +#define ETH_MTL_TXQ_ETS_STAT_ + +/* MTL TxQn idleSlopeCredit,quantum or weights */ + +#define ETH_MTL_TXQ_QNTM_WGHT_MASK 0x001fffff /* Bits 0-20: IdleSlopeCredit, quantum or weights */ + +/* MTL TxQ1 (only) SendSlopCredit */ +#define ETH_MTL_TXQ1_SNDSLP_CRDT_ +/* MTL TxQ1 (only) hiCredit */ +#define ETH_MTL_TXQ1_HI_CRDT_ +/* MTL TxQ1 (only) loCredit */ +#define ETH_MTL_TXQ1_LO_CRDT_ +/* MTL TxQn interrupt control status */ +#define ETH_MTL_TXQ_INTCTRL_STAT_ + +/* MTL RxQn operation mode */ + +#define ETH_MTL_RXQ_OP_MODE_RTC_SHIFT (0) /* Bits 0-1: Rx Queue threshold control */ +#define ETH_MTL_RXQ_OP_MODE_RTC_MASK (3 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT) +# define ETH_MTL_RXQ_OP_MODE_RTC_64 (0 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT) +# define ETH_MTL_RXQ_OP_MODE_RTC_32 (1 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT) +# define ETH_MTL_RXQ_OP_MODE_RTC_96 (2 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT) +# define ETH_MTL_RXQ_OP_MODE_RTC_128 (3 << ETH_MTL_RXQ_OP_MODE_RTC_SHIFT) +#define ETH_MTL_RXQ_OP_MODE_FUP (1 << 3) /* Bit 3 Forward undersized good packets */ +#define ETH_MTL_RXQ_OP_MODE_FEP (1 << 4) /* Bit 4 Forward error packets */ +#define ETH_MTL_RXQ_OP_MODE_RSF (1 << 5) /* Bit 5 Rx Queue store and forward */ +#define ETH_MTL_RXQ_OP_MODE_DIS_TCP_EF (1 << 6) /* Bit 6 Disable dropping of TCP/IP checksum error packets */ +#define ETH_MTL_RXQ_OP_MODE_RQS_SHIFT (20) /* Bits 20-22: Rx Queue size (x256) */ +#define ETH_MTL_RXQ_OP_MODE_RQS_MASK (7 << ETH_MTL_RXQ_OP_MODE_RQS_SHIFT) +# define ETH_MTL_RXQ_OP_MODE_RQS(n) ((uint32_t)((n)-1) << ETH_MTL_RXQ_OP_MODE_RQS_SHIFT) + +/* MTL RxQn missed packet overflow counter */ +#define ETH_MTL_RXQ_MISSPKT_OVRFLW_CNT_ +/* MTL RxQn debug */ +#define ETH_MTL_RXQ_DBG_ + +/* MTL RxQn control */ + +#define ETH_MTL_RXQ_CTRL_WEGT_SHIFT (0) /* Bits 0-2: Rx Queue weight */ +#define ETH_MTL_RXQ_CTRL_WEGT_MASK (7 << ETH_MTL_RXQ_CTRL_WEGT) +# define ETH_MTL_RXQ_CTRL_WEGT(n) ((uint32_t)(n) << ETH_MTL_RXQ_CTRL_WEGT) +#define ETH_MTL_RXQ_CTRL_FRM_ARBIT (1 << 3) /* Bit 3: Rx Queue packet arbitration */ + +/* DMA mode */ + +#define ETH_DMA_MODE_SWR (1 << 0) /* Bit 0: Software reset */ +#define ETH_DMA_MODE_DA_MASK (1 << 1) /* Bit 1: DMA Tx or Rx arbitration scheme */ +# define ETH_DMA_MODE_DA_WRR (0) /* Weighted round-robin with Rx:Tx or Tx:Rx */ +# define ETH_DMA_MODE_DA_FIXED (1 << 1) /* Fixed priority */ +#define ETH_DMA_MODE_TAA_SHIFT (2) /* Bits 2-4: Transmit arbitration algorithm */ +#define ETH_DMA_MODE_TAA_MASK (7 << ETH_DMA_MODE_TAA_SHIFT) +# define ETH_DMA_MODE_TAA_FIXED (0 << ETH_DMA_MODE_TAA_SHIFT) /* Fixed priority */ +# define ETH_DMA_MODE_TAA_WSP (1 << ETH_DMA_MODE_TAA_SHIFT) /* Weighted strict priority */ +# define ETH_DMA_MODE_TAA_WRR (2 << ETH_DMA_MODE_TAA_SHIFT) /* Weighted round-robin */ +#define ETH_DMA_MODE_TXPR (1 << 11) /* Bit 11: Transmit priority */ +#define ETH_DMA_MODE_PR_SHIFT (12) /* Bits 12-14: Priority ratio */ +#define ETH_DMA_MODE_PR_MASK (7 << ETH_DMA_MODE_PR_SHIFT) +# define ETH_DMA_MODE_PR_1TO1 (0 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 1:1 */ +# define ETH_DMA_MODE_PR_3TO1 (2 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 3:1 */ +# define ETH_DMA_MODE_PR_4TO1 (3 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 4:1 */ +# define ETH_DMA_MODE_PR_5TO1 (4 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 5:1 */ +# define ETH_DMA_MODE_PR_6TO1 (5 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 6:1 */ +# define ETH_DMA_MODE_PR_7TO1 (6 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 7:1 */ +# define ETH_DMA_MODE_PR_8TO1 (7 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 8:1 */ + +/* DMA system bus mode */ + +#define ETH_DMA_SYSBUS_MODE_FB (1 << 0) /* Bit 0: Fixed burst length */ +#define ETH_DMA_SYSBUS_MODE_AAL (1 << 12) /* Bit 12: Address-aligned beats */ +#define ETH_DMA_SYSBUS_MODE_MB (1 << 14) /* Bit 14: Mixed burst */ +#define ETH_DMA_SYSBUS_MODE_RB (1 << 15) /* Bit 15: Rebuild INCRx burst */ + +/* DMA interrupt status */ + +#define ETH_DMA_INTR_STAT_DC0IS (1 << 0) /* Bit 0: DMA channel 0 interrupt status */ +#define ETH_DMA_INTR_STAT_DC1IS (1 << 1) /* Bit 1: DMA channel 1 interrupt status */ +#define ETH_DMA_INTR_STAT_MTLIS (1 << 16) /* Bit 16: MTL interrupt status */ +#define ETH_DMA_INTR_STAT_MACIS (1 << 17) /* Bit 17: MAC interrupt status */ + +/* DMA debug status */ +#define ETH_DMA_DBG_STAT_ + +/* DMA channel n control */ + +#define ETH_DMACH_CTRL_PBLx8 (1 << 16) /* Bit 16: 8xPBL mode */ +#define ETH_DMACH_CTRL_DSL_SHIFT (18) /* Bits 18-20: Skip length */ + +/* DMA channel n transmit control */ + +#define ETH_DMACH_TX_CTRL_ST (1 << 0) /* Bit 0: Start or stop transmission command */ +#define ETH_DMACH_TX_CTRL_TCW_SHIFT (1) /* Bits 1-3: Transmit channel weight */ +#define ETH_DMACH_TX_CTRL_TCW_MASK (7 << ETH_DMACH_TX_CTRL_TCW_SHIFT) +# define ETH_DMACH_TX_CTRL_TCW(n) ((uint32_t)(n) << ETH_DMACH_TX_CTRL_TCW_SHIFT) +#define ETH_DMACH_TX_CTRL_OSF (1 << 4) /* Bit 4: Operate on second frame */ +#define ETH_DMACH_TX_CTRL_TxPBL_SHIFT (16) /* Bits 16-21: Transmit programmable burst length */ +#define ETH_DMACH_TX_CTRL_TxPBL_MASK (0x3f << ETH_DMACH_TX_CTRL_TxPBL_SHIFT) +# define ETH_DMACH_TX_CTRL_TxPBL(n) ((uint32_t)(n) << ETH_DMACH_TX_CTRL_TxPBL_SHIFT) + +/* DMA channel n receive control */ + +#define ETH_DMACH_RX_CTRL_SR (1 << 0) /* Bit 0: Start or stop receive command */ +#define ETH_DMACH_RX_CTRL_RBSZ_SHIFT (3) /* Bits 3-14: Receive buffer size */ +#define ETH_DMACH_RX_CTRL_RBSZ_MASK (0xfff << ETH_DMACH_RX_CTRL_RBSZ_SHIFT) +# define ETH_DMACH_RX_CTRL_RBSZ(n) ((uint32_t)(n) << ETH_DMACH_RX_CTRL_RBSZ_SHIFT) +#define ETH_DMACH_RX_CTRL_RxPBL_SHIFT (16) /* Bits 16-21: Receive programmable burst length */ +#define ETH_DMACH_RX_CTRL_RxPBL_MASK (0x3f << ETH_DMACH_RX_CTRL_RxPBL_SHIFT) +# define ETH_DMACH_RX_CTRL_RxPBL(n) ((uint32_t)(n) << ETH_DMACH_RX_CTRL_RxPBL_SHIFT) +#define ETH_DMACH_RX_CTRL_RPF (1 << 31) /* Bit 31: DMA Rx channel n packet flush */ + +/* DMA channel n Tx descriptor list address (32-bit, word-aligned address) */ +/* DMA channel n Rx descriptor list address (32-bit, word-aligned address) */ +/* DMA channel n Tx descriptor tail pointer (32-bit, word-aligned address) */ +/* DMA channel n Rx descriptor tail pointer (32-bit, word-aligned address) */ + +/* DMA channel n Tx descriptor ring length */ + +#define ETH_DMACH_TXDESC_RING_LENGTH_SHIFT (0) /* Bits 0-9: Transmit ring length */ +#define ETH_DMACH_TXDESC_RING_LENGTH_MASK (0x3ff << ETH_DMACH_TXDESC_RING_LENGTH_SHIFT) +# define ETH_DMACH_TXDESC_RING_LENGTH(n) ((uint32_t)((n)-1) << ETH_DMACH_TXDESC_RING_LENGTH_SHIFT) + +/* DMA channel n Rx descriptor ring length */ + +#define ETH_DMACH_RXDESC_RING_LENGTH_SHIFT (0) /* Bits 0-9: Receive ring length */ +#define ETH_DMACH_RXDESC_RING_LENGTH_MASK (0x3ff << ETH_DMACH_RXDESC_RING_LENGTH_SHIFT) +# define ETH_DMACH_RXDESC_RING_LENGTH(n) ((uint32_t)((n)-1) << ETH_DMACH_RXDESC_RING_LENGTH_SHIFT) + +/* DMA channel n interrupt enable and DMA channel n DMA status */ + +#define ETH_DMACH_INT_TI (1 << 0) /* Bit 0: Transmit interrupt */ +#define ETH_DMACH_INT_TS (1 << 1) /* Bit 1: Transmitter stopped */ +#define ETH_DMACH_INT_TBU (1 << 2) /* Bit 2: Transmit buffer unavailable */ +#define ETH_DMACH_INT_RI (1 << 6) /* Bit 6: Receive interrupt */ +#define ETH_DMACH_INT_RBU (1 << 7) /* Bit 7: Receive buffer unavailable */ +#define ETH_DMACH_INT_RS (1 << 8) /* Bit 8: Receiver stopped */ +#define ETH_DMACH_INT_RWT (1 << 9) /* Bit 9: Receive watchdog timeout */ +#define ETH_DMACH_INT_ETI (1 << 10) /* Bit 10: Early transmit interrupt */ +#define ETH_DMACH_INT_ERI (1 << 11) /* Bit 11: Early receive interrupt */ +#define ETH_DMACH_INT_FBE (1 << 12) /* Bit 12: Fatal bus error */ +#define ETH_DMACH_INT_AI (1 << 14) /* Bit 14: Abnormal interrupt summary */ +#define ETH_DMACH_INT_NI (1 << 15) /* Bit 15: Normal interrupt summary */ + +/* DMA channel n receive interrupt watchdog timer */ +#define ETH_DMACH_RX_INT_WDTIMER_ +/* DMA channel n slot function control and status */ +#define ETH_DMACH_SLOT_FUNC_CTRL_STAT_ +/* DMA channel n current host transmit descriptor */ +#define ETH_DMACH_CUR_HST_TXDESC_ +/* DMA channel n current host receive descriptor */ +#define ETH_DMACH_CUR_HST_RXDESC_ +/* DMA channel n current host transmit buffer address */ +#define ETH_DMACH_CUR_HST_TXBUF_ +/* DMA channel n current application receive buffer address */ +#define ETH_DMACH_CUR_HST_RXBUF_ + +/* DMA channel n missed frame count */ +#define ETH_DMACH_MISS_FRAME_CNT_ + +/* DMA descriptors ******************************************************************************************/ + +/* Receive descriptor (read-format) */ +/* RDES0: 32-bit address */ +/* RDES1: Reserved */ +/* RDES2: 32-bit address */ + +/* RDES3: */ + +#define ETH_RXDES3_BUF1V (1 << 24) /* Bit 24: Buffer 1 address valid */ +#define ETH_RXDES3_BUF2V (1 << 25) /* Bit 25: Buffer 1 address valid */ +#define ETH_RXDES3_IOC (1 << 30) /* Bit 30: Interrupt enabled on completion */ +#define ETH_RXDES3_OWN (1 << 31) /* Bit 31: Own bit */ + +/* Receive descriptor (writeback-format) */ +/* RDES0: Reserved */ + +/* RDES1: */ + +#define ETH_RXDES1_PT_SHIFT (0) /* Bits 0-2: Payload type */ +#define ETH_RXDES1_PT_MASK (7 << ETH_RXDES1_PT_SHIFT) +# define ETH_RXDES1_PT_UNKNOWN (0 << ETH_RXDES1_PT_SHIFT) /* Unknown */ +# define ETH_RXDES1_PT_UDP (1 << ETH_RXDES1_PT_SHIFT) /* UDP */ +# define ETH_RXDES1_PT_TCP (2 << ETH_RXDES1_PT_SHIFT) /* TCP */ +# define ETH_RXDES1_PT_ICMP (3 << ETH_RXDES1_PT_SHIFT) /* ICMP */ +# define ETH_RXDES1_PT_IGMP (4 << ETH_RXDES1_PT_SHIFT) /* IGMP */ +# define ETH_RXDES1_PT_AVUCP (5 << ETH_RXDES1_PT_SHIFT) /* AV untagged control packet */ +# define ETH_RXDES1_PT_AVTDP (6 << ETH_RXDES1_PT_SHIFT) /* AV tagged data packet */ +# define ETH_RXDES1_PT_AVTCP (7 << ETH_RXDES1_PT_SHIFT) /* AV tagged control packet */ +#define ETH_RXDES1_IPHE (1 << 3) /* Bit 3: IP header error */ +#define ETH_RXDES1_IPV4 (1 << 4) /* Bit 4: IPV4 header present */ +#define ETH_RXDES1_IPV6 (1 << 5) /* Bit 5: IPv6 header present */ +#define ETH_RXDES1_IPCB (1 << 6) /* Bit 6: IP checksum bypassed */ +#define ETH_RXDES1_IPCE (1 << 7) /* Bit 7: IP payload error */ +#define ETH_RXDES1_PMT_SHIFT (8) /* Bits 8-11: PTP message type */ +#define ETH_RXDES1_PMT_MASK (15 << ETH_RXDES1_PMT_SHIFT) +# define ETH_RXDES1_PMT_NONE (0 << ETH_RXDES1_PMT_SHIFT) /* No PTP message received */ +# define ETH_RXDES1_PMT_SYNC (1 << ETH_RXDES1_PMT_SHIFT) /* SYNC */ +# define ETH_RXDES1_PMT_FOLLOWUP (2 << ETH_RXDES1_PMT_SHIFT) /* Follow_Up */ +# define ETH_RXDES1_PMT_DELAYREQ (3 << ETH_RXDES1_PMT_SHIFT) /* Delay Req */ +# define ETH_RXDES1_PMT_DELAYRESP (4 << ETH_RXDES1_PMT_SHIFT) /* Delay Resp */ +# define ETH_RXDES1_PMT_PDELAYREQ (5 << ETH_RXDES1_PMT_SHIFT) /* Pdelay Req */ +# define ETH_RXDES1_PMT_PDELAYRESP (6 << ETH_RXDES1_PMT_SHIFT) /* Pdelay Resp */ +# define ETH_RXDES1_PMT_PDELAYFOLLOWUP (7 << ETH_RXDES1_PMT_SHIFT) /* Pdelay Resp follow-up */ +# define ETH_RXDES1_PMT_ANNOUNCE (8 << ETH_RXDES1_PMT_SHIFT) /* Announce */ +# define ETH_RXDES1_PMT_MGMNT (9 << ETH_RXDES1_PMT_SHIFT) /* Management */ +# define ETH_RXDES1_PMT_SIGNALING (10 << ETH_RXDES1_PMT_SHIFT) /* Signaling */ +# define ETH_RXDES1_PMT_RESERVERD (15 << ETH_RXDES1_PMT_SHIFT) /* Reserved message type */ +#define ETH_RXDES1_PFT (1 << 12) /* Bit 12: PTP packet type */ +#define ETH_RXDES1_PV (1 << 13) /* Bit 13: PTP version */ +#define ETH_RXDES1_TSA (1 << 14) /* Bit 14: Timestamp available */ +#define ETH_RXDES1_TD (1 << 15) /* Bit 15: Timestamp dropped */ +#define ETH_RXDES1_OPC_SHIFT (16) /* Bits 16-31: OAM sub-type code */ + +/* RXDES2: */ + +#define ETH_RXDES2_SAF (1 << 16) /* Bit 16: SA address filter fail */ +#define ETH_RXDES2_DAF (1 << 17) /* Bit 17: Destination address filter fail */ +#define ETH_RXDES2_MADRM_SHIFT (19) /* Bits 19-26: MAC address match */ +#define ETH_RXDES2_MADRM_MASK (0xff << ETH_RXDES2_MADRM_SHIFT) + +/* RXDES3: */ + +#define ETH_RXDES3_PL_SHIFT (0) /* Bits 0-14: Packet length */ +#define ETH_RXDES3_PL_MASK (0x7fff << ETH_RXDES3_PL_SHIFT) +#define ETH_RXDES3_ES (1 << 15) /* Bit 15: Error summary */ +#define ETH_RXDES3_LT_SHIFT (16) /* Bits 16-18: Length/type */ +#define ETH_RXDES3_LT_MASK (7 << ETH_RXDES3_LT_SHIFT) +# define ETH_RXDES3_LT_PKTLEN (0 << ETH_RXDES3_LT_SHIFT) /* Packet is a length packet */ +# define ETH_RXDES3_LT_PKTTYPE (1 << ETH_RXDES3_LT_SHIFT) /* Packet is a type packet */ +# define ETH_RXDES3_LT_ARPREQ (3 << ETH_RXDES3_LT_SHIFT) /* Packet is a ARP request packet type */ +# define ETH_RXDES3_LT_VLAN (4 << ETH_RXDES3_LT_SHIFT) /* Packet is a type packet with VLAN tag */ +# define ETH_RXDES3_LT_DVLAN (5 << ETH_RXDES3_LT_SHIFT) /* Packet is a type packet with double VLAN tag */ +# define ETH_RXDES3_LT_CTRLPKT (6 << ETH_RXDES3_LT_SHIFT) /* Packet is a MAC control packet type */ +# define ETH_RXDES3_LT_OAM (7 << ETH_RXDES3_LT_SHIFT) /* Packet is a OAM packet type */ +#define ETH_RXDES3_DE (1 << 19) /* Bit 19: Dribble bit error */ +#define ETH_RXDES3_RE (1 << 20) /* Bit 20: Receive error */ +#define ETH_RXDES3_OE (1 << 21) /* Bit 21: Overflow error */ +#define ETH_RXDES3_RWT (1 << 22) /* Bit 22: Receive watchdog timeout */ +#define ETH_RXDES3_GP (1 << 23) /* Bit 23: Giant packet */ +#define ETH_RXDES3_CE (1 << 24) /* Bit 24: CRC error */ +#define ETH_RXDES3_RS0V (1 << 25) /* Bit 25: Receive status RDES0 valid */ +#define ETH_RXDES3_RS1V (1 << 26) /* Bit 26: Receive status RDES1 valid */ +#define ETH_RXDES3_RS2V (1 << 27) /* Bit 27: Receive status RDES2 valid */ +#define ETH_RXDES3_LD (1 << 28) /* Bit 28: Last descriptor */ +#define ETH_RXDES3_FD (1 << 29) /* Bit 29: First descriptor */ +#define ETH_RXDES3_CTXT (1 << 30) /* Bit 30: Receive context descriptor */ + /* Bit 31: Own bit (see read-format) */ + +/* Transmit normal descriptor (read-format) */ +/* TDES0/1: 32-bit address */ + +/* TDES2: */ + +#define ETH_TXDES2_B1L_SHIFT (0) /* Bits 0-13: Buffer 1 length */ +#define ETH_TXDES2_B1L_MASK (0x3fff << ETH_TXDES2_B1L_SHIFT) +# define ETH_TXDES2_B1L(n) ((uint32_t)(n) << ETH_TXDES2_B1L_SHIFT) +#define ETH_TXDES2_B2L_SHIFT (16) /* Bits 16-29: Buffer 2 length */ +#define ETH_TXDES2_B2L_MASK (0x3fff << ETH_TXDES2_B2L_SHIFT) +# define ETH_TXDES2_B2L(n) ((uint32_t)(n) << ETH_TXDES2_B2L_SHIFT) +#define ETH_TXDES2_TTSE (1 << 30) /* Bit 30: Transmit timestamp enable */ +#define ETH_TXDES2_IOC (1 << 31) /* Bit 31: Interrupt on completion */ + +/* TDES3: */ + +#define ETH_TXDES3_FL_SHIFT (0) /* Bits 0-14: Frame length */ +#define ETH_TXDES3_FL_MASK (0x7fff << ETH_TXDES3_FL_SHIFT) +# define ETH_TXDES3_FL(n) ((uint32_t)(n) << ETH_TXDES3_FL_SHIFT) +#define ETH_TXDES3_CIC_SHIFT (16) /* Bits 16-17: Checksum insertion control */ +#define ETH_TXDES3_CIC_MASK (3 << ETH_TXDES3_CIC_SHIFT) +# define ETH_TXDES3_CIC_DISABLED (0 << ETH_TXDES3_CIC_SHIFT) /* Checksum insertion disabled */ +# define ETH_TXDES3_CIC_IPHDR (1 << ETH_TXDES3_CIC_SHIFT) /* Only IP header checksum */ +# define ETH_TXDES3_CIC_PAYLOAD (2 << ETH_TXDES3_CIC_SHIFT) /* IP header checksum and payload checksum */ +# define ETH_TXDES3_CIC_ALL (3 << ETH_TXDES3_CIC_SHIFT) /* IP Header checksum, payload, and pseudo-header checksum */ +#define ETH_TXDES3_SLOTNUM_SHIFT (19) /* Bits 19-22: Slot number control bits in AV mode */ +#define ETH_TXDES3_SLOTNUM_MASK (15 << ETH_TXDES3_SLOTNUM_SHIFT) +#define ETH_TXDES3_CPC_SHIFT (26) /* Bits 26-27: CRC pad control */ +#define ETH_TXDES3_CPC_MASK (3 << ETH_TXDES2_B1L_SHIFT) +# define ETH_TXDES3_CPC_CRCPAD (0 << ETH_TXDES2_B1L_SHIFT) /* CRC and pad insertion */ +# define ETH_TXDES3_CPC_CRC (1 << ETH_TXDES2_B1L_SHIFT) /* CRC insertion (disable pad insertion) */ +# define ETH_TXDES3_CPC_DISABLED (2 << ETH_TXDES2_B1L_SHIFT) /* Disable CRC insertion */ +# define ETH_TXDES3_CPC_REPLACMENT (3 << ETH_TXDES2_B1L_SHIFT) /* CRC replacement */ +#define ETH_TXDES3_LD (1 << 28) /* Bit 28: Last descriptor */ +#define ETH_TXDES3_FD (1 << 29) /* Bit 29: First descriptor */ +#define ETH_TXDES3_CTXT (1 << 30) /* Bit 30: Context type */ +#define ETH_TXDES3_OWN (1 << 31) /* Bit 31: Own bit */ + +/* Transmit normal descriptor (writeback-format) */ +/* TDES0/1: 64-bit transmit packet timestamp */ +/* TDES2: Reserved */ + +/* TDES3: */ + +#define ETH_TXDES3_IHE (1 << 0) /* Bit 0: IP header error */ +#define ETH_TXDES3_DB (1 << 1) /* Bit 1: Deferred bit */ +#define ETH_TXDES3_UF (1 << 2) /* Bit 2: Underflow error */ +#define ETH_TXDES3_ED (1 << 3) /* Bit 3: Excessive deferral */ +#define ETH_TXDES3_CC_SHIFT (4) /* Bits 4-7: Collision count */ +#define ETH_TXDES3_EC (1 << 8) /* Bit 8: Excessive collision */ +#define ETH_TXDES3_LC (1 << 9) /* Bit 9: Late collision */ +#define ETH_TXDES3_NC (1 << 10) /* Bit 10: No carrier */ +#define ETH_TXDES3_LOC (1 << 11) /* Bit 11: Loss of carrier */ +#define ETH_TXDES3_PCE (1 << 12) /* Bit 12: Payload checksum error */ +#define ETH_TXDES3_FF (1 << 13) /* Bit 13: Packet flushed */ +#define ETH_TXDES3_JT (1 << 14) /* Bit 14: Jabber timeout */ +#define ETH_TXDES3_ES (1 << 15) /* Bit 15: Error summary */ +#define ETH_TXDES3_TTSS (1 << 17) /* Bit 17: Tx timestamp status */ + /* Bit 28: (see read format) */ + /* Bit 29: (see read format) */ + /* Bit 30: (see read format) */ + /* Bit 31: (see read format) */ + +/************************************************************************************************************ + * Public Types + ************************************************************************************************************/ + +/* Receive descriptor structure (read format) */ + +struct enet_rxdesc_s +{ + uint32_t buffer1; /* Buffer 1 address */ + uint32_t reserved; /* Reserved */ + uint32_t buffer2; /* Buffer 2 or next descriptor address */ + uint32_t ctrl; /* Buffer 1/2 byte counts and control */ +}; + +/* Transmit descriptor structure (read format) */ + +struct enet_txdesc_s +{ + uint32_t buffer1; /* TDES0 Buffer 1 address */ + uint32_t buffer2; /* TDES1 Buffer 2 address */ + uint32_t buflen; /* TDES2 Buffer 1/2 byte counts */ + uint32_t ctrlstat; /* TDES3 Control and status word */ +}; + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_ETHERNET_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_flexcomm.h b/arch/arm/src/lpc54xx/chip/lpc54_flexcomm.h new file mode 100644 index 0000000000000000000000000000000000000000..e1c5badc150440483606c20ec9b519e3a3584cfa --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_flexcomm.h @@ -0,0 +1,116 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/chip/lpc54_flexcomm.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_FLEXCOMM_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_FLEXCOMM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC54_FLEXCOMM_PSELID_OFFSET 0x0ff8 /* Peripheral Select /Flexcomm Interface ID */ +#define LPC54_FLEXCOMM_PID_OFFSET 0x0ffc /* Peripheral identification register */ + +/* Register addresses ***************************************************************/ + +#define LPC54_FLEXCOMM0_PSELID (LPC54_FLEXCOMM0_BASE+LPC54_FLEXCOMM_PSELID_OFFSET) +#define LPC54_FLEXCOMM0_PID (LPC54_FLEXCOMM0_BASE+LPC54_FLEXCOMM_PID_OFFSET) + +#define LPC54_FLEXCOMM1_PSELID (LPC54_FLEXCOMM1_BASE+LPC54_FLEXCOMM_PSELID_OFFSET) +#define LPC54_FLEXCOMM1_PID (LPC54_FLEXCOMM1_BASE+LPC54_FLEXCOMM_PID_OFFSET) + +#define LPC54_FLEXCOMM2_PSELID (LPC54_FLEXCOMM2_BASE+LPC54_FLEXCOMM_PSELID_OFFSET) +#define LPC54_FLEXCOMM2_PID (LPC54_FLEXCOMM2_BASE+LPC54_FLEXCOMM_PID_OFFSET) + +#define LPC54_FLEXCOMM3_PSELID (LPC54_FLEXCOMM3_BASE+LPC54_FLEXCOMM_PSELID_OFFSET) +#define LPC54_FLEXCOMM3_PID (LPC54_FLEXCOMM3_BASE+LPC54_FLEXCOMM_PID_OFFSET) + +#define LPC54_FLEXCOMM4_PSELID (LPC54_FLEXCOMM4_BASE+LPC54_FLEXCOMM_PSELID_OFFSET) +#define LPC54_FLEXCOMM4_PID (LPC54_FLEXCOMM4_BASE+LPC54_FLEXCOMM_PID_OFFSET) + +#define LPC54_FLEXCOMM5_PSELID (LPC54_FLEXCOMM5_BASE+LPC54_FLEXCOMM_PSELID_OFFSET) +#define LPC54_FLEXCOMM5_PID (LPC54_FLEXCOMM5_BASE+LPC54_FLEXCOMM_PID_OFFSET) + +#define LPC54_FLEXCOMM6_PSELID (LPC54_FLEXCOMM6_BASE+LPC54_FLEXCOMM_PSELID_OFFSET) +#define LPC54_FLEXCOMM6_PID (LPC54_FLEXCOMM6_BASE+LPC54_FLEXCOMM_PID_OFFSET) + +#define LPC54_FLEXCOMM7_PSELID (LPC54_FLEXCOMM7_BASE+LPC54_FLEXCOMM_PSELID_OFFSET) +#define LPC54_FLEXCOMM7_PID (LPC54_FLEXCOMM7_BASE+LPC54_FLEXCOMM_PID_OFFSET) + +#define LPC54_FLEXCOMM8_PSELID (LPC54_FLEXCOMM8_BASE+LPC54_FLEXCOMM_PSELID_OFFSET) +#define LPC54_FLEXCOMM8_PID (LPC54_FLEXCOMM8_BASE+LPC54_FLEXCOMM_PID_OFFSET) + +#define LPC54_FLEXCOMM9_PSELID (LPC54_FLEXCOMM9_BASE+LPC54_FLEXCOMM_PSELID_OFFSET) +#define LPC54_FLEXCOMM9_PID (LPC54_FLEXCOMM9_BASE+LPC54_FLEXCOMM_PID_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* Peripheral Select /Flexcomm Interface ID */ + +#define FLEXCOMM_PSELID_PERSEL_SHIFT (0) /* Bits 0-2: Peripheral Select */ +#define FLEXCOMM_PSELID_PERSEL_MASK (7 << FLEXCOMM_PSELID_PERSEL_SHIFT) +# define FLEXCOMM_PSELID_PERSEL_NONE (0 << FLEXCOMM_PSELID_PERSEL_SHIFT) /* No peripheral selected */ +# define FLEXCOMM_PSELID_PERSEL_USART (1 << FLEXCOMM_PSELID_PERSEL_SHIFT) /* USART function selected */ +# define FLEXCOMM_PSELID_PERSEL_SPI (2 << FLEXCOMM_PSELID_PERSEL_SHIFT) /* SPI function selected */ +# define FLEXCOMM_PSELID_PERSEL_I2C (3 << FLEXCOMM_PSELID_PERSEL_SHIFT) /* I2C function selected */ +# define FLEXCOMM_PSELID_PERSEL_I2STX (4 << FLEXCOMM_PSELID_PERSEL_SHIFT) /* I2S transmit function */ +# define FLEXCOMM_PSELID_PERSEL_I2SRX (5 << FLEXCOMM_PSELID_PERSEL_SHIFT) /* I2S receive function */ +#define FLEXCOMM_PSELID_LOCK (1 << 3) /* Bit 3: Lock the peripheral select */ +#define FLEXCOMM_PSELID_USARTPRESENT (1 << 4) /* Bit 4: USART present indicator */ +#define FLEXCOMM_PSELID_SPIPRESENT (1 << 5) /* Bit 5: SPI present indicator */ +#define FLEXCOMM_PSELID_I2CPRESENT (1 << 6) /* Bit 6: I2C present indicator */ +#define FLEXCOMM_PSELID_I2SPRESENT (1 << 7) /* Bit 7: I2S present indicator */ +#define FLEXCOMM_PSELID_ID_SHIFT (12) /* Bits 12-31: Flexcomm Interface ID */ +#define FLEXCOMM_PSELID_ID_MASK (0xfffff << FLEXCOMM_PSELID_ID_SHIFT) + +/* Peripheral identification register */ + +#define FLEXCOMM_PID_MINOR_SHIFT (8) /* Bits 8-11: Minor revision number */ +#define FLEXCOMM_PID_MINOR_MASK (15 << FLEXCOMM_PID_MINOR_SHIFT) +#define FLEXCOMM_PID_MAJOR_SHIFT (12) /* Bits 12-15: Major revision number */ +#define FLEXCOMM_PID_MAJOR_MASK (15 << FLEXCOMM_PID_MAJOR_SHIFT) +#define FLEXCOMM_PID_ID_SHIFT (16) /* Bits 15-31: Module ID for selected function */ +#define FLEXCOMM_PID_ID_MASK (0xffff << FLEXCOMM_PID_ID_SHIFT) + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_FLEXCOMM_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_gint.h b/arch/arm/src/lpc54xx/chip/lpc54_gint.h new file mode 100644 index 0000000000000000000000000000000000000000..f0eb80db55d9cfdf754dc73bee7152bcab788dcd --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_gint.h @@ -0,0 +1,90 @@ +/**************************************************************************************************** + * arch/arm/src/lpc54xx/lpc54_gint.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GINT_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GINT_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register offsets *********************************************************************************/ + +#define LPC54_GINT_CTRL_OFFSET 0x0000 /* GPIO grouped interrupt control */ +#define LPC54_GINT_PORT_POL0_OFFSET 0x0020 /* GPIO grouped interrupt port 0 polarity */ +#define LPC54_GINT_PORT_POL0_OFFSET 0x0024 /* GPIO grouped interrupt port 1 polarity */ +#define LPC54_GINT_PORT_ENA0_OFFSET 0x0040 /* GPIO grouped interrupt port 0 enable */ +#define LPC54_GINT_PORT_ENA1_OFFSET 0x0044 /* GPIO grouped interrupt port 1 enable */ + +/* Register addresses *******************************************************************************/ + +#define LPC54_GINT0_CTRL (LPC54_GINT0_BASE + LPC54_GINT_CTRL_OFFSET) +#define LPC54_GINT0_PORT_POL0 (LPC54_GINT0_BASE + LPC54_GINT_PORT_POL0_OFFSET) +#define LPC54_GINT0_PORT_POL0 (LPC54_GINT0_BASE + LPC54_GINT_PORT_POL1_OFFSET) +#define LPC54_GINT0_PORT_ENA0 (LPC54_GINT0_BASE + LPC54_GINT_PORT_ENA0_OFFSET) +#define LPC54_GINT0_PORT_ENA1 (LPC54_GINT0_BASE + LPC54_GINT_PORT_ENA1_OFFSET) + +#define LPC54_GINT1_CTRL (LPC54_GINT0_BASE + LPC54_GINT_CTRL_OFFSET) +#define LPC54_GINT1_PORT_POL0 (LPC54_GINT0_BASE + LPC54_GINT_PORT_POL0_OFFSET) +#define LPC54_GINT1_PORT_POL0 (LPC54_GINT0_BASE + LPC54_GINT_PORT_POL1_OFFSET) +#define LPC54_GINT1_PORT_ENA0 (LPC54_GINT0_BASE + LPC54_GINT_PORT_ENA0_OFFSET) +#define LPC54_GINT1_PORT_ENA1 (LPC54_GINT0_BASE + LPC54_GINT_PORT_ENA1_OFFSET) + +/* Register bit definitions *************************************************************************/ + +/* GPIO grouped interrupt control */ + +#define GINT_CTRL_INT (1 << 0) /* Bit 0: Group interrupt status */ +#define GINT_CTRL_COMB (1 << 1) /* Bit 1: Combine enabled inputs for group interrupt 0 */ +#define GINT_CTRL_TRIG (1 << 2) /* Bit 2" Group interrupt trigger 0 */ + +/* GPIO grouped interrupt port 0/1 polarity */ + +#define GINT_PORT_POL0(n) (1 << (n)) /* Configure pin polarity of port0 pins for group interrupt */ +#define GINT_PORT_POL1(n) (1 << (n)) /* Configure pin polarity of port1 pins for group interrupt */ + +/* GPIO grouped interrupt port 0/1 enable */ + +#define GINT_PORT_ENA0(n) (1 << (n)) /* Enable port0 pin for group interrupt */ +#define GINT_PORT_ENA1(n) (1 << (n)) /* Enable port1 pin for group interrupt */ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GINT_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_gpio.h b/arch/arm/src/lpc54xx/chip/lpc54_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..f9fbcc2a2bd5b883c8060ff0a2a1f6cc6ffc15f3 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_gpio.h @@ -0,0 +1,108 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/chip/lpc54_flexcomm.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GPIO_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include "chip/lpc54_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#define LPC54_GPIO_PORT0 0 +#define LPC54_GPIO_PORT1 1 +#define LPC54_GPIO_PORT2 2 +#define LPC54_GPIO_PORT3 3 +#define LPC54_GPIO_PORT4 4 +#define LPC54_GPIO_PORT5 5 +#define LPC54_GPIO_NPORTS 6 + +/* Register offsets *****************************************************************/ +/* Byte and word access to individual pins */ + +#define LPC54_GPIO_B_OFFSET(p) (0x0000 + (p)) +#define LPC54_GPIO_W_OFFSET(p) (0x1000 + ((p) << 2)) + +/* Word access to individual port regisers */ + +#define LPC54_GPIO_PORT_OFFSET(n) ((n) << 2) +#define LPC54_GPIO_DIR_OFFSET(n) (0x2000 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_MASK_OFFSET(n) (0x2080 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_PIN_OFFSET(n) (0x2100 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_MPIN_OFFSET(n) (0x2180 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_SET_OFFSET(n) (0x2200 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_CLR_OFFSET(n) (0x2280 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_NOT_OFFSET(n) (0x2300 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_DIRSET_OFFSET(n) (0x2380 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_DIRCLR_OFFSET(n) (0x2400 + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_DIRNOT_OFFSET(n) (0x2480 + LPC54_GPIO_PORT_OFFSET(n)) + +/* Register addresses ***************************************************************/ + +/* Byte and word access to individual pins */ + +#define LPC54_GPIO_B(p) (LPC54_GPIO_BASE + LPC54_GPIO_B_OFFSET(p)) +#define LPC54_GPIO_W(p) (LPC54_GPIO_BASE + LPC54_GPIO_W_OFFSET(p)) + +/* Word access to individual port regisers */ + +#define LPC54_GPIO_PORT(n) (LPC54_GPIO_BASE + LPC54_GPIO_PORT_OFFSET(n)) +#define LPC54_GPIO_DIR(n) (LPC54_GPIO_BASE + LPC54_GPIO_DIR_OFFSET(n)) +#define LPC54_GPIO_MASK(n) (LPC54_GPIO_BASE + LPC54_GPIO_MASK_OFFSET(n)) +#define LPC54_GPIO_PIN(n) (LPC54_GPIO_BASE + LPC54_GPIO_PIN_OFFSET(n)) +#define LPC54_GPIO_MPIN(n) (LPC54_GPIO_BASE + LPC54_GPIO_MPIN_OFFSET(n)) +#define LPC54_GPIO_SET(n) (LPC54_GPIO_BASE + LPC54_GPIO_SET_OFFSET(n)) +#define LPC54_GPIO_CLR(n) (LPC54_GPIO_BASE + LPC54_GPIO_CLR_OFFSET(n)) +#define LPC54_GPIO_NOT(n) (LPC54_GPIO_BASE + LPC54_GPIO_NOT_OFFSET(n)) +#define LPC54_GPIO_DIRSET(n) (LPC54_GPIO_BASE + LPC54_GPIO_DIRSET_OFFSET(n)) +#define LPC54_GPIO_DIRCLR(n) (LPC54_GPIO_BASE + LPC54_GPIO_DIRCLR_OFFSET(n)) +#define LPC54_GPIO_DIRNOT(n) (LPC54_GPIO_BASE + LPC54_GPIO_DIRNOT_OFFSET(n)) + +/* Register bit definitions *********************************************************/ + +/* Port registers are all bit arrays with one bit corresponding each of the 32 pins + * of the port. + */ + +#define GPIO_PORT_BIT(n) (1 << ((n) & 31)) + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GPIO_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_i2c.h b/arch/arm/src/lpc54xx/chip/lpc54_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..871f7959bc523d6840bf5d4b659eb49e03f25583 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_i2c.h @@ -0,0 +1,418 @@ +/**************************************************************************************************** + * arch/arm/src/lpc54xx/lpc54_i2c.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_I2C_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_I2C_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register offsets *********************************************************************************/ + +/* Shared I2C registers */ + +#define LPC54_I2C_CFG_OFFSET 0x0800 /* Configuration for shared functions */ +#define LPC54_I2C_STAT_OFFSET 0x0804 /* Status register for shared functions */ +#define LPC54_I2C_INTENSET_OFFSET 0x0808 /* Interrupt enable set and read */ +#define LPC54_I2C_INTENCLR_OFFSET 0x080c /* Interrupt enable clear */ +#define LPC54_I2C_TIMEOUT_OFFSET 0x0810 /* Time-out value */ +#define LPC54_I2C_CLKDIV_OFFSET 0x0814 /* Clock pre-divider for the entire I2C interface */ +#define LPC54_I2C_INTSTAT_OFFSET 0x0818 /* Interrupt status register for shared functions */ + +/* Master function registers */ + +#define LPC54_I2C_MSTCTL_OFFSET 0x0820 /* Master control */ +#define LPC54_I2C_MSTTIME_OFFSET 0x0824 /* Master timing configuration */ +#define LPC54_I2C_MSTDAT_OFFSET 0x0828 /* Combined Master receiver and transmitter data */ + +/* Slave function registers */ + +#define LPC54_I2C_SLVCTL_OFFSET 0x0840 /* Slave control */ +#define LPC54_I2C_SLVDAT_OFFSET 0x0844 /* Combined Slave receiver and transmitter data */ +#define LPC54_I2C_SLVADR0_OFFSET 0x0848 /* Slave address 0 */ +#define LPC54_I2C_SLVADR1_OFFSET 0x084c /* Slave address 1 */ +#define LPC54_I2C_SLVADR2_OFFSET 0x0850 /* Slave address 2 */ +#define LPC54_I2C_SLVADR3_OFFSET 0x0854 /* Slave address 3 */ +#define LPC54_I2C_SLVQUAL0_OFFSET 0x0858 /* Slave qualification for address 0 */ + +/* Monitor function registers */ + +#define LPC54_I2C_MONRXDAT_OFFSET 0x0880 /* Monitor receiver data */ + +/* ID register */ + +#define LPC54_I2C_ID_OFFSET 0x0ffc /* I2C module Identification */ + +/* Register addresses *******************************************************************************/ + +#define LPC54_I2C0_CFG (LPC54_FLEXCOMM0_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C0_STAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C0_INTENSET (LPC54_FLEXCOMM0_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C0_INTENCLR (LPC54_FLEXCOMM0_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C0_TIMEOUT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C0_CLKDIV (LPC54_FLEXCOMM0_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C0_INTSTAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C0_MSTCTL (LPC54_FLEXCOMM0_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C0_MSTTIME (LPC54_FLEXCOMM0_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C0_MSTDAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C0_SLVCTL (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C0_SLVDAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C0_SLVADR0 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C0_SLVADR1 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C0_SLVADR2 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C0_SLVADR3 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C0_SLVQUAL0 (LPC54_FLEXCOMM0_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C0_MONRXDAT (LPC54_FLEXCOMM0_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C0_ID (LPC54_FLEXCOMM0_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C1_CFG (LPC54_FLEXCOMM1_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C1_STAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C1_INTENSET (LPC54_FLEXCOMM1_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C1_INTENCLR (LPC54_FLEXCOMM1_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C1_TIMEOUT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C1_CLKDIV (LPC54_FLEXCOMM1_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C1_INTSTAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C1_MSTCTL (LPC54_FLEXCOMM1_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C1_MSTTIME (LPC54_FLEXCOMM1_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C1_MSTDAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C1_SLVCTL (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C1_SLVDAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C1_SLVADR0 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C1_SLVADR1 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C1_SLVADR2 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C1_SLVADR3 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C1_SLVQUAL0 (LPC54_FLEXCOMM1_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C1_MONRXDAT (LPC54_FLEXCOMM1_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C1_ID (LPC54_FLEXCOMM1_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C2_CFG (LPC54_FLEXCOMM2_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C2_STAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C2_INTENSET (LPC54_FLEXCOMM2_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C2_INTENCLR (LPC54_FLEXCOMM2_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C2_TIMEOUT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C2_CLKDIV (LPC54_FLEXCOMM2_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C2_INTSTAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C2_MSTCTL (LPC54_FLEXCOMM2_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C2_MSTTIME (LPC54_FLEXCOMM2_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C2_MSTDAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C2_SLVCTL (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C2_SLVDAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C2_SLVADR0 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C2_SLVADR1 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C2_SLVADR2 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C2_SLVADR3 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C2_SLVQUAL0 (LPC54_FLEXCOMM2_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C2_MONRXDAT (LPC54_FLEXCOMM2_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C2_ID (LPC54_FLEXCOMM2_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C3_CFG (LPC54_FLEXCOMM3_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C3_STAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C3_INTENSET (LPC54_FLEXCOMM3_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C3_INTENCLR (LPC54_FLEXCOMM3_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C3_TIMEOUT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C3_CLKDIV (LPC54_FLEXCOMM3_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C3_INTSTAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C3_MSTCTL (LPC54_FLEXCOMM3_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C3_MSTTIME (LPC54_FLEXCOMM3_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C3_MSTDAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C3_SLVCTL (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C3_SLVDAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C3_SLVADR0 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C3_SLVADR1 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C3_SLVADR2 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C3_SLVADR3 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C3_SLVQUAL0 (LPC54_FLEXCOMM3_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C3_MONRXDAT (LPC54_FLEXCOMM3_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C3_ID (LPC54_FLEXCOMM3_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C4_CFG (LPC54_FLEXCOMM4_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C4_STAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C4_INTENSET (LPC54_FLEXCOMM4_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C4_INTENCLR (LPC54_FLEXCOMM4_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C4_TIMEOUT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C4_CLKDIV (LPC54_FLEXCOMM4_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C4_INTSTAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C4_MSTCTL (LPC54_FLEXCOMM4_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C4_MSTTIME (LPC54_FLEXCOMM4_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C4_MSTDAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C4_SLVCTL (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C4_SLVDAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C4_SLVADR0 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C4_SLVADR1 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C4_SLVADR2 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C4_SLVADR3 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C4_SLVQUAL0 (LPC54_FLEXCOMM4_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C4_MONRXDAT (LPC54_FLEXCOMM4_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C4_ID (LPC54_FLEXCOMM4_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C5_CFG (LPC54_FLEXCOMM5_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C5_STAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C5_INTENSET (LPC54_FLEXCOMM5_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C5_INTENCLR (LPC54_FLEXCOMM5_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C5_TIMEOUT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C5_CLKDIV (LPC54_FLEXCOMM5_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C5_INTSTAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C5_MSTCTL (LPC54_FLEXCOMM5_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C5_MSTTIME (LPC54_FLEXCOMM5_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C5_MSTDAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C5_SLVCTL (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C5_SLVDAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C5_SLVADR0 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C5_SLVADR1 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C5_SLVADR2 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C5_SLVADR3 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C5_SLVQUAL0 (LPC54_FLEXCOMM5_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C5_MONRXDAT (LPC54_FLEXCOMM5_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C5_ID (LPC54_FLEXCOMM5_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C6_CFG (LPC54_FLEXCOMM6_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C6_STAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C6_INTENSET (LPC54_FLEXCOMM6_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C6_INTENCLR (LPC54_FLEXCOMM6_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C6_TIMEOUT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C6_CLKDIV (LPC54_FLEXCOMM6_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C6_INTSTAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C6_MSTCTL (LPC54_FLEXCOMM6_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C6_MSTTIME (LPC54_FLEXCOMM6_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C6_MSTDAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C6_SLVCTL (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C6_SLVDAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C6_SLVADR0 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C6_SLVADR1 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C6_SLVADR2 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C6_SLVADR3 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C6_SLVQUAL0 (LPC54_FLEXCOMM6_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C6_MONRXDAT (LPC54_FLEXCOMM6_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C6_ID (LPC54_FLEXCOMM6_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C7_CFG (LPC54_FLEXCOMM7_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C7_STAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C7_INTENSET (LPC54_FLEXCOMM7_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C7_INTENCLR (LPC54_FLEXCOMM7_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C7_TIMEOUT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C7_CLKDIV (LPC54_FLEXCOMM7_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C7_INTSTAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C7_MSTCTL (LPC54_FLEXCOMM7_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C7_MSTTIME (LPC54_FLEXCOMM7_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C7_MSTDAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C7_SLVCTL (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C7_SLVDAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C7_SLVADR0 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C7_SLVADR1 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C7_SLVADR2 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C7_SLVADR3 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C7_SLVQUAL0 (LPC54_FLEXCOMM7_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C7_MONRXDAT (LPC54_FLEXCOMM7_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C7_ID (LPC54_FLEXCOMM7_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C8_CFG (LPC54_FLEXCOMM8_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C8_STAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C8_INTENSET (LPC54_FLEXCOMM8_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C8_INTENCLR (LPC54_FLEXCOMM8_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C8_TIMEOUT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C8_CLKDIV (LPC54_FLEXCOMM8_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C8_INTSTAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C8_MSTCTL (LPC54_FLEXCOMM8_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C8_MSTTIME (LPC54_FLEXCOMM8_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C8_MSTDAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C8_SLVCTL (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C8_SLVDAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C8_SLVADR0 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C8_SLVADR1 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C8_SLVADR2 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C8_SLVADR3 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C8_SLVQUAL0 (LPC54_FLEXCOMM8_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C8_MONRXDAT (LPC54_FLEXCOMM8_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C8_ID (LPC54_FLEXCOMM8_BASE + LPC54_I2C_ID_OFFSET + +#define LPC54_I2C9_CFG (LPC54_FLEXCOMM9_BASE + LPC54_I2C_CFG_OFFSET) +#define LPC54_I2C9_STAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_STAT_OFFSET) +#define LPC54_I2C9_INTENSET (LPC54_FLEXCOMM9_BASE + LPC54_I2C_INTENSET_OFFSET) +#define LPC54_I2C9_INTENCLR (LPC54_FLEXCOMM9_BASE + LPC54_I2C_INTENCLR_OFFSET) +#define LPC54_I2C9_TIMEOUT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_TIMEOUT_OFFSET) +#define LPC54_I2C9_CLKDIV (LPC54_FLEXCOMM9_BASE + LPC54_I2C_CLKDIV_OFFSET) +#define LPC54_I2C9_INTSTAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_INTSTAT_OFFSET) +#define LPC54_I2C9_MSTCTL (LPC54_FLEXCOMM9_BASE + LPC54_I2C_MSTCTL_OFFSET) +#define LPC54_I2C9_MSTTIME (LPC54_FLEXCOMM9_BASE + LPC54_I2C_MSTTIME_OFFSET) +#define LPC54_I2C9_MSTDAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_MSTDAT_OFFSET) +#define LPC54_I2C9_SLVCTL (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVCTL_OFFSET) +#define LPC54_I2C9_SLVDAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVDAT_OFFSET) +#define LPC54_I2C9_SLVADR0 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVADR0_OFFSET) +#define LPC54_I2C9_SLVADR1 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVADR1_OFFSET) +#define LPC54_I2C9_SLVADR2 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVADR2_OFFSET) +#define LPC54_I2C9_SLVADR3 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVADR3_OFFSET) +#define LPC54_I2C9_SLVQUAL0 (LPC54_FLEXCOMM9_BASE + LPC54_I2C_SLVQUAL0_OFFSET) +#define LPC54_I2C9_MONRXDAT (LPC54_FLEXCOMM9_BASE + LPC54_I2C_MONRXDAT_OFFSET) +#define LPC54_I2C9_ID (LPC54_FLEXCOMM9_BASE + LPC54_I2C_ID_OFFSET + +/* Register bit definitions *************************************************************************/ + +/* Configuration for shared functions */ + +#define I2C_CFG_MSTEN (1 << 0) /* Bit 0: Master enable */ +#define I2C_CFG_SLVEN (1 << 1) /* Bit 1: Slave enable */ +#define I2C_CFG_MONEN (1 << 2) /* Bit 2: Monitor enable */ +#define I2C_CFG_TIMEOUTEN (1 << 3) /* Bit 3: I2C bus time-out enable */ +#define I2C_CFG_MONCLKSTR (1 << 4) /* Bit 4: Monitor function clock stretching */ +#define I2C_CFG_HSCAPABLE (1 << 5) /* Bit 5: High-speed mode capable enable */ + +#define I2C_CFG_ALLENABLES 0x1f + +/* Status, set and write, and clear register for shared functions */ +/* Master function state codes (MSTSTATE) */ + +#define I2C_MASTER_STATE_IDLE (0) /* Idle */ +#define I2C_MASTER_STATE_RXAVAIL (1) /* Received data is available (Master Receiver mode) */ +#define I2C_MASTER_STATE_TXOK (2) /* Data can be transmitted (Master Transmitter mode) */ +#define I2C_MASTER_STATE_ADDRNAK (3) /* Slave NACKed address */ +#define I2C_MASTER_STATE_DATANAK (4) /* Slave NACKed transmitted data */ + +/* Slave function state codes (SLVSTATE) */ + +#define I2C_SLAVE_STATE_ADDR (0) /* Address plus R/W received */ +#define I2C_SLAVE_STATE_RXAVAIL (1) /* Received data is available (Slave Receiver mode) */ +#define I2C_SLAVE_STATE_TXOK (2) /* Data can be transmitted (Slave Transmitter mode) */ + +/* Interrupt status, set and read, and clear registers */ + +#define I2C_INT_MSTPENDING (1 << 0) /* Bit 0 Master Pending interrupt */ +#define I2C_STAT_MSTSTATE_SHIFT (1) /* Bits 1-3: Master State code (status only) */ +#define I2C_STAT_MSTSTATE_MASK (7 << I2C_STAT_MSTSTATE_SHIFT) +# define I2C_STAT_MSTSTATE_IDLE (0 << I2C_STAT_MSTSTATE_SHIFT) /* Idle */ +# define I2C_STAT_MSTSTATE_RXAVAIL (1 << I2C_STAT_MSTSTATE_SHIFT) /* Receive ready */ +# define I2C_STAT_MSTSTATE_TXOK (2 << I2C_STAT_MSTSTATE_SHIFT) /* Transmit ready */ +# define I2C_STAT_MSTSTATE_ADDRNAK (3 << I2C_STAT_MSTSTATE_SHIFT) /* NACK Address */ +# define I2C_STAT_MSTSTATE_DATANAK (4 << I2C_STAT_MSTSTATE_SHIFT) /* NACK Data */ +#define I2C_INT_MSTARBLOSS (1 << 4) /* Bit 4: Master Arbitration Loss interrupt */ +#define I2C_INT_MSTSTSTPERR (1 << 6) /* Bit 6: Master Start/Stop Error interrupt */ +#define I2C_INT_SLVPENDING (1 << 8) /* Bit 8: Slave Pending interrupt */ +#define I2C_STAT_SLVSTATE_SHIFT (9) /* Bits 9-10: Slave State code (status only) */ +#define I2C_STAT_SLVSTATE_MASK (3 << I2C_STAT_SLVSTATE_SHIFT) +# define I2C_STAT_SLVSTATE_ADDR (0 << I2C_STAT_SLVSTATE_SHIFT) /* Slave address */ +# define I2C_STAT_SLVSTATE_RXAVAIL (1 << I2C_STAT_SLVSTATE_SHIFT) /* Slave receive */ +# define I2C_STAT_SLVSTATE_TXOK (2 << I2C_STAT_SLVSTATE_SHIFT) /* Slave transmit */ +#define I2C_INT_SLVNOTSTR (1 << 11) /* Bit 11: Slave Not Stretching interrupt */ +#define I2C_STAT_SLVIDX_SHIFT (12) /* Bits 12-13: Slave address match Index (status only) */ +#define I2C_STAT_SLVIDX_MASK (3 << I2C_STAT_SLVIDX_SHIFT) +# define I2C_STAT_SLVIDX_ADDR0 (0 << I2C_STAT_SLVIDX_SHIFT) /* Slave address 0 was matched */ +# define I2C_STAT_SLVIDX_ADDR1 (1 << I2C_STAT_SLVIDX_SHIFT) /* Slave address 1 was matched */ +# define I2C_STAT_SLVIDX_ADDR2 (2 << I2C_STAT_SLVIDX_SHIFT) /* Slave address 2 was matched */ +# define I2C_STAT_SLVIDX_ADDR3 (3 << I2C_STAT_SLVIDX_SHIFT) /* Slave address 3 was matched */ +#define I2C_STAT_SLVSEL (1 << 14) /* Bit 14: Slave selected flag (Slave only) */ +#define I2C_INT_SLVDESEL (1 << 15) /* Bit 15: Slave Deselect interrupt */ +#define I2C_INT_MONRDY (1 << 16) /* Bit 16: Monitor data Ready interrupt */ +#define I2C_INT_MONOV (1 << 17) /* Bit 17: Monitor Overrun interrupt */ +#define I2C_STAT_MONACTIVE (1 << 18) /* Bit 18: Monitor Active flag (status only) */ +#define I2C_INT_MONIDLE (1 << 19) /* Bit 19: Monitor Idle interrupt */ +#define I2C_INT_EVENTTIMEOUT (1 << 24) /* Bit 24: Event time-out interrupt */ +#define I2C_INT_SCLTIMEOUT (1 << 25) /* Bit 25: SCL time-out interrupt */ + +#define I2C_INT_MSTPENDING (1 << 0) /* Bit 0 Master Pending interrupt */ +#define I2C_INT_MSTARBLOSS (1 << 4) /* Bit 4: Master Arbitration Loss interrupt */ +#define I2C_INT_MSTSTSTPERR (1 << 6) /* Bit 6: Master Start/Stop Error interrupt */ +#define I2C_INT_SLVPENDING (1 << 8) /* Bit 8: Slave Pending interrupt */ +#define I2C_INT_SLVNOTSTR (1 << 11) /* Bit 11: Slave Not Stretching interrupt */ +#define I2C_INT_SLVDESEL (1 << 15) /* Bit 15: Slave Deselect interrupt */ +#define I2C_INT_MONRDY (1 << 16) /* Bit 16: Monitor data Ready interrupt */ +#define I2C_INT_MONOV (1 << 17) /* Bit 17: Monitor Overrun interrupt */ +#define I2C_INT_MONIDLE (1 << 19) /* Bit 19: Monitor Idle interrupt */ +#define I2C_INT_EVENTTIMEOUT (1 << 24) /* Bit 24: Event time-out interrupt */ +#define I2C_INT_SCLTIMEOUT (1 << 25) /* Bit 25: SCL time-out interrupt */ + +#define I2C_INT_ALL 0x030b8951 + +/* Time-out value */ + +#define I2C_TIMEOUT_SHIFT (0) /* Bits 0-15: Time out value + * Bits 0-3 hardwired to 0xff */ +#define I2C_TIMEOUT_MASK (0xffff << I2C_TIMEOUT_SHIFT) +# define I2C_TIMEOUT(n) ((uint32_t)((n)-1) << I2C_TIMEOUT_SHIFT) + +/* Clock pre-divider for the entire I2C interface */ + +#define I2C_CLKDIV_SHIFT (0) /* Bits 0-15: I2C clock divider */ +#define I2C_CLKDIV_MASK (0xffff << I2C_CLKDIV_SHIFT) +# define I2C_CLKDIV(n) ((uint32_t)((n)-1) << I2C_CLKDIV_SHIFT) + +/* Master control */ + +#define I2C_MSTCTL_MSTCONTINUE (1 << 0) /* Bit 0: Master Continue */ +#define I2C_MSTCTL_MSTSTART (1 << 1) /* Bit 1: Master Start control */ +#define I2C_MSTCTL_MSTSTOP (1 << 2) /* Bit 2: Master Stop control */ +#define I2C_MSTCTL_MSTDMA (1 << 3) /* Bit 3: Master DMA enable */ + +/* Master timing configuration */ + +#define I2C_MSTTIME_SCLLOW_SHIFT (0) /* Bits 0-2 Master SCL Low time */ +#define I2C_MSTTIME_SCLLOW_MASK (7 << I2C_MSTTIME_SCLLOW_SHIFT) +# define I2C_MSTTIME_SCLLOW(n) ((uint32_t)((n)-2) << I2C_MSTTIME_SCLLOW_SHIFT) +#define I2C_MSTTIME_SCLHIGH_SHIFT (4) /* Bits 4-6 Master SCL High time */ +#define I2C_MSTTIME_SCLHIGH_MASK (7 << I2C_MSTTIME_SCLHIGH_SHIFT) +# define I2C_MSTTIME_SCLHIGH(n) ((uint32_t)((n)-2) << I2C_MSTTIME_SCLHIGH_SHIFT) + +/* Combined Master receiver and transmitter data */ + +#define I2C_MSTDAT_SHIFT (0) /* Bits 0-7: Master function data */ +#define I2C_MSTDAT_MASK (0xff << I2C_MSTDAT_SHIFT) +# define I2C_MSTDAT(n) ((uint32_t)(n) << I2C_MSTDAT_SHIFT) + +/* Slave control */ +#define I2C_SLVCTL_ +/* Combined Slave receiver and transmitter data */ +#define I2C_SLVDAT_ +/* Slave address 0 */ +#define I2C_SLVADR0_ +/* Slave address 1 */ +#define I2C_SLVADR1_ +/* Slave address 2 */ +#define I2C_SLVADR2_ +/* Slave address 3 */ +#define I2C_SLVADR3_ +/* Slave qualification for address 0 */ +#define I2C_SLVQUAL0_ +/* Monitor receiver data */ +#define I2C_MONRXDAT_ +/* I2C module Identification */ +#define I2C_ID_ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_I2C_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_inputmux.h b/arch/arm/src/lpc54xx/chip/lpc54_inputmux.h new file mode 100644 index 0000000000000000000000000000000000000000..c90250e9c53f6441dfc23082c13a5fbbbc89194e --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_inputmux.h @@ -0,0 +1,298 @@ +/**************************************************************************************************** + * arch/arm/src/lpc54xx/lpc54_inputmux.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_INPUTMUX_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_INPUTMUX_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register offsets *********************************************************************************/ + +#define LPC54_MUX_SCT0_INMUX_OFFSET(n) (0x0000 + ((n) << 2)) +#define LPC54_MUX_SCT0_INMUX0_OFFSET 0x0000 /* Input mux register for SCT0 input 0 */ +#define LPC54_MUX_SCT0_INMUX1_OFFSET 0x0004 /* Input mux register for SCT0 input 1 */ +#define LPC54_MUX_SCT0_INMUX2_OFFSET 0x0008 /* Input mux register for SCT0 input 2 */ +#define LPC54_MUX_SCT0_INMUX3_OFFSET 0x000c /* Input mux register for SCT0 input 3 */ +#define LPC54_MUX_SCT0_INMUX4_OFFSET 0x0010 /* Input mux register for SCT0 input 4 */ +#define LPC54_MUX_SCT0_INMUX5_OFFSET 0x0014 /* Input mux register for SCT0 input 5 */ +#define LPC54_MUX_SCT0_INMUX6_OFFSET 0x0018 /* Input mux register for SCT0 input 6 */ + +#define LPC54_MUX_PINTSEL_OFFSET(n) (0x00c0 + ((n) << 2)) +#define LPC54_MUX_PINTSEL0_OFFSET 0x00c0 /* Pin interrupt select register 0 */ +#define LPC54_MUX_PINTSEL1_OFFSET 0x00c4 /* Pin interrupt select register 1 */ +#define LPC54_MUX_PINTSEL2_OFFSET 0x00c8 /* Pin interrupt select register 2 */ +#define LPC54_MUX_PINTSEL3_OFFSET 0x00cc /* Pin interrupt select register 3 */ +#define LPC54_MUX_PINTSEL4_OFFSET 0x00d0 /* Pin interrupt select register 4 */ +#define LPC54_MUX_PINTSEL5_OFFSET 0x00d4 /* Pin interrupt select register 5 */ +#define LPC54_MUX_PINTSEL6_OFFSET 0x00d8 /* Pin interrupt select register 6 */ +#define LPC54_MUX_PINTSEL7_OFFSET 0x00dc /* Pin interrupt select register 7 */ + +#define LPC54_MUX_DMA_ITRIG_INMUX_OFFSET(n) (0x00e0 + ((n) << 2)) +#define LPC54_MUX_DMA_ITRIG_INMUX0_OFFSET 0x00e0 /* Trigger select register for DMA channel 0 */ +#define LPC54_MUX_DMA_ITRIG_INMUX1_OFFSET 0x00e4 /* Trigger select register for DMA channel 1 */ +#define LPC54_MUX_DMA_ITRIG_INMUX2_OFFSET 0x00e8 /* Trigger select register for DMA channel 2 */ +#define LPC54_MUX_DMA_ITRIG_INMUX3_OFFSET 0x00ec /* Trigger select register for DMA channel 3 */ +#define LPC54_MUX_DMA_ITRIG_INMUX4_OFFSET 0x00f0 /* Trigger select register for DMA channel 4 */ +#define LPC54_MUX_DMA_ITRIG_INMUX5_OFFSET 0x00f4 /* Trigger select register for DMA channel 5 */ +#define LPC54_MUX_DMA_ITRIG_INMUX6_OFFSET 0x00f8 /* Trigger select register for DMA channel 6 */ +#define LPC54_MUX_DMA_ITRIG_INMUX7_OFFSET 0x00fc /* Trigger select register for DMA channel 7 */ +#define LPC54_MUX_DMA_ITRIG_INMUX8_OFFSET 0x0100 /* Trigger select register for DMA channel 8 */ +#define LPC54_MUX_DMA_ITRIG_INMUX9_OFFSET 0x0104 /* Trigger select register for DMA channel 9 */ +#define LPC54_MUX_DMA_ITRIG_INMUX10_OFFSET 0x0108 /* Trigger select register for DMA channel 10 */ +#define LPC54_MUX_DMA_ITRIG_INMUX11_OFFSET 0x010c /* Trigger select register for DMA channel 11 */ +#define LPC54_MUX_DMA_ITRIG_INMUX12_OFFSET 0x0110 /* Trigger select register for DMA channel 12 */ +#define LPC54_MUX_DMA_ITRIG_INMUX13_OFFSET 0x0114 /* Trigger select register for DMA channel 13 */ +#define LPC54_MUX_DMA_ITRIG_INMUX14_OFFSET 0x0118 /* Trigger select register for DMA channel 14 */ +#define LPC54_MUX_DMA_ITRIG_INMUX15_OFFSET 0x011c /* Trigger select register for DMA channel 15 */ +#define LPC54_MUX_DMA_ITRIG_INMUX16_OFFSET 0x0120 /* Trigger select register for DMA channel 16 */ +#define LPC54_MUX_DMA_ITRIG_INMUX17_OFFSET 0x0124 /* Trigger select register for DMA channel 17 */ +#define LPC54_MUX_DMA_ITRIG_INMUX18_OFFSET 0x0128 /* Trigger select register for DMA channel 18 */ +#define LPC54_MUX_DMA_ITRIG_INMUX19_OFFSET 0x012c /* Trigger select register for DMA channel 19 */ +#define LPC54_MUX_DMA_ITRIG_INMUX20_OFFSET 0x0130 /* Trigger select register for DMA channel 20 */ +#define LPC54_MUX_DMA_ITRIG_INMUX21_OFFSET 0x0134 /* Trigger select register for DMA channel 21 */ +#define LPC54_MUX_DMA_ITRIG_INMUX22_OFFSET 0x0138 /* Trigger select register for DMA channel 22 */ +#define LPC54_MUX_DMA_ITRIG_INMUX23_OFFSET 0x013c /* Trigger select register for DMA channel 23 */ +#define LPC54_MUX_DMA_ITRIG_INMUX24_OFFSET 0x0140 /* Trigger select register for DMA channel 24 */ +#define LPC54_MUX_DMA_ITRIG_INMUX25_OFFSET 0x0144 /* Trigger select register for DMA channel 25 */ +#define LPC54_MUX_DMA_ITRIG_INMUX26_OFFSET 0x0148 /* Trigger select register for DMA channel 26 */ +#define LPC54_MUX_DMA_ITRIG_INMUX27_OFFSET 0x014c /* Trigger select register for DMA channel 27 */ +#define LPC54_MUX_DMA_ITRIG_INMUX28_OFFSET 0x0150 /* Trigger select register for DMA channel 28 */ +#define LPC54_MUX_DMA_ITRIG_INMUX29_OFFSET 0x0154 /* Trigger select register for DMA channel 29 */ + +#define LPC54_MUX_DMA_OTRIG_INMUX_OFFSET(n) (0x0160 + ((n) << 2)) +#define LPC54_MUX_DMA_OTRIG_INMUX0_OFFSET 0x0160 /* DMA output trigger selection to become DMA trigger 18 */ +#define LPC54_MUX_DMA_OTRIG_INMUX1_OFFSET 0x0164 /* DMA output trigger selection to become DMA trigger 19 */ +#define LPC54_MUX_DMA_OTRIG_INMUX2_OFFSET 0x0168 /* DMA output trigger selection to become DMA trigger 20 */ +#define LPC54_MUX_DMA_OTRIG_INMUX3_OFFSET 0x016c /* DMA output trigger selection to become DMA trigger 21 */ + +#define LPC54_MUX_FREQMEAS_REF_OFFSET 0x0180 /* Selection for frequency measurement reference clock */ +#define LPC54_MUX_FREQMEAS_TARGET_OFFSET 0x0184 /* Selection for frequency measurement target clock */ + +/* Register addresses *******************************************************************************/ + +#define LPC54_MUX_SCT0_INMUX(n) (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX_OFFSET(n)) +#define LPC54_MUX_SCT0_INMUX0 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX0_OFFSET) +#define LPC54_MUX_SCT0_INMUX1 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX1_OFFSET) +#define LPC54_MUX_SCT0_INMUX2 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX2_OFFSET) +#define LPC54_MUX_SCT0_INMUX3 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX3_OFFSET) +#define LPC54_MUX_SCT0_INMUX4 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX4_OFFSET) +#define LPC54_MUX_SCT0_INMUX5 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX5_OFFSET) +#define LPC54_MUX_SCT0_INMUX6 (LPC54_MUX_BASE + LPC54_MUX_SCT0_INMUX6_OFFSET) + +#define LPC54_MUX_PINTSEL(n) (LPC54_MUX_BASE + LPC54_MUX_PINTSEL_OFFSET(n)) +#define LPC54_MUX_PINTSEL0 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL0_OFFSET) +#define LPC54_MUX_PINTSEL1 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL1_OFFSET) +#define LPC54_MUX_PINTSEL2 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL2_OFFSET) +#define LPC54_MUX_PINTSEL3 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL3_OFFSET) +#define LPC54_MUX_PINTSEL4 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL4_OFFSET) +#define LPC54_MUX_PINTSEL5 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL5_OFFSET) +#define LPC54_MUX_PINTSEL6 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL6_OFFSET) +#define LPC54_MUX_PINTSEL7 (LPC54_MUX_BASE + LPC54_MUX_PINTSEL7_OFFSET) + +#define LPC54_MUX_DMA_ITRIG_INMUX(n) (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX_OFFSET(n)) +#define LPC54_MUX_DMA_ITRIG_INMUX0 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX0_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX1 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX1_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX2 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX2_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX3 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX3_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX4 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX4_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX5 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX5_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX6 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX6_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX7 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX7_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX8 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX8_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX9 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX9_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX10 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX10_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX11 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX11_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX12 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX12_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX13 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX13_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX14 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX14_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX15 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX15_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX16 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX16_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX17 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX17_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX18 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX18_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX19 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX19_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX20 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX20_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX21 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX21_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX22 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX22_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX23 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX23_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX24 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX24_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX25 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX25_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX26 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX26_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX27 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX27_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX28 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX28_OFFSET) +#define LPC54_MUX_DMA_ITRIG_INMUX29 (LPC54_MUX_BASE + LPC54_MUX_DMA_ITRIG_INMUX29_OFFSET) + +#define LPC54_MUX_DMA_OTRIG_INMUX(n) (LPC54_MUX_BASE + LPC54_MUX_DMA_OTRIG_INMUX_OFFSET(n)) +#define LPC54_MUX_DMA_OTRIG_INMUX0 (LPC54_MUX_BASE + LPC54_MUX_DMA_OTRIG_INMUX0_OFFSET) +#define LPC54_MUX_DMA_OTRIG_INMUX1 (LPC54_MUX_BASE + LPC54_MUX_DMA_OTRIG_INMUX1_OFFSET) +#define LPC54_MUX_DMA_OTRIG_INMUX2 (LPC54_MUX_BASE + LPC54_MUX_DMA_OTRIG_INMUX2_OFFSET) +#define LPC54_MUX_DMA_OTRIG_INMUX3 (LPC54_MUX_BASE + LPC54_MUX_DMA_OTRIG_INMUX3_OFFSET) + +#define LPC54_MUX_FREQMEAS_REF (LPC54_MUX_BASE + LPC54_MUX_FREQMEAS_REF_OFFSET) +#define LPC54_MUX_FREQMEAS_TARGET (LPC54_MUX_BASE + LPC54_MUX_FREQMEAS_TARGET_OFFSET) + +/* Register bit definitions *************************************************************************/ + +/* Input mux register for SCT0 input 0-6 */ + +#define MUX_SCT0_INMUX_SHIFT (0) /* Bits 0-4: Input number to SCT0 inputs 0 to 6 */ +#define MUX_SCT0_INMUX_MASK (31 << MUX_SCT0_INMUX_SHIFT) +# define MUX_SCT0_INMUX_SCTGPI0 (0 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */ +# define MUX_SCT0_INMUX_SCTGPI1 (1 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */ +# define MUX_SCT0_INMUX_SCTGPI2 (2 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */ +# define MUX_SCT0_INMUX_SCTGPI3 (3 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */ +# define MUX_SCT0_INMUX_SCTGPI4 (4 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */ +# define MUX_SCT0_INMUX_SCTGPI5 (5 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */ +# define MUX_SCT0_INMUX_SCTGPI6 (6 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */ +# define MUX_SCT0_INMUX_SCTGPI7 (7 << MUX_SCT0_INMUX_SHIFT) /* function selected from IOCON register */ +# define MUX_SCT0_INMUX_T0OUT0 (8 << MUX_SCT0_INMUX_SHIFT) /* T0_OUT0 */ +# define MUX_SCT0_INMUX_T1OUT0 (9 << MUX_SCT0_INMUX_SHIFT) /* T1_OUT0 */ +# define MUX_SCT0_INMUX_T2OUT0 (10 << MUX_SCT0_INMUX_SHIFT) /* T2_OUT0 */ +# define MUX_SCT0_INMUX_T3OUT0 (11 << MUX_SCT0_INMUX_SHIFT) /* T3_OUT0 */ +# define MUX_SCT0_INMUX_T4OUT0 (12 << MUX_SCT0_INMUX_SHIFT) /* T4_OUT0 */ +# define MUX_SCT0_INMUX_ADCTHCMP (13 << MUX_SCT0_INMUX_SHIFT) /* ADC_THCMP_IRQ */ +# define MUX_SCT0_INMUX_BMATCH (14 << MUX_SCT0_INMUX_SHIFT) /* GPIOINT_BMATCH */ +# define MUX_SCT0_INMUX_USB0 (15 << MUX_SCT0_INMUX_SHIFT) /* USB0_FRAME_TOGGLE */ +# define MUX_SCT0_INMUX_USB1 (16 << MUX_SCT0_INMUX_SHIFT) /* USB1_FRAME_TOGGLE */ +# define MUX_SCT0_INMUX_ARMTXEV (17 << MUX_SCT0_INMUX_SHIFT) /* ARM_TXEV */ +# define MUX_SCT0_INMUX_HALTED (18 << MUX_SCT0_INMUX_SHIFT) /* DEBUG_HALTED */ +# define MUX_SCT0_INMUX_SC0TX (19 << MUX_SCT0_INMUX_SHIFT) /* SMARTCARD0_TX_ACTIVE */ +# define MUX_SCT0_INMUX_SC0RX (20 << MUX_SCT0_INMUX_SHIFT) /* SMARTCARD0_RX_ACTIVE */ +# define MUX_SCT0_INMUX_SC1TX (21 << MUX_SCT0_INMUX_SHIFT) /* SMARTCARD1_TX_ACTIVE */ +# define MUX_SCT0_INMUX_S10RX (22 << MUX_SCT0_INMUX_SHIFT) /* SMARTCARD1_RX_ACTIVE */ +# define MUX_SCT0_INMUX_I2S6SCLK (23 << MUX_SCT0_INMUX_SHIFT) /* I2S6_SCLK */ +# define MUX_SCT0_INMUX_I2S7SCLK (24 << MUX_SCT0_INMUX_SHIFT) /* I2S7_SCLK */ + +/* Pin interrupt select register 0-7 + * + * Pin number select for pin interrupt or pattern match engine input. + * For PIOx_y: pin = (x * 32) + y. + * PIO0_0 to PIO1_31 correspond to numbers 0 to 63. + */ + +#define MUX_PINTSEL(n) (1 << (n)) + +/* Trigger select register for DMA channel 0-29 */ + +#define ITRIG_INMUX_ADC0A (0) /* ADC0 Sequence A interrupt */ +#define ITRIG_INMUX_ADC0B (1) /* ADC0 Sequence B interrupt */ +#define ITRIG_INMUX_SCT0DMA0 (2) /* SCT0 DMA request 0 */ +#define ITRIG_INMUX_SCT0DMA1 (3) /* SCT0 DMA request 1 */ +#define ITRIG_INMUX_PININT0 (4) /* Pin interrupt 0 */ +#define ITRIG_INMUX_PININT1 (5) /* Pin interrupt 1 */ +#define ITRIG_INMUX_PININT2 (6) /* Pin interrupt 2 */ +#define ITRIG_INMUX_PININT3 (7) /* Pin interrupt 3 */ +#define ITRIG_INMUX_CTIMER0MAT0 (8) /* Timer CTIMER0 Match 0 */ +#define ITRIG_INMUX_CTIMER0MAT1 (9) /* Timer CTIMER0 Match 1 */ +#define ITRIG_INMUX_CTIMER1MAT0 (10) /* Timer CTIMER1 Match 0 */ +#define ITRIG_INMUX_CTIMER1MAT1 (11) /* Timer CTIMER1 Match 1 */ +#define ITRIG_INMUX_CTIMER2MAT0 (12) /* Timer CTIMER2 Match 0 */ +#define ITRIG_INMUX_CTIMER2MAT1 (13) /* Timer CTIMER2 Match 1 */ +#define ITRIG_INMUX_CTIMER3MAT0 (14) /* Timer CTIMER3 Match 0 */ +#define ITRIG_INMUX_CTIMER3MAT1 (15) /* Timer CTIMER3 Match 1 */ +#define ITRIG_INMUX_CTIMER4MAT0 (16) /* Timer CTIMER4 Match 0 */ +#define ITRIG_INMUX_CTIMER4MAT1 (17) /* Timer CTIMER4 Match 1 */ +#define ITRIG_INMUX_DMAMUX0 (18) /* DMA output trigger mux 0 */ +#define ITRIG_INMUX_DMAMUX1 (19) /* DMA output trigger mux 1 */ +#define ITRIG_INMUX_DMAMUX2 (20) /* DMA output trigger mux 2 */ +#define ITRIG_INMUX_DMAMUX3 (21) /* DMA output trigger mux 3 */ + +#define MUX_DMA_ITRIG_INMUX_SHIFT (0) /* Bit 0-4: Trigger input number for DMA channel n (n = 0 to 29) */ +#define MUX_DMA_ITRIG_INMUX_MASK (31 << MUX_DMA_ITRIG_INMUX_SHIFT) +# define MUX_DMA_ITRIG_INMUX(n) ((uint32_t)(n) << MUX_DMA_ITRIG_INMUX_SHIFT) +# define MUX_DMA_ITRIG_INMUX_ADC0A (0 << MUX_DMA_ITRIG_INMUX_SHIFT) /* ADC0 Sequence A interrupt */ +# define MUX_DMA_ITRIG_INMUX_ADC0B (1 << MUX_DMA_ITRIG_INMUX_SHIFT) /* ADC0 Sequence B interrupt */ +# define MUX_DMA_ITRIG_INMUX_SCT0DMA0 (2 << MUX_DMA_ITRIG_INMUX_SHIFT) /* SCT0 DMA request 0 */ +# define MUX_DMA_ITRIG_INMUX_SCT0DMA1 (3 << MUX_DMA_ITRIG_INMUX_SHIFT) /* SCT0 DMA request 1 */ +# define MUX_DMA_ITRIG_INMUX_PININT0 (4 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Pin interrupt 0 */ +# define MUX_DMA_ITRIG_INMUX_PININT1 (5 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Pin interrupt 1 */ +# define MUX_DMA_ITRIG_INMUX_PININT2 (6 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Pin interrupt 2 */ +# define MUX_DMA_ITRIG_INMUX_PININT3 (7 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Pin interrupt 3 */ +# define MUX_DMA_ITRIG_INMUX_CTIMER0MAT0 (8 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER0 Match 0 */ +# define MUX_DMA_ITRIG_INMUX_CTIMER0MAT1 (9 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER0 Match 1 */ +# define MUX_DMA_ITRIG_INMUX_CTIMER1MAT0 (10 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER1 Match 0 */ +# define MUX_DMA_ITRIG_INMUX_CTIMER1MAT1 (11 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER1 Match 1 */ +# define MUX_DMA_ITRIG_INMUX_CTIMER2MAT0 (12 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER2 Match 0 */ +# define MUX_DMA_ITRIG_INMUX_CTIMER2MAT1 (13 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER2 Match 1 */ +# define MUX_DMA_ITRIG_INMUX_CTIMER3MAT0 (14 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER3 Match 0 */ +# define MUX_DMA_ITRIG_INMUX_CTIMER3MAT1 (15 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER3 Match 1 */ +# define MUX_DMA_ITRIG_INMUX_CTIMER4MAT0 (16 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER4 Match 0 */ +# define MUX_DMA_ITRIG_INMUX_CTIMER4MAT1 (17 << MUX_DMA_ITRIG_INMUX_SHIFT) /* Timer CTIMER4 Match 1 */ +# define MUX_DMA_ITRIG_INMUX_DMAMUX0 (18 << MUX_DMA_ITRIG_INMUX_SHIFT) /* DMA output trigger mux 0 */ +# define MUX_DMA_ITRIG_INMUX_DMAMUX1 (19 << MUX_DMA_ITRIG_INMUX_SHIFT) /* DMA output trigger mux 1 */ +# define MUX_DMA_ITRIG_INMUX_DMAMUX2 (20 << MUX_DMA_ITRIG_INMUX_SHIFT) /* DMA output trigger mux 2 */ +# define MUX_DMA_ITRIG_INMUX_DMAMUX3 (21 << MUX_DMA_ITRIG_INMUX_SHIFT) /* DMA output trigger mux 3 */ + +/* DMA output trigger selection registers 0-3 */ + +#define MUX_DMA_OTRIG_INMUX_SHIFT (0) /* Bits 0-4: DMA trigger output number for DMA channel n=0..29 */ +#define MUX_DMA_OTRIG_INMUX_MASK (31 << MUX_DMA_OTRIG_INMUX_SHIFT) +# define MUX_DMA_OTRIG_INMUX(n) ((uint32_t)(n) << MUX_DMA_OTRIG_INMUX_SHIFT) + +/* Selection for frequency measurement reference clock */ + +#define MUX_FREQMEAS_REF_SHIFT (0) /* Bits 0-4: Clock source for frequency measure farget clock */ +#define MUX_FREQMEAS_REF_MASK (31 << MUX_FREQMEAS_REF_SHIFT) +# define MUX_FREQMEAS_REF_CLKIN (0 << MUX_FREQMEAS_REF_SHIFT) /* External crystal oscillator (clk_in) */ +# define MUX_FREQMEAS_REF_FRO12M (1 << MUX_FREQMEAS_REF_SHIFT) /* FRO 12 MHz oscillator (fro_12m) */ +# define MUX_FREQMEAS_REF_FROHF (2 << MUX_FREQMEAS_REF_SHIFT) /* FRO 96 or 48 MHz (fro_hf) */ +# define MUX_FREQMEAS_REF_WDTCLK (3 << MUX_FREQMEAS_REF_SHIFT) /* Watchdog oscillator (wdt_clk) */ +# define MUX_FREQMEAS_REF_32KCLK (4 << MUX_FREQMEAS_REF_SHIFT) /* 32 kHz RTC oscillator (32k_clk) */ +# define MUX_FREQMEAS_REF_MAINCLK (5 << MUX_FREQMEAS_REF_SHIFT) /* Main clock (main_clk) */ +# define MUX_FREQMEAS_REF_GPIOCLKA (6 << MUX_FREQMEAS_REF_SHIFT) /* FREQME_GPIO_CLK_A */ +# define MUX_FREQMEAS_REF_GPIOCLKB (7 << MUX_FREQMEAS_REF_SHIFT) /* FREQME_GPIO_CLK_B */ + +/* Selection for frequency measurement target clock */ + +#define MUX_FREQMEAS_TARGET_SHIFT (0) /* Bits 0-4: Selects target clock of the frequency measure function */ +#define MUX_FREQMEAS_TARGET_MASK (31 << MUX_FREQMEAS_TARGET_SHIFT) +# define MUX_FREQMEAS_TARGET_CLKIN (0 << MUX_FREQMEAS_TARGET_SHIFT) /* External crystal oscillator (clk_in) */ +# define MUX_FREQMEAS_TARGET_FRO12M (1 << MUX_FREQMEAS_TARGET_SHIFT) /* FRO 12 MHz oscillator (fro_12m) */ +# define MUX_FREQMEAS_TARGET_FROHF (2 << MUX_FREQMEAS_TARGET_SHIFT) /* FRO 96 or 48 MHz (fro_hf) */ +# define MUX_FREQMEAS_TARGET_WDTCLK (3 << MUX_FREQMEAS_TARGET_SHIFT) /* Watchdog oscillator (wdt_clk) */ +# define MUX_FREQMEAS_TARGET_32KCLK (4 << MUX_FREQMEAS_TARGET_SHIFT) /* 32 kHz RTC oscillator (32k_clk) */ +# define MUX_FREQMEAS_TARGET_MAINCLK (5 << MUX_FREQMEAS_TARGET_SHIFT) /* Main clock (main_clk) */ +# define MUX_FREQMEAS_TARGET_GPIOCLKA (6 << MUX_FREQMEAS_TARGET_SHIFT) /* FREQME_GPIO_CLK_A */ +# define MUX_FREQMEAS_TARGET_ PIOCLKB (7 << MUX_FREQMEAS_TARGET_SHIFT) /* FREQME_GPIO_CLK_B */ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_INPUTMUX_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_iocon.h b/arch/arm/src/lpc54xx/chip/lpc54_iocon.h new file mode 100644 index 0000000000000000000000000000000000000000..4a04936ffa1d62250122d12fd0449e4537f4bfd2 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_iocon.h @@ -0,0 +1,378 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/chip/lpc54_iocon.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC548X_IOCON_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC548X_IOCON_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC54_IOCON_PIO_n_OFFSET(p) ((unsigned int)(p) << 2) +#define LPC54_IOCON_PIO_0_OFFSET (0x0000) /* IOCON Port(n) register 0 */ +#define LPC54_IOCON_PIO_1_OFFSET (0x0004) /* IOCON Port(n) register 1 */ +#define LPC54_IOCON_PIO_2_OFFSET (0x0008) /* IOCON Port(n) register 2 */ +#define LPC54_IOCON_PIO_3_OFFSET (0x000c) /* IOCON Port(n) register 3 */ +#define LPC54_IOCON_PIO_4_OFFSET (0x0010) /* IOCON Port(n) register 4 */ +#define LPC54_IOCON_PIO_5_OFFSET (0x0014) /* IOCON Port(n) register 5 */ +#define LPC54_IOCON_PIO_6_OFFSET (0x0018) /* IOCON Port(n) register 6 */ +#define LPC54_IOCON_PIO_7_OFFSET (0x001c) /* IOCON Port(n) register 7 */ +#define LPC54_IOCON_PIO_8_OFFSET (0x0020) /* IOCON Port(n) register 8 */ +#define LPC54_IOCON_PIO_9_OFFSET (0x0024) /* IOCON Port(n) register 9 */ +#define LPC54_IOCON_PIO_10_OFFSET (0x0028) /* IOCON Port(n) register 10 */ +#define LPC54_IOCON_PIO_11_OFFSET (0x002c) /* IOCON Port(n) register 11 */ +#define LPC54_IOCON_PIO_12_OFFSET (0x0030) /* IOCON Port(n) register 12 */ +#define LPC54_IOCON_PIO_13_OFFSET (0x0034) /* IOCON Port(n) register 13 */ +#define LPC54_IOCON_PIO_14_OFFSET (0x0038) /* IOCON Port(n) register 14 */ +#define LPC54_IOCON_PIO_15_OFFSET (0x003c) /* IOCON Port(n) register 15 */ +#define LPC54_IOCON_PIO_16_OFFSET (0x0040) /* IOCON Port(n) register 16 */ +#define LPC54_IOCON_PIO_17_OFFSET (0x0044) /* IOCON Port(n) register 17 */ +#define LPC54_IOCON_PIO_18_OFFSET (0x0048) /* IOCON Port(n) register 18 */ +#define LPC54_IOCON_PIO_19_OFFSET (0x004c) /* IOCON Port(n) register 19 */ +#define LPC54_IOCON_PIO_20_OFFSET (0x0050) /* IOCON Port(n) register 20 */ +#define LPC54_IOCON_PIO_21_OFFSET (0x0054) /* IOCON Port(n) register 21 */ +#define LPC54_IOCON_PIO_22_OFFSET (0x0058) /* IOCON Port(n) register 22 */ +#define LPC54_IOCON_PIO_23_OFFSET (0x005c) /* IOCON Port(n) register 23 */ +#define LPC54_IOCON_PIO_24_OFFSET (0x0060) /* IOCON Port(n) register 24 */ +#define LPC54_IOCON_PIO_25_OFFSET (0x0064) /* IOCON Port(n) register 25 */ +#define LPC54_IOCON_PIO_26_OFFSET (0x0068) /* IOCON Port(n) register 26 */ +#define LPC54_IOCON_PIO_27_OFFSET (0x006c) /* IOCON Port(n) register 27 */ +#define LPC54_IOCON_PIO_28_OFFSET (0x0070) /* IOCON Port(n) register 28 */ +#define LPC54_IOCON_PIO_29_OFFSET (0x0074) /* IOCON Port(n) register 29 */ +#define LPC54_IOCON_PIO_30_OFFSET (0x0078) /* IOCON Port(n) register 30 */ +#define LPC54_IOCON_PIO_31_OFFSET (0x007c) /* IOCON Port(n) register 31 */ + +/* Register addresses ***************************************************************/ + +#define LPC54_IOCON_PIO_BASE(b) (LPC54_IOCON_BASE + ((unsigned int)(b) << 7)) +#define LPC54_IOCON_PIO0_BASE (LPC54_IOCON_BASE + 0x0000) +#define LPC54_IOCON_PIO1_BASE (LPC54_IOCON_BASE + 0x0080) +#define LPC54_IOCON_PIO2_BASE (LPC54_IOCON_BASE + 0x0100) +#define LPC54_IOCON_PIO3_BASE (LPC54_IOCON_BASE + 0x0180) +#define LPC54_IOCON_PIO4_BASE (LPC54_IOCON_BASE + 0x0200) +#define LPC54_IOCON_PIO5_BASE (LPC54_IOCON_BASE + 0x0280) + +#define LPC54_IOCON_PIO(b,p) (LPC54_IOCON_PIO_BASE(b) + LPC54_IOCON_PIO_n_OFFSET(p)) + +#define LPC54_IOCON_PIO0_0 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_0_OFFSET) +#define LPC54_IOCON_PIO0_1 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_1_OFFSET) +#define LPC54_IOCON_PIO0_2 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_2_OFFSET) +#define LPC54_IOCON_PIO0_3 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_3_OFFSET) +#define LPC54_IOCON_PIO0_4 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_4_OFFSET) +#define LPC54_IOCON_PIO0_5 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_5_OFFSET) +#define LPC54_IOCON_PIO0_6 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_6_OFFSET) +#define LPC54_IOCON_PIO0_7 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_7_OFFSET) +#define LPC54_IOCON_PIO0_8 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_8_OFFSET) +#define LPC54_IOCON_PIO0_9 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_9_OFFSET) +#define LPC54_IOCON_PIO0_10 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_10_OFFSET) +#define LPC54_IOCON_PIO0_11 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_11_OFFSET) +#define LPC54_IOCON_PIO0_12 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_12_OFFSET) +#define LPC54_IOCON_PIO0_13 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_13_OFFSET) +#define LPC54_IOCON_PIO0_14 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_14_OFFSET) +#define LPC54_IOCON_PIO0_15 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_15_OFFSET) +#define LPC54_IOCON_PIO0_16 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_16_OFFSET) +#define LPC54_IOCON_PIO0_17 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_17_OFFSET) +#define LPC54_IOCON_PIO0_18 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_18_OFFSET) +#define LPC54_IOCON_PIO0_19 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_19_OFFSET) +#define LPC54_IOCON_PIO0_20 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_20_OFFSET) +#define LPC54_IOCON_PIO0_21 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_21_OFFSET) +#define LPC54_IOCON_PIO0_22 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_22_OFFSET) +#define LPC54_IOCON_PIO0_23 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_23_OFFSET) +#define LPC54_IOCON_PIO0_24 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_24_OFFSET) +#define LPC54_IOCON_PIO0_25 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_25_OFFSET) +#define LPC54_IOCON_PIO0_26 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_26_OFFSET) +#define LPC54_IOCON_PIO0_27 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_27_OFFSET) +#define LPC54_IOCON_PIO0_28 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_28_OFFSET) +#define LPC54_IOCON_PIO0_29 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_29_OFFSET) +#define LPC54_IOCON_PIO0_30 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_30_OFFSET) +#define LPC54_IOCON_PIO0_31 (LPC54_IOCON_PIO0_BASE + LPC54_IOCON_PIO_31_OFFSET) + +#define LPC54_IOCON_PIO1_0 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_0_OFFSET) +#define LPC54_IOCON_PIO1_1 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_1_OFFSET) +#define LPC54_IOCON_PIO1_2 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_2_OFFSET) +#define LPC54_IOCON_PIO1_3 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_3_OFFSET) +#define LPC54_IOCON_PIO1_4 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_4_OFFSET) +#define LPC54_IOCON_PIO1_5 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_5_OFFSET) +#define LPC54_IOCON_PIO1_6 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_6_OFFSET) +#define LPC54_IOCON_PIO1_7 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_7_OFFSET) +#define LPC54_IOCON_PIO1_8 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_8_OFFSET) +#define LPC54_IOCON_PIO1_9 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_9_OFFSET) +#define LPC54_IOCON_PIO1_10 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_10_OFFSET) +#define LPC54_IOCON_PIO1_11 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_11_OFFSET) +#define LPC54_IOCON_PIO1_12 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_12_OFFSET) +#define LPC54_IOCON_PIO1_13 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_13_OFFSET) +#define LPC54_IOCON_PIO1_14 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_14_OFFSET) +#define LPC54_IOCON_PIO1_15 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_15_OFFSET) +#define LPC54_IOCON_PIO1_16 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_16_OFFSET) +#define LPC54_IOCON_PIO1_17 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_17_OFFSET) +#define LPC54_IOCON_PIO1_18 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_18_OFFSET) +#define LPC54_IOCON_PIO1_19 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_19_OFFSET) +#define LPC54_IOCON_PIO1_20 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_20_OFFSET) +#define LPC54_IOCON_PIO1_21 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_21_OFFSET) +#define LPC54_IOCON_PIO1_22 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_22_OFFSET) +#define LPC54_IOCON_PIO1_23 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_23_OFFSET) +#define LPC54_IOCON_PIO1_24 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_24_OFFSET) +#define LPC54_IOCON_PIO1_25 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_25_OFFSET) +#define LPC54_IOCON_PIO1_26 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_26_OFFSET) +#define LPC54_IOCON_PIO1_27 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_27_OFFSET) +#define LPC54_IOCON_PIO1_28 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_28_OFFSET) +#define LPC54_IOCON_PIO1_29 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_29_OFFSET) +#define LPC54_IOCON_PIO1_30 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_30_OFFSET) +#define LPC54_IOCON_PIO1_31 (LPC54_IOCON_PIO1_BASE + LPC54_IOCON_PIO_31_OFFSET) + +#define LPC54_IOCON_PIO2_0 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_0_OFFSET) +#define LPC54_IOCON_PIO2_1 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_1_OFFSET) +#define LPC54_IOCON_PIO2_2 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_2_OFFSET) +#define LPC54_IOCON_PIO2_3 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_3_OFFSET) +#define LPC54_IOCON_PIO2_4 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_4_OFFSET) +#define LPC54_IOCON_PIO2_5 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_5_OFFSET) +#define LPC54_IOCON_PIO2_6 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_6_OFFSET) +#define LPC54_IOCON_PIO2_7 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_7_OFFSET) +#define LPC54_IOCON_PIO2_8 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_8_OFFSET) +#define LPC54_IOCON_PIO2_9 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_9_OFFSET) +#define LPC54_IOCON_PIO2_10 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_10_OFFSET) +#define LPC54_IOCON_PIO2_11 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_11_OFFSET) +#define LPC54_IOCON_PIO2_12 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_12_OFFSET) +#define LPC54_IOCON_PIO2_13 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_13_OFFSET) +#define LPC54_IOCON_PIO2_14 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_14_OFFSET) +#define LPC54_IOCON_PIO2_15 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_15_OFFSET) +#define LPC54_IOCON_PIO2_16 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_16_OFFSET) +#define LPC54_IOCON_PIO2_17 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_17_OFFSET) +#define LPC54_IOCON_PIO2_18 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_18_OFFSET) +#define LPC54_IOCON_PIO2_19 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_19_OFFSET) +#define LPC54_IOCON_PIO2_20 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_20_OFFSET) +#define LPC54_IOCON_PIO2_21 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_21_OFFSET) +#define LPC54_IOCON_PIO2_22 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_22_OFFSET) +#define LPC54_IOCON_PIO2_23 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_23_OFFSET) +#define LPC54_IOCON_PIO2_24 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_24_OFFSET) +#define LPC54_IOCON_PIO2_25 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_25_OFFSET) +#define LPC54_IOCON_PIO2_26 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_26_OFFSET) +#define LPC54_IOCON_PIO2_27 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_27_OFFSET) +#define LPC54_IOCON_PIO2_28 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_28_OFFSET) +#define LPC54_IOCON_PIO2_29 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_29_OFFSET) +#define LPC54_IOCON_PIO2_30 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_30_OFFSET) +#define LPC54_IOCON_PIO2_31 (LPC54_IOCON_PIO2_BASE + LPC54_IOCON_PIO_31_OFFSET) + +#define LPC54_IOCON_PIO3_0 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_0_OFFSET) +#define LPC54_IOCON_PIO3_1 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_1_OFFSET) +#define LPC54_IOCON_PIO3_2 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_2_OFFSET) +#define LPC54_IOCON_PIO3_3 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_3_OFFSET) +#define LPC54_IOCON_PIO3_4 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_4_OFFSET) +#define LPC54_IOCON_PIO3_5 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_5_OFFSET) +#define LPC54_IOCON_PIO3_6 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_6_OFFSET) +#define LPC54_IOCON_PIO3_7 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_7_OFFSET) +#define LPC54_IOCON_PIO3_8 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_8_OFFSET) +#define LPC54_IOCON_PIO3_9 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_9_OFFSET) +#define LPC54_IOCON_PIO3_10 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_10_OFFSET) +#define LPC54_IOCON_PIO3_11 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_11_OFFSET) +#define LPC54_IOCON_PIO3_12 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_12_OFFSET) +#define LPC54_IOCON_PIO3_13 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_13_OFFSET) +#define LPC54_IOCON_PIO3_14 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_14_OFFSET) +#define LPC54_IOCON_PIO3_15 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_15_OFFSET) +#define LPC54_IOCON_PIO3_16 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_16_OFFSET) +#define LPC54_IOCON_PIO3_17 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_17_OFFSET) +#define LPC54_IOCON_PIO3_18 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_18_OFFSET) +#define LPC54_IOCON_PIO3_19 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_19_OFFSET) +#define LPC54_IOCON_PIO3_20 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_20_OFFSET) +#define LPC54_IOCON_PIO3_21 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_21_OFFSET) +#define LPC54_IOCON_PIO3_22 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_22_OFFSET) +#define LPC54_IOCON_PIO3_23 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_23_OFFSET) +#define LPC54_IOCON_PIO3_24 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_24_OFFSET) +#define LPC54_IOCON_PIO3_25 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_25_OFFSET) +#define LPC54_IOCON_PIO3_26 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_26_OFFSET) +#define LPC54_IOCON_PIO3_27 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_27_OFFSET) +#define LPC54_IOCON_PIO3_28 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_28_OFFSET) +#define LPC54_IOCON_PIO3_29 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_29_OFFSET) +#define LPC54_IOCON_PIO3_30 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_30_OFFSET) +#define LPC54_IOCON_PIO3_31 (LPC54_IOCON_PIO3_BASE + LPC54_IOCON_PIO_31_OFFSET) + +#define LPC54_IOCON_PIO4_0 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_0_OFFSET) +#define LPC54_IOCON_PIO4_1 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_1_OFFSET) +#define LPC54_IOCON_PIO4_2 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_2_OFFSET) +#define LPC54_IOCON_PIO4_3 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_3_OFFSET) +#define LPC54_IOCON_PIO4_4 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_4_OFFSET) +#define LPC54_IOCON_PIO4_5 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_5_OFFSET) +#define LPC54_IOCON_PIO4_6 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_6_OFFSET) +#define LPC54_IOCON_PIO4_7 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_7_OFFSET) +#define LPC54_IOCON_PIO4_8 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_8_OFFSET) +#define LPC54_IOCON_PIO4_9 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_9_OFFSET) +#define LPC54_IOCON_PIO4_10 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_10_OFFSET) +#define LPC54_IOCON_PIO4_11 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_11_OFFSET) +#define LPC54_IOCON_PIO4_12 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_12_OFFSET) +#define LPC54_IOCON_PIO4_13 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_13_OFFSET) +#define LPC54_IOCON_PIO4_14 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_14_OFFSET) +#define LPC54_IOCON_PIO4_15 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_15_OFFSET) +#define LPC54_IOCON_PIO4_16 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_16_OFFSET) +#define LPC54_IOCON_PIO4_17 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_17_OFFSET) +#define LPC54_IOCON_PIO4_18 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_18_OFFSET) +#define LPC54_IOCON_PIO4_19 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_19_OFFSET) +#define LPC54_IOCON_PIO4_20 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_20_OFFSET) +#define LPC54_IOCON_PIO4_21 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_21_OFFSET) +#define LPC54_IOCON_PIO4_22 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_22_OFFSET) +#define LPC54_IOCON_PIO4_23 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_23_OFFSET) +#define LPC54_IOCON_PIO4_24 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_24_OFFSET) +#define LPC54_IOCON_PIO4_25 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_25_OFFSET) +#define LPC54_IOCON_PIO4_26 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_26_OFFSET) +#define LPC54_IOCON_PIO4_27 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_27_OFFSET) +#define LPC54_IOCON_PIO4_28 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_28_OFFSET) +#define LPC54_IOCON_PIO4_29 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_29_OFFSET) +#define LPC54_IOCON_PIO4_30 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_30_OFFSET) +#define LPC54_IOCON_PIO4_31 (LPC54_IOCON_PIO4_BASE + LPC54_IOCON_PIO_31_OFFSET) + +#define LPC54_IOCON_PIO5_0 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_0_OFFSET) +#define LPC54_IOCON_PIO5_1 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_1_OFFSET) +#define LPC54_IOCON_PIO5_2 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_2_OFFSET) +#define LPC54_IOCON_PIO5_3 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_3_OFFSET) +#define LPC54_IOCON_PIO5_4 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_4_OFFSET) +#define LPC54_IOCON_PIO5_5 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_5_OFFSET) +#define LPC54_IOCON_PIO5_6 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_6_OFFSET) +#define LPC54_IOCON_PIO5_7 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_7_OFFSET) +#define LPC54_IOCON_PIO5_8 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_8_OFFSET) +#define LPC54_IOCON_PIO5_9 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_9_OFFSET) +#define LPC54_IOCON_PIO5_10 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_10_OFFSET) +#define LPC54_IOCON_PIO5_11 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_11_OFFSET) +#define LPC54_IOCON_PIO5_12 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_12_OFFSET) +#define LPC54_IOCON_PIO5_13 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_13_OFFSET) +#define LPC54_IOCON_PIO5_14 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_14_OFFSET) +#define LPC54_IOCON_PIO5_15 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_15_OFFSET) +#define LPC54_IOCON_PIO5_16 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_16_OFFSET) +#define LPC54_IOCON_PIO5_17 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_17_OFFSET) +#define LPC54_IOCON_PIO5_18 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_18_OFFSET) +#define LPC54_IOCON_PIO5_19 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_19_OFFSET) +#define LPC54_IOCON_PIO5_20 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_20_OFFSET) +#define LPC54_IOCON_PIO5_21 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_21_OFFSET) +#define LPC54_IOCON_PIO5_22 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_22_OFFSET) +#define LPC54_IOCON_PIO5_23 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_23_OFFSET) +#define LPC54_IOCON_PIO5_24 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_24_OFFSET) +#define LPC54_IOCON_PIO5_25 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_25_OFFSET) +#define LPC54_IOCON_PIO5_26 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_26_OFFSET) +#define LPC54_IOCON_PIO5_27 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_27_OFFSET) +#define LPC54_IOCON_PIO5_28 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_28_OFFSET) +#define LPC54_IOCON_PIO5_29 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_29_OFFSET) +#define LPC54_IOCON_PIO5_30 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_30_OFFSET) +#define LPC54_IOCON_PIO5_31 (LPC54_IOCON_PIO5_BASE + LPC54_IOCON_PIO_31_OFFSET) + +/* Register bit definitions *********************************************************/ +/* IOCON pin function select */ + +#define IOCON_FUNC_GPIO (0) +#define IOCON_FUNC_ALT1 (1) +#define IOCON_FUNC_ALT2 (2) +#define IOCON_FUNC_ALT3 (3) +#define IOCON_FUNC_ALT4 (4) +#define IOCON_FUNC_ALT5 (5) +#define IOCON_FUNC_ALT6 (6) +#define IOCON_FUNC_ALT7 (7) + +/* Pin modes */ + +#define IOCON_MODE_FLOAT (0) /* 00: pin has neither pull-up nor pull-down */ +#define IOCON_MODE_PULLDOWN (1) /* 01: pin has a pull-down resistor enabled */ +#define IOCON_MODE_PULLUP (2) /* 10: pin has a pull-up resistor enabled */ +#define IOCON_MODE_REPEATER (3) /* 11: pin has repeater mode enabled */ + +/* Bit field definitions */ + +#define IOCON_FUNC_SHIFT (0) /* Bits 0-3: Pin function. All types */ +#define IOCON_FUNC_MASK (15 << IOCON_FUNC_SHIFT) +# define IOCON_FUNC(n) ((uint32_t)(n) << IOCON_FUNC_SHIFT) +#define IOCON_MODE_SHIFT (4) /* Bits 4-5: Function mode. Types D,A */ +#define IOCON_MODE_MASK (3 << IOCON_MODE_SHIFT) +# define IOCON_MODE(n) ((uint32_t)(n) << IOCON_MODE_SHIFT) +#define IOCON_I2CSLEW_SHIFT (6) /* Bit 6: I2C slew rate. Type I */ +#define IOCON_I2CSLEW_MASK (1 << IOCON_I2CSLEW_SHIFT) +# define IOCON_I2CSLEW_I2CMODE (0) +# define IOCON_I2CSLEW_GPIO IOCON_I2CSLEW_MASK +#define IOCON_INVERT_SHIFT (7) /* Bit 7: Input polarity. Types D,I,A */ +#define IOCON_INVERT_MASK (1 << IOCON_INVERT_SHIFT) +# define IOCON_INVERT IOCON_INVERT_MASK +#define IOCON_DIGIMODE_SHIFT (8) /* Bit 8: Analog/Digital mode. Types D,I,A */ +#define IOCON_DIGIMODE_MASK (1 << IOCON_DIGIMODE_SHIFT) +# define IOCON_DIGIMODE_ANALOG (0) +# define IOCON_DIGIMODE_DIGITAL IOCON_DIGIMODE_MASK +#define IOCON_FILTEROFF_SHIFT (9) /* Bit 9: Input glitch filter. Types D,I,A */ +#define IOCON_FILTEROFF_MASK (1 << IOCON_FILTEROFF_SHIFT) +# define IOCON_FILTEROFF_ON (0) +# define IOCON_FILTEROFF_OFF IOCON_FILTEROFF_MASK +#define IOCON_SLEW_SHIFT (10) /* Bit 10: Driver slew rate. Type D */ +#define IOCON_SLEW_MASK (1 << IOCON_SLEW_SHIFT) +# define IOCON_SLEW_STANDARD (0) +# define IOCON_SLEW_FAST IOCON_SLEW_MASK +#define IOCON_I2CDRIVE_SHIFT (10) /* Bit 10: Sink capability of pin. Type I */ +#define IOCON_I2CDRIVE_MASK (1 << IOCON_I2CDRIVE_SHIFT) +# define IOCON_I2CDRIVE_LOW (0) +# define IOCON_I2CDRIVE_HIGH IOCON_I2CDRIVE_MASK +#define IOCON_OD_SHIFT (11) /* Bit 11: Open-drain mode. Types D,A */ +#define IOCON_OD_MASK (1 << IOCON_OD_SHIFT) +# define IOCON_OD_PUSHPULL (0) +# define IOCON_OD_OPENDRAIN IOCON_OD_MASK +#define IOCON_I2CFILTEROFF_SHIFT (11) /* Bit 11: I2C filter mode. Type I */ +#define IOCON_I2CFILTEROFF_MASK (1 << IOCON_I2CFILTEROFF_SHIFT) +# define IOCON_I2CFILTEROFF_ON (0) +# define IOCON_I2CFILTEROFF_OFF IOCON_I2CFILTEROFF_MASK + +/* Pin types by port */ + +#define IOCON_PIO0_TYPED_MASK (0x7f7e63ff) /* P0.0-9,13-14,17-22,24-30 */ +#define IOCON_PIO1_TYPED_MASK (0xfffffffe) /* P1.1-31 */ +#define IOCON_PIO2_TYPED_MASK (0xfffffffc) /* P2.2-31 */ +#define IOCON_PIO3_TYPED_MASK (0xfe000000) /* P3.25-31 */ +#define IOCON_PIO4_TYPED_MASK (0xffffffff) /* P4.0-31 */ +#define IOCON_PIO5_TYPED_MASK (0x000007ff) /* P5.0-10 */ + +#define IOCON_PIO0_TYPEI_MASK (0x00006000) /* P0.13-14 */ +#define IOCON_PIO1_TYPEI_MASK (0x00000000) /* None */ +#define IOCON_PIO2_TYPEI_MASK (0x00000000) /* None */ +#define IOCON_PIO3_TYPEI_MASK (0x01800000) /* P3.23-24 */ +#define IOCON_PIO4_TYPEI_MASK (0x00000000) /* None */ +#define IOCON_PIO5_TYPEI_MASK (0x00000000) /* None */ + +#define IOCON_PIO0_TYPEA_MASK (0x80831c00) /* p0.10-12,15-16,23,31 */ +#define IOCON_PIO1_TYPEA_MASK (0x00000001) /* p1.0 */ +#define IOCON_PIO2_TYPEA_MASK (0x00000003) /* p2.0-1 */ +#define IOCON_PIO3_TYPEA_MASK (0x00600000) /* p3.21-22 */ +#define IOCON_PIO4_TYPEA_MASK (0x00000000) /* None */ +#define IOCON_PIO5_TYPEA_MASK (0x00000000) /* None */ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC548X_IOCON_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_lcd.h b/arch/arm/src/lpc54xx/chip/lpc54_lcd.h new file mode 100644 index 0000000000000000000000000000000000000000..57df59026907549b1305dce22d25ca74540ce0ba --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_lcd.h @@ -0,0 +1,335 @@ +/************************************************************************************************ + * arch/arm/src/lpc54xx/chip/lpc54_lcd.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_LCD_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_LCD_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* Register offsets *****************************************************************************/ + +#define LPC54_LCD_TIMH_OFFSET 0x0000 /* Horizontal Timing Control register */ +#define LPC54_LCD_TIMV_OFFSET 0x0004 /* Vertical Timing Control register */ +#define LPC54_LCD_POL_OFFSET 0x0008 /* Clock & Signal Polarity Control register */ +#define LPC54_LCD_LE_OFFSET 0x000c /* Line End Control register */ +#define LPC54_LCD_UPBASE_OFFSET 0x0010 /* Upper Panel Frame Base Address register */ +#define LPC54_LCD_LPBASE_OFFSET 0x0014 /* Lower Panel Frame Base Address register */ +#define LPC54_LCD_CTRL_OFFSET 0x0018 /* LCD Control register */ +#define LPC54_LCD_INTMSK_OFFSET 0x001c /* Interrupt Mask register */ +#define LPC54_LCD_INTRAW_OFFSET 0x0020 /* Raw Interrupt Status register */ +#define LPC54_LCD_INTSTAT_OFFSET 0x0024 /* Masked Interrupt Status register */ +#define LPC54_LCD_INTCLR_OFFSET 0x0028 /* Interrupt Clear register */ +#define LPC54_LCD_UPCURR_OFFSET 0x002c /* Upper Panel Current Address Value register */ +#define LPC54_LCD_LPCURR_OFFSET 0x0030 /* Lower Panel Current Address Value register */ + +/* 256x16-bit Color Palette registers, n=0-127 */ + +#define LPC54_LCD_PAL_OFFSET(n) (0x0200 + ((n) << 2)) + +/* Cursor Image registers, n=0-255 */ + +#define LPC54_LCD_CRSR_IMG_OFFSET(n) (0x0800 + ((n) << 2)) + +#define LPC54_LCD_CRSR_CRTL_OFFSET 0x0c00 /* Cursor Control register */ +#define LPC54_LCD_CRSR_CFG_OFFSET 0x0c04 /* Cursor Configuration register */ +#define LPC54_LCD_CRSR_PAL0_OFFSET 0x0c08 /* Cursor Palette register 0 */ +#define LPC54_LCD_CRSR_PAL1_OFFSET 0x0c0c /* Cursor Palette register 1 */ +#define LPC54_LCD_CRSR_XY_OFFSET 0x0c10 /* Cursor XY Position register */ +#define LPC54_LCD_CRSR_CLIP_OFFSET 0x0c14 /* Cursor Clip Position register */ +#define LPC54_LCD_CRSR_INTMSK_OFFSET 0x0c20 /* Cursor Interrupt Mask regsiter */ +#define LPC54_LCD_CRSR_INTCLR_OFFSET 0x0c24 /* Cursor Interrupt Clear register */ +#define LPC54_LCD_CRSR_INTRAW_OFFSET 0x0c28 /* Cursor Raw Interrupt Status register */ +#define LPC54_LCD_CRSR_INTSTAT_OFFSET 0x0c2c /* Cursor Masked Interrupt Status register */ + +/* Register Addresses ***************************************************************************/ + +#define LPC54_LCD_TIMH (LPC54_LCD_BASE+LPC54_LCD_TIMH_OFFSET) +#define LPC54_LCD_TIMV (LPC54_LCD_BASE+LPC54_LCD_TIMV_OFFSET) +#define LPC54_LCD_POL (LPC54_LCD_BASE+LPC54_LCD_POL_OFFSET) +#define LPC54_LCD_LE (LPC54_LCD_BASE+LPC54_LCD_LE_OFFSET) +#define LPC54_LCD_UPBASE (LPC54_LCD_BASE+LPC54_LCD_UPBASE_OFFSET) +#define LPC54_LCD_LPBASE (LPC54_LCD_BASE+LPC54_LCD_LPBASE_OFFSET) +#define LPC54_LCD_CTRL (LPC54_LCD_BASE+LPC54_LCD_CTRL_OFFSET) +#define LPC54_LCD_INTMSK (LPC54_LCD_BASE+LPC54_LCD_INTMSK_OFFSET) +#define LPC54_LCD_INTRAW (LPC54_LCD_BASE+LPC54_LCD_INTRAW_OFFSET) +#define LPC54_LCD_INTSTAT (LPC54_LCD_BASE+LPC54_LCD_INTSTAT_OFFSET) +#define LPC54_LCD_INTCLR (LPC54_LCD_BASE+ LPC54_LCD_INTCLR_OFFSET) +#define LPC54_LCD_UPCURR (LPC54_LCD_BASE+LPC54_LCD_UPCURR_OFFSET) +#define LPC54_LCD_LPCURR (LPC54_LCD_BASE+LPC54_LCD_LPCURR_OFFSET) + +#define LPC54_LCD_PAL(n) (LPC54_LCD_BASE+LPC54_LCD_PAL_OFFSET(n)) +#define LPC54_LCD_CRSR_IMG(n) (LPC54_LCD_BASE+LPC54_LCD_CRSR_IMG_OFFSET(n)) + +#define LPC54_LCD_CRSR_CRTL (LPC54_LCD_BASE+LPC54_LCD_CRSR_CRTL_OFFSET) +#define LPC54_LCD_CRSR_CFG (LPC54_LCD_BASE+LPC54_LCD_CRSR_CFG_OFFSET) +#define LPC54_LCD_CRSR_PAL0 (LPC54_LCD_BASE+LPC54_LCD_CRSR_PAL0_OFFSET) +#define LPC54_LCD_CRSR_PAL1 (LPC54_LCD_BASE+LPC54_LCD_CRSR_PAL1_OFFSET) +#define LPC54_LCD_CRSR_XY (LPC54_LCD_BASE+LPC54_LCD_CRSR_XY_OFFSET) +#define LPC54_LCD_CRSR_CLIP (LPC54_LCD_BASE+LPC54_LCD_CRSR_CLIP_OFFSET) +#define LPC54_LCD_CRSR_INTMSK (LPC54_LCD_BASE+LPC54_LCD_CRSR_INTMSK_OFFSET) +#define LPC54_LCD_CRSR_INTCLR (LPC54_LCD_BASE+LPC54_LCD_CRSR_INTCLR_OFFSET) +#define LPC54_LCD_CRSR_INTRAW (LPC54_LCD_BASE+LPC54_LCD_CRSR_INTRAW_OFFSET) +#define LPC54_LCD_CRSR_INTSTAT (LPC54_LCD_BASE+LPC54_LCD_CRSR_INTSTAT_OFFSET) + +/* Register Bitfield Definitions ****************************************************************/ + +/* LCD_TIMH - Horizontal Timing Register */ + /* Bits 0-1: Reserved */ +#define LCD_TIMH_PPL_SHIFT (2) /* Bits 2-7: Pixels Per Line - 16-1024ppl */ +#define LCD_TIMH_PPL_MASK (0x3f << LCD_TIMH_PPL_SHIFT) +#define LCD_TIMH_HSW_SHIFT (8) /* Bits 8-15: Horizontal Sync Pulse Width */ +#define LCD_TIMH_HWS_MASK (0xff << LCD_TIMH_HSW_SHIFT) +#define LCD_TIMH_HFP_SHIFT (16) /* Bits 16-23: Horizontal Front Porch */ +#define LCD_TIMH_HFP_MASK (0xff << LCD_TIMH_HFP_SHIFT) +#define LCD_TIMH_HBP_SHIFT (24) /* Bits 24-31: Horizontal Back Porch */ +#define LCD_TIMH_HBP_MASK (0xff << LCD_TIMH_HBP_SHIFT) + +/* LCD_TIMV - Vertical Timing Register */ + +#define LCD_TIMV_LPP_SHIFT (0) /* Bits 0-9: Lines Per Panel 1-1024 lpp*/ +#define LCD_TIMV_LPP_MASK (0x3ff << LCD_TIMV_LPP_SHIFT) +#define LCD_TIMV_VSW_SHIFT (10) /* Bits 10-15: Vertical Synch Pulse Width */ +#define LCD_TIMV_VSW_MASK (0x3f << LCD_TIMV_VSW_SHIFT) +#define LCD_TIMV_VFP_SHIFT (16) /* Bits 16-23: Vertical Front Porch */ +#define LCD_TIMV_VFP_MASK (0xff << LCD_TIMV_VFP_SHIFT) +#define LCD_TIMV_VBP_SHIFT (24) /* Bits 24-31: Vertical Back Porch */ +#define LCD_TIMV_VBP_MASK (0xff << LCD_TIMV_VBP_SHIFT) + +/* LCD_POL - Clock and Signal Polarity Register */ + +#define LCD_POL_PCDLO_SHIFT (0) /* Bits 0-4: Lower 5 bits of panel clock divisor */ +#define LCD_POL_PCDLO_MASK (0x1f << LCD_POL_PCDLO_SHIFT) +# define LCD_POL_PCDLO(n) ((uint32_t)(n) << LCD_POL_PCDLO_SHIFT) + /* Bit 5: Reserved */ +#define LCD_POL_ACB_SHIFT (6) /* Bits 6-10: AC bias pin frequency */ +#define LCD_POL_ACB_MASK (0x1f << LCD_POL_ACB_SHIFT) +#define LCD_POL_IVS (1 << 11) /* Bit 11: Invert vertical sync */ +#define LCD_POL_IHS (1 << 12) /* Bit 12: Invert horizontal sync */ +#define LCD_POL_IPC (1 << 13) /* Bit 13: Invert panel clock */ +#define LCD_POL_IOE (1 << 14) /* Bit 14: Invert output enable */ + /* Bit 15: Reserved */ +#define LCD_POL_CPL_SHIFT (16) /* Bit 16-25: Clocks per line */ +#define LCD_POL_CPL_MASK (0x3ff << LCD_POL_CPL_SHIFT) +# define LCD_POL_CPL(n) ((uint32_t)(n) << LCD_POL_CPL_SHIFT) +#define LCD_POL_BCD (1 << 26) /* Bit 26: Bypass pixel clock divider */ +#define LCD_POL_PCDHI_SHIFT (27) /* Bits 27-31: Upper 5 bits of panel clock divisor */ +#define LCD_POL_PCDHI_MASK (0x1f << LCD_POL_PCDHI_SHIFT) +# define LCD_POL_PCDHI(n) ((uint32_t)(n) << LCD_POL_PCDHI_SHIFT) + +/* LCD_LE - Line End Control Register */ + +#define LCD_LE_LED_SHIFT (0) /* Bits 0-6: Line End delay */ +#define LCD_LE_LED_MASK (0x7f << LCD_LE_LED_SHIFT) + /* Bits 7-15: Reserved */ +#define LCD_LE_LEE (1 << 16) /* Bit 16: LCD line end enable */ + /* Bit 17-31: Reserved */ +/* LCD_UPBASE - Upper Panel Frame Base Address Register */ + /* Bits 0-2: Reserved */ +#define LCD_UPBASE_LCDUPBASE_SHIFT (3) /* Bits 3-31: LCD upper panel base address */ +#define LCD_UPBASE_LCDUPBASE_MASK (0x1FFFFFFF << LCD_UPBASE_LCDUPBASE_SHIFT) + +/* LCD_LPBASE - Lower Panel Frame Base Address Register */ + /* Bits 0-2: Reserved */ +#define LCD_LPBASE_LCDLPBASE_SHIFT (3) /* Bits 3-31: LCD lower panel base address */ +#define LCD_LPBASE_LCDLPBASE_MASK (0x1FFFFFFF << LCD_UPBASE_LCDUPBASE_SHIFT) + +/* LCD_CTRL - Controle Register */ + +#define LCD_CTRL_LCDEN (1 << 0) /* Bit 0: LCD enable control bit */ +#define LCD_CTRL_LCDBPP_SHIFT (1) /* Bits 1-3: LCD bits per pixel */ +#define LCD_CTRL_LCDBPP_MASK (7 << LCD_CTRL_LCDBPP_SHIFT) +# define LCD_CTRL_LCDBPP_1 (0 << LCD_CTRL_LCDBPP_SHIFT) /* 1 bpp */ +# define LCD_CTRL_LCDBPP_2 (1 << LCD_CTRL_LCDBPP_SHIFT) /* 2 bpp */ +# define LCD_CTRL_LCDBPP_4 (2 << LCD_CTRL_LCDBPP_SHIFT) /* 4 bpp */ +# define LCD_CTRL_LCDBPP_8 (3 << LCD_CTRL_LCDBPP_SHIFT) /* 8 bpp */ +# define LCD_CTRL_LCDBPP_16 (4 << LCD_CTRL_LCDBPP_SHIFT) /* 16 bpp */ +# define LCD_CTRL_LCDBPP_24 (5 << LCD_CTRL_LCDBPP_SHIFT) /* 24 bpp (TFT panel only) */ +# define LCD_CTRL_LCDBPP_565 (6 << LCD_CTRL_LCDBPP_SHIFT) /* 16 bpp, 5:6:5 mode */ +# define LCD_CTRL_LCDBPP_444 (7 << LCD_CTRL_LCDBPP_SHIFT) /* 12 bpp, 4:4:4 mode */ +#define LCD_CTRL_LCDBW (1 << 4) /* Bit 4: STN LCD monochrome/color selection */ +#define LCD_CTRL_LCDTFT (1 << 5) /* Bit 5: LCD TFT type selection */ +#define LCD_CTRL_LCDMONO8 (1 << 6) /* Bit 6: Monochrome LCD interface bit */ +#define LCD_CTRL_LCDDUAL (1 << 7) /* Bit 7: Single or Dual LCD panel selection */ +#define LCD_CTRL_BGR (1 << 8) /* Bit 8: Color format */ +#define LCD_CTRL_BEBO (1 << 9) /* Bit 9: Big-Endian Byte Order */ +#define LCD_CTRL_BEPO (1 << 10) /* Bit 10: Big-Endian Pixel Ordering */ +#define LCD_CTRL_LCDPWR (1 << 11) /* Bit 11: LCD Power enable */ +#define LCD_CTRL_LCDVCOMP_SHIFT (12) /* Bits 12-13: LCD Vertical compare interrupt */ +#define LCD_CTRL_LCDVCOMP_MASK (3 << LCD_CTRL_LCDVCOMP_SHIFT) + /* Bits 14-15: Reserved */ +#define LCD_CTRL_WATERMARK (1 << 16) /* Bit 16: LCD DMA FIFO watermark level */ + /* Bits 17-31: Reserved */ +/* LCD_INTMSK - Interrupt Mask Register */ + /* Bits 0: Reserved */ +#define LCD_INTMSK_FUFIM (1 << 1) /* Bit 1: FIFO underflow interrupt enable */ +#define LCD_INTMSK_LNBUIM (1 << 2) /* Bit 2: LCD next base address interrupt enable */ +#define LCD_INTMSK_VCOMPIM (1 << 3) /* Bit 3: Vertical compare interrupt enable */ +#define LCD_INTMSK_BERIM (1 << 4) /* Bit 4: AHB Master error interrupt enable */ + /* Bits 5-31: Reserved */ +#define LCD_INTMSK_ALL (0x1e) + +/* LCD_INTRAW - Raw Interrupt Status Register */ + /* Bits 0: Reserved */ +#define LCD_INTRAW_FUFRIS (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt status */ +#define LCD_INTRAW_LNBURIS (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTRAW_VCOMPRIS (1 << 3) /* Bit 3: Vertical compare interrupt status */ +#define LCD_INTRAW_BERRAW (1 << 4) /* Bit 4: AHB Master bus error interrupt status */ + /* Bits 5-31: Reserved */ +#define LCD_INTRAW_ALL (0x1e) + +/* LCD_INTSTAT - Masked Interrupt Status Register */ + /* Bits 0: Reserved */ +#define LCD_INTSTAT_FUFMIS (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt status */ +#define LCD_INTSTAT_LNBUMIS (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTSTAT_VCOMPMIS (1 << 3) /* Bit 3: Vertical compare interrupt status */ +#define LCD_INTSTAT_BERMIS (1 << 4) /* Bit 4: AHB Master bus error interrupt status */ + /* Bits 15-31: Reserved */ +#define LCD_INTSTAT_ALL (0x1e) + +/* LCD_INTCLR - Interrupt Clear Register */ + /* Bits 0: Reserved */ +#define LCD_INTCLR_FUFIC (1 << 1) /* Bit 1: FIFO Undeflow raw interrupt clear */ +#define LCD_INTCLR_LNBUIC (1 << 2) /* Bit 2: LCD Next address base update intterupt */ +#define LCD_INTCLR_VCOMPIC (1 << 3) /* Bit 3: Vertical compare interrupt clear */ +#define LCD_INTCLR_BERIC (1 << 4) /* Bit 4: AHB Master bus error interrupt clear */ + /* Bits 15-31: Reserved */ +#define LCD_INTCLR_ALL (0x1e) + +/* Upper and Lower Panel Address register has no bitfields */ +/* + * Upper Panel Current Address register (LCDUPCURR) + * Lower Panel Current Address register (LCDLPCURR) + */ + +/* LCD_PAL - Color Palette Registers */ + +#define LCD_PAL_R0_SHIFT (0) /* Bits 0-4: Red palette data */ +#define LCD_PAL_R0_MASK (0x1f << LCD_PAL_R0_SHIFT) +#define LCD_PAL_G0_SHIFT (5) /* Bits 5-9: Green palette data */ +#define LCD_PAL_G0_MASK (0x1f << LCD_PAL_G0_SHIFT) +#define LCD_PAL_B0_SHIFT (10) /* Bits 10-14: Blue paletted data */ +#define LCD_PAL_B0_MASK (0x1f << LCD_PAL_B0_SHIFT) +#define LCD_PAL_I0 (1 << 15) /* Bit 15: Intensity/Unused bit */ +#define LCD_PAL_R1_SHIFT (16) /* Bits 16-20: Red palette data */ +#define LCD_PAL_R1_MASK (0x1f << LCD_PAL_R1_SHIFT) +#define LCD_PAL_G1_SHIFT (21) /* Bits 21-25: Green palette data */ +#define LCD_PAL_G1_MASK (0x1f << LCD_PAL_G1_SHIFT) +#define LCD_PAL_B1_SHIFT (26) /* Bits 26-30: Blue palette data */ +#define LCD_PAL_B1_MASK (0x1f << LCD_PAL_B1_SHIFT) +#define LCD_PAL_I1 (1 << 31) /* Bit 31: Intensity/Unused bit */ + +/* LCD_CRSR_IMG - Cursor Image Register - has no bitfields */ +/* The 256 words of the cursor image register defines the appearance + * of either one 64x64 cursor, or 4 32x32 cursors. + */ + +/* LCD CRSR_CTRL - Cursor Control Register */ + +#define LCD_CRSR_CTRL_CRSON (1 << 0) /* Bit 0: Cursor enable */ + /* Bits 1-3: Reserved */ +#define LCD_CRSR_CTRL_CRSRNUM_SHIFT (4) /* Bits 4-5: Cursor image number */ +#define LCD_CRSR_CTRL_CRSRNUM_MASK (3 << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT) + /* Bits 6-31: Reserved */ +/* If the selected cursor is 32x32 */ + +#define LCD_CURSOR0 (0) +#define LCD_CURSOR1 (1) +#define LCD_CURSOR2 (2) +#define LCD_CURSOR3 (3) + +/* LCD CRSR_CFG - Cursor Configuration Register */ + +#define LCD_CRSR_CFG_CRSRSIZE (1 << 0) /* Bit 0: Cursor size selection */ +#define LCD_CRSR_CFG_FRAMESYNC (1 << 1) /* Bit 1: Cursor frame sync type */ + /* Bits 2-31: Reserved */ + +#define LCD_CURSOR_SIZE32 (0) /* 32x32 */ +#define LCD_CURSOR_SIZE64 (1) /* 64x64 */ +#define LCD_CURSOR_FRAMEASYNC (0) /* Cursor coordinates are asynchronous */ +#define LCD_CURSOR_FRAMESYNC (1) /* coordinates are synchronize to framesync pulse */ + +/* LCD CRSR_PAL0/1 - Cursor Palette Registers */ + +#define LCD_CRSR_PAL_RED_SHIFT (0) /* Bits 0-7: Red color componnent */ +#define LCD_CRSR_PAL_RED_MASK (0xff << LCD_CRSR_PAL0_RED_SHIFT) +#define LCD_CRSR_PAL_GREEN_SHIFT (8) /* Bits 8-15: Green color component */ +#define LCD_CRSR_PAL_GREEN_MASK (0xff << LCD_CRSR_PAL0_GREEN_SHIFT) +#define LCD_CRSR_PAL_BLUE_SHIFT (16) /* Bits 16-23: Blue color component */ +#define LCD_CRSR_PAL_BLUE_MASK (0xff << LCD_CRSR_PAL0_BLUE_SHIFT) + /* Bits 24-31: Reserved */ +/* LCD CRSR_XY - Cursor XY Position Register */ + +#define LCD_CRSR_CRSRX_SHIFT (0) /* Bits 0-9: X ordinate */ +#define LCD_CRSR_CRSRX_MASK (0x3ff << LCD_CRSR_CRSRX_SHIFT) + /* Bits 10-15: Reserved */ +#define LCD_CRSR_CRSRY_SHIFT (16) /* Bits 16-25: Y ordinate */ +#define LCD_CRSR_CRSRY_MASK (0x3ff << LCD_CRSR_CRSRY_SHIFT) + /* Bits 26-31: Reserved */ +/* LCD CRSR_CLIP - Cursor Clip Position Register */ + +#define LCD_CRSR_CRSRCLIPX_SHIFT (0) /* Bits 0-5: X clip position */ +#define LCD_CRSR_CRSRCLIPX_MASK (0x3f << LCD_CRSR_CRSRCLIPX_SHIFT) + /* Bits 6-7: Reserved */ +#define LCD_CRSR_CRSRCLIPY_SHIFT (8) /* Bits 8-13: Reserved */ +#define LCD_CRSR_CRSRCLIPY_MASK (0x3f << LCD_CRSR_CRSRCLIPY_SHIFT) + /* Bits 14-31: Reserved */ +/* LCD CRSR_INTMSK - Cursor Interrrupt Mask Register */ + +#define LCD_CRSR_INTMSK_CRSRIM (1 << 0) /* Bit 0: Cursor interrupt mask */ + /* Bits 1-31: Reserved */ +/* LCD CRSR_INTCLR - Cursor Interrrupt Clear Register */ + +#define LCD_CRSR_INTCLR_CRSRIC (1 << 0) /* Bit 0: Cursor interrupt clear */ + /* Bits 1-31: Reserved */ + +/* LCD CRSR_INTRAW - Cursor Raw Interrrupt Status Register */ + +#define LCD_CRSR_INTRAW_CRSRRIS (1 << 0) /* Bit 0: Cursor raw interrupt status */ + /* Bits 1-31: Reserved */ +/* LCD CRSR_INTSTAT - Mask Interrrupt Status Register */ + +#define LCD_CRSR_INTSTAT_CRSRMIS (1 << 0) /* Bit 0: Cursor mask interrupt status */ + /* Bits 1-31: Reserved */ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_LCD_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_memorymap.h b/arch/arm/src/lpc54xx/chip/lpc54_memorymap.h new file mode 100644 index 0000000000000000000000000000000000000000..42c7f82cfd4721d123c202cceb321212093e4b68 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_memorymap.h @@ -0,0 +1,52 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/chip/lpc54_memorymap.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_MEMORYMAP_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_FAMILY_LPC546XX) +# include "chip/lpc546x_memorymap.h" +#else +# error "Unsupported LPC54 family" +#endif + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_MEMORYMAP_H */ + diff --git a/arch/arm/src/lpc54xx/chip/lpc54_pinmux.h b/arch/arm/src/lpc54xx/chip/lpc54_pinmux.h new file mode 100644 index 0000000000000000000000000000000000000000..de259f200edf46ecbf89f5790e61b38e57a4dfc6 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_pinmux.h @@ -0,0 +1,53 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/chip/lpc54_pinmux.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINMUX_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINMUX_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "lpc54_gpio.h" + +#if defined(CONFIG_ARCH_FAMILY_LPC546XX) +# include "chip/lpc546x_pinmux.h" +#else +# error "Unsupported LPC54 family" +#endif + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINMUX_H */ + diff --git a/arch/arm/src/lpc54xx/chip/lpc54_pint.h b/arch/arm/src/lpc54xx/chip/lpc54_pint.h new file mode 100644 index 0000000000000000000000000000000000000000..6e0f03501c3ed3db2420d7490ab02636aa8ce4a6 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_pint.h @@ -0,0 +1,200 @@ +/**************************************************************************************************** + * arch/arm/src/lpc54xx/chip/lpc54_pint.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINT_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINT_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register offsets *********************************************************************************/ + +#define LPC54_PINT_ISEL_OFFSET 0x0000 /* Pin interrupt mode */ +#define LPC54_PINT_IENR_OFFSET 0x0004 /* Pin interrupt level or rising edge interrupt enable */ +#define LPC54_PINT_SIENR_OFFSET 0x0008 /* Pin interrupt level or rising edge interrupt enable set */ +#define LPC54_PINT_CIENR_OFFSET 0x000c /* Pin interrupt level or rising edge interrupt enable clear */ +#define LPC54_PINT_IENF_OFFSET 0x0010 /* Pin interrupt active level or falling edge interrupt enable */ +#define LPC54_PINT_SIENF_OFFSET 0x0014 /* Pin interrupt active level or falling edge interrupt set */ +#define LPC54_PINT_CIENF_OFFSET 0x0018 /* Pin interrupt active level or falling edge interrupt clear */ +#define LPC54_PINT_RISE_OFFSET 0x001c /* Pin interrupt rising edge */ +#define LPC54_PINT_FALL_OFFSET 0x0020 /* Pin interrupt falling edge */ +#define LPC54_PINT_IST_OFFSET 0x0024 /* Pin interrupt status */ +#define LPC54_PINT_PMCTRL_OFFSET 0x0028 /* Pattern match interrupt control */ +#define LPC54_PINT_PMSRC_OFFSET 0x002c /* Pattern match interrupt bit-slice source */ +#define LPC54_PINT_PMCFG_OFFSET 0x0030 /* Pattern match interrupt bit slice configuration */ + +/* Register addresses *******************************************************************************/ + +#define LPC54_PINT_ISEL (LPC54_PINT_BASE + LPC54_PINT_ISEL_OFFSET) +#define LPC54_PINT_IENR (LPC54_PINT_BASE + LPC54_PINT_IENR_OFFSET) +#define LPC54_PINT_SIENR (LPC54_PINT_BASE + LPC54_PINT_SIENR_OFFSET) +#define LPC54_PINT_CIENR (LPC54_PINT_BASE + LPC54_PINT_CIENR_OFFSET) +#define LPC54_PINT_IENF (LPC54_PINT_BASE + LPC54_PINT_IENF_OFFSET) +#define LPC54_PINT_SIENF (LPC54_PINT_BASE + LPC54_PINT_SIENF_OFFSET) +#define LPC54_PINT_CIENF (LPC54_PINT_BASE + LPC54_PINT_CIENF_OFFSET) +#define LPC54_PINT_RISE (LPC54_PINT_BASE + LPC54_PINT_RISE_OFFSET) +#define LPC54_PINT_FALL (LPC54_PINT_BASE + LPC54_PINT_FALL_OFFSET) +#define LPC54_PINT_IST (LPC54_PINT_BASE + LPC54_PINT_IST_OFFSET) +#define LPC54_PINT_PMCTRL (LPC54_PINT_BASE + LPC54_PINT_PMCTRL_OFFSET) +#define LPC54_PINT_PMSRC (LPC54_PINT_BASE + LPC54_PINT_PMSRC_OFFSET) +#define LPC54_PINT_PMCFG (LPC54_PINT_BASE + LPC54_PINT_PMCFG_OFFSET) + +/* Register bit definitions *************************************************************************/ + +/* Pin interrupt mode */ + +#define PINT_PMODE(n) (1 << (n)) /* Pin n level(1) or edge(0) sensitive. n=0..7 */ + +/* Pin interrupt level or rising edge interrupt enable, set, and clear registers */ + +#define PINT_ENRL(n) (1 << (n)) /* Pin n enable(1) or disable(0) rising/level. n=0..7 */ + +/* Pin interrupt active level or falling edge interrupt enable, set, and clear registers */ + +#define PINT_ENAF(n) (1 << (n)) /* Pin n enable(1) or disable(0) falling/active. n=0..7 */ + +/* Pin interrupt rising edge */ + +#define PINT_RDET(n) (1 << (n)) /* R:Rising edge detected, W:Clear. n=0..7 */ + +/* Pin interrupt falling edge */ + +#define PINT_FDET(n) (1 << (n)) /* R:Falling edge detected, W:Clear. n=0..7 */ + +/* Pin interrupt status */ + +#define PINT_PSTAT(n) (1 << (n)) /* R:Interrupt pending, W:Clear edge or toggle level. n=0..7 */ + +/* Pattern match interrupt control */ + +#define PINT_PMCTRL_SELPMATCH (1 << 0) /* Bit 0: Rin interrupts interrupt or pattern match function */ +#define PINT_PMCTRL_ENARXEV (1 << 1) /* Bit 1: Enables RXEV output to CPU */ +#define PINT_PMCTRL_PMAT_SHIFT (24) /* Bits 24-31: Current state of pattern matches */ + +/* Pattern match interrupt bit-slice source */ + +/* PINTSELn=1 indicates that PINSETn is the source to bit slice m. */ + +#define PINT_PMSRC_PINTSEL0 0 +#define PINT_PMSRC_PINTSEL1 1 +#define PINT_PMSRC_PINTSEL2 2 +#define PINT_PMSRC_PINTSEL3 3 +#define PINT_PMSRC_PINTSEL4 4 +#define PINT_PMSRC_PINTSEL5 5 +#define PINT_PMSRC_PINTSEL6 6 +#define PINT_PMSRC_PINTSEL7 7 + +#define PINT_PMSRC_SRC0_SHIFT (8) /* Bits 8-10: Selects PINSELn as input source for bit slice 0 */ +#define PINT_PMSRC_SRC0_MASK (7 << PINT_PMSRC_SRC0_SHIFT) +# define PINT_PMSRC_SRC0(n) ((uint32_t)(n) << PINT_PMSRC_SRC0_SHIFT) +#define PINT_PMSRC_SRC1_SHIFT (11) /* Bits 11-13: Selects PINSELn as input source for bit slice 0 */ +#define PINT_PMSRC_SRC1_MASK (7 << PINT_PMSRC_SRC1_SHIFT) +# define PINT_PMSRC_SRC1(n) ((uint32_t)(n) << PINT_PMSRC_SRC1_SHIFT) +#define PINT_PMSRC_SRC2_SHIFT (14) /* Bits 14-16: Selects PINSELn as input source for bit slice 0 */ +#define PINT_PMSRC_SRC2_MASK (7 << PINT_PMSRC_SRC2_SHIFT) +# define PINT_PMSRC_SRC2(n) ((uint32_t)(n) << PINT_PMSRC_SRC2_SHIFT) +#define PINT_PMSRC_SRC3_SHIFT (17) /* Bits 17-19: Selects PINSELn as input source for bit slice 0 */ +#define PINT_PMSRC_SRC3_MASK (7 << PINT_PMSRC_SRC3_SHIFT) +# define PINT_PMSRC_SRC3(n) ((uint32_t)(n) << PINT_PMSRC_SRC3_SHIFT) +#define PINT_PMSRC_SRC4_SHIFT (20) /* Bits 20-22: Selects PINSELn as input source for bit slice 0 */ +#define PINT_PMSRC_SRC4_MASK (7 << PINT_PMSRC_SRC4_SHIFT) +# define PINT_PMSRC_SRC4(n) ((uint32_t)(n) << PINT_PMSRC_SRC4_SHIFT) +#define PINT_PMSRC_SRC5_SHIFT (23) /* Bits 23-25: Selects PINSELn as input source for bit slice 0 */ +#define PINT_PMSRC_SRC5_MASK (7 << PINT_PMSRC_SRC5_SHIFT) +# define PINT_PMSRC_SRC5(n) ((uint32_t)(n) << PINT_PMSRC_SRC5_SHIFT) +#define PINT_PMSRC_SRC6_SHIFT (26) /* Bits 26-28: Selects PINSELn as input source for bit slice 0 */ +#define PINT_PMSRC_SRC6_MASK (7 << PINT_PMSRC_SRC6_SHIFT) +# define PINT_PMSRC_SRC6(n) ((uint32_t)(n) << PINT_PMSRC_SRC6_SHIFT) +#define PINT_PMSRC_SRC7_SHIFT (29) /* Bits 29-31: Selects PINSELn as input source for bit slice 0 */ +#define PINT_PMSRC_SRC7_MASK (7 << PINT_PMSRC_SRC7_SHIFT) +# define PINT_PMSRC_SRC7(n) ((uint32_t)(n) << PINT_PMSRC_SRC7_SHIFT) + +/* Pattern match interrupt bit slice configuration */ + +/* PINT_PMCFG_ENDPTSn: Determines whether slice n is an endpoint of a product term (minterm). Pin + * interrupt n in the NVIC is raised if the minterm evaluates as true. + */ + +#define PINT_PMCFG_ENDPTS0 (1 << 0) /* Bit 0: Slice n is an endpoint */ +#define PINT_PMCFG_ENDPTS1 (1 << 1) /* Bit 1: Slice n is an endpoint */ +#define PINT_PMCFG_ENDPTS2 (1 << 2) /* Bit 2: Slice n is an endpoint */ +#define PINT_PMCFG_ENDPTS3 (1 << 3) /* Bit 3: Slice n is an endpoint */ +#define PINT_PMCFG_ENDPTS4 (1 << 4) /* Bit 4: Slice n is an endpoint */ +#define PINT_PMCFG_ENDPTS5 (1 << 5) /* Bit 5: Slice n is an endpoint */ +#define PINT_PMCFG_ENDPTS6 (1 << 6) /* Bit 6: Slice n is an endpoint */ + +#define PINT_PMCFG_HIGH 0 /* Constant HIGH */ +#define PINT_PMCFG_RISING 1 /* Sticky rising edge */ +#define PINT_PMCFG_FALLING 2 /* Sticky falling edge */ +#define PINT_PMCFG_BOTH 3 /* Sticky rising or falling edge */ +#define PINT_PMCFG_HIGH_LEVEL 4 /* High level */ +#define PINT_PMCFG_LOW_LEVEL 5 /* Low level */ +#define PINT_PMCFG_ZERO 6 /* Constant 0 */ +#define PINT_PMCFG_EVENT 7 /* Event */ + +#define PINT_PMCFG_CFG0_SHIFT (8) /* Bits 8-10: Match condition for bit slice 0 */ +#define PINT_PMCFG_CFG0_MASK (7 << PINT_PMCFG_CFG0_SHIFT) +# define PINT_PMCFG_CFG0(n) ((uint32_t)(n) << PINT_PMCFG_CFG0_SHIFT) +#define PINT_PMCFG_CFG1_SHIFT (8) /* Bits 11-13: Match condition for bit slice 1 */ +#define PINT_PMCFG_CFG1_MASK (7 << PINT_PMCFG_CFG1_SHIFT) +# define PINT_PMCFG_CFG1(n) ((uint32_t)(n) << PINT_PMCFG_CFG1_SHIFT) +#define PINT_PMCFG_CFG2_SHIFT (8) /* Bits 14-16: Match condition for bit slice 2 */ +#define PINT_PMCFG_CFG2_MASK (7 << PINT_PMCFG_CFG2_SHIFT) +# define PINT_PMCFG_CFG2(n) ((uint32_t)(n) << PINT_PMCFG_CFG2_SHIFT) +#define PINT_PMCFG_CFG3_SHIFT (8) /* Bits 17-19: Match condition for bit slice 3 */ +#define PINT_PMCFG_CFG3_MASK (7 << PINT_PMCFG_CFG3_SHIFT) +# define PINT_PMCFG_CFG3(n) ((uint32_t)(n) << PINT_PMCFG_CFG3_SHIFT) +#define PINT_PMCFG_CFG4_SHIFT (8) /* Bits 20-22: Match condition for bit slice 4 */ +#define PINT_PMCFG_CFG4_MASK (7 << PINT_PMCFG_CFG4_SHIFT) +# define PINT_PMCFG_CFG4(n) ((uint32_t)(n) << PINT_PMCFG_CFG4_SHIFT) +#define PINT_PMCFG_CFG5_SHIFT (8) /* Bits 23-25: Match condition for bit slice 5 */ +#define PINT_PMCFG_CFG5_MASK (7 << PINT_PMCFG_CFG5_SHIFT) +# define PINT_PMCFG_CFG5(n) ((uint32_t)(n) << PINT_PMCFG_CFG5_SHIFT) +#define PINT_PMCFG_CFG6_SHIFT (8) /* Bits 26-28: Match condition for bit slice 6 */ +#define PINT_PMCFG_CFG6_MASK (7 << PINT_PMCFG_CFG6_SHIFT) +# define PINT_PMCFG_CFG6(n) ((uint32_t)(n) << PINT_PMCFG_CFG6_SHIFT) +#define PINT_PMCFG_CFG7_SHIFT (8) /* Bits 29-31: Match condition for bit slice 7 */ +#define PINT_PMCFG_CFG7_MASK (7 << PINT_PMCFG_CFG7_SHIFT) +# define PINT_PMCFG_CFG7(n) ((uint32_t)(n) << PINT_PMCFG_CFG7_SHIFT) + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINT_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_rit.h b/arch/arm/src/lpc54xx/chip/lpc54_rit.h new file mode 100644 index 0000000000000000000000000000000000000000..9c63be06ad8b387b2fd414489dbcd695d417caf3 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_rit.h @@ -0,0 +1,87 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/lpc54_rit.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_RIT_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_RIT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC54_RIT_COMPVAL_OFFSET 0x0000 /* LS 48-bit Compare register */ +#define LPC54_RIT_MASK_OFFSET 0x0004 /* LS 48-bit Mask register */ +#define LPC54_RIT_CTRL_OFFSET 0x0008 /* Control register */ +#define LPC54_RIT_COUNTER_OFFSET 0x000c /* LS 48-bit counter */ +#define LPC54_RIT_COMPVALH_OFFSET 0x0010 /* MS 48-bit Compare register */ +#define LPC54_RIT_MASKH_OFFSET 0x0014 /* MS 48-bit Mask register */ +#define LPC54_RIT_COUNTERH_OFFSET 0x001c /* MS 48-bit counter */ + +/* Register addresses ***************************************************************/ + +#define LPC54_RIT_COMPVAL (LPC54_RIT_BASE+LPC54_RIT_COMPVAL_OFFSET) +#define LPC54_RIT_MASK (LPC54_RIT_BASE+LPC54_RIT_MASK_OFFSET) +#define LPC54_RIT_CTRL (LPC54_RIT_BASE+LPC54_RIT_CTRL_OFFSET) +#define LPC54_RIT_COUNTER (LPC54_RIT_BASE+LPC54_RIT_COUNTER_OFFSET) +#define LPC54_RIT_COMPVALH (LPC54_RIT_BASE+LPC54_RIT_COMPVALH_OFFSET) +#define LPC54_RIT_MASKH (LPC54_RIT_BASE+LPC54_RIT_MASKH_OFFSET) +#define LPC54_RIT_COUNTERH (LPC54_RIT_BASE+LPC54_RIT_COUNTERH_OFFSET) + +/* Register bit definitions *********************************************************/ +/* LS Compare register (Bits 0-31: value compared to the counter) */ +/* MS Compare register (Bits 21-47: value compared to the counter) */ + +/* LS Mask register (Bits 0-31: 32-bit mask value) */ +/* MS Mask register (Bits 32-47: 16-bit mask value) */ + +/* Control register */ + +#define RIT_CTRL_INT (1 << 0) /* Bit 0: Interrupt flag */ +#define RIT_CTRL_ENCLR (1 << 1) /* Bit 1: Timer enable clear */ +#define RIT_CTRL_ENBR (1 << 2) /* Bit 2: Timer enable for debug */ +#define RIT_CTRL_EN (1 << 3) /* Bit 3: Timer enable */ + /* Bits 4-31: Reserved */ +/* LS 48-bit counter (Bits 0-31: 48-bit up counter) */ +/* MS 48-bit counter (Bits 32-47: 48-bit up counter) */ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_RIT_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_rom.h b/arch/arm/src/lpc54xx/chip/lpc54_rom.h new file mode 100644 index 0000000000000000000000000000000000000000..32f5a32c610c7eed8ef9c7442b5e3fe5bb594017 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_rom.h @@ -0,0 +1,113 @@ +/******************************************************************************************** + * arch/arm/src/lpc54xx/lpc54_rom.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_ROM_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_ROM_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* Table offsets ****************************************************************************/ + +/* First level table offsets */ + +#define LPC54_USB_API_OFFSET 0x0000 +#define LPC54_OTP_API_OFFSET 0x0038 + +/* USB API table offsets (to be provided) */ + +/* OTP API driver table offsets */ + +#define LPC54_OTP_API_INIT_OFFSET 0x0000 +#define LPC54_OTP_API_ENABLEBANKWRITEMASK_OFFSET 0x0004 +#define LPC54_OTP_API_DISABLEBANKWRITEMASK_OFFSET 0x0008 +#define LPC54_OTP_API_ENABLEBANKWRITELOCK_OFFSET 0x000c +#define LPC54_OTP_API_ENABLEBANKREADLOCK_OFFSET 0x0010 +#define LPC54_OTP_API_PROGRAMREG_OFFSET 0x0014 +#define LPC54_OTP_API_RNGREAD_OFFSET 0x002c +#define LPC54_OTP_API_GETDRIVERVERSION_OFFSET 0x0030 + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/* Dereference the LPC54_ROM_DRIVERTAB address to get the address of the ROM driver table. + * Not often that I get to use a pointer-to-a-pointer-to-a-pointer. The result of de- + * referencing the LPC54_ROM_DRIVERTAB is a pointer to an array of type uinptr_t *. + */ + +#define lpc54_driver_vtable (*(uintptr_t ***)LPC54_ROM_DRIVERTAB) + +/* Index the ROM driver table to get the specific driver table. Perhaps in the future these + * uintptr_t * arrays would be replaced with proper vtable structures. + */ + +#define lpc54_usb_vtable lpc54_driver_vtable[LPC54_USB_API_OFFSET >> 2] +#define lpc54_otg_vtable lpc54_driver_vtable[LPC54_OTP_API_OFFSET >> 2] + +/* Then, finally, index the specific driver table to get the API entry point */ + +/******************************************************************************************** + * Public Types/Functions + ********************************************************************************************/ + +/******************************************************************************************** + * Name: lpc54_rng_read + * + * Description: + * Returns a 32 bit random number from hardware. The Random Number Generator is accessed + * through an API call located in the ROM. + * + * Input Parameters: + * None + * + * Returned Value: + * Unsigned random number + * + ********************************************************************************************/ + +typedef CODE unsigned int (*rng_read_t)(void); + +#define LPC54_RNG_READ ((rng_read_t)(lpc54_otg_vtable[LPC54_OTP_API_RNGREAD_OFFSET >> 2])) + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_ROM_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_rtc.h b/arch/arm/src/lpc54xx/chip/lpc54_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..5a6f730cdd57e5993fbe03b4ee0ad0ea1577ec41 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_rtc.h @@ -0,0 +1,96 @@ +/******************************************************************************************** + * arch/arm/src/lpc54xx/lpc54_rtc.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_RTC_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_RTC_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +#define LPC54_RTC_NGPREGS 8 /* Nubmer of general purpose registers */ + +/* Register offsets *************************************************************************/ + +#define LPC54_RTC_CTRL_OFFSET 0x0000 /* RTC control */ +#define LPC54_RTC_MATCH_OFFSET 0x0004 /* RTC match */ +#define LPC54_RTC_COUNT_OFFSET 0x0008 /* RTC counter */ +#define LPC54_RTC_WAKE_OFFSET 0x000c /* High-resolution/wake-up timer control */ + +/* General purpose registers */ + +#define LPC54_RTC_GPREG_OFFSET(n) (0x0040 + ((n) << 2)) + +/* Register addresses ***********************************************************************/ + +#define LPC54_RTC_CTRL (LPC54_RTC_BASE + LPC54_RTC_CTRL_OFFSET) +#define LPC54_RTC_MATCH (LPC54_RTC_BASE + LPC54_RTC_MATCH_OFFSET) +#define LPC54_RTC_COUNT (LPC54_RTC_BASE + LPC54_RTC_COUNT_OFFSET) +#define LPC54_RTC_WAKE (LPC54_RTC_BASE + LPC54_RTC_WAKE_OFFSET) + +/* General purpose registers */ + +#define LPC54_RTC_GPREG(n) (LPC54_RTC_BASE + LPC54_RTC_GPREG_OFFSET(n)) + +/* Register bit definitions *****************************************************************/ + +/* RTC control */ + +#define RTC_CTRL_SWRESET (1 << 0) /* Bit 0: Software reset control */ +#define RTC_CTRL_ALARM1HZ (1 << 2) /* Bit 2: RTC 1 Hz timer alarm flag status */ +#define RTC_CTRL_WAKE1KHZ (1 << 3) /* Bit 3: RTC 1 kHz timer wake-up flag status */ +#define RTC_CTRL_ALARMDPDEN (1 << 4) /* Bit 4: RTC 1 Hz timer alarm enable for deep power-down */ +#define RTC_CTRL_WAKEDPDEN (1 << 5) /* Bit 5: RTC 1 kHz timer wake-up enable for deep power-down */ +#define RTC_CTRL_RTC1KHZEN (1 << 6) /* Bit 6: RTC 1 kHz clock enable */ +#define RTC_CTRL_RTCEN (1 << 7) /* Bit 7: RTC enable */ +#define RTC_CTRL_OSCPD (1 << 8) /* Bit 8: RTC oscillator power-down control */ + +/* RTC match (32-bit timer match value) */ +/* RTC counter (32-bit counter value) */ + +/* High-resolution/wake-up timer control */ + +#define RTC_WAKE_MASK 0xffff /* Bits 0-15: 16 hi-resoution/wake-up timer */ + +/* General purpose registers (32-bit value) */ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_RTC_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_sdmmc.h b/arch/arm/src/lpc54xx/chip/lpc54_sdmmc.h new file mode 100644 index 0000000000000000000000000000000000000000..9c94ef728f02d50645262976172c78ec98a1ee33 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_sdmmc.h @@ -0,0 +1,401 @@ +/************************************************************************************************ + * arch/arm/src/lpc54xx/lpc54_sdmmc.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SDMMC_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SDMMC_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +#define LPC54_TXFIFO_DEPTH 32 +#define LPC54_TXFIFO_WIDTH 4 +#define LPC54_RXFIFO_DEPTH 32 +#define LPC54_RXFIFO_WIDTH 4 + +/* MCI register offsets (with respect to the MCI base) ******************************************/ + +#define LPC54_SDMMC_CTRL_OFFSET 0x0000 /* Control register */ +#define LPC54_SDMMC_PWREN_OFFSET 0x0004 /* Power Enable Register */ +#define LPC54_SDMMC_CLKDIV_OFFSET 0x0008 /* Clock-divider register */ +#define LPC54_SDMMC_CLKENA_OFFSET 0x0010 /* Clock-enable register */ +#define LPC54_SDMMC_TMOUT_OFFSET 0x0014 /* Time-out register */ +#define LPC54_SDMMC_CTYPE_OFFSET 0x0018 /* Card-type register */ +#define LPC54_SDMMC_BLKSIZ_OFFSET 0x001c /* Block-size register */ +#define LPC54_SDMMC_BYTCNT_OFFSET 0x0020 /* Byte-count register */ +#define LPC54_SDMMC_INTMASK_OFFSET 0x0024 /* Interrupt-mask register */ +#define LPC54_SDMMC_CMDARG_OFFSET 0x0028 /* Command-argument register */ +#define LPC54_SDMMC_CMD_OFFSET 0x002c /* Command register */ +#define LPC54_SDMMC_RESP0_OFFSET 0x0030 /* Response-0 register */ +#define LPC54_SDMMC_RESP1_OFFSET 0x0034 /* Response-1 register */ +#define LPC54_SDMMC_RESP2_OFFSET 0x0038 /* Response-2 register */ +#define LPC54_SDMMC_RESP3_OFFSET 0x003c /* Response-3 register */ +#define LPC54_SDMMC_MINTSTS_OFFSET 0x0040 /* Masked interrupt-status register */ +#define LPC54_SDMMC_RINTSTS_OFFSET 0x0044 /* Raw interrupt-status register */ +#define LPC54_SDMMC_STATUS_OFFSET 0x0048 /* Status register */ +#define LPC54_SDMMC_FIFOTH_OFFSET 0x004c /* FIFO threshold register */ +#define LPC54_SDMMC_CDETECT_OFFSET 0x0050 /* Card-detect register value */ +#define LPC54_SDMMC_WRTPRT_OFFSET 0x0054 /* Write-protect register */ +#define LPC54_SDMMC_TCBCNT_OFFSET 0x005c /* Transferred CIU card byte count */ +#define LPC54_SDMMC_TBBCNT_OFFSET 0x0060 /* Transferred host to BIU-FIFO byte count */ +#define LPC54_SDMMC_DEBNCE_OFFSET 0x0064 /* Debounce count register */ +#define LPC54_SDMMC_RSTN_OFFSET 0x0078 /* Hardware Reset */ +#define LPC54_SDMMC_BMOD_OFFSET 0x0080 /* Bus Mode Register */ +#define LPC54_SDMMC_PLDMND_OFFSET 0x0084 /* Poll Demand Register */ +#define LPC54_SDMMC_DBADDR_OFFSET 0x0088 /* Descriptor List Base Address Register */ +#define LPC54_SDMMC_IDSTS_OFFSET 0x008c /* Internal DMAC Status Register */ +#define LPC54_SDMMC_IDINTEN_OFFSET 0x0090 /* Internal DMAC Interrupt Enable Register */ +#define LPC54_SDMMC_DSCADDR_OFFSET 0x0094 /* Current Host Descriptor Address Register */ +#define LPC54_SDMMC_BUFADDR_OFFSET 0x0098 /* Current Buffer Descriptor Address Register */ +#define LPC54_SDMMC_CARDTHRCTL_OFFSET 0x0100 /* Card threshold control */ +#define LPC54_SDMMC_BACKENDPWRL_OFFSET 0x0104 /* Power control */ + +#define LPC54_SDMMC_DATA_OFFSET 0x0200 /* Data FIFO read/write (>=) */ + +/* MCI register (virtual) addresses *************************************************************/ + +#define LPC54_SDMMC_CTRL (LPC54_SDMMC_BASE + LPC54_SDMMC_CTRL_OFFSET) +#define LPC54_SDMMC_PWREN (LPC54_SDMMC_BASE + LPC54_SDMMC_PWREN_OFFSET) +#define LPC54_SDMMC_CLKDIV (LPC54_SDMMC_BASE + LPC54_SDMMC_CLKDIV_OFFSET) +#define LPC54_SDMMC_CLKENA (LPC54_SDMMC_BASE + LPC54_SDMMC_CLKENA_OFFSET) +#define LPC54_SDMMC_TMOUT (LPC54_SDMMC_BASE + LPC54_SDMMC_TMOUT_OFFSET) +#define LPC54_SDMMC_CTYPE (LPC54_SDMMC_BASE + LPC54_SDMMC_CTYPE_OFFSET) +#define LPC54_SDMMC_BLKSIZ (LPC54_SDMMC_BASE + LPC54_SDMMC_BLKSIZ_OFFSET) +#define LPC54_SDMMC_BYTCNT (LPC54_SDMMC_BASE + LPC54_SDMMC_BYTCNT_OFFSET) +#define LPC54_SDMMC_INTMASK (LPC54_SDMMC_BASE + LPC54_SDMMC_INTMASK_OFFSET) +#define LPC54_SDMMC_CMDARG (LPC54_SDMMC_BASE + LPC54_SDMMC_CMDARG_OFFSET) +#define LPC54_SDMMC_CMD (LPC54_SDMMC_BASE + LPC54_SDMMC_CMD_OFFSET) +#define LPC54_SDMMC_RESP0 (LPC54_SDMMC_BASE + LPC54_SDMMC_RESP0_OFFSET) +#define LPC54_SDMMC_RESP1 (LPC54_SDMMC_BASE + LPC54_SDMMC_RESP1_OFFSET) +#define LPC54_SDMMC_RESP2 (LPC54_SDMMC_BASE + LPC54_SDMMC_RESP2_OFFSET) +#define LPC54_SDMMC_RESP3 (LPC54_SDMMC_BASE + LPC54_SDMMC_RESP3_OFFSET) +#define LPC54_SDMMC_MINTSTS (LPC54_SDMMC_BASE + LPC54_SDMMC_MINTSTS_OFFSET) +#define LPC54_SDMMC_RINTSTS (LPC54_SDMMC_BASE + LPC54_SDMMC_RINTSTS_OFFSET) +#define LPC54_SDMMC_STATUS (LPC54_SDMMC_BASE + LPC54_SDMMC_STATUS_OFFSET) +#define LPC54_SDMMC_FIFOTH (LPC54_SDMMC_BASE + LPC54_SDMMC_FIFOTH_OFFSET) +#define LPC54_SDMMC_CDETECT (LPC54_SDMMC_BASE + LPC54_SDMMC_CDETECT_OFFSET) +#define LPC54_SDMMC_WRTPRT (LPC54_SDMMC_BASE + LPC54_SDMMC_WRTPRT_OFFSET) +#define LPC54_SDMMC_TCBCNT (LPC54_SDMMC_BASE + LPC54_SDMMC_TCBCNT_OFFSET) +#define LPC54_SDMMC_TBBCNT (LPC54_SDMMC_BASE + LPC54_SDMMC_TBBCNT_OFFSET) +#define LPC54_SDMMC_TBBCNT (LPC54_SDMMC_BASE + LPC54_SDMMC_TBBCNT_OFFSET) +#define LPC54_SDMMC_DEBNCE (LPC54_SDMMC_BASE + LPC54_SDMMC_DEBNCE_OFFSET) +#define LPC54_SDMMC_RSTN (LPC54_SDMMC_BASE + LPC54_SDMMC_RSTN_OFFSET) +#define LPC54_SDMMC_BMOD (LPC54_SDMMC_BASE + LPC54_SDMMC_BMOD_OFFSET) +#define LPC54_SDMMC_PLDMND (LPC54_SDMMC_BASE + LPC54_SDMMC_PLDMND_OFFSET) +#define LPC54_SDMMC_DBADDR (LPC54_SDMMC_BASE + LPC54_SDMMC_DBADDR_OFFSET) +#define LPC54_SDMMC_IDSTS (LPC54_SDMMC_BASE + LPC54_SDMMC_IDSTS_OFFSET) +#define LPC54_SDMMC_IDINTEN (LPC54_SDMMC_BASE + LPC54_SDMMC_IDINTEN_OFFSET) +#define LPC54_SDMMC_DSCADDR (LPC54_SDMMC_BASE + LPC54_SDMMC_DSCADDR_OFFSET) +#define LPC54_SDMMC_BUFADDR (LPC54_SDMMC_BASE + LPC54_SDMMC_BUFADDR_OFFSET) +#define LPC54_SDMMC_CARDTHRCTL (LPC54_SDMMC_BASE + LPC54_SDMMC_CARDTHRCTL_OFFSET) +#define LPC54_SDMMC_BACKENDPWRL (LPC54_SDMMC_BASE + LPC54_SDMMC_BACKENDPWRL_OFFSET) + +#define LPC54_SDMMC_DATA (LPC54_SDMMC_BASE + LPC54_SDMMC_DATA_OFFSET) + +/* MCI register bit definitions *****************************************************************/ + +/* Control register CTRL */ + +#define SDMMC_CTRL_CNTLRRESET (1 << 0) /* Bit 0: Reset Module controller */ +#define SDMMC_CTRL_FIFORESET (1 << 1) /* Bit 1: Reset to data FIFO to reset FIFO pointers */ +#define SDMMC_CTRL_DMARESET (1 << 2) /* Bit 2: Reset internal DMA interface control logic */ + /* Bit 3: Reserved */ +#define SDMMC_CTRL_INTENABLE (1 << 4) /* Bit 4: Enable interrupts */ + /* Bit 5: Reserved */ +#define SDMMC_CTRL_READWAIT (1 << 6) /* Bit 6: Assert read wait */ +#define SDMMC_CTRL_SENDIRQRESP (1 << 7) /* Bit 7: Send auto IRQ response */ +#define SDMMC_CTRL_ABORTREAD (1 << 8) /* Bit 8: Reset data state-machine (suspend sequence) */ +#define SDMMC_CTRL_SENDCCSD (1 << 9) /* Bit 9: Send CCSD to CE-ATA device */ +#define SDMMC_CTRL_AUTOSTOP (1 << 10) /* Bit 10: Send STOP after CCSD to CE-ATA device */ +#define SDMMC_CTRL_CEATAINT (1 << 11) /* Bit 11: CE-ATA device interrupts enabled */ + /* Bits 12-15: Reserved */ +#define SDMMC_CTRL_CDVA0 (1 << 16) /* Bit 16: Controls SD_VOLT0 pin */ +#define SDMMC_CTRL_CDVA1 (1 << 17) /* Bit 17: Controls SD_VOLT1 pin */ +#define SDMMC_CTRL_CDVA2 (1 << 18) /* Bit 18: Controls SD_VOLT2 pin */ + /* Bits 19-23: Reserved */ + /* Bit 24: Reserved - always write it as 0 */ +#define SDMMC_CTRL_INTDMA (1 << 25) /* Bit 25: SD/MMC DMA use */ + /* Bits 26-31: Reserved */ +/* Power Enable Register (PWREN) */ + +#define SDMMC_PWREN (1 << 0) /* Bit 0: Power on/off switch */ + /* Bits 1-31: Reserved */ +/* Clock divider register CLKDIV + * + * Clock division is 2*n. For example, value of 0 means divide by 2 * 0 = 0 (no division, + * bypass), value of 1 means divide by 2 * 1 = 2, value of 255 means divide by 2 * 255 = 510, + * and so on. + */ + +#define SDMMC_CLKDIV0_SHIFT (0) /* Bits 0-7: Clock divider 0 value */ +#define SDMMC_CLKDIV0_MASK (255 << SDMMC_CLKDIV0_SHIFT) +# define SDMMC_CLKDIV0(n) ((((n) + 1) >> 1) << SDMMC_CLKDIV0_SHIFT) + /* Bits 8-31: Reserved */ + +/* Clock enable register CLKENA */ + +#define SDMMC_CLKENA_ENABLE (1 << 0) /* Bit 0: Clock enable */ + /* Bits 1-15: Reserved */ +#define SDMMC_CLKENA_LOWPOWER (1 << 16) /* Bit 16: Low-power mode */ + /* Bits 17-31: Reserved */ +/* Timeout register TMOUT */ + +#define SDMMC_TMOUT_RESPONSE_SHIFT (0) /* Bits 0-7: Response timeout value */ +#define SDMMC_TMOUT_RESPONSE_MASK (255 << SDMMC_TMOUT_RESPONSE_SHIFT) +#define SDMMC_TMOUT_DATA_SHIFT (8) /* Bits 8-31: Data Read Timeout value */ +#define SDMMC_TMOUT_DATA_MASK (0x00ffffff << SDMMC_TMOUT_DATA_SHIFT) + +/* Card type register CTYPE */ + +#define SDMMC_CTYPE_WIDTH1 (0) /* 1-bit mode */ +#define SDMMC_CTYPE_WIDTH4 (1 << 0) /* Bit 0: 4-bit mode */ + /* Bits 1-15: Reserved */ +#define SDMMC_CTYPE_WIDTH8 (1 << 16) /* Bit 16: 8-bit mode */ + /* Bits 17-31: Reserved */ +/* Blocksize register BLKSIZ */ + +#define SDMMC_BLKSIZ_SHIFT (0) /* Bits 0-15: Block size */ +#define SDMMC_BLKSIZ_MASK (0xffff << SDMMC_BLKSIZ_SHIFT) + /* Bits 16-31: Reserved */ +/* Interrupt mask register INTMASK + * Masked interrupt status register MINTSTS + * Raw interrupt status register RINTSTS + */ + +#define SDMMC_INT_CDET (1 << 0) /* Bit 0: Card detect */ +#define SDMMC_INT_RE (1 << 1) /* Bit 1: Response error */ +#define SDMMC_INT_CDONE (1 << 2) /* Bit 2: Command done */ +#define SDMMC_INT_DTO (1 << 3) /* Bit 3: Data transfer over */ +#define SDMMC_INT_TXDR (1 << 4) /* Bit 4: Transmit FIFO data request */ +#define SDMMC_INT_RXDR (1 << 5) /* Bit 5: Receive FIFO data request */ +#define SDMMC_INT_RCRC (1 << 6) /* Bit 6: Response CRC error */ +#define SDMMC_INT_DCRC (1 << 7) /* Bit 7: Data CRC error */ +#define SDMMC_INT_RTO (1 << 8) /* Bit 8: Response timeout */ +#define SDMMC_INT_DRTO (1 << 9) /* Bit 9: Data read timeout */ +#define SDMMC_INT_HTO (1 << 10) /* Bit 10: Data starvation-by-cpu timeout */ +#define SDMMC_INT_FRUN (1 << 11) /* Bit 11: FIFO underrun/overrun error */ +#define SDMMC_INT_HLE (1 << 12) /* Bit 12: Hardware locked write error */ +#define SDMMC_INT_SBE (1 << 13) /* Bit 13: Start-bit error */ +#define SDMMC_INT_ACD (1 << 14) /* Bit 14: Auto command done */ +#define SDMMC_INT_EBE (1 << 15) /* Bit 15: End-bit error (read)/Write no CRC */ +#define SDMMC_INT_SDMMC (1 << 16) /* Bit 16: SD/MMC interrupt */ + /* Bits 17-31: Reserved */ +#define SDMMC_INT_ALL (0x1ffff) + +/* Command register CMD */ + +#define SDMMC_CMD_CMDINDEX_SHIFT (0) /* Bits 0-5: 5:0 Command index */ +#define SDMMC_CMD_CMDINDEX_MASK (63 << SDMMC_CMD_CMDINDEX_SHIFT) + +#define SDMMC_CMD_RESPONSE (1 << 6) /* Bit 6: Response expected from card */ +#define SDMMC_CMD_LONGRESP (1 << 7) /* Bit 7: Long response expected from card */ +#define SDMMC_CMD_WAITRESP_SHIFT (6) /* Bits 6-7: Response expected */ +#define SDMMC_CMD_WAITRESP_MASK (3 << SDMMC_CMD_WAITRESP_SHIFT) +# define SDMMC_CMD_NORESPONSE (0 << SDMMC_CMD_WAITRESP_SHIFT) /* x0: No response */ +# define SDMMC_CMD_SHORTRESPONSE (1 << SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response */ +# define SDMMC_CMD_LONGRESPONSE (3 << SDMMC_CMD_WAITRESP_SHIFT) /* 11: Long response */ +#define SDMMC_CMD_RESPCRC (1 << 8) /* Bit 8: Check response CRC */ +#define SDMMC_CMD_DATAXFREXPTD (1 << 9) /* Bit 9: Data transfer expected (read/write) */ +#define SDMMC_CMD_WRITE (1 << 10) /* Bit 10: Write to card */ +#define SDMMC_CMD_XFRMODE (1 << 11) /* Bit 11: Stream data transfer command */ +#define SDMMC_CMD_AUTOSTOP (1 << 12) /* Bit 12: Send stop command at end of data transfer */ +#define SDMMC_CMD_WAITPREV (1 << 13) /* Bit 13: Wait previous transfer complete before sending */ +#define SDMMC_CMD_STOPABORT (1 << 14) /* Bit 14: Stop current data transfer */ +#define SDMMC_CMD_SENDINIT (1 << 15) /* Bit 15: Send initialization sequence before command */ + /* Bits 16-20: Reserved */ +#define SDMMC_CMD_UPDCLOCK (1 << 21) /* Bit 21: Update clock register value (no command) */ +#define SDMMC_CMD_READCEATA (1 << 22) /* Bit 22: Performing read access on CE-ATA device */ +#define SDMMC_CMD_CCSEXPTD (1 << 23) /* Bit 23: Expect command completion from CE-ATA device */ +#define SDMMC_CMD_ENABOOT (1 << 24) /* Bit 24: Enable Boot */ +#define SDMMC_CMD_BACKEXPTED (1 << 25) /* Bit 25: Expect Boot Acknowledge */ +#define SDMMC_CMD_DISBOOT (1 << 26) /* Bit 26: Disable Boot */ +#define SDMMC_CMD_BOOTMODE (1 << 27) /* Bit 27: Boot Mode */ +#define SDMMC_CMD_VSWITCH (1 << 28) /* Bit 28: Voltage switch bit */ +#define SDMMC_CMD_USEHOLD (1 << 29) /* Bit 29: Use Hold Registert */ + /* Bit 30: Reserved */ +#define SDMMC_CMD_STARTCMD (1 << 31) /* Bit 31: Start command */ + +/* Status register STATUS */ + +#define SDMMC_STATUS_RXWMARK (1 << 0) /* Bit 0: FIFO reached Receive watermark level */ +#define SDMMC_STATUS_TXWMARK (1 << 1) /* Bit 1: FIFO reached Transmit watermark level */ +#define SDMMC_STATUS_FIFOEMPTY (1 << 2) /* Bit 2: FIFO is empty */ +#define SDMMC_STATUS_FIFOFULL (1 << 3) /* Bit 3: FIFO is full */ +#define SDMMC_STATUS_FSMSTATE_SHIFT (4) /* Bits 4-7: 7:4 Command FSM states */ +#define SDMMC_STATUS_FSMSTATE_MASK (15 << SDMMC_STATUS_FSMSTATE_SHIFT) +# define SDMMC_STATUS_FSMSTATE_IDLE (0 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Idle */ +# define SDMMC_STATUS_FSMSTATE_INIT (1 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Send init sequence */ +# define SDMMC_STATUS_FSMSTATE_TXSTART (2 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd start bit */ +# define SDMMC_STATUS_FSMSTATE_TXTXBIT (3 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd tx bit */ +# define SDMMC_STATUS_FSMSTATE_TXCMDARG (4 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd index + arg */ +# define SDMMC_STATUS_FSMSTATE_TXCMDCRC (5 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd crc7 */ +# define SDMMC_STATUS_FSMSTATE_TXEND (6 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Tx cmd end bit */ +# define SDMMC_STATUS_FSMSTATE_RXSTART (7 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp start bit */ +# define SDMMC_STATUS_FSMSTATE_RXIRQ (8 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp IRQ response */ +# define SDMMC_STATUS_FSMSTATE_RXTXBIT (9 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp tx bit */ +# define SDMMC_STATUS_FSMSTATE_RXCMD (10 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp cmd idx */ +# define SDMMC_STATUS_FSMSTATE_RXRESP (11 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp data */ +# define SDMMC_STATUS_FSMSTATE_RXRESPCRC (12 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp crc7 */ +# define SDMMC_STATUS_FSMSTATE_RXEND (13 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Rx resp end bit */ +# define SDMMC_STATUS_FSMSTATE_WAITNCC (14 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Cmd path wait NCC */ +# define SDMMC_STATUS_FSMSTATE_WAITTURN (15 << SDMMC_STATUS_FSMSTATE_SHIFT) /* Wait; CMD-to-resp turnaround */ +#define SDMMC_STATUS_DAT3 (1 << 8) /* Bit 8: DAT3=1: Card present */ +#define SDMMC_STATUS_DATABUSY (1 << 9) /* Bit 9: Card data busy */ +#define SDMMC_STATUS_MCBUSY (1 << 10) /* Bit 10: Data transmit/receive state machine busy */ +#define SDMMC_STATUS_RESPINDEX_SHIFT (11) /* Bits 11-16: Index of previous response */ +#define SDMMC_STATUS_RESPINDEX_MASK (63 << SDMMC_STATUS_RESPINDEX_SHIFT) +#define SDMMC_STATUS_FIFOCOUNT_SHIFT (17) /* Bits 17-29: FIFO count */ +#define SDMMC_STATUS_FIFOCOUNT_MASK (0x1fff << SDMMC_STATUS_FIFOCOUNT_SHIFT) +#define SDMMC_STATUS_DMAACK (1 << 30) /* Bit 30: DMA acknowledge signal state */ +#define SDMMC_STATUS_DMAREQ (1 << 31) /* Bit 31: DMA request signal state */ + +/* FIFO threshold register FIFOTH */ + +#define SDMMC_FIFOTH_TXWMARK_SHIFT (0) /* Bits 0-11: FIFO threshold level when transmitting */ +#define SDMMC_FIFOTH_TXWMARK_MASK (0xfff << SDMMC_FIFOTH_TXWMARK_SHIFT) +# define SDMMC_FIFOTH_TXWMARK(n) ((uint32_t)(n) << SDMMC_FIFOTH_TXWMARK_SHIFT) + /* Bits 12-15: Reserved */ +#define SDMMC_FIFOTH_RXWMARK_SHIFT (16) /* Bits 16-27: FIFO threshold level when receiving */ +#define SDMMC_FIFOTH_RXWMARK_MASK (0xfff << SDMMC_FIFOTH_RXWMARK_SHIFT) +# define SDMMC_FIFOTH_RXWMARK(n) ((uint32_t)(n) << SDMMC_FIFOTH_RXWMARK_SHIFT) +#define SDMMC_FIFOTH_DMABURST_SHIFT (28) /* Bits 28-30: Burst size for multiple transaction */ +#define SDMMC_FIFOTH_DMABURST_MASK (7 << SDMMC_FIFOTH_DMABURST_SHIFT) +# define SDMMC_FIFOTH_DMABURST_1XFR (0 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 1 transfer */ +# define SDMMC_FIFOTH_DMABURST_4XFRS (1 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 4 transfers */ +# define SDMMC_FIFOTH_DMABURST_8XFRS (2 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 8 transfers */ +# define SDMMC_FIFOTH_DMABURST_16XFRS (3 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 16 transfers */ +# define SDMMC_FIFOTH_DMABURST_32XFRS (4 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 32 transfers */ +# define SDMMC_FIFOTH_DMABURST_64XFRS (5 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 64 transfers */ +# define SDMMC_FIFOTH_DMABURST_128XFRS (6 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 128 transfers */ +# define SDMMC_FIFOTH_DMABURST_256XFRS (7 << SDMMC_FIFOTH_DMABURST_SHIFT) /* 256 transfers */ + /* Bit 31: Reserved */ +/* Card detect register CDETECT */ + +#define SDMMC_CDETECT_NOTPRESENT (1 << 0) /* Bit 0: Card detect */ + /* Bit 1-31: Reserved */ +/* Write protect register WRTPRT */ + +#define SDMMC_WRTPRT_PROTECTED (1 << 0) /* Bit 0: Write protect */ + /* Bit 1-31: Reserved */ +/* Debounce count register */ + +#define SDMMC_DEBNCE_MASK 0x00ffffff /* Bits 0-23: Debounce count */ + /* Bit 24-31: Reserved */ + +/* Hardware Reset */ + +#define SDMMC_RSTN (1 << 0) /* Bit 0: Hardware reset */ + /* Bit 1-31: Reserved */ + +/* Bus Mode Register */ + +#define SDMMC_BMOD_SWR (1 << 0) /* Bit 0: Software Reset */ +#define SDMMC_BMOD_FB (1 << 1) /* Bit 1: Fixed Burst */ +#define SDMMC_BMOD_DSL_SHIFT (2) /* Bits 2-6: Descriptor Skip Length */ +#define SDMMC_BMOD_DSL_MASK (31 << SDMMC_BMOD_DSL_SHIFT) +# define SDMMC_BMOD_DSL(n) ((uint32_t)(n) << SDMMC_BMOD_DSL_SHIFT) +#define SDMMC_BMOD_DE (1 << 7) /* Bit 7: SD/MMC DMA Enable */ +#define SDMMC_BMOD_PBL_SHIFT (8) /* Bits 8-10: Programmable Burst Length */ +#define SDMMC_BMOD_PBL_MASK (7 << SDMMC_BMOD_PBL_SHIFT) +# define SDMMC_BMOD_PBL_1XFRS (0 << SDMMC_BMOD_PBL_SHIFT) /* 1 transfer */ +# define SDMMC_BMOD_PBL_4XFRS (1 << SDMMC_BMOD_PBL_SHIFT) /* 4 transfers */ +# define SDMMC_BMOD_PBL_8XFRS (2 << SDMMC_BMOD_PBL_SHIFT) /* 8 transfers */ +# define SDMMC_BMOD_PBL_16XFRS (3 << SDMMC_BMOD_PBL_SHIFT) /* 16 transfers */ +# define SDMMC_BMOD_PBL_32XFRS (4 << SDMMC_BMOD_PBL_SHIFT) /* 32 transfers */ +# define SDMMC_BMOD_PBL_64XFRS (5 << SDMMC_BMOD_PBL_SHIFT) /* 64 transfers */ +# define SDMMC_BMOD_PBL_128XFRS (6 << SDMMC_BMOD_PBL_SHIFT) /* 128 transfers */ +# define SDMMC_BMOD_PBL_256XFRS (7 << SDMMC_BMOD_PBL_SHIFT) /* 256 transfers */ + /* Bits 11-31: Reserved */ +/* Internal DMAC Status Register */ + +#define SDMMC_IDSTS_TI (1 << 0) /* Bit 0: Transmit Interrupt */ +#define SDMMC_IDSTS_RI (1 << 1) /* Bit 1: Receive Interrupt */ +#define SDMMC_IDSTS_FBE (1 << 2) /* Bit 2: Fatal Bus Error Interrupt */ + /* Bit 3: Reserved */ +#define SDMMC_IDSTS_DU (1 << 4) /* Bit 4: Descriptor Unavailable Interrupt */ +#define SDMMC_IDSTS_CES (1 << 5) /* Bit 5: Card Error Summary */ + /* Bits 6-7: Reserved */ +#define SDMMC_IDSTS_NIS (1 << 8) /* Bit 8: Normal Interrupt Summary */ +#define SDMMC_IDSTS_AIS (1 << 9) /* Bit 9: Abnormal Interrupt Summary */ +#define SDMMC_IDSTS_EB_SHIFT (10) /* Bits 10-12: Error Bits */ +#define SDMMC_IDSTS_EB_MASK (7 << SDMMC_IDSTS_EB_SHIFT) +# define SDMMC_IDSTS_EB_TXHABORT (1 << SDMMC_IDSTS_EB_SHIFT) /* Host Abort received during transmission */ +# define SDMMC_IDSTS_EB_RXHABORT (2 << SDMMC_IDSTS_EB_SHIFT) /* Host Abort received during reception */ +#define SDMMC_IDSTS_FSM_SHIFT (13) /* Bits 13-16: DMAC state machine present state */ +#define SDMMC_IDSTS_FSM_MASK (15 << SDMMC_IDSTS_FSM_SHIFT) +# define SDMMC_IDSTS_FSM_DMAIDLE (0 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_IDLE*/ +# define SDMMC_IDSTS_FSM_DMASUSP (1 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_SUSPEND */ +# define SDMMC_IDSTS_FSM_DESCRD (2 << SDMMC_IDSTS_FSM_SHIFT) /* DESC_RD */ +# define SDMMC_IDSTS_FSM_DESCCHK (3 << SDMMC_IDSTS_FSM_SHIFT) /* DESC_CHK */ +# define SDMMC_IDSTS_FSM_DMARDREQW (4 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_RD_REQ_WAIT */ +# define SDMMC_IDSTS_FSM_DMAWRREQW (5 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_WR_REQ_WAIT */ +# define SDMMC_IDSTS_FSM_DMARD (6 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_RD */ +# define SDMMC_IDSTS_FSM_DMAWR (7 << SDMMC_IDSTS_FSM_SHIFT) /* DMA_WR */ +# define SDMMC_IDSTS_FSM_DMACLOSE (8 << SDMMC_IDSTS_FSM_SHIFT) /* DESC_CLOSE */ + /* Bits 17-31: Reserved */ +/* Internal DMAC Interrupt Enable Register */ + +#define SDMMC_IDINTEN_TI (1 << 0) /* Bit 0: Transmit Interrupt */ +#define SDMMC_IDINTEN_RI (1 << 1) /* Bit 1: Receive Interrupt */ +#define SDMMC_IDINTEN_FBE (1 << 2) /* Bit 2: Fatal Bus Error Interrupt */ + /* Bit 3: Reserved */ +#define SDMMC_IDINTEN_DU (1 << 4) /* Bit 4: Descriptor Unavailable Interrupt */ +#define SDMMC_IDINTEN_CES (1 << 5) /* Bit 5: Card Error Summary */ + /* Bits 6-7: Reserved */ +#define SDMMC_IDINTEN_NIS (1 << 8) /* Bit 8: Normal Interrupt Summary */ +#define SDMMC_IDINTEN_AIS (1 << 9) /* Bit 9: Abnormal Interrupt Summary */ + /* Bits 10-31: Reserved */ +#define SDMMC_IDINTEN_ALL 0x00000333 + +/* Card threshold control */ + +#define SDMMC_CARDTHRCTL_CARDRDTHREN (1 << 0) /* Bit 0: Card read threshold enable */ +#define SDMMC_CARDTHRCTL_BSYCLRINTEN (1 << 1) /* Bit 1: Busy clear interrupt enable */ + /* Bits 1-15: Reserved */ +#define SDMMC_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16) /* Bits 16-23: Card threshold size */ +#define SDMMC_CARDTHRCTL_CARDTHRESHOLD_MASK (0xff << SDMMC_CARDTHRCTL_CARDTHRESHOLD_SHIFT) + +/* Power control */ + +#define SDMMC_BACKENDPWRL (1 << 0) /* Bit 0: Back-end Power control for card application. */ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SDMMC_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_spi.h b/arch/arm/src/lpc54xx/chip/lpc54_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..9ab286e18a9a02895093eafd273e5329691b9ba1 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_spi.h @@ -0,0 +1,297 @@ +/**************************************************************************************************** + * arch/arm/src/lpc54xx/lpc54_spi.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SPI_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SPI_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register offsets *********************************************************************************/ + +/* Registers for the SPI function */ + +#define LPC54_SPI_CFG_OFFSET 0x0400 /* SPI Configuration register */ +#define LPC54_SPI_DLY_OFFSET 0x0404 /* SPI Delay register */ +#define LPC54_SPI_STAT_OFFSET 0x0408 /* SPI Status */ +#define LPC54_SPI_INTENSET_OFFSET 0x040c /* SPI Interrupt Enable read and set */ +#define LPC54_SPI_INTENCLR_OFFSET 0x0410 /* SPI Interrupt Enable Clear */ +#define LPC54_SPI_DIV_OFFSET 0x0424 /* SPI clock Divider */ +#define LPC54_SPI_INTSTAT_OFFSET 0x0428 /* SPI Interrupt Status */ + +/* Registers for FIFO control and data access */ + +#define LPC54_SPI_FIFOCFG_OFFSET 0x0e00 /* FIFO configuration and enable register */ +#define LPC54_SPI_FIFOSTAT_OFFSET 0x0e04 /* FIFO status register */ +#define LPC54_SPI_FIFOTRIG_OFFSET 0x0e08 /* FIFO trigger level settings for interrupt and DMA request */ +#define LPC54_SPI_FIFOINTENSET_OFFSET 0x0e10 /* FIFO interrupt enable set (enable) and read register */ +#define LPC54_SPI_FIFOINTENCLR_OFFSET 0x0e14 /* FIFO interrupt enable clear (disable) and read register */ +#define LPC54_SPI_FIFOINTSTAT_OFFSET 0x0e18 /* FIFO interrupt status register */ +#define LPC54_SPI_FIFOWR_OFFSET 0x0e20 /* FIFO write data */ +#define LPC54_SPI_FIFORD_OFFSET 0x0e30 /* FIFO read data */ +#define LPC54_SPI_FIFORDNOPOP_OFFSET 0x0e40 /* FIFO data read with no FIFO pop */ + +/* ID register */ + +#define LPC54_SPI_ID_OFFSET 0x0ffc /* SPI module Identification */ + +/* Register addresses *******************************************************************************/ + +#define LPC54_SPI0_CFG (LPC54_FLEXCOMM0_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI0_DLY (LPC54_FLEXCOMM0_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI0_STAT (LPC54_FLEXCOMM0_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI0_INTENSET (LPC54_FLEXCOMM0_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI0_INTENCLR (LPC54_FLEXCOMM0_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI0_DIV (LPC54_FLEXCOMM0_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI0_INTSTAT (LPC54_FLEXCOMM0_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI0_FIFOCFG (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI0_FIFOSTAT (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI0_FIFOTRIG (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI0_FIFOINTENSET (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI0_FIFOINTENCLR (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI0_FIFOINTSTAT (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI0_FIFOWR (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI0_FIFORD (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI0_FIFORDNOPOP (LPC54_FLEXCOMM0_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI0_ID (LPC54_FLEXCOMM0_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI1_CFG (LPC54_FLEXCOMM1_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI1_DLY (LPC54_FLEXCOMM1_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI1_STAT (LPC54_FLEXCOMM1_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI1_INTENSET (LPC54_FLEXCOMM1_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI1_INTENCLR (LPC54_FLEXCOMM1_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI1_DIV (LPC54_FLEXCOMM1_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI1_INTSTAT (LPC54_FLEXCOMM1_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI1_FIFOCFG (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI1_FIFOSTAT (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI1_FIFOTRIG (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI1_FIFOINTENSET (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI1_FIFOINTENCLR (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI1_FIFOINTSTAT (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI1_FIFOWR (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI1_FIFORD (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI1_FIFORDNOPOP (LPC54_FLEXCOMM1_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI1_ID (LPC54_FLEXCOMM1_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI2_CFG (LPC54_FLEXCOMM2_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI2_DLY (LPC54_FLEXCOMM2_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI2_STAT (LPC54_FLEXCOMM2_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI2_INTENSET (LPC54_FLEXCOMM2_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI2_INTENCLR (LPC54_FLEXCOMM2_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI2_DIV (LPC54_FLEXCOMM2_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI2_INTSTAT (LPC54_FLEXCOMM2_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI2_FIFOCFG (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI2_FIFOSTAT (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI2_FIFOTRIG (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI2_FIFOINTENSET (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI2_FIFOINTENCLR (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI2_FIFOINTSTAT (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI2_FIFOWR (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI2_FIFORD (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI2_FIFORDNOPOP (LPC54_FLEXCOMM2_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI2_ID (LPC54_FLEXCOMM2_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI3_CFG (LPC54_FLEXCOMM3_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI3_DLY (LPC54_FLEXCOMM3_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI3_STAT (LPC54_FLEXCOMM3_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI3_INTENSET (LPC54_FLEXCOMM3_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI3_INTENCLR (LPC54_FLEXCOMM3_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI3_DIV (LPC54_FLEXCOMM3_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI3_INTSTAT (LPC54_FLEXCOMM3_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI3_FIFOCFG (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI3_FIFOSTAT (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI3_FIFOTRIG (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI3_FIFOINTENSET (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI3_FIFOINTENCLR (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI3_FIFOINTSTAT (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI3_FIFOWR (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI3_FIFORD (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI3_FIFORDNOPOP (LPC54_FLEXCOMM3_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI3_ID (LPC54_FLEXCOMM3_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI4_CFG (LPC54_FLEXCOMM4_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI4_DLY (LPC54_FLEXCOMM4_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI4_STAT (LPC54_FLEXCOMM4_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI4_INTENSET (LPC54_FLEXCOMM4_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI4_INTENCLR (LPC54_FLEXCOMM4_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI4_DIV (LPC54_FLEXCOMM4_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI4_INTSTAT (LPC54_FLEXCOMM4_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI4_FIFOCFG (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI4_FIFOSTAT (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI4_FIFOTRIG (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI4_FIFOINTENSET (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI4_FIFOINTENCLR (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI4_FIFOINTSTAT (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI4_FIFOWR (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI4_FIFORD (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI4_FIFORDNOPOP (LPC54_FLEXCOMM4_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI4_ID (LPC54_FLEXCOMM4_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI5_CFG (LPC54_FLEXCOMM5_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI5_DLY (LPC54_FLEXCOMM5_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI5_STAT (LPC54_FLEXCOMM5_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI5_INTENSET (LPC54_FLEXCOMM5_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI5_INTENCLR (LPC54_FLEXCOMM5_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI5_DIV (LPC54_FLEXCOMM5_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI5_INTSTAT (LPC54_FLEXCOMM5_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI5_FIFOCFG (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI5_FIFOSTAT (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI5_FIFOTRIG (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI5_FIFOINTENSET (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI5_FIFOINTENCLR (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI5_FIFOINTSTAT (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI5_FIFOWR (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI5_FIFORD (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI5_FIFORDNOPOP (LPC54_FLEXCOMM5_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI5_ID (LPC54_FLEXCOMM5_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI6_CFG (LPC54_FLEXCOMM6_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI6_DLY (LPC54_FLEXCOMM6_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI6_STAT (LPC54_FLEXCOMM6_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI6_INTENSET (LPC54_FLEXCOMM6_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI6_INTENCLR (LPC54_FLEXCOMM6_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI6_DIV (LPC54_FLEXCOMM6_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI6_INTSTAT (LPC54_FLEXCOMM6_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI6_FIFOCFG (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI6_FIFOSTAT (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI6_FIFOTRIG (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI6_FIFOINTENSET (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI6_FIFOINTENCLR (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI6_FIFOINTSTAT (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI6_FIFOWR (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI6_FIFORD (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI6_FIFORDNOPOP (LPC54_FLEXCOMM6_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI6_ID (LPC54_FLEXCOMM6_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI7_CFG (LPC54_FLEXCOMM7_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI7_DLY (LPC54_FLEXCOMM7_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI7_STAT (LPC54_FLEXCOMM7_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI7_INTENSET (LPC54_FLEXCOMM7_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI7_INTENCLR (LPC54_FLEXCOMM7_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI7_DIV (LPC54_FLEXCOMM7_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI7_INTSTAT (LPC54_FLEXCOMM7_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI7_FIFOCFG (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI7_FIFOSTAT (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI7_FIFOTRIG (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI7_FIFOINTENSET (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI7_FIFOINTENCLR (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI7_FIFOINTSTAT (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI7_FIFOWR (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI7_FIFORD (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI7_FIFORDNOPOP (LPC54_FLEXCOMM7_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI7_ID (LPC54_FLEXCOMM7_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI8_CFG (LPC54_FLEXCOMM8_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI8_DLY (LPC54_FLEXCOMM8_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI8_STAT (LPC54_FLEXCOMM8_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI8_INTENSET (LPC54_FLEXCOMM8_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI8_INTENCLR (LPC54_FLEXCOMM8_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI8_DIV (LPC54_FLEXCOMM8_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI8_INTSTAT (LPC54_FLEXCOMM8_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI8_FIFOCFG (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI8_FIFOSTAT (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI8_FIFOTRIG (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI8_FIFOINTENSET (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI8_FIFOINTENCLR (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI8_FIFOINTSTAT (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI8_FIFOWR (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI8_FIFORD (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI8_FIFORDNOPOP (LPC54_FLEXCOMM8_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI8_ID (LPC54_FLEXCOMM8_BASE + LPC54_SPI_ID_OFFSET) + +#define LPC54_SPI9_CFG (LPC54_FLEXCOMM9_BASE + LPC54_SPI_CFG_OFFSET) +#define LPC54_SPI9_DLY (LPC54_FLEXCOMM9_BASE + LPC54_SPI_DLY_OFFSET) +#define LPC54_SPI9_STAT (LPC54_FLEXCOMM9_BASE + LPC54_SPI_STAT_OFFSET) +#define LPC54_SPI9_INTENSET (LPC54_FLEXCOMM9_BASE + LPC54_SPI_INTENSET_OFFSET) +#define LPC54_SPI9_INTENCLR (LPC54_FLEXCOMM9_BASE + LPC54_SPI_INTENCLR_OFFSET) +#define LPC54_SPI9_DIV (LPC54_FLEXCOMM9_BASE + LPC54_SPI_DIV_OFFSET) +#define LPC54_SPI9_INTSTAT (LPC54_FLEXCOMM9_BASE + LPC54_SPI_INTSTAT_OFFSET) +#define LPC54_SPI9_FIFOCFG (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFOCFG_OFFSET) +#define LPC54_SPI9_FIFOSTAT (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFOSTAT_OFFSET) +#define LPC54_SPI9_FIFOTRIG (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFOTRIG_OFFSET) +#define LPC54_SPI9_FIFOINTENSET (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFOINTENSET_OFFSET) +#define LPC54_SPI9_FIFOINTENCLR (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFOINTENCLR_OFFSET) +#define LPC54_SPI9_FIFOINTSTAT (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFOINTSTAT_OFFSET) +#define LPC54_SPI9_FIFOWR (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFOWR_OFFSET) +#define LPC54_SPI9_FIFORD (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFORD_OFFSET) +#define LPC54_SPI9_FIFORDNOPOP (LPC54_FLEXCOMM9_BASE + LPC54_SPI_FIFORDNOPOP_OFFSET) +#define LPC54_SPI9_ID (LPC54_FLEXCOMM9_BASE + LPC54_SPI_ID_OFFSET) + +/* Register bit definitions *************************************************************************/ + +/* SPI Configuration register */ +#define SPI_CFG_ +/* SPI Delay register */ +#define SPI_DLY_ +/* SPI Status register */ +#define SPI_STAT_ +/* SPI Interrupt Enable read and set */ +#define SPI_INTENSET_ +/* SPI Interrupt Enable Clear */ +#define SPI_INTENCLR_ +/* SPI clock Divider */ +#define SPI_DIV_ +/* SPI Interrupt Status */ +#define SPI_INTSTAT_ +/* FIFO configuration and enable register */ +#define SPI_FIFOCFG_ +/* FIFO status register */ +#define SPI_FIFOSTAT_ +/* FIFO trigger level settings for interrupt and DMA request */ +#define SPI_FIFOTRIG_ +/* FIFO interrupt enable set (enable) and read register */ +#define SPI_FIFOINTENSET_ +/* FIFO interrupt enable clear (disable) and read register */ +#define SPI_FIFOINTENCLR_ +/* FIFO interrupt status register */ +#define SPI_FIFOINTSTAT_ +/* FIFO write data */ +#define SPI_FIFOWR_ +/* FIFO read data */ +#define SPI_FIFORD_ +/* FIFO data read with no FIFO pop */ +#define SPI_FIFORDNOPOP_ +/* SPI module Identification */ +#define SPI_ID_ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SPI_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_syscon.h b/arch/arm/src/lpc54xx/chip/lpc54_syscon.h new file mode 100644 index 0000000000000000000000000000000000000000..2de9d22540d135ee921810b820c4b3050bff47b8 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_syscon.h @@ -0,0 +1,924 @@ +/******************************************************************************************** + * arch/arm/src/lpc54xx/chip/lpc54_syscon.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SYSCON_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SYSCON_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *************************************************************************/ + +/* Main system configuration */ + +#define LPC54_SYSCON_AHBMATPRIO_OFFSET 0x0010 /* AHB multilayer matrix priority control */ +#define LPC54_SYSCON_SYSTCKCAL_OFFSET 0x0040 /* System tick counter calibration */ +#define LPC54_SYSCON_NMISRC_OFFSET 0x0048 /* NMI source select */ +#define LPC54_SYSCON_ASYNCAPBCTRL_OFFSET 0x004c /* Asynchronous APB control */ +#define LPC54_SYSCON_PIOPORCAP0_OFFSET 0x00c0 /* POR captured value of port 0 */ +#define LPC54_SYSCON_PIOPORCAP1_OFFSET 0x00c4 /* POR captured value of port 1 */ +#define LPC54_SYSCON_PIORESCAP0_OFFSET 0x00d0 /* Reset captured value of port 0 */ +#define LPC54_SYSCON_PIORESCAP1_OFFSET 0x00d4 /* Reset captured value of port 1 */ +#define LPC54_SYSCON_PRESETCTRL0_OFFSET 0x0100 /* Peripheral reset control 0 */ +#define LPC54_SYSCON_PRESETCTRL1_OFFSET 0x0104 /* Peripheral reset control 1 */ +#define LPC54_SYSCON_PRESETCTRL2_OFFSET 0x0108 /* Peripheral reset control 2 */ +#define LPC54_SYSCON_PRESETCTRLSET0_OFFSET 0x0120 /* Set bits in PRESETCTRL0 */ +#define LPC54_SYSCON_PRESETCTRLSET1_OFFSET 0x0124 /* Set bits in PRESETCTRL1 */ +#define LPC54_SYSCON_PRESETCTRLSET2_OFFSET 0x0128 /* Set bits in PRESETCTRL2 */ +#define LPC54_SYSCON_PRESETCTRLCLR0_OFFSET 0x0140 /* Clear bits in PRESETCTRL0 */ +#define LPC54_SYSCON_PRESETCTRLCLR1_OFFSET 0x0144 /* Clear bits in PRESETCTRL1 */ +#define LPC54_SYSCON_PRESETCTRLCLR2_OFFSET 0x0148 /* Clear bits in PRESETCTRL2 */ +#define LPC54_SYSCON_SYSRSTSTAT_OFFSET 0x01f0 /* System reset status register */ +#define LPC54_SYSCON_AHBCLKCTRL0_OFFSET 0x0200 /* AHB Clock control 0 */ +#define LPC54_SYSCON_AHBCLKCTRL1_OFFSET 0x0204 /* AHB Clock control 1 */ +#define LPC54_SYSCON_AHBCLKCTRL2_OFFSET 0x0208 /* AHB Clock control 2 */ +#define LPC54_SYSCON_AHBCLKCTRLSET0_OFFSET 0x0220 /* Set bits in AHBCLKCTRL0 */ +#define LPC54_SYSCON_AHBCLKCTRLSET1_OFFSET 0x0224 /* Set bits in AHBCLKCTRL1 */ +#define LPC54_SYSCON_AHBCLKCTRLSET2_OFFSET 0x0228 /* Set bits in AHBCLKCTRL2 */ +#define LPC54_SYSCON_AHBCLKCTRLCLR0_OFFSET 0x0240 /* Clear bits in AHBCLKCTRL0 */ +#define LPC54_SYSCON_AHBCLKCTRLCLR1_OFFSET 0x0244 /* Clear bits in AHBCLKCTRL1 */ +#define LPC54_SYSCON_AHBCLKCTRLCLR2_OFFSET 0x0248 /* Clear bits in AHBCLKCTRL2 */ +#define LPC54_SYSCON_MAINCLKSELA_OFFSET 0x0280 /* Main clock source select A */ +#define LPC54_SYSCON_MAINCLKSELB_OFFSET 0x0284 /* Main clock source select B */ +#define LPC54_SYSCON_CLKOUTSELA_OFFSET 0x0288 /* CLKOUT clock source select */ +#define LPC54_SYSCON_SYSPLLCLKSEL_OFFSET 0x0290 /* PLL clock source select */ +#define LPC54_SYSCON_AUDPLLCLKSEL_OFFSET 0x0298 /* Audio PLL clock source select */ +#define LPC54_SYSCON_SPIFICLKSEL_OFFSET 0x02a0 /* SPIFI clock source select */ +#define LPC54_SYSCON_ADCCLKSEL_OFFSET 0x02a4 /* ADC clock source select */ +#define LPC54_SYSCON_USB0CLKSEL_OFFSET 0x02a8 /* USB0 clock source select */ +#define LPC54_SYSCON_USB1CLKSEL_OFFSET 0x02ac /* USB1 clock source select */ +#define LPC54_SYSCON_FCLKSEL0_OFFSET 0x02b0 /* Flexcomm Interface 0 clock source select */ +#define LPC54_SYSCON_FCLKSEL1_OFFSET 0x02b4 /* Flexcomm Interface 1 clock source select */ +#define LPC54_SYSCON_FCLKSEL2_OFFSET 0x02b8 /* Flexcomm Interface 2 clock source select */ +#define LPC54_SYSCON_FCLKSEL3_OFFSET 0x02bc /* Flexcomm Interface 3 clock source select */ +#define LPC54_SYSCON_FCLKSEL4_OFFSET 0x02c0 /* Flexcomm Interface 4 clock source select */ +#define LPC54_SYSCON_FCLKSEL5_OFFSET 0x02c4 /* Flexcomm Interface 5 clock source select */ +#define LPC54_SYSCON_FCLKSEL6_OFFSET 0x02c8 /* Flexcomm Interface 6 clock source select */ +#define LPC54_SYSCON_FCLKSEL7_OFFSET 0x02cc /* Flexcomm Interface 7 clock source select */ +#define LPC54_SYSCON_FCLKSEL8_OFFSET 0x02d0 /* Flexcomm Interface 8 clock source select */ +#define LPC54_SYSCON_FCLKSEL9_OFFSET 0x02d4 /* Flexcomm Interface 9 clock source select */ +#define LPC54_SYSCON_MCLKCLKSEL_OFFSET 0x02e0 /* MCLK clock source select */ +#define LPC54_SYSCON_FRGCLKSEL_OFFSET 0x02e8 /* Fractional Rate Generator clock source select */ +#define LPC54_SYSCON_DMICCLKSEL_OFFSET 0x02ec /* Digital microphone (DMIC) subsystem clock select */ +#define LPC54_SYSCON_SCTCLKSEL_OFFSET 0x02f0 /* SCTimer/PWM clock source select */ +#define LPC54_SYSCON_LCDCLKSEL_OFFSET 0x02f4 /* LCD clock source select */ +#define LPC54_SYSCON_SDIOCLKSEL_OFFSET 0x02f8 /* SDIO clock source select */ +#define LPC54_SYSCON_SYSTICKCLKDIV_OFFSET 0x0300 /* SYSTICK clock divider */ +#define LPC54_SYSCON_ARMTRCLKDIV_OFFSET 0x0304 /* ARM Trace clock divider */ +#define LPC54_SYSCON_CAN0CLKDIV_OFFSET 0x0308 /* MCAN0 clock divider */ +#define LPC54_SYSCON_CAN1CLKDIV_OFFSET 0x030c /* MCAN1 clock divider */ +#define LPC54_SYSCON_SC0CLKDIV_OFFSET 0x0310 /* Smartcard0 clock divider */ +#define LPC54_SYSCON_SC1CLKDIV_OFFSET 0x0314 /* Smartcard1 clock divider */ +#define LPC54_SYSCON_AHBCLKDIV_OFFSET 0x0380 /* System clock divider */ +#define LPC54_SYSCON_CLKOUTDIV_OFFSET 0x0384 /* CLKOUT clock divider */ +#define LPC54_SYSCON_FROHFDIV_OFFSET 0x0388 /* FROHF clock divider */ +#define LPC54_SYSCON_SPIFICLKDIV_OFFSET 0x0390 /* SPIFI clock divider */ +#define LPC54_SYSCON_ADCCLKDIV_OFFSET 0x0394 /* ADC clock divider */ +#define LPC54_SYSCON_USB0CLKDIV_OFFSET 0x0398 /* USB0 clock divider */ +#define LPC54_SYSCON_USB1CLKDIV_OFFSET 0x039c /* USB1 clock divider */ +#define LPC54_SYSCON_FRGCTRL_OFFSET 0x03a0 /* Fractional rate divider */ +#define LPC54_SYSCON_DMICCLKDIV_OFFSET 0x03a8 /* DMIC clock divider */ +#define LPC54_SYSCON_MCLKDIV_OFFSET 0x03ac /* I2S MCLK clock divider */ +#define LPC54_SYSCON_LCDCLKDIV_OFFSET 0x03b0 /* LCD clock divider */ +#define LPC54_SYSCON_SCTCLKDIV_OFFSET 0x03b4 /* SCT/PWM clock divider */ +#define LPC54_SYSCON_EMCCLKDIV_OFFSET 0x03b8 /* EMC clock divider */ +#define LPC54_SYSCON_SDIOCLKDIV_OFFSET 0x03bc /* SDIO clock divider */ +#define LPC54_SYSCON_FLASHCFG_OFFSET 0x0400 /* Flash wait states configuration */ +#define LPC54_SYSCON_USB0CLKCTRL_OFFSET 0x040c /* USB0 clock control */ +#define LPC54_SYSCON_USB0CLKSTAT_OFFSET 0x0410 /* USB0 clock status */ +#define LPC54_SYSCON_FREQMECTRL_OFFSET 0x0418 /* Frequency measure register */ +#define LPC54_SYSCON_MCLKIO_OFFSET 0x0420 /* MCLK input/output control */ +#define LPC54_SYSCON_USB1CLKCTRL_OFFSET 0x0424 /* USB1 clock control */ +#define LPC54_SYSCON_USB1CLKSTAT_OFFSET 0x0428 /* USB1 clock status */ +#define LPC54_SYSCON_EMCSYSCTRL_OFFSET 0x0444 /* EMC system control */ +#define LPC54_SYSCON_EMCDLYCTRL_OFFSET 0x0448 /* EMC clock delay control */ +#define LPC54_SYSCON_EMCDLYCAL_OFFSET 0x044c /* EMC delay chain calibration control */ +#define LPC54_SYSCON_ETHPHYSEL_OFFSET 0x0450 /* Ethernet PHY selection */ +#define LPC54_SYSCON_ETHSBDCTRL_OFFSET 0x0454 /* Ethernet SBD flow control */ +#define LPC54_SYSCON_SDIOCLKCTRL_OFFSET 0x0460 /* SDIO CCLKIN phase and delay control */ +#define LPC54_SYSCON_FROCTRL_OFFSET 0x0500 /* FRO oscillator control */ +#define LPC54_SYSCON_SYSOSCCTRL_OFFSET 0x0504 /* System oscillator control */ +#define LPC54_SYSCON_WDTOSCCTRL_OFFSET 0x0508 /* Watchdog oscillator control */ +#define LPC54_SYSCON_RTCOSCCTRL_OFFSET 0x050c /* RTC oscillator 32 kHz output control */ +#define LPC54_SYSCON_USBPLLCTRL_OFFSET 0x051c /* USB PLL control */ +#define LPC54_SYSCON_USBPLLSTAT_OFFSET 0x0520 /* USB PLL status */ +#define LPC54_SYSCON_SYSPLLCTRL_OFFSET 0x0580 /* System PLL control */ +#define LPC54_SYSCON_SYSPLLSTAT_OFFSET 0x0584 /* PLL status */ +#define LPC54_SYSCON_SYSPLLNDEC_OFFSET 0x0588 /* PLL N divider */ +#define LPC54_SYSCON_SYSPLLPDEC_OFFSET 0x058c /* PLL P divider */ +#define LPC54_SYSCON_SYSPLLMDEC_OFFSET 0x0590 /* System PLL M divider */ +#define LPC54_SYSCON_AUDPLLCTRL_OFFSET 0x05a0 /* Audio PLL control */ +#define LPC54_SYSCON_AUDPLLSTAT_OFFSET 0x05a4 /* Audio PLL status */ +#define LPC54_SYSCON_AUDPLLNDEC_OFFSET 0x05a8 /* Audio PLL N divider */ +#define LPC54_SYSCON_AUDPLLPDEC_OFFSET 0x05ac /* Audio PLL P divider */ +#define LPC54_SYSCON_AUDPLLMDEC_OFFSET 0x05b0 /* Audio PLL M divider */ +#define LPC54_SYSCON_AUDPLLFRAC_OFFSET 0x05b4 /* Audio PLL fractional divider control */ +#define LPC54_SYSCON_PDSLEEPCFG0_OFFSET 0x0600 /* Sleep configuration register 0 */ +#define LPC54_SYSCON_PDSLEEPCFG1_OFFSET 0x0604 /* Sleep configuration register 1 */ +#define LPC54_SYSCON_PDRUNCFG0_OFFSET 0x0610 /* Power configuration register 0 */ +#define LPC54_SYSCON_PDRUNCFG1_OFFSET 0x0614 /* Power configuration register 1 */ +#define LPC54_SYSCON_PDRUNCFGSET0_OFFSET 0x0620 /* Set bits in PDRUNCFG0 */ +#define LPC54_SYSCON_PDRUNCFGSET1_OFFSET 0x0624 /* Set bits in PDRUNCFG1 */ +#define LPC54_SYSCON_PDRUNCFGCLR0_OFFSET 0x0630 /* Clear bits in PDRUNCFG0 */ +#define LPC54_SYSCON_PDRUNCFGCLR1_OFFSET 0x0634 /* Clear bits in PDRUNCFG1 */ +#define LPC54_SYSCON_STARTER0_OFFSET 0x0680 /* Start logic 0 wake-up enable register */ +#define LPC54_SYSCON_STARTER1_OFFSET 0x0684 /* Start logic 1 wake-up enable register */ +#define LPC54_SYSCON_STARTERSET0_OFFSET 0x06a0 /* Set bits in STARTER0 */ +#define LPC54_SYSCON_STARTERSET1_OFFSET 0x06a4 /* Set bits in STARTER1 */ +#define LPC54_SYSCON_STARTERCLR0_OFFSET 0x06c0 /* Clear bits in STARTER0 */ +#define LPC54_SYSCON_STARTERCLR1_OFFSET 0x06c4 /* Clear bits in STARTER1 */ +#define LPC54_SYSCON_HWWAKE_OFFSET 0x0780 /* Configures special cases of hardware wake-up */ +#define LPC54_SYSCON_AUTOCGOR_OFFSET 0x0e04 /* Auto clock-gate override */ +#define LPC54_SYSCON_JTAGIDCODE_OFFSET 0x0ff4 /* JTAG ID code */ +#define LPC54_SYSCON_DEVICE_ID0_OFFSET 0x0ff8 /* Part ID */ +#define LPC54_SYSCON_DEVICE_ID1_OFFSET 0x0ffc /* Boot ROM and die revision */ + +/* Asynchronous system configuration */ + +#define LPC54_SYSCON_ASYNCPRESETCTRL_OFFSET 0x0000 /* Async peripheral reset control */ +#define LPC54_SYSCON_ASYNCPRESETCTRLSET_OFFSET 0x0004 /* Set bits in ASYNCPRESETCTRL */ +#define LPC54_SYSCON_ASYNCPRESETCTRLCLR_OFFSET 0x0008 /* Clear bits in ASYNCPRESETCTRL */ +#define LPC54_SYSCON_ASYNCAPBCLKCTRL_OFFSET 0x0010 /* Async peripheral clock control */ +#define LPC54_SYSCON_ASYNCAPBCLKCTRLSET_OFFSET 0x0014 /* Set bits in ASYNCAPBCLKCTRL */ +#define LPC54_SYSCON_ASYNCAPBCLKCTRLCLR_OFFSET 0x0018 /* Clear bits in ASYNCAPBCLKCTRL */ +#define LPC54_SYSCON_ASYNCAPBCLKSELA_OFFSET 0x0020 /* Async APB clock source select A */ + +/* Other system configuration */ + +#define LPC54_SYSCON_BODCTRL_OFFSET 0x0044 /* Brown-Out Detect control */ + +/* Register addresses ***********************************************************************/ + +/* Main system configuration */ + +#define LPC54_SYSCON_AHBMATPRIO (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBMATPRIO_OFFSET) +#define LPC54_SYSCON_SYSTCKCAL (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSTCKCAL_OFFSET) +#define LPC54_SYSCON_NMISRC (LPC54_SYSCON_BASE + LPC54_SYSCON_NMISRC_OFFSET) +#define LPC54_SYSCON_ASYNCAPBCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_ASYNCAPBCTRL_OFFSET) +#define LPC54_SYSCON_PIOPORCAP0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PIOPORCAP0_OFFSET) +#define LPC54_SYSCON_PIOPORCAP1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PIOPORCAP1_OFFSET) +#define LPC54_SYSCON_PIORESCAP0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PIORESCAP0_OFFSET) +#define LPC54_SYSCON_PIORESCAP1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PIORESCAP1_OFFSET) +#define LPC54_SYSCON_PRESETCTRL0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRL0_OFFSET) +#define LPC54_SYSCON_PRESETCTRL1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRL1_OFFSET) +#define LPC54_SYSCON_PRESETCTRL2 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRL2_OFFSET) +#define LPC54_SYSCON_PRESETCTRLSET0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRLSET0_OFFSET) +#define LPC54_SYSCON_PRESETCTRLSET1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRLSET1_OFFSET) +#define LPC54_SYSCON_PRESETCTRLSET2 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRLSET2_OFFSET) +#define LPC54_SYSCON_PRESETCTRLCLR0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRLCLR0_OFFSET) +#define LPC54_SYSCON_PRESETCTRLCLR1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRLCLR1_OFFSET) +#define LPC54_SYSCON_PRESETCTRLCLR2 (LPC54_SYSCON_BASE + LPC54_SYSCON_PRESETCTRLCLR2_OFFSET) +#define LPC54_SYSCON_SYSRSTSTAT (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSRSTSTAT_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRL0 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRL0_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRL1 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRL1_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRL2 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRL2_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRLSET0 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRLSET0_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRLSET1 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRLSET1_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRLSET2 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRLSET2_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRLCLR0 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRLCLR0_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRLCLR1 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRLCLR1_OFFSET) +#define LPC54_SYSCON_AHBCLKCTRLCLR2 (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKCTRLCLR2_OFFSET) +#define LPC54_SYSCON_MAINCLKSELA (LPC54_SYSCON_BASE + LPC54_SYSCON_MAINCLKSELA_OFFSET) +#define LPC54_SYSCON_MAINCLKSELB (LPC54_SYSCON_BASE + LPC54_SYSCON_MAINCLKSELB_OFFSET) +#define LPC54_SYSCON_CLKOUTSELA (LPC54_SYSCON_BASE + LPC54_SYSCON_CLKOUTSELA_OFFSET) +#define LPC54_SYSCON_SYSPLLCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSPLLCLKSEL_OFFSET) +#define LPC54_SYSCON_AUDPLLCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_AUDPLLCLKSEL_OFFSET) +#define LPC54_SYSCON_SPIFICLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_SPIFICLKSEL_OFFSET) +#define LPC54_SYSCON_ADCCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_ADCCLKSEL_OFFSET) +#define LPC54_SYSCON_USB0CLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_USB0CLKSEL_OFFSET) +#define LPC54_SYSCON_USB1CLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_USB1CLKSEL_OFFSET) +#define LPC54_SYSCON_FCLKSEL0 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL0_OFFSET) +#define LPC54_SYSCON_FCLKSEL1 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL1_OFFSET) +#define LPC54_SYSCON_FCLKSEL2 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL2_OFFSET) +#define LPC54_SYSCON_FCLKSEL3 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL3_OFFSET) +#define LPC54_SYSCON_FCLKSEL4 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL4_OFFSET) +#define LPC54_SYSCON_FCLKSEL5 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL5_OFFSET) +#define LPC54_SYSCON_FCLKSEL6 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL6_OFFSET) +#define LPC54_SYSCON_FCLKSEL7 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL7_OFFSET) +#define LPC54_SYSCON_FCLKSEL8 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL8_OFFSET) +#define LPC54_SYSCON_FCLKSEL9 (LPC54_SYSCON_BASE + LPC54_SYSCON_FCLKSEL9_OFFSET) +#define LPC54_SYSCON_MCLKCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_MCLKCLKSEL_OFFSET) +#define LPC54_SYSCON_FRGCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_FRGCLKSEL_OFFSET) +#define LPC54_SYSCON_DMICCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_DMICCLKSEL_OFFSET) +#define LPC54_SYSCON_SCTCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_SCTCLKSEL_OFFSET) +#define LPC54_SYSCON_LCDCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_LCDCLKSEL_OFFSET) +#define LPC54_SYSCON_SDIOCLKSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_SDIOCLKSEL_OFFSET) +#define LPC54_SYSCON_SYSTICKCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSTICKCLKDIV_OFFSET) +#define LPC54_SYSCON_ARMTRCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_ARMTRCLKDIV_OFFSET) +#define LPC54_SYSCON_CAN0CLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_CAN0CLKDIV_OFFSET) +#define LPC54_SYSCON_CAN1CLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_CAN1CLKDIV_OFFSET) +#define LPC54_SYSCON_SC0CLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_SC0CLKDIV_OFFSET) +#define LPC54_SYSCON_SC1CLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_SC1CLKDIV_OFFSET) +#define LPC54_SYSCON_AHBCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_AHBCLKDIV_OFFSET) +#define LPC54_SYSCON_CLKOUTDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_CLKOUTDIV_OFFSET) +#define LPC54_SYSCON_FROHFDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_FROHFDIV_OFFSET) +#define LPC54_SYSCON_SPIFICLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_SPIFICLKDIV_OFFSET) +#define LPC54_SYSCON_ADCCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_ADCCLKDIV_OFFSET) +#define LPC54_SYSCON_USB0CLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_USB0CLKDIV_OFFSET) +#define LPC54_SYSCON_USB1CLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_USB1CLKDIV_OFFSET) +#define LPC54_SYSCON_FRGCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_FRGCTRL_OFFSET) +#define LPC54_SYSCON_DMICCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_DMICCLKDIV_OFFSET) +#define LPC54_SYSCON_MCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_MCLKDIV_OFFSET) +#define LPC54_SYSCON_LCDCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_LCDCLKDIV_OFFSET) +#define LPC54_SYSCON_SCTCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_SCTCLKDIV_OFFSET) +#define LPC54_SYSCON_EMCCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_EMCCLKDIV_OFFSET) +#define LPC54_SYSCON_SDIOCLKDIV (LPC54_SYSCON_BASE + LPC54_SYSCON_SDIOCLKDIV_OFFSET) +#define LPC54_SYSCON_FLASHCFG (LPC54_SYSCON_BASE + LPC54_SYSCON_FLASHCFG_OFFSET) +#define LPC54_SYSCON_USB0CLKCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_USB0CLKCTRL_OFFSET) +#define LPC54_SYSCON_USB0CLKSTAT (LPC54_SYSCON_BASE + LPC54_SYSCON_USB0CLKSTAT_OFFSET) +#define LPC54_SYSCON_FREQMECTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_FREQMECTRL_OFFSET) +#define LPC54_SYSCON_MCLKIO (LPC54_SYSCON_BASE + LPC54_SYSCON_MCLKIO_OFFSET) +#define LPC54_SYSCON_USB1CLKCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_USB1CLKCTRL_OFFSET) +#define LPC54_SYSCON_USB1CLKSTAT (LPC54_SYSCON_BASE + LPC54_SYSCON_USB1CLKSTAT_OFFSET) +#define LPC54_SYSCON_EMCSYSCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_EMCSYSCTRL_OFFSET) +#define LPC54_SYSCON_EMCDLYCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_EMCDLYCTRL_OFFSET) +#define LPC54_SYSCON_EMCDLYCAL (LPC54_SYSCON_BASE + LPC54_SYSCON_EMCDLYCAL_OFFSET) +#define LPC54_SYSCON_ETHPHYSEL (LPC54_SYSCON_BASE + LPC54_SYSCON_ETHPHYSEL_OFFSET) +#define LPC54_SYSCON_ETHSBDCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_ETHSBDCTRL_OFFSET) +#define LPC54_SYSCON_SDIOCLKCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_SDIOCLKCTRL_OFFSET) +#define LPC54_SYSCON_FROCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_FROCTRL_OFFSET) +#define LPC54_SYSCON_SYSOSCCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSOSCCTRL_OFFSET) +#define LPC54_SYSCON_WDTOSCCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_WDTOSCCTRL_OFFSET) +#define LPC54_SYSCON_RTCOSCCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_RTCOSCCTRL_OFFSET) +#define LPC54_SYSCON_USBPLLCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_USBPLLCTRL_OFFSET) +#define LPC54_SYSCON_USBPLLSTAT (LPC54_SYSCON_BASE + LPC54_SYSCON_USBPLLSTAT_OFFSET) +#define LPC54_SYSCON_SYSPLLCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSPLLCTRL_OFFSET) +#define LPC54_SYSCON_SYSPLLSTAT (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSPLLSTAT_OFFSET) +#define LPC54_SYSCON_SYSPLLNDEC (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSPLLNDEC_OFFSET) +#define LPC54_SYSCON_SYSPLLPDEC (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSPLLPDEC_OFFSET) +#define LPC54_SYSCON_SYSPLLMDEC (LPC54_SYSCON_BASE + LPC54_SYSCON_SYSPLLMDEC_OFFSET) +#define LPC54_SYSCON_AUDPLLCTRL (LPC54_SYSCON_BASE + LPC54_SYSCON_AUDPLLCTRL_OFFSET) +#define LPC54_SYSCON_AUDPLLSTAT (LPC54_SYSCON_BASE + LPC54_SYSCON_AUDPLLSTAT_OFFSET) +#define LPC54_SYSCON_AUDPLLNDEC (LPC54_SYSCON_BASE + LPC54_SYSCON_AUDPLLNDEC_OFFSET) +#define LPC54_SYSCON_AUDPLLPDEC (LPC54_SYSCON_BASE + LPC54_SYSCON_AUDPLLPDEC_OFFSET) +#define LPC54_SYSCON_AUDPLLMDEC (LPC54_SYSCON_BASE + LPC54_SYSCON_AUDPLLMDEC_OFFSET) +#define LPC54_SYSCON_AUDPLLFRAC (LPC54_SYSCON_BASE + LPC54_SYSCON_AUDPLLFRAC_OFFSET) +#define LPC54_SYSCON_PDSLEEPCFG0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PDSLEEPCFG0_OFFSET) +#define LPC54_SYSCON_PDSLEEPCFG1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PDSLEEPCFG1_OFFSET) +#define LPC54_SYSCON_PDRUNCFG0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PDRUNCFG0_OFFSET) +#define LPC54_SYSCON_PDRUNCFG1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PDRUNCFG1_OFFSET) +#define LPC54_SYSCON_PDRUNCFGSET0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PDRUNCFGSET0_OFFSET) +#define LPC54_SYSCON_PDRUNCFGSET1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PDRUNCFGSET1_OFFSET) +#define LPC54_SYSCON_PDRUNCFGCLR0 (LPC54_SYSCON_BASE + LPC54_SYSCON_PDRUNCFGCLR0_OFFSET) +#define LPC54_SYSCON_PDRUNCFGCLR1 (LPC54_SYSCON_BASE + LPC54_SYSCON_PDRUNCFGCLR1_OFFSET) +#define LPC54_SYSCON_STARTER0 (LPC54_SYSCON_BASE + LPC54_SYSCON_STARTER0_OFFSET) +#define LPC54_SYSCON_STARTER1 (LPC54_SYSCON_BASE + LPC54_SYSCON_STARTER1_OFFSET) +#define LPC54_SYSCON_STARTERSET0 (LPC54_SYSCON_BASE + LPC54_SYSCON_STARTERSET0_OFFSET) +#define LPC54_SYSCON_STARTERSET1 (LPC54_SYSCON_BASE + LPC54_SYSCON_STARTERSET1_OFFSET) +#define LPC54_SYSCON_STARTERCLR0 (LPC54_SYSCON_BASE + LPC54_SYSCON_STARTERCLR0_OFFSET) +#define LPC54_SYSCON_STARTERCLR1 (LPC54_SYSCON_BASE + LPC54_SYSCON_STARTERCLR1_OFFSET) +#define LPC54_SYSCON_HWWAKE (LPC54_SYSCON_BASE + LPC54_SYSCON_HWWAKE_OFFSET) +#define LPC54_SYSCON_AUTOCGOR (LPC54_SYSCON_BASE + LPC54_SYSCON_AUTOCGOR_OFFSET) +#define LPC54_SYSCON_JTAGIDCODE (LPC54_SYSCON_BASE + LPC54_SYSCON_JTAGIDCODE_OFFSET) +#define LPC54_SYSCON_DEVICE_ID0 (LPC54_SYSCON_BASE + LPC54_SYSCON_DEVICE_ID0_OFFSET) +#define LPC54_SYSCON_DEVICE_ID1 (LPC54_SYSCON_BASE + LPC54_SYSCON_DEVICE_ID1_OFFSET) + +/* Asynchronous system configuration */ + +#define LPC54_SYSCON_ASYNCPRESETCTRL (LPC54_ASYSCON_BASE + LPC54_SYSCON_ASYNCPRESETCTRL_OFFSET) +#define LPC54_SYSCON_ASYNCPRESETCTRLSET (LPC54_ASYSCON_BASE + LPC54_SYSCON_ASYNCPRESETCTRLSET_OFFSET) +#define LPC54_SYSCON_ASYNCPRESETCTRLCLR (LPC54_ASYSCON_BASE + LPC54_SYSCON_ASYNCPRESETCTRLCLR_OFFSET) +#define LPC54_SYSCON_ASYNCAPBCLKCTRL (LPC54_ASYSCON_BASE + LPC54_SYSCON_ASYNCAPBCLKCTRL_OFFSET) +#define LPC54_SYSCON_ASYNCAPBCLKCTRLSET (LPC54_ASYSCON_BASE + LPC54_SYSCON_ASYNCAPBCLKCTRLSET_OFFSET) +#define LPC54_SYSCON_ASYNCAPBCLKCTRLCLR (LPC54_ASYSCON_BASE + LPC54_SYSCON_ASYNCAPBCLKCTRLCLR_OFFSET) +#define LPC54_SYSCON_ASYNCAPBCLKSELA (LPC54_ASYSCON_BASE + LPC54_SYSCON_ASYNCAPBCLKSELA_OFFSET) + +/* Other system configuration */ + +#define LPC54_SYSCON_BODCTRL (LPC54_OSYSCON_BASE + LPC54_SYSCON_BODCTRL_OFFSET) + +/* Register bit definitions *****************************************************************/ + +/* Main system configuration */ + +/* AHB multilayer matrix priority control */ +#define SYSCON_AHBMATPRIO_ +/* System tick counter calibration */ +#define SYSCON_SYSTCKCAL_ +/* NMI source select */ +#define SYSCON_NMISRC_ +/* Asynchronous APB control */ +#define SYSCON_ASYNCAPBCTRL_ +/* POR captured value of port 0 */ +#define SYSCON_PIOPORCAP0_ +/* POR captured value of port 1 */ +#define SYSCON_PIOPORCAP1_ +/* Reset captured value of port 0 */ +#define SYSCON_PIORESCAP0_ +/* Reset captured value of port 1 */ +#define SYSCON_PIORESCAP1_ + +/* Peripheral reset control 0: PRESETCTRL0, PRESETCTRLSET0, and PRESETCTRLCLR0 */ + +#define SYSCON_PRESETCTRL0_FLASH (1 << 7) /* Bit 7: Reset the flash controller */ +#define SYSCON_PRESETCTRL0_FMC (1 << 8) /* Bit 8: Reset the Flash accelerator */ +#define SYSCON_PRESETCTRL0_EEPROM (1 << 9) /* Bit 9: Reset EEPROM */ +#define SYSCON_PRESETCTRL0_SPIFI (1 << 10) /* Bit 10: Reset the SPIFI */ +#define SYSCON_PRESETCTRL0_INPUTMUX (1 << 11) /* Bit 11: Reset the input muxes */ +#define SYSCON_PRESETCTRL0_IOCON (1 << 13) /* Bit 13: Reset the IOCON block */ +#define SYSCON_PRESETCTRL0_GPIO0 (1 << 14) /* Bit 14: Reset the GPIO0 port registers */ +#define SYSCON_PRESETCTRL0_GPIO1 (1 << 15) /* Bit 15: Reset the GPIO1 port registers */ +#define SYSCON_PRESETCTRL0_GPIO2 (1 << 16) /* Bit 16: Reset the GPIO2 port registers */ +#define SYSCON_PRESETCTRL0_GPIO3 (1 << 17) /* Bit 17: Reset the GPIO3 port registers */ +#define SYSCON_PRESETCTRL0_PINT (1 << 18) /* Bit 18: Reset the pin interrupt block */ +#define SYSCON_PRESETCTRL0_GINT (1 << 19) /* Bit 19: Reset the grouped pin interrupt block */ +#define SYSCON_PRESETCTRL0_DMA (1 << 20) /* Bit 20: Reset the DMA controller */ +#define SYSCON_PRESETCTRL0_CRC (1 << 21) /* Bit 21: Reset the CRC engine */ +#define SYSCON_PRESETCTRL0_WWDT (1 << 22) /* Bit 22: Reset the Watchdog Timer */ +#define SYSCON_PRESETCTRL0_RTC (1 << 23) /* Bit 23: Enables the bus clock for the RTC */ +#define SYSCON_PRESETCTRL0_ADC0 (1 << 27) /* Bit 27: Reset the ADC0 register interface */ + +/* Peripheral reset control 2: PRESETCTRL1, PRESETCTRLSET1, and PRESETCTRLCLR1 */ + +#define SYSCON_PRESETCTRL1_MRT (1 << 0) /* Bit 0: Reset the Multi-Rate Timer */ +#define SYSCON_PRESETCTRL1_SCT0 (1 << 2) /* Bit 2: Reset SCT0 */ +#define SYSCON_PRESETCTRL1_MCAN0 (1 << 7) /* Bit 7: Reset MCAN0 */ +#define SYSCON_PRESETCTRL1_MCAN1 (1 << 8) /* Bit 8: Reset MCAN1 */ +#define SYSCON_PRESETCTRL1_UTICK (1 << 10) /* Bit 10: Reset the Micro-tick Timer */ +#define SYSCON_PRESETCTRL1_FLEXCOMM0 (1 << 11) /* Bit 11: Reset Flexcomm Interface 0 */ +#define SYSCON_PRESETCTRL1_FLEXCOMM1 (1 << 12) /* Bit 12: Reset Flexcomm Interface 1 */ +#define SYSCON_PRESETCTRL1_FLEXCOMM2 (1 << 13) /* Bit 13: Reset Flexcomm Interface 2 */ +#define SYSCON_PRESETCTRL1_FLEXCOMM3 (1 << 14) /* Bit 14: Reset Flexcomm Interface 3 */ +#define SYSCON_PRESETCTRL1_FLEXCOMM4 (1 << 15) /* Bit 15: Reset Flexcomm Interface 4 */ +#define SYSCON_PRESETCTRL1_FLEXCOMM5 (1 << 16) /* Bit 16: Reset Flexcomm Interface 5 */ +#define SYSCON_PRESETCTRL1_FLEXCOMM6 (1 << 17) /* Bit 17: Reset Flexcomm Interface 6 */ +#define SYSCON_PRESETCTRL1_FLEXCOMM7 (1 << 18) /* Bit 18: Reset Flexcomm Interface 7 */ +#define SYSCON_PRESETCTRL1_DMIC (1 << 19) /* Bit 19: Reset the digital microphone interface */ +#define SYSCON_PRESETCTRL1_CTIMER2 (1 << 22) /* Bit 22: Reset CTIMER 2 */ +#define SYSCON_PRESETCTRL1_USB0D (1 << 25) /* Bit 25: Reset the USB0 device interface */ +#define SYSCON_PRESETCTRL1_CTIMER0 (1 << 26) /* Bit 26: Reset timer CTIMER0 */ +#define SYSCON_PRESETCTRL1_CTIMER1 (1 << 27) /* Bit 27: Reset timer CTIMER1 */ + +/* Peripheral reset control 2: PRESETCTRL2, PRESETCTRL2, and PRESETCTRLCLR2 */ + +#define SYSCON_PRESETCTRL2_LCD (1 << 2) /* Bit 2: Reset the LCD interface */ +#define SYSCON_PRESETCTRL2_SDIO (1 << 3) /* Bit 3: Reset the SDIO interface */ +#define SYSCON_PRESETCTRL2_USB1H (1 << 4) /* Bit 4: Reset the USB1 host interface */ +#define SYSCON_PRESETCTRL2_USB1D (1 << 5) /* Bit 5: Reset the USB1 device interface */ +#define SYSCON_PRESETCTRL2_USB1RAM (1 << 6) /* Bit 6: Reset the USB1 RAM interface */ +#define SYSCON_PRESETCTRL2_EMC (1 << 7) /* Bit 7: Reset the EMC interface */ +#define SYSCON_PRESETCTRL2_ETH (1 << 8) /* Bit 8: Reset the ethernet interface */ +#define SYSCON_PRESETCTRL2_GPIO4 (1 << 9) /* Bit 9: Reset the GPIO4 interface */ +#define SYSCON_PRESETCTRL2_GPIO5 (1 << 10) /* Bit 10: Reset the GPIO5 interface */ +#define SYSCON_PRESETCTRL2_OTP (1 << 12) /* Bit 12: Reset the OTP interface */ +#define SYSCON_PRESETCTRL2_RNG (1 << 13) /* Bit 13: Reset the RNG interface */ +#define SYSCON_PRESETCTRL2_FLEXCOMM8 (1 << 14) /* Bit 14: Reset the Flexcomm Interface 8 */ +#define SYSCON_PRESETCTRL2_FLEXCOMM9 (1 << 15) /* Bit 15: Reset the Flexcomm Interface 9 */ +#define SYSCON_PRESETCTRL2_USB0HMR (1 << 16) /* Bit 16: Reset the USB host master interface */ +#define SYSCON_PRESETCTRL2_USB0HSL (1 << 17) /* Bit 17: Reset the USB host slave interface */ +#define SYSCON_PRESETCTRL2_SHA (1 << 18) /* Bit 18: Reset the SHA interface */ +#define SYSCON_PRESETCTRL2_SC0 (1 << 19) /* Bit 19: Reset the Smart card0 interface */ +#define SYSCON_PRESETCTRL2_SC1 (1 << 20) /* Bit 20: Reset the Smart card1 interface */ + +/* System reset status register */ +#define SYSCON_SYSRSTSTAT_ + +/* AHB Clock control 0: AHBCLKCTRL0, AHBCLKCTRLCLR0, and AHBCLKCTRLSET0 */ + +#define SYSCON_AHBCLKCTRL0_ROM (1 << 1) /* Bit 1: Enables the clock for the Boot ROM */ +#define SYSCON_AHBCLKCTRL0_SRAM1 (1 << 3) /* Bit 3: Enables the clock for SRAM1 */ +#define SYSCON_AHBCLKCTRL0_SRAM2 (1 << 4) /* Bit 4: Enables the clock for SRAM2 */ +#define SYSCON_AHBCLKCTRL0_SRAM3 (1 << 5) /* Bit 5: Enables the clock for SRAM3 */ +#define SYSCON_AHBCLKCTRL0_FLASH (1 << 7) /* Bit 7: Enables the clock for the flash controller */ +#define SYSCON_AHBCLKCTRL0_FMC (1 << 8) /* Bit 8: Enables the clock for the Flash accelerator */ +#define SYSCON_AHBCLKCTRL0_EEPROM (1 << 9) /* Bit 9: Enables the clock for EEPROM */ +#define SYSCON_AHBCLKCTRL0_SPIFI (1 << 10) /* Bit 10: Enables the clock for the SPIFI */ +#define SYSCON_AHBCLKCTRL0_INPUTMUX (1 << 11) /* Bit 11: Enables the clock for the input muxes */ +#define SYSCON_AHBCLKCTRL0_IOCON (1 << 13) /* Bit 13: Enables the clock for the IOCON block */ +#define SYSCON_AHBCLKCTRL0_GPIO0 (1 << 14) /* Bit 14: Enables the clock for the GPIO0 port registers */ +#define SYSCON_AHBCLKCTRL0_GPIO1 (1 << 15) /* Bit 15: Enables the clock for the GPIO1 port registers */ +#define SYSCON_AHBCLKCTRL0_GPIO2 (1 << 16) /* Bit 16: Enables the clock for the GPIO2 port registers */ +#define SYSCON_AHBCLKCTRL0_GPIO3 (1 << 17) /* Bit 17: Enables the clock for the GPIO3 port registers */ +#define SYSCON_AHBCLKCTRL0_PINT (1 << 18) /* Bit 18: Enables the clock for the pin interrupt block */ +#define SYSCON_AHBCLKCTRL0_GINT (1 << 19) /* Bit 19: Enables the clock for the grouped pin interrupt block */ +#define SYSCON_AHBCLKCTRL0_DMA (1 << 20) /* Bit 20: Enables the clock for the DMA controller */ +#define SYSCON_AHBCLKCTRL0_CRC (1 << 21) /* Bit 21: Enables the clock for the CRC engine */ +#define SYSCON_AHBCLKCTRL0_WWDT (1 << 22) /* Bit 22: Enables the clock for the Watchdog Timer */ +#define SYSCON_AHBCLKCTRL0_RTC (1 << 23) /* Bit 23: Enables the bus clock for the RTC */ +#define SYSCON_AHBCLKCTRL0_ADC0 (1 << 27) /* Bit 27: Enables the clock for the ADC0 register interface */ + +/* AHB Clock control 1: AHBCLKCTRL1, AHBCLKCTRLCLR1, and AHBCLKCTRLSET1 */ + +#define SYSCON_AHBCLKCTRL1_MRT (1 << 0) /* Bit 0: Enables the clock for the Multi-Rate Timer */ +#define SYSCON_AHBCLKCTRL1_RIT (1 << 1) /* Bit 1: Enables the clock for the Repetitive Interrupt Timer */ +#define SYSCON_AHBCLKCTRL1_SCT0 (1 << 2) /* Bit 2: Enables the clock for SCT0 */ +#define SYSCON_AHBCLKCTRL1_MCAN0 (1 << 7) /* Bit 7: Enables the clock for MCAN0 */ +#define SYSCON_AHBCLKCTRL1_MCAN1 (1 << 8) /* Bit 8: Enables the clock for MCAN1 */ +#define SYSCON_AHBCLKCTRL1_UTICK (1 << 10) /* Bit 10: Enables the clock for the Micro-tick Timer */ +#define SYSCON_AHBCLKCTRL1_FLEXCOMM0 (1 << 11) /* Bit 11: Enables the clock for Flexcomm Interface 0 */ +#define SYSCON_AHBCLKCTRL1_FLEXCOMM1 (1 << 12) /* Bit 12: Enables the clock for Flexcomm Interface 1 */ +#define SYSCON_AHBCLKCTRL1_FLEXCOMM2 (1 << 13) /* Bit 13: Enables the clock for Flexcomm Interface 2 */ +#define SYSCON_AHBCLKCTRL1_FLEXCOMM3 (1 << 14) /* Bit 14: Enables the clock for Flexcomm Interface 3 */ +#define SYSCON_AHBCLKCTRL1_FLEXCOMM4 (1 << 15) /* Bit 15: Enables the clock for Flexcomm Interface 4 */ +#define SYSCON_AHBCLKCTRL1_FLEXCOMM5 (1 << 16) /* Bit 16: Enables the clock for Flexcomm Interface 5 */ +#define SYSCON_AHBCLKCTRL1_FLEXCOMM6 (1 << 17) /* Bit 17: Enables the clock for Flexcomm Interface 6 */ +#define SYSCON_AHBCLKCTRL1_FLEXCOMM7 (1 << 18) /* Bit 18: Enables the clock for Flexcomm Interface 7 */ +#define SYSCON_AHBCLKCTRL1_DMIC (1 << 19) /* Bit 19: Enables the clock for the digital microphone interface */ +#define SYSCON_AHBCLKCTRL1_CTIMER2 (1 << 22) /* Bit 22: Enables the clock for CTIMER 2 */ +#define SYSCON_AHBCLKCTRL1_USB0D (1 << 25) /* Bit 25: Enables the clock for the USB0 device interface */ +#define SYSCON_AHBCLKCTRL1_CTIMER0 (1 << 26) /* Bit 26: Enables the clock for timer CTIMER0 */ +#define SYSCON_AHBCLKCTRL1_CTIMER1 (1 << 27) /* Bit 27: Enables the clock for timer CTIMER1 */ + +/* AHB Clock control 2: AHBCLKCTRL2, AHBCLKCTRLCLR2, and AHBCLKCTRLSET2 */ + +#define SYSCON_AHBCLKCTRL2_LCD (1 << 2) /* Bit 2: Enables the clock for the LCD interface */ +#define SYSCON_AHBCLKCTRL2_SDIO (1 << 3) /* Bit 3: Enables the clock for the SDIO interface */ +#define SYSCON_AHBCLKCTRL2_USB1H (1 << 4) /* Bit 4: Enables the clock for the USB1 host interface */ +#define SYSCON_AHBCLKCTRL2_USB1D (1 << 5) /* Bit 5: Enables the clock for the USB1 device interface */ +#define SYSCON_AHBCLKCTRL2_USB1RAM (1 << 6) /* Bit 6: Enables the clock for the USB1 RAM interface */ +#define SYSCON_AHBCLKCTRL2_EMC (1 << 7) /* Bit 7: Enables the clock for the EMC interface */ +#define SYSCON_AHBCLKCTRL2_ETH (1 << 8) /* Bit 8: Enables the clock for the ethernet interface */ +#define SYSCON_AHBCLKCTRL2_GPIO4 (1 << 9) /* Bit 9: Enables the clock for the GPIO4 interface */ +#define SYSCON_AHBCLKCTRL2_GPIO5 (1 << 10) /* Bit 10: Enables the clock for the GPIO5 interface */ +#define SYSCON_AHBCLKCTRL2_OTP (1 << 12) /* Bit 12: Enables the clock for the OTP interface */ +#define SYSCON_AHBCLKCTRL2_RNG (1 << 13) /* Bit 13: Enables the clock for the RNG interface */ +#define SYSCON_AHBCLKCTRL2_FLEXCOMM8 (1 << 14) /* Bit 14: Enables the clock for the Flexcomm Interface 8 */ +#define SYSCON_AHBCLKCTRL2_FLEXCOMM9 (1 << 15) /* Bit 15: Enables the clock for the Flexcomm Interface 9 */ +#define SYSCON_AHBCLKCTRL2_USB0HMR (1 << 16) /* Bit 16: Enables the clock for the USB host master interface */ +#define SYSCON_AHBCLKCTRL2_USB0HSL (1 << 17) /* Bit 17: Enables the clock for the USB host slave interface */ +#define SYSCON_AHBCLKCTRL2_SHA (1 << 18) /* Bit 18: Enables the clock for the SHA interface */ +#define SYSCON_AHBCLKCTRL2_SC0 (1 << 19) /* Bit 19: Enables the clock for the Smart card0 interface */ +#define SYSCON_AHBCLKCTRL2_SC1 (1 << 20) /* Bit 20: Enables the clock for the Smart card1 interface */ + +/* Main clock source select A */ + +#define SYSCON_MAINCLKSELA_SHIFT (0) /* Bits 0-1: Clock source for main clock */ +#define SYSCON_MAINCLKSELA_MASK (3 << SYSCON_MAINCLKSELA_SHIFT) +# define SYSCON_MAINCLKSELA_FRO12 (0 << SYSCON_MAINCLKSELA_SHIFT) /* FRO 12 MHz (fro_12m) */ +# define SYSCON_MAINCLKSELA_CLKIN (1 << SYSCON_MAINCLKSELA_SHIFT) /* CLKIN (clk_in) */ +# define SYSCON_MAINCLKSELA_WDTCLK (2 << SYSCON_MAINCLKSELA_SHIFT) /* Watchdog oscillator (wdt_clk) */ +# define SYSCON_MAINCLKSELA_FROHF (3 << SYSCON_MAINCLKSELA_SHIFT) /* FRO 96 or 48 MHz (fro_hf) */ + +/* Main clock source select B */ + +#define SYSCON_MAINCLKSELB_SHIFT (0) /* Bits 0-1: Clock source for main clock */ +#define SYSCON_MAINCLKSELB_MASK (3 << SYSCON_MAINCLKSELB_SHIFT) +# define SYSCON_MAINCLKSELB_MAINCLKSELA (0 << SYSCON_MAINCLKSELB_SHIFT) /* Use MAINCLKSELA selection */ +# define SYSCON_MAINCLKSELB_PLLCLK (2 << SYSCON_MAINCLKSELB_SHIFT) /* System PLL output (pll_clk) */ +# define SYSCON_MAINCLKSELB_32KCLK (3 << SYSCON_MAINCLKSELB_SHIFT) /* RTC oscillator 32 kHz output (32k_clk) */ + +/* CLKOUT clock source select */ +#define SYSCON_CLKOUTSELA_ + +/* PLL clock source select */ + +#define SYSCON_SYSPLLCLKSEL_SHIFT (0) /* Bits 0-2: System PLL clock source selection */ +#define SYSCON_SYSPLLCLKSEL_MASK (7 << SYSCON_SYSPLLCLKSEL_SHIFT) +# define SYSCON_SYSPLLCLKSEL_FFRO (0 << SYSCON_SYSPLLCLKSEL_SHIFT) /* FRO 12 MHz (fro_12m) */ +# define SYSCON_SYSPLLCLKSEL_CLKIN (1 << SYSCON_SYSPLLCLKSEL_SHIFT) /* CLKIN (clk_in) */ +# define SYSCON_SYSPLLCLKSEL_RTC (3 << SYSCON_SYSPLLCLKSEL_SHIFT) /* RTC oscillator 32 KHz ouput */ +# define SYSCON_SYSPLLCLKSEL_NONE (7 << SYSCON_SYSPLLCLKSEL_SHIFT) /* None */ + +/* Audio PLL clock source select */ +#define SYSCON_AUDPLLCLKSEL_ +/* SPIFI clock source select */ +#define SYSCON_SPIFICLKSEL_ +/* ADC clock source select */ +#define SYSCON_ADCCLKSEL_ +/* USB0 clock source select */ +#define SYSCON_USB0CLKSEL_ +/* USB1 clock source select */ +#define SYSCON_USB1CLKSEL_ + +/* Flexcomm Interface 0..9 clock source select */ + +#define SYSCON_FCLKSEL_SHIFT (0) /* Bits 0-2: Flexcomm Interface clock source selection */ +#define SYSCON_FCLKSEL_MASK (7 << SYSCON_FCLKSEL_SHIFT) +# define SYSCON_FCLKSEL_FRO12M (0 << SYSCON_FCLKSEL_SHIFT) /* FRO 12 MHz (fro_12m) */ +# define SYSCON_FCLKSEL_FROHFDIV (1 << SYSCON_FCLKSEL_SHIFT) /* FRO 96 or 48 MHz divided (fro_hf_div) */ +# define SYSCON_FCLKSEL_AUDPLLCLK (2 << SYSCON_FCLKSEL_SHIFT) /* Audio PLL clock (audio_pll_clk) */ +# define SYSCON_FCLKSEL_MCLK (3 << SYSCON_FCLKSEL_SHIFT) /* MCK */ +# define SYSCON_FCLKSEL_FRG (4 << SYSCON_FCLKSEL_SHIFT) /* FRG clock */ +# define SYSCON_FCLKSEL_NONE (7 << SYSCON_FCLKSEL_SHIFT) /* None */ + +/* MCLK clock source select */ + +#define SYSCON_MCLKCLKSEL_SHIFT (0) /* Bits 0-2: MCLK source select */ +#define SYSCON_MCLKCLKSEL_MASK (7 << SYSCON_MCLKCLKSEL_SHIFT) +# define SYSCON_MCLKCLKSEL_FROHFDIV (0 << SYSCON_MCLKCLKSEL_SHIFT) /* FRO 96 or 48 MHz divided (fro_hf_div) */ +# define SYSCON_MCLKCLKSEL_AUDPLLCLK (1 << SYSCON_MCLKCLKSEL_SHIFT) /* Audio PLL clock (audio_pll_clk) */ +# define SYSCON_MCLKCLKSEL_NONE (7 << SYSCON_MCLKCLKSEL_SHIFT) /* None */ + +/* Fractional Rate Generator clock source select */ + +#define SYSCON_FRGCLKSEL_SHIFT (0) /* Bits 0-2: Fractional Rate Generator clock source */ +#define SYSCON_FRGCLKSEL_MASK (7 << SYSCON_FRGCLKSEL_SHIFT) +# define SYSCON_FRGCLKSEL_MAINCLK (0 << SYSCON_FRGCLKSEL_SHIFT) /* Main clock (main_clk) */ +# define SYSCON_FRGCLKSEL_PLLCLK (1 << SYSCON_FRGCLKSEL_SHIFT) /* System PLL output (pll_clk) */ +# define SYSCON_FRGCLKSEL_FRO12M (2 << SYSCON_FRGCLKSEL_SHIFT) /* FRO 12 MHz (fro_12m) */ +# define SYSCON_FRGCLKSEL_FROHF (3 << SYSCON_FRGCLKSEL_SHIFT) /* FRO 96 or 48 MHz (fro_hf) */ +# define SYSCON_FRGCLKSEL_NONE (7 << SYSCON_FRGCLKSEL_SHIFT) /* None */ + +/* Digital microphone (DMIC) subsystem clock select */ +#define SYSCON_DMICCLKSEL_ +/* SCTimer/PWM clock source select */ +#define SYSCON_SCTCLKSEL_ + +/* LCD clock source select */ + +#define SYSCON_LCDCLKSEL_SHIFT (0) /* Bits 0-1: LCD clock source select */ +#define SYSCON_LCDCLKSEL_MASK (3 << SYSCON_LCDCLKSEL_SHIFT) +# define SYSCON_LCDCLKSEL_MAINCLK (0 << SYSCON_LCDCLKSEL_SHIFT) /* Main clock (main_clk) */ +# define SYSCON_LCDCLKSEL_LCDCLKIN (1 << SYSCON_LCDCLKSEL_SHIFT) /* LCD external clock input (LCD_CLKIN) */ +# define SYSCON_LCDCLKSEL_FROHF (2 << SYSCON_LCDCLKSEL_SHIFT) /* FRO 96 or 48 MHz (fro_hf) */ +# define SYSCON_LCDCLKSEL_NONE (3 << SYSCON_LCDCLKSEL_SHIFT) /* None */ + +/* SDIO clock source select */ + +#define SYSCON_SDIOCLKSEL_SHIFT (0) /* Bits 0-2: SDIO clock source select */ +#define SYSCON_SDIOCLKSEL_MASK (7 << SYSCON_SDIOCLKSEL_SHIFT) +# define SYSCON_SDIOCLKSEL_MAINCLK (0 << SYSCON_SDIOCLKSEL_SHIFT) /* Main clock (main_clk) */ +# define SYSCON_SDIOCLKSEL_PLLCLK (1 << SYSCON_SDIOCLKSEL_SHIFT) /* System PLL output (pll_clk) */ +# define SYSCON_SDIOCLKSEL_USBPLLCLK (2 << SYSCON_SDIOCLKSEL_SHIFT) /* USB PLL clock (usb_pll_clk) */ +# define SYSCON_SDIOCLKSEL_FROHF (3 << SYSCON_SDIOCLKSEL_SHIFT) /* FRO 96 or 48 MHz (fro_hf) */ +# define SYSCON_SDIOCLKSEL_AUDIOPLLCLK (4 << SYSCON_SDIOCLKSEL_SHIFT) /* Audio PLL clock (audio_pll_clk) */ + +/* SYSTICK clock divider */ + +#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0) /* Bits 0-7: Clock divider value */ +#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xff << SYSCON_SYSTICKCLKDIV_DIV_SHIFT) +# define SYSCON_SYSTICKCLKDIV_DIV(n) ((uint32_t)((n)-1) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT) +#define SYSCON_SYSTICKCLKDIV_RESET (1 << 29) /* Bit 29: Resets the divider counter */ +#define SYSCON_SYSTICKCLKDIV_HALT (1 << 30) /* Bit 30: Halts the divider counter */ +#define SYSCON_SYSTICKCLKDIV_REQFLAG (1 << 31) /* Bit 31: Divider status flag */ + +/* ARM Trace clock divider */ +#define SYSCON_ARMTRCLKDIV_ +/* MCAN0 clock divider */ +#define SYSCON_CAN0CLKDIV_ +/* MCAN1 clock divider */ +#define SYSCON_CAN1CLKDIV_ +/* Smartcard0 clock divider */ +#define SYSCON_SC0CLKDIV_ +/* Smartcard1 clock divider */ +#define SYSCON_SC1CLKDIV_ +/* System clock divider */ + +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0) /* Bits 0-7: Clock divider value */ +#define SYSCON_AHBCLKDIV_DIV_MASK (0xff << SYSCON_AHBCLKDIV_DIV_SHIFT) +# define SYSCON_AHBCLKDIV_DIV(n) ((uint32_t)((n)-1) << SYSCON_AHBCLKDIV_DIV_SHIFT) +#define SYSCON_AHBCLKDIV_REQFLAG (1 << 31) /* Bit 32: Divider status flag */ + +/* CLKOUT clock divider */ +#define SYSCON_CLKOUTDIV_ +/* FROHF clock divider */ +#define SYSCON_FROHFDIV_ +/* SPIFI clock divider */ +#define SYSCON_SPIFICLKDIV_ +/* ADC clock divider */ +#define SYSCON_ADCCLKDIV_ +/* USB0 clock divider */ +#define SYSCON_USB0CLKDIV_ +/* USB1 clock divider */ +#define SYSCON_USB1CLKDIV_ + +/* Fractional rate divider */ + +#define SYSCON_FRGCTRL_DIV_SHIFT (0) /* Bits 0-7: Denominator of the fractional divider */ +#define SYSCON_FRGCTRL_DIV_MASK (0xff << SYSCON_FRGCTRL_DIV_SHIFT) +# define SYSCON_FRGCTRL_DIV(n) ((uint32_t)((n)-1) << SYSCON_FRGCTRL_DIV_SHIFT) +#define SYSCON_FRGCTRL_MULT_SHIFT (8) /* Bit 8-15: Numerator of the fractional divider */ +#define SYSCON_FRGCTRL_MULT_MASK (0xff << SYSCON_FRGCTRL_MULT_SHIFT) +# define SYSCON_FRGCTRL_MULT(n) ((uint32_t)(n) << SYSCON_FRGCTRL_MULT_SHIFT) + +/* DMIC clock divider */ +#define SYSCON_DMICCLKDIV_ +/* I2S MCLK clock divider */ +#define SYSCON_MCLKDIV_ + +/* LCD clock divider */ + +#define SYSCON_LCDCLKDIV_DIV_SHIFT (0) /* Bits 0-7: Clock divider value */ +#define SYSCON_LCDCLKDIV_DIV_MASK (0xff <> 1) - 1) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT) +#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5) /* Bits 5-9: Frequency select */ +#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x1f << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) +# define SYSCON_WDTOSCCTRL_FREQSEL_04pMHZ (1 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 0.4 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_0p6MHZ (2 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 0.6 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_0p75MHZ (3 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 0.75 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_0p9MHZ (4 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 0.9 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_1p0MHZ (5 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 1.0 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_1p2MHZ (6 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 1.2 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_1p3MHZ (7 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 1.3 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_1p4MHZ (8 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 1.4 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_1p5MHZ (9 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 1.5 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_1p6MHZ (10 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 1.6 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_1p7MHZ (11 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 1.7 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_1p8MHZ (12 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 1.8 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_1p9MHZ (13 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 1.9 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p0MHZ (14 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 2.0 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p05MHZ (15 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 2.05 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p1MHZ (16 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 2.1 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p2MHZ (17 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 2.2 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p25MHZ (18 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 2.25 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p3MHZ (19 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 2.3 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p4MHZ (20 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 2.4 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p45MHZ (21 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 2.45 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p5MHZ (22 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 2.5 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p6MHZ (23 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 2.6 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p65MHZ (24 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 2.65 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p7MHZ (25 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 2.7 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p8MHZ (26 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 2.8 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p85MHZ (27 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 2.85 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p9MHZ (28 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 2.9 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_2p95MHZ (29 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 2.95 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_3p0MHZ (30 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 3.0 MHz */ +# define SYSCON_WDTOSCCTRL_FREQSEL_3p05MHZ (31 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* 3.05 MHz */ + +/* RTC oscillator 32 kHz output control */ + +#define SYSCON_RTCOSCCTRL_EN (1 << 0) /* Bit 0: RTC 32 kHz clock enable */ + +/* USB PLL control */ +#define SYSCON_USBPLLCTRL_ +/* USB PLL status */ +#define SYSCON_USBPLLSTAT_ + +/* System PLL control */ + +#define SYSCON_SYSPLLCTRL_SELR_SHIFT (0) /* Bits 0-3: Bandwidth select R value */ +#define SYSCON_SYSPLLCTRL_SELR_MASK (15 << SYSCON_SYSPLLCTRL_SELR_SHIFT) +# define SYSCON_SYSPLLCTRL_SELR(n) ((uint32_t)(n) << SYSCON_SYSPLLCTRL_SELR_SHIFT) +#define SYSCON_SYSPLLCTRL_SELI_SHIFT (4) /* Bits 4-9: Bandwidth select I value */ +#define SYSCON_SYSPLLCTRL_SELI_MASK (0x3f << SYSCON_SYSPLLCTRL_SELI_SHIFT) +# define SYSCON_SYSPLLCTRL_SELI(n) ((uint32_t)(n) << SYSCON_SYSPLLCTRL_SELI_SHIFT) +#define SYSCON_SYSPLLCTRL_SELP_SHIFT (10) /* Bits 10-14: Bandwidth select P value */ +#define SYSCON_SYSPLLCTRL_SELP_MASK (0x1f << SYSCON_SYSPLLCTRL_SELP_SHIFT) +# define SYSCON_SYSPLLCTRL_SELP(n) ((uint32_t)(n) << SYSCON_SYSPLLCTRL_SELP_SHIFT) +#define SYSCON_SYSPLLCTRL_BYPASS (1 << 15) /* Bit 15: PLL bypass control */ +#define SYSCON_SYSPLLCTRL_UPLIMOFF (1 << 17) /* Bit 17: Disable upper frequency limiter */ +#define SYSCON_SYSPLLCTRL_DIRECTI (1 << 19) /* Bit 19: PLL direct input enable */ +#define SYSCON_SYSPLLCTRL_DIRECTO (1 << 10) /* Bit 20: PLL direct output enable */ + +/* PLL status */ + +#define SYSCON_SYSPLLSTAT_LOCK (1 << 0) /* Bit 0: LOCK PLL lock indicator */ + +/* PLL N divider */ + +#define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0) /* Bits 0-9: Decoded N-divider coefficient */ +#define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3ff << SYSCON_SYSPLLNDEC_NDEC_SHIFT) +# define SYSCON_SYSPLLNDEC_NDEC(n) ((uint32_t)(n) << SYSCON_SYSPLLNDEC_NDEC_SHIFT) +#define SYSCON_SYSPLLNDEC_NREQ (1 << 10) /* Bit 10: NDEC reload request */ + +/* PLL P divider */ + +#define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0) /* Bits 0-6: Decoded P-divider coefficient */ +#define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7f << SYSCON_SYSPLLPDEC_PDEC_SHIFT) +# define SYSCON_SYSPLLPDEC_PDEC(n) ((uint32_t)(n) << SYSCON_SYSPLLPDEC_PDEC_SHIFT) +#define SYSCON_SYSPLLPDEC_PREQ (1 << 7) /* Bit 7: PDEC reload request */ + +/* System PLL M divider */ + +#define SYSCON_SYSPLLMDEC_MDEC_SHIFT (0) /* Bits 0-16: Decoded M-divider coefficient */ +#define SYSCON_SYSPLLMDEC_MDEC_MASK (0xffff << SYSCON_SYSPLLMDEC_MDEC_SHIFT) +# define SYSCON_SYSPLLMDEC_MDEC(n) ((uint32_t)(n) << SYSCON_SYSPLLMDEC_MDEC_SHIFT) +#define SYSCON_SYSPLLMDEC_MREQ (1 << 17) /* Bit 17: MDEC reload request */ + +/* Audio PLL control */ +#define SYSCON_AUDPLLCTRL_ +/* Audio PLL status */ +#define SYSCON_AUDPLLSTAT_ +/* Audio PLL N divider */ +#define SYSCON_AUDPLLNDEC_ +/* Audio PLL P divider */ +#define SYSCON_AUDPLLPDEC_ +/* Audio PLL M divider */ +#define SYSCON_AUDPLLMDEC_ +/* Audio PLL fractional divider control */ +#define SYSCON_AUDPLLFRAC_ +/* Sleep configuration register 0 */ +#define SYSCON_PDSLEEPCFG0_ +/* Sleep configuration register 1 */ +#define SYSCON_PDSLEEPCFG1_ + +/* Power configuration register 0 (also corresponding set/clear registers) */ + +#define SYSCON_PDRUNCFG0_FRO (1 << 4) /* Bit 4: FRO oscillator */ +#define SYSCON_PDRUNCFG0_TS (1 << 6) /* Bit 6: Temp sensor */ +#define SYSCON_PDRUNCFG0_BODRST (1 << 7) /* Bit 7: Brown-out Detect reset */ +#define SYSCON_PDRUNCFG0_BODINTR (1 << 8) /* Bit 8: Brown-out Detect interrupt */ +#define SYSCON_PDRUNCFG0_VD2ANA (1 << 9) /* Bit 9: Analog supply for System Oscillator */ +#define SYSCON_PDRUNCFG0_ADC0 (1 << 10) /* Bit 10: ADC power */ +#define SYSCON_PDRUNCFG0_SRAMX (1 << 13) /* Bit 13: Controls SRAMX */ +#define SYSCON_PDRUNCFG0_SRAM0 (1 << 14) /* Bit 14: Controls SRAM0 */ +#define SYSCON_PDRUNCFG0_SRAM123 (1 << 15) /* Bit 15: Controls SRAM1, SRAM2, and SRAM3 */ +#define SYSCON_PDRUNCFG0_USBRAM (1 << 16) /* Bit 16: Controls USB_RAM */ +#define SYSCON_PDRUNCFG0_VDDA (1 << 19) /* Bit 19: VDDA to the ADC */ +#define SYSCON_PDRUNCFG0_WDTOSC (1 << 20) /* Bit 20: Watchdog oscillator */ +#define SYSCON_PDRUNCFG0_USB0PHY (1 << 21) /* Bit 21: USB0 PHY power */ +#define SYSCON_PDRUNCFG0_SYSPLL (1 << 22) /* Bit 22: System PLL power */ +#define SYSCON_PDRUNCFG0_VREFP (1 << 23) /* Bit 23: VREFP to the ADC */ +#define SYSCON_PDRUNCFG0_VD3 (1 << 26) /* Bit 26: Power control for all PLLs */ +#define SYSCON_PDRUNCFG0_VD4 (1 << 27) /* Bit 27: Power control for all SRAMs and ROM */ +#define SYSCON_PDRUNCFG0_VD5 (1 << 28) /* Bit 28: Power control both USB0 PHY and USB1 PHY */ +#define SYSCON_PDRUNCFG0_VD6 (1 << 29) /* Bit 29 Power control for EEPROM */ + +/* Power configuration register 1 (also corresponding set/clear registers)*/ + +#define SYSCON_PDRUNCFG1_USB1PHY (1 << 0) /* Bit 0: USB1 high speed PHY */ +#define SYSCON_PDRUNCFG1_USB1PLL (1 << 1) /* Bit 1: USB PLL power */ +#define SYSCON_PDRUNCFG1_AUDPLL (1 << 2) /* Bit 2: Audio PLL power and fractional divider */ +#define SYSCON_PDRUNCFG1_SYSOSC (1 << 3) /* Bit 3: System Oscillator Power */ +#define SYSCON_PDRUNCFG1_EEPROM (1 << 5) /* Bit 5: EEPROM power */ +#define SYSCON_PDRUNCFG1_RNG (1 << 7) /* Bit 7: Random Number Generator Power */ + +/* Start logic 0 wake-up enable register */ +#define SYSCON_STARTER0_ +/* Start logic 1 wake-up enable register */ +#define SYSCON_STARTER1_ +/* Set bits in STARTER0 */ +#define SYSCON_STARTERSET0_ +/* Set bits in STARTER1 */ +#define SYSCON_STARTERSET1_ +/* Clear bits in STARTER0 */ +#define SYSCON_STARTERCLR0_ +/* Clear bits in STARTER1 */ +#define SYSCON_STARTERCLR1_ +/* Configures special cases of hardware wake-up */ +#define SYSCON_HWWAKE_ +/* Auto clock-gate override */ +#define SYSCON_AUTOCGOR_ +/* JTAG ID code */ +#define SYSCON_JTAGIDCODE_ +/* Part ID */ +#define SYSCON_DEVICE_ID0_ +/* Boot ROM and die revision */ +#define SYSCON_DEVICE_ID1_ + +/* Asynchronous system configuration */ + +/* Async peripheral reset control, set, and clear registers */ + +#define SYSCON_ASYNCPRESET_CTIMER3 (1 << 13) /* Bit 13: CTIMER3 reset control */ +#define SYSCON_ASYNCPRESET_CTIMER4 (1 << 14) /* Bit 14: CTIMER4 reset control */ + +/* Async peripheral clock control, set and clear registers */ + +#define SYSCON_ASYNCAPBCLKCTRL_CTIMER3 (1 << 13) /* Bit 13: CTIMER3 clock control */ +#define SYSCON_ASYNCAPBCLKCTRL_CTIMER4 (1 << 14) /* Bit 14: CTIMER4 clock control */ + +/* Async APB clock source select A */ +#define SYSCON_ASYNCAPBCLKSELA_ + +/* Other system configuration */ + +/* Brown-Out Detect control */ +#define SYSCON_BODCTRL_ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SYSCON_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_usart.h b/arch/arm/src/lpc54xx/chip/lpc54_usart.h new file mode 100644 index 0000000000000000000000000000000000000000..494f8d268f09a6dd8d7155bc370f7d8eec2bfdf1 --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_usart.h @@ -0,0 +1,420 @@ +/***************************************************************************************************** + * arch/arm/src/lpc54xx/chip/lpc54_usart.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_USART_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_USART_H + +/***************************************************************************************************** + * Included Files + *****************************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/***************************************************************************************************** + * Pre-processor Definitions + *****************************************************************************************************/ + +#define LPC54_USART_FIFO_DEPTH 8 /* All FIFOs are 16x8-bits */ + +/* USART Register Offsets ***************************************************************************/ + +/* Registers for the USART function: */ + +#define LPC54_USART_CFG_OFFSET 0x0000 /* USART Configuration register */ +#define LPC54_USART_CTL_OFFSET 0x0004 /* USART Control register */ +#define LPC54_USART_STAT_OFFSET 0x0008 /* USART Status register */ +#define LPC54_USART_INTENSET_OFFSET 0x000c /* USART Interrupt Enable read and Set register */ +#define LPC54_USART_INTENCLR_OFFSET 0x0010 /* USART Interrupt Enable Clear register */ +#define LPC54_USART_BRG_OFFSET 0x0020 /* USART Baud Rate Generator register */ +#define LPC54_USART_INTSTAT_OFFSET 0x0024 /* USART Interrupt status register */ +#define LPC54_USART_OSR_OFFSET 0x0028 /* USART Oversample selection register */ + +/* Registers for FIFO control and data access: */ + +#define LPC54_USART_FIFOCFG_OFFSET 0x0e00 /* FIFO configuration and enable register */ +#define LPC54_USART_FIFOSTAT_OFFSET 0x0e04 /* FIFO status register */ +#define LPC54_USART_FIFOTRIG_OFFSET 0x0e08 /* FIFO trigger settings for interrupt and DMA request */ +#define LPC54_USART_FIFOINTENSET_OFFSET 0x0e10 /* FIFO interrupt enable set (enable) and read register */ +#define LPC54_USART_FIFOINTENCLR_OFFSET 0x0e14 /* FIFO interrupt enable clear (disable) and read register */ +#define LPC54_USART_FIFOINTSTAT_OFFSET 0x0e18 /* FIFO interrupt status register */ +#define LPC54_USART_FIFOWR_OFFSET 0x0e20 /* FIFO write data */ +#define LPC54_USART_FIFORD_OFFSET 0x0e30 /* FIFO read data */ +#define LPC54_USART_FIFORDNOPOP_OFFSET 0x0e40 /* FIFO data read with no FIFO pop */ + +/* ID register: */ + +#define LPC54_USART_ID_OFFSET 0x0ffc /* USART module Identification */ + +/* USART Register Adreesses **************************************************************************/ + +#define LPC54_USART0_CFG (LPC54_FLEXCOMM0_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART0_CTL (LPC54_FLEXCOMM0_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART0_STAT (LPC54_FLEXCOMM0_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART0_INTENSET (LPC54_FLEXCOMM0_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART0_INTENCLR (LPC54_FLEXCOMM0_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART0_BRG (LPC54_FLEXCOMM0_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART0_INTSTAT (LPC54_FLEXCOMM0_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART0_OSR (LPC54_FLEXCOMM0_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART0_FIFOCFG (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART0_FIFOSTAT (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART0_FIFOTRIG (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART0_FIFOINTENSET (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART0_FIFOINTENCLR (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART0_FIFOINTSTAT (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART0_FIFOWR (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART0_FIFORD (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART0_FIFORDNOPOP (LPC54_FLEXCOMM0_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART0_ID (LPC54_FLEXCOMM0_BASE + LPC54_USART_ID_OFFSET) + +#define LPC54_USART1_CFG (LPC54_FLEXCOMM1_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART1_CTL (LPC54_FLEXCOMM1_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART1_STAT (LPC54_FLEXCOMM1_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART1_INTENSET (LPC54_FLEXCOMM1_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART1_INTENCLR (LPC54_FLEXCOMM1_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART1_BRG (LPC54_FLEXCOMM1_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART1_INTSTAT (LPC54_FLEXCOMM1_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART1_OSR (LPC54_FLEXCOMM1_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART1_FIFOCFG (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART1_FIFOSTAT (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART1_FIFOTRIG (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART1_FIFOINTENSET (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART1_FIFOINTENCLR (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART1_FIFOINTSTAT (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART1_FIFOWR (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART1_FIFORD (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART1_FIFORDNOPOP (LPC54_FLEXCOMM1_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART1_ID (LPC54_FLEXCOMM1_BASE + LPC54_USART_ID_OFFSET) + +#define LPC54_USART2_CFG (LPC54_FLEXCOMM2_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART2_CTL (LPC54_FLEXCOMM2_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART2_STAT (LPC54_FLEXCOMM2_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART2_INTENSET (LPC54_FLEXCOMM2_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART2_INTENCLR (LPC54_FLEXCOMM2_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART2_BRG (LPC54_FLEXCOMM2_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART2_INTSTAT (LPC54_FLEXCOMM2_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART2_OSR (LPC54_FLEXCOMM2_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART2_FIFOCFG (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART2_FIFOSTAT (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART2_FIFOTRIG (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART2_FIFOINTENSET (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART2_FIFOINTENCLR (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART2_FIFOINTSTAT (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART2_FIFOWR (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART2_FIFORD (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART2_FIFORDNOPOP (LPC54_FLEXCOMM2_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART2_ID (LPC54_FLEXCOMM2_BASE + LPC54_USART_ID_OFFSET) + +#define LPC54_USART3_CFG (LPC54_FLEXCOMM3_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART3_CTL (LPC54_FLEXCOMM3_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART3_STAT (LPC54_FLEXCOMM3_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART3_INTENSET (LPC54_FLEXCOMM3_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART3_INTENCLR (LPC54_FLEXCOMM3_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART3_BRG (LPC54_FLEXCOMM3_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART3_INTSTAT (LPC54_FLEXCOMM3_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART3_OSR (LPC54_FLEXCOMM3_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART3_FIFOCFG (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART3_FIFOSTAT (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART3_FIFOTRIG (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART3_FIFOINTENSET (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART3_FIFOINTENCLR (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART3_FIFOINTSTAT (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART3_FIFOWR (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART3_FIFORD (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART3_FIFORDNOPOP (LPC54_FLEXCOMM3_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART3_ID (LPC54_FLEXCOMM3_BASE + LPC54_USART_ID_OFFSET) + +#define LPC54_USART4_CFG (LPC54_FLEXCOMM4_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART4_CTL (LPC54_FLEXCOMM4_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART4_STAT (LPC54_FLEXCOMM4_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART4_INTENSET (LPC54_FLEXCOMM4_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART4_INTENCLR (LPC54_FLEXCOMM4_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART4_BRG (LPC54_FLEXCOMM4_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART4_INTSTAT (LPC54_FLEXCOMM4_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART4_OSR (LPC54_FLEXCOMM4_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART4_FIFOCFG (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART4_FIFOSTAT (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART4_FIFOTRIG (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART4_FIFOINTENSET (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART4_FIFOINTENCLR (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART4_FIFOINTSTAT (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART4_FIFOWR (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART4_FIFORD (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART4_FIFORDNOPOP (LPC54_FLEXCOMM4_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART4_ID (LPC54_FLEXCOMM4_BASE + LPC54_USART_ID_OFFSET) + +#define LPC54_USART5_CFG (LPC54_FLEXCOMM5_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART5_CTL (LPC54_FLEXCOMM5_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART5_STAT (LPC54_FLEXCOMM5_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART5_INTENSET (LPC54_FLEXCOMM5_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART5_INTENCLR (LPC54_FLEXCOMM5_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART5_BRG (LPC54_FLEXCOMM5_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART5_INTSTAT (LPC54_FLEXCOMM5_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART5_OSR (LPC54_FLEXCOMM5_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART5_FIFOCFG (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART5_FIFOSTAT (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART5_FIFOTRIG (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART5_FIFOINTENSET (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART5_FIFOINTENCLR (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART5_FIFOINTSTAT (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART5_FIFOWR (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART5_FIFORD (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART5_FIFORDNOPOP (LPC54_FLEXCOMM5_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART5_ID (LPC54_FLEXCOMM5_BASE + LPC54_USART_ID_OFFSET) + +#define LPC54_USART6_CFG (LPC54_FLEXCOMM6_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART6_CTL (LPC54_FLEXCOMM6_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART6_STAT (LPC54_FLEXCOMM6_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART6_INTENSET (LPC54_FLEXCOMM6_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART6_INTENCLR (LPC54_FLEXCOMM6_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART6_BRG (LPC54_FLEXCOMM6_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART6_INTSTAT (LPC54_FLEXCOMM6_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART6_OSR (LPC54_FLEXCOMM6_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART6_FIFOCFG (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART6_FIFOSTAT (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART6_FIFOTRIG (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART6_FIFOINTENSET (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART6_FIFOINTENCLR (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART6_FIFOINTSTAT (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART6_FIFOWR (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART6_FIFORD (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART6_FIFORDNOPOP (LPC54_FLEXCOMM6_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART6_ID (LPC54_FLEXCOMM6_BASE + LPC54_USART_ID_OFFSET) + +#define LPC54_USART7_CFG (LPC54_FLEXCOMM7_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART7_CTL (LPC54_FLEXCOMM7_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART7_STAT (LPC54_FLEXCOMM7_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART7_INTENSET (LPC54_FLEXCOMM7_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART7_INTENCLR (LPC54_FLEXCOMM7_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART7_BRG (LPC54_FLEXCOMM7_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART7_INTSTAT (LPC54_FLEXCOMM7_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART7_OSR (LPC54_FLEXCOMM7_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART7_FIFOCFG (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART7_FIFOSTAT (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART7_FIFOTRIG (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART7_FIFOINTENSET (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART7_FIFOINTENCLR (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART7_FIFOINTSTAT (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART7_FIFOWR (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART7_FIFORD (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART7_FIFORDNOPOP (LPC54_FLEXCOMM7_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART7_ID (LPC54_FLEXCOMM7_BASE + LPC54_USART_ID_OFFSET) + +#define LPC54_USART8_CFG (LPC54_FLEXCOMM8_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART8_CTL (LPC54_FLEXCOMM8_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART8_STAT (LPC54_FLEXCOMM8_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART8_INTENSET (LPC54_FLEXCOMM8_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART8_INTENCLR (LPC54_FLEXCOMM8_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART8_BRG (LPC54_FLEXCOMM8_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART8_INTSTAT (LPC54_FLEXCOMM8_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART8_OSR (LPC54_FLEXCOMM8_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART8_FIFOCFG (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART8_FIFOSTAT (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART8_FIFOTRIG (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART8_FIFOINTENSET (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART8_FIFOINTENCLR (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART8_FIFOINTSTAT (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART8_FIFOWR (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART8_FIFORD (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART8_FIFORDNOPOP (LPC54_FLEXCOMM8_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART8_ID (LPC54_FLEXCOMM8_BASE + LPC54_USART_ID_OFFSET) + +#define LPC54_USART9_CFG (LPC54_FLEXCOMM9_BASE + LPC54_USART_CFG_OFFSET) +#define LPC54_USART9_CTL (LPC54_FLEXCOMM9_BASE + LPC54_USART_CTL_OFFSET) +#define LPC54_USART9_STAT (LPC54_FLEXCOMM9_BASE + LPC54_USART_STAT_OFFSET) +#define LPC54_USART9_INTENSET (LPC54_FLEXCOMM9_BASE + LPC54_USART_INTENSET_OFFSET) +#define LPC54_USART9_INTENCLR (LPC54_FLEXCOMM9_BASE + LPC54_USART_INTENCLR_OFFSET) +#define LPC54_USART9_BRG (LPC54_FLEXCOMM9_BASE + LPC54_USART_BRG_OFFSET) +#define LPC54_USART9_INTSTAT (LPC54_FLEXCOMM9_BASE + LPC54_USART_INTSTAT_OFFSET) +#define LPC54_USART9_OSR (LPC54_FLEXCOMM9_BASE + LPC54_USART_OSR_OFFSET) +#define LPC54_USART9_FIFOCFG (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFOCFG_OFFSET) +#define LPC54_USART9_FIFOSTAT (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFOSTAT_OFFSET) +#define LPC54_USART9_FIFOTRIG (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFOTRIG_OFFSET) +#define LPC54_USART9_FIFOINTENSET (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFOINTENSET_OFFSET) +#define LPC54_USART9_FIFOINTENCLR (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFOINTENCLR_OFFSET) +#define LPC54_USART9_FIFOINTSTAT (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFOINTSTAT_OFFSET) +#define LPC54_USART9_FIFOWR (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFOWR_OFFSET) +#define LPC54_USART9_FIFORD (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFORD_OFFSET) +#define LPC54_USART9_FIFORDNOPOP (LPC54_FLEXCOMM9_BASE + LPC54_USART_FIFORDNOPOP_OFFSET) +#define LPC54_USART9_ID (LPC54_FLEXCOMM9_BASE + LPC54_USART_ID_OFFSET) + +/* USART Register Bitfield Definitions ***************************************************************/ + +/* USART Configuration register */ + +#define USART_CFG_ENABLE (1 << 0) /* Bit 0 USART Enable */ +#define USART_CFG_DATALEN_SHIFT (2) /* Bits 2-3: Selects the data size for the USART */ +#define USART_CFG_DATALEN_MASK (3 << USART_CFG_DATALEN_SHIFT) +# define USART_CFG_DATALEN_7BIT (0 << USART_CFG_DATALEN_SHIFT) /* 7 bit Data length */ +# define USART_CFG_DATALEN_8BIT (1 << USART_CFG_DATALEN_SHIFT) /* 8 bit Data length */ +# define USART_CFG_DATALEN_9BIT (2 << USART_CFG_DATALEN_SHIFT) /* 9 bit data lengt */ +#define USART_CFG_PARITYSEL_SHIFT (4) /* Bits 4-5: Selects what type of parity is used by the USART */ +#define USART_CFG_PARITYSEL_MASK (3 << USART_CFG_PARITYSEL_SHIFT) +# define USART_CFG_PARITYSEL_NONE (0 << USART_CFG_PARITYSEL_SHIFT) /* No parity */ +# define USART_CFG_PARITYSEL_EVEN (2 << USART_CFG_PARITYSEL_SHIFT) /* Even parity */ +# define USART_CFG_PARITYSEL_ODD (3 << USART_CFG_PARITYSEL_SHIFT) /* Odd parity */ +#define USART_CFG_STOPLEN (1 << 6) /* Bit 6 Number of stop bits appended to transmitted data */ +#define USART_CFG_MODE32K (1 << 7) /* Bit 7 Selects standard or 32 kHz clocking mode */ +#define USART_CFG_LINMODE (1 << 8) /* Bit 8 LIN break mode enable */ +#define USART_CFG_CTSEN (1 << 9) /* Bit 9 CTS Enable */ +#define USART_CFG_SYNCEN (1 << 11) /* Bit 11 Selects synchronous or asynchronous operation */ +#define USART_CFG_CLKPOL (1 << 12) /* Bit 12 Selects clock polarity and sampling edge of RX data */ +#define USART_CFG_SYNCMST (1 << 14) /* Bit 14 Synchronous mode Master select */ +#define USART_CFG_LOOP (1 << 15) /* Bit 15 Selects data loopback mode */ +#define USART_CFG_OETA (1 << 18) /* Bit 18 Output Enable Turnaround time enable for RS-485 operation */ +#define USART_CFG_AUTOADDR (1 << 19) /* Bit 19 Automatic Address matching enable */ +#define USART_CFG_OESEL (1 << 20) /* Bit 20 Output Enable Select */ +#define USART_CFG_OEPOL (1 << 21) /* Bit 21 Output Enable Polarity */ +#define USART_CFG_RXPOL (1 << 22) /* Bit 22 Receive data polarity */ +#define USART_CFG_TXPOL (1 << 23) /* Bit 23 Transmit data polarity */ + +/* USART Control register */ + +#define USART_CTL_TXBRKEN (1 << 1) /* Bit 1: Break Enable */ +#define USART_CTL_ADDRDET (1 << 2) /* Bit 2: Enable address detect mode */ +#define USART_CTL_TXDIS (1 << 6) /* Bit 6: Transmit Disable */ +#define USART_CTL_CC (1 << 8) /* Bit 8: Continuous Clock generation */ +#define USART_CTL_CLRCCONRX (1 << 9) /* Bit 9: Clear Continuous Clock */ +#define USART_CTL_AUTOBAUD (1 << 16) /* Bit 16: Autobaud enable */ + +/* USART Status register, USART Interrupt Enable read and Set register, and USART Interrupt Enable Clear register */ + +#define USART_INTSTAT_RXIDLE (1 << 1) /* Bit 1: Receiver Idle (Status only) */ +#define USART_INT_TXIDLE (1 << 3) /* Bit 3: Transmitter Idle */ +#define USART_INTSTAT_CTS (1 << 4) /* Bit 4: State of the CTS signal (Status only) */ +#define USART_INT_DELTACTS (1 << 5) /* Bit 5: Change in the state of CTS flag */ +#define USART_INT_TXDIS (1 << 6) /* Bit 6: Transmitter Disabled Status flag */ +#define USART_INTSTAT_RXBRK (1 << 10) /* Bit 10: Received Break (Status only) */ +#define USART_INT_DELTARXBRK (1 << 11) /* Bit 11: Change in the state of receiver break detection */ +#define USART_INT_START (1 << 12) /* Bit 12: Start detected on the receiver input */ +#define USART_INT_FRAMERR (1 << 13) /* Bit 13: Framing Error interrupt flag */ +#define USART_INT_PARITYER (1 << 14) /* Bit 14: Parity Error interrupt flag */ +#define USART_INT_RXNOISE (1 << 15) /* Bit 15: Received Noise interrupt flag */ +#define USART_INT_ABERR (1 << 16) /* Bit 16: Auto baud Error */ + +/* USART Baud Rate Generator register */ + +#define USART_BRG_SHIFT (0) /* Bits 0-15: BAUD rate divisor */ +#define USART_BRG_MASK (0xffff << USART_OSR_SHIFT) +# define USART_BRG(n) ((uint32)((n)-1) << USART_OSR_SHIFT) + +/* USART Oversample selection register */ + +#define USART_OSR_SHIFT (0) /* Bits 0-3: Oversample Selection Value. */ +#define USART_OSR_MASK (15 << USART_OSR_SHIFT) +# define USART_OSR(n) ((uint32)((n)-1) << USART_OSR_SHIFT) + +/* FIFO configuration and enable register */ + +#define USART_FIFOCFG_ENABLETX (1 << 0) /* Bit 0: Enable the transmit FIFO */ +#define USART_FIFOCFG_ENABLERX (1 << 1) /* Bit 1: Enable the receive FIFO */ +#define USART_FIFOCFG_SIZE_SHIFT (4) /* Bits 4-5: FIFO size configuration */ +#define USART_FIFOCFG_SIZE_MASK (3 << USART_FIFOCFG_SIZE_SHIFT) +# define USART_FIFOCFG_SIZE_16x8 (0 << USART_FIFOCFG_SIZE_SHIFT) /* FIFO is 16 entries x 8 bits */ +#define USART_FIFOCFG_DMATX (1 << 12) /* Bit 12: DMA configuration for transmit */ +#define USART_FIFOCFG_DMARX (1 << 13) /* Bit 13: DMA configuration for receive */ +#define USART_FIFOCFG_WAKETX (1 << 14) /* Bit 14: Wake-up for transmit FIFO level */ +#define USART_FIFOCFG_WAKERX (1 << 15) /* Bit 15: Wake-up for receive FIFO level */ +#define USART_FIFOCFG_EMPTYTX (1 << 16) /* Bit 16: Empty command for the transmit FIFO */ +#define USART_FIFOCFG_EMPTYRX (1 << 17) /* Bit 17: Empty command for the receive FIFO */ + +/* FIFO status register */ + +#define USART_FIFOSTAT_TXERR (1 << 0) /* Bit 0 TX FIFO error */ +#define USART_FIFOSTAT_RXERR (1 << 1) /* Bit 1 RX FIFO error */ +#define USART_FIFOSTAT_PERINT (1 << 3) /* Bit 3 Peripheral interrupt */ +#define USART_FIFOSTAT_TXEMPTY (1 << 4) /* Bit 4 Transmit FIFO empty */ +#define USART_FIFOSTAT_TXNOTFULL (1 << 5) /* Bit 5 Transmit FIFO not full */ +#define USART_FIFOSTAT_RXNOTEMPTY (1 << 6) /* Bit 6 Receive FIFO not empty */ +#define USART_FIFOSTAT_RXFULL (1 << 7) /* Bit 7 Receive FIFO full */ +#define USART_FIFOSTAT_TXLVL_SHIFT (8) /* Bits 8-12: Transmit FIFO current level */ +#define USART_FIFOSTAT_TXLVL_MASK (31 << USART_FIFOSTAT_TXLVL_SHIFT) +#define USART_FIFOSTAT_RXLVL_SHIFT (16) /* Bits 16-20: Receive FIFO current level */ +#define USART_FIFOSTAT_RXLVL_MASK (31 << USART_FIFOSTAT_RXLVL_SHIFT) + +/* FIFO trigger settings for interrupt and DMA request */ + +#define USART_FIFOTRIG_TXLVLENA (1 << 0) /* Bit 0: Transmit FIFO level trigger enable */ +#define USART_FIFOTRIG_RXLVLENA (1 << 1) /* Bit 1: Receive FIFO level trigger enable */ +#define USART_FIFOTRIG_TXLVL_SHIFT (8) /* Bits 8-11: Transmit FIFO level trigger point */ +#define USART_FIFOTRIG_TXLVL_MASK (15 << USART_FIFOTRIG_TXLVL_SHIFT) +# define USART_FIFOTRIG_TXLVL(n) ((uint32_t)(n) << USART_FIFOTRIG_TXLVL_SHIFT) /* Interrupt when n entries */ +# define USART_FIFOTRIG_TXLVL_EMPTY USART_FIFOTRIG_TXLVL(0) +# define USART_FIFOTRIG_TXLVL_NOTFULL USART_FIFOTRIG_TXLVL(15) +#define USART_FIFOTRIG_RXLVL_SHIFT (16) /* Bits 16-19: Receive FIFO level trigger point */ +#define USART_FIFOTRIG_RXLVL_MASK (15 << USART_FIFOTRIG_RXLVL_SHIFT) +# define USART_FIFOTRIG_RXLVL(n) ((uint32_t)(n) << USART_FIFOTRIG_RXLVL_SHIFT) /* Interrupt when n+1 entries */ +# define USART_FIFOTRIG_RXLVL_NOTEMPY USART_FIFOTRIG_RXLVL(0) +# define USART_FIFOTRIG_RXLVL_FULL USART_FIFOTRIG_RXLVL(15) + +/* FIFO interrupt status register, FIFO interrupt enable set (enable), and read register and FIFO interrupt enable + * clear (disable) and read register + */ + +#define USART_FIFOINT_TXERR (1 << 0) /* Bit 0: Transmit FIFO error interrupt */ +#define USART_FIFOINT_RXERR (1 << 1) /* Bit 1: Receive ERROR error interrupt */ +#define USART_FIFOINT_TXLVL (1 << 2) /* Bit 2: Transmit FIFO level interrupt */ +#define USART_FIFOINT_RXLVL (1 << 3) /* Bit 3: Receive FIFO level interrupt */ +#define USART_FIFOINTSTAT_PERINT (1 << 4) /* Bit 4: Peripheral interrupt (Status only) */ + +#define USART_FIFOINT_ALL 0x0000000f + +/* FIFO write data */ + +#define USART_FIFOWR_TXDATA_SHIFT (0) /* Bits 0-8: Transmit data to the FIFO */ +#define USART_FIFOWR_TXDATA_MASK (0x1ff << USART_FIFOWR_TXDATA_SHIFT) +# define USART_FIFOWR_TXDATA(n) ((uint32_t)(n) << USART_FIFOWR_TXDATA_SHIFT) + +/* FIFO read data register and FIFO data read with no FIFO pop register */ + +#define USART_FIFORD_RXDATA_SHIFT (0) /* Bits 0-8: Received data from the FIFO */ +#define USART_FIFORD_RXDATA_MASK (0x1ff << USART_FIFOWR_TXDATA_SHIFT) + +#define USART_FIFORD_FRAMERR (1 << 13) /* Bit 13: Framing Error status flag */ +#define USART_FIFORD_PARITYERR (1 << 14) /* Bit 14: Parity Error status flag */ +#define USART_FIFORD_RXNOISE (1 << 15) /* Bit 15: Received Noise flag */ + +/* USART module Identification */ + +#define USART_ID_APERTURE_SHIFT (0) /* Bits 0-7: Aperture encoded as (aperture size/4K) -1 */ +#define USART_ID_APERTURE_MASKX (0xff << USART_ID_APERTURE_SHIFT) +#define USART_ID_MINOR_SHIFT (8) /* Bits 8-11: Minor revision of module implementation */ +#define USART_ID_MINOR_MASKX (15 << USART_ID_MINOR_SHIFT) +#define USART_ID_MAJOR_SHIFT (12) /* Bits 12-15: Major revision of module implementation */ +#define USART_ID_MAJOR_MASKX (15 << USART_ID_MAJOR_SHIFT) +#define USART_ID_ID_SHIFT (16) /* Bits 16-31: ID Unique module identifier for this IP block */ +#define USART_ID_ID_MASKX (0xffff << USART_ID_ID_SHIFT) + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_USART_H */ diff --git a/arch/arm/src/lpc54xx/chip/lpc54_wwdt.h b/arch/arm/src/lpc54xx/chip/lpc54_wwdt.h new file mode 100644 index 0000000000000000000000000000000000000000..c292304d308060d4bbdc20f69f257a843254d8da --- /dev/null +++ b/arch/arm/src/lpc54xx/chip/lpc54_wwdt.h @@ -0,0 +1,101 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/lpc54_wwdt.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_WWDT_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_WWDT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/lpc54_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC54_WWDT_MOD_OFFSET 0x0000 /* Watchdog mode register */ +#define LPC54_WWDT_TC_OFFSET 0x0004 /* Watchdog timer constant register */ +#define LPC54_WWDT_FEED_OFFSET 0x0008 /* Watchdog feed sequence register */ +#define LPC54_WWDT_TV_OFFSET 0x000c /* Watchdog timer value register */ +#define LPC54_WWDT_WARNINT_OFFSET 0x0014 /* Watchdog warning interrupt register */ +#define LPC54_WWDT_WINDOW_OFFSET 0x0018 /* Watchdog timer window register */ + +/* Register addresses ***************************************************************/ + +#define LPC54_WWDT_MOD (LPC54_WWDT_BASE+LPC54_WWDT_MOD_OFFSET) +#define LPC54_WWDT_TC (LPC54_WWDT_BASE+LPC54_WWDT_TC_OFFSET) +#define LPC54_WWDT_FEED (LPC54_WWDT_BASE+LPC54_WWDT_FEED_OFFSET) +#define LPC54_WWDT_TV (LPC54_WWDT_BASE+LPC54_WWDT_TV_OFFSET) +#define LPC54_WWDT_WDCLKSEL (LPC54_WWDT_BASE+LPC54_WWDT_WDCLKSEL_OFFSET) +#define LPC54_WWDT_WARNINT (LPC54_WWDT_BASE+LPC54_WWDT_WARNINT_OFFSET) +#define LPC54_WWDT_WINDOW (LPC54_WWDT_BASE+LPC54_WWDT_WINDOW_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* Watchdog mode register */ + +#define WWDT_MOD_WDEN (1 << 0) /* Bit 0: Watchdog enable */ +#define WWDT_MOD_WDRESET (1 << 1) /* Bit 1: Watchdog reset enable */ +#define WWDT_MOD_WDTOF (1 << 2) /* Bit 2: Watchdog time-out */ +#define WWDT_MOD_WDINT (1 << 3) /* Bit 3: Watchdog interrupt */ +#define WWDT_MOD_WDPROTECT (1 << 4) /* Bit 4: Watchdog update mode */ +#define WWDT_MOD_LOCK (1 << 5) /* Bit 5: Prevent disabling WDT */ + /* Bits 6-31: Reserved */ +/* Watchdog timer constant register */ + +#define WWDT_TC_MASK 0x00ffffff /* Bits 0-23: Watchdog time-out value */ + /* Bits 24-31: Reserved */ +/* Watchdog feed sequence register */ + +#define WWDT_FEED_MASK 0xff /* Bits 0-7: Feed value: 0xaa followed by 0x55 */ + /* Bits 14-31: Reserved */ +/* Watchdog timer value register */ + +#define WWDT_TV_MASK 0x00ffffff /* Bits 0-23: Counter timer value */ + /* Bits 24-31: Reserved */ +/* Watchdog warning interrupt register */ + +#define WWDT_WARNINT_MASK 0x03ff /* Bits 0-9: Watchdog warning compare value */ + /* Bits 10-31: Reserved */ +/* Watchdog timer window register */ + +#define WWDT_WINDOW_MASK 0x00ffffff /* Bits 0-23: Watchdog window value */ + /* Bits 24-31: Reserved */ + +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_WWDT_H */ diff --git a/arch/arm/src/lpc54xx/lpc546x_enableclk.h b/arch/arm/src/lpc54xx/lpc546x_enableclk.h new file mode 100644 index 0000000000000000000000000000000000000000..95e1d5bd18f441e768083cb2f9bbf09b5acee49e --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc546x_enableclk.h @@ -0,0 +1,265 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc546x_enableclk.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC546X_ENABLECLK_H +#define __ARCH_ARM_SRC_LPC54XX_LPC546X_ENABLECLK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "up_arch.h" +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define lpc54_periph0_enableclk(b) putreg32((b), LPC54_SYSCON_AHBCLKCTRLSET0) +#define lpc54_periph1_enableclk(b) putreg32((b), LPC54_SYSCON_AHBCLKCTRLSET1) +#define lpc54_periph2_enableclk(b) putreg32((b), LPC54_SYSCON_AHBCLKCTRLSET2) +#define lpc54_asynch_enableclk(b) putreg32((b), LPC54_SYSCON_ASYNCAPBCLKCTRLSET) + +#define lpc54_periph0_disableclk(b) putreg32((b), LPC54_SYSCON_AHBCLKCTRLCLR0) +#define lpc54_periph1_disableclk(b) putreg32((b), LPC54_SYSCON_AHBCLKCTRLCLR1) +#define lpc54_periph2_disableclk(b) putreg32((b), LPC54_SYSCON_AHBCLKCTRLCLR2) +#define lpc54_asynch_disableclk(b) putreg32((b), LPC54_SYSCON_ASYNCAPBCLKCTRLCLR) + +#define lpc54_periph0_isenabled(b) ((getreg32(LPC54_SYSCON_AHBCLKCTRL0) & (b)) != 0) +#define lpc54_periph1_isenabled(b) ((getreg32(LPC54_SYSCON_AHBCLKCTRL1) & (b)) != 0) +#define lpc54_periph2_isenabled(b) ((getreg32(LPC54_SYSCON_AHBCLKCTRL2) & (b)) != 0) +#define lpc54_asynch_isenabled(b) ((getreg32(LPC54_SYSCON_ASYNCAPBCLKCTRL) & (b)) != 0) + +/* Enable peripheral clocking */ + +#define lpc54_rom_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_ROM) +#define lpc54_sram1_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_SRAM1) +#define lpc54_sram2_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_SRAM2) +#define lpc54_sram3_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_SRAM3) +#define lpc54_flash_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_FLASH) +#define lpc54_fmc_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_FMC) +#define lpc54_eeprom_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_EEPROM) +#define lpc54_spifi_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_SPIFI) +#define lpc54_inputmux_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_INPUTMUX) +#define lpc54_iocon_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_IOCON) +#define lpc54_gpio0_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_GPIO0) +#define lpc54_gpio1_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_GPIO1) +#define lpc54_gpio2_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_GPIO2) +#define lpc54_gpio3_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_GPIO3) +#define lpc54_pint_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_PINT) +#define lpc54_gint_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_GINT) +#define lpc54_dma_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_DMA) +#define lpc54_crc_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_CRC) +#define lpc54_wwdt_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_WWDT) +#define lpc54_rtc_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_RTC) +#define lpc54_adc0_enableclk() lpc54_periph0_enableclk(SYSCON_AHBCLKCTRL0_ADC0) + +#define lpc54_mrt_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_MRT) +#define lpc54_rit_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_RIT) +#define lpc54_sct0_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_SCT0) +#define lpc54_mcan0_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_MCAN0) +#define lpc54_mcan1_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_MCAN1) +#define lpc54_utick_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_UTICK) +#define lpc54_flexcomm0_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM0) +#define lpc54_flexcomm1_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM1) +#define lpc54_flexcomm2_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM2) +#define lpc54_flexcomm3_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM3) +#define lpc54_flexcomm4_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM4) +#define lpc54_flexcomm5_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM5) +#define lpc54_flexcomm6_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM6) +#define lpc54_flexcomm7_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM7) +#define lpc54_dmic_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_DMIC) +#define lpc54_ctimer2_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_CTIMER2) +#define lpc54_usb0d_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_USB0D) +#define lpc54_ctimer0_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_CTIMER0) +#define lpc54_ctimer1_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_CTIMER1) + +#define lpc54_lcd_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_LCD) +#define lpc54_sdmmc_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_SDIO) +#define lpc54_usb1h_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_USB1H) +#define lpc54_usb1d_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_USB1D) +#define lpc54_usb1ram_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_USB1RAM) +#define lpc54_emc_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_EMC) +#define lpc54_eth_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_ETH) +#define lpc54_gpio4_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_GPIO4) +#define lpc54_gpio5_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_GPIO5) +#define lpc54_otp_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_OTP) +#define lpc54_rng_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_RNG) +#define lpc54_flexcomm8_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_FLEXCOMM8) +#define lpc54_flexcomm9_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_FLEXCOMM9) +#define lpc54_usb0hmr_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_USB0HMR) +#define lpc54_usb0hsl_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_USB0HSL) +#define lpc54_sha_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_SHA) +#define lpc54_sc0_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_SC0) +#define lpc54_sc1_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_SC1) + +#define lpc54_ctimer3_enableclk() lpc54_asynch_enableclk(SYSCON_ASYNCAPBCLKCTRL_CTIMER3) +#define lpc54_ctimer4_enableclk() lpc54_asynch_enableclk(SYSCON_ASYNCAPBCLKCTRL_CTIMER4) + +/* Disable peripheral clocking */ + +#define lpc54_rom_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_ROM) +#define lpc54_sram1_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_SRAM1) +#define lpc54_sram2_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_SRAM2) +#define lpc54_sram3_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_SRAM3) +#define lpc54_flash_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_FLASH) +#define lpc54_fmc_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_FMC) +#define lpc54_eeprom_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_EEPROM) +#define lpc54_spifi_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_SPIFI) +#define lpc54_inputmux_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_INPUTMUX) +#define lpc54_iocon_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_IOCON) +#define lpc54_gpio0_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_GPIO0) +#define lpc54_gpio1_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_GPIO1) +#define lpc54_gpio2_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_GPIO2) +#define lpc54_gpio3_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_GPIO3) +#define lpc54_pint_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_PINT) +#define lpc54_gint_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_GINT) +#define lpc54_dma_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_DMA) +#define lpc54_crc_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_CRC) +#define lpc54_wwdt_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_WWDT) +#define lpc54_rtc_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_RTC) +#define lpc54_adc0_disableclk() lpc54_periph0_disableclk(SYSCON_AHBCLKCTRL0_ADC0) + +#define lpc54_mrt_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_MRT) +#define lpc54_rit_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_RIT) +#define lpc54_sct0_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_SCT0) +#define lpc54_mcan0_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_MCAN0) +#define lpc54_mcan1_disableclk() lpc54_periph1_disableclkSYSCON_AHBCLKCTRL1_MCAN1) +#define lpc54_utick_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_UTICK) +#define lpc54_flexcomm0_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM0) +#define lpc54_flexcomm1_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM1) +#define lpc54_flexcomm2_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM2) +#define lpc54_flexcomm3_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM3) +#define lpc54_flexcomm4_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM4) +#define lpc54_flexcomm5_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM5) +#define lpc54_flexcomm6_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM6) +#define lpc54_flexcomm7_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_FLEXCOMM7) +#define lpc54_dmic_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_DMIC) +#define lpc54_ctimer2_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_CTIMER2) +#define lpc54_usb0d_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_USB0D) +#define lpc54_ctimer0_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_CTIMER0) +#define lpc54_ctimer1_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_CTIMER1) + +#define lpc54_lcd_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_LCD) +#define lpc54_sdmmc_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_SDIO) +#define lpc54_usb1h_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_USB1H) +#define lpc54_usb1d_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_USB1D) +#define lpc54_usb1ram_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_USB1RAM) +#define lpc54_emc_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_EMC) +#define lpc54_eth_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_ETH) +#define lpc54_gpio4_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_GPIO4) +#define lpc54_gpio5_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_GPIO5) +#define lpc54_otp_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_OTP) +#define lpc54_rng_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_RNG) +#define lpc54_flexcomm8_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_FLEXCOMM8) +#define lpc54_flexcomm9_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_FLEXCOMM9) +#define lpc54_usb0hmr_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_USB0HMR) +#define lpc54_usb0hsl_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_USB0HSL) +#define lpc54_sha_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_SHA) +#define lpc54_sc0_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_SC0) +#define lpc54_sc1_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_SC1) + +#define lpc54_ctimer3_disableclk() lpc54_asynch_disableclk(SYSCON_ASYNCAPBCLKCTRL_CTIMER3) +#define lpc54_ctimer4_disableclk() lpc54_asynch_disableclk(SYSCON_ASYNCAPBCLKCTRL_CTIMER4) + +/* Check if peripheral clocking is enabled */ + +#define lpc54_rom_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_ROM) +#define lpc54_sram1_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_SRAM1) +#define lpc54_sram2_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_SRAM2) +#define lpc54_sram3_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_SRAM3) +#define lpc54_flash_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_FLASH) +#define lpc54_fmc_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_FMC) +#define lpc54_eeprom_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_EEPROM) +#define lpc54_spifi_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_SPIFI) +#define lpc54_inputmux_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_INPUTMUX) +#define lpc54_iocon_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_IOCON) +#define lpc54_gpio0_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_GPIO0) +#define lpc54_gpio1_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_GPIO1) +#define lpc54_gpio2_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_GPIO2) +#define lpc54_gpio3_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_GPIO3) +#define lpc54_pint_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_PINT) +#define lpc54_gint_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_GINT) +#define lpc54_dma_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_DMA) +#define lpc54_crc_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_CRC) +#define lpc54_wwdt_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_WWDT) +#define lpc54_rtc_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_RTC) +#define lpc54_adc0_isenabled() lpc54_periph0_isenabled(SYSCON_AHBCLKCTRL0_ADC0) + +#define lpc54_mrt_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_MRT) +#define lpc54_rit_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_RIT) +#define lpc54_sct0_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_SCT0) +#define lpc54_mcan0_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_MCAN0) +#define lpc54_mcan1_isenabled() lpc54_periph1_isenabledSYSCON_AHBCLKCTRL1_MCAN1) +#define lpc54_utick_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_UTICK) +#define lpc54_flexcomm0_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_FLEXCOMM0) +#define lpc54_flexcomm1_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_FLEXCOMM1) +#define lpc54_flexcomm2_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_FLEXCOMM2) +#define lpc54_flexcomm3_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_FLEXCOMM3) +#define lpc54_flexcomm4_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_FLEXCOMM4) +#define lpc54_flexcomm5_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_FLEXCOMM5) +#define lpc54_flexcomm6_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_FLEXCOMM6) +#define lpc54_flexcomm7_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_FLEXCOMM7) +#define lpc54_dmic_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_DMIC) +#define lpc54_ctimer2_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_CTIMER2) +#define lpc54_usb0d_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_USB0D) +#define lpc54_ctimer0_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_CTIMER0) +#define lpc54_ctimer1_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_CTIMER1) + +#define lpc54_lcd_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_LCD) +#define lpc54_sdmmc_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_SDIO) +#define lpc54_usb1h_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_USB1H) +#define lpc54_usb1d_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_USB1D) +#define lpc54_usb1ram_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_USB1RAM) +#define lpc54_emc_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_EMC) +#define lpc54_eth_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_ETH) +#define lpc54_gpio4_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_GPIO4) +#define lpc54_gpio5_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_GPIO5) +#define lpc54_otp_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_OTP) +#define lpc54_rng_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_RNG) +#define lpc54_flexcomm8_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_FLEXCOMM8) +#define lpc54_flexcomm9_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_FLEXCOMM9) +#define lpc54_usb0hmr_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_USB0HMR) +#define lpc54_usb0hsl_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_USB0HSL) +#define lpc54_sha_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_SHA) +#define lpc54_sc0_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_SC0) +#define lpc54_sc1_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_SC1) + +#define lpc54_ctimer3_isenabled() lpc54_asynch_isenabled(SYSCON_ASYNCAPBCLKCTRL_CTIMER3) +#define lpc54_ctimer4_isenabled() lpc54_asynch_isenabled(SYSCON_ASYNCAPBCLKCTRL_CTIMER4) + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC546X_ENABLECLK_H */ diff --git a/arch/arm/src/lpc54xx/lpc546x_power.h b/arch/arm/src/lpc54xx/lpc546x_power.h new file mode 100644 index 0000000000000000000000000000000000000000..8bce39b63013c261e18d93b7ab0bad2bcd7cc69b --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc546x_power.h @@ -0,0 +1,150 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/lpc546x_power.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC546X_PERIPHPOWER_H +#define __ARCH_ARM_SRC_LPC54XX_LPC546X_PERIPHPOWER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "up_arch.h" +#include "chip/lpc54_syscon.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Setting the bit corresponding in the PDRUNCFGSET0/1 register powers down the + * selected component; clearling the bit enables it. + */ + +#define lpc54_powerup0(s) putreg32((s), LPC54_SYSCON_PDRUNCFGCLR0) +#define lpc54_powerup1(s) putreg32((s), LPC54_SYSCON_PDRUNCFGCLR1) +#define lpc54_powerdown0(s) putreg32((s), LPC54_SYSCON_PDRUNCFGSET0) +#define lpc54_powerdown1(s) putreg32((s), LPC54_SYSCON_PDRUNCFGSET1) +#define lpc54_ispowered0(s) ((getreg32(LPC54_SYSCON_PDRUNCFG0) & (s)) == 0) +#define lpc54_ispowered1(s) ((getreg32(LPC54_SYSCON_PDRUNCFG1) & (s)) == 0) + +/* Enable power */ + +#define lpc54_fro_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_FRO) +#define lpc54_ts_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_TS) +#define lpc54_bodrst_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_BODRST) +#define lpc54_bodintr_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_BODINTR) +#define lpc54_vd2ana_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_VD2ANA) +#define lpc54_adc0_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_ADC0) +#define lpc54_sramx_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_SRAMX) +#define lpc54_sam0_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_SRAM0) +#define lpc54_sram123_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_SRAM123) +#define lpc54_usbram_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_USBRAM) +#define lpc54_vdda_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_VDDA) +#define lpc54_wdtosc_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_WDTOSC) +#define lpc54_usb0phy_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_USB0PHY) +#define lpc54_syspll_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_SYSPLL) +#define lpc54_vrefp_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_VREFP) +#define lpc54_vd3_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_VD3) +#define lpc54_vd4_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_VD4) +#define lpc54_vd5_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_VD5) +#define lpc54_vd6_powerup() lpc54_powerup0(SYSCON_PDRUNCFG0_VD6) + +#define lpc54_usb1phy_powerup() lpc54_powerup1(SYSCON_PDRUNCFG1_USB1PHY) +#define lpc54_usb1pll_powerup() lpc54_powerup1(SYSCON_PDRUNCFG1_USB1PLL) +#define lpc54_audpll_powerup() lpc54_powerup1(SYSCON_PDRUNCFG1_AUDPLL) +#define lpc54_sysosc_powerup() lpc54_powerup1(SYSCON_PDRUNCFG1_SYSOSC) +#define lpc54_eeprom_powerup() lpc54_powerup1(SYSCON_PDRUNCFG1_EEPROM) +#define lpc54_rng_powerup() lpc54_powerup1(SYSCON_PDRUNCFG1_RNG) + +/* Disable power */ + +#define lpc54_fro_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_FRO) +#define lpc54_ts_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_TS) +#define lpc54_bodrst_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_BODRST) +#define lpc54_bodintr_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_BODINTR) +#define lpc54_vd2ana_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_VD2ANA) +#define lpc54_adc0_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_ADC0) +#define lpc54_sramx_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_SRAMX) +#define lpc54_sam0_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_SRAM0) +#define lpc54_sram123_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_SRAM123) +#define lpc54_usbram_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_USBRAM) +#define lpc54_vdda_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_VDDA) +#define lpc54_wdtosc_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_WDTOSC) +#define lpc54_usb0phy_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_USB0PHY) +#define lpc54_syspll_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_SYSPLL) +#define lpc54_vrefp_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_VREFP) +#define lpc54_vd3_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_VD3) +#define lpc54_vd4_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_VD4) +#define lpc54_vd5_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_VD5) +#define lpc54_vd6_powerdown() lpc54_powerdown0(SYSCON_PDRUNCFG0_VD6) + +#define lpc54_usb1phy_powerdown() lpc54_powerdown1(SYSCON_PDRUNCFG1_USB1PHY) +#define lpc54_usb1pll_powerdown() lpc54_powerdown1(SYSCON_PDRUNCFG1_USB1PLL) +#define lpc54_audpll_powerdown() lpc54_powerdown1(SYSCON_PDRUNCFG1_AUDPLL) +#define lpc54_sysosc_powerdown() lpc54_powerdown1(SYSCON_PDRUNCFG1_SYSOSC) +#define lpc54_eeprom_powerdown() lpc54_powerdown1(SYSCON_PDRUNCFG1_EEPROM) +#define lpc54_rng_powerdown() lpc54_powerdown1(SYSCON_PDRUNCFG1_RNG) + +/* Test if power is enabled */ + +#define lpc54_fro_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_FRO) +#define lpc54_ts_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_TS) +#define lpc54_bodrst_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_BODRST) +#define lpc54_bodintr_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_BODINTR) +#define lpc54_vd2ana_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_VD2ANA) +#define lpc54_adc0_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_ADC0) +#define lpc54_sramx_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_SRAMX) +#define lpc54_sam0_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_SRAM0) +#define lpc54_sram123_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_SRAM123) +#define lpc54_usbram_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_USBRAM) +#define lpc54_vdda_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_VDDA) +#define lpc54_wdtosc_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_WDTOSC) +#define lpc54_usb0phy_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_USB0PHY) +#define lpc54_syspll_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_SYSPLL) +#define lpc54_vrefp_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_VREFP) +#define lpc54_vd3_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_VD3) +#define lpc54_vd4_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_VD4) +#define lpc54_vd5_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_VD5) +#define lpc54_vd6_ispowered() lpc54_ispowered0(SYSCON_PDRUNCFG0_VD6) + +#define lpc54_usb1phy_ispowered() lpc54_ispowered1(SYSCON_PDRUNCFG1_USB1PHY) +#define lpc54_usb1pll_ispowered() lpc54_ispowered1(SYSCON_PDRUNCFG1_USB1PLL) +#define lpc54_audpll_ispowered() lpc54_ispowered1(SYSCON_PDRUNCFG1_AUDPLL) +#define lpc54_sysosc_ispowered() lpc54_ispowered1(SYSCON_PDRUNCFG1_SYSOSC) +#define lpc54_eeprom_ispowered() lpc54_ispowered1(SYSCON_PDRUNCFG1_EEPROM) +#define lpc54_rng_ispowered() lpc54_ispowered1(SYSCON_PDRUNCFG1_RNG) + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC546X_PERIPHPOWER_H */ diff --git a/arch/arm/src/lpc54xx/lpc546x_reset.h b/arch/arm/src/lpc54xx/lpc546x_reset.h new file mode 100644 index 0000000000000000000000000000000000000000..20ce44619b93fb05a712226952862e3fd2bc066e --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc546x_reset.h @@ -0,0 +1,125 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc546x_reset.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC546X_RESET_H +#define __ARCH_ARM_SRC_LPC54XX_LPC546X_RESET_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define lpc54_reset_peripheral0(m) \ + lpc54_reset(LPC54_SYSCON_PRESETCTRLSET0, LPC54_SYSCON_PRESETCTRLCLR0, \ + LPC54_SYSCON_PRESETCTRL0, (m)) + +#define lpc54_reset_peripheral1(m) \ + lpc54_reset(LPC54_SYSCON_PRESETCTRLSET1, LPC54_SYSCON_PRESETCTRLCLR1, \ + LPC54_SYSCON_PRESETCTRL1, (m)) + +#define lpc54_reset_peripheral2(m) \ + lpc54_reset(LPC54_SYSCON_PRESETCTRLSET2, LPC54_SYSCON_PRESETCTRLCLR2, \ + LPC54_SYSCON_PRESETCTRL2, (m)) + +#define lpc54_reset_async_peripheral(m) \ + lpc54_reset(LPC54_SYSCON_ASYNCPRESETCTRLSET, LPC54_SYSCON_ASYNCPRESETCTRLCLR, \ + LPC54_SYSCON_ASYNCPRESETCTRL, (m)) + +#define lpc54_reset_flash() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_FLASH) +#define lpc54_reset_fmc() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_FMC) +#define lpc54_reset_eeprom() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_EEPROM) +#define lpc54_reset_spifi() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_SPIFI) +#define lpc54_reset_inputmux() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_INPUTMUX) +#define lpc54_reset_iocon() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_IOCON) +#define lpc54_reset_gpio0() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GPIO0) +#define lpc54_reset_gpio1() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GPIO1) +#define lpc54_reset_gpio2() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GPIO2) +#define lpc54_reset_gpio3() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GPIO3) +#define lpc54_reset_pint() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_PINT) +#define lpc54_reset_gint() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_GINT) +#define lpc54_reset_dma() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_DMA) +#define lpc54_reset_crc() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_CRC) +#define lpc54_reset_wwdt() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_WWDT) +#define lpc54_reset_rtc() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_RTC) +#define lpc54_reset_adc0() lpc54_reset_peripheral0(SYSCON_PRESETCTRL0_ADC0) + +#define lpc54_reset_mrt() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_MRT) +#define lpc54_reset_sct0() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_SCT0) +#define lpc54_reset_mcan0() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_MCAN0) +#define lpc54_reset_mcan1() lpc54_reset_peripheral1SYSCON_PRESETCTRL1_MCAN1) +#define lpc54_reset_utick() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_UTICK) +#define lpc54_reset_flexcomm0() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM0) +#define lpc54_reset_flexcomm1() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM1) +#define lpc54_reset_flexcomm2() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM2) +#define lpc54_reset_flexcomm3() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM3) +#define lpc54_reset_flexcomm4() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM4) +#define lpc54_reset_flexcomm5() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM5) +#define lpc54_reset_flexcomm6() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM6) +#define lpc54_reset_flexcomm7() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_FLEXCOMM7) +#define lpc54_reset_dmic() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_DMIC) +#define lpc54_reset_ctimer2() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_CTIMER2) +#define lpc54_reset_usb0d() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_USB0D) +#define lpc54_reset_ctimer0() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_CTIMER0) +#define lpc54_reset_ctimer1() lpc54_reset_peripheral1(SYSCON_PRESETCTRL1_CTIMER1) + +#define lpc54_reset_lcd() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_LCD) +#define lpc54_reset_sdio() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_SDIO) +#define lpc54_reset_usb1h() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB1H) +#define lpc54_reset_usb1d() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB1D) +#define lpc54_reset_usb1ram() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB1RAM) +#define lpc54_reset_emc() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_EMC) +#define lpc54_reset_eth() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_ETH) +#define lpc54_reset_gpio4() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_GPIO4) +#define lpc54_reset_gpio5() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_GPIO5) +#define lpc54_reset_otp() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_OTP) +#define lpc54_reset_rng() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_RNG) +#define lpc54_reset_flexcomm8() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_FLEXCOMM8) +#define lpc54_reset_flexcomm9() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_FLEXCOMM9) +#define lpc54_reset_usb0hmr() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB0HMR) +#define lpc54_reset_usb0hsl() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_USB0HSL) +#define lpc54_reset_sha() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_SHA) +#define lpc54_reset_sc0() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_SC0) +#define lpc54_reset_sc1() lpc54_reset_peripheral2(SYSCON_PRESETCTRL2_SC1) + +#define lpc54_reset_ctimer3() lpc54_reset_async_peripheral(SYSCON_ASYNCPRESET_CTIMER3) +#define lpc54_reset_ctimer4() lpc54_reset_async_peripheral(SYSCON_ASYNCPRESET_CTIMER4) + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC546X_RESET_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_allocateheap.c b/arch/arm/src/lpc54xx/lpc54_allocateheap.c new file mode 100644 index 0000000000000000000000000000000000000000..cfd5a0719fe65445cd77d303bc2607f69389a0fe --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_allocateheap.c @@ -0,0 +1,411 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpx54_allocateheap.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "chip/lpc54_memorymap.h" +#include "lpc54_mpuinit.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ +/* Terminology. In the flat build (CONFIG_BUILD_FLAT=y), there is only a + * single heap access with the standard allocations (malloc/free). This + * heap is referred to as the user heap. In the protected build + * (CONFIG_BUILD_PROTECTED=y) where an MPU is used to protect a region of + * otherwise flat memory, there will be two allocators: One that allocates + * protected (kernel) memory and one that allocates unprotected (user) + * memory. These are referred to as the kernel and user heaps, + * respectively. + * + * The ARMv7 has no MPU but does have an MMU. With this MMU, it can support + * the kernel build (CONFIG_BUILD_KERNEL=y). In this configuration, there + * is one kernel heap but multiple user heaps: One per task group. However, + * in this case, we need only be concerned about initializing the single + * kernel heap here. + */ + +/* .bss and .data is always positioned in internal SRAM. The remaining SRAM + * after the static .bss, .data, and IDLE stack allocations are always added + * to the heap. + * + * If the EMC is enabled, if there is SRAM or SDRAM configured into the + * AND if the request heap size is non-zero, then that external RAM will + * also be added to the system according to the following definitions: + */ + +#undef HAVE_STATIC_CS0 +#undef HAVE_STATIC_CS1 +#undef HAVE_STATIC_CS2 +#undef HAVE_STATIC_CS3 + +#undef HAVE_DYNAMIC_CS0 +#undef HAVE_DYNAMIC_CS1 +#undef HAVE_DYNAMIC_CS2 +#undef HAVE_DYNAMIC_CS3 + +#ifdef CONFIG_LPC54_EMC +# ifdef CONFIG_LPC54_EMC_STATIC +# if defined(CONFIG_LPC54_EMC_STATIC_CS0) && CONFIG_LPC54_EMC_STATIC_CS0_SIZE > 0 +# define HAVE_STATIC_CS0 1 +# endif +# if defined(CONFIG_LPC54_EMC_STATIC_CS1) && CONFIG_LPC54_EMC_STATIC_CS1_SIZE > 0 +# define HAVE_STATIC_CS1 1 +# endif +# if defined(CONFIG_LPC54_EMC_STATIC_CS2) && CONFIG_LPC54_EMC_STATIC_CS2_SIZE > 0 +# define HAVE_STATIC_CS2 1 +# endif +# if defined(CONFIG_LPC54_EMC_STATIC_CS3) && CONFIG_LPC54_EMC_STATIC_CS3_SIZE > 0 +# define HAVE_STATIC_CS3 1 +# endif +# endif /* CONFIG_LPC54_EMC_STATIC */ +# ifdef CONFIG_LPC54_EMC_DYNAMIC +# if defined(CONFIG_LPC54_EMC_DYNAMIC_CS0) && CONFIG_LPC54_EMC_DYNAMIC_CS0_SIZE > 0 +# define HAVE_DYNAMIC_CS0 1 +# endif +# if defined(CONFIG_LPC54_EMC_DYNAMIC_CS1) && CONFIG_LPC54_EMC_DYNAMIC_CS1_SIZE > 0 +# define HAVE_DYNAMIC_CS1 1 +# endif +# if defined(CONFIG_LPC54_EMC_DYNAMIC_CS2) && CONFIG_LPC54_EMC_DYNAMIC_CS2_SIZE > 0 +# define HAVE_DYNAMIC_CS2 1 +# endif +# if defined(CONFIG_LPC54_EMC_DYNAMIC_CS3) && CONFIG_LPC54_EMC_DYNAMIC_CS3_SIZE > 0 +# define HAVE_DYNAMIC_CS3 1 +# endif +# endif /* CONFIG_LPC54_EMC_DYNAMIC */ +#endif /* CONFIG_LPC54_EMC */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* _sbss is the start of the BSS region (see the linker script) _ebss is the + * end of the BSS regsion (see the linker script). The idle task stack starts + * at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE + * thread is the thread that the system boots on and, eventually, becomes the + * idle, do nothing task that runs only when there is nothing else to run. + * The heap continues from there until the configured end of memory. + * g_idle_topstack is the beginning of this heap region (not necessarily + * aligned). + */ + +const uint32_t g_idle_topstack = (uint32_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap/up_allocate_kheap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * - For the normal "flat" build, this function returns the size of the + * single heap. + * - For the protected build (CONFIG_BUILD_PROTECTED=y) with both kernel- + * and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function + * provides the size of the unprotected, user-space heap. + * - For the kernel build (CONFIG_BUILD_KERNEL=y), this function provides + * the size of the protected, kernel-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated by an analogous up_allocate_kheap(). A custom version of this + * file is needed if memory protection of the kernel heap is required. + * + * The following memory map is assumed for the flat build: + * + * .data region. Size determined at link time. + * .bss region Size determined at link time. + * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Heap. Extends to the end of SRAM. + * + * The following memory map is assumed for the kernel build: + * + * Kernel .data region. Size determined at link time. + * Kernel .bss region Size determined at link time. + * Kernel IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Padding for alignment + * User .data region. Size determined at link time. + * User .bss region Size determined at link time. + * Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE. + * User heap. Extends to the end of SRAM. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_KERNEL +void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) +#else +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +#endif +{ +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + size_t usize = CONFIG_RAM_END - ubase; + + DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); + + /* Return the user-space heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (FAR void *)ubase; + *heap_size = usize; +#else + + /* Return the heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (FAR void *)g_idle_topstack; + *heap_size = CONFIG_RAM_END - g_idle_topstack; +#endif +} + +/**************************************************************************** + * Name: up_allocate_kheap + * + * Description: + * For the kernel build (CONFIG_BUILD_PROTECTED/KERNEL=y) with both kernel- + * and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates + * the kernel-space heap. A custom version of this function is needed if + * memory protection of the kernel heap is required. + * + ****************************************************************************/ + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) +void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) +{ + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); + + /* Return the kernel heap settings (i.e., the part of the heap region + * that was not dedicated to the user heap). + */ + + *heap_start = (FAR void *)USERSPACE->us_bssend; + *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend; +} +#endif + +/**************************************************************************** + * Name: up_addregion + * + * Description: + * Memory may be added in non-contiguous chunks. Additional chunks are + * added by calling this function. + * + ****************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void up_addregion(void) +{ + int remaining = CONFIG_MM_REGIONS; + FAR void *heapstart; + size_t heapsize; + +#ifdef HAVE_STATIC_CS0 + if (remaining > 0) + { + /* Add the SRAM to the user heap */ + + heapstart = (FAR void *)(LPC54_SRAMCS0_BASE + CONFIG_LPC54_EMC_STATIC_CS0_OFFSET); + heapsize = CONFIG_LPC54_EMC_STATIC_CS0_SIZE; + kumm_addregion(heapstart, heapsize); + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Allow user-mode access to the SDRAM heap */ + + lpc54_mpu_uheap((uintptr_t)heapstart, heapsize); +#endif + remaining--; + } +#endif /* HAVE_STATIC_CS0 */ + +#ifdef HAVE_STATIC_CS1 + if (remaining > 0) + { + /* Add the SRAM to the user heap */ + + heapstart = (FAR void *)(LPC54_SRAMCS1_BASE + CONFIG_LPC54_EMC_STATIC_CS1_OFFSET); + heapsize = CONFIG_LPC54_EMC_STATIC_CS1_SIZE; + kumm_addregion(heapstart, heapsize); + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Allow user-mode access to the SDRAM heap */ + + lpc54_mpu_uheap((uintptr_t)heapstart, heapsize); +#endif + remaining--; + } +#endif /* HAVE_STATIC_CS1 */ + +#ifdef HAVE_STATIC_CS2 + if (remaining > 0) + { + /* Add the SRAM to the user heap */ + + heapstart = (FAR void *)(LPC54_SRAMCS2_BASE + CONFIG_LPC54_EMC_STATIC_CS2_OFFSET); + heapsize = CONFIG_LPC54_EMC_STATIC_CS2_SIZE; + kumm_addregion(heapstart, heapsize); + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Allow user-mode access to the SDRAM heap */ + + lpc54_mpu_uheap((uintptr_t)heapstart, heapsize); +#endif + remaining--; + } +#endif /* HAVE_STATIC_CS2 */ + +#ifdef HAVE_STATIC_CS3 + if (remaining > 0) + { + /* Add the SRAM to the user heap */ + + heapstart = (FAR void *)(LPC54_SRAMCS3_BASE + CONFIG_LPC54_EMC_STATIC_CS3_OFFSET); + heapsize = CONFIG_LPC54_EMC_STATIC_CS3_SIZE; + kumm_addregion(heapstart, heapsize); + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Allow user-mode access to the SDRAM heap */ + + lpc54_mpu_uheap((uintptr_t)heapstart, heapsize); +#endif + remaining--; + } +#endif /* HAVE_STATIC_CS3 */ + +#ifdef HAVE_DYNAMIC_CS0 + if (remaining > 0) + { + /* Add the SDRAM to the user heap */ + + heapstart = (FAR void *)(LPC54_DRAMCS0_BASE + CONFIG_LPC54_EMC_DYNAMIC_CS0_OFFSET); + heapsize = CONFIG_LPC54_EMC_DYNAMIC_CS0_SIZE; + kumm_addregion(heapstart, heapsize); + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Allow user-mode access to the SDRAM heap */ + + lpc54_mpu_uheap((uintptr_t)heapstart, heapsize); +#endif + remaining--; + } +#endif /* HAVE_DYNAMIC_CS0 */ + +#ifdef HAVE_DYNAMIC_CS1 + if (remaining > 0) + { + /* Add the SDRAM to the user heap */ + + heapstart = (FAR void *)(LPC54_DRAMCS1_BASE + CONFIG_LPC54_EMC_DYNAMIC_CS1_OFFSET); + heapsize = CONFIG_LPC54_EMC_DYNAMIC_CS1_SIZE; + kumm_addregion(heapstart, heapsize); + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Allow user-mode access to the SDRAM heap */ + + lpc54_mpu_uheap((uintptr_t)heapstart, heapsize); +#endif + remaining--; + } +#endif /* HAVE_DYNAMIC_CS1 */ + +#ifdef HAVE_DYNAMIC_CS2 + if (remaining > 0) + { + /* Add the SDRAM to the user heap */ + + heapstart = (FAR void *)(LPC54_DRAMCS2_BASE + CONFIG_LPC54_EMC_DYNAMIC_CS2_OFFSET); + heapsize = CONFIG_LPC54_EMC_DYNAMIC_CS2_SIZE; + kumm_addregion(heapstart, heapsize); + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Allow user-mode access to the SDRAM heap */ + + lpc54_mpu_uheap((uintptr_t)heapstart, heapsize); +#endif + remaining--; + } +#endif /* HAVE_DYNAMIC_CS2 */ + +#ifdef HAVE_DYNAMIC_CS3 + if (remaining > 0) + { + /* Add the SDRAM to the user heap */ + + heapstart = (FAR void *)(LPC54_DRAMCS3_BASE + CONFIG_LPC54_EMC_DYNAMIC_CS3_OFFSET); + heapsize = CONFIG_LPC54_EMC_DYNAMIC_CS3_SIZE; + kumm_addregion(heapstart, heapsize); + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Allow user-mode access to the SDRAM heap */ + + lpc54_mpu_uheap((uintptr_t)heapstart, heapsize); +#endif + remaining--; + } +#endif /* HAVE_DYNAMIC_CS3 */ +} +#endif /* CONFIG_MM_REGIONS > 1 */ diff --git a/arch/arm/src/lpc54xx/lpc54_clockconfig.c b/arch/arm/src/lpc54xx/lpc54_clockconfig.c new file mode 100644 index 0000000000000000000000000000000000000000..1263767f6f2ee2c37ee2ae8866e83e823c547ab1 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_clockconfig.c @@ -0,0 +1,303 @@ +/**************************************************************************** + * arch/arm/src/lpc54628/lpc54_clockconfig.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Parts of this file were adapted from sample code provided for the LPC54xx + * family from NXP which has a compatible BSD license. + * + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016 - 2017 , NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "chip/lpc54_syscon.h" +#include "lpc54_power.h" +#include "lpc54_clockconfig.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_setvoltage + * + * Description: + * Set voltage for PLL frequency. + * + ****************************************************************************/ + +static void lpc54_setvoltage(uint32_t freq) +{ + if (freq == 12000000) + { + putreg32(0x21e, 0x40020040); + putreg32(4, LPC54_SYSCON_PDRUNCFGSET0); + } + else if (freq == 48000000) + { + putreg32(0x31e, 0x40020040); + putreg32(4, LPC54_SYSCON_PDRUNCFGSET0); + } + else + { + putreg32(4, LPC54_SYSCON_PDRUNCFGCLR0); + } +} + +/**************************************************************************** + * Name: lpc54_power_pll + * + * Description: + * Provide VD3 power to the PLL + * + ****************************************************************************/ + +static void lpc54_power_pll(void) +{ + lpc54_vd3_powerup(); + while ((getreg32(0x40020054) & (1 << 6)) == 0) + { + } +} + +/**************************************************************************** + * Name: lpc54_set_flash_waitstates + * + * Description: + * Set the FLASH wait states for the passed frequency + * + ****************************************************************************/ + +static void lpc54_set_flash_waitstates(uint32_t freq) +{ + uint32_t regval; + + regval = getreg32(LPC54_SYSCON_FLASHCFG); + regval &= ~SYSCON_FLASHCFG_FLASHTIM_MASK; + + if (freq <= 12000000) + { + regval |= SYSCON_FLASHCFG_FLASHTIM(1); + } + else if (freq <= 24000000) + { + regval |= SYSCON_FLASHCFG_FLASHTIM(2); + } + else if (freq <= 36000000) + { + regval |= SYSCON_FLASHCFG_FLASHTIM(3); + } + else if (freq <= 60000000) + { + regval |= SYSCON_FLASHCFG_FLASHTIM(4); + } + else if (freq <= 96000000) + { + regval |= SYSCON_FLASHCFG_FLASHTIM(5); + } + else if (freq <= 120000000) + { + regval |= SYSCON_FLASHCFG_FLASHTIM(6); + } + else if (freq <= 144000000) + { + regval |= SYSCON_FLASHCFG_FLASHTIM(7); + } + else if (freq <= 168000000) + { + regval |= SYSCON_FLASHCFG_FLASHTIM(8); + } + else + { + regval |= SYSCON_FLASHCFG_FLASHTIM(9); + } + + putreg32(regval, LPC54_SYSCON_FLASHCFG); +} + +/**************************************************************************** + * Name: lpc54_configure_pll + * + * Description: + * Configure the PLL. + * + *****************************************************************************/ + +static void lpc54_configure_pll(FAR const struct pll_setup_s *pllsetup) +{ + /* Enable power VD3 for PLLs */ + + lpc54_power_pll(); + + /* Power off PLL during setup changes */ + + lpc54_syspll_powerdown(); + + /* Write PLL setup data */ + + putreg32(pllsetup->pllctrl, LPC54_SYSCON_SYSPLLCTRL); + putreg32(pllsetup->pllndec, LPC54_SYSCON_SYSPLLNDEC); + putreg32(pllsetup->pllndec | SYSCON_SYSPLLNDEC_NREQ, + LPC54_SYSCON_SYSPLLNDEC); + putreg32(pllsetup->pllpdec, LPC54_SYSCON_SYSPLLPDEC); + putreg32(pllsetup->pllpdec | SYSCON_SYSPLLPDEC_PREQ, + LPC54_SYSCON_SYSPLLPDEC); + putreg32(pllsetup->pllmdec, LPC54_SYSCON_SYSPLLMDEC); + putreg32(pllsetup->pllmdec | SYSCON_SYSPLLMDEC_MREQ, + LPC54_SYSCON_SYSPLLMDEC); + + /* Flags for lock or power on */ + + if ((pllsetup->pllflags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0) + { + /* If turning the PLL back on, perform the following sequence to + * accelerate PLL lock. + */ + + volatile uint32_t delay; + uint32_t maxcco = (1 << 18) | 0x5dd2; /* CCO = 1.6Ghz + MDEC enabled */ + uint32_t ssctrl = getreg32(LPC54_SYSCON_SYSPLLMDEC) & ~SYSCON_SYSPLLMDEC_MREQ; + + /* Initialize and power up PLL */ + + putreg32(maxcco, LPC54_SYSCON_SYSPLLMDEC); + lpc54_syspll_powerup(); + + /* Set MREQ to activate */ + + putreg32(maxcco | SYSCON_SYSPLLMDEC_MREQ, LPC54_SYSCON_SYSPLLMDEC); + + /* Delay for 72 uSec @ 12Mhz */ + + for (delay = 0; delay < 172; delay++) + { + } + + /* Clear MREQ to prepare for restoring MREQ */ + + putreg32(ssctrl, LPC54_SYSCON_SYSPLLMDEC); + + /* set original value back and activate */ + + putreg32(ssctrl | SYSCON_SYSPLLMDEC_MREQ, LPC54_SYSCON_SYSPLLMDEC); + + /* Enable PLL */ + + lpc54_syspll_powerup(); + } + + /* Wait for the lock? */ + + if ((pllsetup->pllflags & PLL_SETUPFLAG_WAITLOCK) != 0) + { + while ((getreg32(LPC54_SYSCON_SYSPLLSTAT) & SYSCON_SYSPLLSTAT_LOCK) == 0) + { + } + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_clockconfig + * + * Description: + * Called to initialize the LPC54628. This does whatever setup is needed + * to put the MCU in a usable state. This includes the initialization of + * clocking using the settings in board.h. This function also performs + * other low-level chip as necessary. + * + *****************************************************************************/ + +void lpc54_clockconfig(FAR const struct pll_setup_s *pllsetup) +{ + /* Set up the clock sources */ + /* Power up the FRO 12MHz clock source */ + + lpc54_fro_powerup(); + + /* Switch to FRO 12MHz first to ensure we can change voltage without + * accidentally being below the voltage for current speed. + */ + + putreg32(SYSCON_MAINCLKSELA_FRO12, LPC54_SYSCON_MAINCLKSELA); + putreg32(SYSCON_MAINCLKSELB_MAINCLKSELA, LPC54_SYSCON_MAINCLKSELB); + + /* Set the voltage for the find PLL output frequency. This assumes + * that the PLL output frequncy is >=12MHz. + */ + + lpc54_setvoltage(pllsetup->pllfout); + + /* Set up the FLASH wait states for the core + * + * REVISIT: Should this be the PLL output frequency (Main clock) or + * the AHB clock? + */ + + lpc54_set_flash_waitstates(pllsetup->pllfout); + + /* Set up the PLL clock source to FRO 12MHz */ + + putreg32(pllsetup->pllclksel, LPC54_SYSCON_SYSPLLCLKSEL); + + /* Configure the PLL */ + + lpc54_configure_pll(pllsetup); + + /* Set up the AHB/CPU clock divider */ + + putreg32(pllsetup->ahbdiv, LPC54_SYSCON_AHBCLKDIV); + + /* Switch System clock to SYS PLL */ + + putreg32(SYSCON_MAINCLKSELB_PLLCLK, LPC54_SYSCON_MAINCLKSELB); + putreg32(SYSCON_MAINCLKSELA_FRO12, LPC54_SYSCON_MAINCLKSELA); +} diff --git a/arch/arm/src/lpc54xx/lpc54_clockconfig.h b/arch/arm/src/lpc54xx/lpc54_clockconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..746fd4b8808f943d58731dab5c93436855395e0b --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_clockconfig.h @@ -0,0 +1,139 @@ +/**************************************************************************** + * arch/arm/src/lpc64628/lpc54_clockconfig.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Parts of this file were adapted from sample code provided for the LPC54xx + * family from NXP which has a compatible BSD license. + * + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016 - 2017 , NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRCLPC54628_LPC54_CLOCKCONFIG_H +#define __ARCH_ARM_SRCLPC54628_LPC54_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Frequencies of internal clocks */ + +#define LPC54_SYSTEM_CLOCK 12000000 /* Default System clock value */ +#define LPC54_RTC_CLOCK 32768 /* RTC oscillator 32 kHz output (32k_clk )*/ +#define LPC54_FRO_12MHZ 12000000 /* FRO 12 MHz (fro_12m) */ +#define LPC54_FRO_48MHZ 48000000 /* FRO 48 MHz (fro_48m) */ +#define LPC54_FRO_96MHZ 96000000 /* FRO 96 MHz (fro_96m) */ +#define LPC54_CLKIN 0 /* CLKIN pin clock */ + +/* PLL setup structure flags for pllflags field. These flags control how + * the PLL setup function sets up the PLL + */ + +#define PLL_SETUPFLAG_POWERUP (1 << 0) /* Power on the PLL after setup */ +#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /* Wait for PLL lock and power on */ +#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /* Optimize system voltage for PLL rate */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* PLL setup structure. + * + * This structure can be used to define a PLL configuration. If powering + * up or waiting for PLL lock, the PLL input clock source should be + * configured prior to PLL setup. + */ + +struct pll_setup_s +{ + uint32_t pllclksel; /* PLL clock source register SYSPLLCLKSEL */ + uint32_t pllctrl; /* PLL control register SYSPLLCTRL */ + uint32_t pllndec; /* PLL NDEC register SYSPLLNDEC */ + uint32_t pllpdec; /* PLL PDEC register SYSPLLPDEC */ + uint32_t pllmdec; /* PLL MDEC registers SYSPLLPDEC */ + uint32_t pllfout; /* Actual PLL output frequency */ + uint32_t pllfrac; /* Only aduio PLL has this function*/ + uint32_t pllflags; /* PLL setup flags */ + uint32_t ahbdiv; /* AHB divider */ +}; + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_clockconfig + * + * Description: + * Called to initialize the LPC54628. This does whatever setup is needed + * to put the MCU in a usable state. This includes the initialization of + * clocking using the settings in board.h. This function also performs + * other low-level chip as necessary. + * + *****************************************************************************/ + +void lpc54_clockconfig(FAR const struct pll_setup_s *pllsetup); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRCLPC54628_LPC54_CLOCKCONFIG_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_clrpend.c b/arch/arm/src/lpc54xx/lpc54_clrpend.c new file mode 100644 index 0000000000000000000000000000000000000000..a0cc93a6008b50d32f90726ca14e66dc9fbda029 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_clrpend.c @@ -0,0 +1,82 @@ +/**************************************************************************** + * arch/arm/src/lpc54/lpc54_clrpend.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "nvic.h" +#include "up_arch.h" + +#include "lpc54_irq.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_clrpend + * + * Description: + * Clear a pending interrupt at the NVIC. This does not seem to be required + * for most interrupts. Don't know why... but the LPC54xx Ethernet EMAC + * interrupt definitely needs it! + * + * This function is logically a part of lpc54_irq.c, but I will keep it in + * a separate file so that it will not increase the footprint on LPC54xx + * platforms that do not need this function. + * + ****************************************************************************/ + +void lpc54_clrpend(int irq) +{ + /* Check for external interrupt */ + + if (irq >= LPC54_IRQ_EXTINT) + { + if (irq < (LPC54_IRQ_EXTINT + 32)) + { + putreg32(1 << (irq - LPC54_IRQ_EXTINT), NVIC_IRQ0_31_CLRPEND); + } + else if (irq < LPC54_IRQ_NIRQS) + { + putreg32(1 << (irq - LPC54_IRQ_EXTINT - 32), NVIC_IRQ32_63_CLRPEND); + } + } +} diff --git a/arch/arm/src/lpc54xx/lpc54_config.h b/arch/arm/src/lpc54xx/lpc54_config.h new file mode 100644 index 0000000000000000000000000000000000000000..2d394d0a03388b01b521eb4c25dc98d0fa78a9ca --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_config.h @@ -0,0 +1,412 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/lpc54_config.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_CONFIG_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_CONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration *********************************************************************/ +/* Make sure that no unsupported USART, I2C master, or SPI masgter peripherals are + * enabled. + */ + +#ifndef CONFIG_LPC54_FLEXCOMM0 +# undef CONFIG_LPC54_I2C0_MASTER +# undef CONFIG_LPC54_SPI0_MASTER +# undef CONFIG_LPC54_USART0 +#endif +#ifndef CONFIG_LPC54_FLEXCOMM1 +# undef CONFIG_LPC54_I2C1_MASTER +# undef CONFIG_LPC54_SPI1_MASTER +# undef CONFIG_LPC54_USART1 +#endif +#ifndef CONFIG_LPC54_FLEXCOMM2 +# undef CONFIG_LPC54_I2C2_MASTER +# undef CONFIG_LPC54_SPI2_MASTER +# undef CONFIG_LPC54_USART2 +#endif +#ifndef CONFIG_LPC54_FLEXCOMM3 +# undef CONFIG_LPC54_I2C3_MASTER +# undef CONFIG_LPC54_SPI3_MASTER +# undef CONFIG_LPC54_USART3 +#endif +#ifndef CONFIG_LPC54_FLEXCOMM4 +# undef CONFIG_LPC54_I2C4_MASTER +# undef CONFIG_LPC54_SPI4_MASTER +# undef CONFIG_LPC54_USART4 +#endif +#ifndef CONFIG_LPC54_FLEXCOMM5 +# undef CONFIG_LPC54_I2C5_MASTER +# undef CONFIG_LPC54_SPI5_MASTER +# undef CONFIG_LPC54_USART5 +#endif +#ifndef CONFIG_LPC54_FLEXCOMM6 +# undef CONFIG_LPC54_I2C6_MASTER +# undef CONFIG_LPC54_SPI6_MASTER +# undef CONFIG_LPC54_USART6 +#endif +#ifndef CONFIG_LPC54_FLEXCOMM7 +# undef CONFIG_LPC54_I2C7_MASTER +# undef CONFIG_LPC54_SPI7_MASTER +# undef CONFIG_LPC54_USART7 +#endif +#ifndef CONFIG_LPC54_FLEXCOMM8 +# undef CONFIG_LPC54_I2C8_MASTER +# undef CONFIG_LPC54_SPI8_MASTER +# undef CONFIG_LPC54_USART8 +#endif +#ifndef CONFIG_LPC54_FLEXCOMM9 +# undef CONFIG_LPC54_I2C9_MASTER +# undef CONFIG_LPC54_SPI9_MASTER +# undef CONFIG_LPC54_USART9 +#endif + +#ifdef CONFIG_LPC54_I2C0_MASTER +# undef CONFIG_LPC54_SPI0_MASTER +# undef CONFIG_LPC54_USART0 +#endif +#ifdef CONFIG_LPC54_I2C1_MASTER +# undef CONFIG_LPC54_SPI1_MASTER +# undef CONFIG_LPC54_USART1 +#endif +#ifdef CONFIG_LPC54_I2C2_MASTER +# undef CONFIG_LPC54_SPI2_MASTER +# undef CONFIG_LPC54_USART2 +#endif +#ifdef CONFIG_LPC54_I2C3_MASTER +# undef CONFIG_LPC54_SPI3_MASTER +# undef CONFIG_LPC54_USART3 +#endif +#ifdef CONFIG_LPC54_I2C4_MASTER +# undef CONFIG_LPC54_SPI4_MASTER +# undef CONFIG_LPC54_USART4 +#endif +#ifdef CONFIG_LPC54_I2C5_MASTER +# undef CONFIG_LPC54_SPI5_MASTER +# undef CONFIG_LPC54_USART5 +#endif +#ifdef CONFIG_LPC54_I2C6_MASTER +# undef CONFIG_LPC54_SPI6_MASTER +# undef CONFIG_LPC54_USART6 +#endif +#ifdef CONFIG_LPC54_I2C7_MASTER +# undef CONFIG_LPC54_SPI7_MASTER +# undef CONFIG_LPC54_USART7 +#endif +#ifdef CONFIG_LPC54_I2C8_MASTER +# undef CONFIG_LPC54_SPI8_MASTER +# undef CONFIG_LPC54_USART8 +#endif +#ifdef CONFIG_LPC54_I2C9_MASTER +# undef CONFIG_LPC54_SPI9_MASTER +# undef CONFIG_LPC54_USART9 +#endif + +#ifdef CONFIG_LPC54_SPI0_MASTER +# undef CONFIG_LPC54_USART0 +#endif +#ifdef CONFIG_LPC54_SPI1_MASTER +# undef CONFIG_LPC54_USART1 +#endif +#ifdef CONFIG_LPC54_SPI2_MASTER +# undef CONFIG_LPC54_USART2 +#endif +#ifdef CONFIG_LPC54_SPI3_MASTER +# undef CONFIG_LPC54_USART3 +#endif +#ifdef CONFIG_LPC54_SPI4_MASTER +# undef CONFIG_LPC54_USART4 +#endif +#ifdef CONFIG_LPC54_SPI5_MASTER +# undef CONFIG_LPC54_USART5 +#endif +#ifdef CONFIG_LPC54_SPI6_MASTER +# undef CONFIG_LPC54_USART6 +#endif +#ifdef CONFIG_LPC54_SPI7_MASTER +# undef CONFIG_LPC54_USART7 +#endif +#ifdef CONFIG_LPC54_SPI8_MASTER +# undef CONFIG_LPC54_USART8 +#endif +#ifdef CONFIG_LPC54_SPI9_MASTER +# undef CONFIG_LPC54_USART9 +#endif + +/* Check if we have an I2C device */ + + +#undef CONFIG_LPC54_HAVE_I2C_MASTER +#undef HAVE_I2C_MASTER_DEVICE + +#if defined(CONFIG_LPC54_I2C0_MASTER) || defined(CONFIG_LPC54_I2C1_MASTER) || \ + defined(CONFIG_LPC54_I2C2_MASTER) || defined(CONFIG_LPC54_I2C3_MASTER) || \ + defined(CONFIG_LPC54_I2C4_MASTER) || defined(CONFIG_LPC54_I2C5_MASTER) || \ + defined(CONFIG_LPC54_I2C6_MASTER) || defined(CONFIG_LPC54_I2C7_MASTER) || \ + defined(CONFIG_LPC54_I2C8_MASTER) || defined(CONFIG_LPC54_I2C9_MASTER) +# define HAVE_I2C_MASTER_DEVICE 1 +#endif + +/* Check if we have an SPI device */ + +#undef CONFIG_LPC54_HAVE_SPI_MASTER +#undef HAVE_SP_MASTERI_DEVICE + +#if defined(CONFIG_LPC54_SPI0_MASTER) || defined(CONFIG_LPC54_SPI1_MASTER) || \ + defined(CONFIG_LPC54_SPI2_MASTER) || defined(CONFIG_LPC54_SPI3_MASTER) || \ + defined(CONFIG_LPC54_SPI4_MASTER) || defined(CONFIG_LPC54_SPI5_MASTER) || \ + defined(CONFIG_LPC54_SPI6_MASTER) || defined(CONFIG_LPC54_SPI7_MASTER) || \ + defined(CONFIG_LPC54_SPI8_MASTER) || defined(CONFIG_LPC54_SPI9_MASTER) +# define HAVE_SPI_MASTER_DEVICE 1 +#endif + +/* Map logical USART names (Just for simplicity of naming) */ + +#undef HAVE_USART0 +#undef HAVE_USART1 +#undef HAVE_USART2 +#undef HAVE_USART3 +#undef HAVE_USART4 +#undef HAVE_USART5 +#undef HAVE_USART6 +#undef HAVE_USART7 +#undef HAVE_USART8 +#undef HAVE_USART9 + +#ifdef CONFIG_LPC54_USART0 +# define HAVE_USART0 1 +#endif +#ifdef CONFIG_LPC54_USART1 +# define HAVE_USART1 1 +#endif +#ifdef CONFIG_LPC54_USART2 +# define HAVE_USART2 1 +#endif +#ifdef CONFIG_LPC54_USART3 +# define HAVE_USART3 1 +#endif +#ifdef CONFIG_LPC54_USART4 +# define HAVE_USART4 1 +#endif +#ifdef CONFIG_LPC54_USART5 +# define HAVE_USART5 1 +#endif +#ifdef CONFIG_LPC54_USART6 +# define HAVE_USART6 1 +#endif +#ifdef CONFIG_LPC54_USART7 +# define HAVE_USART7 1 +#endif +#ifdef CONFIG_LPC54_USART8 +# define HAVE_USART8 1 +#endif +#ifdef CONFIG_LPC54_USART9 +# define HAVE_USART9 1 +#endif + +/* Check if we have a USART device */ + +#undef CONFIG_LPC54_HAVE_USART +#undef HAVE_USART_DEVICE + +#if defined(HAVE_USART0) || defined(HAVE_USART1) || defined(HAVE_USART2) || \ + defined(HAVE_USART3) || defined(HAVE_USART4) || defined(HAVE_USART5) || \ + defined(HAVE_USART6) || defined(HAVE_USART7) || defined(HAVE_USART8) || \ + defined(HAVE_USART9) +# define HAVE_USART_DEVICE 1 +#endif + +/* Is there a serial console? There should be at most one defined. It could be on + * any USARTn, n=0,1,2,3,4,5 + */ + +#undef HAVE_USART_CONSOLE + +#if defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(HAVE_USART0) +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# undef CONFIG_USART9_SERIAL_CONSOLE +# define HAVE_USART_CONSOLE 1 +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(HAVE_USART1) +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# undef CONFIG_USART9_SERIAL_CONSOLE +# define HAVE_USART_CONSOLE 1 +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(HAVE_USART2) +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# undef CONFIG_USART9_SERIAL_CONSOLE +# define HAVE_USART_CONSOLE 1 +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(HAVE_USART3) +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# undef CONFIG_USART9_SERIAL_CONSOLE +# define HAVE_USART_CONSOLE 1 +#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(HAVE_USART4) +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# undef CONFIG_USART9_SERIAL_CONSOLE +# define HAVE_USART_CONSOLE 1 +#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(HAVE_USART5) +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# undef CONFIG_USART9_SERIAL_CONSOLE +# define HAVE_USART_CONSOLE 1 +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(HAVE_USART6) +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# undef CONFIG_USART9_SERIAL_CONSOLE +# define HAVE_USART_CONSOLE 1 +#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(HAVE_USART7) +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# undef CONFIG_USART9_SERIAL_CONSOLE +# define HAVE_USART_CONSOLE 1 +#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(HAVE_USART8) +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# undef CONFIG_USART9_SERIAL_CONSOLE +# define HAVE_USART_CONSOLE 1 +#elif defined(CONFIG_USART9_SERIAL_CONSOLE) && defined(HAVE_USART9) +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# define HAVE_USART_CONSOLE 1 +#else +# ifdef CONFIG_DEV_CONSOLE +# warning "No valid CONFIG_[LP]USART[n]_SERIAL_CONSOLE Setting" +# endif +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef CONFIG_USART4_SERIAL_CONSOLE +# undef CONFIG_USART5_SERIAL_CONSOLE +# undef CONFIG_USART6_SERIAL_CONSOLE +# undef CONFIG_USART7_SERIAL_CONSOLE +# undef CONFIG_USART8_SERIAL_CONSOLE +# undef CONFIG_USART9_SERIAL_CONSOLE +#endif + +/* Check USART flow control (Not yet supported) */ + +# undef CONFIG_USART0_FLOWCONTROL +# undef CONFIG_USART1_FLOWCONTROL +# undef CONFIG_USART2_FLOWCONTROL +# undef CONFIG_USART3_FLOWCONTROL +# undef CONFIG_USART4_FLOWCONTROL +# undef CONFIG_USART5_FLOWCONTROL +# undef CONFIG_USART6_FLOWCONTROL +# undef CONFIG_USART7_FLOWCONTROL +# undef CONFIG_USART8_FLOWCONTROL +# undef CONFIG_USART9_FLOWCONTROL + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_CONFIG_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_dma.c b/arch/arm/src/lpc54xx/lpc54_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..9a7e93e74602e53111f838cd6fe3133a556904b3 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_dma.c @@ -0,0 +1,636 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_dma.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip/lpc54_inputmux.h" +#include "chip/lpc54_dma.h" +#include "lpc54_enableclk.h" +#include "lpc54_reset.h" +#include "lpc54_dma.h" + +#ifdef CONFIG_LPC54_DMA + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure represents the state of one DMA channel */ + +struct lpc54_dmach_s +{ + bool inuse; /* True: The channel is in use */ + dma_callback_t callback; /* DMA completion callback function */ + void *arg; /* Argument to pass to the callback function */ +}; + +/* This structure represents the state of the LPC54 DMA block */ + +struct lpc54_dma_s +{ + sem_t exclsem; /* For exclusive access to the DMA channel list */ + + /* This is the state of each DMA channel */ + + struct lpc54_dmach_s dmach[LPC54_DMA_NCHANNELS]; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The state of the LPC54 DMA block */ + +static struct lpc54_dma_s g_dma; + +/* The SRAMBASE register must be configured with an address (preferably in + * on-chip SRAM) where DMA descriptors will be stored. Each DMA channel has + * an entry for the channel descriptor in the SRAM table. + */ + +static struct lpc54_dmachan_desc_s g_dma_desc[LPC54_DMA_NCHANNELS]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_dma_dispatch + * + * Description: + * Dispatch a DMA interrupt. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_dma_dispatch(int ch, int result) +{ + struct lpc54_dmach_s *dmach; + + /* Yes.. Is this channel assigned? Is there a callback function? */ + + dmach = &g_dma.dmach[ch]; + if (dmach->inuse && dmach->callback != NULL) + { + /* Perform the callback */ + + dmach->callback(ch, dmach->arg, result); + } + + /* Disable this channel, mask any further interrupts for this channel, and + * clear any pending interrupts. + */ + + lpc54_dmastop(ch); +} + +/**************************************************************************** + * Name: lpc54_dma_interrupt + * + * Description: + * The common DMA interrupt handler. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int lpc54_dma_interrupt(int irq, FAR void *context, FAR void *arg) +{ + uint32_t pending; + uint32_t bitmask; + int ch; + + /* Check for pending DMA channel error interrupts */ + + pending = getreg32(LPC54_DMA_ERRINT0); + putreg32(pending, LPC54_DMA_ERRINT0); + + for (ch = 0; pending != 0 && ch < LPC54_DMA_NCHANNELS; ch++) + { + /* Check if there is a pending error on this channel */ + + bitmask = DMA_CHANNEL((uint32_t)ch); + if ((pending & bitmask) != 0) + { + /* Dispatch the DMA channel error event */ + + lpc54_dma_dispatch(ch, -EIO); + pending &= ~bitmask; + } + } + + /* Check for pending DMA interrupt A events */ + + pending = getreg32(LPC54_DMA_INTA0); + putreg32(pending, LPC54_DMA_INTA0); + + for (ch = 0; pending != 0 && ch < LPC54_DMA_NCHANNELS; ch++) + { + /* Check if there is a pending interrupt A on this channel */ + + bitmask = DMA_CHANNEL((uint32_t)ch); + if ((pending & bitmask) != 0) + { + /* Dispatch DMA channel interrupt A event */ + + lpc54_dma_dispatch(ch, OK); + pending &= ~bitmask; + } + } + +#if 0 /* interrupt B is not used */ + /* Check for pending DMA interrupt B events */ + + pending = getreg32(LPC54_DMA_INTB0); + putreg32(pending, LPC54_DMA_INTB0); + + for (ch = 0; pending != 0 && ch < LPC54_DMA_NCHANNELS; ch++) + { + /* Check if there is a pending interrupt A on this channel */ + + bitmask = DMA_CHANNEL((uint32_t)ch); + if ((pending & bitmask) != 0) + { + /* Dispatch DMA channel interrupt B event */ + + lpc54_dma_dispatch(ch, OK); + pending &= ~bitmask; + } + } +#endif + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_dmainitialize + * + * Description: + * Initialize the DMA subsystem. Called from up_initialize() early in the + * boot-up sequence. Prototyped in up_internal.h. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void weak_function up_dmainitialize(void) +{ + int ret; + + /* Enable clocking to the DMA block */ + + lpc54_dma_enableclk(); + + /* Reset the DMA peripheral */ + + lpc54_reset_dma(); + + /* Disable and clear all DMA interrupts */ + + putreg32(DMA_ALL_CHANNELS, LPC54_DMA_INTENCLR0); + putreg32(DMA_ALL_CHANNELS, LPC54_DMA_ERRINT0); + putreg32(DMA_ALL_CHANNELS, LPC54_DMA_INTA0); + putreg32(DMA_ALL_CHANNELS, LPC54_DMA_INTB0); + + /* Initialize the DMA state structure */ + + nxsem_init(&g_dma.exclsem, 0, 1); + + /* Set the SRAMBASE to the beginning a array of DMA descriptors, one for + * each DMA channel. + */ + + putreg32((uint32_t)g_dma_desc, LPC54_DMA_SRAMBASE); + + /* Attach and enable the DMA interrupt handler */ + + ret = irq_attach(LPC54_IRQ_DMA, lpc54_dma_interrupt, NULL); + if (ret == OK) + { + up_enable_irq(LPC54_IRQ_DMA); + } + + /* Enable the DMA controller */ + + putreg32(DMA_CTRL_ENABLE, LPC54_DMA_CTRL); +} + +/**************************************************************************** + * Name: lpc54_dma_setup + * + * Description: + * Configure DMA for one transfer. + * + * Input Parameters: + * ch - DMA channel number + * cfg - The content of the DMA channel configuration register. See + * peripheral channel definitions in chip/lpc54_dma.h. The + * caller must provide all fields: PERIPHREQEN, TRIGPOL, + * TRIGTYPE, TRIGBURST, BURSTPOWER, SRCBURSTWRAP, DSTBURSTWRAP, + * and CHPRIORITY. + * xfrcfg - The content of the DMA channel configuration register. See + * peripheral channel definitions in chip/lpc54_dma.h. The + * caller must provide all fields: WIDTH, SRCINC, and DSTINC.\ + * All of fields are managed by the DMA driver + * trigsrc - See input mux DMA trigger ITRIG_INMUX_* definitions in + * chip/lpc54_inputmux.h. + * srcaddr - Source address of the DMA transfer + * dstaddr - Destination address of the DMA transfer + * nbytes - Number of bytes to transfer + * + ****************************************************************************/ + +int lpc54_dma_setup(int ch, uint32_t cfg, uint32_t xfrcfg, uint8_t trigsrc, + uintptr_t srcaddr, uintptr_t dstaddr, size_t nbytes) +{ + struct lpc54_dmach_s *dmach; + uintptr_t base; + uintptr_t regaddr; + uint32_t nxfrs; + uint32_t width; + uint32_t incr; + int ret; + + DEBUGASSERT((unsigned)ch < LPC54_DMA_NCHANNELS && nbytes < 4096); + dmach = &g_dma.dmach[ch]; + + /* Get exclusive access to the DMA data structures and interface */ + + ret = nxsem_wait(&g_dma.exclsem); + if (ret < 0) + { + return ret; + } + + /* Make sure that the DMA channel is not in use */ + + DEBUGASSERT(!dmach->inuse); + if (dmach->inuse) + { + ret = -EBUSY; + goto errout_with_exclsem; + } + + dmach->inuse = true; + + /* Make sure that the trigger is not active */ + + base = LPC54_DMA_CHAN_BASE(ch); + putreg32(0, base + LPC54_DMA_CFG_OFFSET); + + /* Number of transfers */ + + switch (xfrcfg & DMA_XFERCFG_WIDTH_MASK) + { + default: + case DMA_XFERCFG_WIDTH_8BIT: + width = 1; + nxfrs = nbytes; + break; + + case DMA_XFERCFG_WIDTH_16BIT: + width = 2; + nxfrs = ((nbytes + 1) >> 1); + break; + + case DMA_XFERCFG_WIDTH_32BIT: + width = 4; + nxfrs = ((nbytes + 3) >> 2); + break; + } + + /* Check if the number of transfers can be performed */ + + if (nxfrs > LPC54_DMA_MAXXFRS) + { + return -E2BIG; + } + + /* Set up the channel DMA descriptor */ + + g_dma_desc[ch].reserved = 0; + + switch (cfg & DMA_XFERCFG_SRCINC_MASK) + { + default: + case DMA_XFERCFG_SRCINC_NONE: + incr = 0; + break; + + case DMA_XFERCFG_SRCINC_1X: + incr = width; + break; + + case DMA_XFERCFG_SRCINC_2X: + incr = width << 1; + break; + + case DMA_XFERCFG_SRCINC_4X: + incr = width << 2; + incr = 0; + break; + } + + g_dma_desc[ch].srcend = (uint32_t)srcaddr + nxfrs * incr; + + switch (cfg & DMA_XFERCFG_DSTINC_MASK) + { + default: + case DMA_XFERCFG_DSTINC_NONE: + incr = 0; + break; + + case DMA_XFERCFG_DSTINC_1X: + incr = width; + break; + + case DMA_XFERCFG_DSTINC_2X: + incr = width << 1; + break; + + case DMA_XFERCFG_DSTINC_4X: + incr = width << 2; + incr = 0; + break; + } + + g_dma_desc[ch].dstend = (uint32_t)dstaddr + nxfrs * incr; + g_dma_desc[ch].link = 0; + + /* Set the trigger source */ + + regaddr = LPC54_MUX_DMA_ITRIG_INMUX(ch); + putreg32(MUX_DMA_ITRIG_INMUX(trigsrc), regaddr); + + /* Set the channel configuration register. + * + * PERIPHREQEN - Provided by caller + * TRIGPOL - Provided by caller + * TRIGTYPE - Provided by caller + * TRIGBURST - Provided by caller + * BURSTPOWER - Provided by caller + * SRCBURSTWRAP - Provided by caller + * DSTBURSTWRAP - Provided by caller + * CHPRIORITY - Provided by caller + */ + + putreg32(cfg, base + LPC54_DMA_CFG_OFFSET); + + /* Set the channel transfer configuration register + * + * CFGVALID - Current channel descriptor is valid. + * RELOAD - No reload + * SWTRIG - No software trigger + * CLRTRIG - Trigger cleared when descriptor is exhausted + * SETINTA - Use interrupt A + * SETINTB - Don't use interrupt B + * WIDTH - Provided by caller + * SRCINC - Provided by caller + * DSTINC - Provided by caller + * XFERCOUNT - Derived from with and nbytes + */ + + xfrcfg &= ~(DMA_XFERCFG_RELOAD | DMA_XFERCFG_SWTRIG | DMA_XFERCFG_SETINTB | + DMA_XFERCFG_XFERCOUNT_MASK); + xfrcfg |= (DMA_XFERCFG_CFGVALID | DMA_XFERCFG_CLRTRIG | DMA_XFERCFG_SETINTA); + xfrcfg |= DMA_XFERCFG_XFERCOUNT(nxfrs); + putreg32(xfrcfg, base + LPC54_DMA_XFERCFG_OFFSET); + ret = OK; + +errout_with_exclsem: + nxsem_post(&g_dma.exclsem); + return ret; +} + +/**************************************************************************** + * Name: lpc54_dmastart + * + * Description: + * Start the DMA transfer + * + ****************************************************************************/ + +int lpc54_dmastart(int ch, dma_callback_t callback, void *arg) +{ + struct lpc54_dmach_s *dmach; + uintptr_t regaddr; + uint32_t bitmask; + + DEBUGASSERT((unsigned)ch < LPC54_DMA_NCHANNELS); + dmach = &g_dma.dmach[ch]; + DEBUGASSERT(dmach->inuse && callback != NULL); + + /* Save the callback information */ + + dmach->callback = callback; + dmach->arg = arg; + + /* Clear any pending DMA interrupts */ + + bitmask = DMA_CHANNEL(ch); + putreg32(bitmask, LPC54_DMA_ERRINT0); + putreg32(bitmask, LPC54_DMA_INTA0); + putreg32(bitmask, LPC54_DMA_INTB0); + + /* Enable the channel and enable interrupt A and error interrupts. */ + + putreg32(bitmask, LPC54_DMA_ENABLESET0); /* Enable the channel */ + putreg32(bitmask, LPC54_DMA_INTENSET0); /* Enable channel interrupts */ + + /* Enable the trigger for this channel */ + + regaddr = LPC54_DMA_CTLSTAT(ch); + modifyreg32(regaddr, 0, DMA_CTLSTAT_TRIG); + return OK; +} + +/**************************************************************************** + * Name: lpc54_dmastop + * + * Description: + * Cancel the DMA. After lpc54_dmastop() is called, the DMA channel is + * reset and lpc54_dmasetup() must be called before lpc54_dmastart() can be + * called again + * + * This function will be called either by the user directly, by the user + * indirectly via lpc54_dmafree(), or from lpc54_dma_interrupt when the + * transfer completes. + * + ****************************************************************************/ + +void lpc54_dmastop(int ch) +{ + struct lpc54_dmach_s *dmach; + uint32_t bitmask; + + DEBUGASSERT((unsigned)ch < LPC54_DMA_NCHANNELS); + dmach = &g_dma.dmach[ch]; + DEBUGASSERT(dmach->inuse); + + /* Disable this channel and mask any further interrupts from the channel. + * this channel. + */ + + bitmask = DMA_CHANNEL(ch); + putreg32(bitmask, LPC54_DMA_INTENCLR0); /* Disable channel interrupts */ + putreg32(bitmask, LPC54_DMA_ENABLECLR0); /* Disable the channel */ + + /* Clear any pending interrupts for this channel */ + + putreg32(bitmask, LPC54_DMA_ERRINT0); + putreg32(bitmask, LPC54_DMA_INTA0); + putreg32(bitmask, LPC54_DMA_INTB0); + + /* This channel is no longer in use */ + + g_dma.dmach[ch].inuse = false; +} + +/**************************************************************************** + * Name: lpc54_dmasample + * + * Description: + * Sample DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void lpc54_dmasample(int ch, struct lpc54_dmaregs_s *regs) +{ + uintptr_t base; + + DEBUGASSERT((unsigned)ch < LPC54_DMA_NCHANNELS); + + /* Sample the global DMA registers */ + + regs->gbl.ctrl = getreg32(LPC54_DMA_CTRL); + regs->gbl.intstat = getreg32(LPC54_DMA_INTSTAT); + regs->gbl.srambase = getreg32(LPC54_DMA_SRAMBASE); + regs->gbl.enableset0 = getreg32(LPC54_DMA_ENABLESET0); + regs->gbl.active0 = getreg32(LPC54_DMA_ACTIVE0); + regs->gbl.busy0 = getreg32(LPC54_DMA_BUSY0); + regs->gbl.errint0 = getreg32(LPC54_DMA_ERRINT0); + regs->gbl.intenset0 = getreg32(LPC54_DMA_INTENSET0); + regs->gbl.inta0 = getreg32(LPC54_DMA_INTA0); + regs->gbl.intb0 = getreg32(LPC54_DMA_INTB0); + + /* Sample the DMA channel registers */ + + base = LPC54_DMA_CHAN_BASE(ch); + regs->ch.cfg = getreg32(base + LPC54_DMA_CFG_OFFSET); + regs->ch.ctlstat = getreg32(base + LPC54_DMA_CTLSTAT_OFFSET); + regs->ch.xfercfg = getreg32(base + LPC54_DMA_XFERCFG_OFFSET); +} +#endif /* CONFIG_DEBUG_DMA */ + +/**************************************************************************** + * Name: lpc54_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void lpc54_dmadump(int ch, const struct lpc54_dmaregs_s *regs, + const char *msg) +{ + uintptr_t base; + + DEBUGASSERT((unsigned)ch < LPC54_DMA_NCHANNELS && regs != NULL && msg != NULL); + + /* Dump the sampled global DMA registers */ + + dmainfo("Global DMA Registers: %s\n", msg); + dmainfo(" CTRL[%08x]: %08lx\n", + LPC54_DMA_CTRL, (unsigned long)regs->gbl.ctrl); + dmainfo(" INTSTAT[%08x]: %08lx\n", + LPC54_DMA_INTSTAT, (unsigned long)regs->gbl.intstat); + dmainfo(" SRAMBASE[%08x]: %08lx\n", + LPC54_DMA_SRAMBASE, (unsigned long)regs->gbl.srambase); + dmainfo(" ENABLESET0[%08x]: %08lx\n", + LPC54_DMA_ENABLESET0, (unsigned long)regs->gbl.enableset0); + dmainfo(" ACTIVE0[%08x]: %08lx\n", + LPC54_DMA_ACTIVE0, (unsigned long)regs->gbl.active0); + dmainfo(" BUSY0[%08x]: %08lx\n", + LPC54_DMA_BUSY0, (unsigned long)regs->gbl.busy0); + dmainfo(" ERRINT0[%08x]: %08lx\n", + LPC54_DMA_ERRINT0, (unsigned long)regs->gbl.errint0); + dmainfo(" INTENSET0[%08x]: %08lx\n", + LPC54_DMA_INTENSET0, (unsigned long)regs->gbl.intenset0); + dmainfo(" INTA0[%08x]: %08lx\n", + LPC54_DMA_INTA0, (unsigned long)regs->gbl.inta0); + dmainfo(" INTB0[%08x]: %08lx\n", + LPC54_DMA_INTB0, (unsigned long)regs->gbl.intb0); + + /* Dump the DMA channel registers */ + + base = LPC54_DMA_CHAN_BASE(ch); + + dmainfo("Channel DMA Registers: %d\n", ch); + + dmainfo(" CFG[%08x]: %08lx\n", + base + LPC54_DMA_CFG_OFFSET, (unsigned long)regs->ch.cfg); + dmainfo(" CTLSTAT[%08x]: %08lx\n", + base + LPC54_DMA_CTLSTAT_OFFSET, (unsigned long)regs->ch.ctlstat); + dmainfo(" XFERCFG[%08x]: %08lx\n", + base + LPC54_DMA_XFERCFG_OFFSET, (unsigned long)regs->ch.xfercfg); +} +#endif /* CONFIG_DEBUG_DMA */ + +#endif /* CONFIG_LPC54_DMA */ diff --git a/arch/arm/src/lpc54xx/lpc54_dma.h b/arch/arm/src/lpc54xx/lpc54_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..36f938069df790d2f70270c1aed7e7e0f510f55b --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_dma.h @@ -0,0 +1,203 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_dma.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LP54_DMA_H +#define __ARCH_ARM_SRC_LPC54XX_LP54_DMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip/lpc54_dma.h" + +#ifdef CONFIG_LPC54_DMA + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +typedef void (*dma_callback_t)(int ch, void *arg, int result); + +/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ + +#ifdef CONFIG_DEBUG_DMA +struct lpc54_dmaglobalregs_s +{ + /* Global Registers */ + + uint32_t ctrl; /* DMA control */ + uint32_t intstat; /* DMA Interrupt status */ + uint32_t srambase; /* SRAM address of the channel configuration table */ + uint32_t enableset0; /* DMA Channel enable read and set */ + uint32_t active0; /* DMA Channel active status */ + uint32_t busy0; /* DMA Channel busy status */ + uint32_t errint0; /* DMA Error interrupt status */ + uint32_t intenset0; /* DMA Interrupt enable read and set */ + uint32_t inta0; /* DMA Interrupt A status */ + uint32_t intb0; /* DMA Interrupt B status */ +}; + +struct lpc54_dmachanregs_s +{ + /* Channel Registers */ + + uint32_t cfg; /* DMA Configuration register */ + uint32_t ctlstat; /* DMA Control and status register */ + uint32_t xfercfg; /* DMA Transfer configuration register */ +}; + +struct lpc54_dmaregs_s +{ + /* Global Registers */ + + struct lpc54_dmaglobalregs_s gbl; + + /* Channel Registers */ + + struct lpc54_dmachanregs_s ch; +}; +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_dma_setup + * + * Description: + * Configure DMA for one transfer. + * + * Input Parameters: + * ch - DMA channel number + * cfg - The content of the DMA channel configuration register. See + * peripheral channel definitions in chip/lpc54_dma.h. The + * caller must provide all fields: PERIPHREQEN, TRIGPOL, + * TRIGTYPE, TRIGBURST, BURSTPOWER, SRCBURSTWRAP, DSTBURSTWRAP, + * and CHPRIORITY. + * xfrcfg - The content of the DMA channel configuration register. See + * peripheral channel definitions in chip/lpc54_dma.h. The + * caller must provide all fields: WIDTH, SRCINC, and DSTINC.\ + * All of fields are managed by the DMA driver + * trigsrc - See input mux DMA trigger ITRIG_INMUX_* definitions in + * chip/lpc54_inputmux.h. + * srcaddr - Source address of the DMA transfer + * dstaddr - Destination address of the DMA transfer + * nbytes - Number of bytes to transfer + * + ****************************************************************************/ + +int lpc54_dma_setup(int ch, uint32_t cfg, uint32_t xfrcfg, uint8_t trigsrc, + uintptr_t srcaddr, uintptr_t dstaddr, size_t nbytes); + +/**************************************************************************** + * Name: lpc54_dmastart + * + * Description: + * Start the DMA transfer + * + ****************************************************************************/ + +int lpc54_dmastart(int ch, dma_callback_t callback, void *arg); + +/**************************************************************************** + * Name: lpc54_dmastop + * + * Description: + * Cancel the DMA. After lpc54_dmastop() is called, the DMA channel is + * reset and lpc54_dmasetup() must be called before lpc54_dmastart() can be + * called again + * + ****************************************************************************/ + +void lpc54_dmastop(int ch); + +/**************************************************************************** + * Name: lpc54_dmasample + * + * Description: + * Sample DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void lpc54_dmasample(int ch, struct lpc54_dmaregs_s *regs); +#else +# define lpc54_dmasample(handle,regs) +#endif + +/**************************************************************************** + * Name: lpc54_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void lpc54_dmadump(int ch, const struct lpc54_dmaregs_s *regs, + const char *msg); +#else +# define lpc54_dmadump(handle,regs,msg) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_LPC54_DMA */ +#endif /* __ARCH_ARM_SRC_LPC54XX_LP54_DMA_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_emc.c b/arch/arm/src/lpc54xx/lpc54_emc.c new file mode 100644 index 0000000000000000000000000000000000000000..1c570a8f2eb050033f439cb87c471ea7fd09d428 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_emc.c @@ -0,0 +1,542 @@ +/**************************************************************************** + * arch/arm/src/lpc54/lpc54_clrpend.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Parts of this file were adapted from sample code provided for the LPC54xx + * family from NXP which has a compatible BSD license. + * + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016 - 2017 , NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "up_arch.h" + +#include "chip/lpc54_syscon.h" +#include "chip/lpc54_emc.h" +#include "lpc54_config.h" +#include "lpc54_enableclk.h" +#include "lpc54_reset.h" +#include "lpc54_emc.h" + +#ifdef CONFIG_LPC54_EMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define EMC_SDRAM_MODE_CL_SHIFT (4) +#define EMC_SDRAM_MODE_CL_MASK (7 << EMC_SDRAM_MODE_CL_SHIFT) + +#define EMC_DYNCTL_COLUMNBASE_SHIFT (0) +#define EMC_DYNCTL_COLUMNBASE_MASK (3 << EMC_DYNCTL_COLUMNBASE_SHIFT) +#define EMC_DYNCTL_COLUMNPLUS_SHIFT (3) +#define EMC_DYNCTL_COLUMNPLUS_MASK (3 << EMC_DYNCTL_COLUMNPLUS_SHIFT) +#define EMC_DYNCTL_BUSWIDTH_MASK (0x80) +#define EMC_DYNCTL_BUSADDRMAP_MASK (0x20) +#define EMC_DYNCTL_DEVBANKS_BITS_MASK (0x1c) + +#define EMC_SDRAM_BANKCS_BA0_MASK (uint32_t)(0x2000) +#define EMC_SDRAM_BANKCS_BA1_MASK (uint32_t)(0x4000) +#define EMC_SDRAM_BANKCS_BA_MASK (EMC_SDRAM_BANKCS_BA0_MASK | EMC_SDRAM_BANKCS_BA1_MASK) + +#define EMC_REFRESH_CLOCK_SCALE 16 + +#define EMC_SDRAM_WAIT_CYCLES 2000 +#define MHZ_PER_HZ 1000000 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uintptr_t g_dram_csbase[LPC54_EMC_NCS] = +{ + LPC54_DRAMCS0_BASE, LPC54_DRAMCS1_BASE, LPC54_DRAMCS2_BASE, + LPC54_DRAMCS3_BASE +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_emc_timercycles + * + * Description: + * Convert nanoseconds to EMC clock cycles and clip to the provided range. + * + * Input Parameters: + * nsec - Nanoseconds to be converted. + * lower - Lower valid limit + * upper - Upper valid limit + * + ****************************************************************************/ + +static uint32_t lpc54_emc_timercycles(uint32_t nsec, uint32_t lower, + uint32_t upper) +{ + uint32_t cycles; + + cycles = BOARD_EMC_FREQUENCY / MHZ_PER_HZ * nsec; + return ((cycles + MSEC_PER_SEC - 1) / MSEC_PER_SEC); + + /* Decrease according to the plus */ + + if (cycles < lower) + { + cycles = lower; + } + else if (cycles > upper) + { + cycles = upper; + } + + return cycles; +} + +/**************************************************************************** + * Name: lpc54_emc_timercycles + * + * Description: + * Get the shift value to shift the mode register content by. + * + * Input Parameters: + * addrmap - EMC address map for the dynamic memory configuration. This is + * bit 14 ~ bit 7 of the EMC_DYNCONFIG. + * + * Returned Value: + * The offset value to shift the mode register content by. + * + ****************************************************************************/ + +#ifdef CONFIG_LPC54_EMC_DYNAMIC +static uint32_t lpc54_emc_modeoffset(uint32_t addrmap) +{ + uint8_t offset = 0; + uint32_t columbase = addrmap & EMC_DYNCTL_COLUMNBASE_MASK; + + /* First calculate the column length. */ + + if (columbase == 0x10) + { + offset = 8; + } + else + { + if (!columbase) + { + offset = 9; + } + else + { + offset = 8; + } + + /* Add column length increase check. */ + + if (((addrmap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_SHIFT) == 1) + { + offset += 1; + } + else if (((addrmap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_SHIFT) == 2) + { + offset += 2; + } + else + { + /* To avoid MISRA rule 14.10 error. */ + } + } + + /* Add Buswidth/16. */ + + if (addrmap & EMC_DYNCTL_BUSWIDTH_MASK) + { + offset += 2; + } + else + { + offset += 1; + } + + /* Add bank select bit if the sdram address map mode is RBC(row-bank-column) mode. */ + + if (!(addrmap & EMC_DYNCTL_BUSADDRMAP_MASK)) + { + if (!(addrmap & EMC_DYNCTL_DEVBANKS_BITS_MASK)) + { + offset += 1; + } + else + { + offset += 2; + } + } + + return offset; +} +#endif /* CONFIG_LPC54_EMC_DYNAMIC */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_emc_initialize + * + * Description: + * This function enables the EMC clock, initializes the emc system + * configuration, and enable the EMC module. + * + * Input Parameters: + * config - Describes the EMC configuration. + * + ****************************************************************************/ + +void lpc54_emc_initialize(FAR const struct emc_config_s *config) +{ + uint32_t regval; + + /* Enable EMC clock */ + + lpc54_emc_enableclk(); + + /* Reset the EMC */ + + lpc54_reset_emc(); + + /* Set the EMC sytem configure */ + + putreg32(SYSCON_EMCCLKDIV_DIV(config->clkdiv), LPC54_SYSCON_EMCCLKDIV); + + regval = config->clksrc ? SYSCON_EMCSYSCTRL_FBCLKINSEL : 0; + putreg32(regval, LPC54_SYSCON_EMCSYSCTRL); + + /* Set the endian mode */ + + regval = config->bigendian ? EMC_CONFIG_EM : 0; + putreg32(regval, LPC54_EMC_CONFIG); + + /* Enable the EMC module with normal memory map mode and normal work mode. */ + + putreg32(EMC_CONTROL_E, LPC54_EMC_CONTROL); +} + +/**************************************************************************** + * Name: lpc54_emc_sdram_initialize + * + * Description: + * This function initializes the dynamic memory controller in external + * memory controller. This function must be called after lpc54_emc_initialize + * and before accessing the external dynamic memory. + * + * Input Parameters: + * timing - The timing and latency for dynamica memory controller + * setting. It will be used for all dynamic memory chips, + * therefore the worst timing value for all used chips must be + * given. + * chconfig - The EMC dynamic memory controller chip-independent + * configuration array. The dimension of the array is given by + * nchips. + * nchips - The number of chips to configure and the dimension of the + * chconfig array. + * + ****************************************************************************/ + +#ifdef CONFIG_LPC54_EMC_DYNAMIC +void lpc54_emc_sdram_initialize(FAR const struct emc_dynamic_timing_config_s *timing, + FAR const struct emc_dynamic_chip_config_s *chconfig, + unsigned int nchips) +{ + FAR const struct emc_dynamic_chip_config_s *config; + uintptr_t addr; + uint32_t regval; + uint32_t offset; + uint32_t data; + unsigned int i; + volatile unsigned int j; + + DEBUGASSERT(timing != NULL && chconfig != NULL && nchips > 0); + + /* Setting for dynamic memory controller chip independent configuration */ + + for (i = 0, config = chconfig; + i < nchips && config != NULL; + i++, config++) + { + uint8_t caslat; + + regval = EMC_DYNCONFIG_MD(config->dyndev) | + EMC_DYNCONFIG_ADDRMAP(config->addrmap); + putreg32(regval, LPC54_EMC_DYNCONFIG(config->chndx)); + + /* Abstract CAS latency from the SDRAM mode reigster setting values */ + + caslat = (config->mode & EMC_SDRAM_MODE_CL_MASK) >> EMC_SDRAM_MODE_CL_SHIFT; + regval = EMC_DYNRASCAS_RAS(config->rasnclk) | EMC_DYNRASCAS_CAS(caslat); + putreg32(regval, LPC54_EMC_DYNRASCAS(config->chndx)); + } + + /* Configure the Dynamic Memory controller timing/latency for all chips. */ + + regval = EMC_DYNREADCONFIG(timing->rdconfig); + putreg32(regval, LPC54_EMC_DYNREADCONFIG); + + regval = lpc54_emc_timercycles(timing->rp, 1, 16); + putreg32(EMC_DYNRP(regval), LPC54_EMC_DYNRP); + + regval = lpc54_emc_timercycles(timing->ras, 1, 16); + putreg32(EMC_DYNRAS(regval), LPC54_EMC_DYNRAS); + + regval = lpc54_emc_timercycles(timing->srex, 1, 16); + putreg32(EMC_DYNSREX(regval), LPC54_EMC_DYNSREX); + + regval = lpc54_emc_timercycles(timing->apr, 1, 16); + putreg32(EMC_DYNAPR(regval), LPC54_EMC_DYNAPR); + + regval = lpc54_emc_timercycles(timing->dal, 0, 15); + putreg32(EMC_DYNDAL(regval), LPC54_EMC_DYNDAL); + + regval = lpc54_emc_timercycles(timing->wr, 1, 16); + putreg32(EMC_DYNWR(regval), LPC54_EMC_DYNWR); + + regval = lpc54_emc_timercycles(timing->rc, 1, 32); + putreg32(EMC_DYNRC(regval), LPC54_EMC_DYNRC); + + regval = lpc54_emc_timercycles(timing->rfc, 1, 32); + putreg32(EMC_DYNRFC(regval), LPC54_EMC_DYNRFC); + + regval = lpc54_emc_timercycles(timing->xsr, 1, 32); + putreg32(EMC_DYNXSR(regval), LPC54_EMC_DYNXSR); + + regval = lpc54_emc_timercycles(timing->rrd, 1, 16); + putreg32(EMC_DYNRRD(regval), LPC54_EMC_DYNRRD); + + regval = EMC_DYNRRD(timing->mrd); + putreg32(regval, LPC54_EMC_DYNMRD); + + /* Initialize the SDRAM.*/ + + for (j = 0; j < EMC_SDRAM_WAIT_CYCLES; j++) + { + } + + /* Step 2. Issue NOP command. */ + + regval = EMC_DYNCONTROL_CE | EMC_DYNCONTROL_CS | EMC_DYNCONTROL_I_MODE; + putreg32(regval, LPC54_EMC_DYNCONTROL); + + for (j = 0; j < EMC_SDRAM_WAIT_CYCLES; j++) + { + } + + /* Step 3. Issue precharge all command. */ + + regval = EMC_DYNCONTROL_CE | EMC_DYNCONTROL_CS | EMC_DYNCONTROL_I_PALL; + putreg32(regval, LPC54_EMC_DYNCONTROL); + + /* Step 4. Issue two auto-refresh command. */ + + putreg32(2 * EMC_REFRESH_CLOCK_SCALE, LPC54_EMC_DYNREFRESH); + + for (i = 0; i < EMC_SDRAM_WAIT_CYCLES/2; i ++) + { + } + + regval = lpc54_emc_timercycles(timing->refresh, 0, + EMC_REFRESH_CLOCK_SCALE * 2047); + putreg32(regval / EMC_REFRESH_CLOCK_SCALE, LPC54_EMC_DYNREFRESH); + + /* Step 5. Issue a mode command and set the mode value. */ + + regval = EMC_DYNCONTROL_CE | EMC_DYNCONTROL_CS | EMC_DYNCONTROL_I_MODE; + putreg32(regval, LPC54_EMC_DYNCONTROL); + + /* Calculate the mode settings here and to reach the 8 auto-refresh time + * requirement. + */ + + for (i = 0, config = chconfig; + i < nchips && config != NULL; + i++, config++) + { + /* Get the shift value first. */ + + offset = lpc54_emc_modeoffset(config->addrmap); + addr = g_dram_csbase[config->chndx] | + ((uint32_t)(config->mode & ~EMC_SDRAM_BANKCS_BA_MASK ) << offset); + + /* Set the right mode setting value. */ + + data = *(volatile uint32_t *)addr; + data = data; + } + + if (config->dyndev) + { + /* Add extended mode register if the low-power sdram is used. */ + + regval = EMC_DYNCONTROL_CE | EMC_DYNCONTROL_CS | + EMC_DYNCONTROL_I_MODE; + putreg32(regval, LPC54_EMC_DYNCONTROL); + + /* Calculate the mode settings for extended mode register. */ + + for (i = 0, config = chconfig; + i < nchips && config != NULL; + i++, config++) + { + /* Get the shift value first. */ + + offset = lpc54_emc_modeoffset(config->addrmap); + addr = (g_dram_csbase[config->chndx] | + (((uint32_t)(config->extmode & ~EMC_SDRAM_BANKCS_BA_MASK) | + EMC_SDRAM_BANKCS_BA1_MASK) << offset)); + + /* Set the right mode setting value. */ + + data = *(volatile uint32_t *)addr; + data = data; + } + } + + /* Step 6. Issue normal operation command. */ + + regval = EMC_DYNCONTROL_I_NORMAL; + putreg32(regval, LPC54_EMC_DYNCONTROL); + + /* The buffer will be disabled when do the sdram initialization and + * enabled after the initialization during normal opeation. + */ + + for (i = 0, config = chconfig; + i < nchips && config != NULL; + i++, config++) + { + uintptr_t regaddr = LPC54_EMC_DYNCONFIG(config->chndx); + + regval = getreg32(regaddr); + regval |= EMC_DYNCONFIG_B; + putreg32(regval, regaddr); + } +} +#endif /* CONFIG_LPC54_EMC_DYNAMIC */ + +/**************************************************************************** + * Name: lpc54_emc_sram_initialize + * + * Description: + * This function initializes the static memory controller in external + * memory controller. This function must be called after lpc54_emc_initialize + * and before accessing the external dynamic memory. + * + * Input Parameters: + * extwait - The extended wait timeout or the read/write transfer time. + * This is common for all static memory chips and set with + * NULL if not required. + * statconfig - The EMC static memory controller chip independent + * configuration array. The dimension of the array is nchips. + * nchips - The total static memory chip numbers been used and the + * number of entries in the statconfig array. + * + ****************************************************************************/ + +#ifdef CONFIG_LPC54_EMC_STATIC +void lpc54_emc_sram_initialize(FAR uint32_t *extwait, + FAR const struct emc_static_chip_config_s *statconfig, + uint32_t nchips) +{ + FAR const struct emc_static_chip_config_s *config; + uint32_t regval; + unsigned int i; + + /* Initialize extended wait. */ + + DEBUGASSERT(statconfig != NULL && nchips > 0); + + if (extwait) + { +#ifdef CONFIG_DEBUG_ASSERTIONS + for (i = 0, config = statconfig; + i < nchips && config != NULL; i++, + config++) + { + DEBUGASSERT(config->specconfig & EMC_ASYNCPAGEENABLE); + } +#endif + + regval = lpc54_emc_timercycles(*extwait, 1, 1024); + putreg32(EMC_STATEXTWAIT(regval), LPC54_EMC_STATEXTWAIT); + } + + /* Initialize the static memory chip specific configure. */ + + for (i = 0, config = statconfig; + i < nchips && config != NULL; i++, + config++) + { + regval = config->specconfig | config->memwidth; + putreg32(regval, LPC54_EMC_STATCONFIG(config->chndx)); + + regval = lpc54_emc_timercycles(config->waitwriteen, 1, 16); + putreg32(EMC_STATWAITWEN(regval), LPC54_EMC_STATWAITWEN(config->chndx)); + + regval = lpc54_emc_timercycles(config->waitouten, 0, 15); + putreg32(EMC_STATWAITOEN(regval), LPC54_EMC_STATWAITOEN(config->chndx)); + + regval = lpc54_emc_timercycles(config->waitread, 1, 32); + putreg32(EMC_STATWAITRD(regval), LPC54_EMC_STATWAITRD(config->chndx)); + + regval = lpc54_emc_timercycles(config->waitreadpage, 1, 32); + putreg32(EMC_STATWAITPAGE(regval), LPC54_EMC_STATWAITPAGE(config->chndx)); + + regval = lpc54_emc_timercycles(config->waitwrite, 2, 33); + putreg32(EMC_STATWAITWR(regval), LPC54_EMC_STATWAITWR(config->chndx)); + + regval = lpc54_emc_timercycles(config->waitturn, 1, 16); + putreg32(EMC_STATWAITTURN(regval), LPC54_EMC_STATWAITTURN(config->chndx)); + } +} +#endif /* CONFIG_LPC54_EMC_STATIC */ + +#endif /* CONFIG_LPC54_EMC */ diff --git a/arch/arm/src/lpc54xx/lpc54_emc.h b/arch/arm/src/lpc54xx/lpc54_emc.h new file mode 100644 index 0000000000000000000000000000000000000000..54a26139dffc9747ef48a752593394096c8b2f28 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_emc.h @@ -0,0 +1,255 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_emc.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Parts of this file were adapted from sample code provided for the LPC54xx + * family from NXP which has a compatible BSD license. + * + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016 - 2017 , NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_EMC_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_EMC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "lpc54_config.h" + +#ifdef CONFIG_LPC54_EMC + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* EMC Feedback clock input source selection */ + +enum emc_fbclksrc_e +{ + EMC_INTLOOPBACK = 0, /* Use the internal loop back from EMC_CLK output */ + EMC_FBCLLK /* Use the external EMC_FBCLK input */ +}; + +/* EMC module basic configuration structure */ + +struct emc_config_s +{ + bool bigendian; /* True: Memory is big-endian */ + uint8_t clksrc; /* The feedback clock source */ + uint8_t clkdiv; /* EMC_CLK = AHB_CLK / (emc_clkDiv + 1). */ +}; + +/* EMC dynamic read strategy */ + +enum emc_dynamic_read_e +{ + EMC_NODELAY = 0, /* No delay */ + EMC_CMDDELAY, /* Command delayed strategy, using EMCCLKDELAY */ + EMC_CMDDELAYPLUS1, /* Command delayed strategy pluse one clock cycle + * using EMCCLKDELAY */ + EMC_CMDDELAYPLUS2, /* Command delayed strategy pulse two clock cycle + * using EMCCLKDELAY */ +}; + +/* EMC dynamic timing/delay configure structure */ + +struct emc_dynamic_timing_config_s +{ + uint8_t rdconfig; /* Dynamic read strategy (see enum emc_dynamic_read_e) */ + uint32_t refresh; /* The refresh period in units of nanoseconds */ + uint32_t rp; /* Precharge command period in units of nanoseconds */ + uint32_t ras; /* Active to precharge command period in units of + * nanoseconds */ + uint32_t srex; /* Self-refresh exit time in units of nanoseconds */ + uint32_t apr; /* Last data out to active command time in units of + * nanoseconds */ + uint32_t dal; /* Data-in to active command in units of nanoseconds */ + uint32_t wr; /* Write recovery time in unit of nanosecond */ + uint32_t rc; /* Active to active command period in units of + * nanoseconds */ + uint32_t rfc; /* Auto-refresh period and auto-refresh to active + * command period in unit of nanosecond */ + uint32_t xsr; /* Exit self-refresh to active command time in units + * of nanoseconds */ + uint32_t rrd; /* Active bank A to active bank B latency in units of + * nanoseconds */ + uint8_t mrd; /* Load mode register to active command time in units + * of EMCCLK cycles */ +}; + +/* EMC dynamic memory device */ + +enum emc_dynamic_device_e +{ + EMC_SDRAM = 0, /* Dynamic memory device: SDRAM */ + EMC_LPSDRAM /* Dynamic memory device: Low-power SDRAM */ +}; + +/* EMC dynamic memory controller independent chip configuration structure */ + +struct emc_dynamic_chip_config_s +{ + uint8_t chndx; /* Chip Index, range from 0 ~ EMC_DYNAMIC_MEMDEV_NUM - 1 */ + uint8_t dyndev; /* All chips shall use the same device setting. mixed + * use are not supported */ + uint8_t rasnclk; /* Active to read/write delay tRCD */ + uint16_t mode; /* Sdram mode register setting */ + uint16_t extmode; /* Used for low-power sdram device. The extended mode + * register */ + uint8_t addrmap; /* Dynamic device address mapping, choose the address + * mapping for your specific device */ +}; + +/* EMC memory width for static memory device */ + +enum emc_static_memwidth_e +{ + EMC_WIDTH_8BIT = 0, /* 8 bit memory width */ + EMC_WIDTH_16BIT, /* 16 bit memory width */ + EMC_WIDTH_32BIT /* 32 bit memory width */ +}; + +/* Define EMC static "special" configuration */ + +enum emc_static_special_config_e +{ + EMC_ASYNCPAGEENABLE = 0x00000008, /* Enable the asynchronous page mode. + * page length four */ + EMC_ACTIVEHIGHCS = 0x00000040, /* Chip select active high */ + EMC_BYTELANELOW = 0x00000080, /* Reads/writes the respective value + * bits in BLS3:0 are low */ + EMC_EXTWAITENABLE = 0x00000100, /* Extended wait enable */ + EMC_BUFFERENABLE = 0x00080000 /* Buffer enable */ +}; + +/* EMC static memory controller independent chip configuration structure */ + +struct emc_static_chip_config_s +{ + uint8_t chndx; + uint8_t memwidth; /* Memory width */ + uint32_t specconfig; /* Static configuration, OR of enum + * emc_static_special_config_e settings */ + uint32_t waitwriteen; /* The delay form chip select to write enable in + * units of nanoseconds */ + uint32_t waitouten; /* The delay from chip selcet to output enable in + * units of nanoseconds */ + uint32_t waitread; /* In No-page mode, the delay from chip select to + * read access in units of nanoseconds */ + uint32_t waitreadpage; /* In page mode, the read after the first read + * wait states in units of nanoseconds */ + uint32_t waitwrite; /* The delay from chip select to write access in + * units of nanoseconds */ + uint32_t waitturn; /* The Bus turn-around time in units of + * nanoseconds */ +}; + +/*************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_emc_initialize + * + * Description: + * This function enables the EMC clock, initializes the emc system + * configuration, and enable the EMC module. + * + * Input Parameters: + * config - Describes the EMC configuration. + * + ****************************************************************************/ + +void lpc54_emc_initialize(FAR const struct emc_config_s *config); + +/**************************************************************************** + * Name: lpc54_emc_sdram_initialize + * + * Description: + * This function initializes the dynamic memory controller in external + * memory controller. This function must be called after lpc54_emc_initialize + * and before accessing the external dynamic memory. + * + * Input Parameters: + * timing - The timing and latency for dynamica memory controller + * setting. It will be used for all dynamic memory chips, + * therefore the worst timing value for all used chips must be + * given. + * chconfig - The EMC dynamic memory controller chip-independent + * configuration array. The dimension of the array is given by + * nchips. + * nchips - The number of chips to configure and the dimension of the + * chconfig array. + * + ****************************************************************************/ + +#ifdef CONFIG_LPC54_EMC_DYNAMIC +void lpc54_emc_sdram_initialize(FAR const struct emc_dynamic_timing_config_s *timing, + FAR const struct emc_dynamic_chip_config_s *chconfig, + unsigned int nchips); +#endif /* CONFIG_LPC54_EMC_DYNAMIC */ + +/**************************************************************************** + * Name: lpc54_emc_sram_initialize + * + * Description: + * This function initializes the static memory controller in external + * memory controller. This function must be called after lpc54_emc_initialize + * and before accessing the external dynamic memory. + * + * Input Parameters: + * extwait - The extended wait timeout or the read/write transfer time. + * This is common for all static memory chips and set with + * NULL if not required. + * statconfig - The EMC static memory controller chip independent + * configuration array. The dimension of the array is nchips. + * nchips - The total static memory chip numbers been used and the + * number of entries in the statconfig array. + * + ****************************************************************************/ + +#ifdef CONFIG_LPC54_EMC_STATIC +void lpc54_emc_sram_initialize(FAR uint32_t *extwait, + FAR const struct emc_static_chip_config_s *statconfig, + uint32_t nchips); +#endif /* CONFIG_LPC54_EMC_STATIC */ + +#endif /* CONFIG_LPC54_EMC */ +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_EMC_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_enableclk.h b/arch/arm/src/lpc54xx/lpc54_enableclk.h new file mode 100644 index 0000000000000000000000000000000000000000..56a2c1194dc8669296d3b06f59978d4580192a54 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_enableclk.h @@ -0,0 +1,53 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_enableclk.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_ENABLECLK_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_ENABLECLK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the correct definitions for the configured chip */ + +#if defined(CONFIG_ARCH_FAMILY_LPC546XX) +# include "lpc546x_enableclk.h" +#else +# error "Unsupported LPC54 architecture" +#endif + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_ENABLECLK_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_ethernet.c b/arch/arm/src/lpc54xx/lpc54_ethernet.c new file mode 100644 index 0000000000000000000000000000000000000000..d89317247dc74004e777795f607c33154658059d --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_ethernet.c @@ -0,0 +1,3138 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpx54_ethernet.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Some of the logic in this file was developed using sample code provided by + * NXP that has a compatible BSD license: + * + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* TODO: + * + * 1. Timestamps not supported + * + * 2. Multi-queuing not fully; supported. The second queue is intended to + * support QVLAN, AVB type packets which have an 18-byte IEEE 802.1q + * Ethernet header. I propose handling this case with a new network + * interface qvlan_input(). + * + * 3. Multicast address filtering. Unlike other hardware, this Ethernet + * does not seem to support explicit Multicast address filtering as + * needed for ICMPv6 and for IGMP. In these cases, I am simply accepting + * all multicast packets. I am not sure if that is the right thing to + * do. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_NET_PKT +# include +#endif + +#include "up_arch.h" +#include "chip/lpc54_syscon.h" +#include "chip/lpc54_pinmux.h" +#include "chip/lpc54_ethernet.h" +#include "lpc54_enableclk.h" +#include "lpc54_reset.h" +#include "lpc54_gpio.h" + +#include + +#ifdef CONFIG_LPC54_ETHERNET + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Work queue support is required. */ + +#if !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) +#endif + +/* Multicast address filtering. Unlike other hardware, this Ethernet does + * not seem to support explicit Multicast address filtering as needed for + * ICMPv6 and for IGMP. In these cases, I am simply accepting all multicast + * packets. + */ + +#undef LPC54_ACCEPT_ALLMULTICAST +#if defined(CONFIG_LPC54_ETH_RX_ALLMULTICAST) || \ + defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) +# define LPC54_ACCEPT_ALLMULTICAST 1 +#endif + +/* The low priority work queue is preferred. If it is not enabled, LPWORK + * will be the same as HPWORK. + */ + +#define ETHWORK LPWORK + +/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */ + +#define LPC54_WDDELAY (1*CLK_TCK) + +/* TX timeout = 1 minute */ + +#define LPC54_TXTIMEOUT (60*CLK_TCK) + +/* PHY-related definitions */ + +#define LPC54_PHY_TIMEOUT 0x00ffffff /* Timeout for PHY register accesses */ + +#ifdef CONFIG_ETH0_PHY_LAN8720 +# define LPC54_PHYID1_VAL MII_PHYID1_LAN8720 +#else +# error Unrecognized PHY selection +#endif + +/* MTL-related definitions */ + +#define LPC54_MTL_QUEUE_UNIT 256 +#define LPC54_MTL_RXQUEUE_UNITS 8 /* Rx queue size = 2048 bytes */ +#define LPC54_MTL_TXQUEUE_UNITS 8 /* Tx queue size = 2048 bytes */ + +#ifdef CONFIG_LPC54_ETH_TXRR +# define LPC54_MTL_OPMODE_SCHALG ETH_MTL_OP_MODE_SHALG_WSP +#else +# define LPC54_MTL_OPMODE_SCHALG ETH_MTL_OP_MODE_SHALG_SP +#endif + +#ifdef CONFIG_LPC54_ETH_RXRR +# define LPC54_MTL_OPMODE_RAA ETH_MTL_OP_MODE_RAA_WSP +#else +# define LPC54_MTL_OPMODE_RAA ETH_MTL_OP_MODE_RAA_SP +#endif + +/* MAC-related definitions */ + +#define LPC54_MAC_HALFDUPLEX_IPG ETH_MAC_CONFIG_IPG_64 /* Default half-duplex IPG */ + +/* Packet-buffer definitions */ + +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE +# define LPC54_NBUFFERS (CONFIG_LPC54_ETH_NRXDESC0 + \ + CONFIG_LPC54_ETH_NRXDESC1 + \ + CONFIG_LPC54_ETH_NTXDESC0 + \ + CONFIG_LPC54_ETH_NTXDESC1) +#else +# define LPC54_NBUFFERS (CONFIG_LPC54_ETH_NRXDESC0 + \ + CONFIG_LPC54_ETH_NTXDESC0) +#endif + +#define LPC54_BUFFER_SIZE MAX_NET_DEV_MTU +#define LPC54_BUFFER_ALLOC ((MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE + 3) & ~3) +#define LPC54_BUFFER_WORDS ((MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE + 3) >> 2) +#define LPC54_BUFFER_MAX 16384 + +/* DMA and DMA descriptor definitions */ + +#define LPC54_MIN_RINGLEN 4 /* Min length of a ring */ +#define LPC54_MAX_RINGLEN 1023 /* Max length of a ring */ +#define LPC54_MAX_RINGS 2 /* Max number of tx/rx descriptor rings */ +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE +# define LPC54_NRINGS 2 /* Use 2 Rx and Tx rings */ +#else +# define LPC54_NRINGS 1 /* Use 1 Rx and 1 Tx ring */ +#endif + +#ifndef CONFIG_LPC54_ETH_BURSTLEN +# define CONFIG_LPC54_ETH_BURSTLEN 1 +#endif + +#if CONFIG_LPC54_ETH_BURSTLEN < 2 +# define LPC54_BURSTLEN 1 +# define LPC54_PBLx8 0 +#elif CONFIG_LPC54_ETH_BURSTLEN < 4 +# define LPC54_BURSTLEN 2 +# define LPC54_PBLx8 0 +#elif CONFIG_LPC54_ETH_BURSTLEN < 8 +# define LPC54_BURSTLEN 4 +# define LPC54_PBLx8 0 +#elif CONFIG_LPC54_ETH_BURSTLEN < 16 +# define LPC54_BURSTLEN 8 +# define LPC54_PBLx8 0 +#elif CONFIG_LPC54_ETH_BURSTLEN < 32 +# define LPC54_BURSTLEN 16 +# define LPC54_PBLx8 0 +#elif CONFIG_LPC54_ETH_BURSTLEN < 64 +# define LPC54_BURSTLEN 32 +# define LPC54_PBLx8 0 +#elif CONFIG_LPC54_ETH_BURSTLEN < 128 +# define LPC54_BURSTLEN 8 +# define LPC54_PBLx8 ETH_DMACH_CTRL_PBLx8 +#elif CONFIG_LPC54_ETH_BURSTLEN < 256 +# define LPC54_BURSTLEN 16 +# define LPC54_PBLx8 ETH_DMACH_CTRL_PBLx8 +#else +# define LPC54_BURSTLEN 32 +# define LPC54_PBLx8 ETH_DMACH_CTRL_PBLx8 +#endif + +#ifdef CONFIG_LPC54_ETH_DYNAMICMAP +# define LPC54_QUEUEMAP (ETH_MTL_RXQ_DMA_MAP_Q0DDMACH | \ + ETH_MTL_RXQ_DMA_MAP_Q1DDMACH) +#else +# define LPC54_QUEUEMAP ETH_MTL_RXQ_DMA_MAP_Q1MDMACH +#endif + +/* Interrupt masks */ + +#define LPC54_ABNORM_INTMASK (ETH_DMACH_INT_TS | ETH_DMACH_INT_RBU | \ + ETH_DMACH_INT_RS | ETH_DMACH_INT_RWT | \ + ETH_DMACH_INT_FBE | ETH_DMACH_INT_AI) +#define LPC54_TXERR_INTMASK (ETH_DMACH_INT_TS) +#define LPC54_RXERR_INTMASK (ETH_DMACH_INT_RBU | ETH_DMACH_INT_RS | \ + ETH_DMACH_INT_RWT) +#define LPC54_NORM_INTMASK (ETH_DMACH_INT_TI | ETH_DMACH_INT_RI | \ + ETH_DMACH_INT_NI) + +/* This is a helper pointer for accessing the contents of the Ethernet + * header. + */ + +#define ETHBUF ((struct eth_hdr_s *)priv->eth_dev.d_buf) +#define ETH8021QWBUF ((struct eth_8021qhdr_s *)priv->eth_dev.d_buf) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Describes the state of one Tx descriptor ring */ + +struct lpc54_txring_s +{ + struct enet_txdesc_s *tr_desc; /* Tx descriptor base address */ + uint16_t tr_supply; /* Tx supplier ring index */ + uint16_t tr_consume; /* Tx consumer ring index */ + uint16_t tr_ndesc; /* Number or descriptors in the Tx ring */ + uint16_t tr_inuse; /* Number of Tx descriptors in-use */ + uint32_t **tr_buffers; /* Packet buffers assigned to the Rx ring */ +}; + +/* Describes the state of one Rx descriptor ring */ + +struct lpc54_rxring_s +{ + struct enet_rxdesc_s *rr_desc; /* Rx descriptor base address */ + uint16_t rr_supply; /* Available Rx descriptor ring index */ + uint16_t rr_ndesc; /* Number or descriptors in the Rx ring */ + uint32_t **rr_buffers; /* Packet buffers assigned to the Rx ring */ +}; + +/* The lpc54_ethdriver_s encapsulates all state information for a single + * Ethernet interface + */ + +struct lpc54_ethdriver_s +{ + uint8_t eth_bifup : 1; /* 1:ifup 0:ifdown */ + uint8_t eth_fullduplex : 1; /* 1:Full duplex 0:Half duplex mode */ + uint8_t eth_100mbps : 1; /* 1:100mbps 0:10mbps */ + uint8_t eth_rxdiscard : 1; /* 1:Discarding Rx data */ + WDOG_ID eth_txpoll; /* TX poll timer */ + WDOG_ID eth_txtimeout; /* TX timeout timer */ + struct work_s eth_irqwork; /* For deferring interrupt work to the work queue */ + struct work_s eth_pollwork; /* For deferring poll work to the work queue */ + struct work_s eth_timeoutwork; /* For deferring timeout work to the work queue */ + struct sq_queue_s eth_freebuf; /* Free packet buffers */ + + /* Ring state */ + + struct lpc54_txring_s eth_txring[LPC54_NRINGS]; + struct lpc54_rxring_s eth_rxring[LPC54_NRINGS]; + + /* This holds the information visible to the NuttX network */ + + struct net_driver_s eth_dev; /* Interface understood by the network */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* These statically allocated structures are possible because only a single + * instance of the Ethernet device could be supported. In order to support + * multiple devices instances, this data would have to be allocated + * dynamically. + */ + +/* Driver state structure */ + +static struct lpc54_ethdriver_s g_ethdriver; + +/* Rx DMA descriptors */ + +static struct enet_rxdesc_s g_ch0_rxdesc[CONFIG_LPC54_ETH_NRXDESC0]; +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE +static struct enet_rxdesc_s g_ch1_rxdesc[CONFIG_LPC54_ETH_NRXDESC1]; +#endif + +/* Tx DMA descriptors */ + +static struct enet_txdesc_s g_ch0_txdesc[CONFIG_LPC54_ETH_NTXDESC0]; +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE +static struct enet_txdesc_s g_ch1_txdesc[CONFIG_LPC54_ETH_NTXDESC1]; +#endif + +/* Preallocated packet buffers */ + +static uint32_t g_prealloc_buffers[LPC54_NBUFFERS * LPC54_BUFFER_WORDS]; + +/* Packet buffers assigned to Rx and Tx descriptors. The packet buffer + * addresses are lost in the DMA due to write-back from the DMA hardware. + * So we have to remember the buffer assignments explicitly. + * + * REVISIT: According to the User manual, buffer1 and buffer2 addresses + * will be overwritten by DMA write-back data. However, I see that the + * Rx buffer1 and buffer2 addresses are, indeed, used by the NXP example + * code after completion of DMA so the user manual must be wrong. We + * could eliminate this extra array of saved allocation addresses. + */ + +static uint32_t *g_rxbuffers0[CONFIG_LPC54_ETH_NRXDESC0]; +static uint32_t *g_txbuffers0[CONFIG_LPC54_ETH_NTXDESC0]; +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE +static uint32_t *g_rxbuffers1[CONFIG_LPC54_ETH_NRXDESC1]; +static uint32_t *g_txbuffers1[CONFIG_LPC54_ETH_NTXDESC1]; +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register level debug hooks */ + +#ifdef CONFIG_LPC54_ETH_REGDEBUG +static uint32_t lpc54_getreg(uintptr_t addr); +static void lpc54_putreg(uint32_t val, uintptr_t addr); +#else +# define lpc54_getreg(addr) getreg32(addr) +# define lpc54_putreg(val,addr) putreg32(val,addr) +#endif + +/* Common TX logic */ + +static int lpc54_eth_transmit(struct lpc54_ethdriver_s *priv, + unsigned int chan); +static unsigned int lpc54_eth_getring(struct lpc54_ethdriver_s *priv); +static int lpc54_eth_txpoll(struct net_driver_s *dev); + +/* Interrupt handling */ + +static void lpc54_eth_reply(struct lpc54_ethdriver_s *priv); +static void lpc54_eth_rxdispatch(struct lpc54_ethdriver_s *priv); +static int lpc54_eth_receive(struct lpc54_ethdriver_s *priv, + unsigned int chan); +static void lpc54_eth_txdone(struct lpc54_ethdriver_s *priv, + unsigned int chan); + +static void lpc54_eth_channel_work(struct lpc54_ethdriver_s *priv, + unsigned int chan); +static void lpc54_eth_interrupt_work(void *arg); +static int lpc54_eth_interrupt(int irq, void *context, void *arg); +#if 0 /* Not used */ +static int lpc54_pmt_interrupt(int irq, void *context, void *arg); +static int lpc54_mac_interrupt(int irq, void *context, void *arg); +#endif + +/* Watchdog timer expirations */ + +static void lpc54_eth_dotimer(struct lpc54_ethdriver_s *priv); +static void lpc54_eth_dopoll(struct lpc54_ethdriver_s *priv); + +static void lpc54_eth_txtimeout_work(void *arg); +static void lpc54_eth_txtimeout_expiry(int argc, wdparm_t arg, ...); + +static void lpc54_eth_poll_work(void *arg); +static void lpc54_eth_poll_expiry(int argc, wdparm_t arg, ...); + +/* NuttX callback functions */ + +static int lpc54_eth_ifup(struct net_driver_s *dev); +static int lpc54_eth_ifdown(struct net_driver_s *dev); + +static void lpc54_eth_txavail_work(void *arg); +static int lpc54_eth_txavail(struct net_driver_s *dev); + +#ifdef CONFIG_NET_IGMP +static int lpc54_eth_addmac(struct net_driver_s *dev, + const uint8_t *mac); +static int lpc54_eth_rmmac(struct net_driver_s *dev, + const uint8_t *mac); +#endif +#ifdef CONFIG_NETDEV_IOCTL +static int lpc54_eth_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg); +#endif + +/* Packet buffers */ + +static void lpc54_pktbuf_initialize(struct lpc54_ethdriver_s *priv); +static inline uint32_t *lpc54_pktbuf_alloc(struct lpc54_ethdriver_s *priv); +static inline void lpc54_pktbuf_free(struct lpc54_ethdriver_s *priv, + uint32_t *pktbuf); + +/* DMA descriptor rings */ + +static void lpc54_txring_initialize(struct lpc54_ethdriver_s *priv, + unsigned int chan); +static void lpc54_rxring_initialize(struct lpc54_ethdriver_s *priv, + unsigned int chan); +static void lpc54_ring_initialize(struct lpc54_ethdriver_s *priv); + +/* Initialization/PHY control */ + +static void lpc54_set_csrdiv(void); +static uint16_t lpc54_phy_read(struct lpc54_ethdriver_s *priv, + uint8_t phyreg); +static void lpc54_phy_write(struct lpc54_ethdriver_s *priv, + uint8_t phyreg, uint16_t phyval); +static inline bool lpc54_phy_linkstatus(struct lpc54_ethdriver_s *priv); +static int lpc54_phy_autonegotiate(struct lpc54_ethdriver_s *priv); +static int lpc54_phy_reset(struct lpc54_ethdriver_s *priv); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_getreg + * + * Description: + * This function may to used to intercept an monitor all register accesses. + * Clearly this is nothing you would want to do unless you are debugging + * this driver. + * + * Input Parameters: + * addr - The register address to read + * + * Returned Value: + * The value read from the register + * + ****************************************************************************/ + +#ifdef CONFIG_LPC54_ETH_REGDEBUG +static uint32_t lpc54_getreg(uintptr_t addr) +{ + static uintptr_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + + /* Read the value from the register */ + + uint32_t val = getreg32(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + ninfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + ninfo("[repeats %d more times]\n", count-3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + ninfo("%08x->%08x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: lpc54_putreg + * + * Description: + * This function may to used to intercept an monitor all register accesses. + * Clearly this is nothing you would want to do unless you are debugging + * this driver. + * + * Input Parameters: + * val - The value to write to the register + * addr - The register address to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_LPC54_ETH_REGDEBUG +static void lpc54_putreg(uint32_t val, uintptr_t addr) +{ + /* Show the register value being written */ + + ninfo("%08x<-%08x\n", addr, val); + + /* Write the value */ + + putreg32(val, addr); +} +#endif + +/**************************************************************************** + * Name: lpc54_eth_transmit + * + * Description: + * Start hardware transmission. Called either from the txdone interrupt + * handling or from watchdog based polling. + * + * Parameters: + * priv - Reference to the driver state structure + * chan - The channel to send the packet on + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static int lpc54_eth_transmit(struct lpc54_ethdriver_s *priv, + unsigned int chan) +{ + struct lpc54_txring_s *txring; + struct enet_txdesc_s *txdesc; + uint8_t *buffer; + uint32_t regval; + unsigned int buflen; + + /* Verify that the hardware is ready to send another packet. If we get + * here, then we are committed to sending a packet; Higher level logic + * must have assured that we have the resources available to perform the + * send. + */ + + txring = &priv->eth_txring[chan]; + + DEBUGASSERT(priv->eth_dev.d_buf != 0 && priv->eth_dev.d_len > 0 && + priv->eth_dev.d_len <= LPC54_BUFFER_SIZE && + txring->tr_inuse < txring->tr_ndesc); + + /* Fill the descriptor. */ + + txdesc = txring->tr_desc + txring->tr_supply; + buffer = priv->eth_dev.d_buf; + buflen = priv->eth_dev.d_len; + + priv->eth_dev.d_buf = NULL; + priv->eth_dev.d_len = 0; + + if (buflen <= LPC54_BUFFER_MAX) + { + /* Prepare the Tx descriptor for transmission */ + + txdesc->buffer1 = (uint32_t)buffer; + txdesc->buffer2 = (uint32_t)NULL; + + /* One buffer, no timestamp, interrupt on completion */ + + regval = ETH_TXDES2_B1L(buflen) | ETH_TXDES2_B2L(0) | ETH_TXDES2_IOC; + txdesc->buflen = regval; + + /* Full packet length, last descriptor, first descriptor, owned by + * DMA. + */ + + regval = ETH_TXDES3_FL(buflen) | ETH_TXDES3_LD | ETH_TXDES3_FD | + ETH_TXDES3_OWN; + txdesc->ctrlstat = regval; + } +#if LPC54_BUFFER_SIZE > LPC54_BUFFER_MAX + else + { + unsigned int buf2len = buflen - LPC54_BUFFER_MAX; + uint8_t *buffer2 = buffer + LPC54_BUFFER_MAX; + + DEBUGASSERT(buf2len <= LPC54_BUFFER_MAX); + + /* Prepare the Tx descriptor for transmission */ + + txdesc->buffer1 = (uint32_t)buffer; + txdesc->buffer2 = (uint32_t)buffer2; + + /* Two buffers, no timestamp, interrupt on completion */ + + regval = ETH_TXDES2_B1L(LPC54_BUFFER_MAX) | + ETH_TXDES2_B2L(buf2len) | ETH_TXDES2_IOC; + txdesc->buflen = regval; + + /* Full packet length, last descriptor, first descriptor, owned by + * DMA. + */ + + regval = ETH_TXDES3_FL(buflen) | ETH_TXDES3_LD | ETH_TXDES3_FD | + ETH_TXDES3_OWN; + txdesc->ctrlstat = regval; + } +#endif + + /* Increase the index */ + + if (++(txring->tr_supply) >= txring->tr_ndesc) + { + txring->tr_supply = 0; + } + + /* Increment the number of descriptors in-use. */ + + txring->tr_inuse++; + + /* Update the transmit tail address. */ + + txdesc = txring->tr_desc + txring->tr_supply; + if (txring->tr_supply == 0) + { + txdesc = txring->tr_desc + txring->tr_ndesc; + } + + /* Update the DMA tail pointer */ + + lpc54_putreg((uint32_t)txdesc, LPC54_ETH_DMACH_TXDESC_TAIL_PTR(chan)); + + /* Setup the TX timeout watchdog (perhaps restarting the timer) */ + + (void)wd_start(priv->eth_txtimeout, LPC54_TXTIMEOUT, + lpc54_eth_txtimeout_expiry, 1, (wdparm_t)priv); + return OK; +} + +/**************************************************************************** + * Name: lpc54_eth_getring + * + * Description: + * An output message is ready to send, but which queue should we send it + * on? The rule is this: + * + * "Normal" packets (or CONFIG_LPC54_ETH_MULTIQUEUE not selected): + * Always send on ring 0 + * 8021QVLAN AVB packets (and CONFIG_LPC54_ETH_MULTIQUEUE not selected): + * Always send on ring 1 + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * The ring to use when sending the packet. + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static unsigned int lpc54_eth_getring(struct lpc54_ethdriver_s *priv) +{ + unsigned int ring = 0; + +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE + /* Choose the ring ID for different types of frames. For 802.1q VLAN AVB + * frames, uses ring 1. Everything else goes on ring 0. + */ + + if (ETH8021QWBUF->tpid == HTONS(TPID_8021QVLAN) && + ETH8021QWBUF->type == HTONS(ETHTYPE_AVBTP)) + { + ring = 1; + } +#endif + + return ring; +} + +/**************************************************************************** + * Name: lpc54_eth_txpoll + * + * Description: + * The transmitter is available, check if the network has any outgoing + * packets ready to send. This is a callback from devif_poll(). + * devif_poll() may be called: + * + * 1. When the preceding TX packet send is complete, + * 2. When the preceding TX packet send timesout and the interface is reset + * 3. During normal TX polling + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static int lpc54_eth_txpoll(struct net_driver_s *dev) +{ + struct lpc54_ethdriver_s *priv; + struct lpc54_txring_s *txring; + struct lpc54_txring_s *txring0; +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE + struct lpc54_txring_s *txring1; +#endif + unsigned int chan; + + DEBUGASSERT(dev->d_private != NULL && dev->d_buf != NULL); + priv = (struct lpc54_ethdriver_s *)dev->d_private; + + /* If the polling resulted in data that should be sent out on the network, + * the field d_len is set to a value > 0. + */ + + if (priv->eth_dev.d_len > 0) + { + /* Look up the destination MAC address and add it to the Ethernet + * header. + */ + +#ifdef CONFIG_NET_IPv4 +#ifdef CONFIG_NET_IPv6 + if (IFF_IS_IPv4(priv->eth_dev.d_flags)) +#endif + { + arp_out(&priv->eth_dev); + } +#endif /* CONFIG_NET_IPv4 */ + +#ifdef CONFIG_NET_IPv6 +#ifdef CONFIG_NET_IPv4 + else +#endif + { + neighbor_out(&priv->eth_dev); + } +#endif /* CONFIG_NET_IPv6 */ + + /* Send the packet */ + + chan = lpc54_eth_getring(priv); + txring = &priv->eth_txring[chan]; + + (txring->tr_buffers)[txring->tr_supply] = + (uint32_t *)priv->eth_dev.d_buf; + + lpc54_eth_transmit(priv, chan); + + txring0 = &priv->eth_txring[0]; +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE + txring1 = &priv->eth_txring[1]; + + /* We cannot perform the Tx poll now if all of the Tx descriptors for + * both channels are in-use. + */ + + if (txring0->tr_inuse >= txring0->tr_ndesc || + txring1->tr_inuse >= txring1->tr_ndesc) +#else + /* We cannot continue the Tx poll now if all of the Tx descriptors for + * this channel 0 are in-use. + */ + + if (txring0->tr_inuse >= txring0->tr_ndesc) +#endif + { + /* Stop the poll.. no more Tx descriptors */ + + return 1; + } + + /* There is a free descriptor in the ring, allocate a new Tx buffer + * to perform the poll. + */ + + priv->eth_dev.d_buf = (uint8_t *)lpc54_pktbuf_alloc(priv); + if (priv->eth_dev.d_buf == NULL) + { + /* Stop the poll.. no more packet buffers */ + + return 1; + } + } + + /* If zero is returned, the polling will continue until all connections + * have been examined. If there is nothing to be sent, we will return to + * the caller of devif_poll() with an allocated packet buffer. + */ + + return 0; +} + +/**************************************************************************** + * Name: lpc54_eth_reply + * + * Description: + * After a packet has been received and dispatched to the network, it + * may return return with an outgoing packet. This function checks for + * that case and performs the transmission if necessary. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static void lpc54_eth_reply(struct lpc54_ethdriver_s *priv) +{ + struct lpc54_txring_s *txring; + unsigned int chan; + + /* If the packet dispatch resulted in data that should be sent out on the + * network, the field d_len will set to a value > 0. + */ + + if (priv->eth_dev.d_len > 0) + { + /* Update the Ethernet header with the correct MAC address */ + +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE + /* Check for an outgoing 802.1q VLAN packet */ +#warning Missing Logic +#endif + +#ifdef CONFIG_NET_IPv4 +#ifdef CONFIG_NET_IPv6 + /* Check for an outgoing IPv4 packet */ + + if (IFF_IS_IPv4(priv->eth_dev.d_flags)) +#endif + { + arp_out(&priv->eth_dev); + } +#endif + +#ifdef CONFIG_NET_IPv6 +#ifdef CONFIG_NET_IPv4 + /* Otherwise, it must be an outgoing IPv6 packet */ + + else +#endif + { + neighbor_out(&priv->eth_dev); + } +#endif + + /* And send the packet */ + + chan = lpc54_eth_getring(priv); + txring = &priv->eth_txring[chan]; + + (txring->tr_buffers)[txring->tr_supply] = + (uint32_t *)priv->eth_dev.d_buf; + + lpc54_eth_transmit(priv, chan); + } +} + +/**************************************************************************** + * Name: lpc54_eth_rxdispatch + * + * Description: + * A new packet has been received and will be forwarded to the network + * stack. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static void lpc54_eth_rxdispatch(struct lpc54_ethdriver_s *priv) +{ +#ifdef CONFIG_NET_PKT + /* When packet sockets are enabled, feed the frame into the packet tap */ + + pkt_input(&priv->eth_dev); +#endif + + /* We only accept IP packets of the configured type and ARP packets */ + +#ifdef CONFIG_NET_IPv4 + if (ETHBUF->type == HTONS(ETHTYPE_IP)) + { + ninfo("IPv4 packet\n"); + NETDEV_RXIPV4(&priv->eth_dev); + + /* Handle ARP on input, then dispatch IPv4 packet to the network layer */ + + arp_ipin(&priv->eth_dev); + ipv4_input(&priv->eth_dev); + + /* Check for a reply to the IPv4 packet */ + + lpc54_eth_reply(priv); + } + else +#endif +#ifdef CONFIG_NET_IPv6 + if (ETHBUF->type == HTONS(ETHTYPE_IP6)) + { + ninfo("Iv6 packet\n"); + NETDEV_RXIPV6(&priv->eth_dev); + + /* Dispatch IPv6 packet to the network layer */ + + ipv6_input(&priv->eth_dev); + + /* Check for a reply to the IPv6 packet */ + + lpc54_eth_reply(priv); + } + else +#endif +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE + if (ETH8021QWBUF->tpid == HTONS(TPID_8021QVLAN)) + { + ninfo("IEEE 802.1q packet\n"); + NETDEV_RXQVLAN(&priv->eth_dev); + + /* Dispatch the 802.1q VLAN packet to the network layer */ + + qvlan_input(&priv->eth_dev); + + /* Check for a reply to the 802.1q VLAN packet */ + + lpc54_eth_reply(priv); + } + else +#endif +#ifdef CONFIG_NET_ARP + if (ETHBUF->type == htons(ETHTYPE_ARP)) + { + struct lpc54_txring_s *txring; + unsigned int chan; + + /* Dispatch the ARP packet to the network layer */ + + arp_arpin(&priv->eth_dev); + NETDEV_RXARP(&priv->eth_dev); + + /* If the above function invocation resulted in data that should be + * sent out on the network, the field d_len will set to a value > 0. + */ + + if (priv->eth_dev.d_len > 0) + { + chan = lpc54_eth_getring(priv); + txring = &priv->eth_txring[chan]; + + (txring->tr_buffers)[txring->tr_supply] = + (uint32_t *)priv->eth_dev.d_buf; + + lpc54_eth_transmit(priv, chan); + } + } + else +#endif + { + NETDEV_RXDROPPED(&priv->eth_dev); + } + + /* On entry, d_buf refers to the receive buffer as set by logic in + * lpc54_eth_receive(). If lpc54_eth_transmit() was called to reply + * with an outgoing packet, then that packet was removed for transmission + * and d_buf was nullified. Otherwise, d_buf still holds the stale + * receive buffer and we will need to dispose of it here. + */ + + if (priv->eth_dev.d_buf != NULL) + { + lpc54_pktbuf_free(priv, (uint32_t *)priv->eth_dev.d_buf); + } + + priv->eth_dev.d_buf = NULL; + priv->eth_dev.d_len = 0; +} + +/**************************************************************************** + * Name: lpc54_eth_receive + * + * Description: + * An interrupt was received indicating the availability of a new RX packet + * + * Parameters: + * priv - Reference to the driver state structure + * chan - The channel with the completed Rx transfer + * + * Returned Value: + * The number of Rx descriptors processed + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static int lpc54_eth_receive(struct lpc54_ethdriver_s *priv, + unsigned int chan) +{ + struct lpc54_rxring_s *rxring; + struct enet_rxdesc_s *rxdesc; + unsigned int framelen; + unsigned int pktlen; + unsigned int supply; + uint32_t regval; + bool suspend; + int ndesc; + + /* Get the Rx ring associated with this channel */ + + rxring = &priv->eth_rxring[chan]; + + /* If no Rx descriptor is available, then suspend for now */ + + regval = lpc54_getreg(LPC54_ETH_DMACH_STAT(chan)); + suspend = ((regval & ETH_DMACH_INT_RBU) != 0); + + /* Loop until the next full frame is encountered or until we encounter a + * descriptor still owned by the DMA. + */ + + pktlen = 0; + ndesc = 0; + + for (; ; ) + { + /* Get the last Rx descriptor in the ring */ + + supply = rxring->rr_supply; + rxdesc = rxring->rr_desc + supply; + + /* Is this frame still owned by the DMA? */ + + if ((rxdesc->ctrl & ETH_RXDES3_OWN) != 0) + { + /* Yes.. then bail */ + + return ndesc; + } + + ndesc++; + + /* Set the supplier index to the next descriptor */ + + if (++(rxring->rr_supply) > rxring->rr_ndesc) + { + rxring->rr_supply = 0; + } + + /* Is this the last descriptor of the frame? */ + + if ((rxdesc->ctrl & ETH_RXDES3_LD) != 0) + { + /* Have we been discarding Rx data? If so, that was the last + * packet to be discarded. + */ + + if (priv->eth_rxdiscard) + { + priv->eth_rxdiscard = 0; + } + else + { + /* Last frame encountered. This is a valid packet */ + + framelen = (rxdesc->ctrl & ETH_RXDES3_PL_MASK); + pktlen += framelen; + + if (pktlen > 0) + { + /* Recover the buffer. + * + * REVISIT: According to the User manual, buffer1 and + * buffer2 addresses were overwritten by the write-back + * data. However, I see that the buffer1 and buffer2 + * addresses are, indeed, used by the NXP example code + * so the user manual must be wrong. We could eliminate + * this extra array of saved allocation addresses. + */ + + priv->eth_dev.d_buf = (uint8_t *)(rxring->rr_buffers)[supply]; + (rxring->rr_buffers)[supply] = NULL; + DEBUGASSERT(priv->eth_dev.d_buf != NULL); + + priv->eth_dev.d_len = pktlen; + + /* REVISIT: What should we do if there is no Tx buffer + * available. In receiving the packet, we could also + * generate a new outgoing packet that could only be + * handled if there is an available Tx descriptor. + */ + + lpc54_eth_rxdispatch(priv); + + /* Allocate a new Rx buffer and update the Rx buffer + * descriptor. + */ + + rxdesc->buffer1 = (uint32_t)lpc54_pktbuf_alloc(priv); + DEBUGASSERT(rxdesc->buffer1 != 0); + (rxring->rr_buffers)[supply] = (uint32_t *)rxdesc->buffer1; + +#if LPC54_BUFFER_SIZE > LPC54_BUFFER_MAX + rxdesc->buffer2 = rxdesc->buffer1 + LPC54_BUFFER_MAX; +#else + /* The second buffer is not used */ + + rxdesc->buffer2 = 0; +#endif + rxdesc->reserved = 0; + + /* Buffer1 (and maybe 2) valid, interrupt on completion, + * owned by DMA. + */ + + regval = ETH_RXDES3_BUF1V | ETH_RXDES3_IOC | ETH_RXDES3_OWN; +#if LPC54_BUFFER_SIZE > LPC54_BUFFER_MAX + regval |= ETH_RXDES3_BUF2V; +#endif + rxdesc->ctrl = regval; + } + + return ndesc; + } + } + else if (!priv->eth_rxdiscard) + { + /* Not the last Rx descriptor of the packet. + * + * We are attempting to receive a large packet spanning multiple + * Rx descriptors. We cannot support that in this design. We + * would like to: + * + * 1. Accumulate the data in yet another Rx buffer, + * 2. Accumulate the size in the 'pktlen' local variable, then + * 3. Dispatch that extra Rx buffer when the last frame is + * encountered. + * + * The assumption here is that this will never happen if our MTU + * properly advertised. + */ + + NETDEV_RXDROPPED(&priv->eth_dev); + priv->eth_rxdiscard = 1; + } + } + + /* Restart the receiver and clear the RBU status if it was suspended. */ + + if (suspend) + { + uintptr_t regaddr = LPC54_ETH_DMACH_RXDESC_TAIL_PTR(chan); + + /* Clear the RBU status */ + + lpc54_putreg(ETH_DMACH_INT_RBU, LPC54_ETH_DMACH_STAT(chan)); + + /* Writing to the tail pointer register will restart the Rx processing */ + + regval = lpc54_getreg(regaddr); + lpc54_putreg(regval, regaddr); + } + + return ndesc; +} + +/**************************************************************************** + * Name: lpc54_eth_txdone + * + * Description: + * An interrupt was received indicating that the last TX packet(s) is done + * + * Parameters: + * priv - Reference to the driver state structure + * chan - The channel with the completed Tx transfer + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static void lpc54_eth_txdone(struct lpc54_ethdriver_s *priv, + unsigned int chan) +{ + struct lpc54_txring_s *txring; +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE + struct lpc54_txring_s *txring0; + struct lpc54_txring_s *txring1; +#endif + struct enet_txdesc_s *txdesc; + uint32_t *pktbuf; + + /* Reclaim the compled Tx descriptor */ + + txring = &priv->eth_txring[chan]; + txdesc = txring->tr_desc + txring->tr_consume; + + /* Update the first index for transmit buffer free. */ + + while (txring->tr_inuse > 0 && (txdesc->ctrlstat & ETH_TXDES3_OWN) == 0) + { + /* Update statistics */ + + NETDEV_TXDONE(priv->eth_dev); + + /* Free the Tx buffer assigned to the descriptor */ + + pktbuf = txring->tr_buffers[txring->tr_consume]; + DEBUGASSERT(pktbuf != NULL); + if (pktbuf != NULL) + { + lpc54_pktbuf_free(priv, pktbuf); + txring->tr_buffers[txring->tr_consume] = NULL; + } + + /* One less Tx descriptor in use */ + + txring->tr_inuse--; + + /* Update the consume index and the descriptor pointer. */ + + if (++(txring->tr_consume) >= txring->tr_ndesc) + { + txring->tr_consume = 0; + } + + txdesc = txring->tr_desc + txring->tr_consume; + } + + /* If no further transmissions are pending, then cancel the TX timeout. */ + +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE + txring0 = &priv->eth_txring[0]; + txring1 = &priv->eth_txring[1]; + + if (txring0->tr_inuse == 0 && txring1->tr_inuse == 0) + +#else + if (txring->tr_inuse == 0) +#endif + { + wd_cancel(priv->eth_txtimeout); + work_cancel(ETHWORK, &priv->eth_timeoutwork); + } + + /* Poll the network for new TX data. */ + + lpc54_eth_dopoll(priv); +} + +/**************************************************************************** + * Name: lpc54_eth_channel_work + * + * Description: + * Perform interrupt related work for a channel DMA interrupt + * + * Parameters: + * priv - Reference to the driver state structure + * chan - The channel that received the interrupt event. + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static void lpc54_eth_channel_work(struct lpc54_ethdriver_s *priv, + unsigned int chan) +{ + uintptr_t regaddr; + uint32_t status; + uint32_t pending; + + /* Read the DMA status register for this channel */ + + regaddr = LPC54_ETH_DMACH_STAT(chan); + status = lpc54_getreg(regaddr); + pending = status & lpc54_getreg(LPC54_ETH_DMACH_INT_EN(chan)); + + /* Check for abnormal interrupts */ + + if ((pending & LPC54_ABNORM_INTMASK) != 0) + { + /* Acknowledge the abnormal interrupt interrupts except for RBU... + * that is a special case where the status will be cleared in + * lpc54_eth_receive(). See comments below. + */ + + lpc54_putreg((LPC54_ABNORM_INTMASK & ~ETH_DMACH_INT_RBU), regaddr); + + /* Handle the incoming packet */ + + nerr("ERROR: Abnormal interrupt received: %08lx (%08lx)\n", + (unsigned long)pending, (unsigned long)status); + + /* Check for Tx/Rx related errors and update statistics */ + + if ((pending & LPC54_RXERR_INTMASK) != 0) + { + NETDEV_RXERRORS(priv->eth_dev); + } + + if ((pending & LPC54_TXERR_INTMASK) != 0) + { + NETDEV_TXERRORS(priv->eth_dev); + } + + /* The Receive Buffer Unavailable (RBU) error is a special case. It + * means that we have an Rx overrun condition: All of the Rx buffers + * have been filled with packet data and there are no Rx descriptors + * available to receive the next packet. + * + * Often RBU is accompanied by RI but we need to force that condition + * in all cases. In the case of RBU, we need to perform receive + * processing in order to recover from the situation and to resume. + * + * This is really a configuration problem: It really means that we + * have not assigned enough Rx buffers for the environment and + * addressing filtering options that we have selected. + */ + + if ((pending & ETH_DMACH_INT_RBU) != 0) + { + pending |= ETH_DMACH_INT_RI; + } + + pending &= ~LPC54_ABNORM_INTMASK; + } + + /* Check for a receive interrupt */ + + if ((pending & ETH_DMACH_INT_RI) != 0) + { + int ndesc; + + /* Acknowledge the normal receive interrupt */ + + lpc54_putreg(ETH_DMACH_INT_RI | ETH_DMACH_INT_NI, regaddr); + pending &= ~(ETH_DMACH_INT_RI | ETH_DMACH_INT_NI); + + /* Loop until all available Rx packets in the ring have been processed */ + + for (; ; ) + { + /* Dispatch the next packet from the Rx ring */ + + ndesc = lpc54_eth_receive(priv, chan); + if (ndesc > 0) + { + /* Update statistics if a packet was dispatched */ + + NETDEV_RXPACKETS(priv->eth_dev); + } + else + { + break; + } + } + } + + /* Check for a transmit interrupt */ + + if ((pending & ETH_DMACH_INT_TI) != 0) + { + /* Acknowledge the normal receive interrupt */ + + lpc54_putreg(ETH_DMACH_INT_TI | ETH_DMACH_INT_NI, regaddr); + pending &= ~(ETH_DMACH_INT_TI | ETH_DMACH_INT_NI); + + /* Handle the Tx completion event. Reclaim the completed Tx + * descriptors, free packet buffers, and check if we can start a new + * transmission. + */ + + lpc54_eth_txdone(priv, chan); + } + + /* Check for unhandled interrupts (shouldn't be any) */ + + if (pending != 0) + { + nwarn("WARNING: Unhandled interrupts: %08lx (%08lx)\n", + (unsigned long)pending, (unsigned long)status); + lpc54_putreg(pending, regaddr); + } +} + +/**************************************************************************** + * Name: lpc54_eth_interrupt_work + * + * Description: + * Perform interrupt related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() was called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * Runs on a worker thread. + * + ****************************************************************************/ + +static void lpc54_eth_interrupt_work(void *arg) +{ + struct lpc54_ethdriver_s *priv = (struct lpc54_ethdriver_s *)arg; + uint32_t intrstat; + + /* Lock the network to serialize driver operations. */ + + net_lock(); + + /* Check if interrupt is from DMA channel 0. */ + + intrstat = lpc54_getreg(LPC54_ETH_DMA_INTR_STAT); + if ((intrstat & ETH_DMA_INTR_STAT_DC0IS) != 0) + { + lpc54_eth_channel_work(priv, 0); + } + + /* Check if interrupt is from DMA channel 1. */ + + intrstat = lpc54_getreg(LPC54_ETH_DMA_INTR_STAT); + if ((intrstat & ETH_DMA_INTR_STAT_DC1IS) != 0) + { + lpc54_eth_channel_work(priv, 1); + } + + /* Un-lock the network and re-enable Ethernet interrupts */ + + net_unlock(); + up_enable_irq(LPC54_IRQ_ETHERNET); +} + +/**************************************************************************** + * Name: lpc54_eth_interrupt + * + * Description: + * Ethernet interrupt handler + * + * Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * Runs in the context of a the Ethernet interrupt handler. Local + * interrupts are disabled by the interrupt logic. + * + ****************************************************************************/ + +static int lpc54_eth_interrupt(int irq, void *context, void *arg) +{ + struct lpc54_ethdriver_s *priv = (struct lpc54_ethdriver_s *)arg; + + DEBUGASSERT(priv != NULL); + + /* Disable further Ethernet interrupts. Because Ethernet interrupts are + * also disabled if the TX timeout event occurs, there can be no race + * condition here. + */ + + up_disable_irq(LPC54_IRQ_ETHERNET); + + /* Note: We have a race condition which, I believe is handled OK. If + * there is a Tx timeout in place, then that timeout could expire + * anytime and queue additional work to handle the timeout. + */ + + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->eth_irqwork, lpc54_eth_interrupt_work, priv, 0); + return OK; +} + +/**************************************************************************** + * Name: lpc54_pmt_interrupt + * + * Description: + * Ethernet power management interrupt handler + * + * Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * Runs in the context of a the Ethernet PMT interrupt handler. Local + * interrupts are disabled by the interrupt logic. + * + ****************************************************************************/ + +#if 0 /* Not used */ +static int lpc54_pmt_interrupt(int irq, void *context, void *arg) +{ + return OK; +} +#endif + +/**************************************************************************** + * Name: lpc54_mac_interrupt + * + * Description: + * Ethernet MAC interrupt handler + * + * Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * Runs in the context of a the Ethernet MAC handler. Local + * interrupts are disabled by the interrupt logic. + * + ****************************************************************************/ + +#if 0 /* Not used */ +static int lpc54_mac_interrupt(int irq, void *context, void *arg) +{ + return OK; +} +#endif + +/**************************************************************************** + * Name: lpc54_eth_txtimeout_work + * + * Description: + * Perform TX timeout related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * Runs on a worker thread. + * + ****************************************************************************/ + +static void lpc54_eth_txtimeout_work(void *arg) +{ + struct lpc54_ethdriver_s *priv = (struct lpc54_ethdriver_s *)arg; + + /* Lock the network and serialize driver operations if necessary. + * NOTE: Serialization is only required in the case where the driver work + * is performed on an LP worker thread and where more than one LP worker + * thread has been configured. + */ + + net_lock(); + + /* Increment statistics and dump debug info */ + + NETDEV_TXTIMEOUTS(priv->eth_dev); + + /* Then reset the hardware by bringing it down and taking it back up + * again. + */ + + (void)lpc54_eth_ifdown(&priv->eth_dev); + (void)lpc54_eth_ifup(&priv->eth_dev); + + /* Then poll the network for new XMIT data */ + + lpc54_eth_dopoll(priv); + net_unlock(); +} + +/**************************************************************************** + * Name: lpc54_eth_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * Runs in the context of a the timer interrupt handler. Local + * interrupts are disabled by the interrupt logic. + * + ****************************************************************************/ + +static void lpc54_eth_txtimeout_expiry(int argc, wdparm_t arg, ...) +{ + struct lpc54_ethdriver_s *priv = (struct lpc54_ethdriver_s *)arg; + + /* Disable further Ethernet interrupts. This will prevent some race + * conditions with interrupt work. There is still a potential race + * condition with interrupt work that is already queued and in progress. + */ + + up_disable_irq(LPC54_IRQ_ETHERNET); + + /* Schedule to perform the TX timeout processing on the worker thread. */ + + work_queue(ETHWORK, &priv->eth_timeoutwork, lpc54_eth_txtimeout_work, + priv, 0); +} + +/**************************************************************************** + * Name: lpc54_eth_dotimer + * + * Description: + * Check if there are Tx descriptors available and, if so, allocate a Tx + * then perform the normal Tx poll + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static void lpc54_eth_dotimer(struct lpc54_ethdriver_s *priv) +{ + struct lpc54_txring_s *txring0; +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE + struct lpc54_txring_s *txring1; +#endif + + DEBUGASSERT(priv->eth_dev.d_buf == NULL); + + txring0 = &priv->eth_txring[0]; +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE + txring1 = &priv->eth_txring[1]; + + /* We cannot perform the Tx poll now if all of the Tx descriptors for both + * channels are in-use. + */ + + if (txring0->tr_inuse < txring0->tr_ndesc && + txring1->tr_inuse < txring1->tr_ndesc) +#else + /* We cannot perform the Tx poll now if all of the Tx descriptors for this + * channel 0 are in-use. + */ + + if (txring0->tr_inuse < txring0->tr_ndesc) +#endif + { + /* There is a free descriptor in the ring, allocate a new Tx buffer + * to perform the poll. + */ + + priv->eth_dev.d_buf = (uint8_t *)lpc54_pktbuf_alloc(priv); + if (priv->eth_dev.d_buf != NULL) + { + (void)devif_timer(&priv->eth_dev, lpc54_eth_txpoll); + + /* Make sure that the Tx buffer remaining after the poll is + * freed. + */ + + if (priv->eth_dev.d_buf != NULL) + { + lpc54_pktbuf_free(priv, (uint32_t *)priv->eth_dev.d_buf); + priv->eth_dev.d_buf = NULL; + } + } + } +} + +/**************************************************************************** + * Name: lpc54_eth_dopoll + * + * Description: + * Check if there are Tx descriptors available and, if so, allocate a Tx + * then perform the normal Tx poll + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static void lpc54_eth_dopoll(struct lpc54_ethdriver_s *priv) +{ + struct lpc54_txring_s *txring0; +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE + struct lpc54_txring_s *txring1; +#endif + + DEBUGASSERT(priv->eth_dev.d_buf == NULL); + + txring0 = &priv->eth_txring[0]; +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE + txring1 = &priv->eth_txring[1]; + + /* We cannot perform the Tx poll now if all of the Tx descriptors for both + * channels are in-use. + */ + + if (txring0->tr_inuse < txring0->tr_ndesc && + txring1->tr_inuse < txring1->tr_ndesc) +#else + /* We cannot perform the Tx poll now if all of the Tx descriptors for this + * channel 0 are in-use. + */ + + if (txring0->tr_inuse < txring0->tr_ndesc) +#endif + { + /* There is a free descriptor in the ring, allocate a new Tx buffer + * to perform the poll. + */ + + priv->eth_dev.d_buf = (uint8_t *)lpc54_pktbuf_alloc(priv); + if (priv->eth_dev.d_buf != NULL) + { + (void)devif_poll(&priv->eth_dev, lpc54_eth_txpoll); + + /* Make sure that the Tx buffer remaining after the poll is + * freed. + */ + + if (priv->eth_dev.d_buf != NULL) + { + lpc54_pktbuf_free(priv, (uint32_t *)priv->eth_dev.d_buf); + priv->eth_dev.d_buf = NULL; + } + } + } +} + +/**************************************************************************** + * Name: lpc54_eth_poll_work + * + * Description: + * Perform periodic polling from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * Run on a work queue thread. + * + ****************************************************************************/ + +static void lpc54_eth_poll_work(void *arg) +{ + struct lpc54_ethdriver_s *priv = (struct lpc54_ethdriver_s *)arg; + + /* Lock the network and serialize driver operations if necessary. + * NOTE: Serialization is only required in the case where the driver work + * is performed on an LP worker thread and where more than one LP worker + * thread has been configured. + */ + + net_lock(); + + /* Perform the timer poll */ + + lpc54_eth_dotimer(priv); + + /* Setup the watchdog poll timer again */ + + (void)wd_start(priv->eth_txpoll, LPC54_WDDELAY, lpc54_eth_poll_expiry, 1, + (wdparm_t)priv); + net_unlock(); +} + +/**************************************************************************** + * Name: lpc54_eth_poll_expiry + * + * Description: + * Periodic timer handler. Called from the timer interrupt handler. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * Runs in the context of a the timer interrupt handler. Local + * interrupts are disabled by the interrupt logic. + * + ****************************************************************************/ + +static void lpc54_eth_poll_expiry(int argc, wdparm_t arg, ...) +{ + struct lpc54_ethdriver_s *priv = (struct lpc54_ethdriver_s *)arg; + + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->eth_pollwork, lpc54_eth_poll_work, priv, 0); +} + +/**************************************************************************** + * Name: lpc54_eth_ifup + * + * Description: + * NuttX Callback: Bring up the Ethernet interface when an IP address is + * provided + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static int lpc54_eth_ifup(struct net_driver_s *dev) +{ + struct lpc54_ethdriver_s *priv = (struct lpc54_ethdriver_s *)dev->d_private; + uint8_t *mptr; + uintptr_t base; + uint32_t regval; + int ret; + int i; + +#ifdef CONFIG_NET_IPv4 + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); +#endif +#ifdef CONFIG_NET_IPv6 + ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", + dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], + dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], + dev->d_ipv6addr[6], dev->d_ipv6addr[7]); +#endif + + /* Initialize the PHY *****************************************************/ + + ret = lpc54_phy_autonegotiate(priv); + if (ret < 0) + { + nerr("ERROR: lpc54_phy_autonegotiate failed: %d\n", ret); + return ret; + } + + /* Initialize Ethernet DMA ************************************************/ + /* Reset DMA. Resets the logic and all internal registers of the OMA, MTL, + * and MAC. This bit is automatically cleared after the reset operation + * is complete in all Ethernet Block clock domains. + */ + + regval = lpc54_getreg(LPC54_ETH_DMA_MODE); + regval |= ETH_DMA_MODE_SWR; + lpc54_putreg(regval, LPC54_ETH_DMA_MODE); + + /* Wait for the reset bit to be cleared at the completion of the reset */ + + while ((lpc54_getreg(LPC54_ETH_DMA_MODE) & ETH_DMA_MODE_SWR) != 0) + { + } + + /* Set the burst length for each DMA descriptor ring */ + + for (i = 0; i < LPC54_NRINGS; i++) + { + base = LPC54_ETH_DMACH_BASE(i); + lpc54_putreg(LPC54_PBLx8, base + LPC54_ETH_DMACH_CTRL_OFFSET); + + regval = lpc54_getreg(base + LPC54_ETH_DMACH_TX_CTRL_OFFSET); + regval &= ~ETH_DMACH_TX_CTRL_TxPBL_MASK; + regval |= ETH_DMACH_TX_CTRL_TxPBL(LPC54_BURSTLEN); + lpc54_putreg(regval, base + LPC54_ETH_DMACH_TX_CTRL_OFFSET); + + regval = lpc54_getreg(base + LPC54_ETH_DMACH_RX_CTRL_OFFSET); + regval &= ~ETH_DMACH_RX_CTRL_RxPBL_MASK; + regval |= ETH_DMACH_RX_CTRL_RxPBL(LPC54_BURSTLEN); + lpc54_putreg(regval, base + LPC54_ETH_DMACH_RX_CTRL_OFFSET); + } + + /* Initializes the Ethernet MTL *******************************************/ +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE + /* Set the schedule/arbitration for multiple queues */ + + lpc54_putreg(LPC54_MTL_OPMODE_SCHALG | LPC54_MTL_OPMODE_RAA, + LPC54_ETH_MTL_OP_MODE); + + /* Set the Rx queue mapping to DMA channel. */ + + lpc54_putreg(LPC54_QUEUEMAP, LPC54_ETH_MTL_RXQ_DMA_MAP); +#endif + + /* Set transmit queue operation mode + * + * FTQ - Set to flush the queue + * TSF - Depends on configuration + * TXQEN - Queue 0 enabled; queue 1 may be disabled + * TTC - Set to 32 bytes (ignored if TSF set) + * TQS - Set to 2048 bytes + */ + +#ifdef CONFIG_LPC54_ETH_TX_STRFWD + regval = ETH_MTL_TXQ_OP_MODE_TSF; +#else + regval = 0; +#endif + + regval |= ETH_MTL_TXQ_OP_MODE_FTQ | ETH_MTL_TXQ_OP_MODE_TTC_32 | + ETH_MTL_TXQ_OP_MODE_TQS(LPC54_MTL_TXQUEUE_UNITS); + lpc54_putreg(regval | ETH_MTL_TXQ_OP_MODE_TXQEN_ENABLE, + LPC54_ETH_MTL_TXQ_OP_MODE(0)); +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE + lpc54_putreg(regval | ETH_MTL_TXQ_OP_MODE_TXQEN_ENABLE, + LPC54_ETH_MTL_TXQ_OP_MODE(1)); +#else + lpc54_putreg(regval | ETH_MTL_TXQ_OP_MODE_TXQEN_DISABLE, + LPC54_ETH_MTL_TXQ_OP_MODE(1)); +#endif + + /* Set receive receive operation mode + * + * RTC - Set to 64 bytes (ignored if RSF selected) + * FUP - enabled + * FEP - disabled + * RSF - Depends on configuration + * DIS_TCP_EF - Not disabled + * RQS - Set to 2048 bytes + */ + +#ifdef CONFIG_LPC54_ETH_RX_STRFWD + regval = ETH_MTL_RXQ_OP_MODE_RSF; +#else + regval = 0; +#endif + + regval |= ETH_MTL_RXQ_OP_MODE_RTC_64 | ETH_MTL_RXQ_OP_MODE_FUP | + ETH_MTL_RXQ_OP_MODE_RQS(LPC54_MTL_RXQUEUE_UNITS); + lpc54_putreg(regval, LPC54_ETH_MTL_RXQ_OP_MODE(0)); +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE + lpc54_putreg(regval, LPC54_ETH_MTL_RXQ_OP_MODE(1)); + + /* Set the Tx/Rx queue weights. */ + + lpc54_putreg(CONFIG_LPC54_ETH_TXQ0WEIGHT, LPC54_ETH_MTL_TXQ_QNTM_WGHT(0)); + lpc54_putreg(CONFIG_LPC54_ETH_TXQ1WEIGHT, LPC54_ETH_MTL_TXQ_QNTM_WGHT(1)); + + lpc54_putreg(CONFIG_LPC54_ETH_RXQ0WEIGHT, LPC54_ETH_MTL_RXQ_CTRL(0)); + lpc54_putreg(CONFIG_LPC54_ETH_RXQ1WEIGHT, LPC54_ETH_MTL_RXQ_CTRL(1)); +#endif + + /* Initialize the Ethernet MAC ********************************************/ + /* Instantiate the MAC address that application logic should have set in + * the device structure. + * + * "Note that the first DA byte that is received on the MII interface + * corresponds to the LS Byte (bits 7:0) of the MAC address low register. + * For example, if 0x1122 3344 5566 is received (0x11 is the first byte) + * on the MII as the destination address, then the MAC address + * register[47:0] is compared with 0x6655 4433 2211." + */ + + mptr = (uint8_t *)priv->eth_dev.d_mac.ether.ether_addr_octet; + regval = ((uint32_t)mptr[3] << 24) | ((uint32_t)mptr[2] << 16) | + ((uint32_t)mptr[1] << 8) | ((uint32_t)mptr[0]); + lpc54_putreg(regval, LPC54_ETH_MAC_ADDR_LOW); + + regval = ((uint32_t)mptr[5] << 8) | ((uint32_t)mptr[4]); + lpc54_putreg(regval, LPC54_ETH_MAC_ADDR_HIGH); + + /* Set the receive address filter */ + + regval = ETH_MAC_FRAME_FILTER_PCF_NONE; +#ifdef CONFIG_LPC54_ETH_RX_PROMISCUOUS + regval |= ETH_MAC_FRAME_FILTER_PR; +#endif +#ifndef CONFIG_LPC54_ETH_RX_BROADCAST + regval |= ETH_MAC_FRAME_FILTER_DBF; +#endif +#ifdef LPC54_ACCEPT_ALLMULTICAST + regval |= ETH_MAC_FRAME_FILTER_PM; +#endif + lpc54_putreg(regval, LPC54_ETH_MAC_FRAME_FILTER); + +#ifdef CONFIG_LPC54_ETH_FLOWCONTROL + /* Configure flow control */ + + regval = ETH_MAC_RX_FLOW_CTRL_RFE | ETH_MAC_RX_FLOW_CTRL_UP; + lpc54_putreg(regval, LPC54_ETH_MAC_RX_FLOW_CTRL); + + regval = ETH_MAC_TX_FLOW_CTRL_Q_PT(CONFIG_LPC54_ETH_TX_PAUSETIME); + lpc54_putreg(regval, LPC54_ETH_MAC_TX_FLOW_CTRL_Q0); + lpc54_putreg(regval, LPC54_ETH_MAC_TX_FLOW_CTRL_Q1); +#endif + + /* Set the 1uS tick counter*/ + + regval = ETH_MAC_1US_TIC_COUNTR(BOARD_MAIN_CLK / USEC_PER_SEC); + lpc54_putreg(regval, LPC54_ETH_MAC_1US_TIC_COUNTR); + + /* Set the speed and duplex using the values previously determined through + * autonegotiaion. + */ + + regval = ETH_MAC_CONFIG_ECRSFD | ETH_MAC_CONFIG_PS; + +#ifdef CONFIG_LPC54_ETH_8023AS2K + regval |= ENET_MAC_CONFIG_S2KP; +#endif + + if (priv->eth_fullduplex) + { + regval |= ETH_MAC_CONFIG_DM; + } + else + { + regval |= LPC54_MAC_HALFDUPLEX_IPG; + } + + if (priv->eth_100mbps) + { + regval |= ETH_MAC_CONFIG_FES; + } + + lpc54_putreg(regval, LPC54_ETH_MAC_CONFIG); + + /* REVISIT: The User Manual says we need to set the SYSCON sideband flow + * control for each channel. But it is not clear to me what setting that + * refers to nor do I see any such settings in the NXP sample code. + */ + + /* Enable Rx queues */ + + regval = ETH_MAC_RXQ_CTRL0_RXQ0EN_ENABLE | + ETH_MAC_RXQ_CTRL0_RXQ1EN_ENABLE; + lpc54_putreg(regval, LPC54_ETH_MAC_RXQ_CTRL0); + + /* Setup up Ethernet interrupts */ + + regval = LPC54_NORM_INTMASK | LPC54_ABNORM_INTMASK; + lpc54_putreg(regval, LPC54_ETH_DMACH_INT_EN(0)); + lpc54_putreg(regval, LPC54_ETH_DMACH_INT_EN(1)); + + lpc54_putreg(0, LPC54_ETH_MAC_INTR_EN); + + /* Initialize packet buffers */ + + lpc54_pktbuf_initialize(priv); + + /* Initialize descriptors */ + + lpc54_ring_initialize(priv); + + /* Activate DMA on channel 0 */ + + regval = lpc54_getreg(LPC54_ETH_DMACH_RX_CTRL(0)); + regval |= ETH_DMACH_RX_CTRL_SR; + lpc54_putreg(regval, LPC54_ETH_DMACH_RX_CTRL(0)); + + regval = lpc54_getreg(LPC54_ETH_DMACH_TX_CTRL(0)); + regval |= ETH_DMACH_TX_CTRL_ST; + lpc54_putreg(regval, LPC54_ETH_DMACH_TX_CTRL(0)); + + /* Then enable the Rx/Tx */ + + regval = lpc54_getreg(LPC54_ETH_MAC_CONFIG); + regval |= ETH_MAC_CONFIG_RE; + lpc54_putreg(regval, LPC54_ETH_MAC_CONFIG); + + regval |= ETH_MAC_CONFIG_TE; + lpc54_putreg(regval, LPC54_ETH_MAC_CONFIG); + + /* Set and activate a timer process */ + + (void)wd_start(priv->eth_txpoll, LPC54_WDDELAY, lpc54_eth_poll_expiry, 1, + (wdparm_t)priv); + + /* Enable the Ethernet interrupt */ + + priv->eth_bifup = 1; + up_enable_irq(LPC54_IRQ_ETHERNET); + return OK; +} + +/**************************************************************************** + * Name: lpc54_eth_ifdown + * + * Description: + * NuttX Callback: Stop the interface. + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static int lpc54_eth_ifdown(struct net_driver_s *dev) +{ + struct lpc54_ethdriver_s *priv = (struct lpc54_ethdriver_s *)dev->d_private; + irqstate_t flags; + uint32_t regval; + int ret; + + /* Disable the Ethernet interrupt */ + + flags = enter_critical_section(); + up_disable_irq(LPC54_IRQ_ETHERNET); + + /* Cancel the TX poll timer and TX timeout timers */ + + wd_cancel(priv->eth_txpoll); + wd_cancel(priv->eth_txtimeout); + + /* Put the EMAC in its post-reset, non-operational state. This should be + * a known configuration that will guarantee the lpc54_eth_ifup() always + * successfully brings the interface back up. + * + * Reset the Ethernet interface. + */ + + lpc54_reset_eth(); + + /* Set the CSR clock divider */ + + lpc54_set_csrdiv(); + + /* Select MII or RMII mode */ + + regval = lpc54_getreg(LPC54_SYSCON_ETHPHYSEL); + regval &= ~SYSCON_ETHPHYSEL_MASK; +#ifdef CONFIG_LPC54_ETH_MII + regval |= SYSCON_ETHPHYSEL_MII; +#else + regval |= SYSCON_ETHPHYSEL_RMII; +#endif + lpc54_putreg(regval, LPC54_SYSCON_ETHPHYSEL); + + /* Reset the PHY and bring it to an operational state. We must be capable + * of handling PHY ioctl commands while the network is down. + */ + + ret = lpc54_phy_reset(priv); + if (ret < 0) + { + nerr("ERROR: lpc54_phy_reset failed: %d\n", ret); + return ret; + } + + /* Mark the device "down" */ + + priv->eth_bifup = 0; + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: lpc54_eth_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Runs on a work queue thread. + * + ****************************************************************************/ + +static void lpc54_eth_txavail_work(void *arg) +{ + struct lpc54_ethdriver_s *priv = (struct lpc54_ethdriver_s *)arg; + + /* Lock the network and serialize driver operations if necessary. + * NOTE: Serialization is only required in the case where the driver work + * is performed on an LP worker thread and where more than one LP worker + * thread has been configured. + */ + + net_lock(); + + /* Ignore the notification if the interface is not yet up */ + + if (priv->eth_bifup) + { + /* Poll the network for new XMIT data. */ + + lpc54_eth_dopoll(priv); + } + + net_unlock(); +} + +/**************************************************************************** + * Name: lpc54_eth_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static int lpc54_eth_txavail(struct net_driver_s *dev) +{ + struct lpc54_ethdriver_s *priv = (struct lpc54_ethdriver_s *)dev->d_private; + + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->eth_pollwork)) + { + /* Schedule to serialize the poll on the worker thread. */ + + work_queue(ETHWORK, &priv->eth_pollwork, lpc54_eth_txavail_work, priv, 0); + } + + return OK; +} + +/**************************************************************************** + * Name: lpc54_eth_addmac + * + * Description: + * NuttX Callback: Add the specified MAC address to the hardware multicast + * address filtering + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be added + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_IGMP +static int lpc54_eth_addmac(struct net_driver_s *dev, const uint8_t *mac) +{ + /* Unlike other Ethernet hardware, the LPC54xx does not seem to support + * explicit Multicast address filtering as needed for ICMPv6 and for IGMP. + * In these cases, I am simply accepting all multicast packets. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Name: lpc54_eth_rmmac + * + * Description: + * NuttX Callback: Remove the specified MAC address from the hardware multicast + * address filtering + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be removed + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_IGMP +static int lpc54_eth_rmmac(struct net_driver_s *dev, const uint8_t *mac) +{ + /* Unlike other Ethernet hardware, the LPC54xx does not seem to support + * explicit Multicast address filtering as needed for ICMPv6 and for IGMP. + * In these cases, I am simply accepting all multicast packets. + */ + + return -ENOSYS; +} +#endif + +/**************************************************************************** + * Name: lpc54_eth_ioctl + * + * Description: + * Handle network IOCTL commands directed to this device. + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * cmd - The IOCTL command + * arg - The argument for the IOCTL command + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NETDEV_IOCTL +static int lpc54_eth_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg) +{ + struct lpc54_ethdriver_s *priv = (struct lpc54_ethdriver_s *)dev->d_private; + int ret; + + /* Decode and dispatch the driver-specific IOCTL command */ + + switch (cmd) + { + case SIOCGMIIPHY: /* Get MII PHY address */ + { + struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); + req->phy_id = CONFIG_LPC54_ETH_PHYADDR; + ret = OK; + } + break; + + case SIOCGMIIREG: /* Get register from MII PHY */ + { + struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); + req->val_out = lpc54_phy_read(priv, req->reg_num); + ret = OK + } + break; + + case SIOCSMIIREG: /* Set register in MII PHY */ + { + struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); + lpc54_phy_write(priv, req->reg_num, req->val_in); + ret = OK + } + break; + + default: + nerr("ERROR: Unrecognized IOCTL command: %d\n", command); + return -ENOTTY; /* Special return value for this case */ + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: lpc54_pktbuf_initialize + * + * Description: + * Initialize packet buffers my placing all of the pre-allocated packet + * buffers into a free list. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_pktbuf_initialize(struct lpc54_ethdriver_s *priv) +{ + uint32_t *pktbuf; + int i; + + for (i = 0, pktbuf = g_prealloc_buffers; + i < LPC54_NBUFFERS; + i++, pktbuf += LPC54_BUFFER_WORDS) + { + sq_addlast((sq_entry_t *)pktbuf, &priv->eth_freebuf); + } +} + +/**************************************************************************** + * Name: lpc54_pktbuf_alloc + * + * Description: + * Allocate one packet buffer by removing it from the free list. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * A pointer to the allocated packet buffer on succes; NULL is returned if + * there are no available packet buffers. + * + * Assumptions: + * The network must be locked. Mutually exclusive access to the free list + * is maintained by locking the network. + * + ****************************************************************************/ + +static inline uint32_t *lpc54_pktbuf_alloc(struct lpc54_ethdriver_s *priv) +{ + return (uint32_t *)sq_remfirst(&priv->eth_freebuf); +} + +/**************************************************************************** + * Name: lpc54_pktbuf_free + * + * Description: + * Allocate one packet buffer by removing it from the free list. + * + * Parameters: + * priv - Reference to the driver state structure + * pktbuf - The packet buffer to be freed + * + * Returned Value: + * None + * + * Assumptions: + * The network must be locked. Mutually exclusive access to the free list + * is maintained by locking the network. + * + ****************************************************************************/ + +static inline void lpc54_pktbuf_free(struct lpc54_ethdriver_s *priv, + uint32_t *pktbuf) +{ + sq_addlast((sq_entry_t *)pktbuf, &priv->eth_freebuf); +} + +/**************************************************************************** + * Name: lpc54_txring_initialize + * + * Description: + * Initialize one Tx descriptor ring. + * + * Parameters: + * priv - Reference to the driver state structure + * chan - Channel being initialized + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_txring_initialize(struct lpc54_ethdriver_s *priv, + unsigned int chan) +{ + struct lpc54_txring_s *txring; + struct enet_txdesc_s *txdesc; + uint32_t regval; + int i; + + txring = &priv->eth_txring[chan]; + txdesc = txring->tr_desc; + + /* Set the word-aligned Tx descriptor start/tail pointers. */ + + regval = (uint32_t)txdesc; + lpc54_putreg(regval, LPC54_ETH_DMACH_TXDESC_LIST_ADDR(chan)); + + regval += txring->tr_ndesc * sizeof(struct enet_txdesc_s); + lpc54_putreg(regval, LPC54_ETH_DMACH_TXDESC_TAIL_PTR(chan)); + + /* Set the Tx ring length */ + + regval = ETH_DMACH_TXDESC_RING_LENGTH(txring->tr_ndesc); + lpc54_putreg(regval, LPC54_ETH_DMACH_TXDESC_RING_LENGTH(chan)); + + /* Inituialize the Tx desriptors . */ + + for (i = 0; i < txring->tr_ndesc; i++, txdesc++) + { + txdesc->buffer1 = 0; + txdesc->buffer2 = 0; + txdesc->buflen = ETH_TXDES2_IOC; + txdesc->ctrlstat = 0; + } +} + +/**************************************************************************** + * Name: lpc54_rxring_initialize + * + * Description: + * Initialize one Rx descriptor ring. + * + * Parameters: + * priv - Reference to the driver state structure + * chan - Channel being initialized + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_rxring_initialize(struct lpc54_ethdriver_s *priv, + unsigned int chan) +{ + struct lpc54_rxring_s *rxring; + struct enet_rxdesc_s *rxdesc; + uint32_t regval; + int i; + + rxring = &priv->eth_rxring[chan]; + rxdesc = rxring->rr_desc; + + /* Set the word-aligned Rx descriptor start/tail pointers. */ + + regval = (uint32_t)rxdesc; + lpc54_putreg(regval, LPC54_ETH_DMACH_RXDESC_LIST_ADDR(chan)); + + regval += rxring->rr_ndesc * sizeof(struct enet_rxdesc_s); + lpc54_putreg(regval, LPC54_ETH_DMACH_RXDESC_TAIL_PTR(chan)); + + /* Set the Rx ring length */ + + regval = ETH_DMACH_RXDESC_RING_LENGTH(rxring->rr_ndesc); + lpc54_putreg(regval, LPC54_ETH_DMACH_RXDESC_RING_LENGTH(chan)); + + /* Set the receive buffer size (in words) in the Rx control register */ + + regval = lpc54_getreg(LPC54_ETH_DMACH_RX_CTRL(chan)); + regval &= ~ETH_DMACH_RX_CTRL_RBSZ_MASK; + regval |= ETH_DMACH_RX_CTRL_RBSZ(LPC54_BUFFER_SIZE >> 2); + lpc54_putreg(regval, LPC54_ETH_DMACH_RX_CTRL(chan)); + + /* Initialize the Rx descriptor ring. */ + + regval = ETH_RXDES3_BUF1V | ETH_RXDES3_IOC | ETH_RXDES3_OWN; +#if LPC54_BUFFER_SIZE > LPC54_BUFFER_MAX + regval |= ETH_RXDES3_BUF2V; +#endif + + for (i = 0; i < rxring->rr_ndesc; i++, rxdesc++) + { + /* Allocate the first Rx packet buffer */ + + rxdesc->buffer1 = (uint32_t)lpc54_pktbuf_alloc(priv); + DEBUGASSERT(rxdesc->buffer1 != 0); + (rxring->rr_buffers)[i] = (uint32_t *)rxdesc->buffer1; + +#if LPC54_BUFFER_SIZE > LPC54_BUFFER_MAX + /* Configure the second part of a large packet buffer as buffer2 */ + + rxdesc->buffer2 = rxdesc->buffer1 + LPC54_BUFFER_MAX; +#else + /* The second buffer is not used */ + + rxdesc->buffer2 = 0; +#endif + + /* Buffer1 (and maybe 2) valid, interrupt on completion, owned by DMA. */ + + rxdesc->ctrl = regval; + } +} + +/**************************************************************************** + * Name: lpc54_ring_initialize + * + * Description: + * Initialize the Rx and Tx rings for every channel. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_ring_initialize(struct lpc54_ethdriver_s *priv) +{ + /* Initialize ring descriptions */ + + memset(priv->eth_txring, 0, LPC54_NRINGS * sizeof(struct lpc54_txring_s)); + memset(priv->eth_rxring, 0, LPC54_NRINGS * sizeof(struct lpc54_rxring_s)); + + /* Initialize channel 0 rings */ + + memset(g_txbuffers0, 0, CONFIG_LPC54_ETH_NTXDESC0 * sizeof(uint32_t *)); + memset(g_rxbuffers0, 0, CONFIG_LPC54_ETH_NRXDESC0 * sizeof(uint32_t *)); + + priv->eth_txring[0].tr_desc = g_ch0_txdesc; + priv->eth_txring[0].tr_ndesc = CONFIG_LPC54_ETH_NTXDESC0; + priv->eth_txring[0].tr_buffers = g_txbuffers0; + lpc54_txring_initialize(priv, 0); + + priv->eth_rxring[0].rr_desc = g_ch0_rxdesc; + priv->eth_rxring[0].rr_ndesc = CONFIG_LPC54_ETH_NRXDESC0; + priv->eth_rxring[0].rr_buffers = g_rxbuffers0; + lpc54_rxring_initialize(priv, 0); + +#ifdef CONFIG_LPC54_ETH_MULTIQUEUE + /* Initialize channel 1 rings */ + + memset(g_txbuffers1, 0, CONFIG_LPC54_ETH_NTXDESC1 * sizeof(uint32_t *)); + memset(g_rxbuffers1, 0, CONFIG_LPC54_ETH_NRXDESC1 * sizeof(uint32_t *)); + + priv->eth_txring[1].tr_desc = g_ch1_txdesc; + priv->eth_txring[1].tr_ndesc = CONFIG_LPC54_ETH_NTXDESC1; + priv->eth_txring[1].tr_buffers = g_txbuffers1; + lpc54_txring_initialize(priv, 1); + + priv->eth_rxring[1].rr_desc = g_ch1_rxdesc; + priv->eth_rxring[1].rr_ndesc = CONFIG_LPC54_ETH_NRXDESC1; + priv->eth_rxring[1].rr_buffers = g_rxbuffers1; + lpc54_rxring_initialize(priv, 1); +#endif +} + +/**************************************************************************** + * Name: lpc54_set_csrdiv + * + * Description: + * Set the CSR clock divider. The MDC clock derives from the divided down + * CSR clock (aka core clock or main clock). + * + * Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_set_csrdiv(void) +{ + uint32_t srcclk = BOARD_MAIN_CLK / 1000000; + uint32_t regval; + + regval = lpc54_getreg(LPC54_ETH_MAC_MDIO_ADDR); + regval &= ~ETH_MAC_MDIO_ADDR_CR_MASK; + + if (srcclk < 35) + { + regval |= ETH_MAC_MDIO_ADDR_CR_DIV16; /* CSR=20-35 MHz; MDC=CSR/16 */ + } + else if (srcclk < 60) + { + regval |= ETH_MAC_MDIO_ADDR_CR_DIV26; /* CSR=35-60 MHz; MDC=CSR/26 */ + } + else if (srcclk < 100) + { + regval |= ETH_MAC_MDIO_ADDR_CR_DIV42; /* CSR=60-100 MHz; MDC=CSR/42 */ + } + else /* if (srcclk < 150) */ + { + regval |= ETH_MAC_MDIO_ADDR_CR_DIV62; /* CSR=100-150 MHz; MDC=CSR/62 */ + } + + lpc54_putreg(regval, LPC54_ETH_MAC_MDIO_ADDR); +} + +/**************************************************************************** + * Name: lpc54_phy_read + * + * Description: + * Read the content from one PHY register. + * + * Parameters: + * priv - Reference to the driver state structure + * phyreg - The 5-bit PHY address to read + * + * Returned Value: + * The 16-bit value read from the specified PHY register + * + ****************************************************************************/ + +static uint16_t lpc54_phy_read(struct lpc54_ethdriver_s *priv, + uint8_t phyreg) +{ + uint32_t regval; + + /* Set the MII read command. */ + + regval = lpc54_getreg(LPC54_ETH_MAC_MDIO_ADDR); + regval &= ETH_MAC_MDIO_ADDR_CR_MASK; + regval |= ETH_MAC_MDIO_ADDR_MOC_READ | ETH_MAC_MDIO_ADDR_RDA(phyreg) | + ETH_MAC_MDIO_ADDR_PA(CONFIG_LPC54_ETH_PHYADDR); + lpc54_putreg(regval, LPC54_ETH_MAC_MDIO_ADDR); + + /* Initiate the read */ + + regval |= ETH_MAC_MDIO_ADDR_MB; + lpc54_putreg(regval, LPC54_ETH_MAC_MDIO_ADDR); + + /* Wait until the SMI is no longer busy with the read */ + + while ((lpc54_getreg(LPC54_ETH_MAC_MDIO_ADDR) & ETH_MAC_MDIO_ADDR_MB) != 0) + { + } + + return (uint16_t)lpc54_getreg(LPC54_ETH_MAC_MDIO_DATA); +} + +/**************************************************************************** + * Name: lpc54_phy_write + * + * Description: + * Write a new value to of one PHY register. + * + * Parameters: + * priv - Reference to the driver state structure + * phyreg - The 5-bit PHY address to write + * phyval - The 16-bit value to write to the PHY register + * + * Returned Value: + * The 16-bit value read from the specified PHY register + * + ****************************************************************************/ + +static void lpc54_phy_write(struct lpc54_ethdriver_s *priv, + uint8_t phyreg, uint16_t phyval) +{ + uint32_t regval; + + /* Set the MII write command. */ + + regval = lpc54_getreg(LPC54_ETH_MAC_MDIO_ADDR); + regval &= ETH_MAC_MDIO_ADDR_CR_MASK; + regval |= ETH_MAC_MDIO_ADDR_MOC_WRITE | ETH_MAC_MDIO_ADDR_RDA(phyreg) | + ETH_MAC_MDIO_ADDR_PA(CONFIG_LPC54_ETH_PHYADDR); + lpc54_putreg(regval, LPC54_ETH_MAC_MDIO_ADDR); + + /* Set the write data */ + + lpc54_putreg((uint32_t)phyval, LPC54_ETH_MAC_MDIO_DATA); + + /* Initiate the write */ + + regval |= ETH_MAC_MDIO_ADDR_MB; + lpc54_putreg(regval, LPC54_ETH_MAC_MDIO_ADDR); + + /* Wait until the SMI is no longer busy with the write */ + + while ((lpc54_getreg(LPC54_ETH_MAC_MDIO_ADDR) & ETH_MAC_MDIO_ADDR_MB) != 0) + { + } +} + +/**************************************************************************** + * Name: lpc54_phy_linkstatus + * + * Description: + * Read the MII status register and return tru if the link is up. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * true if the link is up + * + ****************************************************************************/ + +static inline bool lpc54_phy_linkstatus(struct lpc54_ethdriver_s *priv) +{ + /* Read the status register and return tru of the linkstatus bit is set. */ + + return ((lpc54_phy_read(priv, MII_MSR) & MII_MSR_LINKSTATUS) != 0); +} + +/**************************************************************************** + * Name: lpc54_phy_autonegotiate + * + * Description: + * Initialize the PHY. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +static int lpc54_phy_autonegotiate(struct lpc54_ethdriver_s *priv) +{ + volatile int32_t timeout; + uint16_t phyval; + + /* Advertise our capabilities. */ + + phyval = (MII_ADVERTISE_CSMA | MII_ADVERTISE_10BASETXHALF | + MII_ADVERTISE_10BASETXFULL | MII_ADVERTISE_100BASETXHALF | + MII_ADVERTISE_100BASETXFULL); + lpc54_phy_write(priv, MII_ADVERTISE, phyval); + + /* Start Auto negotiation and wait until auto negotiation completion */ + + phyval = (MII_MCR_ANENABLE | MII_MCR_ANRESTART); + lpc54_phy_write(priv, MII_MCR, phyval); + + /* Wait for the completion of autonegotiation. */ + +#ifdef CONFIG_ETH0_PHY_LAN8720 + timeout = LPC54_PHY_TIMEOUT; + do + { + if (timeout-- <= 0) + { + nerr("ERROR: Autonegotion timed out\n"); + return -ETIMEDOUT; + } + + phyval = lpc54_phy_read(priv, MII_LAN8720_SCSR); + + } + while ((phyval & MII_LAN8720_SPSCR_ANEGDONE) == 0); +#else +# error Unrecognized PHY +#endif + + /* Wait for the link to be in the UP state */ + + timeout = LPC54_PHY_TIMEOUT; + do + { + if (timeout-- <= 0) + { + nerr("ERROR: Link status UP timed out\n"); + return -ETIMEDOUT; + } + } + while (!lpc54_phy_linkstatus(priv)); + + /* Get the negotiate PHY link mode. */ + +#ifdef CONFIG_ETH0_PHY_LAN8720 + /* Read the LAN8720 SPCR register. */ + + phyval = lpc54_phy_read(priv, MII_LAN8720_SCSR); + priv->eth_fullduplex = ((phyval & MII_LAN8720_SPSCR_DUPLEX) != 0); + priv->eth_100mbps = ((phyval & MII_LAN8720_SPSCR_100MBPS) != 0); +#else +# error Unrecognized PHY +#endif + + return OK; +} + +/**************************************************************************** + * Name: lpc54_phy_reset + * + * Description: + * Reset the PHY and bring it to the operational status + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +static int lpc54_phy_reset(struct lpc54_ethdriver_s *priv) +{ + volatile int32_t timeout; + uint16_t phyid1; + uint16_t phyval; + + /* Read and verify the PHY ID1 register */ + + timeout = LPC54_PHY_TIMEOUT; + do + { + if (timeout-- <= 0) + { + nerr("ERROR: PHY start up timed out\n"); + return -ETIMEDOUT; + } + + phyid1 = lpc54_phy_read(priv, MII_PHYID1); + } + while (phyid1 != LPC54_PHYID1_VAL); + + /* Reset PHY and wait until completion. */ + + lpc54_phy_write(priv, MII_MCR, MII_MCR_RESET); + + timeout = LPC54_PHY_TIMEOUT; + do + { + if (timeout-- <= 0) + { + nerr("ERROR: PHY reset timed out\n"); + return -ETIMEDOUT; + } + + phyval = lpc54_phy_read(priv, MII_MCR); + } + while ((phyval & MII_MCR_RESET) != 0); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_netinitialize + * + * Description: + * Initialize the Ethernet controller and driver. + * + * This is the "standard" network initialization logic called from the + * low-level initialization logic in up_initialize.c. + * + * Parameters: + * intf - In the case where there are multiple EMACs, this value + * identifies which EMAC is to be initialized. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * Called early in initialization before multi-tasking is initiated. + * + ****************************************************************************/ + +int up_netinitialize(int intf) +{ + struct lpc54_ethdriver_s *priv; + int ret; + + /* Get the interface structure associated with this interface number. */ + + DEBUGASSERT(intf == 0); + priv = &g_ethdriver; + + /* Attach the three Ethernet-related IRQs to the handlers */ + + ret = irq_attach(LPC54_IRQ_ETHERNET, lpc54_eth_interrupt, priv); + if (ret < 0) + { + /* We could not attach the ISR to the interrupt */ + + nerr("ERROR: irq_attach failed: %d\n", ret); + return -EAGAIN; + } + +#if 0 /* Not used */ + ret = irq_attach(LPC54_IRQ_ETHERNETPMT, lpc54_pmt_interrupt, priv); + if (ret < 0) + { + /* We could not attach the ISR to the interrupt */ + + nerr("ERROR: irq_attach for PMT failed: %d\n", ret); + return -EAGAIN; + } + + ret = irq_attach(LPC54_IRQ_ETHERNETMACLP, lpc54_mac_interrupt, priv); + if (ret < 0) + { + /* We could not attach the ISR to the interrupt */ + + nerr("ERROR: irq_attach for MAC failed: %d\n", ret); + return -EAGAIN; + } +#endif + + /* Initialize the driver structure */ + + memset(priv, 0, sizeof(struct lpc54_ethdriver_s)); + priv->eth_dev.d_ifup = lpc54_eth_ifup; /* I/F up (new IP address) callback */ + priv->eth_dev.d_ifdown = lpc54_eth_ifdown; /* I/F down callback */ + priv->eth_dev.d_txavail = lpc54_eth_txavail; /* New TX data callback */ +#ifdef CONFIG_NET_IGMP + priv->eth_dev.d_addmac = lpc54_eth_addmac; /* Add multicast MAC address */ + priv->eth_dev.d_rmmac = lpc54_eth_rmmac; /* Remove multicast MAC address */ +#endif +#ifdef CONFIG_NETDEV_IOCTL + priv->eth_dev.d_ioctl = lpc54_eth_ioctl; /* Handle network IOCTL commands */ +#endif + priv->eth_dev.d_private = (void *)&g_ethdriver; /* Used to recover private state from dev */ + + /* Create a watchdog for timing polling for and timing of transmissions */ + + priv->eth_txpoll = wd_create(); /* Create periodic poll timer */ + priv->eth_txtimeout = wd_create(); /* Create TX timeout timer */ + + DEBUGASSERT(priv->eth_txpoll != NULL && priv->eth_txtimeout != NULL); + + /* Configure GPIO pins to support Ethernet */ + /* Common MIIM interface */ + + lpc54_gpio_config(GPIO_ENET_MDIO); /* Ethernet MIIM data input and output */ + lpc54_gpio_config(GPIO_ENET_MDC); /* Ethernet MIIM clock */ + +#ifdef CONFIG_LPC54_ETH_MII + /* MII interface */ + + lpc54_gpio_config(GPIO_ENET_RXD0); /* Ethernet receive data 0-3 */ + lpc54_gpio_config(GPIO_ENET_RXD1); + lpc54_gpio_config(GPIO_ENET_RXD2); + lpc54_gpio_config(GPIO_ENET_RXD3); + lpc54_gpio_config(GPIO_ENET_TXD0); /* Ethernet transmit data 0-3 */ + lpc54_gpio_config(GPIO_ENET_TXD1); + lpc54_gpio_config(GPIO_ENET_TXD2); + lpc54_gpio_config(GPIO_ENET_TXD3); + lpc54_gpio_config(GPIO_ENET_COL); /* Ethernet collision detect */ + lpc54_gpio_config(GPIO_ENET_CRS); /* Ethernet carrier sense */ + lpc54_gpio_config(GPIO_ENET_RX_ER); /* Ethernet transmit error */ + lpc54_gpio_config(GPIO_ENET_TX_CLK); /* Ethernet transmit clock */ + lpc54_gpio_config(GPIO_ENET_RX_CLK); /* Ethernet receive clock */ + lpc54_gpio_config(GPIO_ENET_TX_ER); /* Ethernet receive error */ + lpc54_gpio_config(GPIO_ENET_TX_EN); /* Ethernet transmit enable */ +#else + /* RMII interface. + * + * REF_CLK may be available in some implementations. Clocking from + * PHY appears to be necessary for DMA reset operations. + * RX_ER is optional on switches. + */ + + lpc54_gpio_config(GPIO_ENET_RXD0); /* Ethernet receive data 0-1 */ + lpc54_gpio_config(GPIO_ENET_RXD1); + lpc54_gpio_config(GPIO_ENET_TXD0); /* Ethernet transmit data 0-1 */ + lpc54_gpio_config(GPIO_ENET_TXD1); + lpc54_gpio_config(GPIO_ENET_RX_DV); /* Ethernet receive data valid */ + lpc54_gpio_config(GPIO_ENET_TX_EN); /* Ethernet transmit data enable */ + lpc54_gpio_config(GPIO_ENET_REF_CLK); /* PHY reference clock */ +#endif + + /* Enable clocking to the Ethernet peripheral */ + + lpc54_eth_enableclk(); + + /* Put the interface in the down state. This amounts to resetting the + * device by calling lpc54_eth_ifdown(). + */ + + ret = lpc54_eth_ifdown(&priv->eth_dev); + if (ret < 0) + { + nerr("ERROR: lpc54_eth_ifdown failed: %d\n", ret); + goto errout_with_clock; + } + + /* Register the device with the OS so that socket IOCTLs can be performed */ + + ret = netdev_register(&priv->eth_dev, NET_LL_ETHERNET); + if (ret < 0) + { + nerr("ERROR: netdev_register failed: %d\n", ret); + goto errout_with_clock; + } + + return OK; + +errout_with_clock: + lpc54_eth_disableclk(); + return ret; +} + +#endif /* CONFIG_LPC54_ETHERNET */ diff --git a/arch/arm/src/lpc54xx/lpc54_gpio.c b/arch/arm/src/lpc54xx/lpc54_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..b7794efcca9a212962b19c0e24d15f6d5d33b5d5 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_gpio.c @@ -0,0 +1,458 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_gpio.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "chip/lpc54_iocon.h" +#include "chip/lpc54_gpio.h" +#include "lpc54_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Default input pin configuration */ + +#define PORTPIN_MASK (GPIO_PORT_MASK|GPIO_PIN_MASK) + +/* Pin types */ + +#define PIN_TYPE_UNKNOWN 0 +#define PIN_TYPED (1 << 0) +#define PIN_TYPEI (1 << 1) +#define PIN_TYPEA (1 << 2) + +/* Helpers */ + +#define GPIO_PORTPIN_MASKGPIO_PORTPIN_MASK (GPIO_PORT_MASK | GPIO_PIN_MASK) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint32_t g_typed_mask[LPC54_GPIO_NPORTS] = +{ + IOCON_PIO0_TYPED_MASK, + IOCON_PIO1_TYPED_MASK, + IOCON_PIO2_TYPED_MASK, + IOCON_PIO3_TYPED_MASK, + IOCON_PIO4_TYPED_MASK, + IOCON_PIO5_TYPED_MASK, +}; + +static const uint32_t g_typei_mask[LPC54_GPIO_NPORTS] = +{ + IOCON_PIO0_TYPEI_MASK, + IOCON_PIO1_TYPEI_MASK, + IOCON_PIO2_TYPEI_MASK, + IOCON_PIO3_TYPEI_MASK, + IOCON_PIO4_TYPEI_MASK, + IOCON_PIO5_TYPEI_MASK, +}; + +static const uint32_t g_typea_mask[LPC54_GPIO_NPORTS] = +{ + IOCON_PIO0_TYPEA_MASK, + IOCON_PIO1_TYPEA_MASK, + IOCON_PIO2_TYPEA_MASK, + IOCON_PIO3_TYPEA_MASK, + IOCON_PIO4_TYPEA_MASK, + IOCON_PIO5_TYPEA_MASK, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_pintype + * + * Description: + * Get the LPC548x IOCON register mask. + * + * Type D: FUNC MODE INVERT DIGIMODE FILTEROFF SLEW OD + * Type I: FUNC I2CSLEW INVERT DIGIMODE FILTEROFF I2CDRIVE I2CFILTEROFF + * Type A: FUNC MODE INVERT DIGIMODE FILTEROFF OD + * + ****************************************************************************/ + +static uint8_t lpc54_pintype(unsigned int port, unsigned int pin) +{ + uint8_t pintype = 0; + + if ((g_typed_mask[port] & (1 << pin)) != 0) + { + pintype |= PIN_TYPED; + } + + if ((g_typei_mask[port] & (1 << pin)) != 0) + { + pintype |= PIN_TYPEI; + } + + if ((g_typea_mask[port] & (1 << pin)) != 0) + { + pintype |= PIN_TYPEA; + } + + return pintype; +} + +/**************************************************************************** + * Name: lpc54_setpinfunction + * + * Description: + * Select pin function. + * + ****************************************************************************/ + +static void lpc54_setpinfunction(unsigned int port, unsigned int pin, + unsigned int value) +{ + uintptr_t regaddr; + uint32_t regval; + + regaddr = LPC54_IOCON_PIO(port, pin); + regval = getreg32(regaddr); + regval &= ~IOCON_FUNC_MASK; + regval |= (value << IOCON_FUNC_SHIFT); + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: lpc54_gpio_input + * + * Description: + * Configure a GPIO input pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline void lpc54_gpio_input(unsigned int port, unsigned int pin) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t pinmask = (1 << pin); + + /* Set as input */ + + regaddr = LPC54_GPIO_DIR(port); + regval = getreg32(regaddr); + regval &= ~pinmask; + putreg32(regval, regaddr); + + /* Configure as GPIO */ + + lpc54_setpinfunction(port, pin, IOCON_FUNC_GPIO); +} + +/**************************************************************************** + * Name: lpc54_gpio_output + * + * Description: + * Configure a GPIO output pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline void lpc54_gpio_output(lpc54_pinset_t cfgset, + unsigned int port, unsigned int pin) +{ + uintptr_t regaddr; + uint32_t regval; + + /* Configure the pin as an output */ + + regaddr = LPC54_GPIO_DIR(port); + regval = getreg32(regaddr); + regval |= (1 << pin); + putreg32(regval, regaddr); + + /* Set the initial value of the output. Apparently this cannot be done + * before cofiguring the pin as an output. I don't see anyway to avoid + * glitch. + */ + + lpc54_gpio_write(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO)); +} + +/**************************************************************************** + * Name: lpc54_gpio_alternate + * + * Description: + * Configure a GPIO alternate function pin based on bit-encoded description + * of the pin. + * + ****************************************************************************/ + +static inline void lpc54_gpio_alternate(lpc54_pinset_t cfgset, + unsigned int port, unsigned int pin, + uint32_t alt) +{ + /* Select the alternate pin function */ + + lpc54_setpinfunction(port, pin, alt); +} + +/**************************************************************************** + * Name: lpc54_gpio_iocon + * + * Description: + * Configure the pin IOCON register. + * + ****************************************************************************/ + +static void lpc54_gpio_iocon(lpc54_pinset_t cfgset, unsigned int port, + unsigned int pin) +{ + uintptr_t regaddr; + uint32_t iocon; + uint8_t pintype; + + /* Configure pins for supported pin type(s): + * + * Type D: FUNC MODE INVERT DIGIMODE FILTEROFF SLEW OD + * Type I: FUNC I2CSLEW INVERT DIGIMODE FILTEROFF I2CDRIVE I2CFILTEROFF + * Type A: FUNC MODE INVERT DIGIMODE FILTEROFF OD + */ + + pintype = lpc54_pintype(port, pin); + iocon = IOCON_FUNC(IOCON_FUNC_GPIO); + + /* MODE: Type D and A only */ + + if ((pintype & (PIN_TYPED | PIN_TYPEA)) != 0) + { + uint32_t mode = (cfgset & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT; + iocon |= mode << IOCON_MODE_SHIFT; + } + + /* I2CSLEW: Type I only */ + + if ((pintype & PIN_TYPEI) != 0 && (cfgset & GPIO_I2CSLEW_MASK) != 0) + { + iocon |= IOCON_I2CSLEW_GPIO; + } + + /* INVERT: All types */ + + if ((cfgset & GPIO_INVERT_MASK) != 0) + { + iocon |= IOCON_INVERT; + } + + /* DIGIMODE: All types */ + + if ((cfgset & GPIO_DIGIMODE_MASK) != 0) + { + iocon |= IOCON_DIGIMODE_DIGITAL; + } + + /* FILTEROFF: All types */ + + if ((cfgset & GPIO_FILTEROFF_MASK) != 0) + { + iocon |= IOCON_FILTEROFF_OFF; + } + + /* SLEW: Type D only */ + + if ((pintype & PIN_TYPED) != 0 && (cfgset & GPIO_SLEW_MASK) != 0) + { + iocon |= IOCON_SLEW_FAST; + } + + /* I2CDRIVE: Type I only */ + + if ((pintype & PIN_TYPEI) != 0 && (cfgset & GPIO_I2CDRIVE_MASK) != 0) + { + iocon |= IOCON_I2CDRIVE_HIGH; + } + + /* OD: Type D and A only */ + + if ((pintype & (PIN_TYPED | PIN_TYPEA)) != 0 && + (cfgset & GPIO_OD_MASK) != 0) + { + iocon |= IOCON_OD_OPENDRAIN; + } + + /* I2CFILTEROFF: Type I only */ + + if ((pintype & PIN_TYPEI) != 0 && (cfgset & GPIO_I2CFILTEROFF_MASK) != 0) + { + iocon |= IOCON_I2CFILTEROFF_OFF; + } + + /* Now write the IOCON settings */ + + regaddr = LPC54_IOCON_PIO(port, pin); + putreg32(iocon, regaddr); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_gpio_config + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int lpc54_gpio_config(lpc54_pinset_t cfgset) +{ + unsigned int port; + unsigned int pin; + + /* Verify that this hardware supports the select GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port < LPC54_GPIO_NPORTS) + { + /* Get the pin number and select the port configuration register for + * that pin. + */ + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* First, configure the port as a generic input so that we have a + * known starting point and consistent behavior during the re- + * configuration. + */ + + lpc54_gpio_input(port, pin); + + /* Set the IOCON bits */ + + lpc54_gpio_iocon(cfgset, port, pin); + + /* Handle according to pin function */ + + switch (cfgset & GPIO_FUNC_MASK) + { + case GPIO_INPUT: /* GPIO input pin */ + break; /* Already configured */ + +#ifdef CONFIG_LPC54_GPIOIRQ + case GPIO_INTFE: /* GPIO interrupt falling edge */ + case GPIO_INTRE: /* GPIO interrupt rising edge */ + case GPIO_INTBOTH: /* GPIO interrupt both edges */ + case GPIO_INTLOW: /* GPIO interrupt low level */ + case GPIO_INTHIGH: /* GPIO interrupt high level */ + lpc54_gpio_interrupt(cfgset); + break; +#endif + + case GPIO_OUTPUT: /* GPIO outpout pin */ + lpc54_gpio_output(cfgset, port, pin); + break; + + case GPIO_ALT1: /* Alternate function 1 */ + lpc54_gpio_alternate(cfgset, port, pin, IOCON_FUNC_ALT1); + break; + + case GPIO_ALT2: /* Alternate function 2 */ + lpc54_gpio_alternate(cfgset, port, pin, IOCON_FUNC_ALT2); + break; + + case GPIO_ALT3: /* Alternate function 3 */ + lpc54_gpio_alternate(cfgset, port, pin, IOCON_FUNC_ALT3); + break; + + case GPIO_ALT4: /* Alternate function 4 */ + lpc54_gpio_alternate(cfgset, port, pin, IOCON_FUNC_ALT4); + break; + + case GPIO_ALT5: /* Alternate function 5 */ + lpc54_gpio_alternate(cfgset, port, pin, IOCON_FUNC_ALT5); + break; + + case GPIO_ALT6: /* Alternate function 6 */ + lpc54_gpio_alternate(cfgset, port, pin, IOCON_FUNC_ALT6); + break; + + case GPIO_ALT7: /* Alternate function 7 */ + lpc54_gpio_alternate(cfgset, port, pin, IOCON_FUNC_ALT7); + break; + + default: + return -EINVAL; + } + } + + return OK; +} + +/**************************************************************************** + * Name: lpc54_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void lpc54_gpio_write(lpc54_pinset_t pinset, bool value) +{ + unsigned int portpin = pinset & PORTPIN_MASK; + putreg8((uint32_t)value, LPC54_GPIO_B(portpin)); +} + +/**************************************************************************** + * Name: lpc54_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool lpc54_gpio_read(lpc54_pinset_t pinset) +{ + unsigned int portpin = pinset & PORTPIN_MASK; + return (bool)getreg8(LPC54_GPIO_B(portpin)); +} diff --git a/arch/arm/src/lpc54xx/lpc54_gpio.h b/arch/arm/src/lpc54xx/lpc54_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..8f44f82c86aaafcc85bee7823ed838e411a4ca37 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_gpio.h @@ -0,0 +1,364 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/lpc54_gpio.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_GPIO_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +#include + +#include "chip/lpc54_gpio.h" +#include "chip/lpc54_iocon.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Bit-encoded input to lpc54_gpio_config() ******************************************/ + +/* 32-Bit Encoding: .... .... TTTT TTTT FFFF FMMV PPPN NNNN + * + * Special Pin Functions: TTTT TTTT + * Pin Function: FFFF F + * Pin Mode bits: MM + * Initial value: V (output pins) + * Port number: PPP (0-5) + * Pin number: NNNNN (0-31) + */ + +/* Special Pin Functions: + * For pins that have ADC/DAC, USB, I2C + * + * .... .... TTTT TTTT .... .... .... .... + */ + +#define GPIO_I2CSLEW_SHIFT (16) /* Bit 16: Controls slew rate of I2C pad */ +#define GPIO_I2CSLEW_MASK (1 << GPIO_I2CSLEW_SHIFT) +# define GPIO_I2CSLEW_I2C (0) +# define GPIO_I2CSLEW_GPIO GPIO_I2CSLEW_MASK + +#define GPIO_INVERT_SHIFT (17) /* Bit 17: Input polarity */ +#define GPIO_INVERT_MASK (1 << GPIO_INVERT_SHIFT) +# define GPIO_INVERT GPIO_INVERT_MASK + +#define GPIO_DIGIMODE_SHIFT (18) /* Bit 18: Select Analog/Digital mode */ +#define GPIO_DIGIMODE_MASK (1 << GPIO_DIGIMODE_SHIFT) +# define GPIO_MODE_ANALOG (0) +# define GPIO_MODE_DIGITAL GPIO_DIGIMODE_MASK + +#define GPIO_FILTEROFF_SHIFT (19) /* Bit 19: Controls input glitch filter */ +#define GPIO_FILTEROFF_MASK (1 << GPIO_FILTEROFF_SHIFT) +# define GPIO_FILTER_ON (0) +# define GPIO_FILTER_OFF GPIO_FILTEROFF_MASK + +#define GPIO_SLEW_SHIFT (20) /* Bit 20: Driver slew rate */ +#define GPIO_SLEW_MASK (1 << GPIO_SLEW_SHIFT) +# define GPIO_SLEW_STANDARD (0) +# define GPIO_SLEW_FAST GPIO_SLEW_MASK + +#define GPIO_I2CDRIVE_SHIFT (21) /* Bit 21: Driver slew rate */ +#define GPIO_I2CDRIVE_MASK (1 << GPIO_I2CDRIVE_SHIFT) +# define GPIO_I2CDRIVE_LOW (0) +# define GPIO_I2CDRIVE_HIGH GPIO_I2CDRIVE_MASK + +#define GPIO_OD_SHIFT (22) /* Bit 22: Controls open-drain mode */ +#define GPIO_OD_MASK (1 << GPIO_OD_SHIFT) +# define GPIO_PUSHPULL (0) +# define GPIO_OPENDRAIN GPIO_OD_MASK + +#define GPIO_I2CFILTEROFF_SHIFT (23) /* Bit 23: Configures I2C glitch filter */ +#define GPIO_I2CFILTEROFF_MASK (1 << GPIO_I2CFILTEROFF_SHIFT) +# define GPIO_I2C_FILTER_ON (0) +# define GPIO_I2C_FILTER_OFF GPIO_I2CFILTEROFF_MASK + +/* Pin Function bits: + * Only meaningful when the GPIO function is GPIO_PIN + * + * .... .... .... .... FFFF F... .... .... + */ + +#define GPIO_FUNC_SHIFT (11) /* Bits 11-15: GPIO mode */ +#define GPIO_FUNC_MASK (0x1f << GPIO_FUNC_SHIFT) +# define GPIO_INPUT (0x00 << GPIO_FUNC_SHIFT) /* 00000 GPIO input pin */ +# define GPIO_OUTPUT (0x01 << GPIO_FUNC_SHIFT) /* 00001 GPIO output pin */ + +# define GPIO_INTFE (0x09 << GPIO_FUNC_SHIFT) /* 01001 GPIO interrupt falling edge */ +# define GPIO_INTRE (0x0a << GPIO_FUNC_SHIFT) /* 01010 GPIO interrupt rising edge */ +# define GPIO_INTBOTH (0x0b << GPIO_FUNC_SHIFT) /* 01011 GPIO interrupt both edges */ +# define GPIO_INTLOW (0x0d << GPIO_FUNC_SHIFT) /* 01101 GPIO interrupt low level */ +# define GPIO_INTHIGH (0x0e << GPIO_FUNC_SHIFT) /* 01110 GPIO interrupt high level */ + +# define GPIO_ALT1 (0x11 << GPIO_FUNC_SHIFT) /* 10001 Alternate function 1 */ +# define GPIO_ALT2 (0x12 << GPIO_FUNC_SHIFT) /* 10010 Alternate function 2 */ +# define GPIO_ALT3 (0x13 << GPIO_FUNC_SHIFT) /* 10011 Alternate function 3 */ +# define GPIO_ALT4 (0x14 << GPIO_FUNC_SHIFT) /* 10100 Alternate function 4 */ +# define GPIO_ALT5 (0x15 << GPIO_FUNC_SHIFT) /* 10101 Alternate function 5 */ +# define GPIO_ALT6 (0x16 << GPIO_FUNC_SHIFT) /* 10110 Alternate function 6 */ +# define GPIO_ALT7 (0x17 << GPIO_FUNC_SHIFT) /* 10111 Alternate function 7 */ + +#define GPIO_GPIO_MASK (0x1e << GPIO_FUNC_SHIFT) /* 1111x */ +#define GPIO_GPIO_CODE (0x00 << GPIO_FUNC_SHIFT) /* 0000x */ +#define GPIO_IS_GPIO(ps) (((uint32_t)(ps) & GPIO_GPIO_MASK) == GPIO_GPIO_CODE) +#define GPIO_IS_GPIOINPUT(ps) ((uint32_t)(ps) == GPIO_INPUT) +#define GPIO_IS_GPIOOUTPUT(ps) ((uint32_t)(ps) == GPIO_OUTPUT) + +#define GPIO_INTR_MASK (0x18 << GPIO_FUNC_SHIFT) /* 11xxx */ +#define GPIO_INTR_CODE (0x08 << GPIO_FUNC_SHIFT) /* 01xxx */ +#define GPIO_IS_INTR(ps) (((uint32_t)(ps) & GPIO_INTR_MASK) == GPIO_INTR_CODE) + +#define GPIO_TRIG_MASK (0x18 << GPIO_FUNC_SHIFT) /* 111xx */ +#define GPIO_TRIG_EDGE_CODE (0x08 << GPIO_FUNC_SHIFT) /* 010xx */ +#define GPIO_TRIG_LEVEL_CODE (0x0c << GPIO_FUNC_SHIFT) /* 011xx */ +#define GPIO_IS_INTEDGE(ps) (((uint32_t)(ps) & GPIO_TRIG_MASK) == GPIO_TRIG_EDGE_CODE) +#define GPIO_IS_INTLEVEL(ps) (((uint32_t)(ps) & GPIO_TRIG_MASK) == GPIO_TRIG_LEVEL_CODE) + +#define GPIO_ALT_MASK (0x18 << GPIO_FUNC_SHIFT) /* 11xxx */ +#define GPIO_ALT_CODE (0x10 << GPIO_FUNC_SHIFT) /* 10xxx */ +#define GPIO_IS_ALT(ps) (((uint32_t)(ps) & GPIO_ALT_MASK) == GPIO_ALT_CODE) + +/* Pin Mode: MM + * + * .... .... .... .... .... .MM. .... .... + */ + +#define GPIO_MODE_SHIFT (9) /* Bits 9-10: Pin pull-up mode */ +#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) +# define GPIO_FLOAT (IOCON_MODE_FLOAT << GPIO_MODE_SHIFT) /* Neither pull-up nor -down */ +# define GPIO_PULLDOWN (IOCON_MODE_PULLDOWN << GPIO_MODE_SHIFT) /* Pull-down resistor enabled */ +# define GPIO_PULLUP (IOCON_MODE_PULLUP << GPIO_MODE_SHIFT) /* Pull-up resistor enabled */ +# define GPIO_REPEATER (IOCON_MODE_REPEATER << GPIO_MODE_SHIFT) /* Repeater mode enabled */ + +/* Initial value: V + * + * .... .... .... .... .... ...V .... .... + */ + +#define GPIO_VALUE (1 << 8) /* Bit 8: Initial GPIO output value */ +# define GPIO_VALUE_ONE GPIO_VALUE +# define GPIO_VALUE_ZERO (0) + +/* Port number: PPP (0-5) + * + * .... .... .... .... .... .... PPP. .... + */ + +#define GPIO_PORT_SHIFT (5) /* Bit 5-7: Port number */ +#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) +# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT) +# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT) +# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT) +# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT) +# define GPIO_PORT5 (5 << GPIO_PORT_SHIFT) + +/* Pin number: NNNNN (0-31) + * + * .... .... .... .... .... .... ...N NNNN + */ + +#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */ +#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT) +# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) +# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) +# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) +# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) +# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) +# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) +# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) +# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) +# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) +# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) +# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) +# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) +# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) +# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) +# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) +# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) +# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +typedef uint32_t lpc54_pinset_t; + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc54_gpio_irqinitialize + * + * Description: + * Initialize logic to support interrupting GPIO pins. This function is called by + * the OS inialization logic and is not a user interface. + * + ************************************************************************************/ + +#ifdef CONFIG_LPC54_GPIOIRQ +void lpc54_gpio_irqinitialize(void); +#else +# define lpc54_gpio_irqinitialize() +#endif + +/************************************************************************************ + * Name: lpc54_gpio_config + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ************************************************************************************/ + +int lpc54_gpio_config(lpc54_pinset_t cfgset); + +/************************************************************************************ + * Name: lpc54_gpio_interrupt + * + * Description: + * Configure a GPIO interrupt pin based on bit-encoded description of the pin. + * This function is called by lpc54_gpio_config to setup interrupting pins. It is + * not a user interface. + * + ************************************************************************************/ + +#ifdef CONFIG_LPC54_GPIOIRQ +int lpc54_gpio_interrupt(lpc54_pinset_t pinset); +#endif + +/************************************************************************************ + * Name: lpc54_gpio_irqno + * + * Description: + * Returns the IRQ number that was associated with an interrupt pin after it was + * configured. + * + ************************************************************************************/ + +#ifdef CONFIG_LPC54_GPIOIRQ +int lpc54_gpio_irqno(lpc54_pinset_t pinset); +#endif + +/************************************************************************************ + * Name: lpc54_gpio_ackedge + * + * Description: + * Acknowledge edge interrupts by clearing the associated bits in the rising and + * falling registers. This acknowledgemment is, of course, not needed for level + * interupts. + * + ************************************************************************************/ + +#ifdef CONFIG_LPC54_GPIOIRQ +int lpc54_gpio_ackedge(int irq); +#endif + +/************************************************************************************ + * Name: lpc54_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ************************************************************************************/ + +void lpc54_gpio_write(lpc54_pinset_t pinset, bool value); + +/************************************************************************************ + * Name: lpc54_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ************************************************************************************/ + +bool lpc54_gpio_read(lpc54_pinset_t pinset); + +/************************************************************************************ + * Function: lpc54_gpio_dump + * + * Description: + * Dump all GPIO registers associated with the base address of the provided pinset. + * + ************************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO_INFO +int lpc54_gpio_dump(lpc54_pinset_t pinset, const char *msg); +#else +# define lpc54_gpio_dump(p,m) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_GPIO_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_gpioirq.c b/arch/arm/src/lpc54xx/lpc54_gpioirq.c new file mode 100644 index 0000000000000000000000000000000000000000..8a0a9749c9ca215c467d63e959a6bdd7a27b010c --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_gpioirq.c @@ -0,0 +1,362 @@ +/**************************************************************************** + * arch/arm/src/lpc54/lpc54_gpioirq.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_arch.h" + +#include "chip/lpc54_syscon.h" +#include "chip/lpc54_inputmux.h" +#include "chip/lpc54_pint.h" +#include "lpc54_gpio.h" + +#ifdef CONFIG_LPC54_GPIOIRQ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The maximum number of pin interrupts */ + +#define MAX_PININT 8 + +/* A mask for both the port and pin number */ + +#define GPIO_PORTPIN_MASK (GPIO_PORT_MASK | GPIO_PIN_MASK) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is the set of all pin interrupts that have been allocated. Any pin + * in P0 or P1 may be configured as an interrupts source via the input + * multiplexor. Up to eight pin interrupts are supported. + */ + +static uint8_t g_pinints; + +/* Maps a pin interrupt number to an IRQ number (they are not contiguous) */ + +static const uint8_t g_pinirq[MAX_PININT] = +{ + LPC54_IRQ_PININT0, LPC54_IRQ_PININT1, LPC54_IRQ_PININT2, LPC54_IRQ_PININT3, + LPC54_IRQ_PININT4, LPC54_IRQ_PININT5, LPC54_IRQ_PININT6, LPC54_IRQ_PININT7 +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_alloc_pinint + * + * Description: + * Initialize logic to support interrupting GPIO pins. This function is + * called by the OS inialization logic and is not a user interface. + * + ****************************************************************************/ + +static int lpc54_alloc_pinint(lpc54_pinset_t pinset) +{ + irqstate_t flags = enter_critical_section(); + int pin; + + /* REVISIT: This is overlying complex in the current design. There is + * not yet any mechanism to de-configure a pin. At present, a simple + * counter would be sufficient to assign a pin. This bit-mapped allocator + * is used in the anticipation that such pin-deconfiguration will be + * supported in the future. + */ + + for (pin = 0; pin < MAX_PININT; pin++) + { + uint8_t mask = (1 << pin); + if ((g_pinints & mask) == 0) + { + g_pinints |= mask; + leave_critical_section(flags); + return pin; + } + } + + leave_critical_section(flags); + return -ENOSPC; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_gpio_irqinitialize + * + * Description: + * Initialize logic to support interrupting GPIO pins. This function is + * called by the OS inialization logic and is not a user interface. + * + ****************************************************************************/ + +void lpc54_gpio_irqinitialize(void) +{ + /* NOTE: "Once set up, no clocks are needed for the input multiplexer to + * function. The system clock is needed only to write to or read from the + * INPUT MUX registers. Once the input multiplexer is configured, disable + * the clock to the INPUT MUX block in the AHBCLKCTRL register." + * + * REVISIT: Future power optimization. + */ + +#ifdef CONFIG_LPC54_GPIOIRQ_GROUPS + /* Enable the Input Mux, PINT, and GINT modules */ + + putreg32(SYSCON_AHBCLKCTRL0_INPUTMUX | SYSCON_AHBCLKCTRL0_PINT | + SYSCON_AHBCLKCTRL0_GINT, LPC54_SYSCON_AHBCLKCTRLSET0); +#else + /* Enable the Input Mux and PINT modules */ + + putreg32(SYSCON_AHBCLKCTRL0_INPUTMUX | SYSCON_AHBCLKCTRL0_PINT, + LPC54_SYSCON_AHBCLKCTRLSET0); +#endif +} + +/************************************************************************************ + * Name: lpc54_gpio_interrupt + * + * Description: + * Configure a GPIO interrupt pin based on bit-encoded description of the pin. + * This function is called by lpc54_gpio_config to setup interrupting pins. It is + * not a user interface. + * + ************************************************************************************/ + +int lpc54_gpio_interrupt(lpc54_pinset_t pinset) +{ + uintptr_t regaddr; + uint32_t mask; + unsigned int port; + int pinint; + + /* Is this pin configured as an interrupting pin */ + + if (!GPIO_IS_INTR(pinset)) + { + return -EPERM; + } + + /* Pin interrupts are supported only on P0 and P1 */ + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port > 1) + { + return -EINVAL; + } + + /* Assign a pin interrupt */ + + pinint = lpc54_alloc_pinint(pinset); + if (pinint < 0) + { + return pinint; + } + + /* Make sure that the pin interrupt is disabled at the NVIC. */ + + up_disable_irq(g_pinirq[pinint]); + + /* Select the pin interrupt input: + * + * For PIOm.n: pin = (m * 32) + n. + * PIO0.0 to PIO1.31 correspond to numbers 0 to 63. + */ + + regaddr = LPC54_MUX_PINTSEL(pinint); + putreg32((uint32_t)pinset & GPIO_PORTPIN_MASK, regaddr); + + /* Enable the pin interrupt triggers */ + + mask = (1 << pinint); + if (GPIO_IS_INTLEVEL(pinset)) + { + /* Set the pinint bit to select level sensitive trigger */ + + modifyreg32(LPC54_PINT_ISEL, 0, mask); + } + else + { + /* Clear the pinint bit to select edge sensitive trigger */ + + modifyreg32(LPC54_PINT_ISEL, mask, 0); + } + + switch (pinset & GPIO_FUNC_MASK) + { + /* Write to SIENR to enable rising-edge or level interrupts */ + + case GPIO_INTRE: /* GPIO interrupt rising edge */ + case GPIO_INTBOTH: /* GPIO interrupt both edges */ + case GPIO_INTLOW: /* GPIO interrupt low level */ + case GPIO_INTHIGH: /* GPIO interrupt high level */ + putreg32(mask, LPC54_PINT_SIENR); + break; + + /* Write to CIENR to disable rising-edge or level interrupts */ + + case GPIO_INTFE: /* GPIO interrupt falling edge */ + putreg32(mask, LPC54_PINT_CIENR); + break; + + default: + DEBUGPANIC(); + return -EINVAL; + } + + switch (pinset & GPIO_FUNC_MASK) + { + /* Write to SIENF to enable falling-edge or active-high level + * interrupts. + */ + + case GPIO_INTFE: /* GPIO interrupt falling edge */ + case GPIO_INTBOTH: /* GPIO interrupt both edges */ + case GPIO_INTHIGH: /* GPIO interrupt high level */ + putreg32(mask, LPC54_PINT_SIENF); + break; + + /* Write to CIENF to disable falling-edge or enable active-low level + * interrupts. + */ + + case GPIO_INTRE: /* GPIO interrupt rising edge */ + case GPIO_INTLOW: /* GPIO interrupt low level */ + putreg32(mask, LPC54_PINT_CIENF); + break; + + default: + DEBUGPANIC(); + return -EINVAL; + } + + return OK; +} + +/************************************************************************************ + * Name: lpc54_gpio_irqno + * + * Description: + * Returns the IRQ number that was associated with an interrupt pin after it was + * configured. + * + ************************************************************************************/ + +int lpc54_gpio_irqno(lpc54_pinset_t pinset) +{ + irqstate_t flags; + uintptr_t regaddr; + uint32_t regval; + int portpin = pinset & GPIO_PORTPIN_MASK; + int i; + + flags = enter_critical_section(); + + /* Find the PININT index that as the assignment to the this port and pin */ + + for (i = 0, regaddr = LPC54_MUX_PINTSEL0; + i < MAX_PININT; + i++, regaddr += 4) + { + regval = getreg32(regaddr) & GPIO_PORTPIN_MASK; + if (regval == portpin) + { + leave_critical_section(flags); + return (int)g_pinirq[i]; + } + } + + leave_critical_section(flags); + return -ENOENT; +} + +/************************************************************************************ + * Name: lpc54_gpio_ackedge + * + * Description: + * Acknowledge edge interrupts by clearing the associated bits in the rising and + * falling registers. This acknowledgemment is, of course, not needed for level + * interupts. + * + ************************************************************************************/ + +int lpc54_gpio_ackedge(int irq) +{ + uint32_t regval; + uint32_t mask; + unsigned int pinint; + + /* Map the IRQ number to a pin interrupt number */ + + if (irq >= LPC54_IRQ_PININT0 && irq <= LPC54_IRQ_PININT3) + { + pinint = irq - LPC54_IRQ_PININT0; + } + else if (irq >= LPC54_IRQ_PININT4 && irq <= LPC54_IRQ_PININT7) + { + pinint = irq - LPC54_IRQ_PININT4 + 4; + } + else + { + return -EINVAL; + } + + /* Acknowledge the pin interrupt */ + + mask = (1 << pinint); + regval = getreg32(LPC54_PINT_RISE) & mask; + putreg32(regval, LPC54_PINT_RISE); + + regval = getreg32(LPC54_PINT_FALL) & mask; + putreg32(regval, LPC54_PINT_FALL); + return OK; +} + +#endif /* CONFIG_LPC54_GPIOIRQ */ diff --git a/arch/arm/src/lpc54xx/lpc54_i2c_master.c b/arch/arm/src/lpc54xx/lpc54_i2c_master.c new file mode 100644 index 0000000000000000000000000000000000000000..cf4981676f5267a1c352680221365cc9dca38fad --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_i2c_master.c @@ -0,0 +1,1277 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_i2c_master.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Parts of this file were adapted from sample code provided for the LPC54xx + * family from NXP which has a compatible BSD license. + * + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "chip/lpc54_pinmux.h" +#include "chip/lpc54_syscon.h" +#include "chip/lpc54_flexcomm.h" +#include "chip/lpc54_i2c.h" +#include "lpc54_config.h" +#include "lpc54_clockconfig.h" +#include "lpc54_enableclk.h" +#include "lpc54_gpio.h" +#include "lpc54_i2c_master.h" + +#include + +#ifdef HAVE_I2C_MASTER_DEVICE + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* 20 Millisecond timeout in system clock ticks. */ + +#ifdef CONFIG_DEBUG_I2C_INFO +# define I2C_WDOG_TIMEOUT MSEC2TICK(50) +#else +# define I2C_WDOG_TIMEOUT MSEC2TICK(20) +#endif + +/* Default I2C frequency */ + +#if defined(CONFIG_LPC54_I2C_FAST) || defined(CONFIG_LPC54_I2C_HIGH) +# define I2C_DEFAULT_FREQUENCY 1000000 +#else +# define I2C_DEFAULT_FREQUENCY 400000 +#endif + +/* I2C Master Interrupts */ + +#define I2C_MASTER_INTS \ + (I2C_INT_MSTPENDING | I2C_INT_MSTARBLOSS | I2C_INT_MSTSTSTPERR) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* I2C state */ + +enum lpc54_i2cstate_e +{ + I2CSTATE_IDLE = 0, + I2CSTATE_TRANSMIT, + I2CSTATE_RECEIVE, + I2CSTATE_START, + I2CSTATE_STOP, + I2CSTATE_WAITSTOP +}; + +/* This structure provides the overall state of the I2C driver */ + +struct lpc54_i2cdev_s +{ + struct i2c_master_s dev; /* Generic I2C device */ + uintptr_t base; /* Base address of Flexcomm registers */ + + WDOG_ID timeout; /* Watchdog to timeout when bus hung */ + uint32_t frequency; /* Current I2C frequency */ + uint32_t fclock; /* Flexcomm function clock frequency */ + + struct i2c_msg_s *msgs; /* Remaining transfers (first is in progress) */ + int16_t nmsgs; /* Number of transfer remaining */ + int16_t result; /* The result of the transfer */ + + sem_t exclsem; /* Only one thread can access at a time */ +#ifndef CONFIG_I2C_POLLED + sem_t waitsem; /* Supports wait for state machine completion */ + uint16_t irq; /* Flexcomm IRQ number */ +#endif + uint16_t xfrd; /* Number of bytes transferred */ + volatile uint8_t state; /* State of state machine */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void lpc54_i2c_putreg(struct lpc54_i2cdev_s *priv, + unsigned int regoffset, uint32_t regval); +static inline uint32_t lpc54_i2c_getreg(struct lpc54_i2cdev_s *priv, + unsigned int regoffset); + +static void lpc54_i2c_setfrequency(struct lpc54_i2cdev_s *priv, + uint32_t frequency); +static void lpc54_i2c_timeout(int argc, uint32_t arg, ...); +static void lpc54_i2c_xfrsetup(struct lpc54_i2cdev_s *priv); +static bool lpc54_i2c_nextmsg(struct lpc54_i2cdev_s *priv); +static bool lpc54_i2c_statemachine(struct lpc54_i2cdev_s *priv); +#ifndef CONFIG_I2C_POLLED +static int lpc54_i2c_interrupt(int irq, FAR void *context, FAR void *arg); +#else +static int lpc54_i2c_poll(struct lpc54_i2cdev_s *priv); +#endif +static int lpc54_i2c_transfer(FAR struct i2c_master_s *dev, + FAR struct i2c_msg_s *msgs, int count); +#ifdef CONFIG_I2C_RESET +static int lpc54_i2c_reset(FAR struct i2c_master_s * dev); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct i2c_ops_s lpc54_i2c_ops = +{ + .transfer = lpc54_i2c_transfer +#ifdef CONFIG_I2C_RESET + , .reset = lpc54_i2c_reset +#endif +}; + +#ifdef CONFIG_LPC54_I2C0_MASTER +static struct lpc54_i2cdev_s g_i2c0_dev; +#endif +#ifdef CONFIG_LPC54_I2C1_MASTER +static struct lpc54_i2cdev_s g_i2c1_dev; +#endif +#ifdef CONFIG_LPC54_I2C2_MASTER +static struct lpc54_i2cdev_s g_i2c2_dev; +#endif +#ifdef CONFIG_LPC54_I2C3_MASTER +static struct lpc54_i2cdev_s g_i2c3_dev; +#endif +#ifdef CONFIG_LPC54_I2C4_MASTER +static struct lpc54_i2cdev_s g_i2c4_dev; +#endif +#ifdef CONFIG_LPC54_I2C5_MASTER +static struct lpc54_i2cdev_s g_i2c5_dev; +#endif +#ifdef CONFIG_LPC54_I2C6_MASTER +static struct lpc54_i2cdev_s g_i2c6_dev; +#endif +#ifdef CONFIG_LPC54_I2C7_MASTER +static struct lpc54_i2cdev_s g_i2c7_dev; +#endif +#ifdef CONFIG_LPC54_I2C8_MASTER +static struct lpc54_i2cdev_s g_i2c8_dev; +#endif +#ifdef CONFIG_LPC54_I2C9_MASTER +static struct lpc54_i2cdev_s g_i2c9_dev; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_i2c_putreg + * + * Description: + * Write a value to a register at the offset from the Flexcomm base. + * + ****************************************************************************/ + +static inline void lpc54_i2c_putreg(struct lpc54_i2cdev_s *priv, + unsigned int regoffset, uint32_t regval) +{ + putreg32(regval, priv->base + regoffset); +} + +/**************************************************************************** + * Name: lpc54_i2c_getreg + * + * Description: + * Read the content of a register at the offset from the Flexcomm base. + * + ****************************************************************************/ + +static inline uint32_t lpc54_i2c_getreg(struct lpc54_i2cdev_s *priv, + unsigned int regoffset) +{ + return getreg32(priv->base + regoffset); +} + +/**************************************************************************** + * Name: lpc54_i2c_setfrequency + * + * Description: + * Set the frequency for the next transfer + * + ****************************************************************************/ + +static void lpc54_i2c_setfrequency(struct lpc54_i2cdev_s *priv, + uint32_t frequency) +{ + uint32_t scl; + uint32_t divider; + uint32_t best_scl; + uint32_t best_div; + uint32_t err; + uint32_t best_err; + uint32_t regval; + + i2cinfo("frequency %ld (%ld)\n", (long)frequency, (long)priv->frequency); + + /* Has the I2C frequency changed? */ + + if (frequency != priv->frequency) + { + /* Yes.. instantiate the new I2C frequency */ + + best_err = 0; + + for (scl = 9; scl >= 2; scl--) + { + /* Calculate ideal divider value for the current scl candidate. + * + * SCL High Time: Thi = divider * SCLhi + * SCL High Time: Tlo = divider * SCLlo + * Fscl = Finput / (Thi + Tlo) + * + * If Thi == TloL: Fscl = Finput / (divider * SCL * 2) + * Or: divider = Finput / (Fscl * SCL * 2) + */ + + divider = priv->fclock / (frequency * scl * 2); + + /* Adjust it if it is out of range */ + + if (divider > 0x00010000) + { + divider = 0x00010000; + } + + /* Calculate the frequency error */ + + err = priv->fclock - (frequency * scl * 2 * divider); + if (err < best_err || best_err == 0) + { + best_div = divider; + best_scl = scl; + best_err = err; + } + + if (err == 0 || divider >= 0x10000) + { + /* Break out of the loop early ifeither exact value was found or + * the divider is at its maximum value. + */ + + break; + } + } + + /* Instantiate the new I2C frequency */ + + regval = I2C_CLKDIV(best_div); + lpc54_i2c_putreg(priv, LPC54_I2C_CLKDIV_OFFSET, regval); + + regval = I2C_MSTTIME_SCLLOW(best_scl) | I2C_MSTTIME_SCLHIGH(best_scl); + lpc54_i2c_putreg(priv, LPC54_I2C_MSTTIME_OFFSET, regval); + + priv->frequency = frequency; + } +} + +/**************************************************************************** + * Name: lpc54_i2c_timeout + * + * Description: + * Watchdog timer for timeout of I2C operation + * + ****************************************************************************/ + +static void lpc54_i2c_timeout(int argc, uint32_t arg, ...) +{ + struct lpc54_i2cdev_s *priv = (struct lpc54_i2cdev_s *)arg; + +#ifndef CONFIG_I2C_POLLED + irqstate_t flags = enter_critical_section(); +#endif + + i2cerr("ERROR: Timeout! state=%u\n", priv->state); + + /* Disable further I2C interrupts and return to the IDLE state with the + * timeout result. + */ + + lpc54_i2c_putreg(priv, LPC54_I2C_INTENCLR_OFFSET, I2C_MASTER_INTS); + priv->state = I2CSTATE_IDLE; + + if (priv->result == OK) + { + priv->result = -ETIMEDOUT; + } + +#ifndef CONFIG_I2C_POLLED + /* Wake up any waiters */ + + nxsem_post(&priv->waitsem); + leave_critical_section(flags); +#endif +} + +/**************************************************************************** + * Name: lpc54_i2c_xfrsetup + * + * Description: + * Setup to initiate a transfer. + * + ****************************************************************************/ + +static void lpc54_i2c_xfrsetup(struct lpc54_i2cdev_s *priv) +{ + struct i2c_msg_s *msg; + + DEBUGASSERT(priv != NULL && priv->msgs != NULL); + msg = priv->msgs; + + /* Disable I2C interrupts while configuring for the transfer */ + + lpc54_i2c_putreg(priv, LPC54_I2C_INTENCLR_OFFSET, I2C_MASTER_INTS); + + /* Set up for the transfer */ + + priv->xfrd = 0; + + /* Select the initial state */ + + if ((msg->flags & I2C_M_NORESTART) != 0) + { + /* Start condition will be ommited. Begin the tranfer in the data + * phase. + */ + + if (msg->length == 0) + { + priv->state = I2CSTATE_STOP; + } + else if ((I2C_M_READ & msg->flags) == I2C_M_READ) + { + priv->state = I2CSTATE_RECEIVE; + } + else + { + priv->state = I2CSTATE_TRANSMIT; + } + } + else + { + priv->state = I2CSTATE_START; + } + + /* Set the I2C frequency if provided in this message. Otherwise, use the + * current I2C frequency setting. + */ + + if (msg->frequency > 0) + { + (void)lpc54_i2c_setfrequency(priv, msg->frequency); + } + + /* Clear error status bits */ + + lpc54_i2c_putreg(priv, LPC54_I2C_STAT_OFFSET, I2C_INT_MSTARBLOSS | + I2C_INT_MSTSTSTPERR); + +#ifndef CONFIG_I2C_POLLED + /* Enable I2C master interrupts */ + + lpc54_i2c_putreg(priv, LPC54_I2C_INTENSET_OFFSET, I2C_MASTER_INTS); +#endif +} + +/**************************************************************************** + * Name: lpc54_i2c_nextmsg + * + * Description: + * Called at the completion of each message. If there are more messages, + * this function will perform the setup for the next message. + * + ****************************************************************************/ + +static bool lpc54_i2c_nextmsg(struct lpc54_i2cdev_s *priv) +{ + irqstate_t flags; + + /* Disable interrupts to prevent the timeout while we make the decision + * here. + */ + + flags = enter_critical_section(); + + i2cinfo("nmsgs=%u\n", priv->nmsgs - 1); + + /* Decrement the number of messages remaining. */ + + if (--priv->nmsgs > 0 && priv->result == OK) + { + /* There are more messages, set up for the next message */ + + priv->msgs++; + lpc54_i2c_xfrsetup(priv); + + i2cinfo("state=%u\n", priv->state); + leave_critical_section(flags); + return false; + } + else + { + /* That was the last message... we are done. */ + /* Cancel any timeout */ + + wd_cancel(priv->timeout); + + /* Disable further I2C interrupts and return to the IDLE state */ + + lpc54_i2c_putreg(priv, LPC54_I2C_INTENCLR_OFFSET, I2C_MASTER_INTS); + priv->state = I2CSTATE_IDLE; + + i2cinfo("state=%u\n", priv->state); + leave_critical_section(flags); + return true; + } +} + +/**************************************************************************** + * Name: lpc54_i2c_statemachine + * + * Description: + * This is the I2C transfer state machine that implements the actual + * transfer. It may be called from the interrupt level or is may be used + * without interrupts in a polled mode. + * + ****************************************************************************/ + +static bool lpc54_i2c_statemachine(struct lpc54_i2cdev_s *priv) +{ + struct i2c_msg_s *msg; + uint32_t status; + uint32_t mstate; + + DEBUGASSERT(priv != NULL && priv->msgs != NULL); + msg = priv->msgs; + + i2cinfo("state=%u\n", priv->state); + + status = lpc54_i2c_getreg(priv, LPC54_I2C_STAT_OFFSET); + + if (status & I2C_INT_MSTARBLOSS) + { + i2cerr("ERROR: Arbitation loss\n"); + + lpc54_i2c_putreg(priv, LPC54_I2C_STAT_OFFSET, I2C_INT_MSTARBLOSS); + priv->result = -EIO; + return true; + } + + if (status & I2C_INT_MSTSTSTPERR) + { + i2cerr("ERROR: Start/stop error\n"); + + lpc54_i2c_putreg(priv, LPC54_I2C_STAT_OFFSET, I2C_INT_MSTSTSTPERR); + priv->result = -EIO; + return true; + } + + if ((status & I2C_INT_MSTPENDING) == 0) + { + i2cerr("ERROR: Busy\n"); + + priv->result = -EBUSY; + return true; + } + + /* Get the state of the I2C module */ + + mstate = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + i2cinfo("mstate=%u\n", mstate); + + if ((mstate == I2C_MASTER_STATE_ADDRNAK) || + (mstate == I2C_MASTER_STATE_DATANAK)) + { + /* Slave NACKed last byte, issue stop and return error */ + + lpc54_i2c_putreg(priv, LPC54_I2C_MSTCTL_OFFSET, I2C_MSTCTL_MSTSTOP); + priv->result = -EPERM; + priv->state = I2CSTATE_WAITSTOP; + + i2cerr("ERROR: NAKed, state=%u\n", priv->state); + return false; + } + + switch (priv->state) + { + case I2CSTATE_START: + { + enum lpc54_i2cstate_e newstate; + + if ((msg->flags & I2C_M_READ) == I2C_M_READ) + { + lpc54_i2c_putreg(priv, LPC54_I2C_MSTDAT_OFFSET, + I2C_READADDR8(msg->addr)); + newstate = I2CSTATE_RECEIVE; + } + else + { + lpc54_i2c_putreg(priv, LPC54_I2C_MSTDAT_OFFSET, + I2C_WRITEADDR8(msg->addr)); + newstate = I2CSTATE_TRANSMIT; + } + + if (priv->xfrd >= msg->length) + { + /* No more data, setup for STOP */ + + newstate = I2CSTATE_STOP; + } + + priv->state = newstate; + + /* Send START condition */ + + lpc54_i2c_putreg(priv, LPC54_I2C_MSTCTL_OFFSET, + I2C_MSTCTL_MSTSTART); + } + break; + + case I2CSTATE_TRANSMIT: + { + if (mstate != I2C_MASTER_STATE_TXOK) + { + i2cerr("ERROR bad state=%u, expected %u\n", + mstate, I2C_MASTER_STATE_TXOK); + + priv->result = -EINVAL; + return true; + } + + lpc54_i2c_putreg(priv, LPC54_I2C_MSTDAT_OFFSET, + msg->buffer[priv->xfrd]); + lpc54_i2c_putreg(priv, LPC54_I2C_MSTCTL_OFFSET, + I2C_MSTCTL_MSTCONTINUE); + priv->xfrd++; + + if (priv->xfrd >= msg->length) + { + /* No more data, schedule stop condition */ + + priv->state = I2CSTATE_STOP; + } + } + break; + + case I2CSTATE_RECEIVE: + { + if (mstate != I2C_MASTER_STATE_RXAVAIL) + { + i2cerr("ERROR bad state=%u, expected %u\n", + mstate, I2C_MASTER_STATE_RXAVAIL); + + priv->result = -EINVAL; + return true; + } + + msg->buffer[priv->xfrd] = + lpc54_i2c_getreg(priv, LPC54_I2C_MSTDAT_OFFSET); + + priv->xfrd++; + if (priv->xfrd < msg->length) + { + lpc54_i2c_putreg(priv, LPC54_I2C_MSTCTL_OFFSET, + I2C_MSTCTL_MSTCONTINUE); + } + else + { + /* No more data expected, issue NACK and STOP right away */ + + lpc54_i2c_putreg(priv, LPC54_I2C_MSTCTL_OFFSET, + I2C_MSTCTL_MSTSTOP); + priv->state = I2CSTATE_WAITSTOP; + } + } + break; + + case I2CSTATE_STOP: + { + bool dostop = true; + + /* Is this the last message? */ + + if (priv->nmsgs > 1) + { + struct i2c_msg_s *nextmsg; + + /* No.. Is there a start on the next message? If so, it + * should be preceded by a STOP. + */ + + nextmsg = msg + 1; + dostop = ((nextmsg->flags & I2C_M_NORESTART) != 0); + } + + if (dostop) + { + /* Stop condition is omitted, we are done. Start the next + * message (or return to the IDLE state if none). + */ + + return lpc54_i2c_nextmsg(priv); + } + else + { + /* Send stop condition */ + + lpc54_i2c_putreg(priv, LPC54_I2C_MSTCTL_OFFSET, + I2C_MSTCTL_MSTSTOP); + priv->state = I2CSTATE_WAITSTOP; + } + } + break; + + case I2CSTATE_WAITSTOP: + { + /* Start the next message (or return to the IDLE state if none). */ + + return lpc54_i2c_nextmsg(priv); + } + break; + + case I2CSTATE_IDLE: + default: + priv->result = -EINVAL; + return true; + } + + i2cinfo("state=%u\n", priv->state); + return false; +} + +/**************************************************************************** + * Name: lpc54_i2c_interrupt + * + * Description: + * The I2C Interrupt Handler + * + ****************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static int lpc54_i2c_interrupt(int irq, FAR void *context, FAR void *arg) +{ + struct lpc54_i2cdev_s *priv = (struct lpc54_i2cdev_s *)arg; + bool done; + + DEBUGASSERT(priv != NULL); + + /* Run the I2C state machine */ + + done = lpc54_i2c_statemachine(priv); + if (done) + { + /* Disable further I2C interrupts. */ + + lpc54_i2c_putreg(priv, LPC54_I2C_INTENCLR_OFFSET, I2C_MASTER_INTS); + + /* Wake up wake up any waiters */ + + nxsem_post(&priv->waitsem); + } + + return OK; +} +#endif /* CONFIG_I2C_POLLED */ + +/**************************************************************************** + * Name: lpc54_i2c_transfer + * + * Description: + * Perform a sequence of I2C transfers + * + ****************************************************************************/ + +static int lpc54_i2c_transfer(FAR struct i2c_master_s *dev, + FAR struct i2c_msg_s *msgs, int count) +{ + struct lpc54_i2cdev_s *priv = (struct lpc54_i2cdev_s *)dev; + int ret; + + i2cinfo("count=%d\n", count); + DEBUGASSERT(dev != NULL && msgs != NULL); + + /* Get exclusive access to the I2C bus */ + + nxsem_wait(&priv->exclsem); + + /* Set up for the transfer */ + + priv->xfrd = 0; + priv->msgs = msgs; + priv->nmsgs = count; + priv->result = OK; + + /* Set up the transfer timeout */ + /* wd_start(priv->timeout ...); */ + + wd_start(priv->timeout, priv->nmsgs * I2C_WDOG_TIMEOUT, lpc54_i2c_timeout, + 1, (uint32_t)priv); + + /* Initiate the transfer */ + + lpc54_i2c_xfrsetup(priv); + + /* Loop until the transfer is complete or until a timeout occurs */ + + do + { +#ifndef CONFIG_I2C_POLLED + nxsem_wait(&priv->waitsem); +#else + (void)lpc54_i2c_statemachine(priv); +#endif + } + while (priv->state != I2CSTATE_IDLE); + + ret = priv->result; + i2cinfo("Done, result=%d\n", ret); + + nxsem_post(&priv->exclsem); + return ret; +} + +/************************************************************************************ + * Name: lpc54_i2c_reset + * + * Description: + * Perform an I2C bus reset in an attempt to break loose stuck I2C devices. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ************************************************************************************/ + +#ifdef CONFIG_I2C_RESET +static int lpc54_i2c_reset(FAR struct i2c_master_s * dev) +{ +#warning Missing logic + return OK; +} +#endif /* CONFIG_I2C_RESET */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_i2cbus_initialize + * + * Description: + * Initialise an I2C device + * + ****************************************************************************/ + +struct i2c_master_s *lpc54_i2cbus_initialize(int port) +{ + struct lpc54_i2cdev_s *priv; + irqstate_t flags; + uint32_t regval; + + i2cinfo("port=%d\n", port); + + flags = enter_critical_section(); + + /* Configure the requestin I2C peripheral */ + /* NOTE: The basic FLEXCOMM initialization was performed in + * lpc54_lowputc.c. + */ + +#ifdef CONFIG_LPC54_I2C0_MASTER + if (port == 0) + { + /* Attach 12 MHz clock to FLEXCOMM0 */ + + lpc54_flexcomm0_enableclk(); + + /* Set FLEXCOMM0 to the I2C peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_I2C | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM0_PSELID); + + /* Initialize the state structure */ + + priv = &g_i2c0_dev; + priv->base = LPC54_FLEXCOMM0_BASE; + priv->fclock = BOARD_FLEXCOMM0_FCLK; +#ifndef CONFIG_I2C_POLLED + priv->irq = LPC54_IRQ_FLEXCOMM0; +#endif + + /* Configure I2C pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C0_SCL); + lpc54_gpio_config(GPIO_I2C0_SDA); + + /* Set up the FLEXCOMM0 function clock */ + + putreg32(BOARD_FLEXCOMM0_CLKSEL, LPC54_SYSCON_FCLKSEL0); + } + else +#endif +#ifdef CONFIG_LPC54_I2C1_MASTER + if (port == 1) + { + /* Attach 12 MHz clock to FLEXCOMM1 */ + + lpc54_flexcomm1_enableclk(); + + /* Set FLEXCOMM1 to the I2C peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_I2C | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM1_PSELID); + + /* Initialize the state structure */ + + priv = &g_i2c1_dev; + priv->base = LPC54_FLEXCOMM1_BASE; + priv->fclock = BOARD_FLEXCOMM1_FCLK; +#ifndef CONFIG_I2C_POLLED + priv->irq = LPC54_IRQ_FLEXCOMM1; +#endif + + /* Configure I2C pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C1_SCL); + lpc54_gpio_config(GPIO_I2C1_SDA); + + /* Set up the FLEXCOMM1 function clock */ + + putreg32(BOARD_FLEXCOMM1_CLKSEL, LPC54_SYSCON_FCLKSEL1); + } + else +#endif +#ifdef CONFIG_LPC54_I2C2_MASTER + if (port == 2) + { + /* Attach 12 MHz clock to FLEXCOMM2 */ + + lpc54_flexcomm2_enableclk(); + + /* Set FLEXCOMM2 to the I2C peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_I2C | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM2_PSELID); + + /* Initialize the state structure */ + + priv = &g_i2c2_dev; + priv->base = LPC54_FLEXCOMM2_BASE; + priv->fclock = BOARD_FLEXCOMM2_FCLK; +#ifndef CONFIG_I2C_POLLED + priv->irq = LPC54_IRQ_FLEXCOMM2; +#endif + + /* Configure I2C pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C2_SCL); + lpc54_gpio_config(GPIO_I2C2_SDA); + + /* Set up the FLEXCOMM2 function clock */ + + putreg32(BOARD_FLEXCOMM2_CLKSEL, LPC54_SYSCON_FCLKSEL2); + } + else +#endif +#ifdef CONFIG_LPC54_I2C3_MASTER + if (port == 3) + { + /* Attach 12 MHz clock to FLEXCOMM3 */ + + lpc54_flexcomm3_enableclk(); + + /* Set FLEXCOMM3 to the I2C peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_I2C | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM3_PSELID); + + /* Initialize the state structure */ + + priv = &g_i2c3_dev; + priv->base = LPC54_FLEXCOMM3_BASE; + priv->fclock = BOARD_FLEXCOMM3_FCLK; +#ifndef CONFIG_I2C_POLLED + priv->irq = LPC54_IRQ_FLEXCOMM3; +#endif + + /* Configure I2C pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C3_SCL); + lpc54_gpio_config(GPIO_I2C3_SDA); + + /* Set up the FLEXCOMM3 function clock */ + + putreg32(BOARD_FLEXCOMM3_CLKSEL, LPC54_SYSCON_FCLKSEL3); + } + else +#endif +#ifdef CONFIG_LPC54_I2C4_MASTER + if (port == 4) + { + /* Attach 12 MHz clock to FLEXCOMM4 */ + + lpc54_flexcomm4_enableclk(); + + /* Set FLEXCOMM4 to the I2C peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_I2C | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM4_PSELID); + + /* Initialize the state structure */ + + priv = &g_i2c4_dev; + priv->base = LPC54_FLEXCOMM4_BASE; + priv->fclock = BOARD_FLEXCOMM4_FCLK; +#ifndef CONFIG_I2C_POLLED + priv->irq = LPC54_IRQ_FLEXCOMM4; +#endif + + /* Configure I2C pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C4_SCL); + lpc54_gpio_config(GPIO_I2C4_SDA); + + /* Set up the FLEXCOMM4 function clock */ + + putreg32(BOARD_FLEXCOMM4_CLKSEL, LPC54_SYSCON_FCLKSEL4); + } + else +#endif +#ifdef CONFIG_LPC54_I2C5_MASTER + if (port == 5) + { + /* Attach 12 MHz clock to FLEXCOMM5 */ + + lpc54_flexcomm5_enableclk(); + + /* Set FLEXCOMM5 to the I2C peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_I2C | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM5_PSELID); + + /* Initialize the state structure */ + + priv = &g_i2c5_dev; + priv->base = LPC54_FLEXCOMM5_BASE; + priv->fclock = BOARD_FLEXCOMM5_FCLK; +#ifndef CONFIG_I2C_POLLED + priv->irq = LPC54_IRQ_FLEXCOMM5; +#endif + + /* Configure I2C pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C5_SCL); + lpc54_gpio_config(GPIO_I2C5_SDA); + + /* Set up the FLEXCOMM5 function clock */ + + putreg32(BOARD_FLEXCOMM5_CLKSEL, LPC54_SYSCON_FCLKSEL5); + } + else +#endif +#ifdef CONFIG_LPC54_I2C6_MASTER + if (port == 6) + { + /* Attach 12 MHz clock to FLEXCOMM6 */ + + lpc54_flexcomm6_enableclk(); + + /* Set FLEXCOMM6 to the I2C peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_I2C | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM6_PSELID); + + /* Initialize the state structure */ + + priv = &g_i2c6_dev; + priv->base = LPC54_FLEXCOMM6_BASE; + priv->fclock = BOARD_FLEXCOMM6_FCLK; +#ifndef CONFIG_I2C_POLLED + priv->irq = LPC54_IRQ_FLEXCOMM6; +#endif + + /* Configure I2C pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C6_SCL); + lpc54_gpio_config(GPIO_I2C6_SDA); + + /* Set up the FLEXCOMM6 function clock */ + + putreg32(BOARD_FLEXCOMM6_CLKSEL, LPC54_SYSCON_FCLKSEL6); + } + else +#endif +#ifdef CONFIG_LPC54_I2C7_MASTER + if (port == 7) + { + /* Attach 12 MHz clock to FLEXCOMM7 */ + + lpc54_flexcomm7_enableclk(); + + /* Set FLEXCOMM7 to the I2C peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_I2C | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM7_PSELID); + + /* Initialize the state structure */ + + priv = &g_i2c7_dev; + priv->base = LPC54_FLEXCOMM7_BASE; + priv->fclock = BOARD_FLEXCOMM7_FCLK; +#ifndef CONFIG_I2C_POLLED + priv->irq = LPC54_IRQ_FLEXCOMM7; +#endif + + /* Configure I2C pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C7_SCL); + lpc54_gpio_config(GPIO_I2C7_SDA); + + /* Set up the FLEXCOMM7 function clock */ + + putreg32(BOARD_FLEXCOMM7_CLKSEL, LPC54_SYSCON_FCLKSEL7); + } + else +#endif +#ifdef CONFIG_LPC54_I2C8_MASTER + if (port == 8) + { + /* Attach 12 MHz clock to FLEXCOMM8 */ + + lpc54_flexcomm8_enableclk(); + + /* Set FLEXCOMM8 to the I2C peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_I2C | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM8_PSELID); + + /* Initialize the state structure */ + + priv = &g_i2c8_dev; + priv->base = LPC54_FLEXCOMM8_BASE; + priv->fclock = BOARD_FLEXCOMM8_FCLK; +#ifndef CONFIG_I2C_POLLED + priv->irq = LPC54_IRQ_FLEXCOMM8; +#endif + + /* Configure I2C pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C8_SCL); + lpc54_gpio_config(GPIO_I2C8_SDA); + + /* Set up the FLEXCOMM8 function clock */ + + putreg32(BOARD_FLEXCOMM8_CLKSEL, LPC54_SYSCON_FCLKSEL8); + } + else +#endif +#ifdef CONFIG_LPC54_I2C9_MASTER + if (port == 9) + { + /* Attach 12 MHz clock to FLEXCOMM9 */ + + lpc54_flexcomm9_enableclk(); + + /* Set FLEXCOMM9 to the I2C peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_I2C | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM9_PSELID); + + /* Initialize the state structure */ + + priv = &g_i2c9_dev; + priv->base = LPC54_FLEXCOMM9_BASE; + priv->fclock = BOARD_FLEXCOMM9_FCLK; +#ifndef CONFIG_I2C_POLLED + priv->irq = LPC54_IRQ_FLEXCOMM9; +#endif + + /* Configure I2C pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C9_SCL); + lpc54_gpio_config(GPIO_I2C9_SDA); + + /* Set up the FLEXCOMM9 function clock */ + + putreg32(BOARD_FLEXCOMM9_CLKSEL, LPC54_SYSCON_FCLKSEL9); + } + else +#endif + { + i2cerr("ERROR: Unsupported port=%d\n", port); + return NULL; + } + + leave_critical_section(flags); + + /* Install our operations */ + + priv->dev.ops = &lpc54_i2c_ops; + + /* Enable the I2C peripheral in the master mode */ + + regval = lpc54_i2c_getreg(priv, LPC54_I2C_CFG_OFFSET); + regval &= I2C_CFG_ALLENABLES; + regval |= I2C_CFG_MSTEN; + lpc54_i2c_putreg(priv, LPC54_I2C_CFG_OFFSET, regval); + + /* Set the default I2C frequency */ + + lpc54_i2c_setfrequency(priv, I2C_DEFAULT_FREQUENCY); + + /* Initialize semaphores */ + + nxsem_init(&priv->exclsem, 0, 1); +#ifndef CONFIG_I2C_POLLED + nxsem_init(&priv->waitsem, 0, 0); + + /* The waitsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); +#endif + + /* Allocate a watchdog timer */ + + priv->timeout = wd_create(); + DEBUGASSERT(priv->timeout != 0); + +#ifndef CONFIG_I2C_POLLED + /* Attach Interrupt Handler */ + + irq_attach(priv->irq, lpc54_i2c_interrupt, priv); +#endif + + /* Disable interrupts at the I2C peripheral */ + + lpc54_i2c_putreg(priv, LPC54_I2C_INTENCLR_OFFSET, I2C_INT_ALL); + +#ifndef CONFIG_I2C_POLLED + /* Enable interrupts at the NVIC */ + + up_enable_irq(priv->irq); +#endif + return &priv->dev; +} + +/**************************************************************************** + * Name: lpc54_i2cbus_uninitialize + * + * Description: + * Uninitialise an I2C device + * + ****************************************************************************/ + +int lpc54_i2cbus_uninitialize(FAR struct i2c_master_s * dev) +{ + struct lpc54_i2cdev_s *priv = (struct lpc54_i2cdev_s *) dev; + uint32_t regval; + + /* Disable I2C interrupts */ + + lpc54_i2c_putreg(priv, LPC54_I2C_INTENCLR_OFFSET, I2C_MASTER_INTS); + + /* Disable the I2C peripheral */ + + regval = lpc54_i2c_getreg(priv, LPC54_I2C_CFG_OFFSET); + regval &= I2C_CFG_ALLENABLES; + regval &= ~I2C_CFG_MSTEN; + lpc54_i2c_putreg(priv, LPC54_I2C_CFG_OFFSET, regval); + +#ifndef CONFIG_I2C_POLLED + /* Disable the Flexcomm interface at the NVIC and detach the interrupt. */ + + up_disable_irq(priv->irq); + irq_detach(priv->irq); +#endif + + return OK; +} + +#endif /* HAVE_I2C_MASTER_DEVICE */ diff --git a/arch/arm/src/lpc54xx/lpc54_i2c_master.h b/arch/arm/src/lpc54xx/lpc54_i2c_master.h new file mode 100644 index 0000000000000000000000000000000000000000..1655d0fec5e174af6ad715ed4e683ff22a44fc58 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_i2c_master.h @@ -0,0 +1,87 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_i2c.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_I2C_MASTER_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_I2C_MASTER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "chip/lpc54_i2c.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_i2cbus_initialize + * + * Description: + * Initialize the selected I2C port. And return a unique instance of struct + * struct i2c_master_s. This function may be called to obtain multiple + * instances of the interface, each of which may be set up with a + * different frequency and slave address. + * + * Input Parameter: + * Port number (for hardware that has multiple I2C interfaces) + * + * Returned Value: + * Valid I2C device structure reference on succcess; a NULL on failure + * + ****************************************************************************/ + +FAR struct i2c_master_s *lpc54_i2cbus_initialize(int port); + +/**************************************************************************** + * Name: lpc54_i2cbus_uninitialize + * + * Description: + * De-initialize the selected I2C port, and power down the device. + * + * Input Parameter: + * Device structure as returned by the lpc54_i2cbus_initialize() + * + * Returned Value: + * OK on success, ERROR when internal reference count mismatch or dev + * points to invalid hardware device. + * + ****************************************************************************/ + +int lpc54_i2cbus_uninitialize(FAR struct i2c_master_s *dev); + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_I2C_MASTER_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_idle.c b/arch/arm/src/lpc54xx/lpc54_idle.c new file mode 100644 index 0000000000000000000000000000000000000000..0486e4ea805e33c45ba11cce0b73d4bc2a3d2719 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_idle.c @@ -0,0 +1,186 @@ +/**************************************************************************** + * arch/arm/src/lpc54/lpc54_idle.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include + +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +#define PM_IDLE_DOMAIN 0 /* Revisit */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void up_idlepm(void) +{ + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + irqstate_t flags; + int ret; + + /* Decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + + /* Check for state changes */ + + if (newstate != oldstate) + { + flags = enter_critical_section(); + + /* Perform board-specific, state-dependent logic here */ + + _info("newstate= %d oldstate=%d\n", newstate, oldstate); + + /* Then force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + (void)pm_changestate(PM_IDLE_DOMAIN, oldstate); + } + else + { + /* Save the new state */ + + oldstate = newstate; + } + + /* MCU-specific power management logic */ + + switch (newstate) + { + case PM_NORMAL: + break; + + case PM_IDLE: + break; + + case PM_STANDBY: + lpc54_pmstandby(true); + break; + + case PM_SLEEP: + (void)lpc54_pmsleep(); + break; + + default: + break; + } + + leave_critical_section(flags); + } +} +#else +# define up_idlepm() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + sched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + up_idlepm(); + + /* Sleep until an interrupt occurs to save power */ + + BEGIN_IDLE(); + asm("WFI"); + END_IDLE(); +#endif +} + diff --git a/arch/arm/src/lpc54xx/lpc54_irq.c b/arch/arm/src/lpc54xx/lpc54_irq.c new file mode 100644 index 0000000000000000000000000000000000000000..6397b2af05ea0f99a9e48173445be69bdba8a895 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_irq.c @@ -0,0 +1,562 @@ +/**************************************************************************** + * arch/arm/src/lpc54/lpc54_irq.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "nvic.h" +#include "ram_vectors.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc54_gpio.h" +#include "lpc54_irq.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT) + +/* Given the address of a NVIC ENABLE register, this is the offset to + * the corresponding CLEAR ENABLE register. + */ + +#define NVIC_ENA_OFFSET (0) +#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_current_regs[] holds a references to the current interrupt level + * register storage structure. If is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ + +volatile uint32_t *g_current_regs[1]; + +/* This is the address of the exception vector table (determined by the + * linker script). + */ + +extern uint32_t _vectors[]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_dumpnvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_IRQ_INFO) +static void lpc54_dumpnvic(const char *msg, int irq) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + irqinfo("NVIC (%s, irq=%d):\n", msg, irq); + irqinfo(" INTCTRL: %08x VECTAB: %08x\n", + getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); +#if 0 + irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n", + getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA), + getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE)); +#endif + irqinfo(" IRQ ENABLE: %08x %08x\n", + getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE)); + irqinfo(" SYSH_PRIO: %08x %08x %08x\n", + getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY), + getreg32(NVIC_SYSH12_15_PRIORITY)); + irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY), + getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY), + getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY), + getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY)); + irqinfo(" %08x %08x %08x\n", + getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY), + getreg32(NVIC_IRQ56_59_PRIORITY)); + + leave_critical_section(flags); +} +#else +# define lpc54_dumpnvic(msg, irq) +#endif + +/**************************************************************************** + * Name: lpc54_nmi, lpc54_busfault, lpc54_usagefault, lpc54_pendsv, + * lpc54_dbgmonitor, lpc54_pendsv, lpc54_reserved + * + * Description: + * Handlers for various exceptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +static int lpc54_nmi(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! NMI received\n"); + PANIC(); + return 0; +} + +static int lpc54_busfault(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Bus fault recived\n"); + PANIC(); + return 0; +} + +static int lpc54_usagefault(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Usage fault received\n"); + PANIC(); + return 0; +} + +static int lpc54_pendsv(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! PendSV received\n"); + PANIC(); + return 0; +} + +static int lpc54_dbgmonitor(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Debug Monitor received\n"); + PANIC(); + return 0; +} + +static int lpc54_reserved(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Reserved interrupt\n"); + PANIC(); + return 0; +} +#endif + +/**************************************************************************** + * Name: lpc54_prioritize_syscall + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void lpc54_prioritize_syscall(int priority) +{ + uint32_t regval; + + /* SVCALL is system handler 11 */ + + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); +} +#endif + +/**************************************************************************** + * Name: lpc54_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int lpc54_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, + uintptr_t offset) +{ + int n; + + DEBUGASSERT(irq >= LPC54_IRQ_NMI && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= LPC54_IRQ_EXTINT) + { + n = irq - LPC54_IRQ_EXTINT; + *regaddr = NVIC_IRQ_ENABLE(n) + offset; + *bit = (uint32_t)1 << (n & 0x1f); + } + + /* Handle processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == LPC54_IRQ_MEMFAULT) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == LPC54_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == LPC54_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == LPC54_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + * + * Description: + * Complete initialization of the interrupt system and enable normal, + * interrupt processing. + * + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uint32_t regaddr; +#ifdef CONFIG_DEBUG_FEATURES + uint32_t regval; +#endif + int num_priority_registers; + int i; + + /* Disable all interrupts */ + + for (i = 0; i < LPC54_IRQ_NEXTINT; i += 32) + { + putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); + } + + /* Make sure that we are using the correct vector table. The default + * vector address is 0x0000:0000 but if we are executing code that is + * positioned in SRAM or in external FLASH, then we may need to reset + * the interrupt vector so that it refers to the table in SRAM or in + * external FLASH. + */ + + putreg32((uint32_t)_vectors, NVIC_VECTAB); + +#ifdef CONFIG_ARCH_RAMVECTORS + /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. + */ + + up_ramvec_initialize(); +#endif + + /* Set all interrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); + + /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt + * lines that the NVIC supports: + * + * 0 -> 32 interrupt lines, 8 priority registers + * 1 -> 64 " " " ", 16 priority registers + * 2 -> 96 " " " ", 32 priority registers + * ... + */ + + num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8; + + /* Now set all of the interrupt lines to the default priority */ + + regaddr = NVIC_IRQ0_3_PRIORITY; + while (num_priority_registers--) + { + putreg32(DEFPRIORITY32, regaddr); + regaddr += 4; + } + + /* currents_regs is non-NULL only while processing an interrupt */ + + CURRENT_REGS = NULL; + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(LPC54_IRQ_SVCALL, up_svcall, NULL); + irq_attach(LPC54_IRQ_HARDFAULT, up_hardfault, NULL); + + /* Set the priority of the SVCall interrupt */ + +#ifdef CONFIG_ARCH_IRQPRIO + /* up_prioritize_irq(LPC54_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif + +#ifdef CONFIG_ARMV7M_USEBASEPRI + lpc54_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); +#endif + +#ifdef CONFIG_ARM_MPU + /* If the MPU is enabled, then attach and enable the Memory Management + * Fault handler. + */ + + irq_attach(LPC54_IRQ_MEMFAULT, up_memfault, NULL); + up_enable_irq(LPC54_IRQ_MEMFAULT); +#endif + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG_FEATURES + irq_attach(LPC54_IRQ_NMI, lpc54_nmi, NULL); +#ifndef CONFIG_ARM_MPU + irq_attach(LPC54_IRQ_MEMFAULT, up_memfault, NULL); +#endif + irq_attach(LPC54_IRQ_BUSFAULT, lpc54_busfault, NULL); + irq_attach(LPC54_IRQ_USAGEFAULT, lpc54_usagefault, NULL); + irq_attach(LPC54_IRQ_PENDSV, lpc54_pendsv, NULL); + irq_attach(LPC54_IRQ_DBGMONITOR, lpc54_dbgmonitor, NULL); + irq_attach(LPC54_IRQ_RESERVED, lpc54_reserved, NULL); +#endif + + lpc54_dumpnvic("initial", LPC54_IRQ_NIRQS); + +#if defined(CONFIG_DEBUG_FEATURES) && !defined(CONFIG_ARMV7M_USEBASEPRI) + /* If a debugger is connected, try to prevent it from catching hardfaults. + * If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal + * operation. + */ + + regval = getreg32(NVIC_DEMCR); + regval &= ~NVIC_DEMCR_VCHARDERR; + putreg32(regval, NVIC_DEMCR); +#endif + +#ifdef CONFIG_LPC54_GPIOIRQ + /* Initialize GPIO interrupts */ + + lpc54_gpio_irqinitialize(); +#endif + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + /* And finally, enable interrupts */ + + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (lpc54_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. + */ + + if (irq >= LPC54_IRQ_EXTINT) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } + } + + lpc54_dumpnvic("disable", irq); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (lpc54_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ + + if (irq >= LPC54_IRQ_EXTINT) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } + } + + lpc54_dumpnvic("enable", irq); +} + +/**************************************************************************** + * Name: up_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void up_ack_irq(int irq) +{ + lpc54_clrpend(irq); +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + DEBUGASSERT(irq >= LPC54_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); + + if (irq < LPC54_IRQ_EXTINT) + { + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; + } + else + { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + + irq -= LPC54_IRQ_EXTINT; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + lpc54_dumpnvic("prioritize", irq); + return OK; +} +#endif diff --git a/arch/arm/src/lpc54xx/lpc54_irq.h b/arch/arm/src/lpc54xx/lpc54_irq.h new file mode 100644 index 0000000000000000000000000000000000000000..50f05d7a1d50bc9c1a81b60199246dc5364ed204 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_irq.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_irq.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_IRQ_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_clrpend + * + * Description: + * Clear a pending interrupt at the NVIC. This does not seem to be + * required for most interrupts. + * + ****************************************************************************/ + +void lpc54_clrpend(int irq); + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_IRQ_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_lcd.c b/arch/arm/src/lpc54xx/lpc54_lcd.c new file mode 100644 index 0000000000000000000000000000000000000000..25cb80fc3335eae27060095864f2dd7c0591984e --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_lcd.c @@ -0,0 +1,914 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_lcd.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * This driver derives from the LPC1788 LCD driver. The LPC1788 LCD is + * identical tot he LPC54628 LCD other than some minor clocking differences. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "chip/lpc54_syscon.h" +#include "chip/lpc54_pinmux.h" +#include "lpc54_config.h" +#include "lpc54_enableclk.h" +#include "lpc54_gpio.h" +#include "lpc54_reset.h" +#include "lpc54_lcd.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LPC54_LCD_CLK_PER_LINE \ + (CONFIG_LPC54_LCD_HWIDTH + CONFIG_LPC54_LCD_HPULSE + \ + CONFIG_LPC54_LCD_HFRONTPORCH + CONFIG_LPC54_LCD_HBACKPORCH) +#define LPC54_LCD_LINES_PER_FRAME \ + (CONFIG_LPC54_LCD_VHEIGHT + CONFIG_LPC54_LCD_VPULSE + \ + CONFIG_LPC54_LCD_VFRONTPORCH + CONFIG_LPC54_LCD_VBACKPORCH) +#define LPC54_LCD_PIXEL_CLOCK \ + (LPC54_LCD_CLK_PER_LINE * LPC54_LCD_LINES_PER_FRAME * \ + CONFIG_LPC54_LCD_REFRESH_FREQ) + +/* Framebuffer characteristics in bytes */ + +#define LPC54_STRIDE ((CONFIG_LPC54_LCD_HWIDTH * LPC54_BPP + 7) / 8) +#define LPC54_FBSIZE (LPC54_STRIDE * CONFIG_LPC54_LCD_VHEIGHT) + +/* Delays */ + +#define LPC54_LCD_PWRDIS_DELAY 10000 +#define LPC54_LCD_PWREN_DELAY 10000 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Get information about the video controller configuration and the + * configuration of each color plane. + */ + +static int lpc54_getvideoinfo(FAR struct fb_vtable_s *vtable, + FAR struct fb_videoinfo_s *vinfo); +static int lpc54_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno, + FAR struct fb_planeinfo_s *pinfo); + +/* The following is provided only if the video hardware supports RGB color + * mapping + */ + +#ifdef CONFIG_FB_CMAP +static int lpc54_getcmap(FAR struct fb_vtable_s *vtable, + FAR struct fb_cmap_s *cmap); +static int lpc54_putcmap(FAR struct fb_vtable_s *vtable, + FAR const struct fb_cmap_s *cmap); +#endif + +/* The following is provided only if the video hardware supports a hardware + * cursor + */ + +#ifdef CONFIG_FB_HWCURSOR +static int lpc54_getcursor(FAR struct fb_vtable_s *vtable, + FAR struct fb_cursorattrib_s *attrib); +static int lpc54_setcursor(FAR struct fb_vtable_s *vtable, + FAR struct fb_setcursor_s *settings); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This structure describes the video controller */ + +static const struct fb_videoinfo_s g_videoinfo = +{ + .fmt = LPC54_COLOR_FMT, + .xres = CONFIG_LPC54_LCD_HWIDTH, + .yres = CONFIG_LPC54_LCD_VHEIGHT, + .nplanes = 1, +}; + +/* This structure describes the single color plane */ + +static const struct fb_planeinfo_s g_planeinfo = +{ + .fbmem = (FAR void *)CONFIG_LPC54_LCD_VRAMBASE, + .fblen = LPC54_FBSIZE, + .stride = LPC54_STRIDE, + .display = 0, + .bpp = LPC54_BPP, +}; + +/* Current cursor position */ + +#ifdef CONFIG_FB_HWCURSOR +static struct fb_cursorpos_s g_cpos; + +/* Current cursor size */ + +#ifdef CONFIG_FB_HWCURSORSIZE +static struct fb_cursorsize_s g_csize; +#endif +#endif + +/* The framebuffer object -- There is no private state information in this + * framebuffer driver. + */ + +struct fb_vtable_s g_fbobject = +{ + .getvideoinfo = lpc54_getvideoinfo, + .getplaneinfo = lpc54_getplaneinfo, +#ifdef CONFIG_FB_CMAP + .getcmap = lpc54_getcmap, + .putcmap = lpc54_putcmap, +#endif +#ifdef CONFIG_FB_HWCURSOR + .getcursor = lpc54_getcursor, + .setcursor = lpc54_setcursor, +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_getvideoinfo + ****************************************************************************/ + +static int lpc54_getvideoinfo(FAR struct fb_vtable_s *vtable, + FAR struct fb_videoinfo_s *vinfo) +{ + lcdinfo("vtable=%p vinfo=%p\n", vtable, vinfo); + if (vtable && vinfo) + { + memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); + return OK; + } + + lcderr("ERROR: Returning EINVAL\n"); + return -EINVAL; +} + +/**************************************************************************** + * Name: lpc54_getplaneinfo + ****************************************************************************/ + +static int lpc54_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno, + FAR struct fb_planeinfo_s *pinfo) +{ + lcdinfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo); + if (vtable && planeno == 0 && pinfo) + { + memcpy(pinfo, &g_planeinfo, sizeof(struct fb_planeinfo_s)); + return OK; + } + + lcderr("ERROR: Returning EINVAL\n"); + return -EINVAL; +} + +/**************************************************************************** + * Name: lpc54_getcmap + ****************************************************************************/ + +#ifdef CONFIG_FB_CMAP +static int lpc54_getcmap(FAR struct fb_vtable_s *vtable, + FAR struct fb_cmap_s *cmap) +{ + uint32_t *pal; + uint32_t rgb; + int last; + int i; + + lcdinfo("vtable=%p cmap=%p first=%d len=%d\n", + vtable, cmap, cmap->first, cmap->len); + + DEBUGASSERT(vtable && cmap && + cmap->first < 256 && (cmap->first + cmap->len) < 256); + + pal = (uint32_t *)LPC54_LCD_PAL(cmap->first >> 1); + last = cmap->first + cmap->len; + + /* Handle the case where the first color starts on an odd boundary */ + + i = cmap->first; + if ((i & 1) != 0) + { + rgb = *pal++; + i++; + + /* Save the odd palette value */ + + cmap->red[i] = (rgb & LCD_PAL_R1_MASK) >> LCD_PAL_R1_SHIFT; + cmap->green[i] = (rgb & LCD_PAL_G1_MASK) >> LCD_PAL_G1_SHIFT; + cmap->blue[i] = (rgb & LCD_PAL_B1_MASK) >> LCD_PAL_B1_SHIFT; +#ifdef CONFIG_FB_TRANSPARENCY + cmap->transp[i] = 0; +#endif + } + + /* Handle even colors */ + + for (; i < last; i += 2) + { + rgb = *pal++; + + /* Save the even palette value */ + + cmap->red[i] = (rgb & LCD_PAL_R0_MASK) >> LCD_PAL_R0_SHIFT; + cmap->green[i] = (rgb & LCD_PAL_G0_MASK) >> LCD_PAL_G0_SHIFT; + cmap->blue[i] = (rgb & LCD_PAL_B0_MASK) >> LCD_PAL_B0_SHIFT; +#ifdef CONFIG_FB_TRANSPARENCY + cmap->transp[i] = 0; +#endif + + /* Handle the case where the len ends on an odd boudary */ + + if ((i + 1) < last) + { + /* Save the even palette value */ + + cmap->red[i+1] = (rgb & LCD_PAL_R1_MASK) >> LCD_PAL_R1_SHIFT; + cmap->green[i+1] = (rgb & LCD_PAL_G1_MASK) >> LCD_PAL_G1_SHIFT; + cmap->blue[i+1] = (rgb & LCD_PAL_B1_MASK) >> LCD_PAL_B1_SHIFT; +#ifdef CONFIG_FB_TRANSPARENCY + cmap->transp[i+1] = 0; +#endif + } + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: lpc54_putcmap + ****************************************************************************/ + +#ifdef CONFIG_FB_CMAP +static int lpc54_putcmap(FAR struct fb_vtable_s *vtable, + FAR const struct fb_cmap_s *cmap) +{ + uint32_t *pal; + uint32_t rgb0; + uint32_t rgb1; + int last; + int i; + + lcdinfo("vtable=%p cmap=%p first=%d len=%d\n", + vtable, cmap, cmap->first, cmap->len); + + DEBUGASSERT(vtable && cmap); + + pal = (uint32_t *)LPC54_LCD_PAL(cmap->first >> 1); + last = cmap->first + cmap->len; + + /* Handle the case where the first color starts on an odd boundary */ + + i = cmap->first; + if ((i & 1) != 0) + { + rgb0 = *pal; + rgb0 &= (LCD_PAL_R0_MASK | LCD_PAL_G0_MASK | LCD_PAL_B0_MASK | LCD_PAL_I0); + rgb1 |= ((uint32_t)cmap->red[i] << LCD_PAL_R0_SHIFT | + (uint32_t)cmap->green[i] << LCD_PAL_G0_SHIFT | + (uint32_t)cmap->blue[i] << LCD_PAL_B0_SHIFT); + + /* Save the new palette value */ + + *pal++ = (rgb0 | rgb1); + i++; + } + + /* Handle even colors */ + + for (; i < last; i += 2) + { + uint32_t rgb0 = ((uint32_t)cmap->red[i] << LCD_PAL_R0_SHIFT | + (uint32_t)cmap->green[i] << LCD_PAL_G0_SHIFT | + (uint32_t)cmap->blue[i] << LCD_PAL_B0_SHIFT); + + /* Handle the case where the len ends on an odd boudary */ + + if ((i + 1) >= last) + { + rgb1 = *pal; + rgb1 &= (LCD_PAL_R1_MASK | LCD_PAL_G1_MASK | LCD_PAL_B1_MASK | LCD_PAL_I1); + } + else + { + rgb1 = ((uint32_t)cmap->red[i+1] << LCD_PAL_R1_SHIFT | + (uint32_t)cmap->green[i+1] << LCD_PAL_G1_SHIFT | + (uint32_t)cmap->blue[i+1] << LCD_PAL_B1_SHIFT); + } + + /* Save the new pallete value */ + + *pal++ = (rgb0 | rgb1); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: lpc54_getcursor + ****************************************************************************/ + +#ifdef CONFIG_FB_HWCURSOR +static int lpc54_getcursor(FAR struct fb_vtable_s *vtable, + FAR struct fb_cursorattrib_s *attrib) +{ + lcdinfo("vtable=%p attrib=%p\n", vtable, attrib); + if (vtable && attrib) + { +#ifdef CONFIG_FB_HWCURSORIMAGE + attrib->fmt = LPC54_COLOR_FMT; +#endif + + lcdinfo("pos: (x=%d, y=%d)\n", g_cpos.x, g_cpos.y); + attrib->pos = g_cpos; + +#ifdef CONFIG_FB_HWCURSORSIZE + attrib->mxsize.h = CONFIG_LPC54_LCD_VHEIGHT; + attrib->mxsize.w = CONFIG_LPC54_LCD_HWIDTH; + + lcdinfo("size: (h=%d, w=%d)\n", g_csize.h, g_csize.w); + attrib->size = g_csize; +#endif + return OK; + } + + lcderr("ERROR: Returning EINVAL\n"); + return -EINVAL; +} +#endif + +/**************************************************************************** + * Name: lpc54_setcursor + ****************************************************************************/ + +#ifdef CONFIG_FB_HWCURSOR +static int lpc54_setcursor(FAR struct fb_vtable_s *vtable, + FAR struct fb_setcursor_s *settings) +{ + lcdinfo("vtable=%p settings=%p\n", vtable, settings); + if (vtable && settings) + { + lcdinfo("flags: %02x\n", settings->flags); + if ((flags & FB_CUR_SETPOSITION) != 0) + { + g_cpos = settings->pos; + lcdinfo("pos: (h:%d, w:%d)\n", g_cpos.x, g_cpos.y); + } +#ifdef CONFIG_FB_HWCURSORSIZE + if ((flags & FB_CUR_SETSIZE) != 0) + { + g_csize = settings->size; + lcdinfo("size: (h:%d, w:%d)\n", g_csize.h, g_csize.w); + } +#endif +#ifdef CONFIG_FB_HWCURSORIMAGE + if ((flags & FB_CUR_SETIMAGE) != 0) + { + lcdinfo("image: (h:%d, w:%d) @ %p\n", + settings->img.height, settings->img.width, + settings->img.image); + } +#endif + return OK; + } + + lcderr("ERROR: Returning EINVAL\n"); + return -EINVAL; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_fbinitialize + * + * Description: + * Initialize the framebuffer video hardware associated with the display. + * + * Input parameters: + * display - In the case of hardware with multiple displays, this + * specifies the display. Normally this is zero. + * + * Returned Value: + * Zero is returned on success; a negated errno value is returned on any + * failure. + * + ****************************************************************************/ + +int up_fbinitialize(int display) +{ + uint32_t regval; + uint32_t bcd; + uint32_t pcd; + int i; + + /* Configure pins */ + /* LCD panel data. Pins used depend on the panel configuration: + * + * STN 4BPP: VD0-VD3 (single panel) + * VD0-VD3, VD8-VD11 (dual panel) + * STN 8BPP: VD0-VD7 (single panel) + * VD0-VD15 (dual panel) + * TFT 12BPP: VD4-VD7, VD12-VD15, VD20-VD23 + * TFT 16BPP: VD3-VD7, VD10-VD15, VD19-VD23 + * TFT 24BPP: VD0-VD23 + */ + + lcdinfo("Configuring pins\n"); + +#if !defined(CONFIG_LPC54_LCD_BPP16_565) && !defined(CONFIG_LPC54_LCD_BPP12_444) + lpc54_gpio_config(GPIO_LCD_VD0); + lpc54_gpio_config(GPIO_LCD_VD1); + lpc54_gpio_config(GPIO_LCD_VD2); +#endif +#ifndef CONFIG_LPC54_LCD_BPP12_444 + lpc54_gpio_config(GPIO_LCD_VD3); +#endif + lpc54_gpio_config(GPIO_LCD_VD4); + lpc54_gpio_config(GPIO_LCD_VD5); + lpc54_gpio_config(GPIO_LCD_VD6); + lpc54_gpio_config(GPIO_LCD_VD7); + +#if LPC54_BPP > 8 /* Or STN 8-BPP Dual panel */ +#if !defined(CONFIG_LPC54_LCD_BPP16_565) && !defined(CONFIG_LPC54_LCD_BPP12_444) + lpc54_gpio_config(GPIO_LCD_VD8); + lpc54_gpio_config(GPIO_LCD_VD9); +#endif +#ifndef CONFIG_LPC54_LCD_BPP12_444 + lpc54_gpio_config(GPIO_LCD_VD10); + lpc54_gpio_config(GPIO_LCD_VD11); +#endif + lpc54_gpio_config(GPIO_LCD_VD12); + lpc54_gpio_config(GPIO_LCD_VD13); + lpc54_gpio_config(GPIO_LCD_VD14); + lpc54_gpio_config(GPIO_LCD_VD15); +#endif + +#if LPC54_BPP > 16 || defined(CONFIG_LPC54_LCD_TFTPANEL) +#if !defined(CONFIG_LPC54_LCD_BPP16_565) && !defined(CONFIG_LPC54_LCD_BPP12_444) + lpc54_gpio_config(GPIO_LCD_VD16); + lpc54_gpio_config(GPIO_LCD_VD17); + lpc54_gpio_config(GPIO_LCD_VD18); +#endif +#ifndef CONFIG_LPC54_LCD_BPP12_444 + lpc54_gpio_config(GPIO_LCD_VD19); +#endif + lpc54_gpio_config(GPIO_LCD_VD20); + lpc54_gpio_config(GPIO_LCD_VD21); + lpc54_gpio_config(GPIO_LCD_VD22); + lpc54_gpio_config(GPIO_LCD_VD23); +#endif + + /* Other pins */ + + lpc54_gpio_config(GPIO_LCD_AC); /* STN AC bias drive or TFT data enable output */ + lpc54_gpio_config(GPIO_LCD_DCLK); /* LCD panel clock */ + lpc54_gpio_config(GPIO_LCD_FP); /* Frame pulse (STN). + * Vertical synchronization pulse (TFT) */ + lpc54_gpio_config(GPIO_LCD_LE); /* Line end signal */ + lpc54_gpio_config(GPIO_LCD_LP); /* Line synchronization pulse (STN). + * Horizontal synchronization pulse (TFT) */ + lpc54_gpio_config(GPIO_LCD_PWR); /* LCD panel power enable */ + +#ifdef CONFIG_LPC54_LCD_USE_CLKIN + lpc54_gpio_config(GPIO_LCD_CLKIN); /* Optional clock input */ +#endif + + lcdinfo("Enable clocking to the LCD controller\n"); + + /* Enable clocking to the LCD peripheral */ + + lpc54_lcd_enableclk(); + + /* Route Main clock (or LCK CLKIN) to the LCD. */ + +#ifdef CONFIG_LPC54_LCD_USE_CLKIN + putreg32(SYSCON_LCDCLKSEL_LCDCLKIN, LPC54_SYSCON_LCDCLKSEL); +#else + putreg32(SYSCON_LCDCLKSEL_MAINCLK, LPC54_SYSCON_LCDCLKSEL); +#endif + + /* Set the LCD clock divider to one. */ + + putreg32(SYSCON_LCDCLKDIV_DIV(1), LPC54_SYSCON_LCDCLKDIV); + putreg32(SYSCON_LCDCLKDIV_DIV(1) | SYSCON_LCDCLKDIV_REQFLAG, + LPC54_SYSCON_LCDCLKDIV); + + /* Reset the LCD */ + + lpc54_reset_lcd(); + + lcdinfo("Configuring the LCD controller\n"); + + /* Disable the cursor */ + + regval = getreg32(LPC54_LCD_CRSR_CRTL); + regval &= ~LCD_CRSR_CTRL_CRSON; + putreg32(regval, LPC54_LCD_CRSR_CRTL); + + /* Clear any pending interrupts */ + + putreg32(LCD_INTCLR_ALL, LPC54_LCD_INTCLR); + + /* Disable the LCD controller */ + + putreg32(0, LPC54_LCD_CTRL); + + /* Set the bits per pixel */ + + regval = getreg32(LPC54_LCD_CTRL); + regval &= ~LCD_CTRL_LCDBPP_MASK; + +#if defined(CONFIG_LPC54_LCD_BPP1) + regval |= LCD_CTRL_LCDBPP_1; /* 1 bpp */ +#elif defined(CONFIG_LPC54_LCD_BPP2) + regval |= LCD_CTRL_LCDBPP_2; /* 2 bpp */ +#elif defined(CONFIG_LPC54_LCD_BPP4) + regval |= LCD_CTRL_LCDBPP_4; /* 4 bpp */ +#elif defined(CONFIG_LPC54_LCD_BPP8) + regval |= LCD_CTRL_LCDBPP_8; /* 8 bpp */ +#elif defined(CONFIG_LPC54_LCD_BPP16) + regval |= LCD_CTRL_LCDBPP_16; /* 16 bpp */ +#elif defined(CONFIG_LPC54_LCD_BPP24) + regval |= LCD_CTRL_LCDBPP_24; /* 24-bit TFT panel only */ +#elif defined(CONFIG_LPC54_LCD_BPP16_565) + regval |= LCD_CTRL_LCDBPP_565; /* 16 bpp, 5:6:5 mode */ +#else /* defined(CONFIG_LPC54_LCD_BPP12_444) */ + regval |= LCD_CTRL_LCDBPP_444; /* 12 bpp, 4:4:4 mode */ +#endif + +#ifdef CONFIG_LPC54_LCD_TFTPANEL + /* TFT panel */ + + regval |= LCD_CTRL_LCDTFT; +#else + /* STN panel */ + + regval &= ~LCD_CTRL_LCDTFT; +#endif + +#ifdef CONFIG_LPC54_LCD_BGR + /* Swap red and blue. The colors will be 0x00RRGGBB, not 0x00BBGGRR. */ + + regval |= LCD_CTRL_BGR; +#else + regval &= ~LCD_CTRL_BGR; +#endif + + /* Single panel */ + + regval &= ~LCD_CTRL_LCDDUAL; + + /* Select monochrome or color LCD */ + +#ifdef CONFIG_LPC54_LCD_MONOCHROME + /* Select monochrome LCD */ + + regval &= ~LCD_CTRL_BGR; + + /* Select 4- or 8-bit monochrome interface */ + +#if LPC54_BPP > 4 + regval |= LCD_CTRL_LCDMONO8; +#else + regval &= ~LCD_CTRL_LCDMONO8; +#endif + +#else + /* Select color LCD */ + + regval &= ~(LCD_CTRL_LCDBW | LCD_CTRL_LCDMONO8); + +#endif /* CONFIG_LPC54_LCD_MONOCHROME */ + + /* Little endian byte order */ + + regval &= ~LCD_CTRL_BEBO; + + /* Little endian pixel order */ + + regval &= ~LCD_CTRL_BEPO; + putreg32(regval, LPC54_LCD_CTRL); + + /* Initialize horizontal timing */ + + putreg32(0, LPC54_LCD_TIMH); + + regval = (((CONFIG_LPC54_LCD_HWIDTH/16) - 1) << LCD_TIMH_PPL_SHIFT | + (CONFIG_LPC54_LCD_HPULSE - 1) << LCD_TIMH_HSW_SHIFT | + (CONFIG_LPC54_LCD_HFRONTPORCH - 1) << LCD_TIMH_HFP_SHIFT | + (CONFIG_LPC54_LCD_HBACKPORCH - 1) << LCD_TIMH_HBP_SHIFT); + putreg32(regval, LPC54_LCD_TIMH); + + /* Initialize vertical timing */ + + putreg32(0, LPC54_LCD_TIMV); + + regval = ((CONFIG_LPC54_LCD_VHEIGHT - 1) << LCD_TIMV_LPP_SHIFT | + (CONFIG_LPC54_LCD_VPULSE - 1) << LCD_TIMV_VSW_SHIFT | + (CONFIG_LPC54_LCD_VFRONTPORCH) << LCD_TIMV_VFP_SHIFT | + (CONFIG_LPC54_LCD_VBACKPORCH) << LCD_TIMV_VBP_SHIFT); + putreg32(regval, LPC54_LCD_TIMV); + + /* Get the pixel clock divider */ + +#ifdef CONFIG_LPC54_LCD_USE_CLKIN + pcd = ((uint32_t)CONFIG_LPC54_LCD_CLKIN_FREQUENCY / + (uint32_t)LPC54_LCD_PIXEL_CLOCK) + 1; +#else + pcd = ((uint32_t)BOARD_MAIN_CLK / (uint32_t)LPC54_LCD_PIXEL_CLOCK); +#endif + + /* Check the range of pcd */ + + bcd = 0; + +#ifndef CONFIG_LPC54_LCD_TFTPANEL + DEBUGASSERT(pcd >= 2); +#else + if (pcd <= 1) + { + /* Just bypass the LCD divider */ + + pcd = 0; + bcd = LCD_POL_BCD; + } + else +#endif + { + /* The register value is PCD - 2 */ + + pcd -= 2; + } + + /* Initialize clock and signal polarity. + * + * REVISIT: These need to be configurable. + */ + + regval = getreg32(LPC54_LCD_POL); + + /* LCDFP pin is active LOW and inactive HIGH */ + + regval |= LCD_POL_IVS; + + /* LCDLP pin is active LOW and inactive HIGH */ + + regval |= LCD_POL_IHS; + + /* Data is driven out into the LCD on the falling edge */ + + regval &= ~LCD_POL_IPC; + + /* Set number of clocks per line */ + + regval &= ~LCD_POL_CPL_MASK; + +#if defined(CONFIG_LPC54_LCD_TFTPANEL) + /* TFT panel */ + + regval |= LCD_POL_CPL(CONFIG_LPC54_LCD_HWIDTH - 1); +#else + /* STN panel */ + +#if defined(CONFIG_LPC54_LCD_BPP8) + /* 8-bit monochrome STN panel */ + + regval |= LCD_POL_CPL((CONFIG_LPC54_LCD_HWIDTH / 8) - 1); +#elif defined(CONFIG_LPC54_LCD_BPP4) + /* 4-bit monochrome STN panel */ + + regval |= LCD_POL_CPL((CONFIG_LPC54_LCD_HWIDTH / 4) - 1); +#else + /* Color STN panel. */ + + regval |= LCD_POL_CPL(((CONFIG_LPC54_LCD_HWIDTH * 3) / 8) - 1); +#endif +#endif /* CONFIG_LPC54_LCD_TFTPANEL */ + + /* Set pixel clock divisor (or bypass) */ + + regval &= ~(LCD_POL_PCDLO_MASK | LCD_POL_PCDHI_MASK | LCD_POL_BCD); + regval |= LCD_POL_PCDLO(pcd) & LCD_POL_PCDLO_MASK; + regval |= LCD_POL_PCDHI(pcd >> 5) & LCD_POL_PCDHI_MASK; + regval |= bcd; + + /* LCD_ENAB_M is active high */ + + regval &= ~LCD_POL_IOE; + putreg32(regval, LPC54_LCD_POL); + + /* Frame base address doubleword aligned */ + + putreg32(CONFIG_LPC54_LCD_VRAMBASE & ~7, LPC54_LCD_UPBASE); + putreg32(CONFIG_LPC54_LCD_VRAMBASE & ~7, LPC54_LCD_LPBASE); + + /* Clear the display */ + + lpc54_lcdclear(CONFIG_LPC54_LCD_BACKCOLOR); + +#ifdef CONFIG_LPC54_LCD_BACKLIGHT + /* Turn on the back light */ + + lpc54_backlight(true); +#endif + + putreg32(0, LPC54_LCD_INTMSK); + lcdinfo("Enabling the display\n"); + + for (i = LPC54_LCD_PWREN_DELAY; i; i--) + { + } + + /* Enable LCD */ + + regval = getreg32(LPC54_LCD_CTRL); + regval |= LCD_CTRL_LCDEN; + putreg32(regval, LPC54_LCD_CTRL); + + /* Enable LCD power */ + + for (i = LPC54_LCD_PWREN_DELAY; i; i--) + { + } + + regval = getreg32(LPC54_LCD_CTRL); + regval |= LCD_CTRL_LCDPWR; + putreg32(regval, LPC54_LCD_CTRL); + + return OK; +} + +/**************************************************************************** + * Name: up_fbgetvplane + * + * Description: + * Return a a reference to the framebuffer object for the specified video + * plane of the specified plane. Many OSDs support multiple planes of video. + * + * Input parameters: + * display - In the case of hardware with multiple displays, this + * specifies the display. Normally this is zero. + * vplane - Identifies the plane being queried. + * + * Returned Value: + * A non-NULL pointer to the frame buffer access structure is returned on + * success; NULL is returned on any failure. + * + ****************************************************************************/ + +FAR struct fb_vtable_s *up_fbgetvplane(int display, int vplane) +{ + lcdinfo("vplane: %d\n", vplane); + if (vplane == 0) + { + return &g_fbobject; + } + else + { + return NULL; + } +} + +/**************************************************************************** + * Name: up_fbuninitialize + * + * Description: + * Uninitialize the framebuffer support for the specified display. + * + * Input Parameters: + * display - In the case of hardware with multiple displays, this + * specifies the display. Normally this is zero. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_fbuninitialize(int display) +{ + uint32_t regval; + int i; + + /* We assume there is only one use of the LCD and so we do not need to + * worry about mutually exclusive access to the LCD hardware. + */ + +#ifdef CONFIG_LPC54_LCD_BACKLIGHT + /* Turn off the back light */ + + lpc54_backlight(false); +#endif + + /* Disable the LCD controller */ + + regval = getreg32(LPC54_LCD_CTRL); + regval &= ~LCD_CTRL_LCDPWR; + putreg32(regval, LPC54_LCD_CTRL); + + for (i = LPC54_LCD_PWRDIS_DELAY; i; i--) + { + } + + regval &= ~LCD_CTRL_LCDEN; + putreg32(regval, LPC54_LCD_CTRL); + + /* Turn off clocking to the LCD. modifyreg32() can do this atomically. */ + + putreg32(SYSCON_LCDCLKSEL_NONE, LPC54_SYSCON_LCDCLKSEL); + + /* Disable clocking to the LCD peripheral */ + + lpc54_lcd_disableclk(); +} + +/**************************************************************************** + * Name: lpc54_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the LPC54xx. Clearing + * the display in the normal way by writing a sequences of runs that + * covers the entire display can be slow. Here the dispaly is cleared by + * simply setting all VRAM memory to the specified color. + * + ****************************************************************************/ + +void lpc54_lcdclear(nxgl_mxpixel_t color) +{ + int i; +#if LPC54_BPP > 16 + uint32_t *dest = (uint32_t *)CONFIG_LPC54_LCD_VRAMBASE; + + lcdinfo("Clearing display: color=%08x VRAM=%08x size=%d\n", + color, CONFIG_LPC54_LCD_VRAMBASE, + CONFIG_LPC54_LCD_HWIDTH * CONFIG_LPC54_LCD_VHEIGHT * sizeof(uint32_t)); + +#else + uint16_t *dest = (uint16_t *)CONFIG_LPC54_LCD_VRAMBASE; + + lcdinfo("Clearing display: color=%08x VRAM=%08x size=%d\n", + color, CONFIG_LPC54_LCD_VRAMBASE, + CONFIG_LPC54_LCD_HWIDTH * CONFIG_LPC54_LCD_VHEIGHT * sizeof(uint16_t)); +#endif + + for (i = 0; i < (CONFIG_LPC54_LCD_HWIDTH * CONFIG_LPC54_LCD_VHEIGHT); i++) + { + *dest++ = color; + } +} diff --git a/arch/arm/src/lpc54xx/lpc54_lcd.h b/arch/arm/src/lpc54xx/lpc54_lcd.h new file mode 100644 index 0000000000000000000000000000000000000000..0ffb53ec813ee88e9b609d39fe1717b7df83f2ed --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_lcd.h @@ -0,0 +1,189 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_lcd.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The LPC54 LCD driver uses the common framebuffer interfaces declared in + * include/nuttx/video/fb.h. + */ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_LCD_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_LCD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "chip/lpc54_lcd.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration */ + +/* Base address of the video RAM frame buffer */ + +#ifndef CONFIG_LPC54_LCD_VRAMBASE +# define CONFIG_LPC54_LCD_VRAMBASE ((uint32_t)LPC54_EXTDRAM_CS0 + 0x00010000) +#endif + +/* LCD refresh rate */ + +#ifndef CONFIG_LPC54_LCD_REFRESH_FREQ +# define CONFIG_LPC54_LCD_REFRESH_FREQ (50) /* Hz */ +#endif + +/* Bits per pixel / color format */ + +#undef LPC54_COLOR_FMT +#if defined(CONFIG_LPC54_LCD_BPP1) +# define LPC54_BPP 1 +# define LPC54_COLOR_FMT FB_FMT_Y1 +#elif defined(CONFIG_LPC54_LCD_BPP2) +# define LPC54_BPP 2 +# define LPC54_COLOR_FMT FB_FMT_Y2 +#elif defined(CONFIG_LPC54_LCD_BPP4) +# define LPC54_BPP 4 +# define LPC54_COLOR_FMT FB_FMT_Y4 +#elif defined(CONFIG_LPC54_LCD_BPP8) +# define LPC54_BPP 8 +# define LPC54_COLOR_FMT FB_FMT_Y8 +#elif defined(CONFIG_LPC54_LCD_BPP12_444) +# define LPC54_BPP 1 12 +# define LPC54_COLOR_FMT FB_FMT_RGB12_444 +#elif defined(CONFIG_LPC54_LCD_BPP16) +# define LPC54_BPP 16 +# define LPC54_COLOR_FMT FB_FMT_Y16 +#elif defined(CONFIG_LPC54_LCD_BPP16_565) +# define LPC54_BPP 16 +# define LPC54_COLOR_FMT FB_FMT_RGB16_565 +#elif defined(CONFIG_LPC54_LCD_BPP24) +# define LPC54_BPP 32 /* Only 24 of 32 bits used for RGB */ +# define LPC54_COLOR_FMT FB_FMT_RGB24 +# ifndef CONFIG_LPC54_LCD_TFTPANEL +# error "24 BPP is only available for a TFT panel" +# endif +#else +# ifndef CONFIG_LPC54_LCD_TFTPANEL +# warning "Assuming 24 BPP" +# define LPC54_BPP 24 +# define CONFIG_LPC54_LCD_BPP24 1 +# define LPC54_COLOR_FMT FB_FMT_RGB24 +# else +# warning "Assuming 16 BPP 5:6:5" +# define LPC54_BPP 16 +# define CONFIG_LPC54_LCD_BPP16_565 1 +# define LPC54_COLOR_FMT FB_FMT_RGB16_565 +# endif +#endif + +/* Background color */ + +#ifndef CONFIG_LPC54_LCD_BACKCOLOR +# define CONFIG_LPC54_LCD_BACKCOLOR 0 /* Initial background color */ +#endif + +/* Horizontal video characteristics */ + +#ifndef CONFIG_LPC54_LCD_HWIDTH +# define CONFIG_LPC54_LCD_HWIDTH 480 /* Width in pixels */ +#endif + +#ifndef CONFIG_LPC54_LCD_HPULSE +# define CONFIG_LPC54_LCD_HPULSE 2 +#endif + +#ifndef CONFIG_LPC54_LCD_HFRONTPORCH +# define CONFIG_LPC54_LCD_HFRONTPORCH 5 +#endif + +#ifndef CONFIG_LPC54_LCD_HBACKPORCH +# define CONFIG_LPC54_LCD_HBACKPORCH 40 +#endif + +/* Vertical video characteristics */ + +#ifndef CONFIG_LPC54_LCD_VHEIGHT +# define CONFIG_LPC54_LCD_VHEIGHT 272 /* Height in rows */ +#endif + +#ifndef CONFIG_LPC54_LCD_VPULSE +# define CONFIG_LPC54_LCD_VPULSE 2 +#endif + +#ifndef CONFIG_LPC54_LCD_VFRONTPORCH +# define CONFIG_LPC54_LCD_VFRONTPORCH 8 +#endif + +#ifndef CONFIG_LPC54_LCD_VBACKPORCH +# define CONFIG_LPC54_LCD_VBACKPORCH 8 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the LPC54xx. Clearing + * the display in the normal way by writing a sequences of runs that + * covers the entire display can be slow. Here the dispaly is cleared by + * simply setting all VRAM memory to the specified color. + * + ****************************************************************************/ + +void lpc54_lcdclear(nxgl_mxpixel_t color); + +/**************************************************************************** + * Name: lpc54_backlight + * + * Description: + * If CONFIG_LPC54_LCD_BACKLIGHT is defined, then the board-specific logic + * must provide this interface to turn the backlight on and off. + * + ****************************************************************************/ + +#ifdef CONFIG_LPC54_LCD_BACKLIGHT +void lpc54_backlight(bool blon); +#endif + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_LCD_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_lowputc.c b/arch/arm/src/lpc54xx/lpc54_lowputc.c new file mode 100644 index 0000000000000000000000000000000000000000..9d556bae14ff7e76e5eed88ad72b7d90a3f95b3d --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_lowputc.c @@ -0,0 +1,831 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/lpc54_lowputc.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Parts of this file were adapted from sample code provided for the LPC54xx + * family from NXP which has a compatible BSD license. + * + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016 - 2017 , NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "chip/lpc54_memorymap.h" +#include "chip/lpc54_syscon.h" +#include "chip/lpc54_flexcomm.h" +#include "chip/lpc54_pinmux.h" +#include "chip/lpc54_usart.h" + +#include "lpc54_config.h" +#include "lpc54_enableclk.h" +#include "lpc54_clockconfig.h" +#include "lpc54_gpio.h" +#include "lpc54_lowputc.h" + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#if defined(CONFIG_USART0_SERIAL_CONSOLE) +# define CONSOLE_BASE LPC54_FLEXCOMM0_BASE +# define CONSOLE_BAUD CONFIG_USART0_BAUD +# define CONSOLE_FCLK BOARD_FLEXCOMM0_FCLK +# define CONSOLE_PARITY CONFIG_USART0_PARITY +# define CONSOLE_BITS CONFIG_USART0_BITS +# ifdef CONFIG_USART0_2STOP +# define CONSOLE_STOPBITS2 true +# else +# define CONSOLE_STOPBITS2 false +# endif +# ifdef CONFIG_USART0_IFLOWCONTROL +# define CONSOLE_IFLOW true +# else +# define CONSOLE_IFLOW false +# endif +# ifdef CONFIG_USART0_OFLOWCONTROL +# define CONSOLE_OFLOW true +# else +# define CONSOLE_OFLOW false +# endif +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) +# define CONSOLE_BASE LPC54_FLEXCOMM1_BASE +# define CONSOLE_BAUD CONFIG_USART1_BAUD +# define CONSOLE_FCLK BOARD_FLEXCOMM1_FCLK +# define CONSOLE_PARITY CONFIG_USART1_PARITY +# define CONSOLE_BITS CONFIG_USART1_BITS +# ifdef CONFIG_USART1_2STOP +# define CONSOLE_STOPBITS2 true +# else +# define CONSOLE_STOPBITS2 false +# endif +# ifdef CONFIG_USART1_IFLOWCONTROL +# define CONSOLE_IFLOW true +# else +# define CONSOLE_IFLOW false +# endif +# ifdef CONFIG_USART1_OFLOWCONTROL +# define CONSOLE_OFLOW true +# else +# define CONSOLE_OFLOW false +# endif +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) +# define CONSOLE_BASE LPC54_FLEXCOMM2_BASE +# define CONSOLE_BAUD CONFIG_USART2_BAUD +# define CONSOLE_FCLK BOARD_FLEXCOMM2_FCLK +# define CONSOLE_PARITY CONFIG_USART2_PARITY +# define CONSOLE_BITS CONFIG_USART2_BITS +# ifdef CONFIG_USART2_2STOP +# define CONSOLE_STOPBITS2 true +# else +# define CONSOLE_STOPBITS2 false +# endif +# ifdef CONFIG_USART2_IFLOWCONTROL +# define CONSOLE_IFLOW true +# else +# define CONSOLE_IFLOW false +# endif +# ifdef CONFIG_USART2_OFLOWCONTROL +# define CONSOLE_OFLOW true +# else +# define CONSOLE_OFLOW false +# endif +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) +# define CONSOLE_BASE LPC54_FLEXCOMM3_BASE +# define CONSOLE_BAUD CONFIG_USART3_BAUD +# define CONSOLE_FCLK BOARD_FLEXCOMM3_FCLK +# define CONSOLE_PARITY CONFIG_USART3_PARITY +# define CONSOLE_BITS CONFIG_USART3_BITS +# ifdef CONFIG_USART3_2STOP +# define CONSOLE_STOPBITS2 true +# else +# define CONSOLE_STOPBITS2 false +# endif +# ifdef CONFIG_USART3_IFLOWCONTROL +# define CONSOLE_IFLOW true +# else +# define CONSOLE_IFLOW false +# endif +# ifdef CONFIG_USART3_OFLOWCONTROL +# define CONSOLE_OFLOW true +# else +# define CONSOLE_OFLOW false +# endif +#elif defined(CONFIG_USART4_SERIAL_CONSOLE) +# define CONSOLE_BASE LPC54_FLEXCOMM4_BASE +# define CONSOLE_BAUD CONFIG_USART4_BAUD +# define CONSOLE_FCLK BOARD_FLEXCOMM4_FCLK +# define CONSOLE_PARITY CONFIG_USART4_PARITY +# define CONSOLE_BITS CONFIG_USART4_BITS +# ifdef CONFIG_USART4_2STOP +# define CONSOLE_STOPBITS2 true +# else +# define CONSOLE_STOPBITS2 false +# endif +# ifdef CONFIG_USART4_IFLOWCONTROL +# define CONSOLE_IFLOW true +# else +# define CONSOLE_IFLOW false +# endif +# ifdef CONFIG_USART4_OFLOWCONTROL +# define CONSOLE_OFLOW true +# else +# define CONSOLE_OFLOW false +# endif +#elif defined(CONFIG_USART5_SERIAL_CONSOLE) +# define CONSOLE_BASE LPC54_FLEXCOMM5_BASE +# define CONSOLE_BAUD CONFIG_USART5_BAUD +# define CONSOLE_FCLK BOARD_FLEXCOMM5_FCLK +# define CONSOLE_PARITY CONFIG_USART5_PARITY +# define CONSOLE_BITS CONFIG_USART5_BITS +# ifdef CONFIG_USART5_2STOP +# define CONSOLE_STOPBITS2 true +# else +# define CONSOLE_STOPBITS2 false +# endif +# ifdef CONFIG_USART5_IFLOWCONTROL +# define CONSOLE_IFLOW true +# else +# define CONSOLE_IFLOW false +# endif +# ifdef CONFIG_USART5_OFLOWCONTROL +# define CONSOLE_OFLOW true +# else +# define CONSOLE_OFLOW false +# endif +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) +# define CONSOLE_BASE LPC54_FLEXCOMM6_BASE +# define CONSOLE_BAUD CONFIG_USART6_BAUD +# define CONSOLE_FCLK BOARD_FLEXCOMM6_FCLK +# define CONSOLE_PARITY CONFIG_USART6_PARITY +# define CONSOLE_BITS CONFIG_USART6_BITS +# ifdef CONFIG_USART6_2STOP +# define CONSOLE_STOPBITS2 true +# else +# define CONSOLE_STOPBITS2 false +# endif +# ifdef CONFIG_USART6_IFLOWCONTROL +# define CONSOLE_IFLOW true +# else +# define CONSOLE_IFLOW false +# endif +# ifdef CONFIG_USART6_OFLOWCONTROL +# define CONSOLE_OFLOW true +# else +# define CONSOLE_OFLOW false +# endif +#elif defined(CONFIG_USART7_SERIAL_CONSOLE) +# define CONSOLE_BASE LPC54_FLEXCOMM7_BASE +# define CONSOLE_BAUD CONFIG_USART7_BAUD +# define CONSOLE_FCLK BOARD_FLEXCOMM7_FCLK +# define CONSOLE_PARITY CONFIG_USART7_PARITY +# define CONSOLE_BITS CONFIG_USART7_BITS +# ifdef CONFIG_USART7_2STOP +# define CONSOLE_STOPBITS2 true +# else +# define CONSOLE_STOPBITS2 false +# endif +# ifdef CONFIG_USART7_IFLOWCONTROL +# define CONSOLE_IFLOW true +# else +# define CONSOLE_IFLOW false +# endif +# ifdef CONFIG_USART7_OFLOWCONTROL +# define CONSOLE_OFLOW true +# else +# define CONSOLE_OFLOW false +# endif +#elif defined(CONFIG_USART8_SERIAL_CONSOLE) +# define CONSOLE_BASE LPC54_FLEXCOMM8_BASE +# define CONSOLE_BAUD CONFIG_USART8_BAUD +# define CONSOLE_FCLK BOARD_FLEXCOMM8_FCLK +# define CONSOLE_PARITY CONFIG_USART8_PARITY +# define CONSOLE_BITS CONFIG_USART8_BITS +# ifdef CONFIG_USART8_2STOP +# define CONSOLE_STOPBITS2 true +# else +# define CONSOLE_STOPBITS2 false +# endif +# ifdef CONFIG_USART8_IFLOWCONTROL +# define CONSOLE_IFLOW true +# else +# define CONSOLE_IFLOW false +# endif +# ifdef CONFIG_USART8_OFLOWCONTROL +# define CONSOLE_OFLOW true +# else +# define CONSOLE_OFLOW false +# endif +#elif defined(CONFIG_USART9_SERIAL_CONSOLE) +# define CONSOLE_BASE LPC54_FLEXCOMM9_BASE +# define CONSOLE_BAUD CONFIG_USART9_BAUD +# define CONSOLE_FCLK BOARD_FLEXCOMM9_FCLK +# define CONSOLE_PARITY CONFIG_USART9_PARITY +# define CONSOLE_BITS CONFIG_USART9_BITS +# ifdef CONFIG_USART9_2STOP +# define CONSOLE_STOPBITS2 true +# else +# define CONSOLE_STOPBITS2 false +# endif +# ifdef CONFIG_USART9_IFLOWCONTROL +# define CONSOLE_IFLOW true +# else +# define CONSOLE_IFLOW false +# endif +# ifdef CONFIG_USART9_OFLOWCONTROL +# define CONSOLE_OFLOW true +# else +# define CONSOLE_OFLOW false +# endif +#endif + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +#ifdef HAVE_USART_CONSOLE +/* USART console configuration */ + +static const struct uart_config_s g_console_config= +{ + .baud = CONSOLE_BAUD, + .fclk = CONSOLE_FCLK, + .parity = CONSOLE_PARITY, + .bits = CONSOLE_BITS, + .txlevel = LPC54_USART_FIFO_DEPTH / 2, + .rxlevel = 0, + .stopbits2 = CONSOLE_STOPBITS2, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .iflow = CONSOLE_IFLOW, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + .oflow = CONSOLE_OFLOW, +#endif +}; +#endif /* HAVE_USART_CONSOLE */ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lp54_setbaud + * + * Description: + * Configure the USART BAUD. + * + ************************************************************************************/ + +#ifdef HAVE_USART_DEVICE +static void lp54_setbaud(uintptr_t base, FAR const struct uart_config_s *config) +{ + uint32_t bestdiff = (uint32_t)-1; + uint32_t bestosr = 15; + uint32_t bestbrg = (uint32_t)-1; + uint32_t lastosr = 0; /* Initialized only to avoid warnings */ + uint32_t lastbrg = 0; + uint32_t osr; + uint32_t brg; + uint32_t diff; + uint32_t baud; + + /* Smaller values of OSR can make the sampling position within a data bit less + * accurate and may potentially cause more noise errors or incorrect data. + */ + + for (osr = bestosr; osr >= 8; osr--) + { + brg = (config->fclk / ((osr + 1) * config->baud)) - 1; + if (brg > 0xffff) + { + continue; + } + + baud = config->fclk / ((osr + 1) * (brg + 1)); + if (config->baud < baud) + { + diff = baud - config->baud; + } + else + { + diff = config->baud - baud; + } + + if (diff < bestdiff) + { + bestdiff = diff; + bestosr = osr; + bestbrg = brg; + } + + lastosr = osr; + lastbrg = brg; + } + + /* Check for value over range */ + + if (bestbrg > 0xffff) + { + bestosr = lastosr; + bestbrg = lastbrg; + } + + putreg32(bestosr, base + LPC54_USART_OSR_OFFSET); + putreg32(bestbrg, base + LPC54_USART_BRG_OFFSET); +} +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc54_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level initialization + * including setup of the console USART. This USART initialization is done + * early so that the serial console is available for debugging very early in + * the boot sequence. + * + ************************************************************************************/ + +void lpc54_lowsetup(void) +{ + /* Enable the IOCON and all GPIO modules */ + + putreg32(SYSCON_AHBCLKCTRL0_IOCON | SYSCON_AHBCLKCTRL0_GPIO0 | + SYSCON_AHBCLKCTRL0_GPIO1 | SYSCON_AHBCLKCTRL0_GPIO2 | + SYSCON_AHBCLKCTRL0_GPIO3, LPC54_SYSCON_AHBCLKCTRLSET0); + + putreg32(SYSCON_AHBCLKCTRL2_GPIO4 | SYSCON_AHBCLKCTRL2_GPIO5, + LPC54_SYSCON_AHBCLKCTRLSET2); + + /* TODO: Configure Fractional Rate Generator in case it is selected as a Flexcomm + * clock source. + */ + +#ifdef HAVE_USART_DEVICE +#ifdef HAVE_USART0 + /* Attach 12 MHz clock to FLEXCOMM0 */ + + lpc54_flexcomm0_enableclk(); + + /* Set FLEXCOMM0 to the USART peripheral, locking that configuration in place. */ + + putreg32(FLEXCOMM_PSELID_PERSEL_USART | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM0_PSELID); + + /* Configure USART0 pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_USART0_RXD); + lpc54_gpio_config(GPIO_USART0_TXD); +#ifdef CONFIG_USART0_OFLOWCONTROL + lpc54_gpio_config(GPIO_USART0_CTS); +#endif +#ifdef CONFIG_USART0_IFLOWCONTROL + lpc54_gpio_config(GPIO_USART0_RTS); +#endif + + /* Set up the FLEXCOMM0 function clock */ + + putreg32(BOARD_FLEXCOMM0_CLKSEL, LPC54_SYSCON_FCLKSEL0); + +#endif +#ifdef HAVE_USART1 + /* Attach 12 MHz clock to FLEXCOMM1 */ + + lpc54_flexcomm1_enableclk(); + + /* Set FLEXCOMM1 to the USART peripheral, locking that configuration in place. */ + + putreg32(FLEXCOMM_PSELID_PERSEL_USART | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM1_PSELID); + + /* Configure USART1 pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_USART1_RXD); + lpc54_gpio_config(GPIO_USART1_TXD); +#ifdef CONFIG_USART1_OFLOWCONTROL + lpc54_gpio_config(GPIO_USART1_CTS); +#endif +#ifdef CONFIG_USART1_IFLOWCONTROL + lpc54_gpio_config(GPIO_USART1_RTS); +#endif + + /* Set up the FLEXCOMM1 function clock */ + + putreg32(BOARD_FLEXCOMM1_CLKSEL, LPC54_SYSCON_FCLKSEL1); + +#endif +#ifdef HAVE_USART2 + /* Attach 12 MHz clock to FLEXCOMM2 */ + + lpc54_flexcomm2_enableclk(); + + /* Set FLEXCOMM2 to the USART peripheral, locking that configuration in place. */ + + putreg32(FLEXCOMM_PSELID_PERSEL_USART | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM2_PSELID); + + /* Configure USART2 pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_USART2_RXD); + lpc54_gpio_config(GPIO_USART2_TXD); +#ifdef CONFIG_USART2_OFLOWCONTROL + lpc54_gpio_config(GPIO_USART2_CTS); +#endif +#ifdef CONFIG_USART2_IFLOWCONTROL + lpc54_gpio_config(GPIO_USART2_RTS); +#endif + + /* Set up the FLEXCOMM0 function clock */ + + putreg32(BOARD_FLEXCOMM2_CLKSEL, LPC54_SYSCON_FCLKSEL2); + +#endif +#ifdef HAVE_USART3 + /* Attach 12 MHz clock to FLEXCOMM3 */ + + lpc54_flexcomm3_enableclk(); + + /* Set FLEXCOMM3 to the USART peripheral, locking that configuration in place. */ + + putreg32(FLEXCOMM_PSELID_PERSEL_USART | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM3_PSELID); + + /* Configure USART3 pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_USART3_RXD); + lpc54_gpio_config(GPIO_USART3_TXD); +#ifdef CONFIG_USART3_OFLOWCONTROL + lpc54_gpio_config(GPIO_USART3_CTS); +#endif +#ifdef CONFIG_USART3_IFLOWCONTROL + lpc54_gpio_config(GPIO_USART3_RTS); +#endif + + /* Set up the FLEXCOMM3 function clock */ + + putreg32(BOARD_FLEXCOMM3_CLKSEL, LPC54_SYSCON_FCLKSEL3); + +#endif +#ifdef HAVE_USART4 + /* Attach 12 MHz clock to FLEXCOMM4 */ + + lpc54_flexcomm4_enableclk(); + + /* Set FLEXCOMM4 to the USART peripheral, locking that configuration in place. */ + + putreg32(FLEXCOMM_PSELID_PERSEL_USART | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM4_PSELID); + + /* Configure USART4 pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_USART4_RXD); + lpc54_gpio_config(GPIO_USART4_TXD); +#ifdef CONFIG_USART4_OFLOWCONTROL + lpc54_gpio_config(GPIO_USART4_CTS); +#endif +#ifdef CONFIG_USART4_IFLOWCONTROL + lpc54_gpio_config(GPIO_USART4_RTS); +#endif + + /* Set up the FLEXCOMM4 function clock */ + + putreg32(BOARD_FLEXCOMM4_CLKSEL, LPC54_SYSCON_FCLKSEL4); + +#endif +#ifdef HAVE_USART5 + /* Attach 12 MHz clock to FLEXCOMM5 */ + + lpc54_flexcomm5_enableclk(); + + /* Set FLEXCOMM5 to the USART peripheral, locking that configuration in place. */ + + putreg32(FLEXCOMM_PSELID_PERSEL_USART | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM5_PSELID); + + /* Configure USART5 pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_USART5_RXD); + lpc54_gpio_config(GPIO_USART5_TXD); +#ifdef CONFIG_USART5_OFLOWCONTROL + lpc54_gpio_config(GPIO_USART5_CTS); +#endif +#ifdef CONFIG_USART5_IFLOWCONTROL + lpc54_gpio_config(GPIO_USART5_RTS); +#endif + + /* Set up the FLEXCOMM5 function clock */ + + putreg32(BOARD_FLEXCOMM5_CLKSEL, LPC54_SYSCON_FCLKSEL5); + +#endif +#ifdef HAVE_USART6 + /* Attach 12 MHz clock to FLEXCOMM6 */ + + lpc54_flexcomm6_enableclk(); + + /* Set FLEXCOMM6 to the USART peripheral, locking that configuration in place. */ + + putreg32(FLEXCOMM_PSELID_PERSEL_USART | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM6_PSELID); + + /* Configure USART6 pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_USART6_RXD); + lpc54_gpio_config(GPIO_USART6_TXD); +#ifdef CONFIG_USART6_OFLOWCONTROL + lpc54_gpio_config(GPIO_USART6_CTS); +#endif +#ifdef CONFIG_USART6_IFLOWCONTROL + lpc54_gpio_config(GPIO_USART6_RTS); +#endif + + /* Set up the FLEXCOMM6 function clock */ + + putreg32(BOARD_FLEXCOMM6_CLKSEL, LPC54_SYSCON_FCLKSEL6); + +#endif +#ifdef HAVE_USART7 + /* Attach 12 MHz clock to FLEXCOMM7 */ + + lpc54_flexcomm7_enableclk(); + + /* Set FLEXCOMM7 to the USART peripheral, locking that configuration in place. */ + + putreg32(FLEXCOMM_PSELID_PERSEL_USART | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM7_PSELID); + + /* Configure USART7 pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_USART7_RXD); + lpc54_gpio_config(GPIO_USART7_TXD); +#ifdef CONFIG_USART7_OFLOWCONTROL + lpc54_gpio_config(GPIO_USART7_CTS); +#endif +#ifdef CONFIG_USART7_IFLOWCONTROL + lpc54_gpio_config(GPIO_USART7_RTS); +#endif + + /* Set up the FLEXCOMM7 function clock */ + + putreg32(BOARD_FLEXCOMM7_CLKSEL, LPC54_SYSCON_FCLKSEL7); + +#endif +#ifdef HAVE_USART8 + /* Attach 12 MHz clock to FLEXCOMM8 */ + + lpc54_flexcomm8_enableclk(); + + /* Set FLEXCOMM8 to the USART peripheral, locking that configuration in place. */ + + putreg32(FLEXCOMM_PSELID_PERSEL_USART | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM8_PSELID); + + /* Configure USART8 pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_USART8_RXD); + lpc54_gpio_config(GPIO_USART8_TXD); +#ifdef CONFIG_USART8_OFLOWCONTROL + lpc54_gpio_config(GPIO_USART8_CTS); +#endif +#ifdef CONFIG_USART8_IFLOWCONTROL + lpc54_gpio_config(GPIO_USART8_RTS); +#endif + + /* Set up the FLEXCOMM0 function clock */ + + putreg32(BOARD_FLEXCOMM8_CLKSEL, LPC54_SYSCON_FCLKSEL8); + +#endif +#ifdef HAVE_USART9 + /* Attach 12 MHz clock to FLEXCOMM9 */ + + lpc54_flexcomm9_enableclk(); + + /* Set FLEXCOMM9 to the USART peripheral, locking that configuration in place. */ + + putreg32(FLEXCOMM_PSELID_PERSEL_USART | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM9_PSELID); + + /* Configure USART9 pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_USART9_RXD); + lpc54_gpio_config(GPIO_USART9_TXD); +#ifdef CONFIG_USART9_OFLOWCONTROL + lpc54_gpio_config(GPIO_USART9_CTS); +#endif +#ifdef CONFIG_USART9_IFLOWCONTROL + lpc54_gpio_config(GPIO_USART9_RTS); +#endif + + /* Set up the FLEXCOMM9 function clock */ + + putreg32(BOARD_FLEXCOMM9_CLKSEL, LPC54_SYSCON_FCLKSEL9); + +#endif + +#ifdef HAVE_USART_CONSOLE + /* Configure the console USART (if any) */ + + lpc54_usart_configure(CONSOLE_BASE, &g_console_config); + +#endif /* HAVE_USART_CONSOLE */ +#endif /* HAVE_USART_DEVICE */ +} + +/************************************************************************************ + * Name: lpc54_usart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ************************************************************************************/ + +#ifdef HAVE_USART_DEVICE +void lpc54_usart_configure(uintptr_t base, FAR const struct uart_config_s *config) +{ + uint32_t regval; + + /* Configure baud */ + + lp54_setbaud(base, config); + + /* Configure RX and TX FIFOs */ + /* Empty and enable FIFOs */ + + regval = getreg32(base + LPC54_USART_FIFOCFG_OFFSET); + regval |= (USART_FIFOCFG_ENABLERX | USART_FIFOCFG_EMPTYRX); + regval |= (USART_FIFOCFG_ENABLETX | USART_FIFOCFG_EMPTYTX); + putreg32(regval, base + LPC54_USART_FIFOCFG_OFFSET); + + /* Setup trigger level */ + + regval = getreg32(base + LPC54_USART_FIFOTRIG_OFFSET); + regval &= ~(USART_FIFOTRIG_TXLVL_MASK | USART_FIFOTRIG_RXLVL_MASK); + regval |= USART_FIFOTRIG_RXLVL(config->rxlevel); + regval |= USART_FIFOTRIG_TXLVL(config->txlevel); + putreg32(regval, base + LPC54_USART_FIFOTRIG_OFFSET); + + /* Enable trigger events */ + + regval |= (USART_FIFOTRIG_RXLVLENA | USART_FIFOTRIG_TXLVLENA); + putreg32(regval, base + LPC54_USART_FIFOTRIG_OFFSET); + + /* Setup configuration and enable USART */ + + regval = USART_CFG_ENABLE; + + switch (config->bits) + { + case 7: + regval |= USART_CFG_DATALEN_7BIT; + break; + + default: + case 8: + regval |= USART_CFG_DATALEN_8BIT; + break; + + case 9: + regval |= USART_CFG_DATALEN_9BIT; + break; + } + + switch (config->parity) + { + default: + case 0: + regval |= USART_CFG_PARITYSEL_NONE; + break; + + case 1: + regval |= USART_CFG_PARITYSEL_ODD; + break; + + case 2: + regval |= USART_CFG_PARITYSEL_EVEN; + break; + } + + if (config->stopbits2) + { + regval |= USART_CFG_STOPLEN; + } + + putreg32(regval, base + LPC54_USART_CFG_OFFSET); +} +#endif + +/**************************************************************************** + * Name: lpc54_usart_disable + * + * Description: + * Disable a USART. it will be necessary to again call + * lpc54_usart_configure() in order to use this USART channel again. + * + ****************************************************************************/ + +#ifdef HAVE_USART_DEVICE +void lpc54_usart_disable(uintptr_t base) +{ + /* Disable interrupts */ + + putreg32(USART_FIFOINT_ALL, base + LPC54_USART_FIFOINTENCLR_OFFSET); + + /* Disable the UART */ + + putreg32(0, base + LPC54_USART_CFG_OFFSET); + + /* Disable the FIFOs */ + + putreg32(0, base + LPC54_USART_FIFOCFG_OFFSET); + putreg32(0, base + LPC54_USART_FIFOTRIG_OFFSET); +} +#endif + +/**************************************************************************** + * Name: up_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void up_lowputc(char ch) +{ +#ifdef HAVE_USART_CONSOLE + irqstate_t flags; + + for (; ; ) + { + /* Wait for the transmit FIFO to be not full */ + + while ((getreg32(CONSOLE_BASE + LPC54_USART_FIFOSTAT_OFFSET) & + USART_FIFOSTAT_TXNOTFULL) == 0) + { + } + + /* Disable interrupts so that the fest test and the transmission are + * atomic. + */ + + flags = enter_critical_section(); + if ((getreg32(CONSOLE_BASE + LPC54_USART_FIFOSTAT_OFFSET) & + USART_FIFOSTAT_TXNOTFULL) != 0) + { + /* Send the character */ + + putreg32((uint32_t)ch, CONSOLE_BASE + LPC54_USART_FIFOWR_OFFSET); + leave_critical_section(flags); + return; + } + + leave_critical_section(flags); + } +#endif +} diff --git a/arch/arm/src/lpc54xx/lpc54_lowputc.h b/arch/arm/src/lpc54xx/lpc54_lowputc.h new file mode 100644 index 0000000000000000000000000000000000000000..29820969543de9448aad8e653e2a07b309006458 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_lowputc.h @@ -0,0 +1,115 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/lpc54_lowputc.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_LOWPUTC_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_LOWPUTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifdef HAVE_USART_DEVICE +/* This structure describes the configuration of an UART */ + +struct uart_config_s +{ + uint32_t baud; /* Configured baud */ + uint32_t fclk; /* Input Flexcomm function clock frequency */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (5-9) */ + uint8_t txlevel; /* TX level for event generation */ + uint8_t rxlevel; /* RX level for event generation */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + bool iflow; /* true: Input flow control supported */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + bool oflow; /* true: Output flow control supported. */ +#endif +}; +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc54_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level initialization + * including setup of the console USART. This USART initialization is done + * early so that the serial console is available for debugging very early in + * the boot sequence. + * + ************************************************************************************/ + +void lpc54_lowsetup(void); + +/************************************************************************************ + * Name: lpc54_usart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ************************************************************************************/ + +#ifdef HAVE_USART_DEVICE +void lpc54_usart_configure(uintptr_t base, FAR const struct uart_config_s *config); +#endif + +/**************************************************************************** + * Name: lpc54_usart_disable + * + * Description: + * Disable a USART. it will be necessary to again call + * lpc54_usart_configure() in order to use this USART channel again. + * + ****************************************************************************/ + +#ifdef HAVE_USART_DEVICE +void lpc54_usart_disable(uintptr_t base); +#endif + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_LOWPUTC_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_mpuinit.c b/arch/arm/src/lpc54xx/lpc54_mpuinit.c new file mode 100644 index 0000000000000000000000000000000000000000..ca86292ee9f6d5a8c2067de35f6b1d4de2599897 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_mpuinit.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_mpuinit.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "mpu.h" +#include "lpc54_mpuinit.h" + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef MAX +# define MAX(a,b) a > b ? a : b +#endif + +#ifndef MIN +# define MIN(a,b) a < b ? a : b +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_mpuinitialize + * + * Description: + * Configure the MPU to permit user-space access to only restricted SAM3U + * resources. + * + ****************************************************************************/ + +void lpc54_mpuinitialize(void) +{ + uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); + uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); + + DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart && + dataend >= datastart); + + /* Show MPU information */ + + mpu_showtype(); + + /* Configure user flash and SRAM space */ + + mpu_user_flash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); + + mpu_user_intsram(datastart, dataend - datastart); + + /* Then enable the MPU */ + + mpu_control(true, false, true); +} + +/**************************************************************************** + * Name: lpc54_mpu_uheap + * + * Description: + * Map the user-heap region. + * + * This logic may need an extension to handle external SDRAM). + * + ****************************************************************************/ + +void lpc54_mpu_uheap(uintptr_t start, size_t size) +{ + mpu_user_intsram(start, size); +} + +#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARM_MPU */ + diff --git a/arch/arm/src/lpc54xx/lpc54_mpuinit.h b/arch/arm/src/lpc54xx/lpc54_mpuinit.h new file mode 100644 index 0000000000000000000000000000000000000000..afc44524cc2c42909b6a6e5fa65f9025b627798b --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_mpuinit.h @@ -0,0 +1,78 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/lpc54_mpuinit.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_MPUINIT_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_MPUINIT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/**************************************************************************** + * Name: lpc54_mpuinitialize + * + * Description: + * Configure the MPU to permit user-space access to only unrestricted MCU + * resources. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void lpc54_mpuinitialize(void); +#else +# define lpc54_mpuinitialize() +#endif + +/**************************************************************************** + * Name: lpc54_mpu_uheap + * + * Description: + * Map the user heap region. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void lpc54_mpu_uheap(uintptr_t start, size_t size); +#else +# define lpc54_mpu_uheap(start,size) +#endif + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_MPUINIT_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_power.h b/arch/arm/src/lpc54xx/lpc54_power.h new file mode 100644 index 0000000000000000000000000000000000000000..09bbe51b35bce848e9cb260f0f77b3256cba55f6 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_power.h @@ -0,0 +1,53 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/lpc54_power.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_PERIPHPOWER_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_PERIPHPOWER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* Include the correct logic for the configured chip */ + +#if defined(CONFIG_ARCH_FAMILY_LPC546XX) +# include "lpc546x_power.h" +#else +# error "Unsupported LPC54 architecture" +#endif + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_PERIPHPOWER_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_reset.c b/arch/arm/src/lpc54xx/lpc54_reset.c new file mode 100644 index 0000000000000000000000000000000000000000..621a39e60e4e73cb610d5a19ef18f8b55981e1cc --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_reset.c @@ -0,0 +1,79 @@ +/**************************************************************************** + * arch/arm/src/lpc54/lpc54_reset.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "up_arch.h" +#include "lpc54_reset.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_reset + * + * Description: + * Reset the selected peripheral + * + ****************************************************************************/ + +void lpc54_reset(uintptr_t setreg, uintptr_t clrreg, + uintptr_t statreg, uint32_t mask) +{ + /* Set the bit to put the peripheral in reset */ + + putreg32(mask, setreg); + + /* Wait until the peripheral is in reset */ + + while ((getreg32(statreg) & mask) == 0) + { + } + + /* Clear the bit to take the peripheral out of reset */ + + putreg32(mask, clrreg); + + /* Wait until the peripheral is out of reset */ + + while ((getreg32(statreg) & mask) != 0) + { + } +} diff --git a/arch/arm/src/lpc54xx/lpc54_reset.h b/arch/arm/src/lpc54xx/lpc54_reset.h new file mode 100644 index 0000000000000000000000000000000000000000..b00434a6a3579da0bb71b69d3ada09a23e1470df --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_reset.h @@ -0,0 +1,68 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_reset.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_RESET_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_RESET_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the correct definitions for the configured chip */ + +#if defined(CONFIG_ARCH_FAMILY_LPC546XX) +# include "lpc546x_reset.h" +#else +# error "Unsupported LPC54 architecture" +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_reset + * + * Description: + * Reset the selected peripheral + * + ****************************************************************************/ + +void lpc54_reset(uintptr_t setreg, uintptr_t clrreg, + uintptr_t statreg, uint32_t mask); + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_RESET_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_rng.c b/arch/arm/src/lpc54xx/lpc54_rng.c new file mode 100644 index 0000000000000000000000000000000000000000..dfe9bace8e60eb6b356e295b21b2eba4b7696817 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_rng.c @@ -0,0 +1,193 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_rng.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include "chip/lpc54_rom.h" + +#if defined(CONFIG_LPC54_RNG) +#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static ssize_t lpc54_read(struct file *filep, char *buffer, size_t); + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct rng_dev_s +{ + sem_t rd_devsem; /* Threads can only exclusively access the RNG */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct rng_dev_s g_rngdev; + +static const struct file_operations g_rngops = +{ + NULL, /* open */ + NULL, /* close */ + lpc54_read, /* read */ + NULL, /* write */ + NULL, /* seek */ + NULL /* ioctl */ +#ifndef CONFIG_DISABLE_POLL + , NULL /* poll */ +#endif +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + , NULL /* unlink */ +#endif +}; + +/**************************************************************************** + * Private functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_read + ****************************************************************************/ + +static ssize_t lpc54_read(struct file *filep, char *buffer, size_t buflen) +{ + union + { + uint32_t w; + uint8_t b[4]; + } value; + + ssize_t remaining; + int ret; + int i; + + /* Get exclusive access to ROM random number generator API */ + + ret = nxsem_wait(&g_rngdev.rd_devsem); + if (ret < 0) + { + return ret; + } + + /* Copy the requested number of randome bytes. */ + + for (remaining = buflen; remaining > 0;) + { + /* Read the next 32-bit random value */ + + value.w = LPC54_RNG_READ(); + + /* Return byte at a time to avoid alignment complexities (but + * sacrificing some performance). + */ + + for (i = 0; i < sizeof(uint32_t) && remaining > 0; i++, remaining--) + { + *buffer++ = value.b[i]; + } + } + + nxsem_post(&g_rngdev.rd_devsem); + return buflen; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: devrandom_register + * + * Description: + * Initialize the RNG hardware and register the /dev/random driver. + * Must be called BEFORE devurandom_register. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_DEV_RANDOM +void devrandom_register(void) +{ + nxsem_init(&g_rngdev.rd_devsem, 0, 1); + (void)register_driver("/dev/random", &g_rngops, 0444, NULL); +} +#endif + +/**************************************************************************** + * Name: devurandom_register + * + * Description: + * Register /dev/urandom + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_DEV_URANDOM_ARCH +void devurandom_register(void) +{ +#ifndef CONFIG_DEV_RANDOM + nxsem_init(&g_rngdev.rd_devsem, 0, 1); +#endif + (void)register_driver("/dev/urandom", &g_rngops, 0444, NULL); +} +#endif + +#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ +#endif /* CONFIG_LPC54_RNG */ diff --git a/arch/arm/src/lpc54xx/lpc54_rtc.c b/arch/arm/src/lpc54xx/lpc54_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..ba23c2ad84f12d0c954e8ae86f283617a845e20b --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_rtc.c @@ -0,0 +1,375 @@ +/**************************************************************************** + * arch/arm/src/lpc54/lpc54_rtc.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "up_arch.h" + +#include "chip/lpc54_rtc.h" +#include "lpc54_enableclk.h" +#include "lpc54_rtc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifdef CONFIG_RTC_HIRES +# error "CONFIG_RTC_HIRES is not supported" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +/* Callback to use when the alarm expires */ + +static alarmcb_t g_alarmcb; +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Variable determines if the RTC has been initialized and enabled. */ + +volatile bool g_rtc_enabled = false; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_rtc_interrupt + * + * Description: + * RTC interrupt service routine + * + * Input Parameters: + * irq - The IRQ number that generated the interrupt + * context - Architecture specific register save information. + * + * Returned Value: + * Zero (OK) on success; A negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int lpc54_rtc_interrupt(int irq, void *context, FAR void *arg) +{ + uint32_t status = getreg16(LPC54_RTC_CTRL); + + if ((status & RTC_CTRL_ALARM1HZ) != 0 && g_alarmcb != NULL) + { + /* Clear pending status */ + + putreg32(status | RTC_CTRL_ALARM1HZ | RTC_CTRL_WAKE1KHZ, LPC54_RTC_CTRL); + + /* Perform the alarm callback */ + + g_alarmcb(); + g_alarmcb = NULL; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_rtc_initialize + * + * Description: + * Initialize the hardware RTC per the selected configuration. This function is + * called once during the OS initialization sequence + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_initialize(void) +{ + /* Enable the clock to the RTC register interface and peripheral clock. */ + + lpc54_rtc_enableclk(); + + /* If the 32 kHz output of the RTC is used by another part of the system, enable it + * via the EN bit in the RTCOSCCTRL register + */ + + putreg32(SYSCON_RTCOSCCTRL_EN, LPC54_SYSCON_RTCOSCCTRL); + + /* The RTC is already running or, perhaps waiting to be enabled if it was never + * configured. We will set enable the RTC only if the time if initialized by + * higher level logic. + */ + + g_rtc_enabled = true; + return OK; +} + +/**************************************************************************** + * Name: up_rtc_time + * + * Description: + * Get the current time in seconds. This is similar to the standard time() + * function. This interface is only required if the low-resolution RTC/counter + * hardware implementation selected. It is only used by the RTOS during + * initialization to set up the system time when CONFIG_RTC is set. + * + * Input Parameters: + * None + * + * Returned Value: + * The current time in seconds + * + ****************************************************************************/ + +time_t up_rtc_time(void) +{ + /* Read and return the 32-bit 1Hz RTC counter value */ + + return getreg32(LPC54_RTC_COUNT); +} + +/**************************************************************************** + * Name: up_rtc_settime + * + * Description: + * Set the RTC to the provided time. All RTC implementations must be + * able to set their time based on a standard timespec. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_settime(FAR const struct timespec *tp) +{ + irqstate_t flags; + uint32_t regval; + + /* Read the Break out the time values */ + + flags = enter_critical_section(); + + /* Make sure the the RTC is out of reset, but not enabled. */ + + regval = getreg32(LPC54_RTC_CTRL); + regval &= ~(RTC_CTRL_SWRESET | RTC_CTRL_RTCEN | RTC_CTRL_RTC1KHZEN | + RTC_CTRL_OSCPD); + putreg32(regval, LPC54_RTC_CTRL); + + /* Then write the time in seconds to the counter register. NOTE that we + * can only write to this register when the RTC_EN bit in the RTC CTRL + * Register is 0. + */ + + putreg32(tp->tv_sec, LPC54_RTC_COUNT); + + /* (Re-)enabled the RTC. The counter increments one second after the + * RTC_EN bit is set. + */ + + regval |= RTC_CTRL_RTCEN; + putreg32(regval, LPC54_RTC_CTRL); + + /* Make sure that magic value is in the general purpose register */ + + putreg32(RTC_MAGIC, RTC_MAGIC_REG); + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: lpc54_rtc_setalarm + * + * Description: + * Set up an alarm. + * + * Input Parameters: + * tp - The time to set the alarm + * callback - The function to call when the alarm expires. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int lpc54_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback) +{ + irqstate_t flags; + uint32_t regval; + int ret = -EBUSY; + + /* Is there already something waiting on the ALARM? */ + + flags = enter_critical_section(); + if (g_alarmcb == NULL) + { + /* No.. Save the callback function pointer */ + + g_alarmcb = callback; + + /* Make sure the the RTC is out of reset. */ + + regval = getreg32(LPC54_RTC_CTRL); + regval &= ~(RTC_CTRL_SWRESET | RTC_CTRL_ALARMDPDEN | RTC_CTRL_RTC1KHZEN | + RTC_CTRL_WAKEDPDEN | RTC_CTRL_OSCPD); + putreg32(regval, LPC54_RTC_CTRL); + + /* Make sure that the ALARM interrupt is attached and enabled. */ + + irq_attach(LPC54_IRQ_RTC, lpc54_rtc_interrupt, NULL); + up_enable_irq(LPC54_IRQ_RTC); + + /* Set the alarm match register */ + + putreg32(tp->tv_sec, LPC54_RTC_MATCH); + + /* Enable RTC alarm */ + + regval |= RTC_CTRL_ALARMDPDEN; + putreg32(regval, LPC54_RTC_CTRL); + ret = OK; + } + + leave_critical_section(flags); + return ret; +} +#endif + +/**************************************************************************** + * Name: lpc54_rtc_rdalarm + * + * Description: + * Query an alarm configured in hardware. + * + * Input Parameters: + * time - Current alarm setting. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int lpc54_rtc_rdalarm(FAR struct tm *time) +{ + uint32_t match; + + match = getreg32(LPC54_RTC_MATCH); + (void)gmtime_r((time_t *)&match, time); + return OK; +} +#endif + +/**************************************************************************** + * Name: lpc54_rtc_cancelalarm + * + * Description: + * Cancel a pending alarm alarm + * + * Input Parameters: + * none + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int lpc54_rtc_cancelalarm(void) +{ + irqstate_t flags; + uint32_t regval; + int ret = -ENODATA; + + flags = enter_critical_section(); + if (g_alarmcb != NULL) + { + /* Cancel the global callback function */ + + g_alarmcb = NULL; + + /* Disable the Alarm interrupt */ + + up_disable_irq(LPC54_IRQ_RTC); + + /* Unset the alarm */ + + regval = getreg32(LPC54_RTC_CTRL); + regval &= ~(RTC_CTRL_SWRESET | RTC_CTRL_ALARMDPDEN | RTC_CTRL_RTC1KHZEN | + RTC_CTRL_WAKEDPDEN | RTC_CTRL_OSCPD); + putreg32(regval, LPC54_RTC_CTRL); + + ret = OK; + } + + leave_critical_section(flags); + return ret; +} +#endif diff --git a/arch/arm/src/lpc54xx/lpc54_rtc.h b/arch/arm/src/lpc54xx/lpc54_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..cad7452b2be530285cc37310e49bc02a27d3155b --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_rtc.h @@ -0,0 +1,172 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_rtc.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_RTC_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_RTC_H + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RTC_MAGIC (0xfacefeed) +#define RTC_MAGIC_REG LPC54_RTC_GPREG(0) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_RTC_ALARM +/* The form of an alarm callback */ + +typedef CODE void (*alarmcb_t)(void); +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_rtc_setalarm + * + * Description: + * Set up an alarm. + * + * Input Parameters: + * tp - the time to set the alarm + * callback - the function to call when the alarm expires. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +struct timespec; +int lpc54_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback); +#endif + +/**************************************************************************** + * Name: lpc54_rtc_rdalarm + * + * Description: + * Query an alarm configured in hardware. + * + * Input Parameters: + * time - Current alarm setting. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +struct tm; +int lpc54_rtc_rdalarm(FAR struct tm *time); +#endif + +/**************************************************************************** + * Name: lpc54_rtc_cancelalarm + * + * Description: + * Cancel a pending alarm alarm + * + * Input Parameters: + * none + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int lpc54_rtc_cancelalarm(void); +#endif + +/**************************************************************************** + * Name: lpc54_rtc_lowerhalf + * + * Description: + * Instantiate the RTC lower half driver for the LPC54. General usage: + * + * #include + * #include "lpc54_rtc.h" + * + * struct rtc_lowerhalf_s *lower; + * lower = lpc54_rtc_lowerhalf(); + * rtc_initialize(0, lower); + * + * Input Parameters: + * None + * + * Returned Value: + * On success, a non-NULL RTC lower interface is returned. NULL is + * returned on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_DRIVER +struct rtc_lowerhalf_s; +FAR struct rtc_lowerhalf_s *lpc54_rtc_lowerhalf(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_RTC_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c b/arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c new file mode 100644 index 0000000000000000000000000000000000000000..6413c6d3f74d3eb67c2092b5847a214a0c8ac3bd --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c @@ -0,0 +1,660 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "up_arch.h" + +#include "chip/lpc54_rtc.h" +#include "lpc54_rtc.h" + +#ifdef CONFIG_RTC_DRIVER + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +struct lpc54_cbinfo_s +{ + volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ + volatile FAR void *priv; /* Private argument to accompany callback */ +}; +#endif + +/* This is the private type for the RTC state. It must be cast compatible + * with struct rtc_lowerhalf_s. + */ + +struct lpc54_lowerhalf_s +{ + /* This is the contained reference to the read-only, lower-half + * operations vtable (which may lie in FLASH or ROM) + */ + + FAR const struct rtc_ops_s *ops; + + /* Data following is private to this driver and not visible outside of + * this file. + */ + + sem_t devsem; /* Threads can only exclusively access the RTC */ + +#ifdef CONFIG_RTC_ALARM + /* Alarm callback information */ + + struct lpc54_cbinfo_s cbinfo; +#endif + +#ifdef CONFIG_RTC_PERIODIC + /* Periodic wakeup information */ + + struct lower_setperiodic_s periodic; +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Prototypes for static methods in struct rtc_ops_s */ + +static int lpc54_rdtime(FAR struct rtc_lowerhalf_s *lower, + FAR struct rtc_time *rtctime); +static int lpc54_settime(FAR struct rtc_lowerhalf_s *lower, + FAR const struct rtc_time *rtctime); +static bool lpc54_havesettime(FAR struct rtc_lowerhalf_s *lower); + +#ifdef CONFIG_RTC_ALARM +static int lpc54_setalarm(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setalarm_s *alarminfo); +static int lpc54_setrelative(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setrelative_s *alarminfo); +static int lpc54_cancelalarm(FAR struct rtc_lowerhalf_s *lower, + int alarmid); +static int lpc54_rdalarm(FAR struct rtc_lowerhalf_s *lower, + FAR struct lower_rdalarm_s *alarminfo); +#endif + +#ifdef CONFIG_RTC_PERIODIC +static int lpc54_setperiodic(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setperiodic_s *alarminfo); +static int lpc54_cancelperiodic(FAR struct rtc_lowerhalf_s *lower, int id); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ +/* LPC54 RTC driver operations */ + +static const struct rtc_ops_s g_rtc_ops = +{ + .rdtime = lpc54_rdtime, + .settime = lpc54_settime, + .havesettime = lpc54_havesettime, +#ifdef CONFIG_RTC_ALARM + .setalarm = lpc54_setalarm, + .setrelative = lpc54_setrelative, + .cancelalarm = lpc54_cancelalarm, + .rdalarm = lpc54_rdalarm, +#endif +#ifdef CONFIG_RTC_PERIODIC + .setperiodic = lpc54_setperiodic, + .cancelperiodic = lpc54_cancelperiodic, +#endif +#ifdef CONFIG_RTC_IOCTL + .ioctl = NULL, +#endif +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + .destroy = NULL, +#endif +}; + +/* LPC54 RTC device state */ + +static struct lpc54_lowerhalf_s g_rtc_lowerhalf = +{ + .ops = &g_rtc_ops, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_alarm_callback + * + * Description: + * This is the function that is called from the RTC driver when the alarm + * goes off. It just invokes the upper half drivers callback. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static void lpc54_alarm_callback(void) +{ + FAR struct lpc54_cbinfo_s *cbinfo = &g_rtc_lowerhalf.cbinfo; + + /* Sample and clear the callback information to minimize the window in + * time in which race conditions can occur. + */ + + rtc_alarm_callback_t cb = (rtc_alarm_callback_t)cbinfo->cb; + FAR void *arg = (FAR void *)cbinfo->priv; + + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + /* Perform the callback */ + + if (cb != NULL) + { + cb(arg, 0); + } +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: lpc54_rdtime + * + * Description: + * Implements the rdtime() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * rcttime - The location in which to return the current RTC time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +static int lpc54_rdtime(FAR struct rtc_lowerhalf_s *lower, + FAR struct rtc_time *rtctime) +{ + time_t timer; + + /* The resolution of time is only 1 second */ + + timer = up_rtc_time(); + + /* Convert the one second epoch time to a struct tm */ + + if (!gmtime_r(&timer, (FAR struct tm *)rtctime)) + { + int errcode = get_errno(); + DEBUGASSERT(errcode > 0); + return -errcode; + } + + return OK; +} + +/**************************************************************************** + * Name: lpc54_settime + * + * Description: + * Implements the settime() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * rcttime - The new time to set + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +static int lpc54_settime(FAR struct rtc_lowerhalf_s *lower, + FAR const struct rtc_time *rtctime) +{ + struct timespec ts; + + /* Convert the struct rtc_time to a time_t. Here we assume that struct + * rtc_time is cast compatible with struct tm. + */ + + ts.tv_sec = mktime((FAR struct tm *)rtctime); + ts.tv_nsec = 0; + + /* Now set the time (to one second accuracy) */ + + return up_rtc_settime(&ts); +} + +/**************************************************************************** + * Name: lpc54_havesettime + * + * Description: + * Implements the havesettime() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * + * Returned Value: + * Returns true if RTC date-time have been previously set. + * + ****************************************************************************/ + +static bool lpc54_havesettime(FAR struct rtc_lowerhalf_s *lower) +{ + return getreg32(RTC_MAGIC_REG) == RTC_MAGIC; +} + +/**************************************************************************** + * Name: lpc54_setalarm + * + * Description: + * Set a new alarm. This function implements the setalarm() method of the + * RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int lpc54_setalarm(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setalarm_s *alarminfo) +{ + FAR struct lpc54_lowerhalf_s *priv; + FAR struct lpc54_cbinfo_s *cbinfo; + int ret; + + DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->id == 0); + priv = (FAR struct lpc54_lowerhalf_s *)lower; + + ret = nxsem_wait(&priv->devsem); + if (ret < 0) + { + return ret; + } + + ret = -EINVAL; + if (alarminfo->id == 0) + { + struct timespec ts; + + /* Convert the RTC time to a timespec (1 second accuracy) */ + + ts.tv_sec = mktime((FAR struct tm *)&alarminfo->time); + ts.tv_nsec = 0; + + /* Remember the callback information */ + + cbinfo = &priv->cbinfo; + cbinfo->cb = alarminfo->cb; + cbinfo->priv = alarminfo->priv; + + /* And set the alarm */ + + ret = lpc54_rtc_setalarm(&ts, lpc54_alarm_callback); + if (ret < 0) + { + cbinfo->cb = NULL; + cbinfo->priv = NULL; + } + } + + nxsem_post(&priv->devsem); + return ret; +} +#endif + +/**************************************************************************** + * Name: lpc54_setrelative + * + * Description: + * Set a new alarm relative to the current time. This function implements + * the setrelative() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int lpc54_setrelative(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setrelative_s *alarminfo) +{ + FAR struct lpc54_lowerhalf_s *priv; + FAR struct lpc54_cbinfo_s *cbinfo; + FAR struct timespec ts; + int ret = -EINVAL; + + DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->id == 0); + priv = (FAR struct lpc54_lowerhalf_s *)lower; + + if (alarminfo->id == 0 && alarminfo->reltime > 0) + { + /* Disable pre-emption while we do this so that we don't have to worry + * about being suspended and working on an old time. + */ + + sched_lock(); + + /* Get the current time in seconds */ + + ts.tv_sec = up_rtc_time(); + ts.tv_nsec = 0; + + /* Add the seconds offset. Add one to the number of seconds because + * we are unsure of the phase of the timer. + */ + + ts.tv_sec += (alarminfo->reltime + 1); + + /* Remember the callback information */ + + cbinfo = &priv->cbinfo; + cbinfo->cb = alarminfo->cb; + cbinfo->priv = alarminfo->priv; + + /* And set the alarm */ + + ret = lpc54_rtc_setalarm(&ts, lpc54_alarm_callback); + if (ret < 0) + { + cbinfo->cb = NULL; + cbinfo->priv = NULL; + } + + sched_unlock(); + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: lpc54_cancelalarm + * + * Description: + * Cancel the current alarm. This function implements the cancelalarm() + * method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int lpc54_cancelalarm(FAR struct rtc_lowerhalf_s *lower, int alarmid) +{ + FAR struct lpc54_lowerhalf_s *priv; + FAR struct lpc54_cbinfo_s *cbinfo; + + DEBUGASSERT(lower != NULL); + DEBUGASSERT(alarmid == 0); + priv = (FAR struct lpc54_lowerhalf_s *)lower; + + /* Nullify callback information to reduce window for race conditions */ + + cbinfo = &priv->cbinfo; + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + /* Then cancel the alarm */ + + return lpc54_rtc_cancelalarm(); +} +#endif + +/**************************************************************************** + * Name: lpc54_rdalarm + * + * Description: + * Query the RTC alarm. + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to query the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int lpc54_rdalarm(FAR struct rtc_lowerhalf_s *lower, + FAR struct lower_rdalarm_s *alarminfo) +{ + int ret = -EINVAL; + + DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->id == 0 && + alarminfo->time != NULL); + + if (alarminfo->id == 0) + { + ret = lpc54_rtc_rdalarm((FAR struct tm *)alarminfo->time); + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: lpc54_periodic_callback + * + * Description: + * This is the function that is called from the RTC driver when the periodic + * wakeup goes off. It just invokes the upper half drivers callback. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_PERIODIC +static int lpc54_periodic_callback(void) +{ + FAR struct lpc54_lowerhalf_s *lower; + struct lower_setperiodic_s *cbinfo; + rtc_wakeup_callback_t cb; + FAR void *priv; + + lower = (FAR struct lpc54_lowerhalf_s *)&g_rtc_lowerhalf; + + cbinfo = &lower->periodic; + cb = (rtc_wakeup_callback_t)cbinfo->cb; + priv = (FAR void *)cbinfo->priv; + + /* Perform the callback */ + + if (cb != NULL) + { + cb(priv, 0); + } + + return OK; +} +#endif /* CONFIG_RTC_PERIODIC */ + +/**************************************************************************** + * Name: lpc54_setperiodic + * + * Description: + * Set a new periodic wakeup relative to the current time, with a given + * period. This function implements the setperiodic() method of the RTC + * driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the wakeup activity + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_PERIODIC +static int lpc54_setperiodic(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setperiodic_s *alarminfo) +{ + FAR struct lpc54_lowerhalf_s *priv; + int ret; + + ASSERT(lower != NULL && alarminfo != NULL); + priv = (FAR struct lpc54_lowerhalf_s *)lower; + + ret = nxsem_wait(&priv->devsem); + if (ret < 0) + { + return ret; + } + + memcpy(&priv->periodic, alarminfo, sizeof(struct lower_setperiodic_s)); + + ret = lpc54_rtc_setperiodic(&alarminfo->period, lpc54_periodic_callback); + + nxsem_post(&priv->devsem); + return ret; +} +#endif + +/**************************************************************************** + * Name: lpc54_cancelperiodic + * + * Description: + * Cancel the current periodic wakeup activity. This function implements + * the cancelperiodic() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_PERIODIC +static int lpc54_cancelperiodic(FAR struct rtc_lowerhalf_s *lower, int id) +{ + FAR struct lpc54_lowerhalf_s *priv; + int ret; + + DEBUGASSERT(lower != NULL); + priv = (FAR struct lpc54_lowerhalf_s *)lower; + + DEBUGASSERT(id == 0); + + ret = nxsem_wait(&priv->devsem); + if (ret < 0) + { + return ret; + } + + ret = lpc54_rtc_cancelperiodic(); + + nxsem_post(&priv->devsem); + return ret; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_rtc_lowerhalf + * + * Description: + * Instantiate the RTC lower half driver for the LPC54. General usage: + * + * #include + * #include "lpc54_rtc.h> + * + * struct rtc_lowerhalf_s *lower; + * lower = lpc54_rtc_lowerhalf(); + * rtc_initialize(0, lower); + * + * Input Parameters: + * None + * + * Returned Value: + * On success, a non-NULL RTC lower interface is returned. NULL is + * returned on any failure. + * + ****************************************************************************/ + +FAR struct rtc_lowerhalf_s *lpc54_rtc_lowerhalf(void) +{ + nxsem_init(&g_rtc_lowerhalf.devsem, 0, 1); + + return (FAR struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; +} + +#endif /* CONFIG_RTC_DRIVER */ diff --git a/arch/arm/src/lpc54xx/lpc54_sdmmc.c b/arch/arm/src/lpc54xx/lpc54_sdmmc.c new file mode 100644 index 0000000000000000000000000000000000000000..09cb42526777204524ddbdbcdf8da77cc000f531 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_sdmmc.c @@ -0,0 +1,2791 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_sdmmc.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * This code is based on arch/arm/src/lpc43xx/lpc43_sdmmc.c: + * + * Copyright (C) 2017 Alan Carvalho de Assis. All rights reserved. + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Alan Carvalho de Assis + * + * which was itself based on arch/arm/src/lpc17xx/lpc17_sdcard.c: + * + * Copyright (C) 2013-2014, 2016-2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "chip/lpc54_pinmux.h" +#include "chip/lpc54_syscon.h" +#include "lpc54_enableclk.h" +#include "lpc54_gpio.h" +#include "lpc54_sdmmc.h" + +#include + +#ifdef CONFIG_LPC54_SDMMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MCI_DMADES0_OWN (1UL << 31) +#define MCI_DMADES0_CH (1 << 4) +#define MCI_DMADES0_FS (1 << 3) +#define MCI_DMADES0_LD (1 << 2) +#define MCI_DMADES0_DIC (1 << 1) +#define MCI_DMADES1_MAXTR 4096 +#define MCI_DMADES1_BS1(x) (x) + +/* Configuration ************************************************************/ +/* Required system configuration options in the sched/Kconfig: + * + * CONFIG_SCHED_WORKQUEUE -- Callback support requires work queue support. + * + * Driver-specific configuration options in the drivers/mmcd Kdonfig: + * + * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking + * APIs to manage concurrent accesses on the SD card bus. This is not + * needed for the simple case of a single SD card slot, for example. + * CONFIG_SDIO_WIDTH_D1_ONLY - This may be selected to force the driver + * operate with only a single data line (the default is to use all + * 4 SD data lines). + * CONFIG_MMCSD_HAVE_CARDDETECT - Select if the SD slot supports a card + * detect pin. + * CONFIG_MMCSD_HAVE_WRITEPROTECT - Select if the SD slots supports a + * write protected pin. + * + * Driver-specific configuration options in the arch/arm/src/lpc54xx/Kconfig + * + * CONFIG_LPC54_SDMMC_PWRCTRL - Select if the board supports an output + * pin to enable power to the SD slot. + * CONFIG_LPC54_SDMMC_DMA - Enable SD card DMA. This is a marginally + * optional. For most usages, SD accesses will cause data overruns if + * used without DMA. This will also select CONFIG_SDIO_DMA. + * CONFIG_LPC54_SDMMC_REGDEBUG - Enables some very low-level debug output + * This also requires CONFIG_DEBUG_MEMCARD_INFO + */ + +#ifndef CONFIG_SCHED_WORKQUEUE +# error "Callback support requires CONFIG_SCHED_WORKQUEUE" +#endif + +/* Timing */ + +#define SDCARD_CMDTIMEOUT (10000) +#define SDCARD_LONGTIMEOUT (0x7fffffff) + +/* Type of Card Bus Size */ + +#define SDCARD_BUS_D1 0 +#define SDCARD_BUS_D4 1 +#define SDCARD_BUS_D8 0x100 + +/* FIFO size in bytes */ + +#define LPC54_TXFIFO_SIZE (LPC54_TXFIFO_DEPTH | LPC54_TXFIFO_WIDTH) +#define LPC54_RXFIFO_SIZE (LPC54_RXFIFO_DEPTH | LPC54_RXFIFO_WIDTH) + +/* Data transfer interrupt mask bits */ + +#define SDCARD_RECV_MASK (SDMMC_INT_DTO | SDMMC_INT_DCRC | SDMMC_INT_DRTO | \ + SDMMC_INT_EBE | SDMMC_INT_RXDR | SDMMC_INT_SBE) +#define SDCARD_SEND_MASK (SDMMC_INT_DTO | SDMMC_INT_DCRC | SDMMC_INT_DRTO | \ + SDMMC_INT_EBE | SDMMC_INT_TXDR | SDMMC_INT_SBE) + +#define SDCARD_DMARECV_MASK (SDMMC_INT_DTO | SDMMC_INT_DCRC | SDMMC_INT_DRTO | \ + SDMMC_INT_SBE | SDMMC_INT_EBE) +#define SDCARD_DMASEND_MASK (SDMMC_INT_DTO | SDMMC_INT_DCRC | SDMMC_INT_DRTO | \ + SDMMC_INT_EBE) + +#define SDCARD_DMAERROR_MASK (SDMMC_IDINTEN_FBE | SDMMC_IDINTEN_DU | \ + SDMMC_IDINTEN_AIS) + +#define SDCARD_TRANSFER_ALL (SDMMC_INT_DTO | SDMMC_INT_DCRC | SDMMC_INT_DRTO | \ + SDMMC_INT_EBE | SDMMC_INT_TXDR | SDMMC_INT_RXDR | \ + SDMMC_INT_SBE) + +/* Event waiting interrupt mask bits */ + +#define SDCARD_INT_RESPERR (SDMMC_INT_RE | SDMMC_INT_RCRC | SDMMC_INT_RTO) + +#ifdef CONFIG_MMCSD_HAVE_CARDDETECT +# define SDCARD_INT_CDET SDMMC_INT_CDET +#else +# define SDCARD_INT_CDET 0 +#endif + +#define SDCARD_CMDDONE_STA (SDMMC_INT_CDONE) +#define SDCARD_RESPDONE_STA (0) + +#define SDCARD_CMDDONE_MASK (SDMMC_INT_CDONE) +#define SDCARD_RESPDONE_MASK (SDMMC_INT_CDONE | SDCARD_INT_RESPERR) +#define SDCARD_XFRDONE_MASK (0) /* Handled by transfer masks */ + +#define SDCARD_CMDDONE_CLEAR (SDMMC_INT_CDONE) +#define SDCARD_RESPDONE_CLEAR (SDMMC_INT_CDONE | SDCARD_INT_RESPERR) + +#define SDCARD_XFRDONE_CLEAR (SDCARD_TRANSFER_ALL) + +#define SDCARD_WAITALL_CLEAR (SDCARD_CMDDONE_CLEAR | SDCARD_RESPDONE_CLEAR | \ + SDCARD_XFRDONE_CLEAR) + +/* Let's wait until we have both SD card transfer complete and DMA complete. */ + +#define SDCARD_XFRDONE_FLAG (1) +#define SDCARD_DMADONE_FLAG (2) +#define SDCARD_ALLDONE (3) + +/* Card debounce time. Number of host clocks (SD_CLK) used by debounce + * filter logic for card detect. typical debounce time is 5-25 ms. + * + * Eg. Fsd = 44MHz, ticks = 660,000 + */ + +#define DEBOUNCE_TICKS (15 * BOARD_SDMMC_FREQUENCY / 1000) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct sdmmc_dma_s +{ + volatile uint32_t des0; /* Control and status */ + volatile uint32_t des1; /* Buffer size(s) */ + volatile uint32_t des2; /* Buffer address pointer 1 */ + volatile uint32_t des3; /* Buffer address pointer 2 */ +}; + +/* This structure defines the state of the LPC54XX SD card interface */ + +struct lpc54_dev_s +{ + struct sdio_dev_s dev; /* Standard, base SD card interface */ + + /* LPC54XX-specific extensions */ + /* Event support */ + + sem_t waitsem; /* Implements event waiting */ + sdio_eventset_t waitevents; /* Set of events to be waited for */ + uint32_t waitmask; /* Interrupt enables for event waiting */ + volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */ + WDOG_ID waitwdog; /* Watchdog that handles event timeouts */ + + /* Callback support */ + + sdio_statset_t cdstatus; /* Card status */ + sdio_eventset_t cbevents; /* Set of events to be cause callbacks */ + worker_t callback; /* Registered callback function */ + void *cbarg; /* Registered callback argument */ + struct work_s cbwork; /* Callback work queue structure */ + + /* Interrupt mode data transfer support */ + + uint32_t *buffer; /* Address of current R/W buffer */ + uint32_t xfrmask; /* Interrupt enables for data transfer */ +#ifdef CONFIG_LPC54_SDMMC_DMA + uint32_t dmamask; /* Interrupt enables for DMA transfer */ +#endif + ssize_t remaining; /* Number of bytes remaining in the transfer */ + bool wrdir; /* True: Writing False: Reading */ + + /* DMA data transfer support */ + + bool widebus; /* Required for DMA support */ +#ifdef CONFIG_LPC54_SDMMC_DMA + bool dmamode; /* true: DMA mode transfer */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_LPC54_SDMMC_REGDEBUG +static uint32_t lpc54_getreg(uint32_t addr); +static void lpc54_putreg(uint32_t val, uint32_t addr); +#else +# define lpc54_getreg(addr) getreg32(addr) +# define lpc54_putreg(val,addr) putreg32(val,addr) +#endif + +/* Low-level helpers ********************************************************/ + +static void lpc54_takesem(struct lpc54_dev_s *priv); +#define lpc54_givesem(priv) (sem_post(&priv->waitsem)) +static inline void lpc54_setclock(uint32_t clkdiv); +static inline void lpc54_sdcard_clock(bool enable); +static int lpc54_ciu_sendcmd(uint32_t cmd, uint32_t arg); +static void lpc54_enable_ints(struct lpc54_dev_s *priv); +static void lpc54_disable_allints(struct lpc54_dev_s *priv); +static void lpc54_config_waitints(struct lpc54_dev_s *priv, uint32_t waitmask, + sdio_eventset_t waitevents, sdio_eventset_t wkupevents); +static void lpc54_config_xfrints(struct lpc54_dev_s *priv, uint32_t xfrmask); +#ifdef CONFIG_LPC54_SDMMC_DMA +static void lpc54_config_dmaints(struct lpc54_dev_s *priv, uint32_t xfrmask, + uint32_t dmamask); +#endif + +/* Data Transfer Helpers ****************************************************/ + +static void lpc54_eventtimeout(int argc, uint32_t arg); +static void lpc54_endwait(struct lpc54_dev_s *priv, sdio_eventset_t wkupevent); +static void lpc54_endtransfer(struct lpc54_dev_s *priv, sdio_eventset_t wkupevent); + +/* Interrupt Handling *******************************************************/ + +static int lpc54_sdmmc_interrupt(int irq, void *context, FAR void *arg); + +/* SD Card Interface Methods ************************************************/ + +/* Mutual exclusion */ + +#ifdef CONFIG_SDIO_MUXBUS +static int lpc54_lock(FAR struct sdio_dev_s *dev, bool lock); +#endif + +/* Initialization/setup */ + +static void lpc54_reset(FAR struct sdio_dev_s *dev); +static sdio_capset_t lpc54_capabilities(FAR struct sdio_dev_s *dev); +static uint8_t lpc54_status(FAR struct sdio_dev_s *dev); +static void lpc54_widebus(FAR struct sdio_dev_s *dev, bool enable); +static void lpc54_clock(FAR struct sdio_dev_s *dev, + enum sdio_clock_e rate); +static int lpc54_attach(FAR struct sdio_dev_s *dev); + +/* Command/Status/Data Transfer */ + +static int lpc54_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t arg); +static int lpc54_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, + size_t nbytes); +static int lpc54_sendsetup(FAR struct sdio_dev_s *dev, + FAR const uint8_t *buffer, uint32_t nbytes); +static int lpc54_cancel(FAR struct sdio_dev_s *dev); + +static int lpc54_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd); +static int lpc54_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort); +static int lpc54_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t rlong[4]); +static int lpc54_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort); +static int lpc54_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rnotimpl); + +/* EVENT handler */ + +static void lpc54_waitenable(FAR struct sdio_dev_s *dev, + sdio_eventset_t eventset); +static sdio_eventset_t + lpc54_eventwait(FAR struct sdio_dev_s *dev, uint32_t timeout); +static void lpc54_callbackenable(FAR struct sdio_dev_s *dev, + sdio_eventset_t eventset); +static void lpc54_callback(struct lpc54_dev_s *priv); +static int lpc54_registercallback(FAR struct sdio_dev_s *dev, + worker_t callback, void *arg); + +#ifdef CONFIG_LPC54_SDMMC_DMA +/* DMA */ + +static int lpc54_dmarecvsetup(FAR struct sdio_dev_s *dev, + FAR uint8_t *buffer, size_t buflen); +static int lpc54_dmasendsetup(FAR struct sdio_dev_s *dev, + FAR const uint8_t *buffer, size_t buflen); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct lpc54_dev_s g_scard_dev = +{ + .dev = + { +#ifdef CONFIG_SDIO_MUXBUS + .lock = lpc54_lock, +#endif + .reset = lpc54_reset, + .capabilities = lpc54_capabilities, + .status = lpc54_status, + .widebus = lpc54_widebus, + .clock = lpc54_clock, + .attach = lpc54_attach, + .sendcmd = lpc54_sendcmd, + .recvsetup = lpc54_recvsetup, + .sendsetup = lpc54_sendsetup, + .cancel = lpc54_cancel, + .waitresponse = lpc54_waitresponse, + .recvR1 = lpc54_recvshortcrc, + .recvR2 = lpc54_recvlong, + .recvR3 = lpc54_recvshort, + .recvR4 = lpc54_recvnotimpl, + .recvR5 = lpc54_recvnotimpl, + .recvR6 = lpc54_recvshortcrc, + .recvR7 = lpc54_recvshort, + .waitenable = lpc54_waitenable, + .eventwait = lpc54_eventwait, + .callbackenable = lpc54_callbackenable, + .registercallback = lpc54_registercallback, +#ifdef CONFIG_LPC54_SDMMC_DMA + .dmarecvsetup = lpc54_dmarecvsetup, + .dmasendsetup = lpc54_dmasendsetup, +#endif + }, +}; + +#ifdef CONFIG_LPC54_SDMMC_DMA +static struct sdmmc_dma_s g_sdmmc_dmadd[1 + (0x10000 / MCI_DMADES1_MAXTR)]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_getreg + * + * Description: + * This function may to used to intercept an monitor all register accesses. + * Clearly this is nothing you would want to do unless you are debugging + * this driver. + * + * Input Parameters: + * addr - The register address to read + * + * Returned Value: + * The value read from the register + * + ****************************************************************************/ + +#ifdef CONFIG_LPC54_SDMMC_REGDEBUG +static uint32_t lpc54_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + + /* Read the value from the register */ + + uint32_t val = getreg32(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + mcinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + mcinfo("[repeats %d more times]\n", count-3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + mcinfo("%08x->%08x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: lpc54_putreg + * + * Description: + * This function may to used to intercept an monitor all register accesses. + * Clearly this is nothing you would want to do unless you are debugging + * this driver. + * + * Input Parameters: + * val - The value to write to the register + * addr - The register address to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_LPC54_SDMMC_REGDEBUG +static void lpc54_putreg(uint32_t val, uint32_t addr) +{ + /* Show the register value being written */ + + mcinfo("%08x<-%08x\n", addr, val); + + /* Write the value */ + + putreg32(val, addr); +} +#endif + +/**************************************************************************** + * Name: lpc54_takesem + * + * Description: + * Take the wait semaphore (handling false alarm wakeups due to the receipt + * of signals). + * + * Input Parameters: + * dev - Instance of the SD card device driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_takesem(struct lpc54_dev_s *priv) +{ + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(&priv->waitsem) != 0) + { + /* The only case that an error should occr here is if the wait was + * awakened by a signal. + */ + + DEBUGASSERT(errno == EINTR); + } +} + +/**************************************************************************** + * Name: lpc54_setclock + * + * Description: + * Define the new clock frequency + * + * Input Parameters: + * clkdiv - A new division value to generate the needed frequency. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void lpc54_setclock(uint32_t clkdiv) +{ + mcinfo("clkdiv=%08lx\n", (unsigned long)clkdiv); + + /* Disable the clock before setting frequency */ + + lpc54_sdcard_clock(false); + + /* Inform CIU */ + + lpc54_ciu_sendcmd(SDMMC_CMD_UPDCLOCK | SDMMC_CMD_WAITPREV, 0); + + /* Set Divider0 to desired value */ + + lpc54_putreg(clkdiv, LPC54_SDMMC_CLKDIV); + + /* Inform CIU */ + + lpc54_ciu_sendcmd(SDMMC_CMD_UPDCLOCK | SDMMC_CMD_WAITPREV, 0); + + /* Enable the clock */ + + lpc54_sdcard_clock(true); + + /* Inform CIU */ + + lpc54_ciu_sendcmd(SDMMC_CMD_UPDCLOCK | SDMMC_CMD_WAITPREV, 0); +} + +/**************************************************************************** + * Name: lpc54_sdcard_clock + * + * Description: Enable/Disable the SDCard clock + * + * Input Parameters: + * enable - False = clock disabled; True = clock enabled. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void lpc54_sdcard_clock(bool enable) +{ + if (enable) + { + lpc54_putreg(SDMMC_CLKENA_ENABLE, LPC54_SDMMC_CLKENA); + } + else + { + lpc54_putreg(0, LPC54_SDMMC_CLKENA); + } +} + +/**************************************************************************** + * Name: lpc54_ciu_sendcmd + * + * Description: + * Function to send command to Card interface unit (CIU) + * + * Input Parameters: + * cmd - The command to be executed + * arg - The argument to use with the command. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int lpc54_ciu_sendcmd(uint32_t cmd, uint32_t arg) +{ + volatile int32_t tmo = SDCARD_CMDTIMEOUT; + + mcinfo("cmd=%04lx arg=%04lx\n", (unsigned long)cmd, (unsigned long)arg); + + /* Set command arg reg */ + + lpc54_putreg(arg, LPC54_SDMMC_CMDARG); + lpc54_putreg(SDMMC_CMD_STARTCMD | cmd, LPC54_SDMMC_CMD); + + /* Poll until command is accepted by the CIU */ + + while (--tmo > 0 && (lpc54_getreg(LPC54_SDMMC_CMD) & SDMMC_CMD_STARTCMD) != 0) + { + } + + return (tmo < 1) ? 1 : 0; +} + +/**************************************************************************** + * Name: lpc54_enable_ints + * + * Description: + * Enable/disable SD card interrupts per functional settings. + * + * Input Parameters: + * priv - A reference to the SD card device state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_enable_ints(struct lpc54_dev_s *priv) +{ + uint32_t regval; + +#ifdef CONFIG_LPC54_SDMMC_DMA + mcinfo("waitmask=%04lx xfrmask=%04lx dmamask=%04lx RINTSTS=%08lx\n", + (unsigned long)priv->waitmask, (unsigned long)priv->xfrmask, + (unsigned long)priv->dmamask, + (unsigned long)lpc54_getreg(LPC54_SDMMC_RINTSTS)); + + /* Enable DMA-related interrupts */ + + lpc54_putreg(priv->dmamask, LPC54_SDMMC_IDINTEN); + +#else + mcinfo("waitmask=%04lx xfrmask=%04lx RINTSTS=%08lx\n", + (unsigned long)priv->waitmask, (unsigned long)priv->xfrmask, + (unsigned long)lpc54_getreg(LPC54_SDMMC_RINTSTS)); +#endif + + /* Enable SDMMC interrupts */ + + regval = priv->xfrmask | priv->waitmask | SDCARD_INT_CDET; + lpc54_putreg(regval, LPC54_SDMMC_INTMASK); +} + +/**************************************************************************** + * Name: lpc54_disable_allints + * + * Description: + * Disable all SD card interrupts. + * + * Input Parameters: + * priv - A reference to the SD card device state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_disable_allints(struct lpc54_dev_s *priv) +{ +#ifdef CONFIG_LPC54_SDMMC_DMA + /* Disable DMA-related interrupts */ + + lpc54_putreg(0, LPC54_SDMMC_IDINTEN); + priv->dmamask = 0; +#endif + + /* Disable all SDMMC interrupts (except card detect) */ + + lpc54_putreg(SDCARD_INT_CDET, LPC54_SDMMC_INTMASK); + priv->waitmask = 0; + priv->xfrmask = 0; +} + +/**************************************************************************** + * Name: lpc54_config_waitints + * + * Description: + * Enable/disable SD card interrupts needed to suport the wait function + * + * Input Parameters: + * priv - A reference to the SD card device state structure + * waitmask - The set of bits in the SD card INTMASK register to set + * waitevents - Waited for events + * wkupevent - Wake-up events + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_config_waitints(struct lpc54_dev_s *priv, uint32_t waitmask, + sdio_eventset_t waitevents, + sdio_eventset_t wkupevent) +{ + irqstate_t flags; + + mcinfo("waitevents=%04x wkupevent=%04x\n", + (unsigned)waitevents, (unsigned)wkupevent); + + /* Save all of the data and set the new interrupt mask in one, atomic + * operation. + */ + + flags = enter_critical_section(); + priv->waitevents = waitevents; + priv->wkupevent = wkupevent; + priv->waitmask = waitmask; + + lpc54_enable_ints(priv); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: lpc54_config_xfrints + * + * Description: + * Enable SD card interrupts needed to support the data transfer event + * + * Input Parameters: + * priv - A reference to the SD card device state structure + * xfrmask - The set of bits in the SD card MASK register to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_config_xfrints(struct lpc54_dev_s *priv, uint32_t xfrmask) +{ + irqstate_t flags; + flags = enter_critical_section(); + + priv->xfrmask = xfrmask; + lpc54_enable_ints(priv); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: lpc54_config_dmaints + * + * Description: + * Enable DMA transfer interrupts + * + * Input Parameters: + * priv - A reference to the SD card device state structure + * dmamask - The set of bits in the SD card MASK register to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_LPC54_SDMMC_DMA +static void lpc54_config_dmaints(struct lpc54_dev_s *priv, uint32_t xfrmask, + uint32_t dmamask) +{ + irqstate_t flags; + flags = enter_critical_section(); + + priv->xfrmask = xfrmask; + priv->dmamask = dmamask; + lpc54_enable_ints(priv); + + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: lpc54_eventtimeout + * + * Description: + * The watchdog timeout setup when the event wait start has expired without + * any other waited-for event occurring. + * + * Input Parameters: + * argc - The number of arguments (should be 1) + * arg - The argument (state structure reference cast to uint32_t) + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +static void lpc54_eventtimeout(int argc, uint32_t arg) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)arg; + + mcinfo("argc=%d, arg=%08lx\n", argc, (unsigned long)arg); + + /* There is always race conditions with timer expirations. */ + + DEBUGASSERT((priv->waitevents & SDIOWAIT_TIMEOUT) != 0 || priv->wkupevent != 0); + + /* Is a data transfer complete event expected? */ + + if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0) + { + /* Yes.. wake up any waiting threads */ + + lpc54_endwait(priv, SDIOWAIT_TIMEOUT); + mcerr("ERROR: Timeout: remaining: %d\n", priv->remaining); + } +} + +/**************************************************************************** + * Name: lpc54_endwait + * + * Description: + * Wake up a waiting thread if the waited-for event has occurred. + * + * Input Parameters: + * priv - An instance of the SD card device interface + * wkupevent - The event that caused the wait to end + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +static void lpc54_endwait(struct lpc54_dev_s *priv, sdio_eventset_t wkupevent) +{ + mcinfo("wkupevent=%04x\n", (unsigned)wkupevent); + + /* Cancel the watchdog timeout */ + + (void)wd_cancel(priv->waitwdog); + + /* Disable event-related interrupts */ + + lpc54_config_waitints(priv, 0, 0, wkupevent); + + /* Wake up the waiting thread */ + + lpc54_givesem(priv); +} + +/**************************************************************************** + * Name: lpc54_endtransfer + * + * Description: + * Terminate a transfer with the provided status. This function is called + * only from the SD card interrupt handler when end-of-transfer conditions + * are detected. + * + * Input Parameters: + * priv - An instance of the SD card device interface + * wkupevent - The event that caused the transfer to end + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +static void lpc54_endtransfer(struct lpc54_dev_s *priv, sdio_eventset_t wkupevent) +{ + mcinfo("wkupevent=%04x\n", (unsigned)wkupevent); + + /* Disable all transfer related interrupts */ + + lpc54_config_xfrints(priv, 0); + + /* Clearing pending interrupt status on all transfer related interrupts */ + + lpc54_putreg(priv->waitmask, LPC54_SDMMC_RINTSTS); + + /* Mark the transfer finished */ + + priv->remaining = 0; + + /* Is a thread wait for these data transfer complete events? */ + + if ((priv->waitevents & wkupevent) != 0) + { + /* Yes.. wake up any waiting threads */ + + lpc54_endwait(priv, wkupevent); + } +} + +/**************************************************************************** + * Name: lpc54_sdmmc_interrupt + * + * Description: + * SD card interrupt handler + * + * Input Parameters: + * dev - An instance of the SD card device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int lpc54_sdmmc_interrupt(int irq, void *context, FAR void *arg) +{ + struct lpc54_dev_s *priv = &g_scard_dev; + uint32_t enabled; + uint32_t pending; + + /* Loop while there are pending interrupts. Check the SD card status + * register. Mask out all bits that don't correspond to enabled + * interrupts. (This depends on the fact that bits are ordered + * the same in both the STA and MASK register). If there are non-zero + * bits remaining, then we have work to do here. + */ + + while ((enabled = lpc54_getreg(LPC54_SDMMC_MINTSTS)) != 0) + { + /* Clear pending status */ + + lpc54_putreg(enabled, LPC54_SDMMC_RINTSTS); + +#ifdef CONFIG_MMCSD_HAVE_CARDDETECT + /* Handle in card detection events ************************************/ + + if ((enabled & SDMMC_INT_CDET) != 0) + { + sdio_statset_t cdstatus; + + /* Update card status */ + + cdstatus = priv->cdstatus; + if ((lpc54_getreg(LPC54_SDMMC_CDETECT) & SDMMC_CDETECT_NOTPRESENT) == 0) + { + priv->cdstatus |= SDIO_STATUS_PRESENT; + +#ifdef CONFIG_MMCSD_HAVE_WRITEPROTECT + if ((lpc54_getreg(LPC54_SDMMC_WRTPRT) & SDMMC_WRTPRT_PROTECTED) != 0) + { + priv->cdstatus |= SDIO_STATUS_WRPROTECTED; + } + else +#endif + { + priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED; + } + +#ifdef CONFIG_LPC54_SDMMC_PWRCTRL + /* Enable/ power to the SD card */ + + lpc54_putreg(SDMMC_PWREN, LPC54_SDMMC_PWREN); +#endif + + } + else + { + priv->cdstatus &= ~(SDIO_STATUS_PRESENT | SDIO_STATUS_WRPROTECTED); + +#ifdef CONFIG_LPC54_SDMMC_PWRCTRL + /* Disable power to the SD card */ + + lpc54_putreg(0, LPC54_SDMMC_PWREN); +#endif + } + + mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); + + /* Perform any requested callback if the status has changed */ + + if (cdstatus != priv->cdstatus) + { + lpc54_callback(priv); + } + } +#endif + + /* Handle idata transfer events ***************************************/ + + pending = enabled & priv->xfrmask; + if (pending != 0) + { + /* Handle data request events */ + + if ((pending & SDMMC_INT_TXDR) != 0) + { + uint32_t status; + + /* Transfer data to the TX FIFO */ + + mcinfo("Write FIFO\n"); + DEBUGASSERT(priv->wrdir); + + for (status = lpc54_getreg(LPC54_SDMMC_STATUS); + (status & SDMMC_STATUS_FIFOFULL) == 0 && + priv->remaining > 0; + status = lpc54_getreg(LPC54_SDMMC_STATUS)) + { + lpc54_putreg(*priv->buffer, LPC54_SDMMC_DATA); + priv->buffer++; + priv->remaining -= 4; + } + + /* If all of the data has been transferred to the FIFO, then + * disable further TX data requests and wait for the data end + * event. + */ + + if (priv->remaining <= 0) + { + uint32_t intmask = lpc54_getreg(LPC54_SDMMC_INTMASK); + intmask &= ~SDMMC_INT_TXDR; + lpc54_putreg(intmask, LPC54_SDMMC_INTMASK); + + priv->xfrmask &= ~SDMMC_INT_TXDR; + } + } + else if ((pending & SDMMC_INT_RXDR) != 0) + { + uint32_t status; + + /* Transfer data from the RX FIFO */ + + mcinfo("Read from FIFO\n"); + DEBUGASSERT(!priv->wrdir); + + for (status = lpc54_getreg(LPC54_SDMMC_STATUS); + (status & SDMMC_STATUS_FIFOEMPTY) == 0 && + priv->remaining > 0; + status = lpc54_getreg(LPC54_SDMMC_STATUS)) + { + *priv->buffer = lpc54_getreg(LPC54_SDMMC_DATA); + priv->buffer++; + priv->remaining -= 4; + } + + /* If all of the data has been transferred to the FIFO, then + * just force DTO event processing (the DTO interrupt is not + * actually even enabled in this use case). + */ + + if (priv->remaining <= 0) + { + /* Force the DTO event */ + + pending |= SDMMC_INT_DTO; + } + } + + /* Check for transfer errors */ + /* Handle data block send/receive CRC failure */ + + if ((pending & SDMMC_INT_DCRC) != 0) + { + /* Terminate the transfer with an error */ + + mcerr("ERROR: Data CRC failure, pending=%08x remaining: %d\n", + pending, priv->remaining); + lpc54_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } + + /* Handle data timeout error */ + + else if ((pending & SDMMC_INT_DRTO) != 0) + { + /* Terminate the transfer with an error */ + + mcerr("ERROR: Data timeout, pending=%08x remaining: %d\n", + pending, priv->remaining); + lpc54_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT); + } + + /* Handle RX FIFO overrun error */ + + else if ((pending & SDMMC_INT_FRUN) != 0) + { + /* Terminate the transfer with an error */ + + mcerr("ERROR: RX FIFO overrun, pending=%08x remaining: %d\n", + pending, priv->remaining); + lpc54_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } + + /* Handle TX FIFO underrun error */ + + else if ((pending & SDMMC_INT_FRUN) != 0) + { + /* Terminate the transfer with an error */ + + mcerr("ERROR: TX FIFO underrun, pending=%08x remaining: %d\n", + pending, priv->remaining); + lpc54_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } + + /* Handle start bit error */ + + else if ((pending & SDMMC_INT_SBE) != 0) + { + /* Terminate the transfer with an error */ + + mcerr("ERROR: Start bit, pending=%08x remaining: %d\n", + pending, priv->remaining); + lpc54_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } + + /* Handle data end events. Note that RXDR may accompany DTO, DTO + * will be set on received while there is still data in the FIFO. + * So for the case of receiving, we don't actually even enable the + * DTO interrupt. + */ + + else if ((pending & SDMMC_INT_DTO) != 0) + { + /* Finish the transfer */ + + lpc54_endtransfer(priv, SDIOWAIT_TRANSFERDONE); + } + } + + /* Handle wait events *************************************************/ + + pending = enabled & priv->waitmask; + if (pending != 0) + { + /* Is this a response error event? */ + + if ((pending & SDCARD_INT_RESPERR) != 0) + { + /* If response errors are enabled, then we must certainly be + * waiting for a response. + */ + + DEBUGASSERT((priv->waitevents & SDIOWAIT_RESPONSEDONE) != 0); + + /* Wake the thread up */ + + mcerr("ERROR: Response error, pending=%08x\n", pending); + lpc54_endwait(priv, SDIOWAIT_RESPONSEDONE | SDIOWAIT_ERROR); + } + + /* Is this a command (plus response) completion event? */ + + else if ((pending & SDMMC_INT_CDONE) != 0) + { + /* Yes.. Is their a thread waiting for response done? */ + + if ((priv->waitevents & SDIOWAIT_RESPONSEDONE) != 0) + { + /* Yes.. wake the thread up */ + + lpc54_endwait(priv, SDIOWAIT_RESPONSEDONE); + } + + /* NO.. Is their a thread waiting for command done? */ + + else if ((priv->waitevents & SDIOWAIT_CMDDONE) != 0) + { + /* Yes.. wake the thread up */ + + lpc54_endwait(priv, SDIOWAIT_CMDDONE); + } + } + } + } + +#ifdef CONFIG_LPC54_SDMMC_DMA + /* DMA error events *******************************************************/ + + pending = lpc54_getreg(LPC54_SDMMC_IDSTS); + if ((pending & priv->dmamask) != 0) + { + mcerr("ERROR: IDTS=%08lx\n", (unsigned long)pending); + + /* Clear the pending interrupts */ + + lpc54_putreg(pending, LPC54_SDMMC_IDSTS); + + /* Abort the transfer */ + + lpc54_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: lpc54_lock + * + * Description: + * Locks the bus. Function calls low-level multiplexed bus routines to + * resolve bus requests and acknowledgment issues. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * lock - TRUE to lock, FALSE to unlock. + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_MUXBUS +static int lpc54_lock(FAR struct sdio_dev_s *dev, bool lock) +{ + /* Single SD card instance so there is only one possibility. The multiplex + * bus is part of board support package. + */ + + lpc54_muxbus_sdio_lock(lock); + return OK; +} +#endif + +/**************************************************************************** + * Name: lpc54_reset + * + * Description: + * Reset the SD card controller. Undo all setup and initialization. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_reset(FAR struct sdio_dev_s *dev) +{ + FAR struct lpc54_dev_s *priv = (FAR struct lpc54_dev_s *)dev; + irqstate_t flags; + uint32_t regval; + + mcinfo("Resetting...\n"); + + flags = enter_critical_section(); + + /* Reset DMA controller internal registers. */ + + lpc54_putreg(SDMMC_BMOD_SWR, LPC54_SDMMC_BMOD); + + /* Reset all blocks */ + + lpc54_putreg(SDMMC_CTRL_CNTLRRESET | SDMMC_CTRL_FIFORESET | + SDMMC_CTRL_DMARESET, LPC54_SDMMC_CTRL); + + while ((lpc54_getreg(LPC54_SDMMC_CTRL) & + (SDMMC_CTRL_CNTLRRESET | SDMMC_CTRL_FIFORESET | SDMMC_CTRL_DMARESET)) != 0) + { + } + + /* Reset data */ + + priv->waitevents = 0; /* Set of events to be waited for */ + priv->waitmask = 0; /* Interrupt enables for event waiting */ + priv->wkupevent = 0; /* The event that caused the wakeup */ + + wd_cancel(priv->waitwdog); /* Cancel any timeouts */ + + /* Interrupt mode data transfer support */ + + priv->buffer = 0; /* Address of current R/W buffer */ + priv->remaining = 0; /* Number of bytes remaining in the transfer */ + priv->xfrmask = 0; /* Interrupt enables for data transfer */ +#ifdef CONFIG_LPC54_SDMMC_DMA + priv->dmamask = 0; /* Interrupt enables for DMA transfer */ +#endif + + /* DMA data transfer support */ + + priv->widebus = true; /* Required for DMA support */ + priv->cdstatus = 0; /* Card status is unknown */ + +#ifdef CONFIG_LPC54_SDMMC_DMA + priv->dmamode = false; /* true: DMA mode transfer */ +#endif + + /* Select 1-bit wide bus */ + + lpc54_putreg(SDMMC_CTYPE_WIDTH1, LPC54_SDMMC_CTYPE); + + /* Enable interrupts */ + + regval = lpc54_getreg(LPC54_SDMMC_CTRL); + regval |= SDMMC_CTRL_INTENABLE; + lpc54_putreg(regval, LPC54_SDMMC_CTRL); + + /* Disable Interrupts except for card detection. */ + + lpc54_putreg(SDCARD_INT_CDET, LPC54_SDMMC_INTMASK); + +#ifdef CONFIG_MMCSD_HAVE_CARDDETECT + /* Set the card debounce time. Number of host clocks (SD_CLK) used by + * debounce filter logic for card detect. typical debounce time is 5-25 + * ms. + */ + + lpc54_putreg(DEBOUNCE_TICKS, LPC54_SDMMC_DEBNCE); +#endif + + /* Clear to Interrupts */ + + lpc54_putreg(0xffffffff, LPC54_SDMMC_RINTSTS); + + /* Define MAX Timeout */ + + lpc54_putreg(SDCARD_LONGTIMEOUT, LPC54_SDMMC_TMOUT); + + /* Disable clock to CIU (needs latch) */ + + lpc54_putreg(0, LPC54_SDMMC_CLKENA); + leave_critical_section(flags); + +#if defined(CONFIG_LPC54_SDMMC_PWRCTRL) && !defined(CONFIG_MMCSD_HAVE_CARDDETECT) + /* Enable power to the SD card */ + + lpc54_putreg(SDMMC_PWREN, LPC54_SDMMC_PWREN); +#endif +} + +/**************************************************************************** + * Name: lpc54_capabilities + * + * Description: + * Get capabilities (and limitations) of the SDIO driver (optional) + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Returns a bitset of status values (see SDIO_CAPS_* defines) + * + ****************************************************************************/ + +static sdio_capset_t lpc54_capabilities(FAR struct sdio_dev_s *dev) +{ + sdio_capset_t caps = 0; + + caps |= SDIO_CAPS_DMABEFOREWRITE; + +#ifdef CONFIG_SDIO_WIDTH_D1_ONLY + caps |= SDIO_CAPS_1BIT_ONLY; +#endif +#ifdef CONFIG_LPC54_SDMMC_DMA + caps |= SDIO_CAPS_DMASUPPORTED; +#endif + + return caps; +} + +/**************************************************************************** + * Name: lpc54_status + * + * Description: + * Get SD card status. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Returns a bitset of status values (see lpc54_status_* defines) + * + ****************************************************************************/ + +static sdio_statset_t lpc54_status(FAR struct sdio_dev_s *dev) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev; + + mcinfo("cdstatus=%02x\n", priv->cdstatus); + + return priv->cdstatus; +} + +/**************************************************************************** + * Name: lpc54_widebus + * + * Description: + * Called after change in Bus width has been selected (via ACMD6). Most + * controllers will need to perform some special operations to work + * correctly in the new bus mode. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * wide - true: wide bus (4-bit) bus mode enabled + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_widebus(FAR struct sdio_dev_s *dev, bool wide) +{ + mcinfo("wide=%d\n", wide); +} + +/**************************************************************************** + * Name: lpc54_clock + * + * Description: + * Enable/disable SD card clocking + * + * Input Parameters: + * dev - An instance of the SD card device interface + * rate - Specifies the clocking to use (see enum sdio_clock_e) + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev; + uint8_t clkdiv; + uint8_t ctype; + bool enabled = false; + bool widebus = false; + + switch (rate) + { + /* Disable clocking (with default ID mode divisor) */ + + default: + case CLOCK_SDIO_DISABLED: + clkdiv = SDMMC_CLKDIV0(BOARD_CLKDIV_INIT); + ctype = SDCARD_BUS_D1; + enabled = false; + widebus = false; + return; + break; + + /* Enable in initial ID mode clocking (<400KHz) */ + + case CLOCK_IDMODE: + clkdiv = SDMMC_CLKDIV0(BOARD_CLKDIV_INIT); + ctype = SDCARD_BUS_D1; + enabled = true; + widebus = false; + break; + + /* Enable in MMC normal operation clocking */ + + case CLOCK_MMC_TRANSFER: + clkdiv = SDMMC_CLKDIV0(BOARD_CLKDIV_MMCXFR); + ctype = SDCARD_BUS_D1; + enabled = true; + widebus = false; + break; + + /* SD normal operation clocking (wide 4-bit mode) */ + + case CLOCK_SD_TRANSFER_4BIT: +#ifndef CONFIG_SDIO_WIDTH_D1_ONLY + clkdiv = SDMMC_CLKDIV0(BOARD_CLKDIV_SDWIDEXFR); + ctype = SDCARD_BUS_D4; + enabled = true; + widebus = true; + break; +#endif + + /* SD normal operation clocking (narrow 1-bit mode) */ + + case CLOCK_SD_TRANSFER_1BIT: + clkdiv = SDMMC_CLKDIV0(BOARD_CLKDIV_SDXFR); + ctype = SDCARD_BUS_D1; + enabled = true; + widebus = false; + break; + } + + /* Setup the card bus width */ + + mcinfo("widebus=%d\n", widebus); + + priv->widebus = widebus; + lpc54_putreg(ctype, LPC54_SDMMC_CTYPE); + + /* Set the new clock frequency division */ + + lpc54_setclock(clkdiv); + + /* Enable the new clock */ + + lpc54_sdcard_clock(enabled); +} + +/**************************************************************************** + * Name: lpc54_attach + * + * Description: + * Attach and prepare interrupts + * + * Input Parameters: + * dev - An instance of the SD card device interface + * + * Returned Value: + * OK on success; A negated errno on failure. + * + ****************************************************************************/ + +static int lpc54_attach(FAR struct sdio_dev_s *dev) +{ + int ret; + uint32_t regval; + + mcinfo("Attaching..\n"); + + /* Attach the SD card interrupt handler */ + + ret = irq_attach(LPC54_IRQ_SDMMC, lpc54_sdmmc_interrupt, NULL); + if (ret == OK) + { + /* Disable all interrupts at the SD card controller and clear static + * interrupt flags + */ + + lpc54_putreg(0, LPC54_SDMMC_INTMASK); + lpc54_putreg(SDMMC_INT_ALL, LPC54_SDMMC_RINTSTS); + + /* Enable Interrupts to happen when the INTMASK is activated */ + + regval = lpc54_getreg(LPC54_SDMMC_CTRL); + regval |= SDMMC_CTRL_INTENABLE; + lpc54_putreg(regval, LPC54_SDMMC_CTRL); + + /* Enable card detection interrupts */ + + lpc54_putreg(SDCARD_INT_CDET, LPC54_SDMMC_INTMASK); + + /* Enable SD card interrupts at the NVIC. They can now be enabled at + * the SD card controller as needed. + */ + + up_enable_irq(LPC54_IRQ_SDMMC); + } + + return ret; +} + +/**************************************************************************** + * Name: lpc54_sendcmd + * + * Description: + * Send the SD card command + * + * Input Parameters: + * dev - An instance of the SD card device interface + * cmd - The command to send (32-bits, encoded) + * arg - 32-bit argument required with some commands + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int lpc54_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t arg) +{ + uint32_t regval = 0; + uint32_t cmdidx; + + mcinfo("cmd=%04x arg=%04x\n", cmd, arg); + + /* The CMD0 needs the SENDINIT CMD */ + + if (cmd == 0) + { + regval |= SDMMC_CMD_SENDINIT; + } + + /* Is this a Read/Write Transfer Command ? */ + + if ((cmd & MMCSD_WRDATAXFR) == MMCSD_WRDATAXFR) + { + regval |= SDMMC_CMD_DATAXFREXPTD | SDMMC_CMD_WRITE | SDMMC_CMD_WAITPREV; + } + else if ((cmd & MMCSD_RDDATAXFR) == MMCSD_RDDATAXFR) + { + regval |= SDMMC_CMD_DATAXFREXPTD | SDMMC_CMD_WAITPREV; + } + + /* Set WAITRESP bits */ + + switch (cmd & MMCSD_RESPONSE_MASK) + { + case MMCSD_NO_RESPONSE: + regval |= SDMMC_CMD_NORESPONSE; + break; + + case MMCSD_R1B_RESPONSE: + regval |= SDMMC_CMD_WAITPREV; + case MMCSD_R1_RESPONSE: + case MMCSD_R3_RESPONSE: + case MMCSD_R4_RESPONSE: + case MMCSD_R5_RESPONSE: + case MMCSD_R6_RESPONSE: + case MMCSD_R7_RESPONSE: + regval |= SDMMC_CMD_SHORTRESPONSE; + break; + + case MMCSD_R2_RESPONSE: + regval |= SDMMC_CMD_LONGRESPONSE; + break; + } + + /* Set the command index */ + + cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT; + regval |= cmdidx; + + mcinfo("cmd: %04x arg: %04x regval: %08x\n", cmd, arg, regval); + + /* Write the SD card CMD */ + + lpc54_putreg(SDCARD_RESPDONE_CLEAR | SDCARD_CMDDONE_CLEAR, + LPC54_SDMMC_RINTSTS); + lpc54_ciu_sendcmd(regval, arg); + + return OK; +} + +/**************************************************************************** + * Name: lpc54_recvsetup + * + * Description: + * Setup hardware in preparation for data transfer from the card in non-DMA + * (interrupt driven mode). This method will do whatever controller setup + * is necessary. This would be called for SD memory just BEFORE sending + * CMD13 (SEND_STATUS), CMD17 (READ_SINGLE_BLOCK), CMD18 + * (READ_MULTIPLE_BLOCKS), ACMD51 (SEND_SCR), etc. Normally, SDCARD_WAITEVENT + * will be called to receive the indication that the transfer is complete. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * buffer - Address of the buffer in which to receive the data + * nbytes - The number of bytes in the transfer + * + * Returned Value: + * Number of bytes sent on success; a negated errno on failure + * + ****************************************************************************/ + +static int lpc54_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, + size_t nbytes) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev; + uint32_t blocksize; + uint32_t bytecnt; +#ifdef CONFIG_LPC54_SDMMC_DMA + uint32_t regval; +#endif + + mcinfo("nbytes=%ld\n", (long) nbytes); + + DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0); + DEBUGASSERT(((uint32_t)buffer & 3) == 0); + + /* Save the destination buffer information for use by the interrupt handler */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = nbytes; + priv->wrdir = false; +#ifdef CONFIG_LPC54_SDMMC_DMA + priv->dmamode = false; +#endif + + /* Then set up the SD card data path */ + + if (nbytes < 64) + { + blocksize = nbytes; + bytecnt = nbytes; + } + else + { + blocksize = 64; + bytecnt = nbytes; + DEBUGASSERT((nbytes & 0x3f) == 0); + } + + lpc54_putreg(blocksize, LPC54_SDMMC_BLKSIZ); + lpc54_putreg(bytecnt, LPC54_SDMMC_BYTCNT); + + /* Configure the FIFO so that we will receive the RXDR interrupt whenever + * there are more than 1 words (at least 8 bytes) in the RX FIFO. + */ + + lpc54_putreg(SDMMC_FIFOTH_RXWMARK(1), LPC54_SDMMC_FIFOTH); + +#ifdef CONFIG_LPC54_SDMMC_DMA + /* Make sure that internal DMA is disabled */ + + lpc54_putreg(0, LPC54_SDMMC_BMOD); + + regval = lpc54_getreg(LPC54_SDMMC_CTRL); + regval &= ~SDMMC_CTRL_INTDMA; + lpc54_putreg(regval, LPC54_SDMMC_CTRL); +#endif + + /* Configure the transfer interrupts */ + + lpc54_config_xfrints(priv, SDCARD_RECV_MASK); + return OK; +} + +/**************************************************************************** + * Name: lpc54_sendsetup + * + * Description: + * Setup hardware in preparation for data transfer from the card. This + * method will do whatever controller setup is necessary. This would be + * called for SD memory just AFTER sending CMD24 (WRITE_BLOCK), CMD25 + * (WRITE_MULTIPLE_BLOCK), ... and before SDCARD_SENDDATA is called. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * buffer - Address of the buffer containing the data to send + * nbytes - The number of bytes in the transfer + * + * Returned Value: + * Number of bytes sent on success; a negated errno on failure + * + ****************************************************************************/ + +static int lpc54_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, + size_t nbytes) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev; +#ifdef CONFIG_LPC54_SDMMC_DMA + uint32_t regval; +#endif + + mcinfo("nbytes=%ld\n", (long)nbytes); + + DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0); + DEBUGASSERT(((uint32_t)buffer & 3) == 0); + + /* Save the source buffer information for use by the interrupt handler */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = nbytes; + priv->wrdir = true; +#ifdef CONFIG_LPC54_SDMMC_DMA + priv->dmamode = false; +#endif + + /* Configure the FIFO so that we will receive the TXDR interrupt whenever + * there the TX FIFO is at least half empty. + */ + + lpc54_putreg(SDMMC_FIFOTH_TXWMARK(LPC54_TXFIFO_DEPTH / 2), + LPC54_SDMMC_FIFOTH); + +#ifdef CONFIG_LPC54_SDMMC_DMA + /* Make sure that internal DMA is disabled */ + + lpc54_putreg(0, LPC54_SDMMC_BMOD); + + regval = lpc54_getreg(LPC54_SDMMC_CTRL); + regval &= ~SDMMC_CTRL_INTDMA; + lpc54_putreg(regval, LPC54_SDMMC_CTRL); +#endif + + /* Configure the transfer interrupts */ + + lpc54_config_xfrints(priv, SDCARD_SEND_MASK); + return OK; +} + +/**************************************************************************** + * Name: lpc54_cancel + * + * Description: + * Cancel the data transfer setup of SDCARD_RECVSETUP, SDCARD_SENDSETUP, + * SDCARD_DMARECVSETUP or SDCARD_DMASENDSETUP. This must be called to cancel + * the data transfer setup if, for some reason, you cannot perform the + * transfer. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * + * Returned Value: + * OK is success; a negated errno on failure + * + ****************************************************************************/ + +static int lpc54_cancel(FAR struct sdio_dev_s *dev) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev; + + mcinfo("Cancelling..\n"); + + /* Disable all transfer- and event- related interrupts */ + + lpc54_disable_allints(priv); + + /* Clearing pending interrupt status on all transfer- and event- related + * interrupts + */ + + lpc54_putreg(SDCARD_WAITALL_CLEAR, LPC54_SDMMC_RINTSTS); + + /* Cancel any watchdog timeout */ + + (void)wd_cancel(priv->waitwdog); + + /* Mark no transfer in progress */ + + priv->remaining = 0; + return OK; +} + +/**************************************************************************** + * Name: lpc54_waitresponse + * + * Description: + * Poll-wait for the response to the last command to be ready. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * cmd - The command that was sent. See 32-bit command definitions above. + * + * Returned Value: + * OK is success; a negated errno on failure + * + ****************************************************************************/ + +static int lpc54_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) +{ + volatile int32_t timeout; + uint32_t events; + + mcinfo("cmd=%04x\n", cmd); + + switch (cmd & MMCSD_RESPONSE_MASK) + { + case MMCSD_NO_RESPONSE: + events = SDCARD_CMDDONE_STA; + timeout = SDCARD_CMDTIMEOUT; + break; + + case MMCSD_R1_RESPONSE: + case MMCSD_R1B_RESPONSE: + case MMCSD_R2_RESPONSE: + case MMCSD_R6_RESPONSE: + events = (SDCARD_CMDDONE_STA | SDCARD_RESPDONE_STA); + timeout = SDCARD_LONGTIMEOUT; + break; + + case MMCSD_R4_RESPONSE: + case MMCSD_R5_RESPONSE: + return -ENOSYS; + + case MMCSD_R3_RESPONSE: + case MMCSD_R7_RESPONSE: + events = (SDCARD_CMDDONE_STA | SDCARD_RESPDONE_STA); + timeout = SDCARD_CMDTIMEOUT; + break; + + default: + return -EINVAL; + } + + mcinfo("cmd: %04x events: %04x STATUS: %08x RINTSTS: %08x\n", + cmd, events, lpc54_getreg(LPC54_SDMMC_STATUS), + lpc54_getreg(LPC54_SDMMC_RINTSTS)); + + /* Then wait for the response (or timeout or error) */ + + while ((lpc54_getreg(LPC54_SDMMC_RINTSTS) & events) != events) + { + if (--timeout <= 0) + { + mcerr("ERROR: Timeout cmd: %04x events: %04x STA: %08x RINTSTS: %08x\n", + cmd, events, lpc54_getreg(LPC54_SDMMC_STATUS), + lpc54_getreg(LPC54_SDMMC_RINTSTS)); + return -ETIMEDOUT; + } + else if ((lpc54_getreg(LPC54_SDMMC_RINTSTS) & SDCARD_INT_RESPERR) != 0) + { + mcerr("ERROR: SDMMC failure cmd: %04x events: %04x STA: %08x RINTSTS: %08x\n", + cmd, events, lpc54_getreg(LPC54_SDMMC_STATUS), + lpc54_getreg(LPC54_SDMMC_RINTSTS)); + return -EIO; + } + } + + lpc54_putreg(SDCARD_CMDDONE_CLEAR, LPC54_SDMMC_RINTSTS); + return OK; +} + +/**************************************************************************** + * Name: lpc54_recvRx + * + * Description: + * Receive response to SD card command. Only the critical payload is + * returned -- that is 32 bits for 48 bit status and 128 bits for 136 bit + * status. The driver implementation should verify the correctness of + * the remaining, non-returned bits (CRCs, CMD index, etc.). + * + * Input Parameters: + * dev - An instance of the SD card device interface + * Rx - Buffer in which to receive the response + * + * Returned Value: + * Number of bytes sent on success; a negated errno on failure. Here a + * failure means only a faiure to obtain the requested reponse (due to + * transport problem -- timeout, CRC, etc.). The implementation only + * assures that the response is returned intacta and does not check errors + * within the response itself. + * + ****************************************************************************/ + +static int lpc54_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort) +{ + uint32_t regval; + + int ret = OK; + + mcinfo("cmd=%04x\n", cmd); + + /* R1 Command response (48-bit) + * 47 0 Start bit + * 46 0 Transmission bit (0=from card) + * 45:40 bit5 - bit0 Command index (0-63) + * 39:8 bit31 - bit0 32-bit card status + * 7:1 bit6 - bit0 CRC7 + * 0 1 End bit + * + * R1b Identical to R1 with the additional busy signaling via the data + * line. + * + * R6 Published RCA Response (48-bit, SD card only) + * 47 0 Start bit + * 46 0 Transmission bit (0=from card) + * 45:40 bit5 - bit0 Command index (0-63) + * 39:8 bit31 - bit0 32-bit Argument Field, consisting of: + * [31:16] New published RCA of card + * [15:0] Card status bits {23,22,19,12:0} + * 7:1 bit6 - bit0 CRC7 + * 0 1 End bit + */ + + +#ifdef CONFIG_DEBUG_FEATURES + if (!rshort) + { + mcerr("ERROR: rshort=NULL\n"); + ret = -EINVAL; + } + + /* Check that this is the correct response to this command */ + + else if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE) + { + mcerr("ERROR: Wrong response CMD=%04x\n", cmd); + ret = -EINVAL; + } + else +#endif + { + /* Check if a timeout or CRC error occurred */ + + regval = lpc54_getreg(LPC54_SDMMC_RINTSTS); + if ((regval & SDMMC_INT_RTO) != 0) + { + mcerr("ERROR: Command timeout: %08x\n", regval); + ret = -ETIMEDOUT; + } + else if ((regval & SDMMC_INT_RCRC) != 0) + { + mcerr("ERROR: CRC failure: %08x\n", regval); + ret = -EIO; + } + } + + /* Clear all pending message completion events and return the R1/R6 + * response. + */ + + lpc54_putreg(SDCARD_RESPDONE_CLEAR | SDCARD_CMDDONE_CLEAR, + LPC54_SDMMC_RINTSTS); + *rshort = lpc54_getreg(LPC54_SDMMC_RESP0); + mcinfo("CRC=%04x\n", *rshort); + + return ret; +} + +static int lpc54_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t rlong[4]) +{ + uint32_t regval; + int ret = OK; + + mcinfo("cmd=%04x\n", cmd); + + /* R2 CID, CSD register (136-bit) + * 135 0 Start bit + * 134 0 Transmission bit (0=from card) + * 133:128 bit5 - bit0 Reserved + * 127:1 bit127 - bit1 127-bit CID or CSD register + * (including internal CRC) + * 0 1 End bit + */ + +#ifdef CONFIG_DEBUG_FEATURES + /* Check that R1 is the correct response to this command */ + + if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE) + { + mcerr("ERROR: Wrong response CMD=%04x\n", cmd); + ret = -EINVAL; + } + else +#endif + { + /* Check if a timeout or CRC error occurred */ + + regval = lpc54_getreg(LPC54_SDMMC_RINTSTS); + if (regval & SDMMC_INT_RTO) + { + mcerr("ERROR: Timeout STA: %08x\n", regval); + ret = -ETIMEDOUT; + } + else if (regval & SDMMC_INT_RCRC) + { + mcerr("ERROR: CRC fail STA: %08x\n", regval); + ret = -EIO; + } + } + + /* Return the long response */ + + lpc54_putreg(SDCARD_RESPDONE_CLEAR | SDCARD_CMDDONE_CLEAR, + LPC54_SDMMC_RINTSTS); + if (rlong) + { + rlong[0] = lpc54_getreg(LPC54_SDMMC_RESP3); + rlong[1] = lpc54_getreg(LPC54_SDMMC_RESP2); + rlong[2] = lpc54_getreg(LPC54_SDMMC_RESP1); + rlong[3] = lpc54_getreg(LPC54_SDMMC_RESP0); + } + + return ret; +} + +static int lpc54_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort) +{ + uint32_t regval; + int ret = OK; + + mcinfo("cmd=%04x\n", cmd); + + /* R3 OCR (48-bit) + * 47 0 Start bit + * 46 0 Transmission bit (0=from card) + * 45:40 bit5 - bit0 Reserved + * 39:8 bit31 - bit0 32-bit OCR register + * 7:1 bit6 - bit0 Reserved + * 0 1 End bit + */ + + /* Check that this is the correct response to this command */ + +#ifdef CONFIG_DEBUG_FEATURES + if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE) + { + mcerr("ERROR: Wrong response CMD=%04x\n", cmd); + ret = -EINVAL; + } + else +#endif + { + /* Check if a timeout occurred (Apparently a CRC error can terminate + * a good response) + */ + + regval = lpc54_getreg(LPC54_SDMMC_RINTSTS); + if (regval & SDMMC_INT_RTO) + { + mcerr("ERROR: Timeout STA: %08x\n", regval); + ret = -ETIMEDOUT; + } + } + + lpc54_putreg(SDCARD_RESPDONE_CLEAR | SDCARD_CMDDONE_CLEAR, + LPC54_SDMMC_RINTSTS); + if (rshort) + { + *rshort = lpc54_getreg(LPC54_SDMMC_RESP0); + } + + return ret; +} + +/* MMC responses not supported */ + +static int lpc54_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rnotimpl) +{ + mcinfo("cmd=%04x\n", cmd); + + lpc54_putreg(SDCARD_RESPDONE_CLEAR | SDCARD_CMDDONE_CLEAR, + LPC54_SDMMC_RINTSTS); + return -ENOSYS; +} + +/**************************************************************************** + * Name: lpc54_waitenable + * + * Description: + * Enable/disable of a set of SD card wait events. This is part of the + * the SDCARD_WAITEVENT sequence. The set of to-be-waited-for events is + * configured before calling lpc54_eventwait. This is done in this way + * to help the driver to eliminate race conditions between the command + * setup and the subsequent events. + * + * The enabled events persist until either (1) SDCARD_WAITENABLE is called + * again specifying a different set of wait events, or (2) SDCARD_EVENTWAIT + * returns. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * eventset - A bitset of events to enable or disable (see SDIOWAIT_* + * definitions). 0=disable; 1=enable. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_waitenable(FAR struct sdio_dev_s *dev, + sdio_eventset_t eventset) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev; + uint32_t waitmask; + + mcinfo("eventset=%04x\n", (unsigned int)eventset); + DEBUGASSERT(priv != NULL); + + /* Disable event-related interrupts */ + + lpc54_config_waitints(priv, 0, 0, 0); + + /* Select the interrupt mask that will give us the appropriate wakeup + * interrupts. + */ + + waitmask = 0; + if ((eventset & SDIOWAIT_CMDDONE) != 0) + { + waitmask |= SDCARD_CMDDONE_MASK; + } + + if ((eventset & SDIOWAIT_RESPONSEDONE) != 0) + { + waitmask |= SDCARD_RESPDONE_MASK; + } + + if ((eventset & SDIOWAIT_TRANSFERDONE) != 0) + { + waitmask |= SDCARD_XFRDONE_MASK; + } + + /* Enable event-related interrupts */ + + lpc54_config_waitints(priv, waitmask, eventset, 0); +} + +/**************************************************************************** + * Name: lpc54_eventwait + * + * Description: + * Wait for one of the enabled events to occur (or a timeout). Note that + * all events enabled by SDCARD_WAITEVENTS are disabled when lpc54_eventwait + * returns. SDCARD_WAITEVENTS must be called again before lpc54_eventwait + * can be used again. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * timeout - Maximum time in milliseconds to wait. Zero means immediate + * timeout with no wait. The timeout value is ignored if + * SDIOWAIT_TIMEOUT is not included in the waited-for eventset. + * + * Returned Value: + * Event set containing the event(s) that ended the wait. Should always + * be non-zero. All events are disabled after the wait concludes. + * + ****************************************************************************/ + +static sdio_eventset_t lpc54_eventwait(FAR struct sdio_dev_s *dev, + uint32_t timeout) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev; + sdio_eventset_t wkupevent = 0; + irqstate_t flags; + int ret; + + mcinfo("timeout=%lu\n", (unsigned long)timeout); + + /* There is a race condition here... the event may have completed before + * we get here. In this case waitevents will be zero, but wkupevents will + * be non-zero (and, hopefully, the semaphore count will also be non-zero. + */ + + flags = enter_critical_section(); + DEBUGASSERT(priv->waitevents != 0 || priv->wkupevent != 0); + + /* Check if the timeout event is specified in the event set */ + + if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0) + { + int delay; + + /* Yes.. Handle a cornercase: The user request a timeout event but + * with timeout == 0? + */ + + if (!timeout) + { + /* Then just tell the caller that we already timed out */ + + wkupevent = SDIOWAIT_TIMEOUT; + goto errout; + } + + /* Start the watchdog timer */ + + delay = MSEC2TICK(timeout); + ret = wd_start(priv->waitwdog, delay, (wdentry_t)lpc54_eventtimeout, + 1, (uint32_t)priv); + if (ret != OK) + { + mcerr("ERROR: wd_start failed: %d\n", ret); + } + } + + /* Loop until the event (or the timeout occurs). Race conditions are avoided + * by calling lpc54_waitenable prior to triggering the logic that will cause + * the wait to terminate. Under certain race conditions, the waited-for + * may have already occurred before this function was called! + */ + + for (; ; ) + { + /* Wait for an event in event set to occur. If this the event has already + * occurred, then the semaphore will already have been incremented and + * there will be no wait. + */ + + lpc54_takesem(priv); + wkupevent = priv->wkupevent; + + /* Check if the event has occurred. When the event has occurred, then + * evenset will be set to 0 and wkupevent will be set to a nonzero value. + */ + + if (wkupevent != 0) + { + /* Yes... break out of the loop with wkupevent non-zero */ + + break; + } + } + + /* Disable all transfer- and event- related interrupts */ + + lpc54_disable_allints(priv); + +errout: + leave_critical_section(flags); + mcinfo("wkupevent=%04x\n", wkupevent); + return wkupevent; +} + +/**************************************************************************** + * Name: lpc54_callbackenable + * + * Description: + * Enable/disable of a set of SD card callback events. This is part of the + * the SD card callback sequence. The set of events is configured to enabled + * callbacks to the function provided in lpc54_registercallback. + * + * Events are automatically disabled once the callback is performed and no + * further callback events will occur until they are again enabled by + * calling this methos. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * eventset - A bitset of events to enable or disable (see SDIOMEDIA_* + * definitions). 0=disable; 1=enable. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_callbackenable(FAR struct sdio_dev_s *dev, + sdio_eventset_t eventset) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev; + + mcinfo("eventset: %02x\n", eventset); + DEBUGASSERT(priv != NULL); + + priv->cbevents = eventset; + lpc54_callback(priv); +} + +/**************************************************************************** + * Name: lpc54_registercallback + * + * Description: + * Register a callback that that will be invoked on any media status + * change. Callbacks should not be made from interrupt handlers, rather + * interrupt level events should be handled by calling back on the work + * thread. + * + * When this method is called, all callbacks should be disabled until they + * are enabled via a call to SDCARD_CALLBACKENABLE + * + * Input Parameters: + * dev - Device-specific state data + * callback - The funtion to call on the media change + * arg - A caller provided value to return with the callback + * + * Returned Value: + * 0 on success; negated errno on failure. + * + ****************************************************************************/ + +static int lpc54_registercallback(FAR struct sdio_dev_s *dev, + worker_t callback, void *arg) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev; + + mcinfo("callback=%p arg=%p\n", callback, arg); + + /* Disable callbacks and register this callback and its argument */ + + mcinfo("Register %p(%p)\n", callback, arg); + DEBUGASSERT(priv != NULL); + + priv->cbevents = 0; + priv->cbarg = arg; + priv->callback = callback; + return OK; +} + +/**************************************************************************** + * Name: lpc54_dmarecvsetup + * + * Description: + * Setup to perform a read DMA. If the processor supports a data cache, + * then this method will also make sure that the contents of the DMA memory + * and the data cache are coherent. For read transfers this may mean + * invalidating the data cache. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * buffer - The memory to DMA from + * buflen - The size of the DMA transfer in bytes + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_LPC54_SDMMC_DMA +static int lpc54_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, + size_t buflen) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev; + uint32_t regval; + uint32_t ctrl; + uint32_t maxs; + int i; + + /* Don't bother with DMA if the entire transfer will fit in the RX FIFO or + * if we do not have a 4-bit wide bus. + */ + + DEBUGASSERT(priv != NULL); + + if (buflen <= LPC54_RXFIFO_SIZE || !priv->widebus) + { + return lpc54_recvsetup(dev, buffer, buflen); + } + + mcinfo("buflen=%lu\n", (unsigned long)buflen); + DEBUGASSERT(buffer != NULL && buflen > 0 && ((uint32_t)buffer & 3) == 0); + + /* Reset DMA controller internal registers. The SWR bit automatically + * clears in one clock cycle. + */ + + lpc54_putreg(SDMMC_BMOD_SWR, LPC54_SDMMC_BMOD); + + /* Save the destination buffer information for use by the interrupt handler */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = buflen; + priv->wrdir = false; + priv->dmamode = true; + + /* Reset the FIFO and DMA */ + + regval = lpc54_getreg(LPC54_SDMMC_CTRL); + regval |= SDMMC_CTRL_FIFORESET | SDMMC_CTRL_DMARESET; + lpc54_putreg(regval, LPC54_SDMMC_CTRL); + + while ((lpc54_getreg(LPC54_SDMMC_CTRL) & SDMMC_CTRL_DMARESET) != 0) + { + } + + /* Configure the FIFO so that we will receive the DMA/FIFO requests whenever + * there more than than (FIFO_DEPTH/2) - 1 words in the FIFO. + */ + + regval = SDMMC_FIFOTH_RXWMARK(LPC54_RXFIFO_DEPTH / 2 - 1) | + SDMMC_FIFOTH_DMABURST_4XFRS; + lpc54_putreg(regval, LPC54_SDMMC_FIFOTH); + + /* Setup DMA list */ + + i = 0; + while (buflen > 0) + { + /* Limit size of the transfer to maximum buffer size */ + + maxs = buflen; + + if (maxs > MCI_DMADES1_MAXTR) + { + maxs = MCI_DMADES1_MAXTR; + } + + buflen -= maxs; + + /* Set buffer size */ + + g_sdmmc_dmadd[i].des1 = MCI_DMADES1_BS1(maxs); + + /* Setup buffer address (chained) */ + + g_sdmmc_dmadd[i].des2 = (uint32_t)priv->buffer + (i * MCI_DMADES1_MAXTR); + + /* Setup basic control */ + + ctrl = MCI_DMADES0_OWN | MCI_DMADES0_CH; + + if (i == 0) + { + ctrl |= MCI_DMADES0_FS; /* First DMA buffer */ + } + + /* No more data? Then this is the last descriptor */ + + if (buflen == 0) + { + ctrl |= MCI_DMADES0_LD; + } + else + { + ctrl |= MCI_DMADES0_DIC; + } + + /* Another descriptor is needed */ + + g_sdmmc_dmadd[i].des0 = ctrl; + g_sdmmc_dmadd[i].des3 = (uint32_t) &g_sdmmc_dmadd[i + 1]; + i++; + } + + lpc54_putreg((uint32_t)&g_sdmmc_dmadd[0], LPC54_SDMMC_DBADDR); + + /* Enable internal DMA, burst size of 4, fixed burst */ + + regval = lpc54_getreg(LPC54_SDMMC_CTRL); + regval |= SDMMC_CTRL_INTDMA; + lpc54_putreg(regval, LPC54_SDMMC_CTRL); + + regval = SDMMC_BMOD_DE | SDMMC_BMOD_PBL_4XFRS | SDMMC_BMOD_DSL(4); + lpc54_putreg(regval, LPC54_SDMMC_BMOD); + + /* Setup DMA error interrupts */ + + lpc54_config_dmaints(priv, SDCARD_DMARECV_MASK, SDCARD_DMAERROR_MASK); + return OK; +} +#endif + +/**************************************************************************** + * Name: lpc54_dmasendsetup + * + * Description: + * Setup to perform a write DMA. If the processor supports a data cache, + * then this method will also make sure that the contents of the DMA memory + * and the data cache are coherent. For write transfers, this may mean + * flushing the data cache. + * + * Input Parameters: + * dev - An instance of the SD card device interface + * buffer - The memory to DMA into + * buflen - The size of the DMA transfer in bytes + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_LPC54_SDMMC_DMA +static int lpc54_dmasendsetup(FAR struct sdio_dev_s *dev, + FAR const uint8_t *buffer, size_t buflen) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev; + uint32_t regval; + + /* Don't bother with DMA if the entire transfer will fit in the TX FIFO or + * if we do not have a 4-bit wide bus. + */ + + DEBUGASSERT(priv != NULL); + + if (buflen <= LPC54_TXFIFO_SIZE || !priv->widebus) + { + return lpc54_sendsetup(dev, buffer, buflen); + } + + mcinfo("buflen=%lu\n", (unsigned long)buflen); + DEBUGASSERT(buffer != NULL && buflen > 0 && ((uint32_t)buffer & 3) == 0); + + /* Reset DMA controller internal registers. The SWR bit automatically + * clears in one clock cycle. + */ + + lpc54_putreg(SDMMC_BMOD_SWR, LPC54_SDMMC_BMOD); + + /* Save the destination buffer information for use by the interrupt + * handler. + */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = buflen; + priv->wrdir = true; + priv->dmamode = true; + + /* Reset the FIFO and DMA */ + + regval = lpc54_getreg(LPC54_SDMMC_CTRL); + regval |= SDMMC_CTRL_FIFORESET | SDMMC_CTRL_DMARESET; + lpc54_putreg(regval, LPC54_SDMMC_CTRL); + + while ((lpc54_getreg(LPC54_SDMMC_CTRL) & SDMMC_CTRL_DMARESET) != 0) + { + } + + /* Configure the FIFO so that we will receive the DMA/FIFO requests whenever + * there are FIFO_DEPTH/2 or fewer words in the FIFO. + */ + + regval = SDMMC_FIFOTH_TXWMARK(LPC54_TXFIFO_DEPTH / 2) | + SDMMC_FIFOTH_DMABURST_4XFRS; + lpc54_putreg(regval, LPC54_SDMMC_FIFOTH); + + /* Setup DMA descriptor list */ + + g_sdmmc_dmadd[0].des0 = MCI_DMADES0_OWN | MCI_DMADES0_CH | MCI_DMADES0_LD; + g_sdmmc_dmadd[0].des1 = 512; + g_sdmmc_dmadd[0].des2 = (uint32_t)priv->buffer; + g_sdmmc_dmadd[0].des3 = (uint32_t)&g_sdmmc_dmadd[1]; + + lpc54_putreg((uint32_t) &g_sdmmc_dmadd[0], LPC54_SDMMC_DBADDR); + + /* Enable internal DMA, burst size of 4, fixed burst */ + + regval = lpc54_getreg(LPC54_SDMMC_CTRL); + regval |= SDMMC_CTRL_INTDMA; + lpc54_putreg(regval, LPC54_SDMMC_CTRL); + + regval = SDMMC_BMOD_DE | SDMMC_BMOD_PBL_4XFRS | SDMMC_BMOD_DSL(4); + lpc54_putreg(regval, LPC54_SDMMC_BMOD); + + /* Setup DMA error interrupts */ + + lpc54_config_dmaints(priv, SDCARD_DMASEND_MASK, SDCARD_DMAERROR_MASK); + return OK; +} +#endif + +/**************************************************************************** + * Name: lpc54_callback + * + * Description: + * Perform callback. + * + * Assumptions: + * This function does not execute in the context of an interrupt handler. + * It may be invoked on any user thread or scheduled on the work thread + * from an interrupt handler. + * + ****************************************************************************/ + +static void lpc54_callback(struct lpc54_dev_s *priv) +{ + /* Is a callback registered? */ + + mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", + priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus); + + if (priv->callback) + { + /* Yes.. Check for enabled callback events */ + + if ((priv->cdstatus & SDIO_STATUS_PRESENT) != 0) + { + /* Media is present. Is the media inserted event enabled? */ + + if ((priv->cbevents & SDIOMEDIA_INSERTED) == 0) + { + /* No... return without performing the callback */ + + return; + } + } + else + { + /* Media is not present. Is the media eject event enabled? */ + + if ((priv->cbevents & SDIOMEDIA_EJECTED) == 0) + { + /* No... return without performing the callback */ + + return; + } + } + + /* Perform the callback, disabling further callbacks. Of course, the + * the callback can (and probably should) re-enable callbacks. + */ + + priv->cbevents = 0; + + /* Callbacks cannot be performed in the context of an interrupt handler. + * If we are in an interrupt handler, then queue the callback to be + * performed later on the work thread. + */ + + if (up_interrupt_context()) + { + /* Yes.. queue it */ + + mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); + (void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0); + } + else + { + /* No.. then just call the callback here */ + + mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg); + priv->callback(priv->cbarg); + } + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_sdmmc_initialize + * + * Description: + * Initialize the SD/MMC peripheral for normal operation. + * + * Input Parameters: + * slotno - Not used. + * + * Returned Values: + * A reference to an SD card interface structure. NULL is returned on failures. + * + ****************************************************************************/ + +FAR struct sdio_dev_s *lpc54_sdmmc_initialize(int slotno) +{ + struct lpc54_dev_s *priv = &g_scard_dev; + irqstate_t flags; + uint32_t regval; + + mcinfo("slotno=%d\n", slotno); + flags = enter_critical_section(); + + /* Set the SD/MMMC clock source */ + + lpc54_putreg(BOARD_SDMMC_CLKSRC, LPC54_SYSCON_SDIOCLKSEL); + + /* Set up the clock divider to obtain the desired clock rate. + * NOTE: The SDIO function clock to the interface can be up to 50 MHZ. + */ + + regval = SYSCON_SDIOCLKDIV_DIV(BOARD_SDMMC_CLKDIV); + lpc54_putreg(regval, LPC54_SYSCON_SDIOCLKDIV); + lpc54_putreg(regval | SYSCON_SDIOCLKDIV_REQFLAG, LPC54_SYSCON_SDIOCLKDIV); + + /* Enable clocking to the SD/MMC peripheral */ + + lpc54_sdmmc_enableclk(); + + /* REVISIT: The delay values on the sample and drive inputs and outputs + * can be adjusted using the SDIOCLKCTRL register in the SYSCON block. + */ + + /* Initialize semaphores */ + + sem_init(&priv->waitsem, 0, 0); + + /* The waitsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + + /* Create a watchdog timer */ + + priv->waitwdog = wd_create(); + DEBUGASSERT(priv->waitwdog != NULL); + + /* Configure GPIOs for 4-bit, wide-bus operation */ + + lpc54_gpio_config(GPIO_SD_D0); +#ifndef CONFIG_SDIO_WIDTH_D1_ONLY + lpc54_gpio_config(GPIO_SD_D1); + lpc54_gpio_config(GPIO_SD_D2); + lpc54_gpio_config(GPIO_SD_D3); +#endif +#ifdef CONFIG_MMCSD_HAVE_CARDDETECT + lpc54_gpio_config(GPIO_SD_CARD_DET_N); +#endif + lpc54_gpio_config(GPIO_SD_CLK); + lpc54_gpio_config(GPIO_SD_CMD); +#ifdef CONFIG_LPC54_SDMMC_PWRCTRL + lpc54_gpio_config(GPIO_SD_POW_EN); +#endif +#ifdef CONFIG_MMCSD_HAVE_WRITEPROTECT + lpc54_gpio_config(GPIO_SD_WR_PRT); +#endif + + /* Reset the card and assure that it is in the initial, unconfigured + * state. + */ + + lpc54_reset(&priv->dev); + + leave_critical_section(flags); + return &g_scard_dev.dev; +} + +#endif /* CONFIG_LPC54_SDMMC */ diff --git a/arch/arm/src/lpc54xx/lpc54_sdmmc.h b/arch/arm/src/lpc54xx/lpc54_sdmmc.h new file mode 100644 index 0000000000000000000000000000000000000000..7eb00403c55dd833eac291f54a6e4e46f500a755 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_sdmmc.h @@ -0,0 +1,88 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/lpc54_sdmmc.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_SDMMC_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_SDMMC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include + +#include "chip.h" +#include "chip/lpc54_sdmmc.h" + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: lpc54_sdmmc_initialize + * + * Description: + * Initialize the SD/MMC peripheral for normal operation. + * + * Input Parameters: + * slotno - Not used. + * + * Returned Values: + * A reference to an SDIO interface structure. NULL is returned on failures. + * + ****************************************************************************/ + +struct lpc54_sdmmc_dev_s; /* See include/nuttx/sdio.h */ +FAR struct sdio_dev_s *lpc54_sdmmc_initialize(int slotno); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_SDMMC_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_serial.c b/arch/arm/src/lpc54xx/lpc54_serial.c new file mode 100644 index 0000000000000000000000000000000000000000..7c74dec93be5935cdb4497b6b3e5cf894f6f499f --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_serial.c @@ -0,0 +1,1528 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_serial.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "chip.h" +#include "lpc54_config.h" +#include "chip/lpc54_usart.h" +#include "lpc54_clockconfig.h" +#include "lpc54_lowputc.h" +#include "lpc54_serial.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Some sanity checks *******************************************************/ +/* Is there at least one USART enabled and configured as a RS-232 device? */ + +#ifndef HAVE_USART_DEVICE +# warning "No USARTs enabled" +#endif + +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of up_putc. + */ + +#if defined(HAVE_USART_DEVICE) && defined(USE_SERIALDRIVER) + +/* Which USART with be tty0/console and which tty1-4? The console will + * always be ttyS0. If there is no console then will use the lowest + * numbered USART. + */ + +/* First pick the console and ttys0. This could be any of USART0-5 */ + +#if defined(CONFIG_USART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* USART0 is console */ +# define TTYS0_DEV g_uart0port /* USART0 is ttyS0 */ +# define USART0_ASSIGNED 1 +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* USART1 is console */ +# define TTYS0_DEV g_uart1port /* USART1 is ttyS0 */ +# define USART1_ASSIGNED 1 +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2port /* USART2 is console */ +# define TTYS0_DEV g_uart2port /* USART2 is ttyS0 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart3port /* USART3 is console */ +# define TTYS0_DEV g_uart3port /* USART3 is ttyS0 */ +# define USART3_ASSIGNED 1 +#elif defined(CONFIG_USART4_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart4port /* USART4 is console */ +# define TTYS0_DEV g_uart4port /* USART4 is ttyS0 */ +# define USART4_ASSIGNED 1 +#elif defined(CONFIG_USART5_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart5port /* USART5 is console */ +# define TTYS5_DEV g_uart5port /* USART5 is ttyS0 */ +# define USART5_ASSIGNED 1 +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart6port /* USART6 is console */ +# define TTYS6_DEV g_uart6port /* USART6 is ttyS0 */ +# define USART6_ASSIGNED 1 +#elif defined(CONFIG_USART7_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart7port /* USART7 is console */ +# define TTYS7_DEV g_uart7port /* USART7 is ttyS0 */ +# define USART7_ASSIGNED 1 +#elif defined(CONFIG_USART8_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart8port /* USART8 is console */ +# define TTYS8_DEV g_uart8port /* USART8 is ttyS0 */ +# define USART8_ASSIGNED 1 +#elif defined(CONFIG_USART9_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart9port /* USART9 is console */ +# define TTYS9_DEV g_uart9port /* USART9 is ttyS0 */ +# define USART9_ASSIGNED 1 +#else +# undef CONSOLE_DEV /* No console */ +# if defined(HAVE_USART0) +# define TTYS0_DEV g_uart0port /* USART0 is ttyS0 */ +# define USART0_ASSIGNED 1 +# elif defined(HAVE_USART1) +# define TTYS0_DEV g_uart1port /* USART1 is ttyS0 */ +# define USART1_ASSIGNED 1 +# elif defined(HAVE_USART2) +# define TTYS0_DEV g_uart2port /* USART2 is ttyS0 */ +# define USART2_ASSIGNED 1 +# elif defined(HAVE_USART3) +# define TTYS0_DEV g_uart3port /* USART3 is ttyS0 */ +# define USART3_ASSIGNED 1 +# elif defined(HAVE_USART4) +# define TTYS0_DEV g_uart4port /* USART4 is ttyS0 */ +# define USART4_ASSIGNED 1 +# elif defined(HAVE_USART5) +# define TTYS0_DEV g_uart5port /* USART5 is ttyS0 */ +# define USART5_ASSIGNED 1 +# elif defined(HAVE_USART6) +# define TTYS0_DEV g_uart6port /* USART6 is ttyS0 */ +# define USART7_ASSIGNED 1 +# elif defined(HAVE_USART7) +# define TTYS0_DEV g_uart7port /* USART7 is ttyS0 */ +# define USART7_ASSIGNED 1 +# elif defined(HAVE_USART8) +# define TTYS0_DEV g_uart8port /* USART8 is ttyS0 */ +# define USART8_ASSIGNED 1 +# elif defined(HAVE_USART9) +# define TTYS0_DEV g_uart9port /* USART9 is ttyS0 */ +# define USART9_ASSIGNED 1 +# endif +#endif + +/* Pick ttys1. This could be any of USART0-9 excluding the console USART. */ + +#if defined(HAVE_USART0) && !defined(USART0_ASSIGNED) +# define TTYS1_DEV g_uart0port /* USART0 is ttyS1 */ +# define USART0_ASSIGNED 1 +#elif defined(HAVE_USART1) && !defined(USART1_ASSIGNED) +# define TTYS1_DEV g_uart1port /* USART1 is ttyS1 */ +# define USART1_ASSIGNED 1 +#elif defined(HAVE_USART2) && !defined(USART2_ASSIGNED) +# define TTYS1_DEV g_uart2port /* USART2 is ttyS1 */ +# define USART2_ASSIGNED 1 +#elif defined(HAVE_USART3) && !defined(USART3_ASSIGNED) +# define TTYS1_DEV g_uart3port /* USART3 is ttyS1 */ +# define USART3_ASSIGNED 1 +#elif defined(HAVE_USART4) && !defined(USART4_ASSIGNED) +# define TTYS1_DEV g_uart4port /* USART4 is ttyS1 */ +# define USART4_ASSIGNED 1 +#elif defined(HAVE_USART5) && !defined(USART5_ASSIGNED) +# define TTYS1_DEV g_uart5port /* USART5 is ttyS1 */ +# define USART5_ASSIGNED 1 +#elif defined(HAVE_USART6) && !defined(USART6_ASSIGNED) +# define TTYS1_DEV g_uart6port /* USART6 is ttyS1 */ +# define USART6_ASSIGNED 1 +#elif defined(HAVE_USART7) && !defined(USART7_ASSIGNED) +# define TTYS1_DEV g_uart7port /* USART7 is ttyS1 */ +# define USART7_ASSIGNED 1 +#elif defined(HAVE_USART8) && !defined(USART8_ASSIGNED) +# define TTYS1_DEV g_uart8port /* USART8 is ttyS1 */ +# define USART8_ASSIGNED 1 +#elif defined(HAVE_USART9) && !defined(USART9_ASSIGNED) +# define TTYS1_DEV g_uart9port /* USART9 is ttyS1 */ +# define USART9_ASSIGNED 1 +#endif + +/* Pick ttys2. This could be one of USART1-9. It can't be USART0 because + * that is either not enabled OR was already assigned as ttyS0 or ttys1. + * One of USART 1-9 could also be the console. + */ + +#if defined(HAVE_USART1) && !defined(USART1_ASSIGNED) +# define TTYS2_DEV g_uart1port /* USART1 is ttyS2 */ +# define USART1_ASSIGNED 1 +#elif defined(HAVE_USART2) && !defined(USART2_ASSIGNED) +# define TTYS2_DEV g_uart2port /* USART2 is ttyS2 */ +# define USART2_ASSIGNED 1 +#elif defined(HAVE_USART3) && !defined(USART3_ASSIGNED) +# define TTYS2_DEV g_uart3port /* USART3 is ttyS2 */ +# define USART3_ASSIGNED 1 +#elif defined(HAVE_USART4) && !defined(USART4_ASSIGNED) +# define TTYS2_DEV g_uart4port /* USART4 is ttyS2 */ +# define USART4_ASSIGNED 1 +#elif defined(HAVE_USART5) && !defined(USART5_ASSIGNED) +# define TTYS2_DEV g_uart5port /* USART5 is ttyS2 */ +# define USART5_ASSIGNED 1 +#elif defined(HAVE_USART6) && !defined(USART6_ASSIGNED) +# define TTYS2_DEV g_uart6port /* USART6 is ttyS2 */ +# define USART6_ASSIGNED 1 +#elif defined(HAVE_USART7) && !defined(USART7_ASSIGNED) +# define TTYS2_DEV g_uart7port /* USART7 is ttyS2 */ +# define USART7_ASSIGNED 1 +#elif defined(HAVE_USART8) && !defined(USART8_ASSIGNED) +# define TTYS2_DEV g_uart8port /* USART8 is ttyS2 */ +# define USART8_ASSIGNED 1 +#elif defined(HAVE_USART9) && !defined(USART9_ASSIGNED) +# define TTYS2_DEV g_uart9port /* USART9 is ttyS2 */ +# define USART9_ASSIGNED 1 +#endif + +/* Pick ttys3. This could be one of USART2-9. It can't be USART0-1 because + * those are either not enabled OR were already assigned as ttyS0, 1, or 2. + * One of USART 2-9 could also be the console. + */ + +#if defined(HAVE_USART2) && !defined(USART2_ASSIGNED) +# define TTYS3_DEV g_uart2port /* USART2 is ttyS3 */ +# define USART2_ASSIGNED 1 +#elif defined(HAVE_USART3) && !defined(USART3_ASSIGNED) +# define TTYS3_DEV g_uart3port /* USART3 is ttyS3 */ +# define USART3_ASSIGNED 1 +#elif defined(HAVE_USART4) && !defined(USART4_ASSIGNED) +# define TTYS3_DEV g_uart4port /* USART4 is ttyS3 */ +# define USART4_ASSIGNED 1 +#elif defined(HAVE_USART5) && !defined(USART5_ASSIGNED) +# define TTYS3_DEV g_uart5port /* USART5 is ttyS3 */ +# define USART5_ASSIGNED 1 +#elif defined(HAVE_USART6) && !defined(USART6_ASSIGNED) +# define TTYS3_DEV g_uart6port /* USART6 is ttyS3 */ +# define USART6_ASSIGNED 1 +#elif defined(HAVE_USART7) && !defined(USART7_ASSIGNED) +# define TTYS3_DEV g_uart7port /* USART7 is ttyS3 */ +# define USART7_ASSIGNED 1 +#elif defined(HAVE_USART8) && !defined(USART8_ASSIGNED) +# define TTYS3_DEV g_uart8port /* USART8 is ttyS3 */ +# define USART8_ASSIGNED 1 +#elif defined(HAVE_USART9) && !defined(USART9_ASSIGNED) +# define TTYS3_DEV g_uart9port /* USART9 is ttyS3 */ +# define USART9_ASSIGNED 1 +#endif + +/* Pick ttys4. This could be one of USART3-9. It can't be USART0-2 because + * those are either not enabled OR were already assigned as ttyS0-3. One + * of USART 3-9 could also be the console. + */ + +#if defined(HAVE_USART3) && !defined(USART3_ASSIGNED) +# define TTYS4_DEV g_uart3port /* USART3 is ttyS4 */ +# define USART3_ASSIGNED 1 +#elif defined(HAVE_USART4) && !defined(USART4_ASSIGNED) +# define TTYS4_DEV g_uart4port /* USART4 is ttyS4 */ +# define USART4_ASSIGNED 1 +#elif defined(HAVE_USART5) && !defined(USART5_ASSIGNED) +# define TTYS4_DEV g_uart5port /* USART5 is ttyS4 */ +# define USART5_ASSIGNED 1 +#elif defined(HAVE_USART6) && !defined(USART6_ASSIGNED) +# define TTYS4_DEV g_uart6port /* USART6 is ttyS4 */ +# define USART6_ASSIGNED 1 +#elif defined(HAVE_USART7) && !defined(USART7_ASSIGNED) +# define TTYS4_DEV g_uart7port /* USART7 is ttyS4 */ +# define USART7_ASSIGNED 1 +#elif defined(HAVE_USART8) && !defined(USART8_ASSIGNED) +# define TTYS4_DEV g_uart8port /* USART8 is ttyS4 */ +# define USART8_ASSIGNED 1 +#elif defined(HAVE_USART9) && !defined(USART9_ASSIGNED) +# define TTYS4_DEV g_uart9port /* USART9 is ttyS4 */ +# define USART9_ASSIGNED 1 +#endif + +/* Pick ttys5. This could be one of USART4-9. It can't be USART0-3 because + * those are either not enabled OR were already assigned as ttyS0-4. One + * of USART4-9 could also be the console. + */ + +#if defined(HAVE_USART4) && !defined(USART4_ASSIGNED) +# define TTYS5_DEV g_uart4port /* USART4 is ttyS5 */ +# define USART4_ASSIGNED 1 +#elif defined(HAVE_USART5) && !defined(USART5_ASSIGNED) +# define TTYS5_DEV g_uart5port /* USART5 is ttyS5 */ +# define USART5_ASSIGNED 1 +#elif defined(HAVE_USART6) && !defined(USART6_ASSIGNED) +# define TTYS5_DEV g_uart6port /* USART6 is ttyS5 */ +# define USART6_ASSIGNED 1 +#elif defined(HAVE_USART7) && !defined(USART7_ASSIGNED) +# define TTYS5_DEV g_uart7port /* USART7 is ttyS5 */ +# define USART7_ASSIGNED 1 +#elif defined(HAVE_USART8) && !defined(USART8_ASSIGNED) +# define TTYS5_DEV g_uart8port /* USART8 is ttyS5 */ +# define USART8_ASSIGNED 1 +#elif defined(HAVE_USART9) && !defined(USART9_ASSIGNED) +# define TTYS5_DEV g_uart9port /* USART9 is ttyS5 */ +# define USART9_ASSIGNED 1 +#endif + +/* Pick ttys6. This could be one of USART5-9. It can't be USART0-4 because + * those are either not enabled OR were already assigned as ttyS0-5. One + * of USART5-9 could also be the console. + */ + +#if defined(HAVE_USART5) && !defined(USART5_ASSIGNED) +# define TTYS6_DEV g_uart5port /* USART5 is ttyS6 */ +# define USART5_ASSIGNED 1 +#elif defined(HAVE_USART6) && !defined(USART6_ASSIGNED) +# define TTYS6_DEV g_uart6port /* USART6 is ttyS6 */ +# define USART6_ASSIGNED 1 +#elif defined(HAVE_USART7) && !defined(USART7_ASSIGNED) +# define TTYS6_DEV g_uart7port /* USART7 is ttyS6 */ +# define USART7_ASSIGNED 1 +#elif defined(HAVE_USART8) && !defined(USART8_ASSIGNED) +# define TTYS6_DEV g_uart8port /* USART8 is ttyS6 */ +# define USART8_ASSIGNED 1 +#elif defined(HAVE_USART9) && !defined(USART9_ASSIGNED) +# define TTYS6_DEV g_uart9port /* USART9 is ttyS6 */ +# define USART9_ASSIGNED 1 +#endif + +/* Pick ttys7. This could be one of USART6-9. It can't be USART0-5 because + * those are either not enabled OR were already assigned as ttyS0-6. One + * of USART6-9 could also be the console. + */ + +#if defined(HAVE_USART6) && !defined(USART6_ASSIGNED) +# define TTYS7_DEV g_uart6port /* USART6 is ttyS7 */ +# define USART6_ASSIGNED 1 +#elif defined(HAVE_USART7) && !defined(USART7_ASSIGNED) +# define TTYS7_DEV g_uart7port /* USART7 is ttyS7 */ +# define USART7_ASSIGNED 1 +#elif defined(HAVE_USART8) && !defined(USART8_ASSIGNED) +# define TTYS7_DEV g_uart8port /* USART8 is ttyS7 */ +# define USART8_ASSIGNED 1 +#elif defined(HAVE_USART9) && !defined(USART9_ASSIGNED) +# define TTYS7_DEV g_uart9port /* USART9 is ttyS7 */ +# define USART9_ASSIGNED 1 +#endif + +/* Pick ttys8. This could be one of USART7-9. It can't be USART0-6 because + * those are either not enabled OR were already assigned as ttyS0-7. One + * of USART7-9 could also be the console. + */ + +#if defined(HAVE_USART7) && !defined(USART7_ASSIGNED) +# define TTYS8_DEV g_uart7port /* USART7 is ttyS8 */ +# define USART7_ASSIGNED 1 +#elif defined(HAVE_USART8) && !defined(USART8_ASSIGNED) +# define TTYS8_DEV g_uart8port /* USART8 is ttyS8 */ +# define USART8_ASSIGNED 1 +#elif defined(HAVE_USART9) && !defined(USART9_ASSIGNED) +# define TTYS8_DEV g_uart9port /* USART9 is ttyS8 */ +# define USART9_ASSIGNED 1 +#endif + +/* Event sets */ + +#define CCR_RX_EVENTS (USART_FIFOINT_RXLVL | USART_FIFOINT_RXERR) +#define CCR_TX_EVENTS (USART_FIFOINT_TXLVL | USART_FIFOINT_TXERR) +#define CCR_ERROR_EVENTS (USART_FIFOINT_RXERR | USART_FIFOINT_TXERR | \ + USART_FIFOINTSTAT_PERINT) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure provides the state of one USART device */ + +struct lpc54_dev_s +{ + uintptr_t uartbase; /* Base address of USART registers */ + uint8_t irq; /* IRQ associated with this USART */ + + /* USART configuration */ + + struct uart_config_s config; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int lpc54_setup(struct uart_dev_s *dev); +static void lpc54_shutdown(struct uart_dev_s *dev); +static int lpc54_attach(struct uart_dev_s *dev); +static void lpc54_detach(struct uart_dev_s *dev); +static int lpc54_interrupt(int irq, void *context, FAR void *arg); +static int lpc54_ioctl(struct file *filep, int cmd, unsigned long arg); +static int lpc54_receive(struct uart_dev_s *dev, uint32_t *status); +static void lpc54_rxint(struct uart_dev_s *dev, bool enable); +static bool lpc54_rxavailable(struct uart_dev_s *dev); +static void lpc54_send(struct uart_dev_s *dev, int ch); +static void lpc54_txint(struct uart_dev_s *dev, bool enable); +static bool lpc54_txready(struct uart_dev_s *dev); +static bool lpc54_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = lpc54_setup, + .shutdown = lpc54_shutdown, + .attach = lpc54_attach, + .detach = lpc54_detach, + .ioctl = lpc54_ioctl, + .receive = lpc54_receive, + .rxint = lpc54_rxint, + .rxavailable = lpc54_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = lpc54_send, + .txint = lpc54_txint, + .txready = lpc54_txready, + .txempty = lpc54_txempty, +}; + +/* I/O buffers */ + +#ifdef HAVE_USART0 +static char g_uart0rxbuffer[CONFIG_USART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_USART0_TXBUFSIZE]; +#endif +#ifdef HAVE_USART1 +static char g_uart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_USART1_TXBUFSIZE]; +#endif +#ifdef HAVE_USART2 +static char g_uart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_USART2_TXBUFSIZE]; +#endif +#ifdef HAVE_USART3 +static char g_uart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; +static char g_uart3txbuffer[CONFIG_USART3_TXBUFSIZE]; +#endif +#ifdef HAVE_USART4 +static char g_uart4rxbuffer[CONFIG_USART4_RXBUFSIZE]; +static char g_uart4txbuffer[CONFIG_USART4_TXBUFSIZE]; +#endif +#ifdef HAVE_USART5 +static char g_uart5rxbuffer[CONFIG_USART5_RXBUFSIZE]; +static char g_uart5txbuffer[CONFIG_USART5_TXBUFSIZE]; +#endif + +/* This describes the state of the LPC54xx USART0 port. */ + +#ifdef HAVE_USART0 +static struct lpc54_dev_s g_uart0priv = +{ + .uartbase = LPC54_FLEXCOMM0_BASE, + .irq = LPC54_IRQ_FLEXCOMM0, + .config = + { + .baud = CONFIG_USART0_BAUD, + .fclk = BOARD_FLEXCOMM0_FCLK, + .parity = CONFIG_USART0_PARITY, + .bits = CONFIG_USART0_BITS, + .txlevel = LPC54_USART_FIFO_DEPTH / 2, + .rxlevel = 0, + .stopbits2 = CONFIG_USART0_2STOP, +#ifdef CONFIG_USART0_IFLOWCONTROL + .iflow = true, +#endif +#ifdef CONFIG_USART0_OFLOWCONTROL + .oflow = true, +#endif + } +}; + +static uart_dev_t g_uart0port = +{ + .recv = + { + .size = CONFIG_USART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +/* This describes the state of the LPC54xx USART1 port. */ + +#ifdef HAVE_USART1 +static struct lpc54_dev_s g_uart1priv = +{ + .uartbase = LPC54_FLEXCOMM1_BASE, + .irq = LPC54_IRQ_FLEXCOMM1, + .config = + { + .baud = CONFIG_USART1_BAUD, + .fclk = BOARD_FLEXCOMM1_FCLK, + .parity = CONFIG_USART1_PARITY, + .bits = CONFIG_USART1_BITS, + .txlevel = LPC54_USART_FIFO_DEPTH / 2, + .rxlevel = 0, + .stopbits2 = CONFIG_USART1_2STOP, +#ifdef CONFIG_USART1_IFLOWCONTROL + .iflow = true, +#endif +#ifdef CONFIG_USART1_OFLOWCONTROL + .oflow = true, +#endif + } +}; + +static uart_dev_t g_uart1port = +{ + .recv = + { + .size = CONFIG_USART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +/* This describes the state of the LPC54xx USART2 port. */ + +#ifdef HAVE_USART2 +static struct lpc54_dev_s g_uart2priv = +{ + .uartbase = LPC54_FLEXCOMM2_BASE, + .irq = LPC54_IRQ_FLEXCOMM2, + .config = + { + .baud = CONFIG_USART2_BAUD, + .fclk = BOARD_FLEXCOMM2_FCLK, + .parity = CONFIG_USART2_PARITY, + .bits = CONFIG_USART2_BITS, + .txlevel = LPC54_USART_FIFO_DEPTH / 2, + .rxlevel = 0, + .stopbits2 = CONFIG_USART2_2STOP, +#ifdef CONFIG_USART2_IFLOWCONTROL + .iflow = true, +#endif +#ifdef CONFIG_USART2_OFLOWCONTROL + .oflow = true, +#endif + } +}; + +static uart_dev_t g_uart2port = +{ + .recv = + { + .size = CONFIG_USART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; +#endif + +/* This describes the state of the LPC54xx USART3 port. */ + +#ifdef HAVE_USART3 +static struct lpc54_dev_s g_uart3priv = +{ + .uartbase = LPC54_FLEXCOMM3_BASE, + .irq = LPC54_IRQ_FLEXCOMM3, + .config = + { + .baud = CONFIG_USART3_BAUD, + .fclk = BOARD_FLEXCOMM3_FCLK, + .parity = CONFIG_USART3_PARITY, + .bits = CONFIG_USART3_BITS, + .txlevel = LPC54_USART_FIFO_DEPTH / 2, + .rxlevel = 0, + .stopbits2 = CONFIG_USART3_2STOP, +#ifdef CONFIG_USART3_IFLOWCONTROL + .iflow = true, +#endif +#ifdef CONFIG_USART3_OFLOWCONTROL + .oflow = true, +#endif + } +}; + +static uart_dev_t g_uart3port = +{ + .recv = + { + .size = CONFIG_USART3_RXBUFSIZE, + .buffer = g_uart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART3_TXBUFSIZE, + .buffer = g_uart3txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart3priv, +}; +#endif + +/* This describes the state of the LPC54xx USART4 port. */ + +#ifdef HAVE_USART4 +static struct lpc54_dev_s g_uart4priv = +{ + .uartbase = LPC54_FLEXCOMM4_BASE, + .irq = LPC54_IRQ_FLEXCOMM4, + .config = + { + .baud = CONFIG_USART4_BAUD, + .fclk = BOARD_FLEXCOMM4_FCLK, + .parity = CONFIG_USART4_PARITY, + .bits = CONFIG_USART4_BITS, + .txlevel = LPC54_USART_FIFO_DEPTH / 2, + .rxlevel = 0, + .stopbits2 = CONFIG_USART4_2STOP, +#ifdef CONFIG_USART4_IFLOWCONTROL + .iflow = true, +#endif +#ifdef CONFIG_USART4_OFLOWCONTROL + .oflow = true, +#endif + } +}; + +static uart_dev_t g_uart4port = +{ + .recv = + { + .size = CONFIG_USART4_RXBUFSIZE, + .buffer = g_uart4rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART4_TXBUFSIZE, + .buffer = g_uart4txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart4priv, +}; +#endif + +/* This describes the state of the LPC54xx USART5 port. */ + +#ifdef HAVE_USART5 +static struct lpc54_dev_s g_uart5priv = +{ + .uartbase = LPC54_FLEXCOMM5_BASE, + .irq = LPC54_IRQ_FLEXCOMM5, + .config = + { + .baud = CONFIG_USART5_BAUD, + .fclk = BOARD_FLEXCOMM5_FCLK, + .parity = CONFIG_USART5_PARITY, + .bits = CONFIG_USART5_BITS, + .txlevel = LPC54_USART_FIFO_DEPTH / 2, + .rxlevel = 0, + .stopbits2 = CONFIG_USART5_2STOP, +#ifdef CONFIG_USART5_IFLOWCONTROL + .iflow = true, +#endif +#ifdef CONFIG_USART5_OFLOWCONTROL + .oflow = true, +#endif + } +}; + +static uart_dev_t g_uart5port = +{ + .recv = + { + .size = CONFIG_USART5_RXBUFSIZE, + .buffer = g_uart5rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART5_TXBUFSIZE, + .buffer = g_uart5txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart5priv, +}; +#endif + +/* This describes the state of the LPC54xx USART6 port. */ + +#ifdef HAVE_USART6 +static struct lpc54_dev_s g_uart6priv = +{ + .uartbase = LPC54_FLEXCOMM6_BASE, + .irq = LPC54_IRQ_FLEXCOMM6, + .config = + { + .baud = CONFIG_USART6_BAUD, + .fclk = BOARD_FLEXCOMM6_FCLK, + .parity = CONFIG_USART6_PARITY, + .bits = CONFIG_USART6_BITS, + .txlevel = LPC54_USART_FIFO_DEPTH / 2, + .rxlevel = 0, + .stopbits2 = CONFIG_USART6_2STOP, +#ifdef CONFIG_USART6_IFLOWCONTROL + .iflow = true, +#endif +#ifdef CONFIG_USART6_OFLOWCONTROL + .oflow = true, +#endif + } +}; + +static uart_dev_t g_uart6port = +{ + .recv = + { + .size = CONFIG_USART6_RXBUFSIZE, + .buffer = g_uart6rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART6_TXBUFSIZE, + .buffer = g_uart6txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart6priv, +}; +#endif + +/* This describes the state of the LPC54xx USART7 port. */ + +#ifdef HAVE_USART7 +static struct lpc54_dev_s g_uart7priv = +{ + .uartbase = LPC54_FLEXCOMM7_BASE, + .irq = LPC54_IRQ_FLEXCOMM7, + .config = + { + .baud = CONFIG_USART7_BAUD, + .fclk = BOARD_FLEXCOMM7_FCLK, + .parity = CONFIG_USART7_PARITY, + .bits = CONFIG_USART7_BITS, + .txlevel = LPC54_USART_FIFO_DEPTH / 2, + .rxlevel = 0, + .stopbits2 = CONFIG_USART7_2STOP, +#ifdef CONFIG_USART7_IFLOWCONTROL + .iflow = true, +#endif +#ifdef CONFIG_USART7_OFLOWCONTROL + .oflow = true, +#endif + } +}; + +static uart_dev_t g_uart7port = +{ + .recv = + { + .size = CONFIG_USART7_RXBUFSIZE, + .buffer = g_uart7rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART7_TXBUFSIZE, + .buffer = g_uart7txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart7priv, +}; +#endif + +/* This describes the state of the LPC54xx USART8 port. */ + +#ifdef HAVE_USART8 +static struct lpc54_dev_s g_uart8priv = +{ + .uartbase = LPC54_FLEXCOMM8_BASE, + .irq = LPC54_IRQ_FLEXCOMM8, + .config = + { + .baud = CONFIG_USART8_BAUD, + .fclk = BOARD_FLEXCOMM8_FCLK, + .parity = CONFIG_USART8_PARITY, + .bits = CONFIG_USART8_BITS, + .txlevel = LPC54_USART_FIFO_DEPTH / 2, + .rxlevel = 0, + .stopbits2 = CONFIG_USART8_2STOP, +#ifdef CONFIG_USART8_IFLOWCONTROL + .iflow = true, +#endif +#ifdef CONFIG_USART8_OFLOWCONTROL + .oflow = true, +#endif + } +}; + +static uart_dev_t g_uart8port = +{ + .recv = + { + .size = CONFIG_USART8_RXBUFSIZE, + .buffer = g_uart8rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART8_TXBUFSIZE, + .buffer = g_uart8txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart8priv, +}; +#endif + +/* This describes the state of the LPC54xx USART9 port. */ + +#ifdef HAVE_USART9 +static struct lpc54_dev_s g_uart9priv = +{ + .uartbase = LPC54_FLEXCOMM9_BASE, + .irq = LPC54_IRQ_FLEXCOMM9, + .config = + { + .baud = CONFIG_USART9_BAUD, + .fclk = BOARD_FLEXCOMM9_FCLK, + .parity = CONFIG_USART9_PARITY, + .bits = CONFIG_USART9_BITS, + .txlevel = LPC54_USART_FIFO_DEPTH / 2, + .rxlevel = 0, + .stopbits2 = CONFIG_USART9_2STOP, +#ifdef CONFIG_USART9_IFLOWCONTROL + .iflow = true, +#endif +#ifdef CONFIG_USART9_OFLOWCONTROL + .oflow = true, +#endif + } +}; + +static uart_dev_t g_uart9port = +{ + .recv = + { + .size = CONFIG_USART9_RXBUFSIZE, + .buffer = g_uart9rxbuffer, + }, + .xmit = + { + .size = CONFIG_USART9_TXBUFSIZE, + .buffer = g_uart9txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart9priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_serialin + ****************************************************************************/ + +static inline uint32_t lpc54_serialin(struct lpc54_dev_s *priv, + unsigned int offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: lpc54_serialout + ****************************************************************************/ + +static inline void lpc54_serialout(struct lpc54_dev_s *priv, + unsigned int offset, uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: lpc54_modifyreg + ****************************************************************************/ + +static inline void lpc54_modifyreg(struct lpc54_dev_s *priv, unsigned int offset, + uint32_t setbits, uint32_t clrbits) +{ + irqstate_t flags; + uintptr_t regaddr = priv->uartbase + offset; + uint32_t regval; + + flags = enter_critical_section(); + + regval = getreg32(regaddr); + regval &= ~clrbits; + regval |= setbits; + putreg32(regval, regaddr); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: lpc54_fifoint_enable + ****************************************************************************/ + +static inline void lpc54_fifoint_enable(struct lpc54_dev_s *priv, uint32_t intset) +{ + lpc54_serialout(priv, LPC54_USART_FIFOINTENSET_OFFSET, intset); +} + +/**************************************************************************** + * Name: lpc54_fifoint_disable + ****************************************************************************/ + +static inline void lpc54_fifoint_disable(struct lpc54_dev_s *priv, uint32_t intset) +{ + lpc54_serialout(priv, LPC54_USART_FIFOINTENCLR_OFFSET, intset); +} + +/**************************************************************************** + * Name: lpc54_fifoint_disableall + ****************************************************************************/ + +static void lpc54_fifoint_disableall(struct lpc54_dev_s *priv, uint32_t *intset) +{ + irqstate_t flags; + + flags = enter_critical_section(); + if (intset) + { + *intset = lpc54_serialin(priv, LPC54_USART_FIFOINTENCLR_OFFSET); + } + + lpc54_serialout(priv, LPC54_USART_FIFOINTENCLR_OFFSET, USART_FIFOINT_ALL); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: lpc54_setup + * + * Description: + * Configure the USART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int lpc54_setup(struct uart_dev_s *dev) +{ +#ifndef CONFIG_SUPPRESS_USART_CONFIG + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev->priv; + + /* Configure the USART as an RS-232 USART */ + + lpc54_usart_configure(priv->uartbase, &priv->config); +#endif + + /* Make sure that all interrupts are disabled */ + + lpc54_fifoint_disableall(priv, NULL); + return OK; +} + +/**************************************************************************** + * Name: lpc54_shutdown + * + * Description: + * Disable the USART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void lpc54_shutdown(struct uart_dev_s *dev) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev->priv; + + /* Disable interrupts */ + + lpc54_fifoint_disableall(priv, NULL); + + /* Reset hardware and disable Rx and Tx */ + + lpc54_usart_disable(priv->uartbase); +} + +/**************************************************************************** + * Name: lpc54_attach + * + * Description: + * Configure the USART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() methods are called. + * + ****************************************************************************/ + +static int lpc54_attach(struct uart_dev_s *dev) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev->priv; + int ret; + + /* Attach and enable the IRQ(s). The interrupts are (probably) still + * disabled in the C2 register. + */ + + ret = irq_attach(priv->irq, lpc54_interrupt, dev); + if (ret == OK) + { + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: lpc54_detach + * + * Description: + * Detach USART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void lpc54_detach(struct uart_dev_s *dev) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev->priv; + + /* Disable interrupts */ + + lpc54_fifoint_disableall(priv, NULL); + up_disable_irq(priv->irq); + + /* Detach from the interrupt(s) */ + + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: lpc54_interrupt + * + * Description: + * This is the USART status interrupt handler. It will be invoked when an + * interrupt received on the 'irq' It should call uart_transmitchars or + * uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * approprite uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int lpc54_interrupt(int irq, void *context, FAR void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct lpc54_dev_s *priv; + int passes; + uint32_t regval; + bool handled; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct lpc54_dev_s *)dev->priv; + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + handled = true; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = false; + + /* Read and clear FIFO interrupt status */ + + regval = lpc54_serialin(priv, LPC54_USART_FIFOINTSTAT_OFFSET); + lpc54_serialout(priv, LPC54_USART_FIFOINTSTAT_OFFSET, regval); + + /* Handle incoming, receive bytes. + * Check if the received FIFO is not empty. + */ + + if ((regval & USART_FIFOINT_RXLVL) != 0) + { + /* Process incoming bytes */ + + uart_recvchars(dev); + handled = true; + } + + /* Handle outgoing, transmit bytes. + * Check if the received FIFO is not full. + */ + + if ((regval & USART_FIFOINT_TXLVL) != 0) + { + /* Process outgoing bytes */ + + uart_xmitchars(dev); + handled = true; + } + +#ifdef CONFIG_DEBUG_FEATURES + /* Check for error conditions */ + + if ((regval & CCR_ERROR_EVENTS) != 0) + { + /* And now do... what? Should we reset FIFOs on a FIFO error? */ +#warning Misssing logic + } +#endif + } + + return OK; +} + +/**************************************************************************** + * Name: lpc54_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int lpc54_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#if 0 /* Reserved for future growth */ + struct inode *inode; + struct uart_dev_s *dev; + struct lpc54_dev_s *priv; + int ret = OK; + + DEBUGASSERT(filep, filep->f_inode); + inode = filep->f_inode; + dev = inode->i_private; + + DEBUGASSERT(dev, dev->priv); + priv = (struct lpc54_dev_s *)dev->priv; + + switch (cmd) + { + case xxx: /* Add commands here */ + break; + + default: + ret = -ENOTTY; + break; + } + + return ret; +#else + return -ENOTTY; +#endif +} + +/**************************************************************************** + * Name: lpc54_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the USART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int lpc54_receive(struct uart_dev_s *dev, uint32_t *status) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev->priv; + uint32_t fiford; + + /* Get input data along with receiver control information */ + + fiford = lpc54_serialin(priv, LPC54_USART_FIFORD_OFFSET); + + /* Return receiver control information */ + + if (status) + { + *status = fiford && ~USART_FIFORD_RXDATA_MASK; + } + + /* Then return the actual received data. */ + + return fiford & USART_FIFORD_RXDATA_MASK; +} + +/**************************************************************************** + * Name: lpc54_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void lpc54_rxint(struct uart_dev_s *dev, bool enable) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev->priv; + + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + /* Receive an interrupt when their is anything in the Rx data register (or an Rx + * timeout occurs). + */ + + lpc54_fifoint_enable(priv, CCR_RX_EVENTS); +#endif + } + else + { + lpc54_fifoint_disable(priv, CCR_RX_EVENTS); + } +} + +/**************************************************************************** + * Name: lpc54_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +static bool lpc54_rxavailable(struct uart_dev_s *dev) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev->priv; + uint32_t regval; + + /* Return true if the receive buffer/fifo is not "empty." */ + + regval = lpc54_serialin(priv, LPC54_USART_FIFOSTAT_OFFSET); + return ((regval & USART_FIFOSTAT_RXNOTEMPTY) != 0); +} + +/**************************************************************************** + * Name: lpc54_send + * + * Description: + * This method will send one byte on the USART. + * + ****************************************************************************/ + +static void lpc54_send(struct uart_dev_s *dev, int ch) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev->priv; + lpc54_serialout(priv, LPC54_USART_FIFOWR_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: lpc54_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void lpc54_txint(struct uart_dev_s *dev, bool enable) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev->priv; + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + irqstate_t flags; + + /* Enable the TX interrupt */ + + flags = enter_critical_section(); + lpc54_fifoint_enable(priv, CCR_TX_EVENTS); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); + leave_critical_section(flags); +#endif + } + else + { + /* Disable the TX interrupt */ + + lpc54_fifoint_disable(priv, CCR_TX_EVENTS); + } +} + +/**************************************************************************** + * Name: lpc54_txready + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool lpc54_txready(struct uart_dev_s *dev) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev->priv; + uint32_t regval; + + /* Return true if the transmit FIFO is "not full." */ + + regval = lpc54_serialin(priv, LPC54_USART_FIFOSTAT_OFFSET); + return ((regval & USART_FIFOSTAT_TXNOTFULL) != 0); +} + +/**************************************************************************** + * Name: lpc54_txempty + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool lpc54_txempty(struct uart_dev_s *dev) +{ + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)dev->priv; + uint32_t regval; + + /* Return true if the transmit FIFO is "empty." */ + + regval = lpc54_serialin(priv, LPC54_USART_FIFOSTAT_OFFSET); + return ((regval & USART_FIFOSTAT_TXEMPTY) != 0); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_earlyserialinit + * + * Description: + * Performs the low level USART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before lpc54_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in xmc_lowsetup() and main clock iniialization + * performed in xmc_clock_configure(). + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void lpc54_earlyserialinit(void) +{ + /* Disable interrupts from all USARTS. The console is enabled in + * pic32mx_consoleinit() + */ + + lpc54_fifoint_disableall(TTYS0_DEV.priv, NULL); +#ifdef TTYS1_DEV + lpc54_fifoint_disableall(TTYS1_DEV.priv, NULL); +#endif +#ifdef TTYS2_DEV + lpc54_fifoint_disableall(TTYS2_DEV.priv, NULL); +#endif +#ifdef TTYS3_DEV + lpc54_fifoint_disableall(TTYS3_DEV.priv, NULL); +#endif +#ifdef TTYS4_DEV + lpc54_fifoint_disableall(TTYS4_DEV.priv, NULL); +#endif +#ifdef TTYS5_DEV + lpc54_fifoint_disableall(TTYS5_DEV.priv, NULL); +#endif +#ifdef TTYS6_DEV + lpc54_fifoint_disableall(TTYS6_DEV.priv, NULL); +#endif +#ifdef TTYS7_DEV + lpc54_fifoint_disableall(TTYS7_DEV.priv, NULL); +#endif +#ifdef TTYS8_DEV + lpc54_fifoint_disableall(TTYS8_DEV.priv, NULL); +#endif +#ifdef TTYS9_DEV + lpc54_fifoint_disableall(TTYS9_DEV.priv, NULL); +#endif + + /* Configuration whichever one is the console */ + +#ifdef HAVE_USART_CONSOLE + CONSOLE_DEV.isconsole = true; + lpc54_setup(&CONSOLE_DEV); +#endif +} +#endif + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that lpc54_earlyserialinit was called previously. + * + * Input Parameters: + * None + * + * Returns Value: + * None + * + ****************************************************************************/ + +void up_serialinit(void) +{ +#ifdef HAVE_USART_CONSOLE + /* Register the serial console */ + + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all USARTs */ + + (void)uart_register("/dev/ttyS0", &TTYS0_DEV); +#ifdef TTYS1_DEV + (void)uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +#ifdef TTYS2_DEV + (void)uart_register("/dev/ttyS2", &TTYS2_DEV); +#endif +#ifdef TTYS3_DEV + (void)uart_register("/dev/ttyS3", &TTYS3_DEV); +#endif +#ifdef TTYS4_DEV + (void)uart_register("/dev/ttyS4", &TTYS4_DEV); +#endif +#ifdef TTYS5_DEV + (void)uart_register("/dev/ttyS5", &TTYS5_DEV); +#endif +#ifdef TTYS6_DEV + (void)uart_register("/dev/ttyS6", &TTYS6_DEV); +#endif +#ifdef TTYS7_DEV + (void)uart_register("/dev/ttyS7", &TTYS7_DEV); +#endif +#ifdef TTYS8_DEV + (void)uart_register("/dev/ttyS8", &TTYS8_DEV); +#endif +#ifdef TTYS9_DEV + (void)uart_register("/dev/ttyS9", &TTYS9_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_USART_CONSOLE + struct lpc54_dev_s *priv = (struct lpc54_dev_s *)CONSOLE_DEV.priv; + uint32_t intset; + + lpc54_fifoint_disableall(priv, &intset); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); + lpc54_fifoint_enable(priv, intset); +#endif + + return ch; +} + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_USART_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); + return ch; +} +#endif + +#endif /* HAVE_USART_DEVICE && USE_SERIALDRIVER */ diff --git a/arch/arm/src/lpc54xx/lpc54_serial.h b/arch/arm/src/lpc54xx/lpc54_serial.h new file mode 100644 index 0000000000000000000000000000000000000000..44cac56f5a5fc5529016d5173461eecaa6ea268c --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_serial.h @@ -0,0 +1,66 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_serial.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_SERIAL_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_SERIAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "lpc54_config.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_earlyserialinit + * + * Description: + * Performs the low level USART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before lpc54_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in xmc_lowsetup() and main clock iniialization + * performed in xmc_clock_configure(). + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void lpc54_earlyserialinit(void); +#endif + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_SERIAL_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_spi_master.c b/arch/arm/src/lpc54xx/lpc54_spi_master.c new file mode 100644 index 0000000000000000000000000000000000000000..665c1a4242dd8e244fbf76077209dfe8f64d5bd6 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_spi_master.c @@ -0,0 +1,1040 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_spi.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip/lpc54_pinmux.h" +#include "chip/lpc54_syscon.h" +#include "chip/lpc54_flexcomm.h" +#include "chip/lpc54_spi.h" +#include "lpc54_config.h" +#include "lpc54_enableclk.h" +#include "lpc54_spi_master.h" + +#ifdef HAVE_SPI_MASTER_DEVICE + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure descibes the state of the SSP driver */ + +struct lpc54_spidev_s +{ + struct spi_dev_s dev; /* Externally visible part of the SPI interface */ + uintptr_t base; /* Base address of Flexcomm registers */ + sem_t exclsem; /* Held while chip is selected for mutual exclusion */ + uint32_t fclock; /* Flexcomm function clock frequency */ + uint32_t frequency; /* Requested clock frequency */ + uint32_t actual; /* Actual clock frequency */ + uint16_t irq; /* Flexcomm IRQ number */ + uint8_t nbits; /* Width of word in bits (8 to 16) */ + uint8_t mode; /* Mode 0,1,2,3 */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline bool lpc54_spi_16bitmode(FAR struct lpc54_spidev_s *priv); + +/* SPI methods */ + +static int lpc54_spi_lock(FAR struct spi_dev_s *dev, bool lock); +static void lpc54_spi_select(FAR struct spi_dev_s *dev, uint32_t devid, + bool selected); +static uint32_t lpc54_spi_setfrequency(FAR struct spi_dev_s *dev, + uint32_t frequency); +static void lpc54_spi_setmode(FAR struct spi_dev_s *dev, + enum spi_mode_e mode); +static void lpc54_spi_setbits(FAR struct spi_dev_s *dev, int nbits); +static uint16_t lpc54_spi_send(FAR struct spi_dev_s *dev, uint16_t ch); +#ifdef CONFIG_LPC54_SPI_MASTER_DMA +static void lpc54_spi_exchange_nodma(FAR struct spi_dev_s *dev, + FAR const void *txbuffer, FAR void *rxbuffer, + size_t nwords) +#endif +static void lpc54_spi_exchange(FAR struct spi_dev_s *dev, + FAR const void *txbuffer, FAR void *rxbuffer, + size_t nwords); +#ifndef CONFIG_SPI_EXCHANGE +static void lpc54_spi_sndblock(FAR struct spi_dev_s *dev, + FAR const void *buffer, size_t nwords); +static void lpc54_spi_recvblock(FAR struct spi_dev_s *dev, + FAR void *buffer, size_t nwords); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct spi_ops_s g_spi_ops = +{ + .lock = lpc54_spi_lock, + .select = lpc54_spiselect, + .setfrequency = lpc54_spi_setfrequency, + .setmode = lpc54_spi_setmode, + .setbits = lpc54_spi_setbits, +#ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = 0, /* Not supported */ +#endif + .status = lpc54_spistatus, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = lpc54_spicmddata, +#endif + .send = lpc54_spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = lpc54_spi_exchange, +#else + .sndblock = lpc54_spi_sndblock, + .recvblock = lpc54_spi_recvblock, +#endif +#ifdef CONFIG_SPI_CALLBACK + .registercallback = lpc54_spiregister, /* Provided externally */ +#else + .registercallback = 0, /* Not implemented */ +#endif +}; + +#ifdef CONFIG_LPC54_I2C0_MASTER +static struct lpc54_spidev_s g_spi0_dev; +#endif +#ifdef CONFIG_LPC54_I2C1_MASTER +static struct lpc54_spidev_s g_spi1_dev; +#endif +#ifdef CONFIG_LPC54_I2C2_MASTER +static struct lpc54_spidev_s g_spi2_dev; +#endif +#ifdef CONFIG_LPC54_I2C3_MASTER +static struct lpc54_spidev_s g_spi3_dev; +#endif +#ifdef CONFIG_LPC54_I2C4_MASTER +static struct lpc54_spidev_s g_spi4_dev; +#endif +#ifdef CONFIG_LPC54_I2C5_MASTER +static struct lpc54_spidev_s g_spi5_dev; +#endif +#ifdef CONFIG_LPC54_I2C6_MASTER +static struct lpc54_spidev_s g_spi6_dev; +#endif +#ifdef CONFIG_LPC54_I2C7_MASTER +static struct lpc54_spidev_s g_spi7_dev; +#endif +#ifdef CONFIG_LPC54_I2C8_MASTER +static struct lpc54_spidev_s g_spi8_dev; +#endif +#ifdef CONFIG_LPC54_I2C9_MASTER +static struct lpc54_spidev_s g_spi9_dev; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_spi_putreg + * + * Description: + * Write a value to a register at the offset from the Flexcomm base. + * + ****************************************************************************/ + +static inline void lpc54_spi_putreg(struct lpc54_spidev_s *priv, + unsigned int regoffset, uint32_t regval) +{ + putreg32(value, priv->base + regoffset); +} + +/**************************************************************************** + * Name: lpc54_spi_gettreg + * + * Description: + * Read the content of a register at the offset from the Flexcomm base. + * + ****************************************************************************/ + +static inline void lpc54_spi_gettreg(struct lpc54_spidev_s *priv, + unsigned int regoffset) +{ + return getreg32(priv->base + regoffset); +} + +/**************************************************************************** + * Name: lpc54_spi_16bitmode + * + * Description: + * Check if the SPI is operating in > 8-bit mode (16-bit accesses) + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * true: 16-bit mode, false: 8-bit mode + * + ****************************************************************************/ + +static inline bool lpc54_spi_16bitmode(FAR struct lpc54_spidev_s *priv) +{ +#warning Missing logic + return false; +} + +/**************************************************************************** + * Name: lpc54_spi_lock + * + * Description: + * On SPI busses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the busses for a sequence of + * transfers. The bus should be locked before the chip is selected. After + * locking the SPI bus, the caller should then also call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. If the SPI buss is being shared, then it + * may have been left in an incompatible state. + * + * Input Parameters: + * dev - Device-specific state data + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int lpc54_spi_lock(FAR struct spi_dev_s *dev, bool lock) +{ + FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev; + int ret; + + if (lock) + { + /* Take the semaphore (perhaps waiting) */ + + do + { + ret = nxsem_wait(&priv->exclsem); + + /* The only case that an error should occur here is if the wait + * was awakened by a signal. + */ + + DEBUGASSERT(ret == OK || ret == -EINTR); + } + while (ret == -EINTR); + } + else + { + (void)nxsem_post(&priv->exclsem); + ret = OK; + } + + return ret; +} + +/**************************************************************************** + * Name: lpc54_spi_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static uint32_t lpc54_spi_setfrequency(FAR struct spi_dev_s *dev, + uint32_t frequency) +{ + FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev; + uint32_t actual; + + /* Check if the requested frequence is the same as the frequency selection */ + + DEBUGASSERT(priv && frequency <= priv->fclock / 2); + + if (priv->frequency == frequency) + { + /* We are already at this frequency. Return the actual. */ + + return priv->actual; + } + + /* Set the new SPI frequency */ +#warning Missing logic + + /* Save the frequency setting */ + + priv->frequency = frequency; + priv->actual = actual; + + spiinfo("Frequency %d->%d\n", frequency, actual); + return actual; +} + +/**************************************************************************** + * Name: lpc54_spi_setmode + * + * Description: + * Set the SPI mode. Optional. See enum spi_mode_e for mode definitions + * + * Input Parameters: + * dev - Device-specific state data + * mode - The SPI mode requested + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void lpc54_spi_setmode(FAR struct spi_dev_s *dev, + enum spi_mode_e mode) +{ + FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev; + uint32_t regval; + + /* Has the mode changed? */ + + if (mode != priv->mode) + { + /* Yes... Set the new mode */ +#warning Missing logic + + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ +#warning Missing logic + break; + + case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ +#warning Missing logic + break; + + case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ +#warning Missing logic + break; + + case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ +#warning Missing logic + break; + + default: + DEBUGPANIC(); + return; + } + +#warning Missing logic + + /* Save the mode so that subsequent re-configuratins will be faster */ + + priv->mode = mode; + } +} + +/**************************************************************************** + * Name: lpc54_spi_setbits + * + * Description: + * Set the number if bits per word. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits requests + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void lpc54_spi_setbits(FAR struct spi_dev_s *dev, int nbits) +{ + FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev; + uint32_t regval; + + /* Has the number of bits changed? */ + + DEBUGASSERT(priv && nbits > 7 && nbits < 17); + + if (nbits != priv->nbits) + { + /* Yes... Set the number word width */ +#warning Missing logic + + /* Save the selection so the subsequence re-configurations will be faster */ + + priv->nbits = nbits; + } +} + +/**************************************************************************** + * Name: lpc54_spi_send + * + * Description: + * Exchange one word on SPI + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * response + * + ****************************************************************************/ + +static uint16_t lpc54_spi_send(FAR struct spi_dev_s *dev, uint16_t wd) +{ + uint16_t ret; + + /* Write the data to transmitted to the SPI Data Register */ +#warning Missing logic + + /* Read the SPI Status Register again to clear the status bit */ +#warning Missing logic + + return ret; +} + +/**************************************************************************** + * Name: lpc54_spi_exchange (no DMA). aka lpc54_spi_exchange_nodma + * + * Description: + * Exchange a block of data on SPI without using DMA + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to a buffer in which to receive data + * nwords - the length of data to be exchaned in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_LPC54_SPI_MASTER_DMA +static void lpc54_spi_exchange(FAR struct spi_dev_s *dev, + FAR const void *txbuffer, FAR void *rxbuffer, + size_t nwords) +#else +static void lpc54_spi_exchange_nodma(FAR struct spi_dev_s *dev, + FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords) +#endif +{ + FAR struct lpc54_spidev_s *priv = (FAR struct lpc54_spidev_s *)dev; + DEBUGASSERT(priv && priv->base); + + spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", + txbuffer, rxbuffer, nwords); + + /* 8- or 16-bit mode? */ + + if (lpc54_spi_16bitmode(priv)) + { + /* 16-bit mode */ + + const uint16_t *src = (const uint16_t *)txbuffer; + uint16_t *dest = (uint16_t *)rxbuffer; + uint16_t word; + + while (nwords-- > 0) + { + /* Get the next word to write. Is there a source buffer? */ + + if (src) + { + word = *src++; + } + else + { + word = 0xffff; + } + + /* Exchange one word */ + + word = spi_send(dev, word); + + /* Is there a buffer to receive the return value? */ + + if (dest) + { + *dest++ = word; + } + } + } + else + { + /* 8-bit mode */ + + const uint8_t *src = (const uint8_t *)txbuffer; + uint8_t *dest = (uint8_t *)rxbuffer; + uint8_t word; + + while (nwords-- > 0) + { + /* Get the next word to write. Is there a source buffer? */ + + if (src) + { + word = *src++; + } + else + { + word = 0xff; + } + + /* Exchange one word */ + + word = (uint8_t)spi_send(dev, (uint16_t)word); + + /* Is there a buffer to receive the return value? */ + + if (dest) + { + *dest++ = word; + } + } + } +} + +/**************************************************************************** + * Name: lpc54_spi_exchange (no DMA). aka lpc54_spi_exchange_nodma + * + * Description: + * Exchange a block of data on SPI without using DMA + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to a buffer in which to receive data + * nwords - the length of data to be exchaned in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_LPC54_SPI_MASTER_DMA +static void lpc54_spi_exchange(FAR struct spi_dev_s *dev, + FAR const void *txbuffer, FAR void *rxbuffer, + size_t nwords) +{ + /* If the transfer is small, then perform the exchange without using DMA. */ +#warning Missing logic + + /* Otherwise, use DMA */ +#warning Missing logic +} +#endif /* CONFIG_LPC54_SPI_MASTER_DMA */ + +/**************************************************************************** + * Name: lpc54_spi_sndblock + * + * Description: + * Send a block of data on SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_spi_sndblock(FAR struct spi_dev_s *dev, + FAR const void *buffer, size_t nwords) +{ + spiinfo("txbuffer=%p nwords=%d\n", txbuffer, nwords); + return lpc54_spi_exchange(dev, txbuffer, NULL, nwords); +} + +/**************************************************************************** + * Name: lpc54_spi_recvblock + * + * Description: + * Revice a block of data from SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer in which to recieve data + * nwords - the length of data that can be received in the buffer in + * number of words. The wordsize is determined by the number of + * bits-per-word selected for the SPI interface. If nbits <= 8, + * the data is packed into uint8_t's; if nbits >8, the data is + * packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc54_spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, + size_t nwords) +{ + spiinfo("rxbuffer=%p nwords=%d\n", rxbuffer, nwords); + return lpc54_spi_exchange(dev, NULL, rxbuffer, nwords); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_spibus_initialize + * + * Description: + * Initialize the selected SPI port + * 0 - SPI0 + * 1 - SPI1 + * ... + * 9 - SSP9 + * + * Input Parameter: + * port - SPI peripheral number. 0..9 + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_dev_s *lpc54_spibus_initialize(int port) +{ + struct lpc54_spidev_s *priv; + irqstate_t flags; + + flags = enter_critical_section(); + + /* Configure the requestin SPI peripheral */ + /* NOTE: The basic FLEXCOMM initialization was performed in + * lpc54_lowputc.c. + */ + +#ifdef CONFIG_LPC54_I2C0_MASTER + if (port == 0) + { + /* Attach 12 MHz clock to FLEXCOMM0 */ + + lpc54_flexcomm0_enableclk(); + + /* Set FLEXCOMM0 to the SPI peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM0_PSELID); + + /* Initialize the state structure */ + + priv = &g_spi0_dev; + priv->base = LPC54_FLEXCOMM0_BASE; + priv->irqid = LPC54_IRQ_FLEXCOMM0; + priv->fclock = BOARD_FLEXCOMM0_FCLK; + + /* Configure SPI pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C0_SCK); + lpc54_gpio_config(GPIO_I2C0_MOSI); + lpc54_gpio_config(GPIO_I2C0_MISO); + + /* Set up the FLEXCOMM0 function clock */ + + putreg32(BOARD_FLEXCOMM0_CLKSEL, LPC54_SYSCON_FCLKSEL0); + } + else +#endif +#ifdef CONFIG_LPC54_I2C1_MASTER + if (port == 1) + { + /* Attach 12 MHz clock to FLEXCOMM1 */ + + lpc54_flexcomm1_enableclk(); + + /* Set FLEXCOMM1 to the SPI peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM1_PSELID); + + /* Initialize the state structure */ + + priv = &g_spi1_dev; + priv->base = LPC54_FLEXCOMM1_BASE; + priv->irqid = LPC54_IRQ_FLEXCOMM1; + priv->fclock = BOARD_FLEXCOMM1_FCLK; + + /* Configure SPI pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C1_SCK); + lpc54_gpio_config(GPIO_I2C1_MOSI); + lpc54_gpio_config(GPIO_I2C1_MISO); + + /* Set up the FLEXCOMM1 function clock */ + + putreg32(BOARD_FLEXCOMM1_CLKSEL, LPC54_SYSCON_FCLKSEL1); + } + else +#endif +#ifdef CONFIG_LPC54_I2C2_MASTER + if (port == 2) + { + /* Attach 12 MHz clock to FLEXCOMM2 */ + + lpc54_flexcomm2_enableclk(); + + /* Set FLEXCOMM2 to the SPI peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM2_PSELID); + + /* Initialize the state structure */ + + priv = &g_spi2_dev; + priv->base = LPC54_FLEXCOMM2_BASE; + priv->irqid = LPC54_IRQ_FLEXCOMM2; + priv->fclock = BOARD_FLEXCOMM2_FCLK; + + /* Configure SPI pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C2_SCK); + lpc54_gpio_config(GPIO_I2C2_MOSI); + lpc54_gpio_config(GPIO_I2C2MISO); + + /* Set up the FLEXCOMM2 function clock */ + + putreg32(BOARD_FLEXCOMM2_CLKSEL, LPC54_SYSCON_FCLKSEL2); + } + else +#endif +#ifdef CONFIG_LPC54_I2C3_MASTER + if (port == 3) + { + /* Attach 12 MHz clock to FLEXCOMM3 */ + + lpc54_flexcomm3_enableclk(); + + /* Set FLEXCOMM3 to the SPI peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM3_PSELID); + + /* Initialize the state structure */ + + priv = &g_spi3_dev; + priv->base = LPC54_FLEXCOMM3_BASE; + priv->irqid = LPC54_IRQ_FLEXCOMM3; + priv->fclock = BOARD_FLEXCOMM3_FCLK; + + /* Configure SPI pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C3_SCK); + lpc54_gpio_config(GPIO_I2C3_MOSI); + lpc54_gpio_config(GPIO_I2C3_MISO); + + /* Set up the FLEXCOMM3 function clock */ + + putreg32(BOARD_FLEXCOMM3_CLKSEL, LPC54_SYSCON_FCLKSEL3); + } + else +#endif +#ifdef CONFIG_LPC54_I2C4_MASTER + if (port == 4) + { + /* Attach 12 MHz clock to FLEXCOMM4 */ + + lpc54_flexcomm4_enableclk(); + + /* Set FLEXCOMM4 to the SPI peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM4_PSELID); + + /* Initialize the state structure */ + + priv = &g_spi4_dev; + priv->base = LPC54_FLEXCOMM4_BASE; + priv->irqid = LPC54_IRQ_FLEXCOMM4; + priv->fclock = BOARD_FLEXCOMM4_FCLK; + + /* Configure SPI pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C4_SCK); + lpc54_gpio_config(GPIO_I2C4_MOSI); + lpc54_gpio_config(GPIO_I2C4_MISO); + + /* Set up the FLEXCOMM4 function clock */ + + putreg32(BOARD_FLEXCOMM4_CLKSEL, LPC54_SYSCON_FCLKSEL4); + } + else +#endif +#ifdef CONFIG_LPC54_I2C5_MASTER + if (port == 5) + { + /* Attach 12 MHz clock to FLEXCOMM5 */ + + lpc54_flexcomm5_enableclk(); + + /* Set FLEXCOMM5 to the SPI peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM5_PSELID); + + /* Initialize the state structure */ + + priv = &g_spi5_dev; + priv->base = LPC54_FLEXCOMM5_BASE; + priv->irqid = LPC54_IRQ_FLEXCOMM5; + priv->fclock = BOARD_FLEXCOMM5_FCLK; + + /* Configure SPI pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C5_SCK); + lpc54_gpio_config(GPIO_I2C5_MOSI); + lpc54_gpio_config(GPIO_I2C5_MISO); + + /* Set up the FLEXCOMM5 function clock */ + + putreg32(BOARD_FLEXCOMM5_CLKSEL, LPC54_SYSCON_FCLKSEL5); + } + else +#endif +#ifdef CONFIG_LPC54_I2C6_MASTER + if (port == 6) + { + /* Attach 12 MHz clock to FLEXCOMM6 */ + + lpc54_flexcomm6_enableclk(); + + /* Set FLEXCOMM6 to the SPI peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM6_PSELID); + + /* Initialize the state structure */ + + priv = &g_spi6_dev; + priv->base = LPC54_FLEXCOMM6_BASE; + priv->irqid = LPC54_IRQ_FLEXCOMM6; + priv->fclock = BOARD_FLEXCOMM6_FCLK; + + /* Configure SPI pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C6_SCK); + lpc54_gpio_config(GPIO_I2C6_MOSI); + lpc54_gpio_config(GPIO_I2C6_MISO); + + /* Set up the FLEXCOMM6 function clock */ + + putreg32(BOARD_FLEXCOMM6_CLKSEL, LPC54_SYSCON_FCLKSEL6); + } + else +#endif +#ifdef CONFIG_LPC54_I2C7_MASTER + if (port == 7) + { + /* Attach 12 MHz clock to FLEXCOMM7 */ + + lpc54_flexcomm7_enableclk(); + + /* Set FLEXCOMM7 to the SPI peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM7_PSELID); + + /* Initialize the state structure */ + + priv = &g_spi7_dev; + priv->base = LPC54_FLEXCOMM7_BASE; + priv->irqid = LPC54_IRQ_FLEXCOMM7; + priv->fclock = BOARD_FLEXCOMM7_FCLK; + + /* Configure SPI pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C7_SCK); + lpc54_gpio_config(GPIO_I2C7_MOSI); + lpc54_gpio_config(GPIO_I2C7_MISO); + + /* Set up the FLEXCOMM7 function clock */ + + putreg32(BOARD_FLEXCOMM7_CLKSEL, LPC54_SYSCON_FCLKSEL7); + } + else +#endif +#ifdef CONFIG_LPC54_I2C8_MASTER + if (port == 8) + { + /* Attach 12 MHz clock to FLEXCOMM8 */ + + lpc54_flexcomm8_enableclk(); + + /* Set FLEXCOMM8 to the SPI peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM8_PSELID); + + /* Initialize the state structure */ + + priv = &g_spi8_dev; + priv->base = LPC54_FLEXCOMM8_BASE; + priv->irqid = LPC54_IRQ_FLEXCOMM8; + priv->fclock = BOARD_FLEXCOMM8_FCLK; + + /* Configure SPI pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C8_SCK); + lpc54_gpio_config(GPIO_I2C8_MOSI); + lpc54_gpio_config(GPIO_I2C8_MISO); + + /* Set up the FLEXCOMM8 function clock */ + + putreg32(BOARD_FLEXCOMM8_CLKSEL, LPC54_SYSCON_FCLKSEL8); + } + else +#endif +#ifdef CONFIG_LPC54_I2C9_MASTER + if (port == 9) + { + /* Attach 12 MHz clock to FLEXCOMM9 */ + + lpc54_flexcomm9_enableclk(); + + /* Set FLEXCOMM9 to the SPI peripheral, locking that configuration + * in place. + */ + + putreg32(FLEXCOMM_PSELID_PERSEL_SPI | FLEXCOMM_PSELID_LOCK, + LPC54_FLEXCOMM9_PSELID); + + /* Initialize the state structure */ + + priv = &g_spi9_dev; + priv->base = LPC54_FLEXCOMM9_BASE; + priv->irqid = LPC54_IRQ_FLEXCOMM9; + priv->fclock = BOARD_FLEXCOMM9_FCLK; + + /* Configure SPI pins (defined in board.h) */ + + lpc54_gpio_config(GPIO_I2C9_SCK); + lpc54_gpio_config(GPIO_I2C9_MOSI); + lpc54_gpio_config(GPIO_I2C9_MISO); + + /* Set up the FLEXCOMM9 function clock */ + + putreg32(BOARD_FLEXCOMM9_CLKSEL, LPC54_SYSCON_FCLKSEL9); + } + else +#endif + { + return NULL; + } + + leave_critical_section(flags); + + /* Enable the SPI peripheral*/ + /* Configure 8-bit SPI mode and master mode */ +#warning Missing logic + + /* Set the initial SPI configuration */ + + priv->frequency = 0; + priv->nbits = 8; + priv->mode = SPIDEV_MODE0; + priv->dev.ops = &g_spi_ops; + + /* Select a default frequency of approx. 400KHz */ + + lpc54_spi_setfrequency((FAR struct spi_dev_s *)priv, 400000); + + /* Initialize the SPI semaphore that enforces mutually exclusive access */ + + nxsem_init(&priv->exclsem, 0, 1); + return &priv->dev; +} + +#endif /* HAVE_SPI_MASTER_DEVICE */ diff --git a/arch/arm/src/lpc54xx/lpc54_spi_master.h b/arch/arm/src/lpc54xx/lpc54_spi_master.h new file mode 100644 index 0000000000000000000000000000000000000000..376c3a6e7680796629856439072abc6906d52bbb --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_spi_master.h @@ -0,0 +1,180 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/lpc54_spi_master.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_SPI_MASTER_H +#define __ARCH_ARM_SRC_LPC54XX_SPI_MASTER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#ifdef HAVE_SPI_MASTER_DEVICE + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* This header file defines interfaces to common SPI logic. To use this common SPI + * logic on your board: + * + * 1. Provide logic in lpc54_boardinitialize() to configure SPI chip select pins. + * 2. Provide the lpc54_spiselect() and lpc54_spistatus() functions in your + * board-specific logic. These functions will perform chip selection + * and status operations using GPIOs in the way your board is configured. + * 3. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide + * lpc54_spicmddata() functions in your board-specific logic. This + * function will perform cmd/data selection operations using GPIOs in the + * way your board is configured. + * 4. Your low level board initialization logic should call lpc54_spibus_initialize. + * 5. The handle returned by lpc54_spibus_initialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(), + * for example, will bind the SPI driver to the SPI MMC/SD driver). + */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: lpc54_spibus_initialize + * + * Description: + * Initialize the selected SPI port + * 0 - SPI0 + * 1 - SPI1 + * ... + * 9 - SPI9 + * + * Input Parameter: + * port - SPI peripheral number, 0.. 9. + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_dev_s *lpc54_spibus_initialize(int port); + +/************************************************************************************ + * Name: lpc54_spiselect, lpc54_spistatus, and lpc54_spicmddata + * + * Description: + * These functions must be provided in your board-specific logic. The + * lpc54_spiselect function will perform chip selection and the lpc54_spistatus + * will perform status operations using GPIOs in the way your board is configured. + * + * If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, then + * lpc54_spicmddata must also be provided. This functions performs cmd/data + * selection operations using GPIOs in the way your board is configured. + * + ************************************************************************************/ + +void lpc54_spiselect(FAR struct spi_dev_s *dev, uint32_t devid, bool selected); +uint8_t lpc54_spistatus(FAR struct spi_dev_s *dev, uint32_t devid); + +#ifdef CONFIG_SPI_CMDDATA +int lpc54_spicmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); +#endif + +/************************************************************************************ + * Name: spi_flush + * + * Description: + * Flush and discard any words left in the RX fifo. This can be called from + * spiselect after a device is deselected (if you worry about such things). + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ************************************************************************************/ + +void spi_flush(FAR struct spi_dev_s *dev); + +/************************************************************************************ + * Name: lpc54_spi/spiregister + * + * Description: + * If the board supports a card detect callback to inform the SPI-based MMC/SD + * driver when an SD card is inserted or removed, then CONFIG_SPI_CALLBACK should + * be defined and the following function(s) must must be implemented. These + * functions implements the registercallback method of the SPI interface (see + * include/nuttx/spi/spi.h for details) + * + * Input Parameters: + * dev - Device-specific state data + * callback - The function to call on the media change + * arg - A caller provided value to return with the callback + * + * Returned Value: + * 0 on success; negated errno on failure. + * + ************************************************************************************/ + +#ifdef CONFIG_SPI_CALLBACK +int lpc54_spiregister(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* HAVE_SPI_MASTER_DEVICE */ +#endif /* __ARCH_ARM_SRC_LPC54XX_SPI_MASTER_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_start.c b/arch/arm/src/lpc54xx/lpc54_start.c new file mode 100644 index 0000000000000000000000000000000000000000..a9eaad1cf1a16e1f84435b1aaf1d94ce42427912 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_start.c @@ -0,0 +1,283 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_start.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "up_internal.h" +#include "nvic.h" + +#include "chip/lpc54_syscon.h" +#include "lpc54_clockconfig.h" +#include "lpc54_userspace.h" +#include "lpc54_lowputc.h" +#include "lpc54_serial.h" +#include "lpc54_start.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: showprogress + * + * Description: + * Print a character on the UART to show boot status. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) up_lowputc(c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This describes the initial PLL configuration */ + +static const struct pll_setup_s g_initial_pll_setup = +{ + .pllclksel = BOARD_PLL_CLKSEL, + .pllctrl = SYSCON_SYSPLLCTRL_SELR(BOARD_PLL_SELR) | + SYSCON_SYSPLLCTRL_SELI(BOARD_PLL_SELI) | + SYSCON_SYSPLLCTRL_SELP(BOARD_PLL_SELP), + .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(BOARD_PLL_MDEC)), + .pllndec = (SYSCON_SYSPLLNDEC_NDEC(BOARD_PLL_NDEC)), + .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(BOARD_PLL_PDEC)), + .pllfout = BOARD_PLL_FOUT, + .pllflags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP, + .ahbdiv = SYSCON_AHBCLKDIV_DIV(BOARD_AHBCLKDIV) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_fpuconfig + * + * Description: + * Configure the FPU. Relative bit settings: + * + * CPACR: Enables access to CP10 and CP11 + * CONTROL.FPCA: Determines whether the FP extension is active in the + * current context: + * FPCCR.ASPEN: Enables automatic FP state preservation, then the + * processor sets this bit to 1 on successful completion of any FP + * instruction. + * FPCCR.LSPEN: Enables lazy context save of FP state. When this is + * done, the processor reserves space on the stack for the FP state, + * but does not save that state information to the stack. + * + * Software must not change the value of the ASPEN bit or LSPEN bit while either: + * - the CPACR permits access to CP10 and CP11, that give access to the FP + * extension, or + * - the CONTROL.FPCA bit is set to 1 + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FPU +#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) +static inline void lpc54_fpuconfig(void) +{ + uint32_t regval; + + /* Set CONTROL.FPCA so that we always get the extended context frame + * with the volatile FP registers stacked above the basic context. + */ + + regval = getcontrol(); + regval |= (1 << 2); + setcontrol(regval); + + /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend + * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we + * are going to turn on CONTROL.FPCA for all contexts. + */ + + regval = getreg32(NVIC_FPCCR); + regval &= ~((1 << 31) | (1 << 30)); + putreg32(regval, NVIC_FPCCR); + + /* Enable full access to CP10 and CP11 */ + + regval = getreg32(NVIC_CPACR); + regval |= ((3 << (2 * 10)) | (3 << (2 * 11))); + putreg32(regval, NVIC_CPACR); +} +#else +static inline void lpc54_fpuconfig(void) +{ + uint32_t regval; + + /* Clear CONTROL.FPCA so that we do not get the extended context frame + * with the volatile FP registers stacked in the saved context. + */ + + regval = getcontrol(); + regval &= ~(1 << 2); + setcontrol(regval); + + /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend + * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we + * are going to keep CONTROL.FPCA off for all contexts. + */ + + regval = getreg32(NVIC_FPCCR); + regval &= ~((1 << 31) | (1 << 30)); + putreg32(regval, NVIC_FPCCR); + + /* Enable full access to CP10 and CP11 */ + + regval = getreg32(NVIC_CPACR); + regval |= ((3 << (2 * 10)) | (3 << (2 * 11))); + putreg32(regval, NVIC_CPACR); +} +#endif + +#else +# define lpc54_fpuconfig() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _start + * + * Description: + * This is the reset entry point. + * + ****************************************************************************/ + +void __start(void) +{ + const uint32_t *src; + uint32_t *dest; + uint32_t regval; + + /* Make sure that interrupts are disabled */ + + __asm__ __volatile__ ("\tcpsid i\n"); + + /* Enable the SRAM clock to make the stack usable */ + + regval = (SYSCON_AHBCLKCTRL0_SRAM1 | SYSCON_AHBCLKCTRL0_SRAM2 | + SYSCON_AHBCLKCTRL0_SRAM3); + putreg32(regval, LPC54_SYSCON_AHBCLKCTRLSET0); + + /* Configure the clocking and the console uart so that we can get debug + * output as soon as possible. NOTE: That this logic must not assume that + * .bss or .data have beeninitialized. + */ + + lpc54_clockconfig(&g_initial_pll_setup); + lpc54_lowsetup(); + showprogress('A'); + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = &_sbss; dest < &_ebss; ) + { + *dest++ = 0; + } + + showprogress('B'); + + /* Move the initialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = &_eronly, dest = &_sdata; dest < &_edata; ) + { + *dest++ = *src++; + } + + showprogress('C'); + + /* Initialize the FPU (if configured) */ + + lpc54_fpuconfig(); + showprogress('D'); + + /* Perform early serial initialization */ + +#ifdef USE_EARLYSERIALINIT + lpc54_earlyserialinit(); +#endif + showprogress('E'); + + /* For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + */ + +#ifdef CONFIG_BUILD_PROTECTED + lpc54_userspace(); + showprogress('F'); +#endif + + /* Initialize onboard resources */ + + lpc54_board_initialize(); + showprogress('G'); + + /* Then start NuttX */ + + showprogress('\r'); + showprogress('\n'); + os_start(); + + /* Shouldn't get here */ + + for (; ; ); +} diff --git a/arch/arm/src/lpc54xx/lpc54_start.h b/arch/arm/src/lpc54xx/lpc54_start.h new file mode 100644 index 0000000000000000000000000000000000000000..8378c6e7c7f3da3526bc4c71df9a6a0d3945b825 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_start.h @@ -0,0 +1,88 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/lpc54_start.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_START_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_START_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "up_internal.h" +#include "chip.h" + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* g_idle_topstack: _sbss is the start of the BSS region as defined by the linker + * script. _ebss lies at the end of the BSS region. The idle task stack starts at + * the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is + * the thread that the system boots on and, eventually, becomes the IDLE, do + * nothing task that runs only when there is nothing else to run. The heap + * continues from there until the end of memory. g_idle_topstack is a read-only + * variable the provides this computed address. + */ + +extern const uintptr_t g_idle_topstack; + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc54_board_initialize + * + * Description: + * All LPC54xx architectures must provide the following entry point. This entry + * point is called early in the initialization -- after clocking and memory have + * been configured but before caches have been enabled and before any devices have + * been initialized. + * + ************************************************************************************/ + +void lpc54_board_initialize(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_START_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_tickless.c b/arch/arm/src/lpc54xx/lpc54_tickless.c new file mode 100644 index 0000000000000000000000000000000000000000..57dd593cf8faec0e74c9d95e0226e76e75a084c2 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_tickless.c @@ -0,0 +1,802 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_rit.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from the LPC43xx tickless mode logic + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "up_arch.h" +#include "chip.h" +#include "chip/lpc54_rit.h" + +#ifdef CONFIG_SCHED_TICKLESS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef min +# define min(a,b) (a < b ? a : b) +#endif + +#define COUNTER_MAX 0x0000ffffffffffffllu + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint64_t g_to_reset = COUNTER_MAX / 2; +static uint64_t g_to_reset_next = COUNTER_MAX / 2 + COUNTER_MAX / 4; +static uint64_t g_to_end = COUNTER_MAX / 2 + COUNTER_MAX / 4 + COUNTER_MAX / 8; /* any alarm should no last more than COUNTER_MAX/8 */ +static struct timespec g_max_ts; + +static uint64_t g_common_div; +static uint64_t g_min_ticks; +static uint64_t g_min_nsec; + +static uint64_t g_reset_ticks = 1000; /* Ticks to add to force a reset */ + +static struct timespec g_base_ts; /* Time base */ +static uint64_t g_base_rest; /* Rest of ticks that is < g_min_ticks */ + +static struct timespec g_alarm_ts; /* alarm_time to set on next interrupt, used if not already g_armed */ + +static bool g_alarm_time_set = false; /* true if alarm_time set and need to be processed */ +static bool g_call = false; /* true if callback should be called on next interrupt */ +static bool g_forced_int = false; /* true if interrupt was forced with mask, no reset */ +static bool g_armed = false; /* true if alarm is g_armed for next match */ +static uint32_t g_synch = 0; /* Synch all calls, recursion is possible */ +static irqstate_t g_flags; + +static uint32_t g_cached_ctrl; +static uint64_t g_cached_mask; +static uint64_t g_cached_compare; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Some timer HW functions */ + +static inline void lpc54_set_counter(uint64_t value) +{ + putreg32(0, LPC54_RIT_COUNTER); + putreg16((uint32_t)(value >> 32), LPC54_RIT_COUNTERH); + putreg32((uint32_t)(value & 0xffffffffllu), LPC54_RIT_COUNTER); +} + +static uint64_t lpc54_get_counter(void) +{ + uint32_t ls; + uint16_t ms; + uint16_t verify; + + do + { + ms = getreg16(LPC54_RIT_COUNTERH); + ls = getreg32(LPC54_RIT_COUNTER); + verify = getreg16(LPC54_RIT_COUNTERH); + } + while (verify != ms); + + return (uint64_t)ms << 32 | (uint64_t)ls; +} + +static void lpc54_set_compare(uint64_t value) +{ + irqstate_t flags; + + if (value != g_cached_compare) + { + g_cached_compare = value; + + flags = enter_critical_section(); + putreg32(0, LPC54_RIT_COMPVAL); + putreg16((uint32_t)(value >> 32), LPC54_RIT_COMPVALH); + putreg32((uint32_t)(value & 0xffffffffllu), LPC54_RIT_COMPVAL); + leave_critical_section(); + } +} + +static inline uint64_t lpc54_get_compare(void) +{ + return g_cached_compare; +} + + static void lpc54_set_mask(uint64_t value) +{ + irqstate_t flags; + + if (value != g_cached_mask) + { + g_cached_mask = value; + + flags = enter_critical_section(); + putreg32(0, LPC54_RIT_MASK); + putreg16((uint32_t)(value >> 32), LPC54_RIT_MASKH); + putreg32((uint32_t)(value & 0xffffffffllu), LPC54_RIT_MASK); + leave_critical_section(); + putreg32(value, ); + } +} + +static inline uint64_t lpc54_get_mask(void) +{ + return g_cached_mask; +} + +static inline bool lpc54_get_ctrl_bit(uint32_t bit) +{ + return (g_cached_ctrl & bit) != 0; +} + +static inline void lpc54_set_ctrl_bit(uint32_t bit, bool value) +{ + if (lpc54_get_ctrl_bit(bit) != value) + { + if (value) + { + g_cached_ctrl |= bit; + } + else + { + g_cached_ctrl &= ~bit; + } + + putreg32(g_cached_ctrl, LPC54_RIT_CTRL); + } +} + +static inline void lpc54_set_reset_on_match(bool value) +{ + lpc54_set_ctrl_bit(RIT_CTRL_ENCLR, value); +} + +static inline bool lpc54_get_reset_on_match(void) +{ + return lpc54_get_ctrl_bit(RIT_CTRL_ENCLR); +} + +static inline void lpc54_set_enable(bool value) +{ + lpc54_set_ctrl_bit(RIT_CTRL_EN, value); +} + +static inline bool lpc54_get_enable(void) +{ + return lpc54_get_ctrl_bit(RIT_CTRL_EN); +} + +static inline void lpc54_clear_interrupt(void) +{ + putreg32(g_cached_ctrl | RIT_CTRL_INT, LPC54_RIT_CTRL); +} + +static inline bool lpc54_get_interrupt(void) +{ + return (getreg32(LPC54_RIT_CTRL) & RIT_CTRL_INT) != 0; +} + +/* Converters */ + +static uint32_t common_div(uint32_t a, uint32_t b) +{ + while (b != 0) + { + int h = a % b; + a = b; + b = h; + } + + return a; +} + +static void lpc54_ts_add(FAR const struct timespec *ts1, + FAR const struct timespec *ts2, + FAR struct timespec *ts3) +{ + time_t sec = ts1->tv_sec + ts2->tv_sec; + long nsec = ts1->tv_nsec + ts2->tv_nsec; + + if (nsec >= NSEC_PER_SEC) + { + nsec -= NSEC_PER_SEC; + sec++; + } + + ts3->tv_sec = sec; + ts3->tv_nsec = nsec; +} + +static void lpc54_ts_sub(FAR const struct timespec *ts1, + FAR const struct timespec *ts2, + FAR struct timespec *ts3) +{ + time_t sec; + long nsec; + + if (ts1->tv_sec < ts2->tv_sec) + { + sec = 0; + nsec = 0; + } + else if (ts1->tv_sec == ts2->tv_sec && ts1->tv_nsec <= ts2->tv_nsec) + { + sec = 0; + nsec = 0; + } + else + { + sec = ts1->tv_sec - ts2->tv_sec; + if (ts1->tv_nsec < ts2->tv_nsec) + { + nsec = (ts1->tv_nsec + NSEC_PER_SEC) - ts2->tv_nsec; + sec--; + } + else + { + nsec = ts1->tv_nsec - ts2->tv_nsec; + } + } + + ts3->tv_sec = sec; + ts3->tv_nsec = nsec; +} + +static inline uint64_t lpc54_ts2tick(FAR const struct timespec *ts) +{ + return (uint64_t)ts->tv_sec * LPC54_CCLK + + ((uint64_t)ts->tv_nsec / g_min_nsec * g_min_ticks)); +} + +static uint64_t lpc54_tick2ts(uint64_t ticks, FAR struct timespec *ts, + bool with_rest) +{ + uint64_t ticks_whole; + uint64_t ticks_rest = 0; + + if (with_rest) + { + uint64_t ticks_mult = ticks/g_min_ticks; + ticks_whole = ticks_mult*g_min_ticks; + ticks_rest = ticks - ticks_whole; + } + else + { + ticks_whole = ticks; + } + + ts->tv_sec = ticks_whole/LPC54_CCLK; + ts->tv_nsec = ((ticks_whole % LPC54_CCLK) / g_min_ticks) * g_min_nsec; + + return ticks_rest; +} + +/* Logic functions */ + +static inline void lpc54_sync_up(void) +{ + irqstate_t flags; + flags = enter_critical_section(); + + if (g_synch == 0) + { + g_flags = flags; + } + + g_synch++; +} + +static inline void lpc54_sync_down(void) +{ + g_synch--; + if (g_synch == 0) + { + leave_critical_section(g_flags); + } +} + +/* Assuming safe timer state, force interrupt, no reset possible */ + +static inline void lpc54_force_int(void) +{ + g_forced_int = true; + lpc54_set_reset_on_match(false); + lpc54_set_mask(COUNTER_MAX); + lpc54_set_compare(COUNTER_MAX); +} + +/* Init all vars, g_forced_int should not be cleared */ + +static inline void lpc54_init_timer_vars(void) +{ + g_alarm_time_set = false; + g_call = false; + g_armed = false; +} + +/* Calc g_reset_ticks and set compare to g_to_reset */ + +static void lpc54_calibrate_init(void) +{ + uint64_t counter = lpc54_get_counter(); + uint64_t counter_after = lpc54_get_counter(); + + counter_after = g_to_reset + counter; + counter_after = counter_after - counter; + + /* Shift to to Reset */ + + lpc54_set_compare(counter_after); + + counter_after = lpc54_get_counter(); + g_reset_ticks = (counter_after - counter) * 2; +} + +/* Process current and set timer in default safe state */ + +static void lpc54_save_timer(bool from_isr) +{ + if (g_forced_int) /* special case of forced interrupt by mask */ + { + g_forced_int = false; + lpc54_set_compare(COUNTER_MAX); + lpc54_set_mask(0); + lpc54_clear_interrupt(); + } + else + { + /* Process reset if any */ + + uint64_t match = lpc54_get_compare(); + + /* Move to end, no resets during processing */ + + lpc54_set_compare(COUNTER_MAX); + lpc54_set_mask(0); + + if (from_isr || lpc54_get_interrupt()) + { + if (lpc54_get_reset_on_match()) /* Was reset? */ + { + struct timespec match_ts; + g_base_rest = lpc54_tick2ts(match + g_base_rest, + &match_ts, true); + lpc54_ts_add(&g_base_ts, &match_ts, &g_base_ts); + } + + lpc54_clear_interrupt(); + } + } +} + +/* Assuming safe timer state, true if set, false - time is in the past */ + +static bool lpc54_set_safe_compare(uint64_t compare_to_set) +{ + uint64_t counter; + bool reset; + bool reset_after; + + if (compare_to_set < g_to_reset) + { + lpc54_set_reset_on_match(false); + } + else + { + lpc54_set_reset_on_match(true); + } + + lpc54_set_compare(compare_to_set); + + /* Check if ok */ + + reset = lpc54_get_interrupt(); + counter = lpc54_get_counter(); + reset_after = lpc54_get_interrupt(); + + if (reset != reset_after) + { + /* Was a reset get new counter */ + + counter = lpc54_get_counter(); + } + + if (reset_after || (!reset_after && compare_to_set > counter)) + { + return true; + } + else + { + lpc54_set_compare(COUNTER_MAX); + + return false; + } +} + +/* Assuming safe timer state, set_safe_compare in loop */ + +static void lpc54_looped_forced_set_compare(void) +{ + uint32_t i = 1; + + bool result = + lpc54_set_safe_compare(lpc54_get_counter() + g_reset_ticks); + + while (!result) + { + i++; + result = + lpc54_set_safe_compare(lpc54_get_counter() + g_reset_ticks * i); + } +} + +/* Assuming safe timer state, true if set, false - time is in the past */ + +static bool lpc54_set_calc_arm(uint64_t curr, uint64_t to_set, bool arm) +{ + uint64_t calc_time; + bool set; + + if (curr < g_to_reset_next) + { + calc_time = min(g_to_reset_next, to_set); + } + else + { + if (curr < g_to_end) + { + calc_time = min(curr + g_reset_ticks, to_set); + } + else + { + lpc54_looped_forced_set_compare(); + return true; + } + } + + set = lpc54_set_safe_compare(calc_time); + if (arm && set && (calc_time == to_set)) + { + g_armed = true; + } + + return set; +} + +/* Assuming safe timer state, try to set compare for normal operation */ + +static void lpc54_set_default_compare(uint64_t curr) +{ + bool result = lpc54_set_calc_arm(curr, COUNTER_MAX, false); + if (!result) + { + result = lpc54_set_calc_arm(lpc54_get_counter(), COUNTER_MAX, + false); + if (!result) + { + lpc54_looped_forced_set_compare(); + } + } +} + +/* Calculates ticks to set from g_alarm_ts and g_base_ts/g_base_rest, + * COUNTER_MAX if overflow. + */ + +static inline uint64_t lpc54_calc_to_set(void) +{ + struct timespec diff_ts; + struct timespec ovf_ts; + + lpc54_ts_sub(&g_alarm_ts, &g_base_ts, &diff_ts); + + lpc54_ts_sub(&diff_ts, &g_max_ts, &ovf_ts); + if (ovf_ts.tv_sec == 0 && ovf_ts.tv_nsec == 0) /* check overflow */ + { + return (lpc54_ts2tick(&diff_ts) - g_base_rest); + } + else + { + return COUNTER_MAX; + } +} + +/* Assuming safe timer state, used by isr: sets default compare, + * calls alarm. + */ + +static inline void lpc54_tl_alarm(uint64_t curr) +{ + lpc54_init_timer_vars(); + lpc54_set_default_compare(curr); + +#ifdef CONFIG_SCHED_TICKLESS_ALARM + struct timespec ts; + up_timer_gettime(&ts); + sched_alarm_expiration(&ts); +#else + sched_timer_expiration(); +#endif +} + +/* Interrupt handler */ + +static int lpc54_tl_isr(int irq, FAR void *context, FAR void *arg) +{ + uint64_t curr; + + lpc54_sync_up(); + lpc54_save_timer(true); + + curr = lpc54_get_counter(); + if (g_call) + { + lpc54_tl_alarm(curr); + } + else + { + if (g_armed) + { + lpc54_tl_alarm(curr); /* g_armed - g_call alarm */ + } + else + { + if (g_alarm_time_set) /* need to set alarm time */ + { + uint64_t toset = lpc54_calc_to_set(); + + if (toset > curr) + { + if (toset > g_to_end) + { + lpc54_set_default_compare(curr); + } + else + { + bool set = lpc54_set_calc_arm(curr, toset, true); + if (!set) + { + lpc54_tl_alarm(curr); + } + } + } + else + { + lpc54_tl_alarm(curr); + } + } + else + { + lpc54_set_default_compare(curr); + } + } + } + + lpc54_sync_down(); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void arm_timer_initialize(void) +{ + irqstate_t flags; + flags = enter_critical_section(); + + g_cached_ctrl = getreg32(LPC54_RIT_CTRL); + g_cached_ctrl &= ~RIT_CTRL_INT; /* Set interrupt to 0 */ + g_cached_mask = getreg32(LPC54_RIT_MASK); + g_cached_compare = getreg32(LPC54_RIT_COMPVAL); + + g_common_div = common_div(NSEC_PER_SEC, LPC54_CCLK); + g_min_ticks = LPC54_CCLK / g_common_div; + g_min_nsec = NSEC_PER_SEC / g_common_div; + + g_base_ts.tv_sec = 0; + g_base_ts.tv_nsec = 0; + g_base_rest = 0; + + lpc54_tick2ts(g_to_end, &g_max_ts, false); + + lpc54_set_enable(false); + + lpc54_set_compare(COUNTER_MAX); + lpc54_set_counter(0); + lpc54_set_mask(0); + + lpc54_set_reset_on_match(false); + lpc54_clear_interrupt(); + + irq_attach(LPC54M4_IRQ_RITIMER, lpc54_tl_isr, NULL); + up_enable_irq(LPC54M4_IRQ_RITIMER); + + lpc54_init_timer_vars(); + lpc54_set_enable(true); + lpc54_calibrate_init(); + leave_critical_section(flags); +} + +/* No reg changes, only processing */ + +int up_timer_gettime(FAR struct timespec *ts) +{ + struct timespec count_ts; + uint64_t count; + bool reset; + + lpc54_sync_up(); + + /* Order of calls is important, reset can come during processing */ + + reset = lpc54_get_interrupt(); + count = lpc54_get_counter(); + + /* Not processed reset can exist */ + + if (lpc54_get_reset_on_match()) + { + bool reset_after = lpc54_get_interrupt(); + + /* Was a reset during processing? get new counter */ + + if (reset != reset_after) + { + count = lpc54_get_counter(); + } + + if (reset_after) + { + /* Count should be smaller then COUNTER_MAX-g_to_end -> no overflow */ + + count += lpc54_get_compare(); + } + } + + lpc54_tick2ts(count + g_base_rest, &count_ts, false); + lpc54_ts_add(&g_base_ts, &count_ts, ts); + lpc54_sync_down(); + return OK; +} + +int up_alarm_cancel(FAR struct timespec *ts) +{ + lpc54_sync_up(); + + /* No reg changes, only variables logic */ + + if (ts != NULL) + { + up_timer_gettime(ts); + } + + /* Let default setup will be done in interrupt handler or up_alarm_start */ + + lpc54_init_timer_vars(); + + lpc54_sync_down(); + return OK; +} + +int up_alarm_start(FAR const struct timespec *ts) +{ + uint64_t toset; + uint64_t curr; + + lpc54_sync_up(); + lpc54_save_timer(false); + lpc54_init_timer_vars(); + + g_alarm_time_set = true; + g_alarm_ts.tv_sec = ts->tv_sec; + g_alarm_ts.tv_nsec = ts->tv_nsec; + + toset = lpc54_calc_to_set(); + curr = lpc54_get_counter(); + + if (toset > curr) + { + if (toset > g_to_end) /* Future set */ + { + lpc54_set_default_compare(curr); + } + else + { + bool set = lpc54_set_calc_arm(curr, toset, true); + if (!set) /* Signal g_call, force interrupt handler */ + { + g_call = true; + lpc54_force_int(); + } + } + } + else /* Signal g_call, force interrupt handler */ + { + g_call = true; + lpc54_force_int(); + } + + lpc54_sync_down(); + + return OK; +} + +#ifndef CONFIG_SCHED_TICKLESS_ALARM +int up_timer_cancel(FAR struct timespec *ts) +{ + lpc54_sync_up(); + + if (ts != NULL) + { + struct timespec abs_ts; + up_timer_gettime(&abs_ts); + lpc54_ts_sub(&g_alarm_ts, &abs_ts, ts); + } + + lpc54_init_timer_vars(); + lpc54_sync_down(); + return OK; +} + +int up_timer_start(FAR const struct timespec *ts) +{ + lpc54_sync_up(); + + struct timespec abs_ts; + up_timer_gettime(&abs_ts); + lpc54_ts_add(&abs_ts, ts, &abs_ts); + + up_alarm_start(&abs_ts); + + lpc54_sync_down(); + return OK; +} + +#endif /* CONFIG_SCHED_TICKLESS_ALARM */ +#endif /* CONFIG_SCHED_TICKLESS */ diff --git a/arch/arm/src/lpc54xx/lpc54_timerisr.c b/arch/arm/src/lpc54xx/lpc54_timerisr.c new file mode 100644 index 0000000000000000000000000000000000000000..2ff9924129405a74dd21451ab26a4a895052f527 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_timerisr.c @@ -0,0 +1,171 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_timerisr.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "nvic.h" +#include "clock/clock.h" +#include "up_internal.h" +#include "up_arch.h" + +#include "chip/lpc54_syscon.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The SysTick clock may be clocked internally either by the by the system + * clock (CLKSOURCE==1) or by the SysTick function clock (CLKSOURCE==0). + * The SysTick Function clock is equal to: + * + * Fsystick = Fmainclk / SYSTICKCLKDIV + * + * Both the divider value (BOARD_SYSTICKCLKDIV) and the resulting SysTick + * function clock frequency (Fsystick, BOARD_SYSTICK_CLOCK) + * + * The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * reload = (Fsystick / CLK_TICK) - 1 + * + * Tips for selecting BOARD_SYSTICKCLKDIV: The resulting reload value + * should be as large as possible, but must be less than 2^24: + * + * SYSTICKDIV > Fmainclk / CLK_TCK / 2^24 + */ + +#define SYSTICK_RELOAD ((BOARD_SYSTICK_CLOCK / CLK_TCK) - 1) + +/* The size of the reload field is 24 bits. Verify that the reload value + * will fit in the reload register. + */ + +#if SYSTICK_RELOAD > 0x00ffffff +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: lpc54_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +static int lpc54_timerisr(int irq, uint32_t *regs, void *arg) +{ + /* Process timer interrupt */ + + sched_process_timer(); + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: arm_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void arm_timer_initialize(void) +{ + uint32_t regval; + + /* May be clocked internally by the system clock or the SysTick function + * clock. Set the SysTick clock divider in the SYSCON_SYSTICK register. + * Since this function is called early after reset, it is safe to assume + * that the SysTick is disabled and so that no reset or halt actions are + * necessary. + */ + + regval = (SYSCON_SYSTICKCLKDIV_DIV(BOARD_SYSTICKCLKDIV) | + SYSCON_SYSTICKCLKDIV_REQFLAG); + putreg32(regval, LPC54_SYSCON_SYSTICKCLKDIV); + + /* The request flag will be cleared when the divider change is complete */ + + while ((getreg32(LPC54_SYSCON_SYSTICKCLKDIV) & SYSCON_SYSTICKCLKDIV_REQFLAG) != 0) + { + } + + /* Make sure that the SYSTICK clock source is set to use the SysTick + * function clock (CLKSOURCE==0). + */ + + regval = getreg32(NVIC_SYSTICK_CTRL); + regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; + putreg32(regval, NVIC_SYSTICK_CTRL); + + /* Configure SysTick to interrupt at the requested rate */ + + putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(LPC54_IRQ_SYSTICK, (xcpt_t)lpc54_timerisr, NULL); + + /* Enable SysTick interrupts */ + + putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | + NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); + + /* And enable the timer interrupt */ + + up_enable_irq(LPC54_IRQ_SYSTICK); +} diff --git a/wireless/ieee802154/mac802154_notif.h b/arch/arm/src/lpc54xx/lpc54_userspace.c similarity index 62% rename from wireless/ieee802154/mac802154_notif.h rename to arch/arm/src/lpc54xx/lpc54_userspace.c index 886d786c6b62538f792ec356801f1d647ac1f554..1c6229c8bc8ddf630b1ee8f093845b87da4e0ef3 100644 --- a/wireless/ieee802154/mac802154_notif.h +++ b/arch/arm/src/lpc54xx/lpc54_userspace.c @@ -1,15 +1,9 @@ /**************************************************************************** - * wireless/ieee802154/mac802154_notif.h + * arch/arm/src/lpc54xx/lpc54_userspace.c * - * Copyright (C) 2017 Verge Inc. All rights reserved. * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * - * Author: Anthony Merlino * Author: Gregory Nutt * - * The naming and comments for various fields are taken directly - * from the IEEE 802.15.4 2011 standard. - * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -39,9 +33,6 @@ * ****************************************************************************/ -#ifndef __WIRELESS_IEEE802154__MAC802154_NOTIF_H -#define __WIRELESS_IEEE802154__MAC802154_NOTIF_H - /**************************************************************************** * Included Files ****************************************************************************/ @@ -49,41 +40,68 @@ #include #include -#include +#include + +#include -#include +#include "lpc54_mpuinit.h" +#include "lpc54_userspace.h" + +#ifdef CONFIG_BUILD_PROTECTED /**************************************************************************** - * Private Types + * Public Functions ****************************************************************************/ -/* Extend the public ieee802154_notif_s to include a private forward link to - * support a list to handle allocation - */ +/**************************************************************************** + * Name: lpc54_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ -struct mac802154_notif_s +void lpc54_userspace(void) { - struct ieee802154_notif_s pub; /* Publically visible structure */ - FAR struct mac802154_notif_s *flink; /* Supports a singly linked list */ - uint8_t nclients; -}; + uint8_t *src; + uint8_t *dest; + uint8_t *end; -/**************************************************************************** - * Function Prototypes - ****************************************************************************/ + /* Clear all of user-space .bss */ + + DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && + USERSPACE->us_bssstart <= USERSPACE->us_bssend); + + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; + + while (dest != end) + { + *dest++ = 0; + } + + /* Initialize all of user-space .data */ + + DEBUGASSERT(USERSPACE->us_datasource != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart <= USERSPACE->us_dataend); -struct ieee802154_privmac_s; /* Forward Reference */ + src = (uint8_t *)USERSPACE->us_datasource; + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; -void mac802154_notifpool_init(FAR struct ieee802154_privmac_s *priv); + while (dest != end) + { + *dest++ = *src++; + } -int mac802154_notif_alloc(FAR struct ieee802154_privmac_s *priv, - FAR struct ieee802154_notif_s **notif, - bool allow_interrupt); + /* Configure the MPU to permit user-space access to its FLASH and RAM */ -void mac802154_notify(FAR struct ieee802154_privmac_s *priv, - FAR struct ieee802154_notif_s *notif); + lpc54_mpuinitialize(); +} -void mac802154_notif_free_locked(FAR struct ieee802154_privmac_s * priv, - FAR struct ieee802154_notif_s *notif); +#endif /* CONFIG_BUILD_PROTECTED */ -#endif /* __WIRELESS_IEEE802154__MAC802154_NOTIF_H */ \ No newline at end of file diff --git a/arch/arm/src/lpc54xx/lpc54_userspace.h b/arch/arm/src/lpc54xx/lpc54_userspace.h new file mode 100644 index 0000000000000000000000000000000000000000..44f708dc5cacefb496ef3b5401b3f4b4ad9acc25 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_userspace.h @@ -0,0 +1,64 @@ +/************************************************************************************ + * arch/arm/src/lpc54xx/lpc54_userspace.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_USERSPACE_H +#define __ARCH_ARM_SRC_LPC54XX_LPC54_USERSPACE_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/**************************************************************************** + * Name: lpc54_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void lpc54_userspace(void); +#endif + +#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_USERSPACE_H */ diff --git a/arch/arm/src/lpc54xx/lpc54_wwdt.c b/arch/arm/src/lpc54xx/lpc54_wwdt.c new file mode 100644 index 0000000000000000000000000000000000000000..a664d2ba99246fd2b6bf40bd1ab3ab31508200e6 --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_wwdt.c @@ -0,0 +1,681 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_wwdt.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "chip/lpc54_wwdt.h" +#include "lpc54_power.h" +#include "lpc54_wdt.h" + +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_LPC54_WWDT) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Clocking *****************************************************************/ + +#define WWDT_FREQ 3000000 /* Watchdog clock is IRC 12MHz, but + * it has fixed divider by 4 */ +#define LPC54_MAX_WWDT_TC 0xFFFFFF /* 24-bit counter max value */ +#define LPC54_MIN_WWDT_TC 0xFF /* 8-bit counter min value */ +#define LPC54_MAX_WWDT_WINDOW 0xFFFFFF /* 24-bit max value */ +#define LPC54_MIN_WWDT_WINDOW 0x100 /* Minimum window value allowed */ +#define WWDT_WARNINT_VALUE 0x3FF /* 10-bit max value */ +#define WWDT_MAXTIMEOUT 5592 /* Max timeout value in miliseconds */ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_LPC54_WWDT_DEFTIMOUT +# define CONFIG_LPC54_WWDT_DEFTIMOUT WWDT_MAXTIMEOUT +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * well-known watchdog_lowerhalf_s structure. + */ + +struct lpc54_lowerhalf_wwdt_s +{ + FAR const struct watchdog_ops_s *ops; /* Lower half operations */ + xcpt_t handler; /* Current watchdog interrupt handler */ + uint32_t timeout; /* The actual timeout value */ + bool started; /* The timer has been started */ + uint32_t reload; /* The 24-bit reload field reset value */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void lpc54_setwindow(uint32_t window); +static void lpc54_setwarning(uint32_t warning); + +/* Interrupt hanlding *******************************************************/ + +static int lpc54_wwdt_interrupt(int irq, FAR void *context); + +/* "Lower half" driver methods **********************************************/ + +static int lpc54_start(FAR struct watchdog_lowerhalf_s *lower); +static int lpc54_stop(FAR struct watchdog_lowerhalf_s *lower); +static int lpc54_keepalive(FAR struct watchdog_lowerhalf_s *lower); +static int lpc54_getstatus(FAR struct watchdog_lowerhalf_s *lower, + FAR struct watchdog_status_s *status); +static int lpc54_settimeout(FAR struct watchdog_lowerhalf_s *lower, + uint32_t timeout); +static xcpt_t lpc54_capture(FAR struct watchdog_lowerhalf_s *lower, + xcpt_t handler); +static int lpc54_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static const struct watchdog_ops_s g_wdgops = +{ + .start = lpc54_start, + .stop = lpc54_stop, + .keepalive = lpc54_keepalive, + .getstatus = lpc54_getstatus, + .settimeout = lpc54_settimeout, + .capture = lpc54_capture, + .ioctl = lpc54_ioctl, +}; + +/* "Lower half" driver state */ + +static struct lpc54_lowerhalf_wwdt_s g_wdgdev; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_setwindow + * + * Description: + * The window register determines the highest timeout value allowed when a + * watchdog feed is performed. If a feed valid sequence completes prior to + * timeout value reaching the value in window, a watchdog event will occur. + * + * window resets to the maximum possible timeout value, so windowing is not + * in effect. Values of window below 0x100 will make it impossible to ever + * feed the watchdog successfully + * + ****************************************************************************/ + +static void lpc54_setwindow(uint32_t window) +{ + /* WWDT window minimum value limiting */ + + if (window < 0x100) + { + window = 0x100; + } + + putreg32(window, LPC54_WWDT_WINDOW); +} + +/**************************************************************************** + * Name: lpc54_setwarning + * + * Description: + * The WDWARNINT register determines the watchdog timer counter value that + * will generate a watchdog interrupt. When the watchdog timer counter + * matches the value defined by WDWARNINT, an interrupt will be generated + * after the subsequent WDCLK. A match of the watchdog timer counter to + * WDWARNINT occurs when the bottom 10 bits of the counter have the same + * value as the 10 bits of WARNINT, and the remaining upper bits of the + * counter are all 0. This gives a maximum time of 1,023 watchdog timer + * counts (4,096 watchdog clocks) for the interrupt to occur prior to a + * watchdog event. If WDWARNINT is set to 0, the interrupt will occur at + * the same time as the watchdog event. + * + ****************************************************************************/ + +static void lpc54_setwarning(uint32_t warning) +{ + /* WWDT warning maximum value limiting */ + + if (warning > 0x3FF) + { + warning = 0x3FF; + } + + putreg32(warning, LPC54_WWDT_WARNINT); +} + +/**************************************************************************** + * Name: lpc54_wwdt_interrupt + * + * Description: + * WWDT warning interrupt + * + * Input Parameters: + * Usual interrupt handler arguments. + * + * Returned Values: + * Always returns OK. + * + ****************************************************************************/ + +static int lpc54_wwdt_interrupt(int irq, FAR void *context) +{ + FAR struct lpc54_lowerhalf_wwdt_s *priv = &g_wdgdev; + uint32_t regval; + + /* Check if the watchdog warning interrupt is really pending */ + + regval = getreg32(LPC54_WWDT_MOD); + if ((regval & WWDT_MOD_WDINT) != 0) + { + /* Is there a registered handler? */ + + if (priv->handler) + { + /* Yes... NOTE: This interrupt service routine (ISR) must reload + * the WWDT counter to prevent the reset. Otherwise, we will + * reset upon return. + */ + + priv->handler(irq, context); + } + + /* The watchdog interrupt flag is cleared by writing '1' to the WDINT + * bit in the WDMOD register. + */ + + regval |= WWDT_MOD_WDINT; + putreg32(regval, LPC54_WWDT_MOD); + } + + return OK; +} + +/**************************************************************************** + * Name: lpc54_start + * + * Description: + * Start the watchdog timer, resetting the time to the current timeout, + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc54_start(FAR struct watchdog_lowerhalf_s *lower) +{ + FAR struct lpc54_lowerhalf_wwdt_s *priv = + (FAR struct lpc54_lowerhalf_wwdt_s *)lower; + + wdinfo("Entry\n"); + DEBUGASSERT(priv); + + /* The watchdog is always disabled after a reset. It is enabled by setting + * the WDEN bit in the WDMOD register, then it cannot be disabled again + * except by a reset. + * + * Watchdog is enabled and will reset the chip + */ + + putreg32(WWDT_MOD_WDEN | WWDT_MOD_WDRESET , LPC54_WWDT_MOD); + + /* Feed the watchdog to enable it */ + + putreg32(0xAA, LPC54_WWDT_FEED); + putreg32(0x55, LPC54_WWDT_FEED); + + priv->started = true; + return OK; +} + +/**************************************************************************** + * Name: lpc54_stop + * + * Description: + * Stop the watchdog timer + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc54_stop(FAR struct watchdog_lowerhalf_s *lower) +{ + + /* The watchdog is always disabled after a reset. It is enabled by setting + * the WDEN bit in the WDMOD register, then it cannot be disabled again + * except by a reset. + */ + + wdinfo("Entry\n"); + return -ENOSYS; +} + +/**************************************************************************** + * Name: lpc54_keepalive + * + * Description: + * Reset the watchdog timer to the current timeout value, prevent any + * imminent watchdog timeouts. This is sometimes referred as "pinging" + * the watchdog timer or "feeding the dog". + * + * The application program must write in the FEED register at regular + * intervals during normal operation to prevent an MCU reset. This operation + * must occur only when the counter value is lower than the window register + * value. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc54_keepalive(FAR struct watchdog_lowerhalf_s *lower) +{ + FAR struct lpc54_lowerhalf_wwdt_s *priv = + (FAR struct lpc54_lowerhalf_wwdt_s *)lower; + + wdinfo("Entry\n"); + DEBUGASSERT(priv); + + /* Feed the watchdog */ + + putreg32(0xAA, LPC54_WWDT_FEED); + putreg32(0x55, LPC54_WWDT_FEED); + + return OK; +} + +/**************************************************************************** + * Name: lpc54_getstatus + * + * Description: + * Get the current watchdog timer status + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * status - The location to return the watchdog status information. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc54_getstatus(FAR struct watchdog_lowerhalf_s *lower, + FAR struct watchdog_status_s *status) +{ + FAR struct lpc54_lowerhalf_wwdt_s *priv = + (FAR struct lpc54_lowerhalf_wwdt_s *)lower; + uint32_t elapsed; + uint32_t reload; + + wdinfo("Entry\n"); + DEBUGASSERT(priv); + + /* Return the status bit */ + + status->flags = WDFLAGS_RESET; + if (priv->started) + { + status->flags |= WDFLAGS_ACTIVE; + } + + if (priv->handler) + { + status->flags |= WDFLAGS_CAPTURE; + } + + /* Return the actual timeout is milliseconds */ + + status->timeout = priv->timeout; + + /* Get the time remaining until the watchdog expires (in milliseconds) */ + + + reload = getreg32(LPC54_WWDT_TC); + elapsed = priv->reload - reload; + status->timeleft = (priv->timeout * elapsed) / (priv->reload + 1); + + wdinfo("Status :\n"); + wdinfo(" flags : %08x\n", status->flags); + wdinfo(" timeout : %d\n", status->timeout); + wdinfo(" timeleft : %d\n", status->flags); + return OK; +} + +/**************************************************************************** + * Name: lpc54_settimeout + * + * Description: + * Set a new timeout value (and reset the watchdog timer) + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * timeout - The new timeout value in milliseconds. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc54_settimeout(FAR struct watchdog_lowerhalf_s *lower, + uint32_t timeout) +{ + FAR struct lpc54_lowerhalf_wwdt_s *priv = + (FAR struct lpc54_lowerhalf_wwdt_s *)lower; + uint32_t reload; + uint32_t regval; + + DEBUGASSERT(priv); + wdinfo("Entry: timeout=%d\n", timeout); + + /* Can this timeout be represented? */ + + if (timeout < 1 || timeout > WWDT_MAXTIMEOUT) + { + wderr("ERROR: Cannot represent timeout=%d > %d\n", + timeout, WWDT_MAXTIMEOUT_MS); + return -ERANGE; + } + + /* Determine timeout value */ + + reload = WWDT_FREQ/1000; + reload = timeout * reload; + + /* Make sure that the final reload value is within range */ + + if (reload > LPC54_MAX_WWDT_TC) + { + reload = LPC54_MAX_WWDT_TC; + } + + /* Save the actual timeout value in milliseconds*/ + + priv->timeout = timeout; + + /* Remember the selected values */ + + priv->reload = reload; + wdinfo("reload=%d timout=%d\n", reload, priv->timeout); + regval = reload; + putreg32(regval, LPC54_WWDT_TC); + + /* Reset the t window value to the maximum value.. essentially disabling + * the lower limit of the watchdog reset time. + */ + + lpc54_setwindow(LPC54_MAX_WWDT_WINDOW); + + /* Set the warning interrupt register value */ + + lpc54_setwarning(WWDT_WARNINT_VALUE); + return OK; +} + +/**************************************************************************** + * Name: lpc54_capture + * + * Description: + * Don't reset on watchdog timer timeout; instead, call this user provider + * timeout handler. NOTE: Providing handler==NULL will restore the reset + * behavior. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * newhandler - The new watchdog expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored, + * + * Returned Values: + * The previous watchdog expiration function pointer or NULL is there was + * no previous function pointer, i.e., if the previous behavior was + * reset-on-expiration (NULL is also returned if an error occurs). + * + ****************************************************************************/ + +static xcpt_t lpc54_capture(FAR struct watchdog_lowerhalf_s *lower, + xcpt_t handler) +{ + FAR struct lpc54_lowerhalf_wwdt_s *priv = + (FAR struct lpc54_lowerhalf_wwdt_s *)lower; + irqstate_t flags; + xcpt_t oldhandler; + uint16_t regval; + + DEBUGASSERT(priv); + wdinfo("Entry: handler=%p\n", handler); + + /* Get the old handler return value */ + + flags = enter_critical_section(); + oldhandler = priv->handler; + + /* Save the new handler */ + + priv->handler = handler; + + /* Are we attaching or detaching the handler? */ + + regval = getreg32(LPC54_WWDT_MOD); + if (handler) + { + /* Attaching... Enable the watchdog interrupt */ + + regval |= WWDT_MOD_WDINT; + putreg32(regval, LPC54_WWDT_MOD); + + up_enable_irq(LPC54_IRQ_WDT); + } + else + { + /* Detaching... Disable the EWI interrupt */ + + regval &= ~WWDT_MOD_WDINT; + putreg32(regval, LPC54_WWDT_MOD); + + up_disable_irq(LPC54_IRQ_WDT); + } + + leave_critical_section(flags); + return oldhandler; +} + +/**************************************************************************** + * Name: lp54_ioctl + * + * Description: + * Any ioctl commands that are not recognized by the "upper-half" driver + * are forwarded to the lower half driver through this method. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * cmd - The ioctl command value + * arg - The optional argument that accompanies the 'cmd'. The + * interpretation of this argument depends on the particular + * command. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc54_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd, + unsigned long arg) +{ + FAR struct lpc54_lowerhalf_wwdt_s *priv = + (FAR struct lpc54_lowerhalf_wwdt_s *)lower; + int ret = -ENOTTY; + + DEBUGASSERT(priv); + wdinfo("Entry: cmd=%d arg=%ld\n", cmd, arg); + + /* WDIOC_MINTIME: Set the minimum ping time. If two keepalive ioctls + * are received within this time, a reset event will be generated. + * Argument: A 32-bit time value in milliseconds. + */ + + if (cmd == WDIOC_MINTIME) + { + uint32_t mintime = (uint32_t)arg; + + /* The minimum time should be strictly less than the total delay + * which, in turn, will be less than or equal to LPC54_MAX_WWDT_TC + */ + + ret = -EINVAL; + if (mintime < priv->timeout) + { + uint32_t window = mintime*WWDT_FREQ/1000; + DEBUGASSERT(window < priv->reload); + lpc54_setwindow( window ); + ret = OK; + } + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_wwdt_initialize + * + * Description: + * Initialize the WWDT watchdog time. The watchdog timer is initialized and + * registers as 'devpath. The initial state of the watchdog time is + * disabled. + * + * Input Parameters: + * devpath - The full path to the watchdog. This should be of the form + * /dev/watchdog0 + * + * Returned Values: + * None + * + ****************************************************************************/ + +void lpc54_wwdt_initialize(FAR const char *devpath) +{ + FAR struct lpc54_lowerhalf_wwdt_s *priv = &g_wdgdev; + + wdinfo("Entry: devpath=%s\n", devpath); + + /* Initialize the driver state structure. Here we assume: (1) the state + * structure lies in .bss and was zeroed at reset time. (2) This function + * is only called once so it is never necessary to re-zero the structure. + */ + + priv->ops = &g_wdgops; + + /* Turn on and configure the Watchdog oscillator. Set the PDEN_WDT_OSC bit + * in the PDRUNCG0 register and setup the Watchdog oscillator control + * register, WDTOSCCTRL. + */ + + lpc54_wdtosc_powerup(); +#warning "Mising WDTOSCCTRL setup" + + /* Enable the register interface (WWDT bus clock): Set the WWDT bit in the + * AHBCLKCTRL0 register. + */ + + lpc54_wwdt_enableclk(); + + /* For waking up from a WWDT interrupt, enable the watchdog interrupt for + * wake-up in the STARTER0 register. + */ + + /* Set watchdog mode register to zero */ + + putreg32(0, LPC54_WWDT_MOD); + + /* Attach our watchdog interrupt handler (But don't enable it yet) */ + + (void)irq_attach(LPC54_IRQ_WDT, lpc54_wwdt_interrupt); + + /* Select an arbitrary initial timeout value. But don't start the watchdog + * yet. NOTE: If the "Hardware watchdog" feature is enabled through the + * device option bits, the watchdog is automatically enabled at power-on. + */ + + lpc54_settimeout((FAR struct watchdog_lowerhalf_s *)priv, + CONFIG_LPC54_WWDT_DEFTIMOUT); + + /* Register the watchdog driver as /dev/watchdog0 */ + + (void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv); +} + +#endif /* CONFIG_WATCHDOG && CONFIG_LPC54_WWDT */ diff --git a/arch/arm/src/lpc54xx/lpc54_wwdt.h b/arch/arm/src/lpc54xx/lpc54_wwdt.h new file mode 100644 index 0000000000000000000000000000000000000000..db0822a48ea87fbaf877e452eeea182056b9cc4f --- /dev/null +++ b/arch/arm/src/lpc54xx/lpc54_wwdt.h @@ -0,0 +1,97 @@ +/**************************************************************************** + * arch/arm/src/lpc54xx/lpc54_wdt.h + * + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_WDT_H +#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_WDT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc54_wdt.h" + +#ifdef CONFIG_WATCHDOG + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_wwdt_initialize + * + * Description: + * Initialize the WWDG watchdog time. The watchdog timer is initializeed and + * registers as 'devpath. The initial state of the watchdog time is + * disabled. + * + * Input Parameters: + * devpath - The full path to the watchdog. This should be of the form + * /dev/watchdog0 + * + * Returned Values: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_LPC54_WWDT +void lpc54_wwdt_initialize(FAR const char *devpath); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_WATCHDOG */ +#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_WDT_H */ diff --git a/arch/arm/src/nuc1xx/nuc_start.c b/arch/arm/src/nuc1xx/nuc_start.c index 80c01077ae817643421d210c4bab4ba6e52c60ca..e38e08caab09e763ceb46b32b554905ae1027415 100644 --- a/arch/arm/src/nuc1xx/nuc_start.c +++ b/arch/arm/src/nuc1xx/nuc_start.c @@ -1,8 +1,7 @@ /**************************************************************************** * arch/arm/src/nuc1xx/nuc_start.c - * arch/arm/src/chip/nuc_start.c * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -45,7 +44,6 @@ #include #include -#include #include "up_arch.h" #include "up_internal.h" @@ -54,6 +52,7 @@ #include "nuc_lowputc.h" #include "nuc_clockconfig.h" #include "nuc_userspace.h" +#include "nuc_start.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/nuc1xx/nuc_start.h b/arch/arm/src/nuc1xx/nuc_start.h new file mode 100644 index 0000000000000000000000000000000000000000..f38559e3c9a4ecc25751ac4b1aa6acba0e918812 --- /dev/null +++ b/arch/arm/src/nuc1xx/nuc_start.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/nuc1xx/nuc_start.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NUC1XX_NUC_START_H +#define __ARCH_ARM_SRC_NUC1XX_NUC_START_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: nuc_boardinitialize + * + * Description: + * All NUC1xx architectures must provide the following entry point. This entry + * point is called early in the initialization -- after clocking and memory have + * been configured but before caches have been enabled and before any devices have + * been initialized. + * + ************************************************************************************/ + +void nuc_boardinitialize(void); + +#endif /* __ARCH_ARM_SRC_NUC1XX_NUC_START_H */ diff --git a/arch/arm/src/sam34/sam_start.c b/arch/arm/src/sam34/sam_start.c index 71537f1c38b4507c8854eebbe2b4d21264393f11..a57cd23576523c2df0cabf11972419f0a30833d2 100644 --- a/arch/arm/src/sam34/sam_start.c +++ b/arch/arm/src/sam34/sam_start.c @@ -1,7 +1,8 @@ /**************************************************************************** * arch/arm/src/sam34/sam_start.c * - * Copyright (C) 2009-2010, 2012-2013, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010, 2012-2013, 2015, 2017 Gregory Nutt. All + * rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -44,7 +45,6 @@ #include #include -#include #include "up_arch.h" #include "up_internal.h" @@ -58,6 +58,8 @@ # include "nvic.h" #endif +#include "sam_start.h" + /**************************************************************************** * Private Function prototypes ****************************************************************************/ diff --git a/arch/arm/src/sam34/sam_start.h b/arch/arm/src/sam34/sam_start.h new file mode 100644 index 0000000000000000000000000000000000000000..73e033f49c7cc453f0f9f20bd9b3af0495df45e6 --- /dev/null +++ b/arch/arm/src/sam34/sam_start.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/sam34/sam_start.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_SAM_START_H +#define __ARCH_ARM_SRC_SAM34_SAM_START_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: sam_boardinitialize + * + * Description: + * All SAM3/4 architectures must provide the following entry point. This entry + * point is called early in the initialization -- after clocking and memory have + * been configured but before caches have been enabled and before any devices have + * been initialized. + * + ************************************************************************************/ + +void sam_boardinitialize(void); + +#endif /* __ARCH_ARM_SRC_SAM34_SAM_START_H */ diff --git a/arch/arm/src/sama5/sam_boot.c b/arch/arm/src/sama5/sam_boot.c index d2d154613cb961c7a1288e0873ad16c20e043e48..0098100945f27d4a745874326748a9570404825d 100644 --- a/arch/arm/src/sama5/sam_boot.c +++ b/arch/arm/src/sama5/sam_boot.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/sama5/sam_boot.c * - * Copyright (C) 2013-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -66,14 +66,7 @@ #include "sam_lowputc.h" #include "sam_serial.h" #include "sam_lcd.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ +#include "sam_boot.h" /**************************************************************************** * Public Data @@ -84,10 +77,6 @@ extern uint32_t _vector_start; /* Beginning of vector block */ extern uint32_t _vector_end; /* End+1 of vector block */ -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_boot.h b/arch/arm/src/sama5/sam_boot.h new file mode 100644 index 0000000000000000000000000000000000000000..2f1352ad7c5f6b1faf4b2c2b24d08bb4a83cb42e --- /dev/null +++ b/arch/arm/src/sama5/sam_boot.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/sama5/sam_boot.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMA5_SAM_BOOT_H +#define __ARCH_ARM_SRC_SAMA5_SAM_BOOT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: sam_boardinitialize + * + * Description: + * All SAMA5 architectures must provide the following entry point. This entry + * point is called early in the initialization -- after clocking and memory have + * been configured but before caches have been enabled and before any devices have + * been initialized. + * + ************************************************************************************/ + +void sam_boardinitialize(void); + +#endif /* __ARCH_ARM_SRC_SAMA5_SAM_BOOT_H */ diff --git a/arch/arm/src/sama5/sam_hsmci.c b/arch/arm/src/sama5/sam_hsmci.c index 1e6b476106e1c68a0689a65474db0bc5e03c3d45..b5093d36b041f027a241cd89121e3f7f837c0a5a 100644 --- a/arch/arm/src/sama5/sam_hsmci.c +++ b/arch/arm/src/sama5/sam_hsmci.c @@ -2213,6 +2213,7 @@ static int sam_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, unsigned int nwords; const uint32_t *ptr; uint32_t sr; + irqstate_t flags; DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); DEBUGASSERT(((uint32_t)buffer & 3) == 0); @@ -2232,10 +2233,13 @@ static int sam_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, /* Copy each word to the TX FIFO * - * REVISIT: If TX data underruns occur, then it may be necessary to - * disable pre-emption around this loop. + * It is necessary to disable pre-emption and interrupts around this loop + * in order to avoid a TX data underrun. */ + sched_lock(); + flags = enter_critical_section(); + nwords = (buflen + 3) >> 2; ptr = (const uint32_t *)buffer; @@ -2260,6 +2264,8 @@ static int sam_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, } } + leave_critical_section(flags); + sched_unlock(); return OK; } diff --git a/arch/arm/src/samdl/sam_start.c b/arch/arm/src/samdl/sam_start.c index f46e114fd66e41b78858a7151ca856d5ae723a27..c412d185d28e07a49c975c01ddcd889f234d737d 100644 --- a/arch/arm/src/samdl/sam_start.c +++ b/arch/arm/src/samdl/sam_start.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/samdl/sam_start.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -44,7 +44,6 @@ #include #include -#include #include "up_arch.h" #include "up_internal.h" @@ -53,6 +52,7 @@ #include "sam_lowputc.h" #include "sam_clockconfig.h" #include "sam_userspace.h" +#include "sam_start.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/samdl/sam_start.h b/arch/arm/src/samdl/sam_start.h new file mode 100644 index 0000000000000000000000000000000000000000..849131c819e2088953b6ad43895e302b38c6854b --- /dev/null +++ b/arch/arm/src/samdl/sam_start.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/samdl/sam_start.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMDL_SAM_START_H +#define __ARCH_ARM_SRC_SAMDL_SAM_START_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: sam_boardinitialize + * + * Description: + * All SAMD/L architectures must provide the following entry point. This entry + * point is called early in the initialization -- after clocking and memory have + * been configured but before caches have been enabled and before any devices have + * been initialized. + * + ************************************************************************************/ + +void sam_boardinitialize(void); + +#endif /* __ARCH_ARM_SRC_SAMDL_SAM_START_H */ diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig index 5350bc43152fe53804aed772c85c424b29dae333..c63dbe3b1d94a1375a920d9312aa1d0d86a263bd 100644 --- a/arch/arm/src/samv7/Kconfig +++ b/arch/arm/src/samv7/Kconfig @@ -753,6 +753,8 @@ endif # SAMV7_WDT || SAMV7_RSWDT menuconfig SAMV7_PROGMEM bool "FLASH program memory" + default n + select ARCH_HAVE_PROGMEM ---help--- Enable support FLASH interfaces as defined in include/nuttx/progmem.h diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c index 687154ae0b0fc5c076fa30b4279b3f6e5b667a16..b6df58bc1818ca18168cfb99a6d95d3d1926c38e 100644 --- a/arch/arm/src/samv7/sam_hsmci.c +++ b/arch/arm/src/samv7/sam_hsmci.c @@ -2200,6 +2200,7 @@ static int sam_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, unsigned int remaining; const uint32_t *src; uint32_t sr; + irqstate_t flags; DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); @@ -2229,10 +2230,13 @@ static int sam_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, /* Copy each word to the TX FIFO * - * REVISIT: If TX data underruns occur, then it may be necessary to - * disable pre-emption around this loop. + * It is necessary to disable pre-emption and interrupts around this loop + * in order to avoid a TX data underrun. */ + sched_lock(); + flags = enter_critical_section(); + src = (const uint32_t *)buffer; remaining = buflen; @@ -2302,6 +2306,8 @@ static int sam_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, } } + leave_critical_section(flags); + sched_unlock(); return OK; } diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 123107416cf8f8e53b30460609f071749f26d9af..141058ece8bb899c44beae7984d1467fa9ee821d 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -6971,6 +6971,15 @@ config STM32_USART_SINGLEWIRE Enable single wire UART support. The option enables support for the TIOCSSINGLEWIRE ioctl in the STM32 serial driver. +if PM +config PM_SERIAL_ACTIVITY + int "PM serial activity" + default 10 + ---help--- + PM activity reported to power management logic on every serial + interrupt. +endif + endif # STM32_SERIALDRIVER endmenu # U[S]ART Configuration @@ -7823,7 +7832,7 @@ endmenu endif # STM32_DMA2D menu "QEncoder Driver" - depends on QENCODER + depends on SENSORS_QENCODER depends on STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 || STM32_TIM5 || STM32_TIM8 config STM32_TIM1_QE diff --git a/arch/arm/src/stm32/chip/stm32_otghs.h b/arch/arm/src/stm32/chip/stm32_otghs.h index 2e8f124f5cfe07fa6b6f65216c7476bbc155e02f..d3a900f7407823ad1baf209a117a9b7e971c0f0f 100644 --- a/arch/arm/src/stm32/chip/stm32_otghs.h +++ b/arch/arm/src/stm32/chip/stm32_otghs.h @@ -79,7 +79,7 @@ #define STM32_OTGHS_CID_OFFSET 0x003c /* Core ID register */ #define STM32_OTGHS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ -#define STM32_OTGHS_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2)) +#define STM32_OTGHS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) #define STM32_OTGHS_DIEPTXF1_OFFSET 0x0104 /* Device IN endpoint transmit FIFO1 size register */ #define STM32_OTGHS_DIEPTXF2_OFFSET 0x0108 /* Device IN endpoint transmit FIFO2 size register */ #define STM32_OTGHS_DIEPTXF3_OFFSET 0x010c /* Device IN endpoint transmit FIFO3 size register */ diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_adc.h b/arch/arm/src/stm32/chip/stm32f33xxx_adc.h index ec84f5c9f8d848b69d27ff2f8da4c4cd457bf9a7..4d10780c05b13c2404ee484403c0d683bcbca721 100644 --- a/arch/arm/src/stm32/chip/stm32f33xxx_adc.h +++ b/arch/arm/src/stm32/chip/stm32f33xxx_adc.h @@ -84,7 +84,7 @@ #define STM32_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */ #define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */ #define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */ -#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register 2 */ +#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register */ #define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */ /* Master and Slave ADC Common Registers */ @@ -384,7 +384,7 @@ /* ADC injected sequence register */ #define ADC_JSQR_JL_SHIFT (0) /* Bits 0-1: Injected Sequence length */ -#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT) +#define ADC_JSQR_JL_MASK (2 << ADC_JSQR_JL_SHIFT) # define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */ #define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-5: External Trigger Selection for injected group */ #define ADC_JSQR_JEXTSEL_MASK (15 << ADC_JSQR_JEXTSEL_SHIFT) @@ -414,8 +414,8 @@ #define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) # define ADC_JSQR_JSQ1(ch) ((ch) << ADC_JSQR_JSQ1_SHIFT) /* Channel number 1..18 */ #define ADC_JSQR_JSQ2_SHIFT (14) /* Bits 14-18: 2nd conversion in injected sequence */ -#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_MASK) -# define ADC_JSQR_JSQ2(ch) ((ch) << ADC_JSQR_JSQ2_MASK) /* Channel number 1..18 */ +#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT) +# define ADC_JSQR_JSQ2(ch) ((ch) << ADC_JSQR_JSQ2_SHIFT) /* Channel number 1..18 */ #define ADC_JSQR_JSQ3_SHIFT (20) /* Bits 20-24: 3rd conversion in injected sequence */ #define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) # define ADC_JSQR_JSQ3(ch) ((ch) << ADC_JSQR_JSQ3_SHIFT) /* Channel number 1..18 */ diff --git a/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h b/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h index 36606382671aa5ced84bf17aa4cce798ffd98c1c..c2b29f152820fa4ebc4e99251addcacfd097d81f 100644 --- a/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h +++ b/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h @@ -78,7 +78,7 @@ #define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */ #define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ -#define STM32_OTGFS_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2)) +#define STM32_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) #define STM32_OTGFS_DIEPTXF1_OFFSET 0x0104 /* Device IN endpoint transmit FIFO1 size register */ #define STM32_OTGFS_DIEPTXF2_OFFSET 0x0108 /* Device IN endpoint transmit FIFO2 size register */ #define STM32_OTGFS_DIEPTXF3_OFFSET 0x010c /* Device IN endpoint transmit FIFO3 size register */ diff --git a/arch/arm/src/stm32/gnu/stm32_vectors.S b/arch/arm/src/stm32/gnu/stm32_vectors.S index b322d9e6cda447124225d4723cc7fd7b9af7cffc..a8feaa635f604fce81a63d8259bf31fdcf762f29 100644 --- a/arch/arm/src/stm32/gnu/stm32_vectors.S +++ b/arch/arm/src/stm32/gnu/stm32_vectors.S @@ -106,7 +106,7 @@ .thumb .file "stm32_vectors.S" -/* Check if common ARMv7 interrupt vectoring is used (see arch/arm/src/armv7-m/up_vectors.S) */ +/* Check if common ARMv7 interrupt vectoring is used (see arch/arm/src/armv7-m/up_vectors.c) */ #ifndef CONFIG_ARMV7M_CMNVECTOR diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index 200f31d95c7624b679af31c278b2a204ca188778..7ec37927bd5ee01c8e8f63fa4e91715f7d14771c 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -2250,7 +2250,7 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) * ****************************************************************************/ -#ifdef CONFIG_STM32_STM32L15XX +#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) static void adc_ioc_enable_tvref_register(FAR struct adc_dev_s *dev, bool enable) { @@ -2265,6 +2265,32 @@ static void adc_ioc_enable_tvref_register(FAR struct adc_dev_s *dev, ainfo("STM32_ADC_CCR value: 0x%08x\n", getreg32(STM32_ADC_CCR)); } + +#elif defined(CONFIG_STM32_STM32F10XX) +static void adc_ioc_enable_tvref_register(FAR struct adc_dev_s *dev, + bool enable) +{ +#if defined(CONFIG_STM32_ADC1) + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + + /* TSVREF bit is only available in the STM32_ADC1_CR2 register. */ + + if (priv->intf == 1) + { + if (enable) + { + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, 0, ADC_CR2_TSVREFE); + } + else + { + adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, ADC_CR2_TSVREFE, 0); + } + } + + ainfo("STM32_ADC_CR2 value: 0x%08x\n", + adc_getreg(priv, STM32_ADC_CR2_OFFSET)); +#endif /* CONFIG_STM32_ADC1 */ +} #endif /**************************************************************************** @@ -2661,7 +2687,17 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) adc_startconv(priv, true); break; -#ifdef CONFIG_STM32_STM32L15XX +#if defined(CONFIG_STM32_STM32F10XX) + case IO_ENABLE_TEMPER_VOLT_CH: + adc_ioc_enable_tvref_register(dev, *(bool *)arg); + break; + +#elif defined(CONFIG_STM32_STM32F20XX) + case IO_ENABLE_TEMPER_VOLT_CH: + adc_ioc_enable_tvref_register(dev, *(bool *)arg); + break; + +#elif defined(CONFIG_STM32_STM32L15XX) case IO_ENABLE_TEMPER_VOLT_CH: adc_ioc_enable_tvref_register(dev, *(bool *)arg); break; diff --git a/arch/arm/src/stm32/stm32_adc.h b/arch/arm/src/stm32/stm32_adc.h index eebba26746f925fb6dfefd8df70276e1f9b7faa6..dd02bae856279330934d8c5ad19ec3fd5dabccf6 100644 --- a/arch/arm/src/stm32/stm32_adc.h +++ b/arch/arm/src/stm32/stm32_adc.h @@ -1056,250 +1056,250 @@ */ #if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) -# define ADC1_JEXTSEL_T1CC1 ADC12_CFGR_JEXTSEL_T1CC1 -# define ADC1_JEXTSEL_T1CC2 ADC12_CFGR_JEXTSEL_T1CC2 -# define ADC1_JEXTSEL_T1CC3 ADC12_CFGR_JEXTSEL_T1CC3 -# define ADC1_JEXTSEL_T1CC4 ADC12_CFGR_JEXTSEL_T1CC4 -# define ADC1_JEXTSEL_T1TRGO ADC12_CFGR_JEXTSEL_T1TRGO -# define ADC2_JEXTSEL_T1CC1 ADC12_CFGR_JEXTSEL_T1CC1 -# define ADC2_JEXTSEL_T1CC2 ADC12_CFGR_JEXTSEL_T1CC2 -# define ADC2_JEXTSEL_T1CC3 ADC12_CFGR_JEXTSEL_T1CC3 -# define ADC2_JEXTSEL_T1CC4 ADC12_CFGR_JEXTSEL_T1CC4 -# define ADC2_JEXTSEL_T1TRGO ADC12_CFGR_JEXTSEL_T1TRGO -# define ADC3_JEXTSEL_T1CC1 ADC34_CFGR_JEXTSEL_T1CC1 -# define ADC3_JEXTSEL_T1CC2 ADC34_CFGR_JEXTSEL_T1CC2 -# define ADC3_JEXTSEL_T1CC3 ADC34_CFGR_JEXTSEL_T1CC3 -# define ADC3_JEXTSEL_T1CC4 ADC34_CFGR_JEXTSEL_T1CC4 -# define ADC3_JEXTSEL_T1TRGO ADC34_CFGR_JEXTSEL_T1TRGO -# define ADC4_JEXTSEL_T1CC1 ADC34_CFGR_JEXTSEL_T1CC1 -# define ADC4_JEXTSEL_T1CC2 ADC34_CFGR_JEXTSEL_T1CC2 -# define ADC4_JEXTSEL_T1CC3 ADC34_CFGR_JEXTSEL_T1CC3 -# define ADC4_JEXTSEL_T1CC4 ADC34_CFGR_JEXTSEL_T1CC4 -# define ADC4_JEXTSEL_T1TRGO ADC34_CFGR_JEXTSEL_T1TRGO -# define ADC1_JEXTSEL_T2CC1 ADC12_CFGR_JEXTSEL_T2CC1 -# define ADC1_JEXTSEL_T2CC2 ADC12_CFGR_JEXTSEL_T2CC2 -# define ADC1_JEXTSEL_T2CC3 ADC12_CFGR_JEXTSEL_T2CC3 -# define ADC1_JEXTSEL_T2CC4 ADC12_CFGR_JEXTSEL_T2CC4 -# define ADC1_JEXTSEL_T2TRGO ADC12_CFGR_JEXTSEL_T2TRGO -# define ADC2_JEXTSEL_T2CC1 ADC12_CFGR_JEXTSEL_T2CC1 -# define ADC2_JEXTSEL_T2CC2 ADC12_CFGR_JEXTSEL_T2CC2 -# define ADC2_JEXTSEL_T2CC3 ADC12_CFGR_JEXTSEL_T2CC3 -# define ADC2_JEXTSEL_T2CC4 ADC12_CFGR_JEXTSEL_T2CC4 -# define ADC2_JEXTSEL_T2TRGO ADC12_CFGR_JEXTSEL_T2TRGO -# define ADC3_JEXTSEL_T2CC1 ADC34_CFGR_JEXTSEL_T2CC1 -# define ADC3_JEXTSEL_T2CC2 ADC34_CFGR_JEXTSEL_T2CC2 -# define ADC3_JEXTSEL_T2CC3 ADC34_CFGR_JEXTSEL_T2CC3 -# define ADC3_JEXTSEL_T2CC4 ADC34_CFGR_JEXTSEL_T2CC4 -# define ADC3_JEXTSEL_T2TRGO ADC34_CFGR_JEXTSEL_T2TRGO -# define ADC4_JEXTSEL_T2CC1 ADC34_CFGR_JEXTSEL_T2CC1 -# define ADC4_JEXTSEL_T2CC2 ADC34_CFGR_JEXTSEL_T2CC2 -# define ADC4_JEXTSEL_T2CC3 ADC34_CFGR_JEXTSEL_T2CC3 -# define ADC4_JEXTSEL_T2CC4 ADC34_CFGR_JEXTSEL_T2CC4 -# define ADC4_JEXTSEL_T2TRGO ADC34_CFGR_JEXTSEL_T2TRGO -# define ADC1_JEXTSEL_T3CC1 ADC12_CFGR_JEXTSEL_T3CC1 -# define ADC1_JEXTSEL_T3CC2 ADC12_CFGR_JEXTSEL_T3CC2 -# define ADC1_JEXTSEL_T3CC3 ADC12_CFGR_JEXTSEL_T3CC3 -# define ADC1_JEXTSEL_T3CC4 ADC12_CFGR_JEXTSEL_T3CC4 -# define ADC1_JEXTSEL_T3TRGO ADC12_CFGR_JEXTSEL_T3TRGO -# define ADC2_JEXTSEL_T3CC1 ADC12_CFGR_JEXTSEL_T3CC1 -# define ADC2_JEXTSEL_T3CC2 ADC12_CFGR_JEXTSEL_T3CC2 -# define ADC2_JEXTSEL_T3CC3 ADC12_CFGR_JEXTSEL_T3CC3 -# define ADC2_JEXTSEL_T3CC4 ADC12_CFGR_JEXTSEL_T3CC4 -# define ADC2_JEXTSEL_T3TRGO ADC12_CFGR_JEXTSEL_T3TRGO -# define ADC3_JEXTSEL_T3CC1 ADC34_CFGR_JEXTSEL_T3CC1 -# define ADC3_JEXTSEL_T3CC2 ADC34_CFGR_JEXTSEL_T3CC2 -# define ADC3_JEXTSEL_T3CC3 ADC34_CFGR_JEXTSEL_T3CC3 -# define ADC3_JEXTSEL_T3CC4 ADC34_CFGR_JEXTSEL_T3CC4 -# define ADC3_JEXTSEL_T3TRGO ADC34_CFGR_JEXTSEL_T3TRGO -# define ADC4_JEXTSEL_T3CC1 ADC34_CFGR_JEXTSEL_T3CC1 -# define ADC4_JEXTSEL_T3CC2 ADC34_CFGR_JEXTSEL_T3CC2 -# define ADC4_JEXTSEL_T3CC3 ADC34_CFGR_JEXTSEL_T3CC3 -# define ADC4_JEXTSEL_T3CC4 ADC34_CFGR_JEXTSEL_T3CC4 -# define ADC4_JEXTSEL_T3TRGO ADC34_CFGR_JEXTSEL_T3TRGO -# define ADC1_JEXTSEL_T4CC1 ADC12_CFGR_JEXTSEL_T4CC1 -# define ADC1_JEXTSEL_T4CC2 ADC12_CFGR_JEXTSEL_T4CC2 -# define ADC1_JEXTSEL_T4CC3 ADC12_CFGR_JEXTSEL_T4CC3 -# define ADC1_JEXTSEL_T4CC4 ADC12_CFGR_JEXTSEL_T4CC4 -# define ADC1_JEXTSEL_T4TRGO ADC12_CFGR_JEXTSEL_T4TRGO -# define ADC2_JEXTSEL_T4CC1 ADC12_CFGR_JEXTSEL_T4CC1 -# define ADC2_JEXTSEL_T4CC2 ADC12_CFGR_JEXTSEL_T4CC2 -# define ADC2_JEXTSEL_T4CC3 ADC12_CFGR_JEXTSEL_T4CC3 -# define ADC2_JEXTSEL_T4CC4 ADC12_CFGR_JEXTSEL_T4CC4 -# define ADC2_JEXTSEL_T4TRGO ADC12_CFGR_JEXTSEL_T4TRGO -# define ADC3_JEXTSEL_T4CC1 ADC34_CFGR_JEXTSEL_T4CC1 -# define ADC3_JEXTSEL_T4CC2 ADC34_CFGR_JEXTSEL_T4CC2 -# define ADC3_JEXTSEL_T4CC3 ADC34_CFGR_JEXTSEL_T4CC3 -# define ADC3_JEXTSEL_T4CC4 ADC34_CFGR_JEXTSEL_T4CC4 -# define ADC3_JEXTSEL_T4TRGO ADC34_CFGR_JEXTSEL_T4TRGO -# define ADC4_JEXTSEL_T4CC1 ADC34_CFGR_JEXTSEL_T4CC1 -# define ADC4_JEXTSEL_T4CC2 ADC34_CFGR_JEXTSEL_T4CC2 -# define ADC4_JEXTSEL_T4CC3 ADC34_CFGR_JEXTSEL_T4CC3 -# define ADC4_JEXTSEL_T4CC4 ADC34_CFGR_JEXTSEL_T4CC4 -# define ADC4_JEXTSEL_T4TRGO ADC34_CFGR_JEXTSEL_T4TRGO -# define ADC1_JEXTSEL_T5CC1 ADC12_CFGR_JEXTSEL_T5CC1 -# define ADC1_JEXTSEL_T5CC2 ADC12_CFGR_JEXTSEL_T5CC2 -# define ADC1_JEXTSEL_T5CC3 ADC12_CFGR_JEXTSEL_T5CC3 -# define ADC1_JEXTSEL_T5CC4 ADC12_CFGR_JEXTSEL_T5CC4 -# define ADC1_JEXTSEL_T5TRGO ADC12_CFGR_JEXTSEL_T5TRGO -# define ADC2_JEXTSEL_T5CC1 ADC12_CFGR_JEXTSEL_T5CC1 -# define ADC2_JEXTSEL_T5CC2 ADC12_CFGR_JEXTSEL_T5CC2 -# define ADC2_JEXTSEL_T5CC3 ADC12_CFGR_JEXTSEL_T5CC3 -# define ADC2_JEXTSEL_T5CC4 ADC12_CFGR_JEXTSEL_T5CC4 -# define ADC2_JEXTSEL_T5TRGO ADC12_CFGR_JEXTSEL_T5TRGO -# define ADC3_JEXTSEL_T5CC1 ADC34_CFGR_JEXTSEL_T5CC1 -# define ADC3_JEXTSEL_T5CC2 ADC34_CFGR_JEXTSEL_T5CC2 -# define ADC3_JEXTSEL_T5CC3 ADC34_CFGR_JEXTSEL_T5CC3 -# define ADC3_JEXTSEL_T5CC4 ADC34_CFGR_JEXTSEL_T5CC4 -# define ADC3_JEXTSEL_T5TRGO ADC34_CFGR_JEXTSEL_T5TRGO -# define ADC4_JEXTSEL_T5CC1 ADC34_CFGR_JEXTSEL_T5CC1 -# define ADC4_JEXTSEL_T5CC2 ADC34_CFGR_JEXTSEL_T5CC2 -# define ADC4_JEXTSEL_T5CC3 ADC34_CFGR_JEXTSEL_T5CC3 -# define ADC4_JEXTSEL_T5CC4 ADC34_CFGR_JEXTSEL_T5CC4 -# define ADC4_JEXTSEL_T5TRGO ADC34_CFGR_JEXTSEL_T5TRGO -# define ADC1_JEXTSEL_T6CC1 ADC12_CFGR_JEXTSEL_T6CC1 -# define ADC1_JEXTSEL_T6CC2 ADC12_CFGR_JEXTSEL_T6CC2 -# define ADC1_JEXTSEL_T6CC3 ADC12_CFGR_JEXTSEL_T6CC3 -# define ADC1_JEXTSEL_T6CC4 ADC12_CFGR_JEXTSEL_T6CC4 -# define ADC1_JEXTSEL_T6TRGO ADC12_CFGR_JEXTSEL_T6TRGO -# define ADC2_JEXTSEL_T6CC1 ADC12_CFGR_JEXTSEL_T6CC1 -# define ADC2_JEXTSEL_T6CC2 ADC12_CFGR_JEXTSEL_T6CC2 -# define ADC2_JEXTSEL_T6CC3 ADC12_CFGR_JEXTSEL_T6CC3 -# define ADC2_JEXTSEL_T6CC4 ADC12_CFGR_JEXTSEL_T6CC4 -# define ADC2_JEXTSEL_T6TRGO ADC12_CFGR_JEXTSEL_T6TRGO -# define ADC3_JEXTSEL_T6CC1 ADC34_CFGR_JEXTSEL_T6CC1 -# define ADC3_JEXTSEL_T6CC2 ADC34_CFGR_JEXTSEL_T6CC2 -# define ADC3_JEXTSEL_T6CC3 ADC34_CFGR_JEXTSEL_T6CC3 -# define ADC3_JEXTSEL_T6CC4 ADC34_CFGR_JEXTSEL_T6CC4 -# define ADC3_JEXTSEL_T6TRGO ADC34_CFGR_JEXTSEL_T6TRGO -# define ADC4_JEXTSEL_T6CC1 ADC34_CFGR_JEXTSEL_T6CC1 -# define ADC4_JEXTSEL_T6CC2 ADC34_CFGR_JEXTSEL_T6CC2 -# define ADC4_JEXTSEL_T6CC3 ADC34_CFGR_JEXTSEL_T6CC3 -# define ADC4_JEXTSEL_T6CC4 ADC34_CFGR_JEXTSEL_T6CC4 -# define ADC4_JEXTSEL_T6TRGO ADC34_CFGR_JEXTSEL_T6TRGO -# define ADC1_JEXTSEL_T7CC1 ADC12_CFGR_JEXTSEL_T7CC1 -# define ADC1_JEXTSEL_T7CC2 ADC12_CFGR_JEXTSEL_T7CC2 -# define ADC1_JEXTSEL_T7CC3 ADC12_CFGR_JEXTSEL_T7CC3 -# define ADC1_JEXTSEL_T7CC4 ADC12_CFGR_JEXTSEL_T7CC4 -# define ADC1_JEXTSEL_T7TRGO ADC12_CFGR_JEXTSEL_T7TRGO -# define ADC2_JEXTSEL_T7CC1 ADC12_CFGR_JEXTSEL_T7CC1 -# define ADC2_JEXTSEL_T7CC2 ADC12_CFGR_JEXTSEL_T7CC2 -# define ADC2_JEXTSEL_T7CC3 ADC12_CFGR_JEXTSEL_T7CC3 -# define ADC2_JEXTSEL_T7CC4 ADC12_CFGR_JEXTSEL_T7CC4 -# define ADC2_JEXTSEL_T7TRGO ADC12_CFGR_JEXTSEL_T7TRGO -# define ADC3_JEXTSEL_T7CC1 ADC34_CFGR_JEXTSEL_T7CC1 -# define ADC3_JEXTSEL_T7CC2 ADC34_CFGR_JEXTSEL_T7CC2 -# define ADC3_JEXTSEL_T7CC3 ADC34_CFGR_JEXTSEL_T7CC3 -# define ADC3_JEXTSEL_T7CC4 ADC34_CFGR_JEXTSEL_T7CC4 -# define ADC3_JEXTSEL_T7TRGO ADC34_CFGR_JEXTSEL_T7TRGO -# define ADC4_JEXTSEL_T7CC1 ADC34_CFGR_JEXTSEL_T7CC1 -# define ADC4_JEXTSEL_T7CC2 ADC34_CFGR_JEXTSEL_T7CC2 -# define ADC4_JEXTSEL_T7CC3 ADC34_CFGR_JEXTSEL_T7CC3 -# define ADC4_JEXTSEL_T7CC4 ADC34_CFGR_JEXTSEL_T7CC4 -# define ADC4_JEXTSEL_T7TRGO ADC34_CFGR_JEXTSEL_T7TRGO -# define ADC1_JEXTSEL_T8CC1 ADC12_CFGR_JEXTSEL_T8CC1 -# define ADC1_JEXTSEL_T8CC2 ADC12_CFGR_JEXTSEL_T8CC2 -# define ADC1_JEXTSEL_T8CC3 ADC12_CFGR_JEXTSEL_T8CC3 -# define ADC1_JEXTSEL_T8CC4 ADC12_CFGR_JEXTSEL_T8CC4 -# define ADC1_JEXTSEL_T8TRGO ADC12_CFGR_JEXTSEL_T8TRGO -# define ADC2_JEXTSEL_T8CC1 ADC12_CFGR_JEXTSEL_T8CC1 -# define ADC2_JEXTSEL_T8CC2 ADC12_CFGR_JEXTSEL_T8CC2 -# define ADC2_JEXTSEL_T8CC3 ADC12_CFGR_JEXTSEL_T8CC3 -# define ADC2_JEXTSEL_T8CC4 ADC12_CFGR_JEXTSEL_T8CC4 -# define ADC2_JEXTSEL_T8TRGO ADC12_CFGR_JEXTSEL_T8TRGO -# define ADC3_JEXTSEL_T8CC1 ADC34_CFGR_JEXTSEL_T8CC1 -# define ADC3_JEXTSEL_T8CC2 ADC34_CFGR_JEXTSEL_T8CC2 -# define ADC3_JEXTSEL_T8CC3 ADC34_CFGR_JEXTSEL_T8CC3 -# define ADC3_JEXTSEL_T8CC4 ADC34_CFGR_JEXTSEL_T8CC4 -# define ADC3_JEXTSEL_T8TRGO ADC34_CFGR_JEXTSEL_T8TRGO -# define ADC4_JEXTSEL_T8CC1 ADC34_CFGR_JEXTSEL_T8CC1 -# define ADC4_JEXTSEL_T8CC2 ADC34_CFGR_JEXTSEL_T8CC2 -# define ADC4_JEXTSEL_T8CC3 ADC34_CFGR_JEXTSEL_T8CC3 -# define ADC4_JEXTSEL_T8CC4 ADC34_CFGR_JEXTSEL_T8CC4 -# define ADC4_JEXTSEL_T8TRGO ADC34_CFGR_JEXTSEL_T8TRGO -# define ADC1_JEXTSEL_T9CC1 ADC12_CFGR_JEXTSEL_T9CC1 -# define ADC1_JEXTSEL_T9CC2 ADC12_CFGR_JEXTSEL_T9CC2 -# define ADC1_JEXTSEL_T9CC3 ADC12_CFGR_JEXTSEL_T9CC3 -# define ADC1_JEXTSEL_T9CC4 ADC12_CFGR_JEXTSEL_T9CC4 -# define ADC1_JEXTSEL_T9TRGO ADC12_CFGR_JEXTSEL_T9TRGO -# define ADC2_JEXTSEL_T9CC1 ADC12_CFGR_JEXTSEL_T9CC1 -# define ADC2_JEXTSEL_T9CC2 ADC12_CFGR_JEXTSEL_T9CC2 -# define ADC2_JEXTSEL_T9CC3 ADC12_CFGR_JEXTSEL_T9CC3 -# define ADC2_JEXTSEL_T9CC4 ADC12_CFGR_JEXTSEL_T9CC4 -# define ADC2_JEXTSEL_T9TRGO ADC12_CFGR_JEXTSEL_T9TRGO -# define ADC3_JEXTSEL_T9CC1 ADC34_CFGR_JEXTSEL_T9CC1 -# define ADC3_JEXTSEL_T9CC2 ADC34_CFGR_JEXTSEL_T9CC2 -# define ADC3_JEXTSEL_T9CC3 ADC34_CFGR_JEXTSEL_T9CC3 -# define ADC3_JEXTSEL_T9CC4 ADC34_CFGR_JEXTSEL_T9CC4 -# define ADC3_JEXTSEL_T9TRGO ADC34_CFGR_JEXTSEL_T9TRGO -# define ADC4_JEXTSEL_T9CC1 ADC34_CFGR_JEXTSEL_T9CC1 -# define ADC4_JEXTSEL_T9CC2 ADC34_CFGR_JEXTSEL_T9CC2 -# define ADC4_JEXTSEL_T9CC3 ADC34_CFGR_JEXTSEL_T9CC3 -# define ADC4_JEXTSEL_T9CC4 ADC34_CFGR_JEXTSEL_T9CC4 -# define ADC4_JEXTSEL_T9TRGO ADC34_CFGR_JEXTSEL_T9TRGO -# define ADC1_JEXTSEL_T10CC1 ADC12_CFGR_JEXTSEL_T10CC1 -# define ADC1_JEXTSEL_T10CC2 ADC12_CFGR_JEXTSEL_T10CC2 -# define ADC1_JEXTSEL_T10CC3 ADC12_CFGR_JEXTSEL_T10CC3 -# define ADC1_JEXTSEL_T10CC4 ADC12_CFGR_JEXTSEL_T10CC4 -# define ADC1_JEXTSEL_T10TRGO ADC12_CFGR_JEXTSEL_T10TRGO -# define ADC2_JEXTSEL_T10CC1 ADC12_CFGR_JEXTSEL_T10CC1 -# define ADC2_JEXTSEL_T10CC2 ADC12_CFGR_JEXTSEL_T10CC2 -# define ADC2_JEXTSEL_T10CC3 ADC12_CFGR_JEXTSEL_T10CC3 -# define ADC2_JEXTSEL_T10CC4 ADC12_CFGR_JEXTSEL_T10CC4 -# define ADC2_JEXTSEL_T10TRGO ADC12_CFGR_JEXTSEL_T10TRGO -# define ADC3_JEXTSEL_T10CC1 ADC34_CFGR_JEXTSEL_T10CC1 -# define ADC3_JEXTSEL_T10CC2 ADC34_CFGR_JEXTSEL_T10CC2 -# define ADC3_JEXTSEL_T10CC3 ADC34_CFGR_JEXTSEL_T10CC3 -# define ADC3_JEXTSEL_T10CC4 ADC34_CFGR_JEXTSEL_T10CC4 -# define ADC3_JEXTSEL_T10TRGO ADC34_CFGR_JEXTSEL_T10TRGO -# define ADC4_JEXTSEL_T10CC1 ADC34_CFGR_JEXTSEL_T10CC1 -# define ADC4_JEXTSEL_T10CC2 ADC34_CFGR_JEXTSEL_T10CC2 -# define ADC4_JEXTSEL_T10CC3 ADC34_CFGR_JEXTSEL_T10CC3 -# define ADC4_JEXTSEL_T10CC4 ADC34_CFGR_JEXTSEL_T10CC4 -# define ADC4_JEXTSEL_T10TRGO ADC34_CFGR_JEXTSEL_T10TRGO -# define ADC1_JEXTSEL_T15CC1 ADC12_CFGR_JEXTSEL_T15CC1 -# define ADC1_JEXTSEL_T15CC2 ADC12_CFGR_JEXTSEL_T15CC2 -# define ADC1_JEXTSEL_T15CC3 ADC12_CFGR_JEXTSEL_T15CC3 -# define ADC1_JEXTSEL_T15CC4 ADC12_CFGR_JEXTSEL_T15CC4 -# define ADC1_JEXTSEL_T15TRGO ADC12_CFGR_JEXTSEL_T15TRGO -# define ADC2_JEXTSEL_T15CC1 ADC12_CFGR_JEXTSEL_T15CC1 -# define ADC2_JEXTSEL_T15CC2 ADC12_CFGR_JEXTSEL_T15CC2 -# define ADC2_JEXTSEL_T15CC3 ADC12_CFGR_JEXTSEL_T15CC3 -# define ADC2_JEXTSEL_T15CC4 ADC12_CFGR_JEXTSEL_T15CC4 -# define ADC2_JEXTSEL_T15TRGO ADC12_CFGR_JEXTSEL_T15TRGO -# define ADC3_JEXTSEL_T15CC1 ADC34_CFGR_JEXTSEL_T15CC1 -# define ADC3_JEXTSEL_T15CC2 ADC34_CFGR_JEXTSEL_T15CC2 -# define ADC3_JEXTSEL_T15CC3 ADC34_CFGR_JEXTSEL_T15CC3 -# define ADC3_JEXTSEL_T15CC4 ADC34_CFGR_JEXTSEL_T15CC4 -# define ADC3_JEXTSEL_T15TRGO ADC34_CFGR_JEXTSEL_T15TRGO -# define ADC4_JEXTSEL_T15CC1 ADC34_CFGR_JEXTSEL_T15CC1 -# define ADC4_JEXTSEL_T15CC2 ADC34_CFGR_JEXTSEL_T15CC2 -# define ADC4_JEXTSEL_T15CC3 ADC34_CFGR_JEXTSEL_T15CC3 -# define ADC4_JEXTSEL_T15CC4 ADC34_CFGR_JEXTSEL_T15CC4 -# define ADC4_JEXTSEL_T15TRGO ADC34_CFGR_JEXTSEL_T15TRGO -# define ADC1_JEXTSEL_T20CC1 ADC12_CFGR_JEXTSEL_T20CC1 -# define ADC1_JEXTSEL_T20CC2 ADC12_CFGR_JEXTSEL_T20CC2 -# define ADC1_JEXTSEL_T20CC3 ADC12_CFGR_JEXTSEL_T20CC3 -# define ADC1_JEXTSEL_T20CC4 ADC12_CFGR_JEXTSEL_T20CC4 -# define ADC1_JEXTSEL_T20TRGO ADC12_CFGR_JEXTSEL_T20TRGO -# define ADC2_JEXTSEL_T20CC1 ADC12_CFGR_JEXTSEL_T20CC1 -# define ADC2_JEXTSEL_T20CC2 ADC12_CFGR_JEXTSEL_T20CC2 -# define ADC2_JEXTSEL_T20CC3 ADC12_CFGR_JEXTSEL_T20CC3 -# define ADC2_JEXTSEL_T20CC4 ADC12_CFGR_JEXTSEL_T20CC4 -# define ADC2_JEXTSEL_T20TRGO ADC12_CFGR_JEXTSEL_T20TRGO -# define ADC3_JEXTSEL_T20CC1 ADC34_CFGR_JEXTSEL_T20CC1 -# define ADC3_JEXTSEL_T20CC2 ADC34_CFGR_JEXTSEL_T20CC2 -# define ADC3_JEXTSEL_T20CC3 ADC34_CFGR_JEXTSEL_T20CC3 -# define ADC3_JEXTSEL_T20CC4 ADC34_CFGR_JEXTSEL_T20CC4 -# define ADC3_JEXTSEL_T20TRGO ADC34_CFGR_JEXTSEL_T20TRGO -# define ADC4_JEXTSEL_T20CC1 ADC34_CFGR_JEXTSEL_T20CC1 -# define ADC4_JEXTSEL_T20CC2 ADC34_CFGR_JEXTSEL_T20CC2 -# define ADC4_JEXTSEL_T20CC3 ADC34_CFGR_JEXTSEL_T20CC3 -# define ADC4_JEXTSEL_T20CC4 ADC34_CFGR_JEXTSEL_T20CC4 -# define ADC4_JEXTSEL_T20TRGO ADC34_CFGR_JEXTSEL_T20TRGO -# define ADC1_JEXTSEL_HRTTRG2 ADC12_CFGR_JEXTSEL_HRT1TRG2 -# define ADC1_JEXTSEL_HRTTRG4 ADC12_CFGR_JEXTSEL_HRT1TRG4 -# define ADC2_JEXTSEL_HRTTRG2 ADC12_CFGR_JEXTSEL_HRT1TRG2 -# define ADC2_JEXTSEL_HRTTRG4 ADC12_CFGR_JEXTSEL_HRT1TRG4 +# define ADC1_JEXTSEL_T1CC1 ADC12_JSQR_JEXTSEL_T1CC1 +# define ADC1_JEXTSEL_T1CC2 ADC12_JSQR_JEXTSEL_T1CC2 +# define ADC1_JEXTSEL_T1CC3 ADC12_JSQR_JEXTSEL_T1CC3 +# define ADC1_JEXTSEL_T1CC4 ADC12_JSQR_JEXTSEL_T1CC4 +# define ADC1_JEXTSEL_T1TRGO ADC12_JSQR_JEXTSEL_T1TRGO +# define ADC2_JEXTSEL_T1CC1 ADC12_JSQR_JEXTSEL_T1CC1 +# define ADC2_JEXTSEL_T1CC2 ADC12_JSQR_JEXTSEL_T1CC2 +# define ADC2_JEXTSEL_T1CC3 ADC12_JSQR_JEXTSEL_T1CC3 +# define ADC2_JEXTSEL_T1CC4 ADC12_JSQR_JEXTSEL_T1CC4 +# define ADC2_JEXTSEL_T1TRGO ADC12_JSQR_JEXTSEL_T1TRGO +# define ADC3_JEXTSEL_T1CC1 ADC34_JSQR_JEXTSEL_T1CC1 +# define ADC3_JEXTSEL_T1CC2 ADC34_JSQR_JEXTSEL_T1CC2 +# define ADC3_JEXTSEL_T1CC3 ADC34_JSQR_JEXTSEL_T1CC3 +# define ADC3_JEXTSEL_T1CC4 ADC34_JSQR_JEXTSEL_T1CC4 +# define ADC3_JEXTSEL_T1TRGO ADC34_JSQR_JEXTSEL_T1TRGO +# define ADC4_JEXTSEL_T1CC1 ADC34_JSQR_JEXTSEL_T1CC1 +# define ADC4_JEXTSEL_T1CC2 ADC34_JSQR_JEXTSEL_T1CC2 +# define ADC4_JEXTSEL_T1CC3 ADC34_JSQR_JEXTSEL_T1CC3 +# define ADC4_JEXTSEL_T1CC4 ADC34_JSQR_JEXTSEL_T1CC4 +# define ADC4_JEXTSEL_T1TRGO ADC34_JSQR_JEXTSEL_T1TRGO +# define ADC1_JEXTSEL_T2CC1 ADC12_JSQR_JEXTSEL_T2CC1 +# define ADC1_JEXTSEL_T2CC2 ADC12_JSQR_JEXTSEL_T2CC2 +# define ADC1_JEXTSEL_T2CC3 ADC12_JSQR_JEXTSEL_T2CC3 +# define ADC1_JEXTSEL_T2CC4 ADC12_JSQR_JEXTSEL_T2CC4 +# define ADC1_JEXTSEL_T2TRGO ADC12_JSQR_JEXTSEL_T2TRGO +# define ADC2_JEXTSEL_T2CC1 ADC12_JSQR_JEXTSEL_T2CC1 +# define ADC2_JEXTSEL_T2CC2 ADC12_JSQR_JEXTSEL_T2CC2 +# define ADC2_JEXTSEL_T2CC3 ADC12_JSQR_JEXTSEL_T2CC3 +# define ADC2_JEXTSEL_T2CC4 ADC12_JSQR_JEXTSEL_T2CC4 +# define ADC2_JEXTSEL_T2TRGO ADC12_JSQR_JEXTSEL_T2TRGO +# define ADC3_JEXTSEL_T2CC1 ADC34_JSQR_JEXTSEL_T2CC1 +# define ADC3_JEXTSEL_T2CC2 ADC34_JSQR_JEXTSEL_T2CC2 +# define ADC3_JEXTSEL_T2CC3 ADC34_JSQR_JEXTSEL_T2CC3 +# define ADC3_JEXTSEL_T2CC4 ADC34_JSQR_JEXTSEL_T2CC4 +# define ADC3_JEXTSEL_T2TRGO ADC34_JSQR_JEXTSEL_T2TRGO +# define ADC4_JEXTSEL_T2CC1 ADC34_JSQR_JEXTSEL_T2CC1 +# define ADC4_JEXTSEL_T2CC2 ADC34_JSQR_JEXTSEL_T2CC2 +# define ADC4_JEXTSEL_T2CC3 ADC34_JSQR_JEXTSEL_T2CC3 +# define ADC4_JEXTSEL_T2CC4 ADC34_JSQR_JEXTSEL_T2CC4 +# define ADC4_JEXTSEL_T2TRGO ADC34_JSQR_JEXTSEL_T2TRGO +# define ADC1_JEXTSEL_T3CC1 ADC12_JSQR_JEXTSEL_T3CC1 +# define ADC1_JEXTSEL_T3CC2 ADC12_JSQR_JEXTSEL_T3CC2 +# define ADC1_JEXTSEL_T3CC3 ADC12_JSQR_JEXTSEL_T3CC3 +# define ADC1_JEXTSEL_T3CC4 ADC12_JSQR_JEXTSEL_T3CC4 +# define ADC1_JEXTSEL_T3TRGO ADC12_JSQR_JEXTSEL_T3TRGO +# define ADC2_JEXTSEL_T3CC1 ADC12_JSQR_JEXTSEL_T3CC1 +# define ADC2_JEXTSEL_T3CC2 ADC12_JSQR_JEXTSEL_T3CC2 +# define ADC2_JEXTSEL_T3CC3 ADC12_JSQR_JEXTSEL_T3CC3 +# define ADC2_JEXTSEL_T3CC4 ADC12_JSQR_JEXTSEL_T3CC4 +# define ADC2_JEXTSEL_T3TRGO ADC12_JSQR_JEXTSEL_T3TRGO +# define ADC3_JEXTSEL_T3CC1 ADC34_JSQR_JEXTSEL_T3CC1 +# define ADC3_JEXTSEL_T3CC2 ADC34_JSQR_JEXTSEL_T3CC2 +# define ADC3_JEXTSEL_T3CC3 ADC34_JSQR_JEXTSEL_T3CC3 +# define ADC3_JEXTSEL_T3CC4 ADC34_JSQR_JEXTSEL_T3CC4 +# define ADC3_JEXTSEL_T3TRGO ADC34_JSQR_JEXTSEL_T3TRGO +# define ADC4_JEXTSEL_T3CC1 ADC34_JSQR_JEXTSEL_T3CC1 +# define ADC4_JEXTSEL_T3CC2 ADC34_JSQR_JEXTSEL_T3CC2 +# define ADC4_JEXTSEL_T3CC3 ADC34_JSQR_JEXTSEL_T3CC3 +# define ADC4_JEXTSEL_T3CC4 ADC34_JSQR_JEXTSEL_T3CC4 +# define ADC4_JEXTSEL_T3TRGO ADC34_JSQR_JEXTSEL_T3TRGO +# define ADC1_JEXTSEL_T4CC1 ADC12_JSQR_JEXTSEL_T4CC1 +# define ADC1_JEXTSEL_T4CC2 ADC12_JSQR_JEXTSEL_T4CC2 +# define ADC1_JEXTSEL_T4CC3 ADC12_JSQR_JEXTSEL_T4CC3 +# define ADC1_JEXTSEL_T4CC4 ADC12_JSQR_JEXTSEL_T4CC4 +# define ADC1_JEXTSEL_T4TRGO ADC12_JSQR_JEXTSEL_T4TRGO +# define ADC2_JEXTSEL_T4CC1 ADC12_JSQR_JEXTSEL_T4CC1 +# define ADC2_JEXTSEL_T4CC2 ADC12_JSQR_JEXTSEL_T4CC2 +# define ADC2_JEXTSEL_T4CC3 ADC12_JSQR_JEXTSEL_T4CC3 +# define ADC2_JEXTSEL_T4CC4 ADC12_JSQR_JEXTSEL_T4CC4 +# define ADC2_JEXTSEL_T4TRGO ADC12_JSQR_JEXTSEL_T4TRGO +# define ADC3_JEXTSEL_T4CC1 ADC34_JSQR_JEXTSEL_T4CC1 +# define ADC3_JEXTSEL_T4CC2 ADC34_JSQR_JEXTSEL_T4CC2 +# define ADC3_JEXTSEL_T4CC3 ADC34_JSQR_JEXTSEL_T4CC3 +# define ADC3_JEXTSEL_T4CC4 ADC34_JSQR_JEXTSEL_T4CC4 +# define ADC3_JEXTSEL_T4TRGO ADC34_JSQR_JEXTSEL_T4TRGO +# define ADC4_JEXTSEL_T4CC1 ADC34_JSQR_JEXTSEL_T4CC1 +# define ADC4_JEXTSEL_T4CC2 ADC34_JSQR_JEXTSEL_T4CC2 +# define ADC4_JEXTSEL_T4CC3 ADC34_JSQR_JEXTSEL_T4CC3 +# define ADC4_JEXTSEL_T4CC4 ADC34_JSQR_JEXTSEL_T4CC4 +# define ADC4_JEXTSEL_T4TRGO ADC34_JSQR_JEXTSEL_T4TRGO +# define ADC1_JEXTSEL_T5CC1 ADC12_JSQR_JEXTSEL_T5CC1 +# define ADC1_JEXTSEL_T5CC2 ADC12_JSQR_JEXTSEL_T5CC2 +# define ADC1_JEXTSEL_T5CC3 ADC12_JSQR_JEXTSEL_T5CC3 +# define ADC1_JEXTSEL_T5CC4 ADC12_JSQR_JEXTSEL_T5CC4 +# define ADC1_JEXTSEL_T5TRGO ADC12_JSQR_JEXTSEL_T5TRGO +# define ADC2_JEXTSEL_T5CC1 ADC12_JSQR_JEXTSEL_T5CC1 +# define ADC2_JEXTSEL_T5CC2 ADC12_JSQR_JEXTSEL_T5CC2 +# define ADC2_JEXTSEL_T5CC3 ADC12_JSQR_JEXTSEL_T5CC3 +# define ADC2_JEXTSEL_T5CC4 ADC12_JSQR_JEXTSEL_T5CC4 +# define ADC2_JEXTSEL_T5TRGO ADC12_JSQR_JEXTSEL_T5TRGO +# define ADC3_JEXTSEL_T5CC1 ADC34_JSQR_JEXTSEL_T5CC1 +# define ADC3_JEXTSEL_T5CC2 ADC34_JSQR_JEXTSEL_T5CC2 +# define ADC3_JEXTSEL_T5CC3 ADC34_JSQR_JEXTSEL_T5CC3 +# define ADC3_JEXTSEL_T5CC4 ADC34_JSQR_JEXTSEL_T5CC4 +# define ADC3_JEXTSEL_T5TRGO ADC34_JSQR_JEXTSEL_T5TRGO +# define ADC4_JEXTSEL_T5CC1 ADC34_JSQR_JEXTSEL_T5CC1 +# define ADC4_JEXTSEL_T5CC2 ADC34_JSQR_JEXTSEL_T5CC2 +# define ADC4_JEXTSEL_T5CC3 ADC34_JSQR_JEXTSEL_T5CC3 +# define ADC4_JEXTSEL_T5CC4 ADC34_JSQR_JEXTSEL_T5CC4 +# define ADC4_JEXTSEL_T5TRGO ADC34_JSQR_JEXTSEL_T5TRGO +# define ADC1_JEXTSEL_T6CC1 ADC12_JSQR_JEXTSEL_T6CC1 +# define ADC1_JEXTSEL_T6CC2 ADC12_JSQR_JEXTSEL_T6CC2 +# define ADC1_JEXTSEL_T6CC3 ADC12_JSQR_JEXTSEL_T6CC3 +# define ADC1_JEXTSEL_T6CC4 ADC12_JSQR_JEXTSEL_T6CC4 +# define ADC1_JEXTSEL_T6TRGO ADC12_JSQR_JEXTSEL_T6TRGO +# define ADC2_JEXTSEL_T6CC1 ADC12_JSQR_JEXTSEL_T6CC1 +# define ADC2_JEXTSEL_T6CC2 ADC12_JSQR_JEXTSEL_T6CC2 +# define ADC2_JEXTSEL_T6CC3 ADC12_JSQR_JEXTSEL_T6CC3 +# define ADC2_JEXTSEL_T6CC4 ADC12_JSQR_JEXTSEL_T6CC4 +# define ADC2_JEXTSEL_T6TRGO ADC12_JSQR_JEXTSEL_T6TRGO +# define ADC3_JEXTSEL_T6CC1 ADC34_JSQR_JEXTSEL_T6CC1 +# define ADC3_JEXTSEL_T6CC2 ADC34_JSQR_JEXTSEL_T6CC2 +# define ADC3_JEXTSEL_T6CC3 ADC34_JSQR_JEXTSEL_T6CC3 +# define ADC3_JEXTSEL_T6CC4 ADC34_JSQR_JEXTSEL_T6CC4 +# define ADC3_JEXTSEL_T6TRGO ADC34_JSQR_JEXTSEL_T6TRGO +# define ADC4_JEXTSEL_T6CC1 ADC34_JSQR_JEXTSEL_T6CC1 +# define ADC4_JEXTSEL_T6CC2 ADC34_JSQR_JEXTSEL_T6CC2 +# define ADC4_JEXTSEL_T6CC3 ADC34_JSQR_JEXTSEL_T6CC3 +# define ADC4_JEXTSEL_T6CC4 ADC34_JSQR_JEXTSEL_T6CC4 +# define ADC4_JEXTSEL_T6TRGO ADC34_JSQR_JEXTSEL_T6TRGO +# define ADC1_JEXTSEL_T7CC1 ADC12_JSQR_JEXTSEL_T7CC1 +# define ADC1_JEXTSEL_T7CC2 ADC12_JSQR_JEXTSEL_T7CC2 +# define ADC1_JEXTSEL_T7CC3 ADC12_JSQR_JEXTSEL_T7CC3 +# define ADC1_JEXTSEL_T7CC4 ADC12_JSQR_JEXTSEL_T7CC4 +# define ADC1_JEXTSEL_T7TRGO ADC12_JSQR_JEXTSEL_T7TRGO +# define ADC2_JEXTSEL_T7CC1 ADC12_JSQR_JEXTSEL_T7CC1 +# define ADC2_JEXTSEL_T7CC2 ADC12_JSQR_JEXTSEL_T7CC2 +# define ADC2_JEXTSEL_T7CC3 ADC12_JSQR_JEXTSEL_T7CC3 +# define ADC2_JEXTSEL_T7CC4 ADC12_JSQR_JEXTSEL_T7CC4 +# define ADC2_JEXTSEL_T7TRGO ADC12_JSQR_JEXTSEL_T7TRGO +# define ADC3_JEXTSEL_T7CC1 ADC34_JSQR_JEXTSEL_T7CC1 +# define ADC3_JEXTSEL_T7CC2 ADC34_JSQR_JEXTSEL_T7CC2 +# define ADC3_JEXTSEL_T7CC3 ADC34_JSQR_JEXTSEL_T7CC3 +# define ADC3_JEXTSEL_T7CC4 ADC34_JSQR_JEXTSEL_T7CC4 +# define ADC3_JEXTSEL_T7TRGO ADC34_JSQR_JEXTSEL_T7TRGO +# define ADC4_JEXTSEL_T7CC1 ADC34_JSQR_JEXTSEL_T7CC1 +# define ADC4_JEXTSEL_T7CC2 ADC34_JSQR_JEXTSEL_T7CC2 +# define ADC4_JEXTSEL_T7CC3 ADC34_JSQR_JEXTSEL_T7CC3 +# define ADC4_JEXTSEL_T7CC4 ADC34_JSQR_JEXTSEL_T7CC4 +# define ADC4_JEXTSEL_T7TRGO ADC34_JSQR_JEXTSEL_T7TRGO +# define ADC1_JEXTSEL_T8CC1 ADC12_JSQR_JEXTSEL_T8CC1 +# define ADC1_JEXTSEL_T8CC2 ADC12_JSQR_JEXTSEL_T8CC2 +# define ADC1_JEXTSEL_T8CC3 ADC12_JSQR_JEXTSEL_T8CC3 +# define ADC1_JEXTSEL_T8CC4 ADC12_JSQR_JEXTSEL_T8CC4 +# define ADC1_JEXTSEL_T8TRGO ADC12_JSQR_JEXTSEL_T8TRGO +# define ADC2_JEXTSEL_T8CC1 ADC12_JSQR_JEXTSEL_T8CC1 +# define ADC2_JEXTSEL_T8CC2 ADC12_JSQR_JEXTSEL_T8CC2 +# define ADC2_JEXTSEL_T8CC3 ADC12_JSQR_JEXTSEL_T8CC3 +# define ADC2_JEXTSEL_T8CC4 ADC12_JSQR_JEXTSEL_T8CC4 +# define ADC2_JEXTSEL_T8TRGO ADC12_JSQR_JEXTSEL_T8TRGO +# define ADC3_JEXTSEL_T8CC1 ADC34_JSQR_JEXTSEL_T8CC1 +# define ADC3_JEXTSEL_T8CC2 ADC34_JSQR_JEXTSEL_T8CC2 +# define ADC3_JEXTSEL_T8CC3 ADC34_JSQR_JEXTSEL_T8CC3 +# define ADC3_JEXTSEL_T8CC4 ADC34_JSQR_JEXTSEL_T8CC4 +# define ADC3_JEXTSEL_T8TRGO ADC34_JSQR_JEXTSEL_T8TRGO +# define ADC4_JEXTSEL_T8CC1 ADC34_JSQR_JEXTSEL_T8CC1 +# define ADC4_JEXTSEL_T8CC2 ADC34_JSQR_JEXTSEL_T8CC2 +# define ADC4_JEXTSEL_T8CC3 ADC34_JSQR_JEXTSEL_T8CC3 +# define ADC4_JEXTSEL_T8CC4 ADC34_JSQR_JEXTSEL_T8CC4 +# define ADC4_JEXTSEL_T8TRGO ADC34_JSQR_JEXTSEL_T8TRGO +# define ADC1_JEXTSEL_T9CC1 ADC12_JSQR_JEXTSEL_T9CC1 +# define ADC1_JEXTSEL_T9CC2 ADC12_JSQR_JEXTSEL_T9CC2 +# define ADC1_JEXTSEL_T9CC3 ADC12_JSQR_JEXTSEL_T9CC3 +# define ADC1_JEXTSEL_T9CC4 ADC12_JSQR_JEXTSEL_T9CC4 +# define ADC1_JEXTSEL_T9TRGO ADC12_JSQR_JEXTSEL_T9TRGO +# define ADC2_JEXTSEL_T9CC1 ADC12_JSQR_JEXTSEL_T9CC1 +# define ADC2_JEXTSEL_T9CC2 ADC12_JSQR_JEXTSEL_T9CC2 +# define ADC2_JEXTSEL_T9CC3 ADC12_JSQR_JEXTSEL_T9CC3 +# define ADC2_JEXTSEL_T9CC4 ADC12_JSQR_JEXTSEL_T9CC4 +# define ADC2_JEXTSEL_T9TRGO ADC12_JSQR_JEXTSEL_T9TRGO +# define ADC3_JEXTSEL_T9CC1 ADC34_JSQR_JEXTSEL_T9CC1 +# define ADC3_JEXTSEL_T9CC2 ADC34_JSQR_JEXTSEL_T9CC2 +# define ADC3_JEXTSEL_T9CC3 ADC34_JSQR_JEXTSEL_T9CC3 +# define ADC3_JEXTSEL_T9CC4 ADC34_JSQR_JEXTSEL_T9CC4 +# define ADC3_JEXTSEL_T9TRGO ADC34_JSQR_JEXTSEL_T9TRGO +# define ADC4_JEXTSEL_T9CC1 ADC34_JSQR_JEXTSEL_T9CC1 +# define ADC4_JEXTSEL_T9CC2 ADC34_JSQR_JEXTSEL_T9CC2 +# define ADC4_JEXTSEL_T9CC3 ADC34_JSQR_JEXTSEL_T9CC3 +# define ADC4_JEXTSEL_T9CC4 ADC34_JSQR_JEXTSEL_T9CC4 +# define ADC4_JEXTSEL_T9TRGO ADC34_JSQR_JEXTSEL_T9TRGO +# define ADC1_JEXTSEL_T10CC1 ADC12_JSQR_JEXTSEL_T10CC1 +# define ADC1_JEXTSEL_T10CC2 ADC12_JSQR_JEXTSEL_T10CC2 +# define ADC1_JEXTSEL_T10CC3 ADC12_JSQR_JEXTSEL_T10CC3 +# define ADC1_JEXTSEL_T10CC4 ADC12_JSQR_JEXTSEL_T10CC4 +# define ADC1_JEXTSEL_T10TRGO ADC12_JSQR_JEXTSEL_T10TRGO +# define ADC2_JEXTSEL_T10CC1 ADC12_JSQR_JEXTSEL_T10CC1 +# define ADC2_JEXTSEL_T10CC2 ADC12_JSQR_JEXTSEL_T10CC2 +# define ADC2_JEXTSEL_T10CC3 ADC12_JSQR_JEXTSEL_T10CC3 +# define ADC2_JEXTSEL_T10CC4 ADC12_JSQR_JEXTSEL_T10CC4 +# define ADC2_JEXTSEL_T10TRGO ADC12_JSQR_JEXTSEL_T10TRGO +# define ADC3_JEXTSEL_T10CC1 ADC34_JSQR_JEXTSEL_T10CC1 +# define ADC3_JEXTSEL_T10CC2 ADC34_JSQR_JEXTSEL_T10CC2 +# define ADC3_JEXTSEL_T10CC3 ADC34_JSQR_JEXTSEL_T10CC3 +# define ADC3_JEXTSEL_T10CC4 ADC34_JSQR_JEXTSEL_T10CC4 +# define ADC3_JEXTSEL_T10TRGO ADC34_JSQR_JEXTSEL_T10TRGO +# define ADC4_JEXTSEL_T10CC1 ADC34_JSQR_JEXTSEL_T10CC1 +# define ADC4_JEXTSEL_T10CC2 ADC34_JSQR_JEXTSEL_T10CC2 +# define ADC4_JEXTSEL_T10CC3 ADC34_JSQR_JEXTSEL_T10CC3 +# define ADC4_JEXTSEL_T10CC4 ADC34_JSQR_JEXTSEL_T10CC4 +# define ADC4_JEXTSEL_T10TRGO ADC34_JSQR_JEXTSEL_T10TRGO +# define ADC1_JEXTSEL_T15CC1 ADC12_JSQR_JEXTSEL_T15CC1 +# define ADC1_JEXTSEL_T15CC2 ADC12_JSQR_JEXTSEL_T15CC2 +# define ADC1_JEXTSEL_T15CC3 ADC12_JSQR_JEXTSEL_T15CC3 +# define ADC1_JEXTSEL_T15CC4 ADC12_JSQR_JEXTSEL_T15CC4 +# define ADC1_JEXTSEL_T15TRGO ADC12_JSQR_JEXTSEL_T15TRGO +# define ADC2_JEXTSEL_T15CC1 ADC12_JSQR_JEXTSEL_T15CC1 +# define ADC2_JEXTSEL_T15CC2 ADC12_JSQR_JEXTSEL_T15CC2 +# define ADC2_JEXTSEL_T15CC3 ADC12_JSQR_JEXTSEL_T15CC3 +# define ADC2_JEXTSEL_T15CC4 ADC12_JSQR_JEXTSEL_T15CC4 +# define ADC2_JEXTSEL_T15TRGO ADC12_JSQR_JEXTSEL_T15TRGO +# define ADC3_JEXTSEL_T15CC1 ADC34_JSQR_JEXTSEL_T15CC1 +# define ADC3_JEXTSEL_T15CC2 ADC34_JSQR_JEXTSEL_T15CC2 +# define ADC3_JEXTSEL_T15CC3 ADC34_JSQR_JEXTSEL_T15CC3 +# define ADC3_JEXTSEL_T15CC4 ADC34_JSQR_JEXTSEL_T15CC4 +# define ADC3_JEXTSEL_T15TRGO ADC34_JSQR_JEXTSEL_T15TRGO +# define ADC4_JEXTSEL_T15CC1 ADC34_JSQR_JEXTSEL_T15CC1 +# define ADC4_JEXTSEL_T15CC2 ADC34_JSQR_JEXTSEL_T15CC2 +# define ADC4_JEXTSEL_T15CC3 ADC34_JSQR_JEXTSEL_T15CC3 +# define ADC4_JEXTSEL_T15CC4 ADC34_JSQR_JEXTSEL_T15CC4 +# define ADC4_JEXTSEL_T15TRGO ADC34_JSQR_JEXTSEL_T15TRGO +# define ADC1_JEXTSEL_T20CC1 ADC12_JSQR_JEXTSEL_T20CC1 +# define ADC1_JEXTSEL_T20CC2 ADC12_JSQR_JEXTSEL_T20CC2 +# define ADC1_JEXTSEL_T20CC3 ADC12_JSQR_JEXTSEL_T20CC3 +# define ADC1_JEXTSEL_T20CC4 ADC12_JSQR_JEXTSEL_T20CC4 +# define ADC1_JEXTSEL_T20TRGO ADC12_JSQR_JEXTSEL_T20TRGO +# define ADC2_JEXTSEL_T20CC1 ADC12_JSQR_JEXTSEL_T20CC1 +# define ADC2_JEXTSEL_T20CC2 ADC12_JSQR_JEXTSEL_T20CC2 +# define ADC2_JEXTSEL_T20CC3 ADC12_JSQR_JEXTSEL_T20CC3 +# define ADC2_JEXTSEL_T20CC4 ADC12_JSQR_JEXTSEL_T20CC4 +# define ADC2_JEXTSEL_T20TRGO ADC12_JSQR_JEXTSEL_T20TRGO +# define ADC3_JEXTSEL_T20CC1 ADC34_JSQR_JEXTSEL_T20CC1 +# define ADC3_JEXTSEL_T20CC2 ADC34_JSQR_JEXTSEL_T20CC2 +# define ADC3_JEXTSEL_T20CC3 ADC34_JSQR_JEXTSEL_T20CC3 +# define ADC3_JEXTSEL_T20CC4 ADC34_JSQR_JEXTSEL_T20CC4 +# define ADC3_JEXTSEL_T20TRGO ADC34_JSQR_JEXTSEL_T20TRGO +# define ADC4_JEXTSEL_T20CC1 ADC34_JSQR_JEXTSEL_T20CC1 +# define ADC4_JEXTSEL_T20CC2 ADC34_JSQR_JEXTSEL_T20CC2 +# define ADC4_JEXTSEL_T20CC3 ADC34_JSQR_JEXTSEL_T20CC3 +# define ADC4_JEXTSEL_T20CC4 ADC34_JSQR_JEXTSEL_T20CC4 +# define ADC4_JEXTSEL_T20TRGO ADC34_JSQR_JEXTSEL_T20TRGO +# define ADC1_JEXTSEL_HRTTRG2 ADC12_JSQR_JEXTSEL_HRT1TRG2 +# define ADC1_JEXTSEL_HRTTRG4 ADC12_JSQR_JEXTSEL_HRT1TRG4 +# define ADC2_JEXTSEL_HRTTRG2 ADC12_JSQR_JEXTSEL_HRT1TRG2 +# define ADC2_JEXTSEL_HRTTRG4 ADC12_JSQR_JEXTSEL_HRT1TRG4 #endif #if defined(CONFIG_STM32_TIM1_ADC1) @@ -1856,8 +1856,20 @@ * Public Types ************************************************************************************/ -#ifdef CONFIG_STM32_STM32L15XX -typedef enum ADC_IO_CMDS +#if defined(CONFIG_STM32_STM32F10XX) +enum adc_io_cmds_e +{ + IO_ENABLE_TEMPER_VOLT_CH = 0, +}; + +#elif defined(CONFIG_STM32_STM32F20XX) +enum adc_io_cmds_e +{ + IO_ENABLE_TEMPER_VOLT_CH = 0, +}; + +#elif defined(CONFIG_STM32_STM32L15XX) +enum adc_io_cmds_e { IO_ENABLE_TEMPER_VOLT_CH = 0, IO_ENABLE_DISABLE_PDI, @@ -1871,7 +1883,7 @@ typedef enum ADC_IO_CMDS IO_START_CONV, IO_STOP_ADC, IO_START_ADC, -} ADC_IO_CMDS; +}; /* Channel and sample time pair */ @@ -1952,6 +1964,10 @@ struct stm32_adc_ops_s void (*int_en)(FAR struct stm32_adc_dev_s *dev, uint32_t source); + /* Disable interrupts */ + + void (*int_dis)(FAR struct stm32_adc_dev_s *dev, uint32_t source); + /* Get current ADC data register */ uint32_t (*val_get)(FAR struct stm32_adc_dev_s *dev); diff --git a/arch/arm/src/stm32/stm32_dma2d.c b/arch/arm/src/stm32/stm32_dma2d.c index e2a3a2278ceca413844092d407b18f44ca562af4..a70ed7508580006f1e1da0552113a2ecd198c790 100644 --- a/arch/arm/src/stm32/stm32_dma2d.c +++ b/arch/arm/src/stm32/stm32_dma2d.c @@ -53,7 +53,6 @@ #include #include -#include #include #include "up_arch.h" diff --git a/arch/arm/src/stm32/stm32_dma2d.h b/arch/arm/src/stm32/stm32_dma2d.h index ddaeada7b20e28684c11b7b0868dcbc0bd84945d..a62d16f7af1416b9d294cf5c03f1b11b90f9d5fb 100644 --- a/arch/arm/src/stm32/stm32_dma2d.h +++ b/arch/arm/src/stm32/stm32_dma2d.h @@ -42,26 +42,290 @@ #include #include -#include +#include "stm32_ltdc.h" #ifdef CONFIG_STM32_DMA2D -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ /**************************************************************************** * Public Types ****************************************************************************/ -/**************************************************************************** - * Public Data - ****************************************************************************/ +struct ltdc_area_s; /* see arch/arm/src/stm32/stm32_ltdc.h */ + +/* Blend mode definitions */ + +enum dma2d_blend_e +{ + DMA2D_BLEND_NONE = 0, /* Disable all blend operation */ + DMA2D_BLEND_ALPHA = 0x1, /* Enable alpha blending */ + DMA2D_BLEND_PIXELALPHA = 0x2, /* Enable alpha blending from pixel color */ +}; + +/* The layer is controlled through the following structure */ + +struct dma2d_layer_s +{ + /* Name: getvideoinfo + * + * Description: + * Get video information about the layer + * + * Parameter: + * layer - Reference to the layer control structure + * vinfo - Reference to the video info structure + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getvideoinfo)(FAR struct dma2d_layer_s *layer, + FAR struct fb_videoinfo_s *vinfo); + + /* Name: getplaneinfo + * + * Description: + * Get plane information about the layer + * + * Parameter: + * layer - Reference to the layer control structure + * planeno - Number of the plane + * pinfo - Reference to the plane info structure + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getplaneinfo)(FAR struct dma2d_layer_s *layer, int planeno, + FAR struct fb_planeinfo_s *pinfo); + + /* Name: getlid + * + * Description: + * Get a specific layer identifier. + * + * Parameter: + * layer - Reference to the layer structure + * lid - Reference to store the layer id + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getlid)(FAR struct dma2d_layer_s *layer, int *lid); + +#ifdef CONFIG_STM32_DMA2D_L8 + /* Name: setclut + * + * Description: + * Configure layer clut (color lookup table). + * Non clut is defined during initializing. + * + * Parameter: + * layer - Reference to the layer structure + * cmap - color lookup table with up the 256 entries + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*setclut)(FAR struct dma2d_layer_s *layer, + const FAR struct fb_cmap_s *cmap); + + /* Name: getclut + * + * Description: + * Get configured layer clut (color lookup table). + * + * Parameter: + * layer - Reference to the layer structure + * cmap - Reference to valid color lookup table accept up the 256 color + * entries + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getclut)(FAR struct dma2d_layer_s *layer, FAR struct fb_cmap_s *cmap); +#endif + + /* Name: setalpha + * + * Description: + * Configure layer alpha value factor into blend operation. + * During the layer blend operation the source alpha value is multiplied + * with this alpha value. If the source color format doesn't support alpha + * channel (e.g. non ARGB8888) this alpha value will be used as constant + * alpha value for blend operation. + * Default value during initializing: 0xff + * + * Parameter: + * layer - Reference to the layer structure + * alpha - Alpha value + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*setalpha)(FAR struct dma2d_layer_s *layer, uint8_t alpha); + + /* Name: getalpha + * + * Description: + * Get configured layer alpha value factor for blend operation. + * + * Parameter: + * layer - Reference to the layer structure + * alpha - Reference to store the alpha value + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getalpha)(FAR struct dma2d_layer_s *layer, uint8_t *alpha); + + /* Name: setblendmode + * + * Description: + * Configure blend mode of the layer. + * Default mode during initializing: DMA2D_BLEND_NONE + * Blendmode is active after next update. + * + * Parameter: + * layer - Reference to the layer structure + * mode - Blend mode (see DMA2D_BLEND_*) + * + * Return: + * On success - OK + * On error - -EINVAL + * + * Procedure information: + * DMA2D_BLEND_NONE: + * Informs the driver to disable all blend operation for the given layer. + * That means the layer is opaque. + * + * DMA2D_BLEND_ALPHA: + * Informs the driver to enable alpha blending for the given layer. + * + * DMA2D_BLEND_PIXELALPHA: + * Informs the driver to use the pixel alpha value of the layer instead + * the constant alpha value. This is only useful for ARGB8888 + * color format. + */ + + int (*setblendmode)(FAR struct dma2d_layer_s *layer, uint32_t mode); + + /* Name: getblendmode + * + * Description: + * Get configured blend mode of the layer. + * + * Parameter: + * layer - Reference to the layer structure + * mode - Reference to store the blend mode + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getblendmode)(FAR struct dma2d_layer_s *layer, uint32_t *mode); + + /* Name: blit + * + * Description: + * Copy selected area from a source layer to selected position of the + * destination layer. + * + * Parameter: + * dest - Reference to the destination layer + * destxpos - Selected x target position of the destination layer + * destypos - Selected y target position of the destination layer + * src - Reference to the source layer + * srcarea - Reference to the selected area of the source layer + * + * Return: + * OK - On success + * -EINVAL - If one of the parameter invalid or if the size of the + * selected source area outside the visible area of the + * destination layer. (The visible area usually represents the + * display size) + * -ECANCELED - Operation cancelled, something goes wrong. + */ + + int (*blit)(FAR struct dma2d_layer_s *dest, + fb_coord_t destxpos, fb_coord_t destypos, + FAR const struct dma2d_layer_s *src, + FAR const struct ltdc_area_s *srcarea); + + /* Name: blend + * + * Description: + * Blends the selected area from a background layer with selected position + * of the foreground layer. Copies the result to the selected position of + * the destination layer. Note! The content of the foreground and background + * layer keeps unchanged as long destination layer is unequal to the + * foreground and background layer. + * + * Parameter: + * dest - Reference to the destination layer + * fore - Reference to the foreground layer + * forexpos - Selected x target position of the foreground layer + * foreypos - Selected y target position of the foreground layer + * back - Reference to the background layer + * backarea - Reference to the selected area of the background layer + * + * Return: + * OK - On success + * -EINVAL - If one of the parameter invalid or if the size of the + * selected source area outside the visible area of the + * destination layer. (The visible area usually represents the + * display size) + * -ECANCELED - Operation cancelled, something goes wrong. + */ + + int (*blend)(FAR struct dma2d_layer_s *dest, + fb_coord_t destxpos, fb_coord_t destypos, + FAR const struct dma2d_layer_s *fore, + fb_coord_t forexpos, fb_coord_t foreypos, + FAR const struct dma2d_layer_s *back, + FAR const struct ltdc_area_s *backarea); + + /* Name: fillarea + * + * Description: + * Fill the selected area of the whole layer with a specific color. + * + * Parameter: + * layer - Reference to the layer structure + * area - Reference to the valid area structure select the area + * color - Color to fill the selected area. Color must be formatted + * according to the layer pixel format. + * + * Return: + * OK - On success + * -EINVAL - If one of the parameter invalid or if the size of the + * selected area outside the visible area of the layer. + * -ECANCELED - Operation cancelled, something goes wrong. + */ + + int (*fillarea)(FAR struct dma2d_layer_s *layer, + FAR const struct ltdc_area_s *area, + uint32_t color); +}; /**************************************************************************** * Public Functions ****************************************************************************/ -# ifdef CONFIG_STM32_LTDC_INTERFACE +struct stm32_ltdc_s; /* Forward declaration */ + /**************************************************************************** * Name: stm32_dma2dinitltdc * @@ -84,7 +348,88 @@ ****************************************************************************/ FAR struct dma2d_layer_s *stm32_dma2dinitltdc(FAR struct stm32_ltdc_s *layer); -# endif /* CONFIG_STM32_LTDC_INTERFACE */ + +/**************************************************************************** + * Name: up_dma2dgetlayer + * + * Description: + * Get a dma2d layer structure by the layer identifier + * + * Parameter: + * lid - Layer identifier + * + * Return: + * Reference to the dma2d layer control structure on success or Null if no + * related exist. + * + ****************************************************************************/ + +FAR struct dma2d_layer_s *up_dma2dgetlayer(int lid); + +/**************************************************************************** + * Name: up_dma2dcreatelayer + * + * Description: + * Create a new dma2d layer object to interact with the dma2d controller + * + * Parameter: + * width - Layer width + * height - Layer height + * fmt - Pixel format of the layer + * + * Return: + * On success - A valid dma2d layer reference + * On error - NULL and errno is set to + * -EINVAL if one of the parameter is invalid + * -ENOMEM if no memory available or exceeds + * CONFIG_STM32_DMA2D_NLAYERS + * + ****************************************************************************/ + +FAR struct dma2d_layer_s *up_dma2dcreatelayer(fb_coord_t width, + fb_coord_t height, + uint8_t fmt); + +/**************************************************************************** + * Name: up_dma2dremovelayer + * + * Description: + * Remove and deallocate the dma2d layer + * + * Parameter: + * layer - Reference to the layer to remove + * + * Return: + * On success - OK + * On error - -EINVAL + * + ****************************************************************************/ + +int up_dma2dremovelayer(FAR struct dma2d_layer_s *layer); + +/**************************************************************************** + * Name: up_dma2dinitialize + * + * Description: + * Initialize the dma2d controller + * + * Return: + * OK - On success + * An error if initializing failed. + * + ****************************************************************************/ + +int up_dma2dinitialize(void); + +/**************************************************************************** + * Name: up_dma2duninitialize + * + * Description: + * Uninitialize the dma2d controller + * + ****************************************************************************/ + +void up_dma2duninitialize(void); #endif /* CONFIG_STM32_DMA2D */ #endif /* __ARCH_ARM_SRC_STM32_STM32_DMA2D_H */ diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/stm32/stm32_hrtim.c index 1bf084a2778d09e3bd15ba16cddf5c54dcade0f1..d064c8e1d3b4b4a43aece55a4f696c53e040bb85 100644 --- a/arch/arm/src/stm32/stm32_hrtim.c +++ b/arch/arm/src/stm32/stm32_hrtim.c @@ -181,10 +181,6 @@ # endif #endif -#ifdef CONFIG_STM32_HRTIM_ADC -# error HRTIM ADC Triggering not supported yet -#endif - #if defined(CONFIG_STM32_HRTIM_ADC1_TRG1) || defined(CONFIG_STM32_HRTIM_ADC1_TRG2) || \ defined(CONFIG_STM32_HRTIM_ADC1_TRG3) || defined(CONFIG_STM32_HRTIM_ADC1_TRG4) || \ defined(CONFIG_STM32_HRTIM_ADC2_TRG1) || defined(CONFIG_STM32_HRTIM_ADC2_TRG2) || \ diff --git a/arch/arm/src/stm32/stm32_hrtim.h b/arch/arm/src/stm32/stm32_hrtim.h index b25073cfd1e340ced4ec192e996af5e95f2b8b71..1085951fb9049690e94bcf7a7d8e66cb3aebe442 100644 --- a/arch/arm/src/stm32/stm32_hrtim.h +++ b/arch/arm/src/stm32/stm32_hrtim.h @@ -202,6 +202,25 @@ # endif #endif +/* Helpers **************************************************************************/ + +#define HRTIM_CMP_SET(hrtim, tim, index, cmp) \ + (hrtim)->hd_ops->cmp_update(hrtim, tim, index, cmp) +#define HRTIM_PER_SET(hrtim, tim, per) \ + (hrtim)->hd_ops->per_update(hrtim, tim, per) +#define HRTIM_OUTPUTS_ENABLE(hrtim, tim, state) \ + (hrtim)->hd_ops->outputs_enable(hrtim, tim, state) +#define HRTIM_OUTPUTS_ENABLE(hrtim, tim, state) \ + (hrtim)->hd_ops->outputs_enable(hrtim, tim, state) +#define HRTIM_BURST_CMP_SET(hrtim, cmp) \ + (hrtim)->hd_ops->burst_cmp_set(hrtim, cmp) +#define HRTIM_BURST_PER_SET(hrtim, per) \ + (hrtim)->hd_ops->burst_per_set(hrtim, per) +#define HRTIM_BURST_PRE_SET(hrtim, pre) \ + (hrtim)->hd_ops->burst_pre_set(hrtim, pre) +#define HRTIM_BURST_ENABLE(hrtim, state) \ + (hrtim)->hd_ops->burst_enable(hrtim, state) + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_i2c_alt.c b/arch/arm/src/stm32/stm32_i2c_alt.c index 18dde6c80c603cf8da9a1fb5f674d7678adbc2ae..a2cd2156ec0fb94848bc08438b13fca0320c0ebd 100644 --- a/arch/arm/src/stm32/stm32_i2c_alt.c +++ b/arch/arm/src/stm32/stm32_i2c_alt.c @@ -208,6 +208,7 @@ static const uint16_t I2CEVENT_ISR_SHUTDOWN = 1001; /* ISR gets shutdown static const uint16_t I2CEVENT_ISR_EMPTY_CALL = 1002; /* ISR gets called but no I2C logic comes into play */ static const uint16_t I2CEVENT_MSG_HANDLING = 1003; /* Message Handling 1/1: advances the msg processing param = msgc */ static const uint16_t I2CEVENT_POLL_DEV_NOT_RDY = 1004; /* During polled operation if device is not ready yet */ +static const uint16_t I2CEVENT_ISR_SR1ERROR = 1005; /* ERROR set in SR1 at end of transfer */ static const uint16_t I2CEVENT_ISR_CALL = 1111; /* ISR called */ static const uint16_t I2CEVENT_SENDADDR = 5; /* Start/Master bit set and address sent, param = priv->msgv->addr(EV5 in reference manual) */ @@ -1824,7 +1825,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) * device wasn't ready yet. */ - else + else { #ifdef CONFIG_I2C_POLLED stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); @@ -1836,7 +1837,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) i2cerr("ERROR: No correct state detected(start bit, read or write) \n"); i2cerr(" state %i\n", status); - /* set condition to terminate ISR and wake waiting thread */ + /* Set condition to terminate ISR and wake waiting thread */ priv->dcnt = -1; priv->msgc = 0; @@ -1855,7 +1856,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) if ((status & I2C_SR1_ERRORMASK) != 0) { - stm32_i2c_traceevent(priv, I2CEVENT_ERROR, status & I2C_SR1_ERRORMASK); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_SR1ERROR, status & I2C_SR1_ERRORMASK); /* Clear interrupt flags */ diff --git a/arch/arm/src/stm32/stm32_ltdc.c b/arch/arm/src/stm32/stm32_ltdc.c index 3a24ae84503faf7f886e93c02f09028bbf0fcf2f..5b794d17dd4ac2b2773c8886d5414705f0e7f454 100644 --- a/arch/arm/src/stm32/stm32_ltdc.c +++ b/arch/arm/src/stm32/stm32_ltdc.c @@ -53,8 +53,6 @@ #include #include -#include -#include #include #include "up_arch.h" @@ -919,18 +917,10 @@ static const uintptr_t stm32_clutwr_layer_t[LTDC_NLAYERS] = static bool g_initialized; -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ -/**************************************************************************** - * Configure global register - ****************************************************************************/ - /**************************************************************************** * Name: stm32_ltdc_gpioconfig * @@ -1374,10 +1364,6 @@ static void stm32_lcd_enable(bool enable) reginfo("configured LTDC_GCR=%08x\n", getreg32(STM32_LTDC_GCR)); } -/**************************************************************************** - * Configure layer register - ****************************************************************************/ - /**************************************************************************** * Name: stm32_ltdc_lclutenable * @@ -2193,7 +2179,7 @@ static void stm32_ltdc_linit(int lid) ****************************************************************************/ static int stm32_getvideoinfo(struct fb_vtable_s *vtable, - struct fb_videoinfo_s *vinfo) + struct fb_videoinfo_s *vinfo) { lcdinfo("vtable=%p vinfo=%p\n", vtable, vinfo); if (vtable) @@ -2228,7 +2214,7 @@ static int stm32_getvideoinfo(struct fb_vtable_s *vtable, ****************************************************************************/ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno, - struct fb_planeinfo_s *pinfo) + struct fb_planeinfo_s *pinfo) { lcdinfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo); if (vtable) @@ -2264,7 +2250,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno, #ifdef STM32_LAYER_CLUT_SIZE static int stm32_getcmap(struct fb_vtable_s *vtable, - struct fb_cmap_s *cmap) + struct fb_cmap_s *cmap) { #ifdef CONFIG_STM32_LTDC_L2 return stm32_getclut((FAR struct ltdc_layer_s *)&LAYER_L2, cmap); @@ -2290,7 +2276,7 @@ static int stm32_getcmap(struct fb_vtable_s *vtable, ****************************************************************************/ static int stm32_putcmap(struct fb_vtable_s *vtable, - const struct fb_cmap_s *cmap) + const struct fb_cmap_s *cmap) { #ifdef CONFIG_STM32_LTDC_L2 return stm32_setclut((FAR struct ltdc_layer_s *)&LAYER_L2, cmap); @@ -2317,7 +2303,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, ****************************************************************************/ static int stm32_lgetvideoinfo(struct ltdc_layer_s *layer, - struct fb_videoinfo_s *vinfo) + struct fb_videoinfo_s *vinfo) { lcdinfo("layer=%p vinfo=%p\n", layer, vinfo); FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; @@ -2351,7 +2337,7 @@ static int stm32_lgetvideoinfo(struct ltdc_layer_s *layer, ****************************************************************************/ static int stm32_lgetplaneinfo(struct ltdc_layer_s *layer, int planeno, - struct fb_planeinfo_s *pinfo) + struct fb_planeinfo_s *pinfo) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; @@ -2386,7 +2372,7 @@ static int stm32_lgetplaneinfo(struct ltdc_layer_s *layer, int planeno, #ifdef STM32_LAYER_CLUT_SIZE static int stm32_setclut(struct ltdc_layer_s *layer, - const struct fb_cmap_s *cmap) + const struct fb_cmap_s *cmap) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; int ret; @@ -3020,9 +3006,9 @@ static int stm32_getblendmode(FAR struct ltdc_layer_s *layer, uint32_t *mode) ****************************************************************************/ static int stm32_setarea(FAR struct ltdc_layer_s *layer, - FAR const struct ltdc_area_s *area, - fb_coord_t srcxpos, - fb_coord_t srcypos) + FAR const struct ltdc_area_s *area, + fb_coord_t srcxpos, + fb_coord_t srcypos) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; @@ -3077,8 +3063,8 @@ static int stm32_setarea(FAR struct ltdc_layer_s *layer, ****************************************************************************/ static int stm32_getarea(FAR struct ltdc_layer_s *layer, - FAR struct ltdc_area_s *area, - fb_coord_t *srcxpos, fb_coord_t *srcypos) + FAR struct ltdc_area_s *area, + fb_coord_t *srcxpos, fb_coord_t *srcypos) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; @@ -3333,11 +3319,11 @@ static int stm32_blit(FAR struct ltdc_layer_s *dest, ****************************************************************************/ static int stm32_blend(FAR struct ltdc_layer_s *dest, - fb_coord_t destxpos, fb_coord_t destypos, - FAR const struct dma2d_layer_s *fore, - fb_coord_t forexpos, fb_coord_t foreypos, - FAR const struct dma2d_layer_s *back, - FAR const struct ltdc_area_s *backarea) + fb_coord_t destxpos, fb_coord_t destypos, + FAR const struct dma2d_layer_s *fore, + fb_coord_t forexpos, fb_coord_t foreypos, + FAR const struct dma2d_layer_s *back, + FAR const struct ltdc_area_s *backarea) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)dest; @@ -3382,8 +3368,8 @@ static int stm32_blend(FAR struct ltdc_layer_s *dest, ****************************************************************************/ static int stm32_fillarea(FAR struct ltdc_layer_s *layer, - FAR const struct ltdc_area_s *area, - uint32_t color) + FAR const struct ltdc_area_s *area, + uint32_t color) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; diff --git a/arch/arm/src/stm32/stm32_ltdc.h b/arch/arm/src/stm32/stm32_ltdc.h index 9214d83e351abb40f9a628e1738ffaf4ad1d71b2..33ebc3e5580e995df514c57c0381701d9205d9c4 100644 --- a/arch/arm/src/stm32/stm32_ltdc.h +++ b/arch/arm/src/stm32/stm32_ltdc.h @@ -49,8 +49,6 @@ #include #include -#include - #ifdef CONFIG_STM32_LTDC /************************************************************************************ @@ -61,6 +59,502 @@ * Public Types ************************************************************************************/ +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct dma2d_layer_s; /* see arch/arm/src/stm32/stm32_dma2d.h */ + +/* Blend mode definitions */ + +enum ltdc_blend_e +{ + LTDC_BLEND_NONE = 0, /* Disable all blend operation */ + LTDC_BLEND_ALPHA = 0x1, /* Enable alpha blending */ + LTDC_BLEND_PIXELALPHA = 0x2, /* Enable alpha blending from pixel color */ + LTDC_BLEND_COLORKEY = 0x4, /* Enable colorkey */ + LTDC_BLEND_ALPHAINV = 0x8, /* Inverse alpha blending of source */ + LTDC_BLEND_PIXELALPHAINV = 0x10 /* Invers pixel alpha blending of source */ +}; + +/* layer control definitions */ + +enum ltdc_layer_e +{ + LTDC_LAYER_OWN = 0, /* The given layer */ + LTDC_LAYER_TOP = 0x1, /* The initialized top layer */ + LTDC_LAYER_BOTTOM = 0x2, /* the initialized bottom layer */ + LTDC_LAYER_ACTIVE = 0x4, /* The current visible flip layer */ + LTDC_LAYER_INACTIVE = 0x8 /* The current invisible flip layer */ +#ifdef CONFIG_STM32_DMA2D + ,LTDC_LAYER_DMA2D = 0x10 /* The dma2d interface layer id */ +#endif +}; + +/* Update operation flag */ + +enum ltdc_update_e +{ + LTDC_UPDATE_NONE = 0, /* Update given layer only */ + LTDC_UPDATE_SIM = 0x1, /* Update both layer simultaneous */ + LTDC_UPDATE_FLIP = 0x2, /* Perform flip operation */ + LTDC_UPDATE_ACTIVATE = 0x4 /* Set the given layer to the active layer */ +}; + +/* sync mode definitions */ + +enum ltdc_sync_e +{ + LTDC_SYNC_NONE = 0, /* Immediately */ + LTDC_SYNC_VBLANK = 0x100, /* Upon vertical sync */ + LTDC_SYNC_WAIT = 0x200 /* Waits upon vertical sync */ +}; + +/* Definition of the visible layer position and size */ + +struct ltdc_area_s +{ + fb_coord_t xpos; /* X position in pixel */ + fb_coord_t ypos; /* Y position in pixel */ + fb_coord_t xres; /* X resolution in pixel */ + fb_coord_t yres; /* Y resolution in pixel */ +}; + +/* The layer is controlled through the following structure */ + +struct ltdc_layer_s +{ + /* Name: getvideoinfo + * + * Description: + * Get video information about the layer + * + * Parameter: + * layer - Reference to the layer control structure + * vinfo - Reference to the video info structure + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getvideoinfo)(FAR struct ltdc_layer_s *layer, + FAR struct fb_videoinfo_s *vinfo); + + /* Name: getplaneinfo + * + * Description: + * Get plane information about the layer + * + * Parameter: + * layer - Reference to the layer control structure + * planeno - Number of the plane + * pinfo - Reference to the plane info structure + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getplaneinfo)(FAR struct ltdc_layer_s *layer, int planeno, + FAR struct fb_planeinfo_s *pinfo); + + /* Name: getlid + * + * Description: + * Get a specific layer identifier. + * + * Parameter: + * layer - Reference to the layer structure + * lid - Reference to store the layer id + * flag - Operation flag describe the layer identifier + * e.g. get the current active or inactive layer. + * See LTDC_LAYER_* for possible values + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getlid)(FAR struct ltdc_layer_s *layer, int *lid, uint32_t flag); + +#ifdef CONFIG_FB_CMAP + /* Name: setclut + * + * Description: + * Configure layer clut (color lookup table). + * Non clut is defined during initializing. + * Clut is active during next vertical blank period. Do not need an update. + * + * Parameter: + * layer - Reference to the layer structure + * cmap - color lookup table with up the 256 entries + * enable - Enable or disable clut support (if false cmap is ignored and can + * be NULL) + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*setclut)(FAR struct ltdc_layer_s *layer, + const FAR struct fb_cmap_s *cmap); + + /* Name: getclut + * + * Description: + * Get configured layer clut (color lookup table). + * + * Parameter: + * layer - Reference to the layer structure + * cmap - Reference to valid color lookup table accept up the 256 color + * entries + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getclut)(FAR struct ltdc_layer_s *layer, FAR struct fb_cmap_s *cmap); +#endif + + /* Name: setcolor + * + * Description: + * Configure layer color for the non active layer area. + * Default value during initializing: 0x00000000 + * Color is active after next update. + * + * Parameter: + * layer - Reference to the layer structure + * argb - ARGB8888 color value + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*setcolor)(FAR struct ltdc_layer_s *layer, uint32_t argb); + + /* Name: getcolor + * + * Description: + * Get configured layer color for the non active layer area. + * + * Parameter: + * layer - Reference to the layer structure + * argb - Reference to store the ARGB8888 color value + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getcolor)(FAR struct ltdc_layer_s *layer, uint32_t *argb); + + /* Name: setcolorkey + * + * Description: + * Configure the layer color key (chromakey) for transparence. + * Default value during initializing: 0x00000000 + * Colorkey is active after next update. + * + * Parameter: + * layer - Reference to the layer structure + * rgb - RGB888 color key + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*setcolorkey)(FAR struct ltdc_layer_s *layer, uint32_t rgb); + + /* Name: getcolorkey + * + * Description: + * Get the configured layer color key (chromakey) for transparence. + * + * Parameter: + * layer - Reference to the layer structure + * rgb - Reference to store the RGB888 color key + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getcolorkey)(FAR struct ltdc_layer_s *layer, uint32_t *rgb); + + /* Name: setalpha + * + * Description: + * Configure layer alpha value factor into blend operation. + * During the layer blend operation the source alpha value is multiplied + * with this alpha value. If the source color format doesn't support alpha + * channel (e.g. non ARGB8888) this alpha value will be used as constant + * alpha value for blend operation. + * Default value during initializing: 0xff + * Alpha is active after next update. + * + * Parameter: + * layer - Reference to the layer structure + * alpha - Alpha value + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*setalpha)(FAR struct ltdc_layer_s *layer, uint8_t alpha); + + /* Name: getalpha + * + * Description: + * Get configured layer alpha value factor for blend operation. + * + * Parameter: + * layer - Reference to the layer structure + * alpha - Reference to store the alpha value + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getalpha)(FAR struct ltdc_layer_s *layer, uint8_t *alpha); + + /* Name: setblendmode + * + * Description: + * Configure blend mode of the layer. + * Default mode during initializing: LTDC_BLEND_NONE + * Blendmode is active after next update. + * + * Parameter: + * layer - Reference to the layer structure + * mode - Blend mode (see LTDC_BLEND_*) + * + * Return: + * On success - OK + * On error - -EINVAL + * + * Procedure information: + * LTDC_BLEND_NONE: + * Informs the driver to disable all blend operation for the given layer. + * That means the layer is opaque. Note this has no effect on the + * colorkey settings. + * + * LTDC_BLEND_ALPHA: + * Informs the driver to enable alpha blending for the given layer. + * + * LTDC_BLEND_COLORKEY: + * Informs the driver to enable colorkeying for the given layer. + * + * LTDC_BLEND_SRCPIXELALPHA: + * Informs the driver to use the pixel alpha value of the layer instead + * the constant alpha value. This is only useful for ARGB8888 + * color format. + * + * LTDC_BLEND_DESTPIXELALPHA: + * Informs the driver to use the pixel alpha value of the subjacent layer + * instead the constant alpha value. This is only useful for ARGB8888 + * color format. + */ + + int (*setblendmode)(FAR struct ltdc_layer_s *layer, uint32_t mode); + + /* Name: getblendmode + * + * Description: + * Get configured blend mode of the layer. + * + * Parameter: + * layer - Reference to the layer structure + * mode - Reference to store the blend mode + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getblendmode)(FAR struct ltdc_layer_s *layer, uint32_t *mode); + + /* Name: setarea + * + * Description: + * Configure visible layer area and the reference position of the first + * pixel of the whole layer which is the first visible top left pixel in + * the active area. + * Default value during initializing: + * xpos = 0 + * ypos = 0 + * xres = display x resolution + * yres = display y resolution + * + * Area is active after next update. + * + * Parameter: + * layer - Reference to the layer control structure + * area - Reference to the valid area structure for the new active area + * srcxpos - x position of the visible pixel of the whole layer + * srcypos - y position of the visible pixel of the whole layer + * + * Return: + * On success - OK + * On error - -EINVAL + * + * Procedure Information: + * If the srcxpos and srcypos unequal the xpos and ypos of the coord + * structure this acts like moving the visible area to another position on + * the screen during the next update operation. + */ + + int (*setarea)(FAR struct ltdc_layer_s *layer, + FAR const struct ltdc_area_s *area, + fb_coord_t srcxpos, + fb_coord_t srcypos); + + /* Name: getarea + * + * Description: + * Get configured visible layer area. + * + * Parameter: + * layer - Reference to the layer control structure + * area - Reference to the area structure to store the active area + * srcxpos - Reference to store the referenced x position of the whole layer + * srcypos - Reference to store the reterenced y position of the whole layer + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getarea)(FAR struct ltdc_layer_s *layer, + FAR struct ltdc_area_s *area, + fb_coord_t *srcxpos, + fb_coord_t *srcypos); + + /* Name: update + * + * Description: + * Update current layer settings and make changes visible. + * + * Parameter: + * layer - Reference to the layer structure + * mode - operation mode (see LTDC_UPDATE_*) + * + * Return: + * OK - On success + * -EINVAL - If one of the parameter invalid + * -ECANCELED - Operation cancelled, something goes wrong + * + * Procedure information: + * LTDC_UPDATE_SIM: + * Informs the driver to update both ltdc layers simultaneously. Otherwise + * update the given layer only. + * + * LTDC_UPDATE_FLIP: + * Informs the driver to perform a flip operation. + * This only effects the ltdc layer 1 and 2 and can be useful for double + * buffering. Each flip operation changed the active layer ot the inactive + * and vice versa. In the context of the ltdc that means, the inactive layer + * is complete disabled. So the subjacent layer is the background layer + * (background color). To reactivate both layer and their settings perform + * an update without LTDC_UPDATE_FLIP flag. + * + * LTDC_UPDATE_ACTIVATE: + * Informs the driver that the given layer should be the active layer when + * the operation is complete. + * + * LTDC_SYNC_VBLANK: + * Informs the driver to update the layer upon vertical blank. Otherwise + * immediately. + */ + + int (*update)(FAR struct ltdc_layer_s *layer, uint32_t mode); + +#ifdef CONFIG_STM32_DMA2D + /* Name: blit + * + * Description: + * Copy selected area from a source layer to selected position of the + * destination layer. + * + * Parameter: + * dest - Reference to the destination layer + * destxpos - Selected x position of the destination layer + * destypos - Selected y position of the destination layer + * src - Reference to the source layer + * srcarea - Reference to the selected area of the source layer + * + * Return: + * OK - On success + * -EINVAL - If one of the parameter invalid or if the size of the selected + * source area outside the visible area of the destination layer. + * (The visible area usually represents the display size) + */ + + int (*blit)(FAR struct ltdc_layer_s *dest, + fb_coord_t destxpos, fb_coord_t destypos, + FAR const struct dma2d_layer_s *src, + FAR const struct ltdc_area_s *srcarea); + + /* Name: blend + * + * Description: + * Blends the selected area from a foreground layer with selected position + * of the background layer. Copy the result to the destination layer. Note! + * The content of the foreground and background layer is not changed. + * + * Parameter: + * dest - Reference to the destination layer + * destxpos - Selected x position of the destination layer + * destypos - Selected y position of the destination layer + * fore - Reference to the foreground layer + * forexpos - Selected x position of the foreground layer + * foreypos - Selected y position of the foreground layer + * back - Reference to the background layer + * backarea - Reference to the selected area of the background layer + * + * Return: + * OK - On success + * -EINVAL - If one of the parameter invalid or if the size of the selected + * source area outside the visible area of the destination layer. + * (The visible area usually represents the display size) + */ + + int (*blend)(FAR struct ltdc_layer_s *dest, + fb_coord_t destxpos, fb_coord_t destypos, + FAR const struct dma2d_layer_s *fore, + fb_coord_t forexpos, fb_coord_t foreypos, + FAR const struct dma2d_layer_s *back, + FAR const struct ltdc_area_s *backarea); + + /* Name: fillarea + * + * Description: + * Fill the selected area of the whole layer with a specific color. + * + * Parameter: + * layer - Reference to the layer structure + * area - Reference to the valid area structure select the area + * color - Color to fill the selected area. Color must be formatted + * according to the layer pixel format. + * + * Return: + * OK - On success + * -EINVAL - If one of the parameter invalid or if the size of the selected + * area outside the visible area of the layer. + */ + + int (*fillarea)(FAR struct ltdc_layer_s *layer, + FAR const struct ltdc_area_s *area, + uint32_t color); +#endif +}; + /* Common layer state structure for the LTDC and DMA2D controller */ struct stm32_ltdc_s @@ -92,7 +586,7 @@ struct stm32_ltdc_s /* Operation */ - sem_t *lock; /* Ensure mutually exclusive access */ + sem_t *lock; /* Ensure mutually exclusive access */ }; /************************************************************************************ @@ -102,10 +596,22 @@ struct stm32_ltdc_s /************************************************************************************ * Public Functions ************************************************************************************/ + /* The STM32 LTDC driver uses the common framebuffer interfaces declared in * include/nuttx/video/fb.h. */ +/************************************************************************************ + * Name: stm32_ltdcinitialize + * + * Description: + * Initialize the ltdc controller + * + * Return: + * OK + * + ************************************************************************************/ + int stm32_ltdcinitialize(void); FAR struct fb_vtable_s *stm32_ltdcgetvplane(int vplane); void stm32_ltdcuninitialize(void); diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/stm32/stm32_otgfsdev.c index 90b5b97acee606acd18c52c33a3c0883786aff69..3831e6d0971547dd1f07722de74841a5de4e126e 100644 --- a/arch/arm/src/stm32/stm32_otgfsdev.c +++ b/arch/arm/src/stm32/stm32_otgfsdev.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_otgfsdev.c * - * Copyright (C) 2012-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane * @@ -64,7 +64,6 @@ #include "stm32_otgfs.h" #if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS)) - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -4337,7 +4336,7 @@ static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s #ifdef CONFIG_USBDEV_DMA static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes) { - usbtrace(TRACE_EPALLOCBUFFER, privep->epphy); + usbtrace(TRACE_EPALLOCBUFFER, ((FAR struct stm32_ep_s *)ep)->epphy); #ifdef CONFIG_USBDEV_DMAMEMORY return usbdev_dma_alloc(bytes); @@ -4358,7 +4357,7 @@ static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes) #ifdef CONFIG_USBDEV_DMA static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf) { - usbtrace(TRACE_EPFREEBUFFER, privep->epphy); + usbtrace(TRACE_EPALLOCBUFFER, ((FAR struct stm32_ep_s *)ep)->epphy); #ifdef CONFIG_USBDEV_DMAMEMORY usbdev_dma_free(buf); diff --git a/arch/arm/src/stm32/stm32_rtc.h b/arch/arm/src/stm32/stm32_rtc.h index fff697af4533b95174f662c8b737101c1e923935..c18daf9144b991e843579244cda24097f5d48331 100644 --- a/arch/arm/src/stm32/stm32_rtc.h +++ b/arch/arm/src/stm32/stm32_rtc.h @@ -96,7 +96,7 @@ #else /* !CONFIG_STM32_STM32F10XX */ #if !defined(CONFIG_RTC_MAGIC) -# define CONFIG_RTC_MAGIC (0xfacefeee) +# define CONFIG_RTC_MAGIC (0xfacefeed) #endif #if !defined(CONFIG_RTC_MAGIC_REG) @@ -137,7 +137,7 @@ extern "C" * Public Functions ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: stm32_rtc_irqinitialize * * Description: @@ -150,7 +150,7 @@ extern "C" * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int stm32_rtc_irqinitialize(void); @@ -208,7 +208,7 @@ int stm32_rtc_setdatetime(FAR const struct tm *tp); * Instantiate the RTC lower half driver for the STM32. General usage: * * #include - * #include "stm32_rtc.h> + * #include "stm32_rtc.h" * * struct rtc_lowerhalf_s *lower; * lower = stm32_rtc_lowerhalf(); diff --git a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c b/arch/arm/src/stm32/stm32_rtc_lowerhalf.c index 027382e2076b66746e7e46acd831795f6ce6e59f..ca5d54443970339c1c7c356c624a92a3bbaf586b 100644 --- a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c +++ b/arch/arm/src/stm32/stm32_rtc_lowerhalf.c @@ -839,6 +839,7 @@ static int stm32_periodic_callback(void) * on any failure. * ****************************************************************************/ + #ifdef CONFIG_RTC_PERIODIC static int stm32_setperiodic(FAR struct rtc_lowerhalf_s *lower, FAR const struct lower_setperiodic_s *alarminfo) diff --git a/arch/arm/src/stm32/stm32_rtcounter.c b/arch/arm/src/stm32/stm32_rtcounter.c index 8837b24db8eadbe04134c8f2989ab643827fe410..c01f21d58bdfce28df75d72abe2b21faf297e8d8 100644 --- a/arch/arm/src/stm32/stm32_rtcounter.c +++ b/arch/arm/src/stm32/stm32_rtcounter.c @@ -7,7 +7,7 @@ * With extensions, modifications by: * * Copyright (C) 2011-2013, 2015, 2017 Gregory Nutt. All rights reserved. - * Author: Gregroy Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index 72ed754a978c76bdc59946455f4302e5d4abdf7a..74b70ffd0617aaa5c2b73b50f575bd0844c52a8f 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -245,6 +245,8 @@ #if defined(CONFIG_PM) && !defined(CONFIG_PM_SERIAL_ACTIVITY) # define CONFIG_PM_SERIAL_ACTIVITY 10 +#endif +#if defined(CONFIG_PM) # define PM_IDLE_DOMAIN 0 /* Revisit */ #endif diff --git a/arch/arm/src/stm32/stm32_start.c b/arch/arm/src/stm32/stm32_start.c index ac16478b3372a9f1cc55ed6acf8f9eaf35b990f4..d960ea86e0a4075aef59faedf191040edebbf3be 100644 --- a/arch/arm/src/stm32/stm32_start.c +++ b/arch/arm/src/stm32/stm32_start.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_start.c * - * Copyright (C) 2009, 2011-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -44,7 +44,6 @@ #include #include -#include #include "up_arch.h" #include "up_internal.h" @@ -57,6 +56,8 @@ # include "nvic.h" #endif +#include "stm32_start.h" + /**************************************************************************** * Private Function prototypes ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_start.h b/arch/arm/src/stm32/stm32_start.h new file mode 100644 index 0000000000000000000000000000000000000000..04d5fe840cce3bce6563e5e24e6eb524c1e94d73 --- /dev/null +++ b/arch/arm/src/stm32/stm32_start.h @@ -0,0 +1,62 @@ +/************************************************************************************ + * arch/arm/src/stm32/stm32_start.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_START_H +#define __ARCH_ARM_SRC_STM32_STM32_START_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This entry + * point is called early in the initialization -- after clocking and memory have + * been configured but before caches have been enabled and before any devices have + * been initialized. + * + ************************************************************************************/ + +void stm32_boardinitialize(void); + +#endif /* __ARCH_ARM_SRC_STM32_STM32_START_H */ diff --git a/arch/arm/src/stm32/stm32f20xxx_dma.c b/arch/arm/src/stm32/stm32f20xxx_dma.c index f355c9b0acf15df12e3843164a121befea06eef8..8c06819f7a5db56e83bf8f605713d501a2225245 100644 --- a/arch/arm/src/stm32/stm32f20xxx_dma.c +++ b/arch/arm/src/stm32/stm32f20xxx_dma.c @@ -877,7 +877,7 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) * multiply. */ - switch (ccr & STM32_DMA_SCR_MSIZE_MASK) + switch (ccr & DMA_SCR_MSIZE_MASK) { case DMA_SCR_MSIZE_8BITS: transfer_size = 1; @@ -894,7 +894,7 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) mend = maddr + (count << 2) - 1; break; - default + default: return false; } @@ -912,7 +912,7 @@ bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) * is aligned to the burst length. */ - switch (ccr & STM32_DMA_SCR_MBURST_MASK) + switch (ccr & DMA_SCR_MBURST_MASK) { case DMA_SCR_MBURST_SINGLE: burst_length = transfer_size; diff --git a/arch/arm/src/stm32/stm32f30xxx_i2c.c b/arch/arm/src/stm32/stm32f30xxx_i2c.c index 371d749d0d1ed29a596449de09157939a9f0ee52..8778c6ca000fa4786858019a652b9b1294f3d709 100644 --- a/arch/arm/src/stm32/stm32f30xxx_i2c.c +++ b/arch/arm/src/stm32/stm32f30xxx_i2c.c @@ -8,7 +8,7 @@ * With extensions and modifications for the F1, F2, and F4 by: * * Copyright (C) 2011-2013, 2016-2017 Gregory Nutt. All rights reserved. - * Author: Gregroy Nutt + * Author: Gregory Nutt * * And this version for the STM32 F3 by * diff --git a/arch/arm/src/stm32/stm32f33xxx_adc.c b/arch/arm/src/stm32/stm32f33xxx_adc.c index 81b5a671ae11df341556f0a5861ba9c9c81896d2..4eb887e1484a97afea75710a57901079269086e6 100644 --- a/arch/arm/src/stm32/stm32f33xxx_adc.c +++ b/arch/arm/src/stm32/stm32f33xxx_adc.c @@ -74,6 +74,10 @@ #if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + /* This implementation is for the STM32F33XXX only. * * STM32F33XXX chips are intended for digital power conversion applications, @@ -93,23 +97,28 @@ #warning "ADC support for STM32F33XX under development !" -/* HRTIM triggering needs DMA support */ - -#if defined(ADC_HAVE_HRTIM) && !defined(ADC_HAVE_DMA) -# error "ADC HRTIM Triggering support only with DMA" +#if defined(ADC1_INJECTED_CHAN) && !defined(CONFIG_STM32_ADC1_INJECTED) +# warning +#endif +#if defined(ADC2_INJECTED_CHAN) && !defined(CONFIG_STM32_ADC2_INJECTED) +# warning #endif #if defined(CONFIG_STM32_ADC1_INJECTED) || defined(CONFIG_STM32_ADC2_INJECTED) # define ADC_HAVE_INJECTED 1 #endif -#ifdef ADC_HAVE_INJECTED -# error "ADC injected trigger not implemented yet" +#ifndef CONFIG_STM32_ADC1_INJECTED +# define ADC1_INJECTED_CHAN 0 +#else +# define ADC1_HAVE_JEXTSEL +#endif +#ifndef CONFIG_STM32_ADC2_INJECTED +# define ADC2_INJECTED_CHAN 0 +#else +# define ADC2_HAVE_JEXTSEL #endif -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ /* RCC reset ****************************************************************/ #define STM32_RCC_RSTR STM32_RCC_AHBRSTR @@ -135,13 +144,15 @@ #define ADC_IER_AWD ADC_INT_AWD1 #define ADC_ISR_JEOC ADC_INT_JEOC #define ADC_IER_JEOC ADC_INT_JEOC +#define ADC_ISR_JEOS ADC_INT_JEOS +#define ADC_IER_JEOS ADC_INT_JEOS #define ADC_ISR_OVR ADC_INT_OVR #define ADC_IER_OVR ADC_INT_OVR #define ADC_ISR_ALLINTS (ADC_ISR_EOC | ADC_ISR_AWD | ADC_ISR_JEOC | \ - ADC_ISR_OVR) + ADC_ISR_JEOS | ADC_ISR_OVR) #define ADC_IER_ALLINTS (ADC_IER_EOC | ADC_IER_AWD | ADC_IER_JEOC | \ - ADC_IER_OVR) + ADC_IER_JEOS| ADC_IER_OVR) /* ADC Channels/DMA ********************************************************/ /* The maximum number of channels that can be sampled. If DMA support is @@ -375,9 +386,11 @@ struct stm32_dev_s FAR const struct adc_callback_s *cb; uint8_t irq; /* Interrupt generated by this ADC block */ #endif - uint8_t nchannels; /* Number of channels */ + uint8_t rnchannels; /* Number of regular channels */ uint8_t cr_channels; /* Number of configured regular channels */ +#ifdef ADC_HAVE_INJECTED uint8_t cj_channels; /* Number of configured injected channels */ +#endif uint8_t intf; /* ADC interface number */ uint8_t resolution; /* ADC resolution*/ uint8_t current; /* Current ADC channel being converted */ @@ -487,11 +500,13 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable); #ifdef ADC_HAVE_INJECTED static void adc_inj_startconv(FAR struct stm32_dev_s *priv, bool enable); +static int adc_inj_set_ch(FAR struct adc_dev_s *dev, uint8_t ch); #endif #ifdef CONFIG_STM32_ADC_NOIRQ static void adc_intack(FAR struct stm32_adc_dev_s *dev, uint32_t source); static void adc_inten(FAR struct stm32_adc_dev_s *dev, uint32_t source); +static void adc_intdis(FAR struct stm32_adc_dev_s *dev, uint32_t source); static uint32_t adc_intget(FAR struct stm32_adc_dev_s *dev); static uint32_t adc_regget(FAR struct stm32_adc_dev_s *dev); # ifdef ADC_HAVE_DMA @@ -526,6 +541,7 @@ static const struct stm32_adc_ops_s g_adc_lowerops = .int_ack = adc_intack, .int_get = adc_intget, .int_en = adc_inten, + .int_dis = adc_intdis, .val_get = adc_regget, #ifdef ADC_HAVE_DMA .regbuf_reg = adc_regbufregister, @@ -1367,10 +1383,16 @@ static void adc_enable(FAR struct stm32_dev_s *priv, bool enable) } else if ((regval & ADC_CR_ADEN) != 0 && (regval & ADC_CR_ADDIS) == 0) { - /* Stop ongoing conversions */ + /* Stop ongoing regular conversions */ adc_startconv(priv, false); +#ifdef ADC_HAVE_INJECTED + /* Stop ongoing injected conversion */ + + adc_inj_startconv(priv, false); +#endif + /* Disable the ADC */ adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADDIS); @@ -1387,6 +1409,7 @@ static void adc_enable(FAR struct stm32_dev_s *priv, bool enable) * Description: * Callback for DMA. Called from the DMA transfer complete interrupt after * all channels have been converted and transferred with DMA. + * Only for regular conversion. * * Input Parameters: * @@ -1411,12 +1434,12 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg) { DEBUGASSERT(priv->cb->au_receive != NULL); - for (i = 0; i < priv->nchannels; i++) + for (i = 0; i < priv->rnchannels; i++) { priv->cb->au_receive(dev, priv->r_chanlist[priv->current], priv->r_dmabuffer[priv->current]); priv->current++; - if (priv->current >= priv->nchannels) + if (priv->current >= priv->rnchannels) { /* Restart the conversion sequence from the beginning */ @@ -1579,9 +1602,12 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_modifyreg(priv, STM32_ADC_IER_OFFSET, clrbits, setbits); #endif - /* Configuration of the channel conversions */ + /* Configuration of the regular channel conversions */ - adc_set_ch(dev, 0); + if (priv->cr_channels > 0) + { + adc_set_ch(dev, 0); + } /* ADC CCR configuration */ @@ -1618,7 +1644,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) stm32_dmasetup(priv->dma, priv->base + STM32_ADC_DR_OFFSET, (uint32_t)priv->r_dmabuffer, - priv->nchannels, + priv->rnchannels, ADC_DMA_CONTROL_WORD); stm32_dmastart(priv->dma, adc_dmaconvcallback, dev, false); @@ -1631,8 +1657,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_enable(priv, true); - - /* EXTSEL and JEXTSEL selection: These bits select the external event used + /* EXTSEL selection: These bits select the external event used * to trigger the start of conversion of a regular group. NOTE: * * - The position with of the EXTSEL field varies from one STM32 MCU @@ -1653,14 +1678,12 @@ static void adc_reset(FAR struct adc_dev_s *dev) } #endif -#ifdef ADC_HAVE_JEXTSEL - if (priv->jextsel & HAVE_EXTSEL_MASK) - { - ainfo("Initializing jextsel = 0x%08x\n", (priv->jextsel & ~HAVE_EXTSEL_MASK)); +#ifdef ADC_HAVE_INJECTED + /* Configuration of the injected channel conversions after adc enabled */ - adc_modifyreg(priv, STM32_ADC_JEXTREG_OFFSET, - ADC_JEXTREG_JEXTEN_MASK | ADC_JEXTREG_JEXTSEL_MASK, - ADC_JEXTREG_JEXTEN_DEFAULT | (priv->jextsel & ~HAVE_EXTSEL_MASK)); + if (priv->cj_channels > 0) + { + adc_inj_set_ch(dev, 0); } #endif @@ -1680,6 +1703,10 @@ static void adc_reset(FAR struct adc_dev_s *dev) #ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV { adc_startconv(priv, true); + +#ifdef ADC_HAVE_INJECTED + adc_inj_startconv(priv, true); +#endif } #endif @@ -1701,6 +1728,15 @@ static void adc_reset(FAR struct adc_dev_s *dev) { ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC12_CCR)); } + + ainfo("SMPR1: 0x%08x SMPR2: 0x%08x\n", + adc_getreg(priv, STM32_ADC_SMPR1_OFFSET), + adc_getreg(priv, STM32_ADC_SMPR2_OFFSET)); + + ainfo("JSQR: 0x%08x DIFSEL: 0x%08x IER: 0x%08x\n", + adc_getreg(priv, STM32_ADC_JSQR_OFFSET), + adc_getreg(priv, STM32_ADC_DIFSEL_OFFSET), + adc_getreg(priv, STM32_ADC_IER_OFFSET)); } /**************************************************************************** @@ -1835,7 +1871,7 @@ static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first, int last, int i; for (i = first - 1; - i < priv->nchannels && i < last; + i < priv->rnchannels && i < last; i++, offset += ADC_SQ_OFFSET) { bits |= (uint32_t)priv->r_chanlist[i] << offset; @@ -1868,7 +1904,7 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch) if (ch == 0) { priv->current = 0; - priv->nchannels = priv->cr_channels; + priv->rnchannels = priv->cr_channels; } else { @@ -1880,7 +1916,7 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch) } priv->current = i; - priv->nchannels = 1; + priv->rnchannels = 1; } bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET); @@ -1892,13 +1928,46 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch) bits = adc_sqrbits(priv, ADC_SQR2_FIRST, ADC_SQR2_LAST, ADC_SQR2_SQ_OFFSET); adc_modifyreg(priv, STM32_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits); - bits = ((uint32_t)priv->nchannels - 1) << ADC_SQR1_L_SHIFT | + bits = ((uint32_t)priv->rnchannels - 1) << ADC_SQR1_L_SHIFT | adc_sqrbits(priv, ADC_SQR1_FIRST, ADC_SQR1_LAST, ADC_SQR1_SQ_OFFSET); adc_modifyreg(priv, STM32_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits); return OK; } +#ifdef ADC_HAVE_INJECTED +static int adc_inj_set_ch(FAR struct adc_dev_s *dev, uint8_t ch) +{ + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + uint32_t regval; + int i; + + /* Configure JEXTSEL */ + + if (priv->jextsel & HAVE_EXTSEL_MASK) + { + ainfo("Initializing jextsel = 0x%08x\n", (priv->jextsel & ~HAVE_EXTSEL_MASK)); + + regval = ADC_JEXTREG_JEXTEN_DEFAULT | (priv->jextsel & ~HAVE_EXTSEL_MASK); + } + + /* Configure injected sequence length */ + + regval |= ADC_JSQR_JL(priv->cj_channels); + + /* Configure injected channels */ + + for (i = 0 ; i < priv->cj_channels; i += 1) + { + regval |= priv->j_chanlist[i] << (ADC_JSQR_JSQ1_SHIFT + 6 * i); + } + + adc_putreg(priv, STM32_ADC_JSQR_OFFSET, regval); + + return OK; +} +#endif + /**************************************************************************** * Name: adc_ioctl * @@ -1922,13 +1991,31 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) switch (cmd) { case ANIOC_TRIGGER: - adc_startconv(priv, true); - break; + { + /* Start regular conversion if regular channels configured */ + + if (priv->cr_channels > 0) + { + adc_startconv(priv, true); + } +#ifdef ADC_HAVE_INJECTED + /* Start injected conversion if injected channels configured */ + + if (priv->cj_channels > 0) + { + adc_inj_startconv(priv, true); + } +#endif + + break; + } default: - aerr("ERROR: Unknown cmd: %d\n", cmd); - ret = -ENOTTY; - break; + { + aerr("ERROR: Unknown cmd: %d\n", cmd); + ret = -ENOTTY; + break; + } } return ret; @@ -2005,7 +2092,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev) priv->current++; - if (priv->current >= priv->nchannels) + if (priv->current >= priv->rnchannels) { /* Restart the conversion sequence from the beginning */ @@ -2076,6 +2163,19 @@ static void adc_inten(FAR struct stm32_adc_dev_s *dev, uint32_t source) adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, source); } +/**************************************************************************** + * Name: adc_intdis + ****************************************************************************/ + +static void adc_intdis(FAR struct stm32_adc_dev_s *dev, uint32_t source) +{ + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev; + + /* Disable interrupts */ + + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, source, 0); +} + /**************************************************************************** * Name: adc_ackget ****************************************************************************/ @@ -2134,13 +2234,17 @@ static int adc_regbufregister(FAR struct stm32_adc_dev_s *dev, uint16_t *buffer, static uint32_t adc_injget(FAR struct stm32_adc_dev_s *dev, uint8_t chan) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev; + uint32_t regval = 0; - if (chan > priv->cj_channels) + if (chan > priv->cj_channels-1) { - return 0; + goto errout; } - return adc_getreg(priv, STM32_ADC_JDR1_OFFSET+4*(chan-1)) & ADC_JDR_JDATA_MASK; + regval = adc_getreg(priv, STM32_ADC_JDR1_OFFSET+4*(chan)) & ADC_JDR_JDATA_MASK; + +errout: + return regval; } #endif #endif @@ -2155,7 +2259,7 @@ static uint32_t adc_injget(FAR struct stm32_adc_dev_s *dev, uint8_t chan) * Description: * Initialize the ADC. * - * The logic is, save nchannels : # of channels (conversions) in ADC_SQR1_L + * The logic is, save rnchannels : # of channels (conversions) in ADC_SQR1_L * Then, take the chanlist array and store it in the SQR Regs, * chanlist[0] -> ADC_SQR3_SQ1 * chanlist[1] -> ADC_SQR3_SQ2 @@ -2163,7 +2267,7 @@ static uint32_t adc_injget(FAR struct stm32_adc_dev_s *dev, uint8_t chan) * chanlist[15]-> ADC_SQR1_SQ16 * * up to - * chanlist[nchannels] + * chanlist[rnchannels] * * Input Parameters: * intf - Could be {1,2,3} for ADC1, ADC2, or ADC3 @@ -2175,35 +2279,50 @@ static uint32_t adc_injget(FAR struct stm32_adc_dev_s *dev, uint8_t chan) * ****************************************************************************/ -#ifndef ADC_HAVE_INJECTED -struct adc_dev_s *stm32_adcinitialize(int intf, - FAR const uint8_t *r_chanlist, int cr_channels) -#else - struct adc_dev_s *stm32_adcinitialize(int intf, - FAR const uint8_t *r_chanlist, int cr_channels, - FAR const uint8_t *j_chanlist, int cj_channels) -#endif +struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist, + int channels) { - FAR struct adc_dev_s *dev; + FAR struct adc_dev_s *dev; FAR struct stm32_dev_s *priv; + uint8_t cr_channels = 0; +#ifdef ADC_HAVE_INJECTED + uint8_t cj_channels = 0; + FAR uint8_t *j_chanlist = NULL; +#endif switch (intf) { #ifdef CONFIG_STM32_ADC1 case 1: - ainfo("ADC1 selected\n"); - dev = &g_adcdev1; - break; + { + ainfo("ADC1 selected\n"); + dev = &g_adcdev1; + cr_channels = channels - ADC1_INJECTED_CHAN; +#ifdef ADC_HAVE_INJECTED + cj_channels = ADC1_INJECTED_CHAN; + j_chanlist = (FAR uint8_t *)chanlist + cr_channels; +#endif + break; + } #endif #ifdef CONFIG_STM32_ADC2 case 2: - ainfo("ADC2 selected\n"); - dev = &g_adcdev2; - break; + { + ainfo("ADC2 selected\n"); + dev = &g_adcdev2; + cr_channels = channels - ADC2_INJECTED_CHAN; +#ifdef ADC_HAVE_INJECTED + cj_channels = ADC2_INJECTED_CHAN; + j_chanlist = chanlist + cr_channels; +#endif + break; + } #endif default: - aerr("ERROR: No ADC interface defined\n"); - return NULL; + { + aerr("ERROR: No ADC interface defined\n"); + return NULL; + } } /* Configure the selected ADC */ @@ -2215,10 +2334,10 @@ struct adc_dev_s *stm32_adcinitialize(int intf, /* Configure regular channels */ priv->cr_channels = cr_channels; - memcpy(priv->r_chanlist, r_chanlist, cr_channels); + memcpy(priv->r_chanlist, chanlist, cr_channels); #ifdef ADC_HAVE_INJECTED - /* Configur injected channels */ + /* Configure injected channels */ DEBUGASSERT(cj_channels <= ADC_INJ_MAX_SAMPLES); @@ -2232,9 +2351,9 @@ struct adc_dev_s *stm32_adcinitialize(int intf, #ifdef ADC_HAVE_INJECTED ainfo("intf: %d cr_channels: %d, cj_channels: %d\n", - intf, cr_channels, priv->cj_channels); + intf, priv->cr_channels, priv->cj_channels); #else - ainfo("intf: %d cr_channels: %d\n", intf, cr_channels); + ainfo("intf: %d cr_channels: %d\n", intf, priv->cr_channels); #endif return dev; diff --git a/arch/arm/src/stm32/stm32f33xxx_rcc.c b/arch/arm/src/stm32/stm32f33xxx_rcc.c index 76e19858f4b91b79fc15c2c20e6b4ddba487a822..e7908347db7c2266ef035853f28ba81564d92f6e 100644 --- a/arch/arm/src/stm32/stm32f33xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f33xxx_rcc.c @@ -237,7 +237,7 @@ static inline void rcc_enableapb1(void) #ifdef CONFIG_STM32_CAN1 /* CAN1 clock enable */ - regval |= RCC_APB1ENR_CAN1EN; + regval |= RCC_APB1ENR_CANEN; #endif #ifdef CONFIG_STM32_DAC2 diff --git a/arch/arm/src/stm32f0/Kconfig b/arch/arm/src/stm32f0/Kconfig index 16a87ea1435326212d246eb3084c8b0e01e851fe..9bbee102d4a86e331d22e3f7d13f2744703d226f 100644 --- a/arch/arm/src/stm32f0/Kconfig +++ b/arch/arm/src/stm32f0/Kconfig @@ -1470,4 +1470,13 @@ config USART8_RS485_DIR_POLARITY endif # STM32F0_USART8_SERIALDRIVER +if PM +config PM_SERIAL_ACTIVITY + int "PM serial activity" + default 10 + ---help--- + PM activity reported to power management logic on every serial + interrupt. +endif + endmenu diff --git a/arch/arm/src/stm32f0/stm32f0_i2c.c b/arch/arm/src/stm32f0/stm32f0_i2c.c index 3ae93e42ad40d650c7d024332f5d4a960a6751bb..09993e326112e6a5b790e12a7a34c76c2741546c 100644 --- a/arch/arm/src/stm32f0/stm32f0_i2c.c +++ b/arch/arm/src/stm32f0/stm32f0_i2c.c @@ -5,7 +5,7 @@ * Copyright (C) 2011 Uros Platise. All rights reserved. * Author: Uros Platise * Copyright (C) 2011-2013, 2016-2017 Gregory Nutt. All rights reserved. - * Author: Gregroy Nutt + * Author: Gregory Nutt * Author: John Wharington * Author: Sebastien Lorquet * Author: dev@ziggurat29.com diff --git a/arch/arm/src/stm32f0/stm32f0_serial.c b/arch/arm/src/stm32f0/stm32f0_serial.c index 788967c231d46f3b064a8899f820f54d0ba29918..91d6cc9828b9469faeb0339f7d92108ba3a465ef 100644 --- a/arch/arm/src/stm32f0/stm32f0_serial.c +++ b/arch/arm/src/stm32f0/stm32f0_serial.c @@ -176,6 +176,8 @@ #if defined(CONFIG_PM) && !defined(CONFIG_PM_SERIAL_ACTIVITY) # define CONFIG_PM_SERIAL_ACTIVITY 10 +#endif +#if defined(CONFIG_PM) # define PM_IDLE_DOMAIN 0 /* Revisit */ #endif diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index 707555a8021acc95d91592116300e29b76ec893f..9e80a64934b48cf3070b84721cffe06a35735234 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -12,6 +12,134 @@ choice default ARCH_CHIP_STM32F746 depends on ARCH_CHIP_STM32F7 +config ARCH_CHIP_STM32F722RC + bool "STM32F722RC" + select STM32F7_STM32F722XX + select STM32F7_FLASH_CONFIG_C + select STM32F7_IO_CONFIG_R + ---help--- + STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM + +config ARCH_CHIP_STM32F722RE + bool "STM32F722RE" + select STM32F7_STM32F722XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_R + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM + +config ARCH_CHIP_STM32F722VC + bool "STM32F722VC" + select STM32F7_STM32F722XX + select STM32F7_FLASH_CONFIG_C + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM + +config ARCH_CHIP_STM32F722VE + bool "STM32F722VE" + select STM32F7_STM32F722XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM + +config ARCH_CHIP_STM32F722ZC + bool "STM32F722ZC" + select STM32F7_STM32F722XX + select STM32F7_FLASH_CONFIG_C + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM + +config ARCH_CHIP_STM32F722ZE + bool "STM32F722ZE" + select STM32F7_STM32F722XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM + +config ARCH_CHIP_STM32F722IC + bool "STM32F722IC" + select STM32F7_STM32F722XX + select STM32F7_FLASH_CONFIG_C + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM + +config ARCH_CHIP_STM32F722IE + bool "STM32F722IE" + select STM32F7_STM32F722XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM + +config ARCH_CHIP_STM32F723RC + bool "STM32F723RC" + select STM32F7_STM32F723XX + select STM32F7_FLASH_CONFIG_C + select STM32F7_IO_CONFIG_R + ---help--- + STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM + +config ARCH_CHIP_STM32F723RE + bool "STM32F723RE" + select STM32F7_STM32F723XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_R + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM + +config ARCH_CHIP_STM32F723VC + bool "STM32F723VC" + select STM32F7_STM32F723XX + select STM32F7_FLASH_CONFIG_C + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM + +config ARCH_CHIP_STM32F723VE + bool "STM32F723VE" + select STM32F7_STM32F723XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_V + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM + +config ARCH_CHIP_STM32F723ZC + bool "STM32F723ZC" + select STM32F7_STM32F723XX + select STM32F7_FLASH_CONFIG_C + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM + +config ARCH_CHIP_STM32F723ZE + bool "STM32F723ZE" + select STM32F7_STM32F723XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_Z + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM + +config ARCH_CHIP_STM32F723IC + bool "STM32F723IC" + select STM32F7_STM32F723XX + select STM32F7_FLASH_CONFIG_C + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM + +config ARCH_CHIP_STM32F723IE + bool "STM32F723IE" + select STM32F7_STM32F723XX + select STM32F7_FLASH_CONFIG_E + select STM32F7_IO_CONFIG_I + ---help--- + STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM + config ARCH_CHIP_STM32F745VG bool "STM32F745VG" select STM32F7_STM32F745XX @@ -470,6 +598,14 @@ config ARCH_CHIP_STM32F779AI endchoice # STM32 F7 Chip Selection +config STM32F7_STM32F72XX + bool + default n + +config STM32F7_STM32F73XX + bool + default n + config STM32F7_STM32F74XX bool default n @@ -486,6 +622,10 @@ config STM32F7_STM32F77XX bool default n +config STM32F7_IO_CONFIG_R + bool + default n + config STM32F7_IO_CONFIG_V bool default n @@ -510,6 +650,22 @@ config STM32F7_IO_CONFIG_A bool default n +config STM32F7_STM32F722XX + bool + default n + select STM32F7_STM32F72XX + select ARCH_HAVE_FPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32F7_HAVE_FMC + select STM32F7_HAVE_RNG + select STM32F7_HAVE_SPI4 if !STM32F7_IO_CONFIG_R + select STM32F7_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) + select STM32F7_HAVE_CRYP + select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R + config STM32F7_STM32F745XX bool default n @@ -526,6 +682,8 @@ config STM32F7_STM32F745XX select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V select STM32F7_HAVE_DCMI select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_CAN2 + select STM32F7_HAVE_SPI4 config STM32F7_STM32F746XX bool @@ -544,6 +702,8 @@ config STM32F7_STM32F746XX select STM32F7_HAVE_DCMI select STM32F7_HAVE_LTDC select STM32F7_HAVE_DMA2D + select STM32F7_HAVE_CAN2 + select STM32F7_HAVE_SPI4 config STM32F7_STM32F756XX bool @@ -563,6 +723,8 @@ config STM32F7_STM32F756XX select STM32F7_HAVE_DMA2D select STM32F7_HAVE_CRYP select STM32F7_HAVE_HASH + select STM32F7_HAVE_CAN2 + select STM32F7_HAVE_SPI4 config STM32F7_STM32F765XX bool @@ -584,6 +746,8 @@ config STM32F7_STM32F765XX select STM32F7_HAVE_DCMI select STM32F7_HAVE_DMA2D select STM32F7_HAVE_DFSDM1 + select STM32F7_HAVE_CAN2 + select STM32F7_HAVE_SPI4 config STM32F7_STM32F767XX bool @@ -608,6 +772,8 @@ config STM32F7_STM32F767XX select STM32F7_HAVE_DMA2D select STM32F7_HAVE_JPEG select STM32F7_HAVE_DFSDM1 + select STM32F7_HAVE_CAN2 + select STM32F7_HAVE_SPI4 config STM32F7_STM32F768XX # Revisit Wehn parts released bool @@ -632,6 +798,8 @@ config STM32F7_STM32F768XX # Revisit Wehn parts released select STM32F7_HAVE_DMA2D select STM32F7_HAVE_JPEG select STM32F7_HAVE_DFSDM1 + select STM32F7_HAVE_CAN2 + select STM32F7_HAVE_SPI4 config STM32F7_STM32F768AX # Revisit When parts released bool @@ -655,6 +823,8 @@ config STM32F7_STM32F768AX # Revisit When parts released select STM32F7_HAVE_DMA2D select STM32F7_HAVE_JPEG select STM32F7_HAVE_DFSDM1 + select STM32F7_HAVE_CAN2 + select STM32F7_HAVE_SPI4 config STM32F7_STM32F769XX bool @@ -679,6 +849,8 @@ config STM32F7_STM32F769XX select STM32F7_HAVE_DMA2D select STM32F7_HAVE_JPEG select STM32F7_HAVE_DFSDM1 + select STM32F7_HAVE_CAN2 + select STM32F7_HAVE_SPI4 config STM32F7_STM32F769AX # Revisit When parts released bool @@ -702,6 +874,8 @@ config STM32F7_STM32F769AX # Revisit When parts released select STM32F7_HAVE_DMA2D select STM32F7_HAVE_JPEG select STM32F7_HAVE_DFSDM1 + select STM32F7_HAVE_CAN2 + select STM32F7_HAVE_SPI4 config STM32F7_STM32F777XX bool @@ -728,6 +902,8 @@ config STM32F7_STM32F777XX select STM32F7_HAVE_CRYP select STM32F7_HAVE_HASH select STM32F7_HAVE_DFSDM1 + select STM32F7_HAVE_CAN2 + select STM32F7_HAVE_SPI4 config STM32F7_STM32F778XX # Revisit when parts released bool @@ -754,6 +930,8 @@ config STM32F7_STM32F778XX # Revisit when parts released select STM32F7_HAVE_CRYP select STM32F7_HAVE_HASH select STM32F7_HAVE_DFSDM1 + select STM32F7_HAVE_CAN2 + select STM32F7_HAVE_SPI4 config STM32F7_STM32F778AX bool @@ -779,6 +957,8 @@ config STM32F7_STM32F778AX select STM32F7_HAVE_CRYP select STM32F7_HAVE_HASH select STM32F7_HAVE_DFSDM1 + select STM32F7_HAVE_CAN2 + select STM32F7_HAVE_SPI4 config STM32F7_STM32F779XX bool @@ -805,6 +985,8 @@ config STM32F7_STM32F779XX select STM32F7_HAVE_CRYP select STM32F7_HAVE_HASH select STM32F7_HAVE_DFSDM1 + select STM32F7_HAVE_CAN2 + select STM32F7_HAVE_SPI4 config STM32F7_STM32F779AX bool @@ -830,6 +1012,8 @@ config STM32F7_STM32F779AX select STM32F7_HAVE_CRYP select STM32F7_HAVE_HASH select STM32F7_HAVE_DFSDM1 + select STM32F7_HAVE_CAN2 + select STM32F7_HAVE_SPI4 config STM32F7_FLASH_CONFIG_E bool @@ -852,6 +1036,7 @@ choice that designates the FLASH size. Designator Size in KiB + C 256 E 512 G 1024 I 2048 @@ -871,6 +1056,9 @@ choice config STM32F7_FLASH_OVERRIDE_DEFAULT bool "Default" +config STM32F7_FLASH_OVERRIDE_C + bool "C 256KiB" + config STM32F7_FLASH_OVERRIDE_E bool "E 512KiB" @@ -913,6 +1101,10 @@ config STM32F7_HAVE_RNG bool default n +config STM32F7_HAVE_SPI4 + bool + default n + config STM32F7_HAVE_SPI5 bool default n @@ -937,6 +1129,10 @@ config STM32F7_HAVE_ADC3_DMA bool default n +config STM32F7_HAVE_CAN2 + bool + default n + config STM32F7_HAVE_CAN3 bool default n @@ -1269,6 +1465,7 @@ config STM32F7_SPI3 config STM32F7_SPI4 bool "SPI4" default n + depends on STM32F7_HAVE_SPI4 select SPI select STM32F7_SPI @@ -1683,6 +1880,15 @@ config STM32F7_SERIALBRK_BSDCOMPAT on because the SW starts the break and then the HW automatically clears the break. This makes it is difficult to sent a long break. +if PM +config PM_SERIAL_ACTIVITY + int "PM serial activity" + default 10 + ---help--- + PM activity reported to power management logic on every serial + interrupt. +endif + endmenu # U[S]ART Configuration menu "SPI Configuration" diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 283f28e172eabae8f4eabf032ec0075beead2057..ccb0fe66549f1d9f2fcba3e5e35de444c0ce983d 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -47,13 +47,17 @@ CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S CMN_ASRCS += up_testset.S vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c -CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c +CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_memfault.c up_modifyreg8.c CMN_CSRCS += up_modifyreg16.c up_modifyreg32.c up_releasepending.c CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_systemreset.c up_unblocktask.c up_usestack.c CMN_CSRCS += up_doirq.c up_hardfault.c up_svcall.c up_vfork.c +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CMN_CSRCS += up_idle.c +endif + # Configuration-dependent common files ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) diff --git a/arch/arm/src/stm32f7/chip/stm32_adc.h b/arch/arm/src/stm32f7/chip/stm32_adc.h index 9ac5f68107361a4a16923c173ba282c58c411116..9bf8e1940f1cf8feda1117463a28fd2d4cf53c65 100644 --- a/arch/arm/src/stm32f7/chip/stm32_adc.h +++ b/arch/arm/src/stm32f7/chip/stm32_adc.h @@ -44,7 +44,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# include "chip/stm32f72xx73xx_adc.h" +#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) # include "chip/stm32f74xx77xx_adc.h" #else diff --git a/arch/arm/src/stm32f7/chip/stm32_dbgmcu.h b/arch/arm/src/stm32f7/chip/stm32_dbgmcu.h index 73fcd64dccb157d3efd0db9e13ffaf37c05327ae..4f4d348baf79129dcc52dd15b591a9c94fe51520 100644 --- a/arch/arm/src/stm32f7/chip/stm32_dbgmcu.h +++ b/arch/arm/src/stm32f7/chip/stm32_dbgmcu.h @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32f7/chip/stm32_dbgmcu.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016, 2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane * @@ -44,7 +44,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# include "chip/stm32f72xx73xx_dbgmcu.h" +#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_dbgmcu.h" #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) # include "chip/stm32f76xx77xx_dbgmcu.h" diff --git a/arch/arm/src/stm32f7/chip/stm32_dma.h b/arch/arm/src/stm32f7/chip/stm32_dma.h index 64fa967bca6e423f9d7e6dfb43687d6e558ff1bb..2b9bcfeffd7e2e81eb87b3b437756341e19fbdf3 100644 --- a/arch/arm/src/stm32f7/chip/stm32_dma.h +++ b/arch/arm/src/stm32f7/chip/stm32_dma.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32f7/chip/stm32_dma.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane * @@ -44,7 +44,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# include "chip/stm32f72xx73xx_dma.h" +#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_dma.h" #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) # include "chip/stm32f76xx77xx_dma.h" diff --git a/arch/arm/src/stm32f7/chip/stm32_exti.h b/arch/arm/src/stm32f7/chip/stm32_exti.h index 8663d2f08e7e7b391854fd3e7f632f78e0e50f60..e7de6b6953e4936f9ab1cfafefca608e048617dd 100644 --- a/arch/arm/src/stm32f7/chip/stm32_exti.h +++ b/arch/arm/src/stm32f7/chip/stm32_exti.h @@ -1,9 +1,10 @@ /************************************************************************************ * arch/arm/src/stm32f7/chip/stm32_exti.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane + * Bob Feretich * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -48,7 +49,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \ + defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /************************************************************************************ diff --git a/arch/arm/src/stm32f7/chip/stm32_flash.h b/arch/arm/src/stm32f7/chip/stm32_flash.h index d20bdfe4d33ef60da4151d1b4e9ebab0ad90c49d..91554fe44b3237e1744fff94aa8e6bf37ac65320 100644 --- a/arch/arm/src/stm32f7/chip/stm32_flash.h +++ b/arch/arm/src/stm32f7/chip/stm32_flash.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32f7/chip/stm32_flash.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane * @@ -44,7 +44,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# include "chip/stm32f72xx73xx_flash.h" +#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_flash.h" #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) # include "chip/stm32f76xx77xx_flash.h" diff --git a/arch/arm/src/stm32f7/chip/stm32_gpio.h b/arch/arm/src/stm32f7/chip/stm32_gpio.h index 06431bb787dd4c73008fbf41490209d064e209e6..1d6478e59e4feda3a80213261d5374b08ecfae0e 100644 --- a/arch/arm/src/stm32f7/chip/stm32_gpio.h +++ b/arch/arm/src/stm32f7/chip/stm32_gpio.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32f7/chip/stm32_gpio.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane * @@ -44,7 +44,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# include "chip/stm32f72xx73xx_gpio.h" +#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_gpio.h" #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) # include "chip/stm32f76xx77xx_gpio.h" diff --git a/arch/arm/src/stm32f7/chip/stm32_i2c.h b/arch/arm/src/stm32f7/chip/stm32_i2c.h index f615eb6ec18f0e9df6fda4901be642696a23d012..b1c295c196a4b396e925341d570531564704087c 100644 --- a/arch/arm/src/stm32f7/chip/stm32_i2c.h +++ b/arch/arm/src/stm32f7/chip/stm32_i2c.h @@ -1,9 +1,10 @@ /************************************************************************************ * arch/arm/src/stm32f7/chip/stm32_i2c.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane + * Bob Feretich * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -44,7 +45,8 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \ + defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) # include "chip/stm32f74xx77xx_i2c.h" #else diff --git a/arch/arm/src/stm32f7/chip/stm32_memorymap.h b/arch/arm/src/stm32f7/chip/stm32_memorymap.h index eba94016fd1e7202f3888e0040ad3d2f9632ee1c..591c482a5dd94c65fb23dc7f142a05a177b41afc 100644 --- a/arch/arm/src/stm32f7/chip/stm32_memorymap.h +++ b/arch/arm/src/stm32f7/chip/stm32_memorymap.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32f7/chip/stm32_memorymap.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane * @@ -44,7 +44,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# include "chip/stm32f72xx73xx_memorymap.h" +#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_memorymap.h" #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) # include "chip/stm32f76xx77xx_memorymap.h" diff --git a/arch/arm/src/stm32f7/chip/stm32_pinmap.h b/arch/arm/src/stm32f7/chip/stm32_pinmap.h index 034e32166eb229ed25ca0467f989ac741aa4778d..a6d106b1f678e1c11541b23f31a4745f663fd27d 100644 --- a/arch/arm/src/stm32f7/chip/stm32_pinmap.h +++ b/arch/arm/src/stm32f7/chip/stm32_pinmap.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32f7/chip/stm32_pinmap.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane * @@ -44,7 +44,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# include "chip/stm32f72xx73xx_pinmap.h" +#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_pinmap.h" #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) # include "chip/stm32f76xx77xx_pinmap.h" diff --git a/arch/arm/src/stm32f7/chip/stm32_pwr.h b/arch/arm/src/stm32f7/chip/stm32_pwr.h index e9415d800a7c78766d29ade47bf8865b598f9dae..080fd75496128c65a4702920b84d5f4e5afeb707 100644 --- a/arch/arm/src/stm32f7/chip/stm32_pwr.h +++ b/arch/arm/src/stm32f7/chip/stm32_pwr.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32f7/chip/stm32_pwr.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane * @@ -44,7 +44,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# include "chip/stm32f72xx73xx_pwr.h" +#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_pwr.h" #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) # include "chip/stm32f76xx77xx_pwr.h" diff --git a/arch/arm/src/stm32f7/chip/stm32_rcc.h b/arch/arm/src/stm32f7/chip/stm32_rcc.h index e2dfc8380f987400cf5130ff1cf5a0a1472a0fae..c4fa94a933712f77408f9ab74b95f2e44eae4573 100644 --- a/arch/arm/src/stm32f7/chip/stm32_rcc.h +++ b/arch/arm/src/stm32f7/chip/stm32_rcc.h @@ -1,6 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32f7/chip/stm32_rcc.h * + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane * @@ -43,7 +44,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# include "chip/stm32f72xx73xx_rcc.h" +#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_rcc.h" #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) # include "chip/stm32f76xx77xx_rcc.h" diff --git a/arch/arm/src/stm32f7/chip/stm32_sdmmc.h b/arch/arm/src/stm32f7/chip/stm32_sdmmc.h index 016ddb18fb9eba5cd86a35b1c4829d398354ab29..cd890d2927318573b6a1de5686eb8e0e0083befb 100644 --- a/arch/arm/src/stm32f7/chip/stm32_sdmmc.h +++ b/arch/arm/src/stm32f7/chip/stm32_sdmmc.h @@ -1,9 +1,10 @@ /************************************************************************************ * arch/arm/src/stm32f7/chip/stm32_sdmmc.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane + * Bob Feretich * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -44,7 +45,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# include "stm32f72xx73xx_sdmmc.h" +#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) # include "stm32f74xx77xx_sdmmc.h" #else diff --git a/arch/arm/src/stm32f7/chip/stm32_spi.h b/arch/arm/src/stm32f7/chip/stm32_spi.h index 1874d88bca62f4b3c662db89cfd3f211cceedf75..64db932c32eb3d12ff4b3c73c0d39413a1e8fd84 100644 --- a/arch/arm/src/stm32f7/chip/stm32_spi.h +++ b/arch/arm/src/stm32f7/chip/stm32_spi.h @@ -1,9 +1,10 @@ /************************************************************************************ * arch/arm/src/stm32f7/chip/stm32_spi.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane + * Bob Feretich * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -44,7 +45,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# include "chip/stm32f72xx73xx_spi.h" +#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) # include "chip/stm32f74xx77xx_spi.h" #else diff --git a/arch/arm/src/stm32f7/chip/stm32_syscfg.h b/arch/arm/src/stm32f7/chip/stm32_syscfg.h index b17bc518aa2cce7ce9ba6ece9adc10b6051c14e1..8d0a6340c70bb637bfdc4208d586e8aa4d580859 100644 --- a/arch/arm/src/stm32f7/chip/stm32_syscfg.h +++ b/arch/arm/src/stm32f7/chip/stm32_syscfg.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32f7/chip/stm32_syscfg.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane * @@ -44,7 +44,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# include "chip/stm32f72xx73xx_syscfg.h" +#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_syscfg.h" #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) # include "chip/stm32f76xx77xx_syscfg.h" diff --git a/arch/arm/src/stm32f7/chip/stm32_tim.h b/arch/arm/src/stm32f7/chip/stm32_tim.h index 77204d861d813fc912d22e7ada7516ac2beb213b..672f97667a374973711a699e54d74afbf8c87cbe 100644 --- a/arch/arm/src/stm32f7/chip/stm32_tim.h +++ b/arch/arm/src/stm32f7/chip/stm32_tim.h @@ -44,7 +44,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# include "chip/stm32f72xx73xx_tim.h" +#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "chip/stm32f74xx75xx_tim.h" #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) # include "chip/stm32f76xx77xx_tim.h" diff --git a/arch/arm/src/stm32f7/chip/stm32_uart.h b/arch/arm/src/stm32f7/chip/stm32_uart.h index 7669c675cc39162f66ccbf78492dd8c52b6ac005..c86940e0fc2c0c84cbd2be59feeccccd9dc8517a 100644 --- a/arch/arm/src/stm32f7/chip/stm32_uart.h +++ b/arch/arm/src/stm32f7/chip/stm32_uart.h @@ -44,7 +44,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# include "chip/stm32f72xx73xx_uart.h" +#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) # include "chip/stm32f74xx77xx_uart.h" #else diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_adc.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..55e12efb6b2b6cbcae3fc3b68578ae853ea09a68 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_adc.h @@ -0,0 +1,485 @@ +/**************************************************************************************************** + * arch/arm/src/stm32f7/chip/stm32f72xx73xx_adc.h + * + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */ +#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */ +#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */ +#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */ +#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */ +#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */ +#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */ +#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */ +#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */ +#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */ +#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */ +#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */ +#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */ +#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */ +#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */ +#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */ + + +#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ +#define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */ +#define STM32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */ + +/* Register Addresses *******************************************************************************/ + +#if STM32F7_NADC > 0 +# define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET) +# define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET) +# define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET) +# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC1_HTR (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET) +# define STM32_ADC1_LTR (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET) +# define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET) +# define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET) +# define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET) +# define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET) +# define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET) +# define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET) +# define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET) +# define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET) +# define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) +#endif + +#if STM32F7_NADC > 1 +# define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET) +# define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET) +# define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET) +# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC2_HTR (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET) +# define STM32_ADC2_LTR (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET) +# define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET) +# define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET) +# define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET) +# define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET) +# define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET) +# define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET) +# define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET) +# define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET) +# define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) +#endif + +#if STM32F7_NADC > 2 +# define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET) +# define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET) +# define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET) +# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC3_JOFR1 (STM32_ADC3_BASE+STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC3_JOFR2 (STM32_ADC3_BASE+STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC3_JOFR3 (STM32_ADC3_BASE+STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC3_JOFR4 (STM32_ADC3_BASE+STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC3_HTR (STM32_ADC3_BASE+STM32_ADC_HTR_OFFSET) +# define STM32_ADC3_LTR (STM32_ADC3_BASE+STM32_ADC_LTR_OFFSET) +# define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET) +# define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET) +# define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET) +# define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET) +# define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET) +# define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET) +# define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET) +# define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET) +# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET) +#endif + +#define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET) +#define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET) +#define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ + +/* ADC status register */ + +#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */ +#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */ +#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */ +#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */ +#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */ +#define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */ + +/* ADC control register 1 */ + +#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */ +#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT) +#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */ +#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */ +#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */ +#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */ +#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */ +#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */ +#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT) +#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */ +#define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */ +#define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT) +#define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles. For STM32L15XX: 12 ADCCLK cycles */ +#define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles. For STM32L15XX: 11 ADCCLK cycles */ +#define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles. For STM32L15XX: 9 ADCCLK cycles */ +#define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles. For STM32L15XX: 7 ADCCLK cycles */ +#define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */ + +/* ADC control register 2 */ + +#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */ +#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */ +#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */ +#define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */ +#define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */ +#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */ + /* Bits 12-15: Reserved */ +#define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */ +#define ADC_CR2_JEXTSEL_MASK (0x0f << ADC_CR2_JEXTSEL_SHIFT) +#define ADC_CR2_JEXTSEL_T1TRGO (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 TRGO event */ +#define ADC_CR2_JEXTSEL_T1CC4 (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 CC4 event */ +#define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event */ +#define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */ +#define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */ +#define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */ + /* 0110: NA */ +#define ADC_CR2_JEXTSEL_T8CC4 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 8 CC4 event */ +#define ADC_CR2_JEXTSEL_T1TRGO2 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 1 TRGO2 event */ +#define ADC_CR2_JEXTSEL_T8TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 8 TRGO event */ +#define ADC_CR2_JEXTSEL_T8TRGO2 (0x0a << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 8 TRGO2 event */ +#define ADC_CR2_JEXTSEL_T3CC3 (0x0b << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 3 CC3 event */ +#define ADC_CR2_JEXTSEL_T5TRGO (0x0c << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 5 TRGO event */ +#define ADC_CR2_JEXTSEL_T3CC1 (0x0d << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 3 CC1 event */ +#define ADC_CR2_JEXTSEL_T6TRGO (0x0e << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 6 TRGO event */ + /* 1111: Reserved */ +#define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */ +#define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT) +#define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ +#define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ +#define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ +#define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ +#define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */ + /* Bit 23: Reserved, must be kept at reset value. */ +#define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */ +#define ADC_CR2_EXTSEL_MASK (0x0f << ADC_CR2_EXTSEL_SHIFT) +#define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */ +#define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */ +#define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */ +#define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */ +#define ADC_CR2_EXTSEL_T5TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 5 TRGO event */ +#define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */ +#define ADC_CR2_EXTSEL_T3CC4 (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 3 CC4 event */ +#define ADC_CR2_EXTSEL_T8TRGO (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 8 TRGO event */ +#define ADC_CR2_EXTSEL_T8TRGO2 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 8 TRGO2 event */ +#define ADC_CR2_EXTSEL_T1TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 1 TRGO event */ +#define ADC_CR2_EXTSEL_T1TRGO2 (0x0a << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 1 TRGO2 event */ +#define ADC_CR2_EXTSEL_T2TRGO (0x0b << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 2 TRGO event */ +#define ADC_CR2_EXTSEL_T4TRGO (0x0c << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 4 TRGO event */ +#define ADC_CR2_EXTSEL_T6TRGO (0x0d << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */ + /* 1110: NA */ +#define ADC_CR2_EXTSEL_EXTI11 (0x0f << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */ +#define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */ +#define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT) +#define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */ +#define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ +#define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ +#define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ + +# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */ + +/* ADC sample time register 1 */ + +#define ADC_SMPR_3 0 /* 000: 3 cycles */ +#define ADC_SMPR_15 1 /* 001: 15 cycles */ +#define ADC_SMPR_28 2 /* 010: 28 cycles */ +#define ADC_SMPR_56 3 /* 011: 56 cycles */ +#define ADC_SMPR_84 4 /* 100: 84 cycles */ +#define ADC_SMPR_112 5 /* 101: 112 cycles */ +#define ADC_SMPR_144 6 /* 110: 144 cycles */ +#define ADC_SMPR_480 7 /* 111: 480 cycles */ +#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ +#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT) +#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ +#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT) +#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ +#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT) +#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ +#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT) +#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ +#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT) +#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ +#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT) +#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ +#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT) +#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ +#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT) +#define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ +#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP18_SHIFT) + + +/* ADC sample time register 2 */ + +#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */ +#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT) +#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ +#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT) +#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ +#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT) +#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ +#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT) +#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ +#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT) +#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ +#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT) +#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ +#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT) +#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ +#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT) +#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ +#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT) +#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ +#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT) + + +/* ADC injected channel data offset register 1-4 */ + +#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */ +#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT) + +/* ADC watchdog high threshold register */ + +#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */ +#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT) + +/* ADC watchdog low threshold register */ + +#define ADC_LTR_SHIFT (0) /* Bits 11-0: Analog watchdog low threshold */ +#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT) + +/* ADC regular sequence register 1 */ + +#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */ +#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT) +#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */ +#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT) +#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */ +#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT) +#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */ +#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT) +#define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */ +#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT) +#define ADC_SQR1_RESERVED (0xff000000) +#define ADC_SQR1_FIRST (13) +#define ADC_SQR1_LAST (16) +#define ADC_SQR1_SQ_OFFSET (0) + +/* ADC regular sequence register 2 */ + +#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT) +#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) +#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) +#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */ +#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT) +#define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */ +#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT ) +#define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */ +#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT) +#define ADC_SQR2_RESERVED (0xc0000000) +#define ADC_SQR2_FIRST (7) +#define ADC_SQR2_LAST (12) +#define ADC_SQR2_SQ_OFFSET (0) + +/* ADC regular sequence register 3 */ + +#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */ +#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT) +#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */ +#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT) +#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */ +#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT) +#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */ +#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT) +#define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */ +#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT ) +#define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */ +#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT) +#define ADC_SQR3_RESERVED (0xc0000000) +#define ADC_SQR3_FIRST (1) +#define ADC_SQR3_LAST (6) +#define ADC_SQR3_SQ_OFFSET (0) + +/* Offset between SQ bits */ + +#define ADC_SQ_OFFSET (5) + +/* ADC injected sequence register */ + +#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) +#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT) +#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) +#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT) +#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */ +#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT) + +/* ADC injected data register 1-4 */ + +#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */ +#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) + +/* ADC regular data register */ + +#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */ +#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) + +/* Common status register */ + +#define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */ +#define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */ +#define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */ +#define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */ +#define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */ +#define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */ + +#define ADC_CSR_AWD2 (1 << 8) /* Bit 8: Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */ +#define ADC_CSR_EOC2 (1 << 9) /* Bit 9: End of conversion of ADC2 (copy of EOC in ADC2_SR) */ +#define ADC_CSR_JEOC2 (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */ +#define ADC_CSR_JSTRT2 (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */ +#define ADC_CSR_STRT2 (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */ +#define ADC_CSR_OVR2 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */ + /* Bits 14-15: Reserved, must be kept at reset value. */ +#define ADC_CSR_AWD3 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */ +#define ADC_CSR_EOC3 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */ +#define ADC_CSR_JEOC3 (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */ +#define ADC_CSR_JSTRT3 (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */ +#define ADC_CSR_STRT3 (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */ +#define ADC_CSR_OVR3 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */ + +/* Common control register */ + +# define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */ +# define ADC_CCR_MULTI_MASK (0x1f << ADC_CCR_MULTI_SHIFT) +# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */ + /* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */ +# define ADC_CCR_MULTI_RSISM2 (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */ +# define ADC_CCR_MULTI_RSATM2 (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */ +# define ADC_CCR_MULTI_ISM2 (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */ +# define ADC_CCR_MULTI_RSM2 (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */ +# define ADC_CCR_MULTI_IM2 (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */ +# define ADC_CCR_MULTI_ATM2 (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */ + /* 10001 to 11001: Triple mode (ADC1, 2 and 3) */ +# define ADC_CCR_MULTI_RSISM3 (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */ +# define ADC_CCR_MULTI_RSATM3 (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */ +# define ADC_CCR_MULTI_ISM3 (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */ +# define ADC_CCR_MULTI_RSM3 (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */ +# define ADC_CCR_MULTI_IM3 (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */ +# define ADC_CCR_MULTI_ATM3 (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */ + /* Bits 5-7: Reserved, must be kept at reset value. */ +# define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ +# define ADC_CCR_DELAY_MASK (0xf << ADC_CCR_DELAY_SHIFT) +# define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */ + /* Bit 12 Reserved, must be kept at reset value. */ +# define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */ + +# define ADC_CCR_DMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for multi ADC mode */ +# define ADC_CCR_DMA_MASK (3 << ADC_CCR_DMA_SHIFT) +# define ADC_CCR_DMA_DISABLED (0 << ADC_CCR_DMA_SHIFT) /* 00: DMA mode disabled */ +# define ADC_CCR_DMA_MODE1 (1 << ADC_CCR_DMA_SHIFT) /* 01: DMA mode 1 enabled */ +# define ADC_CCR_DMA_MODE2 (2 << ADC_CCR_DMA_SHIFT) /* 10: DMA mode 2 enabled */ +# define ADC_CCR_DMA_MODE3 (3 << ADC_CCR_DMA_SHIFT) /* 11: DMA mode 3 enabled */ + +# define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */ +# define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT) +# define ADC_CCR_ADCPRE_DIV2 (0 << ADC_CCR_ADCPRE_SHIFT) /* 00: PCLK2 divided by 2 */ +# define ADC_CCR_ADCPRE_DIV4 (1 << ADC_CCR_ADCPRE_SHIFT) /* 01: PCLK2 divided by 4 */ +# define ADC_CCR_ADCPRE_DIV6 (2 << ADC_CCR_ADCPRE_SHIFT) /* 10: PCLK2 divided by 6 */ +# define ADC_CCR_ADCPRE_DIV8 (3 << ADC_CCR_ADCPRE_SHIFT) /* 11: PCLK2 divided by 8 */ + /* Bits 18-21: Reserved, must be kept at reset value. */ +# define ADC_CCR_VBATE (1 << 22) /* Bit 22: VBAT enable */ +# define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */ + /* Bits 24-31 Reserved, must be kept at reset value. */ + +/* Data register for dual and triple modes (32-bit data with no named fields) */ + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Function Prototypes + ****************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_dbgmcu.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_dbgmcu.h new file mode 100644 index 0000000000000000000000000000000000000000..5d6bda71b58c5ad67359c32c45f44d2557d01e53 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_dbgmcu.h @@ -0,0 +1,108 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/chip/stm32f72xx73xx_dbgmcu.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XXDBGMCU_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XXDBGMCU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Addresses *******************************************************/ + +#define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */ +#define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */ +#define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */ +#define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */ + +/* Register Bitfield Definitions ********************************************/ + +/* MCU identifier */ + +#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */ +#define DBGMCU_IDCODE_DEVID_MASK (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT) +#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */ +#define DBGMCU_IDCODE_REVID_MASK (0xffff << DBGMCU_IDCODE_REVID_SHIFT) + +/* MCU debug */ + +#define DBGMCU_CR_SLEEP (1 << 0) /* Bit 0: Debug Sleep Mode */ +#define DBGMCU_CR_STOP (1 << 1) /* Bit 1: Debug Stop Mode */ +#define DBGMCU_CR_STANDBY (1 << 2) /* Bit 2: Debug Standby mode */ +#define DBGMCU_CR_TRACEIOEN (1 << 5) /* Bit 5: Trace enabled */ + +#define DBGMCU_CR_TRACEMODE_SHIFT (6) /* Bits 7-6: Trace mode pin assignement */ +#define DBGMCU_CR_TRACEMODE_MASK (3 << DBGMCU_CR_TRACEMODE_SHIFT) +#define DBGMCU_CR_ASYNCH (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */ + +/* Debug MCU APB1 freeze register */ + +#define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ +#define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ +#define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */ +#define DBGMCU_APB1_TIM5STOP (1 << 3) /* Bit 3: TIM5 stopped when core is halted */ +#define DBGMCU_APB1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */ +#define DBGMCU_APB1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */ +#define DBGMCU_APB1_TIM12STOP (1 << 6) /* Bit 6: TIM12 stopped when core is halted */ +#define DBGMCU_APB1_TIM13STOP (1 << 7) /* Bit 7: TIM13 stopped when core is halted */ +#define DBGMCU_APB1_TIM14STOP (1 << 8) /* Bit 8: TIM14 stopped when core is halted */ +#define DBGMCU_APB1_LPTIM1STOP (1 << 9) /* Bit 9: LPTIM1 stopped when core is halted */ +#define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */ +#define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */ +#define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */ +#define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: I2C1 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */ + +/* Debug MCU APB2 freeze register */ + +#define DBGMCU_APB2_TIM1STOP (1 << 0) /* Bit 0: TIM1 stopped when core is halted */ +#define DBGMCU_APB2_TIM8STOP (1 << 1) /* Bit 1: TIM8 stopped when core is halted */ +#define DBGMCU_APB2_TIM9STOP (1 << 16) /* Bit 16: TIM9 stopped when core is halted */ +#define DBGMCU_APB2_TIM10STOP (1 << 17) /* Bit 17: TIM10 stopped when core is halted */ +#define DBGMCU_APB2_TIM11STOP (1 << 18) /* Bit 18: TIM11 stopped when core is halted */ + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX74XXDBGMCU_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_dma.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..cf95c80dd80146042ed63e3d2c450ed54aea9bdd --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_dma.h @@ -0,0 +1,546 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f72xx73xx_dma.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XXX73XX_DMA_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XXX73XX_DMA_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* 2 DMA controllers */ + +#define DMA1 (0) +#define DMA2 (1) + +/* 8 DMA streams */ + +#define DMA_STREAM0 (0) +#define DMA_STREAM1 (1) +#define DMA_STREAM2 (2) +#define DMA_STREAM3 (3) +#define DMA_STREAM4 (4) +#define DMA_STREAM5 (5) +#define DMA_STREAM6 (6) +#define DMA_STREAM7 (7) + +/* 8 DMA channels (plus Chan 11?) */ + +#define DMA_CHAN0 (0) +#define DMA_CHAN1 (1) +#define DMA_CHAN2 (2) +#define DMA_CHAN3 (3) +#define DMA_CHAN4 (4) +#define DMA_CHAN5 (5) +#define DMA_CHAN6 (6) +#define DMA_CHAN7 (7) +#define DMA_CHAN11 (11) /* This is suspicious. */ + +/* Register Offsets *****************************************************************/ + +#define STM32_DMA_LISR_OFFSET 0x0000 /* DMA low interrupt status register */ +#define STM32_DMA_HISR_OFFSET 0x0004 /* DMA high interrupt status register */ +#define STM32_DMA_LIFCR_OFFSET 0x0008 /* DMA low interrupt flag clear register */ +#define STM32_DMA_HIFCR_OFFSET 0x000c /* DMA high interrupt flag clear register */ + +#define STM32_DMA_OFFSET(n) (0x0010+0x0018*(n)) +#define STM32_DMA_SCR_OFFSET 0x0000 /* DMA stream n configuration register */ +#define STM32_DMA_SNDTR_OFFSET 0x0004 /* DMA stream n number of data register */ +#define STM32_DMA_SPAR_OFFSET 0x0008 /* DMA stream n peripheral address register */ +#define STM32_DMA_SM0AR_OFFSET 0x000c /* DMA stream n memory 0 address register */ +#define STM32_DMA_SM1AR_OFFSET 0x0010 /* DMA stream n memory 1 address register */ +#define STM32_DMA_SFCR_OFFSET 0x0014 /* DMA stream n FIFO control register */ + +#define STM32_DMA_S0CR_OFFSET 0x0010 /* DMA stream 0 configuration register */ +#define STM32_DMA_S1CR_OFFSET 0x0028 /* DMA stream 1 configuration register */ +#define STM32_DMA_S2CR_OFFSET 0x0040 /* DMA stream 2 configuration register */ +#define STM32_DMA_S3CR_OFFSET 0x0058 /* DMA stream 3 configuration register */ +#define STM32_DMA_S4CR_OFFSET 0x0070 /* DMA stream 4 configuration register */ +#define STM32_DMA_S5CR_OFFSET 0x0088 /* DMA stream 5 configuration register */ +#define STM32_DMA_S6CR_OFFSET 0x00a0 /* DMA stream 6 configuration register */ +#define STM32_DMA_S7CR_OFFSET 0x00b8 /* DMA stream 7 configuration register */ + +#define STM32_DMA_S0NDTR_OFFSET 0x0014 /* DMA stream 0 number of data register */ +#define STM32_DMA_S1NDTR_OFFSET 0x002c /* DMA stream 1 number of data register */ +#define STM32_DMA_S2NDTR_OFFSET 0x0044 /* DMA stream 2 number of data register */ +#define STM32_DMA_S3NDTR_OFFSET 0x005c /* DMA stream 3 number of data register */ +#define STM32_DMA_S4NDTR_OFFSET 0x0074 /* DMA stream 4 number of data register */ +#define STM32_DMA_S5NDTR_OFFSET 0x008c /* DMA stream 5 number of data register */ +#define STM32_DMA_S6NDTR_OFFSET 0x00a4 /* DMA stream 6 number of data register */ +#define STM32_DMA_S7NDTR_OFFSET 0x00bc /* DMA stream 7 number of data register */ + +#define STM32_DMA_S0PAR_OFFSET 0x0018 /* DMA stream 0 peripheral address register */ +#define STM32_DMA_S1PAR_OFFSET 0x0030 /* DMA stream 1 peripheral address register */ +#define STM32_DMA_S2PAR_OFFSET 0x0048 /* DMA stream 2 peripheral address register */ +#define STM32_DMA_S3PAR_OFFSET 0x0060 /* DMA stream 3 peripheral address register */ +#define STM32_DMA_S4PAR_OFFSET 0x0078 /* DMA stream 4 peripheral address register */ +#define STM32_DMA_S5PAR_OFFSET 0x0090 /* DMA stream 5 peripheral address register */ +#define STM32_DMA_S6PAR_OFFSET 0x00a8 /* DMA stream 6 peripheral address register */ +#define STM32_DMA_S7PAR_OFFSET 0x00c0 /* DMA stream 7 peripheral address register */ + +#define STM32_DMA_S0M0AR_OFFSET 0x001c /* DMA stream 0 memory 0 address register */ +#define STM32_DMA_S1M0AR_OFFSET 0x0034 /* DMA stream 1 memory 0 address register */ +#define STM32_DMA_S2M0AR_OFFSET 0x004c /* DMA stream 2 memory 0 address register */ +#define STM32_DMA_S3M0AR_OFFSET 0x0064 /* DMA stream 3 memory 0 address register */ +#define STM32_DMA_S4M0AR_OFFSET 0x007c /* DMA stream 4 memory 0 address register */ +#define STM32_DMA_S5M0AR_OFFSET 0x0094 /* DMA stream 5 memory 0 address register */ +#define STM32_DMA_S6M0AR_OFFSET 0x00ac /* DMA stream 6 memory 0 address register */ +#define STM32_DMA_S7M0AR_OFFSET 0x00c4 /* DMA stream 7 memory 0 address register */ + +#define STM32_DMA_S0M1AR_OFFSET 0x0020 /* DMA stream 0 memory 1 address register */ +#define STM32_DMA_S1M1AR_OFFSET 0x0038 /* DMA stream 1 memory 1 address register */ +#define STM32_DMA_S2M1AR_OFFSET 0x0050 /* DMA stream 2 memory 1 address register */ +#define STM32_DMA_S3M1AR_OFFSET 0x0068 /* DMA stream 3 memory 1 address register */ +#define STM32_DMA_S4M1AR_OFFSET 0x0080 /* DMA stream 4 memory 1 address register */ +#define STM32_DMA_S5M1AR_OFFSET 0x0098 /* DMA stream 5 memory 1 address register */ +#define STM32_DMA_S6M1AR_OFFSET 0x00b0 /* DMA stream 6 memory 1 address register */ +#define STM32_DMA_S7M1AR_OFFSET 0x00c8 /* DMA stream 7 memory 1 address register */ + +#define STM32_DMA_S0FCR_OFFSET 0x0024 /* DMA stream 0 FIFO control register */ +#define STM32_DMA_S1FCR_OFFSET 0x003c /* DMA stream 1 FIFO control register */ +#define STM32_DMA_S2FCR_OFFSET 0x0054 /* DMA stream 2 FIFO control register */ +#define STM32_DMA_S3FCR_OFFSET 0x006c /* DMA stream 3 FIFO control register */ +#define STM32_DMA_S4FCR_OFFSET 0x0084 /* DMA stream 4 FIFO control register */ +#define STM32_DMA_S5FCR_OFFSET 0x009c /* DMA stream 5 FIFO control register */ +#define STM32_DMA_S6FCR_OFFSET 0x00b4 /* DMA stream 6 FIFO control register */ +#define STM32_DMA_S7FCR_OFFSET 0x00cc /* DMA stream 7 FIFO control register */ + +/* Register Addresses ***************************************************************/ + +#define STM32_DMA1_LISRC (STM32_DMA1_BASE+STM32_DMA_LISR_OFFSET) +#define STM32_DMA1_HISRC (STM32_DMA1_BASE+STM32_DMA_HISR_OFFSET) +#define STM32_DMA1_LIFCR (STM32_DMA1_BASE+STM32_DMA_LIFCR_OFFSET) +#define STM32_DMA1_HIFCR (STM32_DMA1_BASE+STM32_DMA_HIFCR_OFFSET) + +#define STM32_DMA1_SCR(n) (STM32_DMA1_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0CR (STM32_DMA1_BASE+STM32_DMA_S0CR_OFFSET) +#define STM32_DMA1_S1CR (STM32_DMA1_BASE+STM32_DMA_S1CR_OFFSET) +#define STM32_DMA1_S2CR (STM32_DMA1_BASE+STM32_DMA_S2CR_OFFSET) +#define STM32_DMA1_S3CR (STM32_DMA1_BASE+STM32_DMA_S3CR_OFFSET) +#define STM32_DMA1_S4CR (STM32_DMA1_BASE+STM32_DMA_S4CR_OFFSET) +#define STM32_DMA1_S5CR (STM32_DMA1_BASE+STM32_DMA_S5CR_OFFSET) +#define STM32_DMA1_S6CR (STM32_DMA1_BASE+STM32_DMA_S6CR_OFFSET) +#define STM32_DMA1_S7CR (STM32_DMA1_BASE+STM32_DMA_S7CR_OFFSET) + +#define STM32_DMA1_SNDTR(n) (STM32_DMA1_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0NDTR (STM32_DMA1_BASE+STM32_DMA_S0NDTR_OFFSET) +#define STM32_DMA1_S1NDTR (STM32_DMA1_BASE+STM32_DMA_S1NDTR_OFFSET) +#define STM32_DMA1_S2NDTR (STM32_DMA1_BASE+STM32_DMA_S2NDTR_OFFSET) +#define STM32_DMA1_S3NDTR (STM32_DMA1_BASE+STM32_DMA_S3NDTR_OFFSET) +#define STM32_DMA1_S4NDTR (STM32_DMA1_BASE+STM32_DMA_S4NDTR_OFFSET) +#define STM32_DMA1_S5NDTR (STM32_DMA1_BASE+STM32_DMA_S5NDTR_OFFSET) +#define STM32_DMA1_S6NDTR (STM32_DMA1_BASE+STM32_DMA_S6NDTR_OFFSET) +#define STM32_DMA1_S7NDTR (STM32_DMA1_BASE+STM32_DMA_S7NDTR_OFFSET) + +#define STM32_DMA1_SPAR(n) (STM32_DMA1_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0PAR (STM32_DMA1_BASE+STM32_DMA_S0PAR_OFFSET) +#define STM32_DMA1_S1PAR (STM32_DMA1_BASE+STM32_DMA_S1PAR_OFFSET) +#define STM32_DMA1_S2PAR (STM32_DMA1_BASE+STM32_DMA_S2PAR_OFFSET) +#define STM32_DMA1_S3PAR (STM32_DMA1_BASE+STM32_DMA_S3PAR_OFFSET) +#define STM32_DMA1_S4PAR (STM32_DMA1_BASE+STM32_DMA_S4PAR_OFFSET) +#define STM32_DMA1_S5PAR (STM32_DMA1_BASE+STM32_DMA_S5PAR_OFFSET) +#define STM32_DMA1_S6PAR (STM32_DMA1_BASE+STM32_DMA_S6PAR_OFFSET) +#define STM32_DMA1_S7PAR (STM32_DMA1_BASE+STM32_DMA_S7PAR_OFFSET) + +#define STM32_DMA1_SM0AR(n) (STM32_DMA1_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0M0AR (STM32_DMA1_BASE+STM32_DMA_S0M0AR_OFFSET) +#define STM32_DMA1_S1M0AR (STM32_DMA1_BASE+STM32_DMA_S1M0AR_OFFSET) +#define STM32_DMA1_S2M0AR (STM32_DMA1_BASE+STM32_DMA_S2M0AR_OFFSET) +#define STM32_DMA1_S3M0AR (STM32_DMA1_BASE+STM32_DMA_S3M0AR_OFFSET) +#define STM32_DMA1_S4M0AR (STM32_DMA1_BASE+STM32_DMA_S4M0AR_OFFSET) +#define STM32_DMA1_S5M0AR (STM32_DMA1_BASE+STM32_DMA_S5M0AR_OFFSET) +#define STM32_DMA1_S6M0AR (STM32_DMA1_BASE+STM32_DMA_S6M0AR_OFFSET) +#define STM32_DMA1_S7M0AR (STM32_DMA1_BASE+STM32_DMA_S7M0AR_OFFSET) + +#define STM32_DMA1_SM1AR(n) (STM32_DMA1_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0M1AR (STM32_DMA1_BASE+STM32_DMA_S0M1AR_OFFSET) +#define STM32_DMA1_S1M1AR (STM32_DMA1_BASE+STM32_DMA_S1M1AR_OFFSET) +#define STM32_DMA1_S2M1AR (STM32_DMA1_BASE+STM32_DMA_S2M1AR_OFFSET) +#define STM32_DMA1_S3M1AR (STM32_DMA1_BASE+STM32_DMA_S3M1AR_OFFSET) +#define STM32_DMA1_S4M1AR (STM32_DMA1_BASE+STM32_DMA_S4M1AR_OFFSET) +#define STM32_DMA1_S5M1AR (STM32_DMA1_BASE+STM32_DMA_S5M1AR_OFFSET) +#define STM32_DMA1_S6M1AR (STM32_DMA1_BASE+STM32_DMA_S6M1AR_OFFSET) +#define STM32_DMA1_S7M1AR (STM32_DMA1_BASE+STM32_DMA_S7M1AR_OFFSET) + +#define STM32_DMA1_SFCR(n) (STM32_DMA1_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0FCR (STM32_DMA1_BASE+STM32_DMA_S0FCR_OFFSET) +#define STM32_DMA1_S1FCR (STM32_DMA1_BASE+STM32_DMA_S1FCR_OFFSET) +#define STM32_DMA1_S2FCR (STM32_DMA1_BASE+STM32_DMA_S2FCR_OFFSET) +#define STM32_DMA1_S3FCR (STM32_DMA1_BASE+STM32_DMA_S3FCR_OFFSET) +#define STM32_DMA1_S4FCR (STM32_DMA1_BASE+STM32_DMA_S4FCR_OFFSET) +#define STM32_DMA1_S5FCR (STM32_DMA1_BASE+STM32_DMA_S5FCR_OFFSET) +#define STM32_DMA1_S6FCR (STM32_DMA1_BASE+STM32_DMA_S6FCR_OFFSET) +#define STM32_DMA1_S7FCR (STM32_DMA1_BASE+STM32_DMA_S7FCR_OFFSET) + +#define STM32_DMA2_LISRC (STM32_DMA2_BASE+STM32_DMA_LISR_OFFSET) +#define STM32_DMA2_HISRC (STM32_DMA2_BASE+STM32_DMA_HISR_OFFSET) +#define STM32_DMA2_LIFCR (STM32_DMA2_BASE+STM32_DMA_LIFCR_OFFSET) +#define STM32_DMA2_HIFCR (STM32_DMA2_BASE+STM32_DMA_HIFCR_OFFSET) + +#define STM32_DMA2_SCR(n) (STM32_DMA2_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0CR (STM32_DMA2_BASE+STM32_DMA_S0CR_OFFSET) +#define STM32_DMA2_S1CR (STM32_DMA2_BASE+STM32_DMA_S1CR_OFFSET) +#define STM32_DMA2_S2CR (STM32_DMA2_BASE+STM32_DMA_S2CR_OFFSET) +#define STM32_DMA2_S3CR (STM32_DMA2_BASE+STM32_DMA_S3CR_OFFSET) +#define STM32_DMA2_S4CR (STM32_DMA2_BASE+STM32_DMA_S4CR_OFFSET) +#define STM32_DMA2_S5CR (STM32_DMA2_BASE+STM32_DMA_S5CR_OFFSET) +#define STM32_DMA2_S6CR (STM32_DMA2_BASE+STM32_DMA_S6CR_OFFSET) +#define STM32_DMA2_S7CR (STM32_DMA2_BASE+STM32_DMA_S7CR_OFFSET) + +#define STM32_DMA2_SNDTR(n) (STM32_DMA2_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0NDTR (STM32_DMA2_BASE+STM32_DMA_S0NDTR_OFFSET) +#define STM32_DMA2_S1NDTR (STM32_DMA2_BASE+STM32_DMA_S1NDTR_OFFSET) +#define STM32_DMA2_S2NDTR (STM32_DMA2_BASE+STM32_DMA_S2NDTR_OFFSET) +#define STM32_DMA2_S3NDTR (STM32_DMA2_BASE+STM32_DMA_S3NDTR_OFFSET) +#define STM32_DMA2_S4NDTR (STM32_DMA2_BASE+STM32_DMA_S4NDTR_OFFSET) +#define STM32_DMA2_S5NDTR (STM32_DMA2_BASE+STM32_DMA_S5NDTR_OFFSET) +#define STM32_DMA2_S6NDTR (STM32_DMA2_BASE+STM32_DMA_S6NDTR_OFFSET) +#define STM32_DMA2_S7NDTR (STM32_DMA2_BASE+STM32_DMA_S7NDTR_OFFSET) + +#define STM32_DMA2_SPAR(n) (STM32_DMA2_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0PAR (STM32_DMA2_BASE+STM32_DMA_S0PAR_OFFSET) +#define STM32_DMA2_S1PAR (STM32_DMA2_BASE+STM32_DMA_S1PAR_OFFSET) +#define STM32_DMA2_S2PAR (STM32_DMA2_BASE+STM32_DMA_S2PAR_OFFSET) +#define STM32_DMA2_S3PAR (STM32_DMA2_BASE+STM32_DMA_S3PAR_OFFSET) +#define STM32_DMA2_S4PAR (STM32_DMA2_BASE+STM32_DMA_S4PAR_OFFSET) +#define STM32_DMA2_S5PAR (STM32_DMA2_BASE+STM32_DMA_S5PAR_OFFSET) +#define STM32_DMA2_S6PAR (STM32_DMA2_BASE+STM32_DMA_S6PAR_OFFSET) +#define STM32_DMA2_S7PAR (STM32_DMA2_BASE+STM32_DMA_S7PAR_OFFSET) + +#define STM32_DMA2_SM0AR(n) (STM32_DMA2_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0M0AR (STM32_DMA2_BASE+STM32_DMA_S0M0AR_OFFSET) +#define STM32_DMA2_S1M0AR (STM32_DMA2_BASE+STM32_DMA_S1M0AR_OFFSET) +#define STM32_DMA2_S2M0AR (STM32_DMA2_BASE+STM32_DMA_S2M0AR_OFFSET) +#define STM32_DMA2_S3M0AR (STM32_DMA2_BASE+STM32_DMA_S3M0AR_OFFSET) +#define STM32_DMA2_S4M0AR (STM32_DMA2_BASE+STM32_DMA_S4M0AR_OFFSET) +#define STM32_DMA2_S5M0AR (STM32_DMA2_BASE+STM32_DMA_S5M0AR_OFFSET) +#define STM32_DMA2_S6M0AR (STM32_DMA2_BASE+STM32_DMA_S6M0AR_OFFSET) +#define STM32_DMA2_S7M0AR (STM32_DMA2_BASE+STM32_DMA_S7M0AR_OFFSET) + +#define STM32_DMA2_SM1AR(n) (STM32_DMA2_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0M1AR (STM32_DMA2_BASE+STM32_DMA_S0M1AR_OFFSET) +#define STM32_DMA2_S1M1AR (STM32_DMA2_BASE+STM32_DMA_S1M1AR_OFFSET) +#define STM32_DMA2_S2M1AR (STM32_DMA2_BASE+STM32_DMA_S2M1AR_OFFSET) +#define STM32_DMA2_S3M1AR (STM32_DMA2_BASE+STM32_DMA_S3M1AR_OFFSET) +#define STM32_DMA2_S4M1AR (STM32_DMA2_BASE+STM32_DMA_S4M1AR_OFFSET) +#define STM32_DMA2_S5M1AR (STM32_DMA2_BASE+STM32_DMA_S5M1AR_OFFSET) +#define STM32_DMA2_S6M1AR (STM32_DMA2_BASE+STM32_DMA_S6M1AR_OFFSET) +#define STM32_DMA2_S7M1AR (STM32_DMA2_BASE+STM32_DMA_S7M1AR_OFFSET) + +#define STM32_DMA2_SFCR(n) (STM32_DMA2_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0FCR (STM32_DMA2_BASE+STM32_DMA_S0FCR_OFFSET) +#define STM32_DMA2_S1FCR (STM32_DMA2_BASE+STM32_DMA_S1FCR_OFFSET) +#define STM32_DMA2_S2FCR (STM32_DMA2_BASE+STM32_DMA_S2FCR_OFFSET) +#define STM32_DMA2_S3FCR (STM32_DMA2_BASE+STM32_DMA_S3FCR_OFFSET) +#define STM32_DMA2_S4FCR (STM32_DMA2_BASE+STM32_DMA_S4FCR_OFFSET) +#define STM32_DMA2_S5FCR (STM32_DMA2_BASE+STM32_DMA_S5FCR_OFFSET) +#define STM32_DMA2_S6FCR (STM32_DMA2_BASE+STM32_DMA_S6FCR_OFFSET) +#define STM32_DMA2_S7FCR (STM32_DMA2_BASE+STM32_DMA_S7FCR_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +#define DMA_STREAM_MASK 0x3f +#define DMA_STREAM_FEIF_BIT (1 << 0) /* Bit 0: Stream FIFO error interrupt flag */ +#define DMA_STREAM_DMEIF_BIT (1 << 2) /* Bit 2: Stream direct mode error interrupt flag */ +#define DMA_STREAM_TEIF_BIT (1 << 3) /* Bit 3: Stream Transfer Error flag */ +#define DMA_STREAM_HTIF_BIT (1 << 4) /* Bit 4: Stream Half Transfer flag */ +#define DMA_STREAM_TCIF_BIT (1 << 5) /* Bit 5: Stream Transfer Complete flag */ + +/* DMA interrupt status register and interrupt flag clear register field definitions */ + +#define DMA_INT_STREAM0_SHIFT (0) /* Bits 0-5: DMA Stream 0 interrupt */ +#define DMA_INT_STREAM0_MASK (DMA_STREAM_MASK << DMA_INT_STREAM0_SHIFT) +#define DMA_INT_STREAM1_SHIFT (6) /* Bits 6-11: DMA Stream 1 interrupt */ +#define DMA_INT_STREAM1_MASK (DMA_STREAM_MASK << DMA_INT_STREAM1_SHIFT) +#define DMA_INT_STREAM2_SHIFT (16) /* Bits 16-21: DMA Stream 2 interrupt */ +#define DMA_INT_STREAM2_MASK (DMA_STREAM_MASK << DMA_INT_STREAM2_SHIFT) +#define DMA_INT_STREAM3_SHIFT (22) /* Bits 22-27: DMA Stream 3 interrupt */ +#define DMA_INT_STREAM3_MASK (DMA_STREAM_MASK << DMA_INT_STREAM3_SHIFT) + +#define DMA_INT_STREAM4_SHIFT (0) /* Bits 0-5: DMA Stream 4 interrupt */ +#define DMA_INT_STREAM4_MASK (DMA_STREAM_MASK << DMA_INT_STREAM4_SHIFT) +#define DMA_INT_STREAM5_SHIFT (6) /* Bits 6-11: DMA Stream 5 interrupt */ +#define DMA_INT_STREAM5_MASK (DMA_STREAM_MASK << DMA_INT_STREAM5_SHIFT) +#define DMA_INT_STREAM6_SHIFT (16) /* Bits 16-21: DMA Stream 6 interrupt */ +#define DMA_INT_STREAM6_MASK (DMA_STREAM_MASK << DMA_INT_STREAM6_SHIFT) +#define DMA_INT_STREAM7_SHIFT (22) /* Bits 22-27: DMA Stream 7 interrupt */ +#define DMA_INT_STREAM7_MASK (DMA_STREAM_MASK << DMA_INT_STREAM7_SHIFT) + +/* DMA stream configuration register */ + +#define DMA_SCR_EN (1 << 0) /* Bit 0: Stream enable */ +#define DMA_SCR_DMEIE (1 << 1) /* Bit 1: Direct mode error interrupt enable */ +#define DMA_SCR_TEIE (1 << 2) /* Bit 2: Transfer error interrupt enable */ +#define DMA_SCR_HTIE (1 << 3) /* Bit 3: Half Transfer interrupt enable */ +#define DMA_SCR_TCIE (1 << 4) /* Bit 4: Transfer complete interrupt enable */ +#define DMA_SCR_PFCTRL (1 << 5) /* Bit 5: Peripheral flow controller */ +#define DMA_SCR_DIR_SHIFT (6) /* Bits 6-7: Data transfer direction */ +#define DMA_SCR_DIR_MASK (3 << DMA_SCR_DIR_SHIFT) +# define DMA_SCR_DIR_P2M (0 << DMA_SCR_DIR_SHIFT) /* 00: Peripheral-to-memory */ +# define DMA_SCR_DIR_M2P (1 << DMA_SCR_DIR_SHIFT) /* 01: Memory-to-peripheral */ +# define DMA_SCR_DIR_M2M (2 << DMA_SCR_DIR_SHIFT) /* 10: Memory-to-memory */ +#define DMA_SCR_CIRC (1 << 8) /* Bit 8: Circular mode */ +#define DMA_SCR_PINC (1 << 9) /* Bit 9: Peripheral increment mode */ +#define DMA_SCR_MINC (1 << 10) /* Bit 10: Memory increment mode */ +#define DMA_SCR_PSIZE_SHIFT (11) /* Bits 11-12: Peripheral size */ +#define DMA_SCR_PSIZE_MASK (3 << DMA_SCR_PSIZE_SHIFT) +# define DMA_SCR_PSIZE_8BITS (0 << DMA_SCR_PSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_SCR_PSIZE_16BITS (1 << DMA_SCR_PSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_SCR_PSIZE_32BITS (2 << DMA_SCR_PSIZE_SHIFT) /* 10: 32-bits */ +#define DMA_SCR_MSIZE_SHIFT (13) /* Bits 13-14: Memory size */ +#define DMA_SCR_MSIZE_MASK (3 << DMA_SCR_MSIZE_SHIFT) +# define DMA_SCR_MSIZE_8BITS (0 << DMA_SCR_MSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_SCR_MSIZE_16BITS (1 << DMA_SCR_MSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_SCR_MSIZE_32BITS (2 << DMA_SCR_MSIZE_SHIFT) /* 10: 32-bits */ +#define DMA_SCR_PINCOS (1 << 15) /* Bit 15: Peripheral increment offset size */ +#define DMA_SCR_PL_SHIFT (16) /* Bits 16-17: Stream Priority level */ +#define DMA_SCR_PL_MASK (3 << DMA_SCR_PL_SHIFT) +# define DMA_SCR_PRILO (0 << DMA_SCR_PL_SHIFT) /* 00: Low */ +# define DMA_SCR_PRIMED (1 << DMA_SCR_PL_SHIFT) /* 01: Medium */ +# define DMA_SCR_PRIHI (2 << DMA_SCR_PL_SHIFT) /* 10: High */ +# define DMA_SCR_PRIVERYHI (3 << DMA_SCR_PL_SHIFT) /* 11: Very high */ +#define DMA_SCR_DBM (1 << 18) /* Bit 15: Double buffer mode */ +#define DMA_SCR_CT (1 << 19) /* Bit 19: Current target */ +#define DMA_SCR_PBURST_SHIFT (21) /* Bits 21-22: Peripheral burst transfer configuration */ +#define DMA_SCR_PBURST_MASK (3 << DMA_SCR_PBURST_SHIFT) +# define DMA_SCR_PBURST_SINGLE (0 << DMA_SCR_PBURST_SHIFT) /* 00: Single transfer */ +# define DMA_SCR_PBURST_INCR4 (1 << DMA_SCR_PBURST_SHIFT) /* 01: Incremental burst of 4 beats */ +# define DMA_SCR_PBURST_INCR8 (2 << DMA_SCR_PBURST_SHIFT) /* 10: Incremental burst of 8 beats */ +# define DMA_SCR_PBURST_INCR16 (3 << DMA_SCR_PBURST_SHIFT) /* 11: Incremental burst of 16 beats */ +#define DMA_SCR_MBURST_SHIFT (23) /* Bits 23-24: Memory burst transfer configuration */ +#define DMA_SCR_MBURST_MASK (3 << DMA_SCR_MBURST_SHIFT) +# define DMA_SCR_MBURST_SINGLE (0 << DMA_SCR_MBURST_SHIFT) /* 00: Single transfer */ +# define DMA_SCR_MBURST_INCR4 (1 << DMA_SCR_MBURST_SHIFT) /* 01: Incremental burst of 4 beats */ +# define DMA_SCR_MBURST_INCR8 (2 << DMA_SCR_MBURST_SHIFT) /* 10: Incremental burst of 8 beats */ +# define DMA_SCR_MBURST_INCR16 (3 << DMA_SCR_MBURST_SHIFT) /* 11: Incremental burst of 16 beats */ +#define DMA_SCR_CHSEL_SHIFT (25) /* Bits 25-27: Channel selection */ +#define DMA_SCR_CHSEL_MASK (7 << DMA_SCR_CHSEL_SHIFT) +# define DMA_SCR_CHSEL(n) ((n) << DMA_SCR_CHSEL_SHIFT) + +#define DMA_SCR_ALLINTS (DMA_SCR_DMEIE|DMA_SCR_TEIE|DMA_SCR_HTIE|DMA_SCR_TCIE) + +/* DMA stream number of data register */ + +#define DMA_SNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */ +#define DMA_SNDTR_NDT_MASK (0xffff << DMA_SNDTR_NDT_SHIFT) + +/* DMA stream n FIFO control register */ + +#define DMA_SFCR_FTH_SHIFT (0) /* Bits 0-1: FIFO threshold selection */ +#define DMA_SFCR_FTH_MASK (3 << DMA_SFCR_FTH_SHIFT) +# define DMA_SFCR_FTH_QUARTER (0 << DMA_SFCR_FTH_SHIFT) /* 1/4 full FIFO */ +# define DMA_SFCR_FTH_HALF (1 << DMA_SFCR_FTH_SHIFT) /* 1/2 full FIFO */ +# define DMA_SFCR_FTH_3QUARTER (2 << DMA_SFCR_FTH_SHIFT) /* 3/4 full FIFO */ +# define DMA_SFCR_FTH_FULL (3 << DMA_SFCR_FTH_SHIFT) /* full FIFO */ +#define DMA_SFCR_DMDIS (1 << 2) /* Bit 2: Direct mode disable */ +#define DMA_SFCR_FS_SHIFT (3) /* Bits 3-5: FIFO status */ +#define DMA_SFCR_FS_MASK (7 << DMA_SFCR_FS_SHIFT) +# define DMA_SFCR_FS_QUARTER (0 << DMA_SFCR_FS_SHIFT) /* 0 < fifo_level < 1/4 */ +# define DMA_SFCR_FS_HALF (1 << DMA_SFCR_FS_SHIFT) /* 1/4 = fifo_level < 1/2 */ +# define DMA_SFCR_FS_3QUARTER (2 << DMA_SFCR_FS_SHIFT) /* 1/2 = fifo_level < 3/4 */ +# define DMA_SFCR_FS_ALMOSTFULL (3 << DMA_SFCR_FS_SHIFT) /* 3/4 = fifo_level < full */ +# define DMA_SFCR_FS_EMPTY (4 << DMA_SFCR_FS_SHIFT) /* FIFO is empty */ +# define DMA_SFCR_FS_FULL (5 << DMA_SFCR_FS_SHIFT) /* FIFO is full */ + /* Bit 6: Reserved */ +#define DMA_SFCR_FEIE (1 << 7) /* Bit 7: FIFO error interrupt enable */ + /* Bits 8-31: Reserved */ + +/* DMA Stream mapping. Each DMA stream has a mapping to several possible + * sources/sinks of data. The requests from peripherals assigned to a stream + * are simply OR'ed together before entering the DMA block. This means that only + * one request on a given stream can be enabled at once. + * + * Alternative stream selections are provided with a numeric suffix like _1, _2, etc. + * The DMA driver, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. For example, if + * SPI3_RX connects via DMA STREAM0, then following should be application-specific + * mapping should be used: + * + * #define DMAMAP_SPI3_RX DMAMAP_SPI3_RX_1 + */ + +#define STM32_DMA_MAP(d,s,c) ((d) << 6 | (s) << 3 | (c)) +#define STM32_DMA_CONTROLLER(m) (((m) >> 6) & 1) +#define STM32_DMA_STREAM(m) (((m) >> 3) & 7) +#define STM32_DMA_CHANNEL(m) ((m) & 7) + +#define DMAMAP_SPI3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN0) +#define DMAMAP_SPI3_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN0) +#define DMAMAP_SPI2_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN0) +#define DMAMAP_SPI2_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN0) +#define DMAMAP_SPI3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN0) +#define DMAMAP_SPI3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN0) + +#define DMAMAP_I2C1_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN1) +#define DMAMAP_I2C3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN1) +#define DMAMAP_TIM7_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN1) +#define DMAMAP_TIM7_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN1) +#define DMAMAP_I2C1_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN1) +#define DMAMAP_I2C1_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN1) +#define DMAMAP_I2C1_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN1) + +#define DMAMAP_TIM4_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN2) +#define DMAMAP_TIM4_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN2) +#define DMAMAP_TIM4_UP STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN2) +#define DMAMAP_TIM4_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN2) + +#define DMAMAP_TIM2_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3) +#define DMAMAP_TIM2_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3) +#define DMAMAP_I2C3_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3) +#define DMAMAP_I2C3_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN3) +#define DMAMAP_TIM2_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN3) +#define DMAMAP_TIM2_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3) +#define DMAMAP_TIM2_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3) +#define DMAMAP_TIM2_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3) +#define DMAMAP_TIM2_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3) + +#define DMAMAP_UART5_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN4) +#define DMAMAP_USART3_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN4) +#define DMAMAP_UART4_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN4) +#define DMAMAP_USART3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN4) +#define DMAMAP_UART4_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN4) +#define DMAMAP_USART2_RX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN4) +#define DMAMAP_USART2_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN4) +#define DMAMAP_UART5_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN4) + +#define DMAMAP_UART8_TX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN5) +#define DMAMAP_UART7_TX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN5) +#define DMAMAP_TIM3_CH4 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5) +#define DMAMAP_TIM3_UP STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5) +#define DMAMAP_UART7_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN5) +#define DMAMAP_TIM3_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5) +#define DMAMAP_TIM3_TRIG STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5) +#define DMAMAP_TIM3_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN5) +#define DMAMAP_UART8_RX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN5) +#define DMAMAP_TIM3_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN5) + +#define DMAMAP_TIM5_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6) +#define DMAMAP_TIM5_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6) +#define DMAMAP_TIM5_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6) +#define DMAMAP_TIM5_TRIG_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6) +#define DMAMAP_TIM5_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN6) +#define DMAMAP_TIM5_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6) +#define DMAMAP_TIM5_TRIG_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6) +#define DMAMAP_TIM5_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN6) +#define DMAMAP_TIM5_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN6) + +#define DMAMAP_TIM6_UP STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN7) +#define DMAMAP_I2C2_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN7) +#define DMAMAP_I2C2_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN7) +#define DMAMAP_USART3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN7) +#define DMAMAP_DAC1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN7) +#define DMAMAP_DAC2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN7) +#define DMAMAP_I2C2_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN7) + +#define DMAMAP_ADC1_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN0) +#define DMAMAP_SAI1_A_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN0) +#define DMAMAP_TIM8_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) +#define DMAMAP_TIM8_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) +#define DMAMAP_TIM8_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) +#define DMAMAP_SAI1_A_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN0) +#define DMAMAP_ADC1_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN0) +#define DMAMAP_SAI1_B_1 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN0) +#define DMAMAP_TIM1_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) +#define DMAMAP_TIM1_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) +#define DMAMAP_TIM1_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) +#define DMAMAP_SAI1_B_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN0) + +#define DMAMAP_ADC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN1) +#define DMAMAP_ADC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN1) +#define DMAMAP_SAI1_B STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN1) + +#define DMAMAP_ADC3_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN2) +#define DMAMAP_ADC3_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN2) +#define DMAMAP_SPI5_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN2) +#define DMAMAP_SPI5_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN2) +#define DMAMAP_CRYP_OUT STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN2) +#define DMAMAP_CRYP_IN STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN2) + +#define DMAMAP_SPI1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN3) +#define DMAMAP_SPI1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN3) +#define DMAMAP_SPI1_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN3) +#define DMAMAP_SAI2_A STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN3) +#define DMAMAP_SPI1_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN3) +#define DMAMAP_SAI2_B STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN3) +#define DMAMAP_QUADSPI STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN3) + +#define DMAMAP_SPI4_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN4) +#define DMAMAP_SPI4_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN4) +#define DMAMAP_USART1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN4) +#define DMAMAP_SDMMC1_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN4) +#define DMAMAP_USART1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN4) +#define DMAMAP_SDMMC1_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN4) +#define DMAMAP_USART1_TX STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN4) + +#define DMAMAP_USART6_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN5) +#define DMAMAP_USART6_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN5) +#define DMAMAP_SPI4_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN5) +#define DMAMAP_SPI4_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN5) +#define DMAMAP_USART6_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN5) +#define DMAMAP_USART6_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN5) + +#define DMAMAP_TIM1_TRIG_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN6) +#define DMAMAP_TIM1_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN6) +#define DMAMAP_TIM1_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN6) +#define DMAMAP_TIM1_CH1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN6) +#define DMAMAP_TIM1_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) +#define DMAMAP_TIM1_TRIG_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) +#define DMAMAP_TIM1_COM STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) +#define DMAMAP_TIM1_UP STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN6) +#define DMAMAP_TIM1_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN6) + +#define DMAMAP_TIM8_UP STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN7) +#define DMAMAP_TIM8_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN7) +#define DMAMAP_TIM8_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN7) +#define DMAMAP_TIM8_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN7) +#define DMAMAP_SPI5_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN7) +#define DMAMAP_SPI5_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN7) +#define DMAMAP_TIM8_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) +#define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) +#define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) +#define DMAMAP_SDMMC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN11) +#define DMAMAP_SDMMC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN11) + +#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XXX73XX_DMA_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_flash.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_flash.h new file mode 100644 index 0000000000000000000000000000000000000000..d931bb6e9a62aa8e0a56e646e77a96354cccbdfb --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_flash.h @@ -0,0 +1,212 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f72xx73xx_flash.h + * + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM327_CHIP_STM32F72XX73XX_FLASH_H +#define __ARCH_ARM_SRC_STM327_CHIP_STM32F72XX73XX_FLASH_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Flash size is known from the chip selection: + * + * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on the chip + * part number. This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x + * + * Parts STM32F72xxC have 256Kb of FLASH + * Parts STM32F72xxE have 512Kb of FLASH + * Parts STM32F73xxC have 256Kb of FLASH + * Parts STM32F73xxE have 512Kb of FLASH + * + * N.B. Only Single bank mode is supported + */ + +#define _K(x) ((x)*1024) + +#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32F7_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32F7_FLASH_CONFIG_C) +# define CONFIG_STM32F7_FLASH_OVERRIDE_C +# warning "Flash size not defined defaulting to 256KiB (C)" +#endif + +#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) + +# undef CONFIG_STM32F7_FLASH_CONFIG_C +# undef CONFIG_STM32F7_FLASH_CONFIG_E +# undef CONFIG_STM32F7_FLASH_CONFIG_G + +# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_C) +# define CONFIG_STM32F7_FLASH_CONFIG_C + +# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) +# define CONFIG_STM32F7_FLASH_CONFIG_E + +# endif +#endif + +#if defined(CONFIG_STM32F7_FLASH_CONFIG_C) + +# define STM32_FLASH_NPAGES 6 +# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (1 * 128)) +# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ + _K(64), _K(128)} + +#elif defined(CONFIG_STM32F7_FLASH_CONFIG_E) + +# define STM32_FLASH_NPAGES 8 +# define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (3 * 128)) +# define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ + _K(64), _K(128), _K(128), _K(128)} + +#endif + +/* Register Offsets *****************************************************************/ + +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_KEYR_OFFSET 0x0004 +#define STM32_FLASH_OPTKEYR_OFFSET 0x0008 +#define STM32_FLASH_SR_OFFSET 0x000c +#define STM32_FLASH_CR_OFFSET 0x0010 +#define STM32_FLASH_OPTCR_OFFSET 0x0014 +#define STM32_FLASH_OPTCR1_OFFSET 0x0018 + +/* Register Addresses ***************************************************************/ + +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET) +#define STM32_FLASH_OPTCR1 (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR1_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ +/* Flash Access Control Register (ACR) */ + +#define FLASH_ACR_LATENCY_SHIFT (0) /* Bits 0-3: Latency */ +#define FLASH_ACR_LATENCY_MASK (15 << FLASH_ACR_LATENCY_SHIFT) +# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states */ +# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 0000: Zero wait states */ +# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 0001: One wait state */ +# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 0010: Two wait states */ +# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 0011: Three wait states */ +# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 0100: Four wait states */ +# define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 0101: Five wait states */ +# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 0110: Six wait states */ +# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 0111: Seven wait states */ +# define FLASH_ACR_LATENCY_8 (8 << FLASH_ACR_LATENCY_SHIFT) /* 1000: Eight wait states */ +# define FLASH_ACR_LATENCY_9 (9 << FLASH_ACR_LATENCY_SHIFT) /* 1001: Nine wait states */ +# define FLASH_ACR_LATENCY_10 (10 << FLASH_ACR_LATENCY_SHIFT) /* 1010: Ten wait states */ +# define FLASH_ACR_LATENCY_11 (11 << FLASH_ACR_LATENCY_SHIFT) /* 1011: Eleven wait states */ +# define FLASH_ACR_LATENCY_12 (12 << FLASH_ACR_LATENCY_SHIFT) /* 1100: Twelve wait states */ +# define FLASH_ACR_LATENCY_13 (13 << FLASH_ACR_LATENCY_SHIFT) /* 1101: Thirteen wait states */ +# define FLASH_ACR_LATENCY_14 (14 << FLASH_ACR_LATENCY_SHIFT) /* 1110: Fourteen wait states */ +# define FLASH_ACR_LATENCY_15 (15 << FLASH_ACR_LATENCY_SHIFT) /* 1111: Fifteen wait states */ +#define FLASH_ACR_PRFTEN (1 << 8) /* FLASH prefetch enable */ +#define FLASH_ACR_ARTEN (1 << 9) /* Bit 9: ART Accelerator Enable */ +#define FLASH_ACR_ARTRST (1 << 11) /* Bit 11: ART Accelerator reset */ + +/* Flash Status Register (SR) */ + +#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ +#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ +#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ +#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */ +#define FLASH_SR_PGPERR (1 << 6) /* Bit 6: Programming parallelism error */ +#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */ +#define FLASH_SR_PGRERR (1 << 7) /* Bit 7: PCROP protection error */ +#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ + +/* Flash Control Register (CR) */ + +#define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */ +#define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */ +#define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */ +#define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */ +#define FLASH_CR_SNB_MASK (0xf << FLASH_CR_SNB_SHIFT) /* Used to clear FLASH_CR_SNB bits */ +# define FLASH_CR_SNB(n) ((uint32_t)(n & 0x7) << FLASH_CR_SNB_SHIFT)) /* Sector n, n=0..7 */ +#define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */ +#define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT) +# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* Program x8 */ +# define FLASH_CR_PSIZE_X16 (1 << FLASH_CR_PSIZE_SHIFT) /* Program x16 */ +# define FLASH_CR_PSIZE_X32 (2 << FLASH_CR_PSIZE_SHIFT) /* Program x32 */ +# define FLASH_CR_PSIZE_X64 (3 << FLASH_CR_PSIZE_SHIFT) /* Program x64 */ +#define FLASH_CR_STRT (1 << 16) /* Bit 16: Start Erase */ +#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */ +#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ +#define FLASH_CR_RDERRIE (1 << 26) /* Bit 26: PCROP error interrupt enable */ +#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */ + +/* Flash Option Control Register (OPTCR) */ + +#define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */ +#define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */ +#define FLASH_OPTCR_BORLEV_SHIFT (2) /* Bits 2-3: BOR reset Level */ +#define FLASH_OPTCR_BORLEV_MASK (3 << FLASH_OPTCR_BORLEV_SHIFT) +# define FLASH_OPTCR_VBOR3 (0 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 3 */ +# define FLASH_OPTCR_VBOR2 (1 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 2 */ +# define FLASH_OPTCR_VBOR1 (2 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR Level 1 */ +# define FLASH_OPTCR_VBOR0 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR off */ +#define FLASH_OPTCR_USER_SHIFT (4) /* Bits 5-7: User option bytes */ +#define FLASH_OPTCR_USER_MASK (15 << FLASH_OPTCR_USER_SHIFT) +# define FLASH_OPTCR_WWDG_SW (1 << 4) /* Bit 4: WWDG_SW */ +# define FLASH_OPTCR_IWDG_SW (1 << 5) /* Bit 5: IWDG_SW */ +# define FLASH_OPTCR_NRST_STOP (1 << 6) /* Bit 6: nRST_STOP */ +# define FLASH_OPTCR_NRST_STDBY (1 << 7) /* Bit 7: nRST_STDBY */ +#define FLASH_OPTCR_RDP_SHIFT (8) /* Bits 8-15: Read protect */ +#define FLASH_OPTCR_RDP_MASK (0xff << FLASH_OPTCR_RDP_SHIFT) +# define FLASH_OPTCR_RDP(n) ((uint32_t)(n) << FLASH_OPTCR_RDP_SHIFT) +#define FLASH_OPTCR_NWRP_SHIFT (16) /* Bits 16-23: Not write protect */ +#define FLASH_OPTCR_NWRP_MASK (0xff << FLASH_OPTCR_NWRP_SHIFT) +# define FLASH_OPTCR_NWRP(n) ((uint32_t)(n) << FLASH_OPTCR_NWRP_SHIFT) +#define FLASH_OPTCR_IWDG_STDBY (1 << 30) /* Bit 30: IWDG freeze in stop mode */ +#define FLASH_OPTCR_IWDG_STOP (1 << 31) /* Bit 31: IWDG freeze in standby mode */ + +/* Flash Option Control Register (OPTCR1) */ + +#define FLASH_OPTCR1_BOOTADD0_SHIFT (0) /* Bits 0-15: Boot base address when Boot pin=0 */ +#define FLASH_OPTCR1_BOOTADD0_MASK (0xffff << FLASH_OPTCR1_BOOTADD0_SHIFT) +# define FLASH_OPTCR1_BOOTADD0(n) ((uint32_t)(n) << FLASH_OPTCR1_BOOTADD0_SHIFT) +#define FLASH_OPTCR1_BOOTADD1_SHIFT (16) /* Bits 16-31:Boot base address when Boot pin=1 */ +#define FLASH_OPTCR1_BOOTADD1_MASK (0xffff << FLASH_OPTCR1_BOOTADD1_SHIFT) +# define FLASH_OPTCR1_BOOTADD1(n) ((uint32_t)(n) << FLASH_OPTCR1_BOOTADD1_SHIFT) + +#endif /* __ARCH_ARM_SRC_STM327_CHIP_STM32F72XX73XX_FLASH_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_gpio.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..3927df73ad8a444df79a4940886596db15bed782 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_gpio.h @@ -0,0 +1,404 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f72xxx73xx_gpio.h + * + * Copyright (C) 2005 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_GPIO_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ + +/* Register Addresses ***************************************************************/ + +#if STM32F7_NGPIO > 0 +# define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPI O_BSRR_OFFSET) +# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 1 +# define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 2 +# define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 3 +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 4 +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 5 +# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 6 +# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 7 +# define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 8 +# define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOI_IDR (STM32_GPIOI_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOI_ODR (STM32_GPIOI_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 9 +# define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOJ_PUPDR (STM32_GPIOJ_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOJ_IDR (STM32_GPIOJ_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOJ_ODR (STM32_GPIOJ_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOJ_BSRR (STM32_GPIOJ_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOJ_LCKR (STM32_GPIOJ_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOJ_AFRL (STM32_GPIOJ_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +#if STM32F7_NGPIO > 10 +# define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOK_PUPDR (STM32_GPIOK_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOK_IDR (STM32_GPIOK_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOK_ODR (STM32_GPIOK_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOK_BSRR (STM32_GPIOK_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOK_LCKR (STM32_GPIOK_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOK_AFRL (STM32_GPIOK_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOK_AFRH (STM32_GPIOK_BASE+STM32_GPIO_AFRH_OFFSET) +#endif + +/* Register Bitfield Definitions ****************************************************/ + +/* GPIO port mode register */ + +#define GPIO_MODER_INPUT (0) /* Input */ +#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */ +#define GPIO_MODER_ALT (2) /* Alternate mode */ +#define GPIO_MODER_ANALOG (3) /* Analog mode */ + +#define GPIO_MODER_SHIFT(n) ((n) << 1) +#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n)) + +#define GPIO_MODER0_SHIFT (0) +#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT) +#define GPIO_MODER1_SHIFT (2) +#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT) +#define GPIO_MODER2_SHIFT (4) +#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT) +#define GPIO_MODER3_SHIFT (6) +#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT) +#define GPIO_MODER4_SHIFT (8) +#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT) +#define GPIO_MODER5_SHIFT (10) +#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT) +#define GPIO_MODER6_SHIFT (12) +#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT) +#define GPIO_MODER7_SHIFT (14) +#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT) +#define GPIO_MODER8_SHIFT (16) +#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT) +#define GPIO_MODER9_SHIFT (18) +#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT) +#define GPIO_MODER10_SHIFT (20) +#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT) +#define GPIO_MODER11_SHIFT (22) +#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT) +#define GPIO_MODER12_SHIFT (24) +#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT) +#define GPIO_MODER13_SHIFT (26) +#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT) +#define GPIO_MODER14_SHIFT (28) +#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT) +#define GPIO_MODER15_SHIFT (30) +#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT) + +/* GPIO port output type register */ + +#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */ +#define GPIO_OTYPER_PP(n) (0) /* 0=Ouput push-pull */ + +/* GPIO port output speed register */ + +#define GPIO_OSPEED_2MHz (0) /* 2 MHz Low speed */ +#define GPIO_OSPEED_25MHz (1) /* 25 MHz Medium speed */ +#define GPIO_OSPEED_50MHz (2) /* 50 MHz Fast speed */ +#define GPIO_OSPEED_100MHz (3) /* 100 MHz High speed on 30 pF (80 MHz Output max speed on 15 pF) */ + +#define GPIO_OSPEED_SHIFT(n) ((n) << 1) +#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n)) + +#define GPIO_OSPEED0_SHIFT (0) +#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT) +#define GPIO_OSPEED1_SHIFT (2) +#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT) +#define GPIO_OSPEED2_SHIFT (4) +#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT) +#define GPIO_OSPEED3_SHIFT (6) +#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT) +#define GPIO_OSPEED4_SHIFT (8) +#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT) +#define GPIO_OSPEED5_SHIFT (10) +#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT) +#define GPIO_OSPEED6_SHIFT (12) +#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT) +#define GPIO_OSPEED7_SHIFT (14) +#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT) +#define GPIO_OSPEED8_SHIFT (16) +#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT) +#define GPIO_OSPEED9_SHIFT (18) +#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT) +#define GPIO_OSPEED10_SHIFT (20) +#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT) +#define GPIO_OSPEED11_SHIFT (22) +#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT) +#define GPIO_OSPEED12_SHIFT (24) +#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT) +#define GPIO_OSPEED13_SHIFT (26) +#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT) +#define GPIO_OSPEED14_SHIFT (28) +#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT) +#define GPIO_OSPEED15_SHIFT (30) +#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT) + +/* GPIO port pull-up/pull-down register */ + +#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */ +#define GPIO_PUPDR_PULLUP (1) /* Pull-up */ +#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */ + +#define GPIO_PUPDR_SHIFT(n) ((n) << 1) +#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n)) + +#define GPIO_PUPDR0_SHIFT (0) +#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT) +#define GPIO_PUPDR1_SHIFT (2) +#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT) +#define GPIO_PUPDR2_SHIFT (4) +#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT) +#define GPIO_PUPDR3_SHIFT (6) +#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT) +#define GPIO_PUPDR4_SHIFT (8) +#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT) +#define GPIO_PUPDR5_SHIFT (10) +#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT) +#define GPIO_PUPDR6_SHIFT (12) +#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT) +#define GPIO_PUPDR7_SHIFT (14) +#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT) +#define GPIO_PUPDR8_SHIFT (16) +#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT) +#define GPIO_PUPDR9_SHIFT (18) +#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT) +#define GPIO_PUPDR10_SHIFT (20) +#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT) +#define GPIO_PUPDR11_SHIFT (22) +#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT) +#define GPIO_PUPDR12_SHIFT (24) +#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT) +#define GPIO_PUPDR13_SHIFT (26) +#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT) +#define GPIO_PUPDR14_SHIFT (28) +#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT) +#define GPIO_PUPDR15_SHIFT (30) +#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT) + +/* GPIO port input data register */ + +#define GPIO_IDR(n) (1 << (n)) + +/* GPIO port output data register */ + +#define GPIO_ODR(n) (1 << (n)) + +/* GPIO port bit set/reset register */ + +#define GPIO_BSRR_SET(n) (1 << (n)) +#define GPIO_BSRR_RESET(n) (1 << ((n)+16)) + +/* GPIO port configuration lock register */ + +#define GPIO_LCKR(n) (1 << (n)) +#define GPIO_LCKK (1 << 16) /* Lock key */ + +/* GPIO alternate function low/high register */ + +#define GPIO_AFR_SHIFT(n) ((n) << 2) +#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n)) + +#define GPIO_AFRL0_SHIFT (0) +#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT) +#define GPIO_AFRL1_SHIFT (4) +#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT) +#define GPIO_AFRL2_SHIFT (8) +#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT) +#define GPIO_AFRL3_SHIFT (12) +#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT) +#define GPIO_AFRL4_SHIFT (16) +#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT) +#define GPIO_AFRL5_SHIFT (20) +#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT) +#define GPIO_AFRL6_SHIFT (24) +#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT) +#define GPIO_AFRL7_SHIFT (28) +#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT) + +#define GPIO_AFRH8_SHIFT (0) +#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT) +#define GPIO_AFRH9_SHIFT (4) +#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT) +#define GPIO_AFRH10_SHIFT (8) +#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT) +#define GPIO_AFRH11_SHIFT (12) +#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT) +#define GPIO_AFRH12_SHIFT (16) +#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT) +#define GPIO_AFRH13_SHIFT (20) +#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT) +#define GPIO_AFRH14_SHIFT (24) +#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT) +#define GPIO_AFRH15_SHIFT (28) +#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) + +#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_GPIO_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_memorymap.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_memorymap.h new file mode 100644 index 0000000000000000000000000000000000000000..669fd36abdb47a5baa6a8c32943192f099d65fda --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_memorymap.h @@ -0,0 +1,203 @@ +/************************************************************************************ + * arch/arm/src/chip/stm32f72xx73xx_memorymap.h + * + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XXX73XXX_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XXX73XXX_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* STM32F72XX STM32F73XX Address Blocks *********************************************/ + +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb AHB1-2 peripheral blocks */ +#define STM32_FMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FMC bank1&2 block */ +# define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ +# define STM32_FMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */ +#define STM32_FMC_BASE34 0x80000000 /* 0x80000000-0x9fffffff: 512Mb FMC bank3&4 block */ +# define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ +# define STM32_FMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD */ +#define STM32_FMC_BASE5 0xc0000000 /* 0xc0000000-0xcfffffff: 256Mb FMC SDRAM Bank 1 */ +#define STM32_FMC_BASE6 0xd0000000 /* 0xd0000000-0xdfffffff: 256Mb FMC SDRAM Bank 2 */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M7 block */ + +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) +#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FMC_BANK1) + +/* Code Base Addresses **************************************************************/ + +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ +#define STM32_INSTRAM_BASE 0x00000000 /* 0x00000000-0x00003fff: Instruction RAM (ITCM-RAM) */ +#define STM32_SYSMEM_ICTM 0x00100000 /* 0x00100000-0x0010edbf: System memory (ITCM) */ +#define STM32_FLASH_ITCM 0x00200000 /* 0x00200000-0x002fffff: FLASH memory (ITCM) */ +#define STM32_FLASH_AXIM 0x08000000 /* 0x08000000-0x080fffff: FLASH memory (AXIM) */ +#define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: OTP (AXIM) */ + +/* Information Addresses ************************************************************/ + +#define STM32_SYSMEM_AXIM 0x1ff00000 /* 0x1ff00000-0x1ff076D7: System memory (AXIM) */ +#define STM32_SYSMEM_UID 0x1ff07A10 /* The 96-bit unique device identifier */ +#define STM32_OTP_ICTM 0x00107800 /* 0x00107800-0x00107A0F: OTP (ITCM) */ +#define STM32_OTP_AXIM 0x1ff07800 /* 0x1ff07800-0x1ff07A0F: OTP (AXIM) */ + +/* SRAM Base Addresses **************************************************************/ + +#define STM32_DTCRAM_BASE 0x20000000 /* 0x20000000-0x2000ffff: DTCM-RAM on TCM interface */ +#define STM32_SRAM1_BASE 0x20010000 /* 0x20010000-0x2003bfff: System SRAM1 */ +#define STM32_SRAM2_BASE 0x2003C000 /* 0x2003c000-0x2003ffff: System SRAM2 */ + +/* Peripheral Base Addresses ********************************************************/ + +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40007fff: APB1 */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40016bff: APB2 */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x4007ffff: APB1 */ +#define STM32_AHB2_BASE 0x50000000 /* 0x50000000-0x50060bff: AHB2 */ +#define STM32_AHB3_BASE 0x60000000 /* 0x60000000-0xdfffffff: AHB3 */ + +/* APB1 Base Addresses **************************************************************/ + +#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff: TIM2 */ +#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff: TIM3 */ +#define STM32_TIM4_BASE 0x40000800 /* 0x40000800-0x40000bff: TIM4 */ +#define STM32_TIM5_BASE 0x40000c00 /* 0x40000c00-0x40000fff: TIM5 */ +#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff: TIM6 */ +#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff: TIM7 */ +#define STM32_TIM12_BASE 0x40001800 /* 0x40001800-0x40001bff: TIM12 */ +#define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00-0x40001fff: TIM13 */ +#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 */ +#define STM32_LPTIM1_BASE 0x40002400 /* 0x40002400-0x400027ff: LPTIM1 */ +#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */ +#define STM32_BKP_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */ +#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: WWDG */ +#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: IWDG */ +#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff: SPI2 / I2S2 */ +#define STM32_I2S2_BASE 0x40003800 /* 0x40003800-0x40003bff: SPI2 / I2S2 */ +#define STM32_SPI3_BASE 0x40003c00 /* 0x40003c00-0x40003fff: SPI3 / I2S3 */ +#define STM32_I2S3_BASE 0x40003c00 /* 0x40003c00-0x40003fff: SPI3 / I2S3 */ +#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff: USART2 */ +#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff: USART3 */ +#define STM32_UART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff: UART4 */ +#define STM32_UART5_BASE 0x40005000 /* 0x40005000-0x400053ff: UART5 */ +#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff: I2C1 */ +#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff: I2C2 */ +#define STM32_I2C3_BASE 0x40005c00 /* 0x40005c00-0x40005fff: I2C3 */ +#define STM32_CAN1_BASE 0x40006400 /* 0x40006400-0x400067ff: CAN1 */ +#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff: PWR */ +#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff: DAC */ +#define STM32_UART7_BASE 0x40007800 /* 0x40007800-0x40007bff: UART7 */ +#define STM32_UART8_BASE 0x40007c00 /* 0x40007c00-0x40007fff: UART8 */ + +/* APB2 Base Addresses **************************************************************/ + +#define STM32_TIM1_BASE 0x40010000 /* 0x40010000-0x400103ff: TIM1 */ +#define STM32_TIM8_BASE 0x40010400 /* 0x40010400-0x400107ff: TIM8 */ +#define STM32_USART1_BASE 0x40011000 /* 0x40011000-0x400113ff: USART1 */ +#define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff: USART6 */ +#define STM32_SDMMC2_BASE 0x40011C00 /* 0x4001C000-0x40011fff: SDMMC2 */ +#define STM32_ADC_BASE 0x40012000 /* 0x40012000-0x400123ff: ADC1 - ADC2 - ADC3 */ +# define STM32_ADC1_BASE 0x40012000 /* ADC1 */ +# define STM32_ADC2_BASE 0x40012100 /* ADC2 */ +# define STM32_ADC3_BASE 0x40012200 /* ADC3 */ +# define STM32_ADCCMN_BASE 0x40012300 /* Common */ +#define STM32_SDMMC1_BASE 0x40012c00 /* 0x40012c00-0x40012fff: SDMMC1 */ +#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff: SPI1 */ +#define STM32_SPI4_BASE 0x40013400 /* 0x40013400-0x400137ff: SPI4 */ +#define STM32_SYSCFG_BASE 0x40013800 /* 0x40013800-0x40013bff: SYSCFG */ +#define STM32_EXTI_BASE 0x40013c00 /* 0x40013c00-0x40013fff: EXTI */ +#define STM32_TIM9_BASE 0x40014000 /* 0x40014000-0x400143ff: TIM9 */ +#define STM32_TIM10_BASE 0x40014400 /* 0x40014400-0x400147ff: TIM10 */ +#define STM32_TIM11_BASE 0x40014800 /* 0x40014800-0x40014bff: TIM11 */ +#define STM32_SPI5_BASE 0x40015000 /* 0x40015000-0x400153ff: SPI5 */ +#define STM32_SAI1_BASE 0x40015800 /* 0x40015800-0x40015bff: SAI1 */ +#define STM32_SAI2_BASE 0x40015c00 /* 0x40015c00-0x40015fff: SAI2 */ +#define STM32_OTGPHY_BASE 0x40017c00 /* 0x40017C00-0x40017fff: OTG PHY HS */ + +/* AHB1 Base Addresses **************************************************************/ + +#define STM32_GPIO_INCR 0x400 /* 1K spacing between GPIO groups */ +#define STM32_GPIOA_BASE 0x40020000 /* 0x40020000-0x400203ff: GPIOA */ +#define STM32_GPIOB_BASE 0x40020400 /* 0x40020400-0x400207ff: GPIOB */ +#define STM32_GPIOC_BASE 0x40020800 /* 0x40020800-0x40020bff: GPIOC */ +#define STM32_GPIOD_BASE 0x40020c00 /* 0x40020c00-0x40020fff: GPIOD */ +#define STM32_GPIOE_BASE 0x40021000 /* 0x40021000-0x400213ff: GPIOE */ +#define STM32_GPIOF_BASE 0x40021400 /* 0x40021400-0x400217ff: GPIOF */ +#define STM32_GPIOG_BASE 0x40021800 /* 0x40021800-0x40021bff: GPIOG */ +#define STM32_GPIOH_BASE 0x40021c00 /* 0x40021c00-0x40021fff: GPIOH */ +#define STM32_GPIOI_BASE 0x40022000 /* 0x40022000-0x400223ff: GPIOI */ +#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */ +#define STM32_RCC_BASE 0x40023800 /* 0x40023800-0x40023bff: RCC */ +#define STM32_FLASHIF_BASE 0x40023c00 /* 0x40023c00-0x40023fff: Flash interface */ +#define STM32_BKPSRAM_BASE 0x40024000 /* 0x40024000-0x40024fff: BKPSRAM */ +#define STM32_DMA1_BASE 0x40026000 /* 0x40026000-0x400263ff: DMA1 */ +#define STM32_DMA2_BASE 0x40026400 /* 0x40026400-0x400267ff: DMA2 */ +#define STM32_USBOTGHS_BASE 0x40040000 /* 0x40040000-0x4007ffff: USB OTG HS */ + +/* AHB2 Base Addresses **************************************************************/ + +#define STM32_USBOTGFS_BASE 0x50000000 /* 0x50000000-0x5003ffff: USB OTG FS */ +#define STM32_RNG_BASE 0x50060800 /* 0x50060800-0x50060bff: RNG */ + +/* AHB3 Base Addresses **************************************************************/ + +#define STM32_FMCBANK1_BASE 0x60000000 /* 0x60000000-0x6fffffff: FMC bank 1 */ +#define STM32_FMCBANK2_BASE 0x70000000 /* 0x70000000-0x7fffffff: FMC bank 2 */ +#define STM32_FMCBANK3_BASE 0x80000000 /* 0x80000000-0x8fffffff: FMC bank 3 */ +#define STM32_FMCBANK4_BASE 0x90000000 /* 0x90000000-0x9fffffff: FMC bank 4 */ +#define STM32_FMC_BASE 0xa0000000 /* 0xa0000000-0xa0000fff: FMC control registers */ +#define STM32_QUADSPI_BASE 0xa0001000 /* 0xa0001000-0xa0001fff: QuadSPI Control */ +#define STM32_FMCBANK5_BASE 0xc0000000 /* 0xc0000000-0xcfffffff: FMC bank 5 */ +#define STM32_FMCBANK6_BASE 0xd0000000 /* 0xd0000000-0xdfffffff: FMC bank 6 */ + +/* Cortex-M7 Base Addresses *********************************************************/ +/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this + * address range */ + +#define STM32_DEBUGMCU_BASE 0xe0042000 + +#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_pinmap.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_pinmap.h new file mode 100644 index 0000000000000000000000000000000000000000..9e3f10b6befb23667e7478b27d8e18a406375ce3 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_pinmap.h @@ -0,0 +1,938 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f72xx73xx_pinmap.h + * + * Copyright (C) 2014-2015, 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F72XX73XX_PINMAP_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F72XX73XX_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "stm32_gpio.h" + +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Alternate Pin Functions. All members of the STM32F72|73xxx family share the same + * pin multiplexing (although they may differ in the pins physically available). + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. + * Drivers, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. For example, if + * CAN1_RX connects vis PA11 on some board, then the following definitions should + * appear inthe board.h header file for that board: + * + * #define GPIO_CAN1_RX GPIO_CAN1_RX_1 + * + * The driver will then automatically configre PA11 as the CAN1 RX pin. + */ + +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as frequency, + * open-drain/push-pull, and pull-up/down! Just the basics are defined for most + * pins in this file. + */ + +/* ADC */ + +#define GPIO_ADC1_IN0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0) +#define GPIO_ADC1_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ADC1_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2) +#define GPIO_ADC1_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3) +#define GPIO_ADC1_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_ADC1_IN5 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) +#define GPIO_ADC1_IN6 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6) +#define GPIO_ADC1_IN7 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7) +#define GPIO_ADC1_IN8 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0) +#define GPIO_ADC1_IN9 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1) +#define GPIO_ADC1_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) +#define GPIO_ADC1_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ADC1_IN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ADC1_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ADC1_IN14 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4) +#define GPIO_ADC1_IN15 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5) + +#define GPIO_ADC2_IN0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0) +#define GPIO_ADC2_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ADC2_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2) +#define GPIO_ADC2_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3) +#define GPIO_ADC2_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_ADC2_IN5 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) +#define GPIO_ADC2_IN6 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6) +#define GPIO_ADC2_IN7 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7) +#define GPIO_ADC2_IN8 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0) +#define GPIO_ADC2_IN9 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1) +#define GPIO_ADC2_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) +#define GPIO_ADC2_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ADC2_IN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ADC2_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ADC2_IN14 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4) +#define GPIO_ADC2_IN15 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5) + +#define GPIO_ADC3_IN0 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0) +#define GPIO_ADC3_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ADC3_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2) +#define GPIO_ADC3_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3) +#define GPIO_ADC3_IN4 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN6) +#define GPIO_ADC3_IN5 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN7) +#define GPIO_ADC3_IN6 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN8) +#define GPIO_ADC3_IN7 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN9) +#define GPIO_ADC3_IN8 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN10) + +#define GPIO_ADC3_IN9 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN3) +#define GPIO_ADC3_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) +#define GPIO_ADC3_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ADC3_IN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ADC3_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ADC3_IN14 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN4) +#define GPIO_ADC3_IN15 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN5) + +/* CAN */ + +#define GPIO_CAN1_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_CAN1_RX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_CAN1_RX_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0) +#define GPIO_CAN1_RX_4 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN14) +#define GPIO_CAN1_RX_5 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9) + +#define GPIO_CAN1_TX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12) +#define GPIO_CAN1_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_CAN1_TX_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN1) +#define GPIO_CAN1_TX_4 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13) + +/* DAC -" Once the DAC channel is enabled, the corresponding GPIO pin + * (PA4 or PA5) is automatically connected to the analog converter output + * (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin + * should first be configured to analog (AIN)". + */ + +#define GPIO_DAC1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_DAC2_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) + +/* Event outputs */ + +#define GPIO_PA0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN0) +#define GPIO_PA1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN1) +#define GPIO_PA2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN2) +#define GPIO_PA3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN3) +#define GPIO_PA4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN4) +#define GPIO_PA5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN5) +#define GPIO_PA6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN6) +#define GPIO_PA7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN7) +#define GPIO_PA8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN8) +#define GPIO_PA9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN9) +#define GPIO_PA10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN10) +#define GPIO_PA11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN11) +#define GPIO_PA12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN12) +#define GPIO_PA13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN13) +#define GPIO_PA14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN14) +#define GPIO_PA15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN15) + +#define GPIO_PB0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN0) +#define GPIO_PB1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN1) +#define GPIO_PB2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN2) +#define GPIO_PB3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN3) +#define GPIO_PB4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN4) +#define GPIO_PB5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN5) +#define GPIO_PB6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN6) +#define GPIO_PB7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN7) +#define GPIO_PB8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN8) +#define GPIO_PB9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN9) +#define GPIO_PB10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN10) +#define GPIO_PB11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN11) +#define GPIO_PB12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN12) +#define GPIO_PB13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN13) +#define GPIO_PB14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN14) +#define GPIO_PB15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN15) + +#define GPIO_PC0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN0) +#define GPIO_PC1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN1) +#define GPIO_PC2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN2) +#define GPIO_PC3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN3) +#define GPIO_PC4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN4) +#define GPIO_PC5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN5) +#define GPIO_PC6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN6) +#define GPIO_PC7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN7) +#define GPIO_PC8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN8) +#define GPIO_PC9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN9) +#define GPIO_PC10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN10) +#define GPIO_PC11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN11) +#define GPIO_PC12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN12) +#define GPIO_PC13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN13) +#define GPIO_PC14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN14) +#define GPIO_PC15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTC|GPIO_PIN15) + +#define GPIO_PD0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN0) +#define GPIO_PD1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN1) +#define GPIO_PD2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN2) +#define GPIO_PD3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN3) +#define GPIO_PD4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN4) +#define GPIO_PD5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN5) +#define GPIO_PD6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN6) +#define GPIO_PD7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN7) +#define GPIO_PD8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN8) +#define GPIO_PD9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN9) +#define GPIO_PD10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN10) +#define GPIO_PD11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN11) +#define GPIO_PD12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN12) +#define GPIO_PD13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN13) +#define GPIO_PD14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN14) +#define GPIO_PD15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTD|GPIO_PIN15) + +#define GPIO_PE0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN0) +#define GPIO_PE1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN1) +#define GPIO_PE2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN2) +#define GPIO_PE3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN3) +#define GPIO_PE4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN4) +#define GPIO_PE5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN5) +#define GPIO_PE6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN6) +#define GPIO_PE7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN7) +#define GPIO_PE8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN8) +#define GPIO_PE9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN9) +#define GPIO_PE10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN10) +#define GPIO_PE11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN11) +#define GPIO_PE12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN12) +#define GPIO_PE13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN13) +#define GPIO_PE14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN14) +#define GPIO_PE15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTE|GPIO_PIN15) + +#define GPIO_PF0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN0) +#define GPIO_PF1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN1) +#define GPIO_PF2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN2) +#define GPIO_PF3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN3) +#define GPIO_PF4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN4) +#define GPIO_PF5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN5) +#define GPIO_PF6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN6) +#define GPIO_PF7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN7) +#define GPIO_PF8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN8) +#define GPIO_PF9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN9) +#define GPIO_PF10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN10) +#define GPIO_PF11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN11) +#define GPIO_PF12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN12) +#define GPIO_PF13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN13) +#define GPIO_PF14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN14) +#define GPIO_PF15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTF|GPIO_PIN15) + +#define GPIO_PG0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN0) +#define GPIO_PG1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN1) +#define GPIO_PG2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN2) +#define GPIO_PG3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN3) +#define GPIO_PG4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN4) +#define GPIO_PG5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN5) +#define GPIO_PG6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN6) +#define GPIO_PG7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN7) +#define GPIO_PG8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN8) +#define GPIO_PG9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN9) +#define GPIO_PG10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN10) +#define GPIO_PG11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN11) +#define GPIO_PG12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN12) +#define GPIO_PG13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN13) +#define GPIO_PG14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN14) +#define GPIO_PG15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTG|GPIO_PIN15) + +#define GPIO_PH0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN0) +#define GPIO_PH1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN1) +#define GPIO_PH2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN2) +#define GPIO_PH3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN3) +#define GPIO_PH4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN4) +#define GPIO_PH5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN5) +#define GPIO_PH6_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN6) +#define GPIO_PH7_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN7) +#define GPIO_PH8_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN8) +#define GPIO_PH9_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN9) +#define GPIO_PH10_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN10) +#define GPIO_PH11_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN11) +#define GPIO_PH12_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN12) +#define GPIO_PH13_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN13) +#define GPIO_PH14_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN14) +#define GPIO_PH15_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTH|GPIO_PIN15) + +#define GPIO_PI0_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN0) +#define GPIO_PI1_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN1) +#define GPIO_PI2_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN2) +#define GPIO_PI3_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN3) +#define GPIO_PI4_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN4) +#define GPIO_PI5_EVENTOUT (GPIO_ALT|GPIO_AF15|GPIO_PORTI|GPIO_PIN5) + +/* Flexible Static Memory Controller (FMC) */ + +#define GPIO_FMC_A0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN0) +#define GPIO_FMC_A1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN1) +#define GPIO_FMC_A2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN2) +#define GPIO_FMC_A3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN3) +#define GPIO_FMC_A4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN4) +#define GPIO_FMC_A5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN5) +#define GPIO_FMC_A6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN12) +#define GPIO_FMC_A7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN13) +#define GPIO_FMC_A8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN14) +#define GPIO_FMC_A9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN15) +#define GPIO_FMC_A10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN0) +#define GPIO_FMC_A11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN1) +#define GPIO_FMC_A12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN2) +#define GPIO_FMC_A13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN3) +#define GPIO_FMC_A14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4) +#define GPIO_FMC_A15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5) +#define GPIO_FMC_A16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11) +#define GPIO_FMC_A17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12) +#define GPIO_FMC_A18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN13) +#define GPIO_FMC_A19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN3) +#define GPIO_FMC_A20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN4) +#define GPIO_FMC_A21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN5) +#define GPIO_FMC_A22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN6) +#define GPIO_FMC_A23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN2) +#define GPIO_FMC_A24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN13) +#define GPIO_FMC_A25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN14) +#define GPIO_FMC_ALE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12) +#define GPIO_FMC_BA0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4) +#define GPIO_FMC_BA1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5) +#define GPIO_FMC_CLE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11) +#define GPIO_FMC_CLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN3) +#define GPIO_FMC_D0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN14) +#define GPIO_FMC_D1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN15) +#define GPIO_FMC_D2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN0) +#define GPIO_FMC_D3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN1) +#define GPIO_FMC_D4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN7) +#define GPIO_FMC_D5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN8) +#define GPIO_FMC_D6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN9) +#define GPIO_FMC_D7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN10) +#define GPIO_FMC_D8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN11) +#define GPIO_FMC_D9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN12) +#define GPIO_FMC_D10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN13) +#define GPIO_FMC_D11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN14) +#define GPIO_FMC_D12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN15) +#define GPIO_FMC_D13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8) +#define GPIO_FMC_D14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9) +#define GPIO_FMC_D15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10) +#define GPIO_FMC_D16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN8) +#define GPIO_FMC_D17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN9) +#define GPIO_FMC_D18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN10) +#define GPIO_FMC_D19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN11) +#define GPIO_FMC_D20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN12) +#define GPIO_FMC_D21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN13) +#define GPIO_FMC_D22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN14) +#define GPIO_FMC_D23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN15) +#define GPIO_FMC_D24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN0) +#define GPIO_FMC_D25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN1) +#define GPIO_FMC_D26 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN2) +#define GPIO_FMC_D27 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN3) +#define GPIO_FMC_D28 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN6) +#define GPIO_FMC_D29 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN7) +#define GPIO_FMC_D30 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN9) +#define GPIO_FMC_D31 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN10) +#define GPIO_FMC_INT (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN7) +#define GPIO_FMC_NBL0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN0) +#define GPIO_FMC_NBL1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN1) +#define GPIO_FMC_NBL2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN4) +#define GPIO_FMC_NBL3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN5) +#define GPIO_FMC_NCE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9) +#define GPIO_FMC_NE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7) +#define GPIO_FMC_NE2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9) +#define GPIO_FMC_NE3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10) +#define GPIO_FMC_NE4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN12) +#define GPIO_FMC_NL (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN7) +#define GPIO_FMC_NOE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN4) +#define GPIO_FMC_NWAIT (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6) +#define GPIO_FMC_NWE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN5) +#define GPIO_FMC_SDCKE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3) +#define GPIO_FMC_SDCKE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN5) +#define GPIO_FMC_SDCKE0_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2) +#define GPIO_FMC_SDCKE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_FMC_SDCKE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN7) +#define GPIO_FMC_SDCLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8) +#define GPIO_FMC_SDNCAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15) +#define GPIO_FMC_SDNE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2) +#define GPIO_FMC_SDNE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN4) +#define GPIO_FMC_SDNE0_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3) +#define GPIO_FMC_SDNE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6) +#define GPIO_FMC_SDNE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN6) +#define GPIO_FMC_SDNRAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11) +#define GPIO_FMC_SDNWE_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_FMC_SDNWE_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0) +#define GPIO_FMC_SDNWE_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN5) + +/* I2C */ + +#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6) +#define GPIO_I2C1_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7) +#define GPIO_I2C1_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9) +#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) + +#define GPIO_I2C2_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C2_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN1) +#define GPIO_I2C2_SCL_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN4) +#define GPIO_I2C2_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN11) +#define GPIO_I2C2_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTF|GPIO_PIN0) +#define GPIO_I2C2_SDA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN5) +#define GPIO_I2C2_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12) +#define GPIO_I2C2_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN2) +#define GPIO_I2C2_SMBA_3 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6) + +#define GPIO_I2C3_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN8) +#define GPIO_I2C3_SCL_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN7) +#define GPIO_I2C3_SDA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN9) +#define GPIO_I2C3_SDA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN8) +#define GPIO_I2C3_SMBA_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9) +#define GPIO_I2C3_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9) + +/* I2S */ + +#define GPIO_I2S1_CK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN5) +#define GPIO_I2S1_CK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN3) +#define GPIO_I2S1_MCK (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN4) +#define GPIO_I2S1_SD_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN7) +#define GPIO_I2S1_SD_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN5) +#define GPIO_I2S1_WS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN4) +#define GPIO_I2S1_WS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN15) + +#define GPIO_I2S2_CK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN9) +#define GPIO_I2S2_CK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2S2_CK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN13) +#define GPIO_I2S2_CK_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN3) +#define GPIO_I2S2_CK_5 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN1) +#define GPIO_I2S2_MCK (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN6) +#define GPIO_I2S2_SD_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN15) +#define GPIO_I2S2_SD_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN1) +#define GPIO_I2S2_SD_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN3) +#define GPIO_I2S2_SD_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN3) +#define GPIO_I2S2_WS_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN9) +#define GPIO_I2S2_WS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN12) +#define GPIO_I2S2_WS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN0) +#define GPIO_I2S2_WS_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN4) + +#define GPIO_I2S3_CK_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN3) +#define GPIO_I2S3_CK_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN10) +#define GPIO_I2S3_MCK (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN7) +#define GPIO_I2S3_SD_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN5) +#define GPIO_I2S3_SD_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN12) +#define GPIO_I2S3_SD_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN6) +#define GPIO_I2S3_SD_4 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN2) +#define GPIO_I2S3_WS_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN4) +#define GPIO_I2S3_WS_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN15) + +#define GPIO_I2S_CKIN (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN9) + +/* JTAG */ + +#define GPIO_JTCK (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14) +#define GPIO_JTDI (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15) +#define GPIO_JTDO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3) +#define GPIO_JTMS (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13) +#define GPIO_NJTRST (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4) + +#define GPIO_SWCLK (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14) +#define GPIO_SWDIO (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13) + +/* Low Power Timer */ + +#define GPIO_LPTIM1_ETR_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0) +#define GPIO_LPTIM1_ETR_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN14) +#define GPIO_LPTIM1_IN1_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12) +#define GPIO_LPTIM1_IN1_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN12) +#define GPIO_LPTIM1_IN2_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN1) +#define GPIO_LPTIM1_IN2_4 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN2) +#define GPIO_LPTIM1_OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13) +#define GPIO_LPTIM1_OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13) + +/* Clocks outputs */ + +#define GPIO_MCO1 (GPIO_ALT|GPIO_AF0|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_MCO2 (GPIO_ALT|GPIO_AF0|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) + +/* OTG FS/HS (VBUS PA9 is not an alternate configuration) */ + +#define GPIO_OTGFS_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_OTGFS_DP (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12) +#define GPIO_OTGFS_ID (GPIO_ALT|GPIO_PULLUP|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN10) +#define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) + +#define GPIO_OTGHSFS_DM (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_OTGHSFS_DP (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_OTGHSFS_ID (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12) + +#define GPIO_OTGHS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4) + +#define GPIO_OTGHS_ULPI_CK (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN5) +#define GPIO_OTGHS_ULPI_D0 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN3) +#define GPIO_OTGHS_ULPI_D1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0) +#define GPIO_OTGHS_ULPI_D2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1) +#define GPIO_OTGHS_ULPI_D3 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10) +#define GPIO_OTGHS_ULPI_D4 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11) +#define GPIO_OTGHS_ULPI_D5 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN12) +#define GPIO_OTGHS_ULPI_D6 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN13) +#define GPIO_OTGHS_ULPI_D7 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN5) +#define GPIO_OTGHS_ULPI_DIR_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2) +#define GPIO_OTGHS_ULPI_DIR_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN11) +#define GPIO_OTGHS_ULPI_NXT_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3) +#define GPIO_OTGHS_ULPI_NXT_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN4) +#define GPIO_OTGHS_ULPI_STP (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN0) + +/* QuadSPI */ + +#define GPIO_QUADSPI_BK1_IO0_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTC|GPIO_PIN9) +#define GPIO_QUADSPI_BK1_IO0_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTD|GPIO_PIN11) +#define GPIO_QUADSPI_BK1_IO0_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN8) +#define GPIO_QUADSPI_BK1_IO1_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTC|GPIO_PIN10) +#define GPIO_QUADSPI_BK1_IO1_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTD|GPIO_PIN12) +#define GPIO_QUADSPI_BK1_IO1_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN9) +#define GPIO_QUADSPI_BK1_IO2_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTE|GPIO_PIN2) +#define GPIO_QUADSPI_BK1_IO2_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTF|GPIO_PIN7) +#define GPIO_QUADSPI_BK1_IO3_1 (GPIO_ALT|GPIO_AF9|GPIO_PORTA|GPIO_PIN1) +#define GPIO_QUADSPI_BK1_IO3_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTD|GPIO_PIN13) +#define GPIO_QUADSPI_BK1_IO3_3 (GPIO_ALT|GPIO_AF9|GPIO_PORTF|GPIO_PIN6) +#define GPIO_QUADSPI_BK1_NCS (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN6) + +#define GPIO_QUADSPI_BK2_IO0_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN7) +#define GPIO_QUADSPI_BK2_IO0_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTH|GPIO_PIN2) +#define GPIO_QUADSPI_BK2_IO1_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN8) +#define GPIO_QUADSPI_BK2_IO1_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTH|GPIO_PIN3) +#define GPIO_QUADSPI_BK2_IO2_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN9) +#define GPIO_QUADSPI_BK2_IO2_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTG|GPIO_PIN9) +#define GPIO_QUADSPI_BK2_IO3_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN10) +#define GPIO_QUADSPI_BK2_IO3_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTG|GPIO_PIN14) +#define GPIO_QUADSPI_BK2_NCS (GPIO_ALT|GPIO_AF9|GPIO_PORTC|GPIO_PIN11) + +#define GPIO_QUADSPI_CLK (GPIO_ALT|GPIO_AF9|GPIO_PORTB|GPIO_PIN2) + +/* RTC */ + +#define GPIO_RTC_REFIN (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN15) + +/* Serial Audio Interface */ + +#define GPIO_SAI1_FS_A (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN4) +#define GPIO_SAI1_FS_B (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN9) +#define GPIO_SAI1_MCLK_A (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN2) +#define GPIO_SAI1_MCLK_B (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN7) +#define GPIO_SAI1_SCK_A (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN5) +#define GPIO_SAI1_SCK_B (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN8) +#define GPIO_SAI1_SD_A_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN2) +#define GPIO_SAI1_SD_A_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN1) +#define GPIO_SAI1_SD_A_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTD|GPIO_PIN6) +#define GPIO_SAI1_SD_A_4 (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN6) +#define GPIO_SAI1_SD_B_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTE|GPIO_PIN3) +#define GPIO_SAI1_SD_B_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTF|GPIO_PIN6) + +#define GPIO_SAI2_FS_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN12) +#define GPIO_SAI2_FS_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN7) +#define GPIO_SAI2_FS_B_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN12) +#define GPIO_SAI2_FS_B_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN0) +#define GPIO_SAI2_FS_B_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN13) +#define GPIO_SAI2_FS_B_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN9) +#define GPIO_SAI2_MCLK_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN0) +#define GPIO_SAI2_MCLK_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN4) +#define GPIO_SAI2_MCLK_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN1) +#define GPIO_SAI2_MCLK_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN6) +#define GPIO_SAI2_MCLK_B_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN14) +#define GPIO_SAI2_MCLK_B_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN3) +#define GPIO_SAI2_SCK_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN13) +#define GPIO_SAI2_SCK_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN5) +#define GPIO_SAI2_SCK_B_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN2) +#define GPIO_SAI2_SCK_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN12) +#define GPIO_SAI2_SCK_B_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN2) +#define GPIO_SAI2_SD_A_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTD|GPIO_PIN11) +#define GPIO_SAI2_SD_A_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN6) +#define GPIO_SAI2_SD_B_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN0) +#define GPIO_SAI2_SD_B_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTE|GPIO_PIN11) +#define GPIO_SAI2_SD_B_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN11) +#define GPIO_SAI2_SD_B_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN10) + +/* SD/MMC */ + +#define GPIO_SDMMC1_CK (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12) +#define GPIO_SDMMC1_CMD (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2) +#define GPIO_SDMMC1_D0 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8) +#define GPIO_SDMMC1_D1 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) +#define GPIO_SDMMC1_D2 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10) +#define GPIO_SDMMC1_D3 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11) +#define GPIO_SDMMC1_D4 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_SDMMC1_D5 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_SDMMC1_D6 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_SDMMC1_D7 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) + +#define GPIO_SDMMC2_CK (GPIO_ALT|GPIO_AF11|GPIO_PORTD|GPIO_PIN6) +#define GPIO_SDMMC2_CMD (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN7) +#define GPIO_SDMMC2_D0_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_SDMMC2_D0_2 (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9) +#define GPIO_SDMMC2_D1_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_SDMMC2_D1_2 (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10) +#define GPIO_SDMMC2_D2_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3) +#define GPIO_SDMMC2_D2_2 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11) +#define GPIO_SDMMC2_D3_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SDMMC2_D3_2 (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN12) +#define GPIO_SDMMC2_D4 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_SDMMC2_D5 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_SDMMC2_D6 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_SDMMC2_D7 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) + +/* SPI */ + +#define GPIO_SPI1_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6) +#define GPIO_SPI1_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SPI1_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_SPI1_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_SPI1_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4) +#define GPIO_SPI1_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15) +#define GPIO_SPI1_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN5) +#define GPIO_SPI1_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3) + +#define GPIO_SPI2_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN14) +#define GPIO_SPI2_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN2) +#define GPIO_SPI2_MISO_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN2) +#define GPIO_SPI2_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15) +#define GPIO_SPI2_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN1) +#define GPIO_SPI2_MOSI_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN3) +#define GPIO_SPI2_MOSI_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN3) +#define GPIO_SPI2_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN9) +#define GPIO_SPI2_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN12) +#define GPIO_SPI2_NSS_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN0) +#define GPIO_SPI2_NSS_4 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SPI2_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9) +#define GPIO_SPI2_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN10) +#define GPIO_SPI2_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN13) +#define GPIO_SPI2_SCK_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN3) +#define GPIO_SPI2_SCK_5 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN1) + +#define GPIO_SPI3_MISO_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) +#define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN11) +#define GPIO_SPI3_MOSI_1 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN2) +#define GPIO_SPI3_MOSI_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5) +#define GPIO_SPI3_MOSI_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN12) +#define GPIO_SPI3_MOSI_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN6) +#define GPIO_SPI3_NSS_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4) +#define GPIO_SPI3_NSS_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15) +#define GPIO_SPI3_SCK_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3) +#define GPIO_SPI3_SCK_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN10) + +#define GPIO_SPI4_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN5) +#define GPIO_SPI4_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN13) +#define GPIO_SPI4_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN6) +#define GPIO_SPI4_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN14) +#define GPIO_SPI4_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN4) +#define GPIO_SPI4_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN11) +#define GPIO_SPI4_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN2) +#define GPIO_SPI4_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN12) + +#define GPIO_SPI5_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN8) +#define GPIO_SPI5_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN7) +#define GPIO_SPI5_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN9) +#define GPIO_SPI5_MOSI_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN11) +#define GPIO_SPI5_NSS_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN6) +#define GPIO_SPI5_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN5) +#define GPIO_SPI5_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN7) +#define GPIO_SPI5_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN6) + +/* Timers */ + +#define GPIO_TIM1_BKIN_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM1_BKIN_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN12) +#define GPIO_TIM1_BKIN_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN15) +#define GPIO_TIM1_BKIN2 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN6) +#define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN13) +#define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN8) +#define GPIO_TIM1_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8) +#define GPIO_TIM1_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN9) +#define GPIO_TIM1_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_TIM1_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN9) +#define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN13) +#define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN8) +#define GPIO_TIM1_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM1_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN11) +#define GPIO_TIM1_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM1_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11) +#define GPIO_TIM1_CH2N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM1_CH2N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM1_CH2N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN10) +#define GPIO_TIM1_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM1_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN13) +#define GPIO_TIM1_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM1_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13) +#define GPIO_TIM1_CH3N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM1_CH3N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM1_CH3N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN12) +#define GPIO_TIM1_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM1_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN14) +#define GPIO_TIM1_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM1_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14) +#define GPIO_TIM1_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN12) +#define GPIO_TIM1_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN7) + +#define GPIO_TIM2_CH1IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM2_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM2_CH1IN_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15) +#define GPIO_TIM2_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM2_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM2_CH1OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15) +#define GPIO_TIM2_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM2_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TIM2_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM2_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN10) +#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10) +#define GPIO_TIM2_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM2_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN11) +#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11) +#define GPIO_TIM2_ETR_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM2_ETR_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM2_ETR_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15) + +#define GPIO_TIM3_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM3_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM3_CH1IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM3_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM3_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM3_CH1OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM3_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM3_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM3_CH2IN_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM3_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM3_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM3_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM3_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM3_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM3_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM3_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM3_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM3_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM3_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM3_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN2) + +#define GPIO_TIM4_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM4_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12) +#define GPIO_TIM4_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM4_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12) +#define GPIO_TIM4_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM4_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN13) +#define GPIO_TIM4_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM4_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13) +#define GPIO_TIM4_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM4_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN14) +#define GPIO_TIM4_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM4_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN14) +#define GPIO_TIM4_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM4_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN15) +#define GPIO_TIM4_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM4_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN15) +#define GPIO_TIM4_ETR (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0) + +#define GPIO_TIM5_CH1IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM5_CH1IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN10) +#define GPIO_TIM5_CH1OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM5_CH1OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN10) +#define GPIO_TIM5_CH2IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM5_CH2IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN11) +#define GPIO_TIM5_CH2OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM5_CH2OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN11) +#define GPIO_TIM5_CH3IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM5_CH3IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN12) +#define GPIO_TIM5_CH3OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM5_CH3OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN12) +#define GPIO_TIM5_CH4IN_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM5_CH4IN_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN0) +#define GPIO_TIM5_CH4OUT_1 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM5_CH4OUT_2 (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN0) + +#define GPIO_TIM8_BKIN_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM8_BKIN_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTI|GPIO_PIN4) +#define GPIO_TIM8_BKIN2_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN8) +#define GPIO_TIM8_BKIN2_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTI|GPIO_PIN1) +#define GPIO_TIM8_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM8_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN5) +#define GPIO_TIM8_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM8_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN5) +#define GPIO_TIM8_CH1N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM8_CH1N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM8_CH1N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN13) +#define GPIO_TIM8_CH2IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM8_CH2IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN6) +#define GPIO_TIM8_CH2OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM8_CH2OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN6) +#define GPIO_TIM8_CH2N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM8_CH2N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM8_CH2N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN14) +#define GPIO_TIM8_CH3IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM8_CH3IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN7) +#define GPIO_TIM8_CH3OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM8_CH3OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN7) +#define GPIO_TIM8_CH3N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM8_CH3N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM8_CH3N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN15) +#define GPIO_TIM8_CH4IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM8_CH4IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN2) +#define GPIO_TIM8_CH4OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM8_CH4OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN2) +#define GPIO_TIM8_ETR_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM8_ETR_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN3) + +#define GPIO_TIM9_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM9_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN5) +#define GPIO_TIM9_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM9_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5) +#define GPIO_TIM9_CH2IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM9_CH2IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN6) +#define GPIO_TIM9_CH2OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM9_CH2OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6) + +#define GPIO_TIM10_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM10_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN6) +#define GPIO_TIM10_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM10_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6) + +#define GPIO_TIM11_CH1IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM11_CH1IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN7) +#define GPIO_TIM11_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM11_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7) + +#define GPIO_TIM12_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM12_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN6) +#define GPIO_TIM12_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM12_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6) +#define GPIO_TIM12_CH2IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM12_CH2IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTH|GPIO_PIN9) +#define GPIO_TIM12_CH2OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM12_CH2OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9) + +#define GPIO_TIM13_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM13_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN8) +#define GPIO_TIM13_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM13_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN8) + +#define GPIO_TIM14_CH1IN_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM14_CH1IN_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9) +#define GPIO_TIM14_CH1OUT_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM14_CH1OUT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9) + +/* Trace */ + +#define GPIO_TRACECLK (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN2) +#define GPIO_TRACED0_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN1) +#define GPIO_TRACED0_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN3) +#define GPIO_TRACED0_3 (GPIO_ALT|GPIO_AF0|GPIO_PORTG|GPIO_PIN13) +#define GPIO_TRACED1_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TRACED1_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN4) +#define GPIO_TRACED1_3 (GPIO_ALT|GPIO_AF0|GPIO_PORTG|GPIO_PIN14) +#define GPIO_TRACED2_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTD|GPIO_PIN2) +#define GPIO_TRACED2_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN5) +#define GPIO_TRACED3_1 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN12) +#define GPIO_TRACED3_2 (GPIO_ALT|GPIO_AF0|GPIO_PORTE|GPIO_PIN6) +#define GPIO_TRACESWO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3) + +/* UARTs/USARTs */ + +#define GPIO_USART1_CK (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN8) +#define GPIO_USART1_CTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN11) +#define GPIO_USART1_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN12) +#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10) +#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7) +#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9) +#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) + +#define GPIO_USART2_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN4) +#define GPIO_USART2_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN7) +#define GPIO_USART2_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN0) +#define GPIO_USART2_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN3) +#define GPIO_USART2_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN1) +#define GPIO_USART2_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN4) +#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6) +#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN5) + +#define GPIO_USART3_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN12) +#define GPIO_USART3_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN12) +#define GPIO_USART3_CK_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN10) +#define GPIO_USART3_CTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN13) +#define GPIO_USART3_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN11) +#define GPIO_USART3_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN14) +#define GPIO_USART3_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN12) +#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11) +#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11) +#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN9) +#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10) +#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10) +#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN8) + +#define GPIO_UART4_CTS (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN0) +#define GPIO_UART4_RTS (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN15) +#define GPIO_UART4_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_UART4_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11) +#define GPIO_UART4_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0) +#define GPIO_UART4_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10) + +#define GPIO_UART5_CTS (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN9) +#define GPIO_UART5_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN8) +#define GPIO_UART5_RX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2) +#define GPIO_UART5_TX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN12) + +#define GPIO_USART6_CK_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN8) +#define GPIO_USART6_CK_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN7) +#define GPIO_USART6_CTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN13) +#define GPIO_USART6_CTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN15) +#define GPIO_USART6_RTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN8) +#define GPIO_USART6_RTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN12) +#define GPIO_USART6_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) +#define GPIO_USART6_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9) +#define GPIO_USART6_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_USART6_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14) + +#define GPIO_UART7_CTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTE|GPIO_PIN10) +#define GPIO_UART7_CTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTF|GPIO_PIN9) +#define GPIO_UART7_RTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTE|GPIO_PIN9) +#define GPIO_UART7_RTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTF|GPIO_PIN8) +#define GPIO_UART7_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN7) +#define GPIO_UART7_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6) +#define GPIO_UART7_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN8) +#define GPIO_UART7_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7) + +#define GPIO_UART8_CTS (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN14) +#define GPIO_UART8_RTS (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN15) +#define GPIO_UART8_RX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) +#define GPIO_UART8_TX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) + +#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F72XX73XX_PINMAP_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_pwr.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_pwr.h new file mode 100644 index 0000000000000000000000000000000000000000..6591d0feede57049da5d54368fafa483399ae880 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_pwr.h @@ -0,0 +1,161 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f72xx73xx_pwr.h + * + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_PWR_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_PWR_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CSR1_OFFSET 0x0004 /* Power control/status register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0008 /* Power control register 1 */ +#define STM32_PWR_CSR2_OFFSET 0x000c /* Power control/status register 1 */ + +/* Register Addresses ***************************************************************/ + +#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CSR1 (STM32_PWR_BASE+STM32_PWR_CSR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CSR2 (STM32_PWR_BASE+STM32_PWR_CSR2_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +/* Power control register 1 */ + +#define PWR_CR1_LPDS (1 << 0) /* Bit 0: Low-Power Deepsleep/sleep; low power run */ +#define PWR_CR1_PDDS (1 << 1) /* Bit 1: Power Down Deepsleep */ +#define PWR_CR1_CSBF (1 << 3) /* Bit 3: Clear Standby Flag */ +#define PWR_CR1_PVDE (1 << 4) /* Bit 4: Power Voltage Detector Enable */ +#define PWR_CR1_PLS_SHIFT (5) /* Bits 7-5: PVD Level Selection */ +#define PWR_CR1_PLS_MASK (7 << PWR_CR1_PLS_SHIFT) +# define PWR_CR1_2p0V (0 << PWR_CR1_PLS_SHIFT) /* 000: 2.0V */ +# define PWR_CR1_2p1V (1 << PWR_CR1_PLS_SHIFT) /* 001: 2.1V */ +# define PWR_CR1_2p3V (2 << PWR_CR1_PLS_SHIFT) /* 010: 2.3V */ +# define PWR_CR1_2p5V (3 << PWR_CR1_PLS_SHIFT) /* 011: 2.5V */ +# define PWR_CR1_2p6V (4 << PWR_CR1_PLS_SHIFT) /* 100: 2.6V */ +# define PWR_CR1_2p7V (5 << PWR_CR1_PLS_SHIFT) /* 101: 2.7V */ +# define PWR_CR1_2p8V (6 << PWR_CR1_PLS_SHIFT) /* 110: 2.8V */ +# define PWR_CR1_2p9V (7 << PWR_CR1_PLS_SHIFT) /* 111: 2.9V */ +#define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ +#define PWR_CR1_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */ +#define PWR_CR1_LPUDS (1 << 10) /* Bit 10: Low-power regulator in deepsleep under-drive mode */ +#define PWR_CR1_MRUDS (1 << 11) /* Bit 11: Main regulator in deepsleep under-drive mode */ +#define PWR_CR1_ADCDC1 (1 << 13) /* Bit 13: see AN4073 for details */ +#define PWR_CR1_VOS_SHIFT (14) /* Bits 14-15: Regulator voltage scaling output selection */ +#define PWR_CR1_VOS_MASK (3 << PWR_CR1_VOS_SHIFT) +# define PWR_CR1_VOS_SCALE_3 (1 << PWR_CR1_VOS_SHIFT) /* Fmax = 144MHz */ +# define PWR_CR1_VOS_SCALE_2 (2 << PWR_CR1_VOS_SHIFT) /* Fmax = 168/180MHz */ +# define PWR_CR1_VOS_SCALE_1 (3 << PWR_CR1_VOS_SHIFT) /* Fmax = 180/216MHz */ +#define PWR_CR1_ODEN (1 << 16) /* Bit 16: Over Drive enable */ +#define PWR_CR1_ODSWEN (1 << 17) /* Bit 17: Over Drive switch enabled */ +#define PWR_CR1_UDEN_SHIFT (18) /* Bits 18-19: Under-drive enable in stop mode */ +#define PWR_CR1_UDEN_MASK (3 << PWR_CR1_UDEN_SHIFT) +# define PWR_CR1_UDEN_DISABLE (0 << PWR_CR1_UDEN_SHIFT) /* Under-drive disable */ +# define PWR_CR1_UDEN_ENABLE (3 << PWR_CR1_UDEN_SHIFT) /* Under-drive enable */ + +/* Power control/status register 1 */ + +#define PWR_CSR1_WUIF (1 << 0) /* Bit 0: Wakeup internal flag */ +#define PWR_CSR1_SBF (1 << 1) /* Bit 1: Standby flag */ +#define PWR_CSR1_PVDO (1 << 2) /* Bit 2: PVD Output */ +#define PWR_CSR1_BRR (1 << 3) /* Bit 3: Backup regulator ready */ +#define PWR_CSR1_EIWUP (1 << 8) /* Bit 8: Enable internal wakeup */ +#define PWR_CSR1_BRE (1 << 9) /* Bit 9: Backup regulator enable */ +#define PWR_CSR1_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */ +#define PWR_CSR1_ODRDY (1 << 16) /* Bit 16: Over Drive generator ready */ +#define PWR_CSR1_ODSWRDY (1 << 17) /* Bit 17: Over Drive Switch ready */ +#define PWR_CSR1_UDSRDY_SHIFT (18) /* Bits 18-19: Under-drive ready flag */ +#define PWR_CSR1_UDSRDY_MASK (3 << PWR_CSR1_UDSRDY_SHIFT) +# define PWR_CSR1_UDSRDY_DISAB (0 << PWR_CSR1_UDSRDY_SHIFT) /* Under-drive is disabled */ +# define PWR_CSR1_UDSRDY_STOP (3 << PWR_CSR1_UDSRDY_SHIFT) /* Under-drive mode is activated in Stop mode */ + +/* Power control register 2 */ + +#define PWR_CR2_CWUPF1 (1 << 0) /* Bit 0: Clear Wakeup Pin flag for PA0 */ +#define PWR_CR2_CWUPF2 (1 << 1) /* Bit 1: Clear Wakeup Pin flag for PA2 */ +#define PWR_CR2_CWUPF3 (1 << 2) /* Bit 2: Clear Wakeup Pin flag for PC1 */ +#define PWR_CR2_CWUPF4 (1 << 3) /* Bit 3: Clear Wakeup Pin flag for PC13 */ +#define PWR_CR2_CWUPF5 (1 << 4) /* Bit 4: Clear Wakeup Pin flag for PI8 */ +#define PWR_CR2_CWUPF6 (1 << 5) /* Bit 5: Clear Wakeup Pin flag for PI11 */ +#define PWR_CR2_WUPP1 (1 << 8) /* Bit 8: Wakeup pin polarity bit for PA0 */ +# define PWR_CR2_WUPP1_RISING (0 << 8) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP1_FALLING (1 << 8) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP2 (1 << 9) /* Bit 9: Wakeup pin polarity bit for PA2 */ +# define PWR_CR2_WUPP2_RISING (0 << 9) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP2_FALLING (1 << 9) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP3 (1 << 10) /* Bit 10: Wakeup pin polarity bit for PC1 */ +# define PWR_CR2_WUPP3_RISING (0 << 10) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP3_FALLING (1 << 10) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP4 (1 << 11) /* Bit 11: Wakeup pin polarity bit for PC13 */ +# define PWR_CR2_WUPP4_RISING (0 << 11) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP4_FALLING (1 << 11) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP5 (1 << 12) /* Bit 12: Wakeup pin polarity bit for PI8 */ +# define PWR_CR2_WUPP5_RISING (0 << 12) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP5_FALLING (1 << 12) /* 1= Detection on falling edge */ +#define PWR_CR2_WUPP6 (1 << 13) /* Bits 13: Wakeup pin polarity bit for PI11 */ +# define PWR_CR2_WUPP6_RISING (0 << 13) /* 0=Detection on rising edge */ +# define PWR_CR2_WUPP6_FALLING (1 << 13) /* 1= Detection on falling edge */ + +/* Power control/status register 2 */ + +#define PWR_CSR2_WUPF1 (1 << 0) /* Bit 0: Wakeup Pin flag for PA0 */ +#define PWR_CSR2_WUPF2 (1 << 1) /* Bit 1: Wakeup Pin flag for PA2 */ +#define PWR_CSR2_WUPF3 (1 << 2) /* Bit 2: Wakeup Pin flag for PC1 */ +#define PWR_CSR2_WUPF4 (1 << 3) /* Bit 3: Wakeup Pin flag for PC13 */ +#define PWR_CSR2_WUPF5 (1 << 4) /* Bit 4: Wakeup Pin flag for PI8 */ +#define PWR_CSR2_WUPF6 (1 << 5) /* Bit 5: Wakeup Pin flag for PI11 */ +#define PWR_CSR2_EWUP1 (1 << 8) /* Bit 8: Enable wakeup pin for PA0 */ +#define PWR_CSR2_EWUP2 (1 << 9) /* Bit 9: Enable wakeup pin for PA2 */ +#define PWR_CSR2_EWUP3 (1 << 10) /* Bit 10: Enable wakeup pin for PC1 */ +#define PWR_CSR2_EWUP4 (1 << 11) /* Bit 11: Enable wakeup pin for PC13 */ +#define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */ +#define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */ + +#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_PWR_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_rcc.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_rcc.h new file mode 100644 index 0000000000000000000000000000000000000000..7fa34305f8ebdf463a05d971bc82abc19ff8d98d --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_rcc.h @@ -0,0 +1,669 @@ +/**************************************************************************************************** + * arch/arm/src/stm32f7/chip/stm32f72xx73xx_rcc.h + * + * Copyright (C) 2015-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F72XX73XX_RCC_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F72XX73XX_RCC_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_PLLCFG_OFFSET 0x0004 /* PLL configuration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_CIR_OFFSET 0x000c /* Clock interrupt register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0010 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x0014 /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0018 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR_OFFSET 0x0020 /* APB1 Peripheral reset register */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0024 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0030 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x0034 /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0038 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR_OFFSET 0x0040 /* APB1 Peripheral Clock enable register */ +#define STM32_RCC_APB2ENR_OFFSET 0x0044 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1LPENR_OFFSET 0x0050 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2LPENR_OFFSET 0x0054 /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3LPENR_OFFSET 0x0058 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1LPENR_OFFSET 0x0060 /* RCC APB1 low power mode peripheral clock enable register */ +#define STM32_RCC_APB2LPENR_OFFSET 0x0064 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_BDCR_OFFSET 0x0070 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0074 /* Control/status register */ +#define STM32_RCC_SSCGR_OFFSET 0x0080 /* Spread spectrum clock generation register */ +#define STM32_RCC_PLLI2SCFGR_OFFSET 0x0084 /* PLLI2S configuration register */ +#define STM32_RCC_PLLSAICFGR_OFFSET 0x0088 /* PLLSAI configuration register */ +#define STM32_RCC_DCKCFGR1_OFFSET 0x008c /* Dedicated clocks configuration register 1 */ +#define STM32_RCC_DCKCFGR2_OFFSET 0x0090 /* Dedicated clocks configuration register 2 */ + +/* Register Addresses *******************************************************************************/ + +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_CIR (STM32_RCC_BASE+STM32_RCC_CIR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1LPENR (STM32_RCC_BASE+STM32_RCC_AHB1LPENR_OFFSET) +#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE+STM32_RCC_AHB2LPENR_OFFSET) +#define STM32_RCC_AHB3LPENR (STM32_RCC_BASE+STM32_RCC_AHB3LPENR_OFFSET) +#define STM32_RCC_APB1LPENR (STM32_RCC_BASE+STM32_RCC_APB1LPENR_OFFSET) +#define STM32_RCC_APB2LPENR (STM32_RCC_BASE+STM32_RCC_APB2LPENR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_SSCGR (STM32_RCC_BASE+STM32_RCC_SSCGR_OFFSET) +#define STM32_RCC_PLLI2SCFGR (STM32_RCC_BASE+STM32_RCC_PLLI2SCFGR_OFFSET) +#define STM32_RCC_PLLSAICFGR (STM32_RCC_BASE+STM32_RCC_PLLSAICFGR_OFFSET) +#define STM32_RCC_DCKCFGR1 (STM32_RCC_BASE+STM32_RCC_DCKCFGR1_OFFSET) +#define STM32_RCC_DCKCFGR2 (STM32_RCC_BASE+STM32_RCC_DCKCFGR2_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ + +/* Clock control register */ + +#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */ +#define RCC_CR_HSIRDY (1 << 1) /* Bit 1: Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM_SHIFT (3) /* Bits 7-3: Internal High Speed clock trimming */ +#define RCC_CR_HSITRIM_MASK (0x1f << RCC_CR_HSITRIM_SHIFT) +#define RCC_CR_HSICAL_SHIFT (8) /* Bits 15-8: Internal High Speed clock Calibration */ +#define RCC_CR_HSICAL_MASK (0xff << RCC_CR_HSICAL_SHIFT) +#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */ +#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready flag */ +#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */ +#define RCC_CR_CSSON (1 << 19) /* Bit 19: Clock Security System enable */ +#define RCC_CR_PLLON (1 << 24) /* Bit 24: PLL enable */ +#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: PLL clock ready flag */ +#define RCC_CR_PLLI2SON (1 << 26) /* Bit 26: PLLI2S enable */ +#define RCC_CR_PLLI2SRDY (1 << 27) /* Bit 27: PLLI2S clock ready flag */ +#define RCC_CR_PLLSAION (1 << 28) /* Bit 28: PLLSAI enable */ +#define RCC_CR_PLLSAIRDY (1 << 29) /* Bit 29: PLLSAI clock ready flag */ + +/* PLL configuration register */ + +#define RCC_PLLCFG_PLLM_SHIFT (0) /* Bits 0-5: Main PLL (PLL) and audio PLL (PLLI2S) + * input clock divider */ +#define RCC_PLLCFG_PLLM_MASK (0x3f << RCC_PLLCFG_PLLM_SHIFT) +# define RCC_PLLCFG_PLLM(n) ((n) << RCC_PLLCFG_PLLM_SHIFT) /* n = 2..63 */ +#define RCC_PLLCFG_PLLN_SHIFT (6) /* Bits 6-14: Main PLL (PLL) VCO multiplier */ +#define RCC_PLLCFG_PLLN_MASK (0x1ff << RCC_PLLCFG_PLLN_SHIFT) +# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 2..432 */ +#define RCC_PLLCFG_PLLP_SHIFT (16) /* Bits 16-17: Main PLL (PLL) main system clock divider */ +#define RCC_PLLCFG_PLLP_MASK (3 << RCC_PLLCFG_PLLP_SHIFT) +# define RCC_PLLCFG_PLLP(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLP_SHIFT) /* n=2,4,6,8 */ +# define RCC_PLLCFG_PLLP_2 (0 << RCC_PLLCFG_PLLP_SHIFT) /* 00: PLLP = 2 */ +# define RCC_PLLCFG_PLLP_4 (1 << RCC_PLLCFG_PLLP_SHIFT) /* 01: PLLP = 4 */ +# define RCC_PLLCFG_PLLP_6 (2 << RCC_PLLCFG_PLLP_SHIFT) /* 10: PLLP = 6 */ +# define RCC_PLLCFG_PLLP_8 (3 << RCC_PLLCFG_PLLP_SHIFT) /* 11: PLLP = 8 */ +#define RCC_PLLCFG_PLLSRC (1 << 22) /* Bit 22: Main PLL(PLL) and audio PLL (PLLI2S) + * entry clock source */ +# define RCC_PLLCFG_PLLSRC_HSI (0) +# define RCC_PLLCFG_PLLSRC_HSE RCC_PLLCFG_PLLSRC +#define RCC_PLLCFG_PLLQ_SHIFT (24) /* Bits 24-27: Main PLL (PLL) divider + * (USB OTG FS, SDIO and RNG clocks) */ +#define RCC_PLLCFG_PLLQ_MASK (15 << RCC_PLLCFG_PLLQ_SHIFT) +# define RCC_PLLCFG_PLLQ(n) ((n) << RCC_PLLCFG_PLLQ_SHIFT) /* n=2..15 */ + +#define RCC_PLLCFG_RESET (0x24003010) /* PLLCFG reset value */ + +/* Clock configuration register */ + +#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-1: System clock Switch */ +#define RCC_CFGR_SW_MASK (3 << RCC_CFGR_SW_SHIFT) +# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */ +# define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */ +# define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */ +#define RCC_CFGR_SWS_SHIFT (2) /* Bits 2-3: System Clock Switch Status */ +#define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT) +# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */ +# define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */ +# define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */ +#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 4-7: AHB prescaler */ +#define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT) +# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ +# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ +# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ +# define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ +# define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ +# define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ +# define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ +# define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ +# define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ +#define RCC_CFGR_PPRE1_SHIFT (10) /* Bits 10-12: APB Low speed prescaler (APB1) */ +#define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT) +# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */ +# define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */ +# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */ +# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */ +# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */ +#define RCC_CFGR_PPRE2_SHIFT (13) /* Bits 13-15: APB High speed prescaler (APB2) */ +#define RCC_CFGR_PPRE2_MASK (7 << RCC_CFGR_PPRE2_SHIFT) +# define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */ +# define RCC_CFGR_PPRE2_HCLKd2 (4 << RCC_CFGR_PPRE2_SHIFT) /* 100: HCLK divided by 2 */ +# define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */ +# define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */ +# define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */ +#define RCC_CFGR_RTCPRE_SHIFT (16) /* Bits 16-20: APB High speed prescaler (APB2) */ +#define RCC_CFGR_RTCPRE_MASK (31 << RCC_CFGR_RTCPRE_SHIFT) +# define RCC_CFGR_RTCPRE(n) ((n) << RCC_CFGR_RTCPRE_SHIFT) /* HSE/n, n=1..31 */ +#define RCC_CFGR_MCO1_SHIFT (21) /* Bits 21-22: Microcontroller Clock Output */ +#define RCC_CFGR_MCO1_MASK (3 << RCC_CFGR_MCO1_SHIFT) +# define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 00: HSI clock selected */ +# define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 01: LSE oscillator selected */ +# define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 10: HSE oscillator clock selected */ +# define RCC_CFGR_MCO1_PLL (3 << RCC_CFGR_MCO1_SHIFT) /* 11: PLL clock selected */ +#define RCC_CFGR_I2SSRC (1 << 23) /* Bit 23: I2S clock selection */ +#define RCC_CFGR_MCO1PRE_SHIFT (24) /* Bits 24-26: MCO1 prescaler */ +#define RCC_CFGR_MCO1PRE_MASK (7 << RCC_CFGR_MCO1PRE_SHIFT) +# define RCC_CFGR_MCO1PRE_NONE (0 << RCC_CFGR_MCO1PRE_SHIFT) /* 0xx: no division */ +# define RCC_CFGR_MCO1PRE_DIV2 (4 << RCC_CFGR_MCO1PRE_SHIFT) /* 100: division by 2 */ +# define RCC_CFGR_MCO1PRE_DIV3 (5 << RCC_CFGR_MCO1PRE_SHIFT) /* 101: division by 3 */ +# define RCC_CFGR_MCO1PRE_DIV4 (6 << RCC_CFGR_MCO1PRE_SHIFT) /* 110: division by 4 */ +# define RCC_CFGR_MCO1PRE_DIV5 (7 << RCC_CFGR_MCO1PRE_SHIFT) /* 111: division by 5 */ +#define RCC_CFGR_MCO2PRE_SHIFT (27) /* Bits 27-29: MCO2 prescaler */ +#define RCC_CFGR_MCO2PRE_MASK (7 << RCC_CFGR_MCO2PRE_SHIFT) +# define RCC_CFGR_MCO2PRE_NONE (0 << RCC_CFGR_MCO2PRE_SHIFT) /* 0xx: no division */ +# define RCC_CFGR_MCO2PRE_DIV2 (4 << RCC_CFGR_MCO2PRE_SHIFT) /* 100: division by 2 */ +# define RCC_CFGR_MCO2PRE_DIV3 (5 << RCC_CFGR_MCO2PRE_SHIFT) /* 101: division by 3 */ +# define RCC_CFGR_MCO2PRE_DIV4 (6 << RCC_CFGR_MCO2PRE_SHIFT) /* 110: division by 4 */ +# define RCC_CFGR_MCO2PRE_DIV5 (7 << RCC_CFGR_MCO2PRE_SHIFT) /* 111: division by 5 */ +#define RCC_CFGR_MCO2_SHIFT (30) /* Bits 30-31: Microcontroller clock output 2 */ +#define RCC_CFGR_MCO2_MASK (3 << RCC_CFGR_MCO2_SHIFT) +# define RCC_CFGR_MCO2_SYSCLK (0 << RCC_CFGR_MCO2_SHIFT) /* 00: System clock (SYSCLK) selected */ +# define RCC_CFGR_MCO2_PLLI2S (1 << RCC_CFGR_MCO2_SHIFT) /* 01: PLLI2S clock selected */ +# define RCC_CFGR_MCO2_HSE (2 << RCC_CFGR_MCO2_SHIFT) /* 10: HSE oscillator clock selected */ +# define RCC_CFGR_MCO2_PLL (3 << RCC_CFGR_MCO2_SHIFT) /* 11: PLL clock selected */ + +/* Clock interrupt register */ + +#define RCC_CIR_LSIRDYF (1 << 0) /* Bit 0: LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF (1 << 1) /* Bit 1: LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF (1 << 2) /* Bit 2: HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF (1 << 3) /* Bit 3: HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF (1 << 4) /* Bit 4: PLL Ready Interrupt flag */ +#define RCC_CIR_PLLI2SRDYF (1 << 5) /* Bit 5: PLLI2S Ready Interrupt flag */ +#define RCC_CIR_PLLSAIRDYF (1 << 6) /* Bit 6: PLLSAI Ready Interrupt flag */ +#define RCC_CIR_CSSF (1 << 7) /* Bit 7: Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE (1 << 8) /* Bit 8: LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE (1 << 9) /* Bit 9: LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE (1 << 10) /* Bit 10: HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE (1 << 11) /* Bit 11: HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE (1 << 12) /* Bit 12: PLL Ready Interrupt Enable */ +#define RCC_CIR_PLLI2SRDYIE (1 << 13) /* Bit 13: PLLI2S Ready Interrupt enable */ +#define RCC_CIR_PLLSAIRDYIE (1 << 14) /* Bit 14: PLLSAI Ready Interrupt enable */ +#define RCC_CIR_LSIRDYC (1 << 16) /* Bit 16: LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC (1 << 17) /* Bit 17: LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC (1 << 18) /* Bit 18: HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC (1 << 19) /* Bit 19: HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC (1 << 20) /* Bit 20: PLL Ready Interrupt Clear */ +#define RCC_CIR_PLLI2SRDYC (1 << 21) /* Bit 21: PLLI2S Ready Interrupt clear */ +#define RCC_CIR_PLLSAIRDYC (1 << 22) /* Bit 22: PLLSAI Ready Interrupt clear */ +#define RCC_CIR_CSSC (1 << 23) /* Bit 23: Clock Security System Interrupt Clear */ + +/* AHB1 peripheral reset register */ + +#define RCC_AHB1RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */ +#define RCC_AHB1RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */ +#define RCC_AHB1RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */ +#define RCC_AHB1RSTR_GPIODRST (1 << 3) /* Bit 3: IO port D reset */ +#define RCC_AHB1RSTR_GPIOERST (1 << 4) /* Bit 4: IO port E reset */ +#define RCC_AHB1RSTR_GPIOFRST (1 << 5) /* Bit 5: IO port F reset */ +#define RCC_AHB1RSTR_GPIOGRST (1 << 6) /* Bit 6: IO port G reset */ +#define RCC_AHB1RSTR_GPIOHRST (1 << 7) /* Bit 7: IO port H reset */ +#define RCC_AHB1RSTR_GPIOIRST (1 << 8) /* Bit 8: IO port I reset */ +#define RCC_AHB1RSTR_CRCRST (1 << 12) /* Bit 12 CRC reset */ +#define RCC_AHB1RSTR_DMA1RST (1 << 21) /* Bit 21: DMA1 reset */ +#define RCC_AHB1RSTR_DMA2RST (1 << 22) /* Bit 22: DMA2 reset */ +#define RCC_AHB1RSTR_DMA2DRST (1 << 23) /* Bit 23: DMA2D reset */ +#define RCC_AHB1RSTR_OTGHSRST (1 << 29) /* Bit 29: USB OTG HS module reset */ + +/* AHB2 peripheral reset register */ + +#define RCC_AHB2RSTR_CRYPRST (1 << 4) /* Bit 4: Cryptographic module reset */ +#define RCC_AHB2RSTR_RNGRST (1 << 6) /* Bit 6: Random number generator module reset */ +#define RCC_AHB2RSTR_OTGFSRST (1 << 7) /* Bit 7: USB OTG FS module reset */ + +/* AHB3 peripheral reset register */ + +#define RCC_AHB3RSTR_FMCRST (1 << 0) /* Bit 0: Flexible static memory controller module reset */ +#define RCC_AHB3RSTR_QSPIRST (1 << 1) /* Bit 1: Quad SPI memory controller reset */ + +/* APB1 Peripheral reset register */ + +#define RCC_APB1RSTR_TIM2RST (1 << 0) /* Bit 0: TIM2 reset */ +#define RCC_APB1RSTR_TIM3RST (1 << 1) /* Bit 1: TIM3 reset */ +#define RCC_APB1RSTR_TIM4RST (1 << 2) /* Bit 2: TIM4 reset */ +#define RCC_APB1RSTR_TIM5RST (1 << 3) /* Bit 3: TIM5 reset */ +#define RCC_APB1RSTR_TIM6RST (1 << 4) /* Bit 4: TIM6 reset */ +#define RCC_APB1RSTR_TIM7RST (1 << 5) /* Bit 5: TIM7 reset */ +#define RCC_APB1RSTR_TIM12RST (1 << 6) /* Bit 6: TIM12 reset */ +#define RCC_APB1RSTR_TIM13RST (1 << 7) /* Bit 7: TIM13 reset */ +#define RCC_APB1RSTR_TIM14RST (1 << 8) /* Bit 8: TIM14 reset */ +#define RCC_APB1RSTR_LPTIM1RST (1 << 9) /* Bit 9: LPTIM1 reset */ +#define RCC_APB1RSTR_WWDGRST (1 << 11) /* Bit 11: Window watchdog reset */ +#define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI 2 reset */ +#define RCC_APB1RSTR_SPI3RST (1 << 15) /* Bit 15: SPI 3 reset */ +#define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */ +#define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */ +#define RCC_APB1RSTR_UART4RST (1 << 19) /* Bit 19: UART 4 reset */ +#define RCC_APB1RSTR_UART5RST (1 << 20) /* Bit 20: UART 5 reset */ +#define RCC_APB1RSTR_I2C1RST (1 << 21) /* Bit 21: I2C 1 reset */ +#define RCC_APB1RSTR_I2C2RST (1 << 22) /* Bit 22: I2C 2 reset */ +#define RCC_APB1RSTR_I2C3RST (1 << 23) /* Bit 23: I2C 3 reset */ +#define RCC_APB1RSTR_CAN1RST (1 << 25) /* Bit 25: CAN1 reset */ +#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */ +#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC reset */ +#define RCC_APB1RSTR_UART7RST (1 << 30) /* Bit 30: UART 7 reset */ +#define RCC_APB1RSTR_UART8RST (1 << 31) /* Bit 31: UART 8 reset */ + +/* APB2 Peripheral reset register */ + +#define RCC_APB2RSTR_TIM1RST (1 << 0) /* Bit 0: TIM1 reset */ +#define RCC_APB2RSTR_TIM8RST (1 << 1) /* Bit 1: TIM8 reset */ +#define RCC_APB2RSTR_USART1RST (1 << 4) /* Bit 4: USART1 reset */ +#define RCC_APB2RSTR_USART6RST (1 << 5) /* Bit 5: USART6 reset */ +#define RCC_APB2RSTR_SDMMC2RST (1 << 7) /* Bit 7: SDMMC2 reset */ +#define RCC_APB2RSTR_ADCRST (1 << 8) /* Bit 8: ADC interface reset (common to all ADCs) */ +#define RCC_APB2RSTR_SDMMC1RST (1 << 11) /* Bit 11: SDMMC1 reset */ +#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */ +#define RCC_APB2RSTR_SPI4RST (1 << 13) /* Bit 13: SPI4 reset */ +#define RCC_APB2RSTR_SYSCFGRST (1 << 14) /* Bit 14: System configuration controller reset */ +#define RCC_APB2RSTR_TIM9RST (1 << 16) /* Bit 16: TIM9 reset */ +#define RCC_APB2RSTR_TIM10RST (1 << 17) /* Bit 17: TIM10 reset */ +#define RCC_APB2RSTR_TIM11RST (1 << 18) /* Bit 18: TIM11 reset */ +#define RCC_APB2RSTR_SPI5RST (1 << 20) /* Bit 20: SPI 5 reset */ +#define RCC_APB2RSTR_SAI1RST (1 << 22) /* Bit 22: SAI 1 reset */ +#define RCC_APB2RSTR_SAI2RST (1 << 23) /* Bit 23: SAI 2 reset */ +#define RCC_APB2RSTR_OTGPHYCRST (1 << 31) /* Bit 31: OTGPHYC reset */ + +/* AHB1 Peripheral Clock enable register */ + +#define RCC_AHB1ENR_GPIOEN(n) (1 << (n)) +#define RCC_AHB1ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A clock enable */ +#define RCC_AHB1ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B clock enable */ +#define RCC_AHB1ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C clock enable */ +#define RCC_AHB1ENR_GPIODEN (1 << 3) /* Bit 3: IO port D clock enable */ +#define RCC_AHB1ENR_GPIOEEN (1 << 4) /* Bit 4: IO port E clock enable */ +#define RCC_AHB1ENR_GPIOFEN (1 << 5) /* Bit 5: IO port F clock enable */ +#define RCC_AHB1ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G clock enable */ +#define RCC_AHB1ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H clock enable */ +#define RCC_AHB1ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I clock enable */ +#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */ +#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable */ +#define RCC_AHB1ENR_DTCMRAMEN (1 << 20) /* Bit 20: DTCM RAM clock enable */ +#define RCC_AHB1ENR_DMA1EN (1 << 21) /* Bit 21: DMA1 clock enable */ +#define RCC_AHB1ENR_DMA2EN (1 << 22) /* Bit 22: DMA2 clock enable */ +#define RCC_AHB1ENR_OTGHSEN (1 << 29) /* Bit 29: USB OTG HS clock enable */ +#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable */ + +/* AHB2 Peripheral Clock enable register */ + +#define RCC_AHB2ENR_CRYPEN (1 << 4) /* Bit 4: Cryptographic modules clock enable */ +#define RCC_AHB2ENR_RNGEN (1 << 6) /* Bit 6: Random number generator clock enable */ +#define RCC_AHB2ENR_OTGFSEN (1 << 7) /* Bit 7: USB OTG FS clock enable */ + +/* AHB3 Peripheral Clock enable register */ + +#define RCC_AHB3ENR_FMCEN (1 << 0) /* Bit 0: Flexible static memory controller module clock enable */ +#define RCC_AHB3ENR_QSPIEN (1 << 1) /* Bit 1: Quad SPI memory controller clock enable */ + +/* APB1 Peripheral Clock enable register */ + +#define RCC_APB1ENR_TIM2EN (1 << 0) /* Bit 0: TIM 2 clock enable */ +#define RCC_APB1ENR_TIM3EN (1 << 1) /* Bit 1: TIM 3 clock enable */ +#define RCC_APB1ENR_TIM4EN (1 << 2) /* Bit 2: TIM 4 clock enable */ +#define RCC_APB1ENR_TIM5EN (1 << 3) /* Bit 3: TIM 5 clock enable */ +#define RCC_APB1ENR_TIM6EN (1 << 4) /* Bit 4: TIM 6 clock enable */ +#define RCC_APB1ENR_TIM7EN (1 << 5) /* Bit 5: TIM 7 clock enable */ +#define RCC_APB1ENR_TIM12EN (1 << 6) /* Bit 6: TIM 12 clock enable */ +#define RCC_APB1ENR_TIM13EN (1 << 7) /* Bit 7: TIM 13 clock enable */ +#define RCC_APB1ENR_TIM14EN (1 << 8) /* Bit 8: TIM 14 clock enable */ +#define RCC_APB1ENR_LPTIM1EN (1 << 9) /* Bit 9: LPTIM 1 clock enable */ +#define RCC_APB1ENR_RTCAPBEN (1 << 10) /* Bit 10: RTCAPB clock enable */ +#define RCC_APB1ENR_WWDGEN (1 << 11) /* Bit 11: Window watchdog clock enable */ +#define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI 2 clock enable */ +#define RCC_APB1ENR_SPI3EN (1 << 15) /* Bit 15: SPI 3 clock enable */ +#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */ +#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART 3 clock enable */ +#define RCC_APB1ENR_UART4EN (1 << 19) /* Bit 19: UART 4 clock enable */ +#define RCC_APB1ENR_UART5EN (1 << 20) /* Bit 20: UART 5 clock enable */ +#define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C 1 clock enable */ +#define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C 2 clock enable */ +#define RCC_APB1ENR_I2C3EN (1 << 23) /* Bit 23: I2C 3 clock enable */ +#define RCC_APB1ENR_CAN1EN (1 << 25) /* Bit 25: CAN 1 clock enable */ +#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */ +#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */ +#define RCC_APB1ENR_UART7EN (1 << 30) /* Bit 30: UART7 clock enable */ +#define RCC_APB1ENR_UART8EN (1 << 31) /* Bit 31: UART8 clock enable */ + +/* APB2 Peripheral Clock enable register */ + +#define RCC_APB2ENR_TIM1EN (1 << 0) /* Bit 0: TIM 1 clock enable */ +#define RCC_APB2ENR_TIM8EN (1 << 1) /* Bit 1: TIM 8 clock enable */ +#define RCC_APB2ENR_USART1EN (1 << 4) /* Bit 4: USART 1 clock enable */ +#define RCC_APB2ENR_USART6EN (1 << 5) /* Bit 5: USART 6 clock enable */ +#define RCC_APB2ENR_SDMMC2EN (1 << 7) /* Bit 7: SDMMC 2 clock enable */ +#define RCC_APB2ENR_ADC1EN (1 << 8) /* Bit 8: ADC 1 clock enable */ +#define RCC_APB2ENR_ADC2EN (1 << 9) /* Bit 9: ADC 2 clock enable */ +#define RCC_APB2ENR_ADC3EN (1 << 10) /* Bit 10: ADC 3 clock enable */ +#define RCC_APB2ENR_SDMMC1EN (1 << 11) /* Bit 11: SDMMC 1 clock enable */ +#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI 1 clock enable */ +#define RCC_APB2ENR_SPI4EN (1 << 13) /* Bit 13: SPI 4 clock enable */ +#define RCC_APB2ENR_SYSCFGEN (1 << 14) /* Bit 14: System configuration controller clock enable */ +#define RCC_APB2ENR_TIM9EN (1 << 16) /* Bit 16: TIM 9 clock enable */ +#define RCC_APB2ENR_TIM10EN (1 << 17) /* Bit 17: TIM1 0 clock enable */ +#define RCC_APB2ENR_TIM11EN (1 << 18) /* Bit 18: TIM 11 clock enable */ +#define RCC_APB2ENR_SPI5EN (1 << 20) /* Bit 20: SPI 5 clock enable */ +#define RCC_APB2ENR_SAI1EN (1 << 22) /* Bit 22: SAI 1 clock enable */ +#define RCC_APB2ENR_SAI2EN (1 << 23) /* Bit 23: SAI 2 clock enable */ +#define RCC_APB2ENR_OTGPHYCEN (1 << 31) /* Bit 31: OTGPHYC enable */ + +/* RCC AHB1 low power mode peripheral clock enable register */ + +#define RCC_AHB1LPENR_GPIOLPEN(n) (1 << (n)) +#define RCC_AHB1LPENR_GPIOALPEN (1 << 0) /* Bit 0: IO port A clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOBLPEN (1 << 1) /* Bit 1: IO port B clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOCLPEN (1 << 2) /* Bit 2: IO port C clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIODLPEN (1 << 3) /* Bit 3: IO port D clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOELPEN (1 << 4) /* Bit 4: IO port E clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOFLPEN (1 << 5) /* Bit 5: IO port F clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOGLPEN (1 << 6) /* Bit 6: IO port G clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOHLPEN (1 << 7) /* Bit 7: IO port H clock enable during Sleep mode */ +#define RCC_AHB1LPENR_GPIOILPEN (1 << 8) /* Bit 8: IO port I clock enable during Sleep mode */ +#define RCC_AHB1LPENR_CRCLPEN (1 << 12) /* Bit 12: CRC clock enable during Sleep mode */ +#define RCC_AHB1LPENR_AXILPEN (1 << 13) /* Bit 12: AXI to AHB bridge clock enable during Sleep mode */ +#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) /* Bit 15: Flash interface clock enable during Sleep mode */ +#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) /* Bit 16: SRAM 1 interface clock enable during Sleep mode */ +#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) /* Bit 17: SRAM 2 interface clock enable during Sleep mode */ +#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable during Sleep mode */ +#define RCC_AHB1LPENR_DTCMLPEN (1 << 20) /* Bit 20: DTCM RAM clock enable during Sleep mode */ +#define RCC_AHB1LPENR_DMA1LPEN (1 << 21) /* Bit 21: DMA1 clock enable during Sleep mode */ +#define RCC_AHB1LPENR_DMA2LPEN (1 << 22) /* Bit 22: DMA2 clock enable during Sleep mode */ +#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) /* Bit 29: USB OTG HS clock enable during Sleep mode */ +#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable during Sleep mode */ + +/* RCC AHB2 low power mode peripheral clock enable register */ + +#define RCC_AHB2LPENR_CRYPLPEN (1 << 4) /* Bit 4: Cryptographic modules clock enable during Sleep mode */ +#define RCC_AHB2LPENR_RNGLPEN (1 << 6) /* Bit 6: Random number generator clock enable during Sleep mode */ +#define RCC_AHB2LPENR_OTGFLPSEN (1 << 7) /* Bit 7: USB OTG FS clock enable during Sleep mode */ + +/* RCC AHB3 low power mode peripheral clock enable register */ + +#define RCC_AHB3LPENR_FSMLPEN (1 << 0) /* Bit 0: Flexible static memory controller module clock + * enable during Sleep mode */ +#define RCC_AHB3LPENR_QSPILPEN (1 << 1) /* Bit 1: Quad SPI memory controller clock + * enable during Sleep mode */ + +/* RCC APB1 low power mode peripheral clock enable register */ + +#define RCC_APB1LPENR_TIM2LPEN (1 << 0) /* Bit 0: TIM 2 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM3LPEN (1 << 1) /* Bit 1: TIM 3 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM4LPEN (1 << 2) /* Bit 2: TIM 4 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM5LPEN (1 << 3) /* Bit 3: TIM 5 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM6LPEN (1 << 4) /* Bit 4: TIM 6 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM7LPEN (1 << 5) /* Bit 5: TIM 7 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM12LPEN (1 << 6) /* Bit 6: TIM 12 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM13LPEN (1 << 7) /* Bit 7: TIM 13 clock enable during Sleep mode */ +#define RCC_APB1LPENR_TIM14LPEN (1 << 8) /* Bit 8: TIM 14 clock enable during Sleep mode */ +#define RCC_APB1LPENR_LPTIM1LPEN (1 << 9) /* Bit 9: LPTIM 1 clock enable during Sleep mode */ +#define RCC_APB1LPENR_RTCAPBEN (1 << 10) /* Bit 10: RTCAPB clock enable during Sleep mode */ +#define RCC_APB1LPENR_WWDGLPEN (1 << 11) /* Bit 11: Window watchdog clock enable during Sleep mode */ +#define RCC_APB1LPENR_SPI2LPEN (1 << 14) /* Bit 14: SPI 2 clock enable during Sleep mode */ +#define RCC_APB1LPENR_SPI3LPEN (1 << 15) /* Bit 15: SPI 3 clock enable during Sleep mode */ +#define RCC_APB1LPENR_USART2LPEN (1 << 17) /* Bit 17: USART 2 clock enable during Sleep mode */ +#define RCC_APB1LPENR_USART3LPEN (1 << 18) /* Bit 18: USART 3 clock enable during Sleep mode */ +#define RCC_APB1LPENR_UART4LPEN (1 << 19) /* Bit 19: UART 4 clock enable during Sleep mode */ +#define RCC_APB1LPENR_UART5LPEN (1 << 20) /* Bit 20: UART 5 clock enable during Sleep mode */ +#define RCC_APB1LPENR_I2C1LPEN (1 << 21) /* Bit 21: I2C 1 clock enable during Sleep mode */ +#define RCC_APB1LPENR_I2C2LPEN (1 << 22) /* Bit 22: I2C 2 clock enable during Sleep mode */ +#define RCC_APB1LPENR_I2C3LPEN (1 << 23) /* Bit 23: I2C 3 clock enable during Sleep mode */ +#define RCC_APB1LPENR_CAN1LPEN (1 << 25) /* Bit 25: CAN 1 clock enable during Sleep mode */ +#define RCC_APB1LPENR_PWRLPEN (1 << 28) /* Bit 28: Power interface clock enable during Sleep mode */ +#define RCC_APB1LPENR_DACLPEN (1 << 29) /* Bit 29: DAC interface clock enable during Sleep mode */ +#define RCC_APB1LPENR_UART7LPEN (1 << 30) /* Bit 30: UART 7 clock enable during Sleep mode */ +#define RCC_APB1LPENR_UART8LPEN (1 << 31) /* Bit 31: UART 8 clock enable during Sleep mode */ + +/* RCC APB2 low power mode peripheral clock enable register */ + +#define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* Bit 0: TIM 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_TIM8LPEN (1 << 1) /* Bit 1: TIM 8 clock enable during Sleep mode */ +#define RCC_APB2LPENR_USART1LPEN (1 << 4) /* Bit 4: USART 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_USART6LPEN (1 << 5) /* Bit 5: USART 6 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SDMMC2LPEN (1 << 7) /* Bit 7: SDMMC 2 clock enable during Sleep mode */ +#define RCC_APB2LPENR_ADC1LPEN (1 << 8) /* Bit 8: ADC 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_ADC2LPEN (1 << 9) /* Bit 9: ADC 2 clock enable during Sleep mode */ +#define RCC_APB2LPENR_ADC3LPEN (1 << 10) /* Bit 10: ADC 3 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SDMMC1LPEN (1 << 11) /* Bit 11: SDMMC 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* Bit 12: SPI 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* Bit 13: SPI 4 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) /* Bit 14: System configuration controller clock enable during Sleep mode */ +#define RCC_APB2LPENR_TIM9LPEN (1 << 16) /* Bit 16: TIM 9 clock enable during Sleep mode */ +#define RCC_APB2LPENR_TIM10LPEN (1 << 17) /* Bit 17: TIM 10 clock enable during Sleep mode */ +#define RCC_APB2LPENR_TIM11LPEN (1 << 18) /* Bit 18: TIM 11 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SPI5LPEN (1 << 20) /* Bit 20: SPI 5 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SAI1LPEN (1 << 22) /* Bit 22: SAI 1 clock enable during Sleep mode */ +#define RCC_APB2LPENR_SAI2LPEN (1 << 23) /* Bit 23: SAI 2 clock enable during Sleep mode */ + +/* Backup domain control register */ + +#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ +#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 4:3: LSE oscillator Drive selection */ +#define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT) +# define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Low driving capability */ +# define RCC_BDCR_LSEDRV_MEDHI (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium high driving capability */ +# define RCC_BDCR_LSEDRV_MEDLO (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium low driving capability */ +# define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: High driving capability */ +#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ +#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) +# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ +# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */ +#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ +#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ + +/* Control/status register */ + +#define RCC_CSR_LSION (1 << 0) /* Bit 0: Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY (1 << 1) /* Bit 1: Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF (1 << 24) /* Bit 24: Remove reset flag */ +#define RCC_CSR_BORRSTF (1 << 25) /* Bit 25: BOR reset flag */ +#define RCC_CSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */ +#define RCC_CSR_PORRSTF (1 << 27) /* Bit 27: POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF (1 << 28) /* Bit 28: Software Reset flag */ +#define RCC_CSR_IWDGRSTF (1 << 29) /* Bit 29: Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */ + +/* Spread spectrum clock generation register */ + +#define RCC_SSCGR_MODPER_SHIFT (0) /* Bit 0-12: Modulation period */ +#define RCC_SSCGR_MODPER_MASK (0x1fff << RCC_SSCGR_MODPER_SHIFT) +# define RCC_SSCGR_MODPER(n) ((n) << RCC_SSCGR_MODPER_SHIFT) +#define RCC_SSCGR_INCSTEP_SHIFT (13) /* Bit 13-27: Incrementation step */ +#define RCC_SSCGR_INCSTEP_MASK (0x7fff << RCC_SSCGR_INCSTEP_SHIFT) +# define RCC_SSCGR_INCSTEP(n) ((n) << RCC_SSCGR_INCSTEP_SHIFT) +#define RCC_SSCGR_SPREADSEL (1 << 30) /* Bit 30: Spread Select */ +#define RCC_SSCGR_SSCGEN (1 << 31) /* Bit 31: Spread spectrum modulation enable */ + +/* PLLI2S configuration register */ + +#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT (6) /* Bits 6-14: PLLI2S multiplication factor for VCO */ +#define RCC_PLLI2SCFGR_PLLI2SN_MASK (0x1ff << RCC_PLLI2SCFGR_PLLI2SN_SHIFT) +# define RCC_PLLI2SCFGR_PLLI2SN(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT) +#define RCC_PLLI2SCFGR_PLLI2SQ_SHIFT (24) /* Bits 24-27: PLLI2S division factor for SAIs clock */ +#define RCC_PLLI2SCFGR_PLLI2SQ_MASK (15 << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT) +# define RCC_PLLI2SCFGR_PLLI2SQ(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT) +#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT (28) /* Bits 28-30: PLLI2S division factor for I2S clocks */ +#define RCC_PLLI2SCFGR_PLLI2SR_MASK (7 << RCC_PLLI2SCFGR_PLLI2SR_SHIFT) +# define RCC_PLLI2SCFGR_PLLI2SR(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT) + +/* PLLSAI configuration register */ + +#define RCC_PLLSAICFGR_PLLSAIN_SHIFT (6) /* Bits 6-14: PLLSAI divider (N) for VCO */ +#define RCC_PLLSAICFGR_PLLSAIN_MASK (0x1ff << RCC_PLLSAICFGR_PLLSAIN_SHIFT) +# define RCC_PLLSAICFGR_PLLSAIN(n) ((n) << RCC_PLLSAICFGR_PLLSAIN_SHIFT) +#define RCC_PLLSAICFGR_PLLSAIP_SHIFT (16) /* Bits 16-17: PLLSAI division factor for 48MHz clock */ +#define RCC_PLLSAICFGR_PLLSAIP_MASK (3 << RCC_PLLSAICFGR_PLLSAIP_SHIFT) +# define RCC_PLLSAICFGR_PLLSAIP(n) ((((n)>>1)-1) << RCC_PLLSAICFGR_PLLSAIP_SHIFT) +#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT (24) /* Bits 24-27: PLLSAI division factor for SAI clock */ +#define RCC_PLLSAICFGR_PLLSAIQ_MASK (0x0F << RCC_PLLSAICFGR_PLLSAIQ_SHIFT) +# define RCC_PLLSAICFGR_PLLSAIQ(n) ((n) << RCC_PLLSAICFGR_PLLSAIQ_SHIFT) + +/* Dedicated clocks configuration register 1 */ + +#define RCC_DCKCFGR1_PLLI2SDIVQ_SHIFT (0) /* Bits 0-4: PLLI2S division factor for I2S clock */ +#define RCC_DCKCFGR1_PLLI2SDIVQ_MASK (0x1F << RCC_DCKCFGR1_PLLI2SDIVQ_SHIFT) +# define RCC_DCKCFGR1_PLLI2SDIVQ(n) ((n) << RCC_DCKCFGR1_PLLI2SDIVQ_SHIFT) +#define RCC_DCKCFGR1_PLLSAIDIVQ_SHIFT (8) /* Bits 8-12: PLLSAI division factor for SAI clock */ +#define RCC_DCKCFGR1_PLLSAIDIVQ_MASK (0x1F << RCC_DCKCFGR1_PLLSAIDIVQ_SHIFT) +# define RCC_DCKCFGR1_PLLSAIDIVQ(n) ((n) << RCC_DCKCFGR1_PLLSAIDIVQ_SHIFT) + +#define RCC_DCKCFGR1_SAI1SEL_SHIFT (20) /* Bits 20-21: SAI 1 clock source selection */ +#define RCC_DCKCFGR1_SAI1SEL_MASK (0x3 << RCC_DCKCFGR1_SAI1SEL_SHIFT) +# define RCC_DCKCFGR1_SAI1SEL(n) ((n) << RCC_DCKCFGR1_SAI1SEL_SHIFT) + +#define RCC_DCKCFGR1_SAI2SEL_SHIFT (22) /* Bits 22-23: SAI 2 clock source selection */ +#define RCC_DCKCFGR1_SAI2SEL_MASK (0x3 << RCC_DCKCFGR1_SAI2SEL_SHIFT) +# define RCC_DCKCFGR1_SAI2SEL(n) ((n) << RCC_DCKCFGR1_SAI2SEL_SHIFT) +#define RCC_DCKCFGR1_TIMPRESEL (1 << 24) /* Bit 24: Timer clock prescaler selection */ + +/* Dedicated clocks configuration register 2 */ + +#define RCC_DCKCFGR2_USART1SEL_SHIFT (0) /* Bits 0-1: USART 1 clock source selection */ +#define RCC_DCKCFGR2_USART1SEL_MASK (3 << RCC_DCKCFGR2_USART1SEL_SHIFT) +# define RCC_DCKCFGR2_USART1SEL_APB (0 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* APB2 clock (PCLK2) is selected as USART 1 clock */ +# define RCC_DCKCFGR2_USART1SEL_SYSCLK (1 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* System clock is selected as USART 1 clock */ +# define RCC_DCKCFGR2_USART1SEL_HSI (2 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* HSI clock is selected as USART 1 clock */ +# define RCC_DCKCFGR2_USART1SEL_LSE (3 << RCC_DCKCFGR2_USART1SEL_SHIFT) /* LSE clock is selected as USART 1 clock */ +#define RCC_DCKCFGR2_USART2SEL_SHIFT (2) /* Bits 2-3: USART 2 clock source selection */ +#define RCC_DCKCFGR2_USART2SEL_MASK (3 << RCC_DCKCFGR2_USART2SEL_SHIFT) +# define RCC_DCKCFGR2_USART2SEL_APB (0 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* APB1 clock (PCLK1) is selected as USART 2 clock */ +# define RCC_DCKCFGR2_USART2SEL_SYSCLK (1 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* System clock is selected as USART 2 clock */ +# define RCC_DCKCFGR2_USART2SEL_HSI (2 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* HSI clock is selected as USART 2 clock */ +# define RCC_DCKCFGR2_USART2SEL_LSE (3 << RCC_DCKCFGR2_USART2SEL_SHIFT) /* LSE clock is selected as USART 2 clock */ +#define RCC_DCKCFGR2_USART3SEL_SHIFT (4) /* Bits 4-5: USART 3 clock source selection */ +#define RCC_DCKCFGR2_USART3SEL_MASK (3 << RCC_DCKCFGR2_USART3SEL_SHIFT) +# define RCC_DCKCFGR2_USART3SEL_APB (0 << RCC_DCKCFGR2_USART3SEL_SHIFT) /* APB1 clock (PCLK1) is selected as USART 3 clock */ +# define RCC_DCKCFGR2_USART3SEL_SYSCLK (1 << RCC_DCKCFGR2_USART3SEL_SHIFT) /* System clock is selected as USART 3 clock */ +# define RCC_DCKCFGR2_USART3SEL_HSI (2 << RCC_DCKCFGR2_USART3SEL_SHIFT) /* HSI clock is selected as USART 3 clock */ +# define RCC_DCKCFGR2_USART3SEL_LSE (3 << RCC_DCKCFGR2_USART3SEL_SHIFT) /* LSE clock is selected as USART 3 clock */ +#define RCC_DCKCFGR2_UART4SEL_SHIFT (6) /* Bits 6-7: UART 4 clock source selection */ +#define RCC_DCKCFGR2_UART4SEL_MASK (3 << RCC_DCKCFGR2_UART4SEL_SHIFT) +# define RCC_DCKCFGR2_UART4SEL_APB (0 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 4 clock */ +# define RCC_DCKCFGR2_UART4SEL_SYSCLK (1 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* System clock is selected as UART 4 clock */ +# define RCC_DCKCFGR2_UART4SEL_HSI (2 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* HSI clock is selected as UART 4 clock */ +# define RCC_DCKCFGR2_UART4SEL_LSE (3 << RCC_DCKCFGR2_UART4SEL_SHIFT) /* LSE clock is selected as UART 4 clock */ +#define RCC_DCKCFGR2_UART5SEL_SHIFT (8) /* Bits 8-9: UART 5 clock source selection */ +#define RCC_DCKCFGR2_UART5SEL_MASK (3 << RCC_DCKCFGR2_UART5SEL_SHIFT) +# define RCC_DCKCFGR2_UART5SEL_APB (0 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 5 clock */ +# define RCC_DCKCFGR2_UART5SEL_SYSCLK (1 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* System clock is selected as UART 5 clock */ +# define RCC_DCKCFGR2_UART5SEL_HSI (2 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* HSI clock is selected as UART 5 clock */ +# define RCC_DCKCFGR2_UART5SEL_LSE (3 << RCC_DCKCFGR2_UART5SEL_SHIFT) /* LSE clock is selected as UART 5 clock */ +#define RCC_DCKCFGR2_USART6SEL_SHIFT (10) /* Bits 10-11: USART 6 clock source selection */ +#define RCC_DCKCFGR2_USART6SEL_MASK (3 << RCC_DCKCFGR2_USART6SEL_SHIFT) +# define RCC_DCKCFGR2_USART6SEL_APB (0 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* APB2 clock (PCLK2) is selected as USART 6 clock */ +# define RCC_DCKCFGR2_USART6SEL_SYSCLK (1 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* System clock is selected as USART 6 clock */ +# define RCC_DCKCFGR2_USART6SEL_HSI (2 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* HSI clock is selected as USART 6 clock */ +# define RCC_DCKCFGR2_USART6SEL_LSE (3 << RCC_DCKCFGR2_USART6SEL_SHIFT) /* LSE clock is selected as USART 6 clock */ +#define RCC_DCKCFGR2_UART7SEL_SHIFT (12) /* Bits 12-13: UART 7 clock source selection */ +#define RCC_DCKCFGR2_UART7SEL_MASK (3 << RCC_DCKCFGR2_UART7SEL_SHIFT) +# define RCC_DCKCFGR2_UART7SEL_APB (0 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 7 clock */ +# define RCC_DCKCFGR2_UART7SEL_SYSCLK (1 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* System clock is selected as UART 7 clock */ +# define RCC_DCKCFGR2_UART7SEL_HSI (2 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* HSI clock is selected as UART 7 clock */ +# define RCC_DCKCFGR2_UART7SEL_LSE (3 << RCC_DCKCFGR2_UART7SEL_SHIFT) /* LSE clock is selected as UART 7 clock */ +#define RCC_DCKCFGR2_UART8SEL_SHIFT (14) /* Bits 14-15: UART 8 clock source selection */ +#define RCC_DCKCFGR2_UART8SEL_MASK (3 << RCC_DCKCFGR2_UART8SEL_SHIFT) +# define RCC_DCKCFGR2_UART8SEL_APB (0 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* APB1 clock (PCLK1) is selected as UART 8 clock */ +# define RCC_DCKCFGR2_UART8SEL_SYSCLK (1 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* System clock is selected as UART 8 clock */ +# define RCC_DCKCFGR2_UART8SEL_HSI (2 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* HSI clock is selected as UART 8 clock */ +# define RCC_DCKCFGR2_UART8SEL_LSE (3 << RCC_DCKCFGR2_UART8SEL_SHIFT) /* LSE clock is selected as UART 8 clock */ +#define RCC_DCKCFGR2_I2C1SEL_SHIFT (16) /* Bits 16-17: I2C1 clock source selection */ +#define RCC_DCKCFGR2_I2C1SEL_MASK (3 << RCC_DCKCFGR2_I2C1SEL_SHIFT) +# define RCC_DCKCFGR2_I2C1SEL_APB (0 << RCC_DCKCFGR2_I2C1SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 1 clock */ +# define RCC_DCKCFGR2_I2C1SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C1SEL_SHIFT) /* System clock is selected as I2C 1 clock */ +# define RCC_DCKCFGR2_I2C1SEL_HSI (2 << RCC_DCKCFGR2_I2C1SEL_SHIFT) /* HSI clock is selected as I2C 1 clock */ +#define RCC_DCKCFGR2_I2C2SEL_SHIFT (18) /* Bits 18-19: I2C2 clock source selection */ +#define RCC_DCKCFGR2_I2C2SEL_MASK (3 << RCC_DCKCFGR2_I2C2SEL_SHIFT) +# define RCC_DCKCFGR2_I2C2SEL_APB (0 << RCC_DCKCFGR2_I2C2SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 2 clock */ +# define RCC_DCKCFGR2_I2C2SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C2SEL_SHIFT) /* System clock is selected as I2C 2 clock */ +# define RCC_DCKCFGR2_I2C2SEL_HSI (2 << RCC_DCKCFGR2_I2C2SEL_SHIFT) /* HSI clock is selected as I2C 2 clock */ +#define RCC_DCKCFGR2_I2C3SEL_SHIFT (20) /* Bits 20-21: I2C3 clock source selection */ +#define RCC_DCKCFGR2_I2C3SEL_MASK (3 << RCC_DCKCFGR2_I2C3SEL_SHIFT) +# define RCC_DCKCFGR2_I2C3SEL_APB (0 << RCC_DCKCFGR2_I2C3SEL_SHIFT) /* APB1 clock (PCLK1) is selected as I2C 3 clock */ +# define RCC_DCKCFGR2_I2C3SEL_SYSCLK (1 << RCC_DCKCFGR2_I2C3SEL_SHIFT) /* System clock is selected as I2C 3 clock */ +# define RCC_DCKCFGR2_I2C3SEL_HSI (2 << RCC_DCKCFGR2_I2C3SEL_SHIFT) /* HSI clock is selected as I2C 3 clock */ +#define RCC_DCKCFGR2_LPTIM1SEL_SHIFT (24) /* Bits 24-25: Low power timer 1 clock source selection */ +#define RCC_DCKCFGR2_LPTIM1SEL_MASK (3 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) +# define RCC_DCKCFGR2_LPTIM1SEL_APB (0 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* APB1 clock (PCLK1) is selected as LPTIM 1 clock */ +# define RCC_DCKCFGR2_LPTIM1SEL_SYSCLK (1 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* System clock is selected as LPTIM 1 clock */ +# define RCC_DCKCFGR2_LPTIM1SEL_HSI (2 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* HSI clock is selected as LPTIM 1 clock */ +# define RCC_DCKCFGR2_LPTIM1SEL_LSE (3 << RCC_DCKCFGR2_LPTIM1SEL_SHIFT) /* LSE clock is selected as LPTIM 1 clock */ +#define RCC_DCKCFGR2_CK48MSEL_SHIFT (27) /* Bit 27: 48MHz clock source selection */ +#define RCC_DCKCFGR2_CK48MSEL_MASK (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT) +# define RCC_DCKCFGR2_CK48MSEL_PLL (0 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /* 48MHz clock from PLL is selected */ +# define RCC_DCKCFGR2_CK48MSEL_PLLSAI (1 << RCC_DCKCFGR2_CK48MSEL_SHIFT) /*48MHz clock from PLLSAI is selected */ +#define RCC_DCKCFGR2_SDMMCSEL_SHIFT (28) /* Bit 28: SDMMC1 clock source selection */ +#define RCC_DCKCFGR2_SDMMCSEL_MASK (1 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) +# define RCC_DCKCFGR2_SDMMCSEL_48MHZ (0 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */ +# define RCC_DCKCFGR2_SDMMCSEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* System clock is selected as SDMMC clock */ +#define RCC_DCKCFGR2_SDMMC2SEL_SHIFT (29) /* Bit 29: SDMMC2 clock source selection */ +#define RCC_DCKCFGR2_SDMMC2SEL_MASK (1 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) +# define RCC_DCKCFGR2_SDMMC2SEL_48MHZ (0 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */ +# define RCC_DCKCFGR2_SDMMC2SEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* System clock is selected as SDMMC clock */ + +#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F74XX75XX_RCC_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_sdmmc.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_sdmmc.h new file mode 100644 index 0000000000000000000000000000000000000000..d6f3ad750a9aaef00934bea06e2c4e7002dff309 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_sdmmc.h @@ -0,0 +1,224 @@ + /* arch/arm/src/stm32f7/chip/stm32f72xx73xx_sdmmc.h + * + * Copyright (C) 2009, 2011-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SDMMC_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SDMMC_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_SDMMC_POWER_OFFSET 0x0000 /* SDMMC power control register */ +#define STM32_SDMMC_CLKCR_OFFSET 0x0004 /* SDMMC clock control register */ +#define STM32_SDMMC_ARG_OFFSET 0x0008 /* SDMMC argument register */ +#define STM32_SDMMC_CMD_OFFSET 0x000c /* SDMMC command register */ +#define STM32_SDMMC_RESPCMD_OFFSET 0x0010 /* SDMMC command response register */ +#define STM32_SDMMC_RESP_OFFSET(n) (0x0010+4*(n)) +#define STM32_SDMMC_RESP1_OFFSET 0x0014 /* SDMMC response 1 register */ +#define STM32_SDMMC_RESP2_OFFSET 0x0018 /* SDMMC response 2 register */ +#define STM32_SDMMC_RESP3_OFFSET 0x001c /* SDMMC response 3 register */ +#define STM32_SDMMC_RESP4_OFFSET 0x0020 /* SDMMC response 4 register */ +#define STM32_SDMMC_DTIMER_OFFSET 0x0024 /* SDMMC data timer register */ +#define STM32_SDMMC_DLEN_OFFSET 0x0028 /* SDMMC data length register */ +#define STM32_SDMMC_DCTRL_OFFSET 0x002c /* SDMMC data control register */ +#define STM32_SDMMC_DCOUNT_OFFSET 0x0030 /* SDMMC data counter register */ +#define STM32_SDMMC_STA_OFFSET 0x0034 /* SDMMC status register */ +#define STM32_SDMMC_ICR_OFFSET 0x0038 /* SDMMC interrupt clear register */ +#define STM32_SDMMC_MASK_OFFSET 0x003c /* SDMMC mask register */ +#define STM32_SDMMC_FIFOCNT_OFFSET 0x0048 /* SDMMC FIFO counter register */ +#define STM32_SDMMC_FIFO_OFFSET 0x0080 /* SDMMC data FIFO register */ + + +/* Register Bitfield Definitions ****************************************************/ + +#define STM32_SDMMC_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */ +#define STM32_SDMMC_POWER_PWRCTRL_MASK (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) +# define STM32_SDMMC_POWER_PWRCTRL_OFF (0 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */ +# define STM32_SDMMC_POWER_PWRCTRL_PWRUP (2 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */ +# define STM32_SDMMC_POWER_PWRCTRL_ON (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */ + +#define STM32_SDMMC_POWER_RESET (0) /* Reset value */ + +#define STM32_SDMMC_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */ +#define STM32_SDMMC_CLKCR_CLKDIV_MASK (0xff << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */ +#define STM32_SDMMC_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */ +#define STM32_SDMMC_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */ +#define STM32_SDMMC_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */ +#define STM32_SDMMC_CLKCR_WIDBUS_MASK (3 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) +# define STM32_SDMMC_CLKCR_WIDBUS_D1 (0 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 00: Default (STM32_SDMMC_D0) */ +# define STM32_SDMMC_CLKCR_WIDBUS_D4 (1 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (STM32_SDMMC_D[3:0]) */ +# define STM32_SDMMC_CLKCR_WIDBUS_D8 (2 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (STM32_SDMMC_D[7:0]) */ +#define STM32_SDMMC_CLKCR_NEGEDGE (1 << 13) /* Bit 13: STM32_SDMMC_CK dephasing selection bit */ +#define STM32_SDMMC_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */ + +#define STM32_SDMMC_CLKCR_RESET (0) /* Reset value */ + +#define STM32_SDMMC_ARG_RESET (0) /* Reset value */ + +#define STM32_SDMMC_CMD_CMDINDEX_SHIFT (0) +#define STM32_SDMMC_CMD_CMDINDEX_MASK (0x3f << STM32_SDMMC_CMD_CMDINDEX_SHIFT) +#define STM32_SDMMC_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */ +#define STM32_SDMMC_CMD_WAITRESP_MASK (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT) +# define STM32_SDMMC_CMD_NORESPONSE (0 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 00/10: No response */ +# define STM32_SDMMC_CMD_SHORTRESPONSE (1 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response */ +# define STM32_SDMMC_CMD_LONGRESPONSE (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 11: Long response */ +#define STM32_SDMMC_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */ +#define STM32_SDMMC_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */ +#define STM32_SDMMC_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */ +#define STM32_SDMMC_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */ +#define STM32_SDMMC_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */ +#define STM32_SDMMC_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */ +#define STM32_SDMMC_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */ + +#define STM32_SDMMC_CMD_RESET (0) /* Reset value */ + +#define STM32_SDMMC_RESPCMD_SHIFT (0) +#define STM32_SDMMC_RESPCMD_MASK (0x3f << STM32_SDMMC_RESPCMD_SHIFT) + +#define STM32_SDMMC_DTIMER_RESET (0) /* Reset value */ + +#define STM32_SDMMC_DLEN_SHIFT (0) +#define STM32_SDMMC_DLEN_MASK (0x01ffffff << STM32_SDMMC_DLEN_SHIFT) + +#define STM32_SDMMC_DLEN_RESET (0) /* Reset value */ + +#define STM32_SDMMC_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */ +#define STM32_SDMMC_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */ +#define STM32_SDMMC_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */ +#define STM32_SDMMC_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */ +#define STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */ +#define STM32_SDMMC_DCTRL_DBLOCKSIZE_MASK (15 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_1BYTE (0 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_2BYTES (1 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_4BYTES (2 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_8BYTES (3 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_16BYTES (4 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_32BYTES (5 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_64BYTES (6 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_128BYTES (7 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_256BYTES (8 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_512BYTES (9 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_1KBYTE (10 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_2KBYTES (11 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_4KBYTES (12 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_8KBYTES (13 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_16KBYTES (14 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +#define STM32_SDMMC_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */ +#define STM32_SDMMC_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */ +#define STM32_SDMMC_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */ +#define STM32_SDMMC_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */ + +#define STM32_SDMMC_DCTRL_RESET (0) /* Reset value */ + +#define STM32_SDMMC_DCOUNT_SHIFT (0) +#define STM32_SDMMC_DCOUNT_MASK (0x01ffffff << STM32_SDMMC_DCOUNT_SHIFT) + +#define STM32_SDMMC_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */ +#define STM32_SDMMC_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */ +#define STM32_SDMMC_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */ +#define STM32_SDMMC_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */ +#define STM32_SDMMC_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */ +#define STM32_SDMMC_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */ +#define STM32_SDMMC_STA_CMDREND (1 << 6) /* Bit 6: Command response received */ +#define STM32_SDMMC_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */ +#define STM32_SDMMC_STA_DATAEND (1 << 8) /* Bit 8: Data end */ +#define STM32_SDMMC_STA_STBITERR (1 << 9) /* Bit 9: Start bit not detected */ +#define STM32_SDMMC_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */ +#define STM32_SDMMC_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */ +#define STM32_SDMMC_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */ +#define STM32_SDMMC_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */ +#define STM32_SDMMC_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */ +#define STM32_SDMMC_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */ +#define STM32_SDMMC_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */ +#define STM32_SDMMC_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */ +#define STM32_SDMMC_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */ +#define STM32_SDMMC_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */ +#define STM32_SDMMC_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */ +#define STM32_SDMMC_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */ +#define STM32_SDMMC_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */ +#define STM32_SDMMC_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */ + +#define STM32_SDMMC_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */ +#define STM32_SDMMC_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */ +#define STM32_SDMMC_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */ +#define STM32_SDMMC_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */ +#define STM32_SDMMC_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */ +#define STM32_SDMMC_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */ +#define STM32_SDMMC_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */ +#define STM32_SDMMC_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */ +#define STM32_SDMMC_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */ +#define STM32_SDMMC_ICR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */ +#define STM32_SDMMC_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */ +#define STM32_SDMMC_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */ +#define STM32_SDMMC_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */ + +#define STM32_SDMMC_ICR_RESET 0x00c007ff +#define STM32_SDMMC_ICR_STATICFLAGS 0x000005ff + +#define STM32_SDMMC_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */ +#define STM32_SDMMC_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */ +#define STM32_SDMMC_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */ +#define STM32_SDMMC_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */ +#define STM32_SDMMC_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */ +#define STM32_SDMMC_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */ +#define STM32_SDMMC_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */ +#define STM32_SDMMC_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */ +#define STM32_SDMMC_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */ +#define STM32_SDMMC_MASK_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */ +#define STM32_SDMMC_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */ +#define STM32_SDMMC_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */ +#define STM32_SDMMC_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */ +#define STM32_SDMMC_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */ +#define STM32_SDMMC_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */ +#define STM32_SDMMC_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */ +#define STM32_SDMMC_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */ +#define STM32_SDMMC_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */ +#define STM32_SDMMC_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */ +#define STM32_SDMMC_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */ +#define STM32_SDMMC_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */ +#define STM32_SDMMC_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */ +#define STM32_SDMMC_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */ +#define STM32_SDMMC_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */ + +#define STM32_SDMMC_MASK_RESET (0) + +#define STM32_SDMMC_FIFOCNT_SHIFT (0) +#define STM32_SDMMC_FIFOCNT_MASK (0x0ffffff << STM32_SDMMC_FIFOCNT_SHIFT) + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SDMMC_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_spi.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..fb42f44bc0bbe373ad8a68d0798cc2008c00df0e --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_spi.h @@ -0,0 +1,255 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f72xx73xx_spi.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SPI_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SPI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Maximum allowed speed as per data sheet for all SPIs (both pclk1 and pclk2)*/ + +# define STM32_SPI_CLK_MAX 50000000UL + +/* Register Offsets *****************************************************************/ + +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ +#define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ + +/* Register Addresses ***************************************************************/ + +#if STM32F7_NSPI > 0 +# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) +#endif + +#if STM32F7_NSPI > 1 +# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET) +#endif + +#if STM32F7_NSPI > 2 +# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI3_DR (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET) +#endif + +#if STM32F7_NSPI > 3 +# define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI4_DR (STM32_SPI4_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI4_CRCPR (STM32_SPI4_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI4_RXCRCR (STM32_SPI4_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI4_TXCRCR (STM32_SPI4_BASE+STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI4_I2SPR (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET) +#endif + +#if STM32F7_NSPI > 4 +# define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI5_DR (STM32_SPI5_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI5_CRCPR (STM32_SPI5_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI5_RXCRCR (STM32_SPI5_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI5_TXCRCR (STM32_SPI5_BASE+STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI5_I2SPR (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET) +#endif + +#if STM32F7_NSPI > 5 +# define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI6_DR (STM32_SPI6_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI6_CRCPR (STM32_SPI6_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI6_RXCRCR (STM32_SPI6_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI6_TXCRCR (STM32_SPI6_BASE+STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI6_I2SCFGR (STM32_SPI6_BASE+STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI6_I2SPR (STM32_SPI6_BASE+STM32_SPI_I2SPR_OFFSET) +#endif + +/* Register Bitfield Definitions ****************************************************/ + +/* SPI Control Register 1 */ + +#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */ +#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */ +#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */ +#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */ +#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT) +# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */ +# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */ +# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */ +# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */ +# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */ +# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */ +# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */ +# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */ +#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */ +#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */ +#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */ +#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */ +#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */ +#define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */ +#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */ +#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */ + +/* SPI Control Register 2 */ + +#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */ +#define SPI_CR2_NSSP (1 << 3) /* Bit 3 NSSP: NSS pulse management */ +#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */ +#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */ +#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */ +#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */ +#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */ +#define SPI_CR2_DS_MASK (0xf << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_VAL(bits) (((bits)-1) << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL(4) +# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL(5) +# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL(6) +# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL(7) +# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL(8) +# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL(9) +# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10) +# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11) +# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12) +# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13) +# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14) +# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15) +# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16) +#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */ +#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */ +#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */ + +/* SPI status register */ + +#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */ +#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */ +#define SPI_SR_CHSIDE (1 << 2) /* Bit 2: Channel side (i2s) */ +#define SPI_SR_UDR (1 << 3) /* Bit 3: Underrun flag (i2s) */ +#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */ +#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */ +#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */ +#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */ +#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */ +#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */ +#define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT) +# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */ +# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */ +# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */ +# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */ +#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */ +#define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT) +# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */ +# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */ +# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ +# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ + +/* I2S configuration register */ + +#define SPI_I2SCFGR_CHLEN (1 << 0) /* Bit 0: Channel length (number of bits per audio channel) */ +#define SPI_I2SCFGR_DATLEN_SHIFT (1) /* Bit 1-2: Data length to be transferred */ +#define SPI_I2SCFGR_DATLEN_MASK (3 << SPI_I2SCFGR_DATLEN_SHIFT) +# define SPI_I2SCFGR_DATLEN_16BIT (0 << SPI_I2SCFGR_DATLEN_SHIFT) /* 00: 16-bit data length */ +# define SPI_I2SCFGR_DATLEN_8BIT (1 << SPI_I2SCFGR_DATLEN_SHIFT) /* 01: 24-bit data length */ +# define SPI_I2SCFGR_DATLEN_32BIT (2 << SPI_I2SCFGR_DATLEN_SHIFT) /* 10: 32-bit data length */ +#define SPI_I2SCFGR_CKPOL (1 << 3) /* Bit 3: Steady state clock polarity */ +#define SPI_I2SCFGR_I2SSTD_SHIFT (4) /* Bit 4-5: I2S standard selection */ +#define SPI_I2SCFGR_I2SSTD_MASK (3 << SPI_I2SCFGR_I2SSTD_SHIFT) +# define SPI_I2SCFGR_I2SSTD_PHILLIPS (0 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */ +# define SPI_I2SCFGR_I2SSTD_MSB (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */ +# define SPI_I2SCFGR_I2SSTD_LSB (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */ +# define SPI_I2SCFGR_I2SSTD_PCM (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */ +#define SPI_I2SCFGR_PCMSYNC (1 << 7) /* Bit 7: PCM frame synchronization */ +#define SPI_I2SCFGR_I2SCFG_SHIFT (8) /* Bit 8-9: I2S configuration mode */ +#define SPI_I2SCFGR_I2SCFG_MASK (3 << SPI_I2SCFGR_I2SCFG_SHIFT) +# define SPI_I2SCFGR_I2SCFG_STX (0 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 00: Slave - transmit */ +# define SPI_I2SCFGR_I2SCFG_SRX (1 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 01: Slave - receive */ +# define SPI_I2SCFGR_I2SCFG_MTX (2 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 10: Master - transmit */ +# define SPI_I2SCFGR_I2SCFG_MRX (3 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 11: Master - receive */ +#define SPI_I2SCFGR_I2SE (1 << 10) /* Bit 10: I2S Enable */ +#define SPI_I2SCFGR_I2SMOD (1 << 11) /* Bit 11: I2S mode selection */ +#define SPI_I2SCFGR_ASTRTEN (1 << 12) /* Bit 12: Asynchronous start enable */ + +/* I2S prescaler register */ + +#define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */ +#define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT) +#define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SPI_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_syscfg.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_syscfg.h new file mode 100644 index 0000000000000000000000000000000000000000..14eee6e5a66e76464589bbfdec3970fcf6c6d1a6 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_syscfg.h @@ -0,0 +1,162 @@ +/**************************************************************************************************** + * arch/arm/src/stm32f7/chip/stm32f72xx74xx_syscfg.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SYSCFG_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SYSCFG_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_PMC_OFFSET 0x0004 /* SYSCFG peripheral mode configuration register */ + +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ + +#define STM32_SYSCFG_CMPCR_OFFSET 0x0020 /* Compensation cell control register */ + +/* Register Addresses *******************************************************************************/ + +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_PMC (STM32_SYSCFG_BASE+STM32_SYSCFG_PMC_OFFSET) + +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) + +#define STM32_SYSCFG_CMPCR (STM32_SYSCFG_BASE+STM32_SYSCFG_CMPCR_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ + +/* SYSCFG memory remap register */ + +#define SYSCFG_MEMRMP_MEMBOOT (1 << 0) /* Bit 0: Memory boot mapping */ +#define SYSCFG_MEMRMP_MEMBOOT_ADD0 (0 << 0) /* 0=BOOT_ADD0 defines */ +#define SYSCFG_MEMRMP_MEMBOOT_ADD1 (1 << 0) /* 1=BOOT_ADD1 defines */ +#define SYSCFG_MEMRMP_SWPFMC_SHIFT (10) /* Bits 10-11: FMC memory mapping swap */ +#define SYSCFG_MEMRMP_SWPFMC_MASK (3 << SYSCFG_MEMRMP_SWPFMC_SHIFT) +# define SYSCFG_MEMRMP_SWPFMC_NONE (0 << SYSCFG_MEMRMP_SWPFMC_SHIFT) /* No FMC memory mapping swapping */ +# define SYSCFG_MEMRMP_SWPFMC_NORRAM (1 << SYSCFG_MEMRMP_SWPFMC_SHIFT) /* NOR/RAM and SDRAM memory mapping swapped */ + +/* SYSCFG peripheral mode configuration register */ + +#define SYSCFG_PMC_I2C1_FMP (1 << 0) /* Bit 0: Forces FM+ drive capability on I2C1 SCL & SDA */ +#define SYSCFG_PMC_I2C2_FMP (1 << 1) /* Bit 1: Forces FM+ drive capability on I2C2 SCL & SDA */ +#define SYSCFG_PMC_I2C3_FMP (1 << 2) /* Bit 2: Forces FM+ drive capability on I2C3 SCL & SDA */ +#define SYSCFG_PMC_PB6_FMP (1 << 4) /* Bit 4: Forces FM+ drive capability on the PB6 pin */ +#define SYSCFG_PMC_PB7_FMP (1 << 5) /* Bit 5: Forces FM+ drive capability on the PB7 pin */ +#define SYSCFG_PMC_PB8_FMP (1 << 6) /* Bit 7: Forces FM+ drive capability on the PB8 pin */ +#define SYSCFG_PMC_PB9_FMP (1 << 7) /* Bit 4: Forces FM+ drive capability on the PB9 pin */ +#define SYSCFG_PMC_ADC1DC2 (1 << 16) /* Bit 16: See AN4073 */ +#define SYSCFG_PMC_ADC2DC2 (1 << 17) /* Bit 17: See AN4073 */ +#define SYSCFG_PMC_ADC3DC2 (1 << 18) /* Bit 18: See AN4073 */ + +/* SYSCFG external interrupt configuration register 1-4 */ + +#define SYSCFG_EXTICR_PORTA (0) /* 0000: PA[x] pin */ +#define SYSCFG_EXTICR_PORTB (1) /* 0001: PB[x] pin */ +#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */ +#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */ +#define SYSCFG_EXTICR_PORTE (4) /* 0100: PE[x] pin */ +#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[C] pin */ +#define SYSCFG_EXTICR_PORTG (6) /* 0110: PG[x] pin */ +#define SYSCFG_EXTICR_PORTH (7) /* 0111: PH[x] pin */ +#define SYSCFG_EXTICR_PORTI (8) /* 1000: PI[x] pin */ + +#define SYSCFG_EXTICR_PORT_MASK (15) +#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2) +#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g))) + +#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-3: EXTI 0 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT) +#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-7: EXTI 1 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT) +#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-11: EXTI 2 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT) +#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-15: EXTI 3 coinfiguration */ +#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT) + +#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-3: EXTI 4 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT) +#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-7: EXTI 5 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT) +#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-11: EXTI 6 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT) +#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-15: EXTI 7 coinfiguration */ +#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT) + +#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-3: EXTI 8 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT) +#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-7: EXTI 9 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT) +#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-11: EXTI 10 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT) +#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-15: EXTI 11 coinfiguration */ +#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT) + +#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-3: EXTI 12 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT) +#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-7: EXTI 13 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT) +#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-11: EXTI 14 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT) +#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 coinfiguration */ +#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT) + +/* Compensation cell control register */ + +#define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */ +#define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */ + +#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_tim.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_tim.h new file mode 100644 index 0000000000000000000000000000000000000000..3e91342ea74f14b0f22c839e1f82c55a6c332357 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_tim.h @@ -0,0 +1,1130 @@ +/**************************************************************************************************** + * arch/arm/src/stm32f7/chip/stm32f72xx73xx_tim.h + * + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_TIM_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_TIM_H + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +/* Basic Timers - TIM6 and TIM7 */ + +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ + +/* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5 + * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 + * timers are 16-bit except for TIM2 and 5 are 32-bit + * timers TIM9 and 12 are different then TIM10, TIM11, TIM13, and TIM14 + */ + +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit, TIM2, 5 only) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (32-bit, TIM2, 5, 9, 12 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit on TIM2,5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16 bit and 32-bit on TIM2, 5 only) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16 bit and 32-bit on TIM2, 5 only) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit on all TIMx and 32-bit on TIM2,5 only) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM 3-4, 9, 12 and 32-bit on TIM2,5 only) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM 3-4 and 32-bit on TIM2,5 only) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM 3-4 and 32-bit on TIM2,5 only) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit, TIM2-5 only) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit, TIM2-5 only) */ +#define STM32_GTIM_OR_OFFSET 0x0050 /* Timer 2/5/11 option register */ + +/* Advanced Timers - TIM1 and TIM8 */ + +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (32-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (32 -bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (32-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (32-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (32-bit cnt in lower 16 bit ) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (32-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (32-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 6 (16-bit) */ + +/* Register Addresses *******************************************************************************/ + +/* Advanced Timers - TIM1 and TIM8 */ + +#if STM32F7_NATIM > 0 +# define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) +# define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) +# define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) +# define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) +# define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) +# define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) +# define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) +# define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) +# define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) +# define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) +# define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) +# define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) +# define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) +# define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) +# define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) +# define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) +# define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) +# define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) +# define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) +# define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) +# define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) +# define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) +# define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) +#endif + +#if STM32F7_NATIM > 1 +# define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) +# define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) +# define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) +# define STM32_TIM8_DIER (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET) +# define STM32_TIM8_SR (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET) +# define STM32_TIM8_EGR (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET) +# define STM32_TIM8_CCMR1 (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET) +# define STM32_TIM8_CCMR2 (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET) +# define STM32_TIM8_CCER (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET) +# define STM32_TIM8_CNT (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET) +# define STM32_TIM8_PSC (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET) +# define STM32_TIM8_ARR (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET) +# define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET) +# define STM32_TIM8_CCR1 (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET) +# define STM32_TIM8_CCR2 (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET) +# define STM32_TIM8_CCR3 (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET) +# define STM32_TIM8_CCR4 (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET) +# define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET) +# define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET) +# define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET) +# define STM32_TIM8_CCMR3 (STM32_TIM8_BASE+STM32_ATIM_CCMR3_OFFSET) +# define STM32_TIM8_CCR5 (STM32_TIM8_BASE+STM32_ATIM_CCR5_OFFSET) +# define STM32_TIM8_CCR6 (STM32_TIM8_BASE+STM32_ATIM_CCR6_OFFSET) +#endif + +/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, and TIM5 with DMA. + * All timers are 16-bit except for TIM2 and 5 are 32-bit + */ + +#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +# define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET) +# define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) +#endif + +#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +# define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) +#endif + +#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +# define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM4_DIER (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM4_SR (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM4_EGR (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM4_CCMR1 (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM4_CCMR2 (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM4_CCER (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM4_CNT (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM4_PSC (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM4_ARR (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM4_CCR1 (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM4_CCR2 (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM4_CCR3 (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM4_CCR4 (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM4_DCR (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) +#endif + +#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +# define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM5_DIER (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM5_SR (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM5_EGR (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM5_CCMR1 (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM5_CCMR2 (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM5_CCER (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM5_CNT (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM5_PSC (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM5_ARR (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM5_CCR1 (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM5_CCR2 (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM5_CCR3 (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET) +# define STM32_TIM5_OR (STM32_TIM5_BASE+STM32_GTIM_OR_OFFSET) +#endif + + +/* 16-bit General Timers - TIM9-14 without DMA. Note that (1) these timers + * support only a subset of the general timer registers are supported, and + * (2) TIM9 and TIM12 differ from the others. + */ + +#if STM32F7_NGTIMNDMA > 0 +# define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM9_SR (STM32_TIM9_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM9_EGR (STM32_TIM9_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM9_CCMR1 (STM32_TIM9_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM9_CCER (STM32_TIM9_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM9_CNT (STM32_TIM9_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM9_PSC (STM32_TIM9_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM9_ARR (STM32_TIM9_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM9_CCR1 (STM32_TIM9_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) +#endif + +#if STM32F7_NGTIMNDMA > 1 +# define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM10_EGR (STM32_TIM10_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM10_CCMR1 (STM32_TIM10_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM10_CCER (STM32_TIM10_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM10_CNT (STM32_TIM10_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM10_PSC (STM32_TIM10_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM10_ARR (STM32_TIM10_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) +#endif + +#if STM32F7_NGTIMNDMA > 2 +# define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM11_EGR (STM32_TIM11_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM11_CCMR1 (STM32_TIM11_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM11_CCER (STM32_TIM11_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM11_CNT (STM32_TIM11_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM11_PSC (STM32_TIM11_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM11_ARR (STM32_TIM11_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM11_CCR1 (STM32_TIM11_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) +#endif + +#if STM32F7_NGTIMNDMA > 3 +# define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM12_SR (STM32_TIM12_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM12_EGR (STM32_TIM12_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM12_CCMR1 (STM32_TIM12_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM12_CCER (STM32_TIM12_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM12_CNT (STM32_TIM12_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM12_PSC (STM32_TIM12_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM12_ARR (STM32_TIM12_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM12_CCR1 (STM32_TIM12_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) +#endif + +#if STM32F7_NGTIMNDMA > 4 +# define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM13_EGR (STM32_TIM13_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM13_CCMR1 (STM32_TIM13_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM13_CCER (STM32_TIM13_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM13_CNT (STM32_TIM13_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM13_PSC (STM32_TIM13_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM13_ARR (STM32_TIM13_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) +#endif + +#if STM32F7_NGTIMNDMA > 5 +# define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM14_EGR (STM32_TIM14_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM14_CCMR1 (STM32_TIM14_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM14_CCER (STM32_TIM14_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM14_CNT (STM32_TIM14_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM14_PSC (STM32_TIM14_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM14_ARR (STM32_TIM14_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM14_CCR1 (STM32_TIM14_BASE+STM32_GTIM_CCR1_OFFSET) +#endif + +/* Basic Timers - TIM6 and TIM7 */ + +#if STM32F7_NBTIM > 0 +# define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) +# define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) +# define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) +# define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET) +# define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET) +# define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET) +# define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET) +# define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) +#endif + +#if STM32F7_NBTIM > 1 +# define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) +# define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) +# define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) +# define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET) +# define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET) +# define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET) +# define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET) +# define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************************************/ + +/* Control register 1 */ + +#define ATIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define ATIM_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ +#define ATIM_CR1_URS (1 << 2) /* Bit 2: Update request source */ +#define ATIM_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ +#define ATIM_CR1_DIR (1 << 4) /* Bit 4: Direction */ +#define ATIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned mode selection */ +#define ATIM_CR1_CMS_MASK (3 << ATIM_CR1_CMS_SHIFT) +# define ATIM_CR1_EDGE (0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ +# define ATIM_CR1_CENTER1 (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ +# define ATIM_CR1_CENTER2 (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ +# define ATIM_CR1_CENTER3 (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ +#define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ +#define ATIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock division */ +#define ATIM_CR1_CKD_MASK (3 << ATIM_CR1_CKD_SHIFT) +# define ATIM_CR1_TCKINT (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ +# define ATIM_CR1_2TCKINT (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ +# define ATIM_CR1_4TCKINT (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ +#define ATIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ + +/* Control register 2 */ + +#define ATIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare Preloaded Control */ +#define ATIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare Control Update Selection */ +#define ATIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */ +#define ATIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ +#define ATIM_CR2_MMS_MASK (7 << ATIM_CR2_MMS_SHIFT) +# define ATIM_CR2_MMS_RESET (0 << ATIM_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */ +# define ATIM_CR2_MMS_ENABLE (1 << ATIM_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */ +# define ATIM_CR2_MMS_UPDATE (2 << ATIM_CR2_MMS_SHIFT) /* 010: Update event is TRGO */ +# define ATIM_CR2_MMS_COMPP (3 << ATIM_CR2_MMS_SHIFT) /* 010: Compare Pulse - CC1IF flag */ +# define ATIM_CR2_MMS_OC1REF (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */ +# define ATIM_CR2_MMS_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */ +# define ATIM_CR2_MMS_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */ +# define ATIM_CR2_MMS_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */ +#define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ +#define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ +#define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ +#define ATIM_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */ +#define ATIM_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */ +#define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ +#define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ +#define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ +#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */ +#define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ +#define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ +#define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) +# define ATIM_CR2_MMS2_RESET (0 << ATIM_CR2_MMS2_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRG9 */ +# define ATIM_CR2_MMS2_ENABLE (1 << ATIM_CR2_MMS2_SHIFT) /* 0001: Enable - CNT_EN is TRGO2 */ +# define ATIM_CR2_MMS2_UPDATE (2 << ATIM_CR2_MMS2_SHIFT) /* 0010: Update event is TRGH0*/ +# define ATIM_CR2_MMS2_COMPP (3 << ATIM_CR2_MMS2_SHIFT) /* 0010: Compare Pulse - CC1IF flag */ +# define ATIM_CR2_MMS2_OC1REF (4 << ATIM_CR2_MMS2_SHIFT) /* 0100: Compare OC1REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC2REF (5 << ATIM_CR2_MMS2_SHIFT) /* 0101: Compare OC2REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC3REF (6 << ATIM_CR2_MMS2_SHIFT) /* 0110: Compare OC3REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC4REF (7 << ATIM_CR2_MMS2_SHIFT) /* 0111: Compare OC4REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC5REF (8 << ATIM_CR2_MMS2_SHIFT) /* 1000: Compare OC5REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC6REF (9 << ATIM_CR2_MMS2_SHIFT) /* 1001: Compare OC6REF is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC4 (10 << ATIM_CR2_MMS2_SHIFT) /* 1010: Compare pulse - OC4REF edge is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC6 (11 << ATIM_CR2_MMS2_SHIFT) /* 1011: Compare pulse - OC6REF edge is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC4R6R (12 << ATIM_CR2_MMS2_SHIFT) /* 1100: Compare pulse - OC4REF/OC6REF rising */ +# define ATIM_CR2_MMS2_CMPOC4R6F (13 << ATIM_CR2_MMS2_SHIFT) /* 1101: Compare pulse - OC4REF rising/OC6REF falling */ +# define ATIM_CR2_MMS2_CMPOC5R6R (14 << ATIM_CR2_MMS2_SHIFT) /* 1110: Compare pulse - OC5REF/OC6REF rising */ +# define ATIM_CR2_MMS2_CMPOC5R6F (15 << ATIM_CR2_MMS2_SHIFT) /* 1111: Compare pulse - OC5REF rising/OC6REF falling */ + +/* Slave mode control register */ + +#define ATIM_SMCR_SMS_SHIFT (0) /* Bits 0-2: Slave mode selection */ +#define ATIM_SMCR_SMS_MASK (7 << ATIM_SMCR_SMS_SHIFT) +# define ATIM_SMCR_DISAB (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ +# define ATIM_SMCR_ENCMD1 (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ +# define ATIM_SMCR_ENCMD2 (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ +# define ATIM_SMCR_ENCMD3 (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ +# define ATIM_SMCR_RESET (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ +# define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ +# define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ +# define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ +#define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ +#define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT) +# define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */ +# define ATIM_SMCR_ITR1 (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */ +# define ATIM_SMCR_ITR2 (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */ +# define ATIM_SMCR_ITR3 (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */ +# define ATIM_SMCR_T1FED (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ +# define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ +# define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ +# define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ +#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ +#define ATIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ +#define ATIM_SMCR_ETF_MASK (0x0f << ATIM_SMCR_ETF_SHIFT) +# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ +# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_SMCR_FDTSd165 (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_SMCR_FDTSd166 (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_SMCR_FDTSd168 (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_SMCR_FDTSd325 (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_SMCR_FDTSd326 (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_SMCR_FDTSd328 (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ +#define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT) +# define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ +# define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ +# define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ +# define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ +#define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ +#define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ +#define ATIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ + +/* DMA/Interrupt enable register */ + +#define ATIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define ATIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ +#define ATIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ +#define ATIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ +#define ATIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ +#define ATIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */ +#define ATIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ +#define ATIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */ +#define ATIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ +#define ATIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ +#define ATIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ +#define ATIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ +#define ATIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ +#define ATIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */ +#define ATIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */ + +/* Status register */ + +#define ATIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ +#define ATIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ +#define ATIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */ +#define ATIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */ +#define ATIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */ +#define ATIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */ +#define ATIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */ +#define ATIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */ +#define ATIM_SR_B2IF (1 << 8) /* Bit 8: Break 2 interrupt Flag */ +#define ATIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ +#define ATIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ +#define ATIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ +#define ATIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ +#define ATIM_SR_CC5IF (1 << 16) /* Bit 16: Compare 5 interrupt flag */ +#define ATIM_SR_CC6IF (1 << 17) /* Bit 17: Compare 6 interrupt flag */ + +/* Event generation register */ + +#define ATIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */ +#define ATIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ +#define ATIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ +#define ATIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ +#define ATIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ +#define ATIM_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ +#define ATIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ +#define ATIM_EGR_BG (1 << 7) /* Bit 7: Break Generation */ +#define ATIM_EGR_B2G (1 << 8) /* Bit 8: Break 2 Generation */ + +/* Capture/compare mode register 1 -- Output compare mode */ + +#define ATIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ +#define ATIM_CCMR1_CC1S_MASK (3 << ATIM_CCMR1_CC1S_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ +#define ATIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ +#define ATIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ +#define ATIM_CCMR1_OC1M_MASK (7 << ATIM_CCMR1_OC1M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ +#define ATIM_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ +#define ATIM_CCMR1_CC2S_MASK (3 << ATIM_CCMR1_CC2S_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ +#define ATIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ +#define ATIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ +#define ATIM_CCMR1_OC2M_MASK (7 << ATIM_CCMR1_OC2M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ +#define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ +#define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ + + +/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ + +#define ATIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ +#define ATIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ +#define ATIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ +#define ATIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ + +/* Common CCMR (unshifted) Compare Mode bit field definitions */ + +#define ATIM_CCMR_MODE_FRZN (0) /* 0000: Frozen */ +#define ATIM_CCMR_MODE_CHACT (1) /* 0001: Channel x active on match */ +#define ATIM_CCMR_MODE_CHINACT (2) /* 0010: Channel x inactive on match */ +#define ATIM_CCMR_MODE_OCREFTOG (3) /* 0011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ +#define ATIM_CCMR_MODE_OCREFLO (4) /* 0100: OCxREF forced low */ +#define ATIM_CCMR_MODE_OCREFHI (5) /* 0101: OCxREF forced high */ +#define ATIM_CCMR_MODE_PWM1 (6) /* 0110: PWM mode 1 */ +#define ATIM_CCMR_MODE_PWM2 (7) /* 0111: PWM mode 2 */ +#define ATIM_CCMR_MODE_OPM1 (8) /* 1000: Retrigerrable OPM mode 1 */ +#define ATIM_CCMR_MODE_OPM2 (9) /* 1001: Retrigerrable OPM mode 2 */ +#define ATIM_CCMR_MODE_COMBINED1 (12) /* 1100: Combined PWM mode 1 */ +#define ATIM_CCMR_MODE_COMBINED2 (13) /* 1101: Combined PWM mode 2 */ +#define ATIM_CCMR_MODE_ASYMMETRIC1 (14) /* 1110: Asymmetric PWM mode 1 */ +#define ATIM_CCMR_MODE_ASYMMETRIC2 (15) /* 1111: Asymmetric PWM mode 2 */ + +/* Capture/compare mode register 1 -- Input capture mode */ + + /* Bits 1-0:(same as output compare mode) */ +#define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ +#define ATIM_CCMR1_IC1PSC_MASK (3 << ATIM_CCMR1_IC1PSC_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ +#define ATIM_CCMR1_IC1F_MASK (0x0f << ATIM_CCMR1_IC1F_SHIFT) + /* (See common (unshifted) bit field definitions below) */ + /* Bits 9:8 (same as output compare mode) */ +#define ATIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11:10: Input Capture 2 Prescaler */ +#define ATIM_CCMR1_IC2PSC_MASK (3 << ATIM_CCMR1_IC2PSC_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ +#define ATIM_CCMR1_IC2F_MASK (0x0f << ATIM_CCMR1_IC2F_SHIFT) + /* (See common (unshifted) bit field definitions below) */ + +/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ + +#define ATIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ +#define ATIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ +#define ATIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ +#define ATIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ + +/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ + +#define ATIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ +#define ATIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ +#define ATIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ +#define ATIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ +#define ATIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ +#define ATIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ +#define ATIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ +#define ATIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ +#define ATIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ +#define ATIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ +#define ATIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ +#define ATIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ +#define ATIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ +#define ATIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ +#define ATIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ +#define ATIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +/* Capture/compare mode register 2 - Output Compare mode */ + +#define ATIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ +#define ATIM_CCMR2_CC3S_MASK (3 << ATIM_CCMR2_CC3S_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ +#define ATIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ +#define ATIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ +#define ATIM_CCMR2_OC3M_MASK (7 << ATIM_CCMR2_OC3M_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ +#define ATIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ +#define ATIM_CCMR2_CC4S_MASK (3 << ATIM_CCMR2_CC4S_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ +#define ATIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ +#define ATIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ +#define ATIM_CCMR2_OC4M_MASK (7 << ATIM_CCMR2_OC4M_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ +#define ATIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ +#define ATIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ + +/* Capture/compare mode register 2 - Input Capture Mode */ + + /* Bits 1-0:(same as output compare mode) */ +#define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ +#define ATIM_CCMR1_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ +#define ATIM_CCMR2_IC3F_MASK (0x0f << ATIM_CCMR2_IC3F_SHIFT) + /* (See common (unshifted) bit field definitions above) */ + /* Bits 9:8 (same as output compare mode) */ +#define ATIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11:10: Input Capture 4 Prescaler */ +#define ATIM_CCMR2_IC4PSC_MASK (3 << ATIM_CCMR2_IC4PSC_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ +#define ATIM_CCMR2_IC4F_MASK (0x0f << ATIM_CCMR2_IC4F_SHIFT) + /* (See common (unshifted) bit field definitions above) */ + +/* Capture/compare mode register 3 -- Output compare mode */ + +#define ATIM_CCMR3_OC5FE (1 << 2) /* Bit 2: Output Compare 5 Fast enable */ +#define ATIM_CCMR3_OC5PE (1 << 3) /* Bit 3: Output Compare 5 Preload enable */ +#define ATIM_CCMR3_OC5M_SHIFT (4) /* Bits 6-4: Output Compare 5 Mode */ +#define ATIM_CCMR3_OC5M_MASK (7 << ATIM_CCMR3_OC5M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR3_OC5CE (1 << 7) /* Bit 7: Output Compare 5 Clear Enable */ +#define ATIM_CCMR3_OC6FE (1 << 10) /* Bit 10: Output Compare 6 Fast enable */ +#define ATIM_CCMR3_OC6PE (1 << 11) /* Bit 11: Output Compare 6 Preload enable */ +#define ATIM_CCMR3_OC6M_SHIFT (12) /* Bits 14-12: Output Compare 7 Mode */ +#define ATIM_CCMR3_OC6M_MASK (7 << ATIM_CCMR3_OC6M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR3_OC6CE (1 << 15) /* Bit 15: Output Compare 7 Clear Enable */ +#define ATIM_CCMR3_OC5M (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */ +#define ATIM_CCMR3_OC6M (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */ + + +/* Capture/compare enable register */ + +#define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ +#define ATIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output Polarity */ +#define ATIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 Complementary output enable */ +#define ATIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary output polarity */ +#define ATIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */ +#define ATIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output Polarity */ +#define ATIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 Complementary output enable */ +#define ATIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary output polarity */ +#define ATIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */ +#define ATIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity */ +#define ATIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */ +#define ATIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output polarity */ +#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */ +#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */ +#define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */ +#define ATIM_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 output enable */ +#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ +#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ +#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ + + +/* 16-bit counter register */ + +#define ATIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ +#define ATIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) + +/* Repetition counter register */ + +#define ATIM_RCR_REP_SHIFT (0) /* Bits 0-15: Repetition Counter Value */ +#define ATIM_RCR_REP_MASK (0xffff << ATIM_RCR_REP_SHIFT) + +#define ATIM_RCR_REP_MAX 65536 + +/* Capture/compare registers (CCR) */ + +#define ATIM_CCR5_GC5C1 (1 << 29) /* Bit 29: Group Channel 5 and Channel 1 */ +#define ATIM_CCR5_GC5C2 (1 << 30) /* Bit 30: Group Channel 5 and Channel 2 */ +#define ATIM_CCR5_GC5C3 (1 << 31) /* Bit 31: Group Channel 5 and Channel 3 */ + +#define ATIM_CCR_MASK (0xffff) + +/* Break and dead-time register */ + +#define ATIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ +#define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT) +#define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ +#define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT) +# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ +# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ +# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ +# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */ +#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ +#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ +#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ +#define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ +#define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ +#define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ +#define ATIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ +#define ATIM_BDTR_BKF_MASK (0xf << ATIM_BDTR_BKF_SHIFT) +# define ATIM_BDTR_BKF_NOFILT (0 << ATIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ +# define ATIM_BDTR_BKF_FCKINT2 (1 << ATIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_BDTR_BKF_FCKINT4 (2 << ATIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_BDTR_BKF_FCKINT8 (3 << ATIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_BDTR_BKF_FDTSd26 (4 << ATIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_BDTR_BKF_FDTSd28 (5 << ATIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_BDTR_BKF_FDTSd36 (6 << ATIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_BDTR_BKF_FDTSd38 (7 << ATIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_BDTR_BKF_FDTSd86 (8 << ATIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_BDTR_BKF_FDTSd88 (9 << ATIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_BDTR_BKF_FDTSd165 (10 << ATIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_BDTR_BKF_FDTSd166 (11 << ATIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_BDTR_BKF_FDTSd168 (12 << ATIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_BDTR_BKF_FDTSd325 (13 << ATIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_BDTR_BKF_FDTSd326 (14 << ATIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_BDTR_BKF_FDTSd328 (15 << ATIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define ATIM_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ +#define ATIM_BDTR_BK2F_MASK (0xf << ATIM_BDTR_BK2F_SHIFT) +# define ATIM_BDTR_BK2F_NOFILT (0 << ATIM_BDTR_BK2F_SHIFT) /* 0000: No filter, BRK 2 acts asynchronously */ +# define ATIM_BDTR_BK2F_FCKINT2 (1 << ATIM_BDTR_BK2F_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_BDTR_BK2F_FCKINT4 (2 << ATIM_BDTR_BK2F_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_BDTR_BK2F_FCKINT8 (3 << ATIM_BDTR_BK2F_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd26 (4 << ATIM_BDTR_BK2F_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd28 (5 << ATIM_BDTR_BK2F_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd36 (6 << ATIM_BDTR_BK2F_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd38 (7 << ATIM_BDTR_BK2F_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd86 (8 << ATIM_BDTR_BK2F_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd88 (9 << ATIM_BDTR_BK2F_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd165 (10 << ATIM_BDTR_BK2F_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_BDTR_BK2F_FDTSd166 (11 << ATIM_BDTR_BK2F_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd168 (12 << ATIM_BDTR_BK2F_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ +#define ATIM_BDTR_BK2P (1 << 1525 /* Bit 25:Break 2 polarity */ + + +/* DMA control register */ + +#define ATIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ +#define ATIM_DCR_DBA_MASK (0x1f << ATIM_DCR_DBA_SHIFT) +#define ATIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ +#define ATIM_DCR_DBL_MASK (0x1f << ATIM_DCR_DBL_SHIFT) +# define ATIM_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ + +/* Control register 1 (TIM2-5 and TIM9-14) */ + +#define GTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define GTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ +#define GTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ +#define GTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode (TIM2-5, 9, and 12 only) */ +#define GTIM_CR1_DIR (1 << 4) /* Bit 4: Direction (TIM2-5 only) */ +#define GTIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned Mode Selection (TIM2-5 only) */ +#define GTIM_CR1_CMS_MASK (3 << GTIM_CR1_CMS_SHIFT) +# define GTIM_CR1_EDGE (0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode. */ +# define GTIM_CR1_CENTER1 (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ +# define GTIM_CR1_CENTER2 (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ +# define GTIM_CR1_CENTER3 (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ +#define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ +#define GTIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock Division */ +#define GTIM_CR1_CKD_MASK (3 << GTIM_CR1_CKD_SHIFT) +# define GTIM_CR1_TCKINT (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */ +# define GTIM_CR1_2TCKINT (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */ +# define GTIM_CR1_4TCKINT (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */ +#define GTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ + +/* Control register 2 (TIM2-5, TIM9-12) */ + +#define GTIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/compare preloaded control (TIM15-17 only) */ +#define GTIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/compare control update selection (TIM15-17 only) */ +#define GTIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection (TIM2-5,1,&16 only) */ +#define GTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection (not TIM16) */ +#define GTIM_CR2_MMS_MASK (7 << GTIM_CR2_MMS_SHIFT) +# define GTIM_CR2_MMS_RESET (0 << GTIM_CR2_MMS_SHIFT) /* 000: Reset */ +# define GTIM_CR2_MMS_ENABLE (1 << GTIM_CR2_MMS_SHIFT) /* 001: Enable */ +# define GTIM_CR2_MMS_UPDATE (2 << GTIM_CR2_MMS_SHIFT) /* 010: Update */ +# define GTIM_CR2_MMS_COMPP (3 << GTIM_CR2_MMS_SHIFT) /* 011: Compare Pulse */ +# define GTIM_CR2_MMS_OC1REF (4 << GTIM_CR2_MMS_SHIFT) /* 100: Compare - OC1REF signal is used as trigger output (TRGO) */ +# define GTIM_CR2_MMS_OC2REF (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */ +# define GTIM_CR2_MMS_OC3REF (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ +# define GTIM_CR2_MMS_OC4REF (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ +#define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection (not TIM16) */ +#define GTIM_CR2_OIS1 (1 << 8) /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */ +#define GTIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */ +#define GTIM_CR2_OIS2 (1 << 10) /* Bit 10: Output idle state 2 (OC2 output) (TIM15 only) */ + +/* Slave mode control register (TIM2-5) */ + +#define GTIM_SMCR_SMS_SHIFT (0) /* Bits 2-0: Slave Mode Selection */ +#define GTIM_SMCR_SMS_MASK (7 << GTIM_SMCR_SMS_SHIFT) +# define GTIM_SMCR_DISAB (0 << GTIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ +# define GTIM_SMCR_ENCMD1 (1 << GTIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ +# define GTIM_SMCR_ENCMD2 (2 << GTIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ +# define GTIM_SMCR_ENCMD3 (3 << GTIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ +# define GTIM_SMCR_RESET (4 << GTIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ +# define GTIM_SMCR_GATED (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ +# define GTIM_SMCR_TRIGGER (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ +# define GTIM_SMCR_EXTCLK1 (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ +#define GTIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger Selection */ +#define GTIM_SMCR_TS_MASK (7 << GTIM_SMCR_TS_SHIFT) +# define GTIM_SMCR_ITR0 (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */ +# define GTIM_SMCR_ITR1 (1 << GTIM_SMCR_TS_SHIFT) /* 001: Internal Trigger 1 (ITR1). TIM2 */ +# define GTIM_SMCR_ITR2 (2 << GTIM_SMCR_TS_SHIFT) /* 010: Internal Trigger 2 (ITR2). TIM3 */ +# define GTIM_SMCR_ITR3 (3 << GTIM_SMCR_TS_SHIFT) /* 011: Internal Trigger 3 (ITR3). TIM4 */ +# define GTIM_SMCR_TI1FED (4 << GTIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ +# define GTIM_SMCR_TI1FP1 (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ +# define GTIM_SMCR_TI2FP2 (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ +# define GTIM_SMCR_ETRF (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ +#define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/Slave mode */ +#define GTIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External Trigger Filter (not TIM15) */ +#define GTIM_SMCR_ETF_MASK (0x0f << GTIM_SMCR_ETF_SHIFT) +# define GTIM_SMCR_NOFILT (0 << GTIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ +# define GTIM_SMCR_FCKINT2 (1 << GTIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define GTIM_SMCR_FCKINT4 (2 << GTIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define GTIM_SMCR_FCKINT8 (3 << GTIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define GTIM_SMCR_FDTSd26 (4 << GTIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define GTIM_SMCR_FDTSd28 (5 << GTIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define GTIM_SMCR_FDTSd36 (6 << GTIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define GTIM_SMCR_FDTSd38 (7 << GTIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define GTIM_SMCR_FDTSd86 (8 << GTIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define GTIM_SMCR_FDTSd88 (9 << GTIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define GTIM_SMCR_FDTSd165 (10 << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define GTIM_SMCR_FDTSd166 (11 << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define GTIM_SMCR_FDTSd168 (12 << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define GTIM_SMCR_FDTSd325 (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define GTIM_SMCR_FDTSd326 (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define GTIM_SMCR_FDTSd328 (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External Trigger Prescaler (not TIM15) */ +#define GTIM_SMCR_ETPS_MASK (3 << GTIM_SMCR_ETPS_SHIFT) +# define GTIM_SMCR_PSCOFF (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ +# define GTIM_SMCR_ETRPd2 (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ +# define GTIM_SMCR_ETRPd4 (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ +# define GTIM_SMCR_ETRPd8 (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ +#define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External Clock enable */ +#define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External Trigger Polarity */ +#define GTIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ + +/* DMA/Interrupt enable register (TIM2-5 and TIM9-14) */ + +#define GTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define GTIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ +#define GTIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable (TIM2-5,9,12,&15 only) */ +#define GTIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable (TIM2-5 only) */ +#define GTIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable (TIM2-5 only) */ +#define GTIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable (TIM15-17 only) */ +#define GTIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable (TIM2-5,9,&12 only) */ +#define GTIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable (TIM15-17 only) */ +#define GTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable (TIM2-5&15-17 only) */ +#define GTIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable (TIM2-5&15-17 only) */ +#define GTIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable (TIM2-5&15 only) */ +#define GTIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable (TIM2-5 only) */ +#define GTIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable (TIM2-5 only) */ +#define GTIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable (TIM15-17 only) */ +#define GTIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable (TIM2-5&15-17 only) */ + +/* Status register */ + +#define GTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ +#define GTIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/compare 1 interrupt flag */ +#define GTIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt flag (TIM2-5,9,12,&15 only) */ +#define GTIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt flag (TIM2-5 only) */ +#define GTIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt flag (TIM2-5 only) */ +#define GTIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt flag (TIM15-17 only) */ +#define GTIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag (TIM2-5,9,12&15-17 only) */ +#define GTIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt flag (TIM15-17 only) */ +#define GTIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture flag */ +#define GTIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture flag (TIM2-5,9,12&15 only) */ +#define GTIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture flag (TIM2-5 only) */ +#define GTIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture flag (TIM2-5 only) */ + +/* Event generation register (TIM2-5 and TIM9-14) */ + +#define GTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ +#define GTIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/compare 1 generation */ +#define GTIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/compare 2 generation (TIM2-5,9,12,&15 only) */ +#define GTIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/compare 3 generation (TIM2-5 only) */ +#define GTIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/compare 4 generation (TIM2-5 only) */ +#define GTIM_EGR_COMIG (1 << 5) /* Bit 5: Capture/Compare control update generation (TIM15-17 only) */ +#define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation (TIM2-5,9,12&16-17 only) */ +#define GTIM_EGR_BG (1 << 7) /* Bit 7: Break generation (TIM15-17 only) */ + +/* Capture/compare mode register 1 - Output compare mode (TIM2-5 and TIM9-14) */ + +#define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ +#define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions below) */ +#define GTIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ +#define GTIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ +#define GTIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ +#define GTIM_CCMR1_OC1M_MASK (7 << GTIM_CCMR1_OC1M_SHIFT) + /* (See common CCMR Output Compare Mode definitions below) */ +#define GTIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ +#define GTIM_CCMR1_CC2S_SHIFT (8) /* Bits 9-8: Capture/Compare 2 Selection */ +#define GTIM_CCMR1_CC2S_MASK (3 << GTIM_CCMR1_CC2S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions below) */ +#define GTIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ +#define GTIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ +#define GTIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ +#define GTIM_CCMR1_OC2M_MASK (7 << GTIM_CCMR1_OC2M_SHIFT) + /* (See common CCMR Output Compare Mode definitions below) */ +#define GTIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ +#define GTIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ +#define GTIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ + +/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ + +#define GTIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ +#define GTIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ +#define GTIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ +#define GTIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ + +/* Common CCMR (unshifted) Compare Mode bit field definitions */ + +#define GTIM_CCMR_MODE_FRZN (0) /* 000: Frozen */ +#define GTIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */ +#define GTIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */ +#define GTIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ +#define GTIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */ +#define GTIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */ +#define GTIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ +#define GTIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ + +/* Capture/compare mode register 1 - Input capture mode (TIM2-5 and TIM9-14) */ + + /* Bits 1-0 (Same as Output Compare Mode) */ +#define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ +#define GTIM_CCMR1_IC1PSC_MASK (3 << GTIM_CCMR1_IC1PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ +#define GTIM_CCMR1_IC1F_MASK (0x0f << GTIM_CCMR1_IC1F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + /* Bits 9-8: (Same as Output Compare Mode) */ +#define GTIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11-10: Input Capture 2 Prescaler */ +#define GTIM_CCMR1_IC2PSC_MASK (3 << GTIM_CCMR1_IC2PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ +#define GTIM_CCMR1_IC2F_MASK (0x0f << GTIM_CCMR1_IC2F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + +/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ + +#define GTIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ +#define GTIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ +#define GTIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ +#define GTIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ + +/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ + +#define GTIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ +#define GTIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ +#define GTIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ +#define GTIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ +#define GTIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ +#define GTIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ +#define GTIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ +#define GTIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ +#define GTIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ +#define GTIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ +#define GTIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ +#define GTIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ +#define GTIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ +#define GTIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ +#define GTIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ +#define GTIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +/* Capture/compare mode register 2 - Output Compare mode (TIM2-5 only) */ + +#define GTIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ +#define GTIM_CCMR2_CC3S_MASK (3 << GTIM_CCMR2_CC3S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions above) */ +#define GTIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ +#define GTIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ +#define GTIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ +#define GTIM_CCMR2_OC3M_MASK (7 << GTIM_CCMR2_OC3M_SHIFT) + /* (See common CCMR Output Compare Mode definitions above) */ +#define GTIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ +#define GTIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ +#define GTIM_CCMR2_CC4S_MASK (3 << GTIM_CCMR2_CC4S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions above) */ +#define GTIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ +#define GTIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ +#define GTIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ +#define GTIM_CCMR2_OC4M_MASK (7 << GTIM_CCMR2_OC4M_SHIFT) + /* (See common CCMR Output Compare Mode definitions above) */ +#define GTIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ + +/* Capture/compare mode register 2 - Input capture mode (TIM2-5 only) */ + + /* Bits 1-0 (Same as Output Compare Mode) */ +#define GTIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ +#define GTIM_CCMR2_IC3PSC_MASK (3 << GTIM_CCMR2_IC3PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ +#define GTIM_CCMR2_IC3F_MASK (0x0f << GTIM_CCMR2_IC3F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + /* Bits 9-8: (Same as Output Compare Mode) */ +#define GTIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11-10: Input Capture 4 Prescaler */ +#define GTIM_CCMR2_IC4PSC_MASK (3 << GTIM_CCMR2_IC4PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ +#define GTIM_CCMR2_IC4F_MASK (0x0f << GTIM_CCMR2_IC4F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + +/* Capture/compare enable register (TIM1 and TIM8, TIM2-5 and TIM9-14) */ + +#define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ +#define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ +#define GTIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable (TIM1 and TIM8 only) */ +#define GTIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 output Polarity (F2,F3,F4 and TIM15-17) */ +#define GTIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable (TIM2-5,9&12 only) */ +#define GTIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output polarity (TIM2-5,9&12 only) */ +#define GTIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 complementary output enable (TIM1 and TIM8 only) */ +#define GTIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 output Polarity (F2,F3,F4 and TIM2-5,9,12&15 only) */ +#define GTIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable (TIM2-5 only) */ +#define GTIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity (TIM2-5 only) */ +#define GTIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 complementary output enable (TIM1 and TIM8 only) */ +#define GTIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 output Polarity (F2,F4 and TIM2-5 only) */ +#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ +#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ +#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */ + +/* 16-bit counter register */ + +#define GTIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ +#define GTIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) + +/* DMA control register */ + +#define GTIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ +#define GTIM_DCR_DBA_MASK (0x1f << GTIM_DCR_DBA_SHIFT) +#define GTIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ +#define GTIM_DCR_DBL_MASK (0x1f << GTIM_DCR_DBL_SHIFT) + +/* Timer 2/5 option register */ + +#define TIM2_OR_ITR1_RMP_SHIFT (10) /* Bits 10-11: Internal trigger 1 remap */ +#define TIM2_OR_ITR1_RMP_MASK (3 << TIM2_OR_ITR1_RMP_SHIFT) +# define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */ +# define TIM2_OR_ITR1_PTP (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */ +# define TIM2_OR_ITR1_OTGFSSOF (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */ +# define TIM2_OR_ITR1_OTGHSSOF (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */ + +#define TIM5_OR_TI4_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ +#define TIM5_OR_TI4_RMP_MASK (3 << TIM5_OR_TI4_RMP_SHIFT) +# define TIM5_OR_TI4_GPIO (0 << TIM5_OR_TI4_RMP_SHIFT) /* 00: TIM5_CH4 input connected to GPIO */ +# define TIM5_OR_TI4_LSI (1 << TIM5_OR_TI4_RMP_SHIFT) /* 01: TIM5_CH4 input connected to LSI internal clock */ +# define TIM5_OR_TI4_LSE (2 << TIM5_OR_TI4_RMP_SHIFT) /* 10: TIM5_CH4 input connected to LSE internal clock */ +# define TIM5_OR_TI4_RTC (3 << TIM5_OR_TI4_RMP_SHIFT) /* 11: TIM5_CH4 input connected to RTC output event */ + +#define TIM11_OR_TI1_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ +#define TIM11_OR_TI1_RMP_MASK (3 << TIM11_OR_TI1_RMP_SHIFT) +# define TIM11_OR_TI1_GPIO (0 << TIM11_OR_TI1_RMP_SHIFT) /* 00-11: TIM11_CH1 input connected to GPIO */ +# define TIM11_OR_TI1_HSERTC (3 << TIM11_OR_TI1_RMP_SHIFT) /* 11: TIM11_CH1 input connected to HSE_RTC clock */ + + +/* Control register 1 */ + +#define BTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define BTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ +#define BTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ +#define BTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */ +#define BTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ + +/* Control register 2 */ + +#define BTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ +#define BTIM_CR2_MMS_MASK (7 << BTIM_CR2_MMS_SHIFT) +# define BTIM_CR2_RESET (0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */ +# define BTIM_CR2_ENAB (1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */ +# define BTIM_CR2_UPDT (2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */ + +/* DMA/Interrupt enable register */ + +#define BTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define BTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ + +/* Status register */ + +#define BTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ + +/* Event generation register */ + +#define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_TIM_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_uart.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..ea0c0dd29c144bb488e6adabbb8a407ee32d95c3 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_uart.h @@ -0,0 +1,371 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f74xxf77xx_uart.h + * + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_UART_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_UART_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate Register (32-bits) */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt & status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit data register */ + +/* Register Addresses ***************************************************************/ + +#if STM32F7_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) +#endif + +#if STM32F7_NUSART > 1 +# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) +#endif + +#if STM32F7_NUSART > 2 +# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART3_RTOR (STM32_USART3_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART3_RQR (STM32_USART3_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART3_ISR (STM32_USART3_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART3_ICR (STM32_USART3_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART3_RDR (STM32_USART3_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) +#endif + +#if STM32F7_NUSART > 3 +# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART6_RTOR (STM32_USART6_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART6_RQR (STM32_USART6_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART6_ISR (STM32_USART6_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART6_ICR (STM32_USART6_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART6_RDR (STM32_USART6_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART6_TDR (STM32_USART6_BASE+STM32_USART_TDR_OFFSET) +#endif + +#if STM32F7_NUART > 0 +# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) +# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_UART4_RTOR (STM32_UART4_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_UART4_RQR (STM32_UART4_BASE+STM32_USART_RQR_OFFSET) +# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_UART4_ISR (STM32_UART4_BASE+STM32_USART_ISR_OFFSET) +# define STM32_UART4_ICR (STM32_UART4_BASE+STM32_USART_ICR_OFFSET) +# define STM32_UART4_RDR (STM32_UART4_BASE+STM32_USART_RDR_OFFSET) +# define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) +#endif + +#if STM32F7_NUART > 1 +# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) +# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_UART5_RTOR (STM32_UART5_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_UART5_RQR (STM32_UART5_BASE+STM32_USART_RQR_OFFSET) +# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_UART5_ISR (STM32_UART5_BASE+STM32_USART_ISR_OFFSET) +# define STM32_UART5_ICR (STM32_UART5_BASE+STM32_USART_ICR_OFFSET) +# define STM32_UART5_RDR (STM32_UART5_BASE+STM32_USART_RDR_OFFSET) +# define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) +#endif + +#if STM32F7_NUART > 2 +# define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) +# define STM32_UART7_BRR (STM32_UART7_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART7_GTPR (STM32_UART7_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_UART7_RTOR (STM32_UART7_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_UART7_RQR (STM32_UART7_BASE+STM32_USART_RQR_OFFSET) +# define STM32_UART7_GTPR (STM32_UART7_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_UART7_ISR (STM32_UART7_BASE+STM32_USART_ISR_OFFSET) +# define STM32_UART7_ICR (STM32_UART7_BASE+STM32_USART_ICR_OFFSET) +# define STM32_UART7_RDR (STM32_UART7_BASE+STM32_USART_RDR_OFFSET) +# define STM32_UART7_TDR (STM32_UART7_BASE+STM32_USART_TDR_OFFSET) +#endif + +#if STM32F7_NUART > 3 +# define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) +# define STM32_UART8_BRR (STM32_UART8_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART8_GTPR (STM32_UART8_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_UART8_RTOR (STM32_UART8_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_UART8_RQR (STM32_UART8_BASE+STM32_USART_RQR_OFFSET) +# define STM32_UART8_GTPR (STM32_UART8_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_UART8_ISR (STM32_UART8_BASE+STM32_USART_ISR_OFFSET) +# define STM32_UART8_ICR (STM32_UART8_BASE+STM32_USART_ICR_OFFSET) +# define STM32_UART8_RDR (STM32_UART8_BASE+STM32_USART_RDR_OFFSET) +# define STM32_UART8_TDR (STM32_UART8_BASE+STM32_USART_TDR_OFFSET) +#endif + +/* Register Bitfield Definitions ****************************************************/ + +/* Control register 1 */ + +#define USART_CR1_UE (1 << 0) /* Bit 0: USART enable */ +#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ +#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ +#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ +#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ +#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ +#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ +#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ +#define USART_CR1_WAKE (1 << 11) /* Bit 11: Receiver wakeup method */ +#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length, bit 0 */ +#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */ +#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */ +#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ +#define USART_CR1_DEDT_SHIFT (16) /* Bits 16-20: Driver Enable deassertion time */ +#define USART_CR1_DEDT_MASK (31 << USART_CR1_DEDT_SHIFT) +# define USART_CR1_DEDT(n) ((uint32_t)(n) << USART_CR1_DEDT_SHIFT) +#define USART_CR1_DEAT_SHIFT (21) /* Bits 21-25: Driver Enable assertion time */ +#define USART_CR1_DEAT_MASK (31 << USART_CR1_DEAT_SHIFT) +# define USART_CR1_DEAT(n) ((uint32_t)(n) << USART_CR1_DEAT_SHIFT) +#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */ +#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of Block interrupt enable */ +#define USART_CR1_M1 (1 << 28) /* Bit 31: Word length, bit 1 */ + +#define USART_CR1_ALLINTS \ + (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\ + USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE) + +/* Control register 2 */ + +#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: :7-/4-bit Address Detection */ +#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ +#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ +#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ +#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ +#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ +#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ +#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) +# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ +# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ +# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ +#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ +#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */ +#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */ +#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */ +#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */ +#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */ +#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto baud rate enable */ +#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Auto baud rate mode */ +#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT) +# define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* Start bit */ +# define USART_CR2_ABRMOD_FALL (1 << USART_CR2_ABRMOD_SHIFT) /* Falling edge measurement */ +# define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 0x7F frame detection */ +# define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 0x55 frame detection */ +#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */ +#define USART_CR2_ADD4L_SHIFT (24) /* Bits 24-27: Address[3:0]:of the USART node */ +#define USART_CR2_ADD4L_MASK (15 << USART_CR2_ADD4L_SHIFT) +# define USART_CR2_ADD4L(n) ((uint32_t)(n) << USART_CR2_ADD4L_SHIFT) +#define USART_CR2_ADD4H_SHIFT (28) /* Bits 28-31: Address[4:0] of the USART node */ +#define USART_CR2_ADD4H_MASK (15 << USART_CR2_ADD4H_SHIFT) +# define USART_CR2_ADD4H(n) ((uint32_t)(n) << USART_CR2_ADD4H_SHIFT) +#define USART_CR2_ADD8_SHIFT (24) /* Bits 24-31: Address[7:0] of the USART node */ +#define USART_CR2_ADD8_MASK (255 << USART_CR2_ADD8_SHIFT) +# define USART_CR2_ADD8(n) ((uint32_t)(n) << USART_CR2_ADD8_SHIFT) + +/* Control register 3 */ + +#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ +#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ +#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ +#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ +#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ +#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ +#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ +#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ +#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ +#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ +#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ +#define USART_CR1_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ +#define USART_CR1_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */ +#define USART_CR1_DDRE (1 << 13) /* Bit 13: DMA Disable on Reception Error */ +#define USART_CR1_DEM (1 << 14) /* Bit 14: Driver enable mode */ +#define USART_CR1_DEP (1 << 15) /* Bit 15: Driver enable polarity selection */ +#define USART_CR1_SCARCNT_SHIFT (17) /* Bit 17-19: Smartcard auto-retry count */ +#define USART_CR1_SCARCNT_MASK (7 << USART_CR1_SCARCNT_SHIFT) +# define USART_CR1_SCARCNT(n) ((uint32_t)(n) << USART_CR1_SCARCNT_SHIFT) + +/* Baud Rate Register */ + +#define USART_BRR_SHIFT (0) /* Bits 0-15: USARTDIV[15:0] OVER8=0*/ +#define USART_BRR_MASK (0xffff << USART_BRR_SHIFT) +# define USART_BRR(n) ((uint32_t)(n) << USART_BRR_SHIFT) +#define USART_BRR_0_3_SHIFT (0) /* Bits 0-2: USARTDIV[3:0] OVER8=1 */ +#define USART_BRR_0_3_MASK (0x0fff << USART_BRR_0_3_SHIFT) +# define USART_BRR_0_3(n) ((uint32_t)(n) << USART_BRR_0_3_SHIFT) +#define USART_BRR_4_7_SHIFT (0) /* Bits 4-15: USARTDIV[15:4] OVER8=1*/ +#define USART_BRR_4_7_MASK (0xffff << USART_BRR_4_7_SHIFT) +# define USART_BRR_4_7(n) ((uint32_t)(n) << USART_BRR_4_7_SHIFT) + +/* Guard time and prescaler register */ + +#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ +#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) +# define USART_GTPR_PSC(n) ((uint32_t)(n) << USART_GTPR_PSC_SHIFT) +#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ +#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) +# define USART_GTPR_GT(n) ((uint32_t)(n) << USART_GTPR_GT_SHIFT) + +/* Receiver timeout register */ + +#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */ +#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT) +# define USART_RTOR_RTO(n) ((uint32_t)(n) << USART_RTOR_RTO_SHIFT) +#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block Length */ +#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) +# define USART_RTOR_BLEN(n) ((uint32_t)(n) << USART_RTOR_BLEN_SHIFT) + +/* Request register */ + +#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */ +#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send break request */ +#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */ +#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */ +#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */ + +/* Interrupt & status register */ + +#define USART_ISR_PE (1 << 0) /* Bit 0: Parity error */ +#define USART_ISR_FE (1 << 1) /* Bit 1: Framing error */ +#define USART_ISR_NF (1 << 2) /* Bit 2: Noise detected flag */ +#define USART_ISR_ORE (1 << 3) /* Bit 3: Overrun error */ +#define USART_ISR_IDLE (1 << 4) /* Bit 4: Idle line detected */ +#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read data register not empty */ +#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission complete */ +#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit data register empty */ +#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN break detection flag */ +#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS interrupt flag */ +#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS flag */ +#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout */ +#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block flag */ +#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate error */ +#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate flag */ +#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy flag */ +#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match flag */ +#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break flag */ +#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge flag */ + +#define USART_ISR_ALLBITS (0x0027dfff) + +/* Interrupt flag clear register */ + +#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */ +#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */ +#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected flag *clear flag */ +#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */ +#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */ +#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete */ +#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */ +#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS interrupt clear flag */ +#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */ +#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */ +#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */ + +#define USART_ICR_ALLBITS (0x00021b5f) + +/* Receive data register */ + +#define USART_RDR_SHIFT (0) /* Bits 8:0: Receive data value */ +#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT) + +/* Transmit data register */ + +#define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */ +#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) + +#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_UART_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h index ac5b3e339dd08b6519fbfa72be522b01a17c6408..4d90f7c96df1958c11fc86f2521ca9ab9000c2a9 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h @@ -95,7 +95,7 @@ #define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET) #define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) #define STM32_RCC_AHB1LPENR (STM32_RCC_BASE+STM32_RCC_AHB1LPENR_OFFSET) -#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE+STM32_RCC_AHB2LPENR) +#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE+STM32_RCC_AHB2LPENR_OFFSET) #define STM32_RCC_AHB3LPENR (STM32_RCC_BASE+STM32_RCC_AHB3LPENR_OFFSET) #define STM32_RCC_APB1LPENR (STM32_RCC_BASE+STM32_RCC_APB1LPENR_OFFSET) #define STM32_RCC_APB2LPENR (STM32_RCC_BASE+STM32_RCC_APB2LPENR_OFFSET) diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h index b58f2b20f6b4a6a9035fda3b32fa4801cf22f2e5..f94a4f1e734e025eac3ce2d9c7b1dec9d7ea2cb7 100644 --- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h @@ -95,7 +95,7 @@ #define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET) #define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) #define STM32_RCC_AHB1LPENR (STM32_RCC_BASE+STM32_RCC_AHB1LPENR_OFFSET) -#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE+STM32_RCC_AHB2LPENR) +#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE+STM32_RCC_AHB2LPENR_OFFSET) #define STM32_RCC_AHB3LPENR (STM32_RCC_BASE+STM32_RCC_AHB3LPENR_OFFSET) #define STM32_RCC_APB1LPENR (STM32_RCC_BASE+STM32_RCC_APB1LPENR_OFFSET) #define STM32_RCC_APB2LPENR (STM32_RCC_BASE+STM32_RCC_APB2LPENR_OFFSET) diff --git a/arch/arm/src/stm32f7/stm32_adc.c b/arch/arm/src/stm32f7/stm32_adc.c index c4db6aab4c92c276e424202b733c35ca3571b2ae..0d226ab46a3e462830b359bf2e52fa329af9a7e2 100644 --- a/arch/arm/src/stm32f7/stm32_adc.c +++ b/arch/arm/src/stm32f7/stm32_adc.c @@ -7,6 +7,7 @@ * Diego Sanchez * Paul Alexander Patience * David Sidrane + * Bob Feretich * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -85,7 +86,8 @@ /* This implementation is for the STM32 F7[4-7] only */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \ + defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /**************************************************************************** diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index 4dc26358dd169a0b950b1ff1199997aabe7a9926..a5d185944d547b5728037d867f7913287c5c4427 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -3,6 +3,7 @@ * * Copyright (C) 2015-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt + * Bob Feretich * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -59,7 +60,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM33F75XX) \ + || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /**************************************************************************** diff --git a/arch/arm/src/stm32f7/stm32_dma2d.c b/arch/arm/src/stm32f7/stm32_dma2d.c index 58b7e3d242ce45aab3a729d55786a154f061ae1b..f0ec2123395195801555101cd0d75d126f4cd237 100644 --- a/arch/arm/src/stm32f7/stm32_dma2d.c +++ b/arch/arm/src/stm32f7/stm32_dma2d.c @@ -53,7 +53,6 @@ #include #include -#include #include #include "up_arch.h" diff --git a/arch/arm/src/stm32f7/stm32_dma2d.h b/arch/arm/src/stm32f7/stm32_dma2d.h index 7e0f0213ad4178e5d9dec7ce44dc4de1c021d276..26d9f0faa8b63722de20fd70a05699b984d507f2 100644 --- a/arch/arm/src/stm32f7/stm32_dma2d.h +++ b/arch/arm/src/stm32f7/stm32_dma2d.h @@ -42,15 +42,290 @@ #include #include -#include +#include "stm32_ltdc.h" #ifdef CONFIG_STM32F7_DMA2D +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct ltdc_area_s; /* see arch/arm/src/stm32f7/stm32_ltdc.h */ + +/* Blend mode definitions */ + +enum dma2d_blend_e +{ + DMA2D_BLEND_NONE = 0, /* Disable all blend operation */ + DMA2D_BLEND_ALPHA = 0x1, /* Enable alpha blending */ + DMA2D_BLEND_PIXELALPHA = 0x2, /* Enable alpha blending from pixel color */ +}; + +/* The layer is controlled through the following structure */ + +struct dma2d_layer_s +{ + /* Name: getvideoinfo + * + * Description: + * Get video information about the layer + * + * Parameter: + * layer - Reference to the layer control structure + * vinfo - Reference to the video info structure + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getvideoinfo)(FAR struct dma2d_layer_s *layer, + FAR struct fb_videoinfo_s *vinfo); + + /* Name: getplaneinfo + * + * Description: + * Get plane information about the layer + * + * Parameter: + * layer - Reference to the layer control structure + * planeno - Number of the plane + * pinfo - Reference to the plane info structure + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getplaneinfo)(FAR struct dma2d_layer_s *layer, int planeno, + FAR struct fb_planeinfo_s *pinfo); + + /* Name: getlid + * + * Description: + * Get a specific layer identifier. + * + * Parameter: + * layer - Reference to the layer structure + * lid - Reference to store the layer id + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getlid)(FAR struct dma2d_layer_s *layer, int *lid); + +#ifdef CONFIG_STM32F7_DMA2D_L8 + /* Name: setclut + * + * Description: + * Configure layer clut (color lookup table). + * Non clut is defined during initializing. + * + * Parameter: + * layer - Reference to the layer structure + * cmap - color lookup table with up the 256 entries + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*setclut)(FAR struct dma2d_layer_s *layer, + const FAR struct fb_cmap_s *cmap); + + /* Name: getclut + * + * Description: + * Get configured layer clut (color lookup table). + * + * Parameter: + * layer - Reference to the layer structure + * cmap - Reference to valid color lookup table accept up the 256 color + * entries + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getclut)(FAR struct dma2d_layer_s *layer, FAR struct fb_cmap_s *cmap); +#endif + + /* Name: setalpha + * + * Description: + * Configure layer alpha value factor into blend operation. + * During the layer blend operation the source alpha value is multiplied + * with this alpha value. If the source color format doesn't support alpha + * channel (e.g. non ARGB8888) this alpha value will be used as constant + * alpha value for blend operation. + * Default value during initializing: 0xff + * + * Parameter: + * layer - Reference to the layer structure + * alpha - Alpha value + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*setalpha)(FAR struct dma2d_layer_s *layer, uint8_t alpha); + + /* Name: getalpha + * + * Description: + * Get configured layer alpha value factor for blend operation. + * + * Parameter: + * layer - Reference to the layer structure + * alpha - Reference to store the alpha value + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getalpha)(FAR struct dma2d_layer_s *layer, uint8_t *alpha); + + /* Name: setblendmode + * + * Description: + * Configure blend mode of the layer. + * Default mode during initializing: DMA2D_BLEND_NONE + * Blendmode is active after next update. + * + * Parameter: + * layer - Reference to the layer structure + * mode - Blend mode (see DMA2D_BLEND_*) + * + * Return: + * On success - OK + * On error - -EINVAL + * + * Procedure information: + * DMA2D_BLEND_NONE: + * Informs the driver to disable all blend operation for the given layer. + * That means the layer is opaque. + * + * DMA2D_BLEND_ALPHA: + * Informs the driver to enable alpha blending for the given layer. + * + * DMA2D_BLEND_PIXELALPHA: + * Informs the driver to use the pixel alpha value of the layer instead + * the constant alpha value. This is only useful for ARGB8888 + * color format. + */ + + int (*setblendmode)(FAR struct dma2d_layer_s *layer, uint32_t mode); + + /* Name: getblendmode + * + * Description: + * Get configured blend mode of the layer. + * + * Parameter: + * layer - Reference to the layer structure + * mode - Reference to store the blend mode + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getblendmode)(FAR struct dma2d_layer_s *layer, uint32_t *mode); + + /* Name: blit + * + * Description: + * Copy selected area from a source layer to selected position of the + * destination layer. + * + * Parameter: + * dest - Reference to the destination layer + * destxpos - Selected x target position of the destination layer + * destypos - Selected y target position of the destination layer + * src - Reference to the source layer + * srcarea - Reference to the selected area of the source layer + * + * Return: + * OK - On success + * -EINVAL - If one of the parameter invalid or if the size of the + * selected source area outside the visible area of the + * destination layer. (The visible area usually represents the + * display size) + * -ECANCELED - Operation cancelled, something goes wrong. + */ + + int (*blit)(FAR struct dma2d_layer_s *dest, + fb_coord_t destxpos, fb_coord_t destypos, + FAR const struct dma2d_layer_s *src, + FAR const struct ltdc_area_s *srcarea); + + /* Name: blend + * + * Description: + * Blends the selected area from a background layer with selected position + * of the foreground layer. Copies the result to the selected position of + * the destination layer. Note! The content of the foreground and background + * layer keeps unchanged as long destination layer is unequal to the + * foreground and background layer. + * + * Parameter: + * dest - Reference to the destination layer + * fore - Reference to the foreground layer + * forexpos - Selected x target position of the foreground layer + * foreypos - Selected y target position of the foreground layer + * back - Reference to the background layer + * backarea - Reference to the selected area of the background layer + * + * Return: + * OK - On success + * -EINVAL - If one of the parameter invalid or if the size of the + * selected source area outside the visible area of the + * destination layer. (The visible area usually represents the + * display size) + * -ECANCELED - Operation cancelled, something goes wrong. + */ + + int (*blend)(FAR struct dma2d_layer_s *dest, + fb_coord_t destxpos, fb_coord_t destypos, + FAR const struct dma2d_layer_s *fore, + fb_coord_t forexpos, fb_coord_t foreypos, + FAR const struct dma2d_layer_s *back, + FAR const struct ltdc_area_s *backarea); + + /* Name: fillarea + * + * Description: + * Fill the selected area of the whole layer with a specific color. + * + * Parameter: + * layer - Reference to the layer structure + * area - Reference to the valid area structure select the area + * color - Color to fill the selected area. Color must be formatted + * according to the layer pixel format. + * + * Return: + * OK - On success + * -EINVAL - If one of the parameter invalid or if the size of the + * selected area outside the visible area of the layer. + * -ECANCELED - Operation cancelled, something goes wrong. + */ + + int (*fillarea)(FAR struct dma2d_layer_s *layer, + FAR const struct ltdc_area_s *area, + uint32_t color); +}; + /**************************************************************************** * Public Functions ****************************************************************************/ -# ifdef CONFIG_STM32F7_LTDC_INTERFACE +struct stm32_ltdc_s; /* Forward declaration */ + /**************************************************************************** * Name: stm32_dma2dinitltdc * @@ -72,10 +347,89 @@ * ****************************************************************************/ -struct stm32_ltdc_s; // fwd decl - FAR struct dma2d_layer_s *stm32_dma2dinitltdc(FAR struct stm32_ltdc_s *layer); -# endif /* CONFIG_STM32F7_LTDC_INTERFACE */ + +/**************************************************************************** + * Name: up_dma2dgetlayer + * + * Description: + * Get a dma2d layer structure by the layer identifier + * + * Parameter: + * lid - Layer identifier + * + * Return: + * Reference to the dma2d layer control structure on success or Null if no + * related exist. + * + ****************************************************************************/ + +FAR struct dma2d_layer_s *up_dma2dgetlayer(int lid); + +/**************************************************************************** + * Name: up_dma2dcreatelayer + * + * Description: + * Create a new dma2d layer object to interact with the dma2d controller + * + * Parameter: + * width - Layer width + * height - Layer height + * fmt - Pixel format of the layer + * + * Return: + * On success - A valid dma2d layer reference + * On error - NULL and errno is set to + * -EINVAL if one of the parameter is invalid + * -ENOMEM if no memory available or exceeds + * CONFIG_STM32F7_DMA2D_NLAYERS + * + ****************************************************************************/ + +FAR struct dma2d_layer_s *up_dma2dcreatelayer(fb_coord_t width, + fb_coord_t height, + uint8_t fmt); + +/**************************************************************************** + * Name: up_dma2dremovelayer + * + * Description: + * Remove and deallocate the dma2d layer + * + * Parameter: + * layer - Reference to the layer to remove + * + * Return: + * On success - OK + * On error - -EINVAL + * + ****************************************************************************/ + +int up_dma2dremovelayer(FAR struct dma2d_layer_s *layer); + +/**************************************************************************** + * Name: up_dma2dinitialize + * + * Description: + * Initialize the dma2d controller + * + * Return: + * OK - On success + * An error if initializing failed. + * + ****************************************************************************/ + +int up_dma2dinitialize(void); + +/**************************************************************************** + * Name: up_dma2duninitialize + * + * Description: + * Uninitialize the dma2d controller + * + ****************************************************************************/ + +void up_dma2duninitialize(void); #endif /* CONFIG_STM32F7_DMA2D */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_DMA2D_H */ diff --git a/arch/arm/src/stm32f7/stm32_dtcm.h b/arch/arm/src/stm32f7/stm32_dtcm.h index 0b52bcf96c2fd64fee52861915b5ac3e2e29f09c..905a5c2b42c4a2608c606c25219e678c429a3443 100644 --- a/arch/arm/src/stm32f7/stm32_dtcm.h +++ b/arch/arm/src/stm32f7/stm32_dtcm.h @@ -1,9 +1,10 @@ /**************************************************************************** * arch/arm/src/stm32f7/stm32_dtcm.h * - * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * David Sidrane + * Bob Feretich * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -55,7 +56,8 @@ /* The STM32 F7 have DTCM memory */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \ + || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # define DTCM_START 0x20000000 # define DTCM_END 0x20010000 #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) diff --git a/arch/arm/src/stm32f7/stm32_dumpgpio.c b/arch/arm/src/stm32f7/stm32_dumpgpio.c index 79210b4e8e8094a88e5cb6c9d8ca5114648aa473..12f716316bb23423b8fdbe8f7e75f6726d10cfa8 100644 --- a/arch/arm/src/stm32f7/stm32_dumpgpio.c +++ b/arch/arm/src/stm32f7/stm32_dumpgpio.c @@ -1,8 +1,9 @@ /**************************************************************************** * arch/arm/src/stm32f7/stm32_gpio.c * - * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt + * Bob Feretich * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -58,6 +59,7 @@ */ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ + || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /**************************************************************************** diff --git a/arch/arm/src/stm32f7/stm32_exti_gpio.c b/arch/arm/src/stm32f7/stm32_exti_gpio.c index e388054515967d448d229e5a7126c01a1c53ab0c..e5c67e6f7d18e5edfb6d70934689c49fff6fd517 100644 --- a/arch/arm/src/stm32f7/stm32_exti_gpio.c +++ b/arch/arm/src/stm32f7/stm32_exti_gpio.c @@ -11,6 +11,7 @@ * Copyright (C) 2011 Uros Platise. All rights reserved. * Author: Gregory Nutt * Uros Platise + * Bob Feretich * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -65,7 +66,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \ + || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /**************************************************************************** diff --git a/arch/arm/src/stm32f7/stm32_gpio.c b/arch/arm/src/stm32f7/stm32_gpio.c index 17e8b4c10822e6ea958de283f2921ceca571e6a5..e9b3f0d8a9ad0d5d4a3c387b6665b6614954f3d5 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.c +++ b/arch/arm/src/stm32f7/stm32_gpio.c @@ -1,8 +1,9 @@ /**************************************************************************** * arch/arm/src/stm32f7/stm32_gpio.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt + * Bob Feretich * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -57,7 +58,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \ + || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /**************************************************************************** diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index aea7e7764c9c536fa074844cf7e01132398534b0..13eb58e76be9bb5be3122445b39d39cfe5a6dbac 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -8,9 +8,10 @@ * With extensions and modifications for the F1, F2, and F4 by: * * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. - * Authors: Gregroy Nutt + * Authors: Gregory Nutt * John Wharington * David Sidrane + * Bob Feretich * * Major rewrite of ISR and supporting methods, including support * for NACK and RELOAD by: @@ -159,6 +160,8 @@ * * One of: * + * CONFIG_STM32F7_STM32F72XX + * CONFIG_STM32F7_STM32F73XX * CONFIG_STM32F7_STM32F74XX * CONFIG_STM32F7_STM32F75XX * CONFIG_STM32F7_STM32F76XX @@ -195,6 +198,10 @@ * * References: * + * RM0431: + * ST STM32F72xxx and STM32F73xxx Reference Manual + * Document ID: DocID029480 Revision 1, Jan 2017. + * * RM0316: * ST STM32F76xxx and STM32F77xxx Reference Manual * Document ID: DocID028270 Revision 2, April 2016. diff --git a/arch/arm/src/stm32f7/stm32_ltdc.c b/arch/arm/src/stm32f7/stm32_ltdc.c index c979cc22e314998699a39df84ddee9d4ca3c7e39..3a992d928fad6ff71e94b686e2454a71390f4ec6 100644 --- a/arch/arm/src/stm32f7/stm32_ltdc.c +++ b/arch/arm/src/stm32f7/stm32_ltdc.c @@ -53,8 +53,6 @@ #include #include -#include -#include #include #include "up_arch.h" @@ -915,7 +913,6 @@ static const uintptr_t stm32_clutwr_layer_t[LTDC_NLAYERS] = static bool g_initialized; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -2192,7 +2189,7 @@ static void stm32_ltdc_linit(int lid) ****************************************************************************/ static int stm32_getvideoinfo(struct fb_vtable_s *vtable, - struct fb_videoinfo_s *vinfo) + struct fb_videoinfo_s *vinfo) { lcdinfo("vtable=%p vinfo=%p\n", vtable, vinfo); if (vtable) @@ -2227,7 +2224,7 @@ static int stm32_getvideoinfo(struct fb_vtable_s *vtable, ****************************************************************************/ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno, - struct fb_planeinfo_s *pinfo) + struct fb_planeinfo_s *pinfo) { lcdinfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo); if (vtable) @@ -2263,7 +2260,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno, #ifdef STM32_LAYER_CLUT_SIZE static int stm32_getcmap(struct fb_vtable_s *vtable, - struct fb_cmap_s *cmap) + struct fb_cmap_s *cmap) { #ifdef CONFIG_STM32F7_LTDC_L2 return stm32_getclut((FAR struct ltdc_layer_s *)&LAYER_L2, cmap); @@ -2289,7 +2286,7 @@ static int stm32_getcmap(struct fb_vtable_s *vtable, ****************************************************************************/ static int stm32_putcmap(struct fb_vtable_s *vtable, - const struct fb_cmap_s *cmap) + const struct fb_cmap_s *cmap) { #ifdef CONFIG_STM32F7_LTDC_L2 return stm32_setclut((FAR struct ltdc_layer_s *)&LAYER_L2, cmap); @@ -2316,7 +2313,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, ****************************************************************************/ static int stm32_lgetvideoinfo(struct ltdc_layer_s *layer, - struct fb_videoinfo_s *vinfo) + struct fb_videoinfo_s *vinfo) { lcdinfo("layer=%p vinfo=%p\n", layer, vinfo); FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; @@ -2350,7 +2347,7 @@ static int stm32_lgetvideoinfo(struct ltdc_layer_s *layer, ****************************************************************************/ static int stm32_lgetplaneinfo(struct ltdc_layer_s *layer, int planeno, - struct fb_planeinfo_s *pinfo) + struct fb_planeinfo_s *pinfo) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; @@ -2385,7 +2382,7 @@ static int stm32_lgetplaneinfo(struct ltdc_layer_s *layer, int planeno, #ifdef STM32_LAYER_CLUT_SIZE static int stm32_setclut(struct ltdc_layer_s *layer, - const struct fb_cmap_s *cmap) + const struct fb_cmap_s *cmap) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; int ret; @@ -3019,9 +3016,9 @@ static int stm32_getblendmode(FAR struct ltdc_layer_s *layer, uint32_t *mode) ****************************************************************************/ static int stm32_setarea(FAR struct ltdc_layer_s *layer, - FAR const struct ltdc_area_s *area, - fb_coord_t srcxpos, - fb_coord_t srcypos) + FAR const struct ltdc_area_s *area, + fb_coord_t srcxpos, + fb_coord_t srcypos) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; @@ -3076,8 +3073,8 @@ static int stm32_setarea(FAR struct ltdc_layer_s *layer, ****************************************************************************/ static int stm32_getarea(FAR struct ltdc_layer_s *layer, - FAR struct ltdc_area_s *area, - fb_coord_t *srcxpos, fb_coord_t *srcypos) + FAR struct ltdc_area_s *area, + fb_coord_t *srcxpos, fb_coord_t *srcypos) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; @@ -3332,11 +3329,11 @@ static int stm32_blit(FAR struct ltdc_layer_s *dest, ****************************************************************************/ static int stm32_blend(FAR struct ltdc_layer_s *dest, - fb_coord_t destxpos, fb_coord_t destypos, - FAR const struct dma2d_layer_s *fore, - fb_coord_t forexpos, fb_coord_t foreypos, - FAR const struct dma2d_layer_s *back, - FAR const struct ltdc_area_s *backarea) + fb_coord_t destxpos, fb_coord_t destypos, + FAR const struct dma2d_layer_s *fore, + fb_coord_t forexpos, fb_coord_t foreypos, + FAR const struct dma2d_layer_s *back, + FAR const struct ltdc_area_s *backarea) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)dest; @@ -3381,8 +3378,8 @@ static int stm32_blend(FAR struct ltdc_layer_s *dest, ****************************************************************************/ static int stm32_fillarea(FAR struct ltdc_layer_s *layer, - FAR const struct ltdc_area_s *area, - uint32_t color) + FAR const struct ltdc_area_s *area, + uint32_t color) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; diff --git a/arch/arm/src/stm32f7/stm32_ltdc.h b/arch/arm/src/stm32f7/stm32_ltdc.h index 9ebdd5cf659870da4324e2be0a2289a0b627014c..8b3593e86da3e41f81cf289861d4b805301dafcb 100644 --- a/arch/arm/src/stm32f7/stm32_ltdc.h +++ b/arch/arm/src/stm32f7/stm32_ltdc.h @@ -49,14 +49,504 @@ #include #include -#include - #ifdef CONFIG_STM32F7_LTDC /************************************************************************************ * Public Types ************************************************************************************/ +struct dma2d_layer_s; /* see arch/arm/src/stm32f7/stm32_dma2d.h */ + +/* Blend mode definitions */ + +enum ltdc_blend_e +{ + LTDC_BLEND_NONE = 0, /* Disable all blend operation */ + LTDC_BLEND_ALPHA = 0x1, /* Enable alpha blending */ + LTDC_BLEND_PIXELALPHA = 0x2, /* Enable alpha blending from pixel color */ + LTDC_BLEND_COLORKEY = 0x4, /* Enable colorkey */ + LTDC_BLEND_ALPHAINV = 0x8, /* Inverse alpha blending of source */ + LTDC_BLEND_PIXELALPHAINV = 0x10 /* Invers pixel alpha blending of source */ +}; + +/* layer control definitions */ + +enum ltdc_layer_e +{ + LTDC_LAYER_OWN = 0, /* The given layer */ + LTDC_LAYER_TOP = 0x1, /* The initialized top layer */ + LTDC_LAYER_BOTTOM = 0x2, /* the initialized bottom layer */ + LTDC_LAYER_ACTIVE = 0x4, /* The current visible flip layer */ + LTDC_LAYER_INACTIVE = 0x8 /* The current invisible flip layer */ +#ifdef CONFIG_STM32F7_DMA2D + ,LTDC_LAYER_DMA2D = 0x10 /* The dma2d interface layer id */ +#endif +}; + +/* Update operation flag */ + +enum ltdc_update_e +{ + LTDC_UPDATE_NONE = 0, /* Update given layer only */ + LTDC_UPDATE_SIM = 0x1, /* Update both layer simultaneous */ + LTDC_UPDATE_FLIP = 0x2, /* Perform flip operation */ + LTDC_UPDATE_ACTIVATE = 0x4 /* Set the given layer to the active layer */ +}; + +/* sync mode definitions */ + +enum ltdc_sync_e +{ + LTDC_SYNC_NONE = 0, /* Immediately */ + LTDC_SYNC_VBLANK = 0x100, /* Upon vertical sync */ + LTDC_SYNC_WAIT = 0x200 /* Waits upon vertical sync */ +}; + +/* Definition of the visible layer position and size */ + +struct ltdc_area_s +{ + fb_coord_t xpos; /* X position in pixel */ + fb_coord_t ypos; /* Y position in pixel */ + fb_coord_t xres; /* X resolution in pixel */ + fb_coord_t yres; /* Y resolution in pixel */ +}; + +/* The layer is controlled through the following structure */ + +struct ltdc_layer_s +{ + /* Name: getvideoinfo + * + * Description: + * Get video information about the layer + * + * Parameter: + * layer - Reference to the layer control structure + * vinfo - Reference to the video info structure + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getvideoinfo)(FAR struct ltdc_layer_s *layer, + FAR struct fb_videoinfo_s *vinfo); + + /* Name: getplaneinfo + * + * Description: + * Get plane information about the layer + * + * Parameter: + * layer - Reference to the layer control structure + * planeno - Number of the plane + * pinfo - Reference to the plane info structure + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getplaneinfo)(FAR struct ltdc_layer_s *layer, int planeno, + FAR struct fb_planeinfo_s *pinfo); + + /* Name: getlid + * + * Description: + * Get a specific layer identifier. + * + * Parameter: + * layer - Reference to the layer structure + * lid - Reference to store the layer id + * flag - Operation flag describe the layer identifier + * e.g. get the current active or inactive layer. + * See LTDC_LAYER_* for possible values + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getlid)(FAR struct ltdc_layer_s *layer, int *lid, uint32_t flag); + +#ifdef CONFIG_FB_CMAP + /* Name: setclut + * + * Description: + * Configure layer clut (color lookup table). + * Non clut is defined during initializing. + * Clut is active during next vertical blank period. Do not need an update. + * + * Parameter: + * layer - Reference to the layer structure + * cmap - color lookup table with up the 256 entries + * enable - Enable or disable clut support (if false cmap is ignored and can + * be NULL) + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*setclut)(FAR struct ltdc_layer_s *layer, + const FAR struct fb_cmap_s *cmap); + + /* Name: getclut + * + * Description: + * Get configured layer clut (color lookup table). + * + * Parameter: + * layer - Reference to the layer structure + * cmap - Reference to valid color lookup table accept up the 256 color + * entries + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getclut)(FAR struct ltdc_layer_s *layer, FAR struct fb_cmap_s *cmap); +#endif + + /* Name: setcolor + * + * Description: + * Configure layer color for the non active layer area. + * Default value during initializing: 0x00000000 + * Color is active after next update. + * + * Parameter: + * layer - Reference to the layer structure + * argb - ARGB8888 color value + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*setcolor)(FAR struct ltdc_layer_s *layer, uint32_t argb); + + /* Name: getcolor + * + * Description: + * Get configured layer color for the non active layer area. + * + * Parameter: + * layer - Reference to the layer structure + * argb - Reference to store the ARGB8888 color value + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getcolor)(FAR struct ltdc_layer_s *layer, uint32_t *argb); + + /* Name: setcolorkey + * + * Description: + * Configure the layer color key (chromakey) for transparence. + * Default value during initializing: 0x00000000 + * Colorkey is active after next update. + * + * Parameter: + * layer - Reference to the layer structure + * rgb - RGB888 color key + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*setcolorkey)(FAR struct ltdc_layer_s *layer, uint32_t rgb); + + /* Name: getcolorkey + * + * Description: + * Get the configured layer color key (chromakey) for transparence. + * + * Parameter: + * layer - Reference to the layer structure + * rgb - Reference to store the RGB888 color key + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getcolorkey)(FAR struct ltdc_layer_s *layer, uint32_t *rgb); + + /* Name: setalpha + * + * Description: + * Configure layer alpha value factor into blend operation. + * During the layer blend operation the source alpha value is multiplied + * with this alpha value. If the source color format doesn't support alpha + * channel (e.g. non ARGB8888) this alpha value will be used as constant + * alpha value for blend operation. + * Default value during initializing: 0xff + * Alpha is active after next update. + * + * Parameter: + * layer - Reference to the layer structure + * alpha - Alpha value + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*setalpha)(FAR struct ltdc_layer_s *layer, uint8_t alpha); + + /* Name: getalpha + * + * Description: + * Get configured layer alpha value factor for blend operation. + * + * Parameter: + * layer - Reference to the layer structure + * alpha - Reference to store the alpha value + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getalpha)(FAR struct ltdc_layer_s *layer, uint8_t *alpha); + + /* Name: setblendmode + * + * Description: + * Configure blend mode of the layer. + * Default mode during initializing: LTDC_BLEND_NONE + * Blendmode is active after next update. + * + * Parameter: + * layer - Reference to the layer structure + * mode - Blend mode (see LTDC_BLEND_*) + * + * Return: + * On success - OK + * On error - -EINVAL + * + * Procedure information: + * LTDC_BLEND_NONE: + * Informs the driver to disable all blend operation for the given layer. + * That means the layer is opaque. Note this has no effect on the + * colorkey settings. + * + * LTDC_BLEND_ALPHA: + * Informs the driver to enable alpha blending for the given layer. + * + * LTDC_BLEND_COLORKEY: + * Informs the driver to enable colorkeying for the given layer. + * + * LTDC_BLEND_SRCPIXELALPHA: + * Informs the driver to use the pixel alpha value of the layer instead + * the constant alpha value. This is only useful for ARGB8888 + * color format. + * + * LTDC_BLEND_DESTPIXELALPHA: + * Informs the driver to use the pixel alpha value of the subjacent layer + * instead the constant alpha value. This is only useful for ARGB8888 + * color format. + */ + + int (*setblendmode)(FAR struct ltdc_layer_s *layer, uint32_t mode); + + /* Name: getblendmode + * + * Description: + * Get configured blend mode of the layer. + * + * Parameter: + * layer - Reference to the layer structure + * mode - Reference to store the blend mode + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getblendmode)(FAR struct ltdc_layer_s *layer, uint32_t *mode); + + /* Name: setarea + * + * Description: + * Configure visible layer area and the reference position of the first + * pixel of the whole layer which is the first visible top left pixel in + * the active area. + * Default value during initializing: + * xpos = 0 + * ypos = 0 + * xres = display x resolution + * yres = display y resolution + * + * Area is active after next update. + * + * Parameter: + * layer - Reference to the layer control structure + * area - Reference to the valid area structure for the new active area + * srcxpos - x position of the visible pixel of the whole layer + * srcypos - y position of the visible pixel of the whole layer + * + * Return: + * On success - OK + * On error - -EINVAL + * + * Procedure Information: + * If the srcxpos and srcypos unequal the xpos and ypos of the coord + * structure this acts like moving the visible area to another position on + * the screen during the next update operation. + */ + + int (*setarea)(FAR struct ltdc_layer_s *layer, + FAR const struct ltdc_area_s *area, + fb_coord_t srcxpos, + fb_coord_t srcypos); + + /* Name: getarea + * + * Description: + * Get configured visible layer area. + * + * Parameter: + * layer - Reference to the layer control structure + * area - Reference to the area structure to store the active area + * srcxpos - Reference to store the referenced x position of the whole layer + * srcypos - Reference to store the reterenced y position of the whole layer + * + * Return: + * On success - OK + * On error - -EINVAL + */ + + int (*getarea)(FAR struct ltdc_layer_s *layer, + FAR struct ltdc_area_s *area, + fb_coord_t *srcxpos, + fb_coord_t *srcypos); + + /* Name: update + * + * Description: + * Update current layer settings and make changes visible. + * + * Parameter: + * layer - Reference to the layer structure + * mode - operation mode (see LTDC_UPDATE_*) + * + * Return: + * OK - On success + * -EINVAL - If one of the parameter invalid + * -ECANCELED - Operation cancelled, something goes wrong + * + * Procedure information: + * LTDC_UPDATE_SIM: + * Informs the driver to update both ltdc layers simultaneously. Otherwise + * update the given layer only. + * + * LTDC_UPDATE_FLIP: + * Informs the driver to perform a flip operation. + * This only effects the ltdc layer 1 and 2 and can be useful for double + * buffering. Each flip operation changed the active layer ot the inactive + * and vice versa. In the context of the ltdc that means, the inactive layer + * is complete disabled. So the subjacent layer is the background layer + * (background color). To reactivate both layer and their settings perform + * an update without LTDC_UPDATE_FLIP flag. + * + * LTDC_UPDATE_ACTIVATE: + * Informs the driver that the given layer should be the active layer when + * the operation is complete. + * + * LTDC_SYNC_VBLANK: + * Informs the driver to update the layer upon vertical blank. Otherwise + * immediately. + */ + + int (*update)(FAR struct ltdc_layer_s *layer, uint32_t mode); + +#ifdef CONFIG_STM32F7_DMA2D + /* Name: blit + * + * Description: + * Copy selected area from a source layer to selected position of the + * destination layer. + * + * Parameter: + * dest - Reference to the destination layer + * destxpos - Selected x position of the destination layer + * destypos - Selected y position of the destination layer + * src - Reference to the source layer + * srcarea - Reference to the selected area of the source layer + * + * Return: + * OK - On success + * -EINVAL - If one of the parameter invalid or if the size of the selected + * source area outside the visible area of the destination layer. + * (The visible area usually represents the display size) + */ + + int (*blit)(FAR struct ltdc_layer_s *dest, + fb_coord_t destxpos, fb_coord_t destypos, + FAR const struct dma2d_layer_s *src, + FAR const struct ltdc_area_s *srcarea); + + /* Name: blend + * + * Description: + * Blends the selected area from a foreground layer with selected position + * of the background layer. Copy the result to the destination layer. Note! + * The content of the foreground and background layer is not changed. + * + * Parameter: + * dest - Reference to the destination layer + * destxpos - Selected x position of the destination layer + * destypos - Selected y position of the destination layer + * fore - Reference to the foreground layer + * forexpos - Selected x position of the foreground layer + * foreypos - Selected y position of the foreground layer + * back - Reference to the background layer + * backarea - Reference to the selected area of the background layer + * + * Return: + * OK - On success + * -EINVAL - If one of the parameter invalid or if the size of the selected + * source area outside the visible area of the destination layer. + * (The visible area usually represents the display size) + */ + + int (*blend)(FAR struct ltdc_layer_s *dest, + fb_coord_t destxpos, fb_coord_t destypos, + FAR const struct dma2d_layer_s *fore, + fb_coord_t forexpos, fb_coord_t foreypos, + FAR const struct dma2d_layer_s *back, + FAR const struct ltdc_area_s *backarea); + + /* Name: fillarea + * + * Description: + * Fill the selected area of the whole layer with a specific color. + * + * Parameter: + * layer - Reference to the layer structure + * area - Reference to the valid area structure select the area + * color - Color to fill the selected area. Color must be formatted + * according to the layer pixel format. + * + * Return: + * OK - On success + * -EINVAL - If one of the parameter invalid or if the size of the selected + * area outside the visible area of the layer. + */ + + int (*fillarea)(FAR struct ltdc_layer_s *layer, + FAR const struct ltdc_area_s *area, + uint32_t color); +#endif +}; + /* Common layer state structure for the LTDC and DMA2D controller */ struct stm32_ltdc_s diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index 1ee746da2dc7737306c3c0959b3b3c8750a8fa5e..515819b9f71611b5e4f304b3587c6f4a17a4bab4 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -4358,7 +4358,7 @@ static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s #ifdef CONFIG_USBDEV_DMA static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes) { - usbtrace(TRACE_EPALLOCBUFFER, privep->epphy); + usbtrace(TRACE_EPALLOCBUFFER, ((FAR struct stm32_ep_s *)ep)->epphy); #ifdef CONFIG_USBDEV_DMAMEMORY return usbdev_dma_alloc(bytes); @@ -4379,7 +4379,7 @@ static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes) #ifdef CONFIG_USBDEV_DMA static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf) { - usbtrace(TRACE_EPFREEBUFFER, privep->epphy); + usbtrace(TRACE_EPALLOCBUFFER, ((FAR struct stm32_ep_s *)ep)->epphy); #ifdef CONFIG_USBDEV_DMAMEMORY usbdev_dma_free(buf); diff --git a/arch/arm/src/stm32f7/stm32_rcc.c b/arch/arm/src/stm32f7/stm32_rcc.c index a64ce09ed64c4e5d13b93fbbcfb42d65932bd7a6..4c1b4f3621e63a1ea800a076ffa2a4d8be1bb014 100644 --- a/arch/arm/src/stm32f7/stm32_rcc.c +++ b/arch/arm/src/stm32f7/stm32_rcc.c @@ -75,7 +75,9 @@ /* Include chip-specific clocking initialization logic */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +# include "chip/stm32f72xx73xx_rcc.c" +#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) # include "stm32f74xx75xx_rcc.c" #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) # include "stm32f76xx77xx_rcc.c" diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index f400a9b379c409481aa464cf2bf073f8c9839667..3f639e178ef302d4e824be6427490285c20515a1 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -211,6 +211,8 @@ #if defined(CONFIG_PM) && !defined(CONFIG_PM_SERIAL_ACTIVITY) # define CONFIG_PM_SERIAL_ACTIVITY 10 +#endif +#if defined(CONFIG_PM) # define PM_IDLE_DOMAIN 0 /* Revisit */ #endif diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c new file mode 100644 index 0000000000000000000000000000000000000000..39c9b188059213e11d226c5b7afe5bc89bf60dc4 --- /dev/null +++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c @@ -0,0 +1,1022 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c + * + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "stm32_pwr.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. Normally this is very fast, but I have seen at least one + * board that required this long, long timeout for the HSE to be ready. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/* Same for HSI */ + +#define HSIRDY_TIMEOUT HSERDY_TIMEOUT + +/* HSE divisor to yield ~1MHz RTC clock */ + +#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000 + +/* FLASH wait states */ + +#if !defined(BOARD_FLASH_WAITSTATES) +# error BOARD_FLASH_WAITSTATES not defined +#elif BOARD_FLASH_WAITSTATES < 0 || BOARD_FLASH_WAITSTATES > 15 +# error BOARD_FLASH_WAITSTATES is out of range +#endif + +/* Voltage output scale (default to Scale 1 mode) */ + +#ifndef STM32_PWR_VOS_SCALE +# define STM32_PWR_VOS_SCALE PWR_CR1_VOS_SCALE_1 +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_reset + * + * Description: + * Reset the RCC clock configuration to the default reset state + * + ****************************************************************************/ + +static inline void rcc_reset(void) +{ + uint32_t regval; + + /* Enable the Internal High Speed clock (HSI) */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_HSION; + putreg32(regval, STM32_RCC_CR); + + /* Reset CFGR register */ + + putreg32(0x00000000, STM32_RCC_CFGR); + + /* Reset HSION, HSEON, CSSON and PLLON bits */ + + regval = getreg32(STM32_RCC_CR); + regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); + putreg32(regval, STM32_RCC_CR); + + /* Reset PLLCFGR register to reset default */ + + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); + + /* Reset HSEBYP bit */ + + regval = getreg32(STM32_RCC_CR); + regval &= ~RCC_CR_HSEBYP; + putreg32(regval, STM32_RCC_CR); + + /* Disable all interrupts */ + + putreg32(0x00000000, STM32_RCC_CIR); +} + +/**************************************************************************** + * Name: rcc_enableahb1 + * + * Description: + * Enable selected AHB1 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb1(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB1ENR register to enabled the + * selected AHB1 peripherals. + */ + + regval = getreg32(STM32_RCC_AHB1ENR); + + /* Enable GPIOA, GPIOB, .... GPIOI */ + +#if STM32F7_NGPIO > 0 + regval |= (RCC_AHB1ENR_GPIOAEN +#if STM32F7_NGPIO > 1 + | RCC_AHB1ENR_GPIOBEN +#endif +#if STM32F7_NGPIO > 2 + | RCC_AHB1ENR_GPIOCEN +#endif +#if STM32F7_NGPIO > 3 + | RCC_AHB1ENR_GPIODEN +#endif +#if STM32F7_NGPIO > 4 + | RCC_AHB1ENR_GPIOEEN +#endif +#if STM32F7_NGPIO > 5 + | RCC_AHB1ENR_GPIOFEN +#endif +#if STM32F7_NGPIO > 6 + | RCC_AHB1ENR_GPIOGEN +#endif +#if STM32F7_NGPIO > 7 + | RCC_AHB1ENR_GPIOHEN +#endif +#if STM32F7_NGPIO > 8 + | RCC_AHB1ENR_GPIOIEN +#endif +#if STM32F7_NGPIO > 9 + | RCC_AHB1ENR_GPIOJEN +#endif +#if STM32F7_NGPIO > 10 + | RCC_AHB1ENR_GPIOKEN +#endif + ); +#endif + +#ifdef CONFIG_STM32F7_CRC + /* CRC clock enable */ + + regval |= RCC_AHB1ENR_CRCEN; +#endif + +#ifdef CONFIG_STM32F7_BKPSRAM + /* Backup SRAM clock enable */ + + regval |= RCC_AHB1ENR_BKPSRAMEN; +#endif + +#ifdef CONFIG_ARMV7M_DTCM + /* DTCM data RAM clock enable */ + + regval |= RCC_AHB1ENR_DTCMRAMEN; +#endif + +#ifdef CONFIG_STM32F7_DMA1 + /* DMA 1 clock enable */ + + regval |= RCC_AHB1ENR_DMA1EN; +#endif + +#ifdef CONFIG_STM32F7_DMA2 + /* DMA 2 clock enable */ + + regval |= RCC_AHB1ENR_DMA2EN; +#endif + +#ifdef CONFIG_STM32F7_DMA2D + /* DMA2D clock */ + + regval |= RCC_AHB1ENR_DMA2DEN; +#endif + +#ifdef CONFIG_STM32F7_ETHMAC + /* Ethernet MAC clocking */ + + regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | \ + RCC_AHB1ENR_ETHMACRXEN); + +#ifdef CONFIG_STM32F7_ETH_PTP + /* Precision Time Protocol (PTP) */ + + regval |= RCC_AHB1ENR_ETHMACPTPEN; + +#endif +#endif + +#ifdef CONFIG_STM32F7_OTGHS +#ifdef BOARD_ENABLE_USBOTG_HSULPI + /* Enable clocking for USB OTG HS and external PHY */ + + regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN); +#else + /* Enable only clocking for USB OTG HS */ + + regval |= RCC_AHB1ENR_OTGHSEN; +#endif +#endif /* CONFIG_STM32F7_OTGHS */ + + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableahb2 + * + * Description: + * Enable selected AHB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb2(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB2ENR register to enabled the + * selected AHB2 peripherals. + */ + + regval = getreg32(STM32_RCC_AHB2ENR); + +#ifdef CONFIG_STM32F7_DCMI + /* Camera interface enable */ + + regval |= RCC_AHB2ENR_DCMIEN; +#endif + +#ifdef CONFIG_STM32F7_CRYP + /* Cryptographic modules clock enable */ + + regval |= RCC_AHB2ENR_CRYPEN; +#endif + +#ifdef CONFIG_STM32F7_HASH + /* Hash modules clock enable */ + + regval |= RCC_AHB2ENR_HASHEN; +#endif + +#ifdef CONFIG_STM32F7_RNG + /* Random number generator clock enable */ + + regval |= RCC_AHB2ENR_RNGEN; +#endif + +#ifdef CONFIG_STM32F7_OTGFS + /* USB OTG FS clock enable */ + + regval |= RCC_AHB2ENR_OTGFSEN; +#endif + + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableahb3 + * + * Description: + * Enable selected AHB3 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb3(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB3ENR register to enabled the + * selected AHB3 peripherals. + */ + + regval = getreg32(STM32_RCC_AHB3ENR); + +#ifdef CONFIG_STM32F7_FMC + /* Flexible static memory controller module clock enable */ + + regval |= RCC_AHB3ENR_FMCEN; +#endif + +#ifdef CONFIG_STM32F7_QUADSPI + /* FQuad SPI memory controller clock enable */ + + regval |= RCC_AHB3ENR_QSPIEN; +#endif + + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb1 + * + * Description: + * Enable selected APB1 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb1(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB1ENR register to enabled the + * selected APB1 peripherals. + */ + + regval = getreg32(STM32_RCC_APB1ENR); + +#ifdef CONFIG_STM32F7_TIM2 + /* TIM2 clock enable */ + + regval |= RCC_APB1ENR_TIM2EN; +#endif + +#ifdef CONFIG_STM32F7_TIM3 + /* TIM3 clock enable */ + + regval |= RCC_APB1ENR_TIM3EN; +#endif + +#ifdef CONFIG_STM32F7_TIM4 + /* TIM4 clock enable */ + + regval |= RCC_APB1ENR_TIM4EN; +#endif + +#ifdef CONFIG_STM32F7_TIM5 + /* TIM5 clock enable */ + + regval |= RCC_APB1ENR_TIM5EN; +#endif + +#ifdef CONFIG_STM32F7_TIM6 + /* TIM6 clock enable */ + + regval |= RCC_APB1ENR_TIM6EN; +#endif + +#ifdef CONFIG_STM32F7_TIM7 + /* TIM7 clock enable */ + + regval |= RCC_APB1ENR_TIM7EN; +#endif + +#ifdef CONFIG_STM32F7_TIM12 + /* TIM12 clock enable */ + + regval |= RCC_APB1ENR_TIM12EN; +#endif + +#ifdef CONFIG_STM32F7_TIM13 + /* TIM13 clock enable */ + + regval |= RCC_APB1ENR_TIM13EN; +#endif + +#ifdef CONFIG_STM32F7_TIM14 + /* TIM14 clock enable */ + + regval |= RCC_APB1ENR_TIM14EN; +#endif + +#ifdef CONFIG_STM32F7_LPTIM1 + /* Low-power timer 1 clock enable */ + + regval |= RCC_APB1ENR_LPTIM1EN; +#endif + +#ifdef CONFIG_STM32F7_WWDG + /* Window watchdog clock enable */ + + regval |= RCC_APB1ENR_WWDGEN; +#endif + +#ifdef CONFIG_STM32F7_SPI2 + /* SPI2 clock enable */ + + regval |= RCC_APB1ENR_SPI2EN; +#endif + +#ifdef CONFIG_STM32F7_SPI3 + /* SPI3 clock enable */ + + regval |= RCC_APB1ENR_SPI3EN; +#endif + +#ifdef CONFIG_STM32F7_SPDIFRX + /* SPDIFRX clock enable */ + + regval |= RCC_APB1ENR_SPDIFRXEN; +#endif + +#ifdef CONFIG_STM32F7_USART2 + /* USART 2 clock enable */ + + regval |= RCC_APB1ENR_USART2EN; +#endif + +#ifdef CONFIG_STM32F7_USART3 + /* USART3 clock enable */ + + regval |= RCC_APB1ENR_USART3EN; +#endif + +#ifdef CONFIG_STM32F7_UART4 + /* UART4 clock enable */ + + regval |= RCC_APB1ENR_UART4EN; +#endif + +#ifdef CONFIG_STM32F7_UART5 + /* UART5 clock enable */ + + regval |= RCC_APB1ENR_UART5EN; +#endif + +#ifdef CONFIG_STM32F7_I2C1 + /* I2C1 clock enable */ + + regval |= RCC_APB1ENR_I2C1EN; +#endif + +#ifdef CONFIG_STM32F7_I2C2 + /* I2C2 clock enable */ + + regval |= RCC_APB1ENR_I2C2EN; +#endif + +#ifdef CONFIG_STM32F7_I2C3 + /* I2C3 clock enable */ + + regval |= RCC_APB1ENR_I2C3EN; +#endif + +#ifdef CONFIG_STM32F7_I2C4 + /* I2C4 clock enable */ + + regval |= RCC_APB1ENR_I2C4EN; +#endif + +#ifdef CONFIG_STM32F7_CAN1 + /* CAN 1 clock enable */ + + regval |= RCC_APB1ENR_CAN1EN; +#endif + +#ifdef CONFIG_STM32F7_CAN2 + /* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */ + + regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN); +#endif + +#ifdef CONFIG_STM32F7_CEC + /* CEC clock enable. */ + + regval |= RCC_APB1ENR_CECEN; +#endif + + /* Power interface clock enable. The PWR block is always enabled so that + * we can set the internal voltage regulator for maximum performance. + */ + + regval |= RCC_APB1ENR_PWREN; + +#if defined (CONFIG_STM32F7_DAC1) || defined(CONFIG_STM32F7_DAC2) + /* DAC interface clock enable */ + + regval |= RCC_APB1ENR_DACEN; +#endif + +#ifdef CONFIG_STM32F7_UART7 + /* UART7 clock enable */ + + regval |= RCC_APB1ENR_UART7EN; +#endif + +#ifdef CONFIG_STM32F7_UART8 + /* UART8 clock enable */ + + regval |= RCC_APB1ENR_UART8EN; +#endif + + putreg32(regval, STM32_RCC_APB1ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb2 + * + * Description: + * Enable selected APB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb2(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB2ENR register to enabled the + * selected APB2 peripherals. + */ + + regval = getreg32(STM32_RCC_APB2ENR); + +#ifdef CONFIG_STM32F7_TIM1 + /* TIM1 clock enable */ + + regval |= RCC_APB2ENR_TIM1EN; +#endif + +#ifdef CONFIG_STM32F7_TIM8 + /* TIM8 clock enable */ + + regval |= RCC_APB2ENR_TIM8EN; +#endif + +#ifdef CONFIG_STM32F7_USART1 + /* USART1 clock enable */ + + regval |= RCC_APB2ENR_USART1EN; +#endif + +#ifdef CONFIG_STM32F7_USART6 + /* USART6 clock enable */ + + regval |= RCC_APB2ENR_USART6EN; +#endif + +#ifdef CONFIG_STM32F7_ADC1 + /* ADC1 clock enable */ + + regval |= RCC_APB2ENR_ADC1EN; +#endif + +#ifdef CONFIG_STM32F7_ADC2 + /* ADC2 clock enable */ + + regval |= RCC_APB2ENR_ADC2EN; +#endif + +#ifdef CONFIG_STM32F7_ADC3 + /* ADC3 clock enable */ + + regval |= RCC_APB2ENR_ADC3EN; +#endif + +#ifdef CONFIG_STM32F7_SDMMC1 + /* SDIO clock enable */ + + regval |= RCC_APB2ENR_SDMMC1EN; +#endif + +#ifdef CONFIG_STM32F7_SDMMC2 + /* SDIO clock enable */ + + regval |= RCC_APB2ENR_SDMMC2EN; +#endif + +#ifdef CONFIG_STM32F7_SPI1 + /* SPI1 clock enable */ + + regval |= RCC_APB2ENR_SPI1EN; +#endif + +#ifdef CONFIG_STM32F7_SPI4 + /* SPI4 clock enable */ + + regval |= RCC_APB2ENR_SPI4EN; +#endif + + /* System configuration controller clock enable */ + + regval |= RCC_APB2ENR_SYSCFGEN; + +#ifdef CONFIG_STM32F7_TIM9 + /* TIM9 clock enable */ + + regval |= RCC_APB2ENR_TIM9EN; +#endif + +#ifdef CONFIG_STM32F7_TIM10 + /* TIM10 clock enable */ + + regval |= RCC_APB2ENR_TIM10EN; +#endif + +#ifdef CONFIG_STM32F7_TIM11 + /* TIM11 clock enable */ + + regval |= RCC_APB2ENR_TIM11EN; +#endif + +#ifdef CONFIG_STM32F7_SPI5 + /* SPI5 clock enable */ + + regval |= RCC_APB2ENR_SPI5EN; +#endif + +#ifdef CONFIG_STM32F7_SPI6 + /* SPI6 clock enable */ + + regval |= RCC_APB2ENR_SPI6EN; +#endif + +#ifdef CONFIG_STM32F7_SAI1 + /* SPI6 clock enable */ + + regval |= RCC_APB2ENR_SAI1EN; +#endif + +#ifdef CONFIG_STM32F7_SAI2 + /* SPI6 clock enable */ + + regval |= RCC_APB2ENR_SAI2EN; +#endif + +#ifdef CONFIG_STM32F7_LTDC + /* LTDC clock enable */ + + regval |= RCC_APB2ENR_LTDCEN; +#endif + + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: stm32_stdclockconfig + * + * Description: + * Called to change to new clock based on settings in board.h + * + * NOTE: This logic would need to be extended if you need to select low- + * power clocking modes! + ****************************************************************************/ + +#ifndef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +static void stm32_stdclockconfig(void) +{ + uint32_t regval; + volatile int32_t timeout; + +#ifdef STM32_BOARD_USEHSI + /* Enable Internal High-Speed Clock (HSI) */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_HSION; /* Enable HSI */ + putreg32(regval, STM32_RCC_CR); + + /* Wait until the HSI is ready (or until a timeout elapsed) */ + + for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSIRDY flag is the set in the CR */ + + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } + +#else /* if STM32_BOARD_USEHSE */ + /* Enable External High-Speed Clock (HSE) */ + + regval = getreg32(STM32_RCC_CR); +#ifdef STM32_HSEBYP_ENABLE /* May be defined in board.h header file */ + regval |= RCC_CR_HSEBYP; /* Enable HSE clock bypass */ +#else + regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */ +#endif + regval |= RCC_CR_HSEON; /* Enable HSE */ + putreg32(regval, STM32_RCC_CR); + + /* Wait until the HSE is ready (or until a timeout elapsed) */ + + for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSERDY flag is the set in the CR */ + + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } +#endif + + /* Check for a timeout. If this timeout occurs, then we are hosed. We + * have no real back-up plan, although the following logic makes it look + * as though we do. + */ + + if (timeout > 0) + { + /* Select regulator voltage output Scale 1 mode to support system + * frequencies up to 216 MHz. + */ + + regval = getreg32(STM32_RCC_APB1ENR); + regval |= RCC_APB1ENR_PWREN; + putreg32(regval, STM32_RCC_APB1ENR); + + regval = getreg32(STM32_PWR_CR1); + regval &= ~PWR_CR1_VOS_MASK; + regval |= STM32_PWR_VOS_SCALE; + putreg32(regval, STM32_PWR_CR1); + + /* Set the HCLK source/divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_HPRE_MASK; + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); + + /* Set the PCLK2 divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_PPRE2_MASK; + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); + + /* Set the PCLK1 divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_PPRE1_MASK; + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); + +#ifdef CONFIG_STM32F7_RTC_HSECLOCK + /* Set the RTC clock divisor */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_RTCPRE_MASK; + regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR); + putreg32(regval, STM32_RCC_CFGR); +#endif + + /* Set the PLL dividers and multipliers to configure the main PLL */ + +#ifdef STM32_BOARD_USEHSI + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP | + RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ); +#else /* if STM32_BOARD_USEHSE */ + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP | + RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PLLQ); +#endif + putreg32(regval, STM32_RCC_PLLCFG); + + /* Enable the main PLL */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLON; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the PLL is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) + { + } + + /* Over-drive is needed if + * - Voltage output scale 1 mode is selected and SYSCLK frequency is + * over 180 Mhz. + * - Voltage output scale 2 mode is selected and SYSCLK frequence is + * over 168 Mhz. + */ + + if ((STM32_PWR_VOS_SCALE == PWR_CR1_VOS_SCALE_1 && + STM32_SYSCLK_FREQUENCY > 180000000) || + (STM32_PWR_VOS_SCALE == PWR_CR1_VOS_SCALE_2 && + STM32_SYSCLK_FREQUENCY > 168000000)) + { + /* Enable the Over-drive to extend the clock frequency up to + * 216 Mhz. + */ + + regval = getreg32(STM32_PWR_CR1); + regval |= PWR_CR1_ODEN; + putreg32(regval, STM32_PWR_CR1); + while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODRDY) == 0) + { + } + + regval = getreg32(STM32_PWR_CR1); + regval |= PWR_CR1_ODSWEN; + putreg32(regval, STM32_PWR_CR1); + while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODSWRDY) == 0) + { + } + } + + /* Configure FLASH wait states */ + + regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); + +#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR + /* The Flash memory interface accelerates code execution with a system of + * instruction prefetch and cache lines on ITCM interface (ART + * Accelerator™). + */ + + regval |= FLASH_ACR_ARTEN; + regval |= FLASH_ACR_PRFTEN; +#endif + + putreg32(regval, STM32_FLASH_ACR); + + /* Select the main PLL as system clock source */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_SW_MASK; + regval |= RCC_CFGR_SW_PLL; + putreg32(regval, STM32_RCC_CFGR); + + /* Wait until the PLL source is used as the system clock source */ + + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) + { + } + +#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI) + + /* Configure PLLSAI */ + + regval = getreg32(STM32_RCC_PLLSAICFGR); + regval &= ~( RCC_PLLSAICFGR_PLLSAIN_MASK + | RCC_PLLSAICFGR_PLLSAIP_MASK + | RCC_PLLSAICFGR_PLLSAIQ_MASK +# if defined(CONFIG_STM32F7_LTDC) + | RCC_PLLSAICFGR_PLLSAIR_MASK +# endif + ); + regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN + | STM32_RCC_PLLSAICFGR_PLLSAIP + | STM32_RCC_PLLSAICFGR_PLLSAIQ +# if defined(CONFIG_STM32F7_LTDC) + | STM32_RCC_PLLSAICFGR_PLLSAIR +# endif + ); + putreg32(regval, STM32_RCC_PLLSAICFGR); + + regval = getreg32(STM32_RCC_DCKCFGR1); + regval &= ~(RCC_DCKCFGR1_PLLI2SDIVQ_MASK + | RCC_DCKCFGR1_PLLSAIDIVQ_MASK +# if defined(CONFIG_STM32F7_LTDC) + | RCC_DCKCFGR1_PLLSAIDIVR_MASK +# endif + | RCC_DCKCFGR1_SAI1SEL_MASK + | RCC_DCKCFGR1_SAI2SEL_MASK + | RCC_DCKCFGR1_TIMPRESEL); + + regval |= (STM32_RCC_DCKCFGR1_PLLI2SDIVQ + | STM32_RCC_DCKCFGR1_PLLSAIDIVQ +# if defined(CONFIG_STM32F7_LTDC) + | STM32_RCC_DCKCFGR1_PLLSAIDIVR +# endif + | STM32_RCC_DCKCFGR1_SAI1SRC + | STM32_RCC_DCKCFGR1_SAI2SRC + | STM32_RCC_DCKCFGR1_TIMPRESRC); + + putreg32(regval, STM32_RCC_DCKCFGR1); + + + /* Enable PLLSAI */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLSAION; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the PLLSAI is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAIRDY) == 0) + { + } +#endif +#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLI2S) + + /* Configure PLLI2S */ + + regval = getreg32(STM32_RCC_PLLI2SCFGR); + regval &= ~( RCC_PLLI2SCFGR_PLLI2SN_MASK +# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) + | RCC_PLLI2SCFGR_PLLI2SP_MASK +# endif + | RCC_PLLI2SCFGR_PLLI2SQ_MASK + | RCC_PLLI2SCFGR_PLLI2SR_MASK); + regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SN +# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) + | STM32_RCC_PLLI2SCFGR_PLLI2SP +# endif + | STM32_RCC_PLLI2SCFGR_PLLI2SQ + | STM32_RCC_PLLI2SCFGR_PLLI2SR); + putreg32(regval, STM32_RCC_PLLI2SCFGR); + + regval = getreg32(STM32_RCC_DCKCFGR2); + regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK + | RCC_DCKCFGR2_USART2SEL_MASK + | RCC_DCKCFGR2_UART4SEL_MASK + | RCC_DCKCFGR2_UART5SEL_MASK + | RCC_DCKCFGR2_USART6SEL_MASK + | RCC_DCKCFGR2_UART7SEL_MASK + | RCC_DCKCFGR2_UART8SEL_MASK + | RCC_DCKCFGR2_I2C1SEL_MASK + | RCC_DCKCFGR2_I2C2SEL_MASK + | RCC_DCKCFGR2_I2C3SEL_MASK +# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) + | RCC_DCKCFGR2_I2C4SEL_MASK + | RCC_DCKCFGR2_CECSEL_MASK +# endif + | RCC_DCKCFGR2_LPTIM1SEL_MASK + | RCC_DCKCFGR2_CK48MSEL_MASK + | RCC_DCKCFGR2_SDMMCSEL_MASK + | RCC_DCKCFGR2_SDMMC2SEL_MASK); + + regval |= ( STM32_RCC_DCKCFGR2_USART1SRC + | STM32_RCC_DCKCFGR2_USART2SRC + | STM32_RCC_DCKCFGR2_UART4SRC + | STM32_RCC_DCKCFGR2_UART5SRC + | STM32_RCC_DCKCFGR2_USART6SRC + | STM32_RCC_DCKCFGR2_UART7SRC + | STM32_RCC_DCKCFGR2_UART8SRC + | STM32_RCC_DCKCFGR2_I2C1SRC + | STM32_RCC_DCKCFGR2_I2C2SRC + | STM32_RCC_DCKCFGR2_I2C3SRC +# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) + | STM32_RCC_DCKCFGR2_I2C4SRC + | STM32_RCC_DCKCFGR2_CECSRC +# endif + | STM32_RCC_DCKCFGR2_LPTIM1SRC + | STM32_RCC_DCKCFGR2_CK48MSRC + | STM32_RCC_DCKCFGR2_SDMMCSRC + | STM32_RCC_DCKCFGR2_SDMMC2SRC); + + putreg32(regval, STM32_RCC_DCKCFGR2); + + /* Enable PLLI2S */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLI2SON; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the PLLI2S is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0) + { + } +#endif + +#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK) + /* Low speed internal clock source LSI */ + + stm32_rcc_enablelsi(); +#endif + +#if defined(CONFIG_STM32F7_RTC_LSECLOCK) + /* Low speed external clock source LSE + * + * TODO: There is another case where the LSE needs to + * be enabled: if the MCO1 pin selects LSE as source. + */ + + stm32_rcc_enablelse(); +#endif + } +} +#endif + +/**************************************************************************** + * Name: rcc_enableperiphals + ****************************************************************************/ + +static inline void rcc_enableperipherals(void) +{ + rcc_enableahb1(); + rcc_enableahb2(); + rcc_enableahb3(); + rcc_enableapb1(); + rcc_enableapb2(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index 4cc08673011595304bd74f5ad4a1a2133e7b9462..615e2d455fee73e7f26bc9d5e61294d038a211d4 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -68,6 +68,12 @@ # error BOARD_FLASH_WAITSTATES is out of range #endif +/* Voltage output scale (default to Scale 1 mode) */ + +#ifndef STM32_PWR_VOS_SCALE +# define STM32_PWR_VOS_SCALE PWR_CR1_VOS_SCALE_1 +#endif + /**************************************************************************** * Private Data ****************************************************************************/ @@ -732,7 +738,7 @@ static void stm32_stdclockconfig(void) regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; - regval |= PWR_CR1_VOS_SCALE_1; + regval |= STM32_PWR_VOS_SCALE; putreg32(regval, STM32_PWR_CR1); /* Set the HCLK source/divider */ @@ -788,20 +794,35 @@ static void stm32_stdclockconfig(void) { } - /* Enable the Over-drive to extend the clock frequency to 216 Mhz */ - - regval = getreg32(STM32_PWR_CR1); - regval |= PWR_CR1_ODEN; - putreg32(regval, STM32_PWR_CR1); - while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODRDY) == 0) - { - } + /* Over-drive is needed if + * - Voltage output scale 1 mode is selected and SYSCLK frequency is + * over 180 Mhz. + * - Voltage output scale 2 mode is selected and SYSCLK frequence is + * over 168 Mhz. + */ - regval = getreg32(STM32_PWR_CR1); - regval |= PWR_CR1_ODSWEN; - putreg32(regval, STM32_PWR_CR1); - while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODSWRDY) == 0) + if ((STM32_PWR_VOS_SCALE == PWR_CR1_VOS_SCALE_1 && + STM32_SYSCLK_FREQUENCY > 180000000) || + (STM32_PWR_VOS_SCALE == PWR_CR1_VOS_SCALE_2 && + STM32_SYSCLK_FREQUENCY > 168000000)) { + /* Enable the Over-drive to extend the clock frequency up to + * 216 Mhz. + */ + + regval = getreg32(STM32_PWR_CR1); + regval |= PWR_CR1_ODEN; + putreg32(regval, STM32_PWR_CR1); + while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODRDY) == 0) + { + } + + regval = getreg32(STM32_PWR_CR1); + regval |= PWR_CR1_ODSWEN; + putreg32(regval, STM32_PWR_CR1); + while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODSWRDY) == 0) + { + } } /* Configure FLASH wait states */ diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index 453d0130c681678c8ecbdd55cedce36090ebffea..abc6fc2964cddec617ff40be7c0ff7789ca7df9c 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -77,6 +77,12 @@ # error BOARD_FLASH_WAITSTATES is out of range #endif +/* Voltage output scale (default to Scale 1 mode) */ + +#ifndef STM32_PWR_VOS_SCALE +# define STM32_PWR_VOS_SCALE PWR_CR1_VOS_SCALE_1 +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -738,7 +744,7 @@ static void stm32_stdclockconfig(void) regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; - regval |= PWR_CR1_VOS_SCALE_1; + regval |= STM32_PWR_VOS_SCALE; putreg32(regval, STM32_PWR_CR1); /* Set the HCLK source/divider */ @@ -794,20 +800,35 @@ static void stm32_stdclockconfig(void) { } - /* Enable the Over-drive to extend the clock frequency to 216 Mhz */ - - regval = getreg32(STM32_PWR_CR1); - regval |= PWR_CR1_ODEN; - putreg32(regval, STM32_PWR_CR1); - while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODRDY) == 0) - { - } + /* Over-drive is needed if + * - Voltage output scale 1 mode is selected and SYSCLK frequency is + * over 180 Mhz. + * - Voltage output scale 2 mode is selected and SYSCLK frequence is + * over 168 Mhz. + */ - regval = getreg32(STM32_PWR_CR1); - regval |= PWR_CR1_ODSWEN; - putreg32(regval, STM32_PWR_CR1); - while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODSWRDY) == 0) + if ((STM32_PWR_VOS_SCALE == PWR_CR1_VOS_SCALE_1 && + STM32_SYSCLK_FREQUENCY > 180000000) || + (STM32_PWR_VOS_SCALE == PWR_CR1_VOS_SCALE_2 && + STM32_SYSCLK_FREQUENCY > 168000000)) { + /* Enable the Over-drive to extend the clock frequency up to + * 216 Mhz. + */ + + regval = getreg32(STM32_PWR_CR1); + regval |= PWR_CR1_ODEN; + putreg32(regval, STM32_PWR_CR1); + while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODRDY) == 0) + { + } + + regval = getreg32(STM32_PWR_CR1); + regval |= PWR_CR1_ODSWEN; + putreg32(regval, STM32_PWR_CR1); + while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODSWRDY) == 0) + { + } } /* Configure FLASH wait states */ diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index 3f41fe6e61d482f29f7c85fcdad36142250779e9..645654cd7be6d325d451c85284032c1fb066a6aa 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -3661,6 +3661,15 @@ config STM32L4_SERIALBRK_BSDCOMPAT on because the SW starts the break and then the HW automatically clears the break. This makes it is difficult to sent a long break. +if PM +config PM_SERIAL_ACTIVITY + int "PM serial activity" + default 10 + ---help--- + PM activity reported to power management logic on every serial + interrupt. +endif + endmenu # U[S]ART Configuration menu "SPI Configuration" @@ -3808,7 +3817,7 @@ config STM32L4_CAN_REGDEBUG endmenu menu "QEncoder Driver" - depends on QENCODER + depends on SENSORS_QENCODER depends on STM32L4_TIM1 || STM32L4_TIM2 || STM32L4_TIM3 || STM32L4_TIM4 || STM32L4_TIM5 || STM32L4_TIM8 config STM32L4_TIM1_QE diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index c073ad1a2bd1ff2ee4525ef2998913f19fed4d7d..bb164bfeacca4435e665a582c970f38e01c3038e 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -100,11 +100,15 @@ endif CHIP_ASRCS = CHIP_CSRCS = stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c -CHIP_CSRCS += stm32l4_idle.c stm32l4_irq.c stm32l4_lowputc.c stm32l4_rcc.c +CHIP_CSRCS += stm32l4_irq.c stm32l4_lowputc.c stm32l4_rcc.c CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c stm32l4_waste.c stm32l4_uid.c CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c stm32l4_lsi.c CHIP_CSRCS += stm32l4_pwr.c stm32l4_tim.c stm32l4_flash.c +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CHIP_CSRCS += stm32l4_idle.c +endif + ifeq ($(CONFIG_TIMER),y) CHIP_CSRCS += stm32l4_tim_lowerhalf.c endif diff --git a/arch/arm/src/stm32l4/chip/stm32l4x5xx_otgfs.h b/arch/arm/src/stm32l4/chip/stm32l4x5xx_otgfs.h index ddbb5b0ce5a9fb9ef8c774bc85c7571c4f29d225..efdde6fcc137fa60a07b4bde0dd2b7ae8f9ccb10 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4x5xx_otgfs.h +++ b/arch/arm/src/stm32l4/chip/stm32l4x5xx_otgfs.h @@ -81,7 +81,7 @@ #define STM32L4_OTGFS_GADPCTL_OFSSET 0x005c /* ADP timer, control and status register */ #define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ -#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2)) +#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) /* Host-mode control and status registers */ diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h b/arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h index a01427ea72810400dab01afbbb06d2f2964db300..b2843a0b4a50279afaadd44f6792619c095b08e7 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h +++ b/arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h @@ -81,7 +81,7 @@ #define STM32L4_OTGFS_GADPCTL_OFSSET 0x005c /* ADP timer, control and status register */ #define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ -#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2)) +#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) /* Host-mode control and status registers */ diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c index d4c64cd5a4fdb37796fe82cbdc85e28161002cc4..6fd44d6da30a02d284ea1fedb8bea64b78f893e2 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.c +++ b/arch/arm/src/stm32l4/stm32l4_i2c.c @@ -7,7 +7,7 @@ * Copyright (C) 2011 Uros Platise. All rights reserved. * Author: Uros Platise * Copyright (C) 2011-2013, 2016-2017 Gregory Nutt. All rights reserved. - * Author: Gregroy Nutt + * Author: Gregory Nutt * Author: John Wharington * Author: Sebastien Lorquet * Author: dev@ziggurat29.com @@ -20,7 +20,7 @@ * With extensions and modifications for the F1, F2, and F4 by: * * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. - * Authors: Gregroy Nutt + * Authors: Gregory Nutt * John Wharington * David Sidrane * diff --git a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c index d57701ad6ae468bde64d83ded439bcf14b04324e..2a55633ac6c4850d84bb42357fe970e17fe58dca 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c @@ -71,6 +71,10 @@ ****************************************************************************/ /* Configuration ***************************************************************/ +#ifndef CONFIG_STM32L4_SYSCFG +# error "CONFIG_STM32L4_SYSCFG is required" +#endif + #ifndef CONFIG_USBDEV_EP0_MAXSIZE # define CONFIG_USBDEV_EP0_MAXSIZE 64 #endif @@ -332,19 +336,6 @@ #define STM32L4_TRACEINTID_SETUPDONE (90 + 3) #define STM32L4_TRACEINTID_SETUPRECVD (90 + 4) -/* CONFIG_USB_DUMPBUFFER will dump the contents of buffers to the console. */ - -#define CONFIG_USB_DUMPBUFFER - -#if !defined(CONFIG_DEBUG_INFO) || !defined(CONFIG_DEBUG_FEATURES) -# undef CONFIG_USB_DUMPBUFFER -#endif -#ifdef CONFIG_USB_DUMPBUFFER -# define usb_dumpbuffer(t,b,l) lib_dumpbuffer(t,b,l) -#else -# define usb_dumpbuffer(t,b,l) -#endif - /* Endpoints ******************************************************************/ /* Odd physical endpoint numbers are IN; even are OUT */ @@ -1141,8 +1132,6 @@ static void stm32l4_txfifo_write(FAR struct stm32l4_ep_s *privep, int nwords; int i; - usb_dumpbuffer(">>>",buf,nbytes); - /* Convert the number of bytes to words */ nwords = (nbytes + 3) >> 2; @@ -1531,8 +1520,6 @@ static void stm32l4_rxfifo_read(FAR struct stm32l4_ep_s *privep, *dest++ = data.b[2]; *dest++ = data.b[3]; } - - usb_dumpbuffer("<<<",dest-len,len); } /**************************************************************************** @@ -4404,7 +4391,7 @@ static void stm32l4_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req #ifdef CONFIG_USBDEV_DMA static void *stm32l4_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes) { - usbtrace(TRACE_EPALLOCBUFFER, privep->epphy); + usbtrace(TRACE_EPALLOCBUFFER, ((FAR struct stm32l4_ep_s *)ep)->epphy); #ifdef CONFIG_USBDEV_DMAMEMORY return usbdev_dma_alloc(bytes); @@ -4425,7 +4412,7 @@ static void *stm32l4_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes) #ifdef CONFIG_USBDEV_DMA static void stm32l4_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf) { - usbtrace(TRACE_EPFREEBUFFER, privep->epphy); + usbtrace(TRACE_EPFREEBUFFER, ((FAR struct stm32l4_ep_s *)ep)->epphy); #ifdef CONFIG_USBDEV_DMAMEMORY usbdev_dma_free(buf); @@ -5357,7 +5344,7 @@ static void stm32l4_hwinitialize(FAR struct stm32l4_usbdev_s *priv) address = STM32L4_RXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF0_TX0FD_SHIFT) | (STM32L4_EP0_TXFIFO_WORDS << OTGFS_DIEPTXF0_TX0FSA_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(0)); + stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF0); #endif #if STM32L4_NENDPOINTS > 1 diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.c b/arch/arm/src/stm32l4/stm32l4_rcc.c index d18e0dbc8829b8368cfe58ebb1daaec1d11dadc1..1f90867dc312b5464a5343e2c4eed86dcae96e5e 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rcc.c @@ -56,6 +56,7 @@ #include "stm32l4_flash.h" #include "stm32l4.h" #include "stm32l4_waste.h" +#include "stm32l4_rtc.h" /**************************************************************************** * Pre-processor Definitions @@ -117,8 +118,18 @@ static inline void rcc_resetbkp(void) /* Check if the RTC is already configured */ init_stat = stm32l4_rtc_is_initialized(); - if(!init_stat) + if (!init_stat) { + uint32_t bkregs[STM32L4_RTC_BKCOUNT]; + int i; + + /* Backup backup-registers before RTC reset. */ + + for (i = 0; i < STM32L4_RTC_BKCOUNT; i++) + { + bkregs[i] = getreg32(STM32L4_RTC_BKR(i)); + } + /* Enable write access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). */ @@ -132,6 +143,18 @@ static inline void rcc_resetbkp(void) modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_BDRST); modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_BDRST, 0); + /* Restore backup-registers, except RTC related. */ + + for (i = 0; i < STM32L4_RTC_BKCOUNT; i++) + { + if (RTC_MAGIC_REG == STM32L4_RTC_BKR(i)) + { + continue; + } + + putreg32(bkregs[i], STM32L4_RTC_BKR(i)); + } + (void)stm32l4_pwr_enablebkp(false); } } diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.c b/arch/arm/src/stm32l4/stm32l4_rtc.c index 7707d264c5fa7409916b956cf9146a66e353a780..f083250c7b96cd3055bafd8964e5e5539359289d 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc.c @@ -84,22 +84,6 @@ # error "CONFIG_STM32L4_PWR must selected to use this driver" #endif -#if !defined(CONFIG_RTC_MAGIC) -# define CONFIG_RTC_MAGIC (0xfacefeee) -#endif - -#if !defined(CONFIG_RTC_MAGIC_TIME_SET) -# define CONFIG_RTC_MAGIC_TIME_SET (CONFIG_RTC_MAGIC + 1) -#endif - -#if !defined(CONFIG_RTC_MAGIC_REG) -# define CONFIG_RTC_MAGIC_REG (0) -#endif - -#define RTC_MAGIC CONFIG_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32L4_RTC_BKR(CONFIG_RTC_MAGIC_REG) - /* Constants ****************************************************************/ #define SYNCHRO_TIMEOUT (0x00020000) diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.h b/arch/arm/src/stm32l4/stm32l4_rtc.h index c7da87e212f0dab698b4166bfe35508c15e178bd..e7b06fcb31cb568cf95677fb01fce9690c2fa9bb 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.h +++ b/arch/arm/src/stm32l4/stm32l4_rtc.h @@ -57,6 +57,22 @@ #define STM32L4_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ #define STM32L4_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ +#if !defined(CONFIG_RTC_MAGIC) +# define CONFIG_RTC_MAGIC (0xfacefeee) +#endif + +#if !defined(CONFIG_RTC_MAGIC_TIME_SET) +# define CONFIG_RTC_MAGIC_TIME_SET (CONFIG_RTC_MAGIC + 1) +#endif + +#if !defined(CONFIG_RTC_MAGIC_REG) +# define CONFIG_RTC_MAGIC_REG (0) +#endif + +#define RTC_MAGIC CONFIG_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_RTC_MAGIC_TIME_SET +#define RTC_MAGIC_REG STM32L4_RTC_BKR(CONFIG_RTC_MAGIC_REG) + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index 4cbcb6b4381d4577764fda975a77e925f5f931a0..67602e3c16909467c7a246bb0efc6dae47a97bfe 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -177,7 +177,9 @@ /* Power management definitions */ #if defined(CONFIG_PM) && !defined(CONFIG_PM_SERIAL_ACTIVITY) -# define CONFIG_PM_SERIAL_ACTIVITY 10 +# define CONFIG_PM_SERIAL_ACTIVITY 10 +#endif +#if defined(CONFIG_PM) # define PM_IDLE_DOMAIN 0 /* Revisit */ #endif @@ -214,11 +216,13 @@ struct stm32l4_serial_s bool initialized; +#ifdef CONFIG_PM bool suspended; /* UART device has been suspended. */ /* Interrupt mask value stored before suspending for stop mode. */ uint16_t suspended_ie; +#endif /* If termios are supported, then the following fields may vary at * runtime. @@ -269,7 +273,9 @@ struct stm32l4_serial_s #ifdef SERIAL_HAVE_DMA DMA_HANDLE rxdma; /* currently-open receive DMA stream */ bool rxenable; /* DMA-based reception en/disable */ +#ifdef CONFIG_PM bool rxdmasusp; /* Rx DMA suspended */ +#endif uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */ char *const rxfifo; /* Receive DMA buffer */ #endif @@ -325,6 +331,8 @@ static void stm32l4serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, #endif #ifdef CONFIG_PM +static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend); +static void stm32l4serial_pm_setsuspend(bool suspend); static void stm32l4serial_pmnotify(FAR struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); static int stm32l4serial_pmprepare(FAR struct pm_callback_s *cb, int domain, @@ -734,7 +742,7 @@ static struct stm32l4_serial_s g_uart5priv = /* This table lets us iterate over the configured USARTs */ -FAR static struct stm32l4_serial_s * const uart_devs[STM32L4_NUSART+STM32L4_NUART] = +FAR static struct stm32l4_serial_s * const uart_devs[STM32L4_NUSART + STM32L4_NUART] = { #ifdef CONFIG_STM32L4_USART1 [0] = &g_usart1priv, @@ -754,15 +762,18 @@ FAR static struct stm32l4_serial_s * const uart_devs[STM32L4_NUSART+STM32L4_NUAR }; #ifdef CONFIG_PM -static struct pm_callback_s g_serialcb = +static struct { - .notify = stm32l4serial_pmnotify, - .prepare = stm32l4serial_pmprepare, -}; + struct pm_callback_s pm_cb; + bool serial_suspended; +} g_serialpm = + { + .pm_cb.notify = stm32l4serial_pmnotify, + .pm_cb.prepare = stm32l4serial_pmprepare, + .serial_suspended = false + }; #endif -static bool serial_suspended_for_stop = false; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -1052,6 +1063,7 @@ static void stm32l4serial_setformat(FAR struct uart_dev_s *dev) * ****************************************************************************/ +#ifdef CONFIG_PM static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) { FAR struct stm32l4_serial_s *priv = (struct stm32l4_serial_s *)dev->priv; @@ -1164,6 +1176,41 @@ static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) } #endif } +#endif + +/**************************************************************************** + * Name: stm32l4serial_pm_setsuspend + * + * Description: + * Suspend or resume serial peripherals for/from deep-sleep/stop modes. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32l4serial_pm_setsuspend(bool suspend) +{ + int n; + + /* Already in desired state? */ + + if (suspend == g_serialpm.serial_suspended) + return; + + g_serialpm.serial_suspended = suspend; + + for (n = 0; n < STM32L4_NUSART + STM32L4_NUART; n++) + { + struct stm32l4_serial_s *priv = uart_devs[n]; + + if (!priv || !priv->initialized) + { + continue; + } + + stm32l4serial_setsuspend(&priv->dev, suspend); + } +} +#endif /**************************************************************************** * Name: stm32l4serial_setapbclock @@ -2244,9 +2291,11 @@ static void stm32l4serial_dmareenable(FAR struct stm32l4_serial_s *priv) stm32l4_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, (void *)priv, true); } +#ifdef CONFIG_PM /* Clear DMA suspended flag. */ priv->rxdmasusp = false; +#endif } #endif @@ -2270,6 +2319,7 @@ static bool stm32l4serial_dmaiflowrestart(struct stm32l4_serial_s *priv) if (priv->rxdmanext != RXDMA_BUFFER_SIZE) { +#ifdef CONFIG_PM if (priv->rxdmasusp) { /* Rx DMA in suspended state. */ @@ -2282,6 +2332,7 @@ static bool stm32l4serial_dmaiflowrestart(struct stm32l4_serial_s *priv) } } else +#endif { return false; } @@ -2533,27 +2584,31 @@ static void stm32l4serial_pmnotify(FAR struct pm_callback_s *cb, int domain, { case PM_NORMAL: { - stm32l4_serial_set_suspend(false); + stm32l4serial_pm_setsuspend(false); } break; case PM_IDLE: { - stm32l4_serial_set_suspend(false); + stm32l4serial_pm_setsuspend(false); } break; case PM_STANDBY: { - /* TODO: logic for enabling serial in Stop 1 mode with HSI16 missing */ + /* TODO: Alternative configuration and logic for enabling serial in + * Stop 1 mode with HSI16 missing. Current logic allows + * suspending serial peripherals for Stop 0/1/2 when serial + * Rx/Tx buffers are empty (checked in pmprepare). + */ - stm32l4_serial_set_suspend(true); + stm32l4serial_pm_setsuspend(true); } break; case PM_SLEEP: { - stm32l4_serial_set_suspend(true); + stm32l4serial_pm_setsuspend(true); } break; @@ -2601,90 +2656,75 @@ static void stm32l4serial_pmnotify(FAR struct pm_callback_s *cb, int domain, static int stm32l4serial_pmprepare(FAR struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { + int n; + /* Logic to prepare for a reduced power state goes here. */ - return OK; -} -#endif -#endif /* HAVE_UART */ -#endif /* USE_SERIALDRIVER */ + switch (pmstate) + { + case PM_NORMAL: + case PM_IDLE: + break; -/**************************************************************************** - * Public Functions - ****************************************************************************/ + case PM_STANDBY: + case PM_SLEEP: -#ifdef USE_SERIALDRIVER +#ifdef SERIAL_HAVE_DMA + /* Flush Rx DMA buffers before checking state of serial device + * buffers. + */ -/**************************************************************************** - * Name: stm32l4_is_serial_suspended - * - * Description: - * Check if serial peripherals have been suspended for deep-sleep/stop modes. - * - ****************************************************************************/ + stm32l4_serial_dma_poll(); +#endif -bool stm32l4_is_serial_suspended(void) -{ - return (serial_suspended_for_stop); -} + /* Check if any of the active ports have data pending on Tx/Rx + * buffers. + */ -/**************************************************************************** - * Name: stm32_serial_set_suspend - * - * Description: - * Suspend or resume serial peripherals for/from deep-sleep/stop modes. - * - ****************************************************************************/ + for (n = 0; n < STM32L4_NUSART + STM32L4_NUART; n++) + { + struct stm32l4_serial_s *priv = uart_devs[n]; -void stm32l4_serial_set_suspend(bool suspend) -{ - int n; + if (!priv || !priv->initialized) + { + /* Not active, skip. */ - /* Already in desired state? */ + continue; + } - if (suspend == serial_suspended_for_stop) - return; + if (priv->suspended) + { + /* Port already suspended, skip. */ - serial_suspended_for_stop = suspend; + continue; + } - for (n = 0; n < STM32L4_NUSART+STM32L4_NUART; n++) - { - struct stm32l4_serial_s *priv = uart_devs[n]; + /* Check if port has data pending (Rx & Tx). */ - if (!priv || !priv->initialized) - { - continue; + if (priv->dev.xmit.head != priv->dev.xmit.tail) + { + return ERROR; + } + if (priv->dev.recv.head != priv->dev.recv.tail) + { + return ERROR; + } } - stm32l4serial_setsuspend(&priv->dev, suspend); + break; } + return OK; } +#endif + +#endif /* HAVE_UART */ +#endif /* USE_SERIALDRIVER */ /**************************************************************************** - * Name: stm32l4_serial_get_uart - * - * Description: - * Get serial driver structure for STM32 USART - * + * Public Functions ****************************************************************************/ -FAR uart_dev_t *stm32l4_serial_get_uart(int uart_num) -{ - int uart_idx = uart_num - 1; - - if (uart_idx < 0 || uart_idx >= STM32L4_NUSART+STM32L4_NUART || \ - !uart_devs[uart_idx]) - { - return NULL; - } - - if (!uart_devs[uart_idx]->initialized) - { - return NULL; - } - - return &uart_devs[uart_idx]->dev; -} +#ifdef USE_SERIALDRIVER /**************************************************************************** * Name: up_earlyserialinit @@ -2704,7 +2744,7 @@ void up_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32L4_NUSART+STM32L4_NUART; i++) + for (i = 0; i < STM32L4_NUSART + STM32L4_NUART; i++) { if (uart_devs[i]) { @@ -2743,7 +2783,7 @@ void up_serialinit(void) /* Register to receive power management callbacks */ #ifdef CONFIG_PM - ret = pm_register(&g_serialcb); + ret = pm_register(&g_serialpm.pm_cb); DEBUGASSERT(ret == OK); UNUSED(ret); #endif @@ -2773,7 +2813,7 @@ void up_serialinit(void) strcpy(devname, "/dev/ttySx"); - for (i = 0; i < STM32L4_NUSART+STM32L4_NUART; i++) + for (i = 0; i < STM32L4_NUSART + STM32L4_NUART; i++) { /* Don't create a device for non-configured ports. */ diff --git a/arch/arm/src/stm32l4/stm32l4_uart.h b/arch/arm/src/stm32l4/stm32l4_uart.h index 4f89aff838bc64cee316caa75f4918ddb35dd4f2..b1ec46b13007dbab186d4ecfa7af9b02341f5362 100644 --- a/arch/arm/src/stm32l4/stm32l4_uart.h +++ b/arch/arm/src/stm32l4/stm32l4_uart.h @@ -238,36 +238,6 @@ extern "C" * Public Functions ************************************************************************************/ -/************************************************************************************ - * Name: stm32l4_serial_get_uart - * - * Description: - * Get serial driver structure for STM32 USART - * - ************************************************************************************/ - -FAR uart_dev_t *stm32l4_serial_get_uart(int uart_num); - -/**************************************************************************** - * Name: stm32l4_is_serial_suspended - * - * Description: - * Check if serial peripherals have been suspended for deep-sleep/stop modes. - * - ****************************************************************************/ - -bool stm32l4_is_serial_suspended(void); - -/**************************************************************************** - * Name: stm32_serial_set_suspend - * - * Description: - * Suspend or resume serial peripherals for/from deep-sleep/stop modes. - * - ****************************************************************************/ - -void stm32l4_serial_set_suspend(bool suspend); - /************************************************************************************ * Name: stm32l4_serial_dma_poll * diff --git a/arch/arm/src/tiva/tiva_start.h b/arch/arm/src/tiva/tiva_start.h index ab4a2cd9292db2f43c7f1dc75aa5b7814b63a2b9..ec4c5f71d4a96ab3d6fe28d31e4733ecd7544d9a 100644 --- a/arch/arm/src/tiva/tiva_start.h +++ b/arch/arm/src/tiva/tiva_start.h @@ -43,20 +43,21 @@ #include /**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types + * Public Functions ****************************************************************************/ /**************************************************************************** - * Public Data + * Name: tiva_boardinitialize + * + * Description: + * All Tiva architectures must provide the following entry point. This + * entry point is called early in the initialization -- after clocking and + * memory have been configured but before caches have been enabled and + * before any devices have been initialized. + * ****************************************************************************/ -/**************************************************************************** - * Public Functions - ****************************************************************************/ +void tiva_boardinitialize(void); /**************************************************************************** * Name: board_earlyinit diff --git a/arch/arm/src/xmc4/Kconfig b/arch/arm/src/xmc4/Kconfig index 5a83e363b959d6ab2e5dc08d653df7b2141f4d5c..74816db73aa38f450a74be257b19ad32df8af42b 100644 --- a/arch/arm/src/xmc4/Kconfig +++ b/arch/arm/src/xmc4/Kconfig @@ -45,18 +45,114 @@ config XMC4_USCI_LIN bool default n +config XMC4_LIN0 + bool + default n + +config XMC4_LIN1 + bool + default n + +config XMC4_LIN2 + bool + default n + +config XMC4_LIN3 + bool + default n + +config XMC4_LIN4 + bool + default n + +config XMC4_LIN5 + bool + default n + config XMC4_USCI_SPI bool default n +config XMC4_SPI0 + bool + default n + +config XMC4_SPI1 + bool + default n + +config XMC4_SPI2 + bool + default n + +config XMC4_SPI3 + bool + default n + +config XMC4_SPI4 + bool + default n + +config XMC4_SPI5 + bool + default n + config XMC4_USCI_I2C bool default n +config XMC4_I2C0 + bool + default n + +config XMC4_I2C1 + bool + default n + +config XMC4_I2C2 + bool + default n + +config XMC4_I2C3 + bool + default n + +config XMC4_I2C4 + bool + default n + +config XMC4_I2C5 + bool + default n + config XMC4_USCI_I2S bool default n +config XMC4_I2S0 + bool + default n + +config XMC4_I2S1 + bool + default n + +config XMC4_I2S2 + bool + default n + +config XMC4_I2S3 + bool + default n + +config XMC4_I2S4 + bool + default n + +config XMC4_I2S5 + bool + default n + # Chip families menu "XMC4xxx Peripheral Support" @@ -71,6 +167,7 @@ config XMC4_USIC0 config XMC4_USIC1 bool "USIC1" default n + select XMC4_USIC ---help--- Support USIC1 @@ -104,25 +201,29 @@ config XMC4_USIC0_CHAN0_ISUART Configure USIC0 Channel 0 as a UART config XMC4_USIC0_CHAN0_ISLIN - bool "LIN" + bool "LIN0" + select XMC4_LIN0 select XMC4_USCI_LIN ---help--- Configure USIC0 Channel 0 as a LIN UART config XMC4_USIC0_CHAN0_ISSPI - bool "SPI" + bool "SPI0" + select XMC4_SPI0 select XMC4_USCI_SPI ---help--- Configure USIC0 Channel 0 for SPI communications config XMC4_USIC0_CHAN0_ISI2C - bool "I2C" + bool "I2C0" + select XMC4_I2C0 select XMC4_USCI_I2C ---help--- Configure USIC0 Channel 0 for I2C communications config XMC4_USIC0_CHAN0_ISI2S - bool "I2S" + bool "I2S0" + select XMC4_I2S0 select XMC4_USCI_I2S ---help--- Configure USIC0 Channel 0 for I2S audio @@ -147,25 +248,29 @@ config XMC4_USIC0_CHAN1_ISUART Configure USIC0 Channel 1 as a UART config XMC4_USIC0_CHAN1_ISLIN - bool "LIN" + bool "LIN1" + select XMC4_LIN1 select XMC4_USCI_LIN ---help--- Configure USIC0 Channel 1 as a LIN UART config XMC4_USIC0_CHAN1_ISSPI - bool "SPI" + bool "SPI1" + select XMC4_SPI1 select XMC4_USCI_SPI ---help--- Configure USIC0 Channel 1 for SPI communications config XMC4_USIC0_CHAN1_ISI2C - bool "I2C" + bool "I2C1" + select XMC4_I2C1 select XMC4_USCI_I2C ---help--- Configure USIC0 Channel 1 for I2C communications config XMC4_USIC0_CHAN1_ISI2S - bool "I2S" + bool "I2S1" + select XMC4_I2S1 select XMC4_USCI_I2S ---help--- Configure USIC0 Channel 1 for I2S audio @@ -190,25 +295,29 @@ config XMC4_USIC1_CHAN0_ISUART Configure USIC1 Channel 0 as a UART config XMC4_USIC1_CHAN0_ISLIN - bool "LIN" + bool "LIN2" + select XMC4_LIN2 select XMC4_USCI_LIN ---help--- Configure USIC1 Channel 0 as a LIN UART config XMC4_USIC1_CHAN0_ISSPI - bool "SPI" + bool "SPI2" + select XMC4_SPI2 select XMC4_USCI_SPI ---help--- Configure USIC1 Channel 0 for SPI communications config XMC4_USIC1_CHAN0_ISI2C - bool "I2C" + bool "I2C2" + select XMC4_I2C2 select XMC4_USCI_I2C ---help--- Configure USIC1 Channel 0 for I2C communications config XMC4_USIC1_CHAN0_ISI2S - bool "I2S" + bool "I2S2" + select XMC4_I2S2 select XMC4_USCI_I2S ---help--- Configure USIC1 Channel 0 for I2S audio @@ -233,25 +342,29 @@ config XMC4_USIC1_CHAN1_ISUART Configure USIC1 Channel 1 as a UART config XMC4_USIC1_CHAN1_ISLIN - bool "LIN" + bool "LIN3" + select XMC4_LIN3 select XMC4_USCI_LIN ---help--- Configure USIC1 Channel 1 as a LIN UART config XMC4_USIC1_CHAN1_ISSPI - bool "SPI" + bool "SPI3" + select XMC4_SPI3 select XMC4_USCI_SPI ---help--- Configure USIC1 Channel 1 for SPI communications config XMC4_USIC1_CHAN1_ISI2C - bool "I2C" + bool "I2C3" + select XMC4_I2C3 select XMC4_USCI_I2C ---help--- Configure USIC1 Channel 1 for I2C communications config XMC4_USIC1_CHAN1_ISI2S - bool "I2S" + bool "I2S3" + select XMC4_I2S3 select XMC4_USCI_I2S ---help--- Configure USIC1 Channel 1 for I2S audio @@ -276,25 +389,29 @@ config XMC4_USIC2_CHAN0_ISUART Configure USIC2 Channel 0 as a UART config XMC4_USIC2_CHAN0_ISLIN - bool "LIN" + bool "LIN4" + select XMC4_LIN4 select XMC4_USCI_LIN ---help--- Configure USIC2 Channel 0 as a LIN UART config XMC4_USIC2_CHAN0_ISSPI - bool "SPI" + bool "SPI4" + select XMC4_SPI4 select XMC4_USCI_SPI ---help--- Configure USIC2 Channel 0 for SPI communications config XMC4_USIC2_CHAN0_ISI2C - bool "I2C" + bool "I2C4" + select XMC4_I2C4 select XMC4_USCI_I2C ---help--- Configure USIC2 Channel 0 for I2C communications config XMC4_USIC2_CHAN0_ISI2S - bool "I2S" + bool "I2S4" + select XMC4_I2S4 select XMC4_USCI_I2S ---help--- Configure USIC2 Channel 0 for I2S audio @@ -319,25 +436,29 @@ config XMC4_USIC2_CHAN1_ISUART Configure USIC2 Channel 1 as a UART config XMC4_USIC2_CHAN1_ISLIN - bool "LIN" + bool "LIN5" + select XMC4_LIN5 select XMC4_USCI_LIN ---help--- Configure USIC2 Channel 1 as a LIN UART config XMC4_USIC2_CHAN1_ISSPI - bool "SPI" + bool "SPI5" + select XMC4_SPI5 select XMC4_USCI_SPI ---help--- Configure USIC2 Channel 1 for SPI communications config XMC4_USIC2_CHAN1_ISI2C - bool "I2C" + bool "I2C5" + select XMC4_I2C5 select XMC4_USCI_I2C ---help--- Configure USIC2 Channel 1 for I2C communications config XMC4_USIC2_CHAN1_ISI2S - bool "I2S" + bool "I2S5" + select XMC4_I2S5 select XMC4_USCI_I2S ---help--- Configure USIC2 Channel 1 for I2S audio diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/chip/xmc4_usic.h index 274d0fae53bcadcf52016e16ad65ef1829ecf8c1..0ca992d548f2ca56b7e5f2be40906ba30b7c1319 100644 --- a/arch/arm/src/xmc4/chip/xmc4_usic.h +++ b/arch/arm/src/xmc4/chip/xmc4_usic.h @@ -477,7 +477,7 @@ # define USIC_INPR_TSINP_SR3 (3 << USIC_INPR_TSINP_SHIFT) /* Output SR3 activated */ # define USIC_INPR_TSINP_SR4 (4 << USIC_INPR_TSINP_SHIFT) /* Output SR4 activated */ # define USIC_INPR_TSINP_SR5 (5 << USIC_INPR_TSINP_SHIFT) /* Output SR5 activated */ -#define USIC_INPR_TBINP_SHIFT (4) /* Bits 4-6: Transmit Buffer Interrupt Node Poi */ +#define USIC_INPR_TBINP_SHIFT (4) /* Bits 4-6: Transmit Buffer Interrupt Node Pointer */ #define USIC_INPR_TBINP_MASK (7 << USIC_INPR_TBINP_SHIFT) # define USIC_INPR_TBINP_SR0 (0 << USIC_INPR_TBINP_SHIFT) /* Output SR0 activated */ # define USIC_INPR_TBINP_SR1 (1 << USIC_INPR_TBINP_SHIFT) /* Output SR1 activated */ diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c index 519276f2cdce845923ffc47d146a166d0cb72a45..eeb71dbe0b476adb8e31ca1c5f268aea7c991cac 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.c +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -103,13 +103,7 @@ #define PLL_K2DIV_120MHZ (VCO / 120000000) #define CLKSET_VALUE (0x00000000) -#define SYSCLKCR_VALUE (0x00010001) -#define CPUCLKCR_VALUE (0x00000000) -#define CCUCLKCR_VALUE (0x00000000) -#define WDTCLKCR_VALUE (0x00000000) -#define EBUCLKCR_VALUE (0x00000003) #define USBCLKCR_VALUE (0x00010000) -#define EXTCLKCR_VALUE (0x01200003) #if BOARD_PBDIV == 1 # define PBCLKCR_VALUE SCU_PBCLKCR_PBDIV_FCPU @@ -391,14 +385,46 @@ void xmc4_clock_configure(void) /* Before scaling to final frequency we need to setup the clock dividers */ - putreg32(SYSCLKCR_VALUE, XMC4_SCU_SYSCLKCR); - putreg32(PBCLKCR_VALUE, XMC4_SCU_PBCLKCR); - putreg32(CPUCLKCR_VALUE, XMC4_SCU_CPUCLKCR); - putreg32(CCUCLKCR_VALUE, XMC4_SCU_CCUCLKCR); - putreg32(WDTCLKCR_VALUE, XMC4_SCU_WDTCLKCR); - putreg32(EBUCLKCR_VALUE, XMC4_SCU_EBUCLKCR); + /* Setup fSYS clock */ + + regval = (BOARD_ENABLE_PLL << SCU_SYSCLKCR_SYSSEL); + regval |= SCU_SYSCLKCR_SYSDIV(BOARD_SYSDIV); + putreg32(regval, XMC4_SCU_SYSCLKCR); + + /* Setup peripheral clock divider */ + + putreg32(PBCLKCR_VALUE, XMC4_SCU_PBCLKCR); + + /* Setup fCPU clock */ + + putreg32(BOARD_CPUDIV_ENABLE, XMC4_SCU_CPUCLKCR); + + /* Setup CCU clock */ + + putreg32(BOARD_CCUDIV_ENABLE, XMC4_SCU_CCUCLKCR); + + /* Setup Watchdog clock */ + + regval = (BOARD_WDT_SOURCE << SCU_WDTCLKCR_WDTSEL_SHIFT); + regval |= SCU_WDTCLKCR_WDTDIV(BOARD_WDTDIV); + putreg32(regval, XMC4_SCU_WDTCLKCR); + + /* Setup EBU clock */ + + regval = SCU_EBUCLKCR_EBUDIV(BOARD_EBUDIV); + putreg32(regval, XMC4_SCU_EBUCLKCR); + +#ifdef BOARD_ENABLE_USBPLL + /* Setup USB clock */ + putreg32(USBCLKCR_VALUE | USB_DIV, XMC4_SCU_USBCLKCR); - putreg32(EXTCLKCR_VALUE, XMC4_SCU_EXTCLKCR); +#endif + + /* Setup EXT */ + + regval = (BOARD_EXT_SOURCE << SCU_EXTCLKCR_ECKSEL_SHIFT); + regval |= SCU_EXTCLKCR_ECKDIV(BOARD_EXTDIV); + putreg32(regval, XMC4_SCU_EXTCLKCR); #if BOARD_ENABLE_PLL /* PLL frequency stepping...*/ @@ -436,12 +462,14 @@ void xmc4_clock_configure(void) delay(DELAY_CNT_50US_120MHZ); +#ifdef BOARD_FCPU_144MHZ regval = (SCU_PLLCON1_NDIV(BOARD_PLL_NDIV) | SCU_PLLCON1_K2DIV(BOARD_PLL_K2DIV) | SCU_PLLCON1_PDIV(BOARD_PLL_PDIV)); putreg32(regval, XMC4_SCU_PLLCON1); delay(DELAY_CNT_50US_144MHZ); +#endif #endif /* BOARD_ENABLE_PLL */ diff --git a/arch/arm/src/xmc4/xmc4_gpio.h b/arch/arm/src/xmc4/xmc4_gpio.h index 0dce7af73cd239971622258a52df499da4cc10f2..eebc6e88fb33e001eee467ca3e57742b6179151f 100644 --- a/arch/arm/src/xmc4/xmc4_gpio.h +++ b/arch/arm/src/xmc4/xmc4_gpio.h @@ -65,18 +65,18 @@ /* See chip/xmc4_ports.h for the IOCR definitions */ /* Direct input */ -# define GPIO_INPUT (IOCR_INPUT_NOPULL << GPIO_PINTYPE_SHIFT) -# define GPIO_INPUT_PULLDOWN (IOCR_INPUT_PULLDOWN << GPIO_PINTYPE_SHIFT) -# define GPIO_INPUT_PULLUP (IOCR_INPUT_PULLUP << GPIO_PINTYPE_SHIFT) -# define GPIO_INPUT_CONT (IOCR_INPUT_CONT << GPIO_PINTYPE_SHIFT) +# define GPIO_INPUT (IOCR_INPUT_NOPULL << GPIO_PINTYPE_SHIFT) +# define GPIO_INPUT_PULLDOWN (IOCR_INPUT_PULLDOWN << GPIO_PINTYPE_SHIFT) +# define GPIO_INPUT_PULLUP (IOCR_INPUT_PULLUP << GPIO_PINTYPE_SHIFT) +# define GPIO_INPUT_CONT (IOCR_INPUT_CONT << GPIO_PINTYPE_SHIFT) /* Push-pull Output (direct input) */ -# define GPIO_OUTPUT (IOCR_OUTPUT << GPIO_PINTYPE_SHIFT) -# define GPIO_OUTPUT_ALT1 (IOCR_OUTPUT_ALT1 << GPIO_PINTYPE_SHIFT) -# define GPIO_OUTPUT_ALT2 (IOCR_OUTPUT_ALT2 << GPIO_PINTYPE_SHIFT) -# define GPIO_OUTPUT_ALT3 (IOCR_OUTPUT_ALT3 << GPIO_PINTYPE_SHIFT) -# define GPIO_OUTPUT_ALT4 (IOCR_OUTPUT_ALT4 << GPIO_PINTYPE_SHIFT) +# define GPIO_OUTPUT (IOCR_OUTPUT << GPIO_PINTYPE_SHIFT) +# define GPIO_OUTPUT_ALT1 (IOCR_OUTPUT_ALT1 << GPIO_PINTYPE_SHIFT) +# define GPIO_OUTPUT_ALT2 (IOCR_OUTPUT_ALT2 << GPIO_PINTYPE_SHIFT) +# define GPIO_OUTPUT_ALT3 (IOCR_OUTPUT_ALT3 << GPIO_PINTYPE_SHIFT) +# define GPIO_OUTPUT_ALT4 (IOCR_OUTPUT_ALT4 << GPIO_PINTYPE_SHIFT) # define _GPIO_OUTPUT_BIT (16 << GPIO_PINTYPE_SHIFT) # define GPIO_ISINPUT(p) (((p) & _GPIO_OUTPUT_BIT) == 0) @@ -161,16 +161,16 @@ #define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */ #define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) -# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT) -# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT) -# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT) -# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT) -# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT) -# define GPIO_PORT5 (5 << GPIO_PORT_SHIFT) -# define GPIO_PORT6 (6 << GPIO_PORT_SHIFT) -# define GPIO_PORT7 (7 << GPIO_PORT_SHIFT) -# define GPIO_PORT8 (8 << GPIO_PORT_SHIFT) -# define GPIO_PORT9 (9 << GPIO_PORT_SHIFT) +# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT) +# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT) +# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT) +# define GPIO_PORT4 (4 << GPIO_PORT_SHIFT) +# define GPIO_PORT5 (5 << GPIO_PORT_SHIFT) +# define GPIO_PORT6 (6 << GPIO_PORT_SHIFT) +# define GPIO_PORT7 (7 << GPIO_PORT_SHIFT) +# define GPIO_PORT8 (8 << GPIO_PORT_SHIFT) +# define GPIO_PORT9 (9 << GPIO_PORT_SHIFT) # define GPIO_PORT14 (14 << GPIO_PORT_SHIFT) # define GPIO_PORT15 (15 << GPIO_PORT_SHIFT) diff --git a/arch/arm/src/xmc4/xmc4_lowputc.c b/arch/arm/src/xmc4/xmc4_lowputc.c index 3e374106d0422c0d31fd4076017542a0958719e2..5c673644632039e86517ac681681617e23f9a9ac 100644 --- a/arch/arm/src/xmc4/xmc4_lowputc.c +++ b/arch/arm/src/xmc4/xmc4_lowputc.c @@ -47,9 +47,11 @@ #include "up_internal.h" #include "up_arch.h" +#include #include "xmc4_config.h" #include "chip/xmc4_usic.h" +#include "chip/xmc4_ports.h" #include "chip/xmc4_pinmux.h" #include "xmc4_usic.h" #include "xmc4_gpio.h" @@ -199,28 +201,28 @@ void xmc4_lowsetup(void) */ #ifdef HAVE_UART0 - (void)xmc4_gpio_config(GPIO_UART0_RXD0); - (void)xmc4_gpio_config(GPIO_UART0_TXD0); + (void)xmc4_gpio_config(GPIO_UART0_RXD); + (void)xmc4_gpio_config(GPIO_UART0_TXD); #endif #ifdef HAVE_UART1 - (void)xmc4_gpio_config(GPIO_UART0_RXD1); - (void)xmc4_gpio_config(GPIO_UART0_TXD1); + (void)xmc4_gpio_config(GPIO_UART1_RXD); + (void)xmc4_gpio_config(GPIO_UART1_TXD); #endif #ifdef HAVE_UART2 - (void)xmc4_gpio_config(GPIO_UART0_RXD2); - (void)xmc4_gpio_config(GPIO_UART0_TXD2); + (void)xmc4_gpio_config(GPIO_UART2_RXD); + (void)xmc4_gpio_config(GPIO_UART2_TXD); #endif #ifdef HAVE_UART3 - (void)xmc4_gpio_config(GPIO_UART0_RXD3); - (void)xmc4_gpio_config(GPIO_UART0_TXD3); + (void)xmc4_gpio_config(GPIO_UART3_RXD); + (void)xmc4_gpio_config(GPIO_UART3_TXD); #endif #ifdef HAVE_UART4 - (void)xmc4_gpio_config(GPIO_UART0_RXD4); - (void)xmc4_gpio_config(GPIO_UART0_TXD4); + (void)xmc4_gpio_config(GPIO_UART4_RXD); + (void)xmc4_gpio_config(GPIO_UART4_TXD); #endif #ifdef HAVE_UART5 - (void)xmc4_gpio_config(GPIO_UART0_RXD5); - (void)xmc4_gpio_config(GPIO_UART0_TXD5); + (void)xmc4_gpio_config(GPIO_UART5_RXD); + (void)xmc4_gpio_config(GPIO_UART5_TXD); #endif #ifdef HAVE_UART_CONSOLE @@ -286,11 +288,15 @@ int xmc4_uart_configure(enum usic_channel_e channel, regval = USIC_PCR_ASCMODE_PLBIT | USIC_PCR_ASCMODE_SMD; - /* - Sampling point set equal to the half of the oversampling period */ + /* Enable the receive and transmit status */ + + regval |= USIC_PCR_ASCMODE_RSTEN | USIC_PCR_ASCMODE_TSTEN; + + /* Sampling point set equal to the half of the oversampling period */ regval |= USIC_PCR_ASCMODE_SP((UART_OVERSAMPLING >> 1) + 1); - /* - Configure the number of stop bits */ + /* Configure the number of stop bits */ if (config->stop2) { @@ -309,7 +315,7 @@ int xmc4_uart_configure(enum usic_channel_e channel, * - Set frame length equal to the word length */ - regval = USIC_SCTR_PDL0 | USIC_SCTR_TRM_1LEVEL | + regval = USIC_SCTR_PDL1 | USIC_SCTR_TRM_1LEVEL | USIC_SCTR_FLE(config->nbits) | USIC_SCTR_WLE(config->nbits); putreg32(regval, base + XMC4_USIC_SCTR_OFFSET); @@ -372,8 +378,8 @@ int xmc4_uart_configure(enum usic_channel_e channel, * a data word */ - regval &= ~(USIC_TBCTR_DPTR_MASK | USIC_TBCTR_LIMIT_MASK | USIC_RBCTR_SRBTEN | - USIC_TBCTR_SIZE_MASK | USIC_RBCTR_LOF); + regval &= ~(USIC_TBCTR_DPTR_MASK | USIC_TBCTR_LIMIT_MASK | USIC_TBCTR_STBTEN | + USIC_TBCTR_SIZE_MASK | USIC_TBCTR_LOF); regval |= (USIC_TBCTR_DPTR(16) | USIC_TBCTR_LIMIT(1) | USIC_TBCTR_SIZE_16); putreg32(regval, base + XMC4_USIC_TBCTR_OFFSET); @@ -386,8 +392,8 @@ int xmc4_uart_configure(enum usic_channel_e channel, /* Configure receive FIFO. * * - DPTR = 0 - * - LIMIT = 15 - * - SIZE = 16 + * - LIMIT = 16 + * - SIZE = 15 * - LOF = 1, A standard receive buffer event occurs when the filling * level equals the limit value and gets bigger due to the reception * of a new data word @@ -411,15 +417,18 @@ int xmc4_uart_configure(enum usic_channel_e channel, */ regval = getreg32(base + XMC4_USIC_INPR_OFFSET); - regval &= ~(USIC_INPR_TBINP_MASK | USIC_INPR_RINP_MASK | USIC_INPR_PINP_MASK); + regval &= ~(USIC_INPR_TBINP_MASK | USIC_INPR_RINP_MASK | + USIC_INPR_AINP_MASK | USIC_INPR_PINP_MASK); if (((unsigned int)channel & 1) != 0) { - regval |= (USIC_INPR_TBINP_SR1 | USIC_INPR_RINP_SR1 | USIC_INPR_PINP_SR1); + regval |= (USIC_INPR_TBINP_SR1 | USIC_INPR_RINP_SR1 | + USIC_INPR_AINP_SR1 | USIC_INPR_PINP_SR1); } else { - regval |= (USIC_INPR_TBINP_SR0 | USIC_INPR_RINP_SR0 | USIC_INPR_PINP_SR0); + regval |= (USIC_INPR_TBINP_SR0 | USIC_INPR_RINP_SR0 | + USIC_INPR_AINP_SR0 | USIC_INPR_PINP_SR0); } putreg32(regval, base + XMC4_USIC_INPR_OFFSET); diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c index d9eaf0db53d1cd84c0e4fcaa924b79ed7e45474b..fef3ac077343de3e9ec41c502ed8034652afbdf9 100644 --- a/arch/arm/src/xmc4/xmc4_serial.c +++ b/arch/arm/src/xmc4/xmc4_serial.c @@ -226,9 +226,9 @@ /* Event sets */ #ifdef CONFIG_DEBUG_FEATURES -# define CCR_RX_EVENTS (USIC_CCR_RIEN | USIC_CCR_DLIEN) +# define CCR_RX_EVENTS (USIC_CCR_RIEN | USIC_CCR_AIEN | USIC_CCR_DLIEN) #else -# define CCR_RX_EVENTS (USIC_CCR_RIEN) +# define CCR_RX_EVENTS (USIC_CCR_RIEN | USIC_CCR_AIEN) #endif #define CCR_TX_EVENTS (USIC_CCR_TBIEN) @@ -320,7 +320,7 @@ static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; #endif -/* This describes the state of the Kinetis UART0 port. */ +/* This describes the state of the XMC4 UART0 port. */ #ifdef HAVE_UART0 static struct xmc4_dev_s g_uart0priv = @@ -355,7 +355,7 @@ static uart_dev_t g_uart0port = }; #endif -/* This describes the state of the Kinetis UART1 port. */ +/* This describes the state of the XMC4 UART1 port. */ #ifdef HAVE_UART1 static struct xmc4_dev_s g_uart1priv = @@ -390,7 +390,7 @@ static uart_dev_t g_uart1port = }; #endif -/* This describes the state of the Kinetis UART2 port. */ +/* This describes the state of the XMC4 UART2 port. */ #ifdef HAVE_UART2 static struct xmc4_dev_s g_uart2priv = @@ -425,7 +425,7 @@ static uart_dev_t g_uart2port = }; #endif -/* This describes the state of the Kinetis UART3 port. */ +/* This describes the state of the XMC4 UART3 port. */ #ifdef HAVE_UART3 static struct xmc4_dev_s g_uart3priv = @@ -460,7 +460,7 @@ static uart_dev_t g_uart3port = }; #endif -/* This describes the state of the Kinetis UART4 port. */ +/* This describes the state of the XMC4 UART4 port. */ #ifdef HAVE_UART4 static struct xmc4_dev_s g_uart4priv = @@ -495,7 +495,7 @@ static uart_dev_t g_uart4port = }; #endif -/* This describes the state of the Kinetis UART5 port. */ +/* This describes the state of the XMC4 UART5 port. */ #ifdef HAVE_UART5 static struct xmc4_dev_s g_uart5priv = @@ -644,7 +644,7 @@ static int xmc4_setup(struct uart_dev_s *dev) /* Configure the UART as an RS-232 UART */ - xmc4_uart_configure(priv->uartbase, &priv->config); + xmc4_uart_configure(priv->channel, &priv->config); #endif /* Make sure that all interrupts are disabled */ @@ -916,7 +916,7 @@ static bool xmc4_rxavailable(struct uart_dev_s *dev) struct xmc4_dev_s *priv = (struct xmc4_dev_s *)dev->priv; uint32_t regval; - /* Return true if the transmit buffer/fifo is not "empty." */ + /* Return true if the receive buffer/fifo is not "empty." */ regval = xmc4_serialin(priv, XMC4_USIC_TRBSR_OFFSET); return ((regval & USIC_TRBSR_REMPTY) == 0); diff --git a/arch/arm/src/xmc4/xmc4_timerisr.c b/arch/arm/src/xmc4/xmc4_timerisr.c index dd23b8e2db1a917435aad5b272600f1b9b1a6d75..5f8f2c7f9f7dc2480480c710f39da60fd29c1ce5 100644 --- a/arch/arm/src/xmc4/xmc4_timerisr.c +++ b/arch/arm/src/xmc4/xmc4_timerisr.c @@ -67,7 +67,7 @@ * common system clock of 10 msec/tick cannot be exactly represented with * that value. * - * In the second case, the SysTick counter may run to rapidly to support + * In the second case, the SysTick counter may run too rapidly to support * longer timer tick intervals. For example, if the CPU clock is 144Mhz, * then that 10 msec interval would correspond to a reload value of 1,440,000 * or 0x0015f900. @@ -134,7 +134,7 @@ void arm_timer_initialize(void) /* Set the SysTick interrupt to the default priority */ - regval = getreg32(NVIC_SYSH12_15_PRIORITY); + regval = getreg32(NVIC_SYSH12_15_PRIORITY); regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); putreg32(regval, NVIC_SYSH12_15_PRIORITY); @@ -150,7 +150,7 @@ void arm_timer_initialize(void) * CLKSOURCE=1: fCPU */ - regval = getreg32(NVIC_SYSTICK_CTRL); + regval = getreg32(NVIC_SYSTICK_CTRL); regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; putreg32(regval, NVIC_SYSTICK_CTRL); #endif diff --git a/arch/mips/include/pic32mz/chip.h b/arch/mips/include/pic32mz/chip.h index d36c45152529be38156f738e8a9abb523c003bd7..c54679c66af76063216b4b43d769e36dad7d67f2 100644 --- a/arch/mips/include/pic32mz/chip.h +++ b/arch/mips/include/pic32mz/chip.h @@ -1,7 +1,7 @@ /**************************************************************************** * arch/mips/include/pic32mz/chip.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -52,7 +52,8 @@ */ #if defined(CONFIG_ARCH_CHIP_PIC32MZ2048ECH) -# define CHIP_PIC32MZEC 1 +# define CHIP_PIC32MZEC 1 /* PIC32MZEC family */ +# undef CHIP_PIC32MZEF /* Not PIC32MZEF family */ # define CHIP_BOOTFLASH_KB 160 /* 160Kb boot FLASH */ # define CHIP_PROGFLASH_KB 2048 /* 2048Kb program FLASH */ # define CHIP_DATAMEM_KB 512 /* 512Kb data memory */ @@ -63,7 +64,7 @@ # define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ # define CHIP_NSPI 6 /* 6 SPI/I2S interfaces */ # define CHIP_NCAN 2 /* 2 CAN interfaces */ -# define CHIP_NCRTYPO 0 /* No crtypo support */ +# define CHIP_NCRTYPO 0 /* No crypto support */ # define CHIP_RNG 1 /* 1 Random number generator */ # define CHIP_NDMACH 8 /* 8 programmable DMA channels */ # define CHIP_NUSBDMACHAN 16 /* 16 dedicated DMA channels */ @@ -86,7 +87,8 @@ */ #elif defined(CONFIG_ARCH_CHIP_PIC32MZ2048ECM) -# define CHIP_PIC32MZEC 1 +# define CHIP_PIC32MZEC 1 /* PIC32MZEC family */ +# undef CHIP_PIC32MZEF /* Not PIC32MZEF family */ # define CHIP_BOOTFLASH_KB 160 /* 160Kb boot FLASH */ # define CHIP_PROGFLASH_KB 2048 /* 2048Kb program FLASH */ # define CHIP_DATAMEM_KB 512 /* 512Kb data memory */ @@ -97,7 +99,85 @@ # define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ # define CHIP_NSPI 6 /* 6 SPI/I2S interfaces */ # define CHIP_NCAN 2 /* 2 CAN interfaces */ -# define CHIP_NCRTYPO 1 /* Has crtypo support */ +# define CHIP_NCRTYPO 1 /* Has crypto support */ +# define CHIP_RNG 1 /* 1 Random number generator */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 18 /* 18 dedicated DMA channels */ +# define CHIP_NADC10 48 /* 48 ADC channels */ +# define CHIP_NCM 2 /* 2 Analog comparators */ +# define CHIP_USBHSOTG 1 /* 1 USB 2.0 HSOTG */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NPMP 1 /* Have parallel master port */ +# define CHIP_NEBI 1 /* Have eternal bus interface */ +# define CHIP_NSQI 1 /* 1 Serial quad interface */ +# define CHIP_NRTCC 1 /* Has RTCC */ +# define CHIP_NETHERNET 1 /* 1 Ethernet MAC */ +# define CHIP_NPORTS 10 /* 10 ports (A-H, J-K) */ +# define CHIP_NJTAG 1 /* Has JTAG */ +# define CHIP_NTRACE 1 /* Has trace capability */ + +/* Available in 64/100/124/144 pin packages. Description here is specifically + * for the 124 and 144 pin packages (PIC32MZ2048EFH1100, and + * PIC32MZ2048EFH144). The PIC32MZ2048EFH1100 differs in that it has only + * 40 ADC channels. The PIC32MZ2048EFH1064 differs in that it has only 24 ADC + * channels, two fewer SPI/I2S, one fewer I2C, and no EBI. There are + * additional differences between all family members in the number of pins + * how they may be mapped. + */ + +#elif defined(CONFIG_ARCH_CHIP_PIC32MZ2048EFH) +# undef CHIP_PIC32MZEC /* Not PIC32MZEC family */ +# define CHIP_PIC32MZEF 1 /* PIC32MZEF family */ +# define CHIP_BOOTFLASH_KB 160 /* 160Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 2048 /* 2048Kb program FLASH */ +# define CHIP_DATAMEM_KB 512 /* 512Kb data memory */ +# define CHIP_NTIMERS 9 /* 5 timers */ +# define CHIP_NIC 9 /* 5 input capture */ +# define CHIP_NOC 9 /* 5 output compare */ +# define CHIP_NUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 6 /* 6 SPI/I2S interfaces */ +# define CHIP_NCAN 2 /* 2 CAN 2.0B interfaces */ +# define CHIP_NCRTYPO 0 /* No crypto support */ +# define CHIP_RNG 1 /* 1 Random number generator */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 16 /* 16 dedicated DMA channels */ +# define CHIP_NADC10 48 /* 48 ADC channels */ +# define CHIP_NCM 2 /* 2 Analog comparators */ +# define CHIP_USBHSOTG 1 /* 1 USB 2.0 HSOTG */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NPMP 1 /* Have parallel master port */ +# define CHIP_NEBI 1 /* Have eternal bus interface */ +# define CHIP_NSQI 1 /* 1 Serial quad interface */ +# define CHIP_NRTCC 1 /* Has RTCC */ +# define CHIP_NETHERNET 1 /* 1 Ethernet MAC */ +# define CHIP_NPORTS 10 /* 10 ports (A-H, J-K) */ +# define CHIP_NJTAG 1 /* Has JTAG */ +# define CHIP_NTRACE 1 /* Has trace capability */ + +/* Available in 64/100/124/144 pin packages. Description here is specifically + * for the 124, and 144 pin packages (PIC32MZ2048EFM124, and + * PIC32MZ2048EFH144). The PIC32MZ2048EFM100 differs in that it has only 40 + * ADC channels. The PIC32MZ2048EFM064 differs in that it has only 24 ADC + * channels, two fewer SPI/I2S, one fewer I2C, and no EBI. There are + * additional differences between all family members in the number of pins + * how they may be mapped. + */ + +#elif defined(CONFIG_ARCH_CHIP_PIC32MZ2048EFM) +# undef CHIP_PIC32MZEC /* Not PIC32MZEC family */ +# define CHIP_PIC32MZEF 1 /* PIC32MZEF family */ +# define CHIP_BOOTFLASH_KB 160 /* 160Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 2048 /* 2048Kb program FLASH */ +# define CHIP_DATAMEM_KB 512 /* 512Kb data memory */ +# define CHIP_NTIMERS 9 /* 5 timers */ +# define CHIP_NIC 9 /* 5 input capture */ +# define CHIP_NOC 9 /* 5 output compare */ +# define CHIP_NUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */ +# define CHIP_NSPI 6 /* 6 SPI/I2S interfaces */ +# define CHIP_NCAN 2 /* 2 CAN 2.0B interfaces */ +# define CHIP_NCRTYPO 1 /* Has crypto support */ # define CHIP_RNG 1 /* 1 Random number generator */ # define CHIP_NDMACH 8 /* 8 programmable DMA channels */ # define CHIP_NUSBDMACHAN 18 /* 18 dedicated DMA channels */ diff --git a/arch/mips/include/pic32mz/irq.h b/arch/mips/include/pic32mz/irq.h index f00dc0bebaf79bcd078a1ce16060cabd99a0cb88..06d36b0d067368c25ddc359a4b3ba39ae6edb306 100644 --- a/arch/mips/include/pic32mz/irq.h +++ b/arch/mips/include/pic32mz/irq.h @@ -1,7 +1,7 @@ /**************************************************************************** * arch/mips/include/pic32mz/irq.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -49,6 +49,8 @@ #if defined(CHIP_PIC32MZEC) # include +#elif defined(CHIP_PIC32MZEF) +# include #else # error "Unknown PIC32MZ family #endif diff --git a/arch/mips/include/pic32mz/irq_pic32mzxxxec.h b/arch/mips/include/pic32mz/irq_pic32mzxxxec.h index 64c0727c4dc1b90c01c02dd8d3d1c82812422a4f..bbbd534adc24d4341100b680e43d3da7d03bf609 100644 --- a/arch/mips/include/pic32mz/irq_pic32mzxxxec.h +++ b/arch/mips/include/pic32mz/irq_pic32mzxxxec.h @@ -62,6 +62,7 @@ #define PIC32MZ_IRQ_OC1 7 /* Vector: 7, Output Compare 1 */ #define PIC32MZ_IRQ_INT1 8 /* Vector: 8, External Interrupt 1 */ #define PIC32MZ_IRQ_T2 9 /* Vector: 9, Timer 2 */ + #define PIC32MZ_IRQ_ICE2 10 /* Vector: 10, Input Capture 2 Error */ #define PIC32MZ_IRQ_IC2 11 /* Vector: 11, Input Capture 2 */ #define PIC32MZ_IRQ_OC2 12 /* Vector: 12, Output Compare 2 */ @@ -72,6 +73,7 @@ #define PIC32MZ_IRQ_OC3 17 /* Vector: 17, Output Compare 3 */ #define PIC32MZ_IRQ_INT3 18 /* Vector: 18, External Interrupt 3 */ #define PIC32MZ_IRQ_T4 19 /* Vector: 19, Timer 4 */ + #define PIC32MZ_IRQ_ICE4 20 /* Vector: 20, Input Capture 4 Error */ #define PIC32MZ_IRQ_IC4 21 /* Vector: 21, Input Capture 4 */ #define PIC32MZ_IRQ_OC4 22 /* Vector: 22, Output Compare 4 */ @@ -82,6 +84,7 @@ #define PIC32MZ_IRQ_OC5 27 /* Vector: 27, Output Compare 5 */ #define PIC32MZ_IRQ_T6 28 /* Vector: 28, Timer 6 */ #define PIC32MZ_IRQ_ICE6 29 /* Vector: 29, Input Capture 6 Error */ + #define PIC32MZ_IRQ_IC6 30 /* Vector: 30, Input Capture 6 */ #define PIC32MZ_IRQ_OC6 31 /* Vector: 31, Output Compare 6 */ #define PIC32MZ_IRQ_T7 32 /* Vector: 32, Timer 7 */ @@ -92,6 +95,7 @@ #define PIC32MZ_IRQ_ICE8 37 /* Vector: 37, Input Capture 8 Error */ #define PIC32MZ_IRQ_IC8 38 /* Vector: 38, Input Capture 8 */ #define PIC32MZ_IRQ_OC8 39 /* Vector: 39, Output Compare 8 */ + #define PIC32MZ_IRQ_T9 40 /* Vector: 40, Timer 9 */ #define PIC32MZ_IRQ_ICE9 41 /* Vector: 41, Input Capture 9 Error */ #define PIC32MZ_IRQ_IC9 42 /* Vector: 42, Input Capture 9 */ @@ -102,6 +106,7 @@ #define PIC32MZ_IRQ_AD1CMP2 47 /* Vector: 47, ADC1 Digital Comparator 2 */ #define PIC32MZ_IRQ_AD1CMP3 48 /* Vector: 48, ADC1 Digital Comparator 3 */ #define PIC32MZ_IRQ_AD1CMP4 49 /* Vector: 49, ADC1 Digital Comparator 4 */ + #define PIC32MZ_IRQ_AD1CMP5 50 /* Vector: 50, ADC1 Digital Comparator 5 */ #define PIC32MZ_IRQ_AD1CMP6 51 /* Vector: 51, ADC1 Digital Comparator 6 */ #define PIC32MZ_IRQ_AD1FLT1 52 /* Vector: 52, ADC1 Digital Filter 1 */ @@ -112,6 +117,7 @@ #define PIC32MZ_IRQ_AD1FLT6 57 /* Vector: 57, ADC1 Digital Filter 6 */ /* Vector: 58, Reserved */ #define PIC32MZ_IRQ_AD1DAT0 59 /* Vector: 59, ADC1 Data 0 */ + #define PIC32MZ_IRQ_AD1DAT1 60 /* Vector: 60, ADC1 Data 1 */ #define PIC32MZ_IRQ_AD1DAT2 61 /* Vector: 61, ADC1 Data 2 */ #define PIC32MZ_IRQ_AD1DAT3 62 /* Vector: 62, ADC1 Data 3 */ @@ -122,6 +128,7 @@ #define PIC32MZ_IRQ_AD1DAT8 67 /* Vector: 67, ADC1 Data 8 */ #define PIC32MZ_IRQ_AD1DAT9 68 /* Vector: 68, ADC1 Data 9 */ #define PIC32MZ_IRQ_AD1DAT10 69 /* Vector: 69, ADC1 Data 10 */ + #define PIC32MZ_IRQ_AD1DAT11 70 /* Vector: 70, ADC1 Data 11 */ #define PIC32MZ_IRQ_AD1DAT12 71 /* Vector: 71, ADC1 Data 12 */ #define PIC32MZ_IRQ_AD1DAT13 72 /* Vector: 72, ADC1 Data 13 */ @@ -132,6 +139,7 @@ #define PIC32MZ_IRQ_AD1DAT18 77 /* Vector: 77, ADC1 Data 18 */ #define PIC32MZ_IRQ_AD1DAT19 78 /* Vector: 78, ADC1 Data 19 */ #define PIC32MZ_IRQ_AD1DAT20 79 /* Vector: 79, ADC1 Data 20 */ + #define PIC32MZ_IRQ_AD1DAT21 80 /* Vector: 80, ADC1 Data 21 */ #define PIC32MZ_IRQ_AD1DAT22 81 /* Vector: 81, ADC1 Data 22 */ #define PIC32MZ_IRQ_AD1DAT23 82 /* Vector: 82, ADC1 Data 23 */ @@ -142,6 +150,7 @@ #define PIC32MZ_IRQ_AD1DAT28 87 /* Vector: 87, ADC1 Data 28 */ #define PIC32MZ_IRQ_AD1DAT29 88 /* Vector: 88, ADC1 Data 29 */ #define PIC32MZ_IRQ_AD1DAT30 89 /* Vector: 89, ADC1 Data 30 */ + #define PIC32MZ_IRQ_AD1DAT31 90 /* Vector: 90, ADC1 Data 31 */ #define PIC32MZ_IRQ_AD1DAT32 91 /* Vector: 91, ADC1 Data 32 */ #define PIC32MZ_IRQ_AD1DAT33 92 /* Vector: 92, ADC1 Data 33 */ @@ -152,6 +161,7 @@ #define PIC32MZ_IRQ_AD1DAT38 97 /* Vector: 97, ADC1 Data 38 */ #define PIC32MZ_IRQ_AD1DAT39 98 /* Vector: 98, ADC1 Data 39 */ #define PIC32MZ_IRQ_AD1DAT40 99 /* Vector: 99, ADC1 Data 40 */ + #define PIC32MZ_IRQ_AD1DAT41 100 /* Vector: 100, ADC1 Data 41 */ #define PIC32MZ_IRQ_AD1DAT42 101 /* Vector: 101, ADC1 Data 42 */ #define PIC32MZ_IRQ_AD1DAT43 102 /* Vector: 102, ADC1 Data 43 */ @@ -162,6 +172,7 @@ #define PIC32MZ_IRQ_CTYPTO 107 /* Vector: 107, Crypto Engine Event */ /* Vector: 108, Reserved */ #define PIC32MZ_IRQ_SPI1F 109 /* Vector: 109, SPI1 Fault */ + #define PIC32MZ_IRQ_SPI1RX 110 /* Vector: 110, SPI1 Receive Done */ #define PIC32MZ_IRQ_SPI1TX 111 /* Vector: 111, SPI1 Transfer Done */ #define PIC32MZ_IRQ_U1E 112 /* Vector: 112, UART1 Fault */ @@ -172,6 +183,7 @@ #define PIC32MZ_IRQ_I2C1M 117 /* Vector: 117, I2C1 Master Event */ #define PIC32MZ_IRQ_PORTA 118 /* Vector: 118, PORTA Input Change Interrupt */ #define PIC32MZ_IRQ_PORTB 119 /* Vector: 119, PORTB Input Change Interrupt */ + #define PIC32MZ_IRQ_PORTC 120 /* Vector: 120, PORTC Input Change Interrupt */ #define PIC32MZ_IRQ_PORTD 121 /* Vector: 121, PORTD Input Change Interrupt */ #define PIC32MZ_IRQ_PORTE 122 /* Vector: 122, PORTE Input Change Interrupt */ @@ -182,6 +194,7 @@ #define PIC32MZ_IRQ_PORTK 127 /* Vector: 127, PORTK Input Change Interrupt */ #define PIC32MZ_IRQ_PMP 128 /* Vector: 128, Parallel Master Port */ #define PIC32MZ_IRQ_PMPE 129 /* Vector: 129, Parallel Master Port Error */ + #define PIC32MZ_IRQ_CMP1 130 /* Vector: 130, Comparator 1 Interrupt */ #define PIC32MZ_IRQ_CMP2 131 /* Vector: 131, Comparator 2 Interrupt */ #define PIC32MZ_IRQ_USBGEN 132 /* Vector: 132, USB General Event */ @@ -192,6 +205,7 @@ #define PIC32MZ_IRQ_DMA3 137 /* Vector: 137, DMA Channel 3 */ #define PIC32MZ_IRQ_DMA4 138 /* Vector: 138, DMA Channel 4 */ #define PIC32MZ_IRQ_DMA5 139 /* Vector: 139, DMA Channel 5 */ + #define PIC32MZ_IRQ_DMA6 140 /* Vector: 140, DMA Channel 6 */ #define PIC32MZ_IRQ_DMA7 141 /* Vector: 141, DMA Channel 7 */ #define PIC32MZ_IRQ_SPI2F 142 /* Vector: 142, SPI2 Fault */ @@ -202,6 +216,7 @@ #define PIC32MZ_IRQ_U2TX 147 /* Vector: 147, UART2 Transfer Done */ #define PIC32MZ_IRQ_I2C2COL 148 /* Vector: 148, I2C2 Bus Collision Event */ #define PIC32MZ_IRQ_I2C2S 149 /* Vector: 149, I2C2 Slave Event */ + #define PIC32MZ_IRQ_I2C2M 150 /* Vector: 150, I2C2 Master Event */ #define PIC32MZ_IRQ_CAN1 151 /* Vector: 151, Control Area Network 1 */ #define PIC32MZ_IRQ_CAN2 152 /* Vector: 152, Control Area Network 2 */ @@ -212,7 +227,8 @@ #define PIC32MZ_IRQ_U3E 157 /* Vector: 157, UART3 Fault */ #define PIC32MZ_IRQ_U3RX 158 /* Vector: 158, UART3 Receive Done */ #define PIC32MZ_IRQ_U3TX 159 /* Vector: 159, UART3 Transfer Done */ -#define PIC32MZ_IRQ_I2C3COL 160 /* Vector: 160, I2C3 Bus Collision Event */ + +#define PIC32MZ_IRQ_I2C3COL 160 /* Vector: 160, I2C3 Bus Collision Event */ #define PIC32MZ_IRQ_I2C3S 161 /* Vector: 161, I2C3 Slave Event */ #define PIC32MZ_IRQ_I2C3M 162 /* Vector: 162, I2C3 Master Event */ #define PIC32MZ_IRQ_SPI4F 163 /* Vector: 163, SPI4 Fault */ @@ -222,6 +238,7 @@ #define PIC32MZ_IRQ_FCE 167 /* Vector: 167, Flash Control Event */ #define PIC32MZ_IRQ_PMSEC 168 /* Vector: 168, Prefetch Module SEC Event */ #define PIC32MZ_IRQ_SQI1 169 /* Vector: 169, SQI1 Event */ + #define PIC32MZ_IRQ_U4E 170 /* Vector: 170, UART4 Fault */ #define PIC32MZ_IRQ_U4RX 171 /* Vector: 171, UART4 Receive Done */ #define PIC32MZ_IRQ_U4TX 172 /* Vector: 172, UART4 Transfer Done */ @@ -232,6 +249,7 @@ #define PIC32MZ_IRQ_SPI5RX 177 /* Vector: 177, SPI5 Receive Done */ #define PIC32MZ_IRQ_SPI5TX 178 /* Vector: 178, SPI5 Transfer Done */ #define PIC32MZ_IRQ_U5E 179 /* Vector: 179, UART5 Fault */ + #define PIC32MZ_IRQ_U5RX 180 /* Vector: 180, UART5 Receive Done */ #define PIC32MZ_IRQ_U5TX 181 /* Vector: 181, UART5 Transfer Done */ #define PIC32MZ_IRQ_I2C5COL 182 /* Vector: 182, I2C5 Bus Collision Event */ @@ -242,6 +260,7 @@ #define PIC32MZ_IRQ_SPI6TX 187 /* Vector: 187, SPI6 Transfer Done */ #define PIC32MZ_IRQ_U6E 188 /* Vector: 188, UART6 Fault */ #define PIC32MZ_IRQ_U6RX 189 /* Vector: 189, UART6 Receive Done */ + #define PIC32MZ_IRQ_U6TX 190 /* Vector: 190, UART6 Transfer Done */ #define PIC32MZ_IRQ_BAD 191 /* Not a real IRQ number */ diff --git a/arch/mips/include/pic32mz/irq_pic32mzxxxef.h b/arch/mips/include/pic32mz/irq_pic32mzxxxef.h new file mode 100644 index 0000000000000000000000000000000000000000..e1e1dd6d754058b76b853472de3bb00e9330a751 --- /dev/null +++ b/arch/mips/include/pic32mz/irq_pic32mzxxxef.h @@ -0,0 +1,325 @@ +/**************************************************************************** + * arch/mips/include/pic32mz/irq_pic32mzxxxef.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_MIPS_INCLUDE_PIC32MZ_IRQ_PIC32MZXXXEF_H +#define __ARCH_MIPS_INCLUDE_PIC32MZ_IRQ_PIC32MZXXXEF_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Interrupt vector numbers. These should be used to attach to interrupts + * and to change interrupt priorities. + */ + +#define PIC32MZ_IRQ_CT 0 /* Vector: 0, Core Timer Interrupt */ +#define PIC32MZ_IRQ_CS0 1 /* Vector: 1, Core Software Interrupt 0 */ +#define PIC32MZ_IRQ_CS1 2 /* Vector: 2, Core Software Interrupt 1 */ +#define PIC32MZ_IRQ_INT0 3 /* Vector: 3, External Interrupt 0 */ +#define PIC32MZ_IRQ_T1 4 /* Vector: 4, Timer 1 */ +#define PIC32MZ_IRQ_ICE1 5 /* Vector: 5, Input Capture 1 Error */ +#define PIC32MZ_IRQ_IC1 6 /* Vector: 6, Input Capture 1 */ +#define PIC32MZ_IRQ_OC1 7 /* Vector: 7, Output Compare 1 */ +#define PIC32MZ_IRQ_INT1 8 /* Vector: 8, External Interrupt 1 */ +#define PIC32MZ_IRQ_T2 9 /* Vector: 9, Timer 2 */ + +#define PIC32MZ_IRQ_ICE2 10 /* Vector: 10, Input Capture 2 Error */ +#define PIC32MZ_IRQ_IC2 11 /* Vector: 11, Input Capture 2 */ +#define PIC32MZ_IRQ_OC2 12 /* Vector: 12, Output Compare 2 */ +#define PIC32MZ_IRQ_INT2 13 /* Vector: 13, External Interrupt 2 */ +#define PIC32MZ_IRQ_T3 14 /* Vector: 14, Timer 3 */ +#define PIC32MZ_IRQ_ICE3 15 /* Vector: 15, Input Capture 3 Error */ +#define PIC32MZ_IRQ_IC3 16 /* Vector: 16, Input Capture 3 */ +#define PIC32MZ_IRQ_OC3 17 /* Vector: 17, Output Compare 3 */ +#define PIC32MZ_IRQ_INT3 18 /* Vector: 18, External Interrupt 3 */ +#define PIC32MZ_IRQ_T4 19 /* Vector: 19, Timer 4 */ + +#define PIC32MZ_IRQ_ICE4 20 /* Vector: 20, Input Capture 4 Error */ +#define PIC32MZ_IRQ_IC4 21 /* Vector: 21, Input Capture 4 */ +#define PIC32MZ_IRQ_OC4 22 /* Vector: 22, Output Compare 4 */ +#define PIC32MZ_IRQ_INT4 23 /* Vector: 23, External Interrupt 4 */ +#define PIC32MZ_IRQ_T5 24 /* Vector: 24, Timer 5 */ +#define PIC32MZ_IRQ_ICE5 25 /* Vector: 25, Input Capture 5 Error */ +#define PIC32MZ_IRQ_IC5 26 /* Vector: 26, Input Capture 5 */ +#define PIC32MZ_IRQ_OC5 27 /* Vector: 27, Output Compare 5 */ +#define PIC32MZ_IRQ_T6 28 /* Vector: 28, Timer 6 */ +#define PIC32MZ_IRQ_ICE6 29 /* Vector: 29, Input Capture 6 Error */ + +#define PIC32MZ_IRQ_IC6 30 /* Vector: 30, Input Capture 6 */ +#define PIC32MZ_IRQ_OC6 31 /* Vector: 31, Output Compare 6 */ +#define PIC32MZ_IRQ_T7 32 /* Vector: 32, Timer 7 */ +#define PIC32MZ_IRQ_ICE7 33 /* Vector: 33, Input Capture 7 Error */ +#define PIC32MZ_IRQ_IC7 34 /* Vector: 34, Input Capture 7 */ +#define PIC32MZ_IRQ_OC7 35 /* Vector: 35, Output Compare 7 */ +#define PIC32MZ_IRQ_T8 36 /* Vector: 36, Timer 8 */ +#define PIC32MZ_IRQ_ICE8 37 /* Vector: 37, Input Capture 8 Error */ +#define PIC32MZ_IRQ_IC8 38 /* Vector: 38, Input Capture 8 */ +#define PIC32MZ_IRQ_OC8 39 /* Vector: 39, Output Compare 8 */ + +#define PIC32MZ_IRQ_T9 40 /* Vector: 40, Timer 9 */ +#define PIC32MZ_IRQ_ICE9 41 /* Vector: 41, Input Capture 9 Error */ +#define PIC32MZ_IRQ_IC9 42 /* Vector: 42, Input Capture 9 */ +#define PIC32MZ_IRQ_OC9 43 /* Vector: 43, Output Compare 9 */ +#define PIC32MZ_IRQ_AD1 44 /* Vector: 44, ADC1 Global Interrupt */ +#define PIC32MZ_IRQ_AD1FIFO 45 /* Vector: 45, ADC1 FIFO Data Ready Interrupt */ +#define PIC32MZ_IRQ_AD1CMP1 46 /* Vector: 46, ADC1 Digital Comparator 1 */ +#define PIC32MZ_IRQ_AD1CMP2 47 /* Vector: 47, ADC1 Digital Comparator 2 */ +#define PIC32MZ_IRQ_AD1CMP3 48 /* Vector: 48, ADC1 Digital Comparator 3 */ +#define PIC32MZ_IRQ_AD1CMP4 49 /* Vector: 49, ADC1 Digital Comparator 4 */ + +#define PIC32MZ_IRQ_AD1CMP5 50 /* Vector: 50, ADC1 Digital Comparator 5 */ +#define PIC32MZ_IRQ_AD1CMP6 51 /* Vector: 51, ADC1 Digital Comparator 6 */ +#define PIC32MZ_IRQ_AD1FLT1 52 /* Vector: 52, ADC1 Digital Filter 1 */ +#define PIC32MZ_IRQ_AD1FLT2 53 /* Vector: 53, ADC1 Digital Filter 2 */ +#define PIC32MZ_IRQ_AD1FLT3 54 /* Vector: 54, ADC1 Digital Filter 3 */ +#define PIC32MZ_IRQ_AD1FLT4 55 /* Vector: 55, ADC1 Digital Filter 4 */ +#define PIC32MZ_IRQ_AD1FLT5 56 /* Vector: 56, ADC1 Digital Filter 5 */ +#define PIC32MZ_IRQ_AD1FLT6 57 /* Vector: 57, ADC1 Digital Filter 6 */ +#define PIC32MZ_IRQ_AD1FAULT 59 /* Vector: 58, ADC1 Fault */ +#define PIC32MZ_IRQ_AD1DAT0 59 /* Vector: 59, ADC1 Data 0 */ + +#define PIC32MZ_IRQ_AD1DAT1 60 /* Vector: 60, ADC1 Data 1 */ +#define PIC32MZ_IRQ_AD1DAT2 61 /* Vector: 61, ADC1 Data 2 */ +#define PIC32MZ_IRQ_AD1DAT3 62 /* Vector: 62, ADC1 Data 3 */ +#define PIC32MZ_IRQ_AD1DAT4 63 /* Vector: 63, ADC1 Data 4 */ +#define PIC32MZ_IRQ_AD1DAT5 64 /* Vector: 64, ADC1 Data 5 */ +#define PIC32MZ_IRQ_AD1DAT6 65 /* Vector: 65, ADC1 Data 6 */ +#define PIC32MZ_IRQ_AD1DAT7 66 /* Vector: 66, ADC1 Data 7 */ +#define PIC32MZ_IRQ_AD1DAT8 67 /* Vector: 67, ADC1 Data 8 */ +#define PIC32MZ_IRQ_AD1DAT9 68 /* Vector: 68, ADC1 Data 9 */ +#define PIC32MZ_IRQ_AD1DAT10 69 /* Vector: 69, ADC1 Data 10 */ + +#define PIC32MZ_IRQ_AD1DAT11 70 /* Vector: 70, ADC1 Data 11 */ +#define PIC32MZ_IRQ_AD1DAT12 71 /* Vector: 71, ADC1 Data 12 */ +#define PIC32MZ_IRQ_AD1DAT13 72 /* Vector: 72, ADC1 Data 13 */ +#define PIC32MZ_IRQ_AD1DAT14 73 /* Vector: 73, ADC1 Data 14 */ +#define PIC32MZ_IRQ_AD1DAT15 74 /* Vector: 74, ADC1 Data 15 */ +#define PIC32MZ_IRQ_AD1DAT16 75 /* Vector: 75, ADC1 Data 16 */ +#define PIC32MZ_IRQ_AD1DAT17 76 /* Vector: 76, ADC1 Data 17 */ +#define PIC32MZ_IRQ_AD1DAT18 77 /* Vector: 77, ADC1 Data 18 */ +#define PIC32MZ_IRQ_AD1DAT19 78 /* Vector: 78, ADC1 Data 19 */ +#define PIC32MZ_IRQ_AD1DAT20 79 /* Vector: 79, ADC1 Data 20 */ + +#define PIC32MZ_IRQ_AD1DAT21 80 /* Vector: 80, ADC1 Data 21 */ +#define PIC32MZ_IRQ_AD1DAT22 81 /* Vector: 81, ADC1 Data 22 */ +#define PIC32MZ_IRQ_AD1DAT23 82 /* Vector: 82, ADC1 Data 23 */ +#define PIC32MZ_IRQ_AD1DAT24 83 /* Vector: 83, ADC1 Data 24 */ +#define PIC32MZ_IRQ_AD1DAT25 84 /* Vector: 84, ADC1 Data 25 */ +#define PIC32MZ_IRQ_AD1DAT26 85 /* Vector: 85, ADC1 Data 26 */ +#define PIC32MZ_IRQ_AD1DAT27 86 /* Vector: 86, ADC1 Data 27 */ +#define PIC32MZ_IRQ_AD1DAT28 87 /* Vector: 87, ADC1 Data 28 */ +#define PIC32MZ_IRQ_AD1DAT29 88 /* Vector: 88, ADC1 Data 29 */ +#define PIC32MZ_IRQ_AD1DAT30 89 /* Vector: 89, ADC1 Data 30 */ + +#define PIC32MZ_IRQ_AD1DAT31 90 /* Vector: 90, ADC1 Data 31 */ +#define PIC32MZ_IRQ_AD1DAT32 91 /* Vector: 91, ADC1 Data 32 */ +#define PIC32MZ_IRQ_AD1DAT33 92 /* Vector: 92, ADC1 Data 33 */ +#define PIC32MZ_IRQ_AD1DAT34 93 /* Vector: 93, ADC1 Data 34 */ +#define PIC32MZ_IRQ_AD1DAT35 94 /* Vector: 94, ADC1 Data 35 */ +#define PIC32MZ_IRQ_AD1DAT36 95 /* Vector: 95, ADC1 Data 36 */ +#define PIC32MZ_IRQ_AD1DAT37 96 /* Vector: 96, ADC1 Data 37 */ +#define PIC32MZ_IRQ_AD1DAT38 97 /* Vector: 97, ADC1 Data 38 */ +#define PIC32MZ_IRQ_AD1DAT39 98 /* Vector: 98, ADC1 Data 39 */ +#define PIC32MZ_IRQ_AD1DAT40 99 /* Vector: 99, ADC1 Data 40 */ + +#define PIC32MZ_IRQ_AD1DAT41 100 /* Vector: 100, ADC1 Data 41 */ +#define PIC32MZ_IRQ_AD1DAT42 101 /* Vector: 101, ADC1 Data 42 */ +#define PIC32MZ_IRQ_AD1DAT43 102 /* Vector: 102, ADC1 Data 43 */ +#define PIC32MZ_IRQ_AD1DAT44 103 /* Vector: 103, ADC1 Data 44 */ +#define PIC32MZ_IRQ_COREPERF 104 /* Vector: 104, Core Performance Counter Interrupt */ +#define PIC32MZ_IRQ_COREFDBG 105 /* Vector: 105, Core Fast Debug Channel Interrupt */ +#define PIC32MZ_IRQ_BUSPROT 106 /* Vector: 106, System Bus Protection Violation */ +#define PIC32MZ_IRQ_CTYPTO 107 /* Vector: 107, Crypto Engine Event */ + /* Vector: 108, Reserved */ +#define PIC32MZ_IRQ_SPI1F 109 /* Vector: 109, SPI1 Fault */ + +#define PIC32MZ_IRQ_SPI1RX 110 /* Vector: 110, SPI1 Receive Done */ +#define PIC32MZ_IRQ_SPI1TX 111 /* Vector: 111, SPI1 Transfer Done */ +#define PIC32MZ_IRQ_U1E 112 /* Vector: 112, UART1 Fault */ +#define PIC32MZ_IRQ_U1RX 113 /* Vector: 113, UART1 Receive Done */ +#define PIC32MZ_IRQ_U1TX 114 /* Vector: 114, UART1 Transfer Done */ +#define PIC32MZ_IRQ_I2C1COL 115 /* Vector: 115, I2C1 Bus Collision Event */ +#define PIC32MZ_IRQ_I2C1S 116 /* Vector: 116, I2C1 Slave Event */ +#define PIC32MZ_IRQ_I2C1M 117 /* Vector: 117, I2C1 Master Event */ +#define PIC32MZ_IRQ_PORTA 118 /* Vector: 118, PORTA Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTB 119 /* Vector: 119, PORTB Input Change Interrupt */ + +#define PIC32MZ_IRQ_PORTC 120 /* Vector: 120, PORTC Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTD 121 /* Vector: 121, PORTD Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTE 122 /* Vector: 122, PORTE Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTF 123 /* Vector: 123, PORTF Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTG 124 /* Vector: 124, PORTG Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTH 125 /* Vector: 125, PORTH Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTJ 126 /* Vector: 126, PORTJ Input Change Interrupt */ +#define PIC32MZ_IRQ_PORTK 127 /* Vector: 127, PORTK Input Change Interrupt */ +#define PIC32MZ_IRQ_PMP 128 /* Vector: 128, Parallel Master Port */ +#define PIC32MZ_IRQ_PMPE 129 /* Vector: 129, Parallel Master Port Error */ + +#define PIC32MZ_IRQ_CMP1 130 /* Vector: 130, Comparator 1 Interrupt */ +#define PIC32MZ_IRQ_CMP2 131 /* Vector: 131, Comparator 2 Interrupt */ +#define PIC32MZ_IRQ_USBGEN 132 /* Vector: 132, USB General Event */ +#define PIC32MZ_IRQ_USBDMA 133 /* Vector: 133, USB DMA Event */ +#define PIC32MZ_IRQ_DMA0 134 /* Vector: 134, DMA Channel 0 */ +#define PIC32MZ_IRQ_DMA1 135 /* Vector: 135, DMA Channel 1 */ +#define PIC32MZ_IRQ_DMA2 136 /* Vector: 136, DMA Channel 2 */ +#define PIC32MZ_IRQ_DMA3 137 /* Vector: 137, DMA Channel 3 */ +#define PIC32MZ_IRQ_DMA4 138 /* Vector: 138, DMA Channel 4 */ +#define PIC32MZ_IRQ_DMA5 139 /* Vector: 139, DMA Channel 5 */ + +#define PIC32MZ_IRQ_DMA6 140 /* Vector: 140, DMA Channel 6 */ +#define PIC32MZ_IRQ_DMA7 141 /* Vector: 141, DMA Channel 7 */ +#define PIC32MZ_IRQ_SPI2F 142 /* Vector: 142, SPI2 Fault */ +#define PIC32MZ_IRQ_SPI2RX 143 /* Vector: 143, SPI2 Receive Done */ +#define PIC32MZ_IRQ_SPI2TX 144 /* Vector: 144, SPI2 Transfer Done */ +#define PIC32MZ_IRQ_U2E 145 /* Vector: 145, UART2 Fault */ +#define PIC32MZ_IRQ_U2RX 146 /* Vector: 146, UART2 Receive Done */ +#define PIC32MZ_IRQ_U2TX 147 /* Vector: 147, UART2 Transfer Done */ +#define PIC32MZ_IRQ_I2C2COL 148 /* Vector: 148, I2C2 Bus Collision Event */ +#define PIC32MZ_IRQ_I2C2S 149 /* Vector: 149, I2C2 Slave Event */ + +#define PIC32MZ_IRQ_I2C2M 150 /* Vector: 150, I2C2 Master Event */ +#define PIC32MZ_IRQ_CAN1 151 /* Vector: 151, Control Area Network 1 */ +#define PIC32MZ_IRQ_CAN2 152 /* Vector: 152, Control Area Network 2 */ +#define PIC32MZ_IRQ_ETH 153 /* Vector: 153, Ethernet interrupt */ +#define PIC32MZ_IRQ_SPI3F 154 /* Vector: 154, SPI3 Fault */ +#define PIC32MZ_IRQ_SPI3RX 155 /* Vector: 155, SPI3 Receive Done */ +#define PIC32MZ_IRQ_SPI3TX 156 /* Vector: 156, SPI3 Transfer Done */ +#define PIC32MZ_IRQ_U3E 157 /* Vector: 157, UART3 Fault */ +#define PIC32MZ_IRQ_U3RX 158 /* Vector: 158, UART3 Receive Done */ +#define PIC32MZ_IRQ_U3TX 159 /* Vector: 159, UART3 Transfer Done */ + +#define PIC32MZ_IRQ_I2C3COL 160 /* Vector: 160, I2C3 Bus Collision Event */ +#define PIC32MZ_IRQ_I2C3S 161 /* Vector: 161, I2C3 Slave Event */ +#define PIC32MZ_IRQ_I2C3M 162 /* Vector: 162, I2C3 Master Event */ +#define PIC32MZ_IRQ_SPI4F 163 /* Vector: 163, SPI4 Fault */ +#define PIC32MZ_IRQ_SPI4RX 164 /* Vector: 164, SPI4 Receive Done */ +#define PIC32MZ_IRQ_SPI4TX 165 /* Vector: 165, SPI4 Transfer Done */ +#define PIC32MZ_IRQ_RTCC 166 /* Vector: 166, Real-Time Clock and Calendar */ +#define PIC32MZ_IRQ_FCE 167 /* Vector: 167, Flash Control Event */ +#define PIC32MZ_IRQ_PMSEC 168 /* Vector: 168, Prefetch Module SEC Event */ +#define PIC32MZ_IRQ_SQI1 169 /* Vector: 169, SQI1 Event */ + +#define PIC32MZ_IRQ_U4E 170 /* Vector: 170, UART4 Fault */ +#define PIC32MZ_IRQ_U4RX 171 /* Vector: 171, UART4 Receive Done */ +#define PIC32MZ_IRQ_U4TX 172 /* Vector: 172, UART4 Transfer Done */ +#define PIC32MZ_IRQ_I2C4COL 173 /* Vector: 173, I2C4 Bus Collision Event */ +#define PIC32MZ_IRQ_I2C4S 174 /* Vector: 174, I2C4 Slave Event */ +#define PIC32MZ_IRQ_I2C4M 175 /* Vector: 175, I2C4 Master Event */ +#define PIC32MZ_IRQ_SPI5F 176 /* Vector: 176, SPI5 Fault */ +#define PIC32MZ_IRQ_SPI5RX 177 /* Vector: 177, SPI5 Receive Done */ +#define PIC32MZ_IRQ_SPI5TX 178 /* Vector: 178, SPI5 Transfer Done */ +#define PIC32MZ_IRQ_U5E 179 /* Vector: 179, UART5 Fault */ + +#define PIC32MZ_IRQ_U5RX 180 /* Vector: 180, UART5 Receive Done */ +#define PIC32MZ_IRQ_U5TX 181 /* Vector: 181, UART5 Transfer Done */ +#define PIC32MZ_IRQ_I2C5COL 182 /* Vector: 182, I2C5 Bus Collision Event */ +#define PIC32MZ_IRQ_I2C5S 183 /* Vector: 183, I2C5 Slave Event */ +#define PIC32MZ_IRQ_I2C5M 184 /* Vector: 184, I2C5 Master Event */ +#define PIC32MZ_IRQ_SPI6F 185 /* Vector: 185, SPI6 Fault */ +#define PIC32MZ_IRQ_SPI6RX 186 /* Vector: 186, SPI6 Receive Done */ +#define PIC32MZ_IRQ_SPI6TX 187 /* Vector: 187, SPI6 Transfer Done */ +#define PIC32MZ_IRQ_U6E 188 /* Vector: 188, UART6 Fault */ +#define PIC32MZ_IRQ_U6RX 189 /* Vector: 189, UART6 Receive Done */ + +#define PIC32MZ_IRQ_U6TX 190 /* Vector: 190, UART6 Transfer Done */ + /* Vector: 191, Reserved */ +#define PIC32MZ_IRQ_ADCESR 192 /* Vector: ADC End of Scan Ready */ +#define PIC32MZ_IRQ_ADCACR 193 /* Vector: ADC Analog Circuits Ready */ +#define PIC32MZ_IRQ_ADCUR 194 /* Vector: ADC Update Ready */ + /* Vector: 195, Reserved */ +#define PIC32MZ_IRQ_ADCGEIR 196 /* Vector: ADC Group Early Interrupt Request */ + /* Vector: 197, Reserved */ +#define PIC32MZ_IRQ_ADC0ER 198 /* Vector: ADC0 Early Interrupt */ +#define PIC32MZ_IRQ_ADC1ER 199 /* Vector: ADC1 Early Interrupt */ +#define PIC32MZ_IRQ_ADC2ER 200 /* Vector: ADC2 Early Interrupt */ +#define PIC32MZ_IRQ_ADC3ER 201 /* Vector: ADC3 Early Interrupt */ +#define PIC32MZ_IRQ_ADC4ER 202 /* Vector: ADC4 Early Interrupt */ + /* Vector: 203, Reserved */ + /* Vector: 204, Reserved */ +#define PIC32MZ_IRQ_ADC7ER 205 /* Vector: ADC7 Early Interrupt */ +#define PIC32MZ_IRQ_ADC0WI 206 /* Vector: ADC0 Warm Interrupt */ +#define PIC32MZ_IRQ_ADC1WI 207 /* Vector: ADC1 Warm Interrupt */ +#define PIC32MZ_IRQ_ADC2WI 208 /* Vector: ADC2 Warm Interrupt */ +#define PIC32MZ_IRQ_ADC3WI 209 /* Vector: ADC3 Warm Interrupt */ +#define PIC32MZ_IRQ_ADC4WI 210 /* Vector: ADC4 Warm Interrupt */ + /* Vector: 211, Reserved */ + /* Vector: 212, Reserved */ +#define PIC32MZ_IRQ_ADC7WI 213 /* Vector: ADC7 Warm Interrupt */ + +#define PIC32MZ_IRQ_BAD 214 /* Not a real IRQ number */ +#define NR_IRQS 214 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_INCLUDE_PIC32MZ_IRQ_PIC32MZXXXEF_H */ + diff --git a/arch/mips/src/pic32mz/Kconfig b/arch/mips/src/pic32mz/Kconfig index 0ea6cfeae4d58c6ec1246dcf2226be90615355ca..47d17eaebb2a800622beb63de97259c0c775b2ba 100644 --- a/arch/mips/src/pic32mz/Kconfig +++ b/arch/mips/src/pic32mz/Kconfig @@ -14,13 +14,32 @@ config ARCH_CHIP_PIC32MZ2048ECH bool "PIC32MZ2048ECH" select ARCH_CHIP_PIC32MZEC ---help--- - Microchip PIC32MZ2048ECH (MIPS32 M14K) + Microchip PIC32MZ2048ECH (MIPS32 M14K) such as the + PIC32MZ2048ECH144-I/PH used with the PIC32MZ EC STARTER KIT + DM320006 (no longer available) config ARCH_CHIP_PIC32MZ2048ECM bool "PIC32MZ2048ECM" select ARCH_CHIP_PIC32MZEC ---help--- - Microchip PIC32MZ2048ECM with Crypto Engine (MIPS32 M14K) + Microchip PIC32MZ2048ECM with Crypto Engine (MIPS32 M14K) such as + the ARCH_CHIP_PIC32MZ2048ECM144-I/PH used with the PIC32MZ EC + STARTER KIT DM320006-C (no longer available) + +config ARCH_CHIP_PIC32MZ2048EFH + bool "PIC32MZ2048EFH" + select ARCH_CHIP_PIC32MZEF + ---help--- + Microchip PIC32MZ2048EFH (MIPS32 M14K) such as the + PIC32MZ2048EFH144-I/PH used in the PIC32MZ EF STARTER KIT or as the + PIC32MZ2048EFH100 used with the Mikroe Flip&Click for PIC32MZ. + +config ARCH_CHIP_PIC32MZ2048EFM + bool "PIC32MZ2048EFM" + select ARCH_CHIP_PIC32MZEF + ---help--- + Microchip PIC32MZ2048EFH with Crypto Engine (MIPS32 M14K) such as + the PIC32MZ2048EFM144-I/PH used in the PIC32MZ EF STARTER KIT endchoice @@ -29,6 +48,11 @@ config ARCH_CHIP_PIC32MZEC default n select ARCH_MIPS_M14K +config ARCH_CHIP_PIC32MZEF + bool + default n + select ARCH_MIPS_M14K + config PIC32MZ_MVEC bool default n diff --git a/arch/mips/src/pic32mz/chip/pic32mz-features.h b/arch/mips/src/pic32mz/chip/pic32mz-features.h index 4bc21f258338662764f33663891f76abb083f3a9..6e80282a395bf5a6cb17c40c65a11727e55a87ca 100644 --- a/arch/mips/src/pic32mz/chip/pic32mz-features.h +++ b/arch/mips/src/pic32mz/chip/pic32mz-features.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/mips/src/pic32mz/chip/pic32mz-features.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -44,6 +44,8 @@ #if defined(CONFIG_ARCH_CHIP_PIC32MZEC) # include +#elif defined(CONFIG_ARCH_CHIP_PIC32MZEF) +# include #else # error Unknown PIC32MZ family #endif diff --git a/arch/mips/src/pic32mz/chip/pic32mz-memorymap.h b/arch/mips/src/pic32mz/chip/pic32mz-memorymap.h index a03adba1a86b31d89016aa7eb9953e420ff10d28..cb50d3443471d6d876d873d6a0320d3e81bd441e 100644 --- a/arch/mips/src/pic32mz/chip/pic32mz-memorymap.h +++ b/arch/mips/src/pic32mz/chip/pic32mz-memorymap.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/mips/src/pic32mz/chip/pic32mz-memorymap.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -44,6 +44,8 @@ #if defined(CONFIG_ARCH_CHIP_PIC32MZEC) # include "chip/pic32mzec-memorymap.h" +#elif defined(CONFIG_ARCH_CHIP_PIC32MZEF) +# include "chip/pic32mzef-memorymap.h" #else # error Unknown PIC32MZ family #endif diff --git a/arch/mips/src/pic32mz/chip/pic32mz-pps.h b/arch/mips/src/pic32mz/chip/pic32mz-pps.h index c0fbd48fa58a7e321b0e6b10d42d7e8090cf2757..c59ebab6df18215b7b33883742aa82ef03fd49e4 100644 --- a/arch/mips/src/pic32mz/chip/pic32mz-pps.h +++ b/arch/mips/src/pic32mz/chip/pic32mz-pps.h @@ -1,7 +1,7 @@ /******************************************************************************************** * arch/mips/src/pic32mz/pic32mz-pps.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -51,6 +51,8 @@ #if defined(CONFIG_ARCH_CHIP_PIC32MZEC) # include "chip/pic32mzec-pps.h" +#elif defined(CONFIG_ARCH_CHIP_PIC32MZEF) +# include "chip/pic32mzef-pps.h" #else # error Unknown PIC32MZ family #endif diff --git a/arch/mips/src/pic32mz/chip/pic32mzec-features.h b/arch/mips/src/pic32mz/chip/pic32mzec-features.h index 3a676f887ebcc111e172de02eb34bef7e1422ccb..270f58d1768ae64c828361f1f430a47c18fa7e24 100644 --- a/arch/mips/src/pic32mz/chip/pic32mzec-features.h +++ b/arch/mips/src/pic32mz/chip/pic32mzec-features.h @@ -432,10 +432,10 @@ # define DEVCFG1_FWDT_DISABLED (0 << 23) /* Bit 23=0: Watchdog disabled, can be enabled */ #define DEVCFG1_FWDTWINSZ_SHIFT (24) /* Bits 24-25: Watchdog Timer Window Size bits */ #define DEVCFG1_FWDTWINSZ_MASK (3 << DEVCFG1_FWDTWINSZ_SHIFT) -# define DEVCFG1_FWDTWINSZ_75 (0 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 75% */ -# define DEVCFG1_FWDTWINSZ_50 (1 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 50% */ -# define DEVCFG1_FWDTWINSZ_37p5 (2 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 37.5% */ -# define DEVCFG1_FWDTWINSZ_25 (3 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 25% */ +# define DEVCFG1_FWDTWINSZ_75 (0 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 75% */ +# define DEVCFG1_FWDTWINSZ_50 (1 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 50% */ +# define DEVCFG1_FWDTWINSZ_37p5 (2 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 37.5% */ +# define DEVCFG1_FWDTWINSZ_25 (3 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 25% */ #define DEVCFG1_DMTCNT_SHIFT (26) /* Bits 26-30: Deadman Timer Count Select bits */ #define DEVCFG1_DMTCNT_MASK (31 << DEVCFG1_DMTCNT_SHIFT) # define DEVCFG1_DMTCNT(n) ((uint32_t)((n)-8) << DEVCFG1_DMTCNT_SHIFT) /* 2**n, n=8..31 */ diff --git a/arch/mips/src/pic32mz/chip/pic32mzec-memorymap.h b/arch/mips/src/pic32mz/chip/pic32mzec-memorymap.h index dc878ea96dadd994181b75ebb8e358bbc8795aee..54d95e49ba73da9777fc9529379183b91347660b 100644 --- a/arch/mips/src/pic32mz/chip/pic32mzec-memorymap.h +++ b/arch/mips/src/pic32mz/chip/pic32mzec-memorymap.h @@ -117,26 +117,33 @@ #define PIC32MZ_CVREF_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000e00) /* CVREF */ #define PIC32MZ_OSC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00001200) /* Oscillator */ #define PIC32MZ_PPS_K1BASE (PIC32MZ_SFR_K1BASE + 0x00001400) /* PPS */ + #define PIC32MZ_INT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00010000) /* Interrupt Controller */ #define PIC32MZ_DMA_K1BASE (PIC32MZ_SFR_K1BASE + 0x00011000) /* DMA */ + #define PIC32MZ_I2C_K1BASE (PIC32MZ_SFR_K1BASE + 0x00020000) /* I2C1-I2C5 */ #define PIC32MZ_SPI_K1BASE (PIC32MZ_SFR_K1BASE + 0x00021000) /* SPI1-SPI6 */ #define PIC32MZ_UART_K1BASE (PIC32MZ_SFR_K1BASE + 0x00022000) /* UART1-UART6 */ #define PIC32MZ_PMP_K1BASE (PIC32MZ_SFR_K1BASE + 0x0002e000) /* PMP */ + #define PIC32MZ_TIMER_K1BASE (PIC32MZ_SFR_K1BASE + 0x00040000) /* Timer1-Timer9 */ #define PIC32MZ_IC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00042000) /* IC1-IC9 */ #define PIC32MZ_OC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00044000) /* OC1-OC9 */ #define PIC32MZ_ADC1_K1BASE (PIC32MZ_SFR_K1BASE + 0x0004b000) /* ADC1 */ #define PIC32MZ_CMP_K1BASE (PIC32MZ_SFR_K1BASE + 0x0004c000) /* Comparator 1, 2 */ + #define PIC32MZ_IOPORT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00060000) /* PORTA-PORTK */ + #define PIC32MZ_CAN_K1BASE (PIC32MZ_SFR_K1BASE + 0x00080000) /* CAN1 and CAN2 */ #define PIC32MZ_ETH_K1BASE (PIC32MZ_SFR_K1BASE + 0x00082000) /* Ethernet */ + #define PIC32MZ_PREFETCH_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e0000) /* Prefetch */ #define PIC32MZ_EBI_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e1000) /* EBI */ #define PIC32MZ_SQI1_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e2000) /* SQI1 */ #define PIC32MZ_USB_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e3000) /* USB */ #define PIC32MZ_CRYPTO_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e5000) /* Crypto */ #define PIC32MZ_RNG_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e6000) /* RNG */ + #define PIC32MZ_SYSBUS_K1BASE (PIC32MZ_SFR_K1BASE + 0x000f0000) /* System Bus */ #endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_MEMORYMAP_H */ diff --git a/arch/mips/src/pic32mz/chip/pic32mzec-pps.h b/arch/mips/src/pic32mz/chip/pic32mzec-pps.h index 8ee9f4d7e740cbb0e79f49ed6e1f20a58358c3c7..c027d6a346ce6f9e25732771569f2cb1d45d5360 100644 --- a/arch/mips/src/pic32mz/chip/pic32mzec-pps.h +++ b/arch/mips/src/pic32mz/chip/pic32mzec-pps.h @@ -47,6 +47,8 @@ ********************************************************************************************/ /* PPS Register Offsets *********************************************************************/ +/* Peripheral pin select input register map */ + #define PIC32MZ_INTnR_OFFSET(n) (0x1400 + ((n << 2)) /* n=1..4 */ # define PIC32MZ_INT1R_OFFSET 0x1404 # define PIC32MZ_INT2R_OFFSET 0x1408 @@ -93,7 +95,7 @@ # define PIC32MZ_SDI4R_OFFSET 0x14c0 # define PIC32MZ_SDI5R_OFFSET 0x14cc # define PIC32MZ_SDI6R_OFFSET 0x14d8 -#define PIC32MZ_SSnR_OFFSET(n) (0x1490 + 12*(n)) /* n=1..6 */ +#define PIC32MZ_SSnR_OFFSET(n) (0x1494 + 12*(n)) /* n=1..6 */ # define PIC32MZ_SS1R_OFFSET 0x14a0 # define PIC32MZ_SS2R_OFFSET 0x14ac # define PIC32MZ_SS3R_OFFSET 0x14b8 @@ -107,6 +109,9 @@ # define PIC32MZ_REFCLKI1R_OFFSET 0x14e8 # define PIC32MZ_REFCLKI3R_OFFSET 0x14f0 # define PIC32MZ_REFCLKI4R_OFFSET 0x14f4 + +/* Peripheral pin select output register map */ + #define PIC32MZ_RPAnR_OFFSET(n) (0x1500 + ((n) << 2)) /* n=14,15 */ # define PIC32MZ_RPA14R_OFFSET 0x1538 # define PIC32MZ_RPA15R_OFFSET 0x153c @@ -236,6 +241,9 @@ # define PIC32MZ_REFCLKI1R (PIC32MZ_SFR_K1BASE+PIC32MZ_REFCLKI1R_OFFSET) # define PIC32MZ_REFCLKI3R (PIC32MZ_SFR_K1BASE+PIC32MZ_REFCLKI3R_OFFSET) # define PIC32MZ_REFCLKI4R (PIC32MZ_SFR_K1BASE+PIC32MZ_REFCLKI4R_OFFSET) + +/* Peripheral pin select output register map */ + #define PIC32MZ_RPAnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_RPAnR_OFFSET(n)) # define PIC32MZ_RPA14R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPA14R_OFFSET) # define PIC32MZ_RPA15R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPA15R_OFFSET) @@ -764,8 +772,8 @@ #define T2CKR_RPF1 4 #define T2CKR_RPF4 2 #define T2CKR_RPG1 12 - #define T2CKR_RPG8 1 + #define T3CKR_RPB0 5 #define T3CKR_RPB7 7 #define T3CKR_RPB8 2 diff --git a/arch/mips/src/pic32mz/chip/pic32mzef-features.h b/arch/mips/src/pic32mz/chip/pic32mzef-features.h new file mode 100644 index 0000000000000000000000000000000000000000..9a042287bf0b4648e52ab8ba37d7e24fbaf7d54e --- /dev/null +++ b/arch/mips/src/pic32mz/chip/pic32mzef-features.h @@ -0,0 +1,540 @@ +/************************************************************************************ + * arch/mips/src/pic32mz/chip/pic32mzef-features.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_FEATURES_H +#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_FEATURES_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Register/Flash Offsets ***********************************************************/ + +/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */ + +#define PIC32MZ_CFGCON_OFFSET 0x0000 /* Configuration control register */ +#define PIC32MZ_DEVID_OFFSET 0x0020 /* Device ID and revision register */ +#define PIC32MZ_SYSKEY_OFFSET 0x0030 /* System key register */ +#define PIC32MZ_CFGEBIA_OFFSET 0x00c0 /* External bus interface address pin configuration register */ +#define PIC32MZ_CFGEBIC_OFFSET 0x00d0 /* External bus interface address pin control register */ +#define PIC32MZ_CFGPG_OFFSET 0x00e0 /* Permission group configuration register */ + +/* Alternate Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */ + +#define PIC32MZ_ADEVCFG3_OFFSET 0x0040 /* Alternate device configuration word 3 */ +#define PIC32MZ_ADEVCFG2_OFFSET 0x0044 /* Alternate device configuration word 2 */ +#define PIC32MZ_ADEVCFG1_OFFSET 0x0048 /* Alternate device configuration word 1 */ +#define PIC32MZ_ADEVCFG0_OFFSET 0x004c /* Alternate device configuration word 0 */ +#define PIC32MZ_ADEVCP3_OFFSET 0x0050 /* Alternate device code protect word 3 */ +#define PIC32MZ_ADEVCP2_OFFSET 0x0054 /* Alternate device code protect word 2 */ +#define PIC32MZ_ADEVCP1_OFFSET 0x0058 /* Alternate device code protect word 1 */ +#define PIC32MZ_ADEVCP0_OFFSET 0x005c /* Alternate device code protect word 0 */ +#define PIC32MZ_ADEVSIGN3_OFFSET 0x0060 /* Alternate device signature word 3 */ +#define PIC32MZ_ADEVSIGN2_OFFSET 0x0064 /* Alternate device signature word 2 */ +#define PIC32MZ_ADEVSIGN1_OFFSET 0x0068 /* Alternate device signature word 1 */ +#define PIC32MZ_ADEVSIGN0_OFFSET 0x006c /* Alternate device signature word 0 */ + +/* Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */ + +#define PIC32MZ_DEVCFG3_OFFSET 0x00c0 /* Device configuration word 3 */ +#define PIC32MZ_DEVCFG2_OFFSET 0x00c4 /* Device configuration word 2 */ +#define PIC32MZ_DEVCFG1_OFFSET 0x00c8 /* Device configuration word 1 */ +#define PIC32MZ_DEVCFG0_OFFSET 0x00cc /* Device configuration word 0 */ +#define PIC32MZ_DEVCP3_OFFSET 0x00d0 /* Device code protect word 3 */ +#define PIC32MZ_DEVCP2_OFFSET 0x00d4 /* Device code protect word 2 */ +#define PIC32MZ_DEVCP1_OFFSET 0x00d8 /* Device code protect word 1 */ +#define PIC32MZ_DEVCP0_OFFSET 0x00dc /* Device code protect word 0 */ +#define PIC32MZ_DEVSIGN3_OFFSET 0x00e0 /* Device signature word 3 */ +#define PIC32MZ_DEVSIGN2_OFFSET 0x00e4 /* Device signature word 2 */ +#define PIC32MZ_DEVSIGN1_OFFSET 0x00e8 /* Device signature word 1 */ +#define PIC32MZ_DEVSIGN0_OFFSET 0x00ec /* Device signature word 0 */ + +/* Device ADC Calibration (Boot Flash PIC32MZ_DEVSN_K1BASE) */ + +#define PIC32MZ_DEVADC0_OFFSET 0x0000 /* ADC0 Calibration */ +#define PIC32MZ_DEVADC1_OFFSET 0x0004 /* ADC1 Calibration */ +#define PIC32MZ_DEVADC2_OFFSET 0x0008 /* ADC2 Calibration */ +#define PIC32MZ_DEVADC3_OFFSET 0x000c /* ADC3 Calibration */ +#define PIC32MZ_DEVADC4_OFFSET 0x0010 /* ADC4 Calibration */ +#define PIC32MZ_DEVADC7_OFFSET 0x001c /* ADC7 Calibration */ + +/* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASE) */ + +#define PIC32MZ_DEVSN0_OFFSET 0x0020 /* Device serial number 0 */ +#define PIC32MZ_DEVSN1_OFFSET 0x0024 /* Device serial number 1 */ + +/* Register/Flash Addresses *********************************************************/ + +/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */ + +#define PIC32MZ_CFGCON (PIC32MZ_CONFIG_K1BASE+PIC32MZ_CFGCON_OFFSET) +#define PIC32MZ_DEVID (PIC32MZ_CONFIG_K1BASE+PIC32MZ_DEVID_OFFSET) +#define PIC32MZ_SYSKEY (PIC32MZ_CONFIG_K1BASE+PIC32MZ_SYSKEY_OFFSET) +#define PIC32MZ_CFGEBIA (PIC32MZ_CONFIG_K1BASE+PIC32MZ_CFGEBIA_OFFSET) +#define PIC32MZ_CFGEBIC (PIC32MZ_CONFIG_K1BASE+PIC32MZ_CFGEBIC_OFFSET) +#define PIC32MZ_CFGPG (PIC32MZ_CONFIG_K1BASE+PIC32MZ_CFGPG_OFFSET) + +/* Alternate Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */ + +#define PIC32MZ_ADEVCFG3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCFG3_OFFSET) +#define PIC32MZ_ADEVCFG2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCFG2_OFFSET) +#define PIC32MZ_ADEVCFG1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCFG1_OFFSET) +#define PIC32MZ_ADEVCFG0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCFG0_OFFSET) +#define PIC32MZ_ADEVCP3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCP3_OFFSET) +#define PIC32MZ_ADEVCP2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCP2_OFFSET) +#define PIC32MZ_ADEVCP1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCP1_OFFSET) +#define PIC32MZ_ADEVCP0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVCP0_OFFSET) +#define PIC32MZ_ADEVSIGN3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVSIGN3_OFFSET) +#define PIC32MZ_ADEVSIGN2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVSIGN2_OFFSET) +#define PIC32MZ_ADEVSIGN1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVSIGN1_OFFSET) +#define PIC32MZ_ADEVSIGN0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_ADEVSIGN0_OFFSET) + +/* Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */ + +#define PIC32MZ_DEVCFG3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCFG3_OFFSET) +#define PIC32MZ_DEVCFG2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCFG2_OFFSET) +#define PIC32MZ_DEVCFG1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCFG1_OFFSET) +#define PIC32MZ_DEVCFG0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCFG0_OFFSET) +#define PIC32MZ_DEVCP3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCP3_OFFSET) +#define PIC32MZ_DEVCP2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCP2_OFFSET) +#define PIC32MZ_DEVCP1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCP1_OFFSET) +#define PIC32MZ_DEVCP0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVCP0_OFFSET) +#define PIC32MZ_DEVSIGN3 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVSIGN3_OFFSET) +#define PIC32MZ_DEVSIGN2 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVSIGN2_OFFSET) +#define PIC32MZ_DEVSIGN1 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVSIGN1_OFFSET) +#define PIC32MZ_DEVSIGN0 (PIC32MZ_BOOTCFG_K1BASE+PIC32MZ_DEVSIGN0_OFFSET) + +/* Device ADC Calibration (Boot Flash PIC32MZ_DEVSN_K1BASE) */ + +#define PIC32MZ_DEVADC0 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVADC0_OFFSET) +#define PIC32MZ_DEVADC1 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVADC1_OFFSET) +#define PIC32MZ_DEVADC2 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVADC2_OFFSET) +#define PIC32MZ_DEVADC3 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVADC3_OFFSET) +#define PIC32MZ_DEVADC4 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVADC4_OFFSET) +#define PIC32MZ_DEVADC7 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVADC7_OFFSET) + +/* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASEPIC32MZ_DEVSN_K1BASE) */ + +#define PIC32MZ_DEVSN0 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVSN0_OFFSET) +#define PIC32MZ_DEVSN1 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVSN1_OFFSET) + +/* Register/Flash Bit Field Definitions *********************************************/ + +/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */ +/* Configuration control register + * + * NOTE: To change many of the bits in the register, the unlock sequence must first + * be performed. + */ + +#define CFGCON_TDOEN (1 << 0) /* Bit 0: TDO Enable for 2-Wire JTAG */ +#define CFGCON_TROEN (1 << 2) /* Bit 2: Trace Output Enable bit */ +#define CFGCON_JTAGEN (1 << 3) /* Bit 3: JTAG Port Enable bit */ +#define CFGCON_ECCCON_SHIFT (4) /* Bits 4-5: Flash ECC Configuration bits */ +#define CFGCON_ECCCON_MASK (7 << CFGCON_ECCCON_SHIFT) +# define CFGCON_ECCCON_ECC (0 << CFGCON_ECCCON_SHIFT) /* Flash ECC enabled */ +# define CFGCON_ECCCON_DYNECC (1 << CFGCON_ECCCON_SHIFT) /* Dynamic Flash ECC enabled */ +# define CFGCON_ECCCON_DISLCK (2 << CFGCON_ECCCON_SHIFT) /* ECC / dynamic ECC disabled (locked) */ +# define CFGCON_ECCCON_DISWR (3 << CFGCON_ECCCON_SHIFT) /* ECC / dynamic ECC disabled (writable) */ +#define CFGCON_IOANCPEN (1 << 7) /* Bit 7: I/O Analog Charge Pump Enable bit */ +#define CFGCON_USBSSEN (1 << 8) /* Bit 8: USB Suspend Sleep Enable bit */ +#define CFGCON_PGLOCK (1 << 11) /* Bit 11: Permission Group Lock bit */ +#define CFGCON_PMDLOCK (1 << 12) /* Bit 12: Peripheral Module Disable bit */ +#define CFGCON_IOLOCK (1 << 13) /* Bit 13: Peripheral Pin Select Lock bit */ +#define CFGCON_OCACLK (1 << 16) /* Bit 16: Output Compare Alternate Clock Selection bit */ +#define CFGCON_ICACLK (1 << 17) /* Bit 17: Input Capture Alternate Clock Selection bit */ +#define CFGCON_CPUPRI (1 << 24) /* Bit 24: CPU Arbitration Priority to SRAM */ +#define CFGCON_DMAPRI (1 << 25) /* Bit 25: DMA Read and DMA Write Arbitration Priority */ + +/* Device ID and revision register */ + +#define DEVID_SHIFT (0) /* Bits 0-27: Device ID */ +#define DEVID_MASK (0x0ffffff << DEVID_SHIFT) +#define DEVID_VER_SHIFT (28) /* Bits 28-31: Revision Identifier bits */ +#define DEVID_VER_MASK (15 << DEVID_VER_SHIFT) + +/* System key register: 32-bit key value */ + +#define UNLOCK_SYSKEY_0 (0xaa996655ul) +#define UNLOCK_SYSKEY_1 (0x556699aaul) + +/* External bus interface address pin configuration register */ + +#define CFGEBIA_EBIA0N_SHIFT (0) /* Bits 0-23: EBI address pin 0 enable */ +#define CFGEBIA_EBIA0N_MASK (0x00ffffff << CFGEBIA_EBIA0N_SHIFT) +# define CFGEBIA_EBIA0EN (1 << 0) /* Bit 0: EBI address pin 0 enable */ +# define CFGEBIA_EBIA1EN (1 << 1) /* Bit 1: EBI address pin 1 enable */ +# define CFGEBIA_EBIA2EN (1 << 2) /* Bit 2: EBI address pin 2 enable */ +# define CFGEBIA_EBIA3EN (1 << 3) /* Bit 3: EBI address pin 3 enable */ +# define CFGEBIA_EBIA4EN (1 << 4) /* Bit 4: EBI address pin 4 enable */ +# define CFGEBIA_EBIA5EN (1 << 5) /* Bit 5: EBI address pin 5 enable */ +# define CFGEBIA_EBIA6EN (1 << 6) /* Bit 6: EBI address pin 6 enable */ +# define CFGEBIA_EBIA7EN (1 << 7) /* Bit 7: EBI address pin 7 enable */ +# define CFGEBIA_EBIA8EN (1 << 8) /* Bit 8: EBI address pin 8 enable */ +# define CFGEBIA_EBIA9EN (1 << 9) /* Bit 9: EBI address pin 9 enable */ +# define CFGEBIA_EBIA10EN (1 << 10) /* Bit 10: EBI address pin 10 enable */ +# define CFGEBIA_EBIA11EN (1 << 11) /* Bit 11: EBI address pin 11 enable */ +# define CFGEBIA_EBIA12EN (1 << 12) /* Bit 12: EBI address pin 12 enable */ +# define CFGEBIA_EBIA13EN (1 << 13) /* Bit 13: EBI address pin 13 enable */ +# define CFGEBIA_EBIA14EN (1 << 14) /* Bit 14: EBI address pin 14 enable */ +# define CFGEBIA_EBIA15EN (1 << 15) /* Bit 15: EBI address pin 15 enable */ +# define CFGEBIA_EBIA16EN (1 << 16) /* Bit 16: EBI address pin 16 enable */ +# define CFGEBIA_EBIA17EN (1 << 17) /* Bit 17: EBI address pin 17 enable */ +# define CFGEBIA_EBIA18EN (1 << 18) /* Bit 18: EBI address pin 18 enable */ +# define CFGEBIA_EBIA19EN (1 << 19) /* Bit 19: EBI address pin 19 enable */ +# define CFGEBIA_EBIA20EN (1 << 20) /* Bit 20: EBI address pin 20 enable */ +# define CFGEBIA_EBIA21EN (1 << 21) /* Bit 21: EBI address pin 21 enable */ +# define CFGEBIA_EBIA22EN (1 << 22) /* Bit 22: EBI address pin 22 enable */ +# define CFGEBIA_EBIA23EN (1 << 23) /* Bit 23: EBI address pin 23 enable */ +#define CFGEBIA_EBIPINEN (1 << 31) /* Bit 31: EBI Pin Enable bit */ + +/* External bus interface address pin control register */ + +#define CFGEBIC_EBIDEN0 (1 << 0) /* Bit 0: EBI Data Lower Byte Pin Enable bit */ +#define CFGEBIC_EBIDEN1 (1 << 1) /* Bit 1: EBI Data Upper Byte Pin Enable bit */ +#define CFGEBIC_EBICSEN0 (1 << 4) /* Bit 4: EBICS0 Pin Enable bit */ +#define CFGEBIC_EBICSEN1 (1 << 5) /* Bit 5: EBICS1 Pin Enable bit */ +#define CFGEBIC_EBICSEN2 (1 << 6) /* Bit 6: EBICS2 Pin Enable bit */ +#define CFGEBIC_EBICSEN3 (1 << 7) /* Bit 7: EBICS3 Pin Enable bit */ +#define CFGEBIC_EBIBSEN0 (1 << 8) /* Bit 8: EBIBS0 Pin Enable bit */ +#define CFGEBIC_EBIBSEN1 (1 << 9) /* Bit 9: EBIBS1 Pin Enable bit */ +#define CFGEBIC_EBIOEEN (1 << 12) /* Bit 12: EBIOE Pin Enable bit */ +#define CFGEBIC_EBIWEEN (1 << 13) /* Bit 13: EBIWE Pin Enable bit */ +#define CFGEBIC_EBIRPEN (1 << 16) /* Bit 16: EBIRP Pin Sensitivity Control bit */ +#define CFGEBIC_EBIRDYLVL (1 << 17) /* Bit 17: EBIRDYx Pin Sensitivity Control bit */ +#define CFGEBIC_EBIRDYEN1 (1 << 25) /* Bit 25: EBIRDY1 Pin Enable bit */ +#define CFGEBIC_EBIRDYEN2 (1 << 26) /* Bit 26: EBIRDY2 Pin Enable bit */ +#define CFGEBIC_EBIRDYEN3 (1 << 27) /* Bit 27: EBIRDY3 Pin Enable bit */ +#define CFGEBIC_EBIRDYINV1 (1 << 29) /* Bit 29: EBIRDY1 Inversion Control bit */ +#define CFGEBIC_EBIRDYINV2 (1 << 30) /* Bit 30: EBIRDY2 Inversion Control bit */ +#define CFGEBIC_EBIRDYINV3 (1 << 31) /* Bit 31: EBIRDY3 Inversion Control bit */ + +/* Permission group configuration register */ + +#define CFGPG_GROUP0 0 /* Initiator is assigned to Permission Group 0 */ +#define CFGPG_GROUP1 1 /* Initiator is assigned to Permission Group 1 */ +#define CFGPG_GROUP2 2 /* Initiator is assigned to Permission Group 2 */ +#define CFGPG_GROUP3 3 /* Initiator is assigned to Permission Group 3 */ + +#define CFGPG_CPUPG_SHIFT (0) /* Bits 0-1: CPU Permission Group bits */ +#define CFGPG_CPUPG_MASK (3 << CFGPG_CPUPG_SHIFT) +# define CFGPG_CPUPG(n) ((uint32_t)(n) << CFGPG_CPUPG_SHIFT) +# define CFGPG_CPUPG_GROUP0 CFGPG_CPUPG(CFGPG_GROUP0) +# define CFGPG_CPUPG_GROUP1 CFGPG_CPUPG(CFGPG_GROUP1) +# define CFGPG_CPUPG_GROUP2 CFGPG_CPUPG(CFGPG_GROUP2) +# define CFGPG_CPUPG_GROUP3 CFGPG_CPUPG(CFGPG_GROUP3) +#define CFGPG_DMAPG_SHIFT (4) /* Bits 4-5: DMA Module Permission Group bits */ +#define CFGPG_DMAPG_MASK (3 << CFGPG_DMAPG_SHIFT) +# define CFGPG_DMAPG(n) ((uint32_t)(n) << CFGPG_DMAPG_SHIFT) +# define CFGPG_DMAPG_GROUP0 CFGPG_DMAPG(CFGPG_GROUP0) +# define CFGPG_DMAPG_GROUP1 CFGPG_DMAPG(CFGPG_GROUP1) +# define CFGPG_DMAPG_GROUP2 CFGPG_DMAPG(CFGPG_GROUP2) +# define CFGPG_DMAPG_GROUP3 CFGPG_DMAPG(CFGPG_GROUP3) +#define CFGPG_USBPG_SHIFT (8) /* Bits 8-9: USB Module Permission Group bits */ +#define CFGPG_USBPG_MASK (3 << CFGPG_USBPG_SHIFT) +# define CFGPG_USBPG(n) ((uint32_t)(n) << CFGPG_USBPG_SHIFT) +# define CFGPG_USBPG_GROUP0 CFGPG_USBPG(CFGPG_GROUP0) +# define CFGPG_USBPG_GROUP1 CFGPG_USBPG(CFGPG_GROUP1) +# define CFGPG_USBPG_GROUP2 CFGPG_USBPG(CFGPG_GROUP2) +# define CFGPG_USBPG_GROUP3 CFGPG_USBPG(CFGPG_GROUP3) +#define CFGPG_CAN1PG_SHIFT (12) /* Bits 12-13: CAN1 Module Permission Group bits */ +#define CFGPG_CAN1PG_MASK (3 << CFGPG_CAN1PG_SHIFT) +# define CFGPG_CAN1PG(n) ((uint32_t)(n) << CFGPG_CAN1PG_SHIFT) +# define CFGPG_CAN1PG_GROUP0 CFGPG_CAN1PG(CFGPG_GROUP0) +# define CFGPG_CAN1PG_GROUP1 CFGPG_CAN1PG(CFGPG_GROUP1) +# define CFGPG_CAN1PG_GROUP2 CFGPG_CAN1PG(CFGPG_GROUP2) +# define CFGPG_CAN1PG_GROUP3 CFGPG_CAN1PG(CFGPG_GROUP3) +#define CFGPG_CAN2PG_SHIFT (14) /* Bits 14-15: CAN2 Module Permission Group bits */ +#define CFGPG_CAN2PG_MASK (3 << CFGPG_CAN2PG_SHIFT) +# define CFGPG_CAN2PG(n) ((uint32_t)(n) << CFGPG_CAN2PG_SHIFT) +# define CFGPG_CAN2PG_GROUP0 CFGPG_CAN2PG(CFGPG_GROUP0) +# define CFGPG_CAN2PG_GROUP1 CFGPG_CAN2PG(CFGPG_GROUP1) +# define CFGPG_CAN2PG_GROUP2 CFGPG_CAN2PG(CFGPG_GROUP2) +# define CFGPG_CAN2PG_GROUP3 CFGPG_CAN2PG(CFGPG_GROUP3) +#define CFGPG_ETHPG_SHIFT (16) /* Bits 16-17: Ethernet Module Permission Group bits */ +#define CFGPG_ETHPG_MASK (3 << CFGPG_ETHPG_SHIFT) +# define CFGPG_ETHPG(n) ((uint32_t)(n) << CFGPG_ETHPG_SHIFT) +# define CFGPG_ETHPG_GROUP0 CFGPG_ETHPG(CFGPG_GROUP0) +# define CFGPG_ETHPG_GROUP1 CFGPG_ETHPG(CFGPG_GROUP1) +# define CFGPG_ETHPG_GROUP2 CFGPG_ETHPG(CFGPG_GROUP2) +# define CFGPG_ETHPG_GROUP3 CFGPG_ETHPG(CFGPG_GROUP3) +#define CFGPG_SQI1PG_SHIFT (20) /* Bits 20-21: SQI Module Permission Group bits */ +#define CFGPG_SQI1PG_MASK (3 << CFGPG_SQI1PG_SHIFT) +# define CFGPG_SQI1PG(n) ((uint32_t)(n) << CFGPG_SQI1PG_SHIFT) +# define CFGPG_SQI1PG_GROUP0 CFGPG_SQI1PG(CFGPG_GROUP0) +# define CFGPG_SQI1PG_GROUP1 CFGPG_SQI1PG(CFGPG_GROUP1) +# define CFGPG_SQI1PG_GROUP2 CFGPG_SQI1PG(CFGPG_GROUP2) +# define CFGPG_SQI1PG_GROUP3 CFGPG_SQI1PG(CFGPG_GROUP3) +#define CFGPG_FCPG_SHIFT (22) /* Bits 22-23: Flash Control Permission Group bits */ +#define CFGPG_FCPG_MASK (3 << CFGPG_FCPG_SHIFT) +# define CFGPG_FCPG(n) ((uint32_t)(n) << CFGPG_FCPG_SHIFT) +# define CFGPG_FCPG_GROUP0 CFGPG_FCPG(CFGPG_GROUP0) +# define CFGPG_FCPG_GROUP1 CFGPG_FCPG(CFGPG_GROUP1) +# define CFGPG_FCPG_GROUP2 CFGPG_FCPG(CFGPG_GROUP2) +# define CFGPG_FCPG_GROUP3 CFGPG_FCPG(CFGPG_GROUP3) +#define CFGPG_CRYPTPG_SHIFT (24) /* Bits 24-25: Crypto Engine Permission Group bits */ +#define CFGPG_CRYPTPG_MASK (3 << CFGPG_CRYPTPG_SHIFT) +# define CFGPG_CRYPTPG(n) ((uint32_t)(n) << CFGPG_CRYPTPG_SHIFT) +# define CFGPG_CRYPTPG_GROUP0 CFGPG_CRYPTPG(CFGPG_GROUP0) +# define CFGPG_CRYPTPG_GROUP1 CFGPG_CRYPTPG(CFGPG_GROUP1) +# define CFGPG_CRYPTPG_GROUP2 CFGPG_CRYPTPG(CFGPG_GROUP2) +# define CFGPG_CRYPTPG_GROUP3 CFGPG_CRYPTPG(CFGPG_GROUP3) + +/* Alternate Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */ +/* Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */ +/* Device configuration word 3 / Alternate device configuration word 3 */ + +#define DEVCFG3_USERID_SHIFT (0) /* Bit 0-15: 16-bit user defined value */ +#define DEVCFG3_USERID_MASK (0xffff << DEVCFG3_USERID_SHIFT) +# define DEVCFG3_USERID(n) ((uint32_t)(n) << DEVCFG3_USERID_SHIFT) +#define DEVCFG3_FMIIEN_SHIFT (24) /* Bit 24: Ethernet MII Enable Configuration bit */ +#define DEVCFG3_FMIIEN (1 << 24) /* Bit 24: Ethernet MII Enable Configuration bit */ +#define DEVCFG3_FETHIO_SHIFT (25) /* Bit 25: Ethernet I/O Pin Selection Configuration bit */ +#define DEVCFG3_FETHIO (1 << 25) /* Bit 25: Ethernet I/O Pin Selection Configuration bit */ +#define DEVCFG3_PGL1WAY_SHIFT (27) /* Bit 27: Permission Group Lock One Way Configuration bit */ +#define DEVCFG3_PGL1WAY (1 << 27) /* Bit 27: Permission Group Lock One Way Configuration bit */ +#define DEVCFG3_PMDL1WAY_SHIFT (28) /* Bit 28: Peripheral Module Disable Configuration bit */ +#define DEVCFG3_PMDL1WAY (1 << 28) /* Bit 28: Peripheral Module Disable Configuration bit */ +#define DEVCFG3_IOL1WAY_SHIFT (29) /* Bit 29: Peripheral Pin Select Configuration bit */ +#define DEVCFG3_IOL1WAY (1 << 29) /* Bit 29: Peripheral Pin Select Configuration bit */ +#define DEVCFG3_FUSBIDIO_SHIFT (30) /* Bit 30: USB USBID Selection bit */ +#define DEVCFG3_FUSBIDIO (1 << 30) /* Bit 30: USB USBID Selection bit */ + +#define DEVCFG3_RWO 0x84ff0000 /* Bits 16-23, 31: Reserved, write as one */ + +/* Device configuration word 2 / Alternate device configuration word 2 */ + +#define DEVCFG2_FPLLIDIV_SHIFT (0) /* Bits 0-2: PLL Input Divider bits */ +#define DEVCFG2_FPLLIDIV_MASK (7 << DEVCFG2_FPLLIDIV_SHIFT) +# define DEVCFG2_FPLLIDIV(n) ((uint32_t)((n)-1) << DEVCFG2_FPLLIDIV_SHIFT) /* n=1..8 */ +# define DEVCFG2_FPLLIDIV_1 (0 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 1 */ +# define DEVCFG2_FPLLIDIV_2 (1 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 2 */ +# define DEVCFG2_FPLLIDIV_3 (2 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 3 */ +# define DEVCFG2_FPLLIDIV_4 (3 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 4 */ +# define DEVCFG2_FPLLIDIV_5 (4 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 5 */ +# define DEVCFG2_FPLLIDIV_6 (5 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 6 */ +# define DEVCFG2_FPLLIDIV_7 (6 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 7 */ +# define DEVCFG2_FPLLIDIV_8 (7 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 8 */ +#define DEVCFG2_FPLLRNG_SHIFT (4) /* Bits 4-6: System PLL Divided Input Clock Frequency Range bits */ +#define DEVCFG2_FPLLRNG_MASK (7 << DEVCFG2_FPLLRNG_SHIFT) +# define DEVCFG2_FPLLRNG_BYPASS (0 << DEVCFG2_FPLLRNG_SHIFT) /* Bypass */ +# define DEVCFG2_FPLLRNG_5_10MHZ (1 << DEVCFG2_FPLLRNG_SHIFT) /* 5-10 MHz */ +# define DEVCFG2_FPLLRNG_8_16MHZ (2 << DEVCFG2_FPLLRNG_SHIFT) /* 8-16 MHz */ +# define DEVCFG2_FPLLRNG_13_26MHZ (3 << DEVCFG2_FPLLRNG_SHIFT) /* 13-26 MHz */ +# define DEVCFG2_FPLLRNG_21_42MHZ (4 << DEVCFG2_FPLLRNG_SHIFT) /* 21-42 MHz */ +# define DEVCFG2_FPLLRNG_34_64MHZ (5 << DEVCFG2_FPLLRNG_SHIFT) /* 34-64 MHz */ +#define DEVCFG2_FPLLICLK (1 << 7) /* Bit 7: System PLL Input Clock Select bit */ +#define DEVCFG2_FPLLMULT_SHIFT (8) /* Bits 8-14: System PLL Feedback Divider bits */ +#define DEVCFG2_FPLLMULT_MASK (0x7f << DEVCFG2_FPLLMULT_SHIFT) +# define DEVCFG2_FPLLMULT(n) ((uint32_t)((n)-1) << DEVCFG2_FPLLMULT_SHIFT) /* n=1..128 */ +#define DEVCFG2_FPLLODIV_SHIFT (16) /* Bits 16-18: Default System PLL Output Divisor bits */ +#define DEVCFG2_FPLLODIV_MASK (7 << DEVCFG2_FPLLODIV_SHIFT) +# define DEVCFG2_FPLLODIV_2 (1 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 2 */ +# define DEVCFG2_FPLLODIV_4 (2 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 4 */ +# define DEVCFG2_FPLLODIV_8 (3 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 8 */ +# define DEVCFG2_FPLLODIV_16 (4 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 16 */ +# define DEVCFG2_FPLLODIV_32 (5 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 32 */ +#define DEVCFG2_UPLLFSEL (1 << 30) /* Bit 30: USB PLL Input Frequency Select bit */ +# define DEVCFG2_UPLLFSEL_24MHZ (1 << 30) /* Bit 30=1: UPLL input clock is 24 MHz */ +# define DEVCFG2_UPLLFSEL_12MHZ (0 << 30) /* Bit 30=0: UPLL input clock is 12 MHz */ + +#define DEVCFG2_RWO 0xbff88008 /* Bits 3, 15, 19-29, 31: Reserved, write as one */ + +/* Device configuration word 1 / Alternate device configuration word 1 */ + +#define DEVCFG1_FNOSC_SHIFT (0) /* Bits 0-2: Oscillator Selection bits */ +#define DEVCFG1_FNOSC_MASK (7 << DEVCFG1_FNOSC_SHIFT) +# define DEVCFG1_FNOSC_FRC (0 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV */ +# define DEVCFG1_FNOSC_SPLL (1 << DEVCFG1_FNOSC_SHIFT) /* SPLL */ +# define DEVCFG1_FNOSC_POSC (2 << DEVCFG1_FNOSC_SHIFT) /* POSC (HS, EC) */ +# define DEVCFG1_FNOSC_SOSC (4 << DEVCFG1_FNOSC_SHIFT) /* SOSC */ +# define DEVCFG1_FNOSC_LPRC (5 << DEVCFG1_FNOSC_SHIFT) /* LPRC */ +# define DEVCFG1_FNOSC_FRCDIV (7 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV<2:0> */ +#define DEVCFG1_DMTINV_SHIFT (3) /* Bits 3-5: Deadman Timer Count Window Interval bits */ +#define DEVCFG1_DMTINV_MASK (7 << DEVCFG1_DMTINV_SHIFT) +# define DEVCFG1_DMTINV_0 (0 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value zero */ +# define DEVCFG1_DMTINV_1_2 (1 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 1/2 counter */ +# define DEVCFG1_DMTINV_3_4 (2 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 3/4 counter */ +# define DEVCFG1_DMTINV_7_8 (3 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 7/8 counter */ +# define DEVCFG1_DMTINV_15_16 (4 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 15/16 counter */ +# define DEVCFG1_DMTINV_31_32 (5 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 31/32 counter */ +# define DEVCFG1_DMTINV_63_64 (6 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 63/64 counter */ +# define DEVCFG1_DMTINV_127_128 (7 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 127/128 counter */ +#define DEVCFG1_FSOSCEN (1 << 6) /* Bit 6: Secondary Oscillator Enable bit */ +#define DEVCFG1_IESO (1 << 7) /* Bit 7: Internal External Switchover bit */ +#define DEVCFG1_POSCMOD_SHIFT (8) /* Bits 8-9: Primary Oscillator Configuration bits */ +#define DEVCFG1_POSCMOD_MASK (3 << DEVCFG1_POSCMOD_SHIFT) +# define DEVCFG1_POSCMOD_EC (0 << DEVCFG1_POSCMOD_SHIFT) /* EC mode selected */ +# define DEVCFG1_POSCMOD_HS (2 << DEVCFG1_POSCMOD_SHIFT) /* HS Oscillator mode selected */ +# define DEVCFG1_POSCMOD_DIS (3 << DEVCFG1_POSCMOD_SHIFT) /* POSC disabled */ +#define DEVCFG1_OSCIOFNC (1 << 10) /* Bit 10: CLKO Enable Configuration bit */ +#define DEVCFG1_FCKSM_SHIFT (14) /* Bits 14-15: Clock Switching and Monitoring Selection */ +#define DEVCFG1_FCKSM_MASK (3 << DEVCFG1_FCKSM_SHIFT) +# define DEVCFG1_FCKSM_NONE (0 << DEVCFG1_FCKSM_SHIFT) /* Clock switching/monitoring disabled */ +# define DEVCFG1_FCKSM_SWITCH (1 << DEVCFG1_FCKSM_SHIFT) /* Clock switching enabled */ +# define DEVCFG1_FCKSM_MONITOR (2 << DEVCFG1_FCKSM_SHIFT) /* Clock monitoring enabled */ +# define DEVCFG1_FCKSM_BOTH (3 << DEVCFG1_FCKSM_SHIFT) /* Clock switching/monitoring enabled */ +#define DEVCFG1_WDTPS_SHIFT (16) /* Bits 16-20: Watchdog Timer Postscale Select bits */ +#define DEVCFG1_WDTPS_MASK (31 << DEVCFG1_WDTPS_SHIFT) +# define DEVCFG1_WDTPS_1 (0 << DEVCFG1_WDTPS_SHIFT) /* 1:1 */ +# define DEVCFG1_WDTPS_2 (1 << DEVCFG1_WDTPS_SHIFT) /* 1:2 */ +# define DEVCFG1_WDTPS_4 (2 << DEVCFG1_WDTPS_SHIFT) /* 1:4 */ +# define DEVCFG1_WDTPS_8 (3 << DEVCFG1_WDTPS_SHIFT) /* 1:8 */ +# define DEVCFG1_WDTPS_16 (4 << DEVCFG1_WDTPS_SHIFT) /* 1:16 */ +# define DEVCFG1_WDTPS_32 (5 << DEVCFG1_WDTPS_SHIFT) /* 1:32 */ +# define DEVCFG1_WDTPS_64 (6 << DEVCFG1_WDTPS_SHIFT) /* 1:64 */ +# define DEVCFG1_WDTPS_128 (7 << DEVCFG1_WDTPS_SHIFT) /* 1:128 */ +# define DEVCFG1_WDTPS_256 (8 << DEVCFG1_WDTPS_SHIFT) /* 1:256 */ +# define DEVCFG1_WDTPS_512 (9 << DEVCFG1_WDTPS_SHIFT) /* 1:512 */ +# define DEVCFG1_WDTPS_1024 (10 << DEVCFG1_WDTPS_SHIFT) /* 1:1024 */ +# define DEVCFG1_WDTPS_2048 (11 << DEVCFG1_WDTPS_SHIFT) /* 1:2048 */ +# define DEVCFG1_WDTPS_4096 (12 << DEVCFG1_WDTPS_SHIFT) /* 1:4096 */ +# define DEVCFG1_WDTPS_8192 (13 << DEVCFG1_WDTPS_SHIFT) /* 1:8192 */ +# define DEVCFG1_WDTPS_16384 (14 << DEVCFG1_WDTPS_SHIFT) /* 1:16384 */ +# define DEVCFG1_WDTPS_32768 (15 << DEVCFG1_WDTPS_SHIFT) /* 1:32768 */ +# define DEVCFG1_WDTPS_65536 (16 << DEVCFG1_WDTPS_SHIFT) /* 1:65536 */ +# define DEVCFG1_WDTPS_131072 (17 << DEVCFG1_WDTPS_SHIFT) /* 1:131072 */ +# define DEVCFG1_WDTPS_262144 (18 << DEVCFG1_WDTPS_SHIFT) /* 1:262144 */ +# define DEVCFG1_WDTPS_524288 (19 << DEVCFG1_WDTPS_SHIFT) /* 1:524288 */ +# define DEVCFG1_WDTPS_1048576 (20 << DEVCFG1_WDTPS_SHIFT) /* 1:1048576 */ +#define DEVCFG1_WDTSPGM (1 << 21) /* Bit 21: WDT stop/run during flash programming bit */ +# define DEVCFG1_WDTSPGM_STOP (1 << 21) /* Bit 21=1: WDT stops during flash programming */ +# define DEVCFG1_WDTSPGM_RUN (0 << 21) /* Bit 21=0: WDT runs during flash programming */ +#define DEVCFG1_WINDIS (1 << 22) /* Bit 22: Watchdog Timer Window Enable bit */ +# define DEVCFG1_WDT_NORMAL (1 << 22) /* Bit 22=1: Watchdog normal mode */ +# define DEVCFG1_WDT_WINDOW (0 << 22) /* Bit 22=0: Watchdog window mode */ +#define DEVCFG1_FWDTEN (1 << 23) /* Bit 23: Watchdog Timer Enable bit */ +# define DEVCFG1_FWDT_ENABLED (1 << 23) /* Bit 23=1: Watchdog enabled, cannot be disabled */ +# define DEVCFG1_FWDT_DISABLED (0 << 23) /* Bit 23=0: Watchdog disabled, can be enabled */ +#define DEVCFG1_FWDTWINSZ_SHIFT (24) /* Bits 24-25: Watchdog Timer Window Size bits */ +#define DEVCFG1_FWDTWINSZ_MASK (3 << DEVCFG1_FWDTWINSZ_SHIFT) +# define DEVCFG1_FWDTWINSZ_75 (0 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 75% */ +# define DEVCFG1_FWDTWINSZ_50 (1 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 50% */ +# define DEVCFG1_FWDTWINSZ_37p5 (2 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 37.5% */ +# define DEVCFG1_FWDTWINSZ_25 (3 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 25% */ +#define DEVCFG1_DMTCNT_SHIFT (26) /* Bits 26-30: Deadman Timer Count Select bits */ +#define DEVCFG1_DMTCNT_MASK (31 << DEVCFG1_DMTCNT_SHIFT) +# define DEVCFG1_DMTCNT(n) ((uint32_t)((n)-8) << DEVCFG1_DMTCNT_SHIFT) /* 2**n, n=8..31 */ +# define DEVCFG1_DMTCNT_MIN (0 << DEVCFG1_DMTCNT_SHIFT) /* 2**8 (256) */ +# define DEVCFG1_DMTCNT_MAX (23 << DEVCFG1_DMTCNT_SHIFT) /* 2**31 (2147483648) */ +#define DEVCFG1_FDMTEN (1 << 31) /* Bit 31: Deadman Timer enable bit */ + +#define DEVCFG1_RWO 0x00003800 /* Bits 11-13: Reserved, write as one */ + +/* Device configuration word 0 / Alternate device configuration word 0 */ + +#define DEVCFG0_DEBUG_SHIFT (0) /* Bits 0-1: Background Debugger Enable bits */ +#define DEVCFG0_DEBUG_MASK (3 << DEVCFG0_DEBUG_SHIFT) +# define DEVCFG0_DEBUG_ENABLED (2 << DEVCFG0_DEBUG_SHIFT) /* Debugger is enabled */ +# define DEVCFG0_DEBUG_DISABLED (3 << DEVCFG0_DEBUG_SHIFT) /* Debugger is disabled */ +#define DEVCFG0_JTAGEN (1 << 2) /* Bit 2: JTAG Enable bit(1) */ +#define DEVCFG0_ICESEL_SHIFT (3) /* Bits 3-4: ICE Communication Channel Select bits */ +#define DEVCFG0_ICESEL_MASK (3 << DEVCFG0_ICESEL_SHIFT) +# define DEVCFG0_ICESEL_1 (3 << DEVCFG0_ICESEL_SHIFT) /* PGEC1/PGED1 pair is used */ +# define DEVCFG0_ICESEL_2 (2 << DEVCFG0_ICESEL_SHIFT) /* PGEC2/PGED2 pair is used */ +#define DEVCFG0_TRCEN (1 << 5) /* Bit 5: Trace Enable bit */ +#define DEVCFG0_BOOTISA (1 << 6) /* Bit 6: Boot ISA Selection bit */ +# define DEVCFG0_BOOT_MIPS32 (1 << 6) /* Bit 6=1: Boot code and Exception code is MIPS32 */ +# define DEVCFG0_BOOT_MICROMIPS (0 << 6) /* Bit 6=0: Boot code and Exception code is microMIPS */ +#define DEVCFG0_FECCCON_SHIFT (8) /* Bit 8-9: Dynamic Flash ECC Configuration bits */ +#define DEVCFG0_FECCCON_MASK (3 << DEVCFG0_FECCCON_SHIFT) +# define DEVCFG0_FECCCON_ECC (0 << DEVCFG0_FECCCON_SHIFT) /* Flash ECC enabled (locked) */ +# define DEVCFG0_FECCCON_DYNECC (1 << DEVCFG0_FECCCON_SHIFT) /* Dynamic Flash ECC enabled (locked) */ +# define DEVCFG0_FECCCON_DISLCK (2 << DEVCFG0_FECCCON_SHIFT) /* ECC / dynamic ECC disabled (locked) */ +# define DEVCFG0_FECCCON_DISWR (3 << DEVCFG0_FECCCON_SHIFT) /* ECC / dynamic ECC disabled (writable) */ +#define DEVCFG0_FSLEEP (1 << 10) /* Bit 10: Flash Sleep Mode bit */ +# define DEVCFG0_FSLEEP_OFF (1 << 10) /* Bit 10=1: Flash powered down in sleep mode */ +# define DEVCFG0_FSLEEP_ON (0 << 10) /* Bit 10=0: Flash powerdown controlled by VREGS bit */ +#define DEVCFG0_DBGPER_SHIFT (12) /* Bits 12-14: Debug Mode CPU Access Permission bits */ +#define DEVCFG0_DBGPER_MASK (7 << DEVCFG0_DBGPER_SHIFT) +# define DEVCFG0_DBGPER_GROUP0 (1 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to group 0 regions */ +# define DEVCFG0_DBGPER_GROUP1 (2 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to group 1 regions */ +# define DEVCFG0_DBGPER_GROUP2 (4 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to group 2 regions */ +# define DEVCFG0_DBGPER_ALL (7 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to all regions */ +#define DEVCFG0_SMCLR (1 << 15) /* Bit 15: Soft Master Clear Enable bit */ +#define DEVCFG0_SOSCGAIN_SHIFT (16) /* Bits 16-17: Secondary Oscillator Gain Control bits */ +#define DEVCFG0_SOSCGAIN_MASK (3 << DEVCFG0_SOSCGAIN_SHIFT) +# define DEVCFG0_SOSCGAIN(n) ((uint32_t)(n) << DEVCFG0_SOSCGAIN_SHIFT) +# define DEVCFG0_SOSCGAIN_LOW (0 << DEVCFG0_SOSCGAIN_SHIFT) +# define DEVCFG0_SOSCGAIN_HIGH (3 << DEVCFG0_SOSCGAIN_SHIFT) +#define DEVCFG0_SOSCBOOST (1 << 18) /* Bit 18: Secondary Oscillator Boost Kick Start Enable bit */ +#define DEVCFG0_POSCGAIN_SHIFT (19) /* Bits 19-20: Primary Oscillator Gain Control bits */ +#define DEVCFG0_POSCGAIN_MASK (3 << DEVCFG0_POSCGAIN_SHIFT) +# define DEVCFG0_POSCGAIN(n) ((uint32_t)(n) << DEVCFG0_POSCGAIN_SHIFT) +# define DEVCFG0_POSCGAIN_LOW (0 << DEVCFG0_POSCGAIN_SHIFT) +# define DEVCFG0_POSCGAIN_HIGH (3 << DEVCFG0_POSCGAIN_SHIFT) +#define DEVCFG0_POSCBOOST (1 << 21) /* Bit 21: Primary Oscillator Boost Kick Start Enable bit */ +#define DEVCFG0_EJTAGBEN (1 << 30) /* Bit 30: EJTAG Boot Enable bit */ +# define DEVCFG0_EJTAG_NORMAL (1 << 30) /* Bit 30=1: Normal EJTAG functionality */ +# define DEVCFG0_EJTAG_REDUCED (0 << 30) /* Bit 30=0: Reduced EJTAG functionality */ + +#define DEVCFG0_RW0 0xbfe00880 /* Bits 7, 11, 21-29, 31: Reserved, write as one */ + +/* Device code protect words 1-3 / Alternate device code protect words 1-3 + * + * The DEVCP1 through DEVCP3 and ADEVCP1 through ADEVCP3 registers are used + * for Quad Word programming operation when programming the DEVCP0/ADEVCP0 + * registers, and do not contain any valid information. + */ + +/* Device code protect word 0 / Alternate device code protect word 0 */ + +#define DEVCP0_CP (1 << 28) /* Bit 28: Code-protect bit */ +#define DEVCP0_RWO 0xefffffff /* Bits 0-27, 28-31: Reserved, write as one */ + +/* Device signature words 1-3 / Alternate device signature words 1-3 + * + * The DEVSIGN1 through DEVSIGN3 and ADEVSIGN1 through ADEVSIGN3 registers + * are used for Quad Word programming operation when programming the + * DEVSIGN0/ADESIGN0 registers, and do not contain any valid information. + */ + +/* Device signature word 0 / Alternate device signature word 0 */ + +#define DEVSIGN0_RWZ 0x80000000 /* Bit 31: Reserved, write as zero */ +#define DEVSIGN0_RWO 0x7fffffff /* Bits 0-30: Reserved, write as one */ + +/* Device ADC Calibration (Boot Flash PIC32MZ_DEVSN_K1BASE) */ +/* ADC0-4,7 Calibration: 32-bit calibration values */ + +/* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASE) */ +/* Device serial number 0-1: 32-bit serial number data */ + +#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_FEATURES_H */ diff --git a/arch/mips/src/pic32mz/chip/pic32mzef-memorymap.h b/arch/mips/src/pic32mz/chip/pic32mzef-memorymap.h new file mode 100644 index 0000000000000000000000000000000000000000..d54e7296bd513a8bf6c42ed1632653706339a11e --- /dev/null +++ b/arch/mips/src/pic32mz/chip/pic32mzef-memorymap.h @@ -0,0 +1,147 @@ +/************************************************************************************ + * arch/mips/src/pic32mz/chip/pic32mzef-memorymap.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_MEMORYMAP_H +#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "mips32-memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Physical Memory Map **************************************************************/ +/* Memory Regions */ + +#define PIC32MZ_DATAMEM_PBASE 0x00000000 /* Size depends on CHIP_DATAMEM_KB */ +#define PIC32MZ_PROGFLASH_PBASE 0x1d000000 /* Size depends on CHIP_PROGFLASH_KB */ +#define PIC32MZ_SFR_PBASE 0x1f800000 /* Special function registers */ +#define PIC32MZ_BOOTFLASH_PBASE 0x1fc00000 /* Size depends on CHIP_BOOTFLASH_KB */ +#define PIC32MZ_EBIMEM_PBASE 0x20000000 /* External memory via EBI */ +#define PIC32MZ_SQIMEM_PBASE 0x30000000 /* External memory via SQI */ + +/* Boot FLASH */ + +#define PIC32MZ_LOWERBOOT_PBASE 0x1fc00000 /* Lower boot alias */ +#define PIC32MZ_BOOTCFG_PBASE 0x1fc0ff00 /* Configuration space */ +#define PIC32MZ_UPPERBOOT_PBASE 0x1fc20000 /* Upper boot alias */ +#define PIC32MZ_BOOT1_PBASE 0x1fc40000 /* Boot flash 1 */ +#define PIC32MZ_SEQCFG1_PBASE 0x1fc4ff00 /* Sequence/configuration space 1 */ +#define PIC32MZ_DEVSN_PBASE 0x1fc54000 /* Device serial number */ +#define PIC32MZ_BOOT2_PBASE 0x1fc60000 /* Boot flash 2 */ +#define PIC32MZ_SEQCFG2_PBASE 0x1fc6ff00 /* Sequence/configuration space 2 */ + +/* Virtual Memory Map ***************************************************************/ + +#define PIC32MZ_DATAMEM_K0BASE (KSEG0_BASE + PIC32MZ_DATAMEM_PBASE) +#define PIC32MZ_PROGFLASH_K0BASE (KSEG0_BASE + PIC32MZ_PROGFLASH_PBASE) +#define PIC32MZ_SFR_K0BASE (KSEG0_BASE + PIC32MZ_SFR_PBASE) +#define PIC32MZ_BOOTFLASH_K0BASE (KSEG0_BASE + PIC32MZ_BOOTFLASH_PBASE) +#define PIC32MZ_EBIMEM_K0BASE (KSEG0_BASE + PIC32MZ_EBIMEM_PBASE) +#define PIC32MZ_SQIMEM_K0BASE (KSEG0_BASE + PIC32MZ_SQIMEM_PBASE) + +#define PIC32MZ_DATAMEM_K1BASE (KSEG1_BASE + PIC32MZ_DATAMEM_PBASE) +#define PIC32MZ_PROGFLASH_K1BASE (KSEG1_BASE + PIC32MZ_PROGFLASH_PBASE) +#define PIC32MZ_SFR_K1BASE (KSEG1_BASE + PIC32MZ_SFR_PBASE) +#define PIC32MZ_BOOTFLASH_K1BASE (KSEG1_BASE + PIC32MZ_BOOTFLASH_PBASE) +#define PIC32MZ_EBIMEM_K1BASE (KSEG1_BASE + PIC32MZ_EBIMEM_PBASE) +#define PIC32MZ_SQIMEM_K1BASE (KSEG1_BASE + PIC32MZ_SQIMEM_PBASE) + +/* Boot FLASH */ + +#define PIC32MZ_LOWERBOOT_K0BASE (KSEG0_BASE + PIC32MZ_LOWERBOOT_PBASE) +#define PIC32MZ_BOOTCFG_K0BASE (KSEG0_BASE + PIC32MZ_BOOTCFG_PBASE) +#define PIC32MZ_UPPERBOOT_K0BASE (KSEG0_BASE + PIC32MZ_UPPERBOOT_PBASE) +#define PIC32MZ_BOOT1_K0BASE (KSEG0_BASE + PIC32MZ_BOOT1_PBASE) +#define PIC32MZ_SEQCFG1_K0BASE (KSEG0_BASE + PIC32MZ_SEQCFG1_PBASE) +#define PIC32MZ_DEVSN_K0BASE (KSEG0_BASE + PIC32MZ_DEVSN_PBASE) +#define PIC32MZ_BOOT2_K0BASE (KSEG0_BASE + PIC32MZ_BOOT2_PBASE) +#define PIC32MZ_SEQCFG2_K0BASE (KSEG0_BASE + PIC32MZ_SEQCFG2_PBASE) + +#define PIC32MZ_LOWERBOOT_K1BASE (KSEG1_BASE + PIC32MZ_LOWERBOOT_PBASE) +#define PIC32MZ_BOOTCFG_K1BASE (KSEG1_BASE + PIC32MZ_BOOTCFG_PBASE) +#define PIC32MZ_UPPERBOOT_K1BASE (KSEG1_BASE + PIC32MZ_UPPERBOOT_PBASE) +#define PIC32MZ_BOOT1_K1BASE (KSEG1_BASE + PIC32MZ_BOOT1_PBASE) +#define PIC32MZ_SEQCFG1_K1BASE (KSEG1_BASE + PIC32MZ_SEQCFG1_PBASE) +#define PIC32MZ_DEVSN_K1BASE (KSEG1_BASE + PIC32MZ_DEVSN_PBASE) +#define PIC32MZ_BOOT2_K1BASE (KSEG1_BASE + PIC32MZ_BOOT2_PBASE) +#define PIC32MZ_SEQCFG2_K1BASE (KSEG1_BASE + PIC32MZ_SEQCFG2_PBASE) + +/* Register Base Addresses **********************************************************/ + +#define PIC32MZ_CONFIG_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000000) /* Configuration */ +#define PIC32MZ_FLASHC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000600) /* Flash Controller */ +#define PIC32MZ_WDT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000800) /* Watchdog Timer */ +#define PIC32MZ_DMT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000a00) /* Deadman Timer */ +#define PIC32MZ_RTCC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000c00) /* RTCC */ +#define PIC32MZ_CVREF_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000e00) /* CVREF */ +#define PIC32MZ_OSC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00001200) /* Oscillator */ +#define PIC32MZ_PPS_K1BASE (PIC32MZ_SFR_K1BASE + 0x00001400) /* PPS */ + +#define PIC32MZ_INT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00010000) /* Interrupt Controller */ +#define PIC32MZ_DMA_K1BASE (PIC32MZ_SFR_K1BASE + 0x00011000) /* DMA */ + +#define PIC32MZ_I2C_K1BASE (PIC32MZ_SFR_K1BASE + 0x00020000) /* I2C1-I2C5 */ +#define PIC32MZ_SPI_K1BASE (PIC32MZ_SFR_K1BASE + 0x00021000) /* SPI1-SPI6 */ +#define PIC32MZ_UART_K1BASE (PIC32MZ_SFR_K1BASE + 0x00022000) /* UART1-UART6 */ +#define PIC32MZ_PMP_K1BASE (PIC32MZ_SFR_K1BASE + 0x0002e000) /* PMP */ + +#define PIC32MZ_TIMER_K1BASE (PIC32MZ_SFR_K1BASE + 0x00040000) /* Timer1-Timer9 */ +#define PIC32MZ_IC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00042000) /* IC1-IC9 */ +#define PIC32MZ_OC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00044000) /* OC1-OC9 */ +#define PIC32MZ_ADC1_K1BASE (PIC32MZ_SFR_K1BASE + 0x0004b000) /* ADC1 */ +#define PIC32MZ_CMP_K1BASE (PIC32MZ_SFR_K1BASE + 0x0004c000) /* Comparator 1, 2 */ + +#define PIC32MZ_IOPORT_K1BASE (PIC32MZ_SFR_K1BASE + 0x00060000) /* PORTA-PORTK */ + +#define PIC32MZ_CAN_K1BASE (PIC32MZ_SFR_K1BASE + 0x00080000) /* CAN1 and CAN2 */ +#define PIC32MZ_ETH_K1BASE (PIC32MZ_SFR_K1BASE + 0x00082000) /* Ethernet */ +#define PIC32MZ_USBCR_K1BASE (PIC32MZ_SFR_K1BASE + 0x00084000) /* USBCR */ + +#define PIC32MZ_PREFETCH_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e0000) /* Prefetch */ +#define PIC32MZ_EBI_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e1000) /* EBI */ +#define PIC32MZ_SQI1_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e2000) /* SQI1 */ +#define PIC32MZ_USB_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e3000) /* USB */ +#define PIC32MZ_CRYPTO_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e5000) /* Crypto */ +#define PIC32MZ_RNG_K1BASE (PIC32MZ_SFR_K1BASE + 0x000e6000) /* RNG */ + +#define PIC32MZ_SYSBUS_K1BASE (PIC32MZ_SFR_K1BASE + 0x000f0000) /* System Bus */ + +#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_MEMORYMAP_H */ diff --git a/arch/mips/src/pic32mz/chip/pic32mzef-pps.h b/arch/mips/src/pic32mz/chip/pic32mzef-pps.h new file mode 100644 index 0000000000000000000000000000000000000000..8e65d3f3e9174f70e3d049e678d9355d1ab609b7 --- /dev/null +++ b/arch/mips/src/pic32mz/chip/pic32mzef-pps.h @@ -0,0 +1,1719 @@ +/******************************************************************************************** + * arch/mips/src/pic32mz/pic32mzef-pps.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_PPS_H +#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_PPS_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include "pic32mz-memorymap.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ +/* PPS Register Offsets *********************************************************************/ + +/* Peripheral pin select input register map */ + +#define PIC32MZ_INTnR_OFFSET(n) (0x1400 + ((n << 2)) /* n=1..4 */ +# define PIC32MZ_INT1R_OFFSET 0x1404 +# define PIC32MZ_INT2R_OFFSET 0x1408 +# define PIC32MZ_INT3R_OFFSET 0x140c +# define PIC32MZ_INT4R_OFFSET 0x1410 +#define PIC32MZ_TnCKR_OFFSET(n) (0x1410 + ((n << 2)) /* n=2..9 */ +# define PIC32MZ_I2TKR_OFFSET 0x1418 +# define PIC32MZ_I3TKR_OFFSET 0x141c +# define PIC32MZ_I4TKR_OFFSET 0x1420 +# define PIC32MZ_I5TKR_OFFSET 0x1424 +# define PIC32MZ_I6TKR_OFFSET 0x1428 +# define PIC32MZ_I7TKR_OFFSET 0x142c +# define PIC32MZ_I8TKR_OFFSET 0x1430 +# define PIC32MZ_I9TKR_OFFSET 0x1434 +#define PIC32MZ_ICnR_OFFSET(n) (0x1434 + ((n << 2)) /* n=1..9 */ +# define PIC32MZ_IC1R_OFFSET 0x1438 +# define PIC32MZ_IC2R_OFFSET 0x143c +# define PIC32MZ_IC3R_OFFSET 0x1440 +# define PIC32MZ_IC4R_OFFSET 0x1444 +# define PIC32MZ_IC5R_OFFSET 0x1448 +# define PIC32MZ_IC6R_OFFSET 0x144c +# define PIC32MZ_IC7R_OFFSET 0x1450 +# define PIC32MZ_IC8R_OFFSET 0x1454 +# define PIC32MZ_IC9R_OFFSET 0x1458 +#define PIC32MZ_OCFAR_OFFSET 0x1460 +#define PIC32MZ_UnRXR_OFFSET(n) (0x1460 + ((n << 3)) /* n=1..6 */ +# define PIC32MZ_U1RXR_OFFSET 0x1468 +# define PIC32MZ_U2RXR_OFFSET 0x1470 +# define PIC32MZ_U3RXR_OFFSET 0x1478 +# define PIC32MZ_U4RXR_OFFSET 0x1480 +# define PIC32MZ_U5RXR_OFFSET 0x1488 +# define PIC32MZ_U6RXR_OFFSET 0x1490 +#define PIC32MZ_UnCTSR_OFFSET(n) (0x1464 + ((n << 3)) /* n=1..6 */ +# define PIC32MZ_U1CTSR_OFFSET 0x146c +# define PIC32MZ_U2CTSR_OFFSET 0x1474 +# define PIC32MZ_U3CTSR_OFFSET 0x147c +# define PIC32MZ_U4CTSR_OFFSET 0x1484 +# define PIC32MZ_U5CTSR_OFFSET 0x148c +# define PIC32MZ_U6CTSR_OFFSET 0x1494 +#define PIC32MZ_SDInR_OFFSET(n) (0x1490 + 12*(n)) /* n=1..6 */ +# define PIC32MZ_SDI1R_OFFSET 0x149c +# define PIC32MZ_SDI2R_OFFSET 0x14a8 +# define PIC32MZ_SDI3R_OFFSET 0x14b4 +# define PIC32MZ_SDI4R_OFFSET 0x14c0 +# define PIC32MZ_SDI5R_OFFSET 0x14cc +# define PIC32MZ_SDI6R_OFFSET 0x14d8 +#define PIC32MZ_SSnR_OFFSET(n) (0x1494 + 12*(n)) /* n=1..6 */ +# define PIC32MZ_SS1R_OFFSET 0x14a0 +# define PIC32MZ_SS2R_OFFSET 0x14ac +# define PIC32MZ_SS3R_OFFSET 0x14b8 +# define PIC32MZ_SS4R_OFFSET 0x14c4 +# define PIC32MZ_SS5R_OFFSET 0x14d0 +# define PIC32MZ_SS6R_OFFSET 0x14dc +#define PIC32MZ_CnRXR_OFFSET(n) (0x14dc + ((n) << 2)) /* n=1..2 */ +# define PIC32MZ_C1RXR_OFFSET 0x14e0 +# define PIC32MZ_C2RXR_OFFSET 0x14e4 +#define PIC32MZ_REFCLKInR_OFFSET(n) (0x14e4 + ((n) << 2)) /* n=1,3,4 */ +# define PIC32MZ_REFCLKI1R_OFFSET 0x14e8 +# define PIC32MZ_REFCLKI3R_OFFSET 0x14f0 +# define PIC32MZ_REFCLKI4R_OFFSET 0x14f4 + +/* Peripheral pin select output register map */ + +#define PIC32MZ_RPAnR_OFFSET(n) (0x1500 + ((n) << 2)) /* n=14,15 */ +# define PIC32MZ_RPA14R_OFFSET 0x1538 +# define PIC32MZ_RPA15R_OFFSET 0x153c +#define PIC32MZ_RPBnR_OFFSET(n) (0x1540 + ((n) << 2)) /* n=0..,15 */ +# define PIC32MZ_RPB0R_OFFSET 0x1540 +# define PIC32MZ_RPB1R_OFFSET 0x1544 +# define PIC32MZ_RPB2R_OFFSET 0x1548 +# define PIC32MZ_RPB3R_OFFSET 0x154c +# define PIC32MZ_RPB4R_OFFSET 0x1550 +# define PIC32MZ_RPB5R_OFFSET 0x1554 +# define PIC32MZ_RPB6R_OFFSET 0x1558 +# define PIC32MZ_RPB7R_OFFSET 0x155c +# define PIC32MZ_RPB8R_OFFSET 0x1560 +# define PIC32MZ_RPB9R_OFFSET 0x1564 +# define PIC32MZ_RPB10R_OFFSET 0x1568 +# define PIC32MZ_RPB11R_OFFSET 0x156c +# define PIC32MZ_RPB12R_OFFSET 0x1570 +# define PIC32MZ_RPB13R_OFFSET 0x1574 +# define PIC32MZ_RPB14R_OFFSET 0x1578 +# define PIC32MZ_RPB15R_OFFSET 0x157c +#define PIC32MZ_RPCnR_OFFSET(n) (0x1580 + ((n) << 2)) /* n=1..4,13,14 */ +# define PIC32MZ_RPC1R_OFFSET 0x1584 +# define PIC32MZ_RPC2R_OFFSET 0x1588 +# define PIC32MZ_RPC3R_OFFSET 0x158c +# define PIC32MZ_RPC4R_OFFSET 0x1590 +# define PIC32MZ_RPC13R_OFFSET 0x15b4 +# define PIC32MZ_RPC14R_OFFSET 0x15b8 +#define PIC32MZ_RPDnR_OFFSET(n) (0x15c0 + ((n) << 2)) /* n=0..15 */ +# define PIC32MZ_RPD0R_OFFSET 0x15c0 +# define PIC32MZ_RPD1R_OFFSET 0x15c4 +# define PIC32MZ_RPD2R_OFFSET 0x15c8 +# define PIC32MZ_RPD3R_OFFSET 0x15cc +# define PIC32MZ_RPD4R_OFFSET 0x15d0 +# define PIC32MZ_RPD5R_OFFSET 0x15d4 +# define PIC32MZ_RPD6R_OFFSET 0x15d8 +# define PIC32MZ_RPD7R_OFFSET 0x15dc +# define PIC32MZ_RPD8R_OFFSET 0x15e0 +# define PIC32MZ_RPD9R_OFFSET 0x15e4 +# define PIC32MZ_RPD10R_OFFSET 0x15e8 +# define PIC32MZ_RPD11R_OFFSET 0x15ec +# define PIC32MZ_RPD12R_OFFSET 0x15f0 +# define PIC32MZ_RPD13R_OFFSET 0x15f4 +# define PIC32MZ_RPD14R_OFFSET 0x15f8 +# define PIC32MZ_RPD15R_OFFSET 0x15fc +#define PIC32MZ_RPEnR_OFFSET(n) (0x1600 + ((n) << 2)) /* n=3,5,8-9 */ +# define PIC32MZ_RPE3R_OFFSET 0x160c +# define PIC32MZ_RPE4R_OFFSET 0x1614 +# define PIC32MZ_RPE8R_OFFSET 0x1620 +# define PIC32MZ_RPE9R_OFFSET 0x1624 +#define PIC32MZ_RPFnR_OFFSET(n) (0x1640 + ((n) << 2)) /* n=0-5,8,12-13 */ +# define PIC32MZ_RPF0R_OFFSET 0x1640 +# define PIC32MZ_RPF1R_OFFSET 0x1644 +# define PIC32MZ_RPF2R_OFFSET 0x1648 +# define PIC32MZ_RPF3R_OFFSET 0x164c +# define PIC32MZ_RPF4R_OFFSET 0x1650 +# define PIC32MZ_RPF5R_OFFSET 0x1654 +# define PIC32MZ_RPF8R_OFFSET 0x1660 +# define PIC32MZ_RPF12R_OFFSET 0x1670 +# define PIC32MZ_RPF13R_OFFSET 0x1674 +#define PIC32MZ_RPGnR_OFFSET(n) (0x1680 + ((n) << 2)) /* n=0-1,6-8,9 */ +# define PIC32MZ_RPG0R_OFFSET 0x1680 +# define PIC32MZ_RPG1R_OFFSET 0x1684 +# define PIC32MZ_RPG6R_OFFSET 0x1698 +# define PIC32MZ_RPG7R_OFFSET 0x169c +# define PIC32MZ_RPG8R_OFFSET 0x16a0 +# define PIC32MZ_RPG9R_OFFSET 0x16a4 + +/* PPS Register Addresses *******************************************************************/ + +/* Peripheral pin select input register map */ + +#define PIC32MZ_INTnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_INTnR_OFFSET(n)) +# define PIC32MZ_INT1R (PIC32MZ_SFR_K1BASE+PIC32MZ_INT1R_OFFSET) +# define PIC32MZ_INT2R (PIC32MZ_SFR_K1BASE+PIC32MZ_INT2R_OFFSET) +# define PIC32MZ_INT3R (PIC32MZ_SFR_K1BASE+PIC32MZ_INT3R_OFFSET) +# define PIC32MZ_INT4R (PIC32MZ_SFR_K1BASE+PIC32MZ_INT4R_OFFSET) +#define PIC32MZ_TnCKR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_TnCKR_OFFSET(n)) +# define PIC32MZ_I2TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I2TKR_OFFSET) +# define PIC32MZ_I3TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I3TKR_OFFSET) +# define PIC32MZ_I4TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I4TKR_OFFSET) +# define PIC32MZ_I5TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I5TKR_OFFSET) +# define PIC32MZ_I6TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I6TKR_OFFSET) +# define PIC32MZ_I7TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I7TKR_OFFSET) +# define PIC32MZ_I8TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I8TKR_OFFSET) +# define PIC32MZ_I9TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I9TKR_OFFSET) +#define PIC32MZ_ICnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_ICnR_OFFSET(n)) +# define PIC32MZ_IC1R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC1R_OFFSET) +# define PIC32MZ_IC2R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC2R_OFFSET) +# define PIC32MZ_IC3R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC3R_OFFSET) +# define PIC32MZ_IC4R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC4R_OFFSET) +# define PIC32MZ_IC5R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC5R_OFFSET) +# define PIC32MZ_IC6R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC6R_OFFSET) +# define PIC32MZ_IC7R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC7R_OFFSET) +# define PIC32MZ_IC8R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC8R_OFFSET) +# define PIC32MZ_IC9R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC9R_OFFSET) +#define PIC32MZ_OCFAR (PIC32MZ_SFR_K1BASE+PIC32MZ_OCFAR_OFFSET) +#define PIC32MZ_UnRXR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_UnRXR_OFFSET(n)) +# define PIC32MZ_U1RXR (PIC32MZ_SFR_K1BASE+PIC32MZ_U1RXR_OFFSET) +# define PIC32MZ_U2RXR (PIC32MZ_SFR_K1BASE+PIC32MZ_U2RXR_OFFSET) +# define PIC32MZ_U3RXR (PIC32MZ_SFR_K1BASE+PIC32MZ_U3RXR_OFFSET) +# define PIC32MZ_U4RXR (PIC32MZ_SFR_K1BASE+PIC32MZ_U4RXR_OFFSET) +# define PIC32MZ_U5RXR (PIC32MZ_SFR_K1BASE+PIC32MZ_U5RXR_OFFSET) +# define PIC32MZ_U6RXR (PIC32MZ_SFR_K1BASE+PIC32MZ_U6RXR_OFFSET) +#define PIC32MZ_UnCTSR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_UnCTSR_OFFSET(n) +# define PIC32MZ_U1CTSR (PIC32MZ_SFR_K1BASE+PIC32MZ_U1CTSR_OFFSET) +# define PIC32MZ_U2CTSR (PIC32MZ_SFR_K1BASE+PIC32MZ_U2CTSR_OFFSET) +# define PIC32MZ_U3CTSR (PIC32MZ_SFR_K1BASE+PIC32MZ_U3CTSR_OFFSET) +# define PIC32MZ_U4CTSR (PIC32MZ_SFR_K1BASE+PIC32MZ_U4CTSR_OFFSET) +# define PIC32MZ_U5CTSR (PIC32MZ_SFR_K1BASE+PIC32MZ_U5CTSR_OFFSET) +# define PIC32MZ_U6CTSR (PIC32MZ_SFR_K1BASE+PIC32MZ_U6CTSR_OFFSET) +#define PIC32MZ_SDInR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_SDInR_OFFSET(n)) +# define PIC32MZ_SDI1R (PIC32MZ_SFR_K1BASE+PIC32MZ_SDI1R_OFFSET) +# define PIC32MZ_SDI2R (PIC32MZ_SFR_K1BASE+PIC32MZ_SDI2R_OFFSET) +# define PIC32MZ_SDI3R (PIC32MZ_SFR_K1BASE+PIC32MZ_SDI3R_OFFSET) +# define PIC32MZ_SDI4R (PIC32MZ_SFR_K1BASE+PIC32MZ_SDI4R_OFFSET) +# define PIC32MZ_SDI5R (PIC32MZ_SFR_K1BASE+PIC32MZ_SDI5R_OFFSET) +# define PIC32MZ_SDI6R (PIC32MZ_SFR_K1BASE+PIC32MZ_SDI6R_OFFSET) +#define PIC32MZ_SSnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_SSnR_OFFSET(n)) +# define PIC32MZ_SS1R (PIC32MZ_SFR_K1BASE+PIC32MZ_SS1R_OFFSET) +# define PIC32MZ_SS2R (PIC32MZ_SFR_K1BASE+PIC32MZ_SS2R_OFFSET) +# define PIC32MZ_SS3R (PIC32MZ_SFR_K1BASE+PIC32MZ_SS3R_OFFSET) +# define PIC32MZ_SS4R (PIC32MZ_SFR_K1BASE+PIC32MZ_SS4R_OFFSET) +# define PIC32MZ_SS5R (PIC32MZ_SFR_K1BASE+PIC32MZ_SS5R_OFFSET) +# define PIC32MZ_SS6R (PIC32MZ_SFR_K1BASE+PIC32MZ_SS6R_OFFSET) +#define PIC32MZ_CnRXR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_CnRXR_OFFSET(n)) +# define PIC32MZ_C1RXR (PIC32MZ_SFR_K1BASE+PIC32MZ_C1RXR_OFFSET) +# define PIC32MZ_C2RXR (PIC32MZ_SFR_K1BASE+PIC32MZ_C2RXR_OFFSET) +#define PIC32MZ_REFCLKInR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_REFCLKInR_OFFSET(n)) +# define PIC32MZ_REFCLKI1R (PIC32MZ_SFR_K1BASE+PIC32MZ_REFCLKI1R_OFFSET) +# define PIC32MZ_REFCLKI3R (PIC32MZ_SFR_K1BASE+PIC32MZ_REFCLKI3R_OFFSET) +# define PIC32MZ_REFCLKI4R (PIC32MZ_SFR_K1BASE+PIC32MZ_REFCLKI4R_OFFSET) + +/* Peripheral pin select output register map */ + +#define PIC32MZ_RPAnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_RPAnR_OFFSET(n)) +# define PIC32MZ_RPA14R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPA14R_OFFSET) +# define PIC32MZ_RPA15R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPA15R_OFFSET) +#define PIC32MZ_RPBnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_RPBnR_OFFSET(n)) +# define PIC32MZ_RPB0R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB0R_OFFSET) +# define PIC32MZ_RPB1R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB1R_OFFSET) +# define PIC32MZ_RPB2R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB2R_OFFSET) +# define PIC32MZ_RPB3R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB3R_OFFSET) +# define PIC32MZ_RPB4R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB4R_OFFSET) +# define PIC32MZ_RPB5R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB5R_OFFSET) +# define PIC32MZ_RPB6R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB6R_OFFSET) +# define PIC32MZ_RPB7R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB7R_OFFSET) +# define PIC32MZ_RPB8R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB8R_OFFSET) +# define PIC32MZ_RPB9R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB9R_OFFSET) +# define PIC32MZ_RPB10R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB10R_OFFSET) +# define PIC32MZ_RPB11R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB11R_OFFSET) +# define PIC32MZ_RPB12R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB12R_OFFSET) +# define PIC32MZ_RPB13R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB13R_OFFSET) +# define PIC32MZ_RPB14R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB14R_OFFSET) +# define PIC32MZ_RPB15R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPB15R_OFFSET) +#define PIC32MZ_RPCnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_RPCnR_OFFSET(n)) +# define PIC32MZ_RPC1R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPC1R_OFFSET) +# define PIC32MZ_RPC2R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPC2R_OFFSET) +# define PIC32MZ_RPC3R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPC3R_OFFSET) +# define PIC32MZ_RPC4R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPC4R_OFFSET) +# define PIC32MZ_RPC13R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPC13R_OFFSET) +# define PIC32MZ_RPC14R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPC14R_OFFSET) +#define PIC32MZ_RPDnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_RPDnR_OFFSET(n)) +# define PIC32MZ_RPD0R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD0R_OFFSET) +# define PIC32MZ_RPD1R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD1R_OFFSET) +# define PIC32MZ_RPD2R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD2R_OFFSET) +# define PIC32MZ_RPD3R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD3R_OFFSET) +# define PIC32MZ_RPD4R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD4R_OFFSET) +# define PIC32MZ_RPD5R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD5R_OFFSET) +# define PIC32MZ_RPD6R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD6R_OFFSET) +# define PIC32MZ_RPD7R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD7R_OFFSET) +# define PIC32MZ_RPD8R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD8R_OFFSET) +# define PIC32MZ_RPD9R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD9R_OFFSET) +# define PIC32MZ_RPD10R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD10R_OFFSET) +# define PIC32MZ_RPD11R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD11R_OFFSET) +# define PIC32MZ_RPD12R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD12R_OFFSET) +# define PIC32MZ_RPD13R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD13R_OFFSET) +# define PIC32MZ_RPD14R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD14R_OFFSET) +# define PIC32MZ_RPD15R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPD15R_OFFSET) +#define PIC32MZ_RPEnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_RPEnR_OFFSET(n)) +# define PIC32MZ_RPE3R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPE3R_OFFSET) +# define PIC32MZ_RPE4R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPE4R_OFFSET) +# define PIC32MZ_RPE8R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPE8R_OFFSET) +# define PIC32MZ_RPE9R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPE9R_OFFSET) +#define PIC32MZ_RPFnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_RPFnR_OFFSET(n)) +# define PIC32MZ_RPF0R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF0R_OFFSET) +# define PIC32MZ_RPF1R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF1R_OFFSET) +# define PIC32MZ_RPF2R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF2R_OFFSET) +# define PIC32MZ_RPF3R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF3R_OFFSET) +# define PIC32MZ_RPF4R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF4R_OFFSET) +# define PIC32MZ_RPF5R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF5R_OFFSET) +# define PIC32MZ_RPF8R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF8R_OFFSET) +# define PIC32MZ_RPF12R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF12R_OFFSET) +# define PIC32MZ_RPF13R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPF13R_OFFSET) +#define PIC32MZ_RPGnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_RPGnR_OFFSET(n)) +# define PIC32MZ_RPG0R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPG0R_OFFSET) +# define PIC32MZ_RPG1R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPG1R_OFFSET) +# define PIC32MZ_RPG6R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPG6R_OFFSET) +# define PIC32MZ_RPG7R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPG7R_OFFSET) +# define PIC32MZ_RPG8R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPG8R_OFFSET) +# define PIC32MZ_RPG9R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPG9R_OFFSET) + +/* Input Pin Selection **********************************************************************/ +/* The encoding of the input pin selection is simple. Since we know the devices, we also + * can infer the register address so we need only the value for the register which is + * exactly what is provided by the following definitions. + */ + +#define C1RXR_RPA15 13 +#define C1RXR_RPB1 5 +#define C1RXR_RPB3 8 +#define C1RXR_RPC4 10 +#define C1RXR_RPC13 7 +#define C1RXR_RPD3 0 +#define C1RXR_RPD7 14 +#define C1RXR_RPD11 3 +#define C1RXR_RPD15 11 +#define C1RXR_RPE5 6 +#define C1RXR_RPF0 4 +#define C1RXR_RPF5 2 +#define C1RXR_RPG0 12 +#define C1RXR_RPG7 1 + +#define C2RXR_RPB0 5 +#define C2RXR_RPB7 7 +#define C2RXR_RPB8 2 +#define C2RXR_RPB15 3 +#define C2RXR_RPC3 12 +#define C2RXR_RPD4 4 +#define C2RXR_RPD9 0 +#define C2RXR_RPD12 10 +#define C2RXR_RPE3 6 +#define C2RXR_RPE9 13 +#define C2RXR_RPF8 11 +#define C2RXR_RPF12 9 +#define C2RXR_RPG6 1 + +#define IC1R_RPB2 7 +#define IC1R_RPB6 5 +#define IC1R_RPB14 2 +#define IC1R_RPC2 12 +#define IC1R_RPD0 3 +#define IC1R_RPD1 0 +#define IC1R_RPD5 6 +#define IC1R_RPE8 13 +#define IC1R_RPF2 11 +#define IC1R_RPF3 8 +#define IC1R_RPF13 9 +#define IC1R_RPG9 1 + +#define IC2R_RPB0 5 +#define IC2R_RPB7 7 +#define IC2R_RPB8 2 +#define IC2R_RPB15 3 +#define IC2R_RPC3 12 +#define IC2R_RPD4 4 +#define IC2R_RPD9 0 +#define IC2R_RPD12 10 +#define IC2R_RPE3 6 +#define IC2R_RPE9 13 +#define IC2R_RPF8 11 +#define IC2R_RPF12 9 +#define IC2R_RPG6 1 + +#define IC3R_RPA14 13 +#define IC3R_RPB5 8 +#define IC3R_RPB9 5 +#define IC3R_RPB10 6 +#define IC3R_RPC1 10 +#define IC3R_RPC14 7 +#define IC3R_RPD2 0 +#define IC3R_RPD6 14 +#define IC3R_RPD10 3 +#define IC3R_RPD14 11 +#define IC3R_RPF1 4 +#define IC3R_RPF4 2 +#define IC3R_RPG1 12 +#define IC3R_RPG8 1 + +#define IC4R_RPA15 13 +#define IC4R_RPB1 5 +#define IC4R_RPB3 8 +#define IC4R_RPC4 10 +#define IC4R_RPC13 7 +#define IC4R_RPD3 0 +#define IC4R_RPD7 14 +#define IC4R_RPD11 3 +#define IC4R_RPD15 11 +#define IC4R_RPE5 6 +#define IC4R_RPF0 4 +#define IC4R_RPF5 2 +#define IC4R_RPG0 12 +#define IC4R_RPG7 1 + +#define IC5R_RPB0 5 +#define IC5R_RPB7 7 +#define IC5R_RPB8 2 +#define IC5R_RPB15 3 +#define IC5R_RPC3 12 +#define IC5R_RPD4 4 +#define IC5R_RPD9 0 +#define IC5R_RPD12 10 +#define IC5R_RPE3 6 +#define IC5R_RPE9 13 +#define IC5R_RPF8 11 +#define IC5R_RPF12 9 +#define IC5R_RPG6 1 + +#define IC6R_RPB2 7 +#define IC6R_RPB6 5 +#define IC6R_RPB14 2 +#define IC6R_RPC2 12 +#define IC6R_RPD0 3 +#define IC6R_RPD1 0 +#define IC6R_RPD5 6 +#define IC6R_RPE8 13 +#define IC6R_RPF2 11 +#define IC6R_RPF3 8 +#define IC6R_RPF13 9 +#define IC6R_RPG9 1 + +#define IC7R_RPA14 13 +#define IC7R_RPB5 8 +#define IC7R_RPB9 5 +#define IC7R_RPB10 6 +#define IC7R_RPC1 10 +#define IC7R_RPC14 7 +#define IC7R_RPD2 0 +#define IC7R_RPD6 14 +#define IC7R_RPD10 3 +#define IC7R_RPD14 11 +#define IC7R_RPF1 4 +#define IC7R_RPF4 2 +#define IC7R_RPG1 12 +#define IC7R_RPG8 1 + +#define IC8R_RPA15 13 +#define IC8R_RPB1 5 +#define IC8R_RPB3 8 +#define IC8R_RPC4 10 +#define IC8R_RPC13 7 +#define IC8R_RPD3 0 +#define IC8R_RPD7 14 +#define IC8R_RPD11 3 +#define IC8R_RPD15 11 +#define IC8R_RPE5 6 +#define IC8R_RPF0 4 +#define IC8R_RPF5 2 +#define IC8R_RPG0 12 +#define IC8R_RPG7 1 + +#define IC9R_RPB0 5 +#define IC9R_RPB7 7 +#define IC9R_RPB8 2 +#define IC9R_RPB15 3 +#define IC9R_RPC3 12 +#define IC9R_RPD4 4 +#define IC9R_RPD9 0 +#define IC9R_RPD12 10 +#define IC9R_RPE3 6 +#define IC9R_RPE9 13 +#define IC9R_RPF8 11 +#define IC9R_RPF12 9 +#define IC9R_RPG6 1 + +#define INT1R_RPB2 7 +#define INT1R_RPB6 5 +#define INT1R_RPB14 2 +#define INT1R_RPC2 12 +#define INT1R_RPD0 3 +#define INT1R_RPD1 0 +#define INT1R_RPD5 6 +#define INT1R_RPE8 13 +#define INT1R_RPF2 11 +#define INT1R_RPF3 8 +#define INT1R_RPF13 9 +#define INT1R_RPG9 1 + +#define INT2R_RPB0 5 +#define INT2R_RPB7 7 +#define INT2R_RPB8 2 +#define INT2R_RPB15 3 +#define INT2R_RPC3 12 +#define INT2R_RPD4 4 +#define INT2R_RPD9 0 +#define INT2R_RPD12 10 +#define INT2R_RPE3 6 +#define INT2R_RPE9 13 +#define INT2R_RPF8 11 +#define INT2R_RPF12 9 +#define INT2R_RPG6 1 + +#define INT3R_RPA14 13 +#define INT3R_RPB5 8 +#define INT3R_RPB9 5 +#define INT3R_RPB10 6 +#define INT3R_RPC1 10 +#define INT3R_RPC14 7 +#define INT3R_RPD2 0 +#define INT3R_RPD6 14 +#define INT3R_RPD10 3 +#define INT3R_RPD14 11 +#define INT3R_RPF1 4 +#define INT3R_RPF4 2 +#define INT3R_RPG1 12 +#define INT3R_RPG8 1 + +#define INT4R_RPA15 13 +#define INT4R_RPB1 5 +#define INT4R_RPB3 8 +#define INT4R_RPC4 10 +#define INT4R_RPC13 7 +#define INT4R_RPD3 0 +#define INT4R_RPD7 14 +#define INT4R_RPD11 3 +#define INT4R_RPD15 11 +#define INT4R_RPE5 6 +#define INT4R_RPF0 4 +#define INT4R_RPF5 2 +#define INT4R_RPG0 12 +#define INT4R_RPG7 1 + +#define OCFAR_RPB2 7 +#define OCFAR_RPB6 5 +#define OCFAR_RPB14 2 +#define OCFAR_RPC2 12 +#define OCFAR_RPD0 3 +#define OCFAR_RPD1 0 +#define OCFAR_RPD5 6 +#define OCFAR_RPE8 13 +#define OCFAR_RPF2 11 +#define OCFAR_RPF3 8 +#define OCFAR_RPF13 9 +#define OCFAR_RPG9 1 + +#define REFCLKI1R_RPA14 13 +#define REFCLKI1R_RPB5 8 +#define REFCLKI1R_RPB9 5 +#define REFCLKI1R_RPB10 6 +#define REFCLKI1R_RPC1 10 +#define REFCLKI1R_RPC14 7 +#define REFCLKI1R_RPD2 0 +#define REFCLKI1R_RPD6 14 +#define REFCLKI1R_RPD10 3 +#define REFCLKI1R_RPD14 11 +#define REFCLKI1R_RPF1 4 +#define REFCLKI1R_RPF4 2 +#define REFCLKI1R_RPG1 12 +#define REFCLKI1R_RPG8 1 + +#define REFCLKI3R_RPB2 7 +#define REFCLKI3R_RPB6 5 +#define REFCLKI3R_RPB14 2 +#define REFCLKI3R_RPC2 12 +#define REFCLKI3R_RPD0 3 +#define REFCLKI3R_RPD1 0 +#define REFCLKI3R_RPD5 6 +#define REFCLKI3R_RPE8 13 +#define REFCLKI3R_RPF2 11 +#define REFCLKI3R_RPF3 8 +#define REFCLKI3R_RPF13 9 +#define REFCLKI3R_RPG9 1 + +#define REFCLKI4R_RPA15 13 +#define REFCLKI4R_RPB1 5 +#define REFCLKI4R_RPB3 8 +#define REFCLKI4R_RPC4 10 +#define REFCLKI4R_RPC13 7 +#define REFCLKI4R_RPD3 0 +#define REFCLKI4R_RPD7 14 +#define REFCLKI4R_RPD11 3 +#define REFCLKI4R_RPD15 11 +#define REFCLKI4R_RPE5 6 +#define REFCLKI4R_RPF0 4 +#define REFCLKI4R_RPF5 2 +#define REFCLKI4R_RPG0 12 +#define REFCLKI4R_RPG7 1 + +#define SDI1R_RPA14 13 +#define SDI1R_RPB5 8 +#define SDI1R_RPB9 5 +#define SDI1R_RPB10 6 +#define SDI1R_RPC1 10 +#define SDI1R_RPC14 7 +#define SDI1R_RPD2 0 +#define SDI1R_RPD6 14 +#define SDI1R_RPD10 3 +#define SDI1R_RPD14 11 +#define SDI1R_RPF1 4 +#define SDI1R_RPF4 2 +#define SDI1R_RPG1 12 +#define SDI1R_RPG8 1 + +#define SDI2R_RPA15 13 +#define SDI2R_RPB1 5 +#define SDI2R_RPB3 8 +#define SDI2R_RPC4 10 +#define SDI2R_RPC13 7 +#define SDI2R_RPD3 0 +#define SDI2R_RPD7 14 +#define SDI2R_RPD11 3 +#define SDI2R_RPD15 11 +#define SDI2R_RPE5 6 +#define SDI2R_RPF0 4 +#define SDI2R_RPF5 2 +#define SDI2R_RPG0 12 +#define SDI2R_RPG7 1 + +#define SDI3R_RPA14 13 +#define SDI3R_RPB5 8 +#define SDI3R_RPB9 5 +#define SDI3R_RPB10 6 +#define SDI3R_RPC1 10 +#define SDI3R_RPC14 7 +#define SDI3R_RPD2 0 +#define SDI3R_RPD10 3 +#define SDI3R_RPD14 11 +#define SDI3R_RPD6 14 +#define SDI3R_RPF1 4 +#define SDI3R_RPF4 2 +#define SDI3R_RPG1 12 +#define SDI3R_RPG8 1 + +#define SDI4R_RPA15 13 +#define SDI4R_RPB1 5 +#define SDI4R_RPB3 8 +#define SDI4R_RPC4 10 +#define SDI4R_RPC13 7 +#define SDI4R_RPD3 0 +#define SDI4R_RPD7 14 +#define SDI4R_RPD11 3 +#define SDI4R_RPD15 11 +#define SDI4R_RPE5 6 +#define SDI4R_RPF0 4 +#define SDI4R_RPF5 2 +#define SDI4R_RPG0 12 +#define SDI4R_RPG7 1 + +#define SDI5R_RPA14 13 +#define SDI5R_RPB5 8 +#define SDI5R_RPB9 5 +#define SDI5R_RPB10 6 +#define SDI5R_RPC1 10 +#define SDI5R_RPC14 7 +#define SDI5R_RPD2 0 +#define SDI5R_RPD6 14 +#define SDI5R_RPD10 3 +#define SDI5R_RPD14 11 +#define SDI5R_RPF1 4 +#define SDI5R_RPF4 2 +#define SDI5R_RPG1 12 +#define SDI5R_RPG8 1 + +#define SDI6R_RPB2 7 +#define SDI6R_RPB6 5 +#define SDI6R_RPB14 2 +#define SDI6R_RPC2 12 +#define SDI6R_RPD0 3 +#define SDI6R_RPD1 0 +#define SDI6R_RPD5 6 +#define SDI6R_RPE8 13 +#define SDI6R_RPF2 11 +#define SDI6R_RPF3 8 +#define SDI6R_RPF13 9 +#define SDI6R_RPG9 1 + +#define SS1R_RPB0 5 +#define SS1R_RPB15 3 +#define SS1R_RPB7 7 +#define SS1R_RPB8 2 +#define SS1R_RPC3 12 +#define SS1R_RPD4 4 +#define SS1R_RPD9 0 +#define SS1R_RPD12 10 +#define SS1R_RPE3 6 +#define SS1R_RPE9 13 +#define SS1R_RPF8 11 +#define SS1R_RPF12 9 +#define SS1R_RPG6 1 + +#define SS2R_RPB2 7 +#define SS2R_RPB6 5 +#define SS2R_RPB14 2 +#define SS2R_RPC2 12 +#define SS2R_RPD0 3 +#define SS2R_RPD1 0 +#define SS2R_RPD5 6 +#define SS2R_RPE8 13 +#define SS2R_RPF2 11 +#define SS2R_RPF3 8 +#define SS2R_RPF13 9 +#define SS2R_RPG9 1 + +#define SS3R_RPB0 5 +#define SS3R_RPB7 7 +#define SS3R_RPB8 2 +#define SS3R_RPB15 3 +#define SS3R_RPC3 12 +#define SS3R_RPD4 4 +#define SS3R_RPD9 0 +#define SS3R_RPD12 10 +#define SS3R_RPE3 6 +#define SS3R_RPE9 13 +#define SS3R_RPF8 11 +#define SS3R_RPF12 9 +#define SS3R_RPG6 1 + +#define SS4R_RPB0 5 +#define SS4R_RPB7 7 +#define SS4R_RPB8 2 +#define SS4R_RPB15 3 +#define SS4R_RPC3 12 +#define SS4R_RPD4 4 +#define SS4R_RPD9 0 +#define SS4R_RPD12 10 +#define SS4R_RPE3 6 +#define SS4R_RPE9 13 +#define SS4R_RPF8 11 +#define SS4R_RPF12 9 +#define SS4R_RPG6 1 + +#define SS5R_RPB0 5 +#define SS5R_RPB7 7 +#define SS5R_RPB8 2 +#define SS5R_RPB15 3 +#define SS5R_RPC3 12 +#define SS5R_RPD4 4 +#define SS5R_RPD9 0 +#define SS5R_RPD12 10 +#define SS5R_RPE3 6 +#define SS5R_RPE9 13 +#define SS5R_RPF12 9 +#define SS5R_RPF8 11 +#define SS5R_RPG6 1 + +#define SS6R_RPA14 13 +#define SS6R_RPB5 8 +#define SS6R_RPB9 5 +#define SS6R_RPB10 6 +#define SS6R_RPC1 10 +#define SS6R_RPC14 7 +#define SS6R_RPD2 0 +#define SS6R_RPD6 14 +#define SS6R_RPD10 3 +#define SS6R_RPD14 11 +#define SS6R_RPF1 4 +#define SS6R_RPF4 2 +#define SS6R_RPG1 12 +#define SS6R_RPG8 1 + +#define T2CKR_RPA14 13 +#define T2CKR_RPB5 8 +#define T2CKR_RPB9 5 +#define T2CKR_RPB10 6 +#define T2CKR_RPC1 10 +#define T2CKR_RPC14 7 +#define T2CKR_RPD2 0 +#define T2CKR_RPD6 14 +#define T2CKR_RPD10 3 +#define T2CKR_RPD14 11 +#define T2CKR_RPF1 4 +#define T2CKR_RPF4 2 +#define T2CKR_RPG1 12 + +#define T2CKR_RPG8 1 +#define T3CKR_RPB0 5 +#define T3CKR_RPB7 7 +#define T3CKR_RPB8 2 +#define T3CKR_RPB15 3 +#define T3CKR_RPC3 12 +#define T3CKR_RPD4 4 +#define T3CKR_RPD9 0 +#define T3CKR_RPD12 10 +#define T3CKR_RPE3 6 +#define T3CKR_RPE9 13 +#define T3CKR_RPF8 11 +#define T3CKR_RPF12 9 +#define T3CKR_RPG6 1 + +#define T4CKR_RPB2 7 +#define T4CKR_RPB6 5 +#define T4CKR_RPB14 2 +#define T4CKR_RPC2 12 +#define T4CKR_RPD0 3 +#define T4CKR_RPD1 0 +#define T4CKR_RPD5 6 +#define T4CKR_RPE8 13 +#define T4CKR_RPF2 11 +#define T4CKR_RPF3 8 +#define T4CKR_RPF13 9 +#define T4CKR_RPG9 1 + +#define T5CKR_RPA15 13 +#define T5CKR_RPB1 5 +#define T5CKR_RPB3 8 +#define T5CKR_RPC4 10 +#define T5CKR_RPC13 7 +#define T5CKR_RPD3 0 +#define T5CKR_RPD7 14 +#define T5CKR_RPD11 3 +#define T5CKR_RPD15 11 +#define T5CKR_RPE5 6 +#define T5CKR_RPF0 4 +#define T5CKR_RPF5 2 +#define T5CKR_RPG0 12 +#define T5CKR_RPG7 1 + +#define T6CKR_RPA14 13 +#define T6CKR_RPB5 8 +#define T6CKR_RPB9 5 +#define T6CKR_RPB10 6 +#define T6CKR_RPC1 10 +#define T6CKR_RPC14 7 +#define T6CKR_RPD2 0 +#define T6CKR_RPD6 14 +#define T6CKR_RPD10 3 +#define T6CKR_RPD14 11 +#define T6CKR_RPF1 4 +#define T6CKR_RPF4 2 +#define T6CKR_RPG1 12 +#define T6CKR_RPG8 1 + +#define T7CKR_RPA15 13 +#define T7CKR_RPB1 5 +#define T7CKR_RPB3 8 +#define T7CKR_RPC4 10 +#define T7CKR_RPC13 7 +#define T7CKR_RPD3 0 +#define T7CKR_RPD7 14 +#define T7CKR_RPD11 3 +#define T7CKR_RPD15 11 +#define T7CKR_RPE5 6 +#define T7CKR_RPF0 4 +#define T7CKR_RPF5 2 +#define T7CKR_RPG0 12 +#define T7CKR_RPG7 1 + +#define T8CKR_RPB0 5 +#define T8CKR_RPB7 7 +#define T8CKR_RPB8 2 +#define T8CKR_RPB15 3 +#define T8CKR_RPC3 12 +#define T8CKR_RPD4 4 +#define T8CKR_RPD9 0 +#define T8CKR_RPD12 10 +#define T8CKR_RPE3 6 +#define T8CKR_RPE9 13 +#define T8CKR_RPF8 11 +#define T8CKR_RPF12 9 +#define T8CKR_RPG6 1 + +#define T9CKR_RPB2 7 +#define T9CKR_RPB6 5 +#define T9CKR_RPB14 2 +#define T9CKR_RPC2 12 +#define T9CKR_RPD0 3 +#define T9CKR_RPD1 0 +#define T9CKR_RPD5 6 +#define T9CKR_RPE8 13 +#define T9CKR_RPF2 11 +#define T9CKR_RPF3 8 +#define T9CKR_RPF13 9 +#define T9CKR_RPG9 1 + +#define U1CTSR_RPB0 5 +#define U1CTSR_RPB7 7 +#define U1CTSR_RPB8 2 +#define U1CTSR_RPB15 3 +#define U1CTSR_RPC3 12 +#define U1CTSR_RPD4 4 +#define U1CTSR_RPD9 0 +#define U1CTSR_RPD12 10 +#define U1CTSR_RPE3 6 +#define U1CTSR_RPE9 13 +#define U1CTSR_RPF8 11 +#define U1CTSR_RPF12 9 +#define U1CTSR_RPG6 1 + +#define U1RXR_RPA14 13 +#define U1RXR_RPB5 8 +#define U1RXR_RPB9 5 +#define U1RXR_RPB10 6 +#define U1RXR_RPC1 10 +#define U1RXR_RPC14 7 +#define U1RXR_RPD2 0 +#define U1RXR_RPD6 14 +#define U1RXR_RPD10 3 +#define U1RXR_RPD14 11 +#define U1RXR_RPF1 4 +#define U1RXR_RPF4 2 +#define U1RXR_RPG1 12 +#define U1RXR_RPG8 1 + +#define U2CTSR_RPA14 13 +#define U2CTSR_RPB5 8 +#define U2CTSR_RPB9 5 +#define U2CTSR_RPB10 6 +#define U2CTSR_RPC1 10 +#define U2CTSR_RPC14 7 +#define U2CTSR_RPD2 0 +#define U2CTSR_RPD6 14 +#define U2CTSR_RPD10 3 +#define U2CTSR_RPD14 11 +#define U2CTSR_RPF1 4 +#define U2CTSR_RPF4 2 +#define U2CTSR_RPG1 12 +#define U2CTSR_RPG8 1 + +#define U2RXR_RPB0 5 +#define U2RXR_RPB7 7 +#define U2RXR_RPB8 2 +#define U2RXR_RPB15 3 +#define U2RXR_RPC3 12 +#define U2RXR_RPD4 4 +#define U2RXR_RPD9 0 +#define U2RXR_RPD12 10 +#define U2RXR_RPE3 6 +#define U2RXR_RPE9 13 +#define U2RXR_RPF8 11 +#define U2RXR_RPF12 9 +#define U2RXR_RPG6 1 + +#define U3CTSR_RPB2 7 +#define U3CTSR_RPB6 5 +#define U3CTSR_RPB14 2 +#define U3CTSR_RPC2 12 +#define U3CTSR_RPD0 3 +#define U3CTSR_RPD1 0 +#define U3CTSR_RPD5 6 +#define U3CTSR_RPE8 13 +#define U3CTSR_RPF2 11 +#define U3CTSR_RPF3 8 +#define U3CTSR_RPF13 9 +#define U3CTSR_RPG9 1 + +#define U3RXR_RPA15 13 +#define U3RXR_RPB1 5 +#define U3RXR_RPB3 8 +#define U3RXR_RPC4 10 +#define U3RXR_RPC13 7 +#define U3RXR_RPD3 0 +#define U3RXR_RPD7 14 +#define U3RXR_RPD11 3 +#define U3RXR_RPD15 11 +#define U3RXR_RPE5 6 +#define U3RXR_RPF0 4 +#define U3RXR_RPF5 2 +#define U3RXR_RPG0 12 +#define U3RXR_RPG7 1 + +#define U4CTSR_RPA15 13 +#define U4CTSR_RPB1 5 +#define U4CTSR_RPB3 8 +#define U4CTSR_RPC4 10 +#define U4CTSR_RPC13 7 +#define U4CTSR_RPD3 0 +#define U4CTSR_RPD7 14 +#define U4CTSR_RPD11 3 +#define U4CTSR_RPD15 11 +#define U4CTSR_RPE5 6 +#define U4CTSR_RPF0 4 +#define U4CTSR_RPF5 2 +#define U4CTSR_RPG0 12 +#define U4CTSR_RPG7 1 + +#define U4RXR_RPB2 7 +#define U4RXR_RPB6 5 +#define U4RXR_RPB14 2 +#define U4RXR_RPC2 12 +#define U4RXR_RPD0 3 +#define U4RXR_RPD1 0 +#define U4RXR_RPD5 6 +#define U4RXR_RPE8 13 +#define U4RXR_RPF2 11 +#define U4RXR_RPF3 8 +#define U4RXR_RPF13 9 +#define U4RXR_RPG9 1 + +#define U5CTSR_RPB0 5 +#define U5CTSR_RPB7 7 +#define U5CTSR_RPB8 2 +#define U5CTSR_RPB15 3 +#define U5CTSR_RPC3 12 +#define U5CTSR_RPD4 4 +#define U5CTSR_RPD9 0 +#define U5CTSR_RPD12 10 +#define U5CTSR_RPE3 6 +#define U5CTSR_RPE9 13 +#define U5CTSR_RPF8 11 +#define U5CTSR_RPF12 9 +#define U5CTSR_RPG6 1 + +#define U5RXR_RPA14 13 +#define U5RXR_RPB5 8 +#define U5RXR_RPB9 5 +#define U5RXR_RPB10 6 +#define U5RXR_RPC1 10 +#define U5RXR_RPC14 7 +#define U5RXR_RPD2 0 +#define U5RXR_RPD6 14 +#define U5RXR_RPD10 3 +#define U5RXR_RPD14 11 +#define U5RXR_RPF1 4 +#define U5RXR_RPF4 2 +#define U5RXR_RPG1 12 +#define U5RXR_RPG8 1 + +#define U6CTSR_RPA14 13 +#define U6CTSR_RPB5 8 +#define U6CTSR_RPB9 5 +#define U6CTSR_RPB10 6 +#define U6CTSR_RPC1 10 +#define U6CTSR_RPC14 7 +#define U6CTSR_RPD2 0 +#define U6CTSR_RPD6 14 +#define U6CTSR_RPD10 3 +#define U6CTSR_RPD14 11 +#define U6CTSR_RPF1 4 +#define U6CTSR_RPF4 2 +#define U6CTSR_RPG1 12 +#define U6CTSR_RPG8 1 + +#define U6RXR_RPB2 7 +#define U6RXR_RPB6 5 +#define U6RXR_RPB14 2 +#define U6RXR_RPC2 12 +#define U6RXR_RPD0 3 +#define U6RXR_RPD1 0 +#define U6RXR_RPD5 6 +#define U6RXR_RPE8 13 +#define U6RXR_RPF2 11 +#define U6RXR_RPF3 8 +#define U6RXR_RPF13 9 +#define U6RXR_RPG9 1 + +/* Output Pin Selection *********************************************************************/ +/* The encoding of the output pin selection is a little more complex. Knowing the device + * does not provide sufficient information. So the following definitions include both the + * register value and the register address. + */ + +#define C1OUT_RPB0R 14, PI32MZ_RPB0R +#define C1OUT_RPB7R 14, PI32MZ_RPB7R +#define C1OUT_RPB8R 14, PI32MZ_RPB8R +#define C1OUT_RPB15R 14, PI32MZ_RPB15R +#define C1OUT_RPC3R 14, PI32MZ_RPC3R +#define C1OUT_RPD4R 14, PI32MZ_RPD4R +#define C1OUT_RPD9R 14, PI32MZ_RPD9R +#define C1OUT_RPD12R 14, PI32MZ_RPD12R +#define C1OUT_RPE3R 14, PI32MZ_RPE3R +#define C1OUT_RPE9R 14, PI32MZ_RPE9R +#define C1OUT_RPF8R 14, PI32MZ_RPF8R +#define C1OUT_RPF12R 14, PI32MZ_RPF12R +#define C1OUT_RPG6R 14, PI32MZ_RPG6R + +#define C1TX_RPA14R 15, PI32MZ_RPA14R +#define C1TX_RPB5R 15, PI32MZ_RPB5R +#define C1TX_RPB9R 15, PI32MZ_RPB9R +#define C1TX_RPB10R 15, PI32MZ_RPB10R +#define C1TX_RPC1R 15, PI32MZ_RPC1R +#define C1TX_RPC14R 15, PI32MZ_RPC14R +#define C1TX_RPD2R 15, PI32MZ_RPD2R +#define C1TX_RPD6R 15, PI32MZ_RPD6R +#define C1TX_RPD10R 15, PI32MZ_RPD10R +#define C1TX_RPD14R 15, PI32MZ_RPD14R +#define C1TX_RPF1R 15, PI32MZ_RPF1R +#define C1TX_RPF4R 15, PI32MZ_RPF4R +#define C1TX_RPG1R 15, PI32MZ_RPG1R +#define C1TX_RPG8R 15, PI32MZ_RPG8R + +#define C2OUT_RPA14R 14, PI32MZ_RPA14R +#define C2OUT_RPB5R 14, PI32MZ_RPB5R +#define C2OUT_RPB9R 14, PI32MZ_RPB9R +#define C2OUT_RPB10R 14, PI32MZ_RPB10R +#define C2OUT_RPC1R 14, PI32MZ_RPC1R +#define C2OUT_RPC14R 14, PI32MZ_RPC14R +#define C2OUT_RPD2R 14, PI32MZ_RPD2R +#define C2OUT_RPD6R 14, PI32MZ_RPD6R +#define C2OUT_RPD10R 14, PI32MZ_RPD10R +#define C2OUT_RPD14R 14, PI32MZ_RPD14R +#define C2OUT_RPF1R 14, PI32MZ_RPF1R +#define C2OUT_RPF4R 14, PI32MZ_RPF4R +#define C2OUT_RPG1R 14, PI32MZ_RPG1R +#define C2OUT_RPG8R 14, PI32MZ_RPG8R + +#define C2TX_RPB2R 15, PI32MZ_RPB2R +#define C2TX_RPB6R 15, PI32MZ_RPB6R +#define C2TX_RPB14R 15, PI32MZ_RPB14R +#define C2TX_RPC2R 15, PI32MZ_RPC2R +#define C2TX_RPD0R 15, PI32MZ_RPD0R +#define C2TX_RPD1R 15, PI32MZ_RPD1R +#define C2TX_RPD5R 15, PI32MZ_RPD5R +#define C2TX_RPE8R 15, PI32MZ_RPE8R +#define C2TX_RPF2R 15, PI32MZ_RPF2R +#define C2TX_RPF3R 15, PI32MZ_RPF3R +#define C2TX_RPF13R 15, PI32MZ_RPF13R +#define C2TX_RPG9R 15, PI32MZ_RPG9R + +#define OC1_RPB2R 12, PI32MZ_RPB2R +#define OC1_RPB6R 12, PI32MZ_RPB6R +#define OC1_RPB14R 12, PI32MZ_RPB14R +#define OC1_RPC2R 12, PI32MZ_RPC2R +#define OC1_RPD0R 12, PI32MZ_RPD0R +#define OC1_RPD1R 12, PI32MZ_RPD1R +#define OC1_RPD5R 12, PI32MZ_RPD5R +#define OC1_RPE8R 12, PI32MZ_RPE8R +#define OC1_RPF2R 12, PI32MZ_RPF2R +#define OC1_RPF3R 12, PI32MZ_RPF3R +#define OC1_RPF13R 12, PI32MZ_RPF13R +#define OC1_RPG9R 12, PI32MZ_RPG9R + +#define OC2_RPB2R 11, PI32MZ_RPB2R +#define OC2_RPB6R 11, PI32MZ_RPB6R +#define OC2_RPB14R 11, PI32MZ_RPB14R +#define OC2_RPC2R 11, PI32MZ_RPC2R +#define OC2_RPD0R 11, PI32MZ_RPD0R +#define OC2_RPD1R 11, PI32MZ_RPD1R +#define OC2_RPD5R 11, PI32MZ_RPD5R +#define OC2_RPE8R 11, PI32MZ_RPE8R +#define OC2_RPF2R 11, PI32MZ_RPF2R +#define OC2_RPF3R 11, PI32MZ_RPF3R +#define OC2_RPF13R 11, PI32MZ_RPF13R +#define OC2_RPG9R 11, PI32MZ_RPG9R + +#define OC3_RPA14R 11, PI32MZ_RPA14R +#define OC3_RPB5R 11, PI32MZ_RPB5R +#define OC3_RPB9R 11, PI32MZ_RPB9R +#define OC3_RPB10R 11, PI32MZ_RPB10R +#define OC3_RPC1R 11, PI32MZ_RPC1R +#define OC3_RPC14R 11, PI32MZ_RPC14R +#define OC3_RPD2R 11, PI32MZ_RPD2R +#define OC3_RPD6R 11, PI32MZ_RPD6R +#define OC3_RPD10R 11, PI32MZ_RPD10R +#define OC3_RPD14R 11, PI32MZ_RPD14R +#define OC3_RPF1R 11, PI32MZ_RPF1R +#define OC3_RPF4R 11, PI32MZ_RPF4R +#define OC3_RPG1R 11, PI32MZ_RPG1R +#define OC3_RPG8R 11, PIC32MZ_RPG8R + +#define OC4_RPA15R 11, PIC32MZ_RPA15R +#define OC4_RPB1R 11, PIC32MZ_RPB1R +#define OC4_RPB3R 11, PIC32MZ_RPB3R +#define OC4_RPC4R 11, PIC32MZ_RPC4R +#define OC4_RPC13R 11, PIC32MZ_RPC13R +#define OC4_RPD3R 11, PIC32MZ_RPD3R +#define OC4_RPD7R 11, PIC32MZ_RPD7R +#define OC4_RPD11R 11, PIC32MZ_RPD11R +#define OC4_RPD15R 11, PIC32MZ_RPD15R +#define OC4_RPE5R 11, PIC32MZ_RPE5R +#define OC4_RPF0R 11, PIC32MZ_RPF0R +#define OC4_RPF5R 11, PIC32MZ_RPF5R +#define OC4_RPG0R 11, PIC32MZ_RPG0R +#define OC4_RPG7R 11, PIC32MZ_RPG7R + +#define OC5_RPB0R 11, PIC32MZ_RPB0R +#define OC5_RPB7R 11, PIC32MZ_RPB7R +#define OC5_RPB8R 11, PIC32MZ_RPB8R +#define OC5_RPB15R 11, PIC32MZ_RPB15R +#define OC5_RPC3R 11, PIC32MZ_RPC3R +#define OC5_RPD4R 11, PIC32MZ_RPD4R +#define OC5_RPD9R 11, PIC32MZ_RPD9R +#define OC5_RPD12R 11, PIC32MZ_RPD12R +#define OC5_RPE3R 11, PIC32MZ_RPE3R +#define OC5_RPE9R 11, PIC32MZ_RPE9R +#define OC5_RPF8R 11, PIC32MZ_RPF8R +#define OC5_RPF12R 11, PIC32MZ_RPF12R +#define OC5_RPG6R 11, PIC32MZ_RPG6R + +#define OC6_RPA14R 12, PIC32MZ_RPA14R +#define OC6_RPB5R 12, PIC32MZ_RPB5R +#define OC6_RPB9R 12, PIC32MZ_RPB9R +#define OC6_RPB10R 12, PIC32MZ_RPB10R +#define OC6_RPC1R 12, PIC32MZ_RPC1R +#define OC6_RPC14R 12, PIC32MZ_RPC14R +#define OC6_RPD2R 12, PIC32MZ_RPD2R +#define OC6_RPD6R 12, PIC32MZ_RPD6R +#define OC6_RPD10R 12, PIC32MZ_RPD10R +#define OC6_RPD14R 12, PIC32MZ_RPD14R +#define OC6_RPF1R 12, PIC32MZ_RPF1R +#define OC6_RPF4R 12, PIC32MZ_RPF4R +#define OC6_RPG1R 12, PIC32MZ_RPG1R +#define OC6_RPG8R 12, PIC32MZ_RPG8R + +#define OC7_RPA15R 12, PIC32MZ_RPA15R +#define OC7_RPB1R 12, PIC32MZ_RPB1R +#define OC7_RPB3R 12, PIC32MZ_RPB3R +#define OC7_RPC4R 12, PIC32MZ_RPC4R +#define OC7_RPC13R 12, PIC32MZ_RPC13R +#define OC7_RPD3R 12, PIC32MZ_RPD3R +#define OC7_RPD7R 12, PIC32MZ_RPD7R +#define OC7_RPD11R 12, PIC32MZ_RPD11R +#define OC7_RPD15R 12, PIC32MZ_RPD15R +#define OC7_RPE5R 12, PIC32MZ_RPE5R +#define OC7_RPF0R 12, PIC32MZ_RPF0R +#define OC7_RPF5R 12, PIC32MZ_RPF5R +#define OC7_RPG0R 12, PIC32MZ_RPG0R +#define OC7_RPG7R 12, PIC32MZ_RPG7R + +#define OC8_RPB0R 12, PIC32MZ_RPB0R +#define OC8_RPB7R 12, PIC32MZ_RPB7R +#define OC8_RPB8R 12, PIC32MZ_RPB8R +#define OC8_RPB15R 12, PIC32MZ_RPB15R +#define OC8_RPC3R 12, PIC32MZ_RPC3R +#define OC8_RPD4R 12, PIC32MZ_RPD4R +#define OC8_RPD9R 12, PIC32MZ_RPD9R +#define OC8_RPD12R 12, PIC32MZ_RPD12R +#define OC8_RPE3R 12, PIC32MZ_RPE3R +#define OC8_RPE9R 12, PIC32MZ_RPE9R +#define OC8_RPF8R 12, PIC32MZ_RPF8R +#define OC8_RPF12R 12, PIC32MZ_RPF12R +#define OC8_RPG6R 12, PIC32MZ_RPG6R + +#define OC9_RPB2R 13, PIC32MZ_RPB2R +#define OC9_RPB6R 13, PIC32MZ_RPB6R +#define OC9_RPB14R 13, PIC32MZ_RPB14R +#define OC9_RPC2R 13, PIC32MZ_RPC2R +#define OC9_RPD0R 13, PIC32MZ_RPD0R +#define OC9_RPD1R 13, PIC32MZ_RPD1R +#define OC9_RPD5R 13, PIC32MZ_RPD5R +#define OC9_RPE8R 13, PIC32MZ_RPE8R +#define OC9_RPF2R 13, PIC32MZ_RPF2R +#define OC9_RPF3R 13, PIC32MZ_RPF3R +#define OC9_RPF13R 13, PIC32MZ_RPF13R +#define OC9_RPG9R 13, PIC32MZ_RPG9R + +#define REFCLKO1_RPA15R 15, PIC32MZ_RPA15R +#define REFCLKO1_RPB1R 15, PIC32MZ_RPB1R +#define REFCLKO1_RPB3R 15, PIC32MZ_RPB3R +#define REFCLKO1_RPC4R 15, PIC32MZ_RPC4R +#define REFCLKO1_RPC13R 15, PIC32MZ_RPC13R +#define REFCLKO1_RPD3R 15, PIC32MZ_RPD3R +#define REFCLKO1_RPD7R 15, PIC32MZ_RPD7R +#define REFCLKO1_RPD11R 15, PIC32MZ_RPD11R +#define REFCLKO1_RPD15R 15, PIC32MZ_RPD15R +#define REFCLKO1_RPE5R 15, PIC32MZ_RPE5R +#define REFCLKO1_RPF0R 15, PIC32MZ_RPF0R +#define REFCLKO1_RPF5R 15, PIC32MZ_RPF5R +#define REFCLKO1_RPG0R 15, PIC32MZ_RPG0R +#define REFCLKO1_RPG7R 15, PIC32MZ_RPG7R + +#define REFCLKO3_RPG6R 15, PIC32MZ_RPG6R +#define REFCLKO3_RPB0R 15, PIC32MZ_RPB0R +#define REFCLKO3_RPB7R 15, PIC32MZ_RPB7R +#define REFCLKO3_RPB8R 15, PIC32MZ_RPB8R +#define REFCLKO3_RPB15R 15, PIC32MZ_RPB15R +#define REFCLKO3_RPC3R 15, PIC32MZ_RPC3R +#define REFCLKO3_RPD4R 15, PIC32MZ_RPD4R +#define REFCLKO3_RPD9R 15, PIC32MZ_RPD9R +#define REFCLKO3_RPD12R 15, PIC32MZ_RPD12R +#define REFCLKO3_RPE3R 15, PIC32MZ_RPE3R +#define REFCLKO3_RPE9R 15, PIC32MZ_RPE9R +#define REFCLKO3_RPF8R 15, PIC32MZ_RPF8R +#define REFCLKO3_RPF12R 15, PIC32MZ_RPF12R + +#define REFCLKO4_RPA14R 13, PIC32MZ_RPA14R +#define REFCLKO4_RPB5R 13, PIC32MZ_RPB5R +#define REFCLKO4_RPB9R 13, PIC32MZ_RPB9R +#define REFCLKO4_RPB10R 13, PIC32MZ_RPB10R +#define REFCLKO4_RPC1R 13, PIC32MZ_RPC1R +#define REFCLKO4_RPC14R 13, PIC32MZ_RPC14R +#define REFCLKO4_RPD2R 13, PIC32MZ_RPD2R +#define REFCLKO4_RPD6R 13, PIC32MZ_RPD6R +#define REFCLKO4_RPD10R 13, PIC32MZ_RPD10R +#define REFCLKO4_RPD14R 13, PIC32MZ_RPD14R +#define REFCLKO4_RPF1R 13, PIC32MZ_RPF1R +#define REFCLKO4_RPF4R 13, PIC32MZ_RPF4R +#define REFCLKO4_RPG1R 13, PIC32MZ_RPG1R +#define REFCLKO4_RPG8R 13, PIC32MZ_RPG8R + +#define SDO1_RPA14R 5, PIC32MZ_RPA14R +#define SDO1_RPA15R 5, PIC32MZ_RPA15R +#define SDO1_RPB1R 5, PIC32MZ_RPB1R +#define SDO1_RPB3R 5, PIC32MZ_RPB3R +#define SDO1_RPB5R 5, PIC32MZ_RPB5R +#define SDO1_RPB9R 5, PIC32MZ_RPB9R +#define SDO1_RPB10R 5, PIC32MZ_RPB10R +#define SDO1_RPC1R 5, PIC32MZ_RPC1R +#define SDO1_RPC4R 5, PIC32MZ_RPC4R +#define SDO1_RPC13R 5, PIC32MZ_RPC13R +#define SDO1_RPC14R 5, PIC32MZ_RPC14R +#define SDO1_RPD2R 5, PIC32MZ_RPD2R +#define SDO1_RPD3R 5, PIC32MZ_RPD3R +#define SDO1_RPD6R 5, PIC32MZ_RPD6R +#define SDO1_RPD7R 5, PIC32MZ_RPD7R +#define SDO1_RPD10R 5, PIC32MZ_RPD10R +#define SDO1_RPD11R 5, PIC32MZ_RPD11R +#define SDO1_RPD14R 5, PIC32MZ_RPD14R +#define SDO1_RPD15R 5, PIC32MZ_RPD15R +#define SDO1_RPE5R 5, PIC32MZ_RPE5R +#define SDO1_RPF0R 5, PIC32MZ_RPF0R +#define SDO1_RPF1R 5, PIC32MZ_RPF1R +#define SDO1_RPF4R 5, PIC32MZ_RPF4R +#define SDO1_RPF5R 5, PIC32MZ_RPF5R +#define SDO1_RPG0R 5, PIC32MZ_RPG0R +#define SDO1_RPG1R 5, PIC32MZ_RPG1R +#define SDO1_RPG7R 5, PIC32MZ_RPG7R +#define SDO1_RPG8R 5, PIC32MZ_RPG8R + +#define SDO2_RPA14R 6, PIC32MZ_RPA14R +#define SDO2_RPA15R 6, PIC32MZ_RPA15R +#define SDO2_RPB1R 6, PIC32MZ_RPB1R +#define SDO2_RPB3R 6, PIC32MZ_RPB3R +#define SDO2_RPB5R 6, PIC32MZ_RPB5R +#define SDO2_RPB9R 6, PIC32MZ_RPB9R +#define SDO2_RPB10R 6, PIC32MZ_RPB10R +#define SDO2_RPC1R 6, PIC32MZ_RPC1R +#define SDO2_RPC4R 6, PIC32MZ_RPC4R +#define SDO2_RPC13R 6, PIC32MZ_RPC13R +#define SDO2_RPC14R 6, PIC32MZ_RPC14R +#define SDO2_RPD2R 6, PIC32MZ_RPD2R +#define SDO2_RPD3R 6, PIC32MZ_RPD3R +#define SDO2_RPD6R 6, PIC32MZ_RPD6R +#define SDO2_RPD7R 6, PIC32MZ_RPD7R +#define SDO2_RPD10R 6, PIC32MZ_RPD10R +#define SDO2_RPD11R 6, PIC32MZ_RPD11R +#define SDO2_RPD14R 6, PIC32MZ_RPD14R +#define SDO2_RPD15R 6, PIC32MZ_RPD15R +#define SDO2_RPE5R 6, PIC32MZ_RPE5R +#define SDO2_RPF0R 6, PIC32MZ_RPF0R +#define SDO2_RPF1R 6, PIC32MZ_RPF1R +#define SDO2_RPF4R 6, PIC32MZ_RPF4R +#define SDO2_RPF5R 6, PIC32MZ_RPF5R +#define SDO2_RPG0R 6, PIC32MZ_RPG0R +#define SDO2_RPG1R 6, PIC32MZ_RPG1R +#define SDO2_RPG7R 6, PIC32MZ_RPG7R +#define SDO2_RPG8R 6, PIC32MZ_RPG8R + +#define SDO3_RPA14R 7, PIC32MZ_RPA14R +#define SDO3_RPA15R 7, PIC32MZ_RPA15R +#define SDO3_RPB1R 7, PIC32MZ_RPB1R +#define SDO3_RPB3R 7, PIC32MZ_RPB3R +#define SDO3_RPB5R 7, PIC32MZ_RPB5R +#define SDO3_RPB9R 7, PIC32MZ_RPB9R +#define SDO3_RPB10R 7, PIC32MZ_RPB10R +#define SDO3_RPC1R 7, PIC32MZ_RPC1R +#define SDO3_RPC4R 7, PIC32MZ_RPC4R +#define SDO3_RPC13R 7, PIC32MZ_RPC13R +#define SDO3_RPC14R 7, PIC32MZ_RPC14R +#define SDO3_RPD2R 7, PIC32MZ_RPD2R +#define SDO3_RPD3R 7, PIC32MZ_RPD3R +#define SDO3_RPD6R 7, PIC32MZ_RPD6R +#define SDO3_RPD7R 7, PIC32MZ_RPD7R +#define SDO3_RPD10R 7, PIC32MZ_RPD10R +#define SDO3_RPD11R 7, PIC32MZ_RPD11R +#define SDO3_RPD14R 7, PIC32MZ_RPD14R +#define SDO3_RPD15R 7, PIC32MZ_RPD15R +#define SDO3_RPE5R 7, PIC32MZ_RPE5R +#define SDO3_RPF0R 7, PIC32MZ_RPF0R +#define SDO3_RPF1R 7, PIC32MZ_RPF1R +#define SDO3_RPF4R 7, PIC32MZ_RPF4R +#define SDO3_RPF5R 7, PIC32MZ_RPF5R +#define SDO3_RPG0R 7, PIC32MZ_RPG0R +#define SDO3_RPG1R 7, PIC32MZ_RPG1R +#define SDO3_RPG7R 7, PIC32MZ_RPG7R +#define SDO3_RPG8R 7, PIC32MZ_RPG8R + +#define SDO4_RPA15R 8, PIC32MZ_RPA15R +#define SDO4_RPB1R 8, PIC32MZ_RPB1R +#define SDO4_RPB2R 8, PIC32MZ_RPB2R +#define SDO4_RPB3R 8, PIC32MZ_RPB3R +#define SDO4_RPB6R 8, PIC32MZ_RPB6R +#define SDO4_RPB14R 8, PIC32MZ_RPB14R +#define SDO4_RPC2R 8, PIC32MZ_RPC2R +#define SDO4_RPC4R 8, PIC32MZ_RPC4R +#define SDO4_RPC13R 8, PIC32MZ_RPC13R +#define SDO4_RPD0R 8, PIC32MZ_RPD0R +#define SDO4_RPD1R 8, PIC32MZ_RPD1R +#define SDO4_RPD3R 8, PIC32MZ_RPD3R +#define SDO4_RPD5R 8, PIC32MZ_RPD5R +#define SDO4_RPD7R 8, PIC32MZ_RPD7R +#define SDO4_RPD11R 8, PIC32MZ_RPD11R +#define SDO4_RPD15R 8, PIC32MZ_RPD15R +#define SDO4_RPE5R 8, PIC32MZ_RPE5R +#define SDO4_RPE8R 8, PIC32MZ_RPE8R +#define SDO4_RPF0R 8, PIC32MZ_RPF0R +#define SDO4_RPF2R 8, PIC32MZ_RPF2R +#define SDO4_RPF3R 8, PIC32MZ_RPF3R +#define SDO4_RPF5R 8, PIC32MZ_RPF5R +#define SDO4_RPF13R 8, PIC32MZ_RPF13R +#define SDO4_RPG0R 8, PIC32MZ_RPG0R +#define SDO4_RPG7R 8, PIC32MZ_RPG7R +#define SDO4_RPG9R 8, PIC32MZ_RPG9R + +#define SDO5_RPA14R 9, PIC32MZ_RPA14R +#define SDO5_RPA15R 9, PIC32MZ_RPA15R +#define SDO5_RPB1R 9, PIC32MZ_RPB1R +#define SDO5_RPB3R 9, PIC32MZ_RPB3R +#define SDO5_RPB5R 9, PIC32MZ_RPB5R +#define SDO5_RPB9R 9, PIC32MZ_RPB9R +#define SDO5_RPB10R 9, PIC32MZ_RPB10R +#define SDO5_RPC1R 9, PIC32MZ_RPC1R +#define SDO5_RPC4R 9, PIC32MZ_RPC4R +#define SDO5_RPC13R 9, PIC32MZ_RPC13R +#define SDO5_RPC14R 9, PIC32MZ_RPC14R +#define SDO5_RPD2R 9, PIC32MZ_RPD2R +#define SDO5_RPD3R 9, PIC32MZ_RPD3R +#define SDO5_RPD6R 9, PIC32MZ_RPD6R +#define SDO5_RPD7R 9, PIC32MZ_RPD7R +#define SDO5_RPD10R 9, PIC32MZ_RPD10R +#define SDO5_RPD11R 9, PIC32MZ_RPD11R +#define SDO5_RPD14R 9, PIC32MZ_RPD14R +#define SDO5_RPD15R 9, PIC32MZ_RPD15R +#define SDO5_RPE5R 9, PIC32MZ_RPE5R +#define SDO5_RPF0R 9, PIC32MZ_RPF0R +#define SDO5_RPF1R 9, PIC32MZ_RPF1R +#define SDO5_RPF4R 9, PIC32MZ_RPF4R +#define SDO5_RPF5R 9, PIC32MZ_RPF5R +#define SDO5_RPG0R 9, PIC32MZ_RPG0R +#define SDO5_RPG1R 9, PIC32MZ_RPG1R +#define SDO5_RPG7R 9, PIC32MZ_RPG7R +#define SDO5_RPG8R 9, PIC32MZ_RPG8R + +#define SDO6_RPB0R 10, PIC32MZ_RPB0R +#define SDO6_RPB2R 10, PIC32MZ_RPB2R +#define SDO6_RPB6R 10, PIC32MZ_RPB6R +#define SDO6_RPB7R 10, PIC32MZ_RPB7R +#define SDO6_RPB8R 10, PIC32MZ_RPB8R +#define SDO6_RPB14R 10, PIC32MZ_RPB14R +#define SDO6_RPB15R 10, PIC32MZ_RPB15R +#define SDO6_RPC2R 10, PIC32MZ_RPC2R +#define SDO6_RPC3R 10, PIC32MZ_RPC3R +#define SDO6_RPD0R 10, PIC32MZ_RPD0R +#define SDO6_RPD1R 10, PIC32MZ_RPD1R +#define SDO6_RPD4R 10, PIC32MZ_RPD4R +#define SDO6_RPD5R 10, PIC32MZ_RPD5R +#define SDO6_RPD9R 10, PIC32MZ_RPD9R +#define SDO6_RPD12R 10, PIC32MZ_RPD12R +#define SDO6_RPE3R 10, PIC32MZ_RPE3R +#define SDO6_RPE8R 10, PIC32MZ_RPE8R +#define SDO6_RPE9R 10, PIC32MZ_RPE9R +#define SDO6_RPF2R 10, PIC32MZ_RPF2R +#define SDO6_RPF3R 10, PIC32MZ_RPF3R +#define SDO6_RPF8R 10, PIC32MZ_RPF8R +#define SDO6_RPF12R 10, PIC32MZ_RPF12R +#define SDO6_RPF13R 10, PIC32MZ_RPF13R +#define SDO6_RPG6R 10, PIC32MZ_RPG6R +#define SDO6_RPG9R 10, PIC32MZ_RPG9R + +#define SS1_RPB0R 5, PIC32MZ_RPB0R +#define SS1_RPB7R 5, PIC32MZ_RPB7R +#define SS1_RPB8R 5, PIC32MZ_RPB8R +#define SS1_RPB15R 5, PIC32MZ_RPB15R +#define SS1_RPC3R 5, PIC32MZ_RPC3R +#define SS1_RPD4R 5, PIC32MZ_RPD4R +#define SS1_RPD9R 5, PIC32MZ_RPD9R +#define SS1_RPD12R 5, PIC32MZ_RPD12R +#define SS1_RPE3R 5, PIC32MZ_RPE3R +#define SS1_RPE9R 5, PIC32MZ_RPE9R +#define SS1_RPF8R 5, PIC32MZ_RPF8R +#define SS1_RPF12R 5, PIC32MZ_RPF12R +#define SS1_RPG6R 5, PIC32MZ_RPG6R + +#define SS2_RPB2R 6, PIC32MZ_RPB2R +#define SS2_RPB6R 6, PIC32MZ_RPB6R +#define SS2_RPB14R 6, PIC32MZ_RPB14R +#define SS2_RPC2R 6, PIC32MZ_RPC2R +#define SS2_RPD0R 6, PIC32MZ_RPD0R +#define SS2_RPD1R 6, PIC32MZ_RPD1R +#define SS2_RPD5R 6, PIC32MZ_RPD5R +#define SS2_RPE8R 6, PIC32MZ_RPE8R +#define SS2_RPF2R 6, PIC32MZ_RPF2R +#define SS2_RPF3R 6, PIC32MZ_RPF3R +#define SS2_RPF13R 6, PIC32MZ_RPF13R +#define SS2_RPG9R 6, PIC32MZ_RPG9R + +#define SS3_RPB0R 7, PIC32MZ_RPB0R +#define SS3_RPB7R 7, PIC32MZ_RPB7R +#define SS3_RPB8R 7, PIC32MZ_RPB8R +#define SS3_RPB15R 7, PIC32MZ_RPB15R +#define SS3_RPC3R 7, PIC32MZ_RPC3R +#define SS3_RPD4R 7, PIC32MZ_RPD4R +#define SS3_RPD9R 7, PIC32MZ_RPD9R +#define SS3_RPD12R 7, PIC32MZ_RPD12R +#define SS3_RPE3R 7, PIC32MZ_RPE3R +#define SS3_RPE9R 7, PIC32MZ_RPE9R +#define SS3_RPF8R 7, PIC32MZ_RPF8R +#define SS3_RPF12R 7, PIC32MZ_RPF12R +#define SS3_RPG6R 7, PIC32MZ_RPG6R + +#define SS4_RPB0R 8, PIC32MZ_RPB0R +#define SS4_RPB7R 8, PIC32MZ_RPB7R +#define SS4_RPB8R 8, PIC32MZ_RPB8R +#define SS4_RPB15R 8, PIC32MZ_RPB15R +#define SS4_RPC3R 8, PIC32MZ_RPC3R +#define SS4_RPD4R 8, PIC32MZ_RPD4R +#define SS4_RPD9R 8, PIC32MZ_RPD9R +#define SS4_RPD12R 8, PIC32MZ_RPD12R +#define SS4_RPE3R 8, PIC32MZ_RPE3R +#define SS4_RPE9R 8, PIC32MZ_RPE9R +#define SS4_RPF8R 8, PIC32MZ_RPF8R +#define SS4_RPF12R 8, PIC32MZ_RPF12R +#define SS4_RPG6R 8, PIC32MZ_RPG6R + +#define SS5_RPB0R 9, PIC32MZ_RPB0R +#define SS5_RPB7R 9, PIC32MZ_RPB7R +#define SS5_RPB8R 9, PIC32MZ_RPB8R +#define SS5_RPB15R 9, PIC32MZ_RPB15R +#define SS5_RPC3R 9, PIC32MZ_RPC3R +#define SS5_RPD4R 9, PIC32MZ_RPD4R +#define SS5_RPD9R 9, PIC32MZ_RPD9R +#define SS5_RPD12R 9, PIC32MZ_RPD12R +#define SS5_RPE3R 9, PIC32MZ_RPE3R +#define SS5_RPE9R 9, PIC32MZ_RPE9R +#define SS5_RPF8R 9, PIC32MZ_RPF8R +#define SS5_RPF12R 9, PIC32MZ_RPF12R +#define SS5_RPG6R 9, PIC32MZ_RPG6R + +#define SS6_RPA14R 10, PIC32MZ_RPA14R +#define SS6_RPB5R 10, PIC32MZ_RPB5R +#define SS6_RPB9R 10, PIC32MZ_RPB9R +#define SS6_RPB10R 10, PIC32MZ_RPB10R +#define SS6_RPC1R 10, PIC32MZ_RPC1R +#define SS6_RPC14R 10, PIC32MZ_RPC14R +#define SS6_RPD2R 10, PIC32MZ_RPD2R +#define SS6_RPD6R 10, PIC32MZ_RPD6R +#define SS6_RPD10R 10, PIC32MZ_RPD10R +#define SS6_RPD14R 10, PIC32MZ_RPD14R +#define SS6_RPF1R 10, PIC32MZ_RPF1R +#define SS6_RPF4R 10, PIC32MZ_RPF4R +#define SS6_RPG1R 10, PIC32MZ_RPG1R +#define SS6_RPG8R 10, PIC32MZ_RPG8R + +#define U1RTS_RPB2R 1, PIC32MZ_RPB2R +#define U1RTS_RPB6R 1, PIC32MZ_RPB6R +#define U1RTS_RPB14R 1, PIC32MZ_RPB14R +#define U1RTS_RPC2R 1, PIC32MZ_RPC2R +#define U1RTS_RPD0R 1, PIC32MZ_RPD0R +#define U1RTS_RPD1R 1, PIC32MZ_RPD1R +#define U1RTS_RPD5R 1, PIC32MZ_RPD5R +#define U1RTS_RPE8R 1, PIC32MZ_RPE8R +#define U1RTS_RPF2R 1, PIC32MZ_RPF2R +#define U1RTS_RPF3R 1, PIC32MZ_RPF3R +#define U1RTS_RPF13R 1, PIC32MZ_RPF13R +#define U1RTS_RPG9R 1, PIC32MZ_RPG9R + +#define U1TX_RPA15R 1, PIC32MZ_RPA15R +#define U1TX_RPB1R 1, PIC32MZ_RPB1R +#define U1TX_RPB3R 1, PIC32MZ_RPB3R +#define U1TX_RPC4R 1, PIC32MZ_RPC4R +#define U1TX_RPC13R 1, PIC32MZ_RPC13R +#define U1TX_RPD3R 1, PIC32MZ_RPD3R +#define U1TX_RPD7R 1, PIC32MZ_RPD7R +#define U1TX_RPD11R 1, PIC32MZ_RPD11R +#define U1TX_RPD15R 1, PIC32MZ_RPD15R +#define U1TX_RPE5R 1, PIC32MZ_RPE5R +#define U1TX_RPF0R 1, PIC32MZ_RPF0R +#define U1TX_RPF5R 1, PIC32MZ_RPF5R +#define U1TX_RPG0R 1, PIC32MZ_RPG0R +#define U1TX_RPG7R 1, PIC32MZ_RPG7R + +#define U2RTS_RPA15R 2, PIC32MZ_RPA15R +#define U2RTS_RPB1R 2, PIC32MZ_RPB1R +#define U2RTS_RPB3R 2, PIC32MZ_RPB3R +#define U2RTS_RPC4R 2, PIC32MZ_RPC4R +#define U2RTS_RPC13R 2, PIC32MZ_RPC13R +#define U2RTS_RPD3R 2, PIC32MZ_RPD3R +#define U2RTS_RPD7R 2, PIC32MZ_RPD7R +#define U2RTS_RPD11R 2, PIC32MZ_RPD11R +#define U2RTS_RPD15R 2, PIC32MZ_RPD15R +#define U2RTS_RPE5R 2, PIC32MZ_RPE5R +#define U2RTS_RPF0R 2, PIC32MZ_RPF0R +#define U2RTS_RPF5R 2, PIC32MZ_RPF5R +#define U2RTS_RPG0R 2, PIC32MZ_RPG0R +#define U2RTS_RPG7R 2, PIC32MZ_RPG7R + +#define U2TX_RPB2R 2, PIC32MZ_RPB2R +#define U2TX_RPB6R 2, PIC32MZ_RPB6R +#define U2TX_RPB14R 2, PIC32MZ_RPB14R +#define U2TX_RPC2R 2, PIC32MZ_RPC2R +#define U2TX_RPD0R 2, PIC32MZ_RPD0R +#define U2TX_RPD1R 2, PIC32MZ_RPD1R +#define U2TX_RPD5R 2, PIC32MZ_RPD5R +#define U2TX_RPE8R 2, PIC32MZ_RPE8R +#define U2TX_RPF2R 2, PIC32MZ_RPF2R +#define U2TX_RPF3R 2, PIC32MZ_RPF3R +#define U2TX_RPF13R 2, PIC32MZ_RPF13R +#define U2TX_RPG9R 2, PIC32MZ_RPG9R + +#define U3RTS_RPB0R 1, PIC32MZ_RPB0R +#define U3RTS_RPB7R 1, PIC32MZ_RPB7R +#define U3RTS_RPB8R 1, PIC32MZ_RPB8R +#define U3RTS_RPB15R 1, PIC32MZ_RPB15R +#define U3RTS_RPC3R 1, PIC32MZ_RPC3R +#define U3RTS_RPD4R 1, PIC32MZ_RPD4R +#define U3RTS_RPD9R 1, PIC32MZ_RPD9R +#define U3RTS_RPD12R 1, PIC32MZ_RPD12R +#define U3RTS_RPE3R 1, PIC32MZ_RPE3R +#define U3RTS_RPE9R 1, PIC32MZ_RPE9R +#define U3RTS_RPF8R 1, PIC32MZ_RPF8R +#define U3RTS_RPF12R 1, PIC32MZ_RPF12R +#define U3RTS_RPG6R 1, PIC32MZ_RPG6R + +#define U3TX_RPA14R 1, PIC32MZ_RPA14R +#define U3TX_RPB5R 1, PIC32MZ_RPB5R +#define U3TX_RPB9R 1, PIC32MZ_RPB9R +#define U3TX_RPB10R 1, PIC32MZ_RPB10R +#define U3TX_RPC1R 1, PIC32MZ_RPC1R +#define U3TX_RPC14R 1, PIC32MZ_RPC14R +#define U3TX_RPD2R 1, PIC32MZ_RPD2R +#define U3TX_RPD6R 1, PIC32MZ_RPD6R +#define U3TX_RPD10R 1, PIC32MZ_RPD10R +#define U3TX_RPD14R 1, PIC32MZ_RPD14R +#define U3TX_RPF1R 1, PIC32MZ_RPF1R +#define U3TX_RPF4R 1, PIC32MZ_RPF4R +#define U3TX_RPG1R 1, PIC32MZ_RPG1R +#define U3TX_RPG8R 1, PIC32MZ_RPG8R + +#define U4RTS_RPA14R 2, PIC32MZ_RPA14R +#define U4RTS_RPB5R 2, PIC32MZ_RPB5R +#define U4RTS_RPB9R 2, PIC32MZ_RPB9R +#define U4RTS_RPB10R 2, PIC32MZ_RPB10R +#define U4RTS_RPC1R 2, PIC32MZ_RPC1R +#define U4RTS_RPC14R 2, PIC32MZ_RPC14R +#define U4RTS_RPD2R 2, PIC32MZ_RPD2R +#define U4RTS_RPD6R 2, PIC32MZ_RPD6R +#define U4RTS_RPD10R 2, PIC32MZ_RPD10R +#define U4RTS_RPD14R 2, PIC32MZ_RPD14R +#define U4RTS_RPF1R 2, PIC32MZ_RPF1R +#define U4RTS_RPF4R 2, PIC32MZ_RPF4R +#define U4RTS_RPG1R 2, PIC32MZ_RPG1R +#define U4RTS_RPG8R 2, PIC32MZ_RPG8R + +#define U4TX_RPB0R 2, PIC32MZ_RPB0R +#define U4TX_RPB7R 2, PIC32MZ_RPB7R +#define U4TX_RPB8R 2, PIC32MZ_RPB8R +#define U4TX_RPB15R 2, PIC32MZ_RPB15R +#define U4TX_RPC3R 2, PIC32MZ_RPC3R +#define U4TX_RPD4R 2, PIC32MZ_RPD4R +#define U4TX_RPD9R 2, PIC32MZ_RPD9R +#define U4TX_RPD12R 2, PIC32MZ_RPD12R +#define U4TX_RPE3R 2, PIC32MZ_RPE3R +#define U4TX_RPE9R 2, PIC32MZ_RPE9R +#define U4TX_RPF8R 2, PIC32MZ_RPF8R +#define U4TX_RPF12R 2, PIC32MZ_RPF12R +#define U4TX_RPG6R 2, PIC32MZ_RPG6R + +#define U5RTS_RPB2R 3, PIC32MZ_RPB2R +#define U5RTS_RPB6R 3, PIC32MZ_RPB6R +#define U5RTS_RPB14R 3, PIC32MZ_RPB14R +#define U5RTS_RPC2R 3, PIC32MZ_RPC2R +#define U5RTS_RPD0R 3, PIC32MZ_RPD0R +#define U5RTS_RPD1R 3, PIC32MZ_RPD1R +#define U5RTS_RPD5R 3, PIC32MZ_RPD5R +#define U5RTS_RPE8R 3, PIC32MZ_RPE8R +#define U5RTS_RPF2R 3, PIC32MZ_RPF2R +#define U5RTS_RPF3R 3, PIC32MZ_RPF3R +#define U5RTS_RPF13R 3, PIC32MZ_RPF13R +#define U5RTS_RPG9R 3, PIC32MZ_RPG9R + +#define U5TX_RPA15R 3, PIC32MZ_RPA15R +#define U5TX_RPB1R 3, PIC32MZ_RPB1R +#define U5TX_RPB3R 3, PIC32MZ_RPB3R +#define U5TX_RPC4R 3, PIC32MZ_RPC4R +#define U5TX_RPC13R 3, PIC32MZ_RPC13R +#define U5TX_RPD3R 3, PIC32MZ_RPD3R +#define U5TX_RPD7R 3, PIC32MZ_RPD7R +#define U5TX_RPD11R 3, PIC32MZ_RPD11R +#define U5TX_RPD15R 3, PIC32MZ_RPD15R +#define U5TX_RPE5R 3, PIC32MZ_RPE5R +#define U5TX_RPF0R 3, PIC32MZ_RPF0R +#define U5TX_RPF5R 3, PIC32MZ_RPF5R +#define U5TX_RPG0R 3, PIC32MZ_RPG0R +#define U5TX_RPG7R 3, PIC32MZ_RPG7R + +#define U6RTS_RPA15R 4, PIC32MZ_RPA15R +#define U6RTS_RPB1R 4, PIC32MZ_RPB1R +#define U6RTS_RPB3R 4, PIC32MZ_RPB3R +#define U6RTS_RPC4R 4, PIC32MZ_RPC4R +#define U6RTS_RPC13R 4, PIC32MZ_RPC13R +#define U6RTS_RPD3R 4, PIC32MZ_RPD3R +#define U6RTS_RPD7R 4, PIC32MZ_RPD7R +#define U6RTS_RPD11R 4, PIC32MZ_RPD11R +#define U6RTS_RPD15R 4, PIC32MZ_RPD15R +#define U6RTS_RPE5R 4, PIC32MZ_RPE5R +#define U6RTS_RPF0R 4, PIC32MZ_RPF0R +#define U6RTS_RPF5R 4, PIC32MZ_RPF5R +#define U6RTS_RPG0R 4, PIC32MZ_RPG0R +#define U6RTS_RPG7R 4, PIC32MZ_RPG7R + +#define U6TX_RPB0R 4, PIC32MZ_RPB0R +#define U6TX_RPB2R 4, PIC32MZ_RPB2R +#define U6TX_RPB6R 4, PIC32MZ_RPB6R +#define U6TX_RPB7R 4, PIC32MZ_RPB7R +#define U6TX_RPB8R 4, PIC32MZ_RPB8R +#define U6TX_RPB14R 4, PIC32MZ_RPB14R +#define U6TX_RPB15R 4, PIC32MZ_RPB15R +#define U6TX_RPC2R 4, PIC32MZ_RPC2R +#define U6TX_RPC3R 4, PIC32MZ_RPC3R +#define U6TX_RPD0R 4, PIC32MZ_RPD0R +#define U6TX_RPD1R 4, PIC32MZ_RPD1R +#define U6TX_RPD4R 4, PIC32MZ_RPD4R +#define U6TX_RPD5R 4, PIC32MZ_RPD5R +#define U6TX_RPD9R 4, PIC32MZ_RPD9R +#define U6TX_RPD12R 4, PIC32MZ_RPD12R +#define U6TX_RPE3R 4, PIC32MZ_RPE3R +#define U6TX_RPE8R 4, PIC32MZ_RPE8R +#define U6TX_RPE9R 4, PIC32MZ_RPE9R +#define U6TX_RPF2R 4, PIC32MZ_RPF2R +#define U6TX_RPF3R 4, PIC32MZ_RPF3R +#define U6TX_RPF8R 4, PIC32MZ_RPF8R +#define U6TX_RPF12R 4, PIC32MZ_RPF12R +#define U6TX_RPF13R 4, PIC32MZ_RPF13R +#define U6TX_RPG6R 4, PIC32MZ_RPG6R +#define U6TX_RPG9R 4, PIC32MZ_RPG9R + +#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_PPS_H */ diff --git a/arch/mips/src/pic32mz/pic32mz-config.h b/arch/mips/src/pic32mz/pic32mz-config.h index af150d4979eeefa38a1f2236d6624e97c16b8a31..dfec8ec1eb2865600892eb48ea510613d9ee10fe 100644 --- a/arch/mips/src/pic32mz/pic32mz-config.h +++ b/arch/mips/src/pic32mz/pic32mz-config.h @@ -537,6 +537,20 @@ /* Not yet configurable settings */ +#if defined(CONFIG_ARCH_CHIP_PIC32MZEC) +# define CONFIG_PIC32MX_SMCLR 0 +# define CONFIG_PIC32MX_SOSCGAIN 0 +# define CONFIG_PIC32MX_SOSCBOOST 0 +# define CONFIG_PIC32MX_POSCGAIN 0 +# define CONFIG_PIC32MX_POSCBOOST 0 +#elif defined(CONFIG_ARCH_CHIP_PIC32MZEF) +# define CONFIG_PIC32MX_SMCLR DEVCFG0_SMCLR +# define CONFIG_PIC32MX_SOSCGAIN DEVCFG0_SOSCGAIN_HIGH +# define CONFIG_PIC32MX_SOSCBOOST DEVCFG0_SOSCBOOST +# define CONFIG_PIC32MX_POSCGAIN DEVCFG0_POSCGAIN_HIGH +# define CONFIG_PIC32MX_POSCBOOST DEVCFG0_POSCBOOST +#endif + #define CONFIG_PIC32MZ_FSLEEP DEVCFG0_FSLEEP_OFF #define CONFIG_PIC32MZ_DBGPER DEVCFG0_DBGPER_ALL #define CONFIG_PIC32MZ_EJTAGBEN DEVCFG0_EJTAG_NORMAL diff --git a/arch/mips/src/pic32mz/pic32mz-head.S b/arch/mips/src/pic32mz/pic32mz-head.S index b04ab231f1389997ef5a82243e13fcb8385587ef..5e64bc25b24ac8fe0b596105daa92d2910cbf56f 100644 --- a/arch/mips/src/pic32mz/pic32mz-head.S +++ b/arch/mips/src/pic32mz/pic32mz-head.S @@ -690,29 +690,31 @@ devcfg3: DEVCFG3_RWO devcfg2: - .long CONFIG_PIC32MZ_PLLIDIV | CONFIG_PIC32MZ_FPLLRNG | \ - CONFIG_PIC32MZ_FPLLICLK | CONFIG_PIC32MZ_PLLMULT | \ - CONFIG_PIC32MZ_PLLODIV | CONFIG_PIC32MZ_UPLLFSEL | \ + .long CONFIG_PIC32MZ_PLLIDIV | CONFIG_PIC32MZ_FPLLRNG | \ + CONFIG_PIC32MZ_FPLLICLK | CONFIG_PIC32MZ_PLLMULT | \ + CONFIG_PIC32MZ_PLLODIV | CONFIG_PIC32MZ_UPLLFSEL | \ DEVCFG2_RWO devcfg1: - .long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_DMTINV |\ - CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_IESO | \ - CONFIG_PIC32MZ_POSCMOD | CONFIG_PIC32MZ_OSCIOFNC | \ - CONFIG_PIC32MZ_FCKSM | CONFIG_PIC32MZ_WDTPS | \ - CONFIG_PIC32MZ_WDTSPGM | CONFIG_PIC32MZ_WINDIS | \ - CONFIG_PIC32MZ_FWDTEN | CONFIG_PIC32MZ_FWDTWINSZ | \ - CONFIG_PIC32MZ_DMTCNT | CONFIG_PIC32MZ_FSOSCEN | \ - CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_FDMTEN | \ + .long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_DMTINV |\ + CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_IESO | \ + CONFIG_PIC32MZ_POSCMOD | CONFIG_PIC32MZ_OSCIOFNC | \ + CONFIG_PIC32MZ_FCKSM | CONFIG_PIC32MZ_WDTPS | \ + CONFIG_PIC32MZ_WDTSPGM | CONFIG_PIC32MZ_WINDIS | \ + CONFIG_PIC32MZ_FWDTEN | CONFIG_PIC32MZ_FWDTWINSZ | \ + CONFIG_PIC32MZ_DMTCNT | CONFIG_PIC32MZ_FSOSCEN | \ + CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_FDMTEN | \ DEVCFG1_RWO devcfg0: - .long CONFIG_PIC32MZ_DEBUGGER | CONFIG_PIC32MZ_JTAGEN | \ - CONFIG_PIC32MZ_ICESEL | CONFIG_PIC32MZ_TRCEN | \ - CONFIG_PIC32MZ_BOOTISA | CONFIG_PIC32MZ_FECCCON | \ - CONFIG_PIC32MZ_FSLEEP | CONFIG_PIC32MZ_DBGPER | \ - CONFIG_PIC32MZ_EJTAGBEN | DEVCFG0_RW0 - + .long CONFIG_PIC32MZ_DEBUGGER | CONFIG_PIC32MZ_JTAGEN | \ + CONFIG_PIC32MZ_ICESEL | CONFIG_PIC32MZ_TRCEN | \ + CONFIG_PIC32MZ_BOOTISA | CONFIG_PIC32MZ_FECCCON | \ + CONFIG_PIC32MZ_FSLEEP | CONFIG_PIC32MZ_DBGPER | \ + CONFIG_PIC32MX_SMCLR | CONFIG_PIC32MX_SOSCGAIN | \ + CONFIG_PIC32MX_SOSCBOOST | CONFIG_PIC32MX_POSCGAIN | \ + CONFIG_PIC32MX_POSCBOOST | CONFIG_PIC32MZ_EJTAGBEN | \ + DEVCFG0_RW0 .size devcfg, .-devcfg /* Every word in the configuration space and sequence space has an diff --git a/arch/risc-v/src/common/up_initialize.c b/arch/risc-v/src/common/up_initialize.c index acf400f8268560a60e770d83ad24cad7729e9f3e..83effe7494bdf523179e572929c74a4dd7aab4cf 100644 --- a/arch/risc-v/src/common/up_initialize.c +++ b/arch/risc-v/src/common/up_initialize.c @@ -44,6 +44,7 @@ #include #include #include +#include #include @@ -188,11 +189,19 @@ void up_initialize(void) ramlog_consoleinit(); #endif - /* Initialize the system logging device */ +#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_PSEUDOTERM_SUSV1) + /* Register the master pseudo-terminal multiplexor device */ -#ifdef CONFIG_SYSLOG_CHAR - syslog_initialize(); + (void)ptmx_register(); #endif + + /* Early initialization of the system logging device. Some SYSLOG channel + * can be initialized early in the initialization sequence because they + * depend on only minimal OS initialization. + */ + + syslog_initialize(SYSLOG_INIT_EARLY); + #ifdef CONFIG_RAMLOG_SYSLOG ramlog_sysloginit(); #endif diff --git a/arch/z80/src/z180/z180_mmu.c b/arch/z80/src/z180/z180_mmu.c index 53e6183d0b42279258ae4a0372f01600d69f0e92..acc9065b94366fe28a65fbd6e6873e017f17e5c6 100644 --- a/arch/z80/src/z180/z180_mmu.c +++ b/arch/z80/src/z180/z180_mmu.c @@ -69,9 +69,7 @@ * Private Data ****************************************************************************/ -#ifndef CONFIG_GRAN_SINGLE static GRAN_HANDLE g_physhandle; -#endif static struct z180_cbr_s g_cbrs[CONFIG_MAX_TASKS]; /**************************************************************************** @@ -166,14 +164,9 @@ int up_mmuinit(void) * say that 1 page is 1 byte. */ -#ifdef CONFIG_GRAN_SINGLE -return gran_initialize((FAR void *)Z180_PHYSHEAP_STARTPAGE, - Z180_PHYSHEAP_NPAGES, 0, 0); -#else g_physhandle = gran_initialize((FAR void *)Z180_PHYSHEAP_STARTPAGE, Z180_PHYSHEAP_NPAGES, 0, 0); return g_physhandle ? OK : -ENOMEM; -#endif } /**************************************************************************** @@ -280,12 +273,8 @@ int up_addrenv_create(size_t textsize, size_t datasize, size_t heapsize, /* Now allocate the physical memory to back up the address environment */ -#ifdef CONFIG_GRAN_SINGLE alloc = (uintptr_t)gran_alloc(npages); -#else - alloc = (uintptr_t)gran_alloc(g_physhandle, npages); -#endif - if (!alloc) + if (alloc == NULL) { serr("ERROR: Failed to allocate %d pages\n", npages); ret = -ENOMEM; @@ -337,11 +326,7 @@ int up_addrenv_destroy(FAR group_addrenv_t *addrenv) /* Free the physical address space backing up the mapping */ -#ifdef CONFIG_GRAN_SINGLE - gran_free((FAR void *)cbr->cbr, cbr->pages); -#else gran_free(g_physhandle, (FAR void *)cbr->cbr, cbr->pages); -#endif /* And make the CBR structure available for re-use */ diff --git a/configs/Kconfig b/configs/Kconfig index 469744b05e508f297cd7db09fe5432d5e4900852..c278ece1e8d677905c752aac7acc422be220f7eb 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -39,8 +39,8 @@ config ARCH_BOARD_AVR32DEV1 bool "Atmel AVR32DEV1 board" depends on ARCH_CHIP_AT32UC3B0256 select ARCH_HAVE_LEDS - select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS +# select ARCH_HAVE_BUTTONS +# select ARCH_HAVE_IRQBUTTONS ---help--- This is a port of NuttX to the Atmel AVR32DEV1 board. That board is based on the Atmel AT32UC3B0256 MCU and uses a specially patched @@ -196,6 +196,30 @@ config ARCH_BOARD_FIRE_STM32 and 3 of the boards are supported but only version 2 has been tested. +config ARCH_BOARD_FLIPNCLICK_PIC32MZ + bool "Mikroe Flip&Click PIC32MZ" + depends on ARCH_CHIP_PIC32MZ2048EFH + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + This options selects the Mikroe Flip&Click PIC32MZ board. This + board is an chipKit Arduino-compatible board (but can also be used + with the Mikroe bootloader). It has with four Mikroe Click bus + interfaces in addition to standard Arduino connectors. This board + features the Microchip PIC32MZ2048EFH100 MCU running at 200 MHz + (252Mhz capable). + +config ARCH_BOARD_FLIPNCLICK_SAM3X + bool "Mikroe Flip&Click SAM3X" + depends on ARCH_CHIP_ATSAM3X8E + select ARCH_HAVE_LEDS + ---help--- + This options selects the Mikroe Flip&Click STM32X board. This board + is an Arduino-Due work-alike with four Mikroe Click bus interfaces. + Like the Arduino DUE, this board features the Atmel ATSAM3X8E MCU + running at 84 MHz. + config ARCH_BOARD_FREEDOM_K64F bool "NXP Freedom-k64f development board" depends on ARCH_CHIP_MK64FN1M0VLL12 @@ -244,9 +268,25 @@ config ARCH_BOARD_HYMINI_STM32V A configuration for the HY-Mini STM32v board. This board is based on the STM32F103VCT6 chip. +config ARCH_BOARD_INDIUM_F7 + bool "Indium-F7" + depends on ARCH_CHIP_STM32F722RE || ARCH_CHIP_STM32F722ZE || ARCH_CHIP_STM32F746ZG || ARCH_CHIP_STM32F767ZI + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + Enables board support for the RAF Research Indium-F7 board and using + STMicro Nucleo-144 boards for interim support. The Indium-F7 board + is a special purpose board created by RAF Research LLC. It is + possible to develop basic Indium-F7 software using STMicro Nucleo-144 + development boards. This board support directory provides support for + developing software on both native Indium-F7 hardware and for three + STM32F7 Nucleo-144 development boards. + config ARCH_BOARD_LC823450_XGEVK bool "ON Semiconductor LC823450-XGEVK development board" depends on ARCH_CHIP_LC823450 + select ARCH_HAVE_LEDS ---help--- This port uses the ON Semiconductor LC823450-XGEVK development board. @@ -328,6 +368,15 @@ config ARCH_BOARD_LPCXPRESSO Embedded Artists base board with NXP LPCExpresso LPC1768. This board is based on the NXP LPC1768. The Code Red toolchain is used by default. +config ARCH_BOARD_LPCXPRESSO_LPC54628 + bool "NXP LPCXpresso LPC54628" + depends on ARCH_CHIP_LPC54628 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + LPCXpresso LPC54626 board featuring the NXP LPC54628 MCU. + config ARCH_BOARD_BAMBINO_200E bool "Micromint Bambino 200E" depends on ARCH_CHIP_LPC4330FBD144 @@ -380,6 +429,13 @@ config ARCH_BOARD_MBED that features the NXP LPC1768 microcontroller. This OS is also built with the arm-nuttx-elf toolchain*. STATUS: Contributed. +config ARCH_BOARD_MCB1700 + bool "Keil MCB1700" + depends on ARCH_CHIP_LPC1768 + select ARCH_HAVE_LEDS + ---help--- + The configurations in this directory support the Keil MCB1700. + config ARCH_BOARD_MCU123_LPC214X bool "mcu123.com LPC2148 Development Board" depends on ARCH_CHIP_LPC214X @@ -698,7 +754,7 @@ config ARCH_BOARD_NR5M100_NEXYS4 config ARCH_BOARD_NUCLEO_144 bool "STMicro NUCLEO-144" - depends on ARCH_CHIP_STM32F746ZG || ARCH_CHIP_STM32F767ZI + depends on ARCH_CHIP_STM32F722ZE || ARCH_CHIP_STM32F746ZG || ARCH_CHIP_STM32F767ZI select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS select ARCH_HAVE_IRQBUTTONS @@ -712,6 +768,7 @@ config ARCH_BOARD_NUCLEO_144 STM32F303ZET6 NUCLEO-F303ZE STM32F429ZIT6 NUCLEO-F429ZI STM32F446ZET6 NUCLEO-F446ZE + STM32F722ZET6 NUCLEO-F722ZE STM32F746ZGT6 NUCLEO-F746ZG STM32F767ZIT6 NUCLEO-F767ZI STM32L496ZGT6 NUCLEO-L496ZG @@ -719,6 +776,8 @@ config ARCH_BOARD_NUCLEO_144 Supported in this configuration are: + NUCLEO-F722ZE - STM32F722ZET6 a 216MHz Cortex-M7, w/FPU - + 512KiB Flash memory and 256KiB SRAM. NUCLEO-F746ZG - STM32F746ZGT6 a 216MHz Cortex-M7, w/FPU - 1024KiB Flash memory and 320KiB SRAM. NUCLEO-F767ZI - STM32F767ZIT6 a 216MHz Cortex-M7, w/DPFPU - @@ -1127,14 +1186,23 @@ config ARCH_BOARD_STM3240G_EVAL microcontroller (ARM Cortex-M4 with FPU). This port uses a GNU Cortex-M4 toolchain (such as CodeSourcery). -config ARCH_BOARD_STM32F0_DISCOVERY - bool "STMicro STM32F0-Discovery board" +config ARCH_BOARD_STM32F051_DISCOVERY + bool "STMicro STM32F051-Discovery board" depends on ARCH_CHIP_STM32F051R8 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS select ARCH_HAVE_IRQBUTTONS ---help--- - STMicro STM32F-Discovery board based on the STMicro ARCH_CHIP_STM32F051R8 MCU. + STMicro STM32F051-Discovery board based on the STMicro ARCH_CHIP_STM32F051R8 MCU. + +config ARCH_BOARD_STM32F072_DISCOVERY + bool "STMicro STM32F072-Discovery board" + depends on ARCH_CHIP_STM32F072RB + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + STMicro STM32F072-Discovery board based on the STMicro ARCH_CHIP_STM32F072RB MCU. config ARCH_BOARD_STM32F3_DISCOVERY bool "STMicro STM32F3-Discovery board" @@ -1416,15 +1484,6 @@ config ARCH_BOARD_XMC4500RELAX ---help--- Infineon XMC4000 Relax Lite v1 -config ARCH_BOARD_XTRS - bool "XTRS TRS80 Model 3 emulation" - depends on ARCH_CHIP_Z80 - select UART_SERIALDRIVER - ---help--- - TRS80 Model 3. This port uses a vintage computer based on the Z80. - An emulator for this computer is available to run TRS80 programs on a - linux platform (http://www.tim-mann.org/xtrs.html). - config ARCH_BOARD_Z16F2800100ZCOG bool "Zilog Z16F2800100ZCOG Development Kit" depends on ARCH_CHIP_Z16F2811 @@ -1574,11 +1633,14 @@ config ARCH_BOARD default "ez80f910200kitg" if ARCH_BOARD_EZ80F910200KITG default "ez80f910200zco" if ARCH_BOARD_EZ80F910200ZCO default "fire-stm32v2" if ARCH_BOARD_FIRE_STM32 + default "flipnclick-pic32mz" if ARCH_BOARD_FLIPNCLICK_PIC32MZ + default "flipnclick-sam3x" if ARCH_BOARD_FLIPNCLICK_SAM3X default "freedom-k64f" if ARCH_BOARD_FREEDOM_K64F default "freedom-k66f" if ARCH_BOARD_FREEDOM_K66F default "freedom-kl25z" if ARCH_BOARD_FREEDOM_KL25Z default "freedom-kl26z" if ARCH_BOARD_FREEDOM_KL26Z default "hymini-stm32v" if ARCH_BOARD_HYMINI_STM32V + default "indium-f7" if ARCH_BOARD_INDIUM_F7 default "kwikstik-k40" if ARCH_BOARD_KWIKSTIK_K40 default "launchxl-tms57004" if ARCH_BOARD_LAUNCHXL_TMS57004 default "lc823450-xgevk" if ARCH_BOARD_LC823450_XGEVK @@ -1593,8 +1655,10 @@ config ARCH_BOARD default "lpc4370-link2" if ARCH_BOARD_LPC4370_LINK2 default "lpcxpresso-lpc1115" if ARCH_BOARD_LPCXPRESSO_LPC1115 default "lpcxpresso-lpc1768" if ARCH_BOARD_LPCXPRESSO + default "lpcxpresso-lpc54628" if ARCH_BOARD_LPCXPRESSO_LPC54628 default "maple" if ARCH_BOARD_MAPLE default "mbed" if ARCH_BOARD_MBED + default "mcb1700" if ARCH_BOARD_MCB1700 default "mcu123-lpc214x" if ARCH_BOARD_MCU123_LPC214X default "micropendous3" if ARCH_BOARD_MICROPENDOUS3 default "mirtoo" if ARCH_BOARD_MIRTOO @@ -1657,7 +1721,8 @@ config ARCH_BOARD default "photon" if ARCH_BOARD_PHOTON default "stm32butterfly2" if ARCH_BOARD_STM32_BUTTERFLY2 default "stm32_tiny" if ARCH_BOARD_STM32_TINY - default "stm32f0discovery" if ARCH_BOARD_STM32F0_DISCOVERY + default "stm32f051-discovery" if ARCH_BOARD_STM32F051_DISCOVERY + default "stm32f072-discovery" if ARCH_BOARD_STM32F072_DISCOVERY default "stm32f103-minimum" if ARCH_BOARD_STM32F103_MINIMUM default "stm3210e-eval" if ARCH_BOARD_STM3210E_EVAL default "stm3220g-eval" if ARCH_BOARD_STM3220G_EVAL @@ -1690,7 +1755,6 @@ config ARCH_BOARD default "us7032evb1" if ARCH_BOARD_US7032EVB1 default "viewtool-stm32f107" if ARCH_BOARD_VIEWTOOL_STM32F107 default "xmc4500-relax" if ARCH_BOARD_XMC4500RELAX - default "xtrs" if ARCH_BOARD_XTRS default "z16f2800100zcog" if ARCH_BOARD_Z16F2800100ZCOG default "z80sim" if ARCH_BOARD_Z80SIM default "z8encore000zco" if ARCH_BOARD_Z8ENCORE000ZCO @@ -1795,6 +1859,12 @@ endif if ARCH_BOARD_FIRE_STM32 source "configs/fire-stm32v2/Kconfig" endif +if ARCH_BOARD_FLIPNCLICK_PIC32MZ +source "configs/flipnclick-pic32mz/Kconfig" +endif +if ARCH_BOARD_FLIPNCLICK_SAM3X +source "configs/flipnclick-sam3x/Kconfig" +endif if ARCH_BOARD_FREEDOM_K64F source "configs/freedom-k64f/Kconfig" endif @@ -1810,6 +1880,9 @@ endif if ARCH_BOARD_HYMINI_STM32V source "configs/hymini-stm32v/Kconfig" endif +if ARCH_BOARD_INDIUM_F7 +source "configs/indium-f7/Kconfig" +endif if ARCH_BOARD_KWIKSTIK_K40 source "configs/kwikstik-k40/Kconfig" endif @@ -1849,12 +1922,18 @@ endif if ARCH_BOARD_LPCXPRESSO source "configs/lpcxpresso-lpc1768/Kconfig" endif +if ARCH_BOARD_LPCXPRESSO_LPC54628 +source "configs/lpcxpresso-lpc54628/Kconfig" +endif if ARCH_BOARD_MAPLE source "configs/maple/Kconfig" endif if ARCH_BOARD_MBED source "configs/mbed/Kconfig" endif +if ARCH_BOARD_MCB1700 +source "configs/mcb1700/Kconfig" +endif if ARCH_BOARD_MCU123_LPC214X source "configs/mcu123-lpc214x/Kconfig" endif @@ -2041,8 +2120,11 @@ endif if ARCH_BOARD_STM32_TINY source "configs/stm32_tiny/Kconfig" endif -if ARCH_BOARD_STM32F0_DISCOVERY -source "configs/stm32f0discovery/Kconfig" +if ARCH_BOARD_STM32F051_DISCOVERY +source "configs/stm32f051-discovery/Kconfig" +endif +if ARCH_BOARD_STM32F072_DISCOVERY +source "configs/stm32f072-discovery/Kconfig" endif if ARCH_BOARD_STM32F103_MINIMUM source "configs/stm32f103-minimum/Kconfig" @@ -2134,9 +2216,6 @@ endif if ARCH_BOARD_XMC4500RELAX source "configs/xmc4500-relax/Kconfig" endif -if ARCH_BOARD_XTRS -source "configs/xtrs/Kconfig" -endif if ARCH_BOARD_Z16F2800100ZCOG source "configs/z16f2800100zcog/Kconfig" endif diff --git a/configs/README.txt b/configs/README.txt index c18dd108d281ae0c8511ca213ca9cf077daae2a0..e9ace0cf9bc41fa1973181bbb4fdf599a12f9e8b 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -260,6 +260,19 @@ configs/fire-stm32v2 STM32F103VET6 chip. See http://firestm32.taobao.com . Version 2 and 3 of the boards are supported but only version 2 has been tested. +configs/flipnclick-pic32mz + Board support for the Mikroe Flip&Click PIC32MZ board. This board is an + chipKit Arduino-compatible board (but can also be used with the Mikroe + bootloader). It has with four Mikroe Click bus interfaces in addition to + standard Arduino connectors. This board features the Microchip + PIC32MZ2048EFH100 MCU running at 200 MHz (252Mhz capable). + +configs/flipnclick-sam3x + Board support for the Mikroe Flip&Click STM32X board. This board is an + Arduino-Due work-alike with four Mikroe Click bus interfaces. Like the + Arduino DUE, this board features the Atmel ATSAM3X8E MCU running at 84 + MHz. + configs/freedom-k64f This port uses the NXP/FreeScale FREEDOM-K64F development board. This board uses the Kinetis K64 MK64FN1M0VLL12 Cortex-M4 MCU. @@ -276,6 +289,15 @@ configs/hymini-stm32v A configuration for the HY-Mini STM32v board. This board is based on the STM32F103VCT chip. +configs/indium-f7 + This subdirectory holds board support for the RAF Research Indium-F7 board + and using STMicro Nucleo-144 boards for interim support. The Indium-F7 + board is a special purpose board created by RAF Research LLC. It is + possible to develop basic Indium-F7 software using STMicro Nucleo-144 + development boards. This board support directory provides support for + developing software on both native Indium-F7 hardware and for three + STM32F7 Nucleo-144 development boards. + configs/kwikstik-k40. Kinetis K40 Cortex-M4 MCU. This port uses the NXP/FreeScale KwikStik-K40 development board. @@ -314,6 +336,9 @@ configs/lpcxpresso-lpc1768 is based on the NXP LPC1768. The Code Red toolchain is used by default. STATUS: Under development. +configs/lpcxpresso-lpc54628 + NXP LPCExpresso LPC54628. This board is based on the NXP LPC54628. + configs/lpc4330-xplorer NuttX port to the LPC4330-Xplorer board from NGX Technologies featuring the NXP LPC4330FET100 MCU @@ -342,6 +367,9 @@ configs/mbed that features the NXP LPC1768 microcontroller. This OS is also built with the arm-nuttx-elf toolchain*. STATUS: Contributed. +configs/mcb1700 + Board support for the Keil MCB1700 + configs/mikroe-stm32f4 This is the port of NuttX to the MikroElektronika Mikromedia for STM32F4 development board. Contributed by Ken Petit. @@ -659,8 +687,12 @@ configs/stm32butterfly2 Kamami stm32butterfly2 development board with optional ETH phy. See https://kamami.pl/zestawy-uruchomieniowe-stm32/178507-stm32butterfly2.html -configs/stm32f0discovery - STMicro STM32F-Discovery board based on the STMicro ARCH_CHIP_STM32F051R8 +configs/stm32f051-discovery + STMicro STM32F051-Discovery board based on the STMicro ARCH_CHIP_STM32F051R8 + MCU. + +configs/stm32f072-discovery + STMicro STM32F072-Discovery board based on the STMicro ARCH_CHIP_STM32F072RB MCU. configs/stm32f103-minimum @@ -777,11 +809,6 @@ configs/viewtool-stm32f107 config/xmc4500-relax Infineon XMC4000 Relax Lite v1 -configs/xtrs - TRS80 Model 3. This port uses a vintage computer based on the Z80. - An emulator for this computer is available to run TRS80 programs on a - linux platform (http://www.tim-mann.org/xtrs.html). - configs/z16f2800100zcog z16f Microcontroller. This port use the Zilog z16f2800100zcog development kit and the Zilog ZDS-II Windows command line tools. The diff --git a/configs/arduino-due/README.txt b/configs/arduino-due/README.txt index f85dc97b2c2c20fa563d4013bf0f2ecb5f8e5283..bb6d7f08aa8ad1197ce4e99a1fc82938a624040b 100644 --- a/configs/arduino-due/README.txt +++ b/configs/arduino-due/README.txt @@ -1,5 +1,5 @@ README -^^^^^^ +====== This README discusses issues unique to NuttX configurations for the Arduino DUE board featuring the Atmel ATSAM3X8E MCU running at 84 MHz. @@ -17,25 +17,19 @@ README - ITEAD 2.4" TFT with Touch, Arduino Shield 1.0 Contents -^^^^^^^^ +======== - PIO Pin Usage - Rev 2 vs. Rev 3 - ITEAD 2.4" TFT with Touch - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - Buttons and LEDs - Serial Consoles - Loading Code - - SAM4S Xplained-specific Configuration Options + - Arduino Due-specific Configuration Options - Configurations PIO Pin Usage -^^^^^^^^^^^^^ +============= PORTA PORTB PORTC ------------------------------ ------------------------------ -------------------------------- @@ -114,7 +108,7 @@ PIO Pin Usage ----- ---------- ---- -------- ----- ------------ ---- ------ ----- ----------- ---- --------- Rev 2 vs. Rev 3 -^^^^^^^^^^^^^^^ +=============== This port was performed on the Arduino Due Rev 2 board. NuttX users have reported issues with the serial port on his Arduino Due Rev 3 board. @@ -125,7 +119,7 @@ Rev 2 vs. Rev 3 CONFIG_ARDUINO_DUE_REV3=y ITEAD 2.4" TFT with Touch -^^^^^^^^^^^^^^^^^^^^^^^^^ +========================= The Arduino 2.4" TFT Touch Shield is designed for all the Arduino compatible boards. It works in 3.3V voltage level. It can be directly @@ -250,204 +244,8 @@ ITEAD 2.4" TFT with Touch NOTES: - /CS is connected to ground (XPT2046 is always selected) -Development Environment -^^^^^^^^^^^^^^^^^^^^^^^ - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -^^^^^^^^^^^^^^^^^^^^^ - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The devkitARM GNU toolchain, ok - 4. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the NuttX buildroot toolchain. However, - the make system is setup to default to use the devkitARM toolchain. To use - the CodeSourcery, devkitARM or Raisonance GNU toolchain, you simply need to - add one of the following configuration options to your .config (or defconfig) - file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : Atollic toolchain for Windows - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y : Generic GCC ARM EABI toolchain for Linux - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : Generic GCC ARM EABI toolchain for Windows - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE about Windows native toolchains - ------------------------------------ - - The CodeSourcery (for Windows), Atollic, and devkitARM toolchains are - Windows native toolchains. The CodeSourcery (for Linux), NuttX buildroot, - and, perhaps, the generic GCC toolchains are Cygwin and/or Linux native - toolchains. There are several limitations to using a Windows based - toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -^^^^ - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/sam34, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/sam34/sam_vectors.S. You may need to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by an IDE. - -NuttX EABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.shsam4s-xplained/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toolchain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -^^^^^^^^^^^^^^^^ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - Buttons and LEDs -^^^^^^^^^^^^^^^^ +================ Buttons ------- @@ -493,7 +291,7 @@ Buttons and LEDs has halted. Serial Consoles -^^^^^^^^^^^^^^^ +=============== The SAM3X has a UART and 4 USARTS. The Programming port uses a USB-to- serial chip connected to the first UART0 of the MCU (RX0 and TX0). The @@ -530,39 +328,57 @@ Serial Consoles USB virual COM port in the case of UART0). Loading Code -^^^^^^^^^^^^ +============ Installing the Arduino USB Driver under Windows: ------------------------------------------------ - 1. Download the Windows version of the Arduino software, not the 1.0.x - release but the latest 1.5.x that supports the Due. When the download - finishes, unzip the downloaded file. - 2. Connect the Due to your computer with a USB cable via the Programming port. + + 1. Download the Windows version of the Arduino software, not the 1.0.x + release but the latest (1.5.x or later) that supports the Due. When + the download finishes, unzip the downloaded file. + + In the current 1.8.x release, the Arduino Due support is not included + in the base package but can be added by selecting the "Boards Manager" + from the "Tools" menu. + + 2. Connect the Due to your computer with a USB cable via the Programming + port. + 3. The Windows driver installation should fail. + 4. Open the Device Manger + 5. Look for the listing named "Ports (COM & LPT)". You should see an open - port named "Arduino Due Prog. Port". - 6 Select the "Browse my computer for Driver software" option. + port named "Arduino Due Prog. Port". Right click and select "Update + driver". + + 6. Select the "Browse my computer for Driver software" option. + 7. Right click on the "Arduino Due Prog. Port" and choose "Update Driver Software". + 8. Navigate to the folder with the Arduino IDE you downloaded and unzipped earlier. Locate and select the "Drivers" folder in the main Arduino folder (not the "FTDI USB Drivers" sub-directory). - Uploading NuttX to the Due Using Bossa: - --------------------------------------- - I don't think this can be done because the Arduino software is so dedicated - to "sketches". However, Arduino uses BOSSA under the hood to load code and - you can use BOSSA outside of Arduino. + Loading NuttX to the Due Using Bossa: + ------------------------------------- + + Arduino uses BOSSA under the hood to load code and you can use BOSSA + outside of Arduino. - Uploading NuttX to the Due Using Bossa: - --------------------------------------- Where do you get it? + Generic BOSSA installation files are available here: - http://sourceforge.net/projects/b-o-s-s-a/?source=dlp + https://github.com/shumatech/BOSSA (formerly at + http://sourceforge.net/projects/b-o-s-s-a/?source=dlp) - However, DUE uses a patched version of BOSSA available as source code here: - https://github.com/shumatech/BOSSA/tree/arduino + Pre-built binaries are available: https://github.com/shumatech/BOSSA/releases + + The original Arduino DUE used a patched version of BOSSA available + as source code here: https://github.com/shumatech/BOSSA/tree/arduino + But that has most likely been incorporated into the main github + repository. But, fortunately, since you already installed Arduino, you already have BOSSA installed. In my installation, it is here: @@ -570,7 +386,6 @@ Loading Code C:\Program Files (x86)\Arduino\arduino-1.5.2\hardware\tools\bossac.exe General Procedure - ----------------- 1) Erase the FLASH and put the Due in bootloader mode 2) Write the file to FLASH @@ -578,7 +393,7 @@ Loading Code 4) Reset the DUE Erase FLASH and Put the Due in Bootloader Mode - ---------------------------------------------- + This is accomplished by simply configuring the programming port in 1200 baud and sending something on the programming port. Here is some sample output from a Windows CMD.exe shell. NOTE that my Arduino programming @@ -590,7 +405,7 @@ Loading Code C:\Program Files (x86)\Arduino\arduino-1.5.2\hardware\tools>mode com26:1200,n,8,1 Status for device COM26: - ------------------------ + Baud: 1200 Parity: None Data Bits: 8 @@ -603,7 +418,7 @@ Loading Code DTR circuit: ON RTS circuit: ON - C:\Program Files (x86)\Arduino\arduino-1.5.2\hardware\tools>bossac.exe --port=COM26 -U false -i + C:\Program Files (x86)\Arduino\arduino-1.5.2\hardware\tools>bossac.exe --port=COM26 --usb-port=false -i Device : ATSAM3X8 Chip ID : 285e0a60 Version : v1.1 Dec 15 2010 19:25:04 @@ -625,7 +440,7 @@ Loading Code Erasing, writing, and verifying FLASH with bossac: - $ bossac.exe --port=COM26 -U false -e -w -v -b nuttx.bin -R + $ bossac.exe --port=COM26 --usb-port=false -e -w -v -b nuttx.bin -R Erase flash Write 86588 bytes to flash [==============================] 100% (339/339 pages) @@ -637,19 +452,19 @@ Loading Code Some things that can go wrong: - $ bossac.exe --port=COM26 -U false -e -w -v -b nuttx.bin -R + $ bossac.exe --port=COM26 --usb-port=false -e -w -v -b nuttx.bin -R No device found on COM26 This error means that there is code running on the Due already so the - bootloader cannot connect. Pressing reset and trying again + bootloader cannot connect. Press reset and try again - $ bossac.exe --port=COM26 -U false -e -w -v -b nuttx.bin -R + $ bossac.exe --port=COM26 --usb-port=false -e -w -v -b nuttx.bin -R No device found on COM26 Sill No connection because Duo does not jump to bootloader after reset. Press ERASE button and try again - $ bossac.exe --port=COM26 -U false -e -w -v -b nuttx.bin -R + $ bossac.exe --port=COM26 --usb-port=false -e -w -v -b nuttx.bin -R Erase flash Write 86588 bytes to flash [==============================] 100% (339/339 pages) @@ -659,13 +474,13 @@ Loading Code Set boot flash true CPU reset. - Other useful bossac things operations. - ------------------------------------- + Other useful bossac operations. + a) Write code to FLASH don't change boot mode and don't reset. This lets you examine the FLASH contents that you just loaded while the bootloader is still active. - $ bossac.exe --port=COM26 -U false -e -w -v --boot=0 nuttx.bin + $ bossac.exe --port=COM26 --usb-port=false -e -w -v --boot=0 nuttx.bin Write 64628 bytes to flash [==============================] 100% (253/253 pages) Verify 64628 bytes of flash @@ -674,23 +489,23 @@ Loading Code b) Verify the FLASH contents (the bootloader must be running) - $ bossac.exe --port=COM26 -U false -v nuttx.bin + $ bossac.exe --port=COM26 --usb-port=false -v nuttx.bin Verify 64628 bytes of flash [==============================] 100% (253/253 pages) Verify successful c) Read from FLASH to a file (the bootloader must be running): - $ bossac.exe --port=COM26 -U false --read=4096 nuttx.dump + $ bossac.exe --port=COM26 --usb-port=false --read=4096 nuttx.dump Read 4096 bytes from flash [==============================] 100% (16/16 pages) d) Change to boot from FLASH - $ bossac.exe --port=COM26 -U false --boot=1 + $ bossac.exe --port=COM26 --usb-port=false --boot=1 Set boot flash true - Uploading NuttX to the Due Using JTAG: + Uploading NuttX to the Due Using JTAG ------------------------------------- The JTAG/SWD signals are brought out to a 10-pin header JTAG connector: @@ -714,7 +529,7 @@ Loading Code have been unable to get the get the SAM-ICE to communicate with the Due. Arduino DUE-specific Configuration Options -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +========================================== CONFIG_ARCH - Identifies the arch/ subdirectory. This should be set to: @@ -752,12 +567,9 @@ Arduino DUE-specific Configuration Options CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation of delay loops - CONFIG_ENDIAN_BIG - define if big endian (default is little - endian) - CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case): - CONFIG_RAM_SIZE=0x00008000 (32Kb) + CONFIG_RAM_SIZE=65536 (64Kb) CONFIG_RAM_START - The start address of installed DRAM @@ -766,37 +578,20 @@ Arduino DUE-specific Configuration Options CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that have LEDs - CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt - stack. If defined, this symbol is the size of the interrupt - stack in bytes. If not defined, the user task stacks will be - used during interrupt handling. - - CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions - - CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. - - CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that - cause a 100 second delay during boot-up. This 100 second delay - serves no purpose other than it allows you to calibrate - CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure - the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until - the delay actually is 100 seconds. - Individual subsystems can be enabled: + CONFIG_SAM34_ADC12B - 12-bit Analog To Digital Converter + CONFIG_SAM34_CAN0 - CAN Controller 0 + CONFIG_SAM34_CAN1 - CAN Controller 1 + CONFIG_SAM34_DACC - Digital To Analog Converter + CONFIG_SAM34_DMAC0 - DMA Controller + CONFIG_SAM34_EMAC - Ethernet MAC + CONFIG_SAM34_HSMCI - High Speed Multimedia Card Interface + CONFIG_SAM34_PWM - Pulse Width Modulation CONFIG_SAM34_RTC - Real Time Clock CONFIG_SAM34_RTT - Real Time Timer - CONFIG_SAM34_WDT - Watchdog Timer - CONFIG_SAM34_UART0 - UART 0 - CONFIG_SAM34_SMC - Static Memory Controller CONFIG_SAM34_SDRAMC - SDRAM Controller - CONFIG_SAM34_USART0 - USART 0 - CONFIG_SAM34_USART1 - USART 1 - CONFIG_SAM34_USART2 - USART 2 - CONFIG_SAM34_USART3 - USART 3 - CONFIG_SAM34_HSMCI - High Speed Multimedia Card Interface - CONFIG_SAM34_TWI0 - Two-Wire Interface 0 (master/slave) - CONFIG_SAM34_TWI1 - Two-Wire Interface 1 (master/slave) + CONFIG_SAM34_SMC - Static Memory Controller CONFIG_SAM34_SPI0 - Serial Peripheral Interface 0 CONFIG_SAM34_SPI1 - Serial Peripheral Interface 1 CONFIG_SAM34_SSC - Synchronous Serial Controller @@ -809,15 +604,16 @@ Arduino DUE-specific Configuration Options CONFIG_SAM34_TC6 - Timer Counter 6 CONFIG_SAM34_TC7 - Timer Counter 7 CONFIG_SAM34_TC8 - Timer Counter 8 - CONFIG_SAM34_PWM - Pulse Width Modulation - CONFIG_SAM34_ADC12B - 12-bit Analog To Digital Converter - CONFIG_SAM34_DACC - Digital To Analog Converter - CONFIG_SAM34_DMAC0 - DMA Controller - CONFIG_SAM34_UOTGHS - USB OTG High Speed CONFIG_SAM34_TRNG - True Random Number Generator - CONFIG_SAM34_EMAC - Ethernet MAC - CONFIG_SAM34_CAN0 - CAN Controller 0 - CONFIG_SAM34_CAN1 - CAN Controller 1 + CONFIG_SAM34_TWIM/S0 - Two-Wire Interface 0 (master/slave) + CONFIG_SAM34_TWIM/S1 - Two-Wire Interface 1 (master/slave) + CONFIG_SAM34_UART0 - UART 0 + CONFIG_SAM34_UOTGHS - USB OTG High Speed + CONFIG_SAM34_USART0 - USART 0 + CONFIG_SAM34_USART1 - USART 1 + CONFIG_SAM34_USART2 - USART 2 + CONFIG_SAM34_USART3 - USART 3 + CONFIG_SAM34_WDT - Watchdog Timer Some subsystems can be configured to operate in different ways. The drivers need to know how to configure the subsystem. @@ -828,33 +624,18 @@ Arduino DUE-specific Configuration Options CONFIG_SAM34_GPIOD_IRQ CONFIG_SAM34_GPIOE_IRQ CONFIG_SAM34_GPIOF_IRQ - CONFIG_USART0_SERIALDRIVER - CONFIG_USART1_SERIALDRIVER - CONFIG_USART2_SERIALDRIVER - CONFIG_USART3_SERIALDRIVER - - ST91SAM4S specific device driver settings - - CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=0,1,2,3) or UART - m (m=4,5) for the console and ttys0 (default is the USART1). - CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received. - This specific the size of the receive buffer - CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before - being sent. This specific the size of the transmit buffer - CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be - CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8. - CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity - CONFIG_U[S]ARTn_2STOP - Two stop bits Configurations -^^^^^^^^^^^^^^ +============== - Each SAM4S Xplained configuration is maintained in a sub-directory and + Each Arduino Due configuration is maintained in a sub-directory and can be selected as follow: - cd tools - ./configure.sh arduino-due/ - cd - + tools/configure.sh [OPTIONS] arduino-due/ + + Where typical options are -l to configure to build on Linux or -c to + configure for Cygwin under Linux. 'tools/configure.sh -h' will show + you all of the options. Before building, make sure the PATH environment variable includes the correct path to the directory than holds your toolchain binaries. @@ -936,14 +717,11 @@ Configurations Atmel tools. Try 'which arm-none-eabi-gcc' to make sure that you are selecting the right tool. - See also the "NOTE about Windows native toolchains" in the section call - "GNU Toolchain Options" above. - Configuration sub-directories ----------------------------- nsh: - This configuration directory will built the NuttShell. See NOTES above. + This configuration directory will build the NuttShell. See NOTES above. NOTES: 1. NSH built-in applications are supported. However, there are @@ -952,7 +730,7 @@ Configuration sub-directories Binary Formats: CONFIG_BUILTIN=y : Enable support for built-in programs - Applicaton Configuration: + Application Configuration: CONFIG_NSH_BUILTIN_APPS=y : Enable starting apps from NSH command line 2. By default, this configuration uses UART0 and has support LEDs @@ -1015,7 +793,7 @@ Configuration sub-directories CONFIG_MMCSD=y : Enable MMC/SD support CONFIG_MMCSD_NSLOTS=1 : Only one MMC/SD card slot CONFIG_MMCSD_MULTIBLOCK_DISABLE=n : Should not need to disable multi-block transfers - CONFIG_MMCSD_HAVECARDDETECT=y : I/O1 module as a card detect GPIO + CONFIG_MMCSD_HAVE_CARDDETECT=y : I/O1 module as a card detect GPIO CONFIG_MMCSD_SPI=y : Use the SPI interface to the MMC/SD card CONFIG_MMCSD_SPICLOCK=20000000 : This is a guess for the optimal MMC/SD frequency CONFIG_MMCSD_SPIMODE=0 : Mode 0 is required @@ -1067,7 +845,7 @@ Configuration sub-directories Library Support: CONFIG_SCHED_WORKQUEUE=y : Work queue support required - Applicaton Configuration: + Application Configuration: CONFIG_EXAMPLES_TOUCHSCREEN=y : Enable the touchscreen built-int test Defaults should be okay for related touchscreen settings. Touchscreen diff --git a/configs/arduino-due/include/board.h b/configs/arduino-due/include/board.h index fb1df9ea1ad75042859f9870b61f736220f5e6e6..c8b92d90478fba858322966d7c7806ae81dd1e27 100644 --- a/configs/arduino-due/include/board.h +++ b/configs/arduino-due/include/board.h @@ -224,39 +224,4 @@ GPIO_PIN8 | GPIO_CFG_PULLUP) #endif -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: sam_boardinitialize - * - * Description: - * All SAM3X architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void sam_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_ARDUINO_DUE_INCLUDE_BOARD_H */ diff --git a/configs/arduino-due/nsh/defconfig b/configs/arduino-due/nsh/defconfig index 99ba4a71d9150e6d2a3701254d8ba893968d417b..15814e72310a2dd88fe34e517bf6d0aee79c1235 100644 --- a/configs/arduino-due/nsh/defconfig +++ b/configs/arduino-due/nsh/defconfig @@ -1,7 +1,4 @@ # CONFIG_ARCH_RAMFUNCS is not set -# CONFIG_NSH_CMDOPT_DF_H is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set CONFIG_ARCH_BOARD_ARDUINO_DUE=y CONFIG_ARCH_BOARD="arduino-due" CONFIG_ARCH_CHIP_ATSAM3X8E=y @@ -19,6 +16,7 @@ CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_POLL=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y CONFIG_EXAMPLES_NSH=y +CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_MAX_TASKS=16 @@ -27,6 +25,7 @@ CONFIG_MM_REGIONS=3 CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_STREAMS=8 CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_PREALLOC_MQ_MSGS=4 diff --git a/configs/arduino-due/scripts/arduino-due.ld b/configs/arduino-due/scripts/arduino-due.ld index 4a250f6eb84836c36220590b88708ac2c9cff3f5..6310c5125fdff6811fb1456b56a669dd0e1eca02 100644 --- a/configs/arduino-due/scripts/arduino-due.ld +++ b/configs/arduino-due/scripts/arduino-due.ld @@ -39,17 +39,18 @@ MEMORY { - flash (rx) : ORIGIN = 0x00080000, LENGTH = 1024K - sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K - sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 32K - nfcram (rwx) : ORIGIN = 0x20100000, LENGTH = 4K + flash (rx) : ORIGIN = 0x00080000, LENGTH = 512K + sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K + sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 32K + nfcram (rwx) : ORIGIN = 0x20100000, LENGTH = 4K } OUTPUT_ARCH(arm) ENTRY(_stext) SECTIONS { - .text : { + .text : + { _stext = ABSOLUTE(.); *(.vectors) *(.text .text.*) @@ -65,23 +66,27 @@ SECTIONS _etext = ABSOLUTE(.); } > flash - .init_section : { + .init_section : + { _sinit = ABSOLUTE(.); *(.init_array .init_array.*) _einit = ABSOLUTE(.); } > flash - .ARM.extab : { + .ARM.extab : + { *(.ARM.extab*) } >flash __exidx_start = ABSOLUTE(.); - .ARM.exidx : { + .ARM.exidx : + { *(.ARM.exidx*) } >flash __exidx_end = ABSOLUTE(.); - .data : { + .data : + { _sdata = ABSOLUTE(.); *(.data .data.*) *(.gnu.linkonce.d.*) @@ -91,7 +96,8 @@ SECTIONS _eronly = LOADADDR(.data); - .ramfunc ALIGN(4): { + .ramfunc ALIGN(4): + { _sramfuncs = ABSOLUTE(.); *(.ramfunc .ramfunc.*) _eramfuncs = ABSOLUTE(.); @@ -99,7 +105,8 @@ SECTIONS _framfuncs = LOADADDR(.ramfunc); - .bss : { + .bss : + { _sbss = ABSOLUTE(.); *(.bss .bss.*) *(.gnu.linkonce.b.*) @@ -108,6 +115,7 @@ SECTIONS } > sram0 /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } .stab.excl 0 : { *(.stab.excl) } diff --git a/configs/stm32f0discovery/src/.gitignore b/configs/arduino-due/src/.gitignore similarity index 100% rename from configs/stm32f0discovery/src/.gitignore rename to configs/arduino-due/src/.gitignore diff --git a/configs/arduino-due/src/Makefile b/configs/arduino-due/src/Makefile index e26901a09a1a3124f20bb5a43d575c0e3a05b6f0..2d4df9e6d35fa446cf191ab420332377c3348b64 100644 --- a/configs/arduino-due/src/Makefile +++ b/configs/arduino-due/src/Makefile @@ -1,7 +1,7 @@ ############################################################################ # configs/arduino-due/src/Makefile # -# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Copyright (C) 2013, 2018 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -36,7 +36,7 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = sam_boot.c +CSRCS = sam_boot.c sam_bringup.c ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += sam_autoleds.c diff --git a/configs/arduino-due/src/arduino-due.h b/configs/arduino-due/src/arduino-due.h index 68be762271e916f08020638a61f86693dffe17aa..0e2b6736b347bd156fb3c25fd49247146ab77108 100644 --- a/configs/arduino-due/src/arduino-due.h +++ b/configs/arduino-due/src/arduino-due.h @@ -1,7 +1,7 @@ /************************************************************************************ * configs/arduino-due/src/arduino-due.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -308,17 +308,21 @@ * Public Functions ************************************************************************************/ -/************************************************************************************ - * Name: sam_sram_initialize +/**************************************************************************** + * Name: sam_bringup * * Description: - * Configure and enable SRAM on board the SAM4S Xplained + * Perform architecture-specific initialization * - ************************************************************************************/ + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ -#ifdef CONFIG_SAM34_EXTSRAM0 -void sam_sram_initialize(void); -#endif +int sam_bringup(void); /**************************************************************************** * Name: sam_sdinitialize diff --git a/configs/arduino-due/src/sam_appinit.c b/configs/arduino-due/src/sam_appinit.c index 78587bcce73cc35996d6686f1e9a7e0f11e93168..91e9391daf43ea51834dde2d36366972dd45332e 100644 --- a/configs/arduino-due/src/sam_appinit.c +++ b/configs/arduino-due/src/sam_appinit.c @@ -1,7 +1,7 @@ /**************************************************************************** * config/arduino-due/src/sam_appinit.c * - * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2016, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -39,9 +39,6 @@ #include -#include -#include - #include #include "arduino-due.h" @@ -50,22 +47,8 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_ARDUINO_ITHEAD_TFT) && defined(CONFIG_SPI_BITBANG) && \ - defined(CONFIG_MMCSD_SPI) -/* Support for the SD card slot on the ITEAD TFT shield */ -/* Verify NSH PORT and SLOT settings */ - -# define SAM34_MMCSDSLOTNO 0 /* There is only one slot */ - -# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != SAM34_MMCSDSLOTNO -# error Only one MMC/SD slot: Slot 0 (CONFIG_NSH_MMCSDSLOTNO) -# endif - -/* Default MMC/SD minor number */ - -# ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 -# endif +#ifndef OK +# define OK 0 #endif /**************************************************************************** @@ -84,7 +67,7 @@ * arg - The boardctl() argument is passed to the board_app_initialize() * implementation without modification. The argument has no * meaning to NuttX; the meaning of the argument is a contract - * between the board-specific initalization logic and the + * between the board-specific initialization logic and the * matching application logic. The value cold be such things as a * mode enumeration value, a set of DIP switch switch settings, a * pointer to configuration data read from a file or serial FLASH, @@ -99,21 +82,13 @@ int board_app_initialize(uintptr_t arg) { -#if defined(CONFIG_ARDUINO_ITHEAD_TFT) && defined(CONFIG_SPI_BITBANG) && \ - defined(CONFIG_MMCSD_SPI) - /* Initialize the SPI-based MMC/SD slot */ - - { - int ret = sam_sdinitialize(CONFIG_NSH_MMCSDMINOR); - if (ret < 0) - { - syslog(LOG_ERR, - "board_app_initialize: Failed to initialize MMC/SD slot: %d\n", - ret); - return ret; - } - } -#endif +#ifdef CONFIG_BOARD_INITIALIZE + /* Board initialization already performed by board_initialize() */ return OK; +#else + /* Perform board-specific initialization */ + + return sam_bringup(); +#endif } diff --git a/configs/arduino-due/src/sam_boot.c b/configs/arduino-due/src/sam_boot.c index f720fcddb1ef07b5bd448c467566ca83ef11095e..0d226bc13a66b41d043e552d847d668d72e70d6e 100644 --- a/configs/arduino-due/src/sam_boot.c +++ b/configs/arduino-due/src/sam_boot.c @@ -1,7 +1,7 @@ -/************************************************************************************ +/**************************************************************************** * configs/arduino-due/src/sam_boot.c * - * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2015, 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -31,11 +31,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -45,27 +45,20 @@ #include "arduino-due.h" -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_boardinitialize * * Description: - * All SAM3X architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All SAM3/4 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. * - ************************************************************************************/ + ****************************************************************************/ void sam_boardinitialize(void) { @@ -75,3 +68,25 @@ void sam_boardinitialize(void) board_autoled_initialize(); #endif } + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ + /* Perform board-specific initialization */ + + (void)sam_bringup(); +} +#endif diff --git a/configs/arduino-due/src/sam_bringup.c b/configs/arduino-due/src/sam_bringup.c new file mode 100644 index 0000000000000000000000000000000000000000..298a5b0dbb9704828450ed394b3629a041c9ed73 --- /dev/null +++ b/configs/arduino-due/src/sam_bringup.c @@ -0,0 +1,123 @@ +/**************************************************************************** + * config/arduino-due/src/sam_bringup.c + * + * Copyright (C) 2013, 2016, 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "arduino-due.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_ARDUINO_ITHEAD_TFT) && defined(CONFIG_SPI_BITBANG) && \ + defined(CONFIG_MMCSD_SPI) +/* Support for the SD card slot on the ITEAD TFT shield */ +/* Verify NSH PORT and SLOT settings */ + +# define SAM34_MMCSDSLOTNO 0 /* There is only one slot */ + +# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != SAM34_MMCSDSLOTNO +# error Only one MMC/SD slot: Slot 0 (CONFIG_NSH_MMCSDSLOTNO) +# endif + +/* Default MMC/SD minor number */ + +# ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +# endif +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int sam_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR,"ERROR: Failed to mount procfs at /proc: %d\n", + ret); + } +#endif + +#if defined(CONFIG_ARDUINO_ITHEAD_TFT) && defined(CONFIG_SPI_BITBANG) && \ + defined(CONFIG_MMCSD_SPI) + /* Initialize the SPI-based MMC/SD slot */ + + { + int ret = sam_sdinitialize(CONFIG_NSH_MMCSDMINOR); + if (ret < 0) + { + syslog(LOG_ERR, + "board_app_initialize: Failed to initialize MMC/SD slot: %d\n", + ret); + return ret; + } + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/configs/avr32dev1/include/board.h b/configs/avr32dev1/include/board.h index 75ab88a9972bb8b64758971973a0b54d94f8f782..5154cfadb0ddb8b14a0760a27b53ba6e2b0963c7 100644 --- a/configs/avr32dev1/include/board.h +++ b/configs/avr32dev1/include/board.h @@ -160,45 +160,5 @@ #define BUTTON1 1 /* Bit 0: Button 1 */ #define BUTTON2 2 /* Bit 1: Button 2 */ -/************************************************************************************ - * Public Types - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: avr32_boardinitialize - * - * Description: - * All AVR32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void avr32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_AVR32DEV1_INCLUDE_BOARD_H */ diff --git a/configs/bambino-200e/include/board.h b/configs/bambino-200e/include/board.h index 9f33f9aea7270ffd214145dd94cb222be86dd8de..e7d82180fd4bb0f8899278f4f2a7c11bb549df7f 100644 --- a/configs/bambino-200e/include/board.h +++ b/configs/bambino-200e/include/board.h @@ -141,6 +141,8 @@ #endif +#define BOARD_MAIN_CLK BOARD_FCCO_FREQUENCY /* Main clock frequency */ + /* This is the clock setup we configure for: * * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for source @@ -179,6 +181,10 @@ #define BOARD_SSP1_CLKSRC BASE_SSP1_CLKSEL_IDIVA #define BOARD_SSP1_BASEFREQ BOARD_IDIVA_FREQUENCY +/* SDIO Clocking */ + +#define BOARD_SDIO_CLKSRC BASE_SDIO_CLKSEL_PLL1 + /* USB0 ********************************************************************/ /* Settings needed in lpc43_cpu.c */ @@ -218,6 +224,41 @@ # define BOARD_SPIFI_FREQUENCY (102000000) /* 204MHz / 14 = 14.57MHz */ #endif +/* SD/MMC or SDIO interface + * + * NOTE: The SDIO function clock to the interface can be up to 50 MHZ. + * Example: BOARD_MAIN_CLK=220MHz, CLKDIV=5, Finput=44MHz. + */ + +#define BOARD_SDMMC_MAXFREQ 50000000 +#define BOARD_SDMMC_CEIL(a,b) (((a) + (b) - 1) / (b)) + +#define BOARD_SDMMC_CLKDIV BOARD_SDMMC_CEIL(BOARD_MAIN_CLK, BOARD_SDMMC_MAXFREQ) +#define BOARD_SDMMC_FREQUENCY (BOARD_MAIN_CLK / BOARD_SDMMC_CLKDIV) + +/* Mode-dependent function clock division + * + * Example: BOARD_SDMMC_FREQUENCY=44MHz + * BOARD_CLKDIV_INIT=110, Fsdmmc=400KHz (400KHz max) + * BOARD_CLKDIV_MMCXFR=4[3], Fsdmmc=11Mhz (20MHz max) See NOTE: + * BOARD_CLKDIV_SDWIDEXFR=2, Fsdmmc=22MHz (25MHz max) + * BOARD_CLKDIV_SDXFR=2, Fsdmmc=22MHz (25MHz max) + * + * NOTE: Clock division is 2*n. For example, value of 0 means divide by + * 2 * 0 = 0 (no division, bypass), value of 1 means divide by 2 * 1 = 2, value + * of 255 means divide by 2 * 255 = 510, and so on. + * + * SD/MMC logic will write the value ((clkdiv + 1) >> 1) as the divisor. So an + * odd value calculated below will be moved up to next higher divider value. So + * the value 3 will cause 2 to be written as the divider value and the effective + * divider will be 4. + */ + +#define BOARD_CLKDIV_INIT BOARD_SDMMC_CEIL(BOARD_SDMMC_FREQUENCY, 400000) +#define BOARD_CLKDIV_MMCXFR BOARD_SDMMC_CEIL(BOARD_SDMMC_FREQUENCY, 20000000) +#define BOARD_CLKDIV_SDWIDEXFR BOARD_SDMMC_CEIL(BOARD_SDMMC_FREQUENCY, 25000000) +#define BOARD_CLKDIV_SDXFR BOARD_SDMMC_CEIL(BOARD_SDMMC_FREQUENCY, 25000000) + /* UART clocking ***********************************************************/ /* Configure all U[S]ARTs to use the XTAL input frequency */ @@ -315,45 +356,14 @@ #define GPIO_ENET_RESET (GPIO_MODE_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN4) #define PINCONF_ENET_MDC PINCONF_ENET_MDC_3 -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ +/* SD/MMC pinout */ -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: lpc43_boardinitialize - * - * Description: - * All LPC43xx architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ****************************************************************************/ - -void lpc43_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif +#define GPIO_SD_CARD_DET_N PINCONF_SD_CD_1 +#define GPIO_SD_D0 PINCONF_SD_DAT0_1 +#define GPIO_SD_D1 PINCONF_SD_DAT1_1 +#define GPIO_SD_D2 PINCONF_SD_DAT2_1 +#define GPIO_SD_D3 PINCONF_SD_DAT3_1 +#define GPIO_SD_CMD PINCONF_SD_CMD_1 +#define GPIO_SD_CLK CLKCONF_SD_CLK_2 -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_BAMBINO_200E_INCLUDE_BOARD_H */ diff --git a/configs/bambino-200e/src/bambino-200e.h b/configs/bambino-200e/src/bambino-200e.h index 9a0b85680141c4144b513716407c2ad9b0b83dff..b8805955f8b74bd471fc1e79ed53f709397c3f8c 100644 --- a/configs/bambino-200e/src/bambino-200e.h +++ b/configs/bambino-200e/src/bambino-200e.h @@ -51,6 +51,8 @@ * Pre-processor Definitions ****************************************************************************/ +#define HAVE_MMCSD 1 + /**************************************************************************** * LEDs GPIO PIN SIGNAL NAME * -------------------------------- ------- -------------- @@ -99,6 +101,36 @@ # endif #endif +/* MMC/SD support */ + +#ifdef CONFIG_LPC43_SDMMC + +# ifndef CONFIG_MMCSD +# warning MMC/SD support requires CONFIG_MMCSD +# undef HAVE_MMCSD +# endif + +# ifndef CONFIG_MMCSD_SDIO +# warning MMC/SD support requires CONFIG_MMCSD_SDIO +# undef HAVE_MMCSD +# endif + +# ifdef CONFIG_DISABLE_MOUNTPOINT +# warning MMC/SD cannot be supported with CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_MMCSD +# endif + +# ifdef CONFIG_NSH_MMCSDMINOR +# define MMCSD_MINOR CONFIG_NSH_MMCSDMINOR +# else +# define MMCSD_MINOR 0 +# endif + +#else +# undef HAVE_MMCSD +#endif + + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/configs/bambino-200e/src/lpc43_appinit.c b/configs/bambino-200e/src/lpc43_appinit.c index c00e4979324be65b76b10a462495c01fcc1046b0..6e1efa0b336ba334cd80c6a66d4dafae6fdb9903 100644 --- a/configs/bambino-200e/src/lpc43_appinit.c +++ b/configs/bambino-200e/src/lpc43_appinit.c @@ -58,6 +58,12 @@ # endif #endif +#ifdef CONFIG_LPC43_SDMMC +# include +# include +# include "lpc43_sdmmc.h" +#endif + #include "bambino-200e.h" /**************************************************************************** @@ -162,15 +168,42 @@ static int nsh_spifi_initialize(void) int board_app_initialize(uintptr_t arg) { +#ifdef HAVE_MMCSD + struct sdio_dev_s *sdmmc; +#endif + int ret = 0; + /* Initialize the SPIFI block device */ (void)nsh_spifi_initialize(); +#ifdef HAVE_MMCSD + /* Get an instance of the SDIO interface */ + + sdmmc = lpc43_sdmmc_initialize(0); + if (!sdmmc) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SD/MMC\n"); + } + else + { + /* Bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(MMCSD_MINOR, sdmmc); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + } + } +#endif + #ifdef CONFIG_TIMER /* Registers the timers */ lpc43_timerinitialize(); #endif - return 0; + return ret; } diff --git a/configs/bambino-200e/src/lpc43_buttons.c b/configs/bambino-200e/src/lpc43_buttons.c index 8f96dafd27413c42b82c0a01858b74820b6b1753..7985221aa231c814294a820755d3037821262c80 100644 --- a/configs/bambino-200e/src/lpc43_buttons.c +++ b/configs/bambino-200e/src/lpc43_buttons.c @@ -61,7 +61,7 @@ * by the BUTTON_* definitions in board.h */ -static const uint16_t g_buttoncfg[BOARD_NUM_BUTTONS] = +static const uint16_t g_buttoncfg[NUM_BUTTONS] = { BAMBINO_BUT1 }; @@ -71,7 +71,7 @@ static const uint16_t g_buttoncfg[BOARD_NUM_BUTTONS] = * numbers. */ -static uint8_t g_buttonirq[BOARD_NUM_BUTTONS] = +static uint8_t g_buttonirq[NUM_BUTTONS] = { BAMBINO_BUT1_IRQ }; @@ -98,7 +98,7 @@ void board_button_initialize(void) /* Configure the GPIO pins as interrupting inputs. */ - for (i = 0; i < BOARD_NUM_BUTTONS; i++) + for (i = 0; i < NUM_BUTTONS; i++) { lpc43_configgpio(g_buttoncfg[i]); } @@ -127,7 +127,7 @@ uint32_t board_buttons(void) /* Check that state of each key */ - for (i = 0; i < BOARD_NUM_BUTTONS; i++) + for (i = 0; i < NUM_BUTTONS; i++) { /* A LOW value means that the key is pressed. */ @@ -172,7 +172,7 @@ int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) /* Verify that the button ID is within range */ - if ((unsigned)id < BOARD_NUM_BUTTONS) + if ((unsigned)id < NUM_BUTTONS) { /* Disable interrupts until we are done */ diff --git a/configs/cc3200-launchpad/include/board.h b/configs/cc3200-launchpad/include/board.h index 2b0885beea5625d29544e284f528d62428717db5..d08476a040892a8c4b3d95f43fb892cbb19137db 100644 --- a/configs/cc3200-launchpad/include/board.h +++ b/configs/cc3200-launchpad/include/board.h @@ -174,23 +174,4 @@ #define BUTTON_SW2_BIT (1 << BUTTON_SW2) #define BUTTON_SW3_BIT (1 << BUTTON_SW3) -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Name: tiva_boardinitialize - * - * Description: - * All Tiva architectures must provide the following entry point. This entry - * point is called early in the initialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void tiva_boardinitialize(void); - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_CC3200_LAUNCHPAD_INCLUDE_BOARD_H */ diff --git a/configs/clicker2-stm32/Kconfig b/configs/clicker2-stm32/Kconfig index 572a3498ff71c6ec4f1e02a27cff9c532cf0c533..06af60e12c620a1afdbb979707ce3c316c5d3ea3 100644 --- a/configs/clicker2-stm32/Kconfig +++ b/configs/clicker2-stm32/Kconfig @@ -166,4 +166,13 @@ config CLICKER2_STM32_SYSLOG_FILE_DELAY endif # CLICKER2_STM32_SYSLOG_FILE +config CLICKER2_STM32_RNDIS_MACADDR + hex "RNDIS MAC address" + default 0xfadedeadbeef + depends on RNDIS + ---help--- + If the hardware has no built-in MAC address then the fixed, + software-assigned MAC address MAC address must provided + with this selection. + endif # ARCH_BOARD_CLICKER2_STM32 diff --git a/configs/clicker2-stm32/include/board.h b/configs/clicker2-stm32/include/board.h index 7f757d495164efd67df69cb00074030f51b59a90..fb92f4db54c342a7cfd5c4426c63d3aab2a38bde 100644 --- a/configs/clicker2-stm32/include/board.h +++ b/configs/clicker2-stm32/include/board.h @@ -327,41 +327,4 @@ #define DMAMAP_SDIO DMAMAP_SDIO_1 -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_CLICKER2_STM32_INCLUDE_BOARD_H */ diff --git a/configs/clicker2-stm32/mrf24j40-6lowpan/defconfig b/configs/clicker2-stm32/mrf24j40-6lowpan/defconfig index 0abdcd3d691649419c1e0993163dad03e7b41ff6..29836303738f8a068e6942d238f8fa5c697e9544 100644 --- a/configs/clicker2-stm32/mrf24j40-6lowpan/defconfig +++ b/configs/clicker2-stm32/mrf24j40-6lowpan/defconfig @@ -1,7 +1,6 @@ # CONFIG_DEV_CONSOLE is not set # CONFIG_NET_ETHERNET is not set # CONFIG_NET_IPv4 is not set -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NSH_DISABLE_TELNETD is not set CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BOARD="clicker2-stm32" @@ -47,7 +46,7 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_IND_PREALLOC=32 +CONFIG_IEEE802154_MAC=y CONFIG_IEEE802154_MACDEV=y CONFIG_IEEE802154_MRF24J40=y CONFIG_IEEE802154_NETDEV=y @@ -55,7 +54,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_IOB_BUFSIZE=128 CONFIG_IOB_NBUFFERS=32 CONFIG_IOB_NCHAINS=16 -CONFIG_MAC802154_NNOTIF=48 CONFIG_MAC802154_NTXDESC=32 CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 diff --git a/configs/clicker2-stm32/mrf24j40-mac/defconfig b/configs/clicker2-stm32/mrf24j40-mac/defconfig index 2b48ad0f119ee88ce953e17096671f01a98d5e59..cfad7c2ba98945ce5e7e650e56b3e330d40d9b1c 100644 --- a/configs/clicker2-stm32/mrf24j40-mac/defconfig +++ b/configs/clicker2-stm32/mrf24j40-mac/defconfig @@ -1,11 +1,11 @@ -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD_CLICKER2_STM32=y +CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="arm" CONFIG_BOARD_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y @@ -24,21 +24,20 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y CONFIG_EXAMPLES_NSH=y CONFIG_FS_PROCFS=y CONFIG_FS_WRITABLE=y -CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y CONFIG_IEEE802154_MACDEV=y CONFIG_IEEE802154_MRF24J40=y CONFIG_INTELHEX_BINARY=y -CONFIG_MAC802154_NNOTIF=6 CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_STREAMS=8 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y -# CONFIG_NSH_CMDOPT_DF_H is not set CONFIG_NSH_DISABLE_GET=y CONFIG_NSH_DISABLE_IFUPDOWN=y CONFIG_NSH_DISABLE_PUT=y @@ -49,14 +48,14 @@ CONFIG_NSH_READLINE=y CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_WDOGS=8 -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAMLOG=y CONFIG_RAM_SIZE=131072 CONFIG_RAM_START=0x20000000 +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAMLOG=y CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORKPRIORITY=192 CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 CONFIG_SCHED_WAITPID=y CONFIG_SDCLONE_DISABLE=y CONFIG_START_YEAR=2013 diff --git a/configs/clicker2-stm32/mrf24j40-starhub/defconfig b/configs/clicker2-stm32/mrf24j40-starhub/defconfig index 16f8a8d1a2482be83cb78b207a54c4df42549ab5..84f40e14d45f64592cf38c55ce4442ac9a481356 100644 --- a/configs/clicker2-stm32/mrf24j40-starhub/defconfig +++ b/configs/clicker2-stm32/mrf24j40-starhub/defconfig @@ -1,7 +1,6 @@ # CONFIG_DEV_CONSOLE is not set # CONFIG_NET_ETHERNET is not set # CONFIG_NET_IPv4 is not set -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NSH_DISABLE_TELNETD is not set CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BOARD="clicker2-stm32" @@ -30,7 +29,7 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_IND_PREALLOC=32 +CONFIG_IEEE802154_MAC=y CONFIG_IEEE802154_MACDEV=y CONFIG_IEEE802154_MRF24J40=y CONFIG_IEEE802154_NETDEV=y @@ -38,7 +37,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_IOB_BUFSIZE=128 CONFIG_IOB_NBUFFERS=32 CONFIG_IOB_NCHAINS=16 -CONFIG_MAC802154_NNOTIF=48 CONFIG_MAC802154_NTXDESC=32 CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 diff --git a/configs/clicker2-stm32/mrf24j40-starpoint/defconfig b/configs/clicker2-stm32/mrf24j40-starpoint/defconfig index 5e13b8a4474320c5ce84fd0cdf4d1f11e2974d64..5d300bf367687d0e098f1c6c0a6ec6ea374f1434 100644 --- a/configs/clicker2-stm32/mrf24j40-starpoint/defconfig +++ b/configs/clicker2-stm32/mrf24j40-starpoint/defconfig @@ -1,7 +1,6 @@ # CONFIG_DEV_CONSOLE is not set # CONFIG_NET_ETHERNET is not set # CONFIG_NET_IPv4 is not set -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NSH_DISABLE_TELNETD is not set CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BOARD="clicker2-stm32" @@ -47,7 +46,7 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_IND_PREALLOC=32 +CONFIG_IEEE802154_MAC=y CONFIG_IEEE802154_MACDEV=y CONFIG_IEEE802154_MRF24J40=y CONFIG_IEEE802154_NETDEV=y @@ -55,7 +54,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_IOB_BUFSIZE=128 CONFIG_IOB_NBUFFERS=32 CONFIG_IOB_NCHAINS=16 -CONFIG_MAC802154_NNOTIF=48 CONFIG_MAC802154_NTXDESC=32 CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 diff --git a/configs/clicker2-stm32/src/stm32_appinit.c b/configs/clicker2-stm32/src/stm32_appinit.c index 18840ceeab712dfb038f8ee41699b2c401193371..74e4d24c578056ed19f222a5ca50c95994f3b911 100644 --- a/configs/clicker2-stm32/src/stm32_appinit.c +++ b/configs/clicker2-stm32/src/stm32_appinit.c @@ -98,7 +98,7 @@ int board_app_initialize(uintptr_t arg) if (ret < 0) { syslog(LOG_ERR, "ERROR: stm32_bringup() failed: %d\n", ret); - return ret + return ret; } #endif diff --git a/configs/clicker2-stm32/src/stm32_bringup.c b/configs/clicker2-stm32/src/stm32_bringup.c index ec3abe242c01bae43cce1a6853f20799eee45cd5..7b0ba27bec40d85c03cf0f0f68da0380dfc1ab3f 100644 --- a/configs/clicker2-stm32/src/stm32_bringup.c +++ b/configs/clicker2-stm32/src/stm32_bringup.c @@ -52,9 +52,24 @@ # include #endif +#ifdef CONFIG_RNDIS +# include +# include +#endif + #include "stm32.h" #include "clicker2-stm32.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_RNDIS +# ifndef CONFIG_CLICKER2_STM32_RNDIS_MACADDR +# define CONFIG_CLICKER2_STM32_RNDIS_MACADDR 0xfadedeadbeef +# endif +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -168,6 +183,25 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_RNDIS + uint8_t mac[IFHWADDRLEN]; + + mac[0] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 5)) & 0xff; + mac[1] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 4)) & 0xff; + mac[2] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 3)) & 0xff; + mac[3] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 2)) & 0xff; + mac[4] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 1)) & 0xff; + mac[5] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 0)) & 0xff; + + /* Register USB RNDIS Driver */ + + ret = usbdev_rndis_initialize(mac); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: usbdev_rndis_initialize() failed %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/configs/clicker2-stm32/src/stm32_mrf24j40.c b/configs/clicker2-stm32/src/stm32_mrf24j40.c index bab336cafa1fcdb13b1baa818a117b7908214a3a..e3732fefd9897e830d6f918eb9d2294f9e6f9355 100644 --- a/configs/clicker2-stm32/src/stm32_mrf24j40.c +++ b/configs/clicker2-stm32/src/stm32_mrf24j40.c @@ -290,6 +290,7 @@ static int stm32_mrf24j40_devsetup(FAR struct stm32_priv_s *priv) } #endif + UNUSED(ret); return OK; } diff --git a/configs/cloudctrl/README.txt b/configs/cloudctrl/README.txt index 4ef93e2fc8e9ee3912d62941a4bc04d955876565..486b2693c0a63b5cd00ca69245e05e643596ac62 100644 --- a/configs/cloudctrl/README.txt +++ b/configs/cloudctrl/README.txt @@ -20,12 +20,6 @@ Contents ======== - STM32F107VCT Pin Usage - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI buildroot Toolchain - - NuttX OABI buildroot Toolchain - - NXFLAT Toolchain - Cloudctrl-specific Configuration Options - LEDs - Cloudctrl-specific Configuration Options @@ -167,244 +161,6 @@ PN NAME SIGNAL NOTES 19 VSSA VSSA 20 VREF- VREF- -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment because the development tools that I used only work under Windows. - -GNU Toolchain Options -===================== - - Toolchain Configurations - ------------------------ - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The Atollic Toolchain, - 3. The devkitARM GNU toolchain, - 4. Raisonance GNU toolchain, or - 5. The NuttX buildroot Toolchain (see below). - - Most testing has been conducted using the CodeSourcery toolchain for Windows and - that is the default toolchain in most configurations. To use the Atollic, - devkitARM, Raisonance GNU, or NuttX buildroot toolchain, you simply need to - add one of the following configuration options to your .config (or defconfig) - file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : The Atollic toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE=y : Raisonance RIDE7 under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE: the CodeSourcery (for Windows), Atollic, devkitARM, and Raisonance toolchains are - Windows native toolchains. The CodeSourcery (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - The CodeSourcery Toolchain (2009q1) - ----------------------------------- - The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - The Atollic "Pro" and "Lite" Toolchain - -------------------------------------- - One problem that I had with the Atollic toolchains is that the provide a gcc.exe - and g++.exe in the same bin/ file as their ARM binaries. If the Atollic bin/ path - appears in your PATH variable before /usr/bin, then you will get the wrong gcc - when you try to build host executables. This will cause to strange, uninterpretable - errors build some host binaries in tools/ when you first make. - - The Atollic "Lite" Toolchain - ---------------------------- - The free, "Lite" version of the Atollic toolchain does not support C++ nor - does it support ar, nm, objdump, or objdcopy. If you use the Atollic "Lite" - toolchain, you will have to set: - - CONFIG_HAVE_CXX=n - - In order to compile successfully. Otherwise, you will get errors like: - - "C++ Compiler only available in TrueSTUDIO Professional" - - The make may then fail in some of the post link processing because of some of - the other missing tools. The Make.defs file replaces the ar and nm with - the default system x86 tool versions and these seem to work okay. Disable all - of the following to avoid using objcopy: - - CONFIG_RRLOAD_BINARY=n - CONFIG_INTELHEX_BINARY=n - CONFIG_MOTOROLA_SREC=n - CONFIG_RAW_BINARY=n - - devkitARM - --------- - The devkitARM toolchain includes a version of MSYS make. Make sure that the - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/stm32, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by RIDE. - -NuttX EABI buildroot Toolchain -============================== - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh shenzhou/ - - cd .. - make context - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Edit nuttx/.config to select the buildroot toolchain as described above - and below: - - -CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y - +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y - - 9. Set the PATH variable so tht it includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - detailed PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - LEDs ==== @@ -844,7 +600,5 @@ Where is one of the following: This builds the THTTPD web server example using the THTTPD and the apps/examples/thttpd application. - NOTE: See note above with regard to the EABI/OABI buildroot - toolchains. This example can only be built using the older - OABI toolchain due to incompatibilities introduced in later - GCC releases. + NOTE: This example can only be built using older GCC toolchains + due to incompatibilities introduced in later GCC releases. diff --git a/configs/cloudctrl/include/board.h b/configs/cloudctrl/include/board.h index 14c7fab32f311e799ace1f9784d4e7b3430fa9cc..87c899de6ec04a2dd4fc072f89857f502e83ee78 100644 --- a/configs/cloudctrl/include/board.h +++ b/configs/cloudctrl/include/board.h @@ -310,17 +310,6 @@ extern "C" { /************************************************************************************ * Public Function Prototypes ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); /************************************************************************************ * Name: stm32_lcdclear diff --git a/configs/demo9s12ne64/include/board.h b/configs/demo9s12ne64/include/board.h index 0fc3ed6dec5f21afe42de0e0f52ba44ab8a3b42b..1120d9b7778808c595c23f204a80c1f1a84b524f 100644 --- a/configs/demo9s12ne64/include/board.h +++ b/configs/demo9s12ne64/include/board.h @@ -90,39 +90,4 @@ /* Button definitions ***************************************************************/ -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: hcs12_boardinitialize - * - * Description: - * All HCS12 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void hcs12_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/dk-tm4c129x/include/board.h b/configs/dk-tm4c129x/include/board.h index 3c2827859d33ba93c1d78e6b1e68de07e40cf84c..5279f43cf3264bd6efca01e6bd4c172eef5b179e 100644 --- a/configs/dk-tm4c129x/include/board.h +++ b/configs/dk-tm4c129x/include/board.h @@ -249,18 +249,6 @@ #ifndef __ASSEMBLY__ -/************************************************************************************ - * Name: tiva_boardinitialize - * - * Description: - * All Tiva architectures must provide the following entry point. This entry - * point is called early in the initialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void tiva_boardinitialize(void); - /************************************************************************************ * Name: tiva_tmp100_initialize * diff --git a/configs/ea3131/include/board.h b/configs/ea3131/include/board.h index f41a26d2ac394a021605a37745da417fe1a8acb7..c3d6bac05fc53d1ade568d6bdec4879b82a77f7a 100644 --- a/configs/ea3131/include/board.h +++ b/configs/ea3131/include/board.h @@ -113,40 +113,4 @@ /* Button definitions ***************************************************************/ -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: lpc31_boardinitialize - * - * Description: - * All LPC31XX architectures must provide the following entry point. This entry - * point is called early in the intitialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void lpc31_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/ea3152/include/board.h b/configs/ea3152/include/board.h index b641383325fee38ca6cf44030e364018baf9b51a..c8f1f095711ce855408b0ba2e335274796b85c34 100644 --- a/configs/ea3152/include/board.h +++ b/configs/ea3152/include/board.h @@ -113,39 +113,4 @@ /* Button definitions ***************************************************************/ -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: lpc31_boardinitialize - * - * Description: - * All LPC31XX architectures must provide the following entry point. This entry - * point is called early in the intitialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void lpc31_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/eagle100/README.txt b/configs/eagle100/README.txt index f58ba90bb19a31dc1c6845d3aa4ce524270d137b..8c379b10dfe884ad29acd8d856eccbae445203f3 100644 --- a/configs/eagle100/README.txt +++ b/configs/eagle100/README.txt @@ -9,155 +9,6 @@ References: Micromint: http://www.micromint.com/ Luminary: http://www.luminarymicro.com/ -Development Environment -^^^^^^^^^^^^^^^^^^^^^^^ - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment because the Luminary FLASH programming application was used for - writing to FLASH and this application works only under Windows. - -GNU Toolchain Options -^^^^^^^^^^^^^^^^^^^^^ - - The NuttX make system has been modified to support the multiple toolchain - options including: - - 1. The CodeSourcery GNU toolchain, - 2. The devkitARM GNU toolchain, - 3. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the NuttX buildroot toolchain. However, - the make system is setup to default to use the devkitARM toolchain. To use - the CodeSourcery or devkitARM, you simply need to add one of the following - configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE: the CodeSourcery (for Windows) and devkitARM are Windows native toolchains. - The CodeSourcey (for Linux) and NuttX buildroot toolchains are Cygwin and/or Linux - native toolchains. There are several limitations to using a Windows based - toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -NuttX EABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh eagle100/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - When building the buildroot toolchain, either (1) modify the - cortexm3-eabi-defconfig-4.6.3 configuration to use EABI (using - 'make menuconfig'), or (2) use an exising OABI configuration such - as cortexm3-defconfig-4.3.3 - -NXFLAT Toolchain -^^^^^^^^^^^^^^^^ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - Ethernet-Bootloader ^^^^^^^^^^^^^^^^^^^ diff --git a/configs/eagle100/include/board.h b/configs/eagle100/include/board.h index b2a652db8f4b47fbdfd1a3c3a6f2a313f976770f..2bbb9899026f69628a6ff57b9e0c4bc5ea057a9e 100644 --- a/configs/eagle100/include/board.h +++ b/configs/eagle100/include/board.h @@ -105,23 +105,4 @@ #define LED_ASSERTION 6 /* ON OFF */ #define LED_PANIC 7 /* ON OFF */ -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Name: tiva_boardinitialize - * - * Description: - * All Stellaris architectures must provide the following entry point. This entry - * point is called early in the intitialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void tiva_boardinitialize(void); - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/ekk-lm3s9b96/README.txt b/configs/ekk-lm3s9b96/README.txt index 26ee59d69ea91e3de50d8c49ad6bad97d4e2cf08..8e4b3da0004a2fcc8f276b2a1f5e79d48168f280 100644 --- a/configs/ekk-lm3s9b96/README.txt +++ b/configs/ekk-lm3s9b96/README.txt @@ -7,12 +7,6 @@ Contents ^^^^^^^^ Stellaris EKK-LM3S9B96 Evaluation Kit - Development Environment - GNU Toolchain Options - IDEs - NuttX EABI "buildroot" Toolchain - NuttX OABI "buildroot" Toolchain - NXFLAT Toolchain Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options Configurations @@ -79,197 +73,6 @@ PIN SIGNAL EVB Function 83 PH3/USB0EPEN USB-OTG power switch 76 PH4/USB0PFLT Overcurrent input status from USB-OTG power switch -Development Environment -^^^^^^^^^^^^^^^^^^^^^^^ - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -^^^^^^^^^^^^^^^^^^^^^ - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The devkitARM GNU toolchain, - 3. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the NuttX buildroot toolchain. However, - the make system is setup to default to use the devkitARM toolchain. To use - the CodeSourcery or devkitARM, you simply need to add one of the following - configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE: the CodeSourcery (for Windows) and devkitARM are Windows native toolchains. - The CodeSourcey (for Linux) and NuttX buildroot toolchains are Cygwin and/or Linux - native toolchains. There are several limitations to using a Windows based - toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - - NOTE 3: I recently (i.e., late 2011) tried building with the CodeSourcery Windows - toolchain. The code worked but required 40 seconds to boot (or even until the - status LED illuminates)!! Know idea why. With the buildroot tools, boot time is - a couple of seconds. - -IDEs -^^^^ - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lm, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/tiva/tiva_vectors.S. - -NuttX EABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh ekk-lm3s9b96/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you - are building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -^^^^^^^^^^^^^^^^ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/configs/ekk-lm3s9b96/include/board.h b/configs/ekk-lm3s9b96/include/board.h index 1669d330095d22b4a91229466ef0c86e67888bd2..c137bceb870131eecf3dbac105e80c6ccb88ab09 100644 --- a/configs/ekk-lm3s9b96/include/board.h +++ b/configs/ekk-lm3s9b96/include/board.h @@ -106,23 +106,4 @@ #define LED_ASSERTION 6 /* ON OFF */ #define LED_PANIC 7 /* ON OFF */ -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Name: tiva_boardinitialize - * - * Description: - * All Stellaris architectures must provide the following entry point. This entry - * point is called early in the intitialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void tiva_boardinitialize(void); - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/fire-stm32v2/README.txt b/configs/fire-stm32v2/README.txt index a422d00cf45f71c10dea5915e687be3267c78c4d..dbcf912a22ef7ef77f42ef05238710d11343d262 100644 --- a/configs/fire-stm32v2/README.txt +++ b/configs/fire-stm32v2/README.txt @@ -12,12 +12,6 @@ Contents ======== - Pin Configuration - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - DFU and JTAG - OpenOCD - LEDs @@ -159,235 +153,6 @@ PIN NAME SIGNAL NOTES 99 VSS_3 DGND 100 VDD_3 3V3 -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment because the CodeSourcery Toolchain. - -GNU Toolchain Options -===================== - - Toolchain Configurations - ------------------------ - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The Atollic Toolchain, - 3. The devkitARM GNU toolchain, - 4. Raisonance GNU toolchain, or - 5. The NuttX buildroot Toolchain (see below). - - Most testing has been conducted using the CodeSourcery toolchain for Windows and - that is the default toolchain in most configurations. To use the Atollic, - devkitARM, Raisonance GNU, or NuttX buildroot toolchain, you simply need to - add one of the following configuration options to your .config (or defconfig) - file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : The Atollic toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE=y : Raisonance RIDE7 under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE: the CodeSourcery (for Windows), Atollic, devkitARM, and Raisonance toolchains are - Windows native toolchains. The CodeSourcery (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - The CodeSourcery Toolchain (2009q1) - ----------------------------------- - The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - The Atollic "Pro" and "Lite" Toolchain - -------------------------------------- - One problem that I had with the Atollic toolchains is that the provide a gcc.exe - and g++.exe in the same bin/ file as their ARM binaries. If the Atollic bin/ path - appears in your PATH variable before /usr/bin, then you will get the wrong gcc - when you try to build host executables. This will cause to strange, uninterpretable - errors build some host binaries in tools/ when you first make. - - The Atollic "Lite" Toolchain - ---------------------------- - The free, "Lite" version of the Atollic toolchain does not support C++ nor - does it support ar, nm, objdump, or objdcopy. If you use the Atollic "Lite" - toolchain, you will have to set: - - CONFIG_HAVE_CXX=n - - In order to compile successfully. Otherwise, you will get errors like: - - "C++ Compiler only available in TrueSTUDIO Professional" - - The make may then fail in some of the post link processing because of some of - the other missing tools. The Make.defs file replaces the ar and nm with - the default system x86 tool versions and these seem to work okay. Disable all - of the following to avoid using objcopy: - - CONFIG_RRLOAD_BINARY=n - CONFIG_INTELHEX_BINARY=n - CONFIG_MOTOROLA_SREC=n - CONFIG_RAW_BINARY=n - - devkitARM - --------- - The devkitARM toolchain includes a version of MSYS make. Make sure that the - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/stm32, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/stm32/stm32_vectors.S. You many have to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by an IDE. - -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh fire-stm32v2/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - DFU and JTAG ============ diff --git a/configs/fire-stm32v2/include/board.h b/configs/fire-stm32v2/include/board.h index 3807bff43c8402779bbc9667b7d500a99106fe30..dad4d09ab6b80832281d4a595eb5a73d67f18824 100644 --- a/configs/fire-stm32v2/include/board.h +++ b/configs/fire-stm32v2/include/board.h @@ -380,17 +380,6 @@ extern "C" /************************************************************************************ * Public Function Prototypes ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); /************************************************************************************ * Name: fire_lcdclear diff --git a/configs/fire-stm32v2/nsh/defconfig b/configs/fire-stm32v2/nsh/defconfig index 122c67c5f28e7198b598b055caebb1a6c56a60c3..27651d312f249f4ac4d0ebcc508a39e6cba6e3f5 100644 --- a/configs/fire-stm32v2/nsh/defconfig +++ b/configs/fire-stm32v2/nsh/defconfig @@ -1,4 +1,4 @@ -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set diff --git a/configs/stm32f0discovery/Kconfig b/configs/flipnclick-pic32mz/Kconfig similarity index 80% rename from configs/stm32f0discovery/Kconfig rename to configs/flipnclick-pic32mz/Kconfig index f1776ced8b0d1331b61b6de21a5e9daac586e37f..109d9a47f37b61662703e7d75d7ddb838b2dfb4a 100644 --- a/configs/stm32f0discovery/Kconfig +++ b/configs/flipnclick-pic32mz/Kconfig @@ -3,6 +3,5 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -if ARCH_BOARD_STM32F0_DISCOVERY - +if ARCH_BOARD_FLIPNCLICK_PIC32MZ endif diff --git a/configs/flipnclick-pic32mz/README.txt b/configs/flipnclick-pic32mz/README.txt new file mode 100644 index 0000000000000000000000000000000000000000..000cda2fcc0b43686d5a2493a023704476bb045f --- /dev/null +++ b/configs/flipnclick-pic32mz/README.txt @@ -0,0 +1,275 @@ +configs/flipnclick-pic32mz README +=============================== + + This README file discusses the port of NuttX to the Mikroe Flip&Click + PIC32MZ board. That board features the PIC32MZ2048EFH100 MCU. + + Thanks to John Legg for contributing the Flip&Click PIC32MZ board! + +Contents +======== + + Port Status + On Board Debug Support + Creating Compatible NuttX HEX files + Tool Issues + Serial Console + LEDs + Configurations + +Port Status +=========== + + 2018-01-07: Added architecture support for the PIC32MZ2048EFH100 used on + the Flip&Click PIC32MZ board. + 2018-01-08: Created the basic board configuration for the Mikroe + Flip&Click PIC32MZ board. No testing has yet been performed. At this + point, I have not even figured out how I am going to load and debug + new firmware. I need understand how the memory map is set up when used + with the mikroBootloader. + +On Board Debug Support +====================== + + There are several debug options: + + 1. Using the Arduino IDE (chipKIT core). This is available on the USB-UART + port between the C and D MikroBUS sockets. Usage is described in the + Flip&Click User Manual. + + I don't think trying to use the Arduino IDE is a good option. + + 2. Using the mikroC USB HID bootloader. This is is available on the USB + port between the A and B MikroBUS sockets. Usage is described in the + Flip&Click User Manual. + + There is a simple application available at Mikroe that will allow you + to write .hex files via the USB HID bootloader. However, in order to + use the bootloader, you will have to control the memory map so that the + downloaded code does not clobber the bootloader. + + At this point, I have found no documentation describing how to build + the code outside of the Mikroe toolchain for use with the Mikroe + bootloader. + + 3. There is an undocumented and unpopulated PICKit3 connector between the + B and C mikroBUS sockets. + + 4. There is an undocumented and unpopulated mikroProg connector between + the A and D mikroBUS sockets. + + Since 3) and 4) are undocumented, this would require some research and + would, most likely, clobber the USB HID bootloader (and possibly the + Arduino support as well). + +Creating Compatible NuttX HEX files +=================================== + + Intel Hex Format Files: + ----------------------- + + When NuttX is built it will produce two files in the top-level NuttX + directory: + + 1) nuttx - This is an ELF file, and + 2) nuttx.hex - This is an Intel Hex format file. This is controlled by + the setting CONFIG_INTELHEX_BINARY in the .config file. + + The PICkit tool wants an Intel Hex format file to burn into FLASH. However, + there is a problem with the generated nutt.hex: The tool expects the nuttx.hex + file to contain physical addresses. But the nuttx.hex file generated from the + top-level make will have address in the KSEG0 and KSEG1 regions. + + tools/pic32mx/mkpichex: + ---------------------- + + There is a simple tool in the NuttX tools/pic32mx directory that can be + used to solve both issues with the nuttx.hex file. But, first, you must + build the tool: + + cd tools/pic32mx + make + + Now you will have an excecutable file call mkpichex (or mkpichex.exe on + Cygwin). This program will take the nutt.hex file as an input, it will + convert all of the KSEG0 and KSEG1 addresses to physical address, and + it will write the modified file, replacing the original nuttx.hex. + + To use this file, you need to do the following things: + + export PATH=??? # Add the NuttX tools/pic32mx directory to your + # PATH variable + make # Build nuttx and nuttx.hex + mkpichex $PWD # Convert addresses in nuttx.hex. $PWD is the path + # to the top-level build directory. It is the only + # required input to mkpichex. + +Tool Issues +=========== + + Segger J-Link + ------------- + If using a Jlink that only these versions work with PIC32: + + J-Link BASE / EDU V9 or later + J-Link ULTRA+ / PRO V4 or later + + This is the command to use: + + JLinkGDBServer -device PIC32MZ2048EFH100 -if 2-wire-JTAG-PIC32 -speed 12000 + +Serial Console +============== + + [REVISIT: I am not sure if the USB VCOM ports are available to the + software. That is likely another serial port option]. + + Convenient U[S]ARTs that may be used as the Serial console include: + + 1) An Arduino Serial Shield. The RX and TX pins are available on the + Arduino connector D0 and D1 pins, respectively. These are connected + to UART5, UART5_RX and UART5_TX which are RD14 and RD15, respectively. + + 2) Mikroe Click Serial Shield. There are four Click bus connectors with + serial ports available as follows: + + Click A: UART4 UART4_RX and UART4_TX which are RG9 and RE3, respectively. + Click B: UART3 UART3_RX and UART3_TX which are RF0 and RF1, respectively. + Click C: UART1 UART1_RX and UART1_TX which are RC1 and RE5, respectively. + Click D: UART2 UART2_RX and UART2_TX which are RC3 and RC2, respectively. + + Other serial ports are probably available on the Arduino connector. I + will leave that as an exercise for the interested reader. + + The outputs from these pins is 3.3V. You will need to connect RS232 + transceiver to get the signals to RS232 levels (or connect to the + USB virtual COM port in the case of UART0). + +LEDs and Buttons +================ + + LEDs + ---- + + There are four LEDs on the top, red side of the board. Only + one can be controlled by software: + + LED L - RB14 (SPI3_SCK) + + There are also four LEDs on the back, white side of the board: + + LED A - RA6 + LED B - RA7 + LED C - RE0 + LED D - RE1 + + A high output value illuminates the LEDs. + + These LEDs are available to the application and are all available to the + application unless CONFIG_ARCH_LEDS is defined. In that case, the usage + by the board port is defined in include/board.h and src/sam_autoleds.c. + The LEDs are used to encode OS-related events as follows: + + SYMBOL MEANING LED STATE + L A B C D + ---------------- ----------------------- --- --- --- --- --- + LED_STARTED NuttX has been started OFF ON OFF OFF OFF + LED_HEAPALLOCATE Heap has been allocated OFF OFF ON OFF OFF + LED_IRQSENABLED Interrupts enabled OFF OFF OFF ON OFF + LED_STACKCREATED Idle stack created OFF OFF OFF OFF ON + LED_INIRQ In an interrupt GLO N/C N/C N/C N/C + LED_SIGNAL In a signal handler GLO N/C N/C N/C N/C + LED_ASSERTION An assertion failed GLO N/C N/C N/C N/C + LED_PANIC The system has crashed 2Hz N/C N/C N/C N/C + LED_IDLE MCU is is sleep mode ---- Not used ----- + + Thus if LED L is glowing on and all other LEDs are off (except LED D which + was left on but is no longer controlled by NuttX and so may be in any + state), NuttX has successfully booted and is, apparently, running normally + and taking interrupts. If any of LEDs A-D are statically set, then NuttX + failed to boot and the LED indicates the initialization phase where the + failure occurred. If LED L is flashing at approximately 2Hz, then a fatal + error has been detected and the system has halted. + + NOTE: After booting, LEDs A-D are no longer used by the system and may + be controlled the application. + + Buttons + ------- + + The Flip&Click PIC32MZ has 2 user push buttons labeled T1 and T2 on the + white side of the board: + + PIN LED Notes + ----- ---- ------------------------- + RD10 T1 Sensed low when closed + RD11 T2 Sensed low when closed + + The switches have external pull-up resistors. The switches are pulled high + (+3.3V) and grounded when pressed. + +Configurations +============== + +Information Common to All Configurations +---------------------------------------- + + 1. Each PIC32MZ configuration is maintained in a sub-directory and can be + selected as follow: + + tools/configure.sh flipnclick-pic32mz/ + + Where typical options are -l to configure to build on Linux or -c to + configure for Cygwin under Linux. 'tools/configure.sh -h' will show + you all of the options. + + Before building, make sure the PATH environment variable includes the + correct path to the directory than holds your toolchain binaries. + + And then build NuttX by simply typing the following. At the conclusion + of the make, the nuttx binary will reside in an ELF file called, simply, + nuttx. + + make + + The that is provided above as an argument to the + tools/configure.sh must be is one of the directories listed in the + following paragraph. + + 2. These configurations uses the mconf-based configuration tool. To + change this configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. Execute 'make menuconfig' in the top-level nuttx in order to start + the reconfiguration process. + +Configuration Directories +------------------------- + +Where is one of the following: + + nsh: + + This is the NuttShell (NSH) using the NSH startup logic at + apps/examples/nsh. + + NOTES: + + 1. Serial Console. UART 4 is configured as the Serial Console. This + assumes that you will be using a Mikroe RS-232 Click card in the + mikroBUS A slot. Other serial consoles may be selected by re- + configuring (see the section "Serial Consoles" above). + + 2. Toolchain + + By default, the Pinguino MIPs tool chain is used. This toolchain + selection can easily be changed with 'make menuconfig'. + + 3. Default configuration: These are other things that you may want to + change in the configuration: + + CONFIG_PIC32MZ_DEBUGGER_ENABLE=n : Debugger is disabled + CONFIG_PIC32MZ_TRACE_ENABLE=n : Trace is disabled + CONFIG_PIC32MZ_JTAG_ENABLE=n : JTAG is disabled diff --git a/configs/flipnclick-pic32mz/include/board.h b/configs/flipnclick-pic32mz/include/board.h new file mode 100644 index 0000000000000000000000000000000000000000..490a8cde3fb6d9cc02630a7fb4d5d7ee14f6ff52 --- /dev/null +++ b/configs/flipnclick-pic32mz/include/board.h @@ -0,0 +1,334 @@ +/**************************************************************************** + * configs/flipnclick-pic32mz/include/board.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_FLIPNCLICK_PIC32MZ_INCLUDE_BOARD_H +#define __CONFIGS_FLIPNCLICK_PIC32MZ_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Clocking *****************************************************************/ +/* REVISIT: The PIC32MZ2048EFH100 is capable of operating at 252MHz */ + +/* Crystal frequencies + * + * - A 24 MHz oscillator circuit (Y4) is connected to the on-board + * microcontroller. This oscillator circuit functions as the controller’s + * primary oscillator. Depending on which is populated on the starter kit + * board, a 24 MHz crystal (Y1) may be used instead of Y4. + * - The starter kit also has provisions for an external secondary 32 kHz + * oscillator (Y2); however, this is not populated. + */ + +#define BOARD_POSC_FREQ 24000000 /* Primary OSC XTAL frequency (Y4, 24MHz) */ +#define BOARD_SOSC_FREQ 32000 /* Secondary OSC XTAL frequency (Y2, 32KHz) */ + +/* Oscillator modes. + * + * - BOARD_POSC_ECMODE: An external oscillator is connected to OSC1/OSC2 + * - BOARD_POSC_HSMODE: An external crystal or resonator is connected to + * OSC1/OSC2 + */ + +#define BOARD_FNOSC_SPLL 1 /* Use system PLL */ +#define BOARD_POSC_ECMODE 1 /* External clock (EC) mode */ +#define BOARD_POSC_SWITCH 1 /* Enable clock switching */ +#undef BOARD_POSC_FSCM /* Disable clock monitoring */ + +/* PLL configuration and resulting CPU clock. + * CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV + */ + +#define BOARD_PLL_INPUT BOARD_POSC_FREQ +#define BOARD_PLL_IDIV 3 /* PLL input divider */ +#define BOARD_PLL_MULT 50 /* PLL multiplier */ +#define BOARD_PLL_ODIV 2 /* PLL output divider */ + +#define BOARD_CPU_CLOCK 200000000 /* CPU clock: 200MHz = (24MHz / 3) * 50 / 2) */ + +/* Peripheral clocks */ +/* PBCLK1 + * Peripherals: OSC2 pin + * + * NOTES: + * - PBCLK1 is used by system modules and cannot be turned off + * - PBCLK1 divided by 2 is available on the OSC2 pin in certain clock + * modes. + */ + +#define BOARD_PB1DIV 5 /* Divider = 5 */ +#define BOARD_PBCLK1 40000000 /* PBCLK1 frequency = 200MHz/5 = 40MHz */ + +/* PBCLK2 + * Peripherals: PMP, I2C, UART, SPI + */ + +#define BOARD_PBCLK2_ENABLE 1 /* Enable PBCLK2 */ +#define BOARD_PB2DIV 2 /* Divider = 2 */ +#define BOARD_PBCLK2 100000000 /* PBCLK2 frequency = 200MHz/2 = 100MHz */ + +/* PBCLK3 + * Peripherals: ADC, Comparator, Timers, Output Compare, Input Compare + * + * NOTES: + * - Timer 1 uses SOSC + */ + +#define BOARD_PBCLK3_ENABLE 1 /* Enable PBCLK3 */ +#define BOARD_PB3DIV 4 /* Divider = 4 */ +#define BOARD_PBCLK3 50000000 /* PBCLK3 frequency = 200MHz/4 = 50MHz */ + +/* PBCLK4 + * Peripherals: Ports + */ + +#define BOARD_PBCLK4_ENABLE 1 /* Enable PBCLK4 */ +#define BOARD_PB4DIV 2 /* Divider = 2 */ +#define BOARD_PBCLK4 100000000 /* PBCLK4 frequency = 200MHz/2 = 100MHz */ + +/* PBCLK5 + * Peripherals: Flash, Crypto, RND, USB, CAN, Ethernet, SQI + * + * NOTES: + * - PBCLK5 is used to fetch data from/to the Flash Controller, while the + * FRC clock is used for programming + */ + +#define BOARD_PBCLK5_ENABLE 1 /* Enable PBCLK5 */ +#define BOARD_PB5DIV 2 /* Divider = 2 */ +#define BOARD_PBCLK5 100000000 /* PBCLK5 frequency = 200MHz/2 = 100MHz */ + +/* PBCLK6 + * Peripherals: + */ + +#undef BOARD_PBCLK6_ENABLE + +/* PBCLK7 + * Peripherals: CPU, Deadman timer + */ + +#undef BOARD_PBCLK7_ENABLE + +/* PBCLK8 + * Peripherals: EBI + */ + +#undef BOARD_PBCLK8_ENABLE + +/* Watchdog pre-scaler (re-visit) */ + +#define BOARD_WD_PRESCALER 1048576 /* Watchdog pre-scaler */ + +/* Ethernet MII clocking. + * + * The clock divider used to create the MII Management Clock (MDC). The MIIM + * module uses the PBCLK5 as an input clock. According to the IEEE 802.3 + * Specification this should be no faster than 2.5 MHz. However, some PHYs + * support clock rates up to 12.5 MHz. + */ + +#define BOARD_EMAC_MIIM_DIV 40 /* Ideal: 100MHz/40 = 2.5MHz */ + +/* LED definitions **********************************************************/ +/* There are four LEDs on the top, red side of the board. Only one can be + * controlled by software: + * + * LED L - RB14 (SPI3_SCK) + * + * There are also four LEDs on the back, white side of the board: + * + * LED A - RA6 + * LED B - RA7 + * LED C - RE0 + * LED D - RE1 + * + * A high output value illuminates the LEDs. + */ + +#ifdef CONFIG_ARCH_LEDS +/* LED index values for use with board_userled(): */ + +# define BOARD_LED_A 0 +# define BOARD_LED_B 1 +# define BOARD_LED_C 2 +# define BOARD_LED_D 3 +# define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +# define BOARD_LED_A_BIT (1 << BOARD_LED_A) +# define BOARD_LED_B_BIT (1 << BOARD_LED_B) +# define BOARD_LED_C_BIT (1 << BOARD_LED_C) +# define BOARD_LED_D_BIT (1 << BOARD_LED_D) +#else +/* LED index values for use with board_userled(): */ + +# define BOARD_LED_L 0 +# define BOARD_LED_A 1 +# define BOARD_LED_B 2 +# define BOARD_LED_C 3 +# define BOARD_LED_D 4 +# define BOARD_NLEDS 5 + +/* LED bits for use with board_userled_all() */ + +# define BOARD_LED_L_BIT (1 << BOARD_LED_L) +# define BOARD_LED_A_BIT (1 << BOARD_LED_A) +# define BOARD_LED_B_BIT (1 << BOARD_LED_B) +# define BOARD_LED_C_BIT (1 << BOARD_LED_C) +# define BOARD_LED_D_BIT (1 << BOARD_LED_D) +#endif + +/* These LEDs are available to the application and are all available to the + * application unless CONFIG_ARCH_LEDS is defined. In that case, the usage by the + * board port is defined in include/board.h and src/sam_autoleds.c. The LEDs are + * used to encode OS-related events as follows: + * + * SYMBOL MEANING LED STATE + * L A B C D + * ---------------- ----------------------- --- --- --- --- ---*/ +#define LED_STARTED 0 /* NuttX has been started OFF ON OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON OFF OFF */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF OFF OFF ON OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF OFF OFF OFF ON */ +#define LED_INIRQ 4 /* In an interrupt GLO N/C N/C N/C N/C */ +#define LED_SIGNAL 4 /* In a signal handler GLO N/C N/C N/C N/C */ +#define LED_ASSERTION 4 /* An assertion failed GLO N/C N/C N/C N/C */ +#define LED_PANIC 4 /* The system has crashed 2Hz N/C N/C N/C N/C */ +#undef LED_IDLE /* MCU is is sleep mode ---- Not used ----- */ + +/* Thus if LED L is glowing on and all other LEDs are off (except LED D which + * was left on but is no longer controlled by NuttX and so may be in any state), + * NuttX has successfully booted and is, apparently, running normally and taking + * interrupts. If any of LEDs A-D are statically set, then NuttX failed to boot + * and the LED indicates the initialization phase where the failure occurred. If + * LED L is flashing at approximately 2Hz, then a fatal error has been detected and + * the system has halted. + * + * NOTE: After booting, LEDs A-D are no longer used by the system and may be + * controlled the application. + */ + +/* Switch definitions *******************************************************/ +/* The Flip&Click PIC32MZ has 2 user push buttons labeled T1 and T2 on the + * white side of the board: + * + * PIN LED Notes + * ----- ---- ------------------------- + * RD10 T1 Sensed low when closed + * RD11 T2 Sensed low when closed + * + * The switches have external pull-up resistors. The switches are pulled high + * (+3.3V) and grounded when pressed. + */ + +#define BUTTON_T1 0 +#define BUTTON_T2 1 +#define NUM_BUTTONS 2 + +#define BUTTON_T1_BIT (1 << BUTTON_T1) +#define BUTTON_T2_BIT (1 << BUTTON_T2) + +/* UARTS ********************************************************************/ +/* Convenient U[S]ARTs that may be used as the Serial console include: + * + * 1) An Arduino Serial Shield. The RX and TX pins are available on the + * Arduino connector D0 and D1 pins, respectively. These are connected + * to UART5, UART5_RX and UART5_TX which are RD14 and RD15, respectively. + * + * 2) Mikroe Click Serial Shield. There are four Click bus connectors with + * serial ports available as follows: + * + * Click A: UART4 UART4_RX and UART4_TX which are RG9 and RE3, respectively. + * Click B: UART3 UART3_RX and UART3_TX which are RF0 and RF1, respectively. + * Click C: UART1 UART1_RX and UART1_TX which are RC1 and RE5, respectively. + * Click D: UART2 UART2_RX and UART2_TX which are RC3 and RC2, respectively. + */ + +#define BOARD_U1RX_PPS U1RXR_RPC1 +#define BOARD_U1TX_PPS U1TX_RPE5R + +#define BOARD_U2RX_PPS U2RXR_RPC3 +#define BOARD_U2TX_PPS U2TX_RPC2R + +#define BOARD_U3RX_PPS U3RXR_RPF0 +#define BOARD_U3TX_PPS U3TX_RPF1R + +#define BOARD_U4RX_PPS U4RXR_RPG9 +#define BOARD_U4TX_PPS U4TX_RPE3R + +#define BOARD_U5RX_PPS U5RXR_RPD14 +#define BOARD_U5TX_PPS U5TX_RPD15R + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_FLIPNCLICK_PIC32MZ_INCLUDE_BOARD_H */ diff --git a/configs/flipnclick-pic32mz/nsh/defconfig b/configs/flipnclick-pic32mz/nsh/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..93cfe3849c628a9988761ba8a67255c2525f8647 --- /dev/null +++ b/configs/flipnclick-pic32mz/nsh/defconfig @@ -0,0 +1,51 @@ +# CONFIG_ARCH_RAMFUNCS is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH_BOARD_FLIPNCLICK_PIC32MZ=y +CONFIG_ARCH_BOARD="flipnclick-pic32mz" +CONFIG_ARCH_CHIP_PIC32MZ=y +CONFIG_ARCH_CHIP_PIC32MZ2048EFH=y +CONFIG_ARCH_CHIP_PIC32MZEF=y +CONFIG_ARCH_MIPS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="mips" +CONFIG_BOARD_LOOPSPERMSEC=7245 +CONFIG_BUILTIN=y +CONFIG_DISABLE_POLL=y +CONFIG_EXAMPLES_NSH=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HOST_WINDOWS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MIPS_MICROMIPS=y +CONFIG_MIPS32_TOOLCHAIN_PINGUINOW=y +CONFIG_MMCSD=y +CONFIG_MTD=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PIC32MZ_ICESEL_CH2=y +CONFIG_PIC32MZ_UART4=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=8 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0xa0000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=7 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2012 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_UART4_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=1 diff --git a/configs/flipnclick-pic32mz/scripts/Make.defs b/configs/flipnclick-pic32mz/scripts/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..ae8f8196823429dbdfbbeb7ca76872ccf0784fb5 --- /dev/null +++ b/configs/flipnclick-pic32mz/scripts/Make.defs @@ -0,0 +1,137 @@ +############################################################################ +# configs/flipnclick-pic32mz/scripts/Make.defs +# +# Copyright (C) 2018 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/mips/src/mips32/Toolchain.defs + +ifeq ($(CONFIG_MIPS32_TOOLCHAIN_GNU_ELF),y) + LDSCRIPT = mips-debug.ld +endif + +ifeq ($(CONFIG_MIPS32_TOOLCHAIN_PINGUINOW),y) + LDSCRIPT = pinguino-debug.ld +endif + +ifeq ($(CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL_XC32),y) + LDSCRIPT = xc32-debug.ld + MIPS_MPROCESSOR = 32MZ2048EFH100 +endif + +ifeq ($(CONFIG_MIPS32_TOOLCHAIN_MICROCHIPW_XC32),y) + LDSCRIPT = xc32-debug.ld + MIPS_MPROCESSOR = 32MZ2048EFH100 +endif + +ifeq ($(CONFIG_MIPS32_TOOLCHAIN_MICROCHIPW),y) + LDSCRIPT = c32-debug.ld +endif + +ifeq ($(CONFIG_MIPS32_TOOLCHAIN_MICROCHIPW_LITE),y) + LDSCRIPT = c32-debug.ld +endif + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = + +ifeq ($(CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL_XC32),y) +ifeq ($(CONFIG_DEBUG_FEATURES),y) + ARCHCFLAGS += -D__DEBUG -D__MPLAB_DEBUGGER_PK3=1 -fframe-base-loclist +endif +endif + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +ifeq ($(CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL_XC32),y) + LDFLAGS = -nostdlib --defsym=__MPLAB_BUILD=1 --defsym=__MPLAB_DEBUG=1 --defsym=__DEBUG=1 --defsym=__MPLAB_DEBUGGER_PK3=1 --defsym=_min_heap_size=0 --gc-sections +else + LDFLAGS = # -no-isn32 --relax +endif + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/configs/flipnclick-pic32mz/scripts/c32-debug.ld b/configs/flipnclick-pic32mz/scripts/c32-debug.ld new file mode 100644 index 0000000000000000000000000000000000000000..a9f9518bd11faf509c673acf285e71196cc4a7bd --- /dev/null +++ b/configs/flipnclick-pic32mz/scripts/c32-debug.ld @@ -0,0 +1,336 @@ +/**************************************************************************** + * configs/flipnclick-pic32mz/nsh/c32-debug.ld + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/* Memory Regions ***********************************************************/ + +MEMORY +{ + /* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 2048Kb of + * program FLASH at physical address 0x1d000000 but is always accessed + * at KSEG0 address 0x9d00:0000 + */ + + kseg0_progmem (rx) : ORIGIN = 0x9d000000, LENGTH = 2048K + + /* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have 160Kb of boot + * FLASH: 80Kb at physical address 0x1fc4000 (Boot Flash 1, boot1) and + * 80Kb at physical address 0x1fc60000 (Boot Flash 2, boot2). Either + * may be mappled to the lower boot alias region (0x1fc00000, + * boolalias1) or the upper boot alias region (0x1fc20000, bootalias2). + * This linker script assumes that Boot Flash 1 is mapped to the lower + * alias region and Boot Flash 2 to the upper region. + * + * NOTE: This linker script simply writes into the lower boot alias, + * whichever boot FLASH that may correspond to. The other boot FLASH + * is simply ignored. + * + * The initial reset vector is in KSEG1, but all other accesses are in + * KSEG0. + * + * REGION PHYSICAL KSEG SIZE + * DESCRIPTION START ADDR (BYTES) + * ------------- ---------- ------ ---------------------- + * Exceptions:* + * Reset 0x1fc00000 KSEG1 512 512 + * TLB Refill 0x1fc00200 KSEG1 256 768 + * Cache Error 0x1fc00300 KSEG1 128 896 + * Others 0x1fc00380 KSEG1 128 1024 (1Kb) + * Interrupt 0x1fc00400 KSEG1 128 1152 + * JTAG 0x1fc00480 KSEG1 16 1168 + * Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb) + * Debug code 0x1fc02000 KSEG1 4096-16 12272 + * ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb) + * DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb) + * + * Exceptions assume: + * + * STATUS: BEV=0/1 and EXL=0 + * CAUSE: IV=1 + * JTAG: ProbEn=0 + * And multi-vector support disabled + */ + + kseg1_reset (rx) : ORIGIN = 0xbfc00000, LENGTH = 384 + kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128 + kseg1_ebexcpt (rx) : ORIGIN = 0xbfc00200, LENGTH = 128 + kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128 + kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128 + kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16 + kseg0_bootmem (rx) : ORIGIN = 0x9fc004ac, LENGTH = 8192-1196 + kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16 + kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128 + kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128 + + /* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb + * of data memory at physical address 0x00000000. Since the PIC32MZ + * has no data cache, this memory is always accessed through KSEG1. + * + * When used with MPLABX, we need to set aside 512 bytes of memory + * for use by MPLABX and 128 for DSP register storage. + */ + + kseg1_datamem (rw!x) : ORIGIN = 0xa0000200, LENGTH = 512K - 640 +} + +OUTPUT_FORMAT("elf32-tradlittlemips") +OUTPUT_ARCH(pic32mz) +ENTRY(__start) + +SECTIONS +{ + /* Boot FLASH sections */ + + .reset : + { + KEEP (*(.reset)) + } > kseg1_reset + + /* Exception handlers. The following is assumed: + * + * STATUS: BEV=1 and EXL=0 + * CAUSE: IV=1 + * JTAG: ProbEn=0 + * And multi-vector support disabled + * + * In that configuration, the vector locations become: + * + * Reset, Soft Reset bfc0:0000 + * TLB Refill bfc0:0200 + * Cache Error bfc0:0300 + * All others bfc0:0380 + * Interrupt bfc0:0400 + * EJTAG Debug bfc0:0480 + */ + + /* KSEG1 exception handler "trampolines" */ + + .gen_excpt : + { + KEEP (*(.gen_excpt)) + } > kseg1_genexcpt + + .ebase_excpt : + { + KEEP (*(.ebase_excpt)) + } > kseg1_ebexcpt + + .bev_excpt : + { + KEEP (*(.bev_excpt)) + } > kseg1_bevexcpt + + .int_excpt : + { + KEEP (*(.int_excpt)) + } > kseg1_intexcpt + + .dbg_excpt = ORIGIN(kseg1_dbgexcpt); + + .start : + { + /* KSEG0 Reset startup logic */ + + *(.start) + + /* KSEG0 exception handlers */ + + *(.nmi_handler) + *(.bev_handler) + *(.int_handler) + } > kseg0_bootmem + + .dbg_code = ORIGIN(kseg1_dbgcode); + + .adevcfg : + { + KEEP (*(.adevcfg)) + } > kseg1_adevcfg + + .devcfg : + { + KEEP (*(.devcfg)) + } > kseg1_devcfg + + /* Program FLASH sections */ + + .text : + { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.stub) + KEEP (*(.text.*personality*)) + *(.gnu.linkonce.t.*) + *(.gnu.warning) + *(.mips16.fn.*) + *(.mips16.call.*) + + /* Read-only data is included in the text section */ + + *(.rodata .rodata.*) + *(.rodata1) + *(.gnu.linkonce.r.*) + + /* Small initialized constant global and static data */ + + *(.sdata2 .sdata2.*) + *(.gnu.linkonce.s2.*) + + /* Uninitialized constant global and static data */ + + *(.sbss2 .sbss2.*) + *(.gnu.linkonce.sb2.*) + _etext = ABSOLUTE(.); + } > kseg0_progmem + + /* Initialization data begins here in progmem */ + + _data_loaddr = LOADADDR(.data); + + .eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + + /* RAM functions are positioned at the beginning of RAM so that + * they can be guaranteed to satisfy the 2Kb alignment requirement. + */ + +/* This causes failures if there are no RAM functions + .ramfunc ALIGN(2K) : + { + _sramfunc = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfunc = ABSOLUTE(.); + } > kseg1_datamem AT > kseg0_progmem + + _ramfunc_loadaddr = LOADADDR(.ramfunc); + _ramfunc_sizeof = SIZEOF(.ramfunc); + _bmxdkpba_address = _sramfunc - ORIGIN(kseg1_datamem) ; + _bmxdudba_address = LENGTH(kseg1_datamem) ; + _bmxdupba_address = LENGTH(kseg1_datamem) ; +*/ + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + *(.data1) + } > kseg1_datamem AT > kseg0_progmem + + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } + _gp = ALIGN(16) + 0x7FF0 ; + + .got : + { + *(.got.plt) *(.got) + } > kseg1_datamem AT > kseg0_progmem + + .sdata : + { + *(.sdata .sdata.* .gnu.linkonce.s.*) + } > kseg1_datamem AT > kseg0_progmem + + .lit8 : + { + *(.lit8) + } > kseg1_datamem AT > kseg0_progmem + + .lit4 : + { + *(.lit4) + _edata = ABSOLUTE(.); + } >kseg1_datamem AT>kseg0_progmem + + .sbss : + { + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } >kseg1_datamem + + .bss : + { + *(.dynbss) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > kseg1_datamem + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + /* DWARF debug sections */ + /* DWARF 1 */ + + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + + /* GNU DWARF 1 extensions */ + + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + + /* DWARF 1.1 and DWARF 2 */ + + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + + /* DWARF 2 */ + + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + + /* SGI/MIPS DWARF 2 extensions */ + + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/configs/flipnclick-pic32mz/scripts/mips-debug.ld b/configs/flipnclick-pic32mz/scripts/mips-debug.ld new file mode 100644 index 0000000000000000000000000000000000000000..5dc217f656b1ed6ccd5ae38a4f4f0683031cec02 --- /dev/null +++ b/configs/flipnclick-pic32mz/scripts/mips-debug.ld @@ -0,0 +1,336 @@ +/**************************************************************************** + * configs/flipnclick-pic32mz/nsh/mips-debug.ld + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/* Memory Regions ***********************************************************/ + +MEMORY +{ + /* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 2048Kb of + * program FLASH at physical address 0x1d000000 but is always accessed + * at KSEG0 address 0x9d00:0000 + */ + + kseg0_progmem (rx) : ORIGIN = 0x9d000000, LENGTH = 2048K + + /* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have 160Kb of boot + * FLASH: 80Kb at physical address 0x1fc4000 (Boot Flash 1, boot1) and + * 80Kb at physical address 0x1fc60000 (Boot Flash 2, boot2). Either + * may be mappled to the lower boot alias region (0x1fc00000, + * boolalias1) or the upper boot alias region (0x1fc20000, bootalias2). + * This linker script assumes that Boot Flash 1 is mapped to the lower + * alias region and Boot Flash 2 to the upper region. + * + * NOTE: This linker script simply writes into the lower boot alias, + * whichever boot FLASH that may correspond to. The other boot FLASH + * is simply ignored. + * + * The initial reset vector is in KSEG1, but all other accesses are in + * KSEG0. + * + * REGION PHYSICAL KSEG SIZE + * DESCRIPTION START ADDR (BYTES) + * ------------- ---------- ------ ---------------------- + * Exceptions:* + * Reset 0x1fc00000 KSEG1 512 512 + * TLB Refill 0x1fc00200 KSEG1 256 768 + * Cache Error 0x1fc00300 KSEG1 128 896 + * Others 0x1fc00380 KSEG1 128 1024 (1Kb) + * Interrupt 0x1fc00400 KSEG1 128 1152 + * JTAG 0x1fc00480 KSEG1 16 1168 + * Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb) + * Debug code 0x1fc02000 KSEG1 4096-16 12272 + * ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb) + * DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb) + * + * Exceptions assume: + * + * STATUS: BEV=0/1 and EXL=0 + * CAUSE: IV=1 + * JTAG: ProbEn=0 + * And multi-vector support disabled + */ + + kseg1_reset (rx) : ORIGIN = 0xbfc00000, LENGTH = 384 + kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128 + kseg1_ebexcpt (rx) : ORIGIN = 0xbfc00200, LENGTH = 128 + kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128 + kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128 + kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16 + kseg0_bootmem (rx) : ORIGIN = 0x9fc004ac, LENGTH = 8192-1196 + kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16 + kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128 + kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128 + + /* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb + * of data memory at physical address 0x00000000. Since the PIC32MZ + * has no data cache, this memory is always accessed through KSEG1. + * + * When used with MPLABX, we need to set aside 512 bytes of memory + * for use by MPLABX and 128 for DSP register storage. + */ + + kseg1_datamem (rw!x) : ORIGIN = 0xa0000200, LENGTH = 512K - 640 +} + +OUTPUT_FORMAT("elf32-tradlittlemips") +OUTPUT_ARCH(mips) +ENTRY(__start) + +SECTIONS +{ + /* Boot FLASH sections */ + + .reset : + { + KEEP (*(.reset)) + } > kseg1_reset + + /* Exception handlers. The following is assumed: + * + * STATUS: BEV=1 and EXL=0 + * CAUSE: IV=1 + * JTAG: ProbEn=0 + * And multi-vector support disabled + * + * In that configuration, the vector locations become: + * + * Reset, Soft Reset bfc0:0000 + * TLB Refill bfc0:0200 + * Cache Error bfc0:0300 + * All others bfc0:0380 + * Interrupt bfc0:0400 + * EJTAG Debug bfc0:0480 + */ + + /* KSEG1 exception handler "trampolines" */ + + .gen_excpt : + { + KEEP (*(.gen_excpt)) + } > kseg1_genexcpt + + .ebase_excpt : + { + KEEP (*(.ebase_excpt)) + } > kseg1_ebexcpt + + .bev_excpt : + { + KEEP (*(.bev_excpt)) + } > kseg1_bevexcpt + + .int_excpt : + { + KEEP (*(.int_excpt)) + } > kseg1_intexcpt + + .dbg_excpt = ORIGIN(kseg1_dbgexcpt); + + .start : + { + /* KSEG0 Reset startup logic */ + + *(.start) + + /* KSEG0 exception handlers */ + + *(.nmi_handler) + *(.bev_handler) + *(.int_handler) + } > kseg0_bootmem + + .dbg_code = ORIGIN(kseg1_dbgcode); + + .adevcfg : + { + KEEP (*(.adevcfg)) + } > kseg1_adevcfg + + .devcfg : + { + KEEP (*(.devcfg)) + } > kseg1_devcfg + + /* Program FLASH sections */ + + .text : + { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.stub) + KEEP (*(.text.*personality*)) + *(.gnu.linkonce.t.*) + *(.gnu.warning) + *(.mips16.fn.*) + *(.mips16.call.*) + + /* Read-only data is included in the text section */ + + *(.rodata .rodata.*) + *(.rodata1) + *(.gnu.linkonce.r.*) + + /* Small initialized constant global and static data */ + + *(.sdata2 .sdata2.*) + *(.gnu.linkonce.s2.*) + + /* Uninitialized constant global and static data */ + + *(.sbss2 .sbss2.*) + *(.gnu.linkonce.sb2.*) + _etext = ABSOLUTE(.); + } > kseg0_progmem + + /* Initialization data begins here in progmem */ + + _data_loaddr = LOADADDR(.data); + + .eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + + /* RAM functions are positioned at the beginning of RAM so that + * they can be guaranteed to satisfy the 2Kb alignment requirement. + */ + +/* This causes failures if there are no RAM functions + .ramfunc ALIGN(2K) : + { + _sramfunc = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfunc = ABSOLUTE(.); + } > kseg1_datamem AT > kseg0_progmem + + _ramfunc_loadaddr = LOADADDR(.ramfunc); + _ramfunc_sizeof = SIZEOF(.ramfunc); + _bmxdkpba_address = _sramfunc - ORIGIN(kseg1_datamem) ; + _bmxdudba_address = LENGTH(kseg1_datamem) ; + _bmxdupba_address = LENGTH(kseg1_datamem) ; +*/ + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + *(.data1) + } > kseg1_datamem AT > kseg0_progmem + + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } + _gp = ALIGN(16) + 0x7FF0 ; + + .got : + { + *(.got.plt) *(.got) + } > kseg1_datamem AT > kseg0_progmem + + .sdata : + { + *(.sdata .sdata.* .gnu.linkonce.s.*) + } > kseg1_datamem AT > kseg0_progmem + + .lit8 : + { + *(.lit8) + } > kseg1_datamem AT > kseg0_progmem + + .lit4 : + { + *(.lit4) + _edata = ABSOLUTE(.); + } >kseg1_datamem AT>kseg0_progmem + + .sbss : + { + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } >kseg1_datamem + + .bss : + { + *(.dynbss) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > kseg1_datamem + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + /* DWARF debug sections */ + /* DWARF 1 */ + + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + + /* GNU DWARF 1 extensions */ + + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + + /* DWARF 1.1 and DWARF 2 */ + + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + + /* DWARF 2 */ + + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + + /* SGI/MIPS DWARF 2 extensions */ + + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/configs/flipnclick-pic32mz/scripts/pinguino-debug.ld b/configs/flipnclick-pic32mz/scripts/pinguino-debug.ld new file mode 100644 index 0000000000000000000000000000000000000000..1fae589e674eb7b8f97280da906607b2948c615e --- /dev/null +++ b/configs/flipnclick-pic32mz/scripts/pinguino-debug.ld @@ -0,0 +1,336 @@ +/**************************************************************************** + * configs/flipnclick-pic32mz/nsh/mips-debug.ld + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/* Memory Regions ***********************************************************/ + +MEMORY +{ + /* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 2048Kb of + * program FLASH at physical address 0x1d000000 but is always accessed + * at KSEG0 address 0x9d00:0000 + */ + + kseg0_progmem (rx) : ORIGIN = 0x9d000000, LENGTH = 2048K + + /* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have 160Kb of boot + * FLASH: 80Kb at physical address 0x1fc4000 (Boot Flash 1, boot1) and + * 80Kb at physical address 0x1fc60000 (Boot Flash 2, boot2). Either + * may be mappled to the lower boot alias region (0x1fc00000, + * boolalias1) or the upper boot alias region (0x1fc20000, bootalias2). + * This linker script assumes that Boot Flash 1 is mapped to the lower + * alias region and Boot Flash 2 to the upper region. + * + * NOTE: This linker script simply writes into the lower boot alias, + * whichever boot FLASH that may correspond to. The other boot FLASH + * is simply ignored. + * + * The initial reset vector is in KSEG1, but all other accesses are in + * KSEG0. + * + * REGION PHYSICAL KSEG SIZE + * DESCRIPTION START ADDR (BYTES) + * ------------- ---------- ------ ---------------------- + * Exceptions:* + * Reset 0x1fc00000 KSEG1 512 512 + * TLB Refill 0x1fc00200 KSEG1 256 768 + * Cache Error 0x1fc00300 KSEG1 128 896 + * Others 0x1fc00380 KSEG1 128 1024 (1Kb) + * Interrupt 0x1fc00400 KSEG1 128 1152 + * JTAG 0x1fc00480 KSEG1 16 1168 + * Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb) + * Debug code 0x1fc02000 KSEG1 4096-16 12272 + * ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb) + * DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb) + * + * Exceptions assume: + * + * STATUS: BEV=0/1 and EXL=0 + * CAUSE: IV=1 + * JTAG: ProbEn=0 + * And multi-vector support disabled + */ + + kseg1_reset (rx) : ORIGIN = 0xbfc00000, LENGTH = 384 + kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128 + kseg1_ebexcpt (rx) : ORIGIN = 0xbfc00200, LENGTH = 128 + kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128 + kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128 + kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16 + kseg0_bootmem (rx) : ORIGIN = 0x9fc004ac, LENGTH = 8192-1196 + kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16 + kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128 + kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128 + + /* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb + * of data memory at physical address 0x00000000. Since the PIC32MZ + * has no data cache, this memory is always accessed through KSEG1. + * + * When used with MPLABX, we need to set aside 512 bytes of memory + * for use by MPLABX and 128 for DSP register storage. + */ + + kseg1_datamem (rw!x) : ORIGIN = 0xa0000200, LENGTH = 512K - 640 +} + +OUTPUT_FORMAT("elf32-littlemips") +OUTPUT_ARCH(mips) +ENTRY(__start) + +SECTIONS +{ + /* Boot FLASH sections */ + + .reset : + { + KEEP (*(.reset)) + } > kseg1_reset + + /* Exception handlers. The following is assumed: + * + * STATUS: BEV=1 and EXL=0 + * CAUSE: IV=1 + * JTAG: ProbEn=0 + * And multi-vector support disabled + * + * In that configuration, the vector locations become: + * + * Reset, Soft Reset bfc0:0000 + * TLB Refill bfc0:0200 + * Cache Error bfc0:0300 + * All others bfc0:0380 + * Interrupt bfc0:0400 + * EJTAG Debug bfc0:0480 + */ + + /* KSEG1 exception handler "trampolines" */ + + .gen_excpt : + { + KEEP (*(.gen_excpt)) + } > kseg1_genexcpt + + .ebase_excpt : + { + KEEP (*(.ebase_excpt)) + } > kseg1_ebexcpt + + .bev_excpt : + { + KEEP (*(.bev_excpt)) + } > kseg1_bevexcpt + + .int_excpt : + { + KEEP (*(.int_excpt)) + } > kseg1_intexcpt + + .dbg_excpt = ORIGIN(kseg1_dbgexcpt); + + .start : + { + /* KSEG0 Reset startup logic */ + + *(.start) + + /* KSEG0 exception handlers */ + + *(.nmi_handler) + *(.bev_handler) + *(.int_handler) + } > kseg0_bootmem + + .dbg_code = ORIGIN(kseg1_dbgcode); + + .adevcfg : + { + KEEP (*(.adevcfg)) + } > kseg1_adevcfg + + .devcfg : + { + KEEP (*(.devcfg)) + } > kseg1_devcfg + + /* Program FLASH sections */ + + .text : + { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.stub) + KEEP (*(.text.*personality*)) + *(.gnu.linkonce.t.*) + *(.gnu.warning) + *(.mips16.fn.*) + *(.mips16.call.*) + + /* Read-only data is included in the text section */ + + *(.rodata .rodata.*) + *(.rodata1) + *(.gnu.linkonce.r.*) + + /* Small initialized constant global and static data */ + + *(.sdata2 .sdata2.*) + *(.gnu.linkonce.s2.*) + + /* Uninitialized constant global and static data */ + + *(.sbss2 .sbss2.*) + *(.gnu.linkonce.sb2.*) + _etext = ABSOLUTE(.); + } > kseg0_progmem + + /* Initialization data begins here in progmem */ + + _data_loaddr = LOADADDR(.data); + + .eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + + /* RAM functions are positioned at the beginning of RAM so that + * they can be guaranteed to satisfy the 2Kb alignment requirement. + */ + +/* This causes failures if there are no RAM functions + .ramfunc ALIGN(2K) : + { + _sramfunc = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfunc = ABSOLUTE(.); + } > kseg1_datamem AT > kseg0_progmem + + _ramfunc_loadaddr = LOADADDR(.ramfunc); + _ramfunc_sizeof = SIZEOF(.ramfunc); + _bmxdkpba_address = _sramfunc - ORIGIN(kseg1_datamem) ; + _bmxdudba_address = LENGTH(kseg1_datamem) ; + _bmxdupba_address = LENGTH(kseg1_datamem) ; +*/ + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + *(.data1) + } > kseg1_datamem AT > kseg0_progmem + + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } + _gp = ALIGN(16) + 0x7FF0 ; + + .got : + { + *(.got.plt) *(.got) + } > kseg1_datamem AT > kseg0_progmem + + .sdata : + { + *(.sdata .sdata.* .gnu.linkonce.s.*) + } > kseg1_datamem AT > kseg0_progmem + + .lit8 : + { + *(.lit8) + } > kseg1_datamem AT > kseg0_progmem + + .lit4 : + { + *(.lit4) + _edata = ABSOLUTE(.); + } >kseg1_datamem AT>kseg0_progmem + + .sbss : + { + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } >kseg1_datamem + + .bss : + { + *(.dynbss) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > kseg1_datamem + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + /* DWARF debug sections */ + /* DWARF 1 */ + + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + + /* GNU DWARF 1 extensions */ + + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + + /* DWARF 1.1 and DWARF 2 */ + + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + + /* DWARF 2 */ + + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + + /* SGI/MIPS DWARF 2 extensions */ + + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/configs/flipnclick-pic32mz/scripts/xc32-debug.ld b/configs/flipnclick-pic32mz/scripts/xc32-debug.ld new file mode 100644 index 0000000000000000000000000000000000000000..bbec260d520df8798c2888b743b4e75beead358a --- /dev/null +++ b/configs/flipnclick-pic32mz/scripts/xc32-debug.ld @@ -0,0 +1,336 @@ +/**************************************************************************** + * configs/flipnclick-pic32mz/nsh/mips-debug.ld + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/* Memory Regions ***********************************************************/ + +MEMORY +{ + /* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 2048Kb of + * program FLASH at physical address 0x1d000000 but is always accessed + * at KSEG0 address 0x9d00:0000 + */ + + kseg0_program_mem (rx) : ORIGIN = 0x9d000000, LENGTH = 2048K + + /* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have 160Kb of boot + * FLASH: 80Kb at physical address 0x1fc4000 (Boot Flash 1, boot1) and + * 80Kb at physical address 0x1fc60000 (Boot Flash 2, boot2). Either + * may be mappled to the lower boot alias region (0x1fc00000, + * boolalias1) or the upper boot alias region (0x1fc20000, bootalias2). + * This linker script assumes that Boot Flash 1 is mapped to the lower + * alias region and Boot Flash 2 to the upper region. + * + * NOTE: This linker script simply writes into the lower boot alias, + * whichever boot FLASH that may correspond to. The other boot FLASH + * is simply ignored. + * + * The initial reset vector is in KSEG1, but all other accesses are in + * KSEG0. + * + * REGION PHYSICAL KSEG SIZE + * DESCRIPTION START ADDR (BYTES) + * ------------- ---------- ------ ---------------------- + * Exceptions:* + * Reset 0x1fc00000 KSEG1 512 512 + * TLB Refill 0x1fc00200 KSEG1 256 768 + * Cache Error 0x1fc00300 KSEG1 128 896 + * Others 0x1fc00380 KSEG1 128 1024 (1Kb) + * Interrupt 0x1fc00400 KSEG1 128 1152 + * JTAG 0x1fc00480 KSEG1 16 1168 + * Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb) + * Debug code 0x1fc02000 KSEG1 4096-16 12272 + * ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb) + * DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb) + * + * Exceptions assume: + * + * STATUS: BEV=0/1 and EXL=0 + * CAUSE: IV=1 + * JTAG: ProbEn=0 + * And multi-vector support disabled + */ + + kseg1_reset (rx) : ORIGIN = 0xbfc00000, LENGTH = 384 + kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128 + kseg1_ebexcpt (rx) : ORIGIN = 0xbfc00200, LENGTH = 128 + kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128 + kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128 + kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16 + kseg0_bootmem (rx) : ORIGIN = 0x9fc004ac, LENGTH = 8192-1196 + kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16 + kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128 + kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128 + + /* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb + * of data memory at physical address 0x00000000. Since the PIC32MZ + * has no data cache, this memory is always accessed through KSEG1. + * + * When used with MPLABX, we need to set aside 512 bytes of memory + * for use by MPLABX and 128 for DSP register storage. + */ + + kseg1_data_mem (rw!x) : ORIGIN = 0xa0000200, LENGTH = 512K - 640 +} + +OUTPUT_FORMAT("elf32-tradlittlemips") +OUTPUT_ARCH(pic32mx) +ENTRY(__start) + +SECTIONS +{ + /* Boot FLASH sections */ + + .reset : + { + KEEP (*(.reset)) + } > kseg1_reset + + /* Exception handlers. The following is assumed: + * + * STATUS: BEV=1 and EXL=0 + * CAUSE: IV=1 + * JTAG: ProbEn=0 + * And multi-vector support disabled + * + * In that configuration, the vector locations become: + * + * Reset, Soft Reset bfc0:0000 + * TLB Refill bfc0:0200 + * Cache Error bfc0:0300 + * All others bfc0:0380 + * Interrupt bfc0:0400 + * EJTAG Debug bfc0:0480 + */ + + /* KSEG1 exception handler "trampolines" */ + + .gen_excpt : + { + KEEP (*(.gen_excpt)) + } > kseg1_genexcpt + + .ebase_excpt : + { + KEEP (*(.ebase_excpt)) + } > kseg1_ebexcpt + + .bev_excpt : + { + KEEP (*(.bev_excpt)) + } > kseg1_bevexcpt + + .int_excpt : + { + KEEP (*(.int_excpt)) + } > kseg1_intexcpt + + .dbg_excpt = ORIGIN(kseg1_dbgexcpt); + + .start : + { + /* KSEG0 Reset startup logic */ + + *(.start) + + /* KSEG0 exception handlers */ + + *(.nmi_handler) + *(.bev_handler) + *(.int_handler) + } > kseg0_bootmem + + .dbg_code = ORIGIN(kseg1_dbgcode); + + .adevcfg : + { + KEEP (*(.adevcfg)) + } > kseg1_adevcfg + + .devcfg : + { + KEEP (*(.devcfg)) + } > kseg1_devcfg + + /* Program FLASH sections */ + + .text : + { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.stub) + KEEP (*(.text.*personality*)) + *(.gnu.linkonce.t.*) + *(.gnu.warning) + *(.mips16.fn.*) + *(.mips16.call.*) + + /* Read-only data is included in the text section */ + + *(.rodata .rodata.*) + *(.rodata1) + *(.gnu.linkonce.r.*) + + /* Small initialized constant global and static data */ + + *(.sdata2 .sdata2.*) + *(.gnu.linkonce.s2.*) + + /* Uninitialized constant global and static data */ + + *(.sbss2 .sbss2.*) + *(.gnu.linkonce.sb2.*) + _etext = ABSOLUTE(.); + } > kseg0_program_mem + + /* Initialization data begins here in progmem */ + + _data_loaddr = LOADADDR(.data); + + .eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + + /* RAM functions are positioned at the beginning of RAM so that + * they can be guaranteed to satisfy the 2Kb alignment requirement. + */ + +/* This causes failures if there are no RAM functions + .ramfunc ALIGN(2K) : + { + _sramfunc = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfunc = ABSOLUTE(.); + } > kseg1_data_mem AT > kseg0_program_mem + + _ramfunc_loadaddr = LOADADDR(.ramfunc); + _ramfunc_sizeof = SIZEOF(.ramfunc); + _bmxdkpba_address = _sramfunc - ORIGIN(kseg1_data_mem) ; + _bmxdudba_address = LENGTH(kseg1_data_mem) ; + _bmxdupba_address = LENGTH(kseg1_data_mem) ; +*/ + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + *(.data1) + } > kseg1_data_mem AT > kseg0_program_mem + + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } + _gp = ALIGN(16) + 0x7FF0 ; + + .got : + { + *(.got.plt) *(.got) + } > kseg1_data_mem AT > kseg0_program_mem + + .sdata : + { + *(.sdata .sdata.* .gnu.linkonce.s.*) + } > kseg1_data_mem AT > kseg0_program_mem + + .lit8 : + { + *(.lit8) + } > kseg1_data_mem AT > kseg0_program_mem + + .lit4 : + { + *(.lit4) + _edata = ABSOLUTE(.); + } >kseg1_data_mem AT>kseg0_program_mem + + .sbss : + { + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } >kseg1_data_mem + + .bss : + { + *(.dynbss) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > kseg1_data_mem + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + /* DWARF debug sections */ + /* DWARF 1 */ + + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + + /* GNU DWARF 1 extensions */ + + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + + /* DWARF 1.1 and DWARF 2 */ + + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + + /* DWARF 2 */ + + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + + /* SGI/MIPS DWARF 2 extensions */ + + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/configs/flipnclick-pic32mz/src/.gitignore b/configs/flipnclick-pic32mz/src/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..726d936e1e3390cc875a1fa5681e3c3988fe3c8b --- /dev/null +++ b/configs/flipnclick-pic32mz/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/configs/flipnclick-pic32mz/src/Makefile b/configs/flipnclick-pic32mz/src/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..c8226dc95ef47b0b714eed37113e81ecea41b12e --- /dev/null +++ b/configs/flipnclick-pic32mz/src/Makefile @@ -0,0 +1,53 @@ +############################################################################ +# configs/flipnclick-pic32mz/src/Makefile +# +# Copyright (C) 2015 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = pic32mz_boot.c pic32mz_bringup.c pic32mz_userleds.c pic32mz_spi.c + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += pic32mz_appinit.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += pic32mz_autoleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += pic32mz_buttons.c +endif + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/flipnclick-pic32mz/src/flipnclick-pic32mz.h b/configs/flipnclick-pic32mz/src/flipnclick-pic32mz.h new file mode 100644 index 0000000000000000000000000000000000000000..a1cbc0a8ebc6a19dc6a2421fda7897b1ba9d8e0f --- /dev/null +++ b/configs/flipnclick-pic32mz/src/flipnclick-pic32mz.h @@ -0,0 +1,150 @@ +/**************************************************************************** + * configs/flipnclick-pic32mz/src/flipnclick-pic32mz.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_FLIPNCLICK_PIC32MZ_SRC_FLIPNCLICK_PIC32MZ_H +#define __CONFIGS_FLIPNCLICK_PIC32MZ_SRC_FLIPNCLICK_PIC32MZ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +/* LEDs *********************************************************************/ +/* There are four LEDs on the top, red side of the board. Only one can be + * controlled by software: + * + * LED L - RB14 (SPI3_SCK) + * + * There are also four LEDs on the back, white side of the board: + * + * LED A - RA6 + * LED B - RA7 + * LED C - RE0 + * LED D - RE1 + * + * A high output value illuminates the LEDs. + */ + +#define GPIO_LED_L (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTB | GPIO_PIN14) +#define GPIO_LED_A (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTA | GPIO_PIN6) +#define GPIO_LED_B (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTA | GPIO_PIN7) +#define GPIO_LED_C (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTE | GPIO_PIN0) +#define GPIO_LED_D (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTE | GPIO_PIN1) + +/* The Flip&Click PIC32MZ has 2 user push buttons labeled T1 and T2 on the + * white side of the board: + * + * PIN LED Notes + * ----- ---- ------------------------- + * RD10 T1 Sensed low when closed + * RD11 T2 Sensed low when closed + * + * The switches have external pull-up resistors. The switches are pulled high + * (+3.3V) and grounded when pressed. + */ + +#define GPIO_T1 (GPIO_INPUT | GPIO_INTERRUPT | GPIO_PORTD | GPIO_PIN10) +#define GPIO_T2 (GPIO_INPUT | GPIO_INTERRUPT | GPIO_PORTD | GPIO_PIN11) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Name: pic32mz_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the PCB Logic board. + * + ************************************************************************************/ + +#ifdef CONFIG_PIC32MZ_SPI +void weak_function pic32mz_spidev_initialize(void); +#endif + +/************************************************************************************ + * Name: pic32mz_led_initialize + * + * Description: + * Configure on-board LEDs if LED support has been selected. + * + ************************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void pic32mz_led_initialize(void); +#endif + +/**************************************************************************** + * Name: pic32mz_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int pic32mz_bringup(void); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_FLIPNCLICK_PIC32MZ_SRC_FLIPNCLICK_PIC32MZ_H */ diff --git a/configs/flipnclick-pic32mz/src/pic32mz_appinit.c b/configs/flipnclick-pic32mz/src/pic32mz_appinit.c new file mode 100644 index 0000000000000000000000000000000000000000..68e8e9491202138efc32725919981ac20c4e1649 --- /dev/null +++ b/configs/flipnclick-pic32mz/src/pic32mz_appinit.c @@ -0,0 +1,90 @@ +/**************************************************************************** + * config/flipnclick-pic32mz/src/pic32mz_appinit.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "flipnclick-pic32mz.h" + +#ifdef CONFIG_LIB_BOARDCTL + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + /* If CONFIG_BOARD_INITIALIZE is selected then board initialization was + * already performed in board_initialize. + */ + +#ifndef CONFIG_BOARD_INITIALIZE + return pic32mz_bringup(); +#else + return OK; +#endif +} + +#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/flipnclick-pic32mz/src/pic32mz_autoleds.c b/configs/flipnclick-pic32mz/src/pic32mz_autoleds.c new file mode 100644 index 0000000000000000000000000000000000000000..01d05ea00d07159628af4bdce10c0a6625642ced --- /dev/null +++ b/configs/flipnclick-pic32mz/src/pic32mz_autoleds.c @@ -0,0 +1,227 @@ +/**************************************************************************** + * configs/flipnclick-pic32mz/src/pic32mz_leds.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "pic32mz-gpio.h" +#include "flipnclick-pic32mz.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* There are four LEDs on the top, red side of the board. Only one can be + * controlled by software: + * + * LED L - RB14 (SPI3_SCK) + * + * There are also four LEDs on the back, white side of the board: + * + * LED A - RA6 + * LED B - RA7 + * LED C - RE0 + * LED D - RE1 + * + * A high output value illuminates the LEDs. + * + * These LEDs are available to the application and are all available to the + * application unless CONFIG_ARCH_LEDS is defined. In that case, the usage + * by the board port is defined in include/board.h and src/sam_autoleds.c. + * The LEDs are used to encode OS-related events as follows: + * + * SYMBOL MEANING LED STATE + * L A B C D + * ---------------- ----------------------- --- --- --- --- --- + * LED_STARTED NuttX has been started OFF ON OFF OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF ON OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF OFF ON OFF + * LED_STACKCREATED Idle stack created OFF OFF OFF OFF ON + * LED_INIRQ In an interrupt GLO N/C N/C N/C N/C + * LED_SIGNAL In a signal handler GLO N/C N/C N/C N/C + * LED_ASSERTION An assertion failed GLO N/C N/C N/C N/C + * LED_PANIC The system has crashed 2Hz N/C N/C N/C N/C + * LED_IDLE MCU is is sleep mode ---- Not used ----- + * + * Thus if LED L is glowing on and all other LEDs are off (except LED D + * which was left on but is no longer controlled by NuttX and so may be in + * any state), NuttX has successfully booted and is, apparently, running + * normally and taking interrupts. If any of LEDs A-D are statically set, + * then NuttX failed to boot and the LED indicates the initialization phase + * where the failure occurred. If LED L is flashing at approximately 2Hz, + * then a fatal error has been detected and the system has halted. + * + * NOTE: After booting, LEDs A-D are no longer used by the system and may + * be controlled the application. + */ + +/* LED indices */ + +#define INDEX_LED_L 0 +#define INDEX_LED_A 1 +#define INDEX_LED_B 2 +#define INDEX_LED_C 3 +#define INDEX_LED_D 4 +#define NLEDS 5 + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void board_autoled_setone(int ledndx) +{ + bool ledon[NLEDS] = {false, false, false, false, false}; + + ledon[ledndx] = true; + pic32mz_gpiowrite(GPIO_LED_L, ledon[INDEX_LED_L]); + pic32mz_gpiowrite(GPIO_LED_A, ledon[INDEX_LED_A]); + pic32mz_gpiowrite(GPIO_LED_B, ledon[INDEX_LED_B]); + pic32mz_gpiowrite(GPIO_LED_C, ledon[INDEX_LED_D]); + pic32mz_gpiowrite(GPIO_LED_D, ledon[INDEX_LED_D]); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pic32mz_led_initialize + ****************************************************************************/ + +void pic32mz_led_initialize(void) +{ + /* Configure LED GPIOs for output */ + + pic32mz_configgpio(GPIO_LED_L); + pic32mz_configgpio(GPIO_LED_A); + pic32mz_configgpio(GPIO_LED_B); + pic32mz_configgpio(GPIO_LED_C); + pic32mz_configgpio(GPIO_LED_D); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + /* SYMBOL MEANING LED STATE + * L A B C D + * ------------------- ----------------------- --- --- --- --- --- + * LED_STARTED 0 NuttX has been started OFF ON OFF OFF OFF + * LED_HEAPALLOCATE 1 Heap has been allocated OFF OFF ON OFF OFF + * LED_IRQSENABLED 2 Interrupts enabled OFF OFF OFF ON OFF + * LED_STACKCREATED 3 Idle stack created OFF OFF OFF OFF ON + * LED_INIRQ 4 In an interrupt GLO N/C N/C N/C N/C + * LED_SIGNAL 4 In a signal handler GLO N/C N/C N/C N/C + * LED_ASSERTION 4 An assertion failed GLO N/C N/C N/C N/C + * LED_PANIC 4 The system has crashed 2Hz N/C N/C N/C N/C + */ + + switch (led) + { + default: + case 0: + board_autoled_setone(INDEX_LED_A); + break; + + case 1: + board_autoled_setone(INDEX_LED_B); + break; + + case 2: + board_autoled_setone(INDEX_LED_C); + break; + + case 3: + board_autoled_setone(INDEX_LED_D); + break; + + case 4: + pic32mz_gpiowrite(GPIO_LED_L, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + /* SYMBOL MEANING LED STATE + * L A B C D + * ------------------- ----------------------- --- --- --- --- --- + * LED_STARTED 0 NuttX has been started OFF ON OFF OFF OFF + * LED_HEAPALLOCATE 1 Heap has been allocated OFF OFF ON OFF OFF + * LED_IRQSENABLED 2 Interrupts enabled OFF OFF OFF ON OFF + * LED_STACKCREATED 3 Idle stack created OFF OFF OFF OFF ON + * LED_INIRQ 4 In an interrupt GLO N/C N/C N/C N/C + * LED_SIGNAL 4 In a signal handler GLO N/C N/C N/C N/C + * LED_ASSERTION 4 An assertion failed GLO N/C N/C N/C N/C + * LED_PANIC 4 The system has crashed 2Hz N/C N/C N/C N/C + */ + + switch (led) + { + default: + pic32mz_gpiowrite(GPIO_LED_L, false); + pic32mz_gpiowrite(GPIO_LED_A, false); + pic32mz_gpiowrite(GPIO_LED_B, false); + pic32mz_gpiowrite(GPIO_LED_C, false); + pic32mz_gpiowrite(GPIO_LED_D, false); + break; + + case 4: + pic32mz_gpiowrite(GPIO_LED_L, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/flipnclick-pic32mz/src/pic32mz_boot.c b/configs/flipnclick-pic32mz/src/pic32mz_boot.c new file mode 100644 index 0000000000000000000000000000000000000000..7638d292a4f126b82aebc0e28280e563ba6567fa --- /dev/null +++ b/configs/flipnclick-pic32mz/src/pic32mz_boot.c @@ -0,0 +1,103 @@ +/************************************************************************************ + * configs/flipnclick-pic32mz/src/pic32mz_boot.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include + +#include "flipnclick-pic32mz.h" + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: pic32mz_boardinitialize + * + * Description: + * All PIC32MZ architectures must provide the following entry point. This entry + * point is called early in the initialization -- after all memory has been + * configured and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void pic32mz_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) at least one SPI is enabled, and 2) the weak + * function pic32mz_spidev_initialize() has been brought into the link. + */ + +#ifdef CONFIG_PIC32MZ_SPI + if (pic32mz_spidev_initialize) + { + pic32mz_spidev_initialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + pic32mz_led_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_intiialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ + /* Perform board initialization */ + + (void)pic32mz_bringup(); +} +#endif /* CONFIG_BOARD_INITIALIZE */ diff --git a/configs/xtrs/include/board.h b/configs/flipnclick-pic32mz/src/pic32mz_bringup.c similarity index 81% rename from configs/xtrs/include/board.h rename to configs/flipnclick-pic32mz/src/pic32mz_bringup.c index 2e7f04daeabbea94082d41c7cf6cc37da4f81afd..3ce4337fe40b44b7687b6e5cafc3f763b08311ee 100644 --- a/configs/xtrs/include/board.h +++ b/configs/flipnclick-pic32mz/src/pic32mz_bringup.c @@ -1,7 +1,7 @@ /**************************************************************************** - * configs/xtrs/include/board.h + * config/flipnclick-pic32mz/src/pic32mz_bringup.c * - * Copyright (C) 2008 Gregory Nutt. All rights reserved. + * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,39 +33,32 @@ * ****************************************************************************/ -#ifndef __ARCH_BOARD_BOARD_H -#define __ARCH_BOARD_BOARD_H - /**************************************************************************** * Included Files ****************************************************************************/ -/* Adresses of BIOS routines */ +#include -#include "trs80-m3.h" +#include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ +#include "flipnclick-pic32mz.h" /**************************************************************************** * Public Functions ****************************************************************************/ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif +/**************************************************************************** + * Name: pic32mz_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ -EXTERN void z80_lowputc(char ch) __naked; -EXTERN char z80_lowgetc(void) __naked; +int pic32mz_bringup(void) +{ + int ret; -#undef EXTERN -#if defined(__cplusplus) + UNUSED(ret); + return OK; } -#endif - -#endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/flipnclick-pic32mz/src/pic32mz_buttons.c b/configs/flipnclick-pic32mz/src/pic32mz_buttons.c new file mode 100644 index 0000000000000000000000000000000000000000..9df4b0e54f496b02c7496c6c28388b12006e2981 --- /dev/null +++ b/configs/flipnclick-pic32mz/src/pic32mz_buttons.c @@ -0,0 +1,176 @@ +/**************************************************************************** + * configs/flipnclick-pic32mz/src/pic32mz_buttons.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "pic32mz-gpio.h" +#include "flipnclick-pic32mz.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each switch. This array is indexed by the BUTTON_* + * definitions in board.h + */ + +static const pinset_t g_buttons[NUM_BUTTONS] = +{ + GPIO_T1, GPIO_T2, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + pic32mz_configgpio(g_buttons[i]); + } +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = pic32mz_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button interrupt support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) +{ +#ifdef CONFIG_PIC32MZ_GPIOIRQ_PORTD + int ret = OK; + + if ((unsigned)id < NUM_BUTTONS) + { + /* Perform the attach/detach operation */ + + ret = pic32mz_gpioattach(g_buttons[id], irqhandler, arg); + + /* The interrupt is now disabled. Are we attaching or detaching from + * button interrupt? + */ + + if (ret >= 0) + { + /* Attaching... enable button interrupts now */ + + pic32mz_gpioirqenable(g_buttons[id]); + } + } + + return ret; +#else + return -ENOSYS; +#endif +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/configs/flipnclick-pic32mz/src/pic32mz_spi.c b/configs/flipnclick-pic32mz/src/pic32mz_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..c1387b8054f66efe784516cc7ba8d0e8f65ab772 --- /dev/null +++ b/configs/flipnclick-pic32mz/src/pic32mz_spi.c @@ -0,0 +1,235 @@ +/************************************************************************************ + * configs/flipnclick-pic32mz/src/pic32mz_spi.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "up_arch.h" + +#include "flipnclick-pic32mz.h" + +#ifdef CONFIG_PIC32MZ_SPI + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: pic32mz_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Sure PIC32MZ board. + * + ************************************************************************************/ + +void weak_function pic32mz_spidev_initialize(void) +{ + /* Configure the SPI chip select GPIOs */ + +#warning "Missing logic" +} + +/************************************************************************************ + * Name: pic32mz_spiNselect, pic32mz_spiNstatus, and pic32mz_spiNcmddata + * + * Description: + * These external functions must be provided by board-specific logic. They are + * implementations of the select, status, and cmddata methods of the SPI interface + * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * including pic32mz_spibus_initialize()) are provided by common PIC32MZ logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in pic32mz_boardinitialize() to configure SPI/SPI chip select + * pins. + * 2. Provide pic32mz_spiNselect() and pic32mz_spiNstatus() functions + * in your board-specific logic. These functions will perform chip selection + * and status operations using GPIOs in the way your board is configured. + * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide + * pic32mz_spiNcmddata() functions in your board-specific logic. These + * functions will perform cmd/data selection operations using GPIOs in the way + * your board is configured. + * 3. Add a call to pic32mz_spibus_initialize() in your low level application + * initialization logic + * 4. The handle returned by pic32mz_spibus_initialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ************************************************************************************/ + +struct spi_dev_s; + +#ifdef CONFIG_PIC32MZ_SPI1 +void pic32mz_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +#warning "Missing logic" +} + +uint8_t pic32mz_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + spiinfo("Returning nothing\n"); +#warning "Missing logic" + return 0; +} +#ifdef CONFIG_SPI_CMDDATA +int pic32mz_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#warning "Missing logic" + return 0; +} +#endif +#endif + +#ifdef CONFIG_PIC32MZ_SPI2 +void pic32mz_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +#warning "Missing logic" +} + +uint8_t pic32mz_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + spiinfo("Returning nothing\n"); +#warning "Missing logic" + return 0; +} +#ifdef CONFIG_SPI_CMDDATA +int pic32mz_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#warning "Missing logic" + return 0; +} +#endif +#endif + +#ifdef CONFIG_PIC32MZ_SPI3 +void pic32mz_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +#warning "Missing logic" +} + +uint8_t pic32mz_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + spiinfo("Returning nothing\n"); +#warning "Missing logic" + return 0; +} +#ifdef CONFIG_SPI_CMDDATA +int pic32mz_spi3cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#warning "Missing logic" + return 0; +} +#endif +#endif + +#ifdef CONFIG_PIC32MZ_SPI4 +void pic32mz_spi4select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +#warning "Missing logic" +} + +uint8_t pic32mz_spi4status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + spiinfo("Returning nothing\n"); +#warning "Missing logic" + return 0; +} +#ifdef CONFIG_SPI_CMDDATA +int pic32mz_spi4cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#warning "Missing logic" + return 0; +} +#endif +#endif + +#ifdef CONFIG_PIC32MZ_SPI5 +void pic32mz_spi5select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +#warning "Missing logic" +} + +uint8_t pic32mz_spi5status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + spiinfo("Returning nothing\n"); +#warning "Missing logic" + return 0; +} +#ifdef CONFIG_SPI_CMDDATA +int pic32mz_spi5cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#warning "Missing logic" + return 0; +} +#endif +#endif + +#ifdef CONFIG_PIC32MZ_SPI6 +void pic32mz_spi6select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +#warning "Missing logic" +} + +uint8_t pic32mz_spi6status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + spiinfo("Returning nothing\n"); +#warning "Missing logic" + return 0; +} +#ifdef CONFIG_SPI_CMDDATA +int pic32mz_spi6cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#warning "Missing logic" + return 0; +} +#endif +#endif + +#endif /* CONFIG_PIC32MZ_SPI */ diff --git a/configs/flipnclick-pic32mz/src/pic32mz_userleds.c b/configs/flipnclick-pic32mz/src/pic32mz_userleds.c new file mode 100644 index 0000000000000000000000000000000000000000..ce5252b898b39249fa7b2943b161802a13a53b2c --- /dev/null +++ b/configs/flipnclick-pic32mz/src/pic32mz_userleds.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * configs/flipnclick-pic32mz/src/pic32mz_userleds.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/* There are four LEDs on the top, red side of the board. Only one can be + * controlled by software: + * + * LED L - RB14 (SPI3_SCK) + * + * There are also four LEDs on the back, white side of the board: + * + * LED A - RA6 + * LED B - RA7 + * LED C - RE0 + * LED D - RE1 + * + * A high output value illuminates the LEDs. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "pic32mz-gpio.h" +#include "flipnclick-pic32mz.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ +#ifndef CONFIG_ARCH_LEDS + /* Configure LED GPIOs for output */ + + pic32mz_configgpio(GPIO_LED_L); + pic32mz_configgpio(GPIO_LED_A); + pic32mz_configgpio(GPIO_LED_B); + pic32mz_configgpio(GPIO_LED_C); + pic32mz_configgpio(GPIO_LED_D); +#endif +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + uint32_t ledcfg; + + switch (led) + { +#ifndef CONFIG_ARCH_LEDS + case BOARD_LED_L: + ledcfg = GPIO_LED_L; + break; +#endif + + case BOARD_LED_A: + ledcfg = GPIO_LED_A; + break; + + case BOARD_LED_B: + ledcfg = GPIO_LED_B; + break; + + case BOARD_LED_C: + ledcfg = GPIO_LED_C; + break; + + case BOARD_LED_D: + ledcfg = GPIO_LED_D; + break; + + default: + return; + } + + pic32mz_gpiowrite(ledcfg, ledon); +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + bool ledon; + +#ifndef CONFIG_ARCH_LEDS + ledon = ((ledset & BOARD_LED_L_BIT) != 0); + pic32mz_gpiowrite(GPIO_LED_L, ledon); +#endif + + ledon = ((ledset & BOARD_LED_A_BIT) != 0); + pic32mz_gpiowrite(GPIO_LED_A, ledon); + + ledon = ((ledset & BOARD_LED_B_BIT) != 0); + pic32mz_gpiowrite(GPIO_LED_B, ledon); + + ledon = ((ledset & BOARD_LED_C_BIT) != 0); + pic32mz_gpiowrite(GPIO_LED_C, ledon); + + ledon = ((ledset & BOARD_LED_D_BIT) != 0); + pic32mz_gpiowrite(GPIO_LED_D, ledon); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/configs/flipnclick-sam3x/Kconfig b/configs/flipnclick-sam3x/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..166b712c2a9d0ca41732341b3702f528896af141 --- /dev/null +++ b/configs/flipnclick-sam3x/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_FLIPNCLICK_SAM3X +endif diff --git a/configs/flipnclick-sam3x/README.txt b/configs/flipnclick-sam3x/README.txt new file mode 100644 index 0000000000000000000000000000000000000000..38c319414f6c9229c69b7f4e343ec884916dee85 --- /dev/null +++ b/configs/flipnclick-sam3x/README.txt @@ -0,0 +1,500 @@ +README +====== + + This README discusses issues unique to NuttX configurations for the + Mikroe Flip&Click SAM3X board. This board is an Arduino-Due work-alike + with four Mikroe Click bus interfaces. Like the Arduino-Due, this board + features the Atmel ATSAM3X8E MCU running at 84 MHz. + + Thanks to John Legg for contributing the Flip&Click SAM3X board! + +Contents +======== + + - STATUS + - Buttons and LEDs + - Serial Consoles + - Loading Code + - Flip&Click SAM3X-specific Configuration Options + - Configurations + +STATUS +====== + + 2018-01-07: Created the configuration. At present it does not work; I + believe because of tool-related issues. I do the following: + + a) Open TeraTerm, select COM7 at 1200 baud, type a few ENTERs, and + close teraterm. + + b) Execute the following command which claims to have successfully + written to FLASH. + + bossac.exe --info --debug --port COM7 --usb-port=0 --erase --write --verify -b nuttx.bin -R + + But the code does not boot. There is no indication of life. + + c) Repeat a) then + + bossac.exe --info --debug --port COM7 --usb-port=0 --verify -b nuttx.bin + + And it says that the content of the FLASH is not good. + +Buttons and LEDs +================ + + Buttons + ------- + There are no buttons on the Flip&Click SAM3X board. + + LEDs + ---- + There are four LEDs on the top, blue side of the board. Only + one can be controlled by software: + + LED L - PB27 (PWM13) + + There are also four LEDs on the back, white side of the board: + + LED A - PC6 + LED B - PC5 + LED C - PC7 + LED D - PC8 + + A high output value illuminates the LEDs. + + These LEDs are available to the application and are all available to the + application unless CONFIG_ARCH_LEDS is defined. In that case, the usage + by the board port is defined in include/board.h and src/sam_autoleds.c. + The LEDs are used to encode OS-related events as follows: + + SYMBOL MEANING LED STATE + L A B C D + ---------------- ----------------------- --- --- --- --- --- + LED_STARTED NuttX has been started OFF ON OFF OFF OFF + LED_HEAPALLOCATE Heap has been allocated OFF OFF ON OFF OFF + LED_IRQSENABLED Interrupts enabled OFF OFF OFF ON OFF + LED_STACKCREATED Idle stack created OFF OFF OFF OFF ON + LED_INIRQ In an interrupt GLO N/C N/C N/C N/C + LED_SIGNAL In a signal handler GLO N/C N/C N/C N/C + LED_ASSERTION An assertion failed GLO N/C N/C N/C N/C + LED_PANIC The system has crashed 2Hz N/C N/C N/C N/C + LED_IDLE MCU is is sleep mode ---- Not used ----- + + Thus if LED L is glowing on and all other LEDs are off (except LED D which + was left on but is no longer controlled by NuttX and so may be in any + state), NuttX has successfully booted and is, apparently, running normally + and taking interrupts. If any of LEDs A-D are statically set, then NuttX + failed to boot and the LED indicates the initialization phase where the + failure occurred. If LED L is flashing at approximately 2Hz, then a fatal + error has been detected and the system has halted. + + NOTE: After booting, LEDs A-D are no longer used by the system and may + be controlled the application. + +Serial Consoles +=============== + + The SAM3X has a UART and 4 USARTS. The Programming port uses a USB-to- + serial chip connected to the first of the MCU (RX0 and TX0 on PA8 and PA9, + respectively). The output from that port is visible using the Arduino tool. + + Any of UART and USART0-3 may be used as a serial console. By default, + UART0 is used as the serial console in all configurations. But that is + easily changed by modifying the configuration as described under + "Configurations" below. + + Other convenient U[S]ARTs that may be used as the Serial console include: + + 1) An Arduino Serial Shield. The RX and TX pins are available on the + Arduino connector D0 and D1 pins, respectively. These are connected + to USART0, RXD0 and TXD0 which are PA10 and PA11, respectively. + + 2) Mikroe Click Serial Shield. There are four Click bus connectors with + serial ports available as follows: + + Click A: USART0 RXD0 and TXD0 which are, again, PA10 and PA11. + Click B: USART1 RXD1 and TXD1 which are PA12 and PA13, respectively. + Click C: USART3 RXD3 and TXD3 which are PD5 and PD4, respectively. + Click D: USART3 RXD3 and TXD3 which are, again, PD5 and PD4. + + Other serial ports are probably available on the Arduino connector. I + will leave that as an exercise for the interested reader. + + The outputs from these pins is 3.3V. You will need to connect RS232 + transceiver to get the signals to RS232 levels (or connect to the + USB virtual COM port in the case of UART0). + +Loading Code +============ + + Installing the Arduino USB Driver under Windows + ----------------------------------------------- + + 1. Download the Windows version of the Arduino software, not the 1.0.x + release but the latest (1.5.x or later) that supports the Arduino + Due. When the download finishes, unzip the downloaded file. + + In the current 1.8.x release, the Arduino Due support is not included + in the base package but can be added by selecting the "Boards Manager" + from the "Tools" menu. + + 2. Connect the Flip&Click to your computer with a USB cable via the + Programming port. + + 3. The Windows driver installation should fail. + + 4. Open the Device Manger + + 5. Look for the listing named "Ports (COM & LPT)". You should see an open + port named "Arduino Due Prog. Port". Right click and select "Update + driver". + + 6. Select the "Browse my computer for Driver software" option. + + 7. Right click on the "Arduino Due Prog. Port" and choose "Update Driver + Software". + + 8. Navigate to the folder with the Arduino IDE you downloaded and unzipped + earlier. Locate and select the "Drivers" folder in the main Arduino + folder (not the "FTDI USB Drivers" sub-directory). + + Loading NuttX to the Flip&Click Using Bossa + ------------------------------------------- + + Arduino uses BOSSA under the hood to load code and you can use BOSSA + outside of Arduino. + + Where do you get it? + + Generic BOSSA installation files are available here: + https://github.com/shumatech/BOSSA (formerly at + http://sourceforge.net/projects/b-o-s-s-a/?source=dlp) + + Pre-built binaries are available: https://github.com/shumatech/BOSSA/releases + + The original Arduino DUE used a patched version of BOSSA available + as source code here: https://github.com/shumatech/BOSSA/tree/arduino + But that has most likely been incorporated into the main github + repository. + + But, fortunately, since you already installed Arduino, you already have + BOSSA installed. In my installation, it is here: + + C:\Program Files (x86)\Arduino\arduino-1.5.2\hardware\tools\bossac.exe + + General Procedure + + 1) Erase the FLASH and put the Flip&Click in bootloader mode + 2) Write the file to FLASH + 3) Configure to boot from FLASH + 4) Reset the Flip&Click + + Erase FLASH and Put the Flip&Click in Bootloader Mode + + This is accomplished by simply configuring the programming port in 1200 + baud and sending something on the programming port. Here is some sample + output from a Windows CMD.exe shell. NOTE that my Arduino programming + port shows up as COM7. It may be different on your system. + + To enter boot mode, set the baud to 1200 and send anything to the + programming port: + + C:\Program Files (x86)\Arduino\arduino-1.5.2\hardware\tools>mode com26:1200,n,8,1 + + Status for device COM7: + ------------------------ + Baud: 1200 + Parity: None + Data Bits: 8 + Stop Bits: 1 + Timeout: ON + XON/XOFF: OFF + CTS handshaking: OFF + DSR handshaking: OFF + DSR sensitivity: OFF + DTR circuit: ON + RTS circuit: ON + + C:\Program Files (x86)\Arduino\arduino-1.5.2\hardware\tools>bossac.exe --port=COM7 --usb-port=false -i + Device : ATSAM3X8 + Version : v1.1 Dec 15 2010 19:25:04 + Address : 0x80000 + Pages : 2048 + Page Size : 256 bytes + Total Size : 512KB + Planes : 2 + Lock Regions : 32 + Locked : none + Security : false + Boot Flash : false + + Writing FLASH and Setting FLASH Boot Mode + + In a Cygwin BaSH shell: + + export PATH="/cygdrive/c/Program Files (x86)/Arduino/arduino-1.5.2/hardware/tools":$PATH + + Erasing, writing, and verifying FLASH with bossac: + + $ bossac.exe --port=COM7 --usb-port=false -e -w -v -b nuttx.bin -R + Erase flash + Write 86588 bytes to flash + [==============================] 100% (339/339 pages) + Verify 86588 bytes of flash + [==============================] 100% (339/339 pages) + Verify successful + Set boot flash true + CPU reset. + + Some things that can go wrong: + + $ bossac.exe --port=COM7 --usb-port=false -e -w -v -b nuttx.bin -R + No device found on COM7 + + This error means that there is code running on the Flip&Click already + so the bootloader cannot connect. Press reset and try again + + $ bossac.exe --port=COM7 --usb-port=false -e -w -v -b nuttx.bin -R + No device found on COM7 + + Sill No connection because the board does not jump to bootloader after + reset. Set the baud to 1200 and send something then try again + + $ bossac.exe --port=COM7 --usb-port=false -e -w -v -b nuttx.bin -R + Erase flash + Write 86588 bytes to flash + [==============================] 100% (339/339 pages) + Verify 86588 bytes of flash + [==============================] 100% (339/339 pages) + Verify successful + Set boot flash true + CPU reset. + + Other useful bossac operations. + + a) Write code to FLASH don't change boot mode and don't reset. This lets + you examine the FLASH contents that you just loaded while the bootloader + is still active. + + $ bossac.exe --port=COM7 --usb-port=false -e -w -v --boot=0 nuttx.bin + Write 64628 bytes to flash + [==============================] 100% (253/253 pages) + Verify 64628 bytes of flash + [==============================] 100% (253/253 pages) + Verify successful + + b) Verify the FLASH contents (the bootloader must be running) + + $ bossac.exe --port=COM7 --usb-port=false -v nuttx.bin + Verify 64628 bytes of flash + [==============================] 100% (253/253 pages) + Verify successful + + c) Read from FLASH to a file (the bootloader must be running): + + $ bossac.exe --port=COM7 --usb-port=false --read=4096 nuttx.dump + Read 4096 bytes from flash + [==============================] 100% (16/16 pages) + + d) Change to boot from FLASH + + $ bossac.exe --port=COM7 --usb-port=false --boot=1 + Set boot flash true + + Uploading NuttX to the Flip&Click Using JTAG + -------------------------------------------- + + The JTAG/SWD signals are brought out to a 10-pin header JTAG connector: + + PIN SIGNAL JTAG STANDARD NOTES + --- -------------- ----------------- -------------------------------- + 1 3.3V VTref + 2 JTAG_TMS SWDIO/TMS SAM3X pin 31, Pulled up on board + 3 GND GND + 4 JTAG_TCK SWDCLK/TCK SAM3X pin 28, Pulled up on board + 5 GND GND + 6 JTAG_TDO SWO/EXta/TRACECTL SAM3X pin 30, ulled up on board + 7 N/C Key + 8 JTAG_TDI NC/EXTb/TDI SAM3X pin 29, Pulled up on board + 9 GND GNDDetect + 10 MASTER-RESET nReset + + NOTE: The 10-pin JTAG connector is not populated on the Flip&Click SAM3X. + + You should be able to use a 10- to 20-pin adapter to connect a SAM-ICE + debugger to the Flip&Click SAM3X. I have this Olimex adapter: + https://www.olimex.com/Products/ARM/JTAG/ARM-JTAG-20-10/ . But so far I + have been unable to get the get the SAM-ICE to communicate with the + Flip&Click. + +Flip&Click SAM3X-specific Configuration Options +=============================================== + + CONFIG_ARCH - Identifies the arch/ subdirectory. This should + be set to: + + CONFIG_ARCH=arm + + CONFIG_ARCH_family - For use in C code: + + CONFIG_ARCH_ARM=y + + CONFIG_ARCH_architecture - For use in C code: + + CONFIG_ARCH_CORTEXM3=y + + CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory + + CONFIG_ARCH_CHIP="sam34" + + CONFIG_ARCH_CHIP_name - For use in C code to identify the exact + chip: + + CONFIG_ARCH_CHIP_SAM34 + CONFIG_ARCH_CHIP_SAM3X + CONFIG_ARCH_CHIP_ATSAM3X8E + + CONFIG_ARCH_BOARD - Identifies the configs/ subdirectory and + hence, the board that supports the particular chip or SoC. + + CONFIG_ARCH_BOARD=flipnclick-sam3x (for the Flip&Click SAM3X development board) + + CONFIG_ARCH_BOARD_name - For use in C code + + CONFIG_ARCH_BOARD_FLIPNCLICK_SAM3X=y + + CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation + of delay loops + + CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case): + + CONFIG_RAM_SIZE=65536 (64Kb) + + CONFIG_RAM_START - The start address of installed DRAM + + CONFIG_RAM_START=0x20000000 + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that + have LEDs + + Individual subsystems can be enabled: + + CONFIG_SAM34_ADC12B - 12-bit Analog To Digital Converter + CONFIG_SAM34_CAN0 - CAN Controller 0 + CONFIG_SAM34_CAN1 - CAN Controller 1 + CONFIG_SAM34_DACC - Digital To Analog Converter + CONFIG_SAM34_DMAC0 - DMA Controller + CONFIG_SAM34_EMAC - Ethernet MAC + CONFIG_SAM34_HSMCI - High Speed Multimedia Card Interface + CONFIG_SAM34_PWM - Pulse Width Modulation + CONFIG_SAM34_RTC - Real Time Clock + CONFIG_SAM34_RTT - Real Time Timer + CONFIG_SAM34_SDRAMC - SDRAM Controller + CONFIG_SAM34_SMC - Static Memory Controller + CONFIG_SAM34_SPI0 - Serial Peripheral Interface 0 + CONFIG_SAM34_SPI1 - Serial Peripheral Interface 1 + CONFIG_SAM34_SSC - Synchronous Serial Controller + CONFIG_SAM34_TC0 - Timer Counter 0 + CONFIG_SAM34_TC1 - Timer Counter 1 + CONFIG_SAM34_TC2 - Timer Counter 2 + CONFIG_SAM34_TC3 - Timer Counter 3 + CONFIG_SAM34_TC4 - Timer Counter 4 + CONFIG_SAM34_TC5 - Timer Counter 5 + CONFIG_SAM34_TC6 - Timer Counter 6 + CONFIG_SAM34_TC7 - Timer Counter 7 + CONFIG_SAM34_TC8 - Timer Counter 8 + CONFIG_SAM34_TRNG - True Random Number Generator + CONFIG_SAM34_TWIM/S0 - Two-Wire Interface 0 (master/slave) + CONFIG_SAM34_TWIM/S1 - Two-Wire Interface 1 (master/slave) + CONFIG_SAM34_UART0 - UART 0 + CONFIG_SAM34_UOTGHS - USB OTG High Speed + CONFIG_SAM34_USART0 - USART 0 + CONFIG_SAM34_USART1 - USART 1 + CONFIG_SAM34_USART2 - USART 2 + CONFIG_SAM34_USART3 - USART 3 + CONFIG_SAM34_WDT - Watchdog Timer + + Some subsystems can be configured to operate in different ways. The drivers + need to know how to configure the subsystem. + + CONFIG_SAM34_GPIOA_IRQ + CONFIG_SAM34_GPIOB_IRQ + CONFIG_SAM34_GPIOC_IRQ + CONFIG_SAM34_GPIOD_IRQ + CONFIG_SAM34_GPIOE_IRQ + CONFIG_SAM34_GPIOF_IRQ + +Configurations +^^^^^^^^^^^^^^ + + Each Flip&Click SAM3X configuration is maintained in a sub-directory and + can be selected as follow: + + tools/configure.sh [OPTIONS] flipnclick-sam3x/ + + Where typical options are -l to configure to build on Linux or -c to + configure for Cygwin under Linux. 'tools/configure.sh -h' will show + you all of the options. + + Before building, make sure the PATH environment variable includes the + correct path to the directory than holds your toolchain binaries. + + And then build NuttX by simply typing the following. At the conclusion of + the make, the nuttx binary will reside in an ELF file called, simply, + nuttx. + + make + + The that is provided above as an argument to the tools/configure.sh + must be is one of the following. + + NOTES: + + 1. These configurations use the mconf-based configuration tool. To + change any of these configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Unless stated otherwise, all configurations generate console + output on UART0 which is available both on the USB virtual COM port + and on the PWML connector (see the section "Serial Consoles" above). + + 3. Unless otherwise stated, the configurations are setup for + Cygwin under Windows: + + Build Setup: + CONFIG_HOST_WINDOWS=y : Microsoft Windows + CONFIG_WINDIWS_CYGWIN=y : Cygwin under Windoes + + 3. All of these configurations are set up to build under Windows using the + "GNU Tools for ARM Embedded Processors" that is maintained by ARM + (unless stated otherwise in the description of the configuration). + + https://developer.arm.com/open-source/gnu-toolchain/gnu-rm + + That toolchain selection can easily be reconfigured using + 'make menuconfig'. Here are the relevant current settings: + + System Type -> Toolchain: + CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain for Windows + +Configuration sub-directories +----------------------------- + + nsh: + This configuration directory will build the NuttShell. See NOTES above. + + NOTES: + 1. NSH built-in applications are supported. However, there are + no built-in applications built with the default configuration. + + Binary Formats: + CONFIG_BUILTIN=y : Enable support for built-in programs + + Application Configuration: + CONFIG_NSH_BUILTIN_APPS=y : Enable starting apps from NSH command line diff --git a/configs/flipnclick-sam3x/include/board.h b/configs/flipnclick-sam3x/include/board.h new file mode 100644 index 0000000000000000000000000000000000000000..0e2b42fe5d046c6cd3063da5d8a316bf736282af --- /dev/null +++ b/configs/flipnclick-sam3x/include/board.h @@ -0,0 +1,258 @@ +/************************************************************************************ + * configs/flipnclick-sam3x/include/board.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_FLIPNCLICK_SAM3X_INCLUDE_BOARD_H +#define __CONFIGS_FLIPNCLICK_SAM3X_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +# ifdef CONFIG_SAM34_GPIO_IRQ +# include +# endif +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* After power-on reset, the SAM3X device is running on a 4MHz internal RC. These + * definitions will configure clocking + * + * MAINOSC: Frequency = 12MHz (crystal) + * PLLA: PLL Divider = 1, Multiplier = 14 to generate PLLACK = 168MHz + * Master Clock (MCK): Source = PLLACK, Prescalar = 1 to generate MCK = 84MHz + * CPU clock: 84MHz + */ + +#define BOARD_32KOSC_FREQUENCY (32768) +#define BOARD_SCLK_FREQUENCY (BOARD_32KOSC_FREQUENCY) +#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */ + +/* Main oscillator register settings. + * + * The start up time should be should be: + * Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles. + */ + +#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */ + +/* PLLA configuration. + * + * Divider = 1 + * Multipler = 14 + */ + +#define BOARD_CKGR_PLLAR_MUL (13 << PMC_CKGR_PLLAR_MUL_SHIFT) +#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) +#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS + +/* PMC master clock register settings. + * + * Source = PLLA + * Divider = 2 + */ + +#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA +#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV2 + +/* USB UTMI PLL start-up time */ + +#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT) + +/* Resulting frequencies */ + +#define BOARD_PLLA_FREQUENCY (168000000) /* PLLACK: 14 * 12Mhz / 1 */ +#define BOARD_MCK_FREQUENCY (84000000) /* MCK: PLLACK / 2 */ +#define BOARD_CPU_FREQUENCY (84000000) /* CPU: MCK */ + +/* HSMCI clocking + * + * Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) + * divided by (2*(CLKDIV+1)). + * + * MCI_SPEED = MCCK / (2*(CLKDIV+1)) + * CLKDIV = MCCK / MCI_SPEED / 2 - 1 + * + * Where CLKDIV has a range of 0-255. + */ + +/* MCK = 84MHz, CLKDIV = 104, MCI_SPEED = 84MHz / 2 * (104+1) = 400 KHz */ + +#define HSMCI_INIT_CLKDIV (104 << HSMCI_MR_CLKDIV_SHIFT) + +/* MCK = 84MHz, CLKDIV = 2, MCI_SPEED = 84MHz / 2 * (2+1) = 14 MHz */ + +#define HSMCI_MMCXFR_CLKDIV (1 << HSMCI_MR_CLKDIV_SHIFT) + +/* MCK = 84MHz, CLKDIV = 1, MCI_SPEED = 84MHz / 2 * (1+1) = 21 MHz */ + +#define HSMCI_SDXFR_CLKDIV (1 << HSMCI_MR_CLKDIV_SHIFT) +#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV + +/* FLASH wait states + * + * FWS MAX FREQUENCY + * 1.62V 1.8V + * --- ----- ------ + * 0 17MHz 19MHz + * 1 45MHz 50MHz + * 2 58MHz 64MHz + * 3 70MHz 80MHz + * 4 78MHz 90MHz + */ + +#define BOARD_FWS 4 + +/* LED definitions ******************************************************************/ +/* There are four LEDs on the top, blue side of the board. Only one can be + * controlled by software: + * + * LED L - PB27 (PWM13) + * + * There are also four LEDs on the back, white side of the board: + * + * LED A - PC6 + * LED B - PC5 + * LED C - PC7 + * LED D - PC8 + * + * A high output value illuminates the LEDs. + */ + +#ifdef CONFIG_ARCH_LEDS +/* LED index values for use with board_userled(): */ + +# define BOARD_LED_A 0 +# define BOARD_LED_B 1 +# define BOARD_LED_C 2 +# define BOARD_LED_D 3 +# define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +# define BOARD_LED_A_BIT (1 << BOARD_LED_A) +# define BOARD_LED_B_BIT (1 << BOARD_LED_B) +# define BOARD_LED_C_BIT (1 << BOARD_LED_C) +# define BOARD_LED_D_BIT (1 << BOARD_LED_D) +#else +/* LED index values for use with board_userled(): */ + +# define BOARD_LED_L 0 +# define BOARD_LED_A 1 +# define BOARD_LED_B 2 +# define BOARD_LED_C 3 +# define BOARD_LED_D 4 +# define BOARD_NLEDS 5 + +/* LED bits for use with board_userled_all() */ + +# define BOARD_LED_L_BIT (1 << BOARD_LED_L) +# define BOARD_LED_A_BIT (1 << BOARD_LED_A) +# define BOARD_LED_B_BIT (1 << BOARD_LED_B) +# define BOARD_LED_C_BIT (1 << BOARD_LED_C) +# define BOARD_LED_D_BIT (1 << BOARD_LED_D) +#endif + +/* These LEDs are available to the application and are all available to the + * application unless CONFIG_ARCH_LEDS is defined. In that case, the usage by the + * board port is defined in include/board.h and src/sam_autoleds.c. The LEDs are + * used to encode OS-related events as follows: + * + * SYMBOL MEANING LED STATE + * L A B C D + * ---------------- ----------------------- --- --- --- --- ---*/ +#define LED_STARTED 0 /* NuttX has been started OFF ON OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON OFF OFF */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF OFF OFF ON OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF OFF OFF OFF ON */ +#define LED_INIRQ 4 /* In an interrupt GLO N/C N/C N/C N/C */ +#define LED_SIGNAL 4 /* In a signal handler GLO N/C N/C N/C N/C */ +#define LED_ASSERTION 4 /* An assertion failed GLO N/C N/C N/C N/C */ +#define LED_PANIC 4 /* The system has crashed 2Hz N/C N/C N/C N/C */ +#undef LED_IDLE /* MCU is is sleep mode ---- Not used ----- */ + +/* Thus if LED L is glowing on and all other LEDs are off (except LED D which + * was left on but is no longer controlled by NuttX and so may be in any state), + * NuttX has successfully booted and is, apparently, running normally and taking + * interrupts. If any of LEDs A-D are statically set, then NuttX failed to boot + * and the LED indicates the initialization phase where the failure occurred. If + * LED L is flashing at approximately 2Hz, then a fatal error has been detected and + * the system has halted. + * + * NOTE: After booting, LEDs A-D are no longer used by the system and may be + * controlled the application. + */ + +/* Button definitions ***************************************************************/ +/* There are no buttons on the Arduino Due board. */ + +/* GPIO pin configurations **********************************************************/ +/* Universal Asynchronous Receiver Transceiver (UART) + * + * The SAM3X has a UART and 4 USARTS. The Programming port uses a USB-to- + * serial chip connected to the first of the MCU (RX0 and TX0 on PA8 and PA9, + * respectively). The output from that port is visible using the Arduino tool. + * + * Any of UART and USART0-3 may be used as a serial console. By default, + * UART0 is used as the serial console in all configurations. + * + * There are no alternatives for these pins. + */ + +/* Universal Synchronous Asynchronous Receiver Transmitter (USART) + * + * The RX and TX pins are available on the Arduino connector D0 and D1 pins, + * respectively. These are connected to USART0, RXD0 and TXD0 which are PA10 + * and PA11, respectively. + * + * There are four Click bus connectors with serial ports available as follows: + * + * Click A: USART0 RXD0 and TXD0 which are, again, PA10 and PA11. + * Click B: USART1 RXD1 and TXD1 which are PA12 and PA13, respectively. + * Click C: USART3 RXD3 and TXD3 which are PD5 and PD4, respectively. + * Click D: USART3 RXD3 and TXD3 which are, again, PD5 and PD4. + * + * There are no alternatives for these pins. + */ + +#endif /* __CONFIGS_FLIPNCLICK_SAM3X_INCLUDE_BOARD_H */ diff --git a/configs/flipnclick-sam3x/nsh/defconfig b/configs/flipnclick-sam3x/nsh/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..79057461ad69e6838a1c971524cd704d86776fa6 --- /dev/null +++ b/configs/flipnclick-sam3x/nsh/defconfig @@ -0,0 +1,44 @@ +# CONFIG_ARCH_RAMFUNCS is not set +CONFIG_ARCH_BOARD_FLIPNCLICK_SAM3X=y +CONFIG_ARCH_BOARD="flipnclick-sam3x" +CONFIG_ARCH_CHIP_ATSAM3X8E=y +CONFIG_ARCH_CHIP_SAM34=y +CONFIG_ARCH_CHIP_SAM3X=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="arm" +CONFIG_BOARD_LOOPSPERMSEC=6965 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_POLL=y +CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y +CONFIG_EXAMPLES_NSH=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=3 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=28 +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2013 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/flipnclick-sam3x/scripts/Make.defs b/configs/flipnclick-sam3x/scripts/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..d012d9e51e6b3162997e48e64d805f28193c00ad --- /dev/null +++ b/configs/flipnclick-sam3x/scripts/Make.defs @@ -0,0 +1,109 @@ +############################################################################ +# configs/flipnclick-sam3x/scripts/Make.defs +# +# Copyright (C) 2018 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/flash.ld}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/flash.ld +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/configs/flipnclick-sam3x/scripts/flash.ld b/configs/flipnclick-sam3x/scripts/flash.ld new file mode 100644 index 0000000000000000000000000000000000000000..f40dea61ead452935cda1b111f1ffeed66ff54bf --- /dev/null +++ b/configs/flipnclick-sam3x/scripts/flash.ld @@ -0,0 +1,131 @@ +/**************************************************************************** + * configs/flipnclick-sam3x/scripts/flash.ld + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The ATSAM3X8E has 512KB of FLASH beginning at address 0x0008:0000 and + * up to 100KB SRAM in three memory regions. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00080000, LENGTH = 512K + sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K + sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 32K + nfcram (rwx) : ORIGIN = 0x20100000, LENGTH = 4K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : + { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : + { + *(.ARM.extab*) + } >flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } >flash + __exidx_end = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram0 AT > flash + + _eronly = LOADADDR(.data); + + .ramfunc ALIGN(4): + { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > sram0 AT > flash + + _framfuncs = LOADADDR(.ramfunc); + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram0 + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/flipnclick-sam3x/src/.gitignore b/configs/flipnclick-sam3x/src/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..726d936e1e3390cc875a1fa5681e3c3988fe3c8b --- /dev/null +++ b/configs/flipnclick-sam3x/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/configs/flipnclick-sam3x/src/Makefile b/configs/flipnclick-sam3x/src/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..b2e781f6a9d42a7b130eadef06ee72fe9aab266e --- /dev/null +++ b/configs/flipnclick-sam3x/src/Makefile @@ -0,0 +1,51 @@ +############################################################################ +# configs/flipnclick-sam3x/src/Makefile +# +# Copyright (C) 2018 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = sam_boot.c sam_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += sam_autoleds.c +else +CSRCS += sam_userleds.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += sam_appinit.c +endif + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/flipnclick-sam3x/src/flipnclick-sam3x.h b/configs/flipnclick-sam3x/src/flipnclick-sam3x.h new file mode 100644 index 0000000000000000000000000000000000000000..e35dacbe6d1e3ceb03915d009ecef366e2c706b3 --- /dev/null +++ b/configs/flipnclick-sam3x/src/flipnclick-sam3x.h @@ -0,0 +1,114 @@ +/************************************************************************************ + * configs/flipnclick-sam3x/src/flipnclick-sam3x.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_FLIPNCLICK_SAM3X_SRC_ARDUNO_DUE_H +#define __CONFIGS_FLIPNCLICK_SAM3X_SRC_ARDUNO_DUE_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include + +#include +#include + +#include "chip/sam_pinmap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* There are four LEDs on the top, blue side of the board. Only one can be + * controlled by software: + * + * LED L - PB27 (PWM13) + * + * There are also four LEDs on the back, white side of the board: + * + * LED A - PC6 + * LED B - PC5 + * LED C - PC7 + * LED D - PC8 + * + * A high output value illuminates the LEDs. + */ + +#define GPIO_LED_L (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_CLEAR | \ + GPIO_PORT_PIOB | GPIO_PIN27) +#define GPIO_LED_A (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_CLEAR | \ + GPIO_PORT_PIOC | GPIO_PIN6) +#define GPIO_LED_B (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_CLEAR | \ + GPIO_PORT_PIOC | GPIO_PIN5) +#define GPIO_LED_C (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_CLEAR | \ + GPIO_PORT_PIOC | GPIO_PIN7) +#define GPIO_LED_D (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_CLEAR | \ + GPIO_PORT_PIOC | GPIO_PIN8) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: sam_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int sam_bringup(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_FLIPNCLICK_SAM3X_SRC_ARDUNO_DUE_H */ + diff --git a/configs/flipnclick-sam3x/src/sam_appinit.c b/configs/flipnclick-sam3x/src/sam_appinit.c new file mode 100644 index 0000000000000000000000000000000000000000..55499d73e5db5fff9ce32e7130101a70f1a21467 --- /dev/null +++ b/configs/flipnclick-sam3x/src/sam_appinit.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * config/flipnclick-sam3x/src/sam_appinit.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "flipnclick-sam3x.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef OK +# define OK 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_INITIALIZE + /* Board initialization already performed by board_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return sam_bringup(); +#endif +} diff --git a/configs/flipnclick-sam3x/src/sam_autoleds.c b/configs/flipnclick-sam3x/src/sam_autoleds.c new file mode 100644 index 0000000000000000000000000000000000000000..3f0b450178d88468c1e0d98d9a68e36cfc1e0b37 --- /dev/null +++ b/configs/flipnclick-sam3x/src/sam_autoleds.c @@ -0,0 +1,228 @@ +/**************************************************************************** + * configs/flipnclick-sam3x/src/sam_autoleds.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/* There are four LEDs on the top, blue side of the board. Only one can be + * controlled by software: + * + * LED L - PB27 (PWM13) + * + * There are also four LEDs on the back, white side of the board: + * + * LED A - PC6 + * LED B - PC5 + * LED C - PC7 + * LED D - PC8 + * + * A high output value illuminates the LEDs. + * + * These LEDs are available to the application and are all available to the + * application unless CONFIG_ARCH_LEDS is defined. In that case, the usage + * by the board port is defined in include/board.h and src/sam_autoleds.c. + * The LEDs are used to encode OS-related events as follows: + * + * SYMBOL MEANING LED STATE + * L A B C D + * ---------------- ----------------------- --- --- --- --- --- + * LED_STARTED NuttX has been started OFF ON OFF OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF ON OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF OFF ON OFF + * LED_STACKCREATED Idle stack created OFF OFF OFF OFF ON + * LED_INIRQ In an interrupt GLO N/C N/C N/C N/C + * LED_SIGNAL In a signal handler GLO N/C N/C N/C N/C + * LED_ASSERTION An assertion failed GLO N/C N/C N/C N/C + * LED_PANIC The system has crashed 2Hz N/C N/C N/C N/C + * LED_IDLE MCU is is sleep mode ---- Not used ----- + * + * Thus if LED L is glowing on and all other LEDs are off (except LED D + * which was left on but is no longer controlled by NuttX and so may be in + * any state), NuttX has successfully booted and is, apparently, running + * normally and taking interrupts. If any of LEDs A-D are statically set, + * then NuttX failed to boot and the LED indicates the initialization phase + * where the failure occurred. If LED L is flashing at approximately 2Hz, + * then a fatal error has been detected and the system has halted. + * + * NOTE: After booting, LEDs A-D are no longer used by the system and may + * be controlled the application. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "sam_gpio.h" +#include "flipnclick-sam3x.h" + +/* The board.h file may override pin configurations defined in sam_pinmap.h */ + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Processor Definitinos + ****************************************************************************/ + +/* LED indices */ + +#define INDEX_LED_L 0 +#define INDEX_LED_A 1 +#define INDEX_LED_B 2 +#define INDEX_LED_C 3 +#define INDEX_LED_D 4 +#define NLEDS 5 + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void board_autoled_setone(int ledndx) +{ + bool ledon[NLEDS] = {false, false, false, false, false}; + + ledon[ledndx] = true; + sam_gpiowrite(GPIO_LED_L, ledon[INDEX_LED_L]); + sam_gpiowrite(GPIO_LED_A, ledon[INDEX_LED_A]); + sam_gpiowrite(GPIO_LED_B, ledon[INDEX_LED_B]); + sam_gpiowrite(GPIO_LED_C, ledon[INDEX_LED_D]); + sam_gpiowrite(GPIO_LED_D, ledon[INDEX_LED_D]); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + sam_configgpio(GPIO_LED_L); + sam_configgpio(GPIO_LED_A); + sam_configgpio(GPIO_LED_B); + sam_configgpio(GPIO_LED_C); + sam_configgpio(GPIO_LED_D); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + /* SYMBOL MEANING LED STATE + * L A B C D + * ------------------- ----------------------- --- --- --- --- --- + * LED_STARTED 0 NuttX has been started OFF ON OFF OFF OFF + * LED_HEAPALLOCATE 1 Heap has been allocated OFF OFF ON OFF OFF + * LED_IRQSENABLED 2 Interrupts enabled OFF OFF OFF ON OFF + * LED_STACKCREATED 3 Idle stack created OFF OFF OFF OFF ON + * LED_INIRQ 4 In an interrupt GLO N/C N/C N/C N/C + * LED_SIGNAL 4 In a signal handler GLO N/C N/C N/C N/C + * LED_ASSERTION 4 An assertion failed GLO N/C N/C N/C N/C + * LED_PANIC 4 The system has crashed 2Hz N/C N/C N/C N/C + */ + + switch (led) + { + default: + case 0: + board_autoled_setone(INDEX_LED_A); + break; + + case 1: + board_autoled_setone(INDEX_LED_B); + break; + + case 2: + board_autoled_setone(INDEX_LED_C); + break; + + case 3: + board_autoled_setone(INDEX_LED_D); + break; + + case 4: + sam_gpiowrite(GPIO_LED_L, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + /* SYMBOL MEANING LED STATE + * L A B C D + * ------------------- ----------------------- --- --- --- --- --- + * LED_STARTED 0 NuttX has been started OFF ON OFF OFF OFF + * LED_HEAPALLOCATE 1 Heap has been allocated OFF OFF ON OFF OFF + * LED_IRQSENABLED 2 Interrupts enabled OFF OFF OFF ON OFF + * LED_STACKCREATED 3 Idle stack created OFF OFF OFF OFF ON + * LED_INIRQ 4 In an interrupt GLO N/C N/C N/C N/C + * LED_SIGNAL 4 In a signal handler GLO N/C N/C N/C N/C + * LED_ASSERTION 4 An assertion failed GLO N/C N/C N/C N/C + * LED_PANIC 4 The system has crashed 2Hz N/C N/C N/C N/C + */ + + switch (led) + { + default: + sam_gpiowrite(GPIO_LED_L, false); + sam_gpiowrite(GPIO_LED_A, false); + sam_gpiowrite(GPIO_LED_B, false); + sam_gpiowrite(GPIO_LED_C, false); + sam_gpiowrite(GPIO_LED_D, false); + break; + + case 4: + sam_gpiowrite(GPIO_LED_L, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/flipnclick-sam3x/src/sam_boot.c b/configs/flipnclick-sam3x/src/sam_boot.c new file mode 100644 index 0000000000000000000000000000000000000000..3762c8f944f989506530492d09a2a76d70db05fa --- /dev/null +++ b/configs/flipnclick-sam3x/src/sam_boot.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * configs/flipnclick-sam3x/src/sam_boot.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "flipnclick-sam3x.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_boardinitialize + * + * Description: + * All SAM3/4 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void sam_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ + /* Perform board-specific initialization */ + + (void)sam_bringup(); +} +#endif diff --git a/configs/xtrs/src/xtr_timerisr.c b/configs/flipnclick-sam3x/src/sam_bringup.c similarity index 75% rename from configs/xtrs/src/xtr_timerisr.c rename to configs/flipnclick-sam3x/src/sam_bringup.c index c05c661b35e372d39d86d47b61582493bf2710ae..28a9d427357e4fce8bca49ed72c1b95a54a6b6a9 100644 --- a/configs/xtrs/src/xtr_timerisr.c +++ b/configs/flipnclick-sam3x/src/sam_bringup.c @@ -1,7 +1,7 @@ /**************************************************************************** - * configs/xtrs/src/xtr_timerisr.c + * config/flipnclick-sam3x/src/sam_bringup.c * - * Copyright (C) 2008-2009, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -39,44 +39,51 @@ #include -#include +#include +#include +#include -#include +#include -#include "clock/clock.h" -#include "up_internal.h" +#include "flipnclick-sam3x.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Function: xtrs_timerisr + * Name: sam_bringup * * Description: - * The timer ISR will perform a variety of services for various portions of - * the system. + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library * ****************************************************************************/ -int xtrs_timerisr(int irq, FAR chipreg_t *regs, FAR void *arg) +int sam_bringup(void) { - /* Process timer interrupt */ + int ret; - sched_process_timer(); - return 0; -} +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ -/**************************************************************************** - * Function: xtrs_timer_initialize - * - * Description: - * This function is called during start-up to initialize the timer - * interrupt. - * - ****************************************************************************/ + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR,"ERROR: Failed to mount procfs at /proc: %d\n", + ret); + } +#endif -void xtrs_timer_initialize(void) -{ - /* The timer interrupt was attached in up_irqinitialize -- see comments there */ + UNUSED(ret); + return OK; } diff --git a/configs/flipnclick-sam3x/src/sam_userleds.c b/configs/flipnclick-sam3x/src/sam_userleds.c new file mode 100644 index 0000000000000000000000000000000000000000..7b01e6a20f6ee2691d286f88c3bc82d393985eb4 --- /dev/null +++ b/configs/flipnclick-sam3x/src/sam_userleds.c @@ -0,0 +1,154 @@ +/**************************************************************************** + * configs/flipnclick-sam3x/src/sam_userleds.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/* There are four LEDs on the top, blue side of the board. Only one can be + * controlled by software: + * + * LED L - PB27 (PWM13) + * + * There are also four LEDs on the back, white side of the board: + * + * LED A - PC6 + * LED B - PC5 + * LED C - PC7 + * LED D - PC8 + * + * A high output value illuminates the LEDs. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "sam_gpio.h" +#include "flipnclick-sam3x.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ +#ifndef CONFIG_ARCH_LEDS + /* Configure LED GPIOs for output */ + + sam_configgpio(GPIO_LED_L); + sam_configgpio(GPIO_LED_A); + sam_configgpio(GPIO_LED_B); + sam_configgpio(GPIO_LED_C); + sam_configgpio(GPIO_LED_D); +#endif +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + uint32_t ledcfg; + + switch (led) + { +#ifndef CONFIG_ARCH_LEDS + case BOARD_LED_L: + ledcfg = GPIO_LED_L; + break; +#endif + + case BOARD_LED_A: + ledcfg = GPIO_LED_A; + break; + + case BOARD_LED_B: + ledcfg = GPIO_LED_B; + break; + + case BOARD_LED_C: + ledcfg = GPIO_LED_C; + break; + + case BOARD_LED_D: + ledcfg = GPIO_LED_D; + break; + + default: + return; + } + + sam_gpiowrite(ledcfg, ledon); +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + bool ledon; + +#ifndef CONFIG_ARCH_LEDS + ledon = ((ledset & BOARD_LED_L_BIT) != 0); + sam_gpiowrite(GPIO_LED_L, ledon); +#endif + + ledon = ((ledset & BOARD_LED_A_BIT) != 0); + sam_gpiowrite(GPIO_LED_A, ledon); + + ledon = ((ledset & BOARD_LED_B_BIT) != 0); + sam_gpiowrite(GPIO_LED_B, ledon); + + ledon = ((ledset & BOARD_LED_C_BIT) != 0); + sam_gpiowrite(GPIO_LED_C, ledon); + + ledon = ((ledset & BOARD_LED_D_BIT) != 0); + sam_gpiowrite(GPIO_LED_D, ledon); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/configs/freedom-k64f/README.txt b/configs/freedom-k64f/README.txt index 906c8a4a6c967d7feaaf58fcc5e3d975e4689cbf..5559b2fe5f1363fc99c9ae7fba92f4575446f1fc 100644 --- a/configs/freedom-k64f/README.txt +++ b/configs/freedom-k64f/README.txt @@ -453,7 +453,7 @@ SD Card Support CONFIG_MMCSD=y : Enable MMC/SD support CONFIG_MMSCD_NSLOTS=1 : One slot per driver instance CONFIG_MMCSD_MULTIBLOCK_DISABLE=y : (REVISIT) - CONFIG_MMCSD_HAVECARDDETECT=y : Supports card-detect PIOs + CONFIG_MMCSD_HAVE_CARDDETECT=y : Supports card-detect PIOs CONFIG_MMCSD_MMCSUPPORT=n : Interferes with some SD cards CONFIG_MMCSD_SPI=n : No SPI-based MMC/SD support CONFIG_MMCSD_SDIO=y : SDIO-based MMC/SD support diff --git a/configs/freedom-k64f/include/board.h b/configs/freedom-k64f/include/board.h index b88e37a160f991a5547466ca87d8513cb4cdedc8..34b682d691b093948b87b626614092a01ebde3fe 100644 --- a/configs/freedom-k64f/include/board.h +++ b/configs/freedom-k64f/include/board.h @@ -255,41 +255,4 @@ #define PIN_UART3_RX PIN_UART3_RX_2 #define PIN_UART3_TX PIN_UART3_TX_2 -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: kinetis_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void kinetis_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_FREEDOM_K64F_INCLUDE_BOARD_H */ diff --git a/configs/freedom-k66f/README.txt b/configs/freedom-k66f/README.txt index b1283e8dc9f66c988b34fccfb3bf5f08b1044f3c..7f5da7cffaa2a67a14457a2e98600406c73e9e3c 100644 --- a/configs/freedom-k66f/README.txt +++ b/configs/freedom-k66f/README.txt @@ -456,7 +456,7 @@ SD Card Support CONFIG_MMCSD=y : Enable MMC/SD support CONFIG_MMSCD_NSLOTS=1 : One slot per driver instance CONFIG_MMCSD_MULTIBLOCK_DISABLE=y : (REVISIT) - CONFIG_MMCSD_HAVECARDDETECT=y : Supports card-detect PIOs + CONFIG_MMCSD_HAVE_CARDDETECT=y : Supports card-detect PIOs CONFIG_MMCSD_MMCSUPPORT=n : Interferes with some SD cards CONFIG_MMCSD_SPI=n : No SPI-based MMC/SD support CONFIG_MMCSD_SDIO=y : SDIO-based MMC/SD support diff --git a/configs/freedom-k66f/include/board.h b/configs/freedom-k66f/include/board.h index d69bb153a1f51de5b8ff4b1f1daa4b69d535fe5e..7eb48239e69f5fd7742102d81582dd4cf586a881 100644 --- a/configs/freedom-k66f/include/board.h +++ b/configs/freedom-k66f/include/board.h @@ -405,41 +405,4 @@ #define PIN_RMII0_MDIO PIN_RMII0_MDIO_1 #define PIN_RMII0_MDC PIN_RMII0_MDC_1 -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: kinetis_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void kinetis_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_FREEDOM_K66F_INCLUDE_BOARD_H */ diff --git a/configs/freedom-kl25z/include/board.h b/configs/freedom-kl25z/include/board.h index 129a9b285a768e966048061ee8d88dbc7ffdac3e..918b00d73de63d73351bc18a2d715d1936ecb1b3 100644 --- a/configs/freedom-kl25z/include/board.h +++ b/configs/freedom-kl25z/include/board.h @@ -250,17 +250,6 @@ extern "C" { /************************************************************************************ * Public Function Prototypes ************************************************************************************/ -/************************************************************************************ - * Name: kl_boardinitialize - * - * Description: - * All Kinetis L architectures must provide the following entry point. This entry - * point is called early in the intitialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void kl_boardinitialize(void); /************************************************************************************ * Name: kl_tsi_initialize diff --git a/configs/freedom-kl26z/include/board.h b/configs/freedom-kl26z/include/board.h index c498cdd893a07a119bf09a1adf5c14060010a8d6..8ae3212271fc599b4858844968850885cbc856e2 100644 --- a/configs/freedom-kl26z/include/board.h +++ b/configs/freedom-kl26z/include/board.h @@ -235,17 +235,6 @@ extern "C" /************************************************************************************ * Public Function Prototypes ************************************************************************************/ -/************************************************************************************ - * Name: kl_boardinitialize - * - * Description: - * All Kinetis L architectures must provide the following entry point. This entry - * point is called early in the initialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void kl_boardinitialize(void); /************************************************************************************ * Name: kl_tsi_initialize diff --git a/configs/hymini-stm32v/README.txt b/configs/hymini-stm32v/README.txt index 0ec191311297c4b4af5ad50a019fbcd2a09da367..6726c45992840eab7a9e32745a520ac2d44a40f9 100644 --- a/configs/hymini-stm32v/README.txt +++ b/configs/hymini-stm32v/README.txt @@ -7,209 +7,12 @@ HY-MiniSTM32V development board. Contents ======== - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - ST Bootloader - LEDs - RTC - HY-Mini specific Configuration Options - Configurations -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -===================== - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The devkitARM GNU toolchain, - 3. Raisonance GNU toolchain, or - 4. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the NuttX buildroot toolchain. However, - the make system is setup to default to use the devkitARM toolchain. To use - the CodeSourcery, devkitARM or Raisonance GNU toolchain, you simply need to - add one of the following configuration options to your .config (or defconfig) - file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE=y : Raisonance RIDE7 under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE: the CodeSourcery (for Windows), devkitARM, and Raisonance toolchains are - Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/stm32, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/stm32/stm32_vectors.S. You many have to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by an IDE. - -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh hymini-stm32v/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh hymini-stm32v/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - ST Bootloader ============= @@ -483,7 +286,7 @@ HY-Mini specific Configuration Options Default: Medium CONFIG_STM32_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default: 4-bit transfer mode. - CONFIG_MMCSD_HAVECARDDETECT - Select if SDIO driver card detection + CONFIG_MMCSD_HAVE_CARDDETECT - Select if SDIO driver card detection is 100% accurate (it is on the HY-MiniSTM32V) HY-MiniSTM32V CAN Configuration diff --git a/configs/hymini-stm32v/include/board.h b/configs/hymini-stm32v/include/board.h index 4bbb1b92ba86fd65ad0b30dda887848c67d35b3b..4c711bce41cb3380a67af87ad22f253326c95f21 100644 --- a/configs/hymini-stm32v/include/board.h +++ b/configs/hymini-stm32v/include/board.h @@ -181,40 +181,4 @@ #define BUTTON_KEYA_BIT (1 << BUTTON_KEYA) #define BUTTON_KEYB_BIT (1 << BUTTON_KEYB) - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/hymini-stm32v/nsh2/defconfig b/configs/hymini-stm32v/nsh2/defconfig index af03612f1a7024bc8cdba5ff3ded9acf5c6bb331..497fdf4a5d8120f200a4855b39c7cd0502e15716 100644 --- a/configs/hymini-stm32v/nsh2/defconfig +++ b/configs/hymini-stm32v/nsh2/defconfig @@ -3,6 +3,7 @@ # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set # CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_SPI_CALLBACK is not set CONFIG_ARCH_BOARD_HYMINI_STM32V=y CONFIG_ARCH_BOARD="hymini-stm32v" diff --git a/configs/hymini-stm32v/usbmsc/defconfig b/configs/hymini-stm32v/usbmsc/defconfig index bc5e803748d9fe23ae838fad588cc587f1942bc1..722fb02dbc2cf7b382452d12b1c617d68f7eb030 100644 --- a/configs/hymini-stm32v/usbmsc/defconfig +++ b/configs/hymini-stm32v/usbmsc/defconfig @@ -1,4 +1,4 @@ -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set CONFIG_ARCH_BOARD_HYMINI_STM32V=y CONFIG_ARCH_BOARD="hymini-stm32v" diff --git a/configs/indium-f7/Kconfig b/configs/indium-f7/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..bdf0fe36670bdf50701dddf57e42e4e1a19cea04 --- /dev/null +++ b/configs/indium-f7/Kconfig @@ -0,0 +1,213 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "Using Nucleo-144-F7 Board." +choice + prompt "Select Clock Source." + default INDIUM_CLOCK_MCO + ---help--- + Select the final clock source. + + MCO - Clock provided by the ST-LINK + + HSI - Internal High Speed Oscillator. + +config INDIUM_CLOCK_MCO + bool "MCO 8-MHz" + +config INDIUM_CLOCK_HSI + bool "HSI 16-MHz" + +endchoice # "Select Clock Source." + +choice + prompt "Select Console wiring." + default INDIUM_CONSOLE_MORPHO_UART4 + ---help--- + Select where you will connect the console. + + Virtual COM Port: + + Advantage: Use the ST-Link as a console. No Extra wiring + neded. + + Disdvantage: Not the best choice for initanl bring up. + + ARDUINO Connector: + + Advantage: You have a shield so it is + easy. + + Disdvantage: You loose the use of the + other functions on PC6, PC7 + + STM32F7 + ARDUIONO FUNCTION GPIO + -- ----- --------- ---- + DO RX USART6_RX PG9 + D1 TX USART6_TX PG14 + -- ----- --------- --- + + OR + + Morpho Connector: + + STM32F7 + MORPHO FUNCTION GPIO + -------- --------- ----- + CN12-64 UART8_RX PE0 + CN11-61 UART8_TX PE1 + -------- --------- ----- + + OR + + Morpho Connector UART4: + + STM32F7 + MORPHO FUNCTION GPIO + -------- --------- ----- + CN11-30 UART4_RX PA0 + CN11-28 UART4_TX PA1 + -------- --------- ----- + Note: SB13 must be removed to disable Ethernet. + +config INDIUM_CONSOLE_ARDUINO + bool "Arduino Connector" + select STM32F7_USART6 + select USART6_SERIALDRIVER + select USART6_SERIAL_CONSOLE + +config INDIUM_CONSOLE_VIRTUAL + bool "Virtual Comport" + select STM32F7_USART3 + select USART3_SERIALDRIVER + select USART3_SERIAL_CONSOLE + +config INDIUM_CONSOLE_MORPHO + bool "Morpho Connector" + select STM32F7_UART8 + select UART8_SERIALDRIVER + select UART8_SERIAL_CONSOLE + +config INDIUM_CONSOLE_MORPHO_UART4 + bool "Morpho Connector UART4" + select STM32F7_UART4 + select UART4_SERIALDRIVER + select UART4_SERIAL_CONSOLE + +config INDIUM_CONSOLE_NONE + bool "No Console" + +endchoice # "Select Console wiring" + +config NUCLEO_SPI_TEST + bool "Enable SPI test" + default n + ---help--- + Enable Spi test - initalize and configure SPI to send + NUCLEO_SPI_TEST_MESSAGE text. The text is sent on the + selected SPI Buses with the configured parameters. + Note the CS lines will not be asserted. + +if NUCLEO_SPI_TEST + +config NUCLEO_SPI_TEST_MESSAGE + string "Text to Send on SPI Bus(es)" + default "Hello World" + depends on NUCLEO_SPI_TEST + ---help--- + Text to sent on SPI bus(es) + +config NUCLEO_SPI1_TEST + bool "Test SPI bus 1" + default n + depends on NUCLEO_SPI_TEST + ---help--- + Enable Spi test - on SPI BUS 1 + +if NUCLEO_SPI1_TEST + +config NUCLEO_SPI1_TEST_FREQ + int "SPI 1 Clock Freq in Hz" + default 1000000 + depends on NUCLEO_SPI1_TEST + ---help--- + Sets SPI 1 Clock Freq + +config NUCLEO_SPI1_TEST_BITS + int "SPI 1 number of bits" + default 8 + depends on NUCLEO_SPI1_TEST + ---help--- + Sets SPI 1 bit length + +choice + prompt "SPI BUS 1 Clock Mode" + default INDIUM_SPI1_TEST_MODE3 + ---help--- + Sets SPI 1 clock mode + +config INDIUM_SPI1_TEST_MODE0 + bool "CPOL=0 CHPHA=0" + +config INDIUM_SPI1_TEST_MODE1 + bool "CPOL=0 CHPHA=1" + +config INDIUM_SPI1_TEST_MODE2 + bool "CPOL=1 CHPHA=0" + +config INDIUM_SPI1_TEST_MODE3 + bool "CPOL=1 CHPHA=1" + +endchoice # "SPI BUS 1 Clock Mode" + +endif # INDIUM_SPI1_TEST + +config NUCLEO_SPI2_TEST + bool "Test SPI bus 2" + default n + depends on NUCLEO_SPI_TEST + ---help--- + Enable Spi test - on SPI BUS 2 + +if INDIUM_SPI2_TEST + +config NUCLEO_SPI2_TEST_FREQ + int "SPI 2 Clock Freq in Hz" + default 12000000 + depends on NUCLEO_SPI2_TEST + ---help--- + Sets SPI 2 Clock Freq + +config NUCLEO_SPI2_TEST_BITS + int "SPI 2 number of bits" + default 8 + depends on NUCLEO_SPI2_TEST + ---help--- + Sets SPI 2 bit length + +choice + prompt "SPI BUS 2 Clock Mode" + default INDIUM_SPI2_TEST_MODE3 + ---help--- + Sets SPI 2 clock mode + +config INDIUM_SPI2_TEST_MODE0 + bool "CPOL=0 CHPHA=0" + +config INDIUM_SPI2_TEST_MODE1 + bool "CPOL=0 CHPHA=1" + +config INDIUM_SPI2_TEST_MODE2 + bool "CPOL=1 CHPHA=0" + +config INDIUM_SPI2_TEST_MODE3 + bool "CPOL=1 CHPHA=1" + +endchoice # "SPI BUS 2 Clock Mode" + +endif # NUCLEO_SPI2_TEST +endif # NUCLEO_SPI_TEST + diff --git a/configs/indium-f7/README.txt b/configs/indium-f7/README.txt new file mode 100644 index 0000000000000000000000000000000000000000..236bcc0df26f4031406263a85a2c7c0491b9f99a --- /dev/null +++ b/configs/indium-f7/README.txt @@ -0,0 +1,284 @@ +README +====== + +This README discusses issues unique to NuttX configurations for the RAF Research +Indium-F7 board and using STMicro Nucleo-144 boards for interim support. + +Contents +======== + + - Indium-F7 Boards + - Indium-F7 interim boards (Nucleo-F722ZE, Nucleo-F746ZG, Nucleo-F767ZI) + - Development Environment + - Basic configuaration & build steps + - Configurations + f722-nsh, f746-nsh, and f767-nsh + +Indium-F7 Boards: +================= + +The Indium-F7 board is a is a special purpose board created by RAF Research LLC. +Currently very few Indium-F7 boards exist and those that do are undergoing hardware +feature checkout. However, it is possible to develop basic Indium-F7 software using +STMicro Nucleo-144 development boards. This config directory provides support for +developing software on both native Indium-F7 hardware and for three STM32F7 Nucleo-144 +development boards. + +The configurations supported include: + + STM32 MCU Board Variant Config used + ------------- ------------- ------------------ + STM32F722RET6 Indium-F7 indium-f7/f722-nsh Note1 + STM32F722ZET6 NUCLEO-F722ZE indium-f7/f722-nsh Note1 + STM32F746ZGT6 NUCLEO-F746ZG indium-f7/f746-nsh + STM32F767ZIT6 NUCLEO-F767ZI indium-f7/f767-nsh + Note1: Chip selection ('R' vs 'Z') designates the board being used. + ------------- ------------------ + +Common Board Features: +--------------------- + + Peripherals: 4 leds, 1 push button (3 LEDs, 1 button) under software + control + Debug: Indium-F7 board need separate ST-Link/V2 programmers. + Nucleo have built-in ST-Link/V2 equivalent programmers. + Serial Console: Indium-F7 boards require nsh console on UART4 (Morpho Connector). + Nucleo boards can use the UART4 (Morpho Connector) console or + the NuttX "Virtual Console" (USART3). + +Basic configuration & build steps +================================== + + A GNU GCC-based toolchain is assumed. The PATH environment variable should + be modified to point to the correct path to the Cortex-M7 GCC toolchain (if + different from the default in your PATH variable). + + - Configures nuttx creating .config file in the nuttx directory. + $ cd tools && ./configure.sh indium-f7/f7nn-nsh && cd .. + - Refreshes the .config file with the latest available configurations. + $ make oldconfig + - Select the features you want in the build. + $ make menuconfig + - Builds Nuttx with the features you selected. + $ make + +Nucleo Hardware Notes +===================== + + GPIO - there are 144 I/O lines on the STM32F7xxZxT6 with various pins pined out + on the Nucleo 144. + + See https://developer.mbed.org/platforms/ST-Nucleo-F746ZG/ for slick graphic + pinouts. + + Keep in mind that: + 1) The I/O is 3.3 Volt not 5 Volt like on the Arduino products. + 2) The Nucleo-144 board family has 3 pages of Solder Bridges AKA Solder + Blobs (SB) that can alter the factory configuration. We will note SB + in effect but will assume the facitory defualt settings. + + Our main concern is establishing a console and LED utilization for + debugging. Because so many pins can be multiplexed with so many functions, + the above mentioned graphic may be helpful in indentifying a serial port. + + There are 5 choices that can be made from the menuconfig: + + CONFIG_NUCLEO_CONSOLE_ARDUINO or CONFIG_NUCLEO_CONSOLE_MORPHO or + CONFIG_NUCLEO_CONSOLE_MORPHO_UART4 or CONFIG_NUCLEO_CONSOLE_VIRTUAL or + CONFIG_NUCLEO_CONSOLE_NONE + + For Indium software development we strongly recommend selecting + CONFIG_NUCLEO_CONSOLE_MORPHO_UART4. However, CONFIG_NUCLEO_CONSOLE_VIRTUAL + is also supported when using Nucleo boards. + + The CONFIG_NUCLEO_CONSOLE_MORPHO_UART4 configurations uses Serial Port 4 (UART4) + with TX on PA1 and RX on PA0. Zero Ohm resistor / solder short at + SB13 must be removed/open. (Disables Ethernet MII clocking.) + Serial + ------ + SERIAL_RX PA_1 CN11 30 + SERIAL_TX PA_0 CN11 28 + + The CONFIG_NUCLEO_CONSOLE_VIRTUAL configurations uses Serial Port 3 (USART3) + with TX on PD8 and RX on PD9. + Serial + ------ + SERIAL_RX PD9 + SERIAL_TX PD8 + + These signals are internally connected to the on-board ST-Link. + + Buttons + ------- + The button is connected to the I/O PC15. + + LEDs + ---- + The Board provides a 3 user LEDs, LD1-LD3 + LED1 (Green) PC1 + LED2 (Blue) PC6 + LED3 (Red) PH1 + + - When the I/O is HIGH value, the LEDs are on. + - When the I/O is LOW, the LEDs are off. + + These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + defined. In that case, the usage by the board port is defined in + include/board.h and src/stm32_autoleds.c. The LEDs are used to encode OS + related events as follows when the LEDs are available: + + SYMBOL Meaning RED GREEN BLUE + ------------------- ----------------------- --- ----- ---- + + LED_STARTED NuttX has been started OFF OFF OFF + LED_HEAPALLOCATE Heap has been allocated OFF OFF ON + LED_IRQSENABLED Interrupts enabled OFF ON OFF + LED_STACKCREATED Idle stack created OFF ON ON + LED_INIRQ In an interrupt NC NC ON (momentary) + LED_SIGNAL In a signal handler NC ON OFF (momentary) + LED_ASSERTION An assertion failed ON NC ON (momentary) + LED_PANIC The system has crashed ON OFF OFF (flashing 2Hz) + LED_IDLE MCU is is sleep mode ON OFF OFF + + +OFF - means that the OS is still initializing. Initialization is very fast + so if you see this at all, it probably means that the system is + hanging up somewhere in the initialization phases. + +GREEN - This means that the OS completed initialization. + +BLUE - Whenever and interrupt or signal handler is entered, the BLUE LED is + illuminated and extinguished when the interrupt or signal handler + exits. + +VIOLET - If a recovered assertion occurs, the RED and blue LED will be + illuminated briefly while the assertion is handled. You will + probably never see this. + +Flashing RED - In the event of a fatal crash, all other LEDs will be + extinguished and RED LED will FLASH at a 2Hz rate. + + + Thus if the GREEN LED is lit, NuttX has successfully booted and is, + apparently, running normally. If the RED LED is flashing at + approximately 2Hz, then a fatal error has been detected and the system has + halted. + + + + You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL + + Nucleo 144 FTDI TTL-232R-3V3 + ------------- ------------------- + TXD - CN11-61 - RXD - Pin 5 (Yellow) + RXD - CN12-64 - TXD - Pin 4 (Orange) + GND CN12-63 - GND Pin 1 (Black) + ------------- ------------------- + + *Note you will be reverse RX/TX + + Virtual COM Port (CONFIG_NUCLEO_CONSOLE_VIRTUAL) + ---------------- + Yet another option is to use USART3 and the USB virtual COM port. This + option may be more convenient for long term development, but is painful + to use during board bring-up. + +Configurations +============== + +f7xx-nsh: +--------- + Configures the NuttShell (nsh) located at apps/examples/nsh for the + Nucleo-144 boards. The Configuration enables the serial interfaces + on USART6. Support for builtin applications is enabled, but in the base + configuration no builtin applications are selected (see NOTES below). + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. If this is the intall configuration then Execute + 'cd tools && ./configure.sh indium-f7/nsh && cd ..' + in nuttx/ in order to start configuration process. + Caution: Doing this step more than once will overwrite .config with + the contents of the indium-f7/nsh/defconfig file. + + c. Execute 'make oldconfig' in nuttx/ in order to refresh the + configuration. + + d. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + e. Save the .config file to reuse it in the future starting at step d. + + 2. By default, this configuration uses the ARM GNU toolchain + for Linux. That can easily be reconfigured, of course. + + CONFIG_HOST_LINUX=y : Builds under Linux + CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y : ARM GNU for Linux + + 3. The serial console may be configured to use either USART3 (which would + correspond to the Virtual COM port) or with the console device + configured for USART6 to support an Arduino serial shield (see + instructions above under "Serial Consoles). You will need to check the + defconfig file to see how the console is set up and, perhaps, modify + the configuration accordingly. + + To select the Virtual COM port: + + -CONFIG_NUCLEO_CONSOLE_ARDUINO + +CONFIG_NUCLEO_CONSOLE_VIRTUAL=y + -CONFIG_USART6_SERIAL_CONSOLE=y + +CONFIG_USART3_SERIAL_CONSOLE=y + + To select the Arduino serial shield: + + -CONFIG_NUCLEO_CONSOLE_VIRTUAL=y + +CONFIG_NUCLEO_CONSOLE_ARDUINO + -CONFIG_USART3_SERIAL_CONSOLE=y + +CONFIG_USART6_SERIAL_CONSOLE=y + + Default values for other settings associated with the select USART should + be correct. + +f7xx-evalos: +------------ + This configuration is designed to test the features of the board. + - Configures the NuttShell (nsh) located at apps/examples/nsh for the + Nucleo-144 boards. The console is available on serial interface USART3, + which is accessible over the USB ST-Link interface. + - Configures nsh with advanced features such as autocompletion. + - Configures the on-board LEDs to work with the 'leds' example app. + - Configures the 'helloxx' example app. + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. If this is the intall configuration then Execute + 'cd tools && ./configure.sh indium-f7/evalos && cd ..' + in nuttx/ in order to start configuration process. + Caution: Doing this step more than once will overwrite .config with + the contents of the indium-f7/evalos/defconfig file. + + c. Execute 'make oldconfig' in nuttx/ in order to refresh the + configuration. + + d. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + e. Save the .config file to reuse it in the future starting at step d. + + 2. By default, this configuration uses the ARM GNU toolchain + for Linux. That can easily be reconfigured, of course. + + CONFIG_HOST_LINUX=y : Builds under Linux + CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y : ARM GNU for Linux diff --git a/configs/indium-f7/f722-nsh/Make.defs b/configs/indium-f7/f722-nsh/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..edf666078ebdc2217becd0ddce334802cc899964 --- /dev/null +++ b/configs/indium-f7/f722-nsh/Make.defs @@ -0,0 +1,113 @@ +############################################################################ +# configs/indium-f7/f722-nsh/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Authors: Gregory Nutt +# David Sidrane +# Bob Feretich +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = f722-flash.ld + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/configs/indium-f7/f722-nsh/defconfig b/configs/indium-f7/f722-nsh/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..0e8f51c73023d0e1043cd4b2d1a41d8e0aca1fbd --- /dev/null +++ b/configs/indium-f7/f722-nsh/defconfig @@ -0,0 +1,49 @@ +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH_BOARD_INDIUM_F7=y +CONFIG_ARCH_BOARD="indium-f7" +CONFIG_ARCH_CHIP_STM32F7=y +CONFIG_ARCH_CHIP_STM32F722ZE=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="arm" +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POLL=y +CONFIG_EXAMPLES_NSH=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SERIAL_DISABLE_REORDERING=y +CONFIG_SPI=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2015 +CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32F7_USART_BREAKS=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/indium-f7/f746-evalos/Make.defs b/configs/indium-f7/f746-evalos/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..7a22165f0319e54f8bca28465baa38dcb267c0ab --- /dev/null +++ b/configs/indium-f7/f746-evalos/Make.defs @@ -0,0 +1,114 @@ +############################################################################ +# configs/indium-f7/f746-evalos/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Authors: Gregory Nutt +# Mark Olsson +# David Sidrane +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = f746-flash.ld + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/configs/indium-f7/f746-evalos/defconfig b/configs/indium-f7/f746-evalos/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..35ed6036caf41ac6bd27e0e7dbd5920335036d2e --- /dev/null +++ b/configs/indium-f7/f746-evalos/defconfig @@ -0,0 +1,63 @@ +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLE_DATE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH_BOARD_INDIUM_F7=y +CONFIG_ARCH_BOARD="indium-f7" +CONFIG_ARCH_CHIP_STM32F7=y +CONFIG_ARCH_CHIP_STM32F746ZG=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="arm" +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POLL=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_EXAMPLES_LEDS=y +CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y +CONFIG_EXAMPLES_NSH=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SERIAL_DISABLE_REORDERING=y +CONFIG_SPI=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2015 +CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32F7_USART_BREAKS=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_USERLED_LOWER=y +CONFIG_USERLED=y +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/indium-f7/f746-nsh/Make.defs b/configs/indium-f7/f746-nsh/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..b93957ee7412f5eeca7f1f8d7844c9211c4b0a7b --- /dev/null +++ b/configs/indium-f7/f746-nsh/Make.defs @@ -0,0 +1,114 @@ +############################################################################ +# configs/indium-f7/f746-nsh/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Authors: Gregory Nutt +# David Sidrane +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = f746-flash.ld + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/indium-f7/f746-nsh/defconfig b/configs/indium-f7/f746-nsh/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..7cbe3b8643bda83ce60766091d4fc334e64e0e4d --- /dev/null +++ b/configs/indium-f7/f746-nsh/defconfig @@ -0,0 +1,49 @@ +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH_BOARD_INDIUM_F7=y +CONFIG_ARCH_BOARD="indium-f7" +CONFIG_ARCH_CHIP_STM32F7=y +CONFIG_ARCH_CHIP_STM32F746ZG=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="arm" +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POLL=y +CONFIG_EXAMPLES_NSH=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SERIAL_DISABLE_REORDERING=y +CONFIG_SPI=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2015 +CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32F7_USART_BREAKS=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/indium-f7/f767-evalos/Make.defs b/configs/indium-f7/f767-evalos/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..4a201af9a462c3fa08d95a76c3d397c83d94bbff --- /dev/null +++ b/configs/indium-f7/f767-evalos/Make.defs @@ -0,0 +1,114 @@ +############################################################################ +# configs/indium-f7/f767-evalos/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Authors: Gregory Nutt +# Mark Olsson +# David Sidrane +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = f767-flash.ld + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/configs/indium-f7/f767-evalos/defconfig b/configs/indium-f7/f767-evalos/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..5e653276f93413d58816e22299214d3c5ca69c11 --- /dev/null +++ b/configs/indium-f7/f767-evalos/defconfig @@ -0,0 +1,63 @@ +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLE_DATE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH_BOARD_INDIUM_F7=y +CONFIG_ARCH_BOARD="indium-f7" +CONFIG_ARCH_CHIP_STM32F7=y +CONFIG_ARCH_CHIP_STM32F767ZI=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="arm" +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POLL=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_EXAMPLES_LEDS=y +CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y +CONFIG_EXAMPLES_NSH=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=3 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SERIAL_DISABLE_REORDERING=y +CONFIG_SPI=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2015 +CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32F7_USART_BREAKS=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_USERLED_LOWER=y +CONFIG_USERLED=y +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/indium-f7/f767-nsh/Make.defs b/configs/indium-f7/f767-nsh/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..c4463c010ca2e7c2c74642f37847598cc895ebcd --- /dev/null +++ b/configs/indium-f7/f767-nsh/Make.defs @@ -0,0 +1,114 @@ +############################################################################ +# configs/indium-f7/f767-nsh/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Authors: Gregory Nutt +# David Sidrane +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = f767-flash.ld + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/indium-f7/f767-nsh/defconfig b/configs/indium-f7/f767-nsh/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..4aea913d34db73e498483e22bc2d8f029eaa4b29 --- /dev/null +++ b/configs/indium-f7/f767-nsh/defconfig @@ -0,0 +1,49 @@ +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH_BOARD_INDIUM_F7=y +CONFIG_ARCH_BOARD="indium-f7" +CONFIG_ARCH_CHIP_STM32F7=y +CONFIG_ARCH_CHIP_STM32F767ZI=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="arm" +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POLL=y +CONFIG_EXAMPLES_NSH=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=3 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SERIAL_DISABLE_REORDERING=y +CONFIG_SPI=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2015 +CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32F7_USART_BREAKS=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/indium-f7/include/board.h b/configs/indium-f7/include/board.h new file mode 100644 index 0000000000000000000000000000000000000000..cc7edacb6b2b62846ff71954860b764dbfb70c6f --- /dev/null +++ b/configs/indium-f7/include/board.h @@ -0,0 +1,493 @@ +/************************************************************************************ + * configs/indium-f7/include/board.h + * + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Mark Olsson + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIG_INDIUM_F7_INCLUDE_BOARD_H +#define __CONFIG_INDIUM_F7_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +#ifdef __KERNEL__ +#include "stm32_rcc.h" +#ifdef CONFIG_STM32F7_SDMMC1 +# include "stm32_sdmmc.h" +#endif +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* The Nucleo-144 board provides the following clock sources: + * + * MCO: 8 MHz from MCO output of ST-LINK is used as input clock + * X2: 32.768 KHz crystal for LSE + * X3: HSE crystal oscillator (not provided) + * + * So we have these clock source available within the STM32 + * + * HSI: 16 MHz RC factory-trimmed + * LSI: 32 KHz RC + * HSE: 8 MHz from MCO output of ST-LINK + * LSE: 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * If the HSI is selected then the PLL source is 16,000,000. + * If the HSE is selected then the PLL source is 8,000,000. + * + * PLL_VCO = (PLL_source_frequency / PLLM) * PLLN + * Subject to: + * + * 2 <= PLLM <= 63 + * 192 <= PLLN <= 432 + * 192 MHz <= PLL_VCO <= 432MHz + * + * SYSCLK = PLL_VCO / PLLP + * Subject to + * + * PLLP = {2, 4, 6, 8} + * SYSCLK <= 216 MHz + * + * USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ + * Subject to + * The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC + * and the random number generator need a frequency lower than or equal + * to 48 MHz to work correctly. + * + * 2 <= PLLQ <= 15 + * + * Choose highest SYSCLK with USB OTG FS clock = 48 MHz + * + */ + +#if defined CONFIG_INDIUM_CLOCK_HSI + +/* + * pll_clock_source = HSI = 16 MHz + * PLL_VCO = (16,000,000 / 8) * 216 = 432 MHz + * SYSCLK = 432 MHz / 2 = 216 MHz + * USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz + */ + +# define STM32_BOARD_USEHSI 1 +# define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) +# define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(216) +# define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 8) * 216) + +#else + +/* + * pll_clock_source = MCO = 8 MHz + * PLL_VCO = (8,000,000 / 4) * 216 = 432 MHz + * SYSCLK = 432 MHz / 2 = 216 MHz + * USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz + */ + +# define STM32_BOARD_USEHSE 1 +# define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4) +# define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(216) +# define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 216) + +#endif + +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9) + +#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9) + +/* Configure factors for PLLSAI clock */ + +#define CONFIG_STM32F7_PLLSAI 1 +#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) +#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8) +#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4) +#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2) + +/* Configure Dedicated Clock Configuration Register */ + +#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1) +#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1) +#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0) +#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0) +#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0) +#define STM32_RCC_DCKCFGR1_TIMPRESRC 0 +#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0 +#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0 + +/* Configure factors for PLLI2S clock */ + +#define CONFIG_STM32F7_PLLI2S 1 +#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) +#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) +#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) +#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2) + +/* Configure Dedicated Clock Configuration Register 2 */ + +#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB +#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB +#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB +#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB +#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB +#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB +#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB +#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI +#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI +#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI +#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI +#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB +#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI +#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLL +#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ +#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ + +/* Several prescalers allow the configuration of the two AHB buses, the + * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum + * frequency of the two AHB buses is 216 MHz while the maximum frequency of + * the high-speed APB domains is 108 MHz. The maximum allowed frequency of + * the low-speed APB domain is 54 MHz. + */ + +/* AHB clock (HCLK) is SYSCLK (216 MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ + +/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (108MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* SDMMC dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(118+2)=400 KHz + */ + +#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz + * DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#else +# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz + * DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#else +# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#endif + +#if defined(CONFIG_STM32F7_SDMMC2) +# define GPIO_SDMMC2_D0 GPIO_SDMMC2_D0_1 +# define GPIO_SDMMC2_D1 GPIO_SDMMC2_D1_1 +# define GPIO_SDMMC2_D2 GPIO_SDMMC2_D2_1 +# define GPIO_SDMMC2_D3 GPIO_SDMMC2_D3_1 +#endif + +/* DMA Channl/Stream Selections *****************************************************/ +/* Stream selections for DMA1 */ + +#define DMAMAP_I2C1_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN1) +#define DMAMAP_I2C2_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN7) +#define DMAMAP_SPI2_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN0) +#define DMAMAP_SPI2_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN0) +#define DMAMAP_I2C1_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN1) +#define DMAMAP_I2C2_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN7) + +/* Stream selections for DMA2 */ + +#define DMAMAP_SPI2_RX STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN3) +#define DMAMAP_USART1_RX STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN4) +#define DMAMAP_SPI2_TX STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN3) +#define DMAMAP_ADC1 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN0) +#define DMAMAP_SDMMC1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN6) +#define DMAMAP_USART1_TX STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN4) + +/* FLASH wait states + * + * --------- ---------- ----------- + * VDD MAX SYSCLK WAIT STATES + * --------- ---------- ----------- + * 1.7-2.1 V 180 MHz 8 + * 2.1-2.4 V 216 MHz 9 + * 2.4-2.7 V 216 MHz 8 + * 2.7-3.6 V 216 MHz 7 + * --------- ---------- ----------- + */ + +#define BOARD_FLASH_WAITSTATES 7 + +/* LED definitions ******************************************************************/ +/* The Indium-F7 board has three software controllable LEDs; LD1 a Green LED, LD2 a Blue + * LED and LD3 a Red LED. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_NLEDS 3 + +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_BLUE BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) + +/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in + * include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related + * events as follows: + * + * + * SYMBOL Meaning LED state + * Red Green Blue + * ---------------------- -------------------------- ----- ------ ---- */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ +#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ +#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ +#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ +#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ +#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */ + +/* Thus if the Green LED is statically on, NuttX has successfully booted and + * is, apparently, running normally. If the Red LED is flashing at + * approximately 2Hz, then a fatal error has been detected and the system + * has halted. + */ + +/* Button definitions ***************************************************************/ +/* The Indium-F7 supports one button: Pushbutton B1, labeled "SW2", is + * connected to GPIO PC15. A high value will be sensed when the button is depressed. + * If the button is held down for >3 seconds, the board should power-off. + * For shorter periods, the button is interpreted as "selection" upon release. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ************************************************/ + +#if defined(CONFIG_INDIUM_CONSOLE_ARDUINO) +/* USART6: + * + * These configurations assume that you are using a standard Arduio RS-232 shield + * with the serial interface with RX on pin D0 and TX on pin D1: + * + * -------- --------------- + * STM32F7 + * ARDUIONO FUNCTION GPIO + * -- ----- --------- ----- + * DO RX USART6_RX PG9 + * D1 TX USART6_TX PG14 + * -- ----- --------- ----- + */ + + # define GPIO_USART6_RX GPIO_USART6_RX_2 + # define GPIO_USART6_TX GPIO_USART6_TX_2 +#endif + +/* USART3: + * Use USART3 and the USB virtual COM port + */ + +#if defined(CONFIG_INDIUM_CONSOLE_VIRTUAL) + # define GPIO_USART3_RX GPIO_USART3_RX_3 + # define GPIO_USART3_TX GPIO_USART3_TX_3 +#endif + +#if defined(CONFIG_INDIUM_CONSOLE_MORPHO_UART4) +/* UART4: + * + * This configuration assumes that you disabled Ethernet MII clocking + * by removing SB13 to free PA1. + * + * -------- --------------- + * STM32F7 + * Pin FUNCTION GPIO + * ------- --------- ----- + * CN11 30 UART4_RX PA1 + * CN11 28 UART4_TX PA0 + * ------- --------- ----- + */ + + # define GPIO_UART4_RX GPIO_UART4_RX_1 + # define GPIO_UART4_TX GPIO_UART4_TX_1 + +#endif + +/* DMA channels *************************************************************/ +/* ADC */ + +#define ADC1_DMA_CHAN DMAMAP_ADC1_1 +#define ADC2_DMA_CHAN DMAMAP_ADC2_1 +#define ADC3_DMA_CHAN DMAMAP_ADC3_1 + +/* Standard Indium pin maps */ + +/* SPI + * Indium Nucleo + * PA6 SPI1_MISO 22 CN12-13 + * PA7 SPI1_MOSI 23 CN12-15 + * PA5 SPI1_SCK 21 CN12-11 + * + * PB14 SPI2_MISO 35 CN12-28 + * PB15 SPI2_MOSI 36 CN12-26 + * PB13 SPI2_SCK 34 CN12-30 + */ + +#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 +#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 +#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 + +#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 +#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 +#define GPIO_SPI2_SCK GPIO_SPI2_SCK_3 + +/* I2C + * Indium Nucleo + * PB6 I2C1_SCL 58 CN10-13 + * PB7 I2C1_SDA 59 CN11-21 + * + * PB10 I2C2_SCL 28 CN11-51 + * PB11 I2C2_SDA 29 CN12-18 + */ + +#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 +#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 + +#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1 +#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1 + +/* CAN + * Indium Nucleo + * PB8 CAN1_RX 61 CN12-3 + * PB9 CAN1_TX 62 CN12-5 + */ + +#define GPIO_CAN1_RX GPIO_CAN1_RX_2 +#define GPIO_CAN1_TX GPIO_CAN1_TX_2 + +/* USART + * Indium Nucleo + * PA12 USART1_RTS 45 CN12-12 + * PA11 USART1_CTS 44 CN12-14 + * PA10 USART1_RX 43 CN12-33 + * PA9 USART1_TX 42 CN12-21 + * + * PA3 USART2_RX 17 CN12-37 + * PA2 USART2_TX 16 CN12-35 + */ + +/* define GPIO_USART1_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN12) is default. */ +/* define GPIO_USART1_CTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN11) is default. */ + +#define GPIO_USART1_RX GPIO_USART1_RX_1 +#define GPIO_USART1_TX GPIO_USART1_TX_1 + +#define GPIO_USART2_RX GPIO_USART2_RX_1 +#define GPIO_USART2_TX GPIO_USART2_TX_1 + +#endif /* __CONFIG_INDIUM_F7_INCLUDE_BOARD_H */ diff --git a/configs/indium-f7/scripts/f722-flash.ld b/configs/indium-f7/scripts/f722-flash.ld new file mode 100644 index 0000000000000000000000000000000000000000..58b20a6bc6c3569e7f67fbc735890601e3176271 --- /dev/null +++ b/configs/indium-f7/scripts/f722-flash.ld @@ -0,0 +1,146 @@ +/**************************************************************************** + * configs/indium-f7/scripts/f722-flash.ld + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The STM32F722ZE has 512 KiB of main FLASH memory. This FLASH memory + * can be accessed from either the AXIM interface at address 0x0800:0000 or + * from the ITCM interface at address 0x0020:0000. + * + * Additional information, including the option bytes, is available at at + * FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM). + * + * In the STM32F722ZE, two different boot spaces can be selected through + * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and + * BOOT_ADD1 option bytes: + * + * 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0]. + * ST programmed value: Flash on ITCM at 0x0020:0000 + * 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0]. + * ST programmed value: System bootloader at 0x0010:0000 + * + * NuttX does not modify these option byes. On the unmodified NUCLEO-144 + * board, the BOOT0 pin is at ground so by default, the STM32F722ZE will + * boot from address 0x0020:0000 in ITCM FLASH. + * + * The STM32F722ZE also has 256 KiB of data SRAM (in addition to ITCM SRAM). + * SRAM is split up into three blocks: + * + * 1) 64 KiB of DTCM SRM beginning at address 0x2000:0000 + * 2) 176 KiB of SRAM1 beginning at address 0x2001:0000 + * 3) 16 KiB of SRAM2 beginning at address 0x2003:c000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + itcm (rwx) : ORIGIN = 0x00200000, LENGTH = 512K + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 64K + sram1 (rwx) : ORIGIN = 0x20010000, LENGTH = 176K + sram2 (rwx) : ORIGIN = 0x2003c000, LENGTH = 16K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram1 AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram1 + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/indium-f7/scripts/f746-flash.ld b/configs/indium-f7/scripts/f746-flash.ld new file mode 100644 index 0000000000000000000000000000000000000000..e35bc54df692b6d0d2f3a7c8f61c04c0ec7861b1 --- /dev/null +++ b/configs/indium-f7/scripts/f746-flash.ld @@ -0,0 +1,145 @@ +/**************************************************************************** + * configs/indium-f7/scripts/f746-flash.ld + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The STM32F746ZGT6 has 1024 KiB of main FLASH memory. This FLASH memory + * can be accessed from either the AXIM interface at address 0x0800:0000 or + * from the ITCM interface at address 0x0020:0000. + * + * Additional information, including the option bytes, is available at at + * FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM). + * + * In the STM32F746ZGT6, two different boot spaces can be selected through + * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and + * BOOT_ADD1 option bytes: + * + * 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0]. + * ST programmed value: Flash on ITCM at 0x0020:0000 + * 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0]. + * ST programmed value: System bootloader at 0x0010:0000 + * + * NuttX does not modify these option byes. On the unmodified NUCLEO-144 + * board, the BOOT0 pin is at ground so by default, the STM32F746ZGT6 will + * boot from address 0x0020:0000 in ITCM FLASH. + * + * The STM32F746ZGT6 also has 320 KiB of data SRAM (in addition to ITCM SRAM). + * SRAM is split up into three blocks: + * + * 1) 64 KiB of DTCM SRM beginning at address 0x2000:0000 + * 2) 240 KiB of SRAM1 beginning at address 0x2001:0000 + * 3) 16 KiB of SRAM2 beginning at address 0x2004:c000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + itcm (rwx) : ORIGIN = 0x00200000, LENGTH = 1024K + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 64K + sram1 (rwx) : ORIGIN = 0x20010000, LENGTH = 240K + sram2 (rwx) : ORIGIN = 0x2004c000, LENGTH = 16K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram1 AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram1 + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/indium-f7/scripts/f767-flash.ld b/configs/indium-f7/scripts/f767-flash.ld new file mode 100644 index 0000000000000000000000000000000000000000..2162a633b13ec0881d4587caae609a022f6a506a --- /dev/null +++ b/configs/indium-f7/scripts/f767-flash.ld @@ -0,0 +1,145 @@ +/**************************************************************************** + * configs/indium-f7/scripts/f767-flash.ld + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The STM32F767ZIT6 has 2048 KiB of main FLASH memory. This FLASH memory + * can be accessed from either the AXIM interface at address 0x0800:0000 or + * from the ITCM interface at address 0x0020:0000. + * + * Additional information, including the option bytes, is available at at + * FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM). + * + * In the STM32F767ZIT6, two different boot spaces can be selected through + * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and + * BOOT_ADD1 option bytes: + * + * 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0]. + * ST programmed value: Flash on ITCM at 0x0020:0000 + * 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0]. + * ST programmed value: System bootloader at 0x0010:0000 + * + * NuttX does not modify these option byes. On the unmodified NUCLEO-144 + * board, the BOOT0 pin is at ground so by default, the STM32F767ZIT6 will + * boot from address 0x0020:0000 in ITCM FLASH. + * + * The STM32F767ZIT6 also has 512 KiB of data SRAM (in addition to ITCM SRAM). + * SRAM is split up into three blocks: + * + * 1) 128 KiB of DTCM SRM beginning at address 0x2000:0000 + * 2) 368 KiB of SRAM1 beginning at address 0x2002:0000 + * 3) 16 KiB of SRAM2 beginning at address 0x2007:c000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + itcm (rwx) : ORIGIN = 0x00200000, LENGTH = 2048K + flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 128K + sram1 (rwx) : ORIGIN = 0x20020000, LENGTH = 368K + sram2 (rwx) : ORIGIN = 0x2007c000, LENGTH = 16K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram1 AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram1 + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/indium-f7/scripts/kernel-space.ld b/configs/indium-f7/scripts/kernel-space.ld new file mode 100644 index 0000000000000000000000000000000000000000..b91d91271ebd467e72e235b286a77503c0642b9b --- /dev/null +++ b/configs/indium-f7/scripts/kernel-space.ld @@ -0,0 +1,109 @@ +/**************************************************************************** + * configs/indium-f7/scripts/kernel-space.ld + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/indium-f7/scripts/memory.ld b/configs/indium-f7/scripts/memory.ld new file mode 100644 index 0000000000000000000000000000000000000000..5d949d5a31ae2e9954a9c295e5c1f4ae5127d006 --- /dev/null +++ b/configs/indium-f7/scripts/memory.ld @@ -0,0 +1,129 @@ +/**************************************************************************** + * configs/indium-f7/scripts/memory.ld + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The STM32F746NGH6 has 1024Kb of main FLASH memory. This FLASH memory can + * be accessed from either the AXIM interface at address 0x0800:0000 or from + * the ITCM interface at address 0x0020:0000. + * + * Additional information, including the option bytes, is available at at + * FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM). + * + * In the STM32F746NGH6, two different boot spaces can be selected through + * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and + * BOOT_ADD1 option bytes: + * + * 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0]. + * ST programmed value: Flash on ITCM at 0x0020:0000 + * 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0]. + * ST programmed value: System bootloader at 0x0010:0000 + * + * NuttX does not modify these option byes. On the unmodified STM32F746G + * DISCO board, the BOOT0 pin is at ground so by default, the STM32 will boot + * to address 0x0020:0000 in ITCM FLASH. + * + * The STM32F746NGH6 also has 320Kb of data SRAM (in addition to ITCM SRAM). + * SRAM is split up into three blocks: + * + * 1) 64Kb of DTCM SRM beginning at address 0x2000:0000 + * 2) 240Kb of SRAM1 beginning at address 0x2001:0000 + * 3) 16Kb of SRAM2 beginning at address 0x2004:c000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed (See + * also configs/stm32f746g-disco/scripts/kernel-space.ld). Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x20001 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x20001 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x20001 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x20001 2000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------- ---- Beginning of user heap. Can vary with other settings. + * 0x20004 c000: End+1 of SRAM1 + */ + +MEMORY +{ + /* ITCM boot address */ + + itcm (rwx) : ORIGIN = 0x00200000, LENGTH = 1024K + + /* 1024KB FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 240KB of contiguous SRAM1 */ + + ksram (rwx) : ORIGIN = 0x20010000, LENGTH = 4K + usram (rwx) : ORIGIN = 0x20011000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x20012000, LENGTH = 240K - 8K + + /* DTCM SRAM */ + + dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 64K + sram2 (rwx) : ORIGIN = 0x2004c000, LENGTH = 16K +} diff --git a/configs/indium-f7/scripts/user-space.ld b/configs/indium-f7/scripts/user-space.ld new file mode 100644 index 0000000000000000000000000000000000000000..3799e937496aaac26dcbcf1c69e43c7ea5f31cf6 --- /dev/null +++ b/configs/indium-f7/scripts/user-space.ld @@ -0,0 +1,111 @@ +/**************************************************************************** + * configs/indium-f7/scripts/user-space.ld + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/indium-f7/src/.gitignore b/configs/indium-f7/src/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..726d936e1e3390cc875a1fa5681e3c3988fe3c8b --- /dev/null +++ b/configs/indium-f7/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/configs/indium-f7/src/Makefile b/configs/indium-f7/src/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..ad488f4a193cb89547e5a8b07ef5ddc63297bcbc --- /dev/null +++ b/configs/indium-f7/src/Makefile @@ -0,0 +1,76 @@ +############################################################################ +# configs/indium-f7/src/Makefile +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# David Sidrane +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += stm32_appinitialize.c +endif + +ifeq ($(CONFIG_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_MMCSD),y) +CSRCS += stm32_sdio.c +endif + +ifeq ($(CONFIG_STM32F7_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32F7_BBSRAM),y) +CSRCS += stm32_bbsram.c +endif + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/indium-f7/src/indium-f7.h b/configs/indium-f7/src/indium-f7.h new file mode 100644 index 0000000000000000000000000000000000000000..552e240aa3916a9b944e98ee88149374b7d50628 --- /dev/null +++ b/configs/indium-f7/src/indium-f7.h @@ -0,0 +1,280 @@ +/************************************************************************************ + * configs/indium-f7/src/indium-f7.h + * + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Mark Olsson + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_INDIUM_F7_SRC_INDIUM_F7_H +#define __CONFIGS_INDIUM_F7_SRC_INDIUM_F7_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration ********************************************************************/ +/* procfs File System */ + +#ifdef CONFIG_FS_PROCFS +# ifdef CONFIG_NSH_PROC_MOUNTPOINT +# define STM32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT +# else +# define STM32_PROCFS_MOUNTPOINT "/proc" +# endif +#endif + +/* Indium F7 GPIO Pin Definitions **************************************************/ + +#define GPIO_OUTPUT_INIT_TO_0 GPIO_OUTPUT_CLEAR +#define GPIO_OUTPUT_INIT_TO_1 GPIO_OUTPUT_SET + +/* Oscillator I/O; When internal oscillators are used and these pins are used for GPIOs */ + +#define GPIO_OSC32_OUT (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTC | GPIO_PIN15) +#define GPIO_PD_REQ GPIO_OSC32_OUT +#define GPIO_OSC_IN (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_INIT_TO_1 | \ + GPIO_PORTH | GPIO_PIN0) +#define GPIO_VBAT_ENn GPIO_OSC_IN +#define GPIO_OSC_OUT (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_INIT_TO_0 | \ + GPIO_PORTH | GPIO_PIN1) +#define GPIO_LED_RED GPIO_OSC_OUT + +/* LED + * + * The Indium-F7 board has three LEDs, LD1 a Green LED, LD2 a Blue LED, and + * LD3 a Red LED, that can be controlled by software. + */ + +/* GPIO_LED_RED is defined above in the Oscillator section. */ + +#define GPIO_LED_GREEN (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_INIT_TO_0 | \ + GPIO_PORTC | GPIO_PIN1) +#define GPIO_LED_BLUE (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_INIT_TO_0 | \ + GPIO_PORTA | GPIO_PIN8) + +#define GPIO_LD1 GPIO_LED_GREEN +#define GPIO_LD2 GPIO_LED_BLUE +#define GPIO_LD3 GPIO_LED_RED + +#define LED_DRIVER_PATH "/dev/userleds" + +/* SPI ***************************************************************************/ + +#define GPIO_SPI_CS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ + GPIO_OUTPUT_INIT_TO_1 ) +#define GPIO_SPI1_CS0 (GPIO_SPI_CS | GPIO_PORTC | GPIO_PIN13) + +#define GPIO_SPI2_CS0 (GPIO_SPI_CS | GPIO_PORTB | GPIO_PIN1) +#define GPIO_SPI2_CS1 (GPIO_SPI_CS | GPIO_PORTB | GPIO_PIN12) +#define GPIO_SPI2_CS2 (GPIO_SPI_CS | GPIO_PORTA | GPIO_PIN8) +#define GPIO_SPI2_CS3 (GPIO_SPI_CS | GPIO_PORTA | GPIO_PIN4) + +#define SPI_CS_EXT GPIO_SPI1_CS0 +#define SPI_CS_LSM330_ACL GPIO_SPI2_CS0 +#define SPI_CS_LSM330_GYRO GPIO_SPI2_CS1 +#define SPI_CS_ADXL372 GPIO_SPI2_CS2 +#define SPI_CS_FRAM GPIO_SPI2_CS3 + +/* Logical SPI Chip Selects used to index */ + +#define NUCLEO_SPI_BUS1_CS0 0 +#define NUCLEO_SPI_BUS2_CS0 1 +#define NUCLEO_SPI_BUS2_CS1 2 +#define NUCLEO_SPI_BUS2_CS2 3 +#define NUCLEO_SPI_BUS2_CS3 4 + +#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +# define HAVE_SDIO +#endif + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_MMCSD_SDIO) +# undef HAVE_SDIO +#endif + +#define SDIO_SLOTNO 0 /* Only one slot */ + +#ifdef HAVE_SDIO + +# if defined(CONFIG_STM32F7_SDMMC1) +# define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) +# endif + +# if defined(CONFIG_NSH_MMCSDSLOTNO) && (CONFIG_NSH_MMCSDSLOTNO != 0) +# warning "Only one MMC/SD slot, slot 0" +# define CONFIG_NSH_MMCSDSLOTNO SDIO_SLOTNO +# endif + +# if defined(CONFIG_NSH_MMCSDMINOR) +# define SDIO_MINOR CONFIG_NSH_MMCSDMINOR +# else +# define SDIO_MINOR 0 +# endif + +/* SD card bringup does not work if performed on the IDLE thread because it + * will cause waiting. Use either: + * + * CONFIG_LIB_BOARDCTL=y, OR + * CONFIG_BOARD_INITIALIZE=y && CONFIG_BOARD_INITTHREAD=y + */ + +# if defined(CONFIG_BOARD_INITIALIZE) && !defined(CONFIG_LIB_BOARDCTL) && \ + !defined(CONFIG_BOARD_INITTHREAD) +# warning SDIO initialization cannot be perfomed on the IDLE thread +# undef HAVE_SDIO +# endif +#endif + +/* General GPIO Definitions */ +/* define GPIO_VBAT_ENn is defined in oscillator section. */ +/* define GPIO_PD_REQ is defined in oscillator section. */ + +#define GPIO_PWR_HOLD (GPIO_PORTC | GPIO_PIN14 | GPIO_OUTPUT_INIT_TO_0 | \ + GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_FLOAT | GPIO_SPEED_2MHz) +#define GPIO_B5 (GPIO_PORTB | GPIO_PIN5 | GPIO_OUTPUT_INIT_TO_0 | \ + GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_FLOAT | GPIO_SPEED_2MHz) +#define GPIO_FWENB (GPIO_PORTB | GPIO_PIN0 | GPIO_OUTPUT_INIT_TO_0 | \ + GPIO_OUTPUT | GPIO_PUSHPULL |GPIO_PULLDOWN | GPIO_SPEED_50MHz) + +/* Analog Inputs */ + +#define GPIO_EXT_ADC (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4) +#define GPIO_BATT_ADC (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0) + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. + * + ************************************************************************************/ + +#if defined(CONFIG_SPI) +void stm32_spidev_initialize(void); +#endif + +/************************************************************************************ + * Name: stm32_spidev_bus_test + * + * Description: + * Called to create the defined SPI buses and test them by initializing them + * and sending the NUCLEO_SPI_TEST (no chip select). + * + ************************************************************************************/ + +#if defined(CONFIG_NUCLEO_SPI_TEST) +int stm32_spidev_bus_test(void); +#endif + +/************************************************************************************ + * Name: stm32_dma_alloc_init + * + * Description: + * Called to create a FAT DMA allocator + * + * Returned Value: + * 0 on success or -ENOMEM + * + ************************************************************************************/ + +void stm32_dma_alloc_init(void); + +#if defined (CONFIG_FAT_DMAMEMORY) +int stm32_dma_alloc_init(void); +#endif + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Called at application startup time to initialize the SCMMC functionality. + * + ****************************************************************************/ + +#ifdef CONFIG_MMCSD +int stm32_sdio_initialize(void); +#endif + +/************************************************************************************ + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in inialization to setup USB-related + * GPIO pins for the indium-f7 board. + * + ************************************************************************************/ + +#ifdef CONFIG_STM32F7_OTGFS +void stm32_usbinitialize(void); +#endif + +/************************************************************************************ + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_setup(void); +#endif + +/************************************************************************************ + * Name: stm32_bbsram_int + ************************************************************************************/ + +#ifdef CONFIG_STM32F7_BBSRAM +int stm32_bbsram_int(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_INDIUM_F7_SRC_INDIUM_F7 */ diff --git a/configs/indium-f7/src/stm32_adc.c b/configs/indium-f7/src/stm32_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..79b3cae53ecd7e3614ca08f93df2b6e10cbf4aa7 --- /dev/null +++ b/configs/indium-f7/src/stm32_adc.c @@ -0,0 +1,171 @@ +/************************************************************************************ + * configs/indium-f7/src/stm32_adc.c + * + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_adc.h" +#include "indium-f7.h" + +#ifdef CONFIG_ADC + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration ********************************************************************/ +/* Up to 3 ADC interfaces are supported */ + +#if STM32F7_NADC < 3 +# undef CONFIG_STM32F7_ADC3 +#endif + +#if STM32F7_NADC < 2 +# undef CONFIG_STM32F7_ADC2 +#endif + +#if STM32F7_NADC < 1 +# undef CONFIG_STM32F7_ADC1 +#endif + +#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3) +#ifndef CONFIG_STM32F7_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +/* Identifying number of each ADC channel: Variable Resistor. + * + * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; + */ + +#ifdef CONFIG_STM32F7_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = {3}; + +/* Configurations of pins used byte each ADC channels + * + * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, GPIO_ADC1_IN4, GPIO_ADC1_IN5, + * GPIO_ADC1_IN6, GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9, GPIO_ADC1_IN10, + * GPIO_ADC1_IN11, GPIO_ADC1_IN12, GPIO_ADC1_IN13, GPIO_ADC1_IN15}; + */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN3}; +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32F7_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + if (g_pinlist[i] != 0) + { + stm32_configgpio(g_pinlist[i]); + } + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/configs/indium-f7/src/stm32_appinitialize.c b/configs/indium-f7/src/stm32_appinitialize.c new file mode 100644 index 0000000000000000000000000000000000000000..62f97ee1db4c106167284f52217d12247da93588 --- /dev/null +++ b/configs/indium-f7/src/stm32_appinitialize.c @@ -0,0 +1,155 @@ +/**************************************************************************** + * config/indium-f7/src/stm32_appinitialize.c + * + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Mark Olsson + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "indium-f7.h" +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32F7_BBSRAM + /* Initialize battery-backed RAM */ + + (void)stm32_bbsram_int(); +#endif + +#if defined(CONFIG_FAT_DMAMEMORY) + if (stm32_dma_alloc_init() < 0) + { + syslog(LOG_ERR, "DMA alloc FAILED"); + } +#endif + +#if defined(CONFIG_NUCLEO_SPI_TEST) + /* Create SPI interfaces */ + + ret = stm32_spidev_bus_test(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI interfaces: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_MMCSD) + /* Configure SDIO */ + /* Initialize the SDIO block driver */ + + ret = stm32_sdio_initialize(); + if (ret != OK) + { + ferr("ERROR: Failed to initialize MMC/SD driver: %d\n", ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/configs/indium-f7/src/stm32_autoleds.c b/configs/indium-f7/src/stm32_autoleds.c new file mode 100644 index 0000000000000000000000000000000000000000..527c5b36097ede5a710e8f129a721930108feeba --- /dev/null +++ b/configs/indium-f7/src/stm32_autoleds.c @@ -0,0 +1,189 @@ +/**************************************************************************** + * configs/indium-f7/src/stm32_autoleds.c + * + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "indium-f7.h" +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ARRAYSIZE(x) (sizeof((x)) / sizeof((x)[0])) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Indexed by BOARD_LED_ */ + +static const uint32_t g_ledmap[BOARD_NLEDS] = +{ + GPIO_LED_GREEN, + GPIO_LED_BLUE, + GPIO_LED_RED, +}; + +static bool g_initialized; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void phy_set_led(int led, bool state) +{ + /* Active High */ + + stm32_gpiowrite(g_ledmap[led], state); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + int i; + + /* Configure the LD1 GPIO for output. Initial state is OFF */ + + for (i = 0; i < ARRAYSIZE(g_ledmap); i++) + { + stm32_configgpio(g_ledmap[i]); + } +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + default: + break; + + case LED_HEAPALLOCATE: + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_IRQSENABLED: + phy_set_led(BOARD_LED_BLUE, false); + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_STACKCREATED: + phy_set_led(BOARD_LED_GREEN, true); + phy_set_led(BOARD_LED_BLUE, true); + g_initialized = true; + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, true); + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, true); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + default: + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, false); + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_BLUE, false); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, false); + phy_set_led(BOARD_LED_BLUE, false); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, false); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/indium-f7/src/stm32_bbsram.c b/configs/indium-f7/src/stm32_bbsram.c new file mode 100644 index 0000000000000000000000000000000000000000..df2bafcc08947666732e125ba82eee7dead27b95 --- /dev/null +++ b/configs/indium-f7/src/stm32_bbsram.c @@ -0,0 +1,557 @@ +/**************************************************************************** + * configs/indium-f7/src/stm32_bbsram.c + * + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. + * Authors: David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "indium-f7.h" + +#ifdef CONFIG_STM32F7_BBSRAM + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define FREEZE_STR(s) #s +#define STRINGIFY(s) FREEZE_STR(s) +#define HARDFAULT_FILENO 3 +#define HARDFAULT_PATH BBSRAM_PATH""STRINGIFY(HARDFAULT_FILENO) +#define HARDFAULT_REBOOT_ FILENO 0 +#define HARDFAULT_REBOOT_PATH BBSRAM_PATH""STRINGIFY(HARDFAULT_REBOOT_FILENO) + +#define BBSRAM_SIZE_FN0 (sizeof(int)) +#define BBSRAM_SIZE_FN1 384 +#define BBSRAM_SIZE_FN2 384 +#define BBSRAM_SIZE_FN3 - 1 + +/* The following guides in the amount of the user and interrupt stack + * data we can save. The amount of storage left will dictate the actual + * number of entries of the user stack data saved. If it is too big + * It will be truncated by the call to stm32_bbsram_savepanic + */ +#define BBSRAM_HEADER_SIZE 20 /* This is an assumption */ +#define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ + (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ + BBSRAM_SIZE_FN2)) +#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED) +#if CONFIG_ARCH_INTERRUPTSTACK <= 3 +# define BBSRAM_NUMBER_STACKS 1 +#else +# define BBSRAM_NUMBER_STACKS 2 +#endif +#define BBSRAM_FIXED_ELEMENTS_SIZE (sizeof(info_t)) +#define BBSRAM_LEFTOVER (BBSRAM_REAMINING-\ + BBSRAM_FIXED_ELEMENTS_SIZE) + +#define CONFIG_ISTACK_SIZE (BBSRAM_LEFTOVER/BBSRAM_NUMBER_STACKS/ \ + sizeof(stack_word_t)) +#define CONFIG_USTACK_SIZE (BBSRAM_LEFTOVER/BBSRAM_NUMBER_STACKS/ \ + sizeof(stack_word_t)) + +/* The path to the Battery Backed up SRAM */ + +#define BBSRAM_PATH "/fs/bbr" + +/* The sizes of the files to create (-1) use rest of BBSRAM memory */ + +#define BSRAM_FILE_SIZES \ +{ \ + BBSRAM_SIZE_FN0, \ + BBSRAM_SIZE_FN1, \ + BBSRAM_SIZE_FN2, \ + BBSRAM_SIZE_FN3, \ + 0 \ +} + +#define ARRAYSIZE(a) (sizeof((a))/sizeof(a[0])) + +/* For Assert keep this much of the file name*/ + +#define MAX_FILE_PATH_LENGTH 40 + +#define HEADER_TIME_FMT "%Y-%m-%d-%H:%M:%S" +#define HEADER_TIME_FMT_NUM (2+ 0+ 0+ 0+ 0+ 0) +#define HEADER_TIME_FMT_LEN (((ARRAYSIZE(HEADER_TIME_FMT)-1) + \ + HEADER_TIME_FMT_NUM)) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Used for stack frame storage */ + +typedef uint32_t stack_word_t; + +/* Stack related data */ + +typedef struct +{ + uint32_t sp; + uint32_t top; + uint32_t size; + +} _stack_t; + +typedef struct +{ + _stack_t user; +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + _stack_t interrupt; +#endif +} stack_t; + +/* Not Used for reference only */ + +typedef struct +{ + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t r12; + uint32_t sp; + uint32_t lr; + uint32_t pc; + uint32_t xpsr; + uint32_t d0; + uint32_t d1; + uint32_t d2; + uint32_t d3; + uint32_t d4; + uint32_t d5; + uint32_t d6; + uint32_t d7; + uint32_t d8; + uint32_t d9; + uint32_t d10; + uint32_t d11; + uint32_t d12; + uint32_t d13; + uint32_t d14; + uint32_t d15; + uint32_t fpscr; + uint32_t sp_main; + uint32_t sp_process; + uint32_t apsr; + uint32_t ipsr; + uint32_t epsr; + uint32_t primask; + uint32_t basepri; + uint32_t faultmask; + uint32_t control; + uint32_t s0; + uint32_t s1; + uint32_t s2; + uint32_t s3; + uint32_t s4; + uint32_t s5; + uint32_t s6; + uint32_t s7; + uint32_t s8; + uint32_t s9; + uint32_t s10; + uint32_t s11; + uint32_t s12; + uint32_t s13; + uint32_t s14; + uint32_t s15; + uint32_t s16; + uint32_t s17; + uint32_t s18; + uint32_t s19; + uint32_t s20; + uint32_t s21; + uint32_t s22; + uint32_t s23; + uint32_t s24; + uint32_t s25; + uint32_t s26; + uint32_t s27; + uint32_t s28; + uint32_t s29; + uint32_t s30; + uint32_t s31; +} proc_regs_t; + +/* Flags to identify what is in the dump */ + +typedef enum +{ + REGS_PRESENT = 0x01, + USERSTACK_PRESENT = 0x02, + INTSTACK_PRESENT = 0x04, + INVALID_USERSTACK_PTR = 0x20, + INVALID_INTSTACK_PTR = 0x40, +} fault_flags_t; + +typedef struct +{ + fault_flags_t flags; /* What is in the dump */ + uintptr_t current_regs; /* Used to validate the dump */ + int lineno; /* __LINE__ to up_assert */ + int pid; /* Process ID */ + uint32_t regs[XCPTCONTEXT_REGS]; /* Interrupt register save area */ + stack_t stacks; /* Stack info */ +#if CONFIG_TASK_NAME_SIZE > 0 + char name[CONFIG_TASK_NAME_SIZE + 1]; /* Task name (with NULL + * terminator) */ +#endif + char filename[MAX_FILE_PATH_LENGTH]; /* the Last of chars in + * __FILE__ to up_assert */ +} info_t; + +typedef struct +{ + info_t info; /* The info */ +#if CONFIG_ARCH_INTERRUPTSTACK > 3 /* The amount of stack data is compile time + * sized backed on what is left after the + * other BBSRAM files are defined + * The order is such that only the + * ustack should be truncated + */ + stack_word_t istack[CONFIG_USTACK_SIZE]; +#endif + stack_word_t ustack[CONFIG_ISTACK_SIZE]; +} fullcontext_t; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint8_t g_sdata[STM32F7_BBSRAM_SIZE]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hardfault_get_desc + ****************************************************************************/ + +static int hardfault_get_desc(struct bbsramd_s *desc) +{ + int ret = -ENOENT; + int fd = open(HARDFAULT_PATH, O_RDONLY); + int rv; + + if (fd < 0) + { + syslog(LOG_INFO, "stm32 bbsram: Failed to open Fault Log file [%s] " + "(%d)\n", HARDFAULT_PATH, fd); + } + else + { + ret = -EIO; + rv = ioctl(fd, STM32F7_BBSRAM_GETDESC_IOCTL, + (unsigned long)((uintptr_t)desc)); + + if (rv >= 0) + { + ret = fd; + } + else + { + syslog(LOG_INFO, "stm32 bbsram: Failed to get Fault Log descriptor " + "(%d)\n", rv); + } + } + + return ret; +} + +/**************************************************************************** + * Name: copy_reverse + ****************************************************************************/ + +#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) +{ + while (size--) + { + *dest++ = *src--; + } +} +#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bbsram_int + ****************************************************************************/ + +int stm32_bbsram_int(void) +{ + int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; + char buf[HEADER_TIME_FMT_LEN + 1]; + struct bbsramd_s desc; + int rv; + int state; + struct tm tt; + time_t time_sec; + + + /* Using Battery Backed Up SRAM */ + + stm32_bbsraminitialize(BBSRAM_PATH, filesizes); + +#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) + /* Panic Logging in Battery Backed Up Files */ + /* Do we have an hard fault in BBSRAM? */ + + rv = hardfault_get_desc(&desc); + if (rv >= OK) + { + printf("There is a hard fault logged.\n"); + state = (desc.lastwrite.tv_sec || desc.lastwrite.tv_nsec) ? OK : 1; + + syslog(LOG_INFO, "Fault Log info File No %d Length %d flags:0x%02x " + "state:%d\n",(unsigned int)desc.fileno, (unsigned int) desc.len, + (unsigned int)desc.flags, state); + + if (state == OK) + { + time_sec = desc.lastwrite.tv_sec + (desc.lastwrite.tv_nsec / 1e9); + gmtime_r(&time_sec, &tt); + strftime(buf, HEADER_TIME_FMT_LEN , HEADER_TIME_FMT , &tt); + + syslog(LOG_INFO, "Fault Logged on %s - Valid\n", buf); + } + + close(rv); + rv = unlink(HARDFAULT_PATH); + if (rv < 0) + { + syslog(LOG_INFO, "stm32 bbsram: Failed to unlink Fault Log file [%s" + "] (%d)\n", HARDFAULT_PATH, rv); + } + } +#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ + + return rv; +} + +/**************************************************************************** + * Name: board_crashdump + ****************************************************************************/ + +#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +void board_crashdump(uintptr_t currentsp, FAR void *tcb, + FAR const uint8_t *filename, int lineno) +{ + fullcontext_t *pdump = (fullcontext_t *)&g_sdata; + FAR struct tcb_s *rtcb; + int rv; + + (void)enter_critical_section(); + + rtcb = (FAR struct tcb_s *)tcb; + + /* Zero out everything */ + + memset(pdump, 0, sizeof(fullcontext_t)); + + /* Save Info */ + + pdump->info.lineno = lineno; + + if (filename) + { + int offset = 0; + unsigned int len = strlen((char *)filename) + 1; + + if (len > sizeof(pdump->info.filename)) + { + offset = len - sizeof(pdump->info.filename); + } + + strncpy(pdump->info.filename, (char *)&filename[offset], + sizeof(pdump->info.filename)); + } + + /* Save the value of the pointer for current_regs as debugging info. + * It should be NULL in case of an ASSERT and will aid in cross + * checking the validity of system memory at the time of the + * fault. + */ + + pdump->info.current_regs = (uintptr_t) CURRENT_REGS; + + /* Save Context */ + +#if CONFIG_TASK_NAME_SIZE > 0 + strncpy(pdump->info.name, rtcb->name, CONFIG_TASK_NAME_SIZE); +#endif + + pdump->info.pid = rtcb->pid; + + /* If current_regs is not NULL then we are in an interrupt context + * and the user context is in current_regs else we are running in + * the users context + */ + + if (CURRENT_REGS) + { + pdump->info.stacks.interrupt.sp = currentsp; + pdump->info.flags |= (REGS_PRESENT | USERSTACK_PRESENT | \ + INTSTACK_PRESENT); + memcpy(pdump->info.regs, (void *)CURRENT_REGS, + sizeof(pdump->info.regs)); + pdump->info.stacks.user.sp = pdump->info.regs[REG_R13]; + } + else + { + /* users context */ + + pdump->info.flags |= USERSTACK_PRESENT; + pdump->info.stacks.user.sp = currentsp; + } + + if (pdump->info.pid == 0) + { + pdump->info.stacks.user.top = g_idle_topstack - 4; + pdump->info.stacks.user.size = CONFIG_IDLETHREAD_STACKSIZE; + } + else + { + pdump->info.stacks.user.top = (uint32_t) rtcb->adj_stack_ptr; + pdump->info.stacks.user.size = (uint32_t) rtcb->adj_stack_size; + } + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + /* Get the limits on the interrupt stack memory */ + + pdump->info.stacks.interrupt.top = (uint32_t)&g_intstackbase; + pdump->info.stacks.interrupt.size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); + + /* If In interrupt Context save the interrupt stack data centered + * about the interrupt stack pointer + */ + + if ((pdump->info.flags & INTSTACK_PRESENT) != 0) + { + stack_word_t *ps = (stack_word_t *) pdump->info.stacks.interrupt.sp; + copy_reverse(pdump->istack, &ps[ARRAYSIZE(pdump->istack) / 2], + ARRAYSIZE(pdump->istack)); + } + + /* Is it Invalid? */ + + if (!(pdump->info.stacks.interrupt.sp <= pdump->info.stacks.interrupt.top && + pdump->info.stacks.interrupt.sp > pdump->info.stacks.interrupt.top - + pdump->info.stacks.interrupt.size)) + { + pdump->info.flags |= INVALID_INTSTACK_PTR; + } + +#endif + /* If In interrupt context or User save the user stack data centered + * about the user stack pointer + */ + + if ((pdump->info.flags & USERSTACK_PRESENT) != 0) + { + stack_word_t *ps = (stack_word_t *) pdump->info.stacks.user.sp; + copy_reverse(pdump->ustack, &ps[ARRAYSIZE(pdump->ustack) / 2], + ARRAYSIZE(pdump->ustack)); + } + + /* Is it Invalid? */ + + if (!(pdump->info.stacks.user.sp <= pdump->info.stacks.user.top && + pdump->info.stacks.user.sp > pdump->info.stacks.user.top - + pdump->info.stacks.user.size)) + { + pdump->info.flags |= INVALID_USERSTACK_PTR; + } + + rv = stm32_bbsram_savepanic(HARDFAULT_FILENO, (uint8_t *)pdump, + sizeof(fullcontext_t)); + + /* Test if memory got wiped because of using _sdata */ + + if (rv == -ENXIO) + { + char *dead = "Memory wiped - dump not saved!"; + + while (*dead) + { + up_lowputc(*dead++); + } + } + else if (rv == -ENOSPC) + { + /* hard fault again */ + + up_lowputc('!'); + } + +#if defined(CONFIG_BOARD_RESET_ON_CRASH) + up_systemreset(); +#endif +} +#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ + +#endif /* CONFIG_STM32_BBSRAM */ diff --git a/configs/indium-f7/src/stm32_boot.c b/configs/indium-f7/src/stm32_boot.c new file mode 100644 index 0000000000000000000000000000000000000000..6ead325e58519f9a1ec53d0dd954c8a8ea33535d --- /dev/null +++ b/configs/indium-f7/src/stm32_boot.c @@ -0,0 +1,123 @@ +/************************************************************************************ + * configs/indium-f7/src/stm32_boot.c + * + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include +#include "stm32_gpio.h" + +#include "up_arch.h" +#include "indium-f7.h" + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This entry point + * is called early in the initialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. + * This feature is used for initial Indium Board bringup. + * After boot the Indium applicatuins take over control of LEDs. + */ + + board_autoled_initialize(); +#endif + + /* Configure SPI chip selects */ + + stm32_spidev_initialize(); + + /* Configure General Purpose IO */ + + stm32_configgpio(GPIO_VBAT_ENn); /* Battery Voltage Sample Ctl (-active) */ + stm32_configgpio(GPIO_PD_REQ); /* Powerr Down Req Button */ + stm32_configgpio(GPIO_PWR_HOLD); /* Hold Power On */ + stm32_configgpio(GPIO_B5); /* GPIO B5 */ + stm32_configgpio(GPIO_FWENB); /* FRAM Write Enable */ + + /* Analog Inputs (Also done later by stm32_appinitialize.) */ + + stm32_configgpio(GPIO_EXT_ADC); /* External ADC board pin */ + stm32_configgpio(GPIO_BATT_ADC); /* Battery voltage sense input */ + + /* Other pin configurations are performed when the driver related to the pin is opened. */ +} + +/************************************************************************************ + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional initialization call + * will be performed in the boot-up sequence to a function called + * board_initialize(). board_initialize() will be called immediately after + * up_initialize() is called and just before the initial application is started. + * This additional initialization phase may be used, for example, to initialize + * board-specific device drivers. + * + ************************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ +#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL) + /* Perform NSH initialization here instead of from the NSH. This + * alternative NSH initialization is necessary when NSH is ran in user-space + * but the initialization function must run in kernel space. + */ + + (void)board_app_initialize(0); +#endif +} +#endif diff --git a/configs/indium-f7/src/stm32_buttons.c b/configs/indium-f7/src/stm32_buttons.c new file mode 100644 index 0000000000000000000000000000000000000000..a18345f0315bde2f20ca5b62e0d41b00be361842 --- /dev/null +++ b/configs/indium-f7/src/stm32_buttons.c @@ -0,0 +1,121 @@ +/**************************************************************************** + * configs/indium-f7/src/stm32_buttons.c + * + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "stm32_gpio.h" +#include "indium-f7.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ + stm32_configgpio(GPIO_BTN_USER); +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0; +} + +/************************************************************************************ + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. After + * that, board_buttons() may be called to collect the current state of all + * buttons or board_button_irq() may be called to register button interrupt + * handlers. + * + * After board_button_initialize() has been called, board_buttons() may be called to + * collect the state of all buttons. board_buttons() returns an 32-bit bit set + * with each bit associated with a button. See the BUTTON_*_BIT + * definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that will + * be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See the + * BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ************************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/configs/indium-f7/src/stm32_dma_alloc.c b/configs/indium-f7/src/stm32_dma_alloc.c new file mode 100644 index 0000000000000000000000000000000000000000..a6e4a3cff389efdbb5330cc8bfad835bff02d6d8 --- /dev/null +++ b/configs/indium-f7/src/stm32_dma_alloc.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * configs/indium-f7/stc/stm32_dma_alloc.c + * + * Copyright (C) 2016-2017 PX4 Development Team. All rights reserved. + * Modified by: Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name PX4 nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include +#include +#include + +#include "indium-f7.h" + +#if defined(CONFIG_FAT_DMAMEMORY) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#if !defined(CONFIG_GRAN) +# error microSD DMA support requires CONFIG_GRAN +#endif + +#define BOARD_DMA_ALLOC_POOL_SIZE (8*512) + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +static GRAN_HANDLE dma_allocator; + +/* The DMA heap size constrains the total number of things that can be + * ready to do DMA at a time. + * + * For example, FAT DMA depends on one sector-sized buffer per filesystem plus + * one sector-sized buffer per file. + * + * We use a fundamental alignment / granule size of 64B; this is sufficient + * to guarantee alignment for the largest STM32 DMA burst (16 beats x 32bits). + */ + +static uint8_t g_dma_heap[BOARD_DMA_ALLOC_POOL_SIZE] __attribute__((aligned(64))); + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_dma_alloc_init + * + * Description: + * All boards may optionally provide this API to instantiate a pool of + * memory for uses with FAST FS DMA operations. + * + ************************************************************************************/ + +int stm32_dma_alloc_init(void) +{ + dma_allocator = gran_initialize(g_dma_heap, + sizeof(g_dma_heap), + 7, /* 128B granule - must be > alignment (XXX bug?) */ + 6); /* 64B alignment */ + + if (dma_allocator == NULL) + { + return -ENOMEM; + } + + return OK; +} + +/* DMA-aware allocator stubs for the FAT filesystem. */ + +void *fat_dma_alloc(size_t size) +{ + return gran_alloc(dma_allocator, size); +} + +void fat_dma_free(FAR void *memory, size_t size) +{ + gran_free(dma_allocator, memory, size); +} + +#endif /* CONFIG_FAT_DMAMEMORY */ diff --git a/configs/indium-f7/src/stm32_sdio.c b/configs/indium-f7/src/stm32_sdio.c new file mode 100644 index 0000000000000000000000000000000000000000..9e8fe4806396feb2d93699dd7fcb769c2f3cd32e --- /dev/null +++ b/configs/indium-f7/src/stm32_sdio.c @@ -0,0 +1,179 @@ +/**************************************************************************** + * config/indium-f7/src/stm32_sdio.c + * + * Copyright (C) 2014, 2016-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "indium-f7.h" +#include "stm32_gpio.h" +#include "stm32_sdmmc.h" + +#ifdef CONFIG_MMCSD + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ +/* Card detections requires card support and a card detection GPIO */ + +#define HAVE_NCD 1 +#if !defined(GPIO_SDMMC1_NCD) +# undef HAVE_NCD +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static FAR struct sdio_dev_s *g_sdio_dev; +#ifdef HAVE_NCD +static bool g_sd_inserted = 0xff; /* Impossible value */ +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ncd_interrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef HAVE_NCD +static int stm32_ncd_interrupt(int irq, FAR void *context) +{ + bool present; + + present = !stm32_gpioread(GPIO_SDMMC1_NCD); + if (g_sdio_dev && present != g_sd_inserted) + { + sdio_mediachange(g_sdio_dev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +int stm32_sdio_initialize(void) +{ + int ret; + +#ifdef HAVE_NCD + /* Card detect */ + + bool cd_status; + + /* Configure the card detect GPIO */ + + stm32_configgpio(GPIO_SDMMC1_NCD); + + /* Register an interrupt handler for the card detect pin */ + + (void)stm32_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true, + stm32_ncd_interrupt, NULL); +#endif + + /* Mount the SDIO-based MMC/SD block driver */ + /* First, get an instance of the SDIO interface */ + + finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + finfo("Successfully bound SDIO to the MMC/SD driver\n"); + +#ifdef HAVE_NCD + /* Use SD card detect pin to check if a card is g_sd_inserted */ + + cd_status = !stm32_gpioread(GPIO_SDMMC1_NCD); + finfo("Card detect : %d\n", cd_status); + + sdio_mediachange(g_sdio_dev, cd_status); +#else + /* Assume that the SD card is inserted. What choice do we have? */ + + sdio_mediachange(g_sdio_dev, true); +#endif + + return OK; +} + +#endif /* HAVE_SDIO */ diff --git a/configs/indium-f7/src/stm32_spi.c b/configs/indium-f7/src/stm32_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..3f498ba924b203e328a8da29f6fa0cdc495819d6 --- /dev/null +++ b/configs/indium-f7/src/stm32_spi.c @@ -0,0 +1,435 @@ +/************************************************************************************ + * configs/indium-f7/src/stm32_spi.c + * + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_spi.h" + +#include "indium-f7.h" + +#if defined(CONFIG_SPI) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#define ARRAYSIZE(x) (sizeof((x)) / sizeof((x)[0])) + +#if defined(CONFIG_NUCLEO_SPI1_TEST) +# if defined(CONFIG_NUCLEO_SPI1_TEST_MODE0) +# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE1) +# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE2) +# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE3) +# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_NUCLEO_SPI1_TEST_MODEx defined" +# endif +#endif + +#if defined(CONFIG_NUCLEO_SPI2_TEST) +# if defined(CONFIG_NUCLEO_SPI2_TEST_MODE0) +# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE1) +# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE2) +# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE3) +# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_NUCLEO_SPI2_TEST_MODEx defined" +# endif +#endif + +#if defined(CONFIG_NUCLEO_SPI3_TEST) +# if defined(CONFIG_NUCLEO_SPI3_TEST_MODE0) +# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE1) +# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE2) +# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE3) +# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_NUCLEO_SPI3_TEST_MODEx defined" +# endif +#endif + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +/* Indexed by NUCLEO_SPI_BUSx_CSx */ + +static const uint32_t g_spigpio[] = +{ +#if defined(GPIO_SPI1_CS0) + GPIO_SPI1_CS0, +#endif +#if defined(GPIO_SPI1_CS1) + GPIO_SPI1_CS1, +#endif +#if defined(GPIO_SPI1_CS2) + GPIO_SPI1_CS2, +#endif +#if defined(GPIO_SPI1_CS3) + GPIO_SPI1_CS3, +#endif +#if defined(GPIO_SPI2_CS0) + GPIO_SPI2_CS0, +#endif +#if defined(GPIO_SPI2_CS1) + GPIO_SPI2_CS1, +#endif +#if defined(GPIO_SPI2_CS2) + GPIO_SPI2_CS2, +#endif +#if defined(GPIO_SPI2_CS3) + GPIO_SPI2_CS3, +#endif +#if defined(GPIO_SPI3_CS0) + GPIO_SPI3_CS0, +#endif +#if defined(GPIO_SPI3_CS1) + GPIO_SPI3_CS1, +#endif +#if defined(GPIO_SPI3_CS2) + GPIO_SPI3_CS2, +#endif +#if defined(GPIO_SPI3_CS3) + GPIO_SPI3_CS3, +#endif +}; + +#if defined(CONFIG_NUCLEO_SPI_TEST) +# if defined(CONFIG_STM32F7_SPI1) +struct spi_dev_s *spi1; +# endif +# if defined(CONFIG_STM32F7_SPI2) +struct spi_dev_s *spi2; +# endif +# if defined(CONFIG_STM32F7_SPI3) +struct spi_dev_s *spi3; +# endif +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. + * + ************************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + int i; + + /* Configure SPI CS GPIO for output */ + + for (i = 0; i < ARRAYSIZE(g_spigpio); i++) + { + stm32_configgpio(g_spigpio[i]); + } +} + +/**************************************************************************** + * Name: stm32_spi1/2/3/4/5select and stm32_spi1/2/3/4/5status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be + * provided by board-specific logic. They are implementations of the select + * and status methods of the SPI interface defined by struct spi_ops_s (see + * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) + * are provided by common STM32 logic. To use this common SPI logic on your + * board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your + * board-specific logic. These functions will perform chip selection and + * status operations using GPIOs in the way your board is configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level application + * initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32F7_SPI1 +void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + stm32_gpiowrite(g_spigpio[devid], !selected); +} + +uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32F7_SPI2 +void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + stm32_gpiowrite(g_spigpio[devid], !selected); +} + +uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32F7_SPI3 +void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + stm32_gpiowrite(g_spigpio[devid], !selected); +} + +uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32F7_SPI4 +# ifndef NUCLEO_SPI_BUS4_CS0 +# error "NUCLEO_SPI_BUS4_CSn Are not defined" +# endif + +void stm32_spi4select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + stm32_gpiowrite(g_spigpio[devid], !selected); +} + +uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32F7_SPI5 +# ifndef NUCLEO_SPI_BUS5_CS0 +# error "NUCLEO_SPI_BUS4_CSn Are not defined" +# endif + +void stm32_spi5select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + stm32_gpiowrite(g_spigpio[devid], !selected); +} + +uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32F7_SPI6 +# ifndef NUCLEO_SPI_BUS6_CS +# error "NUCLEO_SPI_BUS4_CSn Are not defined" +# endif +void stm32_spi5select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + stm32_gpiowrite(g_spigpio[devid], !selected); +} + +uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32F7_SPI1 +int stm32_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32F7_SPI2 +int stm32_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32F7_SPI3 +int stm32_spi3cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32F7_SPI4 +int stm32_spi4cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32F7_SPI5 +int stm32_spi5cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32F7_SPI6 +int stm32_spi5cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +:qa + return -ENODEV; +} +#endif + +#endif /* CONFIG_SPI_CMDDATA */ + +#if defined(CONFIG_NUCLEO_SPI_TEST) +int stm32_spidev_bus_test(void) +{ + /* Configure and test SPI-*/ + + uint8_t *tx = (uint8_t *)CONFIG_NUCLEO_SPI_TEST_MESSAGE; + +#if defined(CONFIG_NUCLEO_SPI1_TEST) + spi1 = stm32_spibus_initialize(1); + + if (!spi1) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 1\n"); + return -ENODEV; + } + + /* Default SPI1 to NUCLEO_SPI1_FREQ and mode */ + + SPI_SETFREQUENCY(spi1, CONFIG_NUCLEO_SPI1_TEST_FREQ); + SPI_SETBITS(spi1, CONFIG_NUCLEO_SPI1_TEST_BITS); + SPI_SETMODE(spi1, CONFIG_NUCLEO_SPI1_TEST_MODE); + SPI_EXCHANGE(spi1, tx, NULL, ARRAYSIZE(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); +#endif + +#if defined(CONFIG_NUCLEO_SPI2_TEST) + spi2 = stm32_spibus_initialize(2); + + if (!spi2) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Default SPI2 to NUCLEO_SPI2_FREQ and mode */ + + SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_SPI2_TEST_FREQ); + SPI_SETBITS(spi2, CONFIG_NUCLEO_SPI2_TEST_BITS); + SPI_SETMODE(spi2, CONFIG_NUCLEO_SPI2_TEST_MODE); + SPI_EXCHANGE(spi2, tx, NULL, ARRAYSIZE(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); +#endif + +#if defined(CONFIG_NUCLEO_SPI3_TEST) + spi3 = stm32_spibus_initialize(3); + + if (!spi3) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Default SPI3 to NUCLEO_SPI3_FREQ and mode */ + + SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_SPI3_TEST_FREQ); + SPI_SETBITS(spi3, CONFIG_NUCLEO_SPI3_TEST_BITS); + SPI_SETMODE(spi3, CONFIG_NUCLEO_SPI3_TEST_MODE); + SPI_EXCHANGE(spi3, tx, NULL, ARRAYSIZE(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); +#endif + + return OK; +} +#endif /* NUCLEO_SPI_TEST */ +#endif /* defined(CONFIG_SPI) */ diff --git a/configs/indium-f7/src/stm32_usb.c b/configs/indium-f7/src/stm32_usb.c new file mode 100644 index 0000000000000000000000000000000000000000..794975f51c33b465e69fa236562bfd42a1a331cd --- /dev/null +++ b/configs/indium-f7/src/stm32_usb.c @@ -0,0 +1,332 @@ +/************************************************************************************ + * configs/indium-f7/src/stm32_usb.c + * + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_otg.h" +#include "indium-f7.h" + +#ifdef CONFIG_STM32F7_OTGFS + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_NUCLEO144_USBHOST_PRIO +# define CONFIG_NUCLEO144_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_NUCLEO_USBHOST_STACKSIZE +# define CONFIG_NUCLEO_USBHOST_STACKSIZE 1024 +#endif + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ************************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (;;) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + (void)CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in inialization to setup USB-related + * GPIO pins for the indium-f7 board. + * + ************************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. No GPIO configuration is required */ + + /* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */ + +#ifdef CONFIG_STM32F7_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/*********************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ***********************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int pid; +#if defined(CONFIG_USBHOST_HUB) || defined(CONFIG_USBHOST_MSC) || \ + defined(CONFIG_USBHOST_HIDKBD) || defined(CONFIG_USBHOST_HIDMOUSE) + int ret; +#endif + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + pid = task_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO, + CONFIG_STM32F4DISCO_USBHOST_STACKSIZE, + (main_t)usbhost_waiter, (FAR char * const *)NULL); + return pid < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/*********************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be provided be + * each platform that implements the STM32 OTG FS host interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a charge pump + * or, if 5 V are available on the application board, a basic power switch, must + * be added externally to drive the 5 V VBUS line. The external charge pump can + * be driven by any GPIO output. When the application decides to power on VBUS + * using the chosen GPIO, it must also set the port power bit in the host port + * control and status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, and the core + * clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ***********************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + /* Set the Power Switch by driving the active low enable pin */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable); +} +#endif + +/************************************************************************************ + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent condition is + * detected. + * + * Input Parameter: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned value: + * Zero (OK) is returned on success. Otherwise, a negated errno value is returned + * to indicate the nature of the failure. + * + ************************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/************************************************************************************ + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is + * used. This function is called whenever the USB enters or leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, etc. + * while the USB is suspended. + * + ************************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/configs/indium-f7/src/stm32_userleds.c b/configs/indium-f7/src/stm32_userleds.c new file mode 100644 index 0000000000000000000000000000000000000000..5f5fdfcc5f5b1dfeee078f8e961e69a0aeb8bbdf --- /dev/null +++ b/configs/indium-f7/src/stm32_userleds.c @@ -0,0 +1,145 @@ +/**************************************************************************** + * configs/indium-f7/src/stm32_userleds.c + * + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Mark Olsson + * David Sidrane + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "indium-f7.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ARRAYSIZE(x) (sizeof((x)) / sizeof((x)[0])) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration and is indexed by + * BOARD_LED_ + */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED_GREEN, + GPIO_LED_BLUE, + GPIO_LED_RED, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the + * board_userled_initialize() is available to initialize the LED from user + * application logic. + * + ****************************************************************************/ + +void board_userled_initialize(void) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < ARRAYSIZE(g_ledcfg); i++) + { + stm32_configgpio(g_ledcfg[i]); + } +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is + * available to control the LED from user application logic. + * + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < ARRAYSIZE(g_ledcfg)) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() is + * available to control the LED from user application logic. NOTE: since + * there is only a single LED on-board, this is function is not very useful. + * + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < ARRAYSIZE(g_ledcfg); i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/configs/kwikstik-k40/README.txt b/configs/kwikstik-k40/README.txt index 17c0d93526d5a97a4187e5b9802309da7a44adef..e778f86e616936c6db9cf13eaa36a6ce0c846e9f 100644 --- a/configs/kwikstik-k40/README.txt +++ b/configs/kwikstik-k40/README.txt @@ -19,12 +19,8 @@ Contents - Connections via the Tower Primary Connector Side A - Connections via the Tower Primary Connector Side B - TWR-SER Serial Board Connection - o Development Environment - o GNU Toolchain Options - o IDEs - o NuttX EABI "buildroot" Toolchain - o NuttX OABI "buildroot" Toolchain - o NXFLAT Toolchain + o KwikStik-K40-specific Configuration Options + o Configurations Kinetis KwikStik-K40 Features: ============================== @@ -148,193 +144,6 @@ Finally, we can conclude that UART5 (PTE8/9) is associated with the DB9 connector -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -===================== - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The devkitARM GNU toolchain, - 3. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the CodeSourcery Windows toolchain. To - use the devkitARM or the NuttX GNU toolchain, you simply need to change the - the following configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE: the CodeSourcery (for Windows) and devkitARM toolchains are - Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/k40, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/kinetis/k40_vectors.S. - -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M4 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M4 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - NOTE: The NuttX toolchain may not include optimizations for Cortex-M4 (ARMv7E-M). - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh kwikstik-k40/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M4 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - KwikStik-K40-specific Configuration Options ============================================ diff --git a/configs/kwikstik-k40/include/board.h b/configs/kwikstik-k40/include/board.h index 76fc1de4ca774e97c0ede3ef22623a97da386875..238967304696a455625959d692856fb5fb6bf9c9 100644 --- a/configs/kwikstik-k40/include/board.h +++ b/configs/kwikstik-k40/include/board.h @@ -247,39 +247,4 @@ #define PIN_I2C1_SCL PIN_I2C1_SCL_2 #define PIN_I2C1_SDA PIN_I2C1_SDA_2 -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: kinetis_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -EXTERN void kinetis_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/lc823450-xgevk/README.txt b/configs/lc823450-xgevk/README.txt index d79fdb4f19163d0da1ae38cb5704b2c9806b4d41..63db6a0a3088f93213d7da54f0d04b05745a5265 100644 --- a/configs/lc823450-xgevk/README.txt +++ b/configs/lc823450-xgevk/README.txt @@ -11,14 +11,31 @@ LC823450 related documents are available at http://www.onsemi.com/PowerSolutions/supportDoc.do?type=AppNotes&rpn=LC823450 +OpenOCD for NuttX thread and LC823450 support is available at + + https://github.com/sony/openocd-nuttx/wiki + +MakeIPL2 Tool for eMMC boot is available at + + http://www.onsemi.com/PowerSolutions/supportDoc.do?type=software&rpn=LC823450 + This port is intended to test LC823450 features including SMP. Supported peripherals: -UART, TIMER, RTC, GPIO, DMA, I2C, SPI, LCD, eMMC, USB, WDT, ADC. +UART, TIMER, RTC, GPIO, DMA, I2C, SPI, LCD, eMMC, USB, WDT, ADC, Audio. Settings ^^^^^^^^ -1. Currently only SRAM boot via ICE is supported. +1. eMMC boot and SRAM boot via openocd are supported. + +If you do SRAM boot via openocd+gdb, please specify hookpost-load in .gdbinit +to set MSP (main stack pointer) as follows. + + define hookpost-load + print *(uint32_t *)0x02040000 + set $sp=$ + end + 2. If SWD connection is lost, please specify lower adaptor clock. 3. Both CPUs are running at 160MHz. 4. Internal SRAMs (seg0 to seg5) are used. @@ -28,9 +45,10 @@ Settings SMP related Status ^^^^^^^^^^^^^^^^^^ -Currently SMP feature works on the board but might not be stable. -In addition, console output might be corrupted if the both CPUs -output into the console because UART operates in FIFO mode. +Currently all applications except for ostest work in SMP mode but might stop +due to deadlocks or ASSERT(). + +CPU activities are shown at D9 (CPU0) and D10 (CPU1) respectively. 1. "nsh> smp" works but the result will be corrupted. 2. "nsh> ostest" works but might cause a deadlock or assertion. @@ -128,9 +146,131 @@ nsh> wdog NO ping elapsed=5500 NO ping elapsed=6000 +9. IPL2 and eMMC boot + +IPL2 is the 2nd boot loader based on NuttX and can be built as follows. + + $ make distclean + $ ./tools/configure.sh lc823450-xgevk/ipl2 + $ make V=1 + $ MakeIPL2 ./nuttx.bin 0 2 0 0 0 + $ cp LC8234xx_17S_start_data.boot_bin /tmp/ + +To write the IPL2 (LC8234xx_17S_start_data.boot_bin), +firstly build USB configuration image. + + $ make distclean + $ ./tools/configure.sh lc823450-xgevk/usb + $ make V=1 + +Load the nuttx.bin with openocd + gdb + + $ cd openocd-nuttx + $ ./bootstrap + $ ./configure + $ make + $ sudo ./src/openocd -s ./tcl -f ./tcl/board/lc823450_xgevk.cfg -c init -c "reset halt" + + $ arm-none-eabi-gdb + (gdb) target extended-remote :3333 + (gdb) load ./nuttx + (gdb) symbol-file ./nuttx + (gdb) c + +Start USB MSC to copy nuttx.bin and the IPL2 to the FAT32 partition (/dev/mtdblock0p10) +then dd the files to the kernel partition (/dev/mtdblock0p4) and the IPL2 partition +(/dev/mtdblock0p1) respectively. + + nsh> mkfatfs -F 32 /dev/mtdblock0p10 + nsh> msconn + + $ sudo cp ./nuttx.bin /media/usb0/ + $ sudo cp /tmp/LC8234xx_17S_start_data.boot_bin /media/usb0/ + $ sudo sync + + nsh> msdis + nsh> mount -t vfat /dev/mtdblock0p10 /mnt/sd0 + nsh> dd if=/mnt/sd0/nuttx.bin of=/dev/mtdblock0p4 + nsh> dd if=/mnt/sd0/LC8234xx_17S_start_data.boot_bin of=/dev/mtdblock0p1 + nsh> reboot + +10. Audio playback (WAV/44.1k/16bit/2ch only) + +Firstly, please make sure that the jumper pins are set as follows. + + JP1, JP2 => short + JP3, JP4 => open + +To play WAV file on uSD card, + + nsh> mount -t vfat /dev/mtdblock1 /mnt/sd1 + nsh> nxplayer + nxplayer> play /mnt/sd1/sample.wav + nxplayer> volume 50 + +Please note that a WAV file which contains sub-chunks other than "fmt" +and "data" is not supported in pcm_decode.c So, if your wav file contains +meta-data, please remove the sub-chunks before playing. + +11. Networking + +lc823450/rndis configuration supports networking features with RNDIS. +To use this feature, you have to connect the board to a RNDIS host. +Currently Linux host is only tested but Windows host should work. + +If DHCP server is available, you would see ifconfig results like: + +nsh> ifconfig +eth0 Link encap:Ethernet HWaddr 00:e0:de:ad:be:ff at UP + inet addr:192.168.1.244 DRaddr:192.168.1.1 Mask:255.255.255.0 + + +lo Link encap:Local Loopback at UP + inet addr:127.0.0.1 DRaddr:127.0.0.1 Mask:255.0.0.0 + + + IPv4 TCP UDP ICMP +Received 0007 0000 0006 0000 +Dropped 0001 0000 0000 0000 + IPv4 VHL: 0000 Frg: 0001 + Checksum 0000 0000 0000 ---- + TCP ACK: 0000 SYN: 0000 + RST: 0000 0000 + Type 0000 ---- ---- 0000 +Sent 0003 0000 0003 0000 + Rexmit ---- 0000 ---- ---- + +However, you might need to add a routing table if you want to send +a packet via the router. + +nsh> addroute 0.0.0.0/0 192.168.1.1 +nsh> route +SEQ TARGET NETMASK ROUTER + 1. 0.0.0.0 0.0.0.0 192.168.1.1 + +12. DVFS (Dynamic Voltage and Frequency Scaling) + +lc823450-xgevk/audio and rndis configurations support DVFS. +You can check the status via /proc/dvfs + +nsh> cat /proc/dvfs +cur_freq 160 +enable 0 + +By default, DVFS is disabled. To enable, + +nsh> echo "enable 1" > /proc/dvfs + +In addition, you can change CPU frequency to 160/80/40. To change the +frequency, enable the DVFS first then do the following. + +nsh> echo "cur_freq 80" > /proc/dvfs. + +Currently, DVFS works in manual mode and Vdd1 is fixed to 1.2V +which will be changed in the future version. TODO ^^^^ The following features will be supported. -IPL2 (eMMC boot), Audio, etc. +Accelerometer, etc. diff --git a/configs/lc823450-xgevk/audio/defconfig b/configs/lc823450-xgevk/audio/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..ae8ef0ad3763e87ee2fdb116ec8ff549c8cda39a --- /dev/null +++ b/configs/lc823450-xgevk/audio/defconfig @@ -0,0 +1,149 @@ +CONFIG_AQM_1248A=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="lc823450-xgevk" +CONFIG_ARCH_BOARD_LC823450_XGEVK=y +CONFIG_ARCH_CHIP_LC823450=y +CONFIG_ARCH_FLOAT_H=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STDARG_H=y +CONFIG_AUDIO_BUFFER_NUMBYTES=1024 +CONFIG_AUDIO_EXCLUDE_BALANCE=y +CONFIG_AUDIO_EXCLUDE_FFORWARD=y +CONFIG_AUDIO_EXCLUDE_TONE=y +# CONFIG_AUDIO_FORMAT_MP3 is not set +CONFIG_AUDIO_WM8776=y +CONFIG_AUDIO=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=12061 +CONFIG_BUILTIN=y +CONFIG_C99_BOOL8=y +CONFIG_CODECS_HASH_MD5=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_ERROR=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_WARN=y +CONFIG_DEV_ZERO=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DRIVERS_AUDIO=y +CONFIG_DVFS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_NSH=y +CONFIG_EXAMPLES_NXHELLO_BPP=1 +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_OSTEST=y +CONFIG_EXAMPLES_PIPE=y +CONFIG_EXAMPLES_SMP=y +CONFIG_EXPERIMENTAL=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FATTIME=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_FS_PROCFS=y +CONFIG_HRT_TIMER=y +CONFIG_I2C_RESET=y +CONFIG_I2CTOOL_MAXBUS=1 +CONFIG_I2C=y +CONFIG_I2S=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LC823450_I2C0=y +CONFIG_LC823450_I2C1=y +CONFIG_LC823450_I2S0=y +CONFIG_LC823450_MTD=y +CONFIG_LC823450_MTM0_TICK=y +CONFIG_LC823450_SDIF_SDC=y +CONFIG_LC823450_SPI_DMA=y +CONFIG_LC823450_UART0=y +CONFIG_LCD_ST7565=y +CONFIG_LCD=y +CONFIG_LIB_KBDCODEC=y +CONFIG_LIBM=y +CONFIG_MAX_TASKS=64 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MEMSET_OPTSPEED=y +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_MTD=y +CONFIG_NAME_MAX=765 +CONFIG_NETUTILS_CODECS=y +CONFIG_NFILE_DESCRIPTORS=45 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_ARGCAT is not set +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_CMDOPT_DD_STATS=y +CONFIG_NSH_DISABLE_BASENAME=y +CONFIG_NSH_DISABLE_DIRNAME=y +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_MB=y +CONFIG_NSH_DISABLE_MH=y +CONFIG_NSH_DISABLE_MKFIFO=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_SH=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=128 +CONFIG_NSH_MAXARGUMENTS=10 +CONFIG_NSH_READLINE=y +CONFIG_NX_BLOCKING=y +# CONFIG_NX_DISABLE_1BPP is not set +CONFIG_NXFONT_MONO5X8=y +CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/mnt/sd1" +CONFIG_NX=y +CONFIG_PIPES=y +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_PTHREAD_STACK_DEFAULT=3072 +CONFIG_RAM_SIZE=1044480 +CONFIG_RAM_START=0x02001000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC=y +CONFIG_SCHED_ATEXIT=y +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_ONEXIT_MAX=32 +CONFIG_SCHED_ONEXIT=y +CONFIG_SCHED_STARTHOOK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_SMP_NCPUS=2 +CONFIG_SMP=y +# CONFIG_SPI_EXCHANGE is not set +CONFIG_SPINLOCK_IRQ=y +CONFIG_SPI=y +CONFIG_START_DAY=3 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2013 +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NXPLAYER=y +CONFIG_SYSTEM_USBMSC_CMD_STACKSIZE=2048 +CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/mtdblock0p10" +CONFIG_SYSTEM_USBMSC_DEVPATH2="/dev/mtdblock1" +CONFIG_SYSTEM_USBMSC_NLUNS=2 +CONFIG_SYSTEM_USBMSC=y +CONFIG_TASK_NAME_SIZE=24 +CONFIG_UART0_RXBUFSIZE=512 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_UART0_TXBUFSIZE=2048 +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBDEV_DUALSPEED=y +CONFIG_USBDEV_MAXPOWER=500 +CONFIG_USBDEV=y +CONFIG_USBMSC_EPBULKIN=2 +CONFIG_USBMSC_EPBULKOUT=1 +CONFIG_USBMSC_REMOVABLE=y +CONFIG_USBMSC=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_USERMAIN_STACKSIZE=3072 +CONFIG_WM8776_SWAP_HPOUT=y diff --git a/configs/lc823450-xgevk/include/board.h b/configs/lc823450-xgevk/include/board.h index a65cc9c910638e0b4fd9783aff9625e0ca7c3a7c..7be855611e1ef88506ff8450120326aa93f09a1d 100644 --- a/configs/lc823450-xgevk/include/board.h +++ b/configs/lc823450-xgevk/include/board.h @@ -38,6 +38,21 @@ #include +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#define LED_STARTED 0 /* N/A */ +#define LED_HEAPALLOCATE 1 /* N/A */ +#define LED_IRQSENABLED 2 /* N/A */ +#define LED_STACKCREATED 3 /* N/A */ +#define LED_INIRQ 4 /* N/A */ +#define LED_SIGNAL 5 /* N/A */ +#define LED_ASSERTION 6 /* N/A */ +#define LED_PANIC 7 /* N/A */ +#define LED_CPU0 8 /* LED0 (D9) */ +#define LED_CPU1 9 /* LED1 (D10) */ + /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/configs/lc823450-xgevk/ipl2/defconfig b/configs/lc823450-xgevk/ipl2/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..2279112c48509a0ff7a7e98388321834b4577fef --- /dev/null +++ b/configs/lc823450-xgevk/ipl2/defconfig @@ -0,0 +1,77 @@ +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="lc823450-xgevk" +CONFIG_ARCH_BOARD_LC823450_XGEVK=y +CONFIG_ARCH_CHIP_LC823450=y +CONFIG_ARCH_FLOAT_H=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STDARG_H=y +CONFIG_BOARD_LOOPSPERMSEC=12061 +CONFIG_BUILTIN=y +CONFIG_C99_BOOL8=y +CONFIG_CODECS_HASH_MD5=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_ERROR=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_WARN=y +CONFIG_DEV_ZERO=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_EXPERIMENTAL=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FATTIME=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LC823450_IPL2=y +CONFIG_LC823450_MTD=y +CONFIG_LC823450_SDIF_SDC=y +CONFIG_LC823450_UART0=y +CONFIG_LC823450_UART1=y +CONFIG_LIBM=y +CONFIG_MAX_TASKS=64 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MEMSET_OPTSPEED=y +CONFIG_MTD=y +CONFIG_NAME_MAX=765 +CONFIG_NETUTILS_CODECS=y +CONFIG_NFILE_DESCRIPTORS=45 +CONFIG_NFILE_STREAMS=8 +CONFIG_PIPES=y +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_PTHREAD_STACK_DEFAULT=3072 +CONFIG_RAM_SIZE=1044480 +CONFIG_RAM_START=0x02001000 +CONFIG_RAW_BINARY=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC=y +CONFIG_SCHED_ATEXIT=y +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_INSTRUMENTATION_BUFFER=y +CONFIG_SCHED_INSTRUMENTATION=y +CONFIG_SCHED_ONEXIT_MAX=32 +CONFIG_SCHED_ONEXIT=y +CONFIG_SCHED_STARTHOOK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SENSORS=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=3 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2013 +CONFIG_TASK_NAME_SIZE=24 +CONFIG_UART0_RXBUFSIZE=512 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_UART0_TXBUFSIZE=2048 +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBDEV_DUALSPEED=y +CONFIG_USBDEV_MAXPOWER=500 +CONFIG_USBDEV=y +CONFIG_USER_ENTRYPOINT="ipl2_main" +CONFIG_USERMAIN_STACKSIZE=3072 diff --git a/configs/lc823450-xgevk/nsh/defconfig b/configs/lc823450-xgevk/nsh/defconfig index 38b4a925da339f85045ed887d97016c6bad4d497..74040a673989e2b1560fd721fe0ace0af5220e23 100644 --- a/configs/lc823450-xgevk/nsh/defconfig +++ b/configs/lc823450-xgevk/nsh/defconfig @@ -1,19 +1,15 @@ -# CONFIG_LC823450_SDIF is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NX_DISABLE_1BPP is not set -# CONFIG_SPI_EXCHANGE is not set CONFIG_ADC=y CONFIG_ANALOG=y CONFIG_AQM_1248A=y -CONFIG_ARCH_BOARD_LC823450_XGEVK=y +CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="lc823450-xgevk" +CONFIG_ARCH_BOARD_LC823450_XGEVK=y CONFIG_ARCH_CHIP_LC823450=y CONFIG_ARCH_FLOAT_H=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STDARG_H=y -CONFIG_ARCH="arm" -CONFIG_BOARD_LOOPSPERMSEC=12061 CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=12061 CONFIG_BUILTIN=y CONFIG_C99_BOOL8=y CONFIG_CODECS_HASH_MD5=y @@ -39,12 +35,15 @@ CONFIG_EXAMPLES_WATCHDOG=y CONFIG_EXPERIMENTAL=y CONFIG_FS_PROCFS=y CONFIG_FS_WRITABLE=y +CONFIG_HRT_TIMER=y CONFIG_I2C_RESET=y -CONFIG_I2C=y CONFIG_I2CTOOL_MAXBUS=1 +CONFIG_I2C=y CONFIG_INTELHEX_BINARY=y CONFIG_LC823450_I2C0=y CONFIG_LC823450_I2C1=y +CONFIG_LC823450_MTM0_TICK=y +# CONFIG_LC823450_SDIF is not set CONFIG_LC823450_SPI_DMA=y CONFIG_LC823450_UART0=y CONFIG_LC823450_WDT=y @@ -61,6 +60,7 @@ CONFIG_NETUTILS_CODECS=y CONFIG_NFILE_DESCRIPTORS=45 CONFIG_NFILE_STREAMS=8 CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_ARGCAT is not set CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_BASENAME=y CONFIG_NSH_DISABLE_CP=y @@ -79,8 +79,8 @@ CONFIG_NSH_DISABLE_MKFIFO=y CONFIG_NSH_DISABLE_MKRD=y CONFIG_NSH_DISABLE_MV=y CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_RM=y CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_RM=y CONFIG_NSH_DISABLE_SH=y CONFIG_NSH_DISABLE_WGET=y CONFIG_NSH_DISABLE_XD=y @@ -88,8 +88,9 @@ CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_MAXARGUMENTS=10 CONFIG_NSH_READLINE=y CONFIG_NX_BLOCKING=y -CONFIG_NX=y +# CONFIG_NX_DISABLE_1BPP is not set CONFIG_NXFONT_MONO5X8=y +CONFIG_NX=y CONFIG_PIPES=y CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048 CONFIG_PREALLOC_MQ_MSGS=4 @@ -100,6 +101,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=3072 CONFIG_RAM_SIZE=1044480 CONFIG_RAM_START=0x02001000 CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y CONFIG_RTC_DATETIME=y CONFIG_RTC=y CONFIG_SCHED_ATEXIT=y @@ -115,6 +117,8 @@ CONFIG_SDCLONE_DISABLE=y CONFIG_SERIAL_TERMIOS=y CONFIG_SMP_NCPUS=2 CONFIG_SMP=y +# CONFIG_SPI_EXCHANGE is not set +CONFIG_SPINLOCK_IRQ=y CONFIG_SPI=y CONFIG_START_DAY=3 CONFIG_START_MONTH=10 diff --git a/configs/lc823450-xgevk/rndis/defconfig b/configs/lc823450-xgevk/rndis/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..c07e826ca66abe90b886e1d4afc831ab0c683c92 --- /dev/null +++ b/configs/lc823450-xgevk/rndis/defconfig @@ -0,0 +1,183 @@ +CONFIG_AQM_1248A=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="lc823450-xgevk" +CONFIG_ARCH_BOARD_LC823450_XGEVK=y +CONFIG_ARCH_CHIP_LC823450=y +CONFIG_ARCH_FLOAT_H=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STDARG_H=y +CONFIG_AUDIO_BUFFER_NUMBYTES=1024 +CONFIG_AUDIO_EXCLUDE_BALANCE=y +CONFIG_AUDIO_EXCLUDE_FFORWARD=y +CONFIG_AUDIO_EXCLUDE_TONE=y +# CONFIG_AUDIO_FORMAT_MP3 is not set +CONFIG_AUDIO_WM8776=y +CONFIG_AUDIO=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=12061 +CONFIG_BUILTIN=y +CONFIG_C99_BOOL8=y +CONFIG_CODECS_HASH_MD5=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_ERROR=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_NET=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_WARN=y +CONFIG_DEV_ZERO=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DRIVERS_AUDIO=y +CONFIG_DVFS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_NSH=y +CONFIG_EXAMPLES_NXHELLO_BPP=1 +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_OSTEST=y +CONFIG_EXAMPLES_PIPE=y +CONFIG_EXAMPLES_SMP=y +CONFIG_EXPERIMENTAL=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FATTIME=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_FS_PROCFS=y +CONFIG_HRT_TIMER=y +CONFIG_I2C_RESET=y +CONFIG_I2CTOOL_MAXBUS=1 +CONFIG_I2C=y +CONFIG_I2S=y +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=384 +CONFIG_IOB_NBUFFERS=128 +CONFIG_IOB_NCHAINS=64 +CONFIG_LC823450_I2C0=y +CONFIG_LC823450_I2C1=y +CONFIG_LC823450_I2S0=y +CONFIG_LC823450_MTD=y +CONFIG_LC823450_MTM0_TICK=y +CONFIG_LC823450_SDIF_SDC=y +CONFIG_LC823450_SPI_DMA=y +CONFIG_LC823450_UART0=y +CONFIG_LCD_ST7565=y +CONFIG_LCD=y +CONFIG_LIB_KBDCODEC=y +CONFIG_LIBM=y +CONFIG_MAX_TASKS=64 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MEMSET_OPTSPEED=y +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_MTD=y +CONFIG_NAME_MAX=765 +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BROADCAST=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEVICES=y +CONFIG_NET_ETH_MTU=1500 +CONFIG_NET_ETH_TCP_RECVWNDO=2800 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_ICMP=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_PKT=y +CONFIG_NET_ROUTE=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP_RWND_CONTROL=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NETUTILS_CODECS=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_PING=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET=y +CONFIG_NFILE_DESCRIPTORS=45 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_ARGCAT is not set +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_CMDOPT_DD_STATS=y +CONFIG_NSH_DHCPC=y +CONFIG_NSH_DISABLE_BASENAME=y +CONFIG_NSH_DISABLE_DIRNAME=y +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_MB=y +CONFIG_NSH_DISABLE_MH=y +CONFIG_NSH_DISABLE_MKFIFO=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_SH=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_DRIPADDR=0xa9feab5a +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=128 +CONFIG_NSH_MACADDR=0x00e0deadbeff +CONFIG_NSH_MAXARGUMENTS=10 +CONFIG_NSH_NETINIT_THREAD=y +CONFIG_NSH_NETMASK=0xffff0000 +CONFIG_NSH_NOMAC=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_WGET_USERAGENT="NuttX/7.2x.x (; http://www.nuttx.org/)" +CONFIG_NX_BLOCKING=y +# CONFIG_NX_DISABLE_1BPP is not set +CONFIG_NXFONT_MONO5X8=y +CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/mnt/sd1" +CONFIG_NXPLAYER_HTTP_STREAMING_SUPPORT=y +CONFIG_NX=y +CONFIG_PIPES=y +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_PTHREAD_STACK_DEFAULT=3072 +CONFIG_RAM_SIZE=1044480 +CONFIG_RAM_START=0x02001000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RNDIS=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC=y +CONFIG_SCHED_ATEXIT=y +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_ONEXIT_MAX=32 +CONFIG_SCHED_ONEXIT=y +CONFIG_SCHED_STARTHOOK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SENSORS=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_SMP_NCPUS=2 +CONFIG_SMP=y +# CONFIG_SPI_EXCHANGE is not set +CONFIG_SPINLOCK_IRQ=y +CONFIG_SPI=y +CONFIG_START_DAY=3 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2013 +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NXPLAYER=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=24 +CONFIG_TELNET_CHARACTER_MODE=y +CONFIG_UART0_RXBUFSIZE=512 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_UART0_TXBUFSIZE=2048 +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBDEV_DUALSPEED=y +CONFIG_USBDEV_MAXPOWER=500 +CONFIG_USBDEV=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_USERMAIN_STACKSIZE=3072 +CONFIG_WM8776_SWAP_HPOUT=y diff --git a/configs/lc823450-xgevk/scripts/Make.defs b/configs/lc823450-xgevk/scripts/Make.defs index 49cf8241c036a1f7be66f35c3c8cd910b24404b6..b9f207cc977490c078d00807a35a89ffe1258aa8 100644 --- a/configs/lc823450-xgevk/scripts/Make.defs +++ b/configs/lc823450-xgevk/scripts/Make.defs @@ -37,6 +37,12 @@ include ${TOPDIR}/.config include ${TOPDIR}/tools/Config.mk include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs +ifeq ($(CONFIG_LC823450_IPL2),y) + LDSCRIPT = ld-ipl2.script +else + LDSCRIPT = ld.script +endif + ifeq ($(WINTOOL),y) # Windows-native toolchains DIRLINK = $(TOPDIR)/tools/copydir.sh @@ -44,13 +50,13 @@ ifeq ($(WINTOOL),y) MKDEP = $(TOPDIR)/tools/mkwindeps.sh ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" else # Linux/Cygwin-native toolchain MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) ARCHINCLUDES = -I. -isystem $(TOPDIR)/include ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) endif CC = $(CROSSDEV)gcc @@ -116,8 +122,13 @@ ARCH_LIBPATHS += -L"$(TOPDIR)/arch/arm/src/lc823450" endif ifeq ($(CONFIG_LC823450_SDIF),y) -ARCH_LIBS += $(ARCH_LIBS_OPT)--just-symbols=$(TOPDIR)/arch/arm/src/lc823450/lc823450_symbols.ld -LDFLAGS +=--no-wchar-size-warning +ifeq ($(WINTOOL),y) + ARCH_SYMBOLS = "${shell cygpath -w $(TOPDIR)/arch/arm/src/lc823450/lc823450_symbols.ld}" +else + ARCH_SYMBOLS = $(TOPDIR)/arch/arm/src/lc823450/lc823450_symbols.ld +endif + ARCH_LIBS += $(ARCH_LIBS_OPT) --just-symbols=$(ARCH_SYMBOLS) + LDFLAGS += --no-wchar-size-warning endif diff --git a/configs/lc823450-xgevk/scripts/ld-ipl2.script b/configs/lc823450-xgevk/scripts/ld-ipl2.script new file mode 100644 index 0000000000000000000000000000000000000000..f9408b2f65d57ff1ebb2451a5bbbe57776270509 --- /dev/null +++ b/configs/lc823450-xgevk/scripts/ld-ipl2.script @@ -0,0 +1,120 @@ +/**************************************************************************** + * configs/lc823450-xgevk/scripts/ld-ipl2.script + * + * Copyright (C) 2017 Sony Corporation. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + + +MEMORY +{ + progmem (rx) : ORIGIN = 0x02000e00, LENGTH = 124K + sram (rwx) : ORIGIN = 0x02100000, LENGTH = 256K + ramlog (rwx) : ORIGIN = 0x020fe000, LENGTH = 8K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + + .text : { + _stext = ABSOLUTE(.); + KEEP(*(.vectors)) + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > progmem + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > progmem + + .ARM.extab : { + *(.ARM.extab*) + } > progmem + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > progmem + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(LOADADDR(.data)); + + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > progmem + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + .ramlog : { + *(.ramlog) + } > ramlog + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/lc823450-xgevk/src/Makefile b/configs/lc823450-xgevk/src/Makefile index 975cf9e9bef2464c5822d6e329f7190ed913f45c..2a41b88297ba4ed1aacea290537e1480a5115b5a 100644 --- a/configs/lc823450-xgevk/src/Makefile +++ b/configs/lc823450-xgevk/src/Makefile @@ -72,4 +72,12 @@ ifeq ($(CONFIG_NETDEVICES),y) CSRCS += lc823450_netinit.c endif +ifeq ($(CONFIG_AUDIO_WM8776),y) +CSRCS += lc823450_wm8776.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += lc823450_autoleds.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/lc823450-xgevk/src/lc823450-xgevk.h b/configs/lc823450-xgevk/src/lc823450-xgevk.h index a73818d7c908d5c6de820a22b7574f8b8bf64abe..ab80b2bcd7e21249c980f8ca63fdb3ad98353c30 100644 --- a/configs/lc823450-xgevk/src/lc823450-xgevk.h +++ b/configs/lc823450-xgevk/src/lc823450-xgevk.h @@ -94,5 +94,9 @@ int lc823450_bringup(void); int lc823450_bma250initialize(FAR const char *devpath); #endif +#ifdef CONFIG_AUDIO_WM8776 +int lc823450_wm8776initialize(int minor); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_LC823450_XGEVK_SRC_LC823450_XGEVK_H */ diff --git a/configs/lc823450-xgevk/src/lc823450-xgevk_mux.h b/configs/lc823450-xgevk/src/lc823450-xgevk_mux.h index d55b81da09e6fa42c3bd9ef35d86d60da57e1fe6..97295194ef60988a15be75ca578d7005b0659902 100644 --- a/configs/lc823450-xgevk/src/lc823450-xgevk_mux.h +++ b/configs/lc823450-xgevk/src/lc823450-xgevk_mux.h @@ -149,11 +149,11 @@ 1 << 10 | /* 0: GPIO15, 1:DOUT1 */ \ 0 << 12 | /* 0: GPIO16, 1:NLBEXA0 */ \ 0 << 14 | /* 0: GPIO17, 1:NRD */ \ - 0 << 16 | /* 0: GPIO18, 1:MCLK0, 2:MCLK1 */ \ - 0 << 18 | /* 0: GPIO19, 1:BCK0, 2:DMCKO1 */ \ - 0 << 20 | /* 0: GPIO1A, 1:LRCK0, 2:DMDIN1 */ \ - 2 << 22 | /* 0: GPIO1B, 1:DIN0, 2:DMDIN0 */ \ - 0 << 24 | /* 0: GPIO1C, 1:DOUT0, 2:DMCKO0 */ \ + 1 << 16 | /* 0: GPIO18, 1:MCLK0, 2:MCLK1 */ \ + 1 << 18 | /* 0: GPIO19, 1:BCK0, 2:DMCKO1 */ \ + 1 << 20 | /* 0: GPIO1A, 1:LRCK0, 2:DMDIN1 */ \ + 1 << 22 | /* 0: GPIO1B, 1:DIN0, 2:DMDIN0 */ \ + 1 << 24 | /* 0: GPIO1C, 1:DOUT0, 2:DMCKO0 */ \ 1 << 26 | /* 0: GPIO1D, 1:SCK0 */ \ 0 << 28 | /* 0: GPIO1E, 1:SDI0 */ \ 1 << 30 /* 0: GPIO1F, 1:SDO0 */ @@ -185,7 +185,7 @@ 0 << 10 | /* GPIO15 0:1mA, 1:---, 2:2mA, 3:4mA */ \ 0 << 12 | /* GPIO16 0:2mA, 1:---, 2:4mA, 3:8mA */ \ 0 << 14 | /* GPIO17 0:2mA, 1:---, 2:4mA, 3:8mA */ \ - 0 << 16 | /* GPIO18 0:1mA, 1:---, 2:2mA, 3:4mA */ \ + 3 << 16 | /* GPIO18 0:1mA, 1:---, 2:2mA, 3:4mA */ \ 0 << 18 | /* GPIO19 0:1mA, 1:---, 2:2mA, 3:4mA */ \ 0 << 20 | /* GPIO1A 0:1mA, 1:---, 2:2mA, 3:4mA */ \ 0 << 22 | /* GPIO1B 0:1mA, 1:---, 2:2mA, 3:4mA */ \ diff --git a/configs/xtrs/src/xtr_lowputc.c b/configs/lc823450-xgevk/src/lc823450_autoleds.c similarity index 66% rename from configs/xtrs/src/xtr_lowputc.c rename to configs/lc823450-xgevk/src/lc823450_autoleds.c index 67237730a035b2a68b59d09a04352447c92e2b32..48cacdbd5a3c5aa807a8d9e2d26b4d16502a3f05 100644 --- a/configs/xtrs/src/xtr_lowputc.c +++ b/configs/lc823450-xgevk/src/lc823450_autoleds.c @@ -1,12 +1,8 @@ -/******************************************************************************** - * configs/xtrs/src//xtr_lowputc.c +/**************************************************************************** + * configs/lc823450-xgevk/src/lc823450_autoleds.c * - * Copyright (C) 2008 Jacques Pelletier. All rights reserved. - * Author: Jacques Pelletier - * - * This file is a part of NuttX and hence - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2017 Sony Corporation. All rights reserved. + * Author: Masayuki Ishikawa * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -35,70 +31,85 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************/ + ****************************************************************************/ -/******************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************/ + ****************************************************************************/ #include -#include -#include -#include +#include +#include #include -#include "up_internal.h" +#include +#include -/* Includes trs80-m3.h for assembler call addresses */ +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" -#include +#include "lc823450_gpio.h" +#include "lc823450-xgevk.h" -/******************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************/ + ****************************************************************************/ -/******************************************************************************** - * Public Data - ********************************************************************************/ +#define LED0_PIN (GPIO_PORT0 | GPIO_PIN0) +#define LED1_PIN (GPIO_PORT2 | GPIO_PINF) -/******************************************************************************** - * Private Data - ********************************************************************************/ +/**************************************************************************** + * Public Functions + ****************************************************************************/ -/******************************************************************************** - * Private Functions - ********************************************************************************/ +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ -/******************************************************************************** - * Public Functions - ********************************************************************************/ +void board_autoled_initialize(void) +{ +} -/******************************************************************************** - * Name: z80_lowputc - ********************************************************************************/ +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ -void z80_lowputc(char ch) __naked +void board_autoled_on(int led) { - __asm - ld hl, #2 - add hl, sp - ld a, (hl) - call _TRS80_M3_VDCHAR ;0x0033 - ret - __endasm; + switch (led) + { + case LED_CPU0: + lc823450_gpio_write(LED0_PIN, 1); + break; + + case LED_CPU1: + lc823450_gpio_write(LED1_PIN, 1); + break; + + default: + break; + } } -/******************************************************************************** - * Name: z80_lowgetc - ********************************************************************************/ +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ -char z80_lowgetc(void) __naked +void board_autoled_off(int led) { - __asm - call _TRS80_M3_KBDSCN ;0x002b - ld l, a - ld h, #0 - ret - __endasm; + switch (led) + { + case LED_CPU0: + lc823450_gpio_write(LED0_PIN, 0); + break; + + case LED_CPU1: + lc823450_gpio_write(LED1_PIN, 0); + break; + + default: + break; + } } diff --git a/configs/lc823450-xgevk/src/lc823450_bringup.c b/configs/lc823450-xgevk/src/lc823450_bringup.c index 98447fb1285e73deed28a764a1a5a0c3ad44c72a..8b41c839fe5f4c84aa4f7ef3c354f6d8b73e1de1 100644 --- a/configs/lc823450-xgevk/src/lc823450_bringup.c +++ b/configs/lc823450-xgevk/src/lc823450_bringup.c @@ -45,10 +45,22 @@ #include #include +#ifdef CONFIG_SMP +# include +#endif + +#ifdef CONFIG_RNDIS +# include +#endif + #ifdef CONFIG_WATCHDOG # include "lc823450_wdt.h" #endif +#ifdef CONFIG_DVFS +# include "lc823450_dvfs2.h" +#endif + #include "lc823450-xgevk.h" /**************************************************************************** @@ -72,6 +84,11 @@ int lc823450_bringup(void) #endif #ifdef CONFIG_FS_PROCFS + +#ifdef CONFIG_DVFS + (void)dvfs_procfs_register(); +#endif + /* Mount the procfs file system */ ret = mount(NULL, "/proc", "procfs", 0, NULL); @@ -81,10 +98,43 @@ int lc823450_bringup(void) } #endif +#ifdef CONFIG_FS_FAT + ret = mount("/dev/mtdblock0p10", "/mnt/sd0", "vfat", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount vfat at /mnt/sd0: %d\n", ret); + } +#endif + #ifdef CONFIG_BMA250 lc823450_bma250initialize("/dev/accel"); #endif +#ifdef CONFIG_AUDIO_WM8776 + lc823450_wm8776initialize(0); +#endif + +#if defined(CONFIG_RNDIS) && defined(CONFIG_NSH_MACADDR) + uint8_t mac[6]; + mac[0] = 0xaa; /* TODO */ + mac[1] = (CONFIG_NSH_MACADDR >> (8 * 4)) & 0xff; + mac[2] = (CONFIG_NSH_MACADDR >> (8 * 3)) & 0xff; + mac[3] = (CONFIG_NSH_MACADDR >> (8 * 2)) & 0xff; + mac[4] = (CONFIG_NSH_MACADDR >> (8 * 1)) & 0xff; + mac[5] = (CONFIG_NSH_MACADDR >> (8 * 0)) & 0xff; + usbdev_rndis_initialize(mac); +#endif + +#if defined(CONFIG_SMP) && defined (CONFIG_RNDIS) + cpu_set_t cpuset; + CPU_ZERO(&cpuset); + CPU_SET(1, &cpuset); /* assigned to CPU1 */ + + /* NOTE: pid=4 is assumed to be lpwork */ + + sched_setaffinity(4, sizeof(cpu_set_t), &cpuset); +#endif + /* If we got here then perhaps not all initialization was successful, but * at least enough succeeded to bring-up NSH with perhaps reduced * capabilities. diff --git a/configs/lc823450-xgevk/src/lc823450_netinit.c b/configs/lc823450-xgevk/src/lc823450_netinit.c new file mode 100644 index 0000000000000000000000000000000000000000..a8ee1690c994a4419aaf5734c08564a1686889f9 --- /dev/null +++ b/configs/lc823450-xgevk/src/lc823450_netinit.c @@ -0,0 +1,52 @@ +/**************************************************************************** + * configs/lc823450-xgevk/src/lc823450_netinit.c + * + * Copyright (C) 2017 Sony Corporation. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_netinitialize + ****************************************************************************/ + +void up_netinitialize(void) +{ +} diff --git a/configs/lc823450-xgevk/src/lc823450_wm8776.c b/configs/lc823450-xgevk/src/lc823450_wm8776.c new file mode 100644 index 0000000000000000000000000000000000000000..50116a6ecc58a44dc58bb995e256c374afb000ba --- /dev/null +++ b/configs/lc823450-xgevk/src/lc823450_wm8776.c @@ -0,0 +1,130 @@ +/**************************************************************************** + * configs/lc823450-xgevk/src/lc823450_wm8776.c + * + * Copyright (C) 2017 Sony Corporation. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "lc823450_i2c.h" +#include "lc823450_i2s.h" +#include "lc823450-xgevk.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define WM8776_I2C_PORTNO 0 /* On I2C0 */ +#define WM8776_I2C_ADDR 0x1a + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct wm8776_lower_s g_wm8776info = +{ + .address = WM8776_I2C_ADDR, + .frequency = 400000, +}; + + +/**************************************************************************** + * Name: lc823450_wm8776initialize + ****************************************************************************/ + +int lc823450_wm8776initialize(int minor) +{ + FAR struct audio_lowerhalf_s *wm8776; + FAR struct audio_lowerhalf_s *pcm; + FAR struct i2c_master_s *i2c; + FAR struct i2s_dev_s *i2s; + char devname[12]; + int ret; + + ainfo("Initializing WM8776 \n"); + + /* Initialize I2C */ + + i2c = lc823450_i2cbus_initialize(WM8776_I2C_PORTNO); + + if (!i2c) + { + return -ENODEV; + } + + i2s = lc823450_i2sdev_initialize(); + + wm8776 = wm8776_initialize(i2c, i2s, &g_wm8776info); + + if (!wm8776) + { + auderr("ERROR: Failed to initialize the WM8904\n"); + return -ENODEV; + } + + pcm = pcm_decode_initialize(wm8776); + + if (!pcm) + { + auderr("ERROR: Failed create the PCM decoder\n"); + return -ENODEV; + } + + snprintf(devname, 12, "pcm%d", minor); + + ret = audio_register(devname, pcm); + + if (ret < 0) + { + auderr("ERROR: Failed to register /dev/%s device: %d\n", devname, ret); + } + + return 0; +} + diff --git a/configs/lc823450-xgevk/usb/defconfig b/configs/lc823450-xgevk/usb/defconfig index 164f4b96466663d9d3362c88db6f3af4d2d2ddd7..4b680dbd510be51c813643b17f67c16c44a842f3 100644 --- a/configs/lc823450-xgevk/usb/defconfig +++ b/configs/lc823450-xgevk/usb/defconfig @@ -1,18 +1,15 @@ -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NX_DISABLE_1BPP is not set -# CONFIG_SPI_EXCHANGE is not set CONFIG_ADC=y CONFIG_ANALOG=y CONFIG_AQM_1248A=y -CONFIG_ARCH_BOARD_LC823450_XGEVK=y +CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="lc823450-xgevk" +CONFIG_ARCH_BOARD_LC823450_XGEVK=y CONFIG_ARCH_CHIP_LC823450=y CONFIG_ARCH_FLOAT_H=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STDARG_H=y -CONFIG_ARCH="arm" -CONFIG_BOARD_LOOPSPERMSEC=12061 CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=12061 CONFIG_BUILTIN=y CONFIG_C99_BOOL8=y CONFIG_CODECS_HASH_MD5=y @@ -40,16 +37,18 @@ CONFIG_EXAMPLES_WATCHDOG=y CONFIG_EXPERIMENTAL=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y CONFIG_FS_FATTIME=y +CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y +CONFIG_HRT_TIMER=y CONFIG_I2C_RESET=y -CONFIG_I2C=y CONFIG_I2CTOOL_MAXBUS=1 +CONFIG_I2C=y CONFIG_INTELHEX_BINARY=y CONFIG_LC823450_I2C0=y CONFIG_LC823450_I2C1=y CONFIG_LC823450_MTD=y +CONFIG_LC823450_MTM0_TICK=y CONFIG_LC823450_SDIF_SDC=y CONFIG_LC823450_SPI_DMA=y CONFIG_LC823450_UART0=y @@ -69,6 +68,7 @@ CONFIG_NETUTILS_CODECS=y CONFIG_NFILE_DESCRIPTORS=45 CONFIG_NFILE_STREAMS=8 CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_ARGCAT is not set CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_CMDOPT_DD_STATS=y CONFIG_NSH_DISABLE_EXEC=y @@ -89,8 +89,9 @@ CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_MAXARGUMENTS=10 CONFIG_NSH_READLINE=y CONFIG_NX_BLOCKING=y -CONFIG_NX=y +# CONFIG_NX_DISABLE_1BPP is not set CONFIG_NXFONT_MONO5X8=y +CONFIG_NX=y CONFIG_PIPES=y CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048 CONFIG_PREALLOC_MQ_MSGS=4 @@ -101,6 +102,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=3072 CONFIG_RAM_SIZE=1044480 CONFIG_RAM_START=0x02001000 CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y CONFIG_RTC_DATETIME=y CONFIG_RTC=y CONFIG_SCHED_ATEXIT=y @@ -117,6 +119,8 @@ CONFIG_SENSORS=y CONFIG_SERIAL_TERMIOS=y CONFIG_SMP_NCPUS=2 CONFIG_SMP=y +# CONFIG_SPI_EXCHANGE is not set +CONFIG_SPINLOCK_IRQ=y CONFIG_SPI=y CONFIG_START_DAY=3 CONFIG_START_MONTH=10 diff --git a/configs/lincoln60/README.txt b/configs/lincoln60/README.txt index 534167fa2f7f12d59128609c92ab12b7fd10acf6..d90a11e6a00af69ca61b099a363ea5aba4f3f29a 100644 --- a/configs/lincoln60/README.txt +++ b/configs/lincoln60/README.txt @@ -7,13 +7,6 @@ Contents ^^^^^^^^ Lincoln 60 development board - Development Environment - GNU Toolchain Options - IDEs - NuttX EABI "buildroot" Toolchain - NuttX OABI "buildroot" Toolchain - NXFLAT Toolchain - USB Device Controller Functions Lincoln 60 Configuration Options USB Host Configuration Configurations @@ -54,192 +47,6 @@ Lincoln 60 board The Lincoln 60 has two serial connectors. The serial console defaults to COM1 (UART0). -Development Environment -^^^^^^^^^^^^^^^^^^^^^^^ - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -^^^^^^^^^^^^^^^^^^^^^ - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The devkitARM GNU toolchain, - 3. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the NuttX buildroot toolchain. However, - the make system is setup to default to use the devkitARM toolchain. To use - the CodeSourcery or devkitARM toolchain, you simply need add one of the - following configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE: the CodeSourcery (for Windows)and devkitARM are Windows native toolchains. - The CodeSourcey (for Linux) and NuttX buildroot toolchains are Cygwin and/or - Linux native toolchains. There are several limitations to using a Windows based - toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -^^^^ - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lpc17xx, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/lpc17x/lpc17_vectors.S. - -NuttX EABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lincoln60/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you - are building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conerntions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -^^^^^^^^^^^^^^^^ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - Lincoln 60 Configuration Options ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/configs/lincoln60/include/board.h b/configs/lincoln60/include/board.h index b22aa4de6d3c514f4408120e6f9e033d0b76955b..a7c7acac1f335c0515cefa3f6e8ae540a20c1bc2 100644 --- a/configs/lincoln60/include/board.h +++ b/configs/lincoln60/include/board.h @@ -199,19 +199,6 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -/**************************************************************************** - * Name: lpc17_boardinitialize - * - * Description: - * All LPC17xx architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void lpc17_boardinitialize(void); - /**************************************************************************** * Name: lpc17_led * diff --git a/configs/lincoln60/src/lpc17_buttons.c b/configs/lincoln60/src/lpc17_buttons.c index 48ea4298262f9e1a256f626855e863387578e322..7a9981db8d67d9e69a02ed23363ba2417a89baf5 100644 --- a/configs/lincoln60/src/lpc17_buttons.c +++ b/configs/lincoln60/src/lpc17_buttons.c @@ -64,7 +64,7 @@ * the BUTTON_* and JOYSTICK_* definitions in board.h */ -static const uint16_t g_buttoncfg[BOARD_NUM_BUTTONS] = +static const uint16_t g_buttoncfg[NUM_BUTTONS] = { LINCOLN60_BUT1 }; @@ -74,7 +74,7 @@ static const uint16_t g_buttoncfg[BOARD_NUM_BUTTONS] = * numbers. */ -static uint8_t g_buttonirq[BOARD_NUM_BUTTONS] = +static uint8_t g_buttonirq[NUM_BUTTONS] = { LINCOLN60_BUT1_IRQ }; @@ -105,7 +105,7 @@ void board_button_initialize(void) /* Configure the GPIO pins as interrupting inputs. */ - for (i = 0; i < BOARD_NUM_BUTTONS; i++) + for (i = 0; i < NUM_BUTTONS; i++) { lpc17_configgpio(g_buttoncfg[i]); } @@ -134,7 +134,7 @@ uint32_t board_buttons(void) /* Check that state of each key */ - for (i = 0; i < BOARD_NUM_BUTTONS; i++) + for (i = 0; i < NUM_BUTTONS; i++) { /* A LOW value means that the key is pressed. */ @@ -179,7 +179,7 @@ int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) /* Verify that the button ID is within range */ - if ((unsigned)id < BOARD_NUM_BUTTONS) + if ((unsigned)id < NUM_BUTTONS) { /* Disable interrupts until we are done */ diff --git a/configs/lm3s6432-s2e/README.txt b/configs/lm3s6432-s2e/README.txt index 51faa2204996a42ee1314dea5d674ac375d104bc..3a29a55d35e28c9239ecbcfd0b08c0a1b54ea4c4 100644 --- a/configs/lm3s6432-s2e/README.txt +++ b/configs/lm3s6432-s2e/README.txt @@ -8,12 +8,6 @@ Contents ^^^^^^^^ Stellaris RDK-S2E Reference Design Kit - Development Environment - GNU Toolchain Options - IDEs - NuttX EABI "buildroot" Toolchain - NuttX OABI "buildroot" Toolchain - NXFLFAT Toolchain Stellaris MDL-S2E Reference Design Configuration Options Configurations @@ -75,195 +69,6 @@ C12 PB3 Transciever #ENABLE A6 PB4 Transciever ON B7 PB5 Transciever #OFF -Development Environment -^^^^^^^^^^^^^^^^^^^^^^^ - - Either Linux, Mac OS X or Cygwin on Windows can be used for the development - environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using GCC on - Mac OS X. - -GNU Toolchain Options -^^^^^^^^^^^^^^^^^^^^^ - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The devkitARM GNU toolchain, - 3. The NuttX buildroot Toolchain (see below). - - To use a specific toolchain, you simply need to add one of the following - configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux or on Mac OS X. - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE: the CodeSourcery (for Windows) and devkitARM are Windows native toolchains. - The CodeSourcey (for Linux) and NuttX buildroot toolchains are Cygwin and/or Linux - native toolchains. There are several limitations to using a Windows based - toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -^^^^ - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lm, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/tiva/tiva_vectors.S. - -NuttX EABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - This port was tested with tools built using summon-arm-toolchain; available - from https://github.com/esden/summon-arm-toolchain, however the buildroot - instructions should apply for other platforms. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lm3s6432-s2e/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you - are building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -^^^^^^^^^^^^^^^^ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - Stellaris MDL-S2E Reference Design Configuration Options ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/configs/lm3s6432-s2e/include/board.h b/configs/lm3s6432-s2e/include/board.h index 33a9b56d88ae4472a3bf3a1c5c7aba3f2ed18eff..224f5d097df20440a60024362662e9662ae98a98 100644 --- a/configs/lm3s6432-s2e/include/board.h +++ b/configs/lm3s6432-s2e/include/board.h @@ -107,23 +107,4 @@ #define LED_ASSERTION 6 /* ON OFF */ #define LED_PANIC 7 /* ON OFF */ -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Name: tiva_boardinitialize - * - * Description: - * All Stellaris architectures must provide the following entry point. This entry - * point is called early in the intitialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void tiva_boardinitialize(void); - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/lm3s6965-ek/README.txt b/configs/lm3s6965-ek/README.txt index 02113d495bb31550bea8f4da0c32a761b6bbc084..1eb8346ed78cccc47273913f8b204469358f4e6a 100644 --- a/configs/lm3s6965-ek/README.txt +++ b/configs/lm3s6965-ek/README.txt @@ -7,15 +7,9 @@ Contents ^^^^^^^^ Stellaris LMS36965 Evaluation Kit - Development Environment - GNU Toolchain Options - IDEs - NuttX EABI "buildroot" Toolchain - NuttX OABI "buildroot" Toolchain - NXFLAT Toolchain - USB Device Controller Functions OLED Using OpenOCD and GDB with an FT2232 JTAG emulator + USB Device Controller Functions Stellaris LM3S6965 Evaluation Kit Configuration Options Configurations @@ -183,197 +177,6 @@ Using OpenOCD and GDB with an FT2232 JTAG emulator 2. Reset will restart the processor after loading code. 3. The 'monitor' command can be abbreviated as just 'mon'. -Development Environment -^^^^^^^^^^^^^^^^^^^^^^^ - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -^^^^^^^^^^^^^^^^^^^^^ - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The devkitARM GNU toolchain, - 3. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the NuttX buildroot toolchain. However, - the make system is setup to default to use the devkitARM toolchain. To use - the CodeSourcery or devkitARM, you simply need to add one of the following - configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE: the CodeSourcery (for Windows) and devkitARM are Windows native toolchains. - The CodeSourcey (for Linux) and NuttX buildroot toolchains are Cygwin and/or Linux - native toolchains. There are several limitations to using a Windows based - toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - - NOTE 3: I recently (i.e., late 2011) tried building with the CodeSourcery Windows - toolchain. The code worked but required 40 seconds to boot (or even until the - status LED illuminates)!! Know idea why. With the buildroot tools, boot time is - a couple of seconds. - -IDEs -^^^^ - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lm, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/tiva/tiva_vectors.S. - -NuttX EABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lm3s6965-ek/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you - are building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -^^^^^^^^^^^^^^^^ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - USB Device Controller Functions ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/configs/lm3s6965-ek/include/board.h b/configs/lm3s6965-ek/include/board.h index cf67c6b963514a367293c04e920b70b55174ba6a..4c23ea6692885b3529b2d3ad2e41dd7284c8c374 100644 --- a/configs/lm3s6965-ek/include/board.h +++ b/configs/lm3s6965-ek/include/board.h @@ -105,23 +105,4 @@ #define LED_ASSERTION 6 /* ON OFF */ #define LED_PANIC 7 /* ON OFF */ -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Name: tiva_boardinitialize - * - * Description: - * All Stellaris architectures must provide the following entry point. This entry - * point is called early in the intitialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void tiva_boardinitialize(void); - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/lm3s6965-ek/src/lm_oled.c b/configs/lm3s6965-ek/src/lm_oled.c index 93705b76cdb0a841b6d40f3bf13e43d657740760..3172e019af2fc85aa9fe637d857bb5f20584dfe3 100644 --- a/configs/lm3s6965-ek/src/lm_oled.c +++ b/configs/lm3s6965-ek/src/lm_oled.c @@ -63,11 +63,6 @@ * Verbose debug must also be enabled */ -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_INFO -# undef CONFIG_DEBUG_GRAPHICS -#endif - #ifndef CONFIG_DEBUG_INFO # undef CONFIG_LCD_RITDEBUG #endif diff --git a/configs/lm3s8962-ek/README.txt b/configs/lm3s8962-ek/README.txt index 37d7c8b7440fe57d2f151a6811f9526d9b9b0673..aec451404fb8483a77207f702c15ee27ddb24a5b 100644 --- a/configs/lm3s8962-ek/README.txt +++ b/configs/lm3s8962-ek/README.txt @@ -7,14 +7,8 @@ Contents ^^^^^^^^ Stellaris LMS38962 Evaluation Kit - Development Environment - GNU Toolchain Options - IDEs - NuttX EABI "buildroot" Toolchain - NuttX OABI "buildroot" Toolchain - NXFLAT Toolchain - USB Device Controller Functions OLED + USB Device Controller Functions Stellaris LM3S8962 Evaluation Kit Configuration Options Configurations @@ -103,181 +97,6 @@ OLED display. Some tweaks to drivers/lcd/p14201.c would be required to support that LCD. -Development Environment -^^^^^^^^^^^^^^^^^^^^^^^ - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -^^^^^^^^^^^^^^^^^^^^^ - - The NuttX make system has been modified to support the multiple toolchain - options including: - - 1. The CodeSourcery GNU toolchain, - 2. The devkitARM GNU toolchain, - 3. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the NuttX buildroot toolchain. However, - the make system is setup to default to use the devkitARM toolchain. To use - the CodeSourcery or devkitARM, you simply need to add one of the following - configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE: the CodeSourcery (for Windows) and devkitARM are Windows native toolchains. - The CodeSourcey (for Linux) and NuttX buildroot toolchains are Cygwin and/or Linux - native toolchains. There are several limitations to using a Windows based - toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -^^^^ - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. Here are a few tip before you - start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lm, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/tiva/tiva_vectors.S. - -NuttX EABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lm3s8962-ek/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you - are building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -^^^^^^^^^^^^^^^^ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - USB Device Controller Functions ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/configs/lm3s8962-ek/include/board.h b/configs/lm3s8962-ek/include/board.h index 0574814e9f43d6f609b1476ee1041534013b5628..d3b1e9b721f5c94537ab252bccc7b61163c3896b 100644 --- a/configs/lm3s8962-ek/include/board.h +++ b/configs/lm3s8962-ek/include/board.h @@ -105,23 +105,4 @@ #define LED_ASSERTION 6 /* ON OFF */ #define LED_PANIC 7 /* ON OFF */ -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Name: tiva_boardinitialize - * - * Description: - * All Stellaris architectures must provide the following entry point. This entry - * point is called early in the intitialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void tiva_boardinitialize(void); - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/lm4f120-launchpad/README.txt b/configs/lm4f120-launchpad/README.txt index 432b8503a74ef6e92e7d2a8e9b23edd734b7b9f3..f4e93aec0676f7bb93218ff3fb19d56964c543f5 100644 --- a/configs/lm4f120-launchpad/README.txt +++ b/configs/lm4f120-launchpad/README.txt @@ -8,16 +8,10 @@ Contents Stellaris LM4F120 LaunchPad On-Board GPIO Usage - Development Environment - GNU Toolchain Options - IDEs - NuttX EABI "buildroot" Toolchain - NuttX OABI "buildroot" Toolchain - NXFLAT Toolchain + Using OpenOCD and GDB with an FT2232 JTAG emulator LEDs Serial Console USB Device Controller Functions - Using OpenOCD and GDB with an FT2232 JTAG emulator LM4F120 LaunchPad Configuration Options Configurations @@ -235,198 +229,6 @@ Using OpenOCD and GDB with an FT2232 JTAG emulator 2. Reset will restart the processor after loading code. 3. The 'monitor' command can be abbreviated as just 'mon'. -Development Environment -^^^^^^^^^^^^^^^^^^^^^^^ - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -^^^^^^^^^^^^^^^^^^^^^ - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The NuttX buildroot Toolchain (default, see below), - 2. The CodeSourcery GNU toolchain, - 3. The devkitARM GNU toolchain, - 4. The Atollic toolchain, or - 5. The Code Red toolchain - - All testing has been conducted using the Buildroot toolchain for Cygwin/Linux. - To use a different toolchain, you simply need to add one of the following - configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows or Cygwin - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : The Atollic toolchain under Windows or Cygwin - CONFIG_ARMV7M_TOOLCHAIN_CODEREDW=y : The Code Red toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODEREDL=y : The Code Red toolchain under Linux - - CONFIG_ARMV7M_OABI_TOOLCHAIN=y : If you use an older, OABI buildroot toolchain - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE: the CodeSourcery (for Windows), Atollic, devkitARM, and Code Red (for Windows) - toolchains are Windows native toolchains. The CodeSourcey (for Linux) and NuttX - buildroot toolchains are Cygwin and/or Linux native toolchains. There are several - limitations to using a Windows based toolchain in a Cygwin environment. The three - biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -^^^^ - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lm, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/tiva/tiva_vectors.S. - -NuttX EABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lm4f120-launchpad/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you - are building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -^^^^^^^^^^^^^^^^ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - LEDs ^^^^ The LM4F120 has a single RGB LED. If CONFIG_ARCH_LEDS is defined, then diff --git a/configs/lm4f120-launchpad/include/board.h b/configs/lm4f120-launchpad/include/board.h index 0009ba764ba2b652c167c8130bf04fbd076dd21f..32f21ccad123eda394232a1f7b6db07143d84a08 100644 --- a/configs/lm4f120-launchpad/include/board.h +++ b/configs/lm4f120-launchpad/include/board.h @@ -184,23 +184,4 @@ #define GPIO_UART1_RX GPIO_UART1_RX_1 #define GPIO_UART1_TX GPIO_UART1_TX_1 -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Name: tiva_boardinitialize - * - * Description: - * All Stellaris architectures must provide the following entry point. This entry - * point is called early in the intitialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void tiva_boardinitialize(void); - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_LM4F120_LAUNCHPAD_INCLUDE_BOARD_H */ diff --git a/configs/lpc4330-xplorer/README.txt b/configs/lpc4330-xplorer/README.txt index 83b318ddfd82cf409527ef9b8e956b7221529be9..7477f8e40eb65c6dc9cdf134434718137ca1c06b 100644 --- a/configs/lpc4330-xplorer/README.txt +++ b/configs/lpc4330-xplorer/README.txt @@ -9,9 +9,6 @@ Contents - LPC4330-Xplorer development board - Status - - Development Environment - - GNU Toolchain Options - - IDEs - Code Red IDE/Tools Booting the LPCLink Using GDB @@ -19,9 +16,6 @@ Contents Command Line Flash Programming Executing from SPIFI USB DFU Booting - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - Serial Console - FPU - LPC4330-Xplorer Configuration Options @@ -123,140 +117,6 @@ Status STM32 Ethernet and, as a result, it should be possible to leverage the STM32 Ethernet driver with a little more effort. -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -===================== - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The Code Red GNU toolchain, - 2. The CodeSourcery GNU toolchain, - 3. The Atollic Toolchain, - 4. The devkitARM GNU toolchain, - 5. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the NuttX buildroot toolchain. However, - the make system is setup to default to use the devkitARM toolchain. To use - the CodeSourcery or devkitARM toolchain, you simply need add one of the - following configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODEREDW=y : Code Red "RedSuite" under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : The Atollic toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE: the Code Red, CodeSourcery (for Windows), Atollic and devkitARM toolchains - are Windows native toolchains. The CodeSourcery (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - The CodeSourcery Toolchain (2009q1) - ----------------------------------- - The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - The Atollic "Pro" and "Lite" Toolchain - -------------------------------------- - One problem that I had with the Atollic toolchains is that the provide a gcc.exe - and g++.exe in the same bin/ file as their ARM binaries. If the Atollic bin/ path - appears in your PATH variable before /usr/bin, then you will get the wrong gcc - when you try to build host executables. This will cause to strange, uninterpretable - errors build some host binaries in tools/ when you first make. - - Also, the Atollic toolchains are the only toolchains that have built-in support for - the FPU in these configurations. If you plan to use the Cortex-M4 FPU, you will - need to use the Atollic toolchain for now. See the FPU section below for more - information. - - The Atollic "Lite" Toolchain - ---------------------------- - The free, "Lite" version of the Atollic toolchain does not support C++ nor - does it support ar, nm, objdump, or objdcopy. If you use the Atollic "Lite" - toolchain, you will have to set: - - CONFIG_HAVE_CXX=n - - In order to compile successfully. Otherwise, you will get errors like: - - "C++ Compiler only available in TrueSTUDIO Professional" - - The make may then fail in some of the post link processing because of some of - the other missing tools. The Make.defs file replaces the ar and nm with - the default system x86 tool versions and these seem to work okay. Disable all - of the following to avoid using objcopy: - - CONFIG_RRLOAD_BINARY=n - CONFIG_INTELHEX_BINARY=n - CONFIG_MOTOROLA_SREC=n - CONFIG_RAW_BINARY=n - - devkitARM - --------- - The devkitARM toolchain includes a version of MSYS make. Make sure that the - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project . - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lpc43xx, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/common/up_vectors.S. - Code Red IDE/Tools ^^^^^^^^^^^^^^^^^^ @@ -450,101 +310,6 @@ Code Red IDE/Tools To be provided. -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpc4330-xplorer/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you - are building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - Serial Console ============== diff --git a/configs/lpc4330-xplorer/include/board.h b/configs/lpc4330-xplorer/include/board.h index 0a7c7d5f8c5f3d5c3543566f951e2afe2c0acd2a..48b6c4da3386f65f74d69338c759da36834ef638 100644 --- a/configs/lpc4330-xplorer/include/board.h +++ b/configs/lpc4330-xplorer/include/board.h @@ -316,45 +316,4 @@ #define GPIO_ENET_RESET (GPIO_MODE_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN4) #define PINCONF_ENET_MDC PINCONF_ENET_MDC_3 -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: lpc43_boardinitialize - * - * Description: - * All LPC43xx architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ****************************************************************************/ - -void lpc43_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/lpc4330-xplorer/src/lpc43_buttons.c b/configs/lpc4330-xplorer/src/lpc43_buttons.c index 9e09ce07dc0a5fdce70203d66a1a79496034aacc..4d44c59921271267fd7d187410f00d9ddea54893 100644 --- a/configs/lpc4330-xplorer/src/lpc43_buttons.c +++ b/configs/lpc4330-xplorer/src/lpc43_buttons.c @@ -63,7 +63,7 @@ * by the BUTTON_* definitions in board.h */ -static const uint16_t g_buttoncfg[BOARD_NUM_BUTTONS] = +static const uint16_t g_buttoncfg[NUM_BUTTONS] = { LPC4330_XPLORER_BUT1 }; @@ -73,7 +73,7 @@ static const uint16_t g_buttoncfg[BOARD_NUM_BUTTONS] = * numbers. */ -static uint8_t g_buttonirq[BOARD_NUM_BUTTONS] = +static uint8_t g_buttonirq[NUM_BUTTONS] = { LPC4330_XPLORER_BUT1_IRQ }; @@ -104,7 +104,7 @@ void board_button_initialize(void) /* Configure the GPIO pins as interrupting inputs. */ - for (i = 0; i < BOARD_NUM_BUTTONS; i++) + for (i = 0; i < NUM_BUTTONS; i++) { lpc43_configgpio(g_buttoncfg[i]); } @@ -133,7 +133,7 @@ uint32_t board_buttons(void) /* Check that state of each key */ - for (i = 0; i < BOARD_NUM_BUTTONS; i++) + for (i = 0; i < NUM_BUTTONS; i++) { /* A LOW value means that the key is pressed. */ @@ -178,7 +178,7 @@ int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) /* Verify that the button ID is within range */ - if ((unsigned)id < BOARD_NUM_BUTTONS) + if ((unsigned)id < NUM_BUTTONS) { /* Disable interrupts until we are done */ diff --git a/configs/lpc4337-ws/README.txt b/configs/lpc4337-ws/README.txt index 6f408249813f75589b1abc05804ff27ebf72a26e..e55ccf876d5387802580535820b58841de45f089 100644 --- a/configs/lpc4337-ws/README.txt +++ b/configs/lpc4337-ws/README.txt @@ -10,9 +10,6 @@ Contents - LPC4337-ws development board - Status - - Development Environment - - GNU Toolchain Options - - IDEs - Code Red IDE/Tools Booting the LPCLink Using GDB @@ -20,9 +17,6 @@ Contents Command Line Flash Programming Executing from SPIFI USB DFU Booting - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - LED and Pushbuttons - Serial Console - FPU @@ -119,140 +113,6 @@ Status STM32 Ethernet and, as a result, it should be possible to leverage the STM32 Ethernet driver with a little more effort. -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -===================== - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The Code Red GNU toolchain, - 2. The CodeSourcery GNU toolchain, - 3. The Atollic Toolchain, - 4. The devkitARM GNU toolchain, - 5. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the NuttX buildroot toolchain. However, - the make system is setup to default to use the devkitARM toolchain. To use - the CodeSourcery or devkitARM toolchain, you simply need add one of the - following configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODEREDW=y : Code Red "RedSuite" under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : The Atollic toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE: the Code Red, CodeSourcery (for Windows), Atollic and devkitARM toolchains - are Windows native toolchains. The CodeSourcery (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - The CodeSourcery Toolchain (2009q1) - ----------------------------------- - The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - The Atollic "Pro" and "Lite" Toolchain - -------------------------------------- - One problem that I had with the Atollic toolchains is that the provide a gcc.exe - and g++.exe in the same bin/ file as their ARM binaries. If the Atollic bin/ path - appears in your PATH variable before /usr/bin, then you will get the wrong gcc - when you try to build host executables. This will cause to strange, uninterpretable - errors build some host binaries in tools/ when you first make. - - Also, the Atollic toolchains are the only toolchains that have built-in support for - the FPU in these configurations. If you plan to use the Cortex-M4 FPU, you will - need to use the Atollic toolchain for now. See the FPU section below for more - information. - - The Atollic "Lite" Toolchain - ---------------------------- - The free, "Lite" version of the Atollic toolchain does not support C++ nor - does it support ar, nm, objdump, or objdcopy. If you use the Atollic "Lite" - toolchain, you will have to set: - - CONFIG_HAVE_CXX=n - - In order to compile successfully. Otherwise, you will get errors like: - - "C++ Compiler only available in TrueSTUDIO Professional" - - The make may then fail in some of the post link processing because of some of - the other missing tools. The Make.defs file replaces the ar and nm with - the default system x86 tool versions and these seem to work okay. Disable all - of the following to avoid using objcopy: - - CONFIG_RRLOAD_BINARY=n - CONFIG_INTELHEX_BINARY=n - CONFIG_MOTOROLA_SREC=n - CONFIG_RAW_BINARY=n - - devkitARM - --------- - The devkitARM toolchain includes a version of MSYS make. Make sure that the - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project . - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lpc43xx, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/common/up_vectors.S. - Code Red IDE/Tools ^^^^^^^^^^^^^^^^^^ @@ -446,101 +306,6 @@ Code Red IDE/Tools To be provided. -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh LPC4337-ws/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you - are building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - LED and Pushbuttons =================== diff --git a/configs/lpc4337-ws/include/board.h b/configs/lpc4337-ws/include/board.h index 0fe485ad71e4d011841d7f9c7a688273010ab479..1ed43aaa145c290bf3d1d1af33333e87a90e3284 100644 --- a/configs/lpc4337-ws/include/board.h +++ b/configs/lpc4337-ws/include/board.h @@ -317,46 +317,4 @@ #define PINCONF_SSP1_MOSI PINCONF_SSP1_MOSI_1 #define PINCONF_SSP1_SCK PINCONF_SSP1_SCK_2 -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: lpc43_boardinitialize - * - * Description: - * All LPC43xx architectures must provide the following entry point. This - * entry point is called early in the intitialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void lpc43_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_LPC4337_WS_INCLUDE_BOARD_H */ diff --git a/configs/lpc4357-evb/README.txt b/configs/lpc4357-evb/README.txt index d08fe5f10574b9555d526405e92c02c1af87696c..0b1a7cbce637493df6edf8ce6ad9b7c4b4020d15 100644 --- a/configs/lpc4357-evb/README.txt +++ b/configs/lpc4357-evb/README.txt @@ -10,9 +10,6 @@ Contents - LPC4357-EVB development board - Status - - Development Environment - - GNU Toolchain Options - - IDEs - Code Red IDE/Tools Booting the LPCLink Using GDB @@ -20,9 +17,6 @@ Contents Command Line Flash Programming Executing from SPIFI USB DFU Booting - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - LED and Pushbuttons - Serial Console - FPU @@ -116,140 +110,6 @@ Status STM32 Ethernet and, as a result, it should be possible to leverage the STM32 Ethernet driver with a little more effort. -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -===================== - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The Code Red GNU toolchain, - 2. The CodeSourcery GNU toolchain, - 3. The Atollic Toolchain, - 4. The devkitARM GNU toolchain, - 5. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the NuttX buildroot toolchain. However, - the make system is setup to default to use the devkitARM toolchain. To use - the CodeSourcery or devkitARM toolchain, you simply need add one of the - following configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODEREDW=y : Code Red "RedSuite" under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : The Atollic toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE: the Code Red, CodeSourcery (for Windows), Atollic and devkitARM toolchains - are Windows native toolchains. The CodeSourcery (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - The CodeSourcery Toolchain (2009q1) - ----------------------------------- - The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - The Atollic "Pro" and "Lite" Toolchain - -------------------------------------- - One problem that I had with the Atollic toolchains is that the provide a gcc.exe - and g++.exe in the same bin/ file as their ARM binaries. If the Atollic bin/ path - appears in your PATH variable before /usr/bin, then you will get the wrong gcc - when you try to build host executables. This will cause to strange, uninterpretable - errors build some host binaries in tools/ when you first make. - - Also, the Atollic toolchains are the only toolchains that have built-in support for - the FPU in these configurations. If you plan to use the Cortex-M4 FPU, you will - need to use the Atollic toolchain for now. See the FPU section below for more - information. - - The Atollic "Lite" Toolchain - ---------------------------- - The free, "Lite" version of the Atollic toolchain does not support C++ nor - does it support ar, nm, objdump, or objdcopy. If you use the Atollic "Lite" - toolchain, you will have to set: - - CONFIG_HAVE_CXX=n - - In order to compile successfully. Otherwise, you will get errors like: - - "C++ Compiler only available in TrueSTUDIO Professional" - - The make may then fail in some of the post link processing because of some of - the other missing tools. The Make.defs file replaces the ar and nm with - the default system x86 tool versions and these seem to work okay. Disable all - of the following to avoid using objcopy: - - CONFIG_RRLOAD_BINARY=n - CONFIG_INTELHEX_BINARY=n - CONFIG_MOTOROLA_SREC=n - CONFIG_RAW_BINARY=n - - devkitARM - --------- - The devkitARM toolchain includes a version of MSYS make. Make sure that the - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project . - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lpc43xx, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/common/up_vectors.S. - Code Red IDE/Tools ^^^^^^^^^^^^^^^^^^ @@ -443,101 +303,6 @@ Code Red IDE/Tools To be provided. -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpc4357-xplorer/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you - are building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - LED and Pushbuttons =================== diff --git a/configs/lpc4357-evb/include/board.h b/configs/lpc4357-evb/include/board.h index 91f0e458b4bd287188f5b574729011384dd11dbf..7cd280e419d072f8f67a2b8c936edc4757b94007 100644 --- a/configs/lpc4357-evb/include/board.h +++ b/configs/lpc4357-evb/include/board.h @@ -286,45 +286,4 @@ #define PINCONF_U3_RXD PINCONF_U3_RXD_4 #define PINCONF_U3_DIR PINCONF_U3_DIR_3 -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: lpc43_boardinitialize - * - * Description: - * All LPC43xx architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ****************************************************************************/ - -void lpc43_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* _CONFIGS_LPC4357_EVB_INCLUDE_BOARD_H */ diff --git a/configs/lpc4357-evb/src/lpc43_buttons.c b/configs/lpc4357-evb/src/lpc43_buttons.c index 2ed5097495924df09210ea31bab736d276545514..ab82b449e001f892a66a6fbbd1bc9ef61fa8333f 100644 --- a/configs/lpc4357-evb/src/lpc43_buttons.c +++ b/configs/lpc4357-evb/src/lpc43_buttons.c @@ -65,7 +65,7 @@ */ #if 0 /* Not yet used */ -static const uint16_t g_buttoncfg[BOARD_NUM_BUTTONS] = +static const uint16_t g_buttoncfg[NUM_BUTTONS] = { }; @@ -74,7 +74,7 @@ static const uint16_t g_buttoncfg[BOARD_NUM_BUTTONS] = * numbers. */ -static uint8_t g_buttonirq[BOARD_NUM_BUTTONS] = +static uint8_t g_buttonirq[NUM_BUTTONS] = { }; #endif @@ -106,7 +106,7 @@ void board_button_initialize(void) /* Configure the GPIO pins as interrupting inputs. */ - for (i = 0; i < BOARD_NUM_BUTTONS; i++) + for (i = 0; i < NUM_BUTTONS; i++) { lpc43_configgpio(g_buttoncfg[i]); } @@ -137,7 +137,7 @@ uint32_t board_buttons(void) /* Check that state of each key */ - for (i = 0; i < BOARD_NUM_BUTTONS; i++) + for (i = 0; i < NUM_BUTTONS; i++) { /* A LOW value means that the key is pressed. */ @@ -187,7 +187,7 @@ int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) /* Verify that the button ID is within range */ - if ((unsigned)id < BOARD_NUM_BUTTONS) + if ((unsigned)id < NUM_BUTTONS) { /* Disable interrupts until we are done */ diff --git a/configs/lpc4370-link2/README.txt b/configs/lpc4370-link2/README.txt index 1f0c4092c143c452566b13c2082cd24d60815312..573ed26d254d3307139b9d668e2ab7ab15dfd7ca 100644 --- a/configs/lpc4370-link2/README.txt +++ b/configs/lpc4370-link2/README.txt @@ -10,9 +10,6 @@ Contents - LPC4370-Link2 development board - Status - - Development Environment - - GNU Toolchain Options - - IDEs - Code Red IDE/Tools Booting the LPCLink Using GDB @@ -20,9 +17,6 @@ Contents Command Line Flash Programming Executing from SPIFI USB DFU Booting - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - LED and Pushbuttons - Serial Console - FPU @@ -119,140 +113,6 @@ Status STM32 Ethernet and, as a result, it should be possible to leverage the STM32 Ethernet driver with a little more effort. -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -===================== - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The Code Red GNU toolchain, - 2. The CodeSourcery GNU toolchain, - 3. The Atollic Toolchain, - 4. The devkitARM GNU toolchain, - 5. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the NuttX buildroot toolchain. However, - the make system is setup to default to use the devkitARM toolchain. To use - the CodeSourcery or devkitARM toolchain, you simply need add one of the - following configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODEREDW=y : Code Red "RedSuite" under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : The Atollic toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE: the Code Red, CodeSourcery (for Windows), Atollic and devkitARM toolchains - are Windows native toolchains. The CodeSourcery (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - The CodeSourcery Toolchain (2009q1) - ----------------------------------- - The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - The Atollic "Pro" and "Lite" Toolchain - -------------------------------------- - One problem that I had with the Atollic toolchains is that the provide a gcc.exe - and g++.exe in the same bin/ file as their ARM binaries. If the Atollic bin/ path - appears in your PATH variable before /usr/bin, then you will get the wrong gcc - when you try to build host executables. This will cause to strange, uninterpretable - errors build some host binaries in tools/ when you first make. - - Also, the Atollic toolchains are the only toolchains that have built-in support for - the FPU in these configurations. If you plan to use the Cortex-M4 FPU, you will - need to use the Atollic toolchain for now. See the FPU section below for more - information. - - The Atollic "Lite" Toolchain - ---------------------------- - The free, "Lite" version of the Atollic toolchain does not support C++ nor - does it support ar, nm, objdump, or objdcopy. If you use the Atollic "Lite" - toolchain, you will have to set: - - CONFIG_HAVE_CXX=n - - In order to compile successfully. Otherwise, you will get errors like: - - "C++ Compiler only available in TrueSTUDIO Professional" - - The make may then fail in some of the post link processing because of some of - the other missing tools. The Make.defs file replaces the ar and nm with - the default system x86 tool versions and these seem to work okay. Disable all - of the following to avoid using objcopy: - - CONFIG_RRLOAD_BINARY=n - CONFIG_INTELHEX_BINARY=n - CONFIG_MOTOROLA_SREC=n - CONFIG_RAW_BINARY=n - - devkitARM - --------- - The devkitARM toolchain includes a version of MSYS make. Make sure that the - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project . - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lpc43xx, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/common/up_vectors.S. - Code Red IDE/Tools ^^^^^^^^^^^^^^^^^^ @@ -446,101 +306,6 @@ Code Red IDE/Tools To be provided. -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh LPC4370-xplorer/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you - are building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - LED and Pushbuttons =================== diff --git a/configs/lpc4370-link2/include/board.h b/configs/lpc4370-link2/include/board.h index c53a1fb7b6654aa5c8c9d6801ff3eba6c2627001..3492fd308ffcbfa03ef4c1c22d61a66dd7191d86 100644 --- a/configs/lpc4370-link2/include/board.h +++ b/configs/lpc4370-link2/include/board.h @@ -320,46 +320,4 @@ #define PINCONF_SSP1_SCK PINCONF_SSP1_SCK_1 #define PINCONF_SSP1_SSEL PINCONF_SSP1_SSEL_1 -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: lpc43_boardinitialize - * - * Description: - * All LPC43xx architectures must provide the following entry point. This - * entry point is called early in the intitialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void lpc43_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_LPC4357_LINK2_INCLUDE_BOARD_H */ diff --git a/configs/lpcxpresso-lpc1115/README.txt b/configs/lpcxpresso-lpc1115/README.txt index 41fae32e0ed7ee231eefa0df5ba257bc05c6d3c6..7780bb9ec73e3cee76752e97f7e470193ebe2738 100644 --- a/configs/lpcxpresso-lpc1115/README.txt +++ b/configs/lpcxpresso-lpc1115/README.txt @@ -8,11 +8,6 @@ Contents ^^^^^^^^ LCPXpresso LPC1115 Board - Development Environment - GNU Toolchain Options - NuttX EABI "buildroot" Toolchain - NuttX OABI "buildroot" Toolchain - NXFLAT Toolchain Code Red IDE Using OpenOCD LEDs @@ -60,71 +55,6 @@ LCPXpresso LPC1115 Board P3[25]/MAT0.0/PWM1.2 PAD13 P3[26]/STCLK/MAT0.1/PWM1.3 PAD14 -Development Environment -^^^^^^^^^^^^^^^^^^^^^^^ - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -^^^^^^^^^^^^^^^^^^^^^ - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The Code Red GNU toolchain - 2. The CodeSourcery GNU toolchain, - 3. The devkitARM GNU toolchain, - 4. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the Code Red toolchain and the - make system is setup to default to use the Code Red Linux toolchain. To use - the other toolchain, you simply need add one of the following configuration - options to your .config (or defconfig) file: - - CONFIG_ARMV6M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV6M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV6M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV6M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - CONFIG_ARMV6M_TOOLCHAIN_CODEREDW=n : Code Red toolchain under Windows - CONFIG_ARMV6M_TOOLCHAIN_CODEREDL=y : Code Red toolchain under Linux - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE: the CodeSourcery (for Windows), devkitARM, and Code Red (for Windoes) - are Windows native toolchains. The CodeSourcey (for Linux), Code Red (for Linux) - and NuttX buildroot toolchains are Cygwin and/or Linux native toolchains. There - are several limitations to using a Windows based toolchain in a Cygwin - environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - Code Red IDE ^^^^^^^^^^^^ @@ -231,101 +161,6 @@ Code Red IDE All of the above steps are automated in the bash script flash.sh that can be found in the configs/lpcxpresso/tools directory. -NuttX EABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M0 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/nuttx/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1115/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm0-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you - are building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv6-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -^^^^^^^^^^^^^^^^ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1115/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm0-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - Using OpenOCD ^^^^^^^^^^^^^ diff --git a/configs/lpcxpresso-lpc1115/include/board.h b/configs/lpcxpresso-lpc1115/include/board.h index f4aae460f29544cb1a3542294b03c78e0fcfc408..338a405632ef8089acde5fd9c1040a2e14359ddb 100644 --- a/configs/lpcxpresso-lpc1115/include/board.h +++ b/configs/lpcxpresso-lpc1115/include/board.h @@ -203,44 +203,4 @@ * P3[26]/STCLK/MAT0.1/PWM1.3 PAD14 N/A */ -/************************************************************************************ - * Public Types - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: lpc11_boardinitialize - * - * Description: - * All LPC11xx architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void lpc11_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_LPCXPRESSO_LPC1115_INCLUDE_BOARD_H */ diff --git a/configs/lpcxpresso-lpc1768/README.txt b/configs/lpcxpresso-lpc1768/README.txt index 05e8a7504e0cec1379802411f53e8258a97739f2..319ad11a13300204f7f6910ed0764188ce4d8bc2 100644 --- a/configs/lpcxpresso-lpc1768/README.txt +++ b/configs/lpcxpresso-lpc1768/README.txt @@ -9,11 +9,6 @@ Contents LCPXpresso LPC1768 Board Embedded Artist's Base Board - Development Environment - GNU Toolchain Options - NuttX EABI "buildroot" Toolchain - NuttX OABI "buildroot" Toolchain - NXFLAT Toolchain Code Red IDE LEDs LPCXpresso Configuration Options @@ -227,71 +222,6 @@ USB Device P0.9/I2STX-SDA/MOSI1/MAT2.3 | 5 | PIO0_9-MOSI OLED data in (D1) ----------------------------+-------+-------------- ---------------------------------------- -Development Environment -^^^^^^^^^^^^^^^^^^^^^^^ - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -^^^^^^^^^^^^^^^^^^^^^ - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The Code Red GNU toolchain - 2. The CodeSourcery GNU toolchain, - 3. The devkitARM GNU toolchain, - 4. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the Code Red toolchain and the - make system is setup to default to use the Code Red Linux toolchain. To use - the other toolchain, you simply need add one of the following configuration - options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - CONFIG_ARMV7M_TOOLCHAIN_CODEREDW=n : Code Red toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODEREDL=y : Code Red toolchain under Linux - - You may also have to modify the PATH environment variable if your make cannot - find the tools. - - NOTE: the CodeSourcery (for Windows), devkitARM, and Code Red (for Windoes) - are Windows native toolchains. The CodeSourcey (for Linux), Code Red (for Linux) - and NuttX buildroot toolchains are Cygwin and/or Linux native toolchains. There - are several limitations to using a Windows based toolchain in a Cygwin - environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - Code Red IDE ^^^^^^^^^^^^ @@ -395,101 +325,6 @@ Code Red IDE All of the above steps are automated in the bash script flash.sh that can be found in the configs/lpcxpresso/tools directory. -NuttX EABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/nuttx/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you - are building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -^^^^^^^^^^^^^^^^ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - LEDs ^^^^ diff --git a/configs/lpcxpresso-lpc1768/include/board.h b/configs/lpcxpresso-lpc1768/include/board.h index d8f9221d840151c6bf68be6c8fc693b00bff368e..6fa06314c45af27a876653de4b3f0f3da99806c9 100644 --- a/configs/lpcxpresso-lpc1768/include/board.h +++ b/configs/lpcxpresso-lpc1768/include/board.h @@ -248,43 +248,4 @@ * P4[29]/TX-MCLK/MAT2.1/RXD3 PAD16 N/A */ -/************************************************************************************ - * Public Types - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: lpc17_boardinitialize - * - * Description: - * All LPC17xx architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -EXTERN void lpc17_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/lpcxpresso-lpc1768/nsh/defconfig b/configs/lpcxpresso-lpc1768/nsh/defconfig index 339716342e0e18d7eafd18a4878fe350a6fbdbc9..1c7be2c461597a6612a9a6dac03aa40718343d70 100644 --- a/configs/lpcxpresso-lpc1768/nsh/defconfig +++ b/configs/lpcxpresso-lpc1768/nsh/defconfig @@ -1,4 +1,4 @@ -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set diff --git a/configs/lpcxpresso-lpc54628/Kconfig b/configs/lpcxpresso-lpc54628/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..fba3ae0dc149e815e2546fdeb85a2dc885729123 --- /dev/null +++ b/configs/lpcxpresso-lpc54628/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_LPCXPRESSO +endif diff --git a/configs/lpcxpresso-lpc54628/README.txt b/configs/lpcxpresso-lpc54628/README.txt new file mode 100644 index 0000000000000000000000000000000000000000..31a65ff18e3d55f91c789ca21886b39b77317bb9 --- /dev/null +++ b/configs/lpcxpresso-lpc54628/README.txt @@ -0,0 +1,480 @@ +README +====== + + This directory contains the port to the NXP LPCXpress-LPC54628 board + (OMI1309UL). This board features: + + - LPC54628 Cortex-M4 microcontroller running at up to 220MHz + - 272x480 color LCD with capacitive touch screen + - On-board, high-speed USB, Link2 debug probe with CMSIS-DAP and SEGGER + J-Link protocol options + - UART and SPI port bridging from LPC546xx target to USB via the on- + board debug probe + - Support for external debug probe + - 3 x user LEDs, plus Reset, ISP (3) and user buttons + - Multiple Expansion options, including Arduino UNO and PMod + - Built-in power consumption measurement for target LPC546xx MCU + - 128Mb Micron MT25QL128 Quad-SPI flash + - 16MB Micron MT48LC8M16A2B4 SDRAM + - Knowles SPH0641LM4H digital microphone + - Full size SD/MMC card slot + - NXP MMA8652FCR1 accelerometer + - Stereo audio codec with line in/out + - High and full speed USB ports with micro A/B connector for host or + device functionality + - 10/100Mbps Ethernet (RJ45 connector) + +STATUS +====== + + 2017-12-10: The basic NSH configuration is functional at 220MHz with a + Serial console, timer and LED support. Added support for the external + SDRAM and for the RAM test utility. + 2017-12-11: Fixed an error in board LEDs. Added framework for future + I2C and SPI flexcomm drivers. + 2017-12-12: The SDRAM is now functional and passes the complete RAM + test. Added configuration options and logic to add none, portions, or + all of the external SDRAM to the system heap. Brought in the LPC1788 + LCD driver. The LPC1788 LCD registers are identical to the LPC54xx + (other than a minor clock source setting). + 2017-12-13: Created the fb configuration for testing the LCD. + 2017-12-14: Corrected a misconception about how the video data lines + were configured. The LCD now appears to be fully functional. + 2017-12-15: Added an I2C driver. + 2017-12-16: Added support for LPC54xx GPIO interrupts; added button + support (with interrupts) to the NSH configuration. The button + test appears to functional functional. There are noticeable delays + in receiving the button events, especially when the button is + released. But if you do not press the buttons too quickly all events + are processed. This, I suspect, is a consequence of the strong glitch + filtering that is enabled in the pin configuration. Snappier + response my be obtainable with filtering off. + 2017-12-17: Added a driver for the FT5x06 capacitive, multi-touch + controller. Add support logic for the LPCXpresso-LPC54528 to + initialize and the register the FT5x06 driver. Unfortunately, the + FT5x06 interrupt is on pin P4.0 but pin interrupts are only supported + on P0.m and P1.m, m=0..31. + 2017-12-18: Added an option to the FT5x06 driver to support a timer- + based poll instead of interrupts. This is very inefficient in that it + will introduce delays in touchscreen response and will consume more CPU + bandwidth. The driver appears to be functional. Added the NxWM + configuration to do some integrated testing. NxWM seems to be fully + functional. However, the action of the touchscreen could use some + human factors improvements. I imagine that this is a consequence of + the polled solution. + 2017-12-19: Brought in Alan Carvalho de Assis' LPC43xx SD/MMC driver from + https://github.com/Smoothieware/smoothie-nuttx/tree/master/nuttx/arch/arm/src/lpc43xx + and adapted it for use by the LPC54xx. Unverified as of this writing. + 2017-12-21: Some things are working with he SDMMC drivers but read DMAs + are non-functional and, hence not usable. + 2017-12-23: SDMMC is still non-functional. The first DMA read of 512 bytes + fails with a CRC error. Similar result if clock is reduced, if 1-bit bus + is used, if DMA is disabled., if DEBUG output is disabled. + 2017-12-24: Added basic DMA support; brought in the WWDT driver from the + LPC43 which has the same peripheral. Neither tested; almost certainly + non-functional without some additional investment. + 2017-12-25: Added an RTC driver. It appears to be functional but has not + been well tested. + 2017-12-26: Added an RNG driver. The RNG is actually controlled by a ROM + function. This driver seems to work fine when single stepping. However, + if I collect samples indefinitely, I get a reserved interrupt. The symptom + before the crash is that local variables are getting corrupted after the + call into ROM. Increasing the stack size does not seem to help. Perhaps + to use the ROM at high frequencies it may be necessary to modify the ROM + access timing in some way??? + 2017-12-30: Completed implementation of an Ethernet driver. Untested as + of this writing. Also added the netnsh configuration will, eventually, + be used to test the Ethernet driver. + 2018-01-01: There Ethernet driver appears to be fully functional although + more testing is certainly needed. I believe that there is a memory + corruption issue in the current configuration that cause problems + occasionally. For example, after a longer Telnet session, I sometimes + see the following DEBUGASSERT after exiting the session from the host: + + up_assert: Assertion failed at file:mm_heap/mm_free.c line: 129 + + which is a clear indication heap corruption. Increasing the size of some + stacks might correct this problem, but I have not yet experimented with + that. I have not seen the problem in any other context. + + There is still no support for the Accelerometer, SPIFI, or USB. There is a + complete but not-yet-functional SD card. There is a partial SPI driver, + but no on-board SPI devices to test it. + +Configurations +============== + + Information Common to All Configurations + ---------------------------------------- + Each LPCXpresso-LPC54628 configuration is maintained in a sub-directory + and can be selected as follow: + + .tools/configure.sh [OPTIONS] lpcxpresso-lpc54628/ + + See '.tools/configure.sh -h' for a list of all options. The most typical + are -l to select the Linux host or -c to select the Windows Cygwin host. + + Before starting the build, make sure that your PATH environment variable + includes the correct path to your toolchain. + + And then build NuttX by simply typing the following. At the conclusion of + the make, the nuttx binary will reside in an ELF file called, simply, nuttx. + + make + + The that is provided above as an argument to the tools/configure.sh + must be is one of the following. + + NOTES: + + 1. These configurations use the mconf-based configuration tool. To + change any of these configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Unless stated otherwise, all configurations generate console + output on USART0 (aka Flexcomm0). USART0 connects to the serial + bridge on LPC4322JET100 and should be available as a USB serial + device on your host PC. + + 3. All of these configurations are set up to build under Windows using + the "GNU Tools for ARM Embedded Processors" that is maintained by + ARM (unless stated otherwise in the description of the configuration). + + https://developer.arm.com/open-source/gnu-toolchain/gnu-rm + + That toolchain selection can easily be reconfigured using + 'make menuconfig'. Here are the relevant current settings: + + Build Setup: + CONFIG_HOST_WINDOWS=y : Window environment + CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows + + System Type -> Toolchain: + CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain + + Configuration sub-directories + ----------------------------- + + fb: + + A simple NSH configuration used for some basic debug of LCD using the + framebuffer character drivers. This configuration provides the test + programs: + + - apps/examples/pdcurses, and + - apps/examples/fb + + as NSH built-in applications. + + NOTES: + 1. This configuration enables SDRAM to hold the LCD framebuffer and + enables the LPC54xx LCD driver in order to support the LPCXpresso's + TFT panel. In this configuration, the framebuffer resides in the + the lower half megabyte of SDRAM beginning at address 0xa0000000 + The remainder of the SDRAM from 0xa0080000 up to 0xa1000000 is added + to the heap. + + The is wasteful of SDRAM: Only 261,120 bytes actually used for the + framebuffer. This memory could be reclaimed by changing the DRAM + CS0 offset value in the .config file. + + 2. Some of the pdcurses test rely on some positional input device and so + is not yet usable. Others work fine with no user include: charset, + xmas, firework, worms, rain, for examples. + + 3. I2C2 is enabled (will be used with the capacitive touchscreen). In + order to verify I2C functionality, the I2C tool at apps/system/i2ctool + is enabled in this configuration. + + nsh> i2c dev -b 2 3 77 + 0 1 2 3 4 5 6 7 8 9 a b c d e f + 00: -- -- -- -- -- -- -- -- -- -- -- -- -- + 10: -- -- -- -- -- -- -- -- -- -- 1a -- -- 1d -- -- + 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 30: -- -- -- -- -- -- -- -- 38 -- -- -- -- -- -- -- + 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 70: -- -- -- -- -- -- -- -- + + Codec I2C address: 0x1a + Accel I2C address: 0x1d + Touch panel I2C address: 0x38 + + 4. The touchscreen test program at apps/examples/touchscreen is also + included in this configuration. + + nsh> tc 5 + tc_main: nsamples: 2 + tc_main: Initializing external touchscreen device + tc_main: Opening /dev/input0 + Sample : + npoints : 1 + Point 1 : + id : 0 + flags : 1a + x : 230 + y : 84 + h : 0 + w : 0 + pressure : 0 + etc. + + NOTE that the touchscreen controlled must run in a polled mode! The + FT5x06 interrupt GPIO is on P4.0 and, as far as I know, GPIO + interrupts are not supported on P4. So polled mode only for this + puppy. + + netnsh: + ------ + This is a special version of the NuttShell (nsh) configuration that is + tailored for network testing. This version derives from nsh + configuration so many of the notes there apply here except as noted + below. + + NOTES: + + 1. Networking is enabled. The LPCXpressio-LPC54628 has an SMC _LAN8720 PHY + and RJ45 network connector. Support is enabled for IPv4, IPv6, TCP/IP, + UDP, ICMP, ICMPv6, and ARP. + + The default IP addresses are 10.0.0.2 (IPv4) and fc00::2 (IPv6). You + should reconfigure these as appropriate for your test network. + + 2. SD card and I2C support are not enabled. The I2C tool application is + not enabled + + 3. SDRAM support is enabled and the SDRAM is added to the system heap. + The ramtest application is not enabled. + + 4. This configuration does not include support for asynchronous network + initialization. As a consequence, NSH must bring up the network + before you get the NSH prompt. If the network cable is unplugged, + this can mean a significant delay before you see the prompt. + + 5. In this configuration, the network the network and the Telnet + daemon are available by the time that the NSH prompt is presented. + + Telnet defaults to IPv6 so to use it from the host PS, you would have + to do: + + $ telnet fc00::42 + + + nsh: + + Configures the NuttShell (nsh) application located at examples/nsh. + This configuration was used to bring up the board support and, hence, + is focused on low level, command-line driver testing. It has no + network and no graphics capability. + + NOTES: + + 1. NSH built-in applications are supported. + + Binary Formats: + CONFIG_BUILTIN=y : Enable support for built-in programs + + Application Configuration: + CONFIG_NSH_BUILTIN_APPS=y : Enable starting apps from NSH command line + + 2. SDRAM support is enabled, but the SDRAM is *not* added to the system + heap. The apps/system/ramtest utility is include in the build as an + NSH builtin function that can be used to verify the SDRAM. + + nsh> ramtest -h + RAMTest: Missing required arguments + + Usage: [-w|h|b] + + Where: + starting address of the test. + number of memory locations (in bytes). + -w Sets the width of a memory location to 32-bits. + -h Sets the width of a memory location to 16-bits (default). + -b Sets the width of a memory location to 8-bits. + + The MTL48LC8M16A2B4-6A SDRAM is on CS0 which corresponds to address + 0xa0000000, the size of the memory is 128Mbits or 16Mb. So the DRAM + may be tested with this command: + + NuttShell (NSH) NuttX-7.23 + nsh> ramtest a0000000 16777216 + RAMTest: Marching ones: a0000000 16777216 + RAMTest: Marching zeroes: a0000000 16777216 + RAMTest: Pattern test: a0000000 16777216 55555555 aaaaaaaa + RAMTest: Pattern test: a0000000 16777216 66666666 99999999 + RAMTest: Pattern test: a0000000 16777216 33333333 cccccccc + RAMTest: Address-in-address test: a0000000 16777216 + nsh> + + 3. I2C2 is enabled (will be used with the capacitive touchscreen). In + order to verify I2C functionality, the I2C tool at apps/system/i2ctool + is enabled in this configuration. + + nsh> i2c bus + BUS EXISTS? + Bus 0: NO + Bus 1: NO + Bus 2: YES + Bus 3: NO + Bus 4: NO + Bus 5: NO + Bus 6: NO + Bus 7: NO + Bus 8: NO + Bus 9: NO + nsh> i2c dev -b 2 3 77 + 0 1 2 3 4 5 6 7 8 9 a b c d e f + 00: -- -- -- -- -- -- -- -- -- -- -- -- -- + 10: -- -- -- -- -- -- -- -- -- -- 1a -- -- 1d -- -- + 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + 70: -- -- -- -- -- -- -- -- + + I believe that the on-board Accelerometer, Audio Codec, and touch + panel controller should have been detected (but perhaps the touch + panel is not powered in this configuration since the LCD is not + configured?) + + Codec I2C address: 0x1a + Accel I2C address: 0x1d + Touch panel I2C address: 0x38 + + 4. Support for the on-board USER button is included as well as the + button test program at apps/examples/buttons. This test is useful + for verifying the functionality of GPIO interrupts. + + NuttShell (NSH) NuttX-7.23 + nsh> buttons + buttons_main: Starting the button_daemon + buttons_main: button_daemon started + button_daemon: Running + button_daemon: Opening /dev/buttons + button_daemon: Supported BUTTONs 0x01 + nsh> Sample = 1 + Sample = 0 + Sample = 1 + Sample = 0 + Sample = 1 + Sample = 0 + Sample = 1 + etc. + + There are noticeable delays in receiving the button events, + especially when the button is released. But if you do not press the + buttons too quickly all events are processed. This, I suspect, is a + consequence of the strong glitch filtering that is enabled in the pin + configuration. Snappier response my be obtainable with filtering off + if desired. + + 5. This configuration has been used for testing the SDMMC driver with + these configuration additions: + + CONFIG_EXPERIMENTAL=y + + CONFIG_LPC54_SDMMC=y + CONFIG_LPC54_SDMMC_PWRCTRL=y + CONFIG_LPC54_SDMMC_DMA=y + + CONFIG_SIG_SIGWORK=17 + CONFIG_SCHED_WORKQUEUE=y + CONFIG_SCHED_HPWORK=y + CONFIG_SCHED_HPWORKPRIORITY=224 + CONFIG_SCHED_HPWORKPERIOD=50000 + CONFIG_SCHED_HPWORKSTACKSIZE=2048 + + CONFIG_MMCSD=y + CONFIG_MMCSD_NSLOTS=1 + CONFIG_MMCSD_MULTIBLOCK_DISABLE=y + CONFIG_MMCSD_HAVE_CARDDETECT=y + CONFIG_MMCSD_HAVE_WRITEPROTECT=y + CONFIG_ARCH_HAVE_SDIO=y + CONFIG_SDIO_DMA=y + CONFIG_MMCSD_SDIO=y + + CONFIG_NSH_MMCSDSLOTNO=0 + + 6. The RTC is enabled in this configuration. + + NuttShell (NSH) NuttX-7.23 + nsh> date + Jan 01 00:00:06 1970 + nsh> date -s "DEC 25 08:00:00 2017" + nsh> date + Dec 25 08:00:01 2017 + + After reset: + + NuttShell (NSH) NuttX-7.23 + nsh> date + Dec 25 08:00:05 2017 + + nxwm: + + This is a special configuration setup for the NxWM window manager + UnitTest. This builds on top of the features that were unit tested in + by the fb configuration. + + The NxWM window manager can be found here: + + /NxWidgets/nxwm + + The NxWM unit test can be found at: + + /NxWidgets/UnitTests/nxwm + + Documentation for installing the NxWM unit test can be found here: + + /NxWidgets/UnitTests/README.txt + + Where is whatever path you have select to install + NuttX. + + Here is the quick summary of the build steps (Assuming that all of + the required packages are available in a directory ~/): + + 1. Install the nxwm configuration + + $ cd ~//nuttx + $ tools/configure.sh [OPTIONS] lpcxpresso-lpc54628/nxwm + + Use the -l option with the configure.sh script if you are using a + Linux host; use the -c option if you are using Cygwin under Windows. + Use the -h option to see other selections. + + 2. Make the build context (only) + + $ make context + + 3. Install the nxwm unit test + + $ cd ~//NxWidgets + $ tools/install.sh ~//apps nxwm + Creating symbolic link + - To ~//NxWidgets/UnitTests/nxwm + - At ~//apps/external + + 4. Build the NxWidgets library + + $ cd ~//NxWidgets/libnxwidgets + $ make TOPDIR=~//nuttx + + 5. Build the NxWM library + + $ cd ~//NxWidgets/nxwm + $ make TOPDIR=~//nuttx + + 6. Built NuttX with the installed unit test as the application + + $ cd ~//nuttx + $ make + diff --git a/configs/lpcxpresso-lpc54628/fb/defconfig b/configs/lpcxpresso-lpc54628/fb/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..2234418cfcc7429fd86517b85c2e825919e4ef97 --- /dev/null +++ b/configs/lpcxpresso-lpc54628/fb/defconfig @@ -0,0 +1,82 @@ +# CONFIG_ARCH_FPU is not set +# CONFIG_EXAMPLES_TOUCHSCREEN_ARCHINIT is not set +CONFIG_ARCH_BOARD_LPCXPRESSO_LPC54628=y +CONFIG_ARCH_BOARD="lpcxpresso-lpc54628" +CONFIG_ARCH_CHIP_LPC54628=y +CONFIG_ARCH_CHIP_LPC54XX=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_STDARG_H=y +CONFIG_ARCH="arm" +CONFIG_BOARD_LOOPSPERMSEC=21082 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_NSH=y +CONFIG_EXAMPLES_PDCURSES=y +CONFIG_EXAMPLES_TOUCHSCREEN=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FT5X06_POLLMODE=y +CONFIG_FT5X06_SINGLEPOINT=y +CONFIG_FT5X06_SWAPXY=y +CONFIG_GRAPHICS_PDCURSES=y +CONFIG_I2CTOOL_MAXBUS=9 +CONFIG_INPUT_FT5X06=y +CONFIG_INPUT=y +CONFIG_LPC54_EMC_DYNAMIC_CS0_OFFSET=0x00080000 +CONFIG_LPC54_EMC_DYNAMIC_CS0_SIZE=0x00f80000 +CONFIG_LPC54_EMC_DYNAMIC_CS0=y +CONFIG_LPC54_EMC=y +CONFIG_LPC54_GPIOIRQ=y +CONFIG_LPC54_I2C2_MASTER=y +CONFIG_LPC54_LCD_BGR=y +CONFIG_LPC54_LCD_BPP16_565=y +CONFIG_LPC54_LCD_HBACKPORCH=43 +CONFIG_LPC54_LCD_HFRONTPORCH=8 +CONFIG_LPC54_LCD_VBACKPORCH=12 +CONFIG_LPC54_LCD_VFRONTPORCH=4 +CONFIG_LPC54_LCD_VPULSE=10 +CONFIG_LPC54_LCD_VRAMBASE=0xa0000000 +CONFIG_LPC54_LCD=y +CONFIG_LPC54_USART0=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_NXFONTS_DISABLE_1BPP=y +CONFIG_NXFONTS_DISABLE_24BPP=y +CONFIG_NXFONTS_DISABLE_2BPP=y +CONFIG_NXFONTS_DISABLE_32BPP=y +CONFIG_NXFONTS_DISABLE_4BPP=y +CONFIG_NXFONTS_DISABLE_8BPP=y +CONFIG_PDCURSES_FONT_6X9=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_RAM_SIZE=163840 +CONFIG_RAM_START=0x10000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=13 +CONFIG_START_MONTH=12 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_RAMTEST=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_VIDEO_FB=y +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/lpcxpresso-lpc54628/include/board.h b/configs/lpcxpresso-lpc54628/include/board.h new file mode 100644 index 0000000000000000000000000000000000000000..2ca923462a6649c9f3d67c2287a2bd7dca98a54f --- /dev/null +++ b/configs/lpcxpresso-lpc54628/include/board.h @@ -0,0 +1,457 @@ +/**************************************************************************** + * configs/lpcxpresso-lpc54628/include/board.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef _CONFIGS_LPCXPRESSO_LPC54628_INCLUDE_BOARD_H +#define _CONFIGS_LPCXPRESSO_LPC54628_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking ****************************************************************/ + +#undef BOARD_180MHz +#define BOARD_220MHz 1 + +/* System PLL + * + * Notation: + * Fin = the input to the PLL. + * Fout = the output of the PLL. + * Fref = the PLL reference frequency, the input to the phase frequency + * detector. + * N = optional pre-divider value. + * M = feedback divider value, which represents the multiplier for the + * PLL. + * P = optional post-divider value. An additional divide-by-2 is + * included in the post-divider path. + * + * In all variations of normal mode, the following requirements must be met: + * + * -275 MHz ≤ Fcco ≤ 550 MHz. + * 4 kHz ≤ Fin / N ≤ 25 MHz. + * + * Normal mode with optional pre-divide. In the equations, use N = 1 when + * the pre-divider is not used. The extra divide by 2 is in the feedback + * divider path: + * + * Fout = Fcco = 2 x M x Fin / N + * + * Normal mode with post-divide and optional pre-divide. In the equations, + * use N = 1 when the pre-divider is not used: + * + * Fout = Fcco / (2 x P) = M x Fin / (N x P) + */ + +#define BOARD_PLL_SOURCE /* Select source FR0 12MHz */ +#define BOARD_PLL_FIN LPC54_FRO_12MHZ /* PLL input frequency */ + +#ifdef BOARD_180MHz +/* PLL Clock Source: CLKIN + * Main Clock Source: PLL + * Fout: 220000000 + */ + +# define BOARD_PLL_CLKSEL SYSCON_SYSPLLCLKSEL_CLKIN +# define BOARD_PLL_SELI 32 /* Bandwidth select I value */ +# define BOARD_PLL_SELP 16 /* Bandwidth select P value */ +# define BOARD_PLL_SELR 0 /* Bandwidth select R value */ +# define BOARD_PLL_MDEC 8191 /* Encoded M-divider coefficient */ +# define BOARD_PLL_NDEC 770 /* Encoded N-divider coefficient */ +# define BOARD_PLL_PDEC 98 /* Encoded P-divider coefficient */ +# define BOARD_PLL_FOUT 180000000U /* Pll output frequency */ + +#else /* BOARD_220MHz */ +/* PLL Clock Source: FRO 12MHz + * Main Clock Source: PLL + * Fout: 220000000 + */ + +# define BOARD_PLL_CLKSEL SYSCON_SYSPLLCLKSEL_FFRO +# define BOARD_PLL_SELI 34 /* Bandwidth select I value */ +# define BOARD_PLL_SELP 31 /* Bandwidth select P value */ +# define BOARD_PLL_SELR 0 /* Bandwidth select R value */ +# define BOARD_PLL_MDEC 13243 /* Encoded M-divider coefficient */ +# define BOARD_PLL_NDEC 1 /* Encoded N-divider coefficient */ +# define BOARD_PLL_PDEC 98 /* Encoded P-divider coefficient */ +# define BOARD_PLL_FOUT 220000000 /* Pll output frequency */ +#endif + +#define BOARD_MAIN_CLK BOARD_PLL_FOUT /* Main clock frequency */ + +/* CPU Clock: + * + * AHB Clock Divider: 1 + * AHB Clock Frequency: 180,000,000 or 220,000,000 + */ + +#define BOARD_AHBCLKDIV 1 /* (un-decremented) */ +#define BOARD_AHB_FREQUENCY (BOARD_MAIN_CLK / BOARD_AHBCLKDIV) +#define BOARD_CPU_FREQUENCY BOARD_AHB_FREQUENCY + +/* Fraction Rate Generator (FRG) Clock (Optional Flexcomm0 function clock) + * + * To use the fractional divider, the DIV value must be programmed with the + * fixed value of 256. Then: + * + * Ffrg = (Finput) / (1 + (MULT / DIV)) + * + * Mainclock is used as the FRG clock source. Divider must be such that the + * FRG output frequency is less than equal to 48MHz + * + * MUL = (Finput - Ffrg) * 256) / Ffrg + */ + +/* Revisit: FRGCLK <= 48MHz cannot be realized with the MainClk source */ + +#define BOARD FRGCLK_CLKSEL SYSCON_FRGCLKSEL_MAINCLK +#define BOARD_FRGCLK_INPUT BOARD_MAIN_CLK /* FRG input frequency */ +#define BOARD_FRGCLK 48000000 /* May not be exact */ + +/* SysTick: The SysTick clock may be clocked internally either by the by the + * system clock (CLKSOURCE==1) or by the SysTick function clock (CLKSOURCE==0). + * The SysTick Function clock is equal to: + * + * Fsystick = Fmainclk / SYSTICKCLKDIV + * + * Tips for selecting BOARD_SYSTICKCLKDIV: The resulting SysTick reload value + * should be as large as possible, but must be less than 2^24: + * + * SYSTICKDIV > Fmainclk / CLK_TCK / 2^24 + * + * The logic in lpc54_timerisr.c will always select the SysTick function clock + * as the source (CLKSOURCE==0). NOTE: When the system tick clock divider is + * selected as the clock source, the CPU clock must be at least 2.5 times + * faster than the divider output. + * + * SysTick Divider: (SYSTICKCLKDIV) + */ + +#ifndef CONFIG_SCHED_TICKLESS +# if CONFIG_USEC_PER_TICK == 10000 +# define BOARD_SYSTICKCLKDIV 1 +# else +# error Missing SYSTICK divider +# endif +# define BOARD_SYSTICK_CLOCK (BOARD_AHB_FREQUENCY / BOARD_SYSTICKCLKDIV) +#endif + +/* Flexcomm0: USART0 (REVIST) */ + +#define BOARD_FLEXCOMM0_CLKSEL SYSCON_FCLKSEL_FRO12M +#define BOARD_FLEXCOMM0_FCLK LPC54_FRO_12MHZ + +/* Flexcomm2: I2C2 (REVIST) */ + +#define BOARD_FLEXCOMM2_CLKSEL SYSCON_FCLKSEL_FRO12M +#define BOARD_FLEXCOMM2_FCLK LPC54_FRO_12MHZ + +/* EMC */ + +#ifdef BOARD_220MHz +#define BOARD_EMC_CLKDIV 3 /* EMC Clock = CPU FREQ/3 */ +#else /* if BOARD_180MHz */ +#define BOARD_EMC_CLKDIV 2 /* EMC Clock = CPU FREQ/2 */ +#endif +#define BOARD_EMC_FREQUENCY (BOARD_CPU_FREQUENCY / BOARD_EMC_CLKDIV) + +/* SD/MMC or SDIO interface/ +/* SD/MMC function clock + * + * NOTE: The SDIO function clock to the interface can be up to 50 MHZ. + * Example: BOARD_MAIN_CLK=220MHz, CLKDIV=5, Finput=44MHz. + */ + +#define BOARD_SDMMC_MAXFREQ 50000000 +#define BOARD_SDMMC_CEIL(a,b) (((a) + (b) - 1) / (b)) + +#define BOARD_SDMMC_CLKSRC SYSCON_SDIOCLKSEL_MAINCLK +#define BOARD_SDMMC_CLKDIV BOARD_SDMMC_CEIL(BOARD_MAIN_CLK, BOARD_SDMMC_MAXFREQ) +#define BOARD_SDMMC_FREQUENCY (BOARD_MAIN_CLK / BOARD_SDMMC_CLKDIV) + +/* Mode-dependent function clock division + * + * Example: BOARD_SDMMC_FREQUENCY=44MHz + * BOARD_CLKDIV_INIT=110, Fsdmmc=400KHz (400KHz max) + * BOARD_CLKDIV_MMCXFR=4[3], Fsdmmc=11Mhz (20MHz max) See NOTE: + * BOARD_CLKDIV_SDWIDEXFR=2, Fsdmmc=22MHz (25MHz max) + * BOARD_CLKDIV_SDXFR=2, Fsdmmc=22MHz (25MHz max) + * + * NOTE: Clock division is 2*n. For example, value of 0 means divide by + * 2 * 0 = 0 (no division, bypass), value of 1 means divide by 2 * 1 = 2, value + * of 255 means divide by 2 * 255 = 510, and so on. + * + * SD/MMC logic will write the value ((clkdiv + 1) >> 1) as the divisor. So an + * odd value calculated below will be moved up to next higher divider value. So + * the value 3 will cause 2 to be written as the divider value and the effective + * divider will be 4. + */ + +#define BOARD_CLKDIV_INIT BOARD_SDMMC_CEIL(BOARD_SDMMC_FREQUENCY, 400000) +#define BOARD_CLKDIV_MMCXFR BOARD_SDMMC_CEIL(BOARD_SDMMC_FREQUENCY, 20000000) +#define BOARD_CLKDIV_SDWIDEXFR BOARD_SDMMC_CEIL(BOARD_SDMMC_FREQUENCY, 25000000) +#define BOARD_CLKDIV_SDXFR BOARD_SDMMC_CEIL(BOARD_SDMMC_FREQUENCY, 25000000) + +/* LED definitions *********************************************************/ +/* The LPCXpress-LPC54628 has three user LEDs: D9, D11, and D12. These + * LEDs are for application use. They are illuminated when the driving + * signal from the LPC546xx is low. The LEDs are driven by ports P2-2 (D9), + * P3-3 (D11) and P3-14 (D12). + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_D9 0 +#define BOARD_D11 1 +#ifndef CONFIG_ARCH_LEDS +# define BOARD_D12 2 +# define BOARD_NLEDS 3 +#else +# define BOARD_NLEDS 2 +#endif + +/* LED bits for use with board_userled_all() */ + +#define BOARD_D9_BIT (1 << BOARD_D9) +#define BOARD_D11_BIT (1 << BOARD_D11) +#ifndef CONFIG_ARCH_LEDS +# define BOARD_D12_BIT (1 << BOARD_D12) +#endif + +/* These LEDs are not used by the NuttX port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/lpc54_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + */ + /* D9 D11 D12 */ +#define LED_STARTED 0 /* OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* ON OFF OFF */ +#define LED_IRQSENABLED 2 /* OFF ON OFF */ +#define LED_STACKCREATED 3 /* OFF OFF OFF */ + +#define LED_INIRQ 4 /* NC NC ON (momentary) */ +#define LED_SIGNAL 4 /* NC NC ON (momentary) */ +#define LED_ASSERTION 4 /* NC NC ON (momentary) */ +#define LED_PANIC 4 /* NC NC ON (2Hz flashing) */ +#undef LED_IDLE /* Sleep mode indication not supported */ + +/* After booting, LEDs D9 and D11 are avaible for use by the user. If the + * system booted properly, D9 and D11 should be OFF and D12 should be glowing + * to indicate that interrupts are occurring. If D12 is flash at 2Hz, then + * the system has crashed. + */ + +/* Button definitions *******************************************************/ +/* The LPCXpresso has four switches: + * + * SW2 ISP2 P0.6 + * SW3 ISP1 P0.5 + * SW4 ISP0 P0.4 + * SW5 User Button P1.1 + * + * In all cased, the signal is low when the button is pressed. + * + * SW2, SW3, SW4 can be used to force the LPC546xx in to ISP boot modes. + * After boot these buttons could be used as user buttons. However, they are + * not available when the on-board SRDRAM is used because P0.4, P0.5, and + * P0.6 are also used as EMC_D2, EMC_D3, and EMC_D4, respectively. + * + * So SW5 is really the only button that that is generally available for + * software usage. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Pin Disambiguation *******************************************************/ +/* Flexcomm0/USART0 + * + * USART0 connects to the serial bridge on LPC4322JET100 and is typlical used + * for the serial console. + * + * BRIDGE_UART_RXD -> P0_29-ISP_FC0_RXD -> P0.29 GPIO_FC0_RXD_SDA_MOSI_2 + * BRIDGE_UART_TXD <- P0_30-ISP_FC0_TXD <- P0.30 GPIO_FC0_TXD_SCL_MISO_2 + */ + +#define GPIO_USART0_RXD (GPIO_FC0_RXD_SDA_MOSI_2 | GPIO_FILTER_OFF) +#define GPIO_USART0_TXD (GPIO_FC0_TXD_SCL_MISO_2 | GPIO_FILTER_OFF) + +/* Flexcomm2/I2C + * + * For I2C: + * Type A & D pins need: + * GPIO_OPENDRAIN + GPIO_FILTER_OFF + * Type I pins need for Standard mode I2C need: + * GPIO_FILTER_OFF + GPIO_I2C_FILTER_ON + GPIO_I2CDRIVE_LOW + * Type I pins need for fast speed I2C need: + * GPIO_FILTER_OFF + GPIO_I2C_FILTER_ON or OFF + + * GPIO_I2CDRIVE_LOW or HIGH + * Type I pins need for high speed I2C need: + * GPIO_FILTER_OFF + GPIO_I2C_FILTER_OFF + GPIO_I2CDRIVE_HIGH + * + * The touchscreen controller is on I2C2: SCL P3.24, SDA P3.23. These are + * both Type D/I pins. + */ + +#if defined(CONFIG_LPC54_I2C_FAST) +# define _I2CFILTER GPIO_I2C_FILTER_OFF +# define _I2CDRIVE GPIO_I2CDRIVE_HIGH +#elif defined(CONFIG_LPC54_I2C_HIGH) +# define _I2CFILTER GPIO_I2C_FILTER_OFF +# define _I2CDRIVE GPIO_I2CDRIVE_HIGH +#else +# define _I2CFILTER GPIO_I2C_FILTER_ON +# define _I2CDRIVE GPIO_I2CDRIVE_LOW +#endif + +#define GPIO_I2C2_SCL (GPIO_FC2_RTS_SCL_SSEL1_2 | \ + GPIO_FILTER_OFF | _I2CFILTER | \ + _I2CDRIVE) +#define GPIO_I2C2_SDA (GPIO_FC2_CTS_SDA_SSEL0_2 | \ + GPIO_FILTER_OFF | _I2CFILTER | \ + _I2CDRIVE) + +/* SD/MMC + * + * P2_10-SD_CDn + * P2_6-SD_D0 + * P2_7-SD_D1 + * P2_8-SD_D2 + * P2_9-SD_D3 + * P2_3-SD_CLK + * P2_4-SD_CMD + * P2_5-SD_POW_EN + * P3_15-SD_WPn + */ + +#define GPIO_SD_CARD_DET_N GPIO_SD_CARD_DET_N_2 /* P2.10 */ +#define GPIO_SD_D0 GPIO_SD_D0_3 /* P2.6 */ +#define GPIO_SD_D1 GPIO_SD_D1_3 /* P2.7 */ +#define GPIO_SD_D2 GPIO_SD_D2_3 /* P2.8 */ +#define GPIO_SD_D3 GPIO_SD_D3_3 /* P2.9 */ +#define GPIO_SD_CLK GPIO_SD_CLK_3 /* P2.3 */ +#define GPIO_SD_CMD GPIO_SD_CMD_3 /* P2.4 */ +#define GPIO_SD_POW_EN GPIO_SD_POW_EN_2 /* P2.5 */ +#define GPIO_SD_WR_PRT GPIO_SD_WR_PRT_2 /* P2.15 */ + +/* LCD + * + * There are no alternatives for LCD pins except for the VD0-VD3 pins. + * VD0-VD2 are not used in this hardware configuration. VD3 is on + * P2.21. + */ + +#define GPIO_LCD_VD3 GPIO_LCD_VD3_1 + +/* Ethernet Clock + * + * The Lpcxpresso-LPC546258 uses a LAN8720A PHY in RMII mode. Clocking is + * provided via a 25MHz crystal (Y1). CLKOUT on P3.12 is an option if JS4 + * is reversed. + */ + +#define BOARD_PHY_CLOCK 25000000 /* 25MHz crystal */ + +/* Ethernet RMII mode pins: + * + * P4_16-ENET_MDIO Ethernet MIIM data input and output + * P4_15-ENET_MDC Ethernet MIIM clock + * + * P4_11-ENET_RXD0 Ethernet receive data 0-1 + * P4_12-ENET_RXD1 + * P4_8-ENET_TXD0 Ethernet transmit data 0-1 + * P0_17-ENET_TXD1 + * P4_10-ENET_CRS_DV Ethernet receive data valid + * P4_13-ENET_TX_EN Ethernet transmit data enable + * + * P4_14-ENET_RX_CLK REF_CLK, Reference clock + * P2_26-ENET_PHY_RSTn nRST (Controlled by board logic) + * + * NOTE: You must set JP11 and JP12 to close 1-2 to enable Ethernet + * port functionality. Some pins are shared with USB0 overcurrent + * feature. + */ + + +#define GPIO_ENET_MDIO GPIO_ENET_MDIO_2 /* P4.16 */ +#define GPIO_ENET_MDC GPIO_ENET_MDC_2 /* P4.15 */ + +#define GPIO_ENET_RXD0 GPIO_ENET_RXD0_2 /* P4.11 */ +#define GPIO_ENET_RXD1 GPIO_ENET_RXD1_2 /* P4.12 */ +#define GPIO_ENET_TXD0 GPIO_ENET_TXD0_3 /* P4.8 */ +#define GPIO_ENET_TXD1 GPIO_ENET_TXD1_4 /* P0.17 */ +#define GPIO_ENET_RX_DV GPIO_ENET_RX_DV_2 /* P4.10 */ +#define GPIO_ENET_TX_EN GPIO_ENET_TX_EN_2 /* P4.13 */ + +#define GPIO_ENET_REF_CLK GPIO_ENET_RX_CLK_2 /* P4.14 */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* _CONFIGS_LPCXPRESSO_LPC54628_INCLUDE_BOARD_H */ diff --git a/configs/lpcxpresso-lpc54628/netnsh/defconfig b/configs/lpcxpresso-lpc54628/netnsh/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..89836e6010933641640224f819f5eab7c76a3939 --- /dev/null +++ b/configs/lpcxpresso-lpc54628/netnsh/defconfig @@ -0,0 +1,72 @@ +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH_BOARD_LPCXPRESSO_LPC54628=y +CONFIG_ARCH_BOARD="lpcxpresso-lpc54628" +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP_LPC54628=y +CONFIG_ARCH_CHIP_LPC54XX=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_STDARG_H=y +CONFIG_ARCH="arm" +CONFIG_BOARD_LOOPSPERMSEC=21082 +CONFIG_BUILTIN=y +CONFIG_BUTTONS_LOWER=y +CONFIG_BUTTONS=y +CONFIG_ETH0_PHY_LAN8720=y +CONFIG_EXAMPLES_NSH=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_FS_WRITABLE=y +CONFIG_INPUT=y +CONFIG_LPC54_EMC_DYNAMIC_CS0_SIZE=0x01000000 +CONFIG_LPC54_EMC_DYNAMIC_CS0=y +CONFIG_LPC54_EMC=y +CONFIG_LPC54_ETH_PHYADDR=0 +CONFIG_LPC54_ETHERNET=y +CONFIG_LPC54_GPIOIRQ=y +CONFIG_LPC54_USART0=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_NET_ARP_SEND=y +CONFIG_NET_HOSTNAME="LpcXpresso-Lpc54628" +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMPv6_NEIGHBOR=y +CONFIG_NET_ICMPv6_SOCKET=y +CONFIG_NET_ICMPv6=y +CONFIG_NET_IPv6=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NET=y +CONFIG_NETUTILS_TELNETC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_NOMAC=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_RAM_SIZE=163840 +CONFIG_RAM_START=0x10000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=2 +CONFIG_START_MONTH=12 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_PING6=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/lpcxpresso-lpc54628/nsh/defconfig b/configs/lpcxpresso-lpc54628/nsh/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..70d2e780688fc5bd250aec768fc137873f1034a3 --- /dev/null +++ b/configs/lpcxpresso-lpc54628/nsh/defconfig @@ -0,0 +1,61 @@ +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH_BOARD_LPCXPRESSO_LPC54628=y +CONFIG_ARCH_BOARD="lpcxpresso-lpc54628" +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP_LPC54628=y +CONFIG_ARCH_CHIP_LPC54XX=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_STDARG_H=y +CONFIG_ARCH="arm" +CONFIG_BOARD_LOOPSPERMSEC=21082 +CONFIG_BUILTIN=y +CONFIG_BUTTONS_LOWER=y +CONFIG_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_NSH=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_I2C=y +CONFIG_I2CTOOL_MAXBUS=9 +CONFIG_INPUT=y +CONFIG_LPC54_EMC_DYNAMIC_CS0=y +CONFIG_LPC54_EMC=y +CONFIG_LPC54_GPIOIRQ=y +CONFIG_LPC54_I2C2_MASTER=y +CONFIG_LPC54_RTC=y +CONFIG_LPC54_USART0=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_RAM_SIZE=163840 +CONFIG_RAM_START=0x10000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DRIVER=y +CONFIG_RTC_IOCTL=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=2 +CONFIG_START_MONTH=12 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_RAMTEST=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/lpcxpresso-lpc54628/nxwm/defconfig b/configs/lpcxpresso-lpc54628/nxwm/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..4c2f839ee1a434daa462dc0351ee6ddbeb9a1aaa --- /dev/null +++ b/configs/lpcxpresso-lpc54628/nxwm/defconfig @@ -0,0 +1,103 @@ +# CONFIG_ARCH_FPU is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NXWM_TOUCHSCREEN_DEVINIT is not set +CONFIG_ARCH_BOARD_LPCXPRESSO_LPC54628=y +CONFIG_ARCH_BOARD="lpcxpresso-lpc54628" +CONFIG_ARCH_CHIP_LPC54628=y +CONFIG_ARCH_CHIP_LPC54XX=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_STDARG_H=y +CONFIG_ARCH="arm" +CONFIG_BOARD_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=21082 +CONFIG_BUILTIN=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FT5X06_POLLMODE=y +CONFIG_FT5X06_SINGLEPOINT=y +CONFIG_FT5X06_SWAPXY=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INPUT_FT5X06=y +CONFIG_INPUT=y +CONFIG_LIB_BOARDCTL=y +CONFIG_LPC54_EMC_DYNAMIC_CS0_OFFSET=0x00080000 +CONFIG_LPC54_EMC_DYNAMIC_CS0_SIZE=0x00f80000 +CONFIG_LPC54_EMC_DYNAMIC_CS0=y +CONFIG_LPC54_EMC=y +CONFIG_LPC54_GPIOIRQ=y +CONFIG_LPC54_I2C2_MASTER=y +CONFIG_LPC54_LCD_BGR=y +CONFIG_LPC54_LCD_BPP16_565=y +CONFIG_LPC54_LCD_HBACKPORCH=43 +CONFIG_LPC54_LCD_HFRONTPORCH=8 +CONFIG_LPC54_LCD_VBACKPORCH=12 +CONFIG_LPC54_LCD_VFRONTPORCH=4 +CONFIG_LPC54_LCD_VPULSE=10 +CONFIG_LPC54_LCD_VRAMBASE=0xa0000000 +CONFIG_LPC54_LCD=y +CONFIG_LPC54_USART0=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_TOUCHSCREEN=y +CONFIG_NX=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXTERM_CACHESIZE=32 +CONFIG_NXTERM_CURSORCHAR=95 +CONFIG_NXTERM_MXCHARS=325 +CONFIG_NXTERM_NXKBDIN=y +CONFIG_NXTERM=y +CONFIG_NXTK_BORDERCOLOR1=0x5cb7 +CONFIG_NXTK_BORDERCOLOR2=0x21c9 +CONFIG_NXTK_BORDERCOLOR3=0xffdf +CONFIG_NXWIDGETS_BPP=16 +CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y +CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y +CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb +CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 +CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e +CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 +CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf +CONFIG_NXWIDGETS_SIZEOFCHAR=1 +CONFIG_NXWIDGETS=y +CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y +CONFIG_NXWM_HEXCALCULATOR_FONTID=5 +CONFIG_NXWM_KEYBOARD=y +CONFIG_NXWM_TASKBAR_LEFT=y +CONFIG_NXWM_TASKBAR_VSPACING=4 +CONFIG_NXWM_UNITTEST=y +CONFIG_NXWM=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=8 +CONFIG_RAM_SIZE=163840 +CONFIG_RAM_START=0x10000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_ONEXIT=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=18 +CONFIG_START_MONTH=12 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nxwm_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/lpcxpresso-lpc54628/scripts/Make.defs b/configs/lpcxpresso-lpc54628/scripts/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..6546e22101f451b9efddd94ef702fdd968a2b3c4 --- /dev/null +++ b/configs/lpcxpresso-lpc54628/scripts/Make.defs @@ -0,0 +1,117 @@ +############################################################################ +# configs/lpcxpresso-lpc54628/scripts/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +# Setup for the kind of memory that we are executing from + +LDSCRIPT = flash.ld + +# Setup for Windows vs Linux/Cygwin/OSX environments + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/lpcxpresso-lpc54628/scripts/flash.ld b/configs/lpcxpresso-lpc54628/scripts/flash.ld new file mode 100644 index 0000000000000000000000000000000000000000..fc09e2fffc5a443499319069f3d9fd19abe8470d --- /dev/null +++ b/configs/lpcxpresso-lpc54628/scripts/flash.ld @@ -0,0 +1,116 @@ +/**************************************************************************** + * configs/lpcxpresso-lpc54628/scripts/flash.ld + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The LPC54628 on the LPCXPressio has 512Kb of FLASH at address 0x0000:0000. + * The Main SRAM is comprised of up to a total 160 KB of contiguous, on-chip + * static RAM memory beginning at address 0x2000:0000 (this is in addition + * to SRAMX aso the total device SRAM can be up to 200 KB). + */ + +MEMORY +{ + progmem (rx) : ORIGIN = 0x00000000, LENGTH = 512K + datamem (rwx) : ORIGIN = 0x20000000, LENGTH = 160K +} + +OUTPUT_ARCH(arm) +ENTRY(__start) /* Treat __start as the anchor for dead code stripping */ +EXTERN(_vectors) /* Force the vectors to be included in the output */ +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > progmem + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > progmem + + .ARM.extab : { + *(.ARM.extab*) + } > progmem + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > progmem + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > datamem AT > progmem + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > datamem + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/lpcxpresso-lpc54628/src/Makefile b/configs/lpcxpresso-lpc54628/src/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..d67fcf8c18241b63a983f7539dd7231398661fa7 --- /dev/null +++ b/configs/lpcxpresso-lpc54628/src/Makefile @@ -0,0 +1,71 @@ +############################################################################ +# configs/lpcxpresso-lpc54628/src/Makefile +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = lpc54_boot.c lpc54_bringup.c lpc54_userleds.c lpc54_lcd.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += lpc54_autoleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += lpc54_buttons.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += lpc54_appinit.c +endif + +ifeq ($(CONFIG_LPC54_HAVE_I2C_MASTER),y) +CSRCS += lpc54_i2c.c +endif + +ifeq ($(CONFIG_SYSTEM_I2CTOOL),y) +CSRCS += lpc54_i2ctool.c +endif + +ifeq ($(CONFIG_INPUT_FT5X06),y) +CSRCS += lpc54_ft5x06.c +endif + +ifeq ($(CONFIG_LPC54_EMC),y) +ifeq ($(CONFIG_LPC54_EMC_DYNAMIC),y) +CSRCS += lpc54_sdram.c +endif +endif + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/lpcxpresso-lpc54628/src/lpc54_appinit.c b/configs/lpcxpresso-lpc54628/src/lpc54_appinit.c new file mode 100644 index 0000000000000000000000000000000000000000..caaab219987361baccd059d6636b9ce0accf3ed9 --- /dev/null +++ b/configs/lpcxpresso-lpc54628/src/lpc54_appinit.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * config/lpcxpresso-lpc54628/src/lpc54_appinit.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "lpcxpresso-lpc54628.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_INITIALIZE + /* Board initialization already performed by board_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return lpc54_bringup(); +#endif +} diff --git a/configs/lpcxpresso-lpc54628/src/lpc54_autoleds.c b/configs/lpcxpresso-lpc54628/src/lpc54_autoleds.c new file mode 100644 index 0000000000000000000000000000000000000000..7dce4782d69fd52e3ee86204c24b0d9c66b62fcc --- /dev/null +++ b/configs/lpcxpresso-lpc54628/src/lpc54_autoleds.c @@ -0,0 +1,133 @@ +/**************************************************************************** + * configs/lpcxpresso-lpc54628/src/lpc54_autoleds.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The LPCXpress-LPC54628 has three user LEDs: D9, D11, and D12. These + * LEDs are for application use. They are illuminated when the driving + * signal from the LPC546xx is low. The LEDs are driven by ports P2-2 (D9), + * P3-3 (D11) and P3-14 (D12). + * + * These LEDs are not used by the NuttX port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/lpc54_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * D9 D11 D12 + * LED_STARTED 0 OFF OFF OFF + * LED_HEAPALLOCATE 1 ON OFF OFF + * LED_IRQSENABLED 2 OFF ON OFF + * LED_STACKCREATED 3 OFF OFF OFF + * + * LED_INIRQ 4 NC NC ON (momentary) + * LED_SIGNAL 4 NC NC ON (momentary) + * LED_ASSERTION 4 NC NC ON (momentary) + * LED_PANIC 4 NC NC ON (2Hz flashing) + * LED_IDLE Sleep mode indication not supported + * + * After booting, LEDs D9 and D11 are avaible for use by the user. If the + * system booted properly, D9 and D11 should be OFF and D12 should be glowing + * to indicate that interrupts are occurring. If D12 is flash at 2Hz, then + * the system has crashed. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "lpc54_gpio.h" +#include "lpcxpresso-lpc54628.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + lpc54_gpio_config(GPIO_LED_D9); + lpc54_gpio_config(GPIO_LED_D11); + lpc54_gpio_config(GPIO_LED_D12); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + /* D9 and D11 are only changed during boot up states */ + + if ((unsigned int)led <= 3) + { + bool d9off = (led != 1); + bool d11off = (led != 2); + + lpc54_gpio_write(GPIO_LED_D9, d9off); /* Low illuminates */ + lpc54_gpio_write(GPIO_LED_D11, d11off); /* Low illuminates */ + lpc54_gpio_write(GPIO_LED_D12, true); /* Low illuminates */ + } + else + { + lpc54_gpio_write(GPIO_LED_D12, false); /* Low illuminates */ + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 4) + { + lpc54_gpio_write(GPIO_LED_D12, true); /* Low illuminates */ + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/lpcxpresso-lpc54628/src/lpc54_boot.c b/configs/lpcxpresso-lpc54628/src/lpc54_boot.c new file mode 100644 index 0000000000000000000000000000000000000000..0d7541143a2528ddba25cfd20af8183ffadd3009 --- /dev/null +++ b/configs/lpcxpresso-lpc54628/src/lpc54_boot.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * configs/lpcxpresso-lpc54628/src/lpc54_boot.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "lpcxpresso-lpc54628.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_board_initialize + * + * Description: + * All LPC54xx architectures must provide the following entry point. + * This entry point is called early in the initialization -- after + * clocking and memory have been configured but before caches have been + * enabled and before any devices have been initialized. + * + ****************************************************************************/ + +void lpc54_board_initialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + + /* Configure the LCD GPIOs if LCD support has been selected. This is done + * unconditionally because even if the LCD is not configured, we will + * still want to turn the backlight off. + */ + + lpc54_lcd_initialize(); + +#ifdef CONFIG_LPC54_EMC + /* Initialize SDRAM */ + + lpc54_sdram_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ + /* Perform board-specific initialization */ + + (void)lpc54_bringup(); +} +#endif diff --git a/configs/lpcxpresso-lpc54628/src/lpc54_bringup.c b/configs/lpcxpresso-lpc54628/src/lpc54_bringup.c new file mode 100644 index 0000000000000000000000000000000000000000..5b1bf5152b56944accb84fcf910dc258c41205eb --- /dev/null +++ b/configs/lpcxpresso-lpc54628/src/lpc54_bringup.c @@ -0,0 +1,190 @@ +/**************************************************************************** + * configs/lpcxpresso-lpc54628/src/lpc54_bringup.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifdef CONFIG_VIDEO_FB +# include +#endif + +#ifdef CONFIG_BUTTONS_LOWER +# include +#endif + +#ifdef CONFIG_LPC54_SDMMC +# include +# include +# include "lpc54_sdmmc.h" +#endif + +#ifdef CONFIG_RTC_DRIVER +# include +# include "lpc54_rtc.h" +#endif + +#include "lpcxpresso-lpc54628.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int lpc54_bringup(void) +{ +#ifdef HAVE_MMCSD + struct sdio_dev_s *sdmmc; +#endif +#ifdef HAVE_RTC_DRIVER + struct rtc_lowerhalf_s *rtc; +#endif + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef HAVE_RTC_DRIVER + /* Instantiate the STM32 lower-half RTC driver */ + + rtc = lpc54_rtc_lowerhalf(); + if (rtc == NULL) + { + syslog(LOG_ERR, + "ERROR: Failed to instantiate the RTC lower-half driver\n"); + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, rtc); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to bind/register the RTC driver: %d\n", + ret); + } + } +#endif + +#ifdef HAVE_I2CTOOL + /* Register I2C drivers on behalf of the I2C tool */ + + lpc54_i2ctool(); +#endif + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef HAVE_FT5x06 + /* Register the FT5x06 touch panel driver */ + + ret = lpc54_ft5x06_register(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: lpc54_ft5x06_register() failed: %d\n", ret); + } +#endif + +#ifdef HAVE_MMCSD + /* Get an instance of the SDIO interface */ + + sdmmc = lpc54_sdmmc_initialize(0); + if (!sdmmc) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SD/MMC\n"); + } + else + { + /* Dind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(MMCSD_MINOR, sdmmc); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + } + } +#endif + +#ifdef CONFIG_BUTTONS_LOWER + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/configs/lpcxpresso-lpc54628/src/lpc54_buttons.c b/configs/lpcxpresso-lpc54628/src/lpc54_buttons.c new file mode 100644 index 0000000000000000000000000000000000000000..556347ee15194d73bb315c7abcbfe83c04d503e3 --- /dev/null +++ b/configs/lpcxpresso-lpc54628/src/lpc54_buttons.c @@ -0,0 +1,199 @@ +/**************************************************************************** + * configs/lpcxpresso-lpc54628/src/lpc54_buttons.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include + +#include "lpc54_gpio.h" +#include "lpcxpresso-lpc54628.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_LPC54_GPIOIRQ) && defined(CONFIG_ARCH_IRQBUTTONS) +static uint8_t g_button_irq; +static xcpt_t g_button_handler; +static void *g_button_arg; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_interrupt + * + * Description: + * This function intermediates the interrupt provided to the application + * logic that attached the interrupt. This is necessary to properly + * clear the pending button interrupts. + * + ****************************************************************************/ + +static int board_button_interrupt(int irq, FAR void *context, FAR void *arg) +{ + /* Acknowledge the button interrupt */ + + (void)lpc54_gpio_ackedge(irq); + + /* Transfer control to the attached interrupt handler */ + + if (g_button_handler != NULL) + { + return g_button_handler(irq, context, arg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ + int ret; + + /* Configure the button GPIO interrupt */ + + ret = lpc54_gpio_config(GPIO_BUTTON_USER); + if (ret >= 0) + { +#if defined(CONFIG_LPC54_GPIOIRQ) && defined(CONFIG_ARCH_IRQBUTTONS) + /* Get the IRQ that is associated with the PIN interrupt and attach the + * intermediate button interrupt handler to that interrupt. + */ + + g_button_irq = lpc54_gpio_irqno(GPIO_BUTTON_USER); + (void)irq_attach(g_button_irq, board_button_interrupt, NULL); +#endif + } +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the BUTTON* + * definitions above for the meaning of each bit in the returned value. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + return lpc54_gpio_read(GPIO_BUTTON_USER) ? 0 : BUTTON_USER_BIT; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * This function may be called to register an interrupt handler that will + * be called when a button is depressed or released. The ID value is one + * of the BUTTON* definitions provided above. + * + * Configuration Notes: + * Configuration CONFIG_AVR32_GPIOIRQ must be selected to enable the + * overall GPIO IRQ feature and CONFIG_AVR32_GPIOIRQSETA and/or + * CONFIG_AVR32_GPIOIRQSETB must be enabled to select GPIOs to support + * interrupts on. For button support, bits 2 and 3 must be set in + * CONFIG_AVR32_GPIOIRQSETB (PB2 and PB3). + * + ****************************************************************************/ + +#if defined(CONFIG_LPC54_GPIOIRQ) && defined(CONFIG_ARCH_IRQBUTTONS) +int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + /* Are we attaching or detaching? */ + + if (irqhandler != NULL) + { + /* Yes.. Attach and enable the interrupt */ + + g_button_handler = irqhandler; + g_button_arg = arg; + up_enable_irq(g_button_irq); + } + else + { + /* No.. Disable and detach the interrupt */ + + up_disable_irq(g_button_irq); + g_button_handler = NULL; + g_button_arg = NULL; + } + + ret = OK; + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/configs/lpcxpresso-lpc54628/src/lpc54_ft5x06.c b/configs/lpcxpresso-lpc54628/src/lpc54_ft5x06.c new file mode 100644 index 0000000000000000000000000000000000000000..162089b190bb2b3382358c7dc2e3039ff2830610 --- /dev/null +++ b/configs/lpcxpresso-lpc54628/src/lpc54_ft5x06.c @@ -0,0 +1,269 @@ +/**************************************************************************** + * configs/lpcxpresso-lpc54628/src/lpc54_ft5x06.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "lpc54_config.h" +#include "lpc54_gpio.h" +#include "lpcxpresso-lpc54628.h" + +#ifdef HAVE_FT5x06 + +/**************************************************************************** + * Pre-processor Defintions + ****************************************************************************/ + +#define FT5x06_FREQUENCY 400000 /* For now, will boost later */ + +/**************************************************************************** + * Private Function Ptototypes + ****************************************************************************/ + +#ifndef CONFIG_FT5X06_POLLMODE +static int lpc54_ft5x06_attach(FAR const struct ft5x06_config_s *config, + xcpt_t isr, FAR void *arg); +static void lpc54_ft5x06_enable(FAR const struct ft5x06_config_s *config, + bool enable); +static void lpc54_ft5x06_clear(FAR const struct ft5x06_config_s *config); +#endif + +static void lpc54_ft5x06_wakeup(FAR const struct ft5x06_config_s *config); +static void lpc54_ft5x06_nreset(FAR const struct ft5x06_config_s *config, + bool state); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct ft5x06_config_s g_ft5x06_config = +{ + .address = FT5x06_I2C_ADDRESS, + .frequency = FT5x06_FREQUENCY, +#ifndef CONFIG_FT5X06_POLLMODE + .attach = lpc54_ft5x06_attach, + .enable = lpc54_ft5x06_enable, + .clear = lpc54_ft5x06_clear, +#endif + .wakeup = lpc54_ft5x06_wakeup, + .nreset = lpc54_ft5x06_nreset +}; + +#ifndef CONFIG_FT5X06_POLLMODE +static uint8_t g_ft5x06_irq; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_ft5x06_attach + * + * Description: + * Attach an FT5x06 interrupt handler to a GPIO interrupt + * + ****************************************************************************/ + +#ifndef CONFIG_FT5X06_POLLMODE +static int lpc54_ft5x06_attach(FAR const struct ft5x06_config_s *config, + xcpt_t isr, FAR void *arg) +{ + return irq_attach(g_ft5x06_irq, isr, arg); +} +#endif + +/**************************************************************************** + * Name: lpc54_ft5x06_enable + * + * Description: + * Enable or disable a GPIO interrupt + * + ****************************************************************************/ + +#ifndef CONFIG_FT5X06_POLLMODE +static void lpc54_ft5x06_enable(FAR const struct ft5x06_config_s *config, + bool enable) +{ + if (enable) + { + up_enable_irq(g_ft5x06_irq); + } + else + { + up_disable_irq(g_ft5x06_irq); + } +} +#endif + +/**************************************************************************** + * Name: lpc54_ft5x06_clear + * + * Description: + * Acknowledge/clear any pending GPIO interrupt + * + ****************************************************************************/ + +#ifndef CONFIG_FT5X06_POLLMODE +static void lpc54_ft5x06_clear(FAR const struct ft5x06_config_s *config) +{ + (void)lpc54_gpio_ackedge(g_ft5x06_irq); +} +#endif + +/**************************************************************************** + * Name: lpc54_ft5x06_wakeup + * + * Description: + * Issue WAKE interrupt to FT5x06 to change the FT5x06 from Hibernate to + * Active mode. + * + ****************************************************************************/ + +static void lpc54_ft5x06_wakeup(FAR const struct ft5x06_config_s *config) +{ + /* We do not have access to the WAKE pin in the implementation */ +} + +/**************************************************************************** + * Name: lpc54_ft5x06_nreset + * + * Description: + * Control the chip reset pin (active low) + * + ****************************************************************************/ + +static void lpc54_ft5x06_nreset(FAR const struct ft5x06_config_s *config, + bool nstate) +{ + lpc54_gpio_write(GPIO_FT5x06_CTRSTn, nstate); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_ft5x06_register + * + * Description: + * Register the FT5x06 touch panel driver + * + ****************************************************************************/ + +int lpc54_ft5x06_register(void) +{ + FAR struct i2c_master_s *i2c; + int ret; + +#ifndef CONFIG_FT5X06_POLLMODE + int irq; + + /* Initialize GPIO pins. NOTE: The nRST pin was already configured during + * early LCD initialization. The Part is in reset now. + */ + + lpc54_gpio_config(GPIO_FT5x06_INTR); + irq = lpc54_gpio_irqno(GPIO_FT5x06_INTR); + DEBUGASSERT(irq > 0 && irq < UINT8_MAX); + g_ft5x06_irq = (uint8_t)irq; + + /* Make sure that the interrupt is disabled at the NVIC */ + + lpc54_gpio_ackedge(irq); + up_disable_irq(irq); +#endif + + /* Take the FT5x06 out of reset */ + + lpc54_gpio_write(GPIO_FT5x06_CTRSTn, true); + + /* The FT5x06 is on I2C2. Get the handle and register the F5x06 device */ + + i2c = lpc54_i2c_handle(2, I2C2NDX); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C2 interface\n"); + return -ENODEV; + } + else + { + ret = ft5x06_register(i2c, &g_ft5x06_config, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register FT5x06 driver: %d\n", + ret); + + lpc54_gpio_write(GPIO_FT5x06_CTRSTn, false); + lpc54_i2c_free(I2C2NDX); + return ret; + } + } + + return OK; +} + +/**************************************************************************** + * Name: board_tsc_setup and board_tsc_teardown + * + * Description: + * Stubs for expected interfaces. This implementation does not permit the + * application to mange the touch screen controller. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARDCTL_TSCTEST +int board_tsc_setup(int minor) +{ + DEBUGASSERT(minor == 0); + return OK; +} + +void board_tsc_teardown(void) +{ +} +#endif + +#endif /* HAVE_FT5x06*/ diff --git a/configs/lpcxpresso-lpc54628/src/lpc54_i2c.c b/configs/lpcxpresso-lpc54628/src/lpc54_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..56c0a0bf667a491ce6edf29b4ec9573161a3755a --- /dev/null +++ b/configs/lpcxpresso-lpc54628/src/lpc54_i2c.c @@ -0,0 +1,107 @@ +/**************************************************************************** + * configs/lpcxpresso-lpc54628/src/lpc54_i2c.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "lpc54_config.h" +#include "lpc54_i2c_master.h" +#include "lpcxpresso-lpc54628.h" + +#if defined(HAVE_I2CTOOL) || defined(HAVE_FT5x06) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static FAR struct i2c_master_s *g_i2c_handle[NI2C]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_i2c_handle + * + * Description: + * Create (or reuse) an I2C handle + * + ****************************************************************************/ + +FAR struct i2c_master_s *lpc54_i2c_handle(int bus, int ndx) +{ + FAR struct i2c_master_s *i2c = g_i2c_handle[ndx]; + + if (i2c == NULL) + { + i2c = lpc54_i2cbus_initialize(bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + g_i2c_handle[ndx] = i2c; + } + } + + return i2c; +} + +/**************************************************************************** + * Name: lpc54_i2c_free + * + * Description: + * Free an I2C handle created by lpc54_i2c_handle + * + ****************************************************************************/ + +void lpc54_i2c_free(int ndx) +{ + if (g_i2c_handle[ndx] != NULL) + { + lpc54_i2cbus_uninitialize(g_i2c_handle[ndx]); + g_i2c_handle[ndx] = NULL; + } +} + +#endif /* HAVE_I2CTOOL || HAVE_FT5x06*/ diff --git a/configs/lpcxpresso-lpc54628/src/lpc54_i2ctool.c b/configs/lpcxpresso-lpc54628/src/lpc54_i2ctool.c new file mode 100644 index 0000000000000000000000000000000000000000..f9f3c2500a775a2e47449c66f4ca6cb1367b4e17 --- /dev/null +++ b/configs/lpcxpresso-lpc54628/src/lpc54_i2ctool.c @@ -0,0 +1,132 @@ +/**************************************************************************** + * configs/lpcxpresso-lpc54628/src/lpc54_i2ctool.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "lpc54_config.h" +#include "lpc54_i2c_master.h" +#include "lpcxpresso-lpc54628.h" + +#ifdef HAVE_I2CTOOL + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +static void lpc54_i2c_register(int bus, int ndx) +{ + FAR struct i2c_master_s *i2c; + int ret; + + i2c = lpc54_i2c_handle(bus, ndx); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); + lpc54_i2cbus_uninitialize(i2c); + } + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +void lpc54_i2ctool(void) +{ +#ifdef CONFIG_LPC54_I2C0_MASTER + lpc54_i2c_register(0, I2C0NDX); +#endif +#ifdef CONFIG_LPC54_I2C1_MASTER + lpc54_i2c_register(1, I2C1NDX); +#endif +#ifdef CONFIG_LPC54_I2C2_MASTER + lpc54_i2c_register(2, I2C2NDX); +#endif +#ifdef CONFIG_LPC54_I2C3_MASTER + lpc54_i2c_register(3, I2C3NDX); +#endif +#ifdef CONFIG_LPC54_I2C4_MASTER + lpc54_i2c_register(4, I2C4NDX); +#endif +#ifdef CONFIG_LPC54_I2C5_MASTER + lpc54_i2c_register(5, I2C5NDX); +#endif +#ifdef CONFIG_LPC54_I2C6_MASTER + lpc54_i2c_register(6, I2C6NDX); +#endif +#ifdef CONFIG_LPC54_I2C7_MASTER + lpc54_i2c_register(7, I2C7NDX); +#endif +#ifdef CONFIG_LPC54_I2C8_MASTER + lpc54_i2c_register(8, I2C8NDX); +#endif +#ifdef CONFIG_LPC54_I2C9_MASTER + lpc54_i2c_register(9, I2C9NDX); +#endif +} + +#endif /* HAVE_I2CTOOL */ diff --git a/configs/xtrs/src/xtr_irq.c b/configs/lpcxpresso-lpc54628/src/lpc54_lcd.c similarity index 72% rename from configs/xtrs/src/xtr_irq.c rename to configs/lpcxpresso-lpc54628/src/lpc54_lcd.c index 5cc00da95038004e29a7606fbe2b132693dad7c4..fe2754d2b1cb5c06f1ec31e6d1c8865835596414 100644 --- a/configs/xtrs/src/xtr_irq.c +++ b/configs/lpcxpresso-lpc54628/src/lpc54_lcd.c @@ -1,7 +1,7 @@ /**************************************************************************** - * configs/xtrs/src/xtr_irq.c + * configs/lpcxpresso_lpc54628/src/lpc54_lcd.c * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -39,42 +39,49 @@ #include -#include +#include +#include -#include "up_arch.h" -#include "up_internal.h" +#include "lpc54_lcd.h" +#include "lpc54_gpio.h" -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -int xtrs_timerisr(int irq, FAR chipreg_t *regs); +#include "lpcxpresso-lpc54628.h" /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: up_irqinitialize + * Name: lpc54_lcd_initialize + * + * Description: + * Initialize the LCD. Setup backlight (initially off) + * ****************************************************************************/ -void up_irqinitialize(void) +void lpc54_lcd_initialize(void) { - /* Attach the timer interrupt -- There is no special timer interrupt - * enable in the simulation so it must be enabled here before interrupts - * are enabled. - * - * NOTE: Normally, there are seperate enables for "global" interrupts - * and specific device interrupts. In such a "normal" case, the timer - * interrupt should be attached and enabled in the function - * xtrs_timer_initialize() - */ + /* Configure the LCD backlight (and turn the backlight off) */ - irq_attach(Z80_IRQ_SYSTIMER, (xcpt_t)xtrs_timerisr, NULL); + lpc54_gpio_config(GPIO_LCD_BL); - /* And finally, enable interrupts (including the timer) */ + /* Initiale touchscreen controller nRST GPIOs here (putting it into reset) */ -#ifndef CONFIG_SUPPRESS_INTERRUPTS - up_irq_restore(Z80_C_FLAG); -#endif + lpc54_gpio_config(GPIO_FT5x06_CTRSTn); } + +/**************************************************************************** + * Name: lpc54_backlight + * + * Description: + * If CONFIG_LPC54_LCD_BACKLIGHT is defined, then the board-specific + * logic must provide this interface to turn the backlight on and off. + * + ****************************************************************************/ + +#ifdef CONFIG_LPC54_LCD_BACKLIGHT +void lpc54_backlight(bool blon) +{ + lpc54_gpio_write(GPIO_LCD_BL, blon); /* Hight illuminates */ +} +#endif diff --git a/configs/lpcxpresso-lpc54628/src/lpc54_sdram.c b/configs/lpcxpresso-lpc54628/src/lpc54_sdram.c new file mode 100644 index 0000000000000000000000000000000000000000..febfbec82f98a8057221b7179cbd777cbd9b22b2 --- /dev/null +++ b/configs/lpcxpresso-lpc54628/src/lpc54_sdram.c @@ -0,0 +1,162 @@ +/**************************************************************************** + * configs/lpcxpresso-lpc54628/src/lpc54_bringup.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip/lpc54_pinmux.h" +#include "lpc54_gpio.h" +#include "lpc54_emc.h" +#include "lpcxpresso-lpc54628.h" + +#include + +#if defined(CONFIG_LPC54_EMC) && defined(CONFIG_LPC54_EMC_DYNAMIC) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define EMC_CLOCK_PERIOD_NS (1000000000 / BOARD_EMC_FREQUENCY) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* EMC basic configuration. */ + +static const struct emc_config_s g_emc_config = +{ + .bigendian = false, /* Little endian */ + .clksrc = EMC_INTLOOPBACK, /* Internal loop back from EMC_CLK output */ +#ifdef BOARD_220MHz + .clkdiv = 3, /* EMC Clock = CPU FREQ/3 */ +#else /* if BOARD_180MHz */ + .clkdiv = 2, /* EMC Clock = CPU FREQ/2 */ +#endif +}; + +/* Pin configuration */ + +static const lpc54_pinset_t g_emc_pinset[] = +{ + /* Control signals */ + + GPIO_EMC_CASN, GPIO_EMC_RASN, GPIO_EMC_WEN, GPIO_EMC_CLK0, + GPIO_EMC_CKE0, GPIO_EMC_DYCSN0, GPIO_EMC_DQM0, GPIO_EMC_DQM1, + + /* Address lines */ + + GPIO_EMC_A0, GPIO_EMC_A1, GPIO_EMC_A2, GPIO_EMC_A3, GPIO_EMC_A4, + GPIO_EMC_A5, GPIO_EMC_A6, GPIO_EMC_A7, GPIO_EMC_A8, GPIO_EMC_A9, + GPIO_EMC_A10, GPIO_EMC_A11, GPIO_EMC_A12, GPIO_EMC_A13, GPIO_EMC_A14, + + /* Data lines */ + + GPIO_EMC_D0, GPIO_EMC_D1, GPIO_EMC_D2, GPIO_EMC_D3, GPIO_EMC_D4, + GPIO_EMC_D5, GPIO_EMC_D6, GPIO_EMC_D7, GPIO_EMC_D8, GPIO_EMC_D9, + GPIO_EMC_D10, GPIO_EMC_D11, GPIO_EMC_D12, GPIO_EMC_D13, GPIO_EMC_D14, + GPIO_EMC_D15 +}; + +#define EMC_NPINS (sizeof(g_emc_pinset) / sizeof(lpc54_pinset_t)) + +/* Dynamic memory timing configuration. */ + +static const struct emc_dynamic_timing_config_s g_emc_dynconfig = +{ + .rdconfig = EMC_CMDDELAY, + .refresh = (64 * 1000000 / 4096), /* 4096 rows/ 64ms */ + .rp = 18, + .ras = 42, + .srex = 67, + .apr = 18, + .wr = EMC_CLOCK_PERIOD_NS + 6, /* one clk + 6ns */ + .dal = EMC_CLOCK_PERIOD_NS + 24, + .rc = 60, + .rfc = 60, + .xsr = 67, + .rrd = 12, + .mrd = 2, +}; + +/* Dynamic memory chip specific configuration: Chip 0 - MTL48LC8M16A2B4-6A */ + +static const struct emc_dynamic_chip_config_s g_emc_dynchipconfig = +{ + .chndx = 0, + .dyndev = EMC_SDRAM, + .rasnclk = 2, + .mode = 0x23, + .extmode = 0, /* SDRAM only */ + .addrmap = 0x09, /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/ +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_sdram_initialize + * + * Description: + * Initialize external SDRAM + * + ****************************************************************************/ + +void lpc54_sdram_initialize(void) +{ + int i; + + /* EMC Basic configuration. */ + + lpc54_emc_initialize(&g_emc_config); + + /* Configured pins used on the board */ + + for (i = 0; i < EMC_NPINS; i++) + { + lpc54_gpio_config(g_emc_pinset[i]); + } + + /* EMC Dynamc memory configuration. */ + + lpc54_emc_sdram_initialize(&g_emc_dynconfig, &g_emc_dynchipconfig, 1); +} + +#endif /* CONFIG_LPC54_EMC && CONFIG_LPC54_EMC_DYNAMIC */ diff --git a/configs/lpcxpresso-lpc54628/src/lpc54_userleds.c b/configs/lpcxpresso-lpc54628/src/lpc54_userleds.c new file mode 100644 index 0000000000000000000000000000000000000000..0710cc80427d7b6ba8c26b93d978d5aedfe8bdd2 --- /dev/null +++ b/configs/lpcxpresso-lpc54628/src/lpc54_userleds.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * configs/lpcxpresso-lpc54628/src/lpc54_userleds.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The LPCXpress-LPC54628 has three user LEDs: D9, D11, and D12. These + * LEDs are for application use. They are illuminated when the driving + * signal from the LPC546xx is low. The LEDs are driven by ports P2-2 (D9), + * P3-3 (D11) and P3-14 (D12). + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "lpc54_gpio.h" +#include "lpcxpresso-lpc54628.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ +#ifndef CONFIG_ARCH_LEDS + /* Configure LED GPIOs for output */ + + lpc54_gpio_config(GPIO_LED_D9); + lpc54_gpio_config(GPIO_LED_D11); + lpc54_gpio_config(GPIO_LED_D12); +#endif +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_D9) + { + lpc54_gpio_write(GPIO_LED_D9, !ledon); /* Low illuminates */ + } + else if (led == BOARD_D11) + { + lpc54_gpio_write(GPIO_LED_D11, !ledon); /* Low illuminates */ + } +#ifndef CONFIG_ARCH_LEDS + else if (led == BOARD_D12) + { + lpc54_gpio_write(GPIO_LED_D12, !ledon); /* Low illuminates */ + } +#endif +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + /* Low illuminates */ + + lpc54_gpio_write(GPIO_LED_D9, (ledset & BOARD_D9_BIT) == 0); + lpc54_gpio_write(GPIO_LED_D11, (ledset & BOARD_D11_BIT) == 0); +#ifndef CONFIG_ARCH_LEDS + lpc54_gpio_write(GPIO_LED_D12, (ledset & BOARD_D12_BIT) == 0); +#endif +} diff --git a/configs/lpcxpresso-lpc54628/src/lpcxpresso-lpc54628.h b/configs/lpcxpresso-lpc54628/src/lpcxpresso-lpc54628.h new file mode 100644 index 0000000000000000000000000000000000000000..35eba92525cfccf0ad397180de4ea01d3a4106eb --- /dev/null +++ b/configs/lpcxpresso-lpc54628/src/lpcxpresso-lpc54628.h @@ -0,0 +1,401 @@ +/**************************************************************************** + * configs/lpcxpresso-lpc54628/src/lpcxpresso-lpc54628.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef _CONFIGS_LPCXPRESSO_LPC54628_SRC_LPCXPRESSO_LPC54628_H +#define _CONFIGS_LPCXPRESSO_LPC54628_SRC_LPCXPRESSO_LPC54628_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "lpc54_config.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define HAVE_I2CTOOL 1 +#define HAVE_FT5x06 1 +#define HAVE_MMCSD 1 +#define HAVE_RTC_DRIVER 1 + +/* Do we need to register I2C drivers on behalf of the I2C tool? */ + +#ifdef CONFIG_SYSTEM_I2CTOOL + +# ifndef CONFIG_I2C_DRIVER +# warning CONFIG_SYSTEM_I2CTOOL requires CONFIG_I2C_DRIVER +# undef HAVE_I2CTOOL +# endif + +# ifndef HAVE_I2C_MASTER_DEVICE +# warning CONFIG_SYSTEM_I2CTOOL requires HAVE_I2C_MASTER_DEVICE +# undef HAVE_I2CTOOL +# endif + +#else +# undef HAVE_I2CTOOL +#endif + +/* Do we need to register FT5x06 touch panel driver? */ + +#ifdef CONFIG_INPUT_FT5X06 + +# ifndef CONFIG_LPC54_I2C2_MASTER +# warning CONFIG_INPUT_FT5X06 requires CONFIG_LPC54_I2C2_MASTER +# undef HAVE_FT5x06 +# endif + +# ifndef CONFIG_FT5X06_POLLMODE +# warning CONFIG_INPUT_FT5X06 requires CONFIG_FT5X06_POLLMODE +# undef HAVE_FT5x06 +# endif + +#else +# undef HAVE_FT5x06 +#endif + +/* MMC/SD support */ + +#ifdef CONFIG_LPC54_SDMMC + +# ifndef CONFIG_MMCSD +# warning MMC/SD support requires CONFIG_MMCSD +# undef HAVE_MMCSD +# endif + +# ifndef CONFIG_MMCSD_SDIO +# warning MMC/SD support requires CONFIG_MMCSD_SDIO +# undef HAVE_MMCSD +# endif + +# ifdef CONFIG_DISABLE_MOUNTPOINT +# warning MMC/SD cannot be supported with CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_MMCSD +# endif + +# ifdef CONFIG_NSH_MMCSDMINOR +# define MMCSD_MINOR CONFIG_NSH_MMCSDMINOR +# else +# define MMCSD_MINOR 0 +# endif + +#else +# undef HAVE_MMCSD +#endif + +/* Check if we can support the RTC driver */ + +#if !defined(CONFIG_RTC) || !defined(CONFIG_RTC_DRIVER) +# undef HAVE_RTC_DRIVER +#endif + +/* Indices into a sparse I2C array. Used with lpc54_i2c_handle() */ + +#ifdef CONFIG_LPC54_I2C0_MASTER +# define I2C0NDX 0 +# define I2C0CNT 1 +# define __I2C1NX 1 +#else +# define I2C0CNT 0 +# define __I2C1NX 0 +#endif + +#ifdef CONFIG_LPC54_I2C1_MASTER +# define I2C1NDX __I2C1NX +# define I2C1CNT 1 +# define __I2C2NX (__I2C1NX + 1) +#else +# define I2C1CNT 0 +# define __I2C2NX 0 +#endif + +#ifdef CONFIG_LPC54_I2C2_MASTER +# define I2C2NDX __I2C2NX +# define I2C2CNT 1 +# define __I2C3NX (__I2C2NX + 1) +#else +# define I2C2CNT 0 +# define __I2C3NX __I2C2NX +#endif + +#ifdef CONFIG_LPC54_I2C3_MASTER +# define I2C3NDX __I2C3NX +# define I2C3CNT 1 +# define __I2C4NX (__I2C3NX + 1) +#else +# define I2C3CNT 0 +# define __I2C4NX __I2C3NX +#endif + +#ifdef CONFIG_LPC54_I2C4_MASTER +# define I2C4NDX __I2C4NX +# define I2C4CNT 1 +# define __I2C5NX (__I2C4NX + 1) +#else +# define I2C4CNT 0 +# define __I2C5NX __I2C4NX +#endif + +#ifdef CONFIG_LPC54_I2C5_MASTER +# define I2C5NDX __I2C5NX +# define I2C5CNT 1 +# define __I2C6NX (__I2C5NX + 1) +#else +# define I2C5CNT 0 +# define __I2C6NX __I2C5NX +#endif + +#ifdef CONFIG_LPC54_I2C6_MASTER +# define I2C6NDX __I2C6NX +# define I2C6CNT 1 +# define __I2C7NX (__I2C6NX + 1) +#else +# define I2C6CNT 0 +# define __I2C7NX __I2C6NX +#endif + +#ifdef CONFIG_LPC54_I2C7_MASTER +# define I2C7NDX __I2C7NX +# define I2C7CNT 1 +# define __I2C8NX (__I2C7NX + 1) +#else +# define I2C7CNT 0 +# define __I2C8NX __I2C7NX +#endif + +#ifdef CONFIG_LPC54_I2C8_MASTER +# define I2C8NDX __I2C8NX +# define I2C8CNT 1 +# define __I2C9NX (__I2C8NX + 1) +#else +# define I2C8CNT 0 +# define __I2C9NX __I2C8NX +#endif + +#ifdef CONFIG_LPC54_I2C9_MASTER +# define I2CNDX __I2C9NX +# define I2C9CNT 1 +#else +# define I2C9CNT 0 +#endif + +#define NI2C (I2C0CNT + I2C1CNT + I2C2CNT + I2C3CNT + I2C4CNT + \ + I2C5CNT + I2C6CNT + I2C7CNT + I2C8CNT + I2C9CNT ) + +/* LED definitions **********************************************************/ +/* The LPCXpress-LPC54628 has three user LEDs: D9, D11, and D12. These + * LEDs are for application use. They are illuminated when the driving + * signal from the LPC546xx is low. The LEDs are driven by ports P2-2 (D9), + * P3-3 (D11) and P3-14 (D12). + */ + +#define GPIO_LED_D9 \ + (GPIO_PORT2 | GPIO_PIN2 | GPIO_VALUE_ONE | GPIO_OUTPUT | \ + GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PUSHPULL | GPIO_PULLUP) + +#define GPIO_LED_D11 \ + (GPIO_PORT3 | GPIO_PIN3 | GPIO_VALUE_ONE | GPIO_OUTPUT | \ + GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PUSHPULL | GPIO_PULLUP) + +#define GPIO_LED_D12 \ + (GPIO_PORT3 | GPIO_PIN14 | GPIO_VALUE_ONE | GPIO_OUTPUT | \ + GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PUSHPULL | GPIO_PULLUP) + +/* Button definitions *******************************************************/ +/* The LPCXpresso has four switches: + * + * SW2 ISP2 P0.6 + * SW3 ISP1 P0.5 + * SW4 ISP0 P0.4 + * SW5 User Button P1.1 + * + * In all cased, the signal is low when the button is pressed. + * + * SW2, SW3, SW4 can be used to force the LPC546xx in to ISP boot modes. + * After boot these buttons could be used as user buttons. However, they are + * not available when the on-board SRDRAM is used because P0.4, P0.5, and + * P0.6 are also used as EMC_D2, EMC_D3, and EMC_D4, respectively. + * + * So SW5 is really the only button that that is generally available for + * software usage. When pressed, it will be sensed low. + * + * P1.1 is a Type D pin. + */ + +#define GPIO_BUTTON_USER \ + (GPIO_PORT1 | GPIO_PIN1 | GPIO_INTBOTH | GPIO_MODE_DIGITAL | GPIO_FILTER_ON) + +/* LCD/TSC definitions ******************************************************/ +/* The backlight is controlled by P3.31 and is intended to connect via PWM + * to control the brightness level. For simplicity here, it configured as a + * simple GPIO output. + * + * The output goes to the enable (EN) pin of a AP5724 step-up DC/DC + * converter designed to drive white LEDs with a constant current. A high + * input at EN turns the converter on, and a low input turns it off. + */ + +#define GPIO_LCD_BL \ + (GPIO_PORT3 | GPIO_PIN31 | GPIO_VALUE_ZERO | GPIO_OUTPUT | \ + GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PUSHPULL | GPIO_PULLUP) + +/* The integrated touchscreen uses one GPIO out and one GPIO interrupting + * GPIO input: + * + * P2.27 CT_RSTn Active low + * P4.0 INTR On falling edge, I belieive + * + * The FT4x06's WAKE-UP interrupt pin is not brought out. + */ + +#define GPIO_FT5x06_CTRSTn \ + (GPIO_PORT2 | GPIO_PIN27 | GPIO_VALUE_ZERO | GPIO_OUTPUT | \ + GPIO_MODE_DIGITAL | GPIO_FILTER_OFF | GPIO_PUSHPULL | GPIO_PULLUP) + +#define GPIO_FT5x06_INTR \ + (GPIO_PORT4 | GPIO_PIN20 | GPIO_INTFE | GPIO_MODE_DIGITAL | GPIO_FILTER_OFF) + +/* I2C addresses (7-bit): */ + +#define CODEC_I2C_ADDRESS 0x1a +#define ACCEL_I2C_ADDRESS 0x1d +#define FT5x06_I2C_ADDRESS 0x38 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc54_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int lpc54_bringup(void); + +/**************************************************************************** + * Name: lpc54_sdram_initialize + * + * Description: + * Initialize external SDRAM + * + ****************************************************************************/ + +#ifdef CONFIG_LPC54_EMC +void lpc54_sdram_initialize(void); +#endif + +/**************************************************************************** + * Name: lpc54_lcd_initialize + * + * Description: + * Initialize the LCD. Setup backlight (initially off) + * + ****************************************************************************/ + +void lpc54_lcd_initialize(void); + +/**************************************************************************** + * Name: lpc54_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +void lpc54_i2ctool(void); +#endif + +/**************************************************************************** + * Name: lpc54_ft5x06_register + * + * Description: + * Register the FT5x06 touch panel driver + * + ****************************************************************************/ + +#ifdef HAVE_FT5x06 +int lpc54_ft5x06_register(void); +#endif + +/**************************************************************************** + * Name: lpc54_i2c_handle + * + * Description: + * Create (or reuse) an I2C handle + * + ****************************************************************************/ + +#if defined(HAVE_I2CTOOL) || defined(HAVE_FT5x06) +FAR struct i2c_master_s *lpc54_i2c_handle(int bus, int ndx); +#endif + +/**************************************************************************** + * Name: lpc54_i2c_free + * + * Description: + * Free an I2C handle created by lpc54_i2c_handle + * + ****************************************************************************/ + +#if defined(HAVE_I2CTOOL) || defined(HAVE_FT5x06) +void lpc54_i2c_free(int ndx); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* _CONFIGS_LPCXPRESSO_LPC54628_SRC_LPCXPRESSO_LPC54628_H */ diff --git a/configs/maple/include/board.h b/configs/maple/include/board.h index c45cef1005f6c7060364762c5e83d621a0c2133d..733a8f5e190831bbd59bff202f8f8ebd4a97bb3b 100644 --- a/configs/maple/include/board.h +++ b/configs/maple/include/board.h @@ -162,39 +162,4 @@ #define LED_ASSERTION 6 /* LED1 + LED2 */ #define LED_PANIC 7 /* LED1 / LED2 blinking */ -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_MAPLE_INCLUDE_BOARD_H */ diff --git a/configs/mbed/README.txt b/configs/mbed/README.txt index c74cf4852fd94b4123a14a36e1733be6a2725b76..2ed02719f2767033be5f03caacb2ced3d432efe2 100644 --- a/configs/mbed/README.txt +++ b/configs/mbed/README.txt @@ -6,200 +6,10 @@ README for NuttX port to the mbed.org LPC1768 board (http://mbed.org/) Contents ^^^^^^^^ - Development Environment - GNU Toolchain Options - IDEs - NuttX EABI "buildroot" Toolchain - NuttX OABI "buildroot" Toolchain - NXFLAT Toolchain - USB Device Controller Functions mbed Configuration Options USB Host Configuration Configurations -Development Environment -^^^^^^^^^^^^^^^^^^^^^^^ - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -^^^^^^^^^^^^^^^^^^^^^ - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The devkitARM GNU toolchain, - 3. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the NuttX buildroot toolchain. However, - the make system is setup to default to use the devkitARM toolchain. To use - the CodeSourcery or devkitARM toolchain, you simply need add one of the - following configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - NOTE: the CodeSourcery (for Windows)and devkitARM are Windows native toolchains. - The CodeSourcey (for Linux) and NuttX buildroot toolchains are Cygwin and/or - Linux native toolchains. There are several limitations to using a Windows based - toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -^^^^ - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lpc17xx, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/lpc17x/lpc17_vectors.S. - -NuttX EABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh mbed/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you - are building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -^^^^^^^^^^^^^^^^ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - mbed Configuration Options ^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/configs/mbed/include/board.h b/configs/mbed/include/board.h index 8367f1d5bc629088dec0ca513b75684c830aa79b..add4e96095009f8ab0c9bb18c74a809c2c7b2cc1 100644 --- a/configs/mbed/include/board.h +++ b/configs/mbed/include/board.h @@ -295,17 +295,6 @@ extern "C" /************************************************************************************ * Public Function Prototypes ************************************************************************************/ -/************************************************************************************ - * Name: lpc17_boardinitialize - * - * Description: - * All LPC17xx architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void lpc17_boardinitialize(void); /************************************************************************************ * Name: lpc17_led diff --git a/configs/mbed/nsh/defconfig b/configs/mbed/nsh/defconfig index 66597a84960efa06f6cb8b636803009cffab0f8e..4b0e23d51e6fef0a7aa65fdc7426cf47bcc9be52 100644 --- a/configs/mbed/nsh/defconfig +++ b/configs/mbed/nsh/defconfig @@ -1,4 +1,4 @@ -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_DF_H is not set diff --git a/configs/mcb1700/Kconfig b/configs/mcb1700/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..cdeb93b2b56c57c5d9f62659062e389cee218c93 --- /dev/null +++ b/configs/mcb1700/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_MCB1700 +endif diff --git a/configs/mcb1700/README.txt b/configs/mcb1700/README.txt new file mode 100644 index 0000000000000000000000000000000000000000..5abfa00c55c5efb1c6598f116695370def9e6ca1 --- /dev/null +++ b/configs/mcb1700/README.txt @@ -0,0 +1,278 @@ +README +^^^^^^ + +README for NuttX port to the Keil mcb1700 LPC1768 board. + +Contents +^^^^^^^^ + + USB Device Controller Functions + mcb1700 Configuration Options + USB Host Configuration + Configurations + +mcb1700 Configuration Options +^^^^^^^^^^^^^^^^^^^^^^^^^^ + + CONFIG_ARCH - Identifies the arch/ subdirectory. This should + be set to: + + CONFIG_ARCH=arm + + CONFIG_ARCH_family - For use in C code: + + CONFIG_ARCH_ARM=y + + CONFIG_ARCH_architecture - For use in C code: + + CONFIG_ARCH_CORTEXM3=y + + CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory + + CONFIG_ARCH_CHIP=lpc17xx + + CONFIG_ARCH_CHIP_name - For use in C code to identify the exact + chip: + + CONFIG_ARCH_CHIP_LPC1768=y + + CONFIG_ARCH_BOARD - Identifies the configs subdirectory and + hence, the board that supports the particular chip or SoC. + + CONFIG_ARCH_BOARD=mcb1700 (for the mcb1700.org board) + + CONFIG_ARCH_BOARD_name - For use in C code + + CONFIG_ARCH_BOARD_MCB1700=y + + CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation + of delay loops + + CONFIG_ENDIAN_BIG - define if big endian (default is little + endian) + + CONFIG_RAM_SIZE - Describes the installed DRAM (CPU SRAM in this case): + + CONFIG_RAM_SIZE=(32*1024) (32Kb) + + There is an additional 32Kb of SRAM in AHB SRAM banks 0 and 1. + + CONFIG_RAM_START - The start address of installed DRAM + + CONFIG_RAM_START=0x10000000 + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that + have LEDs + + CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt + stack. If defined, this symbol is the size of the interrupt + stack in bytes. If not defined, the user task stacks will be + used during interrupt handling. + + CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. + + CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that + cause a 100 second delay during boot-up. This 100 second delay + serves no purpose other than it allows you to calibratre + CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure + the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until + the delay actually is 100 seconds. + + Individual subsystems can be enabled: + CONFIG_LPC17_MAINOSC=y + CONFIG_LPC17_PLL0=y + CONFIG_LPC17_PLL1=n + CONFIG_LPC17_ETHERNET=n + CONFIG_LPC17_USBHOST=n + CONFIG_LPC17_USBOTG=n + CONFIG_LPC17_USBDEV=n + CONFIG_LPC17_UART0=y + CONFIG_LPC17_UART1=n + CONFIG_LPC17_UART2=n + CONFIG_LPC17_UART3=n + CONFIG_LPC17_CAN1=n + CONFIG_LPC17_CAN2=n + CONFIG_LPC17_SPI=n + CONFIG_LPC17_SSP0=n + CONFIG_LPC17_SSP1=n + CONFIG_LPC17_I2C0=n + CONFIG_LPC17_I2C1=n + CONFIG_LPC17_I2S=n + CONFIG_LPC17_TMR0=n + CONFIG_LPC17_TMR1=n + CONFIG_LPC17_TMR2=n + CONFIG_LPC17_TMR3=n + CONFIG_LPC17_RIT=n + CONFIG_LPC17_PWM0=n + CONFIG_LPC17_MCPWM=n + CONFIG_LPC17_QEI=n + CONFIG_LPC17_RTC=n + CONFIG_LPC17_WDT=n + CONFIG_LPC17_ADC=n + CONFIG_LPC17_DAC=n + CONFIG_LPC17_GPDMA=n + CONFIG_LPC17_FLASH=n + + LPC17xx specific device driver settings + + CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the + console and ttys0 (default is the UART0). + CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received. + This specific the size of the receive buffer + CONFIG_UARTn_TXBUFSIZE - Characters are buffered before + being sent. This specific the size of the transmit buffer + CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be + CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8. + CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity + CONFIG_UARTn_2STOP - Two stop bits + + LPC17xx specific CAN device driver settings. These settings all + require CONFIG_CAN: + + CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default + Standard 11-bit IDs. + CONFIG_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_CAN1 is defined. + CONFIG_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC17_CAN2 is defined. + CONFIG_CAN1_DIVISOR - CAN1 is clocked at CCLK divided by this number. + (the CCLK frequency is divided by this number to get the CAN clock). + Options = {1,2,4,6}. Default: 4. + CONFIG_CAN2_DIVISOR - CAN2 is clocked at CCLK divided by this number. + (the CCLK frequency is divided by this number to get the CAN clock). + Options = {1,2,4,6}. Default: 4. + CONFIG_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 + CONFIG_CAN_TSEG2 = the number of CAN time quanta in segment 2. Default: 7 + + LPC17xx specific PHY/Ethernet device driver settings. These setting + also require CONFIG_NET and CONFIG_LPC17_ETHERNET. + + CONFIG_ETH0_PHY_KS8721 - Selects Micrel KS8721 PHY + CONFIG_PHY_AUTONEG - Enable auto-negotion + CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. + CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex + + CONFIG_NET_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb + CONFIG_NET_NTXDESC - Configured number of Tx descriptors. Default: 18 + CONFIG_NET_NRXDESC - Configured number of Rx descriptors. Default: 18 + CONFIG_NET_WOL - Enable Wake-up on Lan (not fully implemented). + CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs + CONFIG_DEBUG_FEATURES. + CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets. + Also needs CONFIG_DEBUG_FEATURES. + CONFIG_NET_HASH - Enable receipt of near-perfect match frames. + CONFIG_LPC17_MULTICAST - Enable receipt of multicast (and unicast) frames. + Automatically set if CONFIG_NET_IGMP is selected. + + LPC17xx USB Device Configuration + + CONFIG_LPC17_USBDEV_FRAME_INTERRUPT + Handle USB Start-Of-Frame events. + Enable reading SOF from interrupt handler vs. simply reading on demand. + Probably a bad idea... Unless there is some issue with sampling the SOF + from hardware asynchronously. + CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT + Enable high priority interrupts. I have no idea why you might want to + do that + CONFIG_LPC17_USBDEV_NDMADESCRIPTORS + Number of DMA descriptors to allocate in SRAM. + CONFIG_LPC17_USBDEV_DMA + Enable lpc17xx-specific DMA support + CONFIG_LPC17_USBDEV_NOVBUS + Define if the hardware implementation does not support the VBUS signal + CONFIG_LPC17_USBDEV_NOLED + Define if the hardware implementation does not support the LED output + + LPC17xx USB Host Configuration + + CONFIG_USBHOST_OHCIRAM_SIZE + Total size of OHCI RAM (in AHB SRAM Bank 1) + CONFIG_USBHOST_NEDS + Number of endpoint descriptors + CONFIG_USBHOST_NTDS + Number of transfer descriptors + CONFIG_USBHOST_TDBUFFERS + Number of transfer descriptor buffers + CONFIG_USBHOST_TDBUFSIZE + Size of one transfer descriptor buffer + CONFIG_USBHOST_IOBUFSIZE + Size of one end-user I/O buffer. This can be zero if the + application can guarantee that all end-user I/O buffers + reside in AHB SRAM. + +USB Host Configuration +^^^^^^^^^^^^^^^^^^^^^^ + + The mcb1700 board can be easily modified to support a USB host interface + (Remember to add 2 resistors of 15K to D+ and D- pins). + + The NuttShell (NSH) mcb1700 can also be modified in order to support USB + host operations. To make these modifications, do the following: + + 1. First configure to build the NSH configuration from the top-level + NuttX directory: + + cd tools + ./configure mcb1700/nsh + cd .. + + 2. Then edit the top-level .config file to enable USB host. Make the + following changes using 'make menuconfig': + + System Type -> LPC17xx Peripheral Support + CONFIG_LPC17_USBHOST=y : USB host controller driver support + + Device Drivers -> USB Host Driver Support + CONFIG_USBHOST=y : USB host support + CONFIG_USBHOST_ISOC_DISABLE=y : Not needed + CONFIG_USBHOST_MSC=y : Mass storage class support + + Library Routines + CONFIG_SCHED_WORKQUEUE=y : Enable worker thread + + When this change is made, NSH should be extended to support USB flash + devices. When a FLASH device is inserted, you should see a device + appear in the /dev (pseudo) directory. The device name should be + like /dev/sda, /dev/sdb, etc. The USB mass storage device, is present + it can be mounted from the NSH command line like: + + ls /dev + mount -t vfat /dev/sda /mnt/flash + + Files on the connect USB flash device should then be accessible under + the mountpoint /mnt/flash. + +Configurations +^^^^^^^^^^^^^^ + + General + ------- + + Each mcb1700 configuration is maintained in a sub-directory and can be selected + as follow: + + cd tools + ./configure.sh mcb1700/ + cd - + + Where is one of the mcb1700 subdirectories described in the + following paragraph. + + NOTES: + + 1. These configurations use the mconf-based configuration tool. To + change any of these configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + Configuration Sub-directories + ----------------------------- + + nsh: + Configures the NuttShell (nsh) located at examples/nsh. The + Configuration enables only the serial NSH interfaces. See notes + above for enabling USB host support in this configuration. diff --git a/configs/mcb1700/include/board.h b/configs/mcb1700/include/board.h new file mode 100644 index 0000000000000000000000000000000000000000..b57f4862e8b4d146960ec5e4f345281c8fa52063 --- /dev/null +++ b/configs/mcb1700/include/board.h @@ -0,0 +1,317 @@ +/************************************************************************************ + * configs/mcb1700/include/board.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_MCB1700_INCLUDE_BOARD_H +#define __CONFIGS_MCB1700_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* NOTE: The following definitions require lpc17_syscon.h. It is not included here + * because the including C file may not have that file in its include path. + */ + +#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency */ +#define BOARD_OSCCLK_FREQUENCY BOARD_XTAL_FREQUENCY /* Main oscillator frequency */ +#define BOARD_RTCCLK_FREQUENCY (32000) /* RTC oscillator frequency */ +#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */ + +/* This is the clock setup we configure for: + * + * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for source + * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multiplier=20, pre-divider=1 + * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 + */ + +#define LPC17_CCLK 80000000 /* 80Mhz*/ + +/* Select the main oscillator as the frequency source. SYSCLK is then the frequency + * of the main oscillator. + */ + +#undef CONFIG_LPC17_MAINOSC +#define CONFIG_LPC17_MAINOSC 1 +#define BOARD_SCS_VALUE SYSCON_SCS_OSCEN + +/* Select the main oscillator and CCLK divider. The output of the divider is CCLK. + * The input to the divider (PLLCLK) will be determined by the PLL output. + */ + +#define BOARD_CCLKCFG_DIVIDER 6 +#define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_SHIFT) + +/* PLL0. PLL0 is used to generate the CPU clock divider input (PLLCLK). + * + * Source clock: Main oscillator + * PLL0 Multiplier value (M): 20 + * PLL0 Pre-divider value (N): 1 + * + * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz + */ + +#undef CONFIG_LPC17_PLL0 +#define CONFIG_LPC17_PLL0 1 +#define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN + +#define BOARD_PLL0CFG_MSEL 20 +#define BOARD_PLL0CFG_NSEL 1 +#define BOARD_PLL0CFG_VALUE \ + (((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLL0CFG_MSEL_SHIFT) | \ + ((BOARD_PLL0CFG_NSEL-1) << SYSCON_PLL0CFG_NSEL_SHIFT)) + +/* PLL1 -- Not used. */ + +#undef CONFIG_LPC17_PLL1 +#define BOARD_PLL1CFG_MSEL 36 +#define BOARD_PLL1CFG_NSEL 1 +#define BOARD_PLL1CFG_VALUE \ + (((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \ + ((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT)) + +/* USB divider. This divider is used when PLL1 is not enabled to get the + * USB clock from PLL0: + * + * USBCLK = PLL0CLK / 10 = 48MHz + */ + +#define BOARD_USBCLKCFG_VALUE SYSCON_USBCLKCFG_DIV10 + +/* FLASH Configuration */ + +#undef CONFIG_LPC17_FLASH +#define CONFIG_LPC17_FLASH 1 +#define BOARD_FLASHCFG_VALUE 0x0000303a + +/* Ethernet configuration */ + +//#define ETH_MCFG_CLKSEL_DIV ETH_MCFG_CLKSEL_DIV44 +#define ETH_MCFG_CLKSEL_DIV ETH_MCFG_CLKSEL_DIV20 + +/* LED definitions ******************************************************************/ +/* The MCB1700 has 4 LEDs along the bottom of the board. Blue or off. + * If CONFIG_ARCH_LEDS is defined, the LEDs will be controlled as follows for NuttX + * debug functionality (where NC means "No Change"). + * + * During the boot phases. LED1 and LED2 will show boot status. LED3/4 Not used. + */ + /* LED1 LED2 */ +#define LED_STARTED 0 /* OFF OFF */ +#define LED_HEAPALLOCATE 1 /* BLUE OFF */ +#define LED_IRQSENABLED 2 /* OFF BLUE */ +#define LED_STACKCREATED 3 /* OFF OFF */ + +/* After the system is booted, this logic will no longer use LEDs 1 & 2. They + * are available together with LED3 for use the application software using + * lpc17_led (prototyped below) + */ + /* LED1 LED2 LED3 LED4 */ +#define LED_INIRQ 4 /* NC NC NC ON (momentary) */ +#define LED_SIGNAL 5 /* NC NC NC ON (momentary) */ +#define LED_ASSERTION 6 /* NC NC NC ON (momentary) */ +#define LED_PANIC 7 /* NC NC NC ON (1Hz flashing) */ + + +#define GPIO_SSP0_SCK GPIO_SSP0_SCK_1 +#define GPIO_SSP0_SSEL GPIO_SSP0_SSEL_1 +#define GPIO_SSP0_MISO GPIO_SSP0_MISO_1 +#define GPIO_SSP0_MOSI GPIO_SSP0_MOSI_1 + +/* We need to redefine USB_PWRD as GPIO to get USB Host working + * Also remember to add 2 resistors of 15K to D+ and D- pins. + */ + +#ifdef CONFIG_USBHOST +# ifdef GPIO_USB_PWRD +# undef GPIO_USB_PWRD +# define GPIO_USB_PWRD (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN22) +# endif +#endif + +/* Alternate pin selections *********************************************************/ +/* Pin Description Connector On Board Base Board + * -------------------------------- --------- -------------- --------------------- + * P0[0]/RD1/TXD3/SDA1 J6-9 I2C E2PROM SDA TXD3/SDA1 + * P0[1]/TD1/RXD3/SCL J6-10 RXD3/SCL1 + * P0[2]/TXD0/AD0[7] J6-21 + * P0[3]/RXD0/AD0[6] J6-22 + * P0[4]/I2SRX-CLK/RD2/CAP2.0 J6-38 CAN_RX2 + * P0[5]/I2SRX-WS/TD2/CAP2.1 J6-39 CAN_TX2 + * P0[6]/I2SRX_SDA/SSEL1/MAT2[0] J6-8 SSEL1, OLED CS + * P0[7]/I2STX_CLK/SCK1/MAT2[1] J6-7 SCK1, OLED SCK + * P0[8]/I2STX_WS/MISO1/MAT2[2] J6-6 MISO1 + * P0[9]/I2STX_SDA/MOSI1/MAT2[3] J6-5 MOSI1, OLED data in + * P0[10] J6-40 TXD2/SDA2 + * P0[11] J6-41 RXD2/SCL2 + * P0[15]/TXD1/SCK0/SCK J6-13 TXD1/SCK0 + * P0[16]/RXD1/SSEL0/SSEL J6-14 RXD1/SSEL0 + * P0[17]/CTS1/MISO0/MISO J6-12 MISO0 + * P0[18]/DCD1/MOSI0/MOSI J6-11 MOSI0 + * P0[19]/DSR1/SDA1 PAD17 N/A + * P0[20]/DTR1/SCL1 PAD18 I2C E2PROM SCL N/A + * P0[21]/RI1/MCIPWR/RD1 J6-23 + * P0[22]/RTS1/TD1 J6-24 LED + * P0[23]/AD0[0]/I2SRX_CLK/CAP3[0] J6-15 AD0.0 + * P0[24]/AD0[1]/I2SRX_WS/CAP3[1] J6-16 AD0.1 + * P0[25]/AD0[2]/I2SRX_SDA/TXD3 J6-17 AD0.2 + * P0[26]/AD0[3]/AOUT/RXD3 J6-18 AD0.3/AOUT / RGB LED + * P0[27]/SDA0/USB_SDA J6-25 + * P0[28]/SCL0 J6-26 + * P0[29]/USB_D+ J6-37 USB_D+ + * P0[30]/USB_D- J6-36 USB_D- + */ + +#define GPIO_UART3_TXD GPIO_UART3_TXD_1 +#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 +#define GPIO_UART3_RXD GPIO_UART3_RXD_1 +#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 +#define GPIO_SSP1_SCK GPIO_SSP1_SCK_1 +#define GPIO_UART2_TXD GPIO_UART2_TXD_1 +#define GPIO_UART2_RXD GPIO_UART2_RXD_1 +#define GPIO_UART1_TXD GPIO_UART1_TXD_1 +#define GPIO_SSP0_SCK GPIO_SSP0_SCK_1 +#define GPIO_UART1_RXD GPIO_UART1_RXD_1 +#define GPIO_SSP0_SSEL GPIO_SSP0_SSEL_1 +#define GPIO_SSP0_MISO GPIO_SSP0_MISO_1 +#define GPIO_SSP0_MOSI GPIO_SSP0_MOSI_1 + +/* P1[0]/ENET-TXD0 J6-34? TXD0 TX-(Ethernet PHY) + * P1[1]/ENET_TXD1 J6-35? TXD1 TX+(Ethernet PHY) + * P1[4]/ENET_TX_EN TXEN N/A + * P1[8]/ENET_CRS CRS_DV/MODE2 N/A + * P1[9]/ENET_RXD0 J6-32? RXD0/MODE0 RD-(Ethernet PHY) + * P1[10]/ENET_RXD1 J6-33? RXD1/MODE1 RD+(Ethernet PHY) + * P1[14]/ENET_RX_ER RXER/PHYAD0 N/A + * P1[15]/ENET_REF_CLK REFCLK N/A + * P1[16]/ENET_MDC MDC N/A + * P1[17]/ENET_MDIO MDIO N/A + * P1[18]/USB_UP_LED/PWM1[1]/CAP1[0] PAD1 N/A + * P1[19]/MC0A/USB_PPWR/N_CAP1.1 PAD2 N/A + * P1[20]/MCFB0/PWM1.2/SCK0 PAD3 N/A + * P1[21]/MCABORT/PWM1.3/SSEL0 PAD4 N/A + * P1[22]/MC0B/USB-PWRD/MAT1.0 PAD5 N/A + * P1[23]/MCFB1/PWM1.4/MISO0 PAD6 N/A + * P1[24]/MCFB2/PWM1.5/MOSI0 PAD7 N/A + * P1[25]/MC1A/MAT1.1 PAD8 N/A + * P1[26]/MC1B/PWM1.6/CAP0.0 PAD9 N/A + * P1[27]/CLKOUT/USB-OVRCR-N/CAP0.1 PAD10 N/A + * P1[28]/MC2A/PCAP1.0/MAT0.0 PAD11 N/A + * P1[29]/MC2B/PCAP1.1/MAT0.1 PAD12 N/A + * P1[30]/VBUS/AD0[4] J6-19 AD0.4 + * P1[31]/SCK1/AD0[5] J6-20 AD0.5 + */ + +#define GPIO_ENET_MDC GPIO_ENET_MDC_1 +#define GPIO_ENET_MDIO GPIO_ENET_MDIO_1 + +/* P2[0]/PWM1.1/TXD1 J6-42 PWM1.1 / RGB LED / RS422 RX + * P2[1]/PWM1.2/RXD1 J6-43 PWM1.2 / OLED voltage / RGB LED / RS422 RX + * P2[2]/PWM1.3/CTS1/TRACEDATA[3] J6-44 PWM1.3 + * P2[3]/PWM1.4/DCD1/TRACEDATA[2] J6-45 PWM1.4 + * P2[4]/PWM1.5/DSR1/TRACEDATA[1] J6-46 PWM1.5 + * P2[5]/PWM1[6]/DTR1/TRACEDATA[0] J6-47 PWM1.6 + * P2[6]/PCAP1[0]/RI1/TRACECLK J6-48 + * P2[7]/RD2/RTS1 J6-49 OLED command/data + * P2[8]/TD2/TXD2 J6-50 + * P2[9]/USB_CONNECT/RXD2 PAD19 USB Pullup N/A + * P2[10]/EINT0/NMI J6-51 + * P2[11]/EINT1/I2STX_CLK J6-52 + * P2[12]/EINT2/I2STX_WS J6-53 + * P2[13]/EINT3/I2STX_SDA J6-27 + */ + +#define GPIO_PWM1p1 GPIO_PWM1p1_2 +#define GPIO_PWM1p2 GPIO_PWM1p2_2 +#define GPIO_PWM1p3 GPIO_PWM1p3_2 +#define GPIO_PWM1p4 GPIO_PWM1p4_2 +#define GPIO_PWM1p5 GPIO_PWM1p5_2 +#define GPIO_PWM1p6 GPIO_PWM1p6_2 + +/* P3[25]/MAT0.0/PWM1.2 PAD13 N/A + * P3[26]/STCLK/MAT0.1/PWM1.3 PAD14 N/A + * + * P4[28]/RX-MCLK/MAT2.0/TXD3 PAD15 N/A + * P4[29]/TX-MCLK/MAT2.1/RXD3 PAD16 N/A + */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc17_led + * + * Description: + * Once the system has booted, these functions can be used to control LEDs 1, 2 & 3 + * + ************************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void lpc17_led(int lednum, int state); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_MCB1700_INCLUDE_BOARD_H */ diff --git a/configs/mcb1700/nsh/defconfig b/configs/mcb1700/nsh/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..547ab51b129a805b3d9ea5f2d6d5306b41453b87 --- /dev/null +++ b/configs/mcb1700/nsh/defconfig @@ -0,0 +1,50 @@ +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_DF_H is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_SPI_EXCHANGE is not set +CONFIG_ARCH_BOARD_MCB1700=y +CONFIG_ARCH_BOARD="mcb1700" +CONFIG_ARCH_CHIP_LPC1768=y +CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="arm" +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=7982 +CONFIG_DISABLE_POLL=y +CONFIG_EXAMPLES_NSH=y +CONFIG_FS_FAT=y +CONFIG_LPC17_SSP0=y +CONFIG_LPC17_UART0=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_MMCSD_SPICLOCK=12500000 +CONFIG_MMCSD=y +CONFIG_MTD=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_RAM_SIZE=32768 +CONFIG_RAM_START=0x10000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SDCLONE_DISABLE=y +CONFIG_SPI=y +CONFIG_START_DAY=18 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2017 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/mcb1700/scripts/Make.defs b/configs/mcb1700/scripts/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..d941ce55d832b71b75e9e59922ed643a6505d450 --- /dev/null +++ b/configs/mcb1700/scripts/Make.defs @@ -0,0 +1,111 @@ +############################################################################ +# configs/mcb1700/scripts/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/mcb1700/scripts/ld.script b/configs/mcb1700/scripts/ld.script new file mode 100644 index 0000000000000000000000000000000000000000..82fc62b72e53dda305f025180dfe30e0178e611f --- /dev/null +++ b/configs/mcb1700/scripts/ld.script @@ -0,0 +1,115 @@ +/**************************************************************************** + * configs/mcb1700/scripts/ld.script + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The LPC1768 has 512Kb of FLASH beginning at address 0x0000:0000 and + * 64Kb of total SRAM: 32Kb of SRAM in the CPU block beginning at address + * 0x10000000 and 32Kb of AHB SRAM in two banks of 16Kb beginning at addresses + * 0x20070000 and 0x20080000. Here we assume that .data and .bss will all fit + * into the 32Kb CPU SRAM address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x10000000, LENGTH = 32K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { /* BSS */ + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/mcb1700/src/.gitignore b/configs/mcb1700/src/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..726d936e1e3390cc875a1fa5681e3c3988fe3c8b --- /dev/null +++ b/configs/mcb1700/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/configs/mcb1700/src/Makefile b/configs/mcb1700/src/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..508ef323b17a293c16214538a2314704d16ab053 --- /dev/null +++ b/configs/mcb1700/src/Makefile @@ -0,0 +1,57 @@ +############################################################################ +# configs/mcb1700/src/Makefile +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = lpc17_boot.c lpc17_bringup.c lpc17_leds.c lpc17_dac.c + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += lpc17_appinit.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += lpc17_usbmsc.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += lpc17_pwm.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += lpc17_adc.c +endif + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/mcb1700/src/lpc17_adc.c b/configs/mcb1700/src/lpc17_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..ab25ba6c37384d9a9aba990aeeca26d6580e089b --- /dev/null +++ b/configs/mcb1700/src/lpc17_adc.c @@ -0,0 +1,112 @@ +/************************************************************************************ + * configs/mcb1700/src/lpc17_adc.c + * + * Based on configs/zkit-arm-176/src/up-adc + * + * Copyright (C) 2013 Zilogic Systems. All rights reserved. + * Author: Kannan + * + * Based on configs/lpc1720g-eval/src/lpc17_adc.c + * + * Copyright (C) 2012, 2014, 2016-2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "up_arch.h" + +#include "lpc17_adc.h" +#include "mcb1700.h" + +#ifdef CONFIG_ADC + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: mcb1700_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +int mcb1700_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Call lpc17_adcinitialize() to get an instance of the ADC interface */ + + adc = lpc17_adcinitialize(); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC */ diff --git a/configs/mcb1700/src/lpc17_appinit.c b/configs/mcb1700/src/lpc17_appinit.c new file mode 100644 index 0000000000000000000000000000000000000000..527f447b783a3ccda9834d56bcc5a366440e5790 --- /dev/null +++ b/configs/mcb1700/src/lpc17_appinit.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * config/mcb1700/src/lpc17_appinit.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "mcb1700.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef OK +# define OK 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_INITIALIZE + /* Board initialization already performed by board_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return mcb1700_bringup(); +#endif +} diff --git a/configs/mcb1700/src/lpc17_boot.c b/configs/mcb1700/src/lpc17_boot.c new file mode 100644 index 0000000000000000000000000000000000000000..3e3f93960437a15216180fba2c3ebe60f02480a4 --- /dev/null +++ b/configs/mcb1700/src/lpc17_boot.c @@ -0,0 +1,95 @@ +/************************************************************************************ + * configs/mcb1700/src/lpc17_boot.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "mcb1700.h" + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc17_boardinitialize + * + * Description: + * All LPC17xx architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void lpc17_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ + /* Perform board-specific initialization */ + + (void)mcb1700_bringup(); +} +#endif diff --git a/configs/mcb1700/src/lpc17_bringup.c b/configs/mcb1700/src/lpc17_bringup.c new file mode 100644 index 0000000000000000000000000000000000000000..6b5da0d75eebd8b6713d851e6499e2842146fcd1 --- /dev/null +++ b/configs/mcb1700/src/lpc17_bringup.c @@ -0,0 +1,375 @@ +/**************************************************************************** + * config/mcb1700/src/lpc17_bringup.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "lpc17_ssp.h" +#include "lpc17_gpio.h" +#include "lpc17_usbhost.h" + +#include "mcb1700.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_MMCSD 1 +#define HAVE_USBHOST 1 + +/* MMC/SD is on SSP port 1. There is only a single slot, slot 0 */ + +#ifdef CONFIG_NSH_ARCHINIT +# if !defined(CONFIG_NSH_MMCSDSPIPORTNO) || CONFIG_NSH_MMCSDSPIPORTNO != 1 +# undef CONFIG_NSH_MMCSDSPIPORTNO +# define CONFIG_NSH_MMCSDSPIPORTNO 1 +# endif + +# if !defined(CONFIG_NSH_MMCSDSLOTNO) || CONFIG_NSH_MMCSDSLOTNO != 0 +# undef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO 0 +# endif + +# ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +# endif + +#else +# undef CONFIG_NSH_MMCSDSPIPORTNO +# define CONFIG_NSH_MMCSDSPIPORTNO 1 +# undef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO 0 +# undef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +#endif + +/* Can't support MMC/SD is SSP1 is not enabled */ + +#ifndef CONFIG_LPC17_SSP1 +# undef HAVE_MMCSD +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef HAVE_MMCSD +#endif + +/* USB Host */ + +#ifdef CONFIG_USBHOST +# ifndef CONFIG_LPC17_USBHOST +# error "CONFIG_LPC17_USBHOST is not selected" +# endif +#endif + +#ifdef CONFIG_LPC17_USBHOST +# ifndef CONFIG_USBHOST +# warning "CONFIG_USBHOST is not selected" +# endif +#endif + +#if !defined(CONFIG_USBHOST) || !defined(CONFIG_LPC17_USBHOST) +# undef HAVE_USBHOST +#endif + +#ifdef HAVE_USBHOST +# ifndef CONFIG_MCB1700_USBHOST_PRIO +# define CONFIG_MCB1700_USBHOST_PRIO 50 +# endif +# ifndef CONFIG_MCB1700_USBHOST_STACKSIZE +# define CONFIG_MCB1700_USBHOST_STACKSIZE 1024 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef HAVE_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nsh_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef HAVE_USBHOST +static int nsh_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + syslog(LOG_INFO, "nsh_waiter: Running\n"); + for (;;) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + syslog(LOG_INFO, "nsh_waiter: %s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + (void)CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Name: nsh_sdinitialize + * + * Description: + * Initialize SPI-based microSD. + * + ****************************************************************************/ + +#ifdef HAVE_MMCSD +static int nsh_sdinitialize(void) +{ + FAR struct spi_dev_s *ssp; + int ret; + + /* Enable power to the SD/MMC via a GPIO. LOW enables SD/MMC. */ + + lpc17_gpiowrite(MCB1700_MMC_PWR, false); + + /* Get the SSP port. MMC/SD is on SSP port 1. */ + + ssp = lpc17_sspbus_initialize(CONFIG_NSH_MMCSDSPIPORTNO); + if (!ssp) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SSP port %d\n", + CONFIG_NSH_MMCSDSPIPORTNO); + ret = -ENODEV; + goto errout; + } + + syslog(LOG_INFO, "Successfully initialized SSP port %d\n", + CONFIG_NSH_MMCSDSPIPORTNO); + + /* Bind the SSP port to the slot */ + + ret = mmcsd_spislotinitialize(CONFIG_NSH_MMCSDMINOR, + CONFIG_NSH_MMCSDSLOTNO, ssp); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SSP port %d to MMC/SD slot %d: %d\n", + CONFIG_NSH_MMCSDSPIPORTNO, + CONFIG_NSH_MMCSDSLOTNO, ret); + goto errout; + } + + syslog(LOG_INFO, "Successfully bound SSP port %d to MMC/SD slot %d\n", + CONFIG_NSH_MMCSDSPIPORTNO, + CONFIG_NSH_MMCSDSLOTNO); + return OK; + + /* Disable power to the SD/MMC via a GPIO. HIGH disables SD/MMC. */ + +errout: + lpc17_gpiowrite(MCB1700_MMC_PWR, true); + return ret; +} +#else +# define nsh_sdinitialize() (OK) +#endif + +/**************************************************************************** + * Name: nsh_usbhostinitialize + * + * Description: + * Initialize SPI-based microSD. + * + ****************************************************************************/ + +#ifdef HAVE_USBHOST +static int nsh_usbhostinitialize(void) +{ + int pid; + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + syslog(LOG_INFO, "Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Initialize mass storage support */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + UNUSED(ret); + + /* Then get an instance of the USB host interface */ + + syslog(LOG_INFO, "Initialize USB host\n"); + g_usbconn = lpc17_usbhost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + syslog(LOG_ERR, "ERROR: Start nsh_waiter\n"); + + pid = task_create("usbhost", CONFIG_MCB1700_USBHOST_PRIO, + CONFIG_MCB1700_USBHOST_STACKSIZE, + (main_t)nsh_waiter, (FAR char * const *)NULL); + return pid < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#else +# define nsh_usbhostinitialize() (OK) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mcb1700_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int mcb1700_bringup(void) +{ + int ret; + + /* Initialize SPI-based microSD */ + + ret = nsh_sdinitialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI-based SD card: %d\n", ret); + } + + /* Initialize USB host */ + + ret = nsh_usbhostinitialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + } + +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ + + ret = lpc1766stk_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: lpc1766stk_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + + return ret; +} diff --git a/configs/mcb1700/src/lpc17_dac.c b/configs/mcb1700/src/lpc17_dac.c new file mode 100644 index 0000000000000000000000000000000000000000..f64abe1ab9c2440ca90593931800cb4b4e820ad8 --- /dev/null +++ b/configs/mcb1700/src/lpc17_dac.c @@ -0,0 +1,101 @@ +/************************************************************************************ + * configs/mcb1700/src/lpc17_dac.c + * + * Based on configs/zkit-arm-1769/src/lpc17_dac.c + * + * Copyright (C) 2013 Zilogic Systems. All rights reserved. + * Author: Kannan + * + * Based on configs/stm3220g-eval/src/stm32_dac.c + * + * Copyright (C) 2012, 2014, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc17_dac.h" + +#ifdef CONFIG_DAC + +/************************************************************************************ + * Name: dac_devinit + * + * Description: + * All LPC17xx architectures must provide the following interface to work with + * examples/diag. + * + ************************************************************************************/ + +int dac_devinit(void) +{ + static bool initialized = false; + struct dac_dev_s *dac; + int ret; + + if (!initialized) + { + /* Call lpc17_dacinitialize() to get an instance of the dac interface */ + + dac = lpc17_dacinitialize(); + if (dac == NULL) + { + aerr("ERROR: Failed to get dac interface\n"); + return -ENODEV; + } + + ret = dac_register("/dev/dac0", dac); + if (ret < 0) + { + aerr("ERROR: dac_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_DAC */ diff --git a/configs/mcb1700/src/lpc17_leds.c b/configs/mcb1700/src/lpc17_leds.c new file mode 100644 index 0000000000000000000000000000000000000000..ac4075e7db278f214fa2afc6d10a4345fb1decbe --- /dev/null +++ b/configs/mcb1700/src/lpc17_leds.c @@ -0,0 +1,200 @@ +/**************************************************************************** + * configs/mcb1700/src/lpc17_leds.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc17_gpio.h" + +#include "mcb1700.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Dump GPIO registers */ + +#ifdef CONFIG_DEBUG_LEDS_INFO +# define led_dumpgpio(m) lpc17_dumpgpio(MCB1700_LED3, m) +#else +# define led_dumpgpio(m) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* LED definitions **********************************************************/ +/* The MCB1700 has 4 LEDs along the bottom of the board. Blue or off. + * If CONFIG_ARCH_LEDS is defined, the LEDs will be controlled as follows + * for NuttX debug functionality (where NC means "No Change"). + * + * During the boot phases. LED1 and LED2 will show boot status. LED3/4 Not + * used. + * + * LED1 LED2 + * STARTED OFF OFF + * HEAPALLOCATE BLUE OFF + * IRQSENABLED OFF BLUE + * STACKCREATED OFF OFF + * + * After the system is booted, this logic will no longer use LEDs 1 & 2. + * They are available together with LED3 for use the application software + * using lpc17_led (prototyped below) + */ + +static bool g_initialized; +static int g_nestcount; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure all LED GPIO lines */ + + led_dumpgpio("board_autoled_initialize() Entry)"); + + lpc17_configgpio(MCB1700_LED1); + lpc17_configgpio(MCB1700_LED2); + lpc17_configgpio(MCB1700_LED3); + lpc17_configgpio(MCB1700_LED4); + + led_dumpgpio("board_autoled_initialize() Exit"); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + /* We will control LED1 and LED2 not yet completed the boot sequence. */ + + if (!g_initialized) + { + int led1 = 0; + int led2 = 0; + + switch (led) + { + case LED_STACKCREATED: + g_initialized = true; + case LED_STARTED: + default: + break; + + case LED_HEAPALLOCATE: + led1 = 1; + break; + + case LED_IRQSENABLED: + led2 = 1; + } + + lpc17_led(MCB1700_LED1,led1); + lpc17_led(MCB1700_LED2,led2); + } + + /* We will always control the HB LED */ + + switch (led) + { + case LED_INIRQ: + case LED_SIGNAL: + case LED_ASSERTION: + case LED_PANIC: + lpc17_gpiowrite(MCB1700_HEARTBEAT, false); + g_nestcount++; + + default: + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + /* In all states, OFF can only mean turning off the HB LED */ + + if (g_nestcount <= 1) + { + lpc17_led(MCB1700_HEARTBEAT, true); + g_nestcount = 0; + } + else + { + g_nestcount--; + } +} + +/************************************************************************************ + * Name: lpc17_led + * + * Description: + * Once the system has booted, these functions can be used to control the LEDs + * + ************************************************************************************/ + +void lpc17_led(int lednum, int state) + +{ + lpc17_gpiowrite(lednum, state); +} +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/mcb1700/src/lpc17_pwm.c b/configs/mcb1700/src/lpc17_pwm.c new file mode 100644 index 0000000000000000000000000000000000000000..f7e241c20ab180a4b6050e72d63c67a97593e3b4 --- /dev/null +++ b/configs/mcb1700/src/lpc17_pwm.c @@ -0,0 +1,151 @@ +/************************************************************************************ + * configs/mcb1700/lpc17_pwm.c + * + * Based on configs/lpcexpresso-lpc1768/lpc17_pwm.c + * + * Copyright (C) 2014-2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "up_arch.h" +#include "lpc17_pwm.h" +#include "lpc17_timer.h" +#include "mcb1700.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#ifdef CONFIG_PWM + +FAR struct pwm_lowerhalf_s *lpc17_pwminitialize(int timer); +FAR struct pwm_lowerhalf_s *lpc17_mcpwminitialize(int timer); +FAR struct pwm_lowerhalf_s *lpc17_timerinitialize(int timer); + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: mcb1700_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +int mcb1700_pwm_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + struct pwm_lowerhalf_s *mcpwm; + struct pwm_lowerhalf_s *timer; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call lpc17_pwminitialize() to get an instance of the PWM interface */ + + pwm = lpc17_pwminitialize(0); + if (!pwm) + { + aerr("ERROR: Failed to get the LPC17XX PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + mcpwm = lpc17_mcpwminitialize(0); + if (!mcpwm) + { + aerr("ERROR: Failed to get the LPC17XX MOTOR PWM lower half\n"); + return -ENODEV; + } + + /* Register the MOTOR CONTROL PWM driver at "/dev/mcpwm0" */ + + ret = pwm_register("/dev/mcpwm0", mcpwm); + if (ret < 0) + { + aerr("ERROR: mcpwm_register failed: %d\n", ret); + return ret; + } + + timer = lpc17_timerinitialize(0); + if (!timer) + { + aerr("ERROR: Failed to get the LPC17XX TIMER lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/timer0" */ + + ret = pwm_register("/dev/timer0", timer); + if (ret < 0) + { + aerr("ERROR: timer_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_PWM */ diff --git a/configs/mcb1700/src/mcb1700.h b/configs/mcb1700/src/mcb1700.h new file mode 100644 index 0000000000000000000000000000000000000000..481cbbc5e888236e6b5130e3b3093e1137c10906 --- /dev/null +++ b/configs/mcb1700/src/mcb1700.h @@ -0,0 +1,125 @@ +/************************************************************************************ + * configs/mcb1700/src/mcb1700.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef _CONFIGS_MCB1700_SRC_MCB1700_H +#define _CONFIGS_MCB1700_SRC_MCB1700_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* MCB1700 GPIO Pin Definitions *****************************************************/ + +#define MCB1700_LED1 (GPIO_OUTPUT | GPIO_PORT1 | GPIO_PIN18) +#define MCB1700_LED1_OFF MCB1700_LED1 +#define MCB1700_LED1_ON (MCB1700_LED1 | GPIO_VALUE_ONE) +#define MCB1700_LED2 (GPIO_OUTPUT | GPIO_PORT1 | GPIO_PIN20) +#define MCB1700_LED2_OFF MCB1700_LED2 +#define MCB1700_LED2_ON (MCB1700_LED2 | GPIO_VALUE_ONE) +#define MCB1700_LED3 (GPIO_OUTPUT | GPIO_PORT1 | GPIO_PIN21) +#define MCB1700_LED3_OFF MCB1700_LED3 +#define MCB1700_LED3_ON (MCB1700_LED3 | GPIO_VALUE_ONE) +#define MCB1700_LED4 (GPIO_OUTPUT | GPIO_PORT1 | GPIO_PIN23) +#define MCB1700_LED4_OFF MCB1700_LED4 +#define MCB1700_LED4_ON (MCB1700_LED 4| GPIO_VALUE_ONE) + +#define MCB1700_HEARTBEAT MCB1700_LED4 + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/**************************************************************************** + * Name: mcb1700_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int mcb1700_bringup(void); + +/************************************************************************************ + * Name: mcb1700_sspdev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the NUCLEUS-2G board. + * + ************************************************************************************/ + +void weak_function mcb1700_sspdev_initialize(void); + +/************************************************************************************ + * Name: mcb1700_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int mcb1700_pwm_setup(void); +#endif + +/************************************************************************************ + * Name: mcb1700_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int mcb1700_adc_setup(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* _CONFIGS_MCB1700_SRC_MCB1700_H */ + diff --git a/configs/mikroe-stm32f4/Kconfig b/configs/mikroe-stm32f4/Kconfig index 00a5e41ee4744b0f04a42f368a6e3e59a9a12f4c..077035585251008f84e008f727ed13988be7b5b8 100644 --- a/configs/mikroe-stm32f4/Kconfig +++ b/configs/mikroe-stm32f4/Kconfig @@ -79,7 +79,7 @@ config MIKROE_RAMMTD_SIZE config MIKROE_QETIMER int "Timer to use with QE encoder" default 3 - depends on QENCODER + depends on SENSORS_QENCODER config PM_ALARM_SEC int "PM_STANDBY delay (seconds)" diff --git a/configs/mikroe-stm32f4/README.txt b/configs/mikroe-stm32f4/README.txt index 54c4fd9ef57f60da28f1b83e08046a2d8173b169..ba8785879e4edaf9c76b2a415fe6c47e916db524 100644 --- a/configs/mikroe-stm32f4/README.txt +++ b/configs/mikroe-stm32f4/README.txt @@ -20,12 +20,6 @@ about this board. Contents ======== - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - LEDs - PWM - UARTs @@ -36,235 +30,6 @@ Contents - Mikroe-STM32F4-specific Configuration Options - Configurations -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. - -GNU Toolchain Options -===================== - - Toolchain Configurations - ------------------------ - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The Atollic Toolchain, - 3. The devkitARM GNU toolchain, - 4. Raisonance GNU toolchain, or - 5. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the CodeSourcery toolchain for Linux. To use - the Atollic, devkitARM, Raisonance GNU, or NuttX buildroot toolchain, you simply need to - add one of the following configuration options to your .config (or defconfig) - file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : The Atollic toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE=y : Raisonance RIDE7 under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - NOTE: the CodeSourcery (for Windows), Atollic, devkitARM, and Raisonance toolchains are - Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - The CodeSourcery Toolchain (2009q1) - ----------------------------------- - The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - The Atollic "Pro" and "Lite" Toolchain - -------------------------------------- - One problem that I had with the Atollic toolchains is that the provide a gcc.exe - and g++.exe in the same bin/ file as their ARM binaries. If the Atollic bin/ path - appears in your PATH variable before /usr/bin, then you will get the wrong gcc - when you try to build host executables. This will cause to strange, uninterpretable - errors build some host binaries in tools/ when you first make. - - Also, the Atollic toolchains are the only toolchains that have built-in support for - the FPU in these configurations. If you plan to use the Cortex-M4 FPU, you will - need to use the Atollic toolchain for now. See the FPU section below for more - information. - - The Atollic "Lite" Toolchain - ---------------------------- - The free, "Lite" version of the Atollic toolchain does not support C++ nor - does it support ar, nm, objdump, or objdcopy. If you use the Atollic "Lite" - toolchain, you will have to set: - - CONFIG_HAVE_CXX=n - - In order to compile successfully. Otherwise, you will get errors like: - - "C++ Compiler only available in TrueSTUDIO Professional" - - The make may then fail in some of the post link processing because of some of - the other missing tools. The Make.defs file replaces the ar and nm with - the default system x86 tool versions and these seem to work okay. Disable all - of the following to avoid using objcopy: - - CONFIG_RRLOAD_BINARY=n - CONFIG_INTELHEX_BINARY=n - CONFIG_MOTOROLA_SREC=n - CONFIG_RAW_BINARY=n - - devkitARM - --------- - The devkitARM toolchain includes a version of MSYS make. Make sure that the - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/stm32, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by RIDE. - -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh mikroe-stm32f4/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh mikroe-stm32f4/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - LEDs ==== diff --git a/configs/mikroe-stm32f4/fulldemo/defconfig b/configs/mikroe-stm32f4/fulldemo/defconfig index 55ea6f44f519ae2fd7654043bcaa852074fe4fd4..0896fb141259e03b54aaff1536d048b323e03b03 100644 --- a/configs/mikroe-stm32f4/fulldemo/defconfig +++ b/configs/mikroe-stm32f4/fulldemo/defconfig @@ -3,6 +3,7 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXPLAYER_INCLUDE_PREFERRED_DEVICE is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set # CONFIG_STM32_CCMEXCLUDE is not set @@ -98,7 +99,6 @@ CONFIG_NXWM_KEYBOARD_DEVPATH="/dev/ttyS0" CONFIG_NXWM_KEYBOARD_LISTENERPRIO=100 CONFIG_NXWM_KEYBOARD=y CONFIG_NXWM_MEDIAPLAYER=y -CONFIG_NXWM_STARTWINDOW_MQNAME="nxwm" CONFIG_NXWM_TASKBAR_LEFT=y CONFIG_NXWM_TOUCHSCREEN_CONFIGDATA=y CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=100 diff --git a/configs/mikroe-stm32f4/include/board.h b/configs/mikroe-stm32f4/include/board.h index a985f31e5048cef124e7c3220c58d49c03d50fa7..3928cebe331fbd2a5ff4e733d6e3c4d76e06de9c 100644 --- a/configs/mikroe-stm32f4/include/board.h +++ b/configs/mikroe-stm32f4/include/board.h @@ -257,39 +257,4 @@ #define GPIO_TIM8_CH1IN GPIO_TIM8_CH1IN_1 #define GPIO_TIM8_CH2IN GPIO_TIM8_CH2IN_1 -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_MIKROE_STM32F4_INCLUDE_BOARD_H */ diff --git a/configs/mikroe-stm32f4/nx/defconfig b/configs/mikroe-stm32f4/nx/defconfig index c727a654a59b4515d19d4e795f53fc78e0fbea4b..e7a3b73ef8cad4c4f4efd8942c5eebc88b157126 100644 --- a/configs/mikroe-stm32f4/nx/defconfig +++ b/configs/mikroe-stm32f4/nx/defconfig @@ -4,6 +4,7 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set # CONFIG_SERIAL is not set CONFIG_ARCH_BOARD_MIKROE_STM32F4=y diff --git a/configs/mikroe-stm32f4/nxlines/defconfig b/configs/mikroe-stm32f4/nxlines/defconfig index f6564df8814a7c6777b76748ca093839620b9ded..cce7ac96fe5c2010100b336cf72e51a012eacec1 100644 --- a/configs/mikroe-stm32f4/nxlines/defconfig +++ b/configs/mikroe-stm32f4/nxlines/defconfig @@ -6,6 +6,7 @@ # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set # CONFIG_NX_WRITEONLY is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set # CONFIG_SERIAL is not set CONFIG_ARCH_BOARD_MIKROE_STM32F4=y diff --git a/configs/mikroe-stm32f4/nxtext/defconfig b/configs/mikroe-stm32f4/nxtext/defconfig index 1498198d0cbfa110ef5972f1bc3c56d248259de4..b9e1474e943e4ecf9b43915a17d34ddce63b8e7a 100644 --- a/configs/mikroe-stm32f4/nxtext/defconfig +++ b/configs/mikroe-stm32f4/nxtext/defconfig @@ -4,6 +4,7 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set # CONFIG_SERIAL is not set CONFIG_ARCH_BOARD_MIKROE_STM32F4=y diff --git a/configs/ne64badge/include/board.h b/configs/ne64badge/include/board.h index ddd8ea47aa30487f1cd859553451b14849f2fe1e..6288711639cc2f1acfb15ef689f90c4899f28b82 100644 --- a/configs/ne64badge/include/board.h +++ b/configs/ne64badge/include/board.h @@ -98,39 +98,4 @@ #define BUTTON1 1 /* Bit 0: SW1 button is depressed */ #define BUTTON2 2 /* Bit 1: SW2 button is depressed */ -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: hcs12_boardinitialize - * - * Description: - * All HCS12 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void hcs12_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/nr5m100-nexys4/include/board.h b/configs/nr5m100-nexys4/include/board.h index 0d2dd772f34bf995632c8da69cf693c7f977cdc2..55b16f5fcd0cd8aa30c3fe1f53b6afbe295ea163 100644 --- a/configs/nr5m100-nexys4/include/board.h +++ b/configs/nr5m100-nexys4/include/board.h @@ -139,17 +139,6 @@ extern "C" /************************************************************************************ * Public Function Prototypes ************************************************************************************/ -/************************************************************************************ - * Name: nr5_boardinitialize - * - * Description: - * All NR5 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void nr5_boardinitialize(void); /************************************************************************************ * Name: nr5_ledinit, nr5_setled, and nr5_setleds diff --git a/configs/nucleo-144/Kconfig b/configs/nucleo-144/Kconfig index a6ac8ffbed79291b20c65abb05da7291b746d96a..f5feba81927b6a5994d82b42c35eaa18e41aa789 100644 --- a/configs/nucleo-144/Kconfig +++ b/configs/nucleo-144/Kconfig @@ -40,12 +40,24 @@ choice STM32F7 MORPHO FUNCTION GPIO -------- --------- ----- - CN12-64 USART8_RX PE0 - CN11-61 USART8_TX PE1 + CN12-64 UART8_RX PE0 + CN11-61 UART8_TX PE1 -------- --------- ----- + OR + + Morpho Connector UART4: + + STM32F7 + MORPHO FUNCTION GPIO + -------- --------- ----- + CN11-30 UART4_RX PA0 + CN11-28 UART4_TX PA1 + -------- --------- ----- + Note: SB13 must be removed to disable Ethernet. + config NUCLEO_CONSOLE_ARDUINO - bool "ARDUINO Connector" + bool "Arduino Connector" select STM32F7_USART6 select USART6_SERIALDRIVER select USART6_SERIAL_CONSOLE @@ -62,6 +74,12 @@ config NUCLEO_CONSOLE_MORPHO select UART8_SERIALDRIVER select UART8_SERIAL_CONSOLE +config NUCLEO_CONSOLE_MORPHO_UART4 + bool "Morpho Connector UART4" + select STM32F7_UART4 + select UART4_SERIALDRIVER + select UART4_SERIAL_CONSOLE + config NUCLEO_CONSOLE_NONE bool "No Console" diff --git a/configs/nucleo-144/README.txt b/configs/nucleo-144/README.txt index 37980943c68e3802a2cc0a11a5fb37d6d2873cd3..dbac5556f7d20f10bae560926ea76d5f38bfebcb 100644 --- a/configs/nucleo-144/README.txt +++ b/configs/nucleo-144/README.txt @@ -10,6 +10,7 @@ Contents ======== - Nucleo-144 Boards + - Nucleo F722ZE - Nucleo F746ZG - Nucleo F767ZI - Development Environment @@ -38,6 +39,7 @@ LQFP144 package. Variants include STM32F303ZET6 NUCLEO-F303ZE STM32F429ZIT6 NUCLEO-F429ZI STM32F446ZET6 NUCLEO-F446ZE + STM32F722ZET6 NUCLEO-F722ZE STM32F746ZGT6 NUCLEO-F746ZG STM32F767ZIT6 NUCLEO-F767ZI STM32L496ZGT6 NUCLEO-L496ZG @@ -229,10 +231,11 @@ Hardware debugging. Because so many pins can be multiplexed with so many functions, the above mentioned graphic may be helpful in indentifying a serial port. - There are 4 choices that can be made from the menuconfig: + There are 5 choices that can be made from the menuconfig: CONFIG_NUCLEO_CONSOLE_ARDUINO or CONFIG_NUCLEO_CONSOLE_MORPHO or - CONFIG_NUCLEO_CONSOLE_VIRTUAL or CONFIG_NUCLEO_CONSOLE_NONE + CONFIG_NUCLEO_CONSOLE_MORPHO_UART4 or CONFIG_NUCLEO_CONSOLE_VIRTUAL or + CONFIG_NUCLEO_CONSOLE_NONE The CONFIG_NUCLEO_CONSOLE_NONE makes no preset for the console. YOu shuld still visit the U[S]ART selection and Device Drivers to disable any U[S]ART reamaing. @@ -256,6 +259,14 @@ Hardware SERIAL_RX PE_0 SERIAL_TX PE_1 + The CONFIG_NUCLEO_CONSOLE_MORPHO_UART4 configurations uses Serial Port 4 (UART4) + with TX on PA1 and RX on PA0. Zero Ohm resistor / solder short at + SB13 must be removed/open. (Disables Ethernet MII clocking.) + Serial + ------ + SERIAL_RX PA_1 CN11 30 + SERIAL_TX PA_0 CN11 28 + The CONFIG_NUCLEO_CONSOLE_VIRTUAL configurations uses Serial Port 3 (USART3) with TX on PD8 and RX on PD9. Serial @@ -514,10 +525,29 @@ f7xx-nsh: CONFIG_HOST_LINUX=y : Builds under Linux CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y : ARM GNU for Linux - 3. Although the default console is USART3 (which would correspond to - the Virtual COM port) I have done all testing with the console - device configured for UART8 (see instruction above under "Serial - Consoles). + 3. The serial console may be configured to use either USART3 (which would + correspond to the Virtual COM port) or with the console device + configured for USART6 to support an Arduino serial shield (see + instructions above under "Serial Consoles). You will need to check the + defconfig file to see how the console is set up and, perhaps, modify + the configuration accordingly. + + To select the Virtual COM port: + + -CONFIG_NUCLEO_CONSOLE_ARDUINO + +CONFIG_NUCLEO_CONSOLE_VIRTUAL=y + -CONFIG_USART6_SERIAL_CONSOLE=y + +CONFIG_USART3_SERIAL_CONSOLE=y + + To select the Arduino serial shield: + + -CONFIG_NUCLEO_CONSOLE_VIRTUAL=y + +CONFIG_NUCLEO_CONSOLE_ARDUINO + -CONFIG_USART3_SERIAL_CONSOLE=y + +CONFIG_USART6_SERIAL_CONSOLE=y + + Default values for other settings associated with the select USART should + be correct. f7xx-evalos: ------- diff --git a/configs/nucleo-144/f722-nsh/Make.defs b/configs/nucleo-144/f722-nsh/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..1f4e23615ba36b2dab2dbbb2721568e816cf20c0 --- /dev/null +++ b/configs/nucleo-144/f722-nsh/Make.defs @@ -0,0 +1,115 @@ +############################################################################ +# configs/nucleo-144/f722-nsh/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Authors: Gregory Nutt +# David Sidrane +# Bob Feretich +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +# Change Log: +# bf20171114 Added support for nucleo-144 stm32f72ze +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = f722-flash.ld + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/configs/nucleo-144/f722-nsh/defconfig b/configs/nucleo-144/f722-nsh/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..2953e64237a1a5ca6a28051960a7aa0a2ff82c11 --- /dev/null +++ b/configs/nucleo-144/f722-nsh/defconfig @@ -0,0 +1,51 @@ +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH_BOARD_NUCLEO_144=y +CONFIG_ARCH_BOARD="nucleo-144" +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP_STM32F7=y +CONFIG_ARCH_CHIP_STM32F722ZE=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="arm" +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POLL=y +CONFIG_EXAMPLES_NSH=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SERIAL_DISABLE_REORDERING=y +CONFIG_SPI=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2015 +CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32F7_USART_BREAKS=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/nucleo-144/f746-nsh/defconfig b/configs/nucleo-144/f746-nsh/defconfig index 2327a1d8e109388ffc662a60b4552bb3d74875a3..f63691d12167ff450417c1e18ef891b31fb0620f 100644 --- a/configs/nucleo-144/f746-nsh/defconfig +++ b/configs/nucleo-144/f746-nsh/defconfig @@ -28,6 +28,7 @@ CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 CONFIG_NSH_READLINE=y +CONFIG_NUCLEO_CONSOLE_VIRTUAL=y CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_WDOGS=4 @@ -46,6 +47,6 @@ CONFIG_START_YEAR=2015 CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y CONFIG_STM32F7_USART_BREAKS=y CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/nucleo-144/include/board.h b/configs/nucleo-144/include/board.h index ac06c1fca973b3fb194f14267ed31dcf201239fe..974cb73c9e3a7b81a20f9b0dc2f5f42b061e2500 100644 --- a/configs/nucleo-144/include/board.h +++ b/configs/nucleo-144/include/board.h @@ -1,10 +1,11 @@ /************************************************************************************ * configs/nucleo-144/include/board.h * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * Mark Olsson * David Sidrane + * Bob Feretich * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -374,6 +375,36 @@ # define GPIO_USART3_TX GPIO_USART3_TX_3 #endif +#if defined(CONFIG_NUCLEO_CONSOLE_MORPHO_UART4) +/* UART4: + * + * This configuration assumes that you disabled Ethernet MII clocking + * by removing SB13 to free PA1. + * + * -------- --------------- + * STM32F7 + * Pin FUNCTION GPIO + * ------- --------- ----- + * CN11 30 UART4_RX PA1 + * CN11 28 UART4_TX PA0 + * ------- --------- ----- + */ + + # define GPIO_UART4_RX GPIO_UART4_RX_1 + # define GPIO_UART4_TX GPIO_UART4_TX_1 + +/* USART3 seems to be forced selected by the Nucleo-F746ZG kconfig - bug */ + + # define GPIO_USART3_RX GPIO_USART3_RX_1 + # define GPIO_USART3_TX GPIO_USART3_TX_1 + +/* USART6 seems to be forced selected by the Nucleo-F722E kconfig - bug */ + + # define GPIO_USART6_RX GPIO_USART6_RX_2 + # define GPIO_USART6_TX GPIO_USART6_TX_2 + +#endif + /* USART8: * * This configurations assume that you are connecting to the Morpho connector @@ -467,40 +498,4 @@ #define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2 #define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_1 -/************************************************************************************ - * Public Data - ************************************************************************************/ -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_NUCLEO_144_INCLUDE_BOARD_H */ diff --git a/configs/nucleo-144/scripts/f722-flash.ld b/configs/nucleo-144/scripts/f722-flash.ld new file mode 100644 index 0000000000000000000000000000000000000000..d89c3c43bb021578417e62b51ab0ec54736892aa --- /dev/null +++ b/configs/nucleo-144/scripts/f722-flash.ld @@ -0,0 +1,148 @@ +/**************************************************************************** + * configs/nucleo-144/scripts/f722-flash.ld + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Bob Feretich + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Change Log: + * bf20171114 Created from configs/nucleo-144/scripts/f746-flash.ld + ****************************************************************************/ + +/* The STM32F722ZE has 512 KiB of main FLASH memory. This FLASH memory + * can be accessed from either the AXIM interface at address 0x0800:0000 or + * from the ITCM interface at address 0x0020:0000. + * + * Additional information, including the option bytes, is available at at + * FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM). + * + * In the STM32F722ZE, two different boot spaces can be selected through + * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and + * BOOT_ADD1 option bytes: + * + * 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0]. + * ST programmed value: Flash on ITCM at 0x0020:0000 + * 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0]. + * ST programmed value: System bootloader at 0x0010:0000 + * + * NuttX does not modify these option byes. On the unmodified NUCLEO-144 + * board, the BOOT0 pin is at ground so by default, the STM32F722ZE will + * boot from address 0x0020:0000 in ITCM FLASH. + * + * The STM32F722ZE also has 256 KiB of data SRAM (in addition to ITCM SRAM). + * SRAM is split up into three blocks: + * + * 1) 64 KiB of DTCM SRM beginning at address 0x2000:0000 + * 2) 176 KiB of SRAM1 beginning at address 0x2001:0000 + * 3) 16 KiB of SRAM2 beginning at address 0x2003:c000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + itcm (rwx) : ORIGIN = 0x00200000, LENGTH = 512K + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 64K + sram1 (rwx) : ORIGIN = 0x20010000, LENGTH = 176K + sram2 (rwx) : ORIGIN = 0x2003c000, LENGTH = 16K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram1 AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram1 + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/nucleo-f303re/include/board.h b/configs/nucleo-f303re/include/board.h index 0960f3e6b0af8ecd2cbdad27c2319c5bd8727584..f3760cf12f099597f50294bafeca410e0d2f4621 100644 --- a/configs/nucleo-f303re/include/board.h +++ b/configs/nucleo-f303re/include/board.h @@ -246,37 +246,4 @@ #define ADC3_DMA_CHAN DMACHAN_ADC3 #define ADC4_DMA_CHAN DMACHAN_ADC4_1 -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_NUCLEO_F303RE_INCLUDE_BOARD_H */ diff --git a/configs/nucleo-f303re/nxlines/defconfig b/configs/nucleo-f303re/nxlines/defconfig index 33c68965c7a2d12e7b5e90a5c28362837b7d3c88..202b6004911c094b2b59b760b89825b01a1eceb6 100644 --- a/configs/nucleo-f303re/nxlines/defconfig +++ b/configs/nucleo-f303re/nxlines/defconfig @@ -1,6 +1,7 @@ # CONFIG_ARCH_FPU is not set # CONFIG_DEV_CONSOLE is not set # CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_SERIAL is not set CONFIG_ARCH_BOARD_NUCLEO_F303RE=y CONFIG_ARCH_BOARD="nucleo-f303re" diff --git a/configs/nucleo-f334r8/highpri/defconfig b/configs/nucleo-f334r8/highpri/defconfig index 6f17e7fceaab1257825d88d9894e49360a627de3..d3623b06c9d12e90c15c94bd8fc38448e4b92a19 100644 --- a/configs/nucleo-f334r8/highpri/defconfig +++ b/configs/nucleo-f334r8/highpri/defconfig @@ -94,6 +94,8 @@ CONFIG_STM32_HRTIM1=y CONFIG_STM32_HRTIM_CLK_FROM_PLL=y CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y CONFIG_STM32_HRTIM_TIMA=y +CONFIG_STM32_HRTIM_ADC=y +CONFIG_STM32_HRTIM_ADC1_TRG1=y CONFIG_STM32_JTAG_SW_ENABLE=y CONFIG_STM32_PWR=y CONFIG_STM32_USART2=y diff --git a/configs/nucleo-f334r8/include/board.h b/configs/nucleo-f334r8/include/board.h index 13be4556a98421507c01036dead49191b54f7d6c..4dc9d283b129fe9ad3a5b756e16bec6020279b3c 100644 --- a/configs/nucleo-f334r8/include/board.h +++ b/configs/nucleo-f334r8/include/board.h @@ -270,38 +270,4 @@ #endif /* CONFIG_NUCLEOF334R8_HIGHPRI */ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_NUCLEO_F334R8_INCLUDE_BOARD_H */ diff --git a/configs/nucleo-f334r8/scripts/ld.script b/configs/nucleo-f334r8/scripts/ld.script index 6c11be015b8158fd3a910efbab2fb139cfceb926..76f4c361dc730f6bfd1019fe734321e43abf66a3 100644 --- a/configs/nucleo-f334r8/scripts/ld.script +++ b/configs/nucleo-f334r8/scripts/ld.script @@ -85,6 +85,12 @@ SECTIONS _eronly = ABSOLUTE(.); + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + .data : { _sdata = ABSOLUTE(.); *(.data .data.*) diff --git a/configs/nucleo-f334r8/src/stm32_highpri.c b/configs/nucleo-f334r8/src/stm32_highpri.c index 5b94415a5f585e40a3a5c2f90e40134b3ef77763..620181766d471c8014cb5ef11d6e9fc05003744f 100644 --- a/configs/nucleo-f334r8/src/stm32_highpri.c +++ b/configs/nucleo-f334r8/src/stm32_highpri.c @@ -53,7 +53,6 @@ #include "up_internal.h" #include "ram_vectors.h" -#include "stm32_tim.h" #include #include @@ -106,11 +105,6 @@ #define ADC_REF_VOLTAGE 3.3 #define ADC_VAL_MAX 4095 -#define HRTIM_CMP_SET(hrtim, tim, index, cmp) \ - hrtim->hd_ops->cmp_update(hrtim, tim, index, cmp) -#define HRTIM_PER_SET(hrtim, tim, per) \ - hrtim->hd_ops->per_update(hrtim, tim, per) - /**************************************************************************** * Private Types ****************************************************************************/ @@ -129,6 +123,10 @@ struct highpri_s float volt[DEV1_NCHANNELS]; }; +/**************************************************************************** + * Private Data + ****************************************************************************/ + /* ADC channel list */ static const uint8_t g_chanlist1[DEV1_NCHANNELS] = @@ -152,10 +150,6 @@ static const uint32_t g_pinlist1[DEV1_NCHANNELS] = #endif }; -/**************************************************************************** - * Private Data - ****************************************************************************/ - static struct highpri_s g_highpri; /**************************************************************************** @@ -201,7 +195,6 @@ void adc12_handler(void) } adc->ops->int_ack(adc, pending); - } #endif diff --git a/configs/nucleo-f410rb/include/board.h b/configs/nucleo-f410rb/include/board.h index ab55f5b521837d1008980ffd59c090c1f9d38caf..7369b778c3b08cad781df4f92372cb8c63af9253 100644 --- a/configs/nucleo-f410rb/include/board.h +++ b/configs/nucleo-f410rb/include/board.h @@ -308,40 +308,4 @@ #define BUTTON_USER_BIT (1 << BUTTON_USER) -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_NUCLEO_F410RB_INCLUDE_BOARD_H */ diff --git a/configs/nucleo-f4x1re/Kconfig b/configs/nucleo-f4x1re/Kconfig index 27e172d8418b5c105ff4dd87b3a343178e2bb994..f68500d5006429b3ef979e989c9f4781d91c3676 100644 --- a/configs/nucleo-f4x1re/Kconfig +++ b/configs/nucleo-f4x1re/Kconfig @@ -8,7 +8,7 @@ if ARCH_BOARD_NUCLEO_F401RE config NUCLEO_F401RE_QETIMER int "Timer to use with QE encoder" default 3 - depends on QENCODER + depends on SENSORS_QENCODER config NUCLEO_F401RE_AJOY_MINBUTTONS bool "Minimal Joystick Buttons" diff --git a/configs/nucleo-f4x1re/include/board.h b/configs/nucleo-f4x1re/include/board.h index 888e79c9a5c72f49bd6e9c5b25bb2217099561d4..577dfaa180ad6dcff79b172c87645f84304f00d2 100644 --- a/configs/nucleo-f4x1re/include/board.h +++ b/configs/nucleo-f4x1re/include/board.h @@ -219,40 +219,4 @@ #define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP) #define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP) -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_NUCLEO_F401RE_INCLUDE_BOARD_H */ diff --git a/configs/nucleo-l496zg/include/board.h b/configs/nucleo-l496zg/include/board.h index c3ec31cc06b83b6864f654552480ac1d4f082928..38af59e5be9da38a3c18b81412bafea392c18a6b 100644 --- a/configs/nucleo-l496zg/include/board.h +++ b/configs/nucleo-l496zg/include/board.h @@ -79,7 +79,7 @@ #define STM32L4_HSE_FREQUENCY 8000000ul /* 8 MHz from MCO output */ #define STM32L4_LSE_FREQUENCY 32768 -#define HSI_CLOCK_CONFIG +#define HSE_CLOCK_CONFIG #if defined(HSI_CLOCK_CONFIG) @@ -187,7 +187,212 @@ #elif defined(HSE_CLOCK_CONFIG) -# error "Not implemented" +#define STM32L4_BOARD_USEHSE + +/* Prescaler common to all PLL inputs; will be 1 */ + +#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) + +/* 'main' PLL config; we use this to generate our system clock via the R + * output. We set it up as 8 MHz / 1 * 20 / 2 = 80 MHz + * + * XXX NOTE: currently the main PLL is implicitly turned on and is implicitly + * the system clock; this should be configurable since not all applications may + * want things done this way. + */ + +#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32L4_PLLCFG_PLLP 0 +#undef STM32L4_PLLCFG_PLLP_ENABLED +#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32L4_PLLCFG_PLLQ_ENABLED +#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32L4_PLLCFG_PLLR_ENABLED + +/* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't + * do that with the main PLL's N value. We set N = 12, and enable + * the Q output (ultimately for CLK48) with /4. So, + * 8 MHz / 1 * 12 / 2 = 48 MHz + * + * XXX NOTE: currently the SAIPLL /must/ be explicitly selected in the + * menuconfig, or else all this is a moot point, and the various 48 MHz + * peripherals will not work (RNG at present). I would suggest removing + * that option from Kconfig altogether, and simply making it an option + * that is selected via a #define here, like all these other params. + */ + +#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32L4_PLLSAI1CFG_PLLP 0 +#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#define STM32L4_PLLSAI1CFG_PLLR 0 +#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED + +/* 'SAIPLL2' is not used in this application */ + +#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32L4_PLLSAI2CFG_PLLP 0 +#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#define STM32L4_PLLSAI2CFG_PLLR 0 +#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED + +#define STM32L4_SYSCLK_FREQUENCY 80000000ul + +/* CLK48 will come from PLLSAI1 (implicitly Q) */ + +#define STM32L4_USE_CLK48 1 +#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 + +/* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ + +#define STM32L4_USE_LSE 1 + +/* AHB clock (HCLK) is SYSCLK (80MHz) */ + +#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ + +/* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ + +#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) + +/* Timers driven from APB1 will be twice PCLK1 */ +/* REVISIT : this can be configured */ + +#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (80MHz) */ + +#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) + +/* Timers driven from APB2 will be twice PCLK2 */ +/* REVISIT : this can be configured */ + +#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8,15,16,17 are on APB2, others on APB1 + */ +/* REVISIT : this can be configured */ + +#elif defined(MSI_CLOCK_CONFIG) + +#define STM32L4_BOARD_USEMSI +#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M + +/* Prescaler common to all PLL inputs; will be 1 */ + +#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) + +/* 'main' PLL config; we use this to generate our system clock via the R + * output. We set it up as 4 MHz / 1 * 40 / 2 = 80 MHz + * + * XXX NOTE: currently the main PLL is implicitly turned on and is implicitly + * the system clock; this should be configurable since not all applications may + * want things done this way. + */ + +#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32L4_PLLCFG_PLLP 0 +#undef STM32L4_PLLCFG_PLLP_ENABLED +#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32L4_PLLCFG_PLLQ_ENABLED +#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32L4_PLLCFG_PLLR_ENABLED + +/* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't + * do that with the main PLL's N value. We set N = 12, and enable + * the Q output (ultimately for CLK48) with /4. So, + * 4 MHz / 1 * 24 / 2 = 48 MHz + * + * XXX NOTE: currently the SAIPLL /must/ be explicitly selected in the + * menuconfig, or else all this is a moot point, and the various 48 MHz + * peripherals will not work (RNG at present). I would suggest removing + * that option from Kconfig altogether, and simply making it an option + * that is selected via a #define here, like all these other params. + */ + +#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32L4_PLLSAI1CFG_PLLP 0 +#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#define STM32L4_PLLSAI1CFG_PLLR 0 +#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED + +/* 'SAIPLL2' is not used in this application */ + +#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32L4_PLLSAI2CFG_PLLP 0 +#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#define STM32L4_PLLSAI2CFG_PLLR 0 +#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED + +#define STM32L4_SYSCLK_FREQUENCY 80000000ul + +/* CLK48 will come from PLLSAI1 (implicitly Q) */ + +#define STM32L4_USE_CLK48 1 +#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 + +/* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ + +#define STM32L4_USE_LSE 1 + +/* AHB clock (HCLK) is SYSCLK (80MHz) */ + +#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ + +/* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ + +#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) + +/* Timers driven from APB1 will be twice PCLK1 */ +/* REVISIT : this can be configured */ + +#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (80MHz) */ + +#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) + +/* Timers driven from APB2 will be twice PCLK2 */ +/* REVISIT : this can be configured */ + +#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8,15,16,17 are on APB2, others on APB1 + */ +/* REVISIT : this can be configured */ #endif diff --git a/configs/nucleo-l496zg/src/stm32_usb.c b/configs/nucleo-l496zg/src/stm32_usb.c index 74d8d46d25c4261b3b97df836700834cfa5a74d7..505d78445a41d2c9223138d853ad3b2ed9bdd0ce 100644 --- a/configs/nucleo-l496zg/src/stm32_usb.c +++ b/configs/nucleo-l496zg/src/stm32_usb.c @@ -322,7 +322,7 @@ int stm32_setup_overcurrent(xcpt_t handler, void *arg) ************************************************************************************/ #ifdef CONFIG_USBDEV -void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume) +void stm32l4_usbsuspend(FAR struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); } diff --git a/configs/nutiny-nuc120/include/board.h b/configs/nutiny-nuc120/include/board.h index c1661aa6fa6e0da704234276e845d957d06134e3..f797cce97ff903b4507d1669dc9286344aa11903 100644 --- a/configs/nutiny-nuc120/include/board.h +++ b/configs/nutiny-nuc120/include/board.h @@ -131,40 +131,4 @@ #define NUM_BUTTONS 0 -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: nuc_boardinitialize - * - * Description: - * All NUC1XX architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void nuc_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_NUTINY_NUC12_INCLUDE_BOARD_H */ diff --git a/configs/olimex-lpc-h3131/include/board.h b/configs/olimex-lpc-h3131/include/board.h index f9952ab740d9231643752c319f7f8933761729e6..a411461668bda0a948d5d7c2506afe113ba069c1 100644 --- a/configs/olimex-lpc-h3131/include/board.h +++ b/configs/olimex-lpc-h3131/include/board.h @@ -161,17 +161,6 @@ extern "C" /************************************************************************************ * Public Function Prototypes ************************************************************************************/ -/************************************************************************************ - * Name: lpc31_boardinitialize - * - * Description: - * All LPC31XX architectures must provide the following entry point. This entry - * point is called early in the intitialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void lpc31_boardinitialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/configs/olimex-lpc1766stk/README.txt b/configs/olimex-lpc1766stk/README.txt index bf1d32b4f2195c1cd3ea917dc9601794b39c6877..63b7de124e1c3320dd9b4d2280394a278f319565 100644 --- a/configs/olimex-lpc1766stk/README.txt +++ b/configs/olimex-lpc1766stk/README.txt @@ -7,12 +7,6 @@ Contents ^^^^^^^^ Olimex LPC1766-STK development board - Development Environment - GNU Toolchain Options - IDEs - NuttX EABI "buildroot" Toolchain - NuttX OABI "buildroot" Toolchain - NXFLAT Toolchain LEDs Serial Console Using OpenOCD and GDB with an FT2232 JTAG emulator @@ -163,189 +157,6 @@ Olimex LPC1766-STK development board MISO0 and MOSI0 are join via a 1K ohm resistor so the LCD appears to be write only. -Development Environment -^^^^^^^^^^^^^^^^^^^^^^^ - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -^^^^^^^^^^^^^^^^^^^^^ - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The devkitARM GNU toolchain, - 3. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the NuttX buildroot toolchain. However, - the make system is setup to default to use the devkitARM toolchain. To use - the CodeSourcery or devkitARM toolchain, you simply need add one of the - following configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - NOTE: the CodeSourcery (for Windows)and devkitARM are Windows native toolchains. - The CodeSourcey (for Linux) and NuttX buildroot toolchains are Cygwin and/or - Linux native toolchains. There are several limitations to using a Windows based - toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -^^^^ - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/lpc17xx, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/lpc17x/lpc17_vectors.S. - -NuttX EABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh olimex-lpc1766stk/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you - are building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -^^^^^^^^^^^^^^^^ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - LEDs ^^^^ diff --git a/configs/olimex-lpc1766stk/include/board.h b/configs/olimex-lpc1766stk/include/board.h index e147bc7377b69bb472d5ab854e1243b6418aa2f6..ef1a1701b64b6f25a462643cb1987c7de6b08d06 100644 --- a/configs/olimex-lpc1766stk/include/board.h +++ b/configs/olimex-lpc1766stk/include/board.h @@ -194,7 +194,7 @@ #define BOARD_JOYSTICK_LEFT 6 #define BOARD_JOYSTICK_RIGHT 7 -#define BOARD_NUM_BUTTONS 8 +#define NUM_BUTTONS 8 #define BOARD_BUTTON_BUTTON1_BIT (1 << BOARD_BUTTON_1) #define BOARD_BUTTON_BUTTON2_BIT (1 << BOARD_BUTTON_2) @@ -349,43 +349,4 @@ * P1[31]/SCK1/AD0[5] 20 AIN5 */ -/************************************************************************************ - * Public Types - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: lpc17_boardinitialize - * - * Description: - * All LPC17xx architectures must provide the following entry point. This entry - * point is called early in the intitialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void lpc17_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/olimex-lpc1766stk/nsh/defconfig b/configs/olimex-lpc1766stk/nsh/defconfig index f1fd8616a8297db8ee7b15fb07e679e5bb871ae2..81cc9af906759805b35a6dbb44d7adc20431a070 100644 --- a/configs/olimex-lpc1766stk/nsh/defconfig +++ b/configs/olimex-lpc1766stk/nsh/defconfig @@ -1,4 +1,4 @@ -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_DF_H is not set diff --git a/configs/olimex-lpc1766stk/src/lpc17_buttons.c b/configs/olimex-lpc1766stk/src/lpc17_buttons.c index 179a6785841e93af91a30e846b5b53375de81ee6..19e5830432a4b5ce763adf09a832481c45e9f7c9 100644 --- a/configs/olimex-lpc1766stk/src/lpc17_buttons.c +++ b/configs/olimex-lpc1766stk/src/lpc17_buttons.c @@ -64,7 +64,7 @@ * the BUTTON_* and JOYSTICK_* definitions in board.h */ -static const uint16_t g_buttoncfg[BOARD_NUM_BUTTONS] = +static const uint16_t g_buttoncfg[NUM_BUTTONS] = { LPC1766STK_BUT1, LPC1766STK_BUT2, LPC1766STK_WAKEUP, LPC1766STK_CENTER, LPC1766STK_UP, LPC1766STK_DOWN, LPC1766STK_LEFT, LPC1766STK_RIGHT @@ -75,7 +75,7 @@ static const uint16_t g_buttoncfg[BOARD_NUM_BUTTONS] = * numbers. */ -static uint8_t g_buttonirq[BOARD_NUM_BUTTONS] = +static uint8_t g_buttonirq[NUM_BUTTONS] = { LPC1766STK_BUT1_IRQ, LPC1766STK_BUT2_IRQ, LPC1766STK_WAKEUP_IRQ, LPC1766STK_CENTER_IRQ, LPC1766STK_UP_IRQ, LPC1766STK_DOWN_IRQ, @@ -108,7 +108,7 @@ void board_button_initialize(void) /* Configure the GPIO pins as interrupting inputs. */ - for (i = 0; i < BOARD_NUM_BUTTONS; i++) + for (i = 0; i < NUM_BUTTONS; i++) { lpc17_configgpio(g_buttoncfg[i]); } @@ -137,7 +137,7 @@ uint32_t board_buttons(void) /* Check that state of each key */ - for (i = 0; i < BOARD_NUM_BUTTONS; i++) + for (i = 0; i < NUM_BUTTONS; i++) { /* A LOW value means that the key is pressed. */ @@ -182,7 +182,7 @@ int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) /* Verify that the button ID is within range */ - if ((unsigned)id < BOARD_NUM_BUTTONS) + if ((unsigned)id < NUM_BUTTONS) { /* Disable interrupts until we are done */ diff --git a/configs/olimex-lpc1766stk/usbmsc/defconfig b/configs/olimex-lpc1766stk/usbmsc/defconfig index 516324e2ac9b215e254f49f2009bdbfa91ba813b..a668169a43c4935584cb8404b578d942658a1052 100644 --- a/configs/olimex-lpc1766stk/usbmsc/defconfig +++ b/configs/olimex-lpc1766stk/usbmsc/defconfig @@ -1,4 +1,4 @@ -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_EXCHANGE is not set diff --git a/configs/olimex-lpc1766stk/zmodem/defconfig b/configs/olimex-lpc1766stk/zmodem/defconfig index 86becd2f58f076f41fd282568cb283658b388bce..4a3e5a41034f0ae722d179d8da95901f69dd2dae 100644 --- a/configs/olimex-lpc1766stk/zmodem/defconfig +++ b/configs/olimex-lpc1766stk/zmodem/defconfig @@ -1,4 +1,4 @@ -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set diff --git a/configs/olimex-stm32-e407/include/board.h b/configs/olimex-stm32-e407/include/board.h index df7751c5795574701ac79cbf13834f028e20cac4..e220e0fd06f8305932b2762e0922a1fc2b15c499 100644 --- a/configs/olimex-stm32-e407/include/board.h +++ b/configs/olimex-stm32-e407/include/board.h @@ -255,41 +255,4 @@ #endif -/******************************************************************************* - * Public Data - ******************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/****************************************************************************** - * Public Function Prototypes - *****************************************************************************/ - -/****************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - *****************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_OLIMEX_STM32_E407_INCLUDE_BOARD_H */ diff --git a/configs/olimex-stm32-h405/include/board.h b/configs/olimex-stm32-h405/include/board.h index 86d98da3fab8b5727584ffc378b6188ca289a036..8155a219b0ebb5830fd69fa58649ca4347a31e33 100644 --- a/configs/olimex-stm32-h405/include/board.h +++ b/configs/olimex-stm32-h405/include/board.h @@ -181,45 +181,11 @@ #define GPIO_USART3_CTS GPIO_USART3_CTS_1 //PB13 #define GPIO_USART3_RTS GPIO_USART3_RTS_1 //PB14 -//CAN: +/* CAN: */ + #define GPIO_CAN1_RX GPIO_CAN1_RX_2 //PB8 #define GPIO_CAN1_TX GPIO_CAN1_TX_2 //PB9 #define GPIO_CAN2_RX GPIO_CAN1_RX_2 //PB5 #define GPIO_CAN2_TX GPIO_CAN1_TX_2 //PB6 -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_OLIMEX_STM32_H405_INCLUDE_BOARD_H */ diff --git a/configs/olimex-stm32-h407/include/board.h b/configs/olimex-stm32-h407/include/board.h index 249afdc7ee664ee8e32a4bf49fae8fd6d4c766de..179cf285025fad0bd8b03b1623497bc8fca24195 100644 --- a/configs/olimex-stm32-h407/include/board.h +++ b/configs/olimex-stm32-h407/include/board.h @@ -281,41 +281,4 @@ #define DMAMAP_SDIO DMAMAP_SDIO_1 -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_OLIMEX_STM32_H407_INCLUDE_BOARD_H */ diff --git a/configs/olimex-stm32-p107/include/board.h b/configs/olimex-stm32-p107/include/board.h index c6d0aa873b77c31587c8defd53b80f913440e0bc..6eaee74ddf1aadfac7c8d31beb0b82b05b7da460 100644 --- a/configs/olimex-stm32-p107/include/board.h +++ b/configs/olimex-stm32-p107/include/board.h @@ -117,39 +117,4 @@ # define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ #endif -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -EXTERN void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_OLIMEX_STM32_P107_INCLUDE_BOARD_H */ diff --git a/configs/olimex-stm32-p107/nsh/defconfig b/configs/olimex-stm32-p107/nsh/defconfig index e8e8b2e151b34fc700b97bd867edd7de303e0d3e..b3c828df2a32559dbf8a94e3cf9e9c9626eb77e5 100644 --- a/configs/olimex-stm32-p107/nsh/defconfig +++ b/configs/olimex-stm32-p107/nsh/defconfig @@ -1,4 +1,4 @@ -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_DF_H is not set diff --git a/configs/olimex-stm32-p207/include/board.h b/configs/olimex-stm32-p207/include/board.h index 62cb143755305a3e06517491b40aea38bde2fedf..74c115d3ffa96c1fde38714ab3bdec229de8933e 100644 --- a/configs/olimex-stm32-p207/include/board.h +++ b/configs/olimex-stm32-p207/include/board.h @@ -245,39 +245,4 @@ #define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2 #define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_2 -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_OLIMEX_STM32_P207_INCLUDE_BOARD_H */ diff --git a/configs/olimex-stm32-p407/README.txt b/configs/olimex-stm32-p407/README.txt index f77162379f83a596ba3e9167aae94176c75640eb..f7c2f6ce8e84c4e08aabe6eb13ac5534eaa76a33 100644 --- a/configs/olimex-stm32-p407/README.txt +++ b/configs/olimex-stm32-p407/README.txt @@ -98,7 +98,7 @@ microSD Card Interface Device Drivers -> MMC/SD Driver Support CONFIG_MMCSD=y : Enable MMC/SD support CONFIG_MMSCD_NSLOTS=1 : One slot per driver instance - # CONFIG_MMCSD_HAVECARDDETECT is not set : No card-detect GPIO + # CONFIG_MMCSD_HAVE_CARDDETECT is not set : No card-detect GPIO # CONFIG_MMCSD_MMCSUPPORT is not set : Interferes with some SD cards # CONFIG_MMCSD_SPI is not set : No SPI-based MMC/SD support CONFIG_MMCSD_SDIO=y : SDIO-based MMC/SD support diff --git a/configs/olimex-stm32-p407/include/board.h b/configs/olimex-stm32-p407/include/board.h index 4b7429b3c696aab21a95892d2a8e8f9fcf4ace73..7a26575b6d0ea03d7aff68f1c8afe52407b93c54 100644 --- a/configs/olimex-stm32-p407/include/board.h +++ b/configs/olimex-stm32-p407/include/board.h @@ -316,41 +316,4 @@ #define DMAMAP_SDIO DMAMAP_SDIO_1 -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_OLIMEX_STM32_P407_INCLUDE_BOARD_H */ diff --git a/configs/olimexino-stm32/can/defconfig b/configs/olimexino-stm32/can/defconfig index b7ee6a220bdda94d6739f0c641b6637d120dcb79..0791cf78896bb3acec7037a85f6ff25838837a7e 100644 --- a/configs/olimexino-stm32/can/defconfig +++ b/configs/olimexino-stm32/can/defconfig @@ -37,6 +37,7 @@ CONFIG_EXAMPLES_HELLOXX=y CONFIG_EXAMPLES_NSH=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=12 CONFIG_FS_FAT=y CONFIG_FS_FATTIME=y CONFIG_FS_NAMED_SEMAPHORES=y diff --git a/configs/olimexino-stm32/composite/defconfig b/configs/olimexino-stm32/composite/defconfig index f8fe9eca0eccb7a51ae276ec498ba7f64981b7ad..ad25c1672df44afad64988bea346a67957a24d5b 100644 --- a/configs/olimexino-stm32/composite/defconfig +++ b/configs/olimexino-stm32/composite/defconfig @@ -1,10 +1,8 @@ # CONFIG_DISABLE_OS_API is not set # CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_MMCSD_HAVECARDDETECT is not set -# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_NSH_DISABLE_CMP is not set # CONFIG_NSH_DISABLE_DD is not set -# CONFIG_NSH_DISABLE_DELROUTE is not set # CONFIG_NSH_DISABLE_DF is not set # CONFIG_NSH_DISABLE_EXEC is not set # CONFIG_NSH_DISABLE_EXIT is not set @@ -59,6 +57,7 @@ CONFIG_EXAMPLES_HELLOXX=y CONFIG_EXAMPLES_NSH=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=12 CONFIG_FS_FAT=y CONFIG_FS_FATTIME=y CONFIG_FS_NAMED_SEMAPHORES=y @@ -123,7 +122,6 @@ CONFIG_STM32_USART2=y CONFIG_STM32_USB=y CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSTEM_COMPOSITE=y -CONFIG_SYSTEM_FREE=y CONFIG_SYSTEM_TIME64=y CONFIG_TASK_NAME_SIZE=12 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=768 diff --git a/configs/olimexino-stm32/include/board.h b/configs/olimexino-stm32/include/board.h index 997dcfe7bea8729f3427a464b7aa5d7a468bc0f2..2b091b9a230f25454d6156152da5c2c2ff72adfa 100644 --- a/configs/olimexino-stm32/include/board.h +++ b/configs/olimexino-stm32/include/board.h @@ -174,40 +174,4 @@ * be used by other board-specific logic. */ -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_OLIMEXINO_STM32_INCLUDE_BOARD_H */ diff --git a/configs/olimexino-stm32/nsh/defconfig b/configs/olimexino-stm32/nsh/defconfig index c252fa3a66d249975b3f31bf10b1c840a3615740..30a421918e32dad9584f799cad9313a22dbf31ff 100644 --- a/configs/olimexino-stm32/nsh/defconfig +++ b/configs/olimexino-stm32/nsh/defconfig @@ -1,10 +1,8 @@ # CONFIG_DISABLE_OS_API is not set # CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_MMCSD_HAVECARDDETECT is not set -# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_NSH_DISABLE_CMP is not set # CONFIG_NSH_DISABLE_DD is not set -# CONFIG_NSH_DISABLE_DELROUTE is not set # CONFIG_NSH_DISABLE_DF is not set # CONFIG_NSH_DISABLE_EXEC is not set # CONFIG_NSH_DISABLE_EXIT is not set @@ -47,6 +45,7 @@ CONFIG_EXAMPLES_HELLOXX=y CONFIG_EXAMPLES_NSH=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=12 CONFIG_FS_FAT=y CONFIG_FS_FATTIME=y CONFIG_FS_NAMED_SEMAPHORES=y @@ -109,7 +108,6 @@ CONFIG_STM32_TIM3=y CONFIG_STM32_USART1=y CONFIG_STM32_USART2=y CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_FREE=y CONFIG_SYSTEM_TIME64=y CONFIG_TASK_NAME_SIZE=12 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=768 diff --git a/configs/open1788/Kconfig b/configs/open1788/Kconfig index e5910efdac0ee13327ba13a4957e15ee357ff7f7..3cfdf262504a2585ec012020d82e8829397c2129 100644 --- a/configs/open1788/Kconfig +++ b/configs/open1788/Kconfig @@ -4,4 +4,15 @@ # if ARCH_BOARD_OPEN1788 + +config OPEN1788_DJOYSTICK + bool "Discrete Joystick Support" + default n + depends on !ARCH_BUTTONS && DJOYSTICK + +config OPEN1788_DJOYDEV + string "Joystick Device" + default "/dev/djoy0" + depends on OPEN1788_DJOYSTICK + endif diff --git a/configs/open1788/README.txt b/configs/open1788/README.txt index b5d66c7970180ac9e57bd6f3afb0229c010be335..1feb341c150b26782c83af2ba4d39b6a8150f70f 100644 --- a/configs/open1788/README.txt +++ b/configs/open1788/README.txt @@ -245,43 +245,56 @@ Loading Code with the ISP Board CONFIGURATION ============= - fb - -- +Information Common to All Configurations +---------------------------------------- - A simple configuration used for some basic (non-graphic) debug of the - framebuffer character drivers using apps/examples/fb. This - configuration enables SDRAM to hold the LCD framebuffer and enables - the LPC178x LCD driver in order to support the WaveShare 4.3 inch TFT - panel. + 1. These configurations use the mconf-based configuration tool. To + change this configuration using that tool, you should: - NOTES: + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository + README.txt. - 1. This configuration uses the mconf-based configuration tool. To - change this configuration using that tool, you should: + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. - a. Build and install the kconfig-mconf tool. See nuttx/README.txt - see additional README.txt files in the NuttX tools repository - README.txt. + 2. Most (but not all) configurations use the "GNU Tools for ARM + Embedded Processors" that is maintained by ARM: - b. Execute 'make menuconfig' in nuttx/ in order to start the - reconfiguration process. + https://developer.arm.com/open-source/gnu-toolchain/gnu-rm - 2. This configuration uses the "GNU Tools for ARM Embedded Processors" - that is maintained by ARM: + unless otherwise stated. - https://developer.arm.com/open-source/gnu-toolchain/gnu-rm + That toolchain selection can easily be reconfigured using + 'make menuconfig'. Here are the relevant current settings: - That toolchain selection can easily be reconfigured using - 'make menuconfig'. Here are the relevant current settings: + Build Setup: + CONFIG_HOST_WINDOWS=y : Window environment + CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows - Build Setup: - CONFIG_HOST_WINDOWS=y : Window environment - CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows + System Type -> Toolchain: + CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain + + 3. By Default, UART0 is used as the serial console in all configurations. + This may be connected to your computer via an external RS-232 driver or + via the WaveShare USB ISP/VCOM module. See the section above entitled + "Serial Console" for other options. + +Configuration Directories +------------------------- + + fb + -- + + A simple configuration used for some basic (non-graphic) debug of the + framebuffer character drivers using apps/examples/fb. This + configuration enables SDRAM to hold the LCD framebuffer and enables + the LPC178x LCD driver in order to support the WaveShare 4.3 inch TFT + panel. - System Type -> Toolchain: - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain + NOTES: - 3. In this configuration, the SDRAM is not added to heap but is + 1. In this configuration, the SDRAM is not added to heap but is dedicated to supporting an LCD frame buffer at address 0xa0010000. knsh @@ -299,24 +312,13 @@ CONFIGURATION Make the user-space binaries first (pass1), then make the kernel-space binaries (pass2) - NOTES: - - 1. This configuration uses the mconf-based configuration tool. To - change this configuration using that tool, you should: - - a. Build and install the kconfig-mconf tool. See nuttx/README.txt - see additional README.txt files in the NuttX tools repository. - - b. Execute 'make menuconfig' in nuttx/ in order to start the - reconfiguration process. - - 2. Uses the older, OABI, buildroot toolchain. But that is easily + 1. Uses the older, OABI, buildroot toolchain. But that is easily reconfigured: CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot toolchain CONFIG_ARMV7M_OABI_TOOLCHAIN=y : Older, OABI toolchain - 3. This configuration has DMA-based SD card support enabled by + 2. This configuration has DMA-based SD card support enabled by default. That support can be disabled as follow: CONFIG_LPC17_GPDMA=n : No DMA @@ -326,7 +328,7 @@ CONFIGURATION CONFIG_MMCSD=n : No MMC/SD driver support CONFIG_FS_FAT=n : No FAT file system support - 4. At the end of the build, there will be several files in the top-level + 3. At the end of the build, there will be several files in the top-level NuttX build directory: PASS1: @@ -348,7 +350,7 @@ CONFIGURATION load objects twice to account for write failures. I have not yet found a simple foolproof way to reliably get the code into FLASH. - 5. Combining .hex files. If you plan to use the .hex files with your + 4. Combining .hex files. If you plan to use the .hex files with your debugger or FLASH utility, then you may need to combine the two hex files into a single .hex file. Here is how you can do that. @@ -399,25 +401,16 @@ CONFIGURATION NOTES: - 1. This configuration uses the mconf-based configuration tool. To - change this configuration using that tool, you should: - - a. Build and install the kconfig-mconf tool. See nuttx/README.txt - see additional README.txt files in the NuttX tools repository./README.txt. - - b. Execute 'make menuconfig' in nuttx/ in order to start the - reconfiguration process. - - 2. Uses the older, OABI, buildroot toolchain. But that is easily + 1. Uses the older, OABI, buildroot toolchain. But that is easily reconfigured: CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot toolchain CONFIG_ARMV7M_OABI_TOOLCHAIN=y : Older, OABI toolchain - 3. This NSH has support for built-in applications enabled, however, + 2. This NSH has support for built-in applications enabled, however, no built-in configurations are built in the defulat configuration. - 4. This configuration has DMA-based SD card support enabled by + 3. This configuration has DMA-based SD card support enabled by default. That support can be disabled as follow: CONFIG_LPC17_GPDMA=n : No DMA @@ -427,12 +420,12 @@ CONFIGURATION CONFIG_MMCSD=n : No MMC/SD driver support CONFIG_FS_FAT=n : No FAT file system support - 5. This configuration has been used for verifying SDRAM by modifying + 4. This configuration has been used for verifying SDRAM by modifying the configuration in the following ways: CONFIG_LPC17_EMC=y : Enable the EMC - CONFIG_LPC17_EXTDRAM=y : Configure external DRAM - CONFIG_LPC17_EXTDRAMSIZE=67108864 : DRAM size 2x256/8 = 64MB + CONFIG_LPC17_EXTDRAM=y : Configure external DRAM + CONFIG_LPC17_EXTDRAMSIZE=67108864 : DRAM size 2x256/8 = 64MB CONFIG_SYSTEM_RAMTEST=y : Enable the RAM test built-in In this configuration, the SDRAM is not added to heap and so is @@ -460,7 +453,7 @@ CONFIGURATION CONFIG_SPI_EXCHANGE=n : exchange() method is not supported System Type: - CONFIG_LPC17_GPIOIRQ=y : GPIO interrupt support + CONFIG_LPC17_GPIOIRQ=y : GPIO interrupt support CONFIG_LPC17_SSP1=y : Enable support for SSP1 RTOS Features: @@ -514,22 +507,56 @@ CONFIGURATION NOTES: - 1. This configuration uses the mconf-based configuration tool. To - change this configuration using that tool, you should: - - a. Build and install the kconfig-mconf tool. See nuttx/README.txt - see additional README.txt files in the NuttX tools repository - README.txt. - - b. Execute 'make menuconfig' in nuttx/ in order to start the - reconfiguration process. - - 2. Uses the older, OABI, buildroot toolchain. But that is easily + 1. Uses the older, OABI, buildroot toolchain. But that is easily reconfigured: CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot toolchain CONFIG_ARMV7M_OABI_TOOLCHAIN=y : Older, OABI toolchain - 3. In this configuration, the SDRAM is not added to heap but is + 2. In this configuration, the SDRAM is not added to heap but is dedicated to supporting an LCD frame buffer at address 0xa0010000. + pdcurses + ------- + + A simple NSH configuration used for some basic (non-graphic) debug of + the pdcurses library on top of a framebuffer character drivers. This + configuration provides the test programs from: + + - apps/examples/pdcurses, + - apps/examples/fb, and + - apps/examples/djoystick + + as NSH built-in applications. A discrete joystick is provided to + control pdcurses examples using the joystick buttons on the Open1788 + board. + + This configuration enables SDRAM to hold the LCD framebuffer and + enables the LPC178x LCD driver in order to support the WaveShare 4.3 + inch TFT panel. In this configuration, the SDRAM is not added to heap + but is dedicated to supporting an LCD frame buffer at address + 0xa0010000. + + STATUS: + 2017-11-20: Basic graphics functionality appears to be functional, but + is not fully tested. + + Only keyboard and mouse input are supported by pdcurses. NuttX + supports only USB HID keyboard and mouse. It would require a hub to + use them simultaneously. In a handheld device with an ncurses-style + UI, I don't think that a mouse (or even a touchscreen) makes sense. + + For a handheld device, I think input would be via GPIO keypad, rather + that a full keyboard, and I doubt that you would do any significant + text data entry. I think that up-down-left-right arrows keys and an + enter key is basically all you need for most interaction. + + In NuttX naming that is called a discrete joystick djoystick. There + is a well defined djoystick interface in include/nuttx/input/djoystick.h. + Note that there are dscrete joystick buttons on the Open1788 board so + would be a natural interace in this case. + + A discrete joystick driver was added to pdcurses configuration. It + has been verified that the pdcurses demos that require menu + interactions work well with the discrete joystick. + diff --git a/configs/open1788/include/board.h b/configs/open1788/include/board.h index 11f47847cb0ada5c60abf6aa1f5bd0508dda2226..86394b1bff54bdac7907cd8f58211faf176cd727 100644 --- a/configs/open1788/include/board.h +++ b/configs/open1788/include/board.h @@ -290,7 +290,7 @@ #define BOARD_JOYSTICK_D 6 #define BOARD_JOYSTICK_CTR 7 -#define BOARD_NUM_BUTTONS 8 +#define NUM_BUTTONS 8 #define BOARD_BUTTON_USER1_BIT (1 << BOARD_BUTTON_USER1) #define BOARD_BUTTON_USER2_BIT (1 << BOARD_BUTTON_USER2) @@ -375,7 +375,7 @@ #define GPIO_LCD_VD6 GPIO_LCD_VD6_2 #define GPIO_LCD_VD7 GPIO_LCD_VD7_2 -/* LED G: +/* LCD G: * * VD8 --- Connected to P0[6] * VD9 --- Connected to P0[7] @@ -434,43 +434,4 @@ #define GPIO_SSP1_MOSI GPIO_SSP1_MOSI_2 #define GPIO_SSP1_SCK GPIO_SSP1_SCK_2 -/************************************************************************************ - * Public Types - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: lpc17_boardinitialize - * - * Description: - * All LPC17xx architectures must provide the following entry point. This entry - * point is called early in the intitialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void lpc17_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_OPEN1788_INCLUDE_BOARD_H */ diff --git a/configs/open1788/pdcurses/defconfig b/configs/open1788/pdcurses/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..10997c2889d1cf16b5597aedabb6b0d260bf7022 --- /dev/null +++ b/configs/open1788/pdcurses/defconfig @@ -0,0 +1,72 @@ +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH_BOARD_OPEN1788=y +CONFIG_ARCH_BOARD="open1788" +CONFIG_ARCH_CHIP_LPC1788=y +CONFIG_ARCH_CHIP_LPC17XX=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="arm" +CONFIG_BCH=y +CONFIG_BOARD_LOOPSPERMSEC=11934 +CONFIG_BUILTIN=y +CONFIG_DEV_LOOP=y +CONFIG_DJOYSTICK=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_DJOYSTICK=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_NSH=y +CONFIG_EXAMPLES_PDCURSES=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_ROMFS=y +CONFIG_GRAPHICS_PDCURSES=y +CONFIG_HOST_WINDOWS=y +CONFIG_INPUT=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LPC17_EXTDRAM=y +CONFIG_LPC17_EXTDRAMSIZE=67108864 +CONFIG_LPC17_GPDMA=y +CONFIG_LPC17_GPIOIRQ=y +CONFIG_LPC17_LCD=y +CONFIG_LPC17_SDCARD=y +CONFIG_LPC17_UART0=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_MMCSD_SDIO=y +CONFIG_MMCSD=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NXFONTS_DISABLE_16BPP=y +CONFIG_NXFONTS_DISABLE_1BPP=y +CONFIG_NXFONTS_DISABLE_24BPP=y +CONFIG_NXFONTS_DISABLE_2BPP=y +CONFIG_NXFONTS_DISABLE_4BPP=y +CONFIG_NXFONTS_DISABLE_8BPP=y +CONFIG_OPEN1788_DJOYSTICK=y +CONFIG_PDCURSES_COLORFMT_RGB888=y +CONFIG_PDCURSES_DJOYSTICK=y +CONFIG_PDCURSES_FONT_6X9=y +CONFIG_PIPES=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x10000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=11 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_VIDEO_FB=y +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/open1788/src/Makefile b/configs/open1788/src/Makefile index d34c0982a6c8ce8b03ee601f55e5107b88ba8523..336d84277a129a81b4364ca26b2976b626186e2a 100644 --- a/configs/open1788/src/Makefile +++ b/configs/open1788/src/Makefile @@ -68,6 +68,8 @@ endif ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += lpc17_buttons.c +else ifeq ($(CONFIG_OPEN1788_DJOYSTICK),y) + CSRCS += lpc17_djoystick.c endif ifeq ($(CONFIG_INPUT_ADS7843E),y) diff --git a/configs/open1788/src/lpc17_bringup.c b/configs/open1788/src/lpc17_bringup.c index e2d8667a473478735d5fd80bd83507d2d10b78ff..98a79fcf4ec1c3129fd3871531c3393ef0064aa5 100644 --- a/configs/open1788/src/lpc17_bringup.c +++ b/configs/open1788/src/lpc17_bringup.c @@ -103,7 +103,7 @@ */ #ifdef NSH_HAVE_MMCSD -# ifdef CONFIG_MMCSD_HAVECARDDETECT +# ifdef CONFIG_MMCSD_HAVE_CARDDETECT # define NSH_HAVE_MMCSD_CD 1 # ifdef CONFIG_LPC17_GPIOIRQ # define NSH_HAVE_MMCSD_CDINT 1 @@ -389,7 +389,7 @@ int lpc17_bringup(void) } #ifdef CONFIG_VIDEO_FB - /* Initialize and register the simulated framebuffer driver */ + /* Initialize and register the framebuffer driver */ ret = fb_register(0, 0); if (ret < 0) @@ -398,5 +398,16 @@ int lpc17_bringup(void) } #endif +#ifdef CONFIG_OPEN1788_DJOYSTICK + /* Initialize and register the joystick driver */ + + ret = lpc17_djoy_initialization(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register the joystick driver: %d\n", ret); + return ret; + } +#endif + return ret; } diff --git a/configs/open1788/src/lpc17_buttons.c b/configs/open1788/src/lpc17_buttons.c index f053f0936671bf012b6de98d41933a7324f61c13..e35484bad64692dc24f9a21f33165a5345b857e0 100644 --- a/configs/open1788/src/lpc17_buttons.c +++ b/configs/open1788/src/lpc17_buttons.c @@ -81,7 +81,7 @@ * the BUTTON_* and JOYSTICK_* definitions in board.h */ -static const lpc17_pinset_t g_buttoncfg[BOARD_NUM_BUTTONS] = +static const lpc17_pinset_t g_buttoncfg[NUM_BUTTONS] = { GPIO_USER1, GPIO_USER2, GPIO_USER3, GPIO_JOY_A, GPIO_JOY_B, GPIO_JOY_C, GPIO_JOY_D, GPIO_JOY_CTR @@ -92,7 +92,7 @@ static const lpc17_pinset_t g_buttoncfg[BOARD_NUM_BUTTONS] = * numbers. */ -static uint8_t g_buttonirq[BOARD_NUM_BUTTONS] = +static const uint8_t g_buttonirq[NUM_BUTTONS] = { 0, GPIO_USER2_IRQ, GPIO_USER3_IRQ, GPIO_JOY_A_IRQ, GPIO_JOY_B_IRQ, GPIO_JOY_C_IRQ, GPIO_JOY_D_IRQ, GPIO_JOY_CTR_IRQ @@ -120,7 +120,7 @@ void board_button_initialize(void) /* Configure the GPIO pins as interrupting inputs. */ - for (i = 0; i < BOARD_NUM_BUTTONS; i++) + for (i = 0; i < NUM_BUTTONS; i++) { lpc17_configgpio(g_buttoncfg[i]); } @@ -149,7 +149,7 @@ uint32_t board_buttons(void) /* Check that state of each key */ - for (i = 0; i < BOARD_NUM_BUTTONS; i++) + for (i = 0; i < NUM_BUTTONS; i++) { /* A LOW value means that the key is pressed. */ @@ -196,7 +196,7 @@ int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) /* Verify that the button ID is within range */ - if ((unsigned)id < BOARD_NUM_BUTTONS) + if ((unsigned)id < NUM_BUTTONS) { /* Get the IRQ number for the button; A value of zero indicates that * the button does not support the interrupt function. diff --git a/configs/open1788/src/lpc17_djoystick.c b/configs/open1788/src/lpc17_djoystick.c new file mode 100644 index 0000000000000000000000000000000000000000..6c40f0eb41d1c0ee8a70621e173a90752d4cc690 --- /dev/null +++ b/configs/open1788/src/lpc17_djoystick.c @@ -0,0 +1,340 @@ +/**************************************************************************** + * configs/open1788/src/lpc17_djoystick.c + * + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "lpc17_gpio.h" +#include "open1788.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* The Open1788 supports several buttons. All will read "1" when open and "0" + * when closed + * + * USER1 Connected to P4[26] + * USER2 Connected to P2[22] + * USER3 Connected to P0[10] + * + * And a Joystick + * + * JOY_A Connected to P2[25] + * JOY_B Connected to P2[26] + * JOY_C Connected to P2[23] + * JOY_D Connected to P2[19] + * JOY_CTR Connected to P0[14] + * + * The switches are all connected to ground and should be pulled up and sensed + * with a value of '0' when closed. + * + * Mapping to DJOYSTICK buttons: + * + * DJOY_UP JOY_B + * DJOY_DOWN JOY_C + * DJOY_LEFT JOY_A + * DJOY_RIGHT JOY_D + * DJOY_BUTTON_1 JOY_CTR + * DJOY_BUTTON_2 USER1 + * DJOY_BUTTON_3 USER2 + * DJOY_BUTTON_4 USER3 + */ + +/* Number of Joystick discretes */ + +#define DJOY_NGPIOS 8 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static djoy_buttonset_t djoy_supported(FAR const struct djoy_lowerhalf_s *lower); +static djoy_buttonset_t djoy_sample(FAR const struct djoy_lowerhalf_s *lower); +static void djoy_enable(FAR const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, FAR void *arg); + + +static void djoy_disable(void); +static int djoy_interrupt(int irq, FAR void *context, FAR void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ +/* Pin configuration for each Open1788 joystick "button." Indexed using + * DJOY_* definitions in include/nuttx/input/djoystick.h. + */ + +static const lpc17_pinset_t g_joygpio[DJOY_NGPIOS] = +{ + GPIO_JOY_B, GPIO_JOY_C, GPIO_JOY_A, GPIO_JOY_D, + GPIO_JOY_CTR, GPIO_USER1, GPIO_USER2, GPIO_USER3 +}; + +#ifdef CONFIG_LPC17_GPIOIRQ +/* This array provides the mapping from button ID numbers to button IRQ + * numbers. Indexed using DJOY_* definitions in + * include/nuttx/input/djoystick.h. + */ + +static const uint8_t g_buttonirq[DJOY_NGPIOS] = +{ + GPIO_JOY_B_IRQ, GPIO_JOY_C_IRQ, GPIO_JOY_A_IRQ, GPIO_JOY_D_IRQ, + GPIO_JOY_CTR_IRQ, 0, GPIO_USER2_IRQ, GPIO_USER3_IRQ +}; +#endif + +/* Current interrupt handler and argument */ + +static djoy_interrupt_t g_djoyhandler; +static FAR void *g_djoyarg; + +/* This is the discrete joystick lower half driver interface */ + +static const struct djoy_lowerhalf_s g_djoylower = +{ + .dl_supported = djoy_supported, + .dl_sample = djoy_sample, + .dl_enable = djoy_enable, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: djoy_supported + * + * Description: + * Return the set of buttons supported on the discrete joystick device + * + ****************************************************************************/ + +static djoy_buttonset_t djoy_supported(FAR const struct djoy_lowerhalf_s *lower) +{ + iinfo("Supported: %02x\n", DJOY_ALLBITS); + return (djoy_buttonset_t)DJOY_ALLBITS; +} + +/**************************************************************************** + * Name: djoy_sample + * + * Description: + * Return the current state of all discrete joystick buttons + * + ****************************************************************************/ + +static djoy_buttonset_t djoy_sample(FAR const struct djoy_lowerhalf_s *lower) +{ + djoy_buttonset_t ret = 0; + int i; + + /* Read each joystick GPIO value */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = lpc17_gpioread(g_joygpio[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + iinfo("Returning: %02x\n", DJOY_ALLBITS); + return ret; +} + +/**************************************************************************** + * Name: djoy_enable + * + * Description: + * Enable interrupts on the selected set of joystick buttons. And empty + * set will disable all interrupts. + * + ****************************************************************************/ + +static void djoy_enable(FAR const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, FAR void *arg) +{ +#ifdef CONFIG_LPC17_GPIOIRQ + irqstate_t flags; + djoy_buttonset_t either = press | release; + int irq; + int i; + + iinfo("press: %02x release: %02x handler: %p arg: %p\n", + press, release, handler, arg); + + /* Start with all interrupts disabled */ + + flags = enter_critical_section(); + djoy_disable(); + + /* If no events are indicated or if no handler is provided, then this + * must really be a request to disable interrupts. + */ + + /* REVISIT: Currently does not distinguish press/release selections */ + + if (either && handler != NULL) + { + /* Save the new the handler and argument */ + + g_djoyhandler = handler; + g_djoyarg = arg; + + /* Attach and enable interrupts each GPIO. */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + irq = g_buttonirq[i]; + if (irq > 0) + { + (void)irq_attach(irq, djoy_interrupt, arg); + up_enable_irq(irq); + } + } + } + + leave_critical_section(flags); +#endif +} + +/**************************************************************************** + * Name: djoy_disable + * + * Description: + * Disable all joystick interrupts + * + ****************************************************************************/ + +static void djoy_disable(void) +{ +#ifdef CONFIG_LPC17_GPIOIRQ + irqstate_t flags; + int irq; + int i; + + /* Disable and detach all button handlers for each GPIO */ + + flags = enter_critical_section(); + for (i = 0; i < DJOY_NGPIOS; i++) + { + irq = g_buttonirq[i]; + if (irq > 0) + { + up_disable_irq(irq); + (void)irq_detach(irq); + } + } + + leave_critical_section(flags); +#endif + + /* Nullify the handler and argument */ + + g_djoyhandler = NULL; + g_djoyarg = NULL; +} + +/**************************************************************************** + * Name: djoy_interrupt + * + * Description: + * Discrete joystick interrupt handler + * + ****************************************************************************/ + +static int djoy_interrupt(int irq, FAR void *context, FAR void *arg) +{ + DEBUGASSERT(g_djoyhandler != NULL); + if (g_djoyhandler != NULL) + { + g_djoyhandler(&g_djoylower, g_djoyarg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc17_djoy_initialization + * + * Description: + * Initialize and register the discrete joystick driver + * + ****************************************************************************/ + +int lpc17_djoy_initialization(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE: This is unnecessary for + * interrupting pins since it will also be done by lpc17_gpiosetevent(). + */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + lpc17_configgpio(g_joygpio[i]); + } + + /* Make sure that all interrupts are disabled */ + + djoy_disable(); + + /* Register the joystick device as /dev/djoy0 */ + + return djoy_register(CONFIG_OPEN1788_DJOYDEV, &g_djoylower); +} diff --git a/configs/open1788/src/lpc17_lcd.c b/configs/open1788/src/lpc17_lcd.c index 648d6203fc9a846441e280bc48a3faf2ca61fa5d..2edd1e5627cd1ec7a55f8e73f0d1f7d0541436dc 100644 --- a/configs/open1788/src/lpc17_lcd.c +++ b/configs/open1788/src/lpc17_lcd.c @@ -1,6 +1,5 @@ /************************************************************************************ * configs/open1788/src/lpc17_lcd.c - * arch/arm/src/board/lpc17_lcd.c * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/configs/open1788/src/open1788.h b/configs/open1788/src/open1788.h index 53431273c0bac6ed8cf2cf01d8bb776af99d6d79..589d78b261b5ed164dae27045c77eda500ab897f 100644 --- a/configs/open1788/src/open1788.h +++ b/configs/open1788/src/open1788.h @@ -237,5 +237,17 @@ void open1788_nand_initialize(void); void open1788_lcd_initialize(void); #endif +/**************************************************************************** + * Name: lpc17_djoy_initialization + * + * Description: + * Initialize and register the discrete joystick driver + * + ****************************************************************************/ + +#ifdef CONFIG_OPEN1788_DJOYSTICK +int lpc17_djoy_initialization(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* _CONFIGS_OPEN1788_SRC_OPEN1788_H */ diff --git a/configs/p112/ostest/defconfig b/configs/p112/ostest/defconfig index 148eb1c367db426d2b6221cacdb3a305b8d0ac64..32a74105792fec615994e36f9356a48e26fdc950 100644 --- a/configs/p112/ostest/defconfig +++ b/configs/p112/ostest/defconfig @@ -15,7 +15,6 @@ CONFIG_DISABLE_PTHREAD=y CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=4 CONFIG_EXAMPLES_OSTEST_STACKSIZE=1024 CONFIG_EXAMPLES_OSTEST=y -CONFIG_GRAN_SINGLE=y CONFIG_GRAN=y CONFIG_HOST_WINDOWS=y CONFIG_MAX_TASKS=8 diff --git a/configs/pcduino-a10/include/board.h b/configs/pcduino-a10/include/board.h index 11ea8fa18c6fca36eecbd262f72aedf5ec4817de..8d70982ba088d14994b4a36e0b3a33cb23a1dbc4 100644 --- a/configs/pcduino-a10/include/board.h +++ b/configs/pcduino-a10/include/board.h @@ -157,39 +157,4 @@ .endm #endif /* __ASSEMBLY__ */ -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: a1x_boardinitialize - * - * Description: - * All A1X architectures must provide the following entry point. This entry - * point point is called early in the initialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void a1x_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* !__ASSEMBLY__ */ #endif /* __CONFIGS_PCDUINO_A10_INCLUDE_BOARD_H */ diff --git a/configs/photon/include/board.h b/configs/photon/include/board.h index 94113505a0c94f5f4aab405cdcde1452310e1d11..e9ec9e1e716b96096dc14ce16e1042f38f9f29a1 100644 --- a/configs/photon/include/board.h +++ b/configs/photon/include/board.h @@ -146,6 +146,20 @@ #define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + /* USB OTG HS definitions ***********************************************************/ /* Do not enable external PHY clock or OTG_HS module will not work */ @@ -260,41 +274,4 @@ #define DMAMAP_SDIO DMAMAP_SDIO_1 -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_PHOTON_INCLUDE_BOARD_H */ diff --git a/configs/photon/wlan/defconfig b/configs/photon/wlan/defconfig index 5e3fe78650ecc2f4bf01fe1d60e739d700f25645..8287431703273c4052451f1704eafe4d5b45bf79 100644 --- a/configs/photon/wlan/defconfig +++ b/configs/photon/wlan/defconfig @@ -1,5 +1,5 @@ # CONFIG_ARCH_LEDS is not set -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_DF_H is not set diff --git a/configs/pic32mx-starterkit/nsh2/defconfig b/configs/pic32mx-starterkit/nsh2/defconfig index 4fd623b657d1e19203987e1261bf8e694fca4771..5072e9db3a18ffd78581a34bd18a934e25867bea 100644 --- a/configs/pic32mx-starterkit/nsh2/defconfig +++ b/configs/pic32mx-starterkit/nsh2/defconfig @@ -1,5 +1,5 @@ # CONFIG_ARCH_RAMFUNCS is not set -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NSH_CONSOLE is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set diff --git a/configs/pic32mx7mmb/nsh/defconfig b/configs/pic32mx7mmb/nsh/defconfig index bc119376fa26c920373b3e84f504066868931f58..497af6031d68327b0325b08952640aeea0029bd9 100644 --- a/configs/pic32mx7mmb/nsh/defconfig +++ b/configs/pic32mx7mmb/nsh/defconfig @@ -1,5 +1,5 @@ # CONFIG_ARCH_RAMFUNCS is not set -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_EXCHANGE is not set diff --git a/configs/pic32mz-starterkit/README.txt b/configs/pic32mz-starterkit/README.txt index 567bcde739ef7cbacfdedbffb24539a2fec594ea..9929538de33e40190896bb9da291ebcd3c40c1c0 100644 --- a/configs/pic32mz-starterkit/README.txt +++ b/configs/pic32mz-starterkit/README.txt @@ -357,14 +357,32 @@ LEDs and Buttons Configurations ============== +Information Common to All Configurations +---------------------------------------- + Each PIC32MZ configuration is maintained in a sub-directory and can be selected as follow: - cd tools - ./configure.sh pic32mz-starterkit/ - cd - + tools/configure.sh [OPTIONS] pic32mz-starterkit/ + + Where typical options are -l to configure to build on Linux or -c to + configure for Cygwin under Linux. 'tools/configure.sh -h' will show + you all of the options. + + Before building, make sure the PATH environment variable includes the + correct path to the directory than holds your toolchain binaries. + + And then build NuttX by simply typing the following. At the conclusion of + the make, the nuttx binary will reside in an ELF file called, simply, + nuttx. + + make + + The that is provided above as an argument to the tools/configure.sh + must be is one of the following. -Where is one of the following: +Configuration Directories +------------------------- nsh: diff --git a/configs/pic32mz-starterkit/include/board.h b/configs/pic32mz-starterkit/include/board.h index 05bfa3d8f6fd48665d6c80191c89fbc0e20f0bb9..d3925c9b3cb35828d0901fbd6c128534391422f3 100644 --- a/configs/pic32mz-starterkit/include/board.h +++ b/configs/pic32mz-starterkit/include/board.h @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __CONFIGS_SURE_PIC32MZ_INCLUDE_BOARD_H -#define __CONFIGS_SURE_PIC32MZ_INCLUDE_BOARD_H +#ifndef __CONFIGS_PIC32MZ_STARTERKIT_INCLUDE_BOARD_H +#define __CONFIGS_PIC32MZ_STARTERKIT_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -140,7 +140,6 @@ #define BOARD_PB5DIV 2 /* Divider = 2 */ #define BOARD_PBCLK5 100000000 /* PBCLK5 frequency = 200MHz/2 = 100MHz */ - /* PBCLK6 * Peripherals: */ @@ -313,4 +312,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __CONFIGS_SURE_PIC32MZ_INCLUDE_BOARD_H */ +#endif /* __CONFIGS_PIC32MZ_STARTERKIT_INCLUDE_BOARD_H */ diff --git a/configs/sam3u-ek/README.txt b/configs/sam3u-ek/README.txt index 047beaf47813977f76caccc1c1855bcd75079038..4f63108cbd019c7a882b4ff4000f65fa77606a99 100644 --- a/configs/sam3u-ek/README.txt +++ b/configs/sam3u-ek/README.txt @@ -8,204 +8,14 @@ ATSAM3U4E MCU running at 96MHz. Contents ^^^^^^^^ - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - - AtmelStudio6.1 + - AtmelStudio 6.1 - LEDs - Serial Console - SAM3U-EK-specific Configuration Options - Configurations -Development Environment -^^^^^^^^^^^^^^^^^^^^^^^ - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain. Testing was performed - using the Cygwin environment. - -GNU Toolchain Options -^^^^^^^^^^^^^^^^^^^^^ - - All testing has been conducted using the NuttX buildroot toolchain. To use - other toolchains, such as the CodeSourcery, devkitARM, Atollic, or AtmelStudio - GNU toolchain, you simply need to add one of the following configuration options - to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : Atollic toolchain for Windos - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y : Generic GCC ARM EABI toolchain for Linux - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : Generic GCC ARM EABI toolchain for Windows - - NOTE about Windows native toolchains - ------------------------------------ - - The CodeSourcery (for Windows), Atollic, and devkitARM toolchains are - Windows native toolchains. The CodeSourcery (for Linux), NuttX buildroot, - and, perhaps, the generic GCC toolchains are Cygwin and/or Linux native - toolchains. There are several limitations to using a Windows based - toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -^^^^ - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/sam34, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/sam34/sam_vectors.S. You may need to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by an IDE. - -NuttX EABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh sam3u-ek/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 (and later) GCC toolchain is not compatible - with the NXFLAT tools. See the top-level TODO file (under "Binary loaders") - for more information about this problem. If you plan to use NXFLAT, please do - not use the GCC 4.6.3 toochain; instead use an older toolchain (such as the GCC - 4.3.3 OABI toolchain discussed below). - -NuttX OABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -^^^^^^^^^^^^^^^^ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh sam3u-ek/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - -AtmelStudio6.1 -^^^^^^^^^^^^^^ +AtmelStudio 6.1 +^^^^^^^^^^^^^^^ You can use AtmelStudio6.1 to load and debug code. @@ -628,7 +438,7 @@ Configurations Device Drivers -> MMC/SD Driver Support CONFIG_MMCSD=y : Enable MMC/SD support CONFIG_MMSCD_NSLOTS=1 : One slot per driver instance - CONFIG_MMCSD_HAVECARDDETECT=y : Supports card-detect PIOs + CONFIG_MMCSD_HAVE_CARDDETECT=y : Supports card-detect PIOs CONFIG_MMCSD_SDIO=y : SDIO-based MMC/SD support CONFIG_SDIO_DMA=y : Use SDIO DMA CONFIG_SDIO_BLOCKSETUP=y : Needs to know block sizes diff --git a/configs/sam3u-ek/include/board.h b/configs/sam3u-ek/include/board.h index 52b9647f6c66ae01ee91e5dd9a2d22b58d082148..df11074fd28e93d43c4a9e7df3139fb57c275d19 100644 --- a/configs/sam3u-ek/include/board.h +++ b/configs/sam3u-ek/include/board.h @@ -156,39 +156,4 @@ #define BUTTON1 1 /* Bit 0: Button 1 */ #define BUTTON2 2 /* Bit 1: Button 2 */ -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: sam_boardinitialize - * - * Description: - * All SAM3U architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void sam_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_SAM3U_EK_INCLUDE_BOARD_H */ diff --git a/configs/sam3u-ek/knsh/defconfig b/configs/sam3u-ek/knsh/defconfig index fb3c156632fe393a834d26b92161092b1bc38ce0..42a9605021063657c6426377d3bc41c7c64e3d95 100644 --- a/configs/sam3u-ek/knsh/defconfig +++ b/configs/sam3u-ek/knsh/defconfig @@ -1,5 +1,5 @@ # CONFIG_ARCH_RAMFUNCS is not set -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set diff --git a/configs/sam3u-ek/nx/defconfig b/configs/sam3u-ek/nx/defconfig index eeab7c1caef1160418c2ed21f0fe6d09dbf9d513..cff50854b4fae1593ddd0652289452a475c6f7cc 100644 --- a/configs/sam3u-ek/nx/defconfig +++ b/configs/sam3u-ek/nx/defconfig @@ -2,6 +2,7 @@ # CONFIG_EXAMPLES_NX_DEFAULT_COLORS is not set # CONFIG_NX_DISABLE_16BPP is not set # CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set CONFIG_ARCH_BOARD_SAM3UEK=y CONFIG_ARCH_BOARD="sam3u-ek" CONFIG_ARCH_BUTTONS=y diff --git a/configs/sam3u-ek/nxwm/defconfig b/configs/sam3u-ek/nxwm/defconfig index 2445ea69a664267c3ac38cd059a6ac4a3e7e5862..3e21c6bd89234cfc955beee0e288dfd791de7c84 100644 --- a/configs/sam3u-ek/nxwm/defconfig +++ b/configs/sam3u-ek/nxwm/defconfig @@ -1,9 +1,9 @@ # CONFIG_ARCH_RAMFUNCS is not set -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set CONFIG_ADS7843E_SPIDEV=2 CONFIG_ADS7843E_SWAPXY=y CONFIG_ADS7843E_THRESHX=51 @@ -64,7 +64,6 @@ CONFIG_NXWM_KEYBOARD_LISTENERPRIO=100 CONFIG_NXWM_KEYBOARD_LISTENERSTACK=1024 CONFIG_NXWM_KEYBOARD=y CONFIG_NXWM_NXTERM_STACKSIZE=1596 -CONFIG_NXWM_STARTWINDOW_MQNAME="nxwm" CONFIG_NXWM_STARTWINDOW_STACKSIZE=1596 CONFIG_NXWM_TASKBAR_HSPACING=4 CONFIG_NXWM_TASKBAR_LEFT=y diff --git a/configs/sam4cmp-db/include/board.h b/configs/sam4cmp-db/include/board.h index 1339e6ec670dc725add60ea45d8e51bd1402d6af..dd5245a60bb56c96278ae69ed6054ae2d859882a 100644 --- a/configs/sam4cmp-db/include/board.h +++ b/configs/sam4cmp-db/include/board.h @@ -139,40 +139,4 @@ #define BOARD_FWS 5 -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: sam_boardinitialize - * - * Description: - * All SAM3U architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void sam_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_SAM4CMP_DB_INCLUDE_BOARD_H */ diff --git a/configs/sam4e-ek/README.txt b/configs/sam4e-ek/README.txt index 90fc5cc0d8693c31d21f143621e3282948c276f1..58c4c4c7858c3d0c78da9c8c150ef1f88c133069 100644 --- a/configs/sam4e-ek/README.txt +++ b/configs/sam4e-ek/README.txt @@ -8,12 +8,6 @@ or 120MHz. Contents ======== - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - Atmel Studio 6.1 - Loading Code with J-Link - Loading Code OpenOCD @@ -29,187 +23,6 @@ Contents - SAM4E-EK-specific Configuration Options - Configurations -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -===================== - - The NuttX make system can be configured to support the various different - toolchain options. All testing has been conducted using the NuttX buildroot - toolchain. To use alternative toolchain, you simply need to add change of - the following configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : Atollic toolchain for Windos - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y : Generic GCC ARM EABI toolchain for Linux - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : Generic GCC ARM EABI toolchain for Windows - - NOTE about Windows native toolchains - ------------------------------------ - - There are basically three kinds of GCC toolchains that can be used: - - 1. A Linux native toolchain in a Linux environment, - 2. The buildroot Cygwin tool chain built in the Cygwin environment, - 3. A Windows native toolchain. - - There are several limitations to using a Windows based toolchain (#3) in a - Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' - utility but you might easily find some new path problems. If so, check - out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic - links are used in Nuttx (e.g., include/arch). The make system works - around these problems for the Windows tools by copying directories - instead of linking them. But this can also cause some confusion for - you: For example, you may edit a file in a "linked" directory and find - that your changes had no effect. That is because you are building the - copy of the file in the "fake" symbolic directory. If you use a - Windows toolchain, you should get in the habit of making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/sam34, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/sam34/sam_vectors.S. You may need to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by an IDE. - -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh sam4e-ek/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh sam4e-ek/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - Atmel Studio 6.1 ================ @@ -865,7 +678,7 @@ HSMCI Device Drivers -> MMC/SD Driver Support CONFIG_MMCSD=y : Enable MMC/SD support CONFIG_MMCSD_NSLOTS=1 : One slot per driver instance - CONFIG_MMCSD_HAVECARDDETECT=y : Supports card-detect PIOs + CONFIG_MMCSD_HAVE_CARDDETECT=y : Supports card-detect PIOs CONFIG_MMCSD_SDIO=y : SDIO-based MMC/SD support CONFIG_MMCSD_MULTIBLOCK_DISABLE=y : Probably works but is untested diff --git a/configs/sam4e-ek/include/board.h b/configs/sam4e-ek/include/board.h index 8a9c965ac1dae30bbc2fdb86e93be4109124c886..5c942b818fff36d8abd24aa923d541fe3e2c2d45 100644 --- a/configs/sam4e-ek/include/board.h +++ b/configs/sam4e-ek/include/board.h @@ -283,17 +283,6 @@ extern "C" /************************************************************************************ * Public Function Prototypes ************************************************************************************/ -/************************************************************************************ - * Name: sam_boardinitialize - * - * Description: - * All SAM4E architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void sam_boardinitialize(void); /************************************************************************************ * Name: sam_lcdclear diff --git a/configs/sam4e-ek/nxwm/defconfig b/configs/sam4e-ek/nxwm/defconfig index 9ebf677a6c6bcf76dc9a44fc28ca7d53c24d9f3a..a9b0bb4aea7d76915eab1526bc77c854a4792f64 100644 --- a/configs/sam4e-ek/nxwm/defconfig +++ b/configs/sam4e-ek/nxwm/defconfig @@ -1,9 +1,9 @@ # CONFIG_ARCH_RAMFUNCS is not set # CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set CONFIG_ADS7843E_SWAPXY=y CONFIG_ADS7843E_THRESHX=51 CONFIG_ADS7843E_THRESHY=39 diff --git a/configs/sam4l-xplained/README.txt b/configs/sam4l-xplained/README.txt index 03507e46f567b3669a27b1d6fc8989bda5af79ab..7178b3e31df5deae4bbd0d801979a00a5a18d755 100644 --- a/configs/sam4l-xplained/README.txt +++ b/configs/sam4l-xplained/README.txt @@ -19,12 +19,6 @@ Contents ^^^^^^^^ - Modules - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - LEDs - Serial Consoles - SAM4L Xplained Pro-specific Configuration Options @@ -180,198 +174,6 @@ Modules A prototyping board with logic on board (other than power-related logic). There is no built-in support for the PROTO1 module. -Development Environment -^^^^^^^^^^^^^^^^^^^^^^^ - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -^^^^^^^^^^^^^^^^^^^^^ - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The devkitARM GNU toolchain, ok - 4. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the NuttX buildroot toolchain. To use - the CodeSourcery, devkitARM or Raisonance GNU toolchain, you simply need to - add one of the following configuration options to your .config (or defconfig) - file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : Atollic toolchain for Windos - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y : Generic GCC ARM EABI toolchain for Linux - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : Generic GCC ARM EABI toolchain for Windows - - NOTE about Windows native toolchains - ------------------------------------ - - The CodeSourcery (for Windows), Atollic, and devkitARM toolchains are - Windows native toolchains. The CodeSourcery (for Linux), NuttX buildroot, - and, perhaps, the generic GCC toolchains are Cygwin and/or Linux native - toolchains. There are several limitations to using a Windows based - toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -^^^^ - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/sam34, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/sam34/sam_vectors.S. You may need to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by an IDE. - -NuttX EABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh sam4l-xplained/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -^^^^^^^^^^^^^^^^ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - LEDs ^^^^ There are three LEDs on board the SAM4L Xplained Pro board: The EDBG @@ -723,7 +525,7 @@ Configuration sub-directories CONFIG_MMCSD=y : Enable MMC/SD support CONFIG_MMCSD_NSLOTS=1 : Only one MMC/SD card slot CONFIG_MMCSD_MULTIBLOCK_DISABLE=n : Should not need to disable multi-block transfers - CONFIG_MMCSD_HAVECARDDETECT=y : I/O1 module as a card detect GPIO + CONFIG_MMCSD_HAVE_CARDDETECT=y : I/O1 module as a card detect GPIO CONFIG_MMCSD_SPI=y : Use the SPI interface to the MMC/SD card CONFIG_MMCSD_SPICLOCK=20000000 : This is a guess for the optimal MMC/SD frequency CONFIG_MMCSD_SPIMODE=0 : Mode 0 is required diff --git a/configs/sam4l-xplained/include/board.h b/configs/sam4l-xplained/include/board.h index f299f063ecdba9351663b583c5c9f15b7d7ca4c1..fac6c473131d27cd389f0652c8caf6e989604c70 100644 --- a/configs/sam4l-xplained/include/board.h +++ b/configs/sam4l-xplained/include/board.h @@ -287,40 +287,4 @@ #define GPIO_SPI0_MOSI GPIO_SPI0_MOSI_1 #define GPIO_SPI0_SPCK GPIO_SPI0_SPCK_4 -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: sam_boardinitialize - * - * Description: - * All SAM3U architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void sam_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_SAM4L_XPLAINED_INCLUDE_BOARD_H */ diff --git a/configs/sam4s-xplained-pro/README.txt b/configs/sam4s-xplained-pro/README.txt index 9cb17447dbe98438ff69e595c2c6b54f0982f77c..6b62f3fcdcded3aecc9670bc6a2c8b16fb9ebe63 100644 --- a/configs/sam4s-xplained-pro/README.txt +++ b/configs/sam4s-xplained-pro/README.txt @@ -22,12 +22,6 @@ Contents ^^^^^^^^ - PIO Muliplexing - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - Buttons and LEDs - Serial Consoles - SAM4S Xplained-specific Configuration Options @@ -69,206 +63,6 @@ PIO Muliplexing PA30 J4.5 PC30 SMC_A12 PA31 J1.5 PC31 SMC_A13 -Development Environment -^^^^^^^^^^^^^^^^^^^^^^^ - - Several possibile development enviorments may be use: - - - Linux or OSX native - - Cygwin unders Windows - - MinGW + MSYS under Windows - - Windows native (with GNUMake from GNUWin32). - - All testing has been performed using Cygwin under Windows. - - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. - -GNU Toolchain Options -^^^^^^^^^^^^^^^^^^^^^ - - The NuttX make system has been modified to support the several different - toolchain options. - - All testing has been conducted using the NuttX buildroot toolchain. To use - the CodeSourcery, devkitARM or Raisonance GNU toolchain, you simply need to - add one of the following configuration options to your .config (or defconfig) - file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : Atollic toolchain for Windos - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y : Generic GCC ARM EABI toolchain for Linux - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : Generic GCC ARM EABI toolchain for Windows - - If you are not using CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT, then you may also - have to modify the PATH environment variable if your make cannot find the - tools. - - NOTE about Windows native toolchains - ------------------------------------ - - The CodeSourcery (for Windows), Atollic, and devkitARM toolchains are - Windows native toolchains. The CodeSourcery (for Linux), NuttX buildroot, - and, perhaps, the generic GCC toolchains are Cygwin and/or Linux native - toolchains. There are several limitations to using a Windows based - toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: Older CodeSourcery toolchains (2009q1) do not work with default - optimization level of -Os (See Make.defs). It will work with -O0, -O1, or - -O2, but not with -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -^^^^ - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project (There is a simple RIDE project - in the RIDE subdirectory). - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/sam34, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/sam34/sam_vectors.S. You may need to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by RIDE. - -NuttX EABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh sam4s-xplained-pro/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -^^^^^^^^^^^^^^^^ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh sam4s-xplained-pro/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - Buttons and LEDs ^^^^^^^^^^^^^^^^ diff --git a/configs/sam4s-xplained-pro/include/board.h b/configs/sam4s-xplained-pro/include/board.h index 0ef923c7e3baf7f30c600e98c13110d150c80caf..61b3175d0cccda950ece0314ef392ee59b68d05a 100644 --- a/configs/sam4s-xplained-pro/include/board.h +++ b/configs/sam4s-xplained-pro/include/board.h @@ -251,40 +251,4 @@ #define BUTTON_SW0_BIT (1 << BUTTON_SW0) -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: sam_boardinitialize - * - * Description: - * All SAM3U architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void sam_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_SAM4S_XPLAINED_PRO_INCLUDE_BOARD_H */ diff --git a/configs/sam4s-xplained-pro/src/sam4s-xplained-pro.h b/configs/sam4s-xplained-pro/src/sam4s-xplained-pro.h index d995541bbbd65553adbff01bf2bc4fec776957f3..a20eb969deb67155104a0e7a7394cf259bfd02da 100644 --- a/configs/sam4s-xplained-pro/src/sam4s-xplained-pro.h +++ b/configs/sam4s-xplained-pro/src/sam4s-xplained-pro.h @@ -197,7 +197,7 @@ int sam_hsmci_initialize(void); * ************************************************************************************/ -#if defined(HAVE_HSMCI) && defined(CONFIG_MMCSD_HAVECARDDETECT) +#if defined(HAVE_HSMCI) && defined(CONFIG_MMCSD_HAVE_CARDDETECT) bool sam_cardinserted(int slotno); #endif diff --git a/configs/sam4s-xplained-pro/src/sam_hsmci.c b/configs/sam4s-xplained-pro/src/sam_hsmci.c index 1446269a5d5167b57c317a72b024ff5d29555f5f..dc62e4a56927692e30e11b5c821d6f133b2f3662 100644 --- a/configs/sam4s-xplained-pro/src/sam_hsmci.c +++ b/configs/sam4s-xplained-pro/src/sam_hsmci.c @@ -94,7 +94,7 @@ static struct sam_hsmci_state_s g_hsmci; * ****************************************************************************/ -#ifdef CONFIG_MMCSD_HAVECARDDETECT +#ifdef CONFIG_MMCSD_HAVE_CARDDETECT static int sam_hsmci_cardetect_int(int irq, void *regs, FAR void *arg) { bool inserted; @@ -160,7 +160,7 @@ int sam_hsmci_initialize(void) return ret; } -#ifdef CONFIG_MMCSD_HAVECARDDETECT +#ifdef CONFIG_MMCSD_HAVE_CARDDETECT /* Initialize card-detect GPIO. There is no write-protection GPIO. */ sam_configgpio(GPIO_MCI_CD); @@ -183,7 +183,7 @@ int sam_hsmci_initialize(void) /* Enable card detect interrupts */ -#ifdef CONFIG_MMCSD_HAVECARDDETECT +#ifdef CONFIG_MMCSD_HAVE_CARDDETECT sam_gpioirqenable(MCI_CD_IRQ); #endif } @@ -199,7 +199,7 @@ int sam_hsmci_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_MMCSD_HAVECARDDETECT +#ifdef CONFIG_MMCSD_HAVE_CARDDETECT bool sam_cardinserted(int slotno) { bool removed; diff --git a/configs/sam4s-xplained/README.txt b/configs/sam4s-xplained/README.txt index 6aab73ec5b51c56dddbc763e160c3069c4e16a42..9dd7f85cfad7633c51294f8a73267425e8d1ae7e 100644 --- a/configs/sam4s-xplained/README.txt +++ b/configs/sam4s-xplained/README.txt @@ -22,12 +22,6 @@ Contents ^^^^^^^^ - PIO Muliplexing - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - Buttons and LEDs - Serial Consoles - SAM4S Xplained-specific Configuration Options @@ -69,201 +63,6 @@ PIO Muliplexing PA30 J4.5 PC30 SMC_A12 PA31 J1.5 PC31 SMC_A13 -Development Environment -^^^^^^^^^^^^^^^^^^^^^^^ - - Several possibile development enviorments may be use: - - - Linux or OSX native - - Cygwin unders Windows - - MinGW + MSYS under Windows - - Windows native (with GNUMake from GNUWin32). - - All testing has been performed using Cygwin under Windows. - - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. - -GNU Toolchain Options -^^^^^^^^^^^^^^^^^^^^^ - - The NuttX make system has been modified to support the several different - toolchain options. - - All testing has been conducted using the NuttX buildroot toolchain. To use - the CodeSourcery, devkitARM or Raisonance GNU toolchain, you simply need to - add one of the following configuration options to your .config (or defconfig) - file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : Atollic toolchain for Windos - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y : Generic GCC ARM EABI toolchain for Linux - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : Generic GCC ARM EABI toolchain for Windows - - NOTE about Windows native toolchains - ------------------------------------ - - The CodeSourcery (for Windows), Atollic, and devkitARM toolchains are - Windows native toolchains. The CodeSourcery (for Linux), NuttX buildroot, - and, perhaps, the generic GCC toolchains are Cygwin and/or Linux native - toolchains. There are several limitations to using a Windows based - toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: Older CodeSourcery toolchains (2009q1) do not work with default - optimization level of -Os (See Make.defs). It will work with -O0, -O1, or - -O2, but not with -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -^^^^ - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/sam34, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/sam34/sam_vectors.S. You may need to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by an IDE. - -NuttX EABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.shsam4s-xplained/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -^^^^^^^^^^^^^^^^ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh sam4s-xplained/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - Buttons and LEDs ^^^^^^^^^^^^^^^^ diff --git a/configs/sam4s-xplained/include/board.h b/configs/sam4s-xplained/include/board.h index 3457a08bd783d98a3606cca6ea35050586246e37..7fb619d9528d76dd7f393888fec0015a35f30f09 100644 --- a/configs/sam4s-xplained/include/board.h +++ b/configs/sam4s-xplained/include/board.h @@ -210,40 +210,4 @@ #define BUTTON_BP2_BIT (1 << BUTTON_BP2) -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: sam_boardinitialize - * - * Description: - * All SAM3U architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void sam_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_SAM4L_XPLAINED_INCLUDE_BOARD_H */ diff --git a/configs/sama5d2-xult/include/board.h b/configs/sama5d2-xult/include/board.h index 7de0ca0df689811c590f695ca51b6f7b460516d6..f995882efdba9d7cb63e3293a576ba8e3835e0d3 100644 --- a/configs/sama5d2-xult/include/board.h +++ b/configs/sama5d2-xult/include/board.h @@ -267,40 +267,4 @@ .endm #endif /* __ASSEMBLY__ */ -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: sam_boardinitialize - * - * Description: - * All SAMA5 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void sam_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* !__ASSEMBLY__ */ #endif /* __CONFIGS_SAMA5D2_XULT_INCLUDE_BOARD_H */ diff --git a/configs/sama5d3-xplained/README.txt b/configs/sama5d3-xplained/README.txt index 2e6cb77045a9c53594a299b260f33d0100f5ccab..8711ba449b6dd989421525846607711d002d8658 100644 --- a/configs/sama5d3-xplained/README.txt +++ b/configs/sama5d3-xplained/README.txt @@ -1129,7 +1129,7 @@ HSMCI Card Slots CONFIG_MMCSD=y : Enable MMC/SD support CONFIG_MMSCD_NSLOTS=1 : One slot per driver instance CONFIG_MMCSD_MULTIBLOCK_DISABLE=y : (REVISIT) - CONFIG_MMCSD_HAVECARDDETECT=y : Supports card-detect PIOs + CONFIG_MMCSD_HAVE_CARDDETECT=y : Supports card-detect PIOs CONFIG_MMCSD_MMCSUPPORT=n : Interferes with some SD cards CONFIG_MMCSD_SPI=n : No SPI-based MMC/SD support CONFIG_MMCSD_SDIO=y : SDIO-based MMC/SD support diff --git a/configs/sama5d3-xplained/include/board.h b/configs/sama5d3-xplained/include/board.h index 2358af2a0e42b4da46c8e7ac825fdc8e4b5de1a8..1cfaba1669f409dc15f262177b03802ef5d62bef 100644 --- a/configs/sama5d3-xplained/include/board.h +++ b/configs/sama5d3-xplained/include/board.h @@ -302,40 +302,4 @@ .endm #endif /* __ASSEMBLY__ */ -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: sam_boardinitialize - * - * Description: - * All SAMA5 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void sam_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* !__ASSEMBLY__ */ #endif /* __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_H */ diff --git a/configs/sama5d3x-ek/README.txt b/configs/sama5d3x-ek/README.txt index 9f6b401f66039a37b574477e8aa25eac55c3c7fc..26007c8f92199e563c45261f42201cf8209c7a7a 100644 --- a/configs/sama5d3x-ek/README.txt +++ b/configs/sama5d3x-ek/README.txt @@ -1305,7 +1305,7 @@ HSMCI Card Slots CONFIG_MMCSD=y : Enable MMC/SD support CONFIG_MMSCD_NSLOTS=1 : One slot per driver instance CONFIG_MMCSD_MULTIBLOCK_DISABLE=y : (REVISIT) - CONFIG_MMCSD_HAVECARDDETECT=y : Supports card-detect PIOs + CONFIG_MMCSD_HAVE_CARDDETECT=y : Supports card-detect PIOs CONFIG_MMCSD_MMCSUPPORT=n : Interferes with some SD cards CONFIG_MMCSD_SPI=n : No SPI-based MMC/SD support CONFIG_MMCSD_SDIO=y : SDIO-based MMC/SD support diff --git a/configs/sama5d3x-ek/include/board.h b/configs/sama5d3x-ek/include/board.h index 9c16288885352777f2d0b85ef5b84874a01cc586..8923c606add22743a3e0530b7b040edaaa8711ab 100644 --- a/configs/sama5d3x-ek/include/board.h +++ b/configs/sama5d3x-ek/include/board.h @@ -343,40 +343,4 @@ .endm #endif /* __ASSEMBLY__ */ -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: sam_boardinitialize - * - * Description: - * All SAMA5 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void sam_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* !__ASSEMBLY__ */ #endif /* __CONFIGS_SAMA5D3X_EK_INCLUDE_BOARD_H */ diff --git a/configs/sama5d3x-ek/nx/defconfig b/configs/sama5d3x-ek/nx/defconfig index 6e116a6d2bb0951f86d5b49441c1fd75a5b5226e..7826eb214284491711886f6569e7f94b4dc9a1a2 100644 --- a/configs/sama5d3x-ek/nx/defconfig +++ b/configs/sama5d3x-ek/nx/defconfig @@ -1,4 +1,5 @@ # CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set CONFIG_ARCH_BOARD_SAMA5D3X_EK=y CONFIG_ARCH_BOARD="sama5d3x-ek" CONFIG_ARCH_CHIP_ATSAMA5D33=y diff --git a/configs/sama5d3x-ek/nxwm/defconfig b/configs/sama5d3x-ek/nxwm/defconfig index e19575143a755bf7ba8e8df97cdb7d5b2433f8a2..998bd7c2523adcfb2d67b30a8125d9b5e1edcb86 100644 --- a/configs/sama5d3x-ek/nxwm/defconfig +++ b/configs/sama5d3x-ek/nxwm/defconfig @@ -1,6 +1,6 @@ -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set CONFIG_ARCH_BOARD_SAMA5D3X_EK=y CONFIG_ARCH_BOARD="sama5d3x-ek" CONFIG_ARCH_CHIP_ATSAMA5D33=y @@ -71,7 +71,6 @@ CONFIG_NXWM_NXTERM_CUSTOM_FONTID=y CONFIG_NXWM_NXTERM_FONTID=3 CONFIG_NXWM_NXTERM_STACKSIZE=1596 CONFIG_NXWM_STARTWINDOW_HSPACING=8 -CONFIG_NXWM_STARTWINDOW_MQNAME="nxwm" CONFIG_NXWM_STARTWINDOW_STACKSIZE=1596 CONFIG_NXWM_STARTWINDOW_VSPACING=8 CONFIG_NXWM_TASKBAR_HSPACING=8 diff --git a/configs/sama5d4-ek/README.txt b/configs/sama5d4-ek/README.txt index 8483a0ddc99a7f7b68882cb6940b18df4cdd042b..40a703e40257a9b9b92c8d0a1daed0a015812a1f 100644 --- a/configs/sama5d4-ek/README.txt +++ b/configs/sama5d4-ek/README.txt @@ -1675,7 +1675,7 @@ HSMCI Card Slots CONFIG_MMCSD=y : Enable MMC/SD support CONFIG_MMSCD_NSLOTS=1 : One slot per driver instance CONFIG_MMCSD_MULTIBLOCK_DISABLE=y : (REVISIT) - CONFIG_MMCSD_HAVECARDDETECT=y : Supports card-detect PIOs + CONFIG_MMCSD_HAVE_CARDDETECT=y : Supports card-detect PIOs CONFIG_MMCSD_MMCSUPPORT=n : Interferes with some SD cards CONFIG_MMCSD_SPI=n : No SPI-based MMC/SD support CONFIG_MMCSD_SDIO=y : SDIO-based MMC/SD support diff --git a/configs/sama5d4-ek/elf/defconfig b/configs/sama5d4-ek/elf/defconfig index 01f7ecd7843fa934a7949691129d6c5e0e210d57..963426af7ca2e3e07fd7514e374271f67367d08d 100644 --- a/configs/sama5d4-ek/elf/defconfig +++ b/configs/sama5d4-ek/elf/defconfig @@ -2,7 +2,6 @@ CONFIG_ARCH_ADDRENV=y CONFIG_ARCH_BOARD_SAMA5D4_EK=y CONFIG_ARCH_BOARD="sama5d4-ek" -CONFIG_BOARD_INITIALIZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP_ATSAMA5D44=y CONFIG_ARCH_CHIP_SAMA5=y @@ -23,19 +22,20 @@ CONFIG_ARCH_TEXT_NPAGES=256 CONFIG_ARCH_TEXT_VBASE=0x80000000 CONFIG_ARCH="arm" CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y -CONFIG_DRIVERS_AUDIO=y +CONFIG_BOARD_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=65775 CONFIG_BOOT_RUNFROMSDRAM=y CONFIG_BUILTIN=y CONFIG_DEV_ZERO=y -CONFIG_ELF=y +CONFIG_DRIVERS_AUDIO=y CONFIG_ELF_STACKSIZE=4096 +CONFIG_ELF=y CONFIG_EXAMPLES_ELF_SYSCALL=y CONFIG_EXAMPLES_ELF=y CONFIG_EXECFUNCS_SYMTAB="exports" CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y CONFIG_FS_ROMFS=y -CONFIG_GRAN_SINGLE=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y diff --git a/configs/sama5d4-ek/include/board.h b/configs/sama5d4-ek/include/board.h index 807fece06ddca0fb7b35136e70df7d53a0e80ad7..f70c397d9e83b73a970e09fda68655df1eedc40c 100644 --- a/configs/sama5d4-ek/include/board.h +++ b/configs/sama5d4-ek/include/board.h @@ -273,40 +273,4 @@ .endm #endif /* __ASSEMBLY__ */ -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: sam_boardinitialize - * - * Description: - * All SAMA5 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void sam_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* !__ASSEMBLY__ */ #endif /* __CONFIGS_SAMA5D4_EK_INCLUDE_BOARD_H */ diff --git a/configs/sama5d4-ek/ipv6/defconfig b/configs/sama5d4-ek/ipv6/defconfig index f3ac2b21f705112ab98f599a439bdf1830aaaa0a..86844bdda00cee3801046541573aca75f03f0ffd 100644 --- a/configs/sama5d4-ek/ipv6/defconfig +++ b/configs/sama5d4-ek/ipv6/defconfig @@ -1,9 +1,9 @@ # CONFIG_AUDIO_FORMAT_MP3 is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NET_IPv4 is not set -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_SAMA5_UART0 is not set # CONFIG_SAMA5_UHPHS_RHPORT1 is not set CONFIG_ARCH_BOARD_SAMA5D4_EK=y diff --git a/configs/sama5d4-ek/knsh/defconfig b/configs/sama5d4-ek/knsh/defconfig index 246e312996c434fbf1ebc78b5b8af4e62f2ec792..cfdf1d64d29394d724f0904bf640bda133125c82 100644 --- a/configs/sama5d4-ek/knsh/defconfig +++ b/configs/sama5d4-ek/knsh/defconfig @@ -41,7 +41,6 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y CONFIG_FS_ROMFS=y -CONFIG_GRAN_SINGLE=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y diff --git a/configs/sama5d4-ek/nsh/defconfig b/configs/sama5d4-ek/nsh/defconfig index c0e15dc5b96ac26ad326bb09995ccad83732e8bb..2ca2d53e145cfdb8865e3bd7fba75f530678ff2a 100644 --- a/configs/sama5d4-ek/nsh/defconfig +++ b/configs/sama5d4-ek/nsh/defconfig @@ -1,8 +1,8 @@ # CONFIG_AUDIO_FORMAT_MP3 is not set # CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_SAMA5_UART0 is not set # CONFIG_SAMA5_UHPHS_RHPORT1 is not set CONFIG_ARCH_BOARD_SAMA5D4_EK=y diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig index 2d0d6ca55da920ce9d0282c509f255ca52d7d1a1..5970178745b1c66734abef288c9ae902aa1b79e8 100644 --- a/configs/sama5d4-ek/nxwm/defconfig +++ b/configs/sama5d4-ek/nxwm/defconfig @@ -1,8 +1,8 @@ # CONFIG_AUDIO_FORMAT_MP3 is not set # CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXPLAYER_COMMAND_LINE is not set # CONFIG_NXPLAYER_INCLUDE_DEVICE_SEARCH is not set # CONFIG_NXWM_MEDIAPLAYER_NOFILTER is not set diff --git a/configs/samd20-xplained/README.txt b/configs/samd20-xplained/README.txt index ac885a6dd133cec24e8c73a21f58fac118f7dc4d..c8af7952be122f9caeb049468b15ce0f43a49d9f 100644 --- a/configs/samd20-xplained/README.txt +++ b/configs/samd20-xplained/README.txt @@ -57,7 +57,7 @@ STATUS/ISSUES with the USART output on SERCOM4. Both symptoms imply some clock- related issue. - The configuration suggests CONFIG_MMCSD_HAVECARDDETECT=y, but as of + The configuration suggests CONFIG_MMCSD_HAVE_CARDDETECT=y, but as of this writing, there is no support for EIC pin interrupts. 4. OLED1 module is untested. These instructions were just lifted from @@ -766,7 +766,7 @@ Configuration sub-directories CONFIG_MMCSD_NSLOTS=1 : Only one MMC/SD card slot CONFIG_MMCSD_MULTIBLOCK_DISABLE=n : Should not need to disable multi-block transfers CONFIG_MMCSD_MMCSUPPORT=n : May interfere with some SD cards - CONFIG_MMCSD_HAVECARDDETECT=y : I/O1 module as a card detect GPIO + CONFIG_MMCSD_HAVE_CARDDETECT=y : I/O1 module as a card detect GPIO CONFIG_MMCSD_SPI=y : Use the SPI interface to the MMC/SD card CONFIG_MMCSD_SPICLOCK=20000000 : This is a guess for the optimal MMC/SD frequency CONFIG_MMCSD_SPIMODE=0 : Mode 0 is required diff --git a/configs/samd20-xplained/include/board.h b/configs/samd20-xplained/include/board.h index 580b5366a240e7c770f0114b83b74fbd206b0caf..0a4823125a9aee0a134808ddd989823dea3c2095 100644 --- a/configs/samd20-xplained/include/board.h +++ b/configs/samd20-xplained/include/board.h @@ -532,41 +532,4 @@ #define BUTTON_SW0_BIT (1 << BUTTON_SW0) -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: sam_boardinitialize - * - * Description: - * All SAM3U architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void sam_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_SAMD20_XPLAINED_INCLUDE_BOARD_H */ diff --git a/configs/samd21-xplained/README.txt b/configs/samd21-xplained/README.txt index 927a84273edb4343063671117aafffc04bc2e46b..3f3624ff181d2bd5fef061d99aa6dc890bab64c5 100644 --- a/configs/samd21-xplained/README.txt +++ b/configs/samd21-xplained/README.txt @@ -631,7 +631,7 @@ Configuration sub-directories CONFIG_MMCSD_NSLOTS=1 : Only one MMC/SD card slot CONFIG_MMCSD_MULTIBLOCK_DISABLE=n : Should not need to disable multi-block transfers CONFIG_MMCSD_MMCSUPPORT=n : May interfere with some SD cards - CONFIG_MMCSD_HAVECARDDETECT=y : I/O1 module as a card detect GPIO + CONFIG_MMCSD_HAVE_CARDDETECT=y : I/O1 module as a card detect GPIO CONFIG_MMCSD_SPI=y : Use the SPI interface to the MMC/SD card CONFIG_MMCSD_SPICLOCK=20000000 : This is a guess for the optimal MMC/SD frequency CONFIG_MMCSD_SPIMODE=0 : Mode 0 is required diff --git a/configs/samd21-xplained/include/board.h b/configs/samd21-xplained/include/board.h index e51baf7a90f5b7c01811ef392c0bd2e5927f5698..4c7ac71b8862431220d9d7426f8fe427af28e9e8 100644 --- a/configs/samd21-xplained/include/board.h +++ b/configs/samd21-xplained/include/board.h @@ -545,41 +545,4 @@ #define BUTTON_SW0_BIT (1 << BUTTON_SW0) -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: sam_boardinitialize - * - * Description: - * All SAM3U architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void sam_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_SAMD21_XPLAINED_INCLUDE_BOARD_H */ diff --git a/configs/same70-xplained/Kconfig b/configs/same70-xplained/Kconfig index ab5c765cfa9430c6e715b7c79074368f0c4086e3..c2bef1b9513b2458188f561bd1d7e37853fc9615 100644 --- a/configs/same70-xplained/Kconfig +++ b/configs/same70-xplained/Kconfig @@ -22,19 +22,44 @@ config SAME70XPLAINED_MB2_SPI default n choice - prompt "Bee mikroBUS" - depends on SAME70XPLAINED_CLICKSHIELD && IEEE802154_MRF24J40 - default SAME70XPLAINED_MB1_BEE + prompt "mikroBUS1 Click" + depends on SAME70XPLAINED_CLICKSHIELD + default SAME70XPLAINED_MB1_NONE + +config SAME70XPLAINED_MB1_NONE + bool "None" config SAME70XPLAINED_MB1_BEE bool "MRF24J40 Bee in mikroBUS1" + depends on IEEE802154_MRF24J40 + select SAME70XPLAINED_MB1_SPI + +config SAME70XPLAINED_MB1_XBEE + bool "XBee in mikroBUS1" + depends on IEEE802154_XBEE select SAME70XPLAINED_MB1_SPI +endchoice # mikroBUS1 Click + +choice + prompt "mikroBUS2 Click" + depends on SAME70XPLAINED_CLICKSHIELD + default SAME70XPLAINED_MB2_NONE + +config SAME70XPLAINED_MB2_NONE + bool "None" + config SAME70XPLAINED_MB2_BEE bool "MRF24J40 Bee in mikroBUS2" + depends on IEEE802154_MRF24J40 + select SAME70XPLAINED_MB2_SPI + +config SAME70XPLAINED_MB2_XBEE + bool "XBee in mikroBUS2" + depends on IEEE802154_XBEE select SAME70XPLAINED_MB2_SPI -endchoice # Bee mikroBUS +endchoice # mikroBUS2 Click config SAME70XPLAINED_HSMCI0_AUTOMOUNT bool "HSMCI0 automounter" diff --git a/configs/same70-xplained/README.txt b/configs/same70-xplained/README.txt index a237b19e7d93ea38be42d219c893875f06e8769e..9695034a64cb1f67e74c630b5e030e4db5d6b13a 100644 --- a/configs/same70-xplained/README.txt +++ b/configs/same70-xplained/README.txt @@ -163,7 +163,7 @@ the SD slots can be enabled with the following settings: CONFIG_MMCSD=y : Enable MMC/SD support CONFIG_MMSCD_NSLOTS=1 : One slot per driver instance CONFIG_MMCSD_MULTIBLOCK_DISABLE=y : (REVISIT) - CONFIG_MMCSD_HAVECARDDETECT=y : Supports card-detect PIOs + CONFIG_MMCSD_HAVE_CARDDETECT=y : Supports card-detect PIOs CONFIG_MMCSD_MMCSUPPORT=n : Interferes with some SD cards CONFIG_MMCSD_SPI=n : No SPI-based MMC/SD support CONFIG_MMCSD_SDIO=y : SDIO-based MMC/SD support diff --git a/configs/same70-xplained/mrf24j40-starhub/defconfig b/configs/same70-xplained/mrf24j40-starhub/defconfig index 58ec4415ca3e178fdc83f010498e5228d46843ec..6de99c7e4303a3c3d4c9f861f4b8e6e03d72e220 100644 --- a/configs/same70-xplained/mrf24j40-starhub/defconfig +++ b/configs/same70-xplained/mrf24j40-starhub/defconfig @@ -37,7 +37,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_IND_PREALLOC=32 +CONFIG_IEEE802154_MAC=y CONFIG_IEEE802154_MACDEV=y CONFIG_IEEE802154_MRF24J40=y CONFIG_IEEE802154_NETDEV=y @@ -45,7 +45,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_IOB_BUFSIZE=128 CONFIG_IOB_NBUFFERS=32 CONFIG_IOB_NCHAINS=16 -CONFIG_MAC802154_NNOTIF=48 CONFIG_MAC802154_NTXDESC=32 CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 diff --git a/configs/same70-xplained/src/Makefile b/configs/same70-xplained/src/Makefile index 8d2583374b7809a48929d1b56ba4ca9bf27d2e4f..4ff7f4b9eb4504ffa47af00a58b4e2a710f1da26 100644 --- a/configs/same70-xplained/src/Makefile +++ b/configs/same70-xplained/src/Makefile @@ -98,4 +98,8 @@ ifeq ($(CONFIG_IEEE802154_MRF24J40),y) CSRCS += sam_mrf24j40.c endif +ifeq ($(CONFIG_IEEE802154_XBEE),y) +CSRCS += sam_xbee.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/same70-xplained/src/sam_spi.c b/configs/same70-xplained/src/sam_spi.c index 81184cf83a8c4d808f7d1bbffec2148fb030cea8..a9095c462d206aa4585469055d289d5ffdc16521 100644 --- a/configs/same70-xplained/src/sam_spi.c +++ b/configs/same70-xplained/src/sam_spi.c @@ -170,6 +170,18 @@ void sam_spi0select(uint32_t devid, bool selected) break; #endif +#ifdef CONFIG_IEEE802154_XBEE + case SPIDEV_IEEE802154(0): + /* Set the GPIO low to select and high to de-select */ + +#if defined(CONFIG_SAME70XPLAINED_MB1_XBEE) + sam_gpiowrite(CLICK_MB1_CS, !selected); +#elif defined(CONFIG_SAME70XPLAINED_MB2_XBEE) + sam_gpiowrite(CLICK_MB2_CS, !selected); +#endif + break; +#endif + default: break; } diff --git a/configs/same70-xplained/src/sam_xbee.c b/configs/same70-xplained/src/sam_xbee.c index b8ff4329ac044a159ddfd788f2fed77146c45155..11542bf08928e4a723bd672f6fb99d0df1d37fa8 100644 --- a/configs/same70-xplained/src/sam_xbee.c +++ b/configs/same70-xplained/src/sam_xbee.c @@ -76,7 +76,7 @@ struct sam_priv_s uint32_t attncfg; uint32_t rstcfg; uint8_t irq; - uint8_t spidev; + uint8_t csno; }; /**************************************************************************** @@ -92,11 +92,12 @@ struct sam_priv_s * irq_enable - Enable or disable the GPIO interrupt */ -static int sam_reset(FAR const struct xbee_lower_s *lower); +static void sam_reset(FAR const struct xbee_lower_s *lower); static int sam_attach_irq(FAR const struct xbee_lower_s *lower, xcpt_t handler, FAR void *arg); static void sam_enable_irq(FAR const struct xbee_lower_s *lower, bool state); +static bool sam_poll_attn(FAR const struct xbee_lower_s *lower); static int sam_xbee_devsetup(FAR struct sam_priv_s *priv); /**************************************************************************** @@ -116,9 +117,11 @@ static int sam_xbee_devsetup(FAR struct sam_priv_s *priv); #ifdef CONFIG_SAME70XPLAINED_MB1_XBEE static struct sam_priv_s g_xbee_mb1_priv = { + .dev.reset = sam_reset, .dev.attach = sam_attach_irq, .dev.enable = sam_enable_irq, - .intcfg = CLICK_MB1_INTR, + .dev.poll = sam_poll_attn, + .attncfg = CLICK_MB1_INTR, .rstcfg = CLICK_MB1_RESET, .irq = IRQ_MB1, .csno = MB1_CSNO, @@ -128,12 +131,14 @@ static struct sam_priv_s g_xbee_mb1_priv = #ifdef CONFIG_SAME70XPLAINED_MB2_XBEE static struct sam_priv_s g_xbee_mb2_priv = { + .dev.reset = sam_reset, .dev.attach = sam_attach_irq, .dev.enable = sam_enable_irq, - .intcfg = CLICK_MB2_INTR, + .dev.poll = sam_poll_attn, + .attncfg = CLICK_MB2_INTR, .rstcfg = CLICK_MB2_RESET, .irq = IRQ_MB2, - .spidev = MB2_CSNO, + .csno = MB2_CSNO, }; #endif @@ -141,7 +146,7 @@ static struct sam_priv_s g_xbee_mb2_priv = * Private Functions ****************************************************************************/ -static int sam_reset(FAR const struct xbee_lower_s *lower) +static void sam_reset(FAR const struct xbee_lower_s *lower) { FAR struct sam_priv_s *priv = (FAR struct sam_priv_s *)lower; @@ -149,14 +154,11 @@ static int sam_reset(FAR const struct xbee_lower_s *lower) /* Reset pulse */ - sam_gpiowrite(priv->rstcfg, true); sam_gpiowrite(priv->rstcfg, false); + up_udelay(1); + sam_gpiowrite(priv->rstcfg, true); - /* Wait minimum 1.5 ms to allow Xbee a proper boot-up sequence */ - /* TODO: Update time according to datasheet */ - - nxsig_usleep(1500); - return OK; + up_mdelay(100); } static int sam_attach_irq(FAR const struct xbee_lower_s *lower, @@ -214,6 +216,13 @@ static void sam_enable_irq(FAR const struct xbee_lower_s *lower, leave_critical_section(flags); } +static bool sam_poll_attn(FAR const struct xbee_lower_s *lower) +{ + FAR struct sam_priv_s *priv = (FAR struct sam_priv_s *)lower; + + return !sam_gpioread(priv->attncfg); +} + /**************************************************************************** * Name: sam_xbee_devsetup * @@ -286,7 +295,7 @@ int sam_xbee_initialize(void) int ret; #ifdef CONFIG_SAME70XPLAINED_MB1_XBEE - wlinfo("Configuring BEE in mikroBUS1\n"); + wlinfo("Configuring XBee in mikroBUS1\n"); ret = sam_xbee_devsetup(&g_xbee_mb1_priv); if (ret < 0) diff --git a/configs/same70-xplained/src/same70-xplained.h b/configs/same70-xplained/src/same70-xplained.h index 009eef7cb51feebbb58967dc0e771eade6ceb7c3..37219453a7322b9c0e52134f9d2b2b4aca229d9c 100644 --- a/configs/same70-xplained/src/same70-xplained.h +++ b/configs/same70-xplained/src/same70-xplained.h @@ -655,5 +655,21 @@ int sam_at24config(void); int sam_mrf24j40_initialize(void); #endif +/**************************************************************************** + * Name: stm32_xbee_initialize + * + * Description: + * Initialize the XBee device. + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef HAVE_XBEE +int sam_xbee_initialize(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_SAME70_XPLAINED_SRC_SAME70_XPLAINED_H */ diff --git a/configs/saml21-xplained/README.txt b/configs/saml21-xplained/README.txt index 94c22382131a59769db064b6eb0cd43923e25718..88323bfd53424ca026c4df12a003b5f8b5c4944d 100644 --- a/configs/saml21-xplained/README.txt +++ b/configs/saml21-xplained/README.txt @@ -798,7 +798,7 @@ Configuration sub-directories CONFIG_MMCSD_NSLOTS=1 : Only one MMC/SD card slot CONFIG_MMCSD_MULTIBLOCK_DISABLE=n : Should not need to disable multi-block transfers CONFIG_MMCSD_MMCSUPPORT=n : May interfere with some SD cards - CONFIG_MMCSD_HAVECARDDETECT=y : I/O1 module as a card detect GPIO + CONFIG_MMCSD_HAVE_CARDDETECT=y : I/O1 module as a card detect GPIO CONFIG_MMCSD_SPI=y : Use the SPI interface to the MMC/SD card CONFIG_MMCSD_SPICLOCK=20000000 : This is a guess for the optimal MMC/SD frequency CONFIG_MMCSD_SPIMODE=0 : Mode 0 is required diff --git a/configs/saml21-xplained/include/board.h b/configs/saml21-xplained/include/board.h index 5cc260d2741d90493bfe8b5d065324ec54be360c..7ddef33682ac5640e1d192c3a02c6518ba659aff 100644 --- a/configs/saml21-xplained/include/board.h +++ b/configs/saml21-xplained/include/board.h @@ -669,41 +669,4 @@ #define BUTTON_SW0_BIT (1 << BUTTON_SW0) -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: sam_boardinitialize - * - * Description: - * All SAM3U architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void sam_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_SAML21_XPLAINED_INCLUDE_BOARD_H */ diff --git a/configs/samv71-xult/README.txt b/configs/samv71-xult/README.txt index b9c4f34054d60c9c88286a03afde1c9478300dce..c290d05badd3964f851c648eba5a8dc609f87661 100644 --- a/configs/samv71-xult/README.txt +++ b/configs/samv71-xult/README.txt @@ -279,7 +279,7 @@ Enabling HSMCI support. The SAMV7-XULT provides a one, full-size SD memory card CONFIG_MMCSD=y : Enable MMC/SD support CONFIG_MMSCD_NSLOTS=1 : One slot per driver instance CONFIG_MMCSD_MULTIBLOCK_DISABLE=y : (REVISIT) - CONFIG_MMCSD_HAVECARDDETECT=y : Supports card-detect PIOs + CONFIG_MMCSD_HAVE_CARDDETECT=y : Supports card-detect PIOs CONFIG_MMCSD_MMCSUPPORT=n : Interferes with some SD cards CONFIG_MMCSD_SPI=n : No SPI-based MMC/SD support CONFIG_MMCSD_SDIO=y : SDIO-based MMC/SD support @@ -1709,28 +1709,6 @@ NOTES: Configuration sub-directories ----------------------------- - fb - -- - - A simple NSH configuration used for some basic (non-graphic) debug of - the framebuffer character driver at drivers/video/fb.c using test at - apps/examples/fb. The SAMv7-XULT LCD driver does not support a - framebuffer! This configuration uses the LCD framebuffer front end at - drivers/lcd/lcd_framebuffer to convert the LCD interface into a - compatible framebuffer interface. - - NOTES: - - 1. This configuration uses USART0 to avoid conflicts with the LCD mode. - See the section about entitle "Serial Console" for connection of - RS-232 driver hardware. - - STATUS: - 2017-09-17: This configuration was completed. The frame buffer driver - is not yet functional. I see the image only on the right side of the - LCD and the colors appear wrong. NOTE that the similar configuration - for the STM3240G-EVAL is fully functional. - knsh: This is identical to the nsh configuration below except that NuttX diff --git a/configs/samv71-xult/fb/defconfig b/configs/samv71-xult/fb/defconfig deleted file mode 100644 index 19b17bd6a1d1fa64afd0348d9638e25771e93aa3..0000000000000000000000000000000000000000 --- a/configs/samv71-xult/fb/defconfig +++ /dev/null @@ -1,104 +0,0 @@ -# CONFIG_ARCH_RAMFUNCS is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_MMCSD_SPI is not set -# CONFIG_NSH_CMDOPT_DF_H is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_SAMV7_UART0 is not set -# CONFIG_SAMV7_UART2 is not set -# CONFIG_SAMV7_UART4 is not set -CONFIG_ARCH_BOARD_SAMV71_XULT=y -CONFIG_ARCH_BOARD="samv71-xult" -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP_SAMV7=y -CONFIG_ARCH_CHIP_SAMV71=y -CONFIG_ARCH_CHIP_SAMV71Q=y -CONFIG_ARCH_CHIP_SAMV71Q21=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARCH="arm" -CONFIG_ARMV7M_DCACHE=y -CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_LAZYFPU=y -CONFIG_AT24XX_ADDR=0x57 -CONFIG_AT24XX_EXTENDED=y -CONFIG_AT24XX_EXTSIZE=160 -CONFIG_AT24XX_SIZE=2 -CONFIG_BOARD_LOOPSPERMSEC=51262 -CONFIG_BOARDCTL_TSCTEST=y -CONFIG_BUILTIN=y -CONFIG_DISABLE_POLL=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y -CONFIG_EXAMPLES_NSH=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_I2CTOOL_MAXBUS=0 -CONFIG_INPUT_MXT=y -CONFIG_INPUT=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_NOGETRUN=y -CONFIG_LCD=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBM=y -CONFIG_MAX_TASKS=16 -CONFIG_MAX_WDOGPARMS=2 -CONFIG_MMCSD_MULTIBLOCK_DISABLE=y -CONFIG_MMCSD_SDIO=y -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_MTD_AT24XX=y -CONFIG_MTD_AT25=y -CONFIG_MTD_CONFIG=y -CONFIG_MTD=y -CONFIG_NFILE_DESCRIPTORS=8 -CONFIG_NFILE_STREAMS=8 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_READLINE=y -CONFIG_NX_BGCOLOR=0x95fa -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_NX=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=393216 -CONFIG_RAM_START=0x20400000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SAMV7_GPIO_IRQ=y -CONFIG_SAMV7_GPIOA_IRQ=y -CONFIG_SAMV7_GPIOB_IRQ=y -CONFIG_SAMV7_GPIOD_IRQ=y -CONFIG_SAMV7_HSMCI0=y -CONFIG_SAMV7_SMC=y -CONFIG_SAMV7_TWIHS0=y -CONFIG_SAMV7_USART0=y -CONFIG_SAMV7_XDMAC=y -CONFIG_SAMV71XULT_LCD_BGCOLOR=0x95fa -CONFIG_SAMV71XULT_MXTXPLND=y -CONFIG_SCHED_HAVE_PARENT=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_ONEXIT=y -CONFIG_SCHED_WAITPID=y -CONFIG_SDCLONE_DISABLE=y -CONFIG_SDIO_BLOCKSETUP=y -CONFIG_START_DAY=10 -CONFIG_START_MONTH=3 -CONFIG_START_YEAR=2014 -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_USART0_SERIAL_CONSOLE=y -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_USERMAIN_STACKSIZE=1526 -CONFIG_VIDEO_FB=y diff --git a/configs/samv71-xult/mrf24j40-starhub/defconfig b/configs/samv71-xult/mrf24j40-starhub/defconfig index 44a209cba950b0fe54e8a84c98f01554b2a7b90b..049029fd30bf33bc94f2088eae5d1c4590614a28 100644 --- a/configs/samv71-xult/mrf24j40-starhub/defconfig +++ b/configs/samv71-xult/mrf24j40-starhub/defconfig @@ -36,7 +36,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HOST_WINDOWS=y CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_IND_PREALLOC=32 +CONFIG_IEEE802154_MAC=y CONFIG_IEEE802154_MACDEV=y CONFIG_IEEE802154_MRF24J40=y CONFIG_IEEE802154_NETDEV=y @@ -44,7 +44,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_IOB_BUFSIZE=128 CONFIG_IOB_NBUFFERS=32 CONFIG_IOB_NCHAINS=16 -CONFIG_MAC802154_NNOTIF=48 CONFIG_MAC802154_NTXDESC=32 CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 diff --git a/configs/samv71-xult/mxtxplnd/defconfig b/configs/samv71-xult/mxtxplnd/defconfig index 61deb1152cee040cfb127a314e77f64b2eb7cd0c..f3d04b42294b18bb7643fe9593dc1e658e89267a 100644 --- a/configs/samv71-xult/mxtxplnd/defconfig +++ b/configs/samv71-xult/mxtxplnd/defconfig @@ -1,8 +1,8 @@ # CONFIG_ARCH_RAMFUNCS is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_MMCSD_SPI is not set -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_SAMV7_UART0 is not set # CONFIG_SAMV7_UART2 is not set # CONFIG_SAMV7_UART4 is not set diff --git a/configs/samv71-xult/nxwm/defconfig b/configs/samv71-xult/nxwm/defconfig index 774a809371cd8b0b0c78054ae7a253c83c4c6f55..80cc25bf5c7d892f7c0fff3c49aa2b987cd6b551 100644 --- a/configs/samv71-xult/nxwm/defconfig +++ b/configs/samv71-xult/nxwm/defconfig @@ -1,10 +1,10 @@ # CONFIG_ARCH_RAMFUNCS is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_MMCSD_SPI is not set -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_SAMV7_UART0 is not set # CONFIG_SAMV7_UART2 is not set # CONFIG_SAMV7_UART4 is not set @@ -85,7 +85,6 @@ CONFIG_NXWM_DEFAULT_FONTID=5 CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y CONFIG_NXWM_HEXCALCULATOR_FONTID=5 CONFIG_NXWM_KEYBOARD=y -CONFIG_NXWM_STARTWINDOW_MQNAME="nxwm" CONFIG_NXWM_TASKBAR_HSPACING=4 CONFIG_NXWM_TASKBAR_LEFT=y CONFIG_NXWM_TASKBAR_VSPACING=4 diff --git a/configs/samv71-xult/vnc/defconfig b/configs/samv71-xult/vnc/defconfig index cd95bd33e44da11ead5015fc015fad4ff88d9678..61c2b9de4c4e0cef88572d05f01543cd7e6936e5 100644 --- a/configs/samv71-xult/vnc/defconfig +++ b/configs/samv71-xult/vnc/defconfig @@ -1,7 +1,6 @@ # CONFIG_ARCH_RAMFUNCS is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_MMCSD_SPI is not set -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NX_DISABLE_8BPP is not set # CONFIG_SAMV7_UART0 is not set # CONFIG_SAMV7_UART2 is not set diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig index 469e3f8467cecfae36b43ea056d4c1403feded83..ac4e18a30d880b9b4296befbb1740da56d0dee77 100644 --- a/configs/samv71-xult/vnxwm/defconfig +++ b/configs/samv71-xult/vnxwm/defconfig @@ -1,7 +1,6 @@ # CONFIG_ARCH_RAMFUNCS is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_MMCSD_SPI is not set -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NX_DISABLE_8BPP is not set # CONFIG_SAMV7_UART0 is not set # CONFIG_SAMV7_UART2 is not set diff --git a/configs/shenzhou/README.txt b/configs/shenzhou/README.txt index 2fb9dd6eec798fdf8ced985790e6ad7fd29b43e5..b76c2f9ef6059673ee5d1ca780d445050859cda8 100644 --- a/configs/shenzhou/README.txt +++ b/configs/shenzhou/README.txt @@ -37,12 +37,6 @@ Contents ======== - STM32F107VCT Pin Usage - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI buildroot Toolchain - - NuttX OABI buildroot Toolchain - - NXFLAT Toolchain - Shenzhou-specific Configuration Options - LEDs - Shenzhou-specific Configuration Options @@ -184,240 +178,6 @@ PN NAME SIGNAL NOTES 19 VSSA VSSA 20 VREF- VREF- -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment because the development tools that I used only work under Windows. - -GNU Toolchain Options -===================== - - Toolchain Configurations - ------------------------ - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The Atollic Toolchain, - 3. The devkitARM GNU toolchain, - 4. Raisonance GNU toolchain, or - 5. The NuttX buildroot Toolchain (see below). - - Most testing has been conducted using the CodeSourcery toolchain for Windows and - that is the default toolchain in most configurations. To use the Atollic, - devkitARM, Raisonance GNU, or NuttX buildroot toolchain, you simply need to - add one of the following configuration options to your .config (or defconfig) - file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : The Atollic toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE=y : Raisonance RIDE7 under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - NOTE: the CodeSourcery (for Windows), Atollic, devkitARM, and Raisonance toolchains are - Windows native toolchains. The CodeSourcery (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - The CodeSourcery Toolchain (2009q1) - ----------------------------------- - The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - The Atollic "Pro" and "Lite" Toolchain - -------------------------------------- - One problem that I had with the Atollic toolchains is that the provide a gcc.exe - and g++.exe in the same bin/ file as their ARM binaries. If the Atollic bin/ path - appears in your PATH variable before /usr/bin, then you will get the wrong gcc - when you try to build host executables. This will cause to strange, uninterpretable - errors build some host binaries in tools/ when you first make. - - The Atollic "Lite" Toolchain - ---------------------------- - The free, "Lite" version of the Atollic toolchain does not support C++ nor - does it support ar, nm, objdump, or objdcopy. If you use the Atollic "Lite" - toolchain, you will have to set: - - CONFIG_HAVE_CXX=n - - In order to compile successfully. Otherwise, you will get errors like: - - "C++ Compiler only available in TrueSTUDIO Professional" - - The make may then fail in some of the post link processing because of some of - the other missing tools. The Make.defs file replaces the ar and nm with - the default system x86 tool versions and these seem to work okay. Disable all - of the following to avoid using objcopy: - - CONFIG_RRLOAD_BINARY=n - CONFIG_INTELHEX_BINARY=n - CONFIG_MOTOROLA_SREC=n - CONFIG_RAW_BINARY=n - - devkitARM - --------- - The devkitARM toolchain includes a version of MSYS make. Make sure that the - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/stm32, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by RIDE. - -NuttX EABI buildroot Toolchain -============================== - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh shenzhou/ - - cd .. - make context - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Edit nuttx/.config to select the buildroot toolchain as described above - and below: - - -CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y - +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y - - 9. Make sure that the PATH variable includes the path to the newly built binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - detailed PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - LEDs ==== @@ -857,7 +617,5 @@ Where is one of the following: This builds the THTTPD web server example using the THTTPD and the apps/examples/thttpd application. - NOTE: See note above with regard to the EABI/OABI buildroot - toolchains. This example can only be built using the older - OABI toolchain due to incompatibilities introduced in later - GCC releases. + NOTE: This example can only be built using the older toolchains + due to incompatibilities introduced in later GCC releases. diff --git a/configs/shenzhou/include/board.h b/configs/shenzhou/include/board.h index f55ca113dfb863c330e420b386ebfa5febc9f1da..e19d4df3d4640a40691fe5d9865674bbb6d68710 100644 --- a/configs/shenzhou/include/board.h +++ b/configs/shenzhou/include/board.h @@ -356,17 +356,6 @@ extern "C" { /************************************************************************************ * Public Function Prototypes ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); /************************************************************************************ * Name: stm32_lcdclear diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig index c98dcd58a8bfdc8860640af96eb15548cf3beb29..33241b13dc7dadcd75b7a2ce32ce4595913ea65a 100644 --- a/configs/shenzhou/nxwm/defconfig +++ b/configs/shenzhou/nxwm/defconfig @@ -1,9 +1,9 @@ -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set # CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set CONFIG_ADS7843E_SPIDEV=3 CONFIG_ADS7843E_SWAPXY=y diff --git a/configs/sim/README.txt b/configs/sim/README.txt index 2d6ed00f914a40d9f292aae627fb566de1a8dcbe..226ddd3ffd8f3933eb7f1f33c7e40cff8f95c187 100644 --- a/configs/sim/README.txt +++ b/configs/sim/README.txt @@ -954,13 +954,9 @@ udgram To use the test: - nsh> mount -t binfs /bin nsh> server & nsh> client - For the sake of sanity, binfs and logins are disabled in this - configuration. - unionfs This is a version of NSH dedicated to performing the simple test @@ -1038,6 +1034,20 @@ unionfs You can see the files in the two file systems before they were unified at apps/examples/unionfs/atestdir and btestdir. +userfs + + This is another NSH configuration that includes the built-in application of apps/examples/userfs to support test of the UserFS on the simulation platform. + + To use the test: + + nsh> userfs # Mounts the UserFS test file system at + # /mnt/ufstest + nsh> mount # Testing is then performed by exercising the + # file system from the command line + nsh> ls -l /mnt/ufstest + nsh> cat /mnt/ufstest/File1 + etc. + ustream This is the same as the nsh configuration except that it includes diff --git a/configs/sim/fb/defconfig b/configs/sim/fb/defconfig index 19a5016415231770a4cdeacdeb636a89f100423c..4d96384304d1ea1b7c28d724d46beaaad28458de 100644 --- a/configs/sim/fb/defconfig +++ b/configs/sim/fb/defconfig @@ -1,5 +1,3 @@ -# CONFIG_NX_DISABLE_8BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set CONFIG_ARCH_BOARD_SIM=y CONFIG_ARCH_BOARD="sim" CONFIG_ARCH_SIM=y @@ -10,14 +8,10 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_POLL=y CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DRIVERS_VIDEO=y CONFIG_EXAMPLES_FB=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_MAX_TASKS=16 -CONFIG_NX_KBD=y -CONFIG_NX_UPDATE=y -CONFIG_NX_XYINPUT_MOUSE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS23X27=y CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_SDCLONE_DISABLE=y CONFIG_SIM_FRAMEBUFFER=y @@ -26,5 +20,4 @@ CONFIG_START_MONTH=11 CONFIG_START_YEAR=2008 CONFIG_USER_ENTRYPOINT="fb_main" CONFIG_USERMAIN_STACKSIZE=4096 -CONFIG_DRIVERS_VIDEO=y CONFIG_VIDEO_FB=y diff --git a/configs/sim/nxwm/defconfig b/configs/sim/nxwm/defconfig index 695f602eb086f4e17adcaf739a36b01ba18c12c4..17fadb5035f764a7eefcb9368d5c13f0082704f1 100644 --- a/configs/sim/nxwm/defconfig +++ b/configs/sim/nxwm/defconfig @@ -1,4 +1,3 @@ -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_NX_DISABLE_32BPP is not set # CONFIG_NX_PACKEDMSFIRST is not set @@ -38,7 +37,6 @@ CONFIG_NXWIDGETS_SIZEOFCHAR=1 CONFIG_NXWIDGETS=y CONFIG_NXWM_BACKGROUND_IMAGE="" CONFIG_NXWM_NXTERM_STACKSIZE=8192 -CONFIG_NXWM_STARTWINDOW_MQNAME="nxwm" CONFIG_NXWM_TASKBAR_LEFT=y CONFIG_NXWM_UNITTEST=y CONFIG_NXWM=y diff --git a/configs/sim/src/sim_bringup.c b/configs/sim/src/sim_bringup.c index aa10551fd3c62637bf6537cdd5839c7eb9137bb5..22351f6270bf62155dc2db2778d4e382cef74e42 100644 --- a/configs/sim/src/sim_bringup.c +++ b/configs/sim/src/sim_bringup.c @@ -46,6 +46,9 @@ #include #include +#include +#include +#include #include #include #include @@ -97,6 +100,9 @@ int sim_bringup(void) { #ifdef CONFIG_ONESHOT FAR struct oneshot_lowerhalf_s *oneshot; +#endif +#ifdef CONFIG_RAMMTD + FAR uint8_t *ramstart; #endif int ret; @@ -112,13 +118,61 @@ int sim_bringup(void) (void)sim_gpio_initialize(); #endif +#ifdef CONFIG_RAMMTD + /* Create a RAM MTD device if configured */ + + ramstart = (FAR uint8_t *)kmm_malloc(32 * 1024); + if (ramstart == NULL) + { + syslog(LOG_ERR, "ERROR: Allocation for RAM MTD failed\n"); + } + else + { + /* Initialized the RAM MTD */ + + FAR struct mtd_dev_s *mtd = rammtd_initialize(ramstart, 32 * 1024); + if (mtd == NULL) + { + syslog(LOG_ERR, "ERROR: rammtd_initialize failed\n"); + kmm_free(ramstart); + } + else + { + /* Erase the RAM MTD */ + + ret = mtd->ioctl(mtd, MTDIOC_BULKERASE, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: IOCTL MTDIOC_BULKERASE failed\n"); + } + +#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) + /* Initialize a SMART Flash block device and bind it to the MTD + * device. + */ + + smart_initialize(0, mtd, NULL); +#elif defined(CONFIG_FS_NXFFS) + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: NXFFS initialization failed: %d\n", + ret); + } +#endif + } + } +#endif + #ifdef CONFIG_ONESHOT /* Get an instance of the simulated oneshot timer */ oneshot = oneshot_initialize(0, 0); if (oneshot == NULL) { - syslog(LOG_ERR, "ERROR: oneshot_initialize faile\n"); + syslog(LOG_ERR, "ERROR: oneshot_initialize failed\n"); } else { diff --git a/configs/sim/userfs/defconfig b/configs/sim/userfs/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..91ee878ec2aa7f3998e9209462e031f91f607842 --- /dev/null +++ b/configs/sim/userfs/defconfig @@ -0,0 +1,61 @@ +# CONFIG_NET_ETHERNET is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_DATE is not set +# CONFIG_NSH_NETINIT is not set +CONFIG_ARCH_BOARD_SIM=y +CONFIG_ARCH_BOARD="sim" +CONFIG_ARCH_SIM=y +CONFIG_ARCH="sim" +CONFIG_BINFMT_EXEPATH=y +CONFIG_BOARD_LOOPSPERMSEC=0 +CONFIG_BOARDCTL_POWEROFF=y +CONFIG_BOOT_RUNFROMEXTSRAM=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_LOOP=y +CONFIG_DEV_ZERO=y +CONFIG_DISABLE_POLL=y +CONFIG_EXAMPLES_NSH=y +CONFIG_EXAMPLES_USERFS_STACKSIZE=8192 +CONFIG_EXAMPLES_USERFS=y +CONFIG_EXPERIMENTAL=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_FS_USERFS=y +CONFIG_FSUTILS_PASSWD_READONLY=y +CONFIG_FSUTILS_PASSWD=y +CONFIG_IDLETHREAD_STACKSIZE=4096 +CONFIG_LIBC_EXECFUNCS=y +CONFIG_MAX_TASKS=64 +CONFIG_NET_LOCAL=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_UDP=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_NFILE_DESCRIPTORS=32 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_ARCHROMFS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FATDEVNO=2 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_ROMFSDEVNO=1 +CONFIG_NSH_ROMFSETC=y +CONFIG_PATH_INITIAL="/bin" +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_DEFAULT=8192 +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_ONEXIT=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SIM_WALLTIME=y +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2008 +CONFIG_TIME_EXTENDED=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_USERMAIN_STACKSIZE=8192 diff --git a/configs/spark/README.txt b/configs/spark/README.txt index 3b8b0ebf6f74b97f47f9ccfd263c6003c9e3de5a..2975270412969d7690f69933b1a7531bb882e444 100644 --- a/configs/spark/README.txt +++ b/configs/spark/README.txt @@ -25,12 +25,6 @@ This README discusses issues unique to NuttX configurations for the Spark Core b Contents ======== - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - Hardware - Core Pin out - LEDs @@ -40,246 +34,6 @@ Contents - Spark -specific Configuration Options - Configurations -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. - -GNU Toolchain Options -===================== - - Toolchain Configurations - ------------------------ - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The Atollic Toolchain, - 3. The devkitARM GNU toolchain, - 4. Raisonance GNU toolchain, or - 5. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the CodeSourcery toolchain for Linux. - To use the Atollic, devkitARM, Raisonance GNU, or NuttX buildroot toolchain, - you simply need to add one of the following configuration options to your - .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=n : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : The Atollic toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=n : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE=y : Raisonance RIDE7 under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=n : NuttX buildroot under Linux or Cygwin (default) - - NOTE: the CodeSourcery (for Windows), Atollic, devkitARM, and Raisonance toolchains are - Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - The CodeSourcery Toolchain (2009q1) - ----------------------------------- - The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - The Atollic "Pro" and "Lite" Toolchain - -------------------------------------- - One problem that I had with the Atollic toolchains is that the provide a gcc.exe - and g++.exe in the same bin/ file as their ARM binaries. If the Atollic bin/ path - appears in your PATH variable before /usr/bin, then you will get the wrong gcc - when you try to build host executables. This will cause to strange, uninterpretable - errors build some host binaries in tools/ when you first make. - - Also, the Atollic toolchains are the only toolchains that have built-in support for - the FPU in these configurations. If you plan to use the Cortex-M4 FPU, you will - need to use the Atollic toolchain for now. See the FPU section below for more - information. - - The Atollic "Lite" Toolchain - ---------------------------- - The free, "Lite" version of the Atollic toolchain does not support C++ nor - does it support ar, nm, objdump, or objdcopy. If you use the Atollic "Lite" - toolchain, you will have to set: - - CONFIG_HAVE_CXX=n - - In order to compile successfully. Otherwise, you will get errors like: - - "C++ Compiler only available in TrueSTUDIO Professional" - - The make may then fail in some of the post link processing because of some of - the other missing tools. The Make.defs file replaces the ar and nm with - the default system x86 tool versions and these seem to work okay. Disable all - of the following to avoid using objcopy: - - CONFIG_RRLOAD_BINARY=n - CONFIG_INTELHEX_BINARY=n - CONFIG_MOTOROLA_SREC=n - CONFIG_RAW_BINARY=n - - devkitARM - --------- - The devkitARM toolchain includes a version of MSYS make. Make sure that the - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Using Sourcery CodeBench from http://www.mentor.com/embedded-software/sourcery-tools/sourcery-codebench/overview - Download and install the latest version (as of this writting it was - sourceryg++-2013.05-64-arm-none-eabi) - - Import the project from git. - File->import->Git-URI, then import a Exiting code as a Makefile progject - from the working directory the git clone was done to. - - Select the Sourcery CodeBench for ARM EABI. N.B. You must do one command line - build, before the make will work in CodeBench. - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/stm32, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by RIDE. - -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh stm32_tiny/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - DFU and JTAG ============ diff --git a/configs/spark/composite/defconfig b/configs/spark/composite/defconfig index 7f0ed8f05caa47035b6d33333ed68910fe7f221f..af4f8711003e91319d754c1a80d14cedf4c18b05 100644 --- a/configs/spark/composite/defconfig +++ b/configs/spark/composite/defconfig @@ -1,15 +1,12 @@ # CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLE_ADDROUTE is not set # CONFIG_NSH_DISABLE_CMP is not set # CONFIG_NSH_DISABLE_DD is not set -# CONFIG_NSH_DISABLE_DELROUTE is not set # CONFIG_NSH_DISABLE_EXEC is not set # CONFIG_NSH_DISABLE_EXIT is not set # CONFIG_NSH_DISABLE_GET is not set # CONFIG_NSH_DISABLE_HEXDUMP is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKFATFS is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -54,6 +51,7 @@ CONFIG_EXAMPLES_CC3000BASIC=y CONFIG_EXAMPLES_NSH=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=12 CONFIG_FS_FATTIME=y CONFIG_FS_NAMED_SEMAPHORES=y CONFIG_IDLETHREAD_STACKSIZE=280 diff --git a/configs/spark/include/board.h b/configs/spark/include/board.h index b44dce3aab73962a21269a9f2e70ff3a577d5395..f88f3923fe1844720882fb5ecf389da4e90ef03a 100644 --- a/configs/spark/include/board.h +++ b/configs/spark/include/board.h @@ -212,42 +212,4 @@ #define BUTTON_USER_BIT (1 << BUTTON_USER) #define BUTTON_ACTIVE_LOW (BUTTON_USER_BIT) - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_SPARK_INCLUDE_BOARD_H */ diff --git a/configs/spark/nsh/defconfig b/configs/spark/nsh/defconfig index 9b003c2629b9a794d29ac03325211cb974f07d21..40363aae9f910caa8e26e8566fcf04650274d5cc 100644 --- a/configs/spark/nsh/defconfig +++ b/configs/spark/nsh/defconfig @@ -1,15 +1,12 @@ # CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLE_ADDROUTE is not set # CONFIG_NSH_DISABLE_CMP is not set # CONFIG_NSH_DISABLE_DD is not set -# CONFIG_NSH_DISABLE_DELROUTE is not set # CONFIG_NSH_DISABLE_EXEC is not set # CONFIG_NSH_DISABLE_EXIT is not set # CONFIG_NSH_DISABLE_GET is not set # CONFIG_NSH_DISABLE_HEXDUMP is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKFATFS is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -45,6 +42,7 @@ CONFIG_EXAMPLES_CC3000BASIC=y CONFIG_EXAMPLES_NSH=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=12 CONFIG_FS_FATTIME=y CONFIG_FS_NAMED_SEMAPHORES=y CONFIG_IDLETHREAD_STACKSIZE=300 diff --git a/configs/spark/usbmsc/defconfig b/configs/spark/usbmsc/defconfig index 4ba067edf01c81735684be513d7dd245f92f6da3..37cd3ef6cc5916471842da9b20e93697ac995281 100644 --- a/configs/spark/usbmsc/defconfig +++ b/configs/spark/usbmsc/defconfig @@ -1,15 +1,12 @@ # CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLE_ADDROUTE is not set # CONFIG_NSH_DISABLE_CMP is not set # CONFIG_NSH_DISABLE_DD is not set -# CONFIG_NSH_DISABLE_DELROUTE is not set # CONFIG_NSH_DISABLE_EXEC is not set # CONFIG_NSH_DISABLE_EXIT is not set # CONFIG_NSH_DISABLE_GET is not set # CONFIG_NSH_DISABLE_HEXDUMP is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKFATFS is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -40,6 +37,7 @@ CONFIG_EXAMPLES_CC3000BASIC=y CONFIG_EXAMPLES_NSH=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=12 CONFIG_FS_FATTIME=y CONFIG_FS_NAMED_SEMAPHORES=y CONFIG_IDLETHREAD_STACKSIZE=280 diff --git a/configs/spark/usbserial/defconfig b/configs/spark/usbserial/defconfig index 5019768367c8d5eedf566c1f189e7bc301c74203..1699ef387d73d23088017037a394cea83f1626d6 100644 --- a/configs/spark/usbserial/defconfig +++ b/configs/spark/usbserial/defconfig @@ -34,6 +34,7 @@ CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=y CONFIG_EXAMPLES_USBSERIAL=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=12 CONFIG_FS_FATTIME=y CONFIG_FS_NAMED_SEMAPHORES=y CONFIG_INTELHEX_BINARY=y diff --git a/configs/stm3210e-eval/README.txt b/configs/stm3210e-eval/README.txt index fb1462c5fab985ebb90d8d1d0975939622ee1f72..97ae979d1cf85c35d6422a70e407ce6d4fb0cdc0 100644 --- a/configs/stm3210e-eval/README.txt +++ b/configs/stm3210e-eval/README.txt @@ -7,12 +7,6 @@ STMicro STM3210E-EVAL development board. Contents ======== - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - DFU and JTAG - OpenOCD - LEDs @@ -22,194 +16,6 @@ Contents - STM3210E-EVAL-specific Configuration Options - Configurations -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -===================== - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The devkitARM GNU toolchain, - 3. Raisonance GNU toolchain, or - 4. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the NuttX buildroot toolchain. However, - the make system is setup to default to use the devkitARM toolchain. To use - the CodeSourcery, devkitARM or Raisonance GNU toolchain, you simply need to - add one of the following configuration options to your .config (or defconfig) - file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE=y : Raisonance RIDE7 under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - NOTE: the CodeSourcery (for Windows), devkitARM, and Raisonance toolchains are - Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/stm32, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/stm32/stm32_vectors.S. You may have to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by an IDE. - -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh stm3210e-eval/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - DFU and JTAG ============ diff --git a/configs/stm3210e-eval/composite/defconfig b/configs/stm3210e-eval/composite/defconfig index c39ea0632d7c0863f9167e01289d1603ed10b443..d881bc64f7fca32756752d516fe25936c7b66bd4 100644 --- a/configs/stm3210e-eval/composite/defconfig +++ b/configs/stm3210e-eval/composite/defconfig @@ -1,4 +1,4 @@ -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_BOARD="stm3210e-eval" diff --git a/configs/stm3210e-eval/include/board.h b/configs/stm3210e-eval/include/board.h index a0b2f41c97f13f103fc1b9d71fae03f5c7c1c01e..f76389222b7973fe769bd85c2cca7fbdcabd467e 100644 --- a/configs/stm3210e-eval/include/board.h +++ b/configs/stm3210e-eval/include/board.h @@ -239,17 +239,6 @@ extern "C" /************************************************************************************ * Public Function Prototypes ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); /************************************************************************************ * Name: stm3210e_lcdclear diff --git a/configs/stm3210e-eval/nsh/defconfig b/configs/stm3210e-eval/nsh/defconfig index 8d7ec1e665dbf1df15b9c9c4e09f92b614891e60..06e1408e1a7dc4bee4f66883ef658e1551b44cd2 100644 --- a/configs/stm3210e-eval/nsh/defconfig +++ b/configs/stm3210e-eval/nsh/defconfig @@ -1,4 +1,4 @@ -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set diff --git a/configs/stm3210e-eval/nsh2/defconfig b/configs/stm3210e-eval/nsh2/defconfig index 70c1fd201ed4a124021ffddd157e9df19fc8fdca..81ba91ba1dc991d23bdf65595b650c21683efd6e 100644 --- a/configs/stm3210e-eval/nsh2/defconfig +++ b/configs/stm3210e-eval/nsh2/defconfig @@ -2,13 +2,14 @@ # CONFIG_EXAMPLES_NX_DEFAULT_FONT is not set # CONFIG_EXAMPLES_NXHELLO_DEFAULT_COLORS is not set # CONFIG_EXAMPLES_NXHELLO_DEFAULT_FONT is not set -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set # CONFIG_NX_PACKEDMSFIRST is not set # CONFIG_NX_WRITEONLY is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_BOARD="stm3210e-eval" diff --git a/configs/stm3210e-eval/nx/defconfig b/configs/stm3210e-eval/nx/defconfig index 51f8aa9359dfff729b62780ab7ad087871781184..ae1a4aeff673ad508b2c8a76d4fcd28cc3566a55 100644 --- a/configs/stm3210e-eval/nx/defconfig +++ b/configs/stm3210e-eval/nx/defconfig @@ -3,6 +3,7 @@ # CONFIG_NX_DISABLE_16BPP is not set # CONFIG_NX_PACKEDMSFIRST is not set # CONFIG_NX_WRITEONLY is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_BOARD="stm3210e-eval" diff --git a/configs/stm3210e-eval/nxterm/defconfig b/configs/stm3210e-eval/nxterm/defconfig index 356cb1222ba04cca6db204bff1262eb8bab019b1..a245f116757c5f2bd2f38b80aa41647243e104ef 100644 --- a/configs/stm3210e-eval/nxterm/defconfig +++ b/configs/stm3210e-eval/nxterm/defconfig @@ -3,6 +3,7 @@ # CONFIG_NX_DISABLE_16BPP is not set # CONFIG_NX_PACKEDMSFIRST is not set # CONFIG_NX_WRITEONLY is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_BOARD="stm3210e-eval" diff --git a/configs/stm3210e-eval/pm/defconfig b/configs/stm3210e-eval/pm/defconfig index 3ba2c78d8a596ce667886a299874d73064553a7a..922c583817ebbc89e0da852cdbf298c8c9ecbf3a 100644 --- a/configs/stm3210e-eval/pm/defconfig +++ b/configs/stm3210e-eval/pm/defconfig @@ -7,6 +7,7 @@ # CONFIG_NX_DISABLE_16BPP is not set # CONFIG_NX_PACKEDMSFIRST is not set # CONFIG_NX_WRITEONLY is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_BOARD="stm3210e-eval" diff --git a/configs/stm3210e-eval/src/stm32_djoystick.c b/configs/stm3210e-eval/src/stm32_djoystick.c index 40e8e3bf2656ef453997864eb9d6399f21f21625..902ee9dba5a86a9d85cdc6c83c93a92c33b09458 100644 --- a/configs/stm3210e-eval/src/stm32_djoystick.c +++ b/configs/stm3210e-eval/src/stm32_djoystick.c @@ -78,7 +78,7 @@ static void djoy_enable(FAR const struct djoy_lowerhalf_s *lower, djoy_interrupt_t handler, FAR void *arg); static void djoy_disable(void); -static int djoy_interrupt(int irq, FAR void *context); +static int djoy_interrupt(int irq, FAR void *context, FAR void *arg); /**************************************************************************** * Private Data @@ -258,7 +258,7 @@ static void djoy_disable(void) * ****************************************************************************/ -static int djoy_interrupt(int irq, FAR void *context) +static int djoy_interrupt(int irq, FAR void *context, FAR void *arg) { DEBUGASSERT(g_djoyhandler); if (g_djoyhandler) diff --git a/configs/stm3210e-eval/usbmsc/defconfig b/configs/stm3210e-eval/usbmsc/defconfig index 59c0641fa312f045d514740de56cacd5281d3b33..bd3c4339a11a8508a2446d11be10a937ab6015a2 100644 --- a/configs/stm3210e-eval/usbmsc/defconfig +++ b/configs/stm3210e-eval/usbmsc/defconfig @@ -1,4 +1,4 @@ -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_BOARD="stm3210e-eval" diff --git a/configs/stm3220g-eval/README.txt b/configs/stm3220g-eval/README.txt index 617a7b54f1a470b0dd7568b286e1ac635d9c6efd..d1f5d9ae0d5a49fda52f7e4eadd255da6e318161 100644 --- a/configs/stm3220g-eval/README.txt +++ b/configs/stm3220g-eval/README.txt @@ -7,15 +7,8 @@ STMicro STM3220G-EVAL development board. Contents ======== - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - - STM3220G-EVAL-specific Configuration Options - - LEDs - Ethernet + - LEDs - PWM - CAN - FSMC SRAM @@ -23,344 +16,6 @@ Contents - STM3220G-EVAL-specific Configuration Options - Configurations -Development Environment -======================= - - Linux, OS X or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment because the Raisonance R-Link emulatator and some RIDE7 development tools - were used and those tools works only under Windows. - -GNU Toolchain Options -===================== - - Toolchain Configurations - ------------------------ - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The Atollic Toolchain, - 3. The devkitARM GNU toolchain, - 4. Raisonance GNU toolchain, - 5. The NuttX buildroot Toolchain (see below), or - 6. Any generic arm-none-eabi GNU toolchain. - - Most testing has been conducted using the CodeSourcery toolchain for Windows and - that is the default toolchain in most configurations. To use the Atollic - devkitARM, Raisonance GNU, or NuttX buildroot toolchain, you simply need to - add one of the following configuration options to your .config (or defconfig) - file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : The Atollic toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE=y : Raisonance RIDE7 under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL : Generic arm-none-eabi toolchain - - The toolchain may also be set using the kconfig-mconf utility (make menuconfig) - or by passing CONFIG_ARMV7M_TOOLCHAIN= to make, where is one - of CODESOURCERYW, CODESOURCERYL, ATOLLOC, DEVKITARM, RAISONANCE, BUILDROOT or - GNU_EABI as described above. - - NOTE: the CodeSourcery (for Windows), Atollic, devkitARM, and Raisonance toolchains are - Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - The CodeSourcery Toolchain (2009q1) - ----------------------------------- - The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - The Atollic "Pro" and "Lite" Toolchain - -------------------------------------- - One problem that I had with the Atollic toolchains is that the provide a gcc.exe - and g++.exe in the same bin/ file as their ARM binaries. If the Atollic bin/ path - appears in your PATH variable before /usr/bin, then you will get the wrong gcc - when you try to build host executables. This will cause to strange, uninterpretable - errors build some host binaries in tools/ when you first make. - - The Atollic "Lite" Toolchain - ---------------------------- - The free, "Lite" version of the Atollic toolchain does not support C++ nor - does it support ar, nm, objdump, or objdcopy. If you use the Atollic "Lite" - toolchain, you will have to set: - - CONFIG_HAVE_CXX=n - - In order to compile successfully. Otherwise, you will get errors like: - - "C++ Compiler only available in TrueSTUDIO Professional" - - The make may then fail in some of the post link processing because of some of - the other missing tools. The Make.defs file replaces the ar and nm with - the default system x86 tool versions and these seem to work okay. Disable all - of the following to avoid using objcopy: - - CONFIG_RRLOAD_BINARY=n - CONFIG_INTELHEX_BINARY=n - CONFIG_MOTOROLA_SREC=n - CONFIG_RAW_BINARY=n - - devkitARM - --------- - The devkitARM toolchain includes a version of MSYS make. Make sure that the - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - - Generic arm-none-eabi GNU Toolchain - ----------------------------------- - There are a number of toolchain projects providing support for the Cortex-M - class processors, including: - - GCC ARM Embedded - https://developer.arm.com/open-source/gnu-toolchain/gnu-rm - - Thumb2 Newlib Toolchain - https://github.com/EliasOenal/TNT - - Summon ARM Toolchain - https://github.com/esden/summon-arm-toolchain - - Yagarto - http://www.yagarto.de - - Others exist for various Linux distributions, MacPorts, etc. Any version - based on GCC 4.6.3 or later should work. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/stm32, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by RIDE. - - Export nuttx to IAR or uVision workspace - ---------------------------------------- - The script nuttx/tools/ide_exporter.py will help to create nuttx project in - these IDEs. Here are few simple the steps to export the IDE workspaces: - - 1) Start the NuttX build from the Cygwin command line before trying to - create your project by running: - - make V=1 |& tee build_log - - This is necessary to certain auto-generated files and directories that - will be needed. This will provide the build log to construct the IDE - project also. - - 2) Export the IDE project base on that make log. The script usage: - - usage: ide_exporter.py [-h] [-v] [-o OUT_DIR] [-d] build_log {iar,uvision_armcc,uvision_gcc} template_dir - - positional arguments: - build_log Log file from make V=1 - {iar,uvision_armcc,uvision_gcc} - The target IDE: iar, uvision_gcc, (uvision_armcc is experimental) - template_dir Directory that contains IDEs template projects - - optional arguments: - -h, --help show this help message and exit - -v, --version show program's version number and exit - -o OUT_DIR, --output OUT_DIR - Output directory - -d, --dump Dump project structure tree - - Example: - cd nuttx - make V=1 |& tee build_log - - ./tools/ide_exporter.py makelog_f2nsh_c iar ./configs/stm3220g-eval/ide/template/iar -o ./configs/stm3220g-eval/ide/nsh/iar - - or - - ./tools/ide_exporter.py makelog_f2nsh_c uvision_gcc ./configs/stm3220g-eval/ide/template/uvision_gcc/ -o ./configs/stm3220g-eval/ide/nsh/uvision - - 3) Limitations: - - IAR supports C only. Iar C++ does not compatible with g++ so disable - C++ if you want to use IAR. - - uvision_armcc : nuttx asm (inline and .asm) can't be compiled with - armcc so do not use this option. - - uvision_gcc : uvision project that uses gcc. Need to specify path to - gnu toolchain. - In uVison menu, select: - - Project/Manage/Project Items.../FolderExtension/Use GCC compiler/ PreFix, Folder - - 4) Template projects' constrains: - - mcu, core, link script shall be configured in template project - - Templates' name are fixed: - - template_nuttx.eww : IAR nuttx workspace template - - template_nuttx_lib.ewp : IAR nuttx library project template - - template_nuttx_main.ewp : IAR nuttx main project template - - template_nuttx.uvmpw : uVision workspace - - template_nuttx_lib.uvproj : uVision library project - - template_nuttx_main.uvproj : uVision main project - - iar: - - Library option shall be set to 'None' so that IAR could use nuttx libc - - __ASSEMBLY__ symbol shall be defined in assembler - - uVision_gcc: - - There should be one fake .S file in projects that has been defined __ASSEMBLY__ in assembler. - - In Option/CC tab : disable warning - - In Option/CC tab : select Compile thump code (or Misc control = -mthumb) - - template_nuttx_lib.uvproj shall add 'Post build action' to copy .a file to .\lib - - template_nuttx_main.uvproj Linker: - - Select 'Do not use Standard System Startup Files' and 'Do not use Standard System Libraries' - - Do not select 'Use Math libraries' - - Misc control = --entry=__start - - 5) How to create template for other configurations: - 1) uVision with gcc toolchain: - - Copy 3 uVision project files - - Select the MCU for main and lib project - - Correct the path to ld script if needed - 2) iar: - - Check if the arch supportes IAR (only armv7-m is support IAR now) - - Select the MCU for main and lib project - - Add new ld script file for IAR - -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh stm3220g-eval/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - Ethernet ======== diff --git a/configs/stm3220g-eval/ide/nsh/iar/README.txt b/configs/stm3220g-eval/ide/nsh/iar/README.txt deleted file mode 100644 index 767946884282662e01549351630bafeafa9c8f00..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/iar/README.txt +++ /dev/null @@ -1,7 +0,0 @@ -README -====== - -These projects are generated by nuttx/tools/ide_exporter.py with -configuration stm3220g-eval/nsh (deselect Library Routes/Have C++ compiler) -You need you need to rebuild this configuration first time to make sure some -auto-generated files are generated correctly before using the IDE diff --git a/configs/stm3220g-eval/ide/nsh/iar/libapps.ewp b/configs/stm3220g-eval/ide/nsh/iar/libapps.ewp deleted file mode 100644 index 209e3755e72145a5f0cf4e3bc811445a3d4ab246..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/iar/libapps.ewp +++ /dev/null @@ -1,2107 +0,0 @@ - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 24 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - Coder - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 24 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - Coder - 0 - - - - - apps - - $PROJ_DIR$/../../../../../../apps/builtin/builtin_forindex.c - - - $PROJ_DIR$/../../../../../../apps/builtin/builtin_list.c - - - $PROJ_DIR$/../../../../../../apps/builtin/exec_builtin.c - - - $PROJ_DIR$/../../../../../../apps/examples/nsh/nsh_main.c - - - $PROJ_DIR$/../../../../../../apps/netutils/tftpc/tftpc_get.c - - - $PROJ_DIR$/../../../../../../apps/netutils/tftpc/tftpc_put.c - - - $PROJ_DIR$/../../../../../../apps/netutils/tftpc/tftpc_packets.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_ipv4addrconv.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_ethaddrconv.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_parsehttpurl.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_setifstatus.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_getifstatus.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_setipv4addr.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_getipv4addr.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_setdripv4addr.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_setipv4netmask.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_getdripv4addr.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_getipv4netmask.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_getarp.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_setarp.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_delarp.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_setipv4dnsaddr.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_server.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_listenon.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_setmacaddr.c - - - $PROJ_DIR$/../../../../../../apps/netutils/netlib/netlib_getmacaddr.c - - - $PROJ_DIR$/../../../../../../apps/netutils/webclient/webclient.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_init.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_parse.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_console.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_script.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_command.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_fscmds.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_ddcmd.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_proccmds.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_mmcmds.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_timcmds.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_envcmds.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_syscmds.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_dbgcmds.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_session.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_fsutils.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_builtin.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_netinit.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_netcmds.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_mntcmds.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_consolemain.c - - - $PROJ_DIR$/../../../../../../apps/nshlib/nsh_test.c - - - $PROJ_DIR$/../../../../../../apps/system/readline/readline_common.c - - - $PROJ_DIR$/../../../../../../apps/system/readline/readline.c - - - diff --git a/configs/stm3220g-eval/ide/nsh/iar/libarch.ewp b/configs/stm3220g-eval/ide/nsh/iar/libarch.ewp deleted file mode 100644 index f043226ad3b894f27ec7dd39bf64b4baa9f985f1..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/iar/libarch.ewp +++ /dev/null @@ -1,2135 +0,0 @@ - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 24 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - Coder - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 24 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - Coder - 0 - - - - - src - - $PROJ_DIR$/../../../../../arch/arm/src/armv7-m/iar/up_saveusercontext.S - - - $PROJ_DIR$/../../../../../arch/arm/src/armv7-m/iar/up_fullcontextrestore.S - - - $PROJ_DIR$/../../../../../arch/arm/src/armv7-m/iar/up_switchcontext.S - - - $PROJ_DIR$/../../../../../arch/arm/src/armv7-m/iar/up_testset.S - - - $PROJ_DIR$/../../../../../arch/arm/src/armv7-m/iar/vfork.S - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_allocateheap.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_start.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_rcc.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_lse.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_lsi.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_gpio.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_exti_gpio.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_flash.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_irq.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_dma.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_lowputc.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_serial.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_spi.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_sdio.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_tim.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_waste.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_ccm.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_uid.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_capture.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_timerisr.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_i2c.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_idle.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_pmstop.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_pmstandby.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_pmsleep.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_pminitialize.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_eth.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_pwr.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_exti_pwr.c - - - $PROJ_DIR$/../../../../../arch/arm/src/chip/stm32_rtc.c - - - $PROJ_DIR$/../../../../../arch/arm/src/armv7-m/up_assert.c - - - $PROJ_DIR$/../../../../../arch/arm/src/armv7-m/up_blocktask.c - - - $PROJ_DIR$/../../../../../arch/arm/src/armv7-m/up_copyfullstate.c - - - $PROJ_DIR$/../../../../../arch/arm/src/common/up_createstack.c - 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- - $PROJ_DIR$/../../../../../sched/signal/sig_queue.c - - - $PROJ_DIR$/../../../../../sched/signal/sig_waitinfo.c - - - $PROJ_DIR$/../../../../../sched/signal/sig_timedwait.c - - - $PROJ_DIR$/../../../../../sched/signal/sig_findaction.c - - - $PROJ_DIR$/../../../../../sched/signal/sig_allocatependingsigaction.c - - - $PROJ_DIR$/../../../../../sched/signal/sig_releasependingsigaction.c - - - $PROJ_DIR$/../../../../../sched/signal/sig_unmaskpendingsignal.c - - - $PROJ_DIR$/../../../../../sched/signal/sig_removependingsignal.c - - - $PROJ_DIR$/../../../../../sched/signal/sig_releasependingsignal.c - - - $PROJ_DIR$/../../../../../sched/signal/sig_lowest.c - - - $PROJ_DIR$/../../../../../sched/signal/sig_mqnotempty.c - - - $PROJ_DIR$/../../../../../sched/signal/sig_cleanup.c - - - $PROJ_DIR$/../../../../../sched/signal/sig_dispatch.c - - - $PROJ_DIR$/../../../../../sched/signal/sig_deliver.c - - - $PROJ_DIR$/../../../../../sched/signal/sig_pause.c - - - $PROJ_DIR$/../../../../../sched/signal/sig_nanosleep.c - - - $PROJ_DIR$/../../../../../sched/task/task_create.c - - - $PROJ_DIR$/../../../../../sched/task/task_init.c - - - $PROJ_DIR$/../../../../../sched/task/task_setup.c - - - $PROJ_DIR$/../../../../../sched/task/task_activate.c - - - $PROJ_DIR$/../../../../../sched/task/task_start.c - - - $PROJ_DIR$/../../../../../sched/task/task_delete.c - - - $PROJ_DIR$/../../../../../sched/task/task_exit.c - - - $PROJ_DIR$/../../../../../sched/task/task_exithook.c - - - $PROJ_DIR$/../../../../../sched/task/task_recover.c - - - $PROJ_DIR$/../../../../../sched/task/task_restart.c - - - $PROJ_DIR$/../../../../../sched/task/task_spawnparms.c - - - $PROJ_DIR$/../../../../../sched/task/task_terminate.c - - - $PROJ_DIR$/../../../../../sched/task/task_getgroup.c - - - $PROJ_DIR$/../../../../../sched/task/task_prctl.c - - - $PROJ_DIR$/../../../../../sched/task/task_getpid.c - - - $PROJ_DIR$/../../../../../sched/task/exit.c - - - $PROJ_DIR$/../../../../../sched/task/task_vfork.c - - - $PROJ_DIR$/../../../../../sched/task/task_spawn.c - - - $PROJ_DIR$/../../../../../sched/timer/timer_initialize.c - - - $PROJ_DIR$/../../../../../sched/timer/timer_create.c - - - $PROJ_DIR$/../../../../../sched/timer/timer_delete.c - - - $PROJ_DIR$/../../../../../sched/timer/timer_getoverrun.c - - - $PROJ_DIR$/../../../../../sched/timer/timer_gettime.c - - - $PROJ_DIR$/../../../../../sched/timer/timer_settime.c - - - $PROJ_DIR$/../../../../../sched/timer/timer_release.c - - - $PROJ_DIR$/../../../../../sched/wdog/wd_initialize.c - - - $PROJ_DIR$/../../../../../sched/wdog/wd_create.c - - - $PROJ_DIR$/../../../../../sched/wdog/wd_start.c - - - $PROJ_DIR$/../../../../../sched/wdog/wd_cancel.c - - - $PROJ_DIR$/../../../../../sched/wdog/wd_delete.c - - - $PROJ_DIR$/../../../../../sched/wdog/wd_gettime.c - - - $PROJ_DIR$/../../../../../sched/wdog/wd_recover.c - - - diff --git a/configs/stm3220g-eval/ide/nsh/iar/nuttx.eww b/configs/stm3220g-eval/ide/nsh/iar/nuttx.eww deleted file mode 100644 index 670709391583b146fd9aa472eb1c63c90035062a..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/iar/nuttx.eww +++ /dev/null @@ -1,37 +0,0 @@ - - - - - $WS_DIR$/libboard.ewp - - - $WS_DIR$/libmm.ewp - - - $WS_DIR$/libfs.ewp - - - $WS_DIR$/libdrivers.ewp - - - $WS_DIR$/libarch.ewp - - - $WS_DIR$/libbinfmt.ewp - - - $WS_DIR$/libsched.ewp - - - $WS_DIR$/libapps.ewp - - - $WS_DIR$/libc.ewp - - - $WS_DIR$/libnet.ewp - - - $WS_DIR$/nuttx_main.ewp - - diff --git a/configs/stm3220g-eval/ide/nsh/iar/nuttx_main.ewp b/configs/stm3220g-eval/ide/nsh/iar/nuttx_main.ewp deleted file mode 100644 index 9e6270d467297d82e7e3550b188e1cc2c29ed7fd..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/iar/nuttx_main.ewp +++ /dev/null @@ -1,1987 +0,0 @@ - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 24 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - Coder - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 24 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - Coder - 0 - - - - - gnu - - $PROJ_DIR$/../../../../../arch/arm/src/chip/iar/stm32_vectors.S - - - - libs - - $PROJ_DIR$/libboard/Obj/libboard.a - - - $PROJ_DIR$/libmm/Obj/libmm.a - - - $PROJ_DIR$/libfs/Obj/libfs.a - - - $PROJ_DIR$/libdrivers/Obj/libdrivers.a - - - $PROJ_DIR$/libarch/Obj/libarch.a - - - $PROJ_DIR$/libbinfmt/Obj/libbinfmt.a - - - $PROJ_DIR$/libsched/Obj/libsched.a - - - $PROJ_DIR$/libapps/Obj/libapps.a - - - $PROJ_DIR$/libc/Obj/libc.a - - - $PROJ_DIR$/libnet/Obj/libnet.a - - - diff --git a/configs/stm3220g-eval/ide/nsh/iar/wfi.mac b/configs/stm3220g-eval/ide/nsh/iar/wfi.mac deleted file mode 100644 index f063baac72436567c7c6fac0a4ea97a7e553166a..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/iar/wfi.mac +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Debug support for low-power modes - * To enter low-power mode, the instruction WFI or WFE must be executed. - * The MCU implements several low-power modes which can either deactivate the CPU clock - * or reduce the power of the CPU. - * The core does not allow FCLK or HCLK to be turned off during a debug session. As these - * are required for the debugger connection, during a debug, they must remain active. The - * MCU integrates special means to allow the user to debug software in low-power modes. - * For this, the debugger host must first set some debug configuration registers to change the - * low-power mode behavior: - * In Sleep mode, DBG_SLEEP bit of DBGMCU_CR register must be previously set by - * the debugger. This will feed HCLK with the same clock that is provided to FCLK - * (system clock previously configured by the software). - * In Stop mode, the bit DBG_STOP must be previously set by the debugger. This will - * enable the internal RC oscillator clock to feed FCLK and HCLK in STOP mode. - */ - -execUserExecutionStarted() -{ - if (!__driverType("sim")) - { - __writeMemory32(__readMemory32(0xE0042004, "Memory") | 0x3, 0xE0042004, "Memory"); // Set DBG_SLEEP and DBG_STOP in DBGMCU_CR - } -} \ No newline at end of file diff --git a/configs/stm3220g-eval/ide/nsh/uvision/README.txt b/configs/stm3220g-eval/ide/nsh/uvision/README.txt deleted file mode 100644 index 767946884282662e01549351630bafeafa9c8f00..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/uvision/README.txt +++ /dev/null @@ -1,7 +0,0 @@ -README -====== - -These projects are generated by nuttx/tools/ide_exporter.py with -configuration stm3220g-eval/nsh (deselect Library Routes/Have C++ compiler) -You need you need to rebuild this configuration first time to make sure some -auto-generated files are generated correctly before using the IDE diff --git a/configs/stm3220g-eval/ide/nsh/uvision/libapps.uvproj b/configs/stm3220g-eval/ide/nsh/uvision/libapps.uvproj deleted file mode 100644 index 08baad007a7931e163c21e9ee1979ad2743f7fc3..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/uvision/libapps.uvproj +++ /dev/null @@ -1,572 +0,0 @@ - - - - 1.1 - -
              ### uVision Project, (C) Keil Software
              - - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M3 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE - - - - 4349 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libapps\Obj\ - apps - 0 - 1 - 1 - 1 - 0 - .\libapps\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M3" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../../apps/nshlib;../../../../../../apps/system/readline;../../../../../../apps/netutils/netlib;../../../../../include;../../../../../../apps/builtin;../../../../../../apps/examples/nsh;../../../../../../apps/netutils/webclient;../../../../../../apps/netutils/tftpc - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../../apps/nshlib;../../../../../../apps/system/readline;../../../../../../apps/netutils/netlib;../../../../../include;../../../../../../apps/builtin;../../../../../../apps/examples/nsh;../../../../../../apps/netutils/webclient;../../../../../../apps/netutils/tftpc - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - apps - - - builtin_forindex.c - 1 - ../../../../../../apps/builtin/builtin_forindex.c - - - builtin_list.c - 1 - ../../../../../../apps/builtin/builtin_list.c - - - exec_builtin.c - 1 - ../../../../../../apps/builtin/exec_builtin.c - - - nsh_main.c - 1 - ../../../../../../apps/examples/nsh/nsh_main.c - - - tftpc_get.c - 1 - ../../../../../../apps/netutils/tftpc/tftpc_get.c - - - tftpc_put.c - 1 - ../../../../../../apps/netutils/tftpc/tftpc_put.c - - - tftpc_packets.c - 1 - ../../../../../../apps/netutils/tftpc/tftpc_packets.c - - - netlib_ipv4addrconv.c - 1 - ../../../../../../apps/netutils/netlib/netlib_ipv4addrconv.c - - - netlib_ethaddrconv.c - 1 - ../../../../../../apps/netutils/netlib/netlib_ethaddrconv.c - - - netlib_parsehttpurl.c - 1 - ../../../../../../apps/netutils/netlib/netlib_parsehttpurl.c - - - netlib_setifstatus.c - 1 - ../../../../../../apps/netutils/netlib/netlib_setifstatus.c - - - netlib_getifstatus.c - 1 - ../../../../../../apps/netutils/netlib/netlib_getifstatus.c - - - netlib_setipv4addr.c - 1 - ../../../../../../apps/netutils/netlib/netlib_setipv4addr.c - - - netlib_getipv4addr.c - 1 - ../../../../../../apps/netutils/netlib/netlib_getipv4addr.c - - - netlib_setdripv4addr.c - 1 - ../../../../../../apps/netutils/netlib/netlib_setdripv4addr.c - - - netlib_setipv4netmask.c - 1 - ../../../../../../apps/netutils/netlib/netlib_setipv4netmask.c - - - netlib_getdripv4addr.c - 1 - ../../../../../../apps/netutils/netlib/netlib_getdripv4addr.c - - - netlib_getipv4netmask.c - 1 - ../../../../../../apps/netutils/netlib/netlib_getipv4netmask.c - - - netlib_getarp.c - 1 - ../../../../../../apps/netutils/netlib/netlib_getarp.c - - - netlib_setarp.c - 1 - ../../../../../../apps/netutils/netlib/netlib_setarp.c - - - netlib_delarp.c - 1 - ../../../../../../apps/netutils/netlib/netlib_delarp.c - - - netlib_setipv4dnsaddr.c - 1 - ../../../../../../apps/netutils/netlib/netlib_setipv4dnsaddr.c - - - netlib_server.c - 1 - ../../../../../../apps/netutils/netlib/netlib_server.c - - - netlib_listenon.c - 1 - ../../../../../../apps/netutils/netlib/netlib_listenon.c - - - netlib_setmacaddr.c - 1 - ../../../../../../apps/netutils/netlib/netlib_setmacaddr.c - - - netlib_getmacaddr.c - 1 - ../../../../../../apps/netutils/netlib/netlib_getmacaddr.c - - - webclient.c - 1 - ../../../../../../apps/netutils/webclient/webclient.c - - - nsh_init.c - 1 - ../../../../../../apps/nshlib/nsh_init.c - - - nsh_parse.c - 1 - ../../../../../../apps/nshlib/nsh_parse.c - - - nsh_console.c - 1 - ../../../../../../apps/nshlib/nsh_console.c - - - nsh_script.c - 1 - ../../../../../../apps/nshlib/nsh_script.c - - - nsh_command.c - 1 - ../../../../../../apps/nshlib/nsh_command.c - - - nsh_fscmds.c - 1 - ../../../../../../apps/nshlib/nsh_fscmds.c - - - nsh_ddcmd.c - 1 - ../../../../../../apps/nshlib/nsh_ddcmd.c - - - nsh_proccmds.c - 1 - ../../../../../../apps/nshlib/nsh_proccmds.c - - - nsh_mmcmds.c - 1 - ../../../../../../apps/nshlib/nsh_mmcmds.c - - - nsh_timcmds.c - 1 - ../../../../../../apps/nshlib/nsh_timcmds.c - - - nsh_envcmds.c - 1 - ../../../../../../apps/nshlib/nsh_envcmds.c - - - nsh_syscmds.c - 1 - ../../../../../../apps/nshlib/nsh_syscmds.c - - - nsh_dbgcmds.c - 1 - ../../../../../../apps/nshlib/nsh_dbgcmds.c - - - nsh_session.c - 1 - ../../../../../../apps/nshlib/nsh_session.c - - - nsh_fsutils.c - 1 - ../../../../../../apps/nshlib/nsh_fsutils.c - - - nsh_builtin.c - 1 - ../../../../../../apps/nshlib/nsh_builtin.c - - - nsh_netinit.c - 1 - ../../../../../../apps/nshlib/nsh_netinit.c - - - nsh_netcmds.c - 1 - ../../../../../../apps/nshlib/nsh_netcmds.c - - - nsh_mntcmds.c - 1 - ../../../../../../apps/nshlib/nsh_mntcmds.c - - - nsh_consolemain.c - 1 - ../../../../../../apps/nshlib/nsh_consolemain.c - - - nsh_test.c - 1 - ../../../../../../apps/nshlib/nsh_test.c - - - readline_common.c - 1 - ../../../../../../apps/system/readline/readline_common.c - - - readline.c - 1 - ../../../../../../apps/system/readline/readline.c - - - - - - - -               diff --git a/configs/stm3220g-eval/ide/nsh/uvision/libarch.uvproj b/configs/stm3220g-eval/ide/nsh/uvision/libarch.uvproj deleted file mode 100644 index 0ef02358108570e4476142703933a2a354cde819..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/uvision/libarch.uvproj +++ /dev/null @@ -1,817 +0,0 @@ - - - - 1.1 - -
              ### uVision Project, (C) Keil Software
              - - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M3 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE - - - - 4349 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libarch\Obj\ - arch - 0 - 1 - 1 - 1 - 0 - .\libarch\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M3" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - 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1 - ../../../../../arch/arm/src/common/up_createstack.c - - - up_mdelay.c - 1 - ../../../../../arch/arm/src/common/up_mdelay.c - - - up_udelay.c - 1 - ../../../../../arch/arm/src/common/up_udelay.c - - - up_exit.c - 1 - ../../../../../arch/arm/src/common/up_exit.c - - - up_initialize.c - 1 - ../../../../../arch/arm/src/common/up_initialize.c - - - up_initialstate.c - 1 - ../../../../../arch/arm/src/armv7-m/up_initialstate.c - - - up_interruptcontext.c - 1 - ../../../../../arch/arm/src/common/up_interruptcontext.c - - - up_memfault.c - 1 - ../../../../../arch/arm/src/armv7-m/up_memfault.c - - - up_modifyreg8.c - 1 - ../../../../../arch/arm/src/common/up_modifyreg8.c - - - up_modifyreg16.c - 1 - ../../../../../arch/arm/src/common/up_modifyreg16.c - - - up_modifyreg32.c - 1 - ../../../../../arch/arm/src/common/up_modifyreg32.c - - - up_releasepending.c - 1 - ../../../../../arch/arm/src/armv7-m/up_releasepending.c - - - up_releasestack.c - 1 - ../../../../../arch/arm/src/common/up_releasestack.c - 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- - - 1.1 - -
              ### uVision Project, (C) Keil Software
              - - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M3 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE - - - - 4349 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libbinfmt\Obj\ - binfmt - 0 - 1 - 1 - 1 - 0 - .\libbinfmt\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M3" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../include;../../../../../sched;../../../../../binfmt - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../include;../../../../../sched;../../../../../binfmt - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - binfmt - - - binfmt_globals.c - 1 - ../../../../../binfmt/binfmt_globals.c - - - binfmt_register.c - 1 - ../../../../../binfmt/binfmt_register.c - - - binfmt_unregister.c - 1 - ../../../../../binfmt/binfmt_unregister.c - - - binfmt_loadmodule.c - 1 - ../../../../../binfmt/binfmt_loadmodule.c - - - binfmt_unloadmodule.c - 1 - ../../../../../binfmt/binfmt_unloadmodule.c - - - binfmt_execmodule.c - 1 - ../../../../../binfmt/binfmt_execmodule.c - - - binfmt_exec.c - 1 - ../../../../../binfmt/binfmt_exec.c - - - binfmt_copyargv.c - 1 - ../../../../../binfmt/binfmt_copyargv.c - - - binfmt_dumpmodule.c - 1 - ../../../../../binfmt/binfmt_dumpmodule.c - - - builtin.c - 1 - ../../../../../binfmt/builtin.c - - - libbuiltin_getname.c - 1 - ../../../../../binfmt/libbuiltin/libbuiltin_getname.c - - - libbuiltin_isavail.c - 1 - ../../../../../binfmt/libbuiltin/libbuiltin_isavail.c - - - - - - - -               diff --git a/configs/stm3220g-eval/ide/nsh/uvision/libboard.uvproj b/configs/stm3220g-eval/ide/nsh/uvision/libboard.uvproj deleted file mode 100644 index ef7bc7218a0473db7f3b1ff5d9e5086856261c2a..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/uvision/libboard.uvproj +++ /dev/null @@ -1,337 +0,0 @@ - - - - 1.1 - -
              ### uVision Project, (C) Keil Software
              - - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M3 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE - - - - 4349 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libboard\Obj\ - board - 0 - 1 - 1 - 1 - 0 - .\libboard\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M3" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../include;../../../../../arch/arm/src/board;../../../../../arch/arm/src/armv7-m;../../../../../sched;../../../../../arch/arm/src/common;../../../../../arch/arm/src/chip - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../include;../../../../../arch/arm/src/board;../../../../../arch/arm/src/armv7-m;../../../../../sched;../../../../../arch/arm/src/common;../../../../../arch/arm/src/chip - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - board - - - stm32_boot.c - 1 - ../../../../../arch/arm/src/board/stm32_boot.c - - - stm32_spi.c - 1 - ../../../../../arch/arm/src/board/stm32_spi.c - - - stm32_autoleds.c - 1 - ../../../../../arch/arm/src/board/stm32_autoleds.c - - - - - - - -               diff --git a/configs/stm3220g-eval/ide/nsh/uvision/libc.uvproj b/configs/stm3220g-eval/ide/nsh/uvision/libc.uvproj deleted file mode 100644 index 90ecb7c9c133efc1eaa0e29119a6c19977ea46b9..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/uvision/libc.uvproj +++ /dev/null @@ -1,1592 +0,0 @@ - - - - 1.1 - -
              ### uVision Project, (C) Keil Software
              - - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M3 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE - - - - 4349 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libc\Obj\ - c - 0 - 1 - 1 - 1 - 0 - .\libc\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M3" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../libc;../../../../../include - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../libc;../../../../../include - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - libc - - - lib_readdirr.c - 1 - ../../../../../libc/dirent/lib_readdirr.c - - - lib_telldir.c - 1 - ../../../../../libc/dirent/lib_telldir.c - - - lib_fixedmath.c - 1 - ../../../../../libc/fixedmath/lib_fixedmath.c - - - lib_b16sin.c - 1 - ../../../../../libc/fixedmath/lib_b16sin.c - - - lib_b16cos.c - 1 - ../../../../../libc/fixedmath/lib_b16cos.c - - - lib_b16atan2.c - 1 - ../../../../../libc/fixedmath/lib_b16atan2.c - - - lib_basename.c - 1 - ../../../../../libc/libgen/lib_basename.c - - - lib_dirname.c - 1 - ../../../../../libc/libgen/lib_dirname.c - - - lib_stream.c - 1 - ../../../../../libc/misc/lib_stream.c - - - lib_filesem.c - 1 - ../../../../../libc/misc/lib_filesem.c - - - lib_utsname.c - 1 - ../../../../../libc/misc/lib_utsname.c - - - lib_tea_encrypt.c - 1 - ../../../../../libc/misc/lib_tea_encrypt.c - - - lib_tea_decrypt.c - 1 - ../../../../../libc/misc/lib_tea_decrypt.c - - - lib_umul32.c - 1 - ../../../../../libc/misc/lib_umul32.c - - - lib_umul64.c - 1 - ../../../../../libc/misc/lib_umul64.c - - - lib_umul32x64.c - 1 - ../../../../../libc/misc/lib_umul32x64.c - - - lib_uadd32x64.c - 1 - ../../../../../libc/misc/lib_uadd32x64.c - - - lib_uadd64.c - 1 - ../../../../../libc/misc/lib_uadd64.c - - - lib_usub64x32.c - 1 - ../../../../../libc/misc/lib_usub64x32.c - - - lib_usub64.c - 1 - ../../../../../libc/misc/lib_usub64.c - - - lib_sendfile.c - 1 - ../../../../../libc/misc/lib_sendfile.c - - - lib_streamsem.c - 1 - ../../../../../libc/misc/lib_streamsem.c - - - lib_match.c - 1 - ../../../../../libc/misc/lib_match.c - - - lib_crc32.c - 1 - ../../../../../libc/misc/lib_crc32.c - - - lib_crc16.c - 1 - ../../../../../libc/misc/lib_crc16.c - - - lib_crc8.c - 1 - ../../../../../libc/misc/lib_crc8.c - - - lib_dumpbuffer.c - 1 - ../../../../../libc/misc/lib_dumpbuffer.c - - - lib_addrconfig.c - 1 - ../../../../../libc/net/lib_addrconfig.c - - - lib_etherntoa.c - 1 - ../../../../../libc/net/lib_etherntoa.c - - - lib_htons.c - 1 - ../../../../../libc/net/lib_htons.c - - - lib_htonl.c - 1 - ../../../../../libc/net/lib_htonl.c - - - lib_inetaddr.c - 1 - ../../../../../libc/net/lib_inetaddr.c - - - lib_inetntoa.c - 1 - ../../../../../libc/net/lib_inetntoa.c - - - lib_inetntop.c - 1 - ../../../../../libc/net/lib_inetntop.c - - - lib_inetpton.c - 1 - ../../../../../libc/net/lib_inetpton.c - - - lib_shutdown.c - 1 - ../../../../../libc/net/lib_shutdown.c - - - lib_netdb.c - 1 - ../../../../../libc/netdb/lib_netdb.c - - - lib_gethostbyname.c - 1 - ../../../../../libc/netdb/lib_gethostbyname.c - - - lib_gethostbynamer.c - 1 - ../../../../../libc/netdb/lib_gethostbynamer.c - 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1 - ../../../../../libc/unistd/lib_gethostname.c - - - lib_sethostname.c - 1 - ../../../../../libc/unistd/lib_sethostname.c - - - - - - - -               diff --git a/configs/stm3220g-eval/ide/nsh/uvision/libdrivers.uvproj b/configs/stm3220g-eval/ide/nsh/uvision/libdrivers.uvproj deleted file mode 100644 index f31ea50bf860b852db499b839ba5ed1177af70af..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/uvision/libdrivers.uvproj +++ /dev/null @@ -1,462 +0,0 @@ - - - - 1.1 - -
              ### uVision Project, (C) Keil Software
              - - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M3 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE - - - - 4349 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libdrivers\Obj\ - drivers - 0 - 1 - 1 - 1 - 0 - .\libdrivers\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M3" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../drivers/bch;../../../../../drivers;../../../../../drivers/i2c;../../../../../drivers/mmcsd;../../../../../drivers/loop;../../../../../drivers/usbhost;../../../../../include - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../drivers/bch;../../../../../drivers;../../../../../drivers/i2c;../../../../../drivers/mmcsd;../../../../../drivers/loop;../../../../../drivers/usbhost;../../../../../include - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - drivers - - - bchlib_setup.c - 1 - ../../../../../drivers/bch/bchlib_setup.c - - - bchlib_teardown.c - 1 - ../../../../../drivers/bch/bchlib_teardown.c - - - bchlib_read.c - 1 - ../../../../../drivers/bch/bchlib_read.c - - - bchlib_write.c - 1 - ../../../../../drivers/bch/bchlib_write.c - - - bchlib_cache.c - 1 - ../../../../../drivers/bch/bchlib_cache.c - - - bchlib_sem.c - 1 - ../../../../../drivers/bch/bchlib_sem.c - - - bchdev_register.c - 1 - ../../../../../drivers/bch/bchdev_register.c - - - bchdev_unregister.c - 1 - ../../../../../drivers/bch/bchdev_unregister.c - - - bchdev_driver.c - 1 - ../../../../../drivers/bch/bchdev_driver.c - - - i2c_read.c - 1 - ../../../../../drivers/i2c/i2c_read.c - - - i2c_write.c - 1 - ../../../../../drivers/i2c/i2c_write.c - - - i2c_writeread.c - 1 - ../../../../../drivers/i2c/i2c_writeread.c - - - losetup.c - 1 - ../../../../../drivers/loop/losetup.c - - - at45db.c - 1 - ../../../../../drivers/mtd/at45db.c - - - ftl.c - 1 - ../../../../../drivers/mtd/ftl.c - - - m25px.c - 1 - ../../../../../drivers/mtd/m25px.c - - - ramtron.c - 1 - ../../../../../drivers/mtd/ramtron.c - - - mtd_config.c - 1 - ../../../../../drivers/mtd/mtd_config.c - - - pipe.c - 1 - ../../../../../drivers/pipes/pipe.c - - - fifo.c - 1 - ../../../../../drivers/pipes/fifo.c - - - pipe_common.c - 1 - ../../../../../drivers/pipes/pipe_common.c - - - serial.c - 1 - ../../../../../drivers/serial/serial.c - - - serial_io.c - 1 - ../../../../../drivers/serial/serial_io.c - - - lowconsole.c - 1 - ../../../../../drivers/serial/lowconsole.c - - - hid_parser.c - 1 - ../../../../../drivers/usbhost/hid_parser.c - - - dev_null.c - 1 - ../../../../../drivers/dev_null.c - - - dev_zero.c - 1 - ../../../../../drivers/dev_zero.c - - - ramdisk.c - 1 - ../../../../../drivers/ramdisk.c - - - - - - - -               diff --git a/configs/stm3220g-eval/ide/nsh/uvision/libfs.uvproj b/configs/stm3220g-eval/ide/nsh/uvision/libfs.uvproj deleted file mode 100644 index 7ce92b3285c19af3407a8f164eed4f88ffafcdd4..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/uvision/libfs.uvproj +++ /dev/null @@ -1,617 +0,0 @@ - - - - 1.1 - -
              ### uVision Project, (C) Keil Software
              - - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M3 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE - - - - 4349 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libfs\Obj\ - fs - 0 - 1 - 1 - 1 - 0 - .\libfs\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M3" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../fs;../../../../../include - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../fs;../../../../../include - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - fs - - - fs_initialize.c - 1 - ../../../../../fs/fs_initialize.c - - - fs_files.c - 1 - ../../../../../fs/inode/fs_files.c - - - fs_foreachinode.c - 1 - ../../../../../fs/inode/fs_foreachinode.c - - - fs_inode.c - 1 - ../../../../../fs/inode/fs_inode.c - - - fs_inodeaddref.c - 1 - ../../../../../fs/inode/fs_inodeaddref.c - - - fs_inodebasename.c - 1 - ../../../../../fs/inode/fs_inodebasename.c - - - fs_inodefind.c - 1 - ../../../../../fs/inode/fs_inodefind.c - - - fs_inoderelease.c - 1 - ../../../../../fs/inode/fs_inoderelease.c - - - fs_inoderemove.c - 1 - ../../../../../fs/inode/fs_inoderemove.c - - - fs_inodereserve.c - 1 - ../../../../../fs/inode/fs_inodereserve.c - - - fs_close.c - 1 - ../../../../../fs/vfs/fs_close.c - - - fs_dup.c - 1 - ../../../../../fs/vfs/fs_dup.c - - - fs_dup2.c - 1 - ../../../../../fs/vfs/fs_dup2.c - - - fs_fcntl.c - 1 - ../../../../../fs/vfs/fs_fcntl.c - - - fs_dupfd.c - 1 - ../../../../../fs/vfs/fs_dupfd.c - - - fs_dupfd2.c - 1 - ../../../../../fs/vfs/fs_dupfd2.c - - - fs_epoll.c - 1 - ../../../../../fs/vfs/fs_epoll.c - - - fs_getfilep.c - 1 - ../../../../../fs/vfs/fs_getfilep.c - - - fs_ioctl.c - 1 - ../../../../../fs/vfs/fs_ioctl.c - - - fs_lseek.c - 1 - ../../../../../fs/vfs/fs_lseek.c - - - fs_mkdir.c - 1 - ../../../../../fs/vfs/fs_mkdir.c - - - fs_open.c - 1 - ../../../../../fs/vfs/fs_open.c - - - fs_poll.c - 1 - ../../../../../fs/vfs/fs_poll.c - - - fs_read.c - 1 - ../../../../../fs/vfs/fs_read.c - - - fs_rename.c - 1 - ../../../../../fs/vfs/fs_rename.c - - - fs_rmdir.c - 1 - ../../../../../fs/vfs/fs_rmdir.c - - - fs_stat.c - 1 - ../../../../../fs/vfs/fs_stat.c - - - fs_statfs.c - 1 - ../../../../../fs/vfs/fs_statfs.c - - - fs_select.c - 1 - ../../../../../fs/vfs/fs_select.c - - - fs_unlink.c - 1 - ../../../../../fs/vfs/fs_unlink.c - - - fs_write.c - 1 - ../../../../../fs/vfs/fs_write.c - - - fs_fsync.c - 1 - ../../../../../fs/vfs/fs_fsync.c - - - fs_pread.c - 1 - ../../../../../fs/vfs/fs_pread.c - - - fs_pwrite.c - 1 - ../../../../../fs/vfs/fs_pwrite.c - - - fs_fdopen.c - 1 - ../../../../../fs/vfs/fs_fdopen.c - - - fs_registerdriver.c - 1 - ../../../../../fs/driver/fs_registerdriver.c - - - fs_unregisterdriver.c - 1 - ../../../../../fs/driver/fs_unregisterdriver.c - - - fs_registerblockdriver.c - 1 - ../../../../../fs/driver/fs_registerblockdriver.c - - - fs_unregisterblockdriver.c - 1 - ../../../../../fs/driver/fs_unregisterblockdriver.c - - - fs_findblockdriver.c - 1 - ../../../../../fs/driver/fs_findblockdriver.c - - - fs_openblockdriver.c - 1 - ../../../../../fs/driver/fs_openblockdriver.c - - - fs_closeblockdriver.c - 1 - ../../../../../fs/driver/fs_closeblockdriver.c - - - fs_blockproxy.c - 1 - ../../../../../fs/driver/fs_blockproxy.c - - - fs_closedir.c - 1 - ../../../../../fs/dirent/fs_closedir.c - - - fs_opendir.c - 1 - ../../../../../fs/dirent/fs_opendir.c - - - fs_readdir.c - 1 - ../../../../../fs/dirent/fs_readdir.c - - - fs_rewinddir.c - 1 - ../../../../../fs/dirent/fs_rewinddir.c - - - fs_seekdir.c - 1 - ../../../../../fs/dirent/fs_seekdir.c - - - fs_mmap.c - 1 - ../../../../../fs/mmap/fs_mmap.c - - - mq_open.c - 1 - ../../../../../fs/mqueue/mq_open.c - - - mq_close.c - 1 - ../../../../../fs/mqueue/mq_close.c - - - mq_unlink.c - 1 - ../../../../../fs/mqueue/mq_unlink.c - - - fs_mount.c - 1 - ../../../../../fs/mount/fs_mount.c - - - fs_umount2.c - 1 - ../../../../../fs/mount/fs_umount2.c - - - fs_foreachmountpoint.c - 1 - ../../../../../fs/mount/fs_foreachmountpoint.c - - - fs_fat32.c - 1 - ../../../../../fs/fat/fs_fat32.c - - - fs_fat32dirent.c - 1 - ../../../../../fs/fat/fs_fat32dirent.c - - - fs_fat32attrib.c - 1 - ../../../../../fs/fat/fs_fat32attrib.c - - - fs_fat32util.c - 1 - ../../../../../fs/fat/fs_fat32util.c - - - - - - - -               diff --git a/configs/stm3220g-eval/ide/nsh/uvision/libmm.uvproj b/configs/stm3220g-eval/ide/nsh/uvision/libmm.uvproj deleted file mode 100644 index 51ca6c8003af39e27bc39e3094a3253c50b230fc..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/uvision/libmm.uvproj +++ /dev/null @@ -1,457 +0,0 @@ - - - - 1.1 - -
              ### uVision Project, (C) Keil Software
              - - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M3 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE - - - - 4349 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libmm\Obj\ - mm - 0 - 1 - 1 - 1 - 0 - .\libmm\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M3" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../mm;../../../../../include - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../mm;../../../../../include - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - mm - - - mm_initialize.c - 1 - ../../../../../mm/mm_heap/mm_initialize.c - - - mm_sem.c - 1 - ../../../../../mm/mm_heap/mm_sem.c - - - mm_addfreechunk.c - 1 - ../../../../../mm/mm_heap/mm_addfreechunk.c - - - mm_size2ndx.c - 1 - ../../../../../mm/mm_heap/mm_size2ndx.c - - - mm_shrinkchunk.c - 1 - ../../../../../mm/mm_heap/mm_shrinkchunk.c - - - mm_brkaddr.c - 1 - ../../../../../mm/mm_heap/mm_brkaddr.c - - - mm_calloc.c - 1 - ../../../../../mm/mm_heap/mm_calloc.c - - - mm_extend.c - 1 - ../../../../../mm/mm_heap/mm_extend.c - - - mm_free.c - 1 - ../../../../../mm/mm_heap/mm_free.c - - - mm_mallinfo.c - 1 - ../../../../../mm/mm_heap/mm_mallinfo.c - - - mm_malloc.c - 1 - ../../../../../mm/mm_heap/mm_malloc.c - - - mm_memalign.c - 1 - ../../../../../mm/mm_heap/mm_memalign.c - - - mm_realloc.c - 1 - ../../../../../mm/mm_heap/mm_realloc.c - - - mm_zalloc.c - 1 - ../../../../../mm/mm_heap/mm_zalloc.c - - - umm_initialize.c - 1 - ../../../../../mm/umm_heap/umm_initialize.c - - - umm_addregion.c - 1 - ../../../../../mm/umm_heap/umm_addregion.c - - - umm_sem.c - 1 - ../../../../../mm/umm_heap/umm_sem.c - - - umm_brkaddr.c - 1 - ../../../../../mm/umm_heap/umm_brkaddr.c - - - umm_calloc.c - 1 - ../../../../../mm/umm_heap/umm_calloc.c - - - umm_extend.c - 1 - ../../../../../mm/umm_heap/umm_extend.c - - - umm_free.c - 1 - ../../../../../mm/umm_heap/umm_free.c - - - umm_mallinfo.c - 1 - ../../../../../mm/umm_heap/umm_mallinfo.c - - - umm_malloc.c - 1 - ../../../../../mm/umm_heap/umm_malloc.c - - - umm_memalign.c - 1 - ../../../../../mm/umm_heap/umm_memalign.c - - - umm_realloc.c - 1 - ../../../../../mm/umm_heap/umm_realloc.c - - - umm_zalloc.c - 1 - ../../../../../mm/umm_heap/umm_zalloc.c - - - umm_globals.c - 1 - ../../../../../mm/umm_heap/umm_globals.c - - - - - - - -               diff --git a/configs/stm3220g-eval/ide/nsh/uvision/libnet.uvproj b/configs/stm3220g-eval/ide/nsh/uvision/libnet.uvproj deleted file mode 100644 index fe8cbdce9cd8e70843cc0d634aa4941989a3d866..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/uvision/libnet.uvproj +++ /dev/null @@ -1,807 +0,0 @@ - - - - 1.1 - -
              ### uVision Project, (C) Keil Software
              - - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M3 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE - - - - 4349 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libnet\Obj\ - net - 0 - 1 - 1 - 1 - 0 - .\libnet\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M3" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../net;../../../../../include - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../net;../../../../../include - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - net - - - bind.c - 1 - ../../../../../net/socket/bind.c - - - connect.c - 1 - ../../../../../net/socket/connect.c - - - getsockname.c - 1 - ../../../../../net/socket/getsockname.c - - - recv.c - 1 - ../../../../../net/socket/recv.c - - - recvfrom.c - 1 - ../../../../../net/socket/recvfrom.c - - - send.c - 1 - ../../../../../net/socket/send.c - - - sendto.c - 1 - ../../../../../net/socket/sendto.c - - - socket.c - 1 - ../../../../../net/socket/socket.c - - - net_sockets.c - 1 - ../../../../../net/socket/net_sockets.c - - - net_close.c - 1 - ../../../../../net/socket/net_close.c - - - net_dupsd.c - 1 - ../../../../../net/socket/net_dupsd.c - - - net_dupsd2.c - 1 - ../../../../../net/socket/net_dupsd2.c - - - net_clone.c - 1 - ../../../../../net/socket/net_clone.c - - - net_poll.c - 1 - ../../../../../net/socket/net_poll.c - - - net_vfcntl.c - 1 - ../../../../../net/socket/net_vfcntl.c - - - listen.c - 1 - ../../../../../net/socket/listen.c - - - accept.c - 1 - ../../../../../net/socket/accept.c - - - net_monitor.c - 1 - ../../../../../net/socket/net_monitor.c - - - setsockopt.c - 1 - ../../../../../net/socket/setsockopt.c - - - getsockopt.c - 1 - ../../../../../net/socket/getsockopt.c - - - net_timeo.c - 1 - ../../../../../net/socket/net_timeo.c - - - net_checksd.c - 1 - ../../../../../net/socket/net_checksd.c - - - tcp_accept.c - 1 - ../../../../../net/tcp/tcp_accept.c - - - tcp_send_unbuffered.c - 1 - ../../../../../net/tcp/tcp_send_unbuffered.c - - - netdev_register.c - 1 - ../../../../../net/netdev/netdev_register.c - - - netdev_ioctl.c - 1 - ../../../../../net/netdev/netdev_ioctl.c - - - netdev_txnotify.c - 1 - ../../../../../net/netdev/netdev_txnotify.c - - - netdev_findbyname.c - 1 - ../../../../../net/netdev/netdev_findbyname.c - - - netdev_findbyaddr.c - 1 - ../../../../../net/netdev/netdev_findbyaddr.c - - - netdev_findbyindex.c - 1 - ../../../../../net/netdev/netdev_findbyindex.c - - - netdev_count.c - 1 - ../../../../../net/netdev/netdev_count.c - - - netdev_foreach.c - 1 - ../../../../../net/netdev/netdev_foreach.c - - - netdev_unregister.c - 1 - ../../../../../net/netdev/netdev_unregister.c - - - netdev_carrier.c - 1 - ../../../../../net/netdev/netdev_carrier.c - - - netdev_default.c - 1 - ../../../../../net/netdev/netdev_default.c - - - netdev_verify.c - 1 - ../../../../../net/netdev/netdev_verify.c - - - net_initialize.c - 1 - ../../../../../net/net_initialize.c - - - iob_add_queue.c - 1 - ../../../../../net/iob/iob_add_queue.c - - - iob_alloc.c - 1 - ../../../../../net/iob/iob_alloc.c - - - iob_alloc_qentry.c - 1 - ../../../../../net/iob/iob_alloc_qentry.c - - - iob_clone.c - 1 - ../../../../../net/iob/iob_clone.c - - - iob_concat.c - 1 - ../../../../../net/iob/iob_concat.c - - - iob_copyin.c - 1 - ../../../../../net/iob/iob_copyin.c - - - iob_copyout.c - 1 - ../../../../../net/iob/iob_copyout.c - - - iob_contig.c - 1 - ../../../../../net/iob/iob_contig.c - - - iob_free.c - 1 - ../../../../../net/iob/iob_free.c - - - iob_free_chain.c - 1 - ../../../../../net/iob/iob_free_chain.c - - - iob_free_qentry.c - 1 - ../../../../../net/iob/iob_free_qentry.c - - - iob_free_queue.c - 1 - ../../../../../net/iob/iob_free_queue.c - - - iob_initialize.c - 1 - ../../../../../net/iob/iob_initialize.c - - - iob_pack.c - 1 - ../../../../../net/iob/iob_pack.c - - - iob_peek_queue.c - 1 - ../../../../../net/iob/iob_peek_queue.c - - - iob_remove_queue.c - 1 - ../../../../../net/iob/iob_remove_queue.c - - - iob_trimhead.c - 1 - ../../../../../net/iob/iob_trimhead.c - - - iob_trimhead_queue.c - 1 - ../../../../../net/iob/iob_trimhead_queue.c - - - iob_trimtail.c - 1 - ../../../../../net/iob/iob_trimtail.c - - - arp_arpin.c - 1 - ../../../../../net/arp/arp_arpin.c - - - arp_out.c - 1 - ../../../../../net/arp/arp_out.c - - - arp_format.c - 1 - ../../../../../net/arp/arp_format.c - - - arp_table.c - 1 - ../../../../../net/arp/arp_table.c - - - arp_timer.c - 1 - ../../../../../net/arp/arp_timer.c - - - icmp_input.c - 1 - ../../../../../net/icmp/icmp_input.c - - - icmp_ping.c - 1 - ../../../../../net/icmp/icmp_ping.c - - - icmp_poll.c - 1 - ../../../../../net/icmp/icmp_poll.c - - - icmp_send.c - 1 - ../../../../../net/icmp/icmp_send.c - - - tcp_conn.c - 1 - ../../../../../net/tcp/tcp_conn.c - - - tcp_seqno.c - 1 - ../../../../../net/tcp/tcp_seqno.c - - - tcp_devpoll.c - 1 - ../../../../../net/tcp/tcp_devpoll.c - - - tcp_finddev.c - 1 - ../../../../../net/tcp/tcp_finddev.c - - - tcp_timer.c - 1 - ../../../../../net/tcp/tcp_timer.c - - - tcp_send.c - 1 - ../../../../../net/tcp/tcp_send.c - - - tcp_input.c - 1 - ../../../../../net/tcp/tcp_input.c - - - tcp_appsend.c - 1 - ../../../../../net/tcp/tcp_appsend.c - - - tcp_listen.c - 1 - ../../../../../net/tcp/tcp_listen.c - - - tcp_callback.c - 1 - ../../../../../net/tcp/tcp_callback.c - - - tcp_backlog.c - 1 - ../../../../../net/tcp/tcp_backlog.c - - - tcp_ipselect.c - 1 - ../../../../../net/tcp/tcp_ipselect.c - - - udp_psock_send.c - 1 - ../../../../../net/udp/udp_psock_send.c - - - udp_psock_sendto.c - 1 - ../../../../../net/udp/udp_psock_sendto.c - - - udp_conn.c - 1 - ../../../../../net/udp/udp_conn.c - - - udp_devpoll.c - 1 - ../../../../../net/udp/udp_devpoll.c - - - udp_send.c - 1 - ../../../../../net/udp/udp_send.c - - - udp_input.c - 1 - ../../../../../net/udp/udp_input.c - - - udp_finddev.c - 1 - ../../../../../net/udp/udp_finddev.c - - - udp_callback.c - 1 - ../../../../../net/udp/udp_callback.c - - - udp_ipselect.c - 1 - ../../../../../net/udp/udp_ipselect.c - - - devif_initialize.c - 1 - ../../../../../net/devif/devif_initialize.c - - - net_setipid.c - 1 - ../../../../../net/devif/net_setipid.c - - - devif_send.c - 1 - ../../../../../net/devif/devif_send.c - - - devif_poll.c - 1 - ../../../../../net/devif/devif_poll.c - - - devif_callback.c - 1 - ../../../../../net/devif/devif_callback.c - - - ipv4_input.c - 1 - ../../../../../net/devif/ipv4_input.c - - - devif_iobsend.c - 1 - ../../../../../net/devif/devif_iobsend.c - - - net_dsec2tick.c - 1 - ../../../../../net/utils/net_dsec2tick.c - - - net_dsec2timeval.c - 1 - ../../../../../net/utils/net_dsec2timeval.c - - - net_timeval2dsec.c - 1 - ../../../../../net/utils/net_timeval2dsec.c - - - net_chksum.c - 1 - ../../../../../net/utils/net_chksum.c - - - - - - - -               diff --git a/configs/stm3220g-eval/ide/nsh/uvision/libsched.uvproj b/configs/stm3220g-eval/ide/nsh/uvision/libsched.uvproj deleted file mode 100644 index b56247bf2d2f98a686a21810b11d69d86126d8ef..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/uvision/libsched.uvproj +++ /dev/null @@ -1,1267 +0,0 @@ - - - - 1.1 - -
              ### uVision Project, (C) Keil Software
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- - clock_systimer.c - 1 - ../../../../../sched/clock/clock_systimer.c - - - clock_systimespec.c - 1 - ../../../../../sched/clock/clock_systimespec.c - - - clock_timespec_add.c - 1 - ../../../../../sched/clock/clock_timespec_add.c - - - clock_timespec_subtract.c - 1 - ../../../../../sched/clock/clock_timespec_subtract.c - - - errno_getptr.c - 1 - ../../../../../sched/errno/errno_getptr.c - - - env_getenvironptr.c - 1 - ../../../../../sched/environ/env_getenvironptr.c - - - env_dup.c - 1 - ../../../../../sched/environ/env_dup.c - - - env_release.c - 1 - ../../../../../sched/environ/env_release.c - - - env_findvar.c - 1 - ../../../../../sched/environ/env_findvar.c - - - env_removevar.c - 1 - ../../../../../sched/environ/env_removevar.c - - - env_clearenv.c - 1 - ../../../../../sched/environ/env_clearenv.c - - - env_getenv.c - 1 - ../../../../../sched/environ/env_getenv.c - - - env_putenv.c - 1 - ../../../../../sched/environ/env_putenv.c - - - env_setenv.c - 1 - ../../../../../sched/environ/env_setenv.c - - - env_unsetenv.c - 1 - ../../../../../sched/environ/env_unsetenv.c - - - group_create.c - 1 - ../../../../../sched/group/group_create.c - - - group_join.c - 1 - ../../../../../sched/group/group_join.c - - - group_leave.c - 1 - ../../../../../sched/group/group_leave.c - - - group_find.c - 1 - ../../../../../sched/group/group_find.c - - - group_setupstreams.c - 1 - ../../../../../sched/group/group_setupstreams.c - - - group_setupidlefiles.c - 1 - ../../../../../sched/group/group_setupidlefiles.c - - - group_setuptaskfiles.c - 1 - ../../../../../sched/group/group_setuptaskfiles.c - - - group_foreachchild.c - 1 - ../../../../../sched/group/group_foreachchild.c - - - group_killchildren.c - 1 - ../../../../../sched/group/group_killchildren.c - - - group_waiter.c - 1 - ../../../../../sched/group/group_waiter.c - - - group_signal.c - 1 - ../../../../../sched/group/group_signal.c - - - os_start.c - 1 - ../../../../../sched/init/os_start.c - - - os_bringup.c - 1 - ../../../../../sched/init/os_bringup.c - - - irq_initialize.c - 1 - ../../../../../sched/irq/irq_initialize.c - - - irq_attach.c - 1 - ../../../../../sched/irq/irq_attach.c - - - irq_dispatch.c - 1 - ../../../../../sched/irq/irq_dispatch.c - - - irq_unexpectedisr.c - 1 - ../../../../../sched/irq/irq_unexpectedisr.c - - - mq_send.c - 1 - ../../../../../sched/mqueue/mq_send.c - - - mq_timedsend.c - 1 - ../../../../../sched/mqueue/mq_timedsend.c - - - mq_sndinternal.c - 1 - ../../../../../sched/mqueue/mq_sndinternal.c - - - mq_receive.c - 1 - ../../../../../sched/mqueue/mq_receive.c - - - mq_timedreceive.c - 1 - ../../../../../sched/mqueue/mq_timedreceive.c - - - mq_rcvinternal.c - 1 - ../../../../../sched/mqueue/mq_rcvinternal.c - - - mq_initialize.c - 1 - ../../../../../sched/mqueue/mq_initialize.c - - - mq_descreate.c - 1 - ../../../../../sched/mqueue/mq_descreate.c - - - mq_desclose.c - 1 - ../../../../../sched/mqueue/mq_desclose.c - - - mq_msgfree.c - 1 - ../../../../../sched/mqueue/mq_msgfree.c - - - mq_msgqalloc.c - 1 - ../../../../../sched/mqueue/mq_msgqalloc.c - - - mq_msgqfree.c - 1 - ../../../../../sched/mqueue/mq_msgqfree.c - - - mq_release.c - 1 - ../../../../../sched/mqueue/mq_release.c - - - mq_recover.c - 1 - ../../../../../sched/mqueue/mq_recover.c - - - mq_setattr.c - 1 - ../../../../../sched/mqueue/mq_setattr.c - - - mq_getattr.c - 1 - ../../../../../sched/mqueue/mq_getattr.c - - - mq_waitirq.c - 1 - ../../../../../sched/mqueue/mq_waitirq.c - - - mq_notify.c - 1 - ../../../../../sched/mqueue/mq_notify.c - - - pg_miss.c - 1 - ../../../../../sched/paging/pg_miss.c - - - pg_worker.c - 1 - ../../../../../sched/paging/pg_worker.c - - - pthread_create.c - 1 - ../../../../../sched/pthread/pthread_create.c - - - pthread_exit.c - 1 - ../../../../../sched/pthread/pthread_exit.c - - - pthread_join.c - 1 - ../../../../../sched/pthread/pthread_join.c - - - pthread_detach.c - 1 - ../../../../../sched/pthread/pthread_detach.c - - - pthread_yield.c - 1 - ../../../../../sched/pthread/pthread_yield.c - - - pthread_getschedparam.c - 1 - ../../../../../sched/pthread/pthread_getschedparam.c - - - pthread_setschedparam.c - 1 - ../../../../../sched/pthread/pthread_setschedparam.c - - - pthread_mutexinit.c - 1 - ../../../../../sched/pthread/pthread_mutexinit.c - - - pthread_mutexdestroy.c - 1 - ../../../../../sched/pthread/pthread_mutexdestroy.c - - - pthread_mutexlock.c - 1 - ../../../../../sched/pthread/pthread_mutexlock.c - - - pthread_mutextrylock.c - 1 - ../../../../../sched/pthread/pthread_mutextrylock.c - - - pthread_mutexunlock.c - 1 - ../../../../../sched/pthread/pthread_mutexunlock.c - - - pthread_condinit.c - 1 - ../../../../../sched/pthread/pthread_condinit.c - - - pthread_conddestroy.c - 1 - ../../../../../sched/pthread/pthread_conddestroy.c - - - pthread_condwait.c - 1 - ../../../../../sched/pthread/pthread_condwait.c - - - pthread_condsignal.c - 1 - ../../../../../sched/pthread/pthread_condsignal.c - - - pthread_condbroadcast.c - 1 - ../../../../../sched/pthread/pthread_condbroadcast.c - - - pthread_barrierinit.c - 1 - ../../../../../sched/pthread/pthread_barrierinit.c - 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../../../../../sched/sched/sched_addblocked.c - - - sched_removeblocked.c - 1 - ../../../../../sched/sched/sched_removeblocked.c - - - sched_free.c - 1 - ../../../../../sched/sched/sched_free.c - - - sched_gettcb.c - 1 - ../../../../../sched/sched/sched_gettcb.c - - - sched_verifytcb.c - 1 - ../../../../../sched/sched/sched_verifytcb.c - - - sched_releasetcb.c - 1 - ../../../../../sched/sched/sched_releasetcb.c - - - sched_getsockets.c - 1 - ../../../../../sched/sched/sched_getsockets.c - - - sched_getstreams.c - 1 - ../../../../../sched/sched/sched_getstreams.c - - - sched_setparam.c - 1 - ../../../../../sched/sched/sched_setparam.c - - - sched_setpriority.c - 1 - ../../../../../sched/sched/sched_setpriority.c - - - sched_getparam.c - 1 - ../../../../../sched/sched/sched_getparam.c - - - sched_setscheduler.c - 1 - ../../../../../sched/sched/sched_setscheduler.c - - - sched_getscheduler.c - 1 - ../../../../../sched/sched/sched_getscheduler.c - - - sched_yield.c - 1 - ../../../../../sched/sched/sched_yield.c - - - sched_rrgetinterval.c - 1 - ../../../../../sched/sched/sched_rrgetinterval.c - - - sched_foreach.c - 1 - ../../../../../sched/sched/sched_foreach.c - - - sched_lock.c - 1 - ../../../../../sched/sched/sched_lock.c - - - sched_unlock.c - 1 - ../../../../../sched/sched/sched_unlock.c - - - sched_lockcount.c - 1 - ../../../../../sched/sched/sched_lockcount.c - - - sched_self.c - 1 - ../../../../../sched/sched/sched_self.c - - - sched_waitpid.c - 1 - ../../../../../sched/sched/sched_waitpid.c - - - sched_roundrobin.c - 1 - ../../../../../sched/sched/sched_roundrobin.c - - - sched_resumescheduler.c - 1 - ../../../../../sched/sched/sched_resumescheduler.c - - - sched_processtimer.c - 1 - ../../../../../sched/sched/sched_processtimer.c - - - sem_destroy.c - 1 - ../../../../../sched/semaphore/sem_destroy.c - - - sem_wait.c - 1 - ../../../../../sched/semaphore/sem_wait.c - - - sem_trywait.c - 1 - ../../../../../sched/semaphore/sem_trywait.c - - - sem_tickwait.c - 1 - ../../../../../sched/semaphore/sem_tickwait.c - - - sem_timedwait.c - 1 - ../../../../../sched/semaphore/sem_timedwait.c - - - sem_timeout.c - 1 - ../../../../../sched/semaphore/sem_timeout.c - - - sem_post.c - 1 - ../../../../../sched/semaphore/sem_post.c - - - sem_recover.c - 1 - ../../../../../sched/semaphore/sem_recover.c - - - sem_reset.c - 1 - ../../../../../sched/semaphore/sem_reset.c - - - sem_waitirq.c - 1 - ../../../../../sched/semaphore/sem_waitirq.c - - - sig_initialize.c - 1 - ../../../../../sched/signal/sig_initialize.c - - - sig_action.c - 1 - ../../../../../sched/signal/sig_action.c - - - sig_procmask.c - 1 - ../../../../../sched/signal/sig_procmask.c - - - sig_pending.c - 1 - ../../../../../sched/signal/sig_pending.c - - - sig_suspend.c - 1 - ../../../../../sched/signal/sig_suspend.c - - - sig_kill.c - 1 - ../../../../../sched/signal/sig_kill.c - - - sig_queue.c - 1 - ../../../../../sched/signal/sig_queue.c - - - sig_waitinfo.c - 1 - ../../../../../sched/signal/sig_waitinfo.c - - - sig_timedwait.c - 1 - ../../../../../sched/signal/sig_timedwait.c - - - sig_findaction.c - 1 - ../../../../../sched/signal/sig_findaction.c - - - sig_allocatependingsigaction.c - 1 - ../../../../../sched/signal/sig_allocatependingsigaction.c - - - sig_releasependingsigaction.c - 1 - ../../../../../sched/signal/sig_releasependingsigaction.c - - - sig_unmaskpendingsignal.c - 1 - ../../../../../sched/signal/sig_unmaskpendingsignal.c - - - sig_removependingsignal.c - 1 - ../../../../../sched/signal/sig_removependingsignal.c - - - sig_releasependingsignal.c - 1 - ../../../../../sched/signal/sig_releasependingsignal.c - - - sig_lowest.c - 1 - ../../../../../sched/signal/sig_lowest.c - - - sig_mqnotempty.c - 1 - ../../../../../sched/signal/sig_mqnotempty.c - - - sig_cleanup.c - 1 - ../../../../../sched/signal/sig_cleanup.c - - - sig_dispatch.c - 1 - ../../../../../sched/signal/sig_dispatch.c - - - sig_deliver.c - 1 - ../../../../../sched/signal/sig_deliver.c - - - sig_pause.c - 1 - ../../../../../sched/signal/sig_pause.c - - - sig_nanosleep.c - 1 - ../../../../../sched/signal/sig_nanosleep.c - - - task_create.c - 1 - ../../../../../sched/task/task_create.c - - - task_init.c - 1 - ../../../../../sched/task/task_init.c - - - task_setup.c - 1 - ../../../../../sched/task/task_setup.c - - - task_activate.c - 1 - ../../../../../sched/task/task_activate.c - - - task_start.c - 1 - ../../../../../sched/task/task_start.c - - - task_delete.c - 1 - ../../../../../sched/task/task_delete.c - - - task_exit.c - 1 - ../../../../../sched/task/task_exit.c - - - task_exithook.c - 1 - ../../../../../sched/task/task_exithook.c - - - task_recover.c - 1 - ../../../../../sched/task/task_recover.c - - - task_restart.c - 1 - ../../../../../sched/task/task_restart.c - - - task_spawnparms.c - 1 - ../../../../../sched/task/task_spawnparms.c - - - task_terminate.c - 1 - ../../../../../sched/task/task_terminate.c - - - task_getgroup.c - 1 - ../../../../../sched/task/task_getgroup.c - - - task_prctl.c - 1 - ../../../../../sched/task/task_prctl.c - - - task_getpid.c - 1 - ../../../../../sched/task/task_getpid.c - - - exit.c - 1 - ../../../../../sched/task/exit.c - - - task_vfork.c - 1 - ../../../../../sched/task/task_vfork.c - - - task_spawn.c - 1 - ../../../../../sched/task/task_spawn.c - - - timer_initialize.c - 1 - ../../../../../sched/timer/timer_initialize.c - - - timer_create.c - 1 - ../../../../../sched/timer/timer_create.c - - - timer_delete.c - 1 - ../../../../../sched/timer/timer_delete.c - - - timer_getoverrun.c - 1 - ../../../../../sched/timer/timer_getoverrun.c - - - timer_gettime.c - 1 - ../../../../../sched/timer/timer_gettime.c - - - timer_settime.c - 1 - ../../../../../sched/timer/timer_settime.c - - - timer_release.c - 1 - ../../../../../sched/timer/timer_release.c - - - wd_initialize.c - 1 - ../../../../../sched/wdog/wd_initialize.c - - - wd_create.c - 1 - ../../../../../sched/wdog/wd_create.c - - - wd_start.c - 1 - ../../../../../sched/wdog/wd_start.c - - - wd_cancel.c - 1 - ../../../../../sched/wdog/wd_cancel.c - - - wd_delete.c - 1 - ../../../../../sched/wdog/wd_delete.c - - - wd_gettime.c - 1 - ../../../../../sched/wdog/wd_gettime.c - - - wd_recover.c - 1 - ../../../../../sched/wdog/wd_recover.c - - - - - - - -               diff --git a/configs/stm3220g-eval/ide/nsh/uvision/nuttx.uvmpw b/configs/stm3220g-eval/ide/nsh/uvision/nuttx.uvmpw deleted file mode 100644 index de01d08212d1807705b10162077ecdf39862f194..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/uvision/nuttx.uvmpw +++ /dev/null @@ -1,55 +0,0 @@ - - - - 1.0 - -
              ### uVision Project, (C) Keil Software
              - - WorkSpace - - - .\libboard.uvproj - - - - .\libmm.uvproj - - - - .\libfs.uvproj - - - - .\libdrivers.uvproj - - - - .\libarch.uvproj - - - - .\libbinfmt.uvproj - - - - .\libsched.uvproj - - - - .\libapps.uvproj - - - - .\libc.uvproj - - - - .\libnet.uvproj - - - - .\nuttx_main.uvproj - 1 - - -               diff --git a/configs/stm3220g-eval/ide/nsh/uvision/nuttx_main.uvproj b/configs/stm3220g-eval/ide/nsh/uvision/nuttx_main.uvproj deleted file mode 100644 index 9ee580a5bd33a8b2f603840db8e428e779fe87a0..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/nsh/uvision/nuttx_main.uvproj +++ /dev/null @@ -1,364 +0,0 @@ - - - - 1.1 - -
              ### uVision Project, (C) Keil Software
              - - - - nuttx - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M3 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE - - - - 4349 - - - - - - - - - - - - 0 - 0 - - - - - \ - - 0 - 0 - 0 - 0 - 1 - - .\nuttx\Obj\ - nuttx - 1 - 0 - 1 - 1 - 0 - .\nuttx\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 6 - - - - - - - - - - - - - - Segger\JL2CM3.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M3" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 2 - 1 - - - - - ../../../../../arch/arm/src/chip;../../../../../arch/arm/src;../../../../../arch/arm/src/armv7-m;../../../../../sched;../../../../../arch/arm/src/common;../../../../../include - - - - 0 - 0 - - - - - ../../../../../arch/arm/src/chip;../../../../../arch/arm/src;../../../../../arch/arm/src/armv7-m;../../../../../sched;../../../../../arch/arm/src/common;../../../../../include - - - - 1 - 0 - 1 - 1 - 0 - - - - - .\lib - --entry=__start -Wl,--start-group -lboard -lmm -lfs -ldrivers -larch -lbinfmt -lsched -lapps -lc -lnet -lgcc -Wl,--end-group - ..\..\..\scripts\ld.script - - - - - - gnu - - - stm32_vectors.S - 1 - ../../../../../arch/arm/src/chip/gnu/stm32_vectors.S - - - 2 - 0 - 0 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - 11 - - - 1 - - - - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 0 - 2 - - - __ASSEMBLY__ - - ../../../../../arch/arm/src/chip;../../../../../arch/arm/src;../../../../../arch/arm/src/armv7-m;../../../../../sched;../../../../../arch/arm/src/common;../../../../../include - - - - - - - - - - - -               diff --git a/configs/stm3220g-eval/ide/template/iar/template_nuttx.eww b/configs/stm3220g-eval/ide/template/iar/template_nuttx.eww deleted file mode 100644 index b276078b0578dffbb03150e63aa6fca6c0668d85..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/template/iar/template_nuttx.eww +++ /dev/null @@ -1,16 +0,0 @@ - - - - - $WS_DIR$\libapps.ewp - - - $WS_DIR$\template_nuttx_lib.ewp - - - $WS_DIR$\template_nuttx_main.ewp - - - - - diff --git a/configs/stm3220g-eval/ide/template/iar/template_nuttx_lib.ewp b/configs/stm3220g-eval/ide/template/iar/template_nuttx_lib.ewp deleted file mode 100644 index cb592dafaefde321b9bf227255540b58ba8f8f59..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/template/iar/template_nuttx_lib.ewp +++ /dev/null @@ -1,1925 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 24 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - Coder - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 24 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - Coder - 0 - - - - - - diff --git a/configs/stm3220g-eval/ide/template/iar/template_nuttx_main.ewp b/configs/stm3220g-eval/ide/template/iar/template_nuttx_main.ewp deleted file mode 100644 index 798ca0eb8fc757f7e2f01f2a7208970fe62853ae..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/template/iar/template_nuttx_main.ewp +++ /dev/null @@ -1,1927 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 24 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - Coder - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 24 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - Coder - 0 - - - - - - diff --git a/configs/stm3220g-eval/ide/template/uvision_gcc/template_nuttx.uvmpw b/configs/stm3220g-eval/ide/template/uvision_gcc/template_nuttx.uvmpw deleted file mode 100644 index 7b04326ec2a9b493a0bde8355be0515b3b0dc5e2..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/template/uvision_gcc/template_nuttx.uvmpw +++ /dev/null @@ -1,21 +0,0 @@ - - - - 1.0 - -
              ### uVision Project, (C) Keil Software
              - - WorkSpace - - - .\template_nuttx_lib.uvproj - 1 - 1 - - - - .\template_nuttx_main.uvproj - 1 - - -               diff --git a/configs/stm3220g-eval/ide/template/uvision_gcc/template_nuttx_lib.uvproj b/configs/stm3220g-eval/ide/template/uvision_gcc/template_nuttx_lib.uvproj deleted file mode 100644 index ab33d27f713a1538e1ec013dffd915cef723528d..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/template/uvision_gcc/template_nuttx_lib.uvproj +++ /dev/null @@ -1,364 +0,0 @@ - - - - 1.1 - -
              ### uVision Project, (C) Keil Software
              - - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M3 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE - - - - 4349 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\nuttx\Obj\ - nuttx - 0 - 1 - 1 - 1 - 0 - .\nuttx\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M3" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - - - - - - - - 0 - 0 - - - __ASSEMBLY__ - - - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - gnu - - - stm32_vectors.S - 1 - ../../../arch/arm/src/chip/gnu/stm32_vectors.S - - - 2 - 0 - 0 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - 11 - - - 1 - - - - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 0 - 2 - - - __ASSEMBLY__ - - - - - - - - - - - - - -               diff --git a/configs/stm3220g-eval/ide/template/uvision_gcc/template_nuttx_main.uvproj b/configs/stm3220g-eval/ide/template/uvision_gcc/template_nuttx_main.uvproj deleted file mode 100644 index 1ab0ae389836d0ce8b3c5f4b957778ac7be32635..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/ide/template/uvision_gcc/template_nuttx_main.uvproj +++ /dev/null @@ -1,364 +0,0 @@ - - - - 1.1 - -
              ### uVision Project, (C) Keil Software
              - - - - nuttx - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M3 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE - - - - 4349 - - - - - - - - - - - - 0 - 0 - - - - - \ - - 0 - 0 - 0 - 0 - 1 - - .\nuttx\Obj\ - nuttx - 1 - 0 - 1 - 1 - 0 - .\nuttx\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 6 - - - - - - - - - - - - - - Segger\JL2CM3.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M3" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 2 - 1 - - - - - - - - - 0 - 0 - - - - - - - - - 1 - 0 - 1 - 1 - 0 - - - - - - --entry=__start - ..\..\..\scripts\ld.script - - - - - - gnu - - - stm32_vectors.S - 1 - ../../../arch/arm/src/chip/gnu/stm32_vectors.S - - - 2 - 0 - 0 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - 11 - - - 1 - - - - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 0 - 2 - - - __ASSEMBLY__ - - - - - - - - - - - - - -               diff --git a/configs/stm3220g-eval/include/board.h b/configs/stm3220g-eval/include/board.h index 74d2b5bea787fc7afa5c16c8671dcf1b186fb734..571f01fb178465a278e2a2a49c7d0eef2ea77eb0 100644 --- a/configs/stm3220g-eval/include/board.h +++ b/configs/stm3220g-eval/include/board.h @@ -459,17 +459,6 @@ extern "C" /************************************************************************************ * Public Function Prototypes ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); /************************************************************************************ * Name: stm3220g_lcdclear diff --git a/configs/stm3220g-eval/nsh/defconfig b/configs/stm3220g-eval/nsh/defconfig index e2331f75efbfe8b77d9237521f8b2495eeb3ee81..a20a2296c17e8c837f1d4e5c0e3f81fddd589167 100644 --- a/configs/stm3220g-eval/nsh/defconfig +++ b/configs/stm3220g-eval/nsh/defconfig @@ -1,4 +1,4 @@ -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set diff --git a/configs/stm3220g-eval/nsh2/defconfig b/configs/stm3220g-eval/nsh2/defconfig index 92c0df11e1aea03a22d9e63a7af2c6b257908ae0..0d7255a4b724b13d349fc358442f71aff6a77246 100644 --- a/configs/stm3220g-eval/nsh2/defconfig +++ b/configs/stm3220g-eval/nsh2/defconfig @@ -1,5 +1,5 @@ # CONFIG_DEV_CONSOLE is not set -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NSH_CONSOLE is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set diff --git a/configs/stm3220g-eval/nxwm/defconfig b/configs/stm3220g-eval/nxwm/defconfig index abd8d86a484787e847114599df62eb414fc053cb..1bfe7f8541516a29d59fd4108b149b0c7a7eeae5 100644 --- a/configs/stm3220g-eval/nxwm/defconfig +++ b/configs/stm3220g-eval/nxwm/defconfig @@ -1,11 +1,11 @@ -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set # CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set CONFIG_ARCH_BOARD_STM3220G_EVAL=y CONFIG_ARCH_BOARD="stm3220g-eval" diff --git a/configs/stm3220g-eval/scripts/stm32f207xG.icf b/configs/stm3220g-eval/scripts/stm32f207xG.icf deleted file mode 100644 index 53041e65a6d6f4a77610d60ada58c11c5ef76e99..0000000000000000000000000000000000000000 --- a/configs/stm3220g-eval/scripts/stm32f207xG.icf +++ /dev/null @@ -1,32 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x2000; -define symbol __ICFEDIT_size_heap__ = 0x2000; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize manually { readwrite }; -do not initialize { section .bss }; -do not initialize { section .data }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file diff --git a/configs/stm3240g-eval/README.txt b/configs/stm3240g-eval/README.txt index 7fb69eeb4938e4052da2b25395f17df8e82437d6..4d7069c878862d318d5427b1f5d9790de732b690 100644 --- a/configs/stm3240g-eval/README.txt +++ b/configs/stm3240g-eval/README.txt @@ -7,15 +7,8 @@ STMicro STM32140G-EVAL development board. Contents ======== - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - - STM3240G-EVAL-specific Configuration Options - - LEDs - Ethernet + - LEDs - PWM - CAN - FPU @@ -24,239 +17,6 @@ Contents - STM3240G-EVAL-specific Configuration Options - Configurations -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment because the Raisonance R-Link emulatator and some RIDE7 development tools - were used and those tools works only under Windows. - -GNU Toolchain Options -===================== - - Toolchain Configurations - ------------------------ - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The Atollic Toolchain, - 3. The devkitARM GNU toolchain, - 4. Raisonance GNU toolchain, or - 5. The NuttX buildroot Toolchain (see below). - - Most testing has been conducted using the CodeSourcery toolchain for Windows and - that is the default toolchain in most configurations (FPU-related testing has - been performed with the Atollic toolchain for windows. To use the Atollic, - devkitARM, Raisonance GNU, or NuttX buildroot toolchain, you simply need to - add one of the following configuration options to your .config (or defconfig) - file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : The Atollic toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE=y : Raisonance RIDE7 under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - NOTE: the CodeSourcery (for Windows), Atollic, devkitARM, and Raisonance toolchains are - Windows native toolchains. The CodeSourcery (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - The CodeSourcery Toolchain (2009q1) - ----------------------------------- - The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - The Atollic "Pro" and "Lite" Toolchain - -------------------------------------- - One problem that I had with the Atollic toolchains is that the provide a gcc.exe - and g++.exe in the same bin/ file as their ARM binaries. If the Atollic bin/ path - appears in your PATH variable before /usr/bin, then you will get the wrong gcc - when you try to build host executables. This will cause to strange, uninterpretable - errors build some host binaries in tools/ when you first make. - - Also, the Atollic toolchains are the only toolchains that have built-in support for - the FPU in these configurations. If you plan to use the Cortex-M4 FPU, you will - need to use the Atollic toolchain for now. See the FPU section below for more - information. - - The Atollic "Lite" Toolchain - ---------------------------- - The free, "Lite" version of the Atollic toolchain does not support C++ nor - does it support ar, nm, objdump, or objcopy. If you use the Atollic "Lite" - toolchain, you will have to set: - - CONFIG_HAVE_CXX=n - - In order to compile successfully. Otherwise, you will get errors like: - - "C++ Compiler only available in TrueSTUDIO Professional" - - The make may then fail in some of the post link processing because of some of - the other missing tools. The Make.defs file replaces the ar and nm with - the default system x86 tool versions and these seem to work okay. Disable all - of the following to avoid using objcopy: - - CONFIG_RRLOAD_BINARY=n - CONFIG_INTELHEX_BINARY=n - CONFIG_MOTOROLA_SREC=n - CONFIG_RAW_BINARY=n - - devkitARM - --------- - The devkitARM toolchain includes a version of MSYS make. Make sure that the - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include paths: You will need include/, arch/arm/src/stm32, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by RIDE. - -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh stm3240g-eval/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - Ethernet ======== @@ -943,14 +703,31 @@ Where is one of the following: -- A simple NSH configuration used for some basic (non-graphic) debug of - the framebuffer character driver at drivers/video/fb.c using test at - apps/examples/fb. The STM3240G-EVAL LCD driver does not support a - framebuffer! This configuration uses the LCD framebuffer front end at + the framebuffer character driver at drivers/video/fb.c. NOTE that + the STM3240G-EVAL LCD driver does not support a framebuffer! It + interfaces with the LCD through a parallel FSMC interface. This + configuration uses the LCD framebuffer front end at drivers/lcd/lcd_framebuffer to convert the LCD interface into a compatible framebuffer interface. + This examples supports the framebuffer test at apps/examples/fb. That + test simply draws a pattern into the framebuffer and updates the LCD. + + This example also supports the pdcurses library at apps/graphics/pdcurses + and the demo programs at apps/examples/pdcurses. This is a good test of + the use of the framebuffer driver in an application. Many of the + pdcurses demos requires user interaction via a mouse, keyboard, or + joystick. No input devices are currently present in the configuration + so no such interaction is possible. + + The STM3240G-EVAL does provide a on-board discrete joystick (djoystick) + that could be used for this interaction. However, those discrete inputs + do not go directly to the STM32 but rather go indirectly through an I/O + expander. I just have not had the motivation to deal with that yet. + STATUS: 2017-09-17: This configuration appears to be fully functional. + 2017-11-25: Non-interactive pdcurses examples added. knxwm: ----- diff --git a/configs/stm3240g-eval/fb/defconfig b/configs/stm3240g-eval/fb/defconfig index ce96d536dbc7bf705523508378109cef2ded896a..f101953f56dafb599af1bc665093e0393799fcb4 100644 --- a/configs/stm3240g-eval/fb/defconfig +++ b/configs/stm3240g-eval/fb/defconfig @@ -1,10 +1,4 @@ # CONFIG_ARCH_FPU is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -# CONFIG_NX_WRITEONLY is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_CHIP_STM32=y @@ -17,6 +11,10 @@ CONFIG_BUILTIN=y CONFIG_DISABLE_POLL=y CONFIG_DRIVERS_VIDEO=y CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_NSH=y +CONFIG_EXAMPLES_PDCURSES=y +CONFIG_FS_PROCFS=y +CONFIG_GRAPHICS_PDCURSES=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HEAP2_BASE=0x64000000 @@ -29,26 +27,25 @@ CONFIG_LCD_FRAMEBUFFER=y CONFIG_LCD_MAXCONTRAST=1 CONFIG_LCD_NOGETRUN=y CONFIG_LCD=y -CONFIG_LIB_BOARDCTL=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_REGIONS=3 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NFILE_DESCRIPTORS=12 CONFIG_NFILE_STREAMS=12 +CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y CONFIG_NSH_LINELEN=64 CONFIG_NSH_READLINE=y -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_MOUSE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXTK_BORDERCOLOR1=0xad55 -CONFIG_NXTK_BORDERCOLOR2=0x6b4d -CONFIG_NXTK_BORDERCOLOR3=0xdedb +CONFIG_NXFONTS_DISABLE_1BPP=y +CONFIG_NXFONTS_DISABLE_24BPP=y +CONFIG_NXFONTS_DISABLE_2BPP=y +CONFIG_NXFONTS_DISABLE_32BPP=y +CONFIG_NXFONTS_DISABLE_4BPP=y +CONFIG_NXFONTS_DISABLE_8BPP=y +CONFIG_PDCURSES_FONT_6X9=y CONFIG_PREALLOC_MQ_MSGS=8 CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_WDOGS=8 @@ -72,6 +69,6 @@ CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_RXBUFSIZE=128 CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_USART3_TXBUFSIZE=128 -CONFIG_USER_ENTRYPOINT="fb_main" +CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_VIDEO_FB=y CONFIG_WDOG_INTRESERVE=1 diff --git a/configs/stm3240g-eval/include/board.h b/configs/stm3240g-eval/include/board.h index 153dbc415769bde5c8d02a0c03977775a58c4ab9..ab14d860414cb9058c097ac326ee855c0f597ced 100644 --- a/configs/stm3240g-eval/include/board.h +++ b/configs/stm3240g-eval/include/board.h @@ -488,17 +488,6 @@ extern "C" /************************************************************************************ * Public Function Prototypes ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); /************************************************************************************ * Name: stm3240g_lcdclear diff --git a/configs/stm3240g-eval/knxwm/defconfig b/configs/stm3240g-eval/knxwm/defconfig index 12ebe0a3a931514bb6a69da1d0b28e4d86e92cb3..8a33d10f5656d2a8a5d5bf259657b883db31b6a9 100644 --- a/configs/stm3240g-eval/knxwm/defconfig +++ b/configs/stm3240g-eval/knxwm/defconfig @@ -2,6 +2,7 @@ # CONFIG_NX_DISABLE_16BPP is not set # CONFIG_NX_PACKEDMSFIRST is not set # CONFIG_NX_WRITEONLY is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set # CONFIG_NXWM_NXTERM is not set CONFIG_ARCH_BOARD_STM3240G_EVAL=y @@ -63,7 +64,6 @@ CONFIG_NXWIDGETS=y CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y CONFIG_NXWM_HEXCALCULATOR_FONTID=5 CONFIG_NXWM_KEYBOARD=y -CONFIG_NXWM_STARTWINDOW_MQNAME="nxwm" CONFIG_NXWM_TASKBAR_LEFT=y CONFIG_NXWM_TASKBAR_VSPACING=4 CONFIG_NXWM_UNITTEST=y diff --git a/configs/stm3240g-eval/nsh2/defconfig b/configs/stm3240g-eval/nsh2/defconfig index 23a3aea1a87434d7d9a87fa7d957a21298e4d933..692234b06e53656e194f0833948fa478ec3f4847 100644 --- a/configs/stm3240g-eval/nsh2/defconfig +++ b/configs/stm3240g-eval/nsh2/defconfig @@ -1,6 +1,6 @@ # CONFIG_ARCH_FPU is not set # CONFIG_DEV_CONSOLE is not set -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NSH_CONSOLE is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set diff --git a/configs/stm3240g-eval/nxterm/defconfig b/configs/stm3240g-eval/nxterm/defconfig index 55df3d5f112e6a1f51fba14b46ec56045a7b02c4..56a2f4cfed5337a3e1977234675f0310cc716d85 100644 --- a/configs/stm3240g-eval/nxterm/defconfig +++ b/configs/stm3240g-eval/nxterm/defconfig @@ -4,6 +4,7 @@ # CONFIG_NX_DISABLE_16BPP is not set # CONFIG_NX_PACKEDMSFIRST is not set # CONFIG_NX_WRITEONLY is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_BOARD="stm3240g-eval" diff --git a/configs/stm3240g-eval/nxwm/defconfig b/configs/stm3240g-eval/nxwm/defconfig index 8fcecbd82d5ffda9dcf360080749a09f161caa9f..a72b8984d487ea8b87bdf621ef70f6135f347ff7 100644 --- a/configs/stm3240g-eval/nxwm/defconfig +++ b/configs/stm3240g-eval/nxwm/defconfig @@ -1,11 +1,11 @@ # CONFIG_ARCH_FPU is not set -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set # CONFIG_NX_PACKEDMSFIRST is not set # CONFIG_NX_WRITEONLY is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_BOARD="stm3240g-eval" diff --git a/configs/stm3240g-eval/src/stm32_bringup.c b/configs/stm3240g-eval/src/stm32_bringup.c index 373152ffb45b50e1c741b07f6815ba292826ddd0..3fcc402b22a9c2f271db91fee9e7970e2b0e3d6b 100644 --- a/configs/stm3240g-eval/src/stm32_bringup.c +++ b/configs/stm3240g-eval/src/stm32_bringup.c @@ -39,6 +39,7 @@ #include +#include #include #include #include @@ -247,7 +248,6 @@ int stm32_bringup(void) { syslog(LOG_ERR, "ERROR: Failed to instantiate the RTC lower-half driver\n"); - return -ENOMEM; } else { @@ -261,7 +261,6 @@ int stm32_bringup(void) syslog(LOG_ERR, "ERROR: Failed to bind/register the RTC driver: %d\n", ret); - return ret; } } #endif @@ -275,18 +274,19 @@ int stm32_bringup(void) if (!spi) { syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 0\n"); - return -ENODEV; } - - /* Now bind the SPI interface to the M25P64/128 SPI FLASH driver */ - - mtd = m25p_initialize(spi); - if (!mtd) + else { - syslog(LOG_ERR, - "ERROR: Failed to bind SPI port 0 to the SPI FLASH driver\n"); - return -ENODEV; + /* Now bind the SPI interface to the M25P64/128 SPI FLASH driver */ + + mtd = m25p_initialize(spi); + if (!mtd) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SPI port 0 to the SPI FLASH driver\n"); + } } + #warning "Now what are we going to do with this SPI FLASH driver?" #endif @@ -300,38 +300,47 @@ int stm32_bringup(void) syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", CONFIG_NSH_MMCSDSLOTNO); - return -ENODEV; } + else + { + /* Now bind the SDIO interface to the MMC/SD driver */ - /* Now bind the SDIO interface to the MMC/SD driver */ + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + } - ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - return ret; + /* Then let's guess and say that there is a card in the slot. I need + * to check to see if the STM3240G-EVAL board supports a GPIO to + * detect if there is a card in the slot. + */ + + sdio_mediachange(sdio, true); } +#endif - /* Then let's guess and say that there is a card in the slot. I need to check to - * see if the STM3240G-EVAL board supports a GPIO to detect if there is a card in - * the slot. - */ +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ - sdio_mediachange(sdio, true); + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } #endif #ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a thread - * will monitor for USB connection and disconnection events. + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread that will monitor for USB connection and disconnection events. */ ret = stm32_usbhost_initialize(); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return ret; } #endif diff --git a/configs/stm32_tiny/README.txt b/configs/stm32_tiny/README.txt index 71fdfd472ee56a431ed952c5e6c5b5b3d8271743..f52599d0746804a75d618f826829f1acb21e7a36 100644 --- a/configs/stm32_tiny/README.txt +++ b/configs/stm32_tiny/README.txt @@ -11,12 +11,6 @@ is (always ?) bundled with a nRF24L01 wireless communication module. Contents ======== - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - LEDs - PWM - UARTs @@ -24,235 +18,6 @@ Contents - STM32 Tiny -specific Configuration Options - Configurations -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. - -GNU Toolchain Options -===================== - - Toolchain Configurations - ------------------------ - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The Atollic Toolchain, - 3. The devkitARM GNU toolchain, - 4. Raisonance GNU toolchain, or - 5. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the CodeSourcery toolchain for Windows. To use - the Atollic, devkitARM, Raisonance GNU, or NuttX buildroot toolchain, you simply need to - add one of the following configuration options to your .config (or defconfig) - file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : The Atollic toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE=y : Raisonance RIDE7 under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - NOTE: the CodeSourcery (for Windows), Atollic, devkitARM, and Raisonance toolchains are - Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - The CodeSourcery Toolchain (2009q1) - ----------------------------------- - The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - The Atollic "Pro" and "Lite" Toolchain - -------------------------------------- - One problem that I had with the Atollic toolchains is that the provide a gcc.exe - and g++.exe in the same bin/ file as their ARM binaries. If the Atollic bin/ path - appears in your PATH variable before /usr/bin, then you will get the wrong gcc - when you try to build host executables. This will cause to strange, uninterpretable - errors build some host binaries in tools/ when you first make. - - Also, the Atollic toolchains are the only toolchains that have built-in support for - the FPU in these configurations. If you plan to use the Cortex-M4 FPU, you will - need to use the Atollic toolchain for now. See the FPU section below for more - information. - - The Atollic "Lite" Toolchain - ---------------------------- - The free, "Lite" version of the Atollic toolchain does not support C++ nor - does it support ar, nm, objdump, or objdcopy. If you use the Atollic "Lite" - toolchain, you will have to set: - - CONFIG_HAVE_CXX=n - - In order to compile successfully. Otherwise, you will get errors like: - - "C++ Compiler only available in TrueSTUDIO Professional" - - The make may then fail in some of the post link processing because of some of - the other missing tools. The Make.defs file replaces the ar and nm with - the default system x86 tool versions and these seem to work okay. Disable all - of the following to avoid using objcopy: - - CONFIG_RRLOAD_BINARY=n - CONFIG_INTELHEX_BINARY=n - CONFIG_MOTOROLA_SREC=n - CONFIG_RAW_BINARY=n - - devkitARM - --------- - The devkitARM toolchain includes a version of MSYS make. Make sure that the - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/stm32, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by RIDE. - -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh stm32_tiny/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - LEDs ==== diff --git a/configs/stm32_tiny/include/board.h b/configs/stm32_tiny/include/board.h index 30b472ca186214af06de5345624c630ddd3c2fc0..30a53440558efccc4b4fdb2fb9f2b1d6a5f8cbe4 100644 --- a/configs/stm32_tiny/include/board.h +++ b/configs/stm32_tiny/include/board.h @@ -161,39 +161,4 @@ #define LED_ASSERTION 6 /* LED1 + LED2 */ #define LED_PANIC 7 /* LED1 / LED2 blinking */ -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -EXTERN void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/stm32butterfly2/include/board.h b/configs/stm32butterfly2/include/board.h index 05a28cb94b8051c5fe1508f355b8b8c7cd148d2d..c768024a0e0e8db4ebee9ab4e25e6eb1ecda7574 100644 --- a/configs/stm32butterfly2/include/board.h +++ b/configs/stm32butterfly2/include/board.h @@ -164,41 +164,4 @@ # error "CONFIG_STM32_SPI2 is not supported" #endif -/******************************************************************************* - * Public Data - ******************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/******************************************************************************* - * Public Function Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - ******************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_STM32_BUTTERFLY2_INCLUDE_BOARD_H */ diff --git a/configs/stm32f051-discovery/Kconfig b/configs/stm32f051-discovery/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..f79b365f7b49395f2ef0c4dc1646fedfda7ec2c1 --- /dev/null +++ b/configs/stm32f051-discovery/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_STM32F051_DISCOVERY + +endif diff --git a/configs/stm32f0discovery/README.txt b/configs/stm32f051-discovery/README.txt similarity index 100% rename from configs/stm32f0discovery/README.txt rename to configs/stm32f051-discovery/README.txt diff --git a/configs/stm32f0discovery/include/board.h b/configs/stm32f051-discovery/include/board.h similarity index 98% rename from configs/stm32f0discovery/include/board.h rename to configs/stm32f051-discovery/include/board.h index a29d0c95f9dd78e7575338b11758a9fbe6958ed1..412a3e72993d241aa83363dae5d67500a5c9d1e3 100644 --- a/configs/stm32f0discovery/include/board.h +++ b/configs/stm32f051-discovery/include/board.h @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/stm32f0discovery/include/board.h + * configs/stm32f051-discovery/include/board.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __CONFIG_STM32F0DISCOVERY_INCLUDE_BOARD_H -#define __CONFIG_STM32F0DISCOVERY_INCLUDE_BOARD_H +#ifndef __CONFIG_STM32F051_DISCOVERY_INCLUDE_BOARD_H +#define __CONFIG_STM32F051_DISCOVERY_INCLUDE_BOARD_H /************************************************************************************ * Included Files @@ -244,4 +244,4 @@ #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 #define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 -#endif /* __CONFIG_STM32F0DISCOVERY_INCLUDE_BOARD_H */ +#endif /* __CONFIG_STM32F051_DISCOVERY_INCLUDE_BOARD_H */ diff --git a/configs/stm32f0discovery/nsh/defconfig b/configs/stm32f051-discovery/nsh/defconfig similarity index 94% rename from configs/stm32f0discovery/nsh/defconfig rename to configs/stm32f051-discovery/nsh/defconfig index b7bb3c1ccfe63ee3c4d56b2fcd05bfd551924fd5..1fd28ffcd7f49e36c7457104b3e072aaf43e2d34 100644 --- a/configs/stm32f0discovery/nsh/defconfig +++ b/configs/stm32f051-discovery/nsh/defconfig @@ -4,8 +4,8 @@ # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_XD is not set # CONFIG_NSH_DISABLEBG is not set -CONFIG_ARCH_BOARD_STM32F0_DISCOVERY=y -CONFIG_ARCH_BOARD="stm32f0discovery" +CONFIG_ARCH_BOARD_STM32F051_DISCOVERY=y +CONFIG_ARCH_BOARD="stm32f051-discovery" CONFIG_ARCH_CHIP_STM32F0=y CONFIG_ARCH_CHIP_STM32F051R8=y CONFIG_ARCH_STACKDUMP=y diff --git a/configs/stm32f0discovery/scripts/Make.defs b/configs/stm32f051-discovery/scripts/Make.defs similarity index 98% rename from configs/stm32f0discovery/scripts/Make.defs rename to configs/stm32f051-discovery/scripts/Make.defs index 55c03a125fb68d350778ed99ff651f9a981d6d51..f6582afc8afe6e68974e2455f7777c004ed1f31e 100644 --- a/configs/stm32f0discovery/scripts/Make.defs +++ b/configs/stm32f051-discovery/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# configs/stm32f0discovery/scripts/Make.defs +# configs/stm32f051-discovery/scripts/Make.defs # # Copyright (C) 2017 Gregory Nutt. All rights reserved. # Author: Gregory Nutt diff --git a/configs/stm32f0discovery/scripts/flash.ld b/configs/stm32f051-discovery/scripts/flash.ld similarity index 98% rename from configs/stm32f0discovery/scripts/flash.ld rename to configs/stm32f051-discovery/scripts/flash.ld index 2996e3017a76297ce379fabcb354299103210551..7af2a639378bad25a853a019b4772a6546a9fe7f 100644 --- a/configs/stm32f0discovery/scripts/flash.ld +++ b/configs/stm32f051-discovery/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/stm32f0discovery/scripts/flash.ld + * configs/stm32f051-discovery/scripts/flash.ld * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/configs/stm32f0discovery/scripts/gnu-elf.ld b/configs/stm32f051-discovery/scripts/gnu-elf.ld similarity index 98% rename from configs/stm32f0discovery/scripts/gnu-elf.ld rename to configs/stm32f051-discovery/scripts/gnu-elf.ld index 7361e546daa9196ecb0a68064f9fed515cb0ba72..6eec6eca23a1967062c6a1b649dfc17a4005282d 100644 --- a/configs/stm32f0discovery/scripts/gnu-elf.ld +++ b/configs/stm32f051-discovery/scripts/gnu-elf.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/stm32f0discovery/scripts/gnu-elf.ld + * configs/stm32f051-discovery/scripts/gnu-elf.ld * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/configs/stm32f051-discovery/src/.gitignore b/configs/stm32f051-discovery/src/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..726d936e1e3390cc875a1fa5681e3c3988fe3c8b --- /dev/null +++ b/configs/stm32f051-discovery/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/configs/stm32f0discovery/src/Makefile b/configs/stm32f051-discovery/src/Makefile similarity index 98% rename from configs/stm32f0discovery/src/Makefile rename to configs/stm32f051-discovery/src/Makefile index 585d6dce802f2b16b2dadc304a715bcb3d1c7604..24959f597f88ce2d7f8e192f2a6513fe19a9656e 100644 --- a/configs/stm32f0discovery/src/Makefile +++ b/configs/stm32f051-discovery/src/Makefile @@ -1,5 +1,5 @@ ############################################################################ -# configs/stm32f0discovery/src/Makefile +# configs/stm32f051-discovery/src/Makefile # # Copyright (C) 2017 Gregory Nutt. All rights reserved. # Author: Gregory Nutt diff --git a/configs/stm32f0discovery/src/stm32_appinit.c b/configs/stm32f051-discovery/src/stm32_appinit.c similarity index 97% rename from configs/stm32f0discovery/src/stm32_appinit.c rename to configs/stm32f051-discovery/src/stm32_appinit.c index 3a0ae46ab20bac09c4bf5b9620a9fc60258722f3..729fec987c13faf7a632729356dd31ec3c20ae58 100644 --- a/configs/stm32f0discovery/src/stm32_appinit.c +++ b/configs/stm32f051-discovery/src/stm32_appinit.c @@ -1,5 +1,5 @@ /**************************************************************************** - * config/stm32f0discovery/src/stm32_appinit.c + * config/stm32f051-discovery/src/stm32_appinit.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -44,7 +44,7 @@ #include -#include "stm32f0discovery.h" +#include "stm32f051-discovery.h" /**************************************************************************** * Public Functions diff --git a/configs/stm32f0discovery/src/stm32_autoleds.c b/configs/stm32f051-discovery/src/stm32_autoleds.c similarity index 98% rename from configs/stm32f0discovery/src/stm32_autoleds.c rename to configs/stm32f051-discovery/src/stm32_autoleds.c index 1627bf2e2597800932448e9a7857ace696b23da0..529dee5978a40e668155ee2d3b5568a4e927abb0 100644 --- a/configs/stm32f0discovery/src/stm32_autoleds.c +++ b/configs/stm32f051-discovery/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/stm32f0discovery/src/stm32_autoleds.c + * configs/stm32f051-discovery/src/stm32_autoleds.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -48,7 +48,7 @@ #include #include "chip.h" -#include "stm32f0discovery.h" +#include "stm32f051-discovery.h" #ifdef CONFIG_ARCH_LEDS diff --git a/configs/stm32f0discovery/src/stm32_boot.c b/configs/stm32f051-discovery/src/stm32_boot.c similarity index 97% rename from configs/stm32f0discovery/src/stm32_boot.c rename to configs/stm32f051-discovery/src/stm32_boot.c index 5c04acd03fcb460fc5f016f7a0187c5e970f347c..8fac2ab07c3831a4f0cb1087e32727f712805d17 100644 --- a/configs/stm32f0discovery/src/stm32_boot.c +++ b/configs/stm32f051-discovery/src/stm32_boot.c @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/stm32f0discovery/src/stm32f0_boot.c + * configs/stm32f051-discovery/src/stm32f0_boot.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -46,7 +46,7 @@ #include #include "up_arch.h" -#include "stm32f0discovery.h" +#include "stm32f051-discovery.h" /************************************************************************************ * Public Functions diff --git a/configs/stm32f0discovery/src/stm32_bringup.c b/configs/stm32f051-discovery/src/stm32_bringup.c similarity index 97% rename from configs/stm32f0discovery/src/stm32_bringup.c rename to configs/stm32f051-discovery/src/stm32_bringup.c index 61003b54f8ecd949111dabef85a7f28f2fba5e6f..fe0ca8b1d430a5f1b1696114d2c4f62ef2220b06 100644 --- a/configs/stm32f0discovery/src/stm32_bringup.c +++ b/configs/stm32f051-discovery/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * config/stm32f0discovery/src/stm32_bringup.c + * config/stm32f051-discovery/src/stm32_bringup.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -42,7 +42,7 @@ #include #include -#include "stm32f0discovery.h" +#include "stm32f051-discovery.h" /**************************************************************************** * Public Functions diff --git a/configs/stm32f0discovery/src/stm32_buttons.c b/configs/stm32f051-discovery/src/stm32_buttons.c similarity index 98% rename from configs/stm32f0discovery/src/stm32_buttons.c rename to configs/stm32f051-discovery/src/stm32_buttons.c index 1bcc3b5e5499efe42fa6f2d4cf3f6be4e6644397..3a40faf6755d837a13cf01158eed31fc27c0510f 100644 --- a/configs/stm32f0discovery/src/stm32_buttons.c +++ b/configs/stm32f051-discovery/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/stm32f0discovery/src/board_buttons.c + * configs/stm32f051-discovery/src/board_buttons.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -47,7 +47,7 @@ #include #include -#include "stm32f0discovery.h" +#include "stm32f051-discovery.h" #ifdef CONFIG_ARCH_BUTTONS diff --git a/configs/stm32f0discovery/src/stm32_userleds.c b/configs/stm32f051-discovery/src/stm32_userleds.c similarity index 97% rename from configs/stm32f0discovery/src/stm32_userleds.c rename to configs/stm32f051-discovery/src/stm32_userleds.c index 1478c7375ce280e99f3de87de56cd6bb6bf25579..fd9d1520e8a84e77451d6c8b41cd46c9e179593c 100644 --- a/configs/stm32f0discovery/src/stm32_userleds.c +++ b/configs/stm32f051-discovery/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/stm32f0discovery/src/stm32_userleds.c + * configs/stm32f051-discovery/src/stm32_userleds.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -48,7 +48,7 @@ #include "chip.h" #include "stm32.h" -#include "stm32f0discovery.h" +#include "stm32f051-discovery.h" #ifndef CONFIG_ARCH_LEDS diff --git a/configs/stm32f0discovery/src/stm32f0discovery.h b/configs/stm32f051-discovery/src/stm32f051-discovery.h similarity index 95% rename from configs/stm32f0discovery/src/stm32f0discovery.h rename to configs/stm32f051-discovery/src/stm32f051-discovery.h index fca605e006ef7583d6cc1a62f93ecbadbf9775f9..ab5de9425322c8b2405d3f69b5869a62f9ee0519 100644 --- a/configs/stm32f0discovery/src/stm32f0discovery.h +++ b/configs/stm32f051-discovery/src/stm32f051-discovery.h @@ -1,5 +1,5 @@ /**************************************************************************************************** - * configs/stm32f0discovery/src/stm32f0discovery.h + * configs/stm32f051-discovery/src/stm32f051-discovery.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -34,8 +34,8 @@ * ****************************************************************************************************/ -#ifndef __CONFIGS_STM32F0DISCOVERY_SRC_STM32F0DISCOVERY_H -#define __CONFIGS_STM32F0DISCOVERY_SRC_STM32F0DISCOVERY_H +#ifndef __CONFIGS_STM32F051_DISCOVERY_SRC_STM32F051_DISCOVERY_H +#define __CONFIGS_STM32F051_DISCOVERY_SRC_STM32F051_DISCOVERY_H /**************************************************************************************************** * Included Files @@ -132,4 +132,4 @@ int stm32_bringup(void); #endif /* __ASSEMBLY__ */ -#endif /* __CONFIGS_STM32F0DISCOVERY_SRC_STM32F0DISCOVERY_H */ +#endif /* __CONFIGS_STM32F051_DISCOVERY_SRC_STM32F051_DISCOVERY_H */ diff --git a/configs/stm32f072-discovery/Kconfig b/configs/stm32f072-discovery/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..9e42c9b444659faa6f811e26620fd7e6a711ab16 --- /dev/null +++ b/configs/stm32f072-discovery/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_STM32F072_DISCOVERY + +endif diff --git a/configs/stm32f072-discovery/README.txt b/configs/stm32f072-discovery/README.txt new file mode 100644 index 0000000000000000000000000000000000000000..243dee33768b0f684814c941d4e677f91439b8c2 --- /dev/null +++ b/configs/stm32f072-discovery/README.txt @@ -0,0 +1,17 @@ +STATUS +====== + +05/17: The basic NSH configuration is functional and shows that there is + 3-4KB of free heap space. However, attempts to extend this have + failed. I suspect that 8KB of SRAM is insufficient to do much + with the existing NSH configuration. Perhaps some fine tuning + can improve this situation but at this point, I think this board + is only useful for the initial STM32 F0 bring-up, perhaps for + embedded solutions that do not use NSH and for general + experimentation. + + There is also support for the Nucleo boards with the STM32 F072 + and F092 MCUs. Those ports do not suffer from these problems and + seem to work well in fairly complex configurations. Apparently 8KB + is SRAM is not usable but the parts with larger 16KB and 32KB SRAMs + are better matches. diff --git a/configs/stm32f072-discovery/include/board.h b/configs/stm32f072-discovery/include/board.h new file mode 100644 index 0000000000000000000000000000000000000000..93c266dcf6054bbcf9c9a30e96d21f8ffc54b2ff --- /dev/null +++ b/configs/stm32f072-discovery/include/board.h @@ -0,0 +1,251 @@ +/************************************************************************************ + * configs/stm32f072-discovery/include/board.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIG_STM32F072_DISCOVERY_INCLUDE_BOARD_H +#define __CONFIG_STM32F072_DISCOVERY_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* Four different clock sources can be used to drive the system clock (SYSCLK): + * + * - HSI high-speed internal oscillator clock + * Generated from an internal 8 MHz RC oscillator + * - HSE high-speed external oscillator clock + * Normally driven by an external crystal (X3). However, this crystal is not + * fitted on the STM32F0-Discovery board. + * - PLL clock + * - MSI multispeed internal oscillator clock + * The MSI clock signal is generated from an internal RC oscillator. Seven frequency + * ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, + * 2.097 MHz (default value) and 4.194 MHz. + * + * The devices have the following two secondary clock sources + * - LSI low-speed internal RC clock + * Drives the watchdog and RTC. Approximately 37KHz + * - LSE low-speed external oscillator clock + * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. + */ + +#define STM32F0_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ + +#define STM32F0_HSI_FREQUENCY 8000000ul /* Approximately 8MHz */ +#define STM32F0_HSI14_FREQUENCY 14000000ul /* HSI14 for ADC */ +#define STM32F0_HSI48_FREQUENCY 48000000ul /* HSI48 for USB, only some STM32F0xx */ +#define STM32F0_HSE_FREQUENCY STM32F0_BOARD_XTAL +#define STM32F0_LSI_FREQUENCY 40000 /* Approximately 40KHz */ +#define STM32F0_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL Configuration + * + * - PLL source is HSI -> 8MHz input (nominal) + * - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output + * - PLL multipler is 12 -> 48MHz PLL VCO clock output (for USB) + * + * Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz + * + * USB: + * If the USB interface is used in the application, it requires a precise + * 48MHz clock which can be generated from either the (1) the internal + * main PLL with the HSE clock source using an HSE crystal oscillator. In + * this case, the PLL VCO clock (defined by STM32F0_CFGR_PLLMUL) must be + * programmed to output a 96 MHz frequency. This is required to provide a + * 48MHz clock to the (USBCLK = PLLVCO/2). Or (2) by using the internal + * 48MHz oscillator in automatic trimming mode. The synchronization for + * this oscillator can be taken from the USB data stream itself (SOF + * signalization) which allows crystal-less operation. + * SYSCLK + * The system clock is derived from the PLL VCO divided by the output + * division factor. + * Limitations: + * - 96 MHz as PLLVCO when the product is in range 1 (1.8V), + * - 48 MHz as PLLVCO when the product is in range 2 (1.5V), + * - 24 MHz when the product is in range 3 (1.2V). + * - Output division to avoid exceeding 32 MHz as SYSCLK. + * - The minimum input clock frequency for PLL is 2 MHz (when using HSE as + * PLL source). + */ + +#define STM32F0_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ +#define STM32F0_PLLSRC_FREQUENCY (STM32F0_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ +#ifdef CONFIG_STM32F0_USB +# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +#else +# undef STM32F0_CFGR2_PREDIV /* Not used with source HSI/2 */ +# define STM32F0_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +# define STM32F0_PLL_FREQUENCY (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ +#endif + +/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output + * frequency (STM32F0_PLL_FREQUENCY divided by the PLLDIV value). + */ + +#define STM32F0_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ +#define STM32F0_SYSCLK_SWS RCC_CFGR_SWS_PLL +#ifdef CONFIG_STM32F0_USB +# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +#else +# define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ +#endif + +#define STM32F0_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32F0_HCLK_FREQUENCY STM32F0_SYSCLK_FREQUENCY +#define STM32F0_BOARD_HCLK STM32F0_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ + +/* APB1 clock (PCLK1) is HCLK (48MHz) */ + +#define STM32F0_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32F0_PCLK1_FREQUENCY (STM32F0_HCLK_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (48MHz) */ + +#define STM32F0_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32F0_PCLK2_FREQUENCY STM32F0_HCLK_FREQUENCY +#define STM32F0_APB2_CLKIN (STM32F0_PCLK2_FREQUENCY) + +/* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */ + +#define STM32F0_APB1_TIM1_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32F0_APB1_TIM2_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32F0_APB1_TIM3_CLKIN (STM32F0_PCLK1_FREQUENCY) + +#define STM32F0_APB1_TIM6_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32F0_APB1_TIM7_CLKIN (STM32F0_PCLK1_FREQUENCY) + +#define STM32F0_APB1_TIM14_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32F0_APB1_TIM15_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32F0_APB1_TIM16_CLKIN (STM32F0_PCLK1_FREQUENCY) +#define STM32F0_APB1_TIM17_CLKIN (STM32F0_PCLK1_FREQUENCY) + +/* LED definitions ******************************************************************/ +/* The STM32F0-Discovery board has four LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD2 default status is red. LD2 turns to green to indicate that + * communications are in progress between the PC and the ST-LINK/V2. + * LD2 PWR: Red LED indicates that the board is powered. + * + * And two LEDs can be controlled by software: + * + * User LD3: Green LED is a user LED connected to the I/O PB7 of the STM32F072RB + * MCU. + * User LD4: Blue LED is a user LED connected to the I/O PB6 of the STM32F072RB + * MCU. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any + * way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD_U */ +#define BOARD_LED2 1 /* User LD_D */ +#define BOARD_LED3 2 /* User LD_L */ +#define BOARD_LED4 3 /* User LD_R */ +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on board the + * STM32F0-Discovery. The following definitions describe how NuttX controls the LEDs: + * + * SYMBOL Meaning LED state + * LED1 LED2 + * ------------------- ----------------------- -------- -------- + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed OFF Blinking + * LED_IDLE STM32 is is sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 3 + +/* Button definitions ***************************************************************/ +/* The STM32F0-Discovery supports two buttons; only one button is controllable by + * software: + * + * B1 USER: user and wake-up button connected to the I/O PA0 of the STM32F072RB. + * B2 RESET: pushbutton connected to NRST is used to RESET the STM32F072RB. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate Pin Functions **********************************************************/ +/* USART 1 */ + +#define GPIO_USART1_TX GPIO_USART1_TX_1 +#define GPIO_USART1_RX GPIO_USART1_RX_1 + +/* I2C pins definition */ + +#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 +#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 + +#endif /* __CONFIG_STM32F072_DISCOVERY_INCLUDE_BOARD_H */ diff --git a/configs/stm32f072-discovery/nsh/defconfig b/configs/stm32f072-discovery/nsh/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..19cb0914acacd4993739b544725636092ab71216 --- /dev/null +++ b/configs/stm32f072-discovery/nsh/defconfig @@ -0,0 +1,57 @@ +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_XD is not set +# CONFIG_NSH_DISABLEBG is not set +CONFIG_ARCH_BOARD_STM32F072_DISCOVERY=y +CONFIG_ARCH_BOARD="stm32f072-discovery" +CONFIG_ARCH_CHIP_STM32F0=y +CONFIG_ARCH_CHIP_STM32F072RB=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="arm" +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_DEFAULT_SMALL=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POLL=y +CONFIG_EXAMPLES_NSH=y +CONFIG_MAX_TASKS=8 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_SMALL=y +CONFIG_NFILE_DESCRIPTORS=6 +CONFIG_NFILE_STREAMS=6 +CONFIG_NPTHREAD_KEYS=0 +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_MOUNT=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NUNGET_CHARS=0 +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=8192 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32F0_PWR=y +CONFIG_STM32F0_USART1=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_USART1_RXBUFSIZE=32 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART1_TXBUFSIZE=32 +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_USERMAIN_STACKSIZE=1536 +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/stm32f072-discovery/scripts/Make.defs b/configs/stm32f072-discovery/scripts/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..c50f33d2d107cd07471ff65ff006d9b74f6cef0a --- /dev/null +++ b/configs/stm32f072-discovery/scripts/Make.defs @@ -0,0 +1,113 @@ +############################################################################ +# configs/stm32f072-discovery/scripts/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# Alan Carvalho de Assis +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = flash.ld + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/configs/stm32f072-discovery/scripts/flash.ld b/configs/stm32f072-discovery/scripts/flash.ld new file mode 100644 index 0000000000000000000000000000000000000000..09cb1757cdb8c2c9204497220553cbd53c38a180 --- /dev/null +++ b/configs/stm32f072-discovery/scripts/flash.ld @@ -0,0 +1,120 @@ +/**************************************************************************** + * configs/stm32f072-discovery/scripts/flash.ld + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The STM32F072RBT6 has 128KB of FLASH beginning at address 0x0800:0000 and + * 16Kb of SRAM at address 0x20000000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/stm32f072-discovery/scripts/gnu-elf.ld b/configs/stm32f072-discovery/scripts/gnu-elf.ld new file mode 100644 index 0000000000000000000000000000000000000000..5531799534e217b55f35f1008156ab00b0cd39a6 --- /dev/null +++ b/configs/stm32f072-discovery/scripts/gnu-elf.ld @@ -0,0 +1,130 @@ +/**************************************************************************** + * configs/stm32f072-discovery/scripts/gnu-elf.ld + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +SECTIONS +{ + .text 0x00000000 : + { + _stext = . ; + *(.text) + *(.text.*) + *(.gnu.warning) + *(.stub) + *(.glue_7) + *(.glue_7t) + *(.jcr) + + /* C++ support: The .init and .fini sections contain specific logic + * to manage static constructors and destructors. + */ + + *(.gnu.linkonce.t.*) + *(.init) /* Old ABI */ + *(.fini) /* Old ABI */ + _etext = . ; + } + + .rodata : + { + _srodata = . ; + *(.rodata) + *(.rodata1) + *(.rodata.*) + *(.gnu.linkonce.r*) + _erodata = . ; + } + + .data : + { + _sdata = . ; + *(.data) + *(.data1) + *(.data.*) + *(.gnu.linkonce.d*) + _edata = . ; + } + + /* C++ support. For each global and static local C++ object, + * GCC creates a small subroutine to construct the object. Pointers + * to these routines (not the routines themselves) are stored as + * simple, linear arrays in the .ctors section of the object file. + * Similarly, pointers to global/static destructor routines are + * stored in .dtors. + */ + + .ctors : + { + _sctors = . ; + *(.ctors) /* Old ABI: Unallocated */ + *(.init_array) /* New ABI: Allocated */ + _edtors = . ; + } + + .dtors : + { + _sdtors = . ; + *(.dtors) /* Old ABI: Unallocated */ + *(.fini_array) /* New ABI: Allocated */ + _edtors = . ; + } + + .bss : + { + _sbss = . ; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.b*) + *(COMMON) + _ebss = . ; + } + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/stm32f072-discovery/src/.gitignore b/configs/stm32f072-discovery/src/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..726d936e1e3390cc875a1fa5681e3c3988fe3c8b --- /dev/null +++ b/configs/stm32f072-discovery/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/configs/stm32f072-discovery/src/Makefile b/configs/stm32f072-discovery/src/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..b40311548d3edbe323c04ee064cf551d7eaccdca --- /dev/null +++ b/configs/stm32f072-discovery/src/Makefile @@ -0,0 +1,68 @@ +############################################################################ +# configs/stm32f072-discovery/src/Makefile +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# Alan Carvalho de Assis +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32F0_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_SENSORS_QENCODER),y) +CSRCS += stm32_qencoder.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += stm32_appinit.c +endif + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/stm32f072-discovery/src/stm32_appinit.c b/configs/stm32f072-discovery/src/stm32_appinit.c new file mode 100644 index 0000000000000000000000000000000000000000..5c02059cdadfea9663e83b72fb1f226a995eb0e8 --- /dev/null +++ b/configs/stm32f072-discovery/src/stm32_appinit.c @@ -0,0 +1,87 @@ +/**************************************************************************** + * config/stm32f072-discovery/src/stm32_appinit.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "stm32f072-discovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + /* Did we already initialize via board_initialize()? */ + +#ifndef CONFIG_BOARD_INITIALIZE + return stm32_bringup(); +#else + return OK; +#endif +} diff --git a/configs/stm32f072-discovery/src/stm32_autoleds.c b/configs/stm32f072-discovery/src/stm32_autoleds.c new file mode 100644 index 0000000000000000000000000000000000000000..528d0d5f7966b46babfa46e2b6f7d690737486ca --- /dev/null +++ b/configs/stm32f072-discovery/src/stm32_autoleds.c @@ -0,0 +1,137 @@ +/**************************************************************************** + * configs/stm32f072-discovery/src/stm32_autoleds.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "stm32f072-discovery.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on + * board the STM32L-Discovery. The following definitions describe how NuttX + * controls the LEDs: + * + * SYMBOL Meaning LED state + * LED1 LED2 + * ------------------- ----------------------- -------- -------- + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed OFF Blinking + * LED_IDLE STM32 is is sleep mode Not used + */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + stm32f0_configgpio(GPIO_LED1); + stm32f0_configgpio(GPIO_LED2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + bool led1on = false; + bool led2on = false; + + switch (led) + { + case 0: /* LED_STARTED, LED_HEAPALLOCATE, LED_IRQSENABLED */ + break; + + case 1: /* LED_STACKCREATED */ + led1on = true; + break; + + default: + case 2: /* LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ + return; + + case 3: /* LED_PANIC */ + led2on = true; + break; + } + + stm32f0_gpiowrite(GPIO_LED1, led1on); + stm32f0_gpiowrite(GPIO_LED2, led2on); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led != 2) + { + stm32f0_gpiowrite(GPIO_LED1, false); + stm32f0_gpiowrite(GPIO_LED2, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/stm32f072-discovery/src/stm32_boot.c b/configs/stm32f072-discovery/src/stm32_boot.c new file mode 100644 index 0000000000000000000000000000000000000000..4d789466fb71c84ef3b4097350de14b9bef9c363 --- /dev/null +++ b/configs/stm32f072-discovery/src/stm32_boot.c @@ -0,0 +1,95 @@ +/************************************************************************************ + * configs/stm32f072-discovery/src/stm32f0_boot.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_arch.h" +#include "stm32f072-discovery.h" + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32f0_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void stm32f0_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ + /* Perform board-specific initialization here if so configured */ + + (void)stm32_bringup(); +} +#endif + diff --git a/configs/stm32f072-discovery/src/stm32_bringup.c b/configs/stm32f072-discovery/src/stm32_bringup.c new file mode 100644 index 0000000000000000000000000000000000000000..43e0c6aa636f81ce90e5ed5e3852479a2bb0aa8f --- /dev/null +++ b/configs/stm32f072-discovery/src/stm32_bringup.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * config/stm32f072-discovery/src/stm32_bringup.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "stm32f072-discovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/configs/stm32f072-discovery/src/stm32_buttons.c b/configs/stm32f072-discovery/src/stm32_buttons.c new file mode 100644 index 0000000000000000000000000000000000000000..63c373a45506e784128d53f3f468c63ef22ace9c --- /dev/null +++ b/configs/stm32f072-discovery/src/stm32_buttons.c @@ -0,0 +1,162 @@ +/**************************************************************************** + * configs/stm32f072-discovery/src/board_buttons.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32f072-discovery.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM32F3Discovery button. This array is indexed by + * the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. After + * that, board_buttons() may be called to collect the current state of all + * buttons or board_button_irq() may be called to register button interrupt + * handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint8_t board_buttons(void) +{ + uint8_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. + */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/************************************************************************************ + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. After + * that, board_buttons() may be called to collect the current state of all + * buttons or board_button_irq() may be called to register button interrupt + * handlers. + * + * After board_button_initialize() has been called, board_buttons() may be called to + * collect the state of all buttons. board_buttons() returns an 8-bit bit set + * with each bit associated with a button. See the BUTTON_*_BIT + * definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that will + * be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See the + * BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ************************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/configs/stm32f072-discovery/src/stm32_userleds.c b/configs/stm32f072-discovery/src/stm32_userleds.c new file mode 100644 index 0000000000000000000000000000000000000000..ee16360a6da6db902053feaeec8d5c9dc97941e6 --- /dev/null +++ b/configs/stm32f072-discovery/src/stm32_userleds.c @@ -0,0 +1,126 @@ +/**************************************************************************** + * configs/stm32f072-discovery/src/stm32_userleds.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f072-discovery.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + uint32_t ledcfg; + + if (led == BOARD_LED1) + { + ledcfg = GPIO_LED1; + } + else if (led == BOARD_LED2) + { + ledcfg = GPIO_LED2; + } + else if (led == BOARD_LED3) + { + ledcfg = GPIO_LED3; + } + else if (led == BOARD_LED4) + { + ledcfg = GPIO_LED4; + } + else + { + return; + } + + stm32_gpiowrite(ledcfg, ledon); +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + bool ledon; + + ledon = ((ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED1, ledon); + + ledon = ((ledset & BOARD_LED2_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, ledon); + + ledon = ((ledset & BOARD_LED3_BIT) != 0); + stm32_gpiowrite(GPIO_LED3, ledon); + + ledon = ((ledset & BOARD_LED4_BIT) != 0); + stm32_gpiowrite(GPIO_LED4, ledon); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/configs/stm32f072-discovery/src/stm32f072-discovery.h b/configs/stm32f072-discovery/src/stm32f072-discovery.h new file mode 100644 index 0000000000000000000000000000000000000000..22893559b73c3363a9f07fcb2734234aa136c011 --- /dev/null +++ b/configs/stm32f072-discovery/src/stm32f072-discovery.h @@ -0,0 +1,141 @@ +/**************************************************************************************************** + * configs/stm32f072-discovery/src/stm32f072-discovery.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __CONFIGS_STM32F072_DISCOVERY_SRC_STM32F072_DISCOVERY_H +#define __CONFIGS_STM32F072_DISCOVERY_SRC_STM32F072_DISCOVERY_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include +#include +#include + +#include "stm32f0_gpio.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Configuration ************************************************************************************/ +/* How many SPI modules does this chip support? */ + +#if STM32F0_NSPI < 1 +# undef CONFIG_STM32F0_SPI1 +# undef CONFIG_STM32F0_SPI2 +# undef CONFIG_STM32F0_SPI3 +#elif STM32F0_NSPI < 2 +# undef CONFIG_STM32F0_SPI2 +# undef CONFIG_STM32F0_SPI3 +#elif STM32F0_NSPI < 3 +# undef CONFIG_STM32F0_SPI3 +#endif + +/* STM32F0Discovery GPIOs ***************************************************************************/ +/* The STM32F0Discovery board has four LEDs. Two of these are controlled by logic on the board and + * are not available for software control: + * + * LD1 COM: LD2 default status is red. LD2 turns to green to indicate that communications are in + * progress between the PC and the ST-LINK/V2. + * LD2 PWR: Red LED indicates that the board is powered. + * + * And two LEDs can be controlled by software: + * + * User LD_U: Green LED is a user LED connected to the I/O PC6 of the STM32F072 MCU. + * User LD_D: Blue LED is a user LED connected to the I/O PB7 of the STM32F072 MCU. + * User LD_L: Green LED is a user LED connected to the I/O PC8 of the STM32F072 MCU. + * User LD_R: Blue LED is a user LED connected to the I/O PB9 of the STM32F072 MCU. + * + * The other side of the LED connects to ground so high value will illuminate the LED. + */ + +#define GPIO_LED1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \ + GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN6) +#define GPIO_LED2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \ + GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN7) +#define GPIO_LED3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \ + GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN8) +#define GPIO_LED4 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \ + GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN9) + +/* Button definitions *******************************************************************************/ +/* The STM32F0Discovery supports two buttons; only one button is controllable by software: + * + * B1 USER: user and wake-up button connected to the I/O PA0 of the STM32F303VCT6. + * B2 RESET: pushbutton connected to NRST is used to RESET the STM32F303VCT6. + * + * NOTE that EXTI interrupts are configured + */ + +#define MIN_IRQBUTTON BUTTON_USER +#define MAX_IRQBUTTON BUTTON_USER +#define NUM_IRQBUTTONS 1 + +#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTA | GPIO_PIN0) + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public data + ****************************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************************************** + * Public Functions + ****************************************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_STM32F072_DISCOVERY_SRC_STM32F072_DISCOVERY_H */ diff --git a/configs/stm32f103-minimum/Kconfig b/configs/stm32f103-minimum/Kconfig index 142bf16bf238580550010f86c5d25ad4a0b65739..c96e8902fc9a1d33dc9e9e333412e63afbb1acee 100644 --- a/configs/stm32f103-minimum/Kconfig +++ b/configs/stm32f103-minimum/Kconfig @@ -5,6 +5,36 @@ if ARCH_BOARD_STM32F103_MINIMUM +config STM32F103MINIMUM_AT24_BLOCKMOUNT + bool "AT24 Serial EEPROM auto-mount" + default n + depends on NSH_ARCHINIT && STM32_I2C1 && MTD_AT24XX + ---help--- + Automatically initialize the AT24 I2C EEPROM driver when NSH starts. + +choice + prompt "AT24 serial EPPROM configuration" + default STM32F103MINIMUM_AT24_FTL + depends on STM32F103MINIMUM_AT24_BLOCKMOUNT + +config STM32F103MINIMUM_AT24_FTL + bool "Create AT24 block driver" + ---help--- + Create the MTD driver for the AT24 and "wrap" the AT24 as a standard + block driver that could then, for example, be mounted using FAT or + any other file system. Any file system may be used, but there will + be no wear-leveling. + +config STM32F103MINIMUM_AT24_NXFFS + bool "Create AT24 NXFFS file system" + depends on FS_NXFFS + ---help--- + Create the MTD driver for the AT24 and mount the AT24 device as + a wear-leveling, NuttX FLASH file system (NXFFS). The downside of + NXFFS is that it can be very slow. + +endchoice # AT24 serial EPPROM configuration + config STM32F103MINIMUM_FLASH bool "MTD driver for external 4Mbyte W25Q32FV FLASH on SPI1" default n @@ -66,6 +96,6 @@ config STM32F103MINIMUM_FLASH_PART_NAMES config STM32F103MINIMUM_QETIMER int "Timer to use with QE encoder" default 4 - depends on QENCODER + depends on SENSORS_QENCODER endif diff --git a/configs/stm32f103-minimum/README.txt b/configs/stm32f103-minimum/README.txt index 7920009787d9d791946fd3dd2c2de5baeb02af56..b78c0b2ba5b9260105f46d3ca407c975dbcd1253 100644 --- a/configs/stm32f103-minimum/README.txt +++ b/configs/stm32f103-minimum/README.txt @@ -12,6 +12,7 @@ Contents - UARTs - Timer Inputs/Outputs - Using 128KiB of Flash instead of 64KiB + - Nintendo Wii Nunchuck - Quadrature Encoder - SDCard support - SPI NOR Flash @@ -245,6 +246,39 @@ Using 128KiB of Flash instead of 64KiB Now NuttX should start normally. +Nintendo Wii Nunchuck: +====================== + + There is a driver on NuttX to support Nintendo Wii Nunchuck Joystick. If you + want to use it please select these options: + + - Enable the I2C1 at System Type -> STM32 Peripheral Support, it will enable: + + CONFIG_STM32_I2C1=y + + - Enable to Custom board/driver initialization at RTOS Features -> RTOS hooks + + CONFIG_BOARD_INITIALIZE=y + + - Enable the I2C Driver Support at Device Drivers, it will enable this symbol: + + CONFIG_I2C=y + + - Nintendo Wii Nunchuck Joystick at Device Drivers -> [*] Input Device Support + + CONFIG_INPUT=y + CONFIG_INPUT_NUNCHUCK=y + + - Enable the Nunchuck joystick example at Application Configuration -> Examples + + CONFIG_EXAMPLES_NUNCHUCK=y + CONFIG_EXAMPLES_NUNCHUCK_DEVNAME="/dev/nunchuck0" + + You need to connect GND and +3.3V pins from Nunchuck connector to GND and 3.3V + of stm32f103-minimum respectively (Nunchuck also can work connected to 5V, but + I don't recommend it). Connect I2C Clock from Nunchuck to SCK (PB6) and the + I2C Data to SDA (PB7). + Quadrature Encoder: =================== diff --git a/configs/stm32f103-minimum/include/board.h b/configs/stm32f103-minimum/include/board.h index 321d5b40fbae1ceb77f9c084f95b576879d8c643..f71653a4478d0809e49c383e86e9c78a637abd39 100644 --- a/configs/stm32f103-minimum/include/board.h +++ b/configs/stm32f103-minimum/include/board.h @@ -200,41 +200,4 @@ #define RGBLED_BPWMTIMER 4 #define RGBLED_BPWMCHANNEL 4 -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_STM32F103_MINIMUM_BOARD_H */ diff --git a/configs/stm32f103-minimum/src/Makefile b/configs/stm32f103-minimum/src/Makefile index 1101523b7add8e7e6207e2da92be0c575261e645..d2a4afcfbe23865a29f5b7c6aa4c806135b2aedd 100644 --- a/configs/stm32f103-minimum/src/Makefile +++ b/configs/stm32f103-minimum/src/Makefile @@ -85,6 +85,12 @@ ifeq ($(CONFIG_MTD_W25),y) CSRCS += stm32_w25.c endif +ifeq ($(CONFIG_MTD_AT24XX),y) +ifeq ($(CONFIG_STM32_I2C1),y) +CSRCS += stm32_at24.c +endif +endif + ifeq ($(CONFIG_AUDIO_TONE),y) CSRCS += stm32_tone.c endif @@ -101,6 +107,14 @@ ifeq ($(CONFIG_SENSORS_HCSR04),y) CSRCS += stm32_hcsr04.c endif +ifeq ($(CONFIG_LCD_MAX7219),y) + CSRCS += stm32_max7219.c +endif + +ifeq ($(CONFIG_INPUT_NUNCHUCK),y) + CSRCS += stm32_nunchuck.c +endif + ifeq ($(CONFIG_LCD_ST7567),y) CSRCS += stm32_lcd.c endif @@ -129,4 +143,8 @@ ifeq ($(CONFIG_USBDEV),y) CSRCS += stm32_usbdev.c endif +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/stm32f103-minimum/src/stm32_apds9960.c b/configs/stm32f103-minimum/src/stm32_apds9960.c index 1174ebf3ab28a64e4a6a63e27f19475be98f13b0..14045df518d848224add9fc8b6e633b8cb345578 100644 --- a/configs/stm32f103-minimum/src/stm32_apds9960.c +++ b/configs/stm32f103-minimum/src/stm32_apds9960.c @@ -111,8 +111,6 @@ static struct stm32_apds9960config_s g_apds9960config = static int apds9960_irq_attach(FAR struct apds9960_config_s *state, xcpt_t isr, FAR void *arg) { - FAR struct stm32_apds9960config_s *priv = - (FAR struct stm32_apds9960config_s *)state; irqstate_t flags; sninfo("apds9960_irq_attach\n"); diff --git a/configs/stm32f103-minimum/src/stm32_at24.c b/configs/stm32f103-minimum/src/stm32_at24.c new file mode 100644 index 0000000000000000000000000000000000000000..9dca10cf15e4bed8a857196c4cf07b32662ef4f2 --- /dev/null +++ b/configs/stm32f103-minimum/src/stm32_at24.c @@ -0,0 +1,146 @@ +/**************************************************************************** + * config/stm32f103-minimum/src/stm32_at24.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "stm32_i2c.h" +#include "stm32f103_minimum.h" + +#ifdef HAVE_AT24 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_at24_automount + * + * Description: + * Initialize and configure the AT24 serial EEPROM + * + ****************************************************************************/ + +int stm32_at24_automount(int minor) +{ + FAR struct i2c_master_s *i2c; + FAR struct mtd_dev_s *mtd; + static bool initialized = false; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* No.. Get the I2C bus driver */ + + finfo("Initialize I2C%d\n", AT24_I2C_BUS); + i2c = stm32_i2cbus_initialize(AT24_I2C_BUS); + if (!i2c) + { + ferr("ERROR: Failed to initialize I2C%d\n", AT24_I2C_BUS); + return -ENODEV; + } + + /* Now bind the I2C interface to the AT24 I2C EEPROM driver */ + + finfo("Bind the AT24 EEPROM driver to I2C%d\n", AT24_I2C_BUS); + mtd = at24c_initialize(i2c); + if (!mtd) + { + ferr("ERROR: Failed to bind TWI%d to the AT24 EEPROM driver\n", + AT24_I2C_BUS); + return -ENODEV; + } + +#if defined(CONFIG_STM32F103MINIMUM_AT24_FTL) + /* And finally, use the FTL layer to wrap the MTD driver as a block driver */ + + finfo("Initialize the FTL layer to create /dev/mtdblock%d\n", AT24_MINOR); + ret = ftl_initialize(AT24_MINOR, mtd); + if (ret < 0) + { + ferr("ERROR: Failed to initialize the FTL layer: %d\n", ret); + return ret; + } + +#elif defined(CONFIG_STM32F103MINIMUM_AT24_NXFFS) + /* Initialize to provide NXFFS on the MTD interface */ + + finfo("Initialize the NXFFS file system\n"); + ret = nxffs_initialize(mtd); + if (ret < 0) + { + ferr("ERROR: NXFFS initialization failed: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/at24 */ + + finfo("Mount the NXFFS file system at /dev/at24\n"); + ret = mount(NULL, "/mnt/at24", "nxffs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount the NXFFS volume: %d\n", errno); + return ret; + } +#endif + /* Now we are initializeed */ + + initialized = true; + } + + return OK; +} + +#endif /* HAVE_AT24 */ diff --git a/configs/stm32f103-minimum/src/stm32_bringup.c b/configs/stm32f103-minimum/src/stm32_bringup.c index 3794698a466d2f2427d0533871bbbd9296af6131..dec8bea5e1a8157b987ab81c6e0546b51ccf03f1 100644 --- a/configs/stm32f103-minimum/src/stm32_bringup.c +++ b/configs/stm32f103-minimum/src/stm32_bringup.c @@ -73,6 +73,10 @@ # include #endif +#ifdef CONFIG_VIDEO_FB +# include +#endif + #include "stm32f103_minimum.h" /* Conditional logic in stm32f103_minimum.h will determine if certain features @@ -153,6 +157,16 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + #ifdef CONFIG_MMCSD ret = stm32_mmcsd_initialize(MMCSD_MINOR); if (ret < 0) @@ -174,6 +188,17 @@ int stm32_bringup(void) } #endif +#ifdef HAVE_AT24 + /* Initialize the AT24 driver */ + + ret = stm32_at24_automount(AT24_MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_at24_automount failed: %d\n", ret); + return ret; + } +#endif /* HAVE_AT24 */ + #ifdef CONFIG_PWM /* Initialize PWM and register the PWM device. */ @@ -270,6 +295,16 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_INPUT_NUNCHUCK + /* Register the Nunchuck driver */ + + ret = nunchuck_initialize("/dev/nunchuck0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: nunchuck_initialize() failed: %d\n", ret); + } +#endif + #ifdef CONFIG_SENSORS_QENCODER /* Initialize and register the qencoder driver */ diff --git a/configs/stm32f103-minimum/src/stm32_max7219.c b/configs/stm32f103-minimum/src/stm32_max7219.c new file mode 100644 index 0000000000000000000000000000000000000000..f905557afdfb162442b02700ccbca5fda90b248f --- /dev/null +++ b/configs/stm32f103-minimum/src/stm32_max7219.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * config/stm32f103-minimum/src/stm32_max7219.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_spi.h" +#include "stm32f103_minimum.h" + +#ifdef CONFIG_NX_LCDDRIVER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LCD_SPI_PORTNO 1 /* On SPI1 */ + +#ifndef CONFIG_LCD_CONTRAST +# define CONFIG_LCD_CONTRAST 60 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +FAR struct spi_dev_s *g_spidev; +FAR struct lcd_dev_s *g_lcddev; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + g_spidev = stm32_spibus_initialize(LCD_SPI_PORTNO); + + if (!g_spidev) + { + lcderr("ERROR: Failed to initialize SPI port %d\n", LCD_SPI_PORTNO); + return 0; + } + + return 1; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +FAR struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + g_lcddev = max7219_initialize(g_spidev, lcddev); + if (!g_lcddev) + { + lcderr("ERROR: Failed to bind SPI port 1 to LCD %d: %d\n", lcddev); + } + else + { + lcdinfo("SPI port 1 bound to LCD %d\n", lcddev); + + return g_lcddev; + } + + return NULL; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} + +#endif /* CONFIG_NX_LCDDRIVER */ diff --git a/configs/stm32f103-minimum/src/stm32_nunchuck.c b/configs/stm32f103-minimum/src/stm32_nunchuck.c new file mode 100644 index 0000000000000000000000000000000000000000..24eb4825414e76e3fb77391bea3564559491edf5 --- /dev/null +++ b/configs/stm32f103-minimum/src/stm32_nunchuck.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * configs/stm32f4discovery/src/stm32_nunchuck.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32_i2c.h" +#include "stm32f103_minimum.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NUNCHUCK_I2C_PORTNO 1 /* On I2C1 */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nunchuck_initialize + * + * Description: + * Initialize and register the Nunchuck joystick driver + * + ****************************************************************************/ + +int nunchuck_initialize(FAR char *devname) +{ + FAR struct i2c_master_s *i2c; + int ret; + + iinfo("Initializing Wii Nunchuck!\n"); + + /* Initialize I2C */ + + i2c = stm32_i2cbus_initialize(NUNCHUCK_I2C_PORTNO); + if (i2c == NULL) + { + return -ENODEV; + } + + /* Register the joystick device as /dev/nunchuck0 */ + + iinfo("Initialize joystick driver: %s\n", devname); + + ret = nunchuck_register(devname, i2c); + if (ret < 0) + { + ierr("ERROR: nunchuck_register failed: %d\n", ret); + } + + return ret; +} diff --git a/configs/stm32f103-minimum/src/stm32_spi.c b/configs/stm32f103-minimum/src/stm32_spi.c index b678e7063350b167b17aaf759e1ffef8be027aa5..2ae29c9e95b06fddc5a09441082f431bee7b2264 100644 --- a/configs/stm32f103-minimum/src/stm32_spi.c +++ b/configs/stm32f103-minimum/src/stm32_spi.c @@ -86,6 +86,10 @@ void stm32_spidev_initialize(void) (void)stm32_configgpio(GPIO_CS_MFRC522); /* MFRC522 chip select */ #endif +#ifdef CONFIG_LCD_MAX7219 + (void)stm32_configgpio(STM32_LCD_CS); /* MAX7219 chip select */ +#endif + #ifdef CONFIG_LCD_ST7567 (void)stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ #endif @@ -146,6 +150,13 @@ void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, } #endif +#ifdef CONFIG_LCD_MAX7219 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } +#endif + #ifdef CONFIG_LCD_PCD8544 if (devid == SPIDEV_DISPLAY(0)) { diff --git a/configs/stm32f103-minimum/src/stm32_usbmsc.c b/configs/stm32f103-minimum/src/stm32_usbmsc.c new file mode 100644 index 0000000000000000000000000000000000000000..68968bdca36395deb46ecc16c4a135302961bf40 --- /dev/null +++ b/configs/stm32f103-minimum/src/stm32_usbmsc.c @@ -0,0 +1,85 @@ +/**************************************************************************** + * configs/stm32f103-minimum/src/stm32_usbmsc.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Configure and register the STM32 SPI-based MMC/SD block driver. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized in board_app_initialize() (see stm32_appinit.c). + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/configs/stm32f103-minimum/src/stm32f103_minimum.h b/configs/stm32f103-minimum/src/stm32f103_minimum.h index d68712fd8d7144a54269e8009ccd154ecd174671..f3159c7eacee0825be1354f17da754eb70a15294 100644 --- a/configs/stm32f103-minimum/src/stm32f103_minimum.h +++ b/configs/stm32f103-minimum/src/stm32f103_minimum.h @@ -44,6 +44,39 @@ #include #include +#define HAVE_AT24 1 + +/* AT24 Serial EEPROM */ + +#define AT24_I2C_BUS 1 /* AT24C256 connected to I2C1 */ +#define AT24_MINOR 0 + +#if !defined(CONFIG_MTD_AT24XX) || !defined(CONFIG_STM32_I2C1) +# undef HAVE_AT24 +#endif + +/* Can't support AT24 features if mountpoints are disabled or if we were not + * asked to mount the AT25 part + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || \ + !defined(CONFIG_STM32F103MINIMUM_AT24_BLOCKMOUNT) +# undef HAVE_AT24 +#endif + +/* If we are going to mount the AT24, then they user must also have told + * us what to do with it by setting one of these. + */ + +#ifndef CONFIG_FS_NXFFS +# undef CONFIG_STM32F103MINIMUM_AT24_NXFFS +#endif + +#if !defined(CONFIG_STM32F103MINIMUM_AT24_FTL) && \ + !defined(CONFIG_STM32F103MINIMUM_AT24_NXFFS) +# undef HAVE_AT24 +#endif + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -229,6 +262,30 @@ int stm32_apds9960initialize(FAR const char *devpath); void stm32_spidev_initialize(void); +/************************************************************************************ + * Name: stm32_mmcsd_initialize + * + * Description: + * Initializes SPI-based SD card + * + ************************************************************************************/ + +#ifdef CONFIG_MMCSD +int stm32_mmcsd_initialize(int minor); +#endif + +/**************************************************************************** + * Name: nunchuck_initialize + * + * Description: + * Initialize and register the button joystick driver + * + ****************************************************************************/ + +#ifdef CONFIG_INPUT_NUNCHUCK +int nunchuck_initialize(FAR char *devname); +#endif + /************************************************************************************ * Name: stm32_hcsr04_initialize * diff --git a/configs/stm32f334-disco/include/board.h b/configs/stm32f334-disco/include/board.h index 3345942110f76e673a8b12967865d78dee9c6efe..115b02abd482c03970a6a6536a2ab05733ed9ecc 100644 --- a/configs/stm32f334-disco/include/board.h +++ b/configs/stm32f334-disco/include/board.h @@ -211,15 +211,15 @@ #define GPIO_USART2_RX GPIO_USART2_RX_3 /* PB4 */ #define GPIO_USART2_TX GPIO_USART2_TX_3 /* PB3 */ -/* Board configuration for powerled example */ - -/* - Set HRTIM TIMC output 1 on PERIOD - * - Reset HRTIM TIMC output 1 on HRTIM EEV2. - * - HRTIM EEV2 is connected to COMP4 output which works as current limit. - * - COMP4 inverting input is connected to DAC1CH1 output. - * - COMP4 non-inverting input is connceted to current sense resitor (1 Ohm). - * - DAC1CH1 DMA transfer is triggered by HRTIM TIMC events, which is used - * to provide slope compensation +/* Board configuration for powerled example: + * - Set HRTIM TIMC output 1 (PB12) on PERIOD. + * - Reset HRTIM TIMC output 1 on HRTIM EEV2. + * - HRTIM EEV2 is connected to COMP4 output which works as current limit. + * - COMP4 inverting input is connected to DAC1CH1 output. + * - COMP4 non-inverting input (PB1) is connceted to current sense + * resitor (1 Ohm). + * - DAC1CH1 DMA transfer is triggered by HRTIM TIMC events, which is used + * to provide slope compensation. */ #if defined(CONFIG_EXAMPLES_POWERLED) @@ -257,37 +257,36 @@ #endif /* CONFIG_EXAMPLES_POWERLED */ -/**************************************************************************** - * Public Data - ****************************************************************************/ +/* Board configuration for SMPS example: + * PA8 - HRTIM_CHA1 + * PA9 - HRTIM_CHA2 + * PA10 - HRTIM_CHB1 + * PA11 - HRTIM_CHB2 + * VIN - ADC Channel 2 (PA1) + * VOUT - ADC Channel 4 (PA3) + */ -#ifndef __ASSEMBLY__ +#if defined(CONFIG_EXAMPLES_SMPS) -#ifdef __cplusplus -extern "C" -{ -#endif +/* ADC configuration ******************************************************/ -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ +#define ADC1_INJECTED_CHAN 2 +#define ADC1_EXTSEL_VALUE 0 +#define ADC1_SMP2 ADC_SMPR_61p5 +#define ADC1_SMP4 ADC_SMPR_61p5 -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ +/* HRTIM configuration ******************************************************/ -void stm32_boardinitialize(void); +#define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_32 +#define HRTIM_TIMA_MODE HRTIM_MODE_CONT -#ifdef __cplusplus -} -#endif +#define HRTIM_TIMB_PRESCALER HRTIM_PRESCALER_32 +#define HRTIM_TIMB_MODE HRTIM_MODE_CONT + +#define HRTIM_ADC_TRG2 HRTIM_ADCTRG24_AC4 + +/* DMA channels *************************************************************/ + +#endif /* CONFIG_EXAMPLES_SMPS */ -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_STM32F334_DISCO_INCLUDE_BOARD_H */ diff --git a/configs/stm32f334-disco/scripts/ld.script b/configs/stm32f334-disco/scripts/ld.script index 07062e20ff31ed877e59b6f8f9251fc7aa272536..1720345916b09da9d4988c78069aa4fc78d74e28 100644 --- a/configs/stm32f334-disco/scripts/ld.script +++ b/configs/stm32f334-disco/scripts/ld.script @@ -85,6 +85,12 @@ SECTIONS _eronly = ABSOLUTE(.); + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + .data : { _sdata = ABSOLUTE(.); *(.data .data.*) diff --git a/configs/stm32f334-disco/src/Makefile b/configs/stm32f334-disco/src/Makefile index 6b9c2fb3a94e5a508409a3afd918257fa44bd743..37debad10b3186f38f434f92df099cae02e58d12 100644 --- a/configs/stm32f334-disco/src/Makefile +++ b/configs/stm32f334-disco/src/Makefile @@ -72,4 +72,8 @@ ifeq ($(CONFIG_DRIVERS_POWERLED),y) CSRCS += stm32_powerled.c endif +ifeq ($(CONFIG_DRIVERS_SMPS),y) +CSRCS += stm32_smps.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/stm32f334-disco/src/stm32_appinit.c b/configs/stm32f334-disco/src/stm32_appinit.c index 665ea6ae5e2935c957aa1397937037a5115d1527..dc9a5d1ce785c24bf84ca42b7b056e01c247d355 100644 --- a/configs/stm32f334-disco/src/stm32_appinit.c +++ b/configs/stm32f334-disco/src/stm32_appinit.c @@ -96,7 +96,7 @@ int board_app_initialize(uintptr_t arg) { int ret; -#ifndef CONFIG_DRIVERS_POWERLED +#if !defined(CONFIG_DRIVERS_POWERLED) && !defined(CONFIG_DRIVERS_SMPS) #ifdef HAVE_LEDS /* Register the LED driver */ @@ -169,6 +169,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_DRIVERS_SMPS + /* Initialize smps and register the smps driver */ + + ret = stm32_smps_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_smps_setup failed: %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/configs/stm32f334-disco/src/stm32_powerled.c b/configs/stm32f334-disco/src/stm32_powerled.c index 4f6f284e5d43209ab5e437241dd534452434c511..f342e71b0af0d247eb86cf32cd3be535dd5a7822 100644 --- a/configs/stm32f334-disco/src/stm32_powerled.c +++ b/configs/stm32f334-disco/src/stm32_powerled.c @@ -84,23 +84,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* REVISIT: Move to stm32_hrtim.h ? */ - -#define HRTIM_CMP_SET(hrtim, tim, index, cmp) \ - hrtim->hd_ops->cmp_update(hrtim, tim, index, cmp) -#define HRTIM_PER_SET(hrtim, tim, per) \ - hrtim->hd_ops->per_update(hrtim, tim, per) -#define HRTIM_OUTPUTS_ENABLE(hrtim, tim, state) \ - hrtim->hd_ops->outputs_enable(hrtim, tim, state) -#define HRTIM_BURST_CMP_SET(hrtim, cmp) \ - hrtim->hd_ops->burst_cmp_set(hrtim, cmp) -#define HRTIM_BURST_PER_SET(hrtim, per) \ - hrtim->hd_ops->burst_per_set(hrtim, per) -#define HRTIM_BURST_PRE_SET(hrtim, pre) \ - hrtim->hd_ops->burst_pre_set(hrtim, pre) -#define HRTIM_BURST_ENABLE(hrtim, state) \ - hrtim->hd_ops->burst_enable(hrtim, state) - #define DAC_BUFFER_INIT(dac, buffer) \ dac->ad_ops->ao_ioctl(dac, IO_DMABUFFER_INIT, (unsigned long)buffer) @@ -507,9 +490,9 @@ static int powerled_limits_set(FAR struct powerled_dev_s *dev, goto errout; } - if (limits->current > LED_ABSOLUTE_CURRENT_LIMIT_mA) + if (limits->current * 1000 > LED_ABSOLUTE_CURRENT_LIMIT_mA) { - limits->current = LED_ABSOLUTE_CURRENT_LIMIT_mA; + limits->current = (float)LED_ABSOLUTE_CURRENT_LIMIT_mA/1000.0; printf("LED current limiit > LED absoulute current limit." " Set current limit to %d.\n", limits->current); diff --git a/configs/stm32f334-disco/src/stm32_smps.c b/configs/stm32f334-disco/src/stm32_smps.c new file mode 100644 index 0000000000000000000000000000000000000000..952af64c1b15ba5220127084a893d539122e7727 --- /dev/null +++ b/configs/stm32f334-disco/src/stm32_smps.c @@ -0,0 +1,689 @@ +/**************************************************************************** + * configs/stm32f334-disco/src/stm32_smps.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "up_internal.h" +#include "ram_vectors.h" + +#include +#include +#include + +#include "stm32_hrtim.h" +#include "stm32_adc.h" + +#if defined(CONFIG_EXAMPLES_SMPS) && defined(CONFIG_DRIVERS_SMPS) + +#warning "STM32F334-DISCO buck-boost converter example under development!" + +#ifndef CONFIG_ARCH_HIPRI_INTERRUPT +# error CONFIG_ARCH_HIPRI_INTERRUPT is required +#endif + +#ifndef CONFIG_ARCH_RAMVECTORS +# error CONFIG_ARCH_RAMVECTORS is required +#endif + +#ifndef CONFIG_ARCH_IRQPRIO +# error CONFIG_ARCH_IRQPRIO is required +#endif + +#ifndef CONFIG_ARCH_FPU +# warning Set CONFIG_ARCH_FPU for hardware FPU support +#endif + +#if !defined(CONFIG_STM32_HRTIM1) || !defined(CONFIG_HRTIM) +# error "SMPS example requires HRTIM1 support" +#endif + +#if !defined(CONFIG_STM32_ADC1) || !defined(CONFIG_ADC) +# error "SMPS example requires ADC1 support" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* ADC1 channels used in this example */ + +#define ADC1_NCHANNELS 2 + +/* ADC1 injected channels numeration */ + +#define VIN_ADC_INJ_CHANNEL 0 +#define VOUT_ADC_INJ_CHANNEL 1 + +/* Voltage reference for ADC */ + +#define ADC_REF_VOLTAGE ((float)3.3) + +/* ADC resolution */ + +#define ADC_VAL_MAX 4095 + +/* Input voltage convertion ratio - 6.8k/(6.8k + 27k) */ + +#define VIN_RATIO (float)((float)(6800+27000)/(float)6800) + +/* Output voltage convertion ratio - 3.3k/(3.3k + 13.3k) */ + +#define VOUT_RATIO (float)((float)(3300+13300)/(float)3300) + +/* Some absolute limits */ + +#define SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA 250 +#define SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV 15000 +#define SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV 15000 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Current converter mode */ + +enum converter_mode_e +{ + CONVERTER_MODE_BUCK, /* Buck mode operations (V_in > V_out) */ + CONVERTER_MODE_BOOST, /* Boost mode operations (V_in < V_out) */ + CONVERTER_MODE_BUCKBOOST, /* Buck-boost operations (V_in near V_out)*/ +}; + +/* SMPS lower drivers structure */ + +struct smps_lower_dev_s +{ + FAR struct hrtim_dev_s *hrtim; /* PWM generation */ + FAR struct adc_dev_s *adc; /* input and output voltage sense */ + FAR struct comp_dev_s *comp; /* not used in this demo - only as reference */ + FAR struct dac_dev_s *dac; /* not used in this demo - only as reference */ + FAR struct opamp_dev_s *opamp; /* not used in this demo - only as reference */ +}; + +/* Private data for smps */ + +struct smps_priv_s +{ + uint8_t conv_mode; /* Converter mode */ + uint16_t vin_raw; /* Voltage input RAW value */ + uint16_t vout_raw; /* Voltage output RAW value */ + float vin; /* Voltage input real value in V */ + float vout; /* Voltage output real value in V */ + bool running; /* Running flag */ +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +static int smps_setup(FAR struct smps_dev_s *dev); +static int smps_shutdown(FAR struct smps_dev_s *dev); +static int smps_start(FAR struct smps_dev_s *dev); +static int smps_stop(FAR struct smps_dev_s *dev); +static int smps_params_set(FAR struct smps_dev_s *dev, + FAR struct smps_params_s *param); +static int smps_mode_set(FAR struct smps_dev_s *dev, uint8_t mode); +static int smps_limits_set(FAR struct smps_dev_s *dev, + FAR struct smps_limits_s *limits); +static int smps_state_get(FAR struct smps_dev_s *dev, + FAR struct smps_state_s *state); +static int smps_fault_set(FAR struct smps_dev_s *dev, uint8_t fault); +static int smps_fault_get(FAR struct smps_dev_s *dev, + FAR uint8_t *fault); +static int smps_fault_clean(FAR struct smps_dev_s *dev, + uint8_t fault); +static int smps_ioctl(FAR struct smps_dev_s *dev, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct smps_lower_dev_s g_smps_lower; +struct smps_priv_s g_smps_priv; +struct smps_s g_smps; + +struct smps_ops_s g_smps_ops = +{ + .setup = smps_setup, + .shutdown = smps_shutdown, + .start = smps_start, + .stop = smps_stop, + .params_set = smps_params_set, + .mode_set = smps_mode_set, + .limits_set = smps_limits_set, + .fault_set = smps_fault_set, + .state_get = smps_state_get, + .fault_get = smps_fault_get, + .fault_clean = smps_fault_clean, + .ioctl = smps_ioctl +}; + +struct smps_dev_s g_smps_dev = +{ + .ops = &g_smps_ops, + .priv = &g_smps +}; + +/* ADC configuration: + * - Input voltage (V_IN) - ADC1 Channel 2 (PA1) + * - Output voltage (V_OUT) - ADC1 Channel 4 (PA3) + * + * ADC channels configured in injected mode. + * + * Transistors configuration in buck mode: + * - T5 - ON + * - T12 - OFF + * - T4 and T11 - buck operation + * Transistors configuration in boost mode: + * - T4 - ON + * - T11 - OFF + * - T5 and T15 - boost operation + * Transistors configuration in buck-boost mode: + * - T4, T11 - buck operation + * - T5 and T15 - boost operation + * + * HRTIM outputs configuration: + * - T4 -> PA8 -> HRTIM_CHA1 + * - T5 -> PA11 -> HRTIM_CHB2 + * - T11 -> PA9 -> HRTIM_CHA2 + * - T15 -> PA10 -> HRTIM_CHB1 + * + */ + +/* ADC channel list */ + +static const uint8_t g_adc1chan[ADC1_NCHANNELS] = +{ + 2, + 4 +}; + +/* Configurations of pins used by ADC channel */ + +static const uint32_t g_adc1pins[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN2, /* PA1 - VIN */ + GPIO_ADC1_IN4, /* PA3 - VOUT */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int smps_shutdown(FAR struct smps_dev_s *dev) +{ + FAR struct smps_s *smps = (FAR struct smps_s *)dev->priv; + FAR struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + + /* Stop smps if running */ + + if (priv->running == true) + { + smps_stop(dev); + } + + /* Reset smps structure */ + + memset(smps, 0, sizeof(struct smps_s)); + + return OK; +} + +/**************************************************************************** + * Name: smps_setup + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_setup(FAR struct smps_dev_s *dev) +{ + FAR struct smps_lower_dev_s *lower = dev->lower; + FAR struct smps_s *smps = (FAR struct smps_s *)dev->priv; + FAR struct hrtim_dev_s *hrtim = NULL; + FAR struct adc_dev_s *adc = NULL; + + /* Initialize smps structure */ + + smps->opmode = SMPS_OPMODE_INIT; + smps->state.state = SMPS_STATE_INIT; + smps->priv = &g_smps_priv; + + /* Check lower half drivers */ + + hrtim = lower->hrtim; + if (hrtim == NULL) + { + printf("ERROR: failed to get hrtim "); + } + + adc = lower->adc; + if (adc == NULL) + { + printf("ERROR: failed to get ADC lower level interface"); + } + +errout: + return OK; +} + +static int smps_start(FAR struct smps_dev_s *dev) +{ + FAR struct smps_lower_dev_s *lower = dev->lower; + FAR struct stm32_adc_dev_s *stm32_adc = + (FAR struct stm32_adc_dev_s *) lower->adc->ad_priv; + FAR struct smps_s *smps = (FAR struct smps_s *)dev->priv; + FAR struct hrtim_dev_s *hrtim = lower->hrtim; + + /* Stop HRTIM PWM */ + + HRTIM_OUTPUTS_ENABLE(hrtim, HRTIM_OUT_TIMA_CH1, false); + HRTIM_OUTPUTS_ENABLE(hrtim, HRTIM_OUT_TIMA_CH2, false); + + HRTIM_OUTPUTS_ENABLE(hrtim, HRTIM_OUT_TIMB_CH1, false); + HRTIM_OUTPUTS_ENABLE(hrtim, HRTIM_OUT_TIMB_CH2, false); + + /* 1 period is 4us - 100% time */ + + HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMA, 18432); + HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMB, 18432); + + /* ADC trigger on TIMA CMP4 */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMA, HRTIM_CMP4, 10000); + + /* Enable ADC interrupts */ + + stm32_adc->ops->int_en(stm32_adc, ADC_INT_JEOS); +} + +static int smps_stop(FAR struct smps_dev_s *dev) +{ + FAR struct smps_lower_dev_s *lower = dev->lower; + FAR struct smps_s *smps = (FAR struct smps_s *)dev->priv; + FAR struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + FAR struct hrtim_dev_s *hrtim = lower->hrtim; + FAR struct stm32_adc_dev_s *stm32_adc = + (FAR struct stm32_adc_dev_s *) lower->adc->ad_priv; + + /* Disable HRTIM outputs */ + + HRTIM_OUTPUTS_ENABLE(hrtim, HRTIM_OUT_TIMA_CH1, false); + HRTIM_OUTPUTS_ENABLE(hrtim, HRTIM_OUT_TIMA_CH2, false); + + HRTIM_OUTPUTS_ENABLE(hrtim, HRTIM_OUT_TIMB_CH1, false); + HRTIM_OUTPUTS_ENABLE(hrtim, HRTIM_OUT_TIMB_CH2, false); + + /* Disable ADC interrupts */ + + stm32_adc->ops->int_dis(stm32_adc, ADC_INT_JEOS); + + /* Reset running flag */ + + priv->running = false; + + return OK; +} + +static int smps_params_set(FAR struct smps_dev_s *dev, + FAR struct smps_params_s *param) +{ + FAR struct smps_s *smps = (FAR struct smps_s *)dev->priv; + int ret = OK; + + /* Only output voltage */ + + smps->param.v_out = param->v_out; + + /* REVISIT: use current and power parameters ? */ + + if (param->i_out > 0) + { + printf("WARNING: Output current parameters not used in this demo\n"); + } + + if (param->p_out > 0) + { + printf("WARNING: Output power parameters not used in this demo\n"); + } + + return ret; +} + +static int smps_mode_set(FAR struct smps_dev_s *dev, uint8_t mode) +{ + FAR struct smps_s *smps = (FAR struct smps_s *)dev->priv; + int ret = OK; + + /* Only constant voltage mode supported */ + + if (mode == SMPS_OPMODE_CV) + { + smps->opmode = mode; + } + else + { + printf("ERROR: unsupported SMPS mode %d!\n", mode); + ret = ERROR; + goto errout; + } + +errout: + return ret; +} + +static int smps_limits_set(FAR struct smps_dev_s *dev, + FAR struct smps_limits_s *limits) +{ + FAR struct smps_s *smps = (FAR struct smps_s *)dev->priv; + int ret = OK; + + /* Some assertions */ + + if (limits->v_out <= 0) + { + printf("Output voltage limit must be set!\n"); + ret = ERROR; + goto errout; + } + + if (limits->v_in <= 0) + { + printf("Input voltage limit must be set!\n"); + ret = ERROR; + goto errout; + } + + if (limits->i_out <= 0) + { + printf("Output current limit must be set!\n"); + ret = ERROR; + goto errout; + } + + if (limits->v_out * 1000 > SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV) + { + limits->v_out = (float)SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV/1000.0; + printf("SMPS output voltage limiit > SMPS absoulute output voltage limit." + " Set output voltage limit to %d.\n", + limits->v_out); + } + + if (limits->v_in * 1000 > SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV) + { + limits->v_in = (float)SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV/1000.0; + printf("SMPS input voltage limiit > SMPS absoulute input voltage limit." + " Set input voltage limit to %d.\n", + limits->v_in); + } + + if (limits->i_out * 1000 > SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA) + { + limits->i_out = (float)SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA/1000.0; + printf("SMPS output current limiit > SMPS absoulute output current limit." + " Set output current limit to %d.\n", + limits->i_out); + } + + /* Set output voltage limit */ + + smps->limits.v_out = limits->v_out; + + /* Set input voltage limit */ + + smps->limits.v_in = limits->v_in; + + /* Set current limit */ + + smps->limits.i_out = limits->i_out; + + /* Lock limits */ + + smps->limits.lock = true; + +errout: + return ret; +} + +static int smps_state_get(FAR struct smps_dev_s *dev, + FAR struct smps_state_s *state) +{ + FAR struct smps_s *smps = (FAR struct smps_s *)dev->priv; + + /* Copy localy stored feedbacks data to status structure */ + + smps->state.fb.v_in = g_smps_priv.vin; + smps->state.fb.v_out = g_smps_priv.vout; + + /* Return state structure to caller */ + + memcpy(state, &smps->state, sizeof(struct smps_state_s)); + + return OK; +} + +static int smps_fault_set(FAR struct smps_dev_s *dev, uint8_t fault) +{ +#warning "missing logic" + return OK; +} + +static int smps_fault_get(FAR struct smps_dev_s *dev, FAR uint8_t *fault) +{ +#warning "missing logic" + return OK; +} + +static int smps_fault_clean(FAR struct smps_dev_s *dev, uint8_t fault) +{ +#warning "missing logic" + return OK; +} + +static int smps_ioctl(FAR struct smps_dev_s *dev, int cmd, unsigned long arg) +{ +#warning "missing logic" + return OK; +} + +static void adc12_handler(void) +{ + FAR struct smps_lower_dev_s *lower = g_smps_dev.lower; + FAR struct stm32_adc_dev_s *stm32_adc = + (FAR struct stm32_adc_dev_s*)lower->adc->ad_priv; + float ref = ADC_REF_VOLTAGE; + float bit = ADC_VAL_MAX; + uint32_t pending; + + pending = stm32_adc->ops->int_get(stm32_adc); + + if (pending & ADC_INT_JEOC) + { + /* Get raw ADC values */ + + g_smps_priv.vout_raw = stm32_adc->ops->inj_get(stm32_adc, VOUT_ADC_INJ_CHANNEL); + g_smps_priv.vin_raw = stm32_adc->ops->inj_get(stm32_adc, VIN_ADC_INJ_CHANNEL); + + /* Convert raw values to real values */ + + g_smps_priv.vout = (g_smps_priv.vout_raw * ref / bit) * VOUT_RATIO; + g_smps_priv.vin = (g_smps_priv.vin_raw * ref / bit) * VIN_RATIO; + +#warning "missing regulator logic!" + + } + + /* Clear pending */ + + stm32_adc->ops->int_ack(stm32_adc, pending); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_smps_setup + * + * Description: + * Initialize SMPS driver. + * + * This function should be call by board_app_initialize(). + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_smps_setup(void) +{ + FAR struct smps_lower_dev_s *lower = &g_smps_lower; + FAR struct smps_dev_s *smps = &g_smps_dev; + FAR struct hrtim_dev_s *hrtim = NULL; + FAR struct adc_dev_s *adc = NULL; + static bool initialized = false; + int ret = OK; + int i; + + /* Initialize only once */ + + if (!initialized) + { + /* Get the HRTIM interface */ + + hrtim = stm32_hrtiminitialize(); + if (hrtim == NULL) + { + printf("ERROR: Failed to get HRTIM1 interface\n"); + return -ENODEV; + } + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1pins[i]); + } + + /* Get the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1chan, ADC1_NCHANNELS); + if (adc == NULL) + { + printf("ERROR: Failed to get ADC %d interface\n", 1); + return -ENODEV; + } + + /* Initialize SMPS lower driver interfaces */ + + lower->hrtim = hrtim; + lower->adc = adc; + lower->comp = NULL; + lower->dac = NULL; + lower->opamp = NULL; + + /* Attach ADC12 ram vector */ + + ret = up_ramvec_attach(STM32_IRQ_ADC12, adc12_handler); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: up_ramvec_attach failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Set the priority of the ADC12 interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + fprintf(stderr, + "highpri_main: ERROR: up_prioritize_irq failed: %d\n", ret); + ret = EXIT_FAILURE; + goto errout; + } + + up_enable_irq(STM32_IRQ_ADC12); + + /* Setup ADC hardware */ + + adc->ad_ops->ao_setup(adc); + + /* We do not need register character drivers for SMPS lower peripherals. + * All control should be done via SMPS character driver. + */ + + ret = smps_register(CONFIG_EXAMPLES_SMPS_DEVPATH, smps, (void *)lower); + if (ret < 0) + { + printf("ERROR: smps_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + +errout: + return ret; +} + +#endif /* CONFIG_EXAMPLE_SMPS && CONFIG_DRIVERS_SMPS*/ diff --git a/configs/stm32f334-disco/src/stm32f334-disco.h b/configs/stm32f334-disco/src/stm32f334-disco.h index 5dd54481ab2afd3c1ea24eef04b25c43da1d0342..904c8acc10d45673f232f45ba37e92e0f2f90e90 100644 --- a/configs/stm32f334-disco/src/stm32f334-disco.h +++ b/configs/stm32f334-disco/src/stm32f334-disco.h @@ -207,4 +207,16 @@ int stm32_opamp_setup(void); int stm32_powerled_setup(void); #endif +/**************************************************************************** + * Name: stm32_smps_setup + * + * Description: + * Initialize SMPS peripheral for the board. + * + ****************************************************************************/ + +#ifdef CONFIG_DRIVERS_SMPS +int stm32_smps_setup(void); +#endif + #endif /* __CONFIGS_STM32F334_DISCO_SRC_STM32F334_DISCO_H */ diff --git a/configs/stm32f3discovery/Kconfig b/configs/stm32f3discovery/Kconfig index 71e736df11f7abd50c7f6c87fde9721ea4c84f88..c3b95ec62a7cef8b58320e240e9750635c36aba1 100644 --- a/configs/stm32f3discovery/Kconfig +++ b/configs/stm32f3discovery/Kconfig @@ -8,7 +8,7 @@ if ARCH_BOARD_STM32F3_DISCOVERY config STM32F3DISCO_QETIMER int "Timer to use with QE encoder" default 3 - depends on QENCODER + depends on SENSORS_QENCODER config PM_BUTTONS bool "PM Button support" diff --git a/configs/stm32f3discovery/README.txt b/configs/stm32f3discovery/README.txt index 1fcf2c6a6d8d391256c327c2c5fe242f0e0a4a41..8e44b0d350eb212fe79ad6680fa99c16321e805c 100644 --- a/configs/stm32f3discovery/README.txt +++ b/configs/stm32f3discovery/README.txt @@ -7,12 +7,6 @@ STMicro STM32F3Discovery development board. Contents ======== - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - LEDs - Serial Console - FPU @@ -20,235 +14,6 @@ Contents - STM32F3Discovery-specific Configuration Options - Configurations -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. - -GNU Toolchain Options -===================== - - Toolchain Configurations - ------------------------ - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The Atollic Toolchain, - 3. The devkitARM GNU toolchain, - 4. Raisonance GNU toolchain, or - 5. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the CodeSourcery toolchain for Windows. To use - the Atollic, devkitARM, Raisonance GNU, or NuttX buildroot toolchain, you simply need to - add one of the following configuration options to your .config (or defconfig) - file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : The Atollic toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE=y : Raisonance RIDE7 under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - NOTE: the CodeSourcery (for Windows), Atollic, devkitARM, and Raisonance toolchains are - Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - The CodeSourcery Toolchain (2009q1) - ----------------------------------- - The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - The Atollic "Pro" and "Lite" Toolchain - -------------------------------------- - One problem that I had with the Atollic toolchains is that the provide a gcc.exe - and g++.exe in the same bin/ file as their ARM binaries. If the Atollic bin/ path - appears in your PATH variable before /usr/bin, then you will get the wrong gcc - when you try to build host executables. This will cause to strange, uninterpretable - errors build some host binaries in tools/ when you first make. - - Also, the Atollic toolchains are the only toolchains that have built-in support for - the FPU in these configurations. If you plan to use the Cortex-M4 FPU, you will - need to use the Atollic toolchain for now. See the FPU section below for more - information. - - The Atollic "Lite" Toolchain - ---------------------------- - The free, "Lite" version of the Atollic toolchain does not support C++ nor - does it support ar, nm, objdump, or objdcopy. If you use the Atollic "Lite" - toolchain, you will have to set: - - CONFIG_HAVE_CXX=n - - In order to compile successfully. Otherwise, you will get errors like: - - "C++ Compiler only available in TrueSTUDIO Professional" - - The make may then fail in some of the post link processing because of some of - the other missing tools. The Make.defs file replaces the ar and nm with - the default system x86 tool versions and these seem to work okay. Disable all - of the following to avoid using objcopy: - - CONFIG_RRLOAD_BINARY=n - CONFIG_INTELHEX_BINARY=n - CONFIG_MOTOROLA_SREC=n - CONFIG_RAW_BINARY=n - - devkitARM - --------- - The devkitARM toolchain includes a version of MSYS make. Make sure that the - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/stm32, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by RIDE. - -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh STM32F3Discovery/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - LEDs ==== diff --git a/configs/stm32f3discovery/include/board.h b/configs/stm32f3discovery/include/board.h index b7980121b67e85201630e7a10e11fe935813109c..8bb05da807b5800d5e1add6b49d36eeb0b204c15 100644 --- a/configs/stm32f3discovery/include/board.h +++ b/configs/stm32f3discovery/include/board.h @@ -272,41 +272,4 @@ #define GPIO_I2C2_SDA GPIO_I2C2_SDA_1 #endif -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_STM32F3DISCOVERY_INCLUDE_BOARD_H */ diff --git a/configs/stm32f411e-disco/include/board.h b/configs/stm32f411e-disco/include/board.h index a50e2d3a5335c8f59774307c25c084667c9ae028..51215454bdeefed096c85facddfde83fee812f0c 100644 --- a/configs/stm32f411e-disco/include/board.h +++ b/configs/stm32f411e-disco/include/board.h @@ -327,40 +327,4 @@ #define BUTTON_USER_BIT (1 << BUTTON_USER) -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_STM32F411E_DISCO_INCLUDE_BOARD_H */ diff --git a/configs/stm32f429i-disco/README.txt b/configs/stm32f429i-disco/README.txt index 7bfd00c18191674b6bf070b80c4f4eb10aa86231..c2438e4cbc49aaf4a14a3bd0d779d6a182d0e29d 100644 --- a/configs/stm32f429i-disco/README.txt +++ b/configs/stm32f429i-disco/README.txt @@ -25,7 +25,7 @@ NOTE: Includes basic NSH command support with full 8MByte SDRAM + the The NSH configuration / testing that has been done so far was performed by connecting an external RS-232 line driver to pins - PA9 (TX) and PA10 (RX) and configuring UART1 as the NSH console. + PA9 (TX) and PA10 (RX) and configuring USART1 as the NSH console. Refer to the http://www.st.com website for further information about this board (search keyword: 429i-disco) @@ -667,20 +667,47 @@ Where is one of the following: 1. This configuration assumes an SST25VF064C 8Mbyte SPI FLASH is connected to SPI4 on the following Discovery board Pins: - SCK: Port PE2 Board Connector P1, Pin 15 - MOSI: Port PE6 Board Connector P1, Pin 11 - MISO: Port PE5 Board Connector P1, Pin 14 - CS: Port PE4 Board Connector P1, Pin 13 + SCK: Port PE2 Board Connector P1, Pin 15 + MOSI: Port PE6 Board Connector P1, Pin 11 + MISO: Port PE5 Board Connector P1, Pin 14 + CS: Port PE4 Board Connector P1, Pin 13 2. This configuration does have UART1 output enabled and set up as the system logging device. To use this UART, you must add an external RS-232 line driver to the UART1 pins of the DISCO board on PA9 and PA10 of connector P1. - ltdc: - ---- - STM32F429I-DISCO LTDC Framebuffer demo example. See - configs/stm32f429i-disco/ltdc/README.txt for additional information. + fb + -- + + STM32F429I-DISCO LTDC Framebuffer demo example. This is a simple + configuration used for some basic (non-graphic) debug of the framebuffer + character drivers using apps/examples/fb. It simply opens the framebuffer + device and draws concentric rectangles of different colors in the + framebuffer: + + nsh> fb + + Also included is the touchscreen test of apps/examples/touchscreen. This + example will simply open the touchscreen driver then collect and display + touch inputs: + + nsh> tc 1 + tc_main: nsamples: 1 + tc_main: Initializing external touchscreen device + tc_main: Opening /dev/input0 + Sample : + npoints : 1 + Point 1 : + id : 0 + flags : 3c + x : 2296 + y : 2311 + h : 0 + w : 0 + pressure : 1 + Terminating! + nsh> nsh: --- @@ -922,12 +949,20 @@ Where is one of the following: 2015-04-30 Appears to be fully functional. + nx + -- + + This a simple test using the graphic example at apps/example/nx. This + configuration illustrates the use of the LCD with the lower performance + SPI interface. + nxwm ---- This is a special configuration setup for the NxWM window manager UnitTest. NOTES: + 1. The NxWM window manager can be found here: nuttx-code/NxWidgets/nxwm @@ -945,12 +980,15 @@ Where is one of the following: 1. Install the nxwm configuration - $ cd ~/nuttx-code/nuttx/tools - $ ./configure.sh stm32f429i-disco/nxwm + $ cd ~/nuttx-code/nuttx + $ tools/configure.sh -l stm32f429i-disco/nxwm + + When the -l option on configure.sh indicates that you are + configuring for a Linux host build environment. Try + 'tools/configure.sh -h' for other options. 2. Make the build context (only) - $ cd .. $ make context ... @@ -959,8 +997,8 @@ Where is one of the following: $ cd ~/nuttx-code/NxWidgets $ tools/install.sh ~/nuttx-code/apps nxwm Creating symbolic link - - To ~/nuttx-code/NxWidgets/UnitTests/nxwm - - At ~/nuttx-code/apps/external + - To ~/nuttx-code/NxWidgets/UnitTests/nxwm + - At ~/nuttx-code/apps/external 4. Build the NxWidgets library @@ -979,19 +1017,25 @@ Where is one of the following: $ cd ~/nuttx-code/nuttx $ make - 3. Performance is not so good in this example configuration because it - uses the slower SPI interfaces. - STATUS: 17-01-08: There are instabilities in this configuration that make it - not usable on this platform. While the equivalent configuration works - on other platforms, this one does not: The calculator display does - not form properly. There are fails in the NxTerm display, usually around - the point where the display should scroll up. - - Update: With all optimizations disabled, the issue seems to go away. - So this is most likely due to using high levels of optimization with a - bleeding edge GCC toolchain. + not usable on this platform. While the equivalent configuration works + on other platforms, this one does not: The calculator display does + not form properly. There are fails in the NxTerm display, usually + around the point where the display should scroll up. + + Update: With all optimizations disabled, the issue seems to go away. + So this is most likely due to using high levels of optimization with a + bleeding edge GCC toolchain. + 17-11-15: The original configuration used the slower SPI LCD interface. + The configuration was converted to use the high performance LTDC frame + buffer interface. Performance is now excellent and I see none of the + instabilities mentioned above even at high levels of optimization. + + The difficulty that I experienced was touching the tiny icons on the + menus. The touscreen controller (along with my fat fingers) does not + appear to have sufficient precision to work in this way. Larger icons + would likely make the interface easier to use. usbnsh: ------ diff --git a/configs/stm32f429i-disco/ltdc/README.txt b/configs/stm32f429i-disco/fb/README.txt similarity index 63% rename from configs/stm32f429i-disco/ltdc/README.txt rename to configs/stm32f429i-disco/fb/README.txt index 4e07cea392567dd81072b29b84f13aaa363989b9..33d1530e57087b72abed63888cef8b51cdcb9f63 100644 --- a/configs/stm32f429i-disco/ltdc/README.txt +++ b/configs/stm32f429i-disco/fb/README.txt @@ -4,23 +4,25 @@ README.txt STM32F429I-DISCO LTDC Framebuffer demo example Configure and build ------------------------------------------------ +------------------- + cd tools -./configure -a stm32f429i-disco/ltdc +./configure -a stm32f429i-disco/fb cd .. make Note! In the current implementation the DMA2D driver only supports clut pixel format -if the LTDC driver it does. Otherwise it will not be compatible with the nx -framework. If CONFIG_FB_CMAP is configured, nx expects that any pixel format +if the LTDC driver it does. Otherwise it will not be compatible with the NX +framework. If CONFIG_FB_CMAP is configured, NX expects that any pixel format supports color lookup tables. This is also the case for non CLUT formats e.g. -FB_FMT_RGB16_565. This may result in wrong color representation by nx if the +FB_FMT_RGB16_565. This may result in wrong color representation by NX if the pixel format is unequal to FB_FMT_RGB8. On the other hand layers with CLUT pixel format are not supported by the DMA2D controller, in the case they will be used as destination layer for the following operations: + - blit - blend - fillarea @@ -29,21 +31,23 @@ To enable clut support in both LTDC and DMA2D driver the following configurations are valid: 1. + - Enable LTDC_INTERFACE and LAYER1/LAYER2 - Layer1 FB_FMT_RGB8 - Layer2 any non clut format But Layer2 can only be used as destination layer for dma2d operations above. -This configuration is not compatibly to nx because LAYER2 will be referenced +This configuration is not compatibly to NX because LAYER2 will be referenced by up_fbgetvplane and is an invalid CLUT pixel format. 2. + - Enable LTDC_INTERFACE and LAYER1/LAYER2 - Layer2 FB_FMT_RGB8 - Layer1 any non clut format But Layer1 can only be used as destination layer for dma2d operations above. -This configuration should be compatibly to nx because LAYER2 will be referenced +This configuration should be compatibly to NX because LAYER2 will be referenced by up_fbgetvplane and is an valid CLUT pixel format. All other non clut configuration work fine. @@ -54,17 +58,17 @@ specific configuration. Loading ------------------------------------------------ +------- + st-flash write nuttx.bin 0x8000000 Executing ------------------------------------------------ -The ltdc is initialized during boot up. -Interaction with NSH is via the serial console at 115200 8N1 baud. -From the nsh comandline execute one (or both) of the examples: -- nx (default nx example) -- ltdc (trivial ltdc interface test) - -Note! The ltdc example ends in an infinite loop. To get control of the nsh -start this example in the background with 'ltdc &'. +--------- + +The ltdc is initialized during boot up. Interaction with NSH is via the serial +console at 115200 8N1 baud. From the nsh comandline execute the fb example: + + nsh> fb + +The test will put a pattern of concentric squares in the framebuffer and terminate. diff --git a/configs/stm32f429i-disco/ltdc/defconfig b/configs/stm32f429i-disco/fb/defconfig similarity index 80% rename from configs/stm32f429i-disco/ltdc/defconfig rename to configs/stm32f429i-disco/fb/defconfig index da7d47325fd21706007a5ed4f5ec3ad945e67a05..48f7668b2eb56fcfc5233a625aad0c2378834683 100644 --- a/configs/stm32f429i-disco/ltdc/defconfig +++ b/configs/stm32f429i-disco/fb/defconfig @@ -1,5 +1,4 @@ # CONFIG_ARCH_FPU is not set -# CONFIG_NX_DISABLE_16BPP is not set # CONFIG_STM32_DMA2D_RGB888 is not set # CONFIG_STM32_FLASH_PREFETCH is not set CONFIG_ARCH_BOARD_STM32F429I_DISCO=y @@ -10,23 +9,23 @@ CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH="arm" CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y -CONFIG_BOARD_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_DEBUG_CUSTOMOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DISABLE_POLL=y -CONFIG_EXAMPLES_LTDC=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y CONFIG_EXAMPLES_NSH=y -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_EXAMPLES_NX=y -CONFIG_FS_PROCFS_REGISTER=y +CONFIG_EXAMPLES_TOUCHSCREEN=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HEAP2_BASE=0xD0000000 CONFIG_HEAP2_SIZE=8081408 +CONFIG_INPUT_STMPE811=y +CONFIG_INPUT=y CONFIG_INTELHEX_BINARY=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 @@ -34,13 +33,11 @@ CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 CONFIG_NSH_READLINE=y -CONFIG_NX_BLOCKING=y -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_WDOGS=4 @@ -48,19 +45,20 @@ CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SDCLONE_DISABLE=y CONFIG_SPI_CMDDATA=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_CCM_PROCFS=y +CONFIG_START_DAY=15 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2017 CONFIG_STM32_CCMEXCLUDE=y CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA2D_NLAYERS=4 +CONFIG_STM32_DMA2D_NLAYERS=1 CONFIG_STM32_DMA2D=y CONFIG_STM32_FSMC_SRAM=y CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C3=y CONFIG_STM32_JTAG_SW_ENABLE=y CONFIG_STM32_LTDC_FB_BASE=0xD07B5000 CONFIG_STM32_LTDC_FB_SIZE=307200 @@ -70,7 +68,12 @@ CONFIG_STM32_PWR=y CONFIG_STM32_SPI5=y CONFIG_STM32_USART1=y CONFIG_STM32F429I_DISCO_ILI9341=y +CONFIG_STMPE811_ACTIVELOW=y +CONFIG_STMPE811_EDGE=y +CONFIG_STMPE811_THRESHX=39 +CONFIG_STMPE811_THRESHY=51 CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_VIDEO_FB=y CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/stm32f429i-disco/ide/ltcd/uvision/README.txt b/configs/stm32f429i-disco/ide/ltcd/uvision/README.txt deleted file mode 100644 index 131dc8dbc65f997f0195c481b860afbe309b713c..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/ltcd/uvision/README.txt +++ /dev/null @@ -1,7 +0,0 @@ -README -====== - -These projects are generated by nuttx/tools/ide_exporter.py with -configuration stm32f429i-disco/ltcd. You need you need to rebuild this -configuration first time to make sure some auto-generated files are -generated correctly before using the IDE diff --git a/configs/stm32f429i-disco/ide/ltcd/uvision/libapps.uvproj b/configs/stm32f429i-disco/ide/ltcd/uvision/libapps.uvproj deleted file mode 100644 index 60f83b361e517713262156b15a2728bdc6a3a62f..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/ltcd/uvision/libapps.uvproj +++ /dev/null @@ -1,473 +0,0 @@ - - - 1.1 -
              ### uVision Project, (C) Keil Software
              - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M4 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE - - - - 5125 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libapps\Obj\ - apps - 0 - 1 - 1 - 1 - 0 - .\libapps\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M4" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../../apps/nshlib;../../../../../../apps/system/readline;../../../../../include;../../../../../../apps/builtin;../../../../../../apps/examples/nsh;../../../../../../apps/examples/nx;../../../../../../apps/examples/ltdc;../../../../../../apps/platform - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../../apps/nshlib;../../../../../../apps/system/readline;../../../../../include;../../../../../../apps/builtin;../../../../../../apps/examples/nsh;../../../../../../apps/examples/nx;../../../../../../apps/examples/ltdc;../../../../../../apps/platform - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - apps - - - builtin_forindex.c - 1 - ../../../../../../apps/builtin/builtin_forindex.c - - - builtin_list.c - 1 - ../../../../../../apps/builtin/builtin_list.c - - - exec_builtin.c - 1 - ../../../../../../apps/builtin/exec_builtin.c - - - dma2d.c - 1 - ../../../../../../apps/examples/ltdc/dma2d.c - - - ltdc_main.c - 1 - ../../../../../../apps/examples/ltdc/ltdc_main.c - - - nsh_main.c - 1 - ../../../../../../apps/examples/nsh/nsh_main.c - - - nx_events.c - 1 - ../../../../../../apps/examples/nx/nx_events.c - - - nx_kbdin.c - 1 - ../../../../../../apps/examples/nx/nx_kbdin.c - - - nx_main.c - 1 - ../../../../../../apps/examples/nx/nx_main.c - - - nsh_init.c - 1 - ../../../../../../apps/nshlib/nsh_init.c - - - nsh_parse.c - 1 - ../../../../../../apps/nshlib/nsh_parse.c - - - nsh_console.c - 1 - ../../../../../../apps/nshlib/nsh_console.c - - - nsh_script.c - 1 - ../../../../../../apps/nshlib/nsh_script.c - - - nsh_command.c - 1 - ../../../../../../apps/nshlib/nsh_command.c - - - nsh_fscmds.c - 1 - ../../../../../../apps/nshlib/nsh_fscmds.c - - - nsh_ddcmd.c - 1 - ../../../../../../apps/nshlib/nsh_ddcmd.c - - - nsh_proccmds.c - 1 - ../../../../../../apps/nshlib/nsh_proccmds.c - - - nsh_mmcmds.c - 1 - ../../../../../../apps/nshlib/nsh_mmcmds.c - - - nsh_timcmds.c - 1 - ../../../../../../apps/nshlib/nsh_timcmds.c - - - nsh_envcmds.c - 1 - ../../../../../../apps/nshlib/nsh_envcmds.c - - - nsh_syscmds.c - 1 - ../../../../../../apps/nshlib/nsh_syscmds.c - - - nsh_dbgcmds.c - 1 - ../../../../../../apps/nshlib/nsh_dbgcmds.c - - - nsh_session.c - 1 - ../../../../../../apps/nshlib/nsh_session.c - - - nsh_fsutils.c - 1 - ../../../../../../apps/nshlib/nsh_fsutils.c - - - nsh_builtin.c - 1 - ../../../../../../apps/nshlib/nsh_builtin.c - - - nsh_mntcmds.c - 1 - ../../../../../../apps/nshlib/nsh_mntcmds.c - - - nsh_consolemain.c - 1 - ../../../../../../apps/nshlib/nsh_consolemain.c - - - nsh_test.c - 1 - ../../../../../../apps/nshlib/nsh_test.c - - - stm32_cxxinitialize.c - 1 - ../../../../../../apps/platform/board/stm32_cxxinitialize.c - - - readline_common.c - 1 - ../../../../../../apps/system/readline/readline_common.c - - - readline.c - 1 - ../../../../../../apps/system/readline/readline.c - - - - - - -               diff --git a/configs/stm32f429i-disco/ide/ltcd/uvision/libarch.uvproj b/configs/stm32f429i-disco/ide/ltcd/uvision/libarch.uvproj deleted file mode 100644 index 05b2e94eb9d72d39c8d9b760a3fd4fc1f287b7ed..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/ltcd/uvision/libarch.uvproj +++ /dev/null @@ -1,823 +0,0 @@ - - - 1.1 -
              ### uVision Project, (C) Keil Software
              - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M4 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE - - - - 5125 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libarch\Obj\ - arch - 0 - 1 - 1 - 1 - 0 - .\libarch\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M4" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../arch/arm/src/chip;../../../../../arch/arm/src;../../../../../arch/arm/src/armv7-m;../../../../../sched;../../../../../arch/arm/src/common;../../../../../include - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../arch/arm/src/chip;../../../../../arch/arm/src;../../../../../arch/arm/src/armv7-m;../../../../../sched;../../../../../arch/arm/src/common;../../../../../include - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - src - - - up_saveusercontext.S - 1 - ../../../../../arch/arm/src/armv7-m/gnu/up_saveusercontext.S - - - 2 - 0 - 0 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - 11 - - - 1 - - - - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 0 - 2 - - - __ASSEMBLY__ - - ../../../../../arch/arm/src/chip;../../../../../arch/arm/src;../../../../../arch/arm/src/armv7-m;../../../../../sched;../../../../../arch/arm/src/common;../../../../../include - - - - - - - up_fullcontextrestore.S - 1 - ../../../../../arch/arm/src/armv7-m/gnu/up_fullcontextrestore.S - - - 2 - 0 - 0 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - 11 - - - 1 - - - - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 0 - 2 - - - __ASSEMBLY__ - - ../../../../../arch/arm/src/chip;../../../../../arch/arm/src;../../../../../arch/arm/src/armv7-m;../../../../../sched;../../../../../arch/arm/src/common;../../../../../include - - - - - - - up_switchcontext.S - 1 - ../../../../../arch/arm/src/armv7-m/gnu/up_switchcontext.S - - - 2 - 0 - 0 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - 11 - - - 1 - - - - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 0 - 2 - - - __ASSEMBLY__ - - ../../../../../arch/arm/src/chip;../../../../../arch/arm/src;../../../../../arch/arm/src/armv7-m;../../../../../sched;../../../../../arch/arm/src/common;../../../../../include - - - - - - - up_testset.S - 1 - ../../../../../arch/arm/src/armv7-m/gnu/up_testset.S - - - 2 - 0 - 0 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - 11 - - - 1 - - - - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 0 - 2 - - - __ASSEMBLY__ - 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- - stm32_exti_gpio.c - 1 - ../../../../../arch/arm/src/chip/stm32_exti_gpio.c - - - stm32_flash.c - 1 - ../../../../../arch/arm/src/chip/stm32_flash.c - - - stm32_irq.c - 1 - ../../../../../arch/arm/src/chip/stm32_irq.c - - - stm32_dma.c - 1 - ../../../../../arch/arm/src/chip/stm32_dma.c - - - stm32_lowputc.c - 1 - ../../../../../arch/arm/src/chip/stm32_lowputc.c - - - stm32_serial.c - 1 - ../../../../../arch/arm/src/chip/stm32_serial.c - - - stm32_spi.c - 1 - ../../../../../arch/arm/src/chip/stm32_spi.c - - - stm32_sdio.c - 1 - ../../../../../arch/arm/src/chip/stm32_sdio.c - - - stm32_tim.c - 1 - ../../../../../arch/arm/src/chip/stm32_tim.c - - - stm32_waste.c - 1 - ../../../../../arch/arm/src/chip/stm32_waste.c - - - stm32_ccm.c - 1 - ../../../../../arch/arm/src/chip/stm32_ccm.c - - - stm32_uid.c - 1 - ../../../../../arch/arm/src/chip/stm32_uid.c - - - stm32_capture.c - 1 - ../../../../../arch/arm/src/chip/stm32_capture.c - - - stm32_timerisr.c - 1 - ../../../../../arch/arm/src/chip/stm32_timerisr.c - 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1 - ../../../../../arch/arm/src/armv7-m/up_blocktask.c - - - up_copyfullstate.c - 1 - ../../../../../arch/arm/src/armv7-m/up_copyfullstate.c - - - up_createstack.c - 1 - ../../../../../arch/arm/src/common/up_createstack.c - - - up_mdelay.c - 1 - ../../../../../arch/arm/src/common/up_mdelay.c - - - up_udelay.c - 1 - ../../../../../arch/arm/src/common/up_udelay.c - - - up_exit.c - 1 - ../../../../../arch/arm/src/common/up_exit.c - - - up_initialize.c - 1 - ../../../../../arch/arm/src/common/up_initialize.c - - - up_initialstate.c - 1 - ../../../../../arch/arm/src/armv7-m/up_initialstate.c - - - up_interruptcontext.c - 1 - ../../../../../arch/arm/src/common/up_interruptcontext.c - - - up_memfault.c - 1 - ../../../../../arch/arm/src/armv7-m/up_memfault.c - - - up_modifyreg8.c - 1 - ../../../../../arch/arm/src/common/up_modifyreg8.c - - - up_modifyreg16.c - 1 - ../../../../../arch/arm/src/common/up_modifyreg16.c - - - up_modifyreg32.c - 1 - ../../../../../arch/arm/src/common/up_modifyreg32.c - - - up_releasepending.c - 1 - ../../../../../arch/arm/src/armv7-m/up_releasepending.c - - - up_releasestack.c - 1 - ../../../../../arch/arm/src/common/up_releasestack.c - - - up_reprioritizertr.c - 1 - ../../../../../arch/arm/src/armv7-m/up_reprioritizertr.c - - - up_schedulesigaction.c - 1 - ../../../../../arch/arm/src/armv7-m/up_schedulesigaction.c - - - up_sigdeliver.c - 1 - ../../../../../arch/arm/src/armv7-m/up_sigdeliver.c - - - up_stackframe.c - 1 - ../../../../../arch/arm/src/common/up_stackframe.c - - - up_systemreset.c - 1 - ../../../../../arch/arm/src/armv7-m/up_systemreset.c - - - up_unblocktask.c - 1 - ../../../../../arch/arm/src/armv7-m/up_unblocktask.c - - - up_usestack.c - 1 - ../../../../../arch/arm/src/common/up_usestack.c - - - up_doirq.c - 1 - ../../../../../arch/arm/src/armv7-m/up_doirq.c - - - up_hardfault.c - 1 - ../../../../../arch/arm/src/armv7-m/up_hardfault.c - - - up_svcall.c - 1 - ../../../../../arch/arm/src/armv7-m/up_svcall.c - - - up_vfork.c - 1 - ../../../../../arch/arm/src/common/up_vfork.c - - - - - - -               diff --git a/configs/stm32f429i-disco/ide/ltcd/uvision/libbinfmt.uvproj b/configs/stm32f429i-disco/ide/ltcd/uvision/libbinfmt.uvproj deleted file mode 100644 index 0fd3774bb6dfb4c8a87a2b8616911be93877f7b0..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/ltcd/uvision/libbinfmt.uvproj +++ /dev/null @@ -1,378 +0,0 @@ - - - 1.1 -
              ### uVision Project, (C) Keil Software
              - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M4 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE - - - - 5125 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libbinfmt\Obj\ - binfmt - 0 - 1 - 1 - 1 - 0 - .\libbinfmt\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M4" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../include;../../../../../sched;../../../../../binfmt - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../include;../../../../../sched;../../../../../binfmt - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - binfmt - - - binfmt_globals.c - 1 - ../../../../../binfmt/binfmt_globals.c - - - binfmt_register.c - 1 - ../../../../../binfmt/binfmt_register.c - - - binfmt_unregister.c - 1 - ../../../../../binfmt/binfmt_unregister.c - - - binfmt_loadmodule.c - 1 - ../../../../../binfmt/binfmt_loadmodule.c - - - binfmt_unloadmodule.c - 1 - ../../../../../binfmt/binfmt_unloadmodule.c - - - binfmt_execmodule.c - 1 - ../../../../../binfmt/binfmt_execmodule.c - - - binfmt_exec.c - 1 - ../../../../../binfmt/binfmt_exec.c - - - binfmt_copyargv.c - 1 - ../../../../../binfmt/binfmt_copyargv.c - - - binfmt_dumpmodule.c - 1 - ../../../../../binfmt/binfmt_dumpmodule.c - - - builtin.c - 1 - ../../../../../binfmt/builtin.c - - - libbuiltin_getname.c - 1 - ../../../../../binfmt/libbuiltin/libbuiltin_getname.c - - - libbuiltin_isavail.c - 1 - ../../../../../binfmt/libbuiltin/libbuiltin_isavail.c - - - - - - -               diff --git a/configs/stm32f429i-disco/ide/ltcd/uvision/libboard.uvproj b/configs/stm32f429i-disco/ide/ltcd/uvision/libboard.uvproj deleted file mode 100644 index 0d807025dff446efb7e1887e7a6678f9c311bb08..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/ltcd/uvision/libboard.uvproj +++ /dev/null @@ -1,358 +0,0 @@ - - - 1.1 -
              ### uVision Project, (C) Keil Software
              - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M4 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE - - - - 5125 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libboard\Obj\ - board - 0 - 1 - 1 - 1 - 0 - .\libboard\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M4" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../include;../../../../../arch/arm/src/board;../../../../../arch/arm/src/armv7-m;../../../../../sched;../../../../../arch/arm/src/common;../../../../../arch/arm/src/chip - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../include;../../../../../arch/arm/src/board;../../../../../arch/arm/src/armv7-m;../../../../../sched;../../../../../arch/arm/src/common;../../../../../arch/arm/src/chip - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - board - - - stm32_boot.c - 1 - ../../../../../arch/arm/src/board/stm32_boot.c - - - stm32_spi.c - 1 - ../../../../../arch/arm/src/board/stm32_spi.c - - - stm32_autoleds.c - 1 - ../../../../../arch/arm/src/board/stm32_autoleds.c - - - stm32_buttons.c - 1 - ../../../../../arch/arm/src/board/stm32_buttons.c - - - stm32_appinit.c - 1 - ../../../../../arch/arm/src/board/stm32_appinit.c - - - stm32_extmem.c - 1 - ../../../../../arch/arm/src/board/stm32_extmem.c - - - stm32_ili93414ws.c - 1 - ../../../../../arch/arm/src/board/stm32_ili93414ws.c - - - stm32_lcd.c - 1 - ../../../../../arch/arm/src/board/stm32_lcd.c - - - - - - -               diff --git a/configs/stm32f429i-disco/ide/ltcd/uvision/libc.uvproj b/configs/stm32f429i-disco/ide/ltcd/uvision/libc.uvproj deleted file mode 100644 index 97ded008652a96d12bfd9851e94ce222c78e3175..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/ltcd/uvision/libc.uvproj +++ /dev/null @@ -1,1528 +0,0 @@ - - - 1.1 -
              ### uVision Project, (C) Keil Software
              - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M4 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE - - - - 5125 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libc\Obj\ - c - 0 - 1 - 1 - 1 - 0 - .\libc\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M4" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../libc;../../../../../include - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../libc;../../../../../include - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - libc - - - lib_readdirr.c - 1 - ../../../../../libc/dirent/lib_readdirr.c - - - lib_telldir.c - 1 - ../../../../../libc/dirent/lib_telldir.c - - - lib_fixedmath.c - 1 - ../../../../../libc/fixedmath/lib_fixedmath.c - - - lib_b16sin.c - 1 - ../../../../../libc/fixedmath/lib_b16sin.c - - - lib_b16cos.c - 1 - ../../../../../libc/fixedmath/lib_b16cos.c - - - lib_b16atan2.c - 1 - ../../../../../libc/fixedmath/lib_b16atan2.c - - - lib_basename.c - 1 - ../../../../../libc/libgen/lib_basename.c - - - lib_dirname.c - 1 - ../../../../../libc/libgen/lib_dirname.c - - - lib_stream.c - 1 - ../../../../../libc/misc/lib_stream.c - - - lib_filesem.c - 1 - ../../../../../libc/misc/lib_filesem.c - - - lib_utsname.c - 1 - ../../../../../libc/misc/lib_utsname.c - - - lib_tea_encrypt.c - 1 - ../../../../../libc/misc/lib_tea_encrypt.c - - - lib_tea_decrypt.c - 1 - ../../../../../libc/misc/lib_tea_decrypt.c - - - lib_umul32.c - 1 - ../../../../../libc/misc/lib_umul32.c - - - lib_umul64.c - 1 - ../../../../../libc/misc/lib_umul64.c - - - lib_umul32x64.c - 1 - ../../../../../libc/misc/lib_umul32x64.c - - - lib_uadd32x64.c - 1 - ../../../../../libc/misc/lib_uadd32x64.c - - - lib_uadd64.c - 1 - ../../../../../libc/misc/lib_uadd64.c - - - lib_usub64x32.c - 1 - ../../../../../libc/misc/lib_usub64x32.c - - - lib_usub64.c - 1 - ../../../../../libc/misc/lib_usub64.c - - - lib_sendfile.c - 1 - ../../../../../libc/misc/lib_sendfile.c - - - lib_streamsem.c - 1 - ../../../../../libc/misc/lib_streamsem.c - - - lib_match.c - 1 - ../../../../../libc/misc/lib_match.c - - - lib_crc32.c - 1 - ../../../../../libc/misc/lib_crc32.c - - - lib_crc16.c - 1 - ../../../../../libc/misc/lib_crc16.c - - - lib_crc8.c - 1 - ../../../../../libc/misc/lib_crc8.c - - - lib_dumpbuffer.c - 1 - ../../../../../libc/misc/lib_dumpbuffer.c - - - lib_dbg.c - 1 - ../../../../../libc/misc/lib_dbg.c - - - lib_addrconfig.c - 1 - ../../../../../libc/net/lib_addrconfig.c - - - lib_etherntoa.c - 1 - ../../../../../libc/net/lib_etherntoa.c - - - lib_htons.c - 1 - ../../../../../libc/net/lib_htons.c - - - lib_htonl.c - 1 - ../../../../../libc/net/lib_htonl.c - - - lib_inetaddr.c - 1 - ../../../../../libc/net/lib_inetaddr.c - - - lib_inetntoa.c - 1 - ../../../../../libc/net/lib_inetntoa.c - - - lib_inetntop.c - 1 - ../../../../../libc/net/lib_inetntop.c - - - lib_inetpton.c - 1 - ../../../../../libc/net/lib_inetpton.c - - - pthread_attrinit.c - 1 - ../../../../../libc/pthread/pthread_attrinit.c - - - pthread_attrdestroy.c - 1 - ../../../../../libc/pthread/pthread_attrdestroy.c - - - pthread_attrsetschedpolicy.c - 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- - lib_getcwd.c - 1 - ../../../../../libc/unistd/lib_getcwd.c - - - lib_sleep.c - 1 - ../../../../../libc/unistd/lib_sleep.c - - - lib_usleep.c - 1 - ../../../../../libc/unistd/lib_usleep.c - - - - - - -               diff --git a/configs/stm32f429i-disco/ide/ltcd/uvision/libcxx.uvproj b/configs/stm32f429i-disco/ide/ltcd/uvision/libcxx.uvproj deleted file mode 100644 index f4013fcd59dc0ac324baacb5ce865981de5f1bbb..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/ltcd/uvision/libcxx.uvproj +++ /dev/null @@ -1,363 +0,0 @@ - - - 1.1 -
              ### uVision Project, (C) Keil Software
              - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M4 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE - - - - 5125 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libcxx\Obj\ - cxx - 0 - 1 - 1 - 1 - 0 - .\libcxx\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M4" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -fno-exceptions -fcheck-new -fno-rtti -Wall -Wshadow -Wundef -g - CONFIG_WCHAR_BUILTIN - - ../../../../../libxx;../../../../../include;../../../../../include/cxx - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../libxx;../../../../../include;../../../../../include/cxx - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - libxx - - - libxx_cxapurevirtual.cxx - 8 - ../../../../../libxx/libxx_cxapurevirtual.cxx - - - libxx_eabi_atexit.cxx - 8 - ../../../../../libxx/libxx_eabi_atexit.cxx - - - libxx_cxa_atexit.cxx - 8 - ../../../../../libxx/libxx_cxa_atexit.cxx - - - libxx_delete.cxx - 8 - ../../../../../libxx/libxx_delete.cxx - - - libxx_deletea.cxx - 8 - ../../../../../libxx/libxx_deletea.cxx - - - libxx_new.cxx - 8 - ../../../../../libxx/libxx_new.cxx - - - libxx_newa.cxx - 8 - ../../../../../libxx/libxx_newa.cxx - - - libxx_stdthrow.cxx - 8 - ../../../../../libxx/libxx_stdthrow.cxx - - - libxx_cxa_guard.cxx - 8 - ../../../../../libxx/libxx_cxa_guard.cxx - - - - - - -               diff --git a/configs/stm32f429i-disco/ide/ltcd/uvision/libdrivers.uvproj b/configs/stm32f429i-disco/ide/ltcd/uvision/libdrivers.uvproj deleted file mode 100644 index 84f1cdcb828656d0662b84a6dd189a7ddaa3f7a2..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/ltcd/uvision/libdrivers.uvproj +++ /dev/null @@ -1,418 +0,0 @@ - - - 1.1 -
              ### uVision Project, (C) Keil Software
              - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M4 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE - - - - 5125 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libdrivers\Obj\ - drivers - 0 - 1 - 1 - 1 - 0 - .\libdrivers\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M4" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../drivers/bch;../../../../../drivers;../../../../../drivers/spi;../../../../../drivers/loop;../../../../../drivers/usbhost;../../../../../include - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../drivers/bch;../../../../../drivers;../../../../../drivers/spi;../../../../../drivers/loop;../../../../../drivers/usbhost;../../../../../include - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - drivers - - - bchlib_setup.c - 1 - ../../../../../drivers/bch/bchlib_setup.c - - - bchlib_teardown.c - 1 - ../../../../../drivers/bch/bchlib_teardown.c - - - bchlib_read.c - 1 - ../../../../../drivers/bch/bchlib_read.c - - - bchlib_write.c - 1 - ../../../../../drivers/bch/bchlib_write.c - - - bchlib_cache.c - 1 - ../../../../../drivers/bch/bchlib_cache.c - - - bchlib_sem.c - 1 - ../../../../../drivers/bch/bchlib_sem.c - - - bchdev_register.c - 1 - ../../../../../drivers/bch/bchdev_register.c - - - bchdev_unregister.c - 1 - ../../../../../drivers/bch/bchdev_unregister.c - - - bchdev_driver.c - 1 - ../../../../../drivers/bch/bchdev_driver.c - - - losetup.c - 1 - ../../../../../drivers/loop/losetup.c - - - pipe.c - 1 - ../../../../../drivers/pipes/pipe.c - - - fifo.c - 1 - ../../../../../drivers/pipes/fifo.c - - - pipe_common.c - 1 - ../../../../../drivers/pipes/pipe_common.c - - - serial.c - 1 - ../../../../../drivers/serial/serial.c - - - serial_io.c - 1 - ../../../../../drivers/serial/serial_io.c - - - lowconsole.c - 1 - ../../../../../drivers/serial/lowconsole.c - - - hid_parser.c - 1 - ../../../../../drivers/usbhost/hid_parser.c - - - dev_null.c - 1 - ../../../../../drivers/dev_null.c - - - dev_zero.c - 1 - ../../../../../drivers/dev_zero.c - - - ramdisk.c - 1 - ../../../../../drivers/ramdisk.c - - - - - - -               diff --git a/configs/stm32f429i-disco/ide/ltcd/uvision/libfs.uvproj b/configs/stm32f429i-disco/ide/ltcd/uvision/libfs.uvproj deleted file mode 100644 index 5aca487cf7b38520291bd485a69817a32f4e08e2..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/ltcd/uvision/libfs.uvproj +++ /dev/null @@ -1,623 +0,0 @@ - - - 1.1 -
              ### uVision Project, (C) Keil Software
              - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M4 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE - - - - 5125 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libfs\Obj\ - fs - 0 - 1 - 1 - 1 - 0 - .\libfs\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M4" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../fs;../../../../../include - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../fs;../../../../../include - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - fs - - - fs_initialize.c - 1 - ../../../../../fs/fs_initialize.c - - - fs_files.c - 1 - ../../../../../fs/inode/fs_files.c - - - fs_foreachinode.c - 1 - ../../../../../fs/inode/fs_foreachinode.c - - - fs_inode.c - 1 - ../../../../../fs/inode/fs_inode.c - - - fs_inodeaddref.c - 1 - ../../../../../fs/inode/fs_inodeaddref.c - - - fs_inodebasename.c - 1 - ../../../../../fs/inode/fs_inodebasename.c - - - fs_inodefind.c - 1 - ../../../../../fs/inode/fs_inodefind.c - - - fs_inoderelease.c - 1 - ../../../../../fs/inode/fs_inoderelease.c - - - fs_inoderemove.c - 1 - ../../../../../fs/inode/fs_inoderemove.c - - - fs_inodereserve.c - 1 - ../../../../../fs/inode/fs_inodereserve.c - - - fs_close.c - 1 - ../../../../../fs/vfs/fs_close.c - - - fs_dup.c - 1 - ../../../../../fs/vfs/fs_dup.c - - - fs_dup2.c - 1 - ../../../../../fs/vfs/fs_dup2.c - - - fs_fcntl.c - 1 - ../../../../../fs/vfs/fs_fcntl.c - - - fs_dupfd.c - 1 - ../../../../../fs/vfs/fs_dupfd.c - - - fs_dupfd2.c - 1 - ../../../../../fs/vfs/fs_dupfd2.c - - - fs_epoll.c - 1 - ../../../../../fs/vfs/fs_epoll.c - - - fs_getfilep.c - 1 - ../../../../../fs/vfs/fs_getfilep.c - - - fs_ioctl.c - 1 - ../../../../../fs/vfs/fs_ioctl.c - - - fs_lseek.c - 1 - ../../../../../fs/vfs/fs_lseek.c - - - fs_mkdir.c - 1 - ../../../../../fs/vfs/fs_mkdir.c - - - fs_open.c - 1 - ../../../../../fs/vfs/fs_open.c - - - fs_poll.c - 1 - ../../../../../fs/vfs/fs_poll.c - - - fs_read.c - 1 - ../../../../../fs/vfs/fs_read.c - - - fs_rename.c - 1 - ../../../../../fs/vfs/fs_rename.c - - - fs_rmdir.c - 1 - ../../../../../fs/vfs/fs_rmdir.c - - - fs_stat.c - 1 - ../../../../../fs/vfs/fs_stat.c - - - fs_statfs.c - 1 - ../../../../../fs/vfs/fs_statfs.c - - - fs_select.c - 1 - ../../../../../fs/vfs/fs_select.c - - - fs_unlink.c - 1 - ../../../../../fs/vfs/fs_unlink.c - - - fs_write.c - 1 - ../../../../../fs/vfs/fs_write.c - - - fs_fsync.c - 1 - ../../../../../fs/vfs/fs_fsync.c - - - fs_pread.c - 1 - ../../../../../fs/vfs/fs_pread.c - - - fs_pwrite.c - 1 - ../../../../../fs/vfs/fs_pwrite.c - - - fs_fdopen.c - 1 - ../../../../../fs/vfs/fs_fdopen.c - - - fs_registerdriver.c - 1 - ../../../../../fs/driver/fs_registerdriver.c - - - fs_unregisterdriver.c - 1 - ../../../../../fs/driver/fs_unregisterdriver.c - - - fs_registerblockdriver.c - 1 - ../../../../../fs/driver/fs_registerblockdriver.c - - - fs_unregisterblockdriver.c - 1 - ../../../../../fs/driver/fs_unregisterblockdriver.c - - - fs_findblockdriver.c - 1 - ../../../../../fs/driver/fs_findblockdriver.c - - - fs_openblockdriver.c - 1 - ../../../../../fs/driver/fs_openblockdriver.c - - - fs_closeblockdriver.c - 1 - ../../../../../fs/driver/fs_closeblockdriver.c - - - fs_blockproxy.c - 1 - ../../../../../fs/driver/fs_blockproxy.c - - - fs_closedir.c - 1 - ../../../../../fs/dirent/fs_closedir.c - - - fs_opendir.c - 1 - ../../../../../fs/dirent/fs_opendir.c - - - fs_readdir.c - 1 - ../../../../../fs/dirent/fs_readdir.c - - - fs_rewinddir.c - 1 - ../../../../../fs/dirent/fs_rewinddir.c - - - fs_seekdir.c - 1 - ../../../../../fs/dirent/fs_seekdir.c - - - fs_mmap.c - 1 - ../../../../../fs/mmap/fs_mmap.c - - - mq_open.c - 1 - ../../../../../fs/mqueue/mq_open.c - - - mq_close.c - 1 - ../../../../../fs/mqueue/mq_close.c - - - mq_unlink.c - 1 - ../../../../../fs/mqueue/mq_unlink.c - - - fs_mount.c - 1 - ../../../../../fs/mount/fs_mount.c - - - fs_umount2.c - 1 - ../../../../../fs/mount/fs_umount2.c - - - fs_foreachmountpoint.c - 1 - ../../../../../fs/mount/fs_foreachmountpoint.c - - - fs_procfs.c - 1 - ../../../../../fs/procfs/fs_procfs.c - - - fs_procfsutil.c - 1 - ../../../../../fs/procfs/fs_procfsutil.c - - - fs_procfsproc.c - 1 - ../../../../../fs/procfs/fs_procfsproc.c - - - fs_procfsuptime.c - 1 - ../../../../../fs/procfs/fs_procfsuptime.c - - - fs_procfscpuload.c - 1 - ../../../../../fs/procfs/fs_procfscpuload.c - - - fs_procfskmm.c - 1 - ../../../../../fs/procfs/fs_procfskmm.c - - - - - - -               diff --git a/configs/stm32f429i-disco/ide/ltcd/uvision/libgraphics.uvproj b/configs/stm32f429i-disco/ide/ltcd/uvision/libgraphics.uvproj deleted file mode 100644 index db4af43a4f1b1046fafaa050a11dfca1687ddcf2..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/ltcd/uvision/libgraphics.uvproj +++ /dev/null @@ -1,728 +0,0 @@ - - - 1.1 -
              ### uVision Project, (C) Keil Software
              - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M4 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE - - - - 5125 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libgraphics\Obj\ - graphics - 0 - 1 - 1 - 1 - 0 - .\libgraphics\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M4" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../graphics/nxglib;../../../../../graphics/nxsu;../../../../../include;../../../../../graphics;../../../../../graphics/nxbe - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../graphics/nxglib;../../../../../graphics/nxsu;../../../../../include;../../../../../graphics;../../../../../graphics/nxbe - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - graphics - - - nxglib_setpixel_1bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_setpixel_1bpp.c - - - nxglib_setpixel_2bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_setpixel_2bpp.c - - - nxglib_setpixel_4bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_setpixel_4bpp.c - - - nxglib_setpixel_8bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_setpixel_8bpp.c - - - nxglib_setpixel_16bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_setpixel_16bpp.c - - - nxglib_setpixel_24bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_setpixel_24bpp.c - - - nxglib_setpixel_32bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_setpixel_32bpp.c - - - nxglib_fillrectangle_1bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_fillrectangle_1bpp.c - - - nxglib_fillrectangle_2bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_fillrectangle_2bpp.c - - - nxglib_fillrectangle_4bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_fillrectangle_4bpp.c - - - nxglib_fillrectangle_8bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_fillrectangle_8bpp.c - - - nxglib_fillrectangle_16bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_fillrectangle_16bpp.c - - - nxglib_fillrectangle_24bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_fillrectangle_24bpp.c - - - nxglib_fillrectangle_32bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_fillrectangle_32bpp.c - - - nxglib_getrectangle_1bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_getrectangle_1bpp.c - - - nxglib_getrectangle_2bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_getrectangle_2bpp.c - - - nxglib_getrectangle_4bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_getrectangle_4bpp.c - - - nxglib_getrectangle_8bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_getrectangle_8bpp.c - - - nxglib_getrectangle_16bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_getrectangle_16bpp.c - - - nxglib_getrectangle_24bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_getrectangle_24bpp.c - - - nxglib_getrectangle_32bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_getrectangle_32bpp.c - - - nxglib_filltrapezoid_1bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_filltrapezoid_1bpp.c - - - nxglib_filltrapezoid_2bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_filltrapezoid_2bpp.c - - - nxglib_filltrapezoid_4bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_filltrapezoid_4bpp.c - - - nxglib_filltrapezoid_8bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_filltrapezoid_8bpp.c - - - nxglib_filltrapezoid_16bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_filltrapezoid_16bpp.c - - - nxglib_filltrapezoid_24bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_filltrapezoid_24bpp.c - - - nxglib_filltrapezoid_32bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_filltrapezoid_32bpp.c - - - nxglib_moverectangle_1bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_moverectangle_1bpp.c - - - nxglib_moverectangle_2bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_moverectangle_2bpp.c - - - nxglib_moverectangle_4bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_moverectangle_4bpp.c - - - nxglib_moverectangle_8bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_moverectangle_8bpp.c - - - nxglib_moverectangle_16bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_moverectangle_16bpp.c - - - nxglib_moverectangle_24bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_moverectangle_24bpp.c - - - nxglib_moverectangle_32bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_moverectangle_32bpp.c - - - nxglib_copyrectangle_1bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_copyrectangle_1bpp.c - - - nxglib_copyrectangle_2bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_copyrectangle_2bpp.c - - - nxglib_copyrectangle_4bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_copyrectangle_4bpp.c - - - nxglib_copyrectangle_8bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_copyrectangle_8bpp.c - - - nxglib_copyrectangle_16bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_copyrectangle_16bpp.c - - - nxglib_copyrectangle_24bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_copyrectangle_24bpp.c - - - nxglib_copyrectangle_32bpp.c - 1 - ../../../../../graphics/nxglib/nxglib_copyrectangle_32bpp.c - - - nxbe_bitmap.c - 1 - ../../../../../graphics/nxbe/nxbe_bitmap.c - - - nxbe_configure.c - 1 - ../../../../../graphics/nxbe/nxbe_configure.c - - - nxbe_colormap.c - 1 - ../../../../../graphics/nxbe/nxbe_colormap.c - - - nxbe_clipper.c - 1 - ../../../../../graphics/nxbe/nxbe_clipper.c - - - nxbe_closewindow.c - 1 - ../../../../../graphics/nxbe/nxbe_closewindow.c - - - nxbe_fill.c - 1 - ../../../../../graphics/nxbe/nxbe_fill.c - - - nxbe_filltrapezoid.c - 1 - ../../../../../graphics/nxbe/nxbe_filltrapezoid.c - - - nxbe_getrectangle.c - 1 - ../../../../../graphics/nxbe/nxbe_getrectangle.c - - - nxbe_lower.c - 1 - ../../../../../graphics/nxbe/nxbe_lower.c - - - nxbe_move.c - 1 - ../../../../../graphics/nxbe/nxbe_move.c - - - nxbe_raise.c - 1 - ../../../../../graphics/nxbe/nxbe_raise.c - - - nxbe_redraw.c - 1 - ../../../../../graphics/nxbe/nxbe_redraw.c - - - nxbe_redrawbelow.c - 1 - ../../../../../graphics/nxbe/nxbe_redrawbelow.c - - - nxbe_setpixel.c - 1 - ../../../../../graphics/nxbe/nxbe_setpixel.c - - - nxbe_setposition.c - 1 - ../../../../../graphics/nxbe/nxbe_setposition.c - - - nxbe_setsize.c - 1 - ../../../../../graphics/nxbe/nxbe_setsize.c - - - nxbe_visible.c - 1 - ../../../../../graphics/nxbe/nxbe_visible.c - - - nx_bitmap.c - 1 - ../../../../../graphics/nxsu/nx_bitmap.c - - - nx_closewindow.c - 1 - ../../../../../graphics/nxsu/nx_closewindow.c - - - nx_fill.c - 1 - ../../../../../graphics/nxsu/nx_fill.c - - - nx_filltrapezoid.c - 1 - ../../../../../graphics/nxsu/nx_filltrapezoid.c - - - nx_getposition.c - 1 - ../../../../../graphics/nxsu/nx_getposition.c - - - nx_getrectangle.c - 1 - ../../../../../graphics/nxsu/nx_getrectangle.c - - - nx_kbdchin.c - 1 - ../../../../../graphics/nxsu/nx_kbdchin.c - - - nx_kbdin.c - 1 - ../../../../../graphics/nxsu/nx_kbdin.c - - - nx_lower.c - 1 - ../../../../../graphics/nxsu/nx_lower.c - - - nx_mousein.c - 1 - ../../../../../graphics/nxsu/nx_mousein.c - - - nx_move.c - 1 - ../../../../../graphics/nxsu/nx_move.c - - - nx_openwindow.c - 1 - ../../../../../graphics/nxsu/nx_openwindow.c - - - nx_raise.c - 1 - ../../../../../graphics/nxsu/nx_raise.c - - - nx_redrawreq.c - 1 - ../../../../../graphics/nxsu/nx_redrawreq.c - - - nx_releasebkgd.c - 1 - ../../../../../graphics/nxsu/nx_releasebkgd.c - - - nx_requestbkgd.c - 1 - ../../../../../graphics/nxsu/nx_requestbkgd.c - - - nx_setpixel.c - 1 - ../../../../../graphics/nxsu/nx_setpixel.c - - - nx_setsize.c - 1 - ../../../../../graphics/nxsu/nx_setsize.c - - - nx_setbgcolor.c - 1 - ../../../../../graphics/nxsu/nx_setbgcolor.c - - - nx_setposition.c - 1 - ../../../../../graphics/nxsu/nx_setposition.c - - - nx_constructwindow.c - 1 - ../../../../../graphics/nxsu/nx_constructwindow.c - - - nxsu_redrawreq.c - 1 - ../../../../../graphics/nxsu/nxsu_redrawreq.c - - - nxsu_reportposition.c - 1 - ../../../../../graphics/nxsu/nxsu_reportposition.c - - - - - - -               diff --git a/configs/stm32f429i-disco/ide/ltcd/uvision/libmm.uvproj b/configs/stm32f429i-disco/ide/ltcd/uvision/libmm.uvproj deleted file mode 100644 index d735f928be62831dc4db28f7f805852652d1acad..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/ltcd/uvision/libmm.uvproj +++ /dev/null @@ -1,453 +0,0 @@ - - - 1.1 -
              ### uVision Project, (C) Keil Software
              - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M4 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE - - - - 5125 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libmm\Obj\ - mm - 0 - 1 - 1 - 1 - 0 - .\libmm\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M4" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../mm;../../../../../include - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../mm;../../../../../include - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - mm - - - mm_initialize.c - 1 - ../../../../../mm/mm_heap/mm_initialize.c - - - mm_sem.c - 1 - ../../../../../mm/mm_heap/mm_sem.c - - - mm_addfreechunk.c - 1 - ../../../../../mm/mm_heap/mm_addfreechunk.c - - - mm_size2ndx.c - 1 - ../../../../../mm/mm_heap/mm_size2ndx.c - - - mm_shrinkchunk.c - 1 - ../../../../../mm/mm_heap/mm_shrinkchunk.c - - - mm_brkaddr.c - 1 - ../../../../../mm/mm_heap/mm_brkaddr.c - - - mm_calloc.c - 1 - ../../../../../mm/mm_heap/mm_calloc.c - - - mm_extend.c - 1 - ../../../../../mm/mm_heap/mm_extend.c - - - mm_free.c - 1 - ../../../../../mm/mm_heap/mm_free.c - - - mm_mallinfo.c - 1 - ../../../../../mm/mm_heap/mm_mallinfo.c - - - mm_malloc.c - 1 - ../../../../../mm/mm_heap/mm_malloc.c - - - mm_memalign.c - 1 - ../../../../../mm/mm_heap/mm_memalign.c - - - mm_realloc.c - 1 - ../../../../../mm/mm_heap/mm_realloc.c - - - mm_zalloc.c - 1 - ../../../../../mm/mm_heap/mm_zalloc.c - - - umm_initialize.c - 1 - ../../../../../mm/umm_heap/umm_initialize.c - - - umm_addregion.c - 1 - ../../../../../mm/umm_heap/umm_addregion.c - - - umm_sem.c - 1 - ../../../../../mm/umm_heap/umm_sem.c - - - umm_brkaddr.c - 1 - ../../../../../mm/umm_heap/umm_brkaddr.c - - - umm_calloc.c - 1 - ../../../../../mm/umm_heap/umm_calloc.c - - - umm_extend.c - 1 - ../../../../../mm/umm_heap/umm_extend.c - - - umm_free.c - 1 - ../../../../../mm/umm_heap/umm_free.c - - - umm_mallinfo.c - 1 - ../../../../../mm/umm_heap/umm_mallinfo.c - - - umm_malloc.c - 1 - ../../../../../mm/umm_heap/umm_malloc.c - - - umm_memalign.c - 1 - ../../../../../mm/umm_heap/umm_memalign.c - - - umm_realloc.c - 1 - ../../../../../mm/umm_heap/umm_realloc.c - - - umm_zalloc.c - 1 - ../../../../../mm/umm_heap/umm_zalloc.c - - - umm_globals.c - 1 - ../../../../../mm/umm_heap/umm_globals.c - - - - - - -               diff --git a/configs/stm32f429i-disco/ide/ltcd/uvision/libnx.uvproj b/configs/stm32f429i-disco/ide/ltcd/uvision/libnx.uvproj deleted file mode 100644 index e7c88eb4e40b1194c97ea922652a82c75ddadf16..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/ltcd/uvision/libnx.uvproj +++ /dev/null @@ -1,658 +0,0 @@ - - - 1.1 -
              ### uVision Project, (C) Keil Software
              - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M4 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE - - - - 5125 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libnx\Obj\ - nx - 0 - 1 - 1 - 1 - 0 - .\libnx\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M4" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../libnx;../../../../../include - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../libnx;../../../../../include - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - libnx - - - nxglib_circlepts.c - 1 - ../../../../../libnx/nxglib/nxglib_circlepts.c - - - nxglib_circletraps.c - 1 - ../../../../../libnx/nxglib/nxglib_circletraps.c - - - nxglib_intersecting.c - 1 - ../../../../../libnx/nxglib/nxglib_intersecting.c - - - nxglib_nonintersecting.c - 1 - ../../../../../libnx/nxglib/nxglib_nonintersecting.c - - - nxglib_nullrect.c - 1 - ../../../../../libnx/nxglib/nxglib_nullrect.c - - - nxglib_rectadd.c - 1 - ../../../../../libnx/nxglib/nxglib_rectadd.c - - - nxglib_rectcopy.c - 1 - ../../../../../libnx/nxglib/nxglib_rectcopy.c - - - nxglib_rectinside.c - 1 - ../../../../../libnx/nxglib/nxglib_rectinside.c - - - nxglib_rectintersect.c - 1 - ../../../../../libnx/nxglib/nxglib_rectintersect.c - - - nxglib_rectoffset.c - 1 - ../../../../../libnx/nxglib/nxglib_rectoffset.c - - - nxglib_rectoverlap.c - 1 - ../../../../../libnx/nxglib/nxglib_rectoverlap.c - - - nxglib_rectsize.c - 1 - ../../../../../libnx/nxglib/nxglib_rectsize.c - - - nxglib_rectunion.c - 1 - ../../../../../libnx/nxglib/nxglib_rectunion.c - - - nxglib_rgb2yuv.c - 1 - ../../../../../libnx/nxglib/nxglib_rgb2yuv.c - - - nxglib_rgbblend.c - 1 - ../../../../../libnx/nxglib/nxglib_rgbblend.c - - - nxglib_runcopy.c - 1 - ../../../../../libnx/nxglib/nxglib_runcopy.c - - - nxglib_runoffset.c - 1 - ../../../../../libnx/nxglib/nxglib_runoffset.c - - - nxglib_splitline.c - 1 - ../../../../../libnx/nxglib/nxglib_splitline.c - - - nxglib_trapcopy.c - 1 - ../../../../../libnx/nxglib/nxglib_trapcopy.c - - - nxglib_trapoffset.c - 1 - ../../../../../libnx/nxglib/nxglib_trapoffset.c - - - nxglib_vectoradd.c - 1 - ../../../../../libnx/nxglib/nxglib_vectoradd.c - - - nxglib_vectsubtract.c - 1 - ../../../../../libnx/nxglib/nxglib_vectsubtract.c - - - nxglib_yuv2rgb.c - 1 - ../../../../../libnx/nxglib/nxglib_yuv2rgb.c - - - nx_drawcircle.c - 1 - ../../../../../libnx/nx/nx_drawcircle.c - - - nx_drawline.c - 1 - ../../../../../libnx/nx/nx_drawline.c - - - nx_fillcircle.c - 1 - ../../../../../libnx/nx/nx_fillcircle.c - - - nxfonts_getfont.c - 1 - ../../../../../libnx/nxfonts/nxfonts_getfont.c - - - nxfonts_convert_1bpp.c - 1 - ../../../../../libnx/nxfonts/nxfonts_convert_1bpp.c - - - nxfonts_convert_2bpp.c - 1 - ../../../../../libnx/nxfonts/nxfonts_convert_2bpp.c - - - nxfonts_convert_4bpp.c - 1 - ../../../../../libnx/nxfonts/nxfonts_convert_4bpp.c - - - nxfonts_convert_8bpp.c - 1 - ../../../../../libnx/nxfonts/nxfonts_convert_8bpp.c - - - nxfonts_convert_16bpp.c - 1 - ../../../../../libnx/nxfonts/nxfonts_convert_16bpp.c - - - nxfonts_convert_24bpp.c - 1 - ../../../../../libnx/nxfonts/nxfonts_convert_24bpp.c - - - nxfonts_convert_32bpp.c - 1 - ../../../../../libnx/nxfonts/nxfonts_convert_32bpp.c - - - nxfonts_bitmaps_mono5x8.c - 1 - ../../../../../libnx/nxfonts/nxfonts_bitmaps_mono5x8.c - - - nxtk_openwindow.c - 1 - ../../../../../libnx/nxtk/nxtk_openwindow.c - - - nxtk_closewindow.c - 1 - ../../../../../libnx/nxtk/nxtk_closewindow.c - - - nxtk_getposition.c - 1 - ../../../../../libnx/nxtk/nxtk_getposition.c - - - nxtk_setposition.c - 1 - ../../../../../libnx/nxtk/nxtk_setposition.c - - - nxtk_setsize.c - 1 - ../../../../../libnx/nxtk/nxtk_setsize.c - - - nxtk_raise.c - 1 - ../../../../../libnx/nxtk/nxtk_raise.c - - - nxtk_lower.c - 1 - ../../../../../libnx/nxtk/nxtk_lower.c - - - nxtk_fillwindow.c - 1 - ../../../../../libnx/nxtk/nxtk_fillwindow.c - - - nxtk_getwindow.c - 1 - ../../../../../libnx/nxtk/nxtk_getwindow.c - - - nxtk_filltrapwindow.c - 1 - ../../../../../libnx/nxtk/nxtk_filltrapwindow.c - - - nxtk_movewindow.c - 1 - ../../../../../libnx/nxtk/nxtk_movewindow.c - - - nxtk_bitmapwindow.c - 1 - ../../../../../libnx/nxtk/nxtk_bitmapwindow.c - - - nxtk_events.c - 1 - ../../../../../libnx/nxtk/nxtk_events.c - - - nxtk_setsubwindows.c - 1 - ../../../../../libnx/nxtk/nxtk_setsubwindows.c - - - nxtk_drawcirclewindow.c - 1 - ../../../../../libnx/nxtk/nxtk_drawcirclewindow.c - - - nxtk_drawlinewindow.c - 1 - ../../../../../libnx/nxtk/nxtk_drawlinewindow.c - - - nxtk_fillcirclewindow.c - 1 - ../../../../../libnx/nxtk/nxtk_fillcirclewindow.c - - - nxtk_block.c - 1 - ../../../../../libnx/nxtk/nxtk_block.c - - - nxtk_opentoolbar.c - 1 - ../../../../../libnx/nxtk/nxtk_opentoolbar.c - - - nxtk_closetoolbar.c - 1 - ../../../../../libnx/nxtk/nxtk_closetoolbar.c - - - nxtk_filltoolbar.c - 1 - ../../../../../libnx/nxtk/nxtk_filltoolbar.c - - - nxtk_gettoolbar.c - 1 - ../../../../../libnx/nxtk/nxtk_gettoolbar.c - - - nxtk_filltraptoolbar.c - 1 - ../../../../../libnx/nxtk/nxtk_filltraptoolbar.c - - - nxtk_movetoolbar.c - 1 - ../../../../../libnx/nxtk/nxtk_movetoolbar.c - - - nxtk_bitmaptoolbar.c - 1 - ../../../../../libnx/nxtk/nxtk_bitmaptoolbar.c - - - nxtk_drawcircletoolbar.c - 1 - ../../../../../libnx/nxtk/nxtk_drawcircletoolbar.c - - - nxtk_drawlinetoolbar.c - 1 - ../../../../../libnx/nxtk/nxtk_drawlinetoolbar.c - - - nxtk_fillcircletoolbar.c - 1 - ../../../../../libnx/nxtk/nxtk_fillcircletoolbar.c - - - nxtk_toolbarbounds.c - 1 - ../../../../../libnx/nxtk/nxtk_toolbarbounds.c - - - nxtk_subwindowclip.c - 1 - ../../../../../libnx/nxtk/nxtk_subwindowclip.c - - - nxtk_containerclip.c - 1 - ../../../../../libnx/nxtk/nxtk_containerclip.c - - - nxtk_subwindowmove.c - 1 - ../../../../../libnx/nxtk/nxtk_subwindowmove.c - - - nxtk_drawframe.c - 1 - ../../../../../libnx/nxtk/nxtk_drawframe.c - - - - - - -               diff --git a/configs/stm32f429i-disco/ide/ltcd/uvision/libsched.uvproj b/configs/stm32f429i-disco/ide/ltcd/uvision/libsched.uvproj deleted file mode 100644 index 5ad556b58207c6c26ef64a0ce8708f73901f9d44..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/ltcd/uvision/libsched.uvproj +++ /dev/null @@ -1,1263 +0,0 @@ - - - 1.1 -
              ### uVision Project, (C) Keil Software
              - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M4 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE - - - - 5125 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\libsched\Obj\ - sched - 0 - 1 - 1 - 1 - 0 - .\libsched\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M4" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - -fno-builtin -Wall -Wstrict-prototypes -Wshadow -Wundef -g - - - ../../../../../sched;../../../../../include - - - - 0 - 0 - - - __ASSEMBLY__ - - ../../../../../sched;../../../../../include - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - sched - - - clock_initialize.c - 1 - ../../../../../sched/clock/clock_initialize.c - - - clock_settime.c - 1 - ../../../../../sched/clock/clock_settime.c - - - clock_gettime.c - 1 - ../../../../../sched/clock/clock_gettime.c - - - clock_getres.c - 1 - ../../../../../sched/clock/clock_getres.c - - - clock_time2ticks.c - 1 - ../../../../../sched/clock/clock_time2ticks.c - - - clock_abstime2ticks.c - 1 - ../../../../../sched/clock/clock_abstime2ticks.c - - - clock_ticks2time.c - 1 - ../../../../../sched/clock/clock_ticks2time.c - - - clock_systimer.c - 1 - ../../../../../sched/clock/clock_systimer.c - - - clock_systimespec.c - 1 - ../../../../../sched/clock/clock_systimespec.c - - - clock_timespec_add.c - 1 - ../../../../../sched/clock/clock_timespec_add.c - - - clock_timespec_subtract.c - 1 - ../../../../../sched/clock/clock_timespec_subtract.c - - - errno_getptr.c - 1 - ../../../../../sched/errno/errno_getptr.c - - - env_getenvironptr.c - 1 - ../../../../../sched/environ/env_getenvironptr.c - - - env_dup.c - 1 - ../../../../../sched/environ/env_dup.c - - - env_release.c - 1 - ../../../../../sched/environ/env_release.c - - - env_findvar.c - 1 - ../../../../../sched/environ/env_findvar.c - - - env_removevar.c - 1 - ../../../../../sched/environ/env_removevar.c - - - env_clearenv.c - 1 - ../../../../../sched/environ/env_clearenv.c - - - env_getenv.c - 1 - ../../../../../sched/environ/env_getenv.c - - - env_putenv.c - 1 - ../../../../../sched/environ/env_putenv.c - - - env_setenv.c - 1 - ../../../../../sched/environ/env_setenv.c - - - env_unsetenv.c - 1 - ../../../../../sched/environ/env_unsetenv.c - - - group_create.c - 1 - ../../../../../sched/group/group_create.c - - - group_join.c - 1 - ../../../../../sched/group/group_join.c - - - group_leave.c - 1 - ../../../../../sched/group/group_leave.c - - - group_find.c - 1 - ../../../../../sched/group/group_find.c - - - group_setupstreams.c - 1 - ../../../../../sched/group/group_setupstreams.c - - - group_setupidlefiles.c - 1 - ../../../../../sched/group/group_setupidlefiles.c - - - group_setuptaskfiles.c - 1 - ../../../../../sched/group/group_setuptaskfiles.c - - - group_foreachchild.c - 1 - ../../../../../sched/group/group_foreachchild.c - - - group_killchildren.c - 1 - ../../../../../sched/group/group_killchildren.c - - - group_waiter.c - 1 - ../../../../../sched/group/group_waiter.c - - - group_signal.c - 1 - ../../../../../sched/group/group_signal.c - - - os_start.c - 1 - ../../../../../sched/init/os_start.c - - - os_bringup.c - 1 - ../../../../../sched/init/os_bringup.c - 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- - task_create.c - 1 - ../../../../../sched/task/task_create.c - - - task_init.c - 1 - ../../../../../sched/task/task_init.c - - - task_setup.c - 1 - ../../../../../sched/task/task_setup.c - - - task_activate.c - 1 - ../../../../../sched/task/task_activate.c - - - task_start.c - 1 - ../../../../../sched/task/task_start.c - - - task_delete.c - 1 - ../../../../../sched/task/task_delete.c - - - task_exit.c - 1 - ../../../../../sched/task/task_exit.c - - - task_exithook.c - 1 - ../../../../../sched/task/task_exithook.c - - - task_recover.c - 1 - ../../../../../sched/task/task_recover.c - - - task_restart.c - 1 - ../../../../../sched/task/task_restart.c - - - task_spawnparms.c - 1 - ../../../../../sched/task/task_spawnparms.c - - - task_terminate.c - 1 - ../../../../../sched/task/task_terminate.c - - - task_getgroup.c - 1 - ../../../../../sched/task/task_getgroup.c - - - task_prctl.c - 1 - ../../../../../sched/task/task_prctl.c - - - task_getpid.c - 1 - ../../../../../sched/task/task_getpid.c - - - exit.c - 1 - ../../../../../sched/task/exit.c - - - task_vfork.c - 1 - ../../../../../sched/task/task_vfork.c - - - task_spawn.c - 1 - ../../../../../sched/task/task_spawn.c - - - timer_initialize.c - 1 - ../../../../../sched/timer/timer_initialize.c - - - timer_create.c - 1 - ../../../../../sched/timer/timer_create.c - - - timer_delete.c - 1 - ../../../../../sched/timer/timer_delete.c - - - timer_getoverrun.c - 1 - ../../../../../sched/timer/timer_getoverrun.c - - - timer_gettime.c - 1 - ../../../../../sched/timer/timer_gettime.c - - - timer_settime.c - 1 - ../../../../../sched/timer/timer_settime.c - - - timer_release.c - 1 - ../../../../../sched/timer/timer_release.c - - - wd_initialize.c - 1 - ../../../../../sched/wdog/wd_initialize.c - - - wd_create.c - 1 - ../../../../../sched/wdog/wd_create.c - - - wd_start.c - 1 - ../../../../../sched/wdog/wd_start.c - - - wd_cancel.c - 1 - ../../../../../sched/wdog/wd_cancel.c - - - wd_delete.c - 1 - ../../../../../sched/wdog/wd_delete.c - - - wd_gettime.c - 1 - ../../../../../sched/wdog/wd_gettime.c - - - wd_recover.c - 1 - ../../../../../sched/wdog/wd_recover.c - - - - - - -               diff --git a/configs/stm32f429i-disco/ide/ltcd/uvision/nuttx.uvmpw b/configs/stm32f429i-disco/ide/ltcd/uvision/nuttx.uvmpw deleted file mode 100644 index b2de32720b9aa74d3d9de7faa48506f1020ebb41..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/ltcd/uvision/nuttx.uvmpw +++ /dev/null @@ -1,45 +0,0 @@ - - - 1.0 -
              ### uVision Project, (C) Keil Software
              - WorkSpace - - libboard.uvproj - - - libapps.uvproj - - - libfs.uvproj - - - libdrivers.uvproj - - - libmm.uvproj - - - libgraphics.uvproj - - - libbinfmt.uvproj - - - libsched.uvproj - - - libarch.uvproj - - - libc.uvproj - - - libnx.uvproj - - - libcxx.uvproj - - - nuttx_main.uvproj - -               diff --git a/configs/stm32f429i-disco/ide/ltcd/uvision/nuttx_main.uvproj b/configs/stm32f429i-disco/ide/ltcd/uvision/nuttx_main.uvproj deleted file mode 100644 index 6f7d85ed5351b23724c5fa1774de597408c3ad3b..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/ltcd/uvision/nuttx_main.uvproj +++ /dev/null @@ -1,360 +0,0 @@ - - - 1.1 -
              ### uVision Project, (C) Keil Software
              - - - nuttx - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M4 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE - - - - 5125 - - - - - - - - - - - - 0 - 0 - - - - - \ - - 0 - 0 - 0 - 0 - 1 - - .\nuttx\Obj\ - nuttx - 1 - 0 - 1 - 1 - 0 - .\nuttx\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 6 - - - - - - - - - - - - - - Segger\JL2CM3.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M4" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 2 - 1 - - - - - ../../../../../arch/arm/src/chip;../../../../../arch/arm/src;../../../../../arch/arm/src/armv7-m;../../../../../sched;../../../../../arch/arm/src/common;../../../../../include - - - - 0 - 0 - - - - - ../../../../../arch/arm/src/chip;../../../../../arch/arm/src;../../../../../arch/arm/src/armv7-m;../../../../../sched;../../../../../arch/arm/src/common;../../../../../include - - - - 1 - 0 - 1 - 1 - 0 - - - - - .\lib - --entry=__start -Wl,--start-group -lboard -lapps -lfs -ldrivers -lmm -lgraphics -lbinfmt -lsched -larch -lc -lnx -lcxx -lgcc -Wl,--end-group - ..\..\..\scripts\ld.script - - - - - - gnu - - - stm32_vectors.S - 1 - ../../../../../arch/arm/src/chip/gnu/stm32_vectors.S - - - 2 - 0 - 0 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - 11 - - - 1 - - - - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 0 - 2 - - - __ASSEMBLY__ - - ../../../../../arch/arm/src/chip;../../../../../arch/arm/src;../../../../../arch/arm/src/armv7-m;../../../../../sched;../../../../../arch/arm/src/common;../../../../../include - - - - - - - - - - -               diff --git a/configs/stm32f429i-disco/ide/template/uvision_gcc/template_nuttx.uvmpw b/configs/stm32f429i-disco/ide/template/uvision_gcc/template_nuttx.uvmpw deleted file mode 100644 index 1ca927da10147c717eb7d6e1cd4ba513badf5ce1..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/template/uvision_gcc/template_nuttx.uvmpw +++ /dev/null @@ -1,21 +0,0 @@ - - - - 1.0 - -
              ### uVision Project, (C) Keil Software
              - - WorkSpace - - - .\template_nuttx_lib.uvproj - 1 - - - - .\template_nuttx_main.uvproj - 1 - 1 - - -               diff --git a/configs/stm32f429i-disco/ide/template/uvision_gcc/template_nuttx_lib.uvproj b/configs/stm32f429i-disco/ide/template/uvision_gcc/template_nuttx_lib.uvproj deleted file mode 100644 index 43a96331d3a7f7fb2899a08a35334f51c1615d17..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/template/uvision_gcc/template_nuttx_lib.uvproj +++ /dev/null @@ -1,364 +0,0 @@ - - - - 1.1 - -
              ### uVision Project, (C) Keil Software
              - - - - nuttx_lib - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M4 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE - - - - 5125 - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\nuttx\Obj\ - nuttx - 0 - 1 - 1 - 1 - 0 - .\nuttx\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 1 - cmd /c mkdir "lib" - cmd /c copy "$Llib@L.a" "lib\" - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 0 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M4" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - - - - - - - - - 0 - 0 - - - __ASSEMBLY__ - - - - - - 1 - 0 - 1 - 1 - 0 - - - - - - - - - - - - - gnu - - - stm32_vectors.S - 1 - ../../../arch/arm/src/chip/gnu/stm32_vectors.S - - - 2 - 0 - 0 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - 11 - - - 1 - - - - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 0 - 2 - - - __ASSEMBLY__ - - - - - - - - - - - - - -               diff --git a/configs/stm32f429i-disco/ide/template/uvision_gcc/template_nuttx_main.uvproj b/configs/stm32f429i-disco/ide/template/uvision_gcc/template_nuttx_main.uvproj deleted file mode 100644 index 4fd24173496ca6a849c249d7e41c4ea2e345c4aa..0000000000000000000000000000000000000000 --- a/configs/stm32f429i-disco/ide/template/uvision_gcc/template_nuttx_main.uvproj +++ /dev/null @@ -1,364 +0,0 @@ - - - - 1.1 - -
              ### uVision Project, (C) Keil Software
              - - - - nuttx - 0x3 - ARM-GNU - 5060020::V5.06 (build 20)::ARMCC - - - Cortex-M4 - ARM - CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE - - - - 5125 - - - - - - - - - - - - 0 - 0 - - - - - \ - - 0 - 0 - 0 - 0 - 1 - - .\nuttx\Obj\ - nuttx - 1 - 0 - 1 - 1 - 0 - ..\nuttx\Lst\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DCM.DLL - -pCM4 - SARMCM3.DLL - - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 6 - - - - - - - - - - - - - - Segger\JL2CM3.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - "Cortex-M4" - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 2 - 1 - - - - - - - - - 0 - 0 - - - - - - - - - 1 - 0 - 1 - 1 - 0 - - - - - - --entry=__start - ..\..\..\scripts\ld.script - - - - - - gnu - - - stm32_vectors.S - 1 - ../../../arch/arm/src/chip/gnu/stm32_vectors.S - - - 2 - 0 - 0 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - 11 - - - 1 - - - - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 0 - 2 - - - __ASSEMBLY__ - - - - - - - - - - - - - -               diff --git a/configs/stm32f429i-disco/include/board.h b/configs/stm32f429i-disco/include/board.h index c3dfbea085615802fcda24825b61f315f17ec209..8774b70f28fbd95d1b1802c9818d293cddf43e82 100644 --- a/configs/stm32f429i-disco/include/board.h +++ b/configs/stm32f429i-disco/include/board.h @@ -206,10 +206,10 @@ /* Alternate function pin selections ************************************************/ -/* UART2: +/* USART1: * * The STM32F4 Discovery has no on-board serial devices, but the console is - * brought out to PA2 (TX) and PA3 (RX) for connection to an external serial device. + * brought out to PA9 (TX) and PA10 (RX) for connection to an external serial device. * (See the README.txt file for other options) */ @@ -436,41 +436,4 @@ #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(BOARD_LTDC_PLLSAIQ) #endif /* CONFIG_STM32_LTDC */ - -/************************************************************************************ - * Public Data - ************************************************************************************/ -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_STM32F429I_DISCO_INCLUDE_BOARD_H */ diff --git a/configs/stm32f429i-disco/lcd/defconfig b/configs/stm32f429i-disco/lcd/defconfig index 523f657c0ef3c62f0baad2341a7171d2c10cfe7b..645971ebbdb49d38f6451f2c5f47a1906d157faa 100644 --- a/configs/stm32f429i-disco/lcd/defconfig +++ b/configs/stm32f429i-disco/lcd/defconfig @@ -1,7 +1,6 @@ # CONFIG_ARCH_FPU is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_STM32_FLASH_PREFETCH is not set CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BOARD="stm32f429i-disco" @@ -21,6 +20,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NX_BPP=16 CONFIG_EXAMPLES_NX=y +CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HEAP2_BASE=0xD0000000 @@ -29,7 +29,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LCD_ILI9341_IFACE0=y CONFIG_LCD_ILI9341=y CONFIG_LCD=y -CONFIG_LIB_BOARDCTL=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 CONFIG_MM_REGIONS=3 diff --git a/configs/stm32f429i-disco/nsh/defconfig b/configs/stm32f429i-disco/nsh/defconfig index f6d7516ef8b764c408ff24733f77c4eb5b285395..bd5a68a343034361983d6fecac0564ef15f74599 100644 --- a/configs/stm32f429i-disco/nsh/defconfig +++ b/configs/stm32f429i-disco/nsh/defconfig @@ -15,6 +15,7 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_DISABLE_POLL=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y CONFIG_EXAMPLES_NSH=y +CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HEAP2_BASE=0xD0000000 diff --git a/configs/stm32f429i-disco/nxwm/defconfig b/configs/stm32f429i-disco/nxwm/defconfig index 3e3f53799e6c7512f6d33fc64d2ce8f14f6dd943..c1bda648f9a343765dd844ce8485b883ee25f4ba 100644 --- a/configs/stm32f429i-disco/nxwm/defconfig +++ b/configs/stm32f429i-disco/nxwm/defconfig @@ -1,7 +1,6 @@ # CONFIG_ARCH_FPU is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set # CONFIG_STM32_FLASH_PREFETCH is not set CONFIG_ARCH_BOARD_STM32F429I_DISCO=y @@ -22,20 +21,17 @@ CONFIG_DISABLE_POLL=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_I2C_POLLED=y +CONFIG_HEAP2_BASE=0xd0000000 +CONFIG_HEAP2_SIZE=8081408 CONFIG_INPUT_STMPE811=y CONFIG_INPUT=y CONFIG_INTELHEX_BINARY=y -CONFIG_LCD_ILI9341_IFACE0=y -CONFIG_LCD_ILI9341=y -CONFIG_LCD=y CONFIG_MAX_TASKS=16 CONFIG_MAX_WDOGPARMS=2 -CONFIG_MM_REGIONS=3 +CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_STREAMS=8 @@ -69,10 +65,12 @@ CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf CONFIG_NXWIDGETS_SIZEOFCHAR=1 CONFIG_NXWIDGETS=y +CONFIG_NXWM_CALIBRATION_AVERAGE=y +CONFIG_NXWM_CALIBRATION_MESSAGES=y +CONFIG_NXWM_CALIBRATION_NSAMPLES=2 CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y CONFIG_NXWM_HEXCALCULATOR_FONTID=5 CONFIG_NXWM_KEYBOARD=y -CONFIG_NXWM_STARTWINDOW_MQNAME="nxwm" CONFIG_NXWM_TASKBAR_LEFT=y CONFIG_NXWM_TASKBAR_VSPACING=4 CONFIG_NXWM_TOUCHSCREEN_LISTENERSTACK=1596 @@ -89,18 +87,22 @@ CONFIG_SCHED_HPWORKPRIORITY=192 CONFIG_SCHED_ONEXIT=y CONFIG_SCHED_WAITPID=y CONFIG_SDCLONE_DISABLE=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 +CONFIG_START_DAY=15 +CONFIG_START_MONTH=11 +CONFIG_STM32_CCMEXCLUDE=y CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA2D_NLAYERS=1 +CONFIG_STM32_DMA2D=y CONFIG_STM32_FSMC_SRAM=y CONFIG_STM32_FSMC=y CONFIG_STM32_I2C3=y CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_LTDC_FB_BASE=0xd07b5000 +CONFIG_STM32_LTDC_FB_SIZE=307200 +CONFIG_STM32_LTDC_INTERFACE=y +CONFIG_STM32_LTDC=y CONFIG_STM32_PWR=y CONFIG_STM32_USART1=y -CONFIG_STM32F429I_DISCO_ILI9341_SPIBITS16=y -CONFIG_STM32F429I_DISCO_ILI9341_SPIFREQUENCY=20000000 CONFIG_STM32F429I_DISCO_ILI9341=y CONFIG_STMPE811_ACTIVELOW=y CONFIG_STMPE811_EDGE=y diff --git a/configs/stm32f429i-disco/src/Makefile b/configs/stm32f429i-disco/src/Makefile index 2ff0cb8d235584b97ff8aa2629468de51077f17e..430b7d201bc165b258fe4a367821a68ca3c9a82c 100644 --- a/configs/stm32f429i-disco/src/Makefile +++ b/configs/stm32f429i-disco/src/Makefile @@ -36,7 +36,7 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = stm32_boot.c stm32_spi.c +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += stm32_autoleds.c @@ -48,7 +48,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_NSH_LIBRARY),y) +ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += stm32_appinit.c endif diff --git a/configs/stm32f429i-disco/src/stm32_appinit.c b/configs/stm32f429i-disco/src/stm32_appinit.c index d7c352f344b0657c375058eae547fe95559797c9..d70edff0ffdc16bb75d4454bbe7e23d2a9ae3532 100644 --- a/configs/stm32f429i-disco/src/stm32_appinit.c +++ b/configs/stm32f429i-disco/src/stm32_appinit.c @@ -39,79 +39,13 @@ #include -#include -#include -#include -#include +#include #include -#include -#ifdef CONFIG_STM32_SPI4 -# include -#endif - -#ifdef CONFIG_MTD_SST25XX -# include -#endif - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifndef CONFIG_STM32F429I_DISCO_FLASH_MINOR -#define CONFIG_STM32F429I_DISCO_FLASH_MINOR 0 -#endif - -#ifdef CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART -#ifdef CONFIG_PLATFORM_CONFIGDATA -# include -#endif -#endif - -#ifdef CONFIG_STM32_OTGHS -# include "stm32_usbhost.h" -#endif - -#include "stm32.h" #include "stm32f429i-disco.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_USBDEV 1 -#define HAVE_USBHOST 1 -#define HAVE_USBMONITOR 1 - -/* Can't support USB host or device features if USB OTG HS is not enabled */ - -#ifndef CONFIG_STM32_OTGHS -# undef HAVE_USBDEV -# undef HAVE_USBHOST -# undef HAVE_USBMONITOR -#endif - -/* Can't support USB device monitor if USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -# undef HAVE_USBMONITOR -#endif - -/* Can't support USB host is USB host is not enabled */ - -#ifndef CONFIG_USBHOST -# undef HAVE_USBHOST -#endif - -/* Check if we should enable the USB monitor before starting NSH */ - -#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_USBMONITOR) -# undef HAVE_USBMONITOR -#endif +#ifdef CONFIG_LIB_BOARDCTL /**************************************************************************** * Public Functions @@ -125,13 +59,6 @@ * called directly from application code, but only indirectly via the * (non-standard) boardctl() interface using the command BOARDIOC_INIT. * - * CONFIG_LIB_BOARDCTL=y : - * Called from the NSH library - * - * CONFIG_BOARD_INITIALIZE=y, CONFIG_NSH_LIBRARY=y, && - * CONFIG_LIB_BOARDCTL=n : - * Called from board_initialize(). - * * Input Parameters: * arg - The boardctl() argument is passed to the board_app_initialize() * implementation without modification. The argument has no @@ -151,242 +78,15 @@ int board_app_initialize(uintptr_t arg) { -#if defined(CONFIG_STM32_SPI4) - FAR struct spi_dev_s *spi; - FAR struct mtd_dev_s *mtd; - FAR struct mtd_geometry_s geo; -#endif - -#if defined(CONFIG_MTD_PARTITION_NAMES) - FAR const char *partname = CONFIG_STM32F429I_DISCO_FLASH_PART_NAMES; -#endif - -#if defined(CONFIG_MTD) && defined(CONFIG_MTD_SST25XX) - int ret; -#elif defined(HAVE_USBHOST) || defined(HAVE_USBMONITOR) - int ret; -#elif defined(CONFIG_SENSORS_L3GD20) - int ret; -#endif - - /* Configure SPI-based devices */ - -#ifdef CONFIG_STM32_SPI4 - /* Get the SPI port */ - - syslog(LOG_INFO, "Initializing SPI port 4\n"); - - spi = stm32_spibus_initialize(4); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 4\n"); - return -ENODEV; - } - - syslog(LOG_INFO, "Successfully initialized SPI port 4\n"); - - /* Now bind the SPI interface to the SST25F064 SPI FLASH driver. This - * is a FLASH device that has been added external to the board (i.e. - * the board does not ship from STM with any on-board FLASH. - */ - -#if defined(CONFIG_MTD) && defined(CONFIG_MTD_SST25XX) - syslog(LOG_INFO, "Bind SPI to the SPI flash driver\n"); - - mtd = sst25xx_initialize(spi); - if (!mtd) - { - syslog(LOG_ERR, "ERROR: Failed to bind SPI port 4 to the SPI FLASH driver\n"); - } - else - { - syslog(LOG_INFO, "Successfully bound SPI port 4 to the SPI FLASH driver\n"); - - /* Get the geometry of the FLASH device */ - - ret = mtd->ioctl(mtd, MTDIOC_GEOMETRY, (unsigned long)((uintptr_t)&geo)); - if (ret < 0) - { - ferr("ERROR: mtd->ioctl failed: %d\n", ret); - return ret; - } - -#ifdef CONFIG_STM32F429I_DISCO_FLASH_PART - { - int partno; - int partsize; - int partoffset; - int partszbytes; - int erasesize; - const char *partstring = CONFIG_STM32F429I_DISCO_FLASH_PART_LIST; - const char *ptr; - FAR struct mtd_dev_s *mtd_part; - char partref[4]; - - /* Now create a partition on the FLASH device */ +#ifdef CONFIG_BOARD_INITIALIZE + /* Board initialization already performed by board_initialize() */ - partno = 0; - ptr = partstring; - partoffset = 0; - - /* Get the Flash erase size */ - - erasesize = geo.erasesize; - - while (*ptr != '\0') - { - /* Get the partition size */ - - partsize = atoi(ptr); - partszbytes = (partsize << 10); /* partsize is defined in KB */ - - /* Check if partition size is bigger then erase block */ - - if (partszbytes < erasesize) - { - ferr("ERROR: Partition size is lesser than erasesize!\n"); - return -1; - } - - /* Check if partition size is multiple of erase block */ - - if ((partszbytes % erasesize) != 0) - { - ferr("ERROR: Partition size is not multiple of erasesize!\n"); - return -1; - } - - mtd_part = mtd_partition(mtd, partoffset, partszbytes / erasesize); - partoffset += partszbytes / erasesize; - -#ifdef CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART - /* Test if this is the config partition */ - - if (CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART_NUMBER == partno) - { - /* Register the partition as the config device */ - - mtdconfig_register(mtd_part); - } - else -#endif - { - /* Now initialize a SMART Flash block device and bind it - * to the MTD device. - */ - -#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) - sprintf(partref, "p%d", partno); - smart_initialize(CONFIG_STM32F429I_DISCO_FLASH_MINOR, mtd_part, partref); -#endif - } - -#if defined(CONFIG_MTD_PARTITION_NAMES) - /* Set the partition name */ - - if (mtd_part == NULL) - { - ferr("ERROR: failed to create partition %s\n", partname); - return -1; - } - - mtd_setpartitionname(mtd_part, partname); - - /* Now skip to next name. We don't need to split the string here - * because the MTD partition logic will only display names up to - * the comma, thus allowing us to use a single static name - * in the code. - */ - - while (*partname != ',' && *partname != '\0') - { - /* Skip to next ',' */ - - partname++; - } - - if (*partname == ',') - { - partname++; - } -#endif - - /* Update the pointer to point to the next size in the list */ - - while ((*ptr >= '0') && (*ptr <= '9')) - { - ptr++; - } - - if (*ptr == ',') - { - ptr++; - } - - /* Increment the part number */ - - partno++; - } - } -#else /* CONFIG_STM32F429I_DISCO_FLASH_PART */ - - /* Configure the device with no partition support */ - - smart_initialize(CONFIG_STM32F429I_DISCO_FLASH_MINOR, mtd, NULL); - -#endif /* CONFIG_STM32F429I_DISCO_FLASH_PART */ - } - -#endif /* CONFIG_MTD */ -#endif /* CONFIG_STM32_SPI4 */ - - /* Create a RAM MTD device if configured */ - -#if defined(CONFIG_RAMMTD) && defined(CONFIG_STM32F429I_DISCO_RAMMTD) - { - uint8_t *start = (uint8_t *) kmm_malloc(CONFIG_STM32F429I_DISCO_RAMMTD_SIZE * 1024); - mtd = rammtd_initialize(start, CONFIG_STM32F429I_DISCO_RAMMTD_SIZE * 1024); - mtd->ioctl(mtd, MTDIOC_BULKERASE, 0); - - /* Now initialize a SMART Flash block device and bind it to the MTD device */ - -#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) - smart_initialize(CONFIG_STM32F429I_DISCO_RAMMTD_MINOR, mtd, NULL); -#endif - } - -#endif /* CONFIG_RAMMTD && CONFIG_STM32F429I_DISCO_RAMMTD */ - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a thread - * will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); - } -#endif + return OK; +#else + /* Perform board-specific initialization */ -#ifdef CONFIG_SENSORS_L3GD20 - ret = stm32_l3gd20initialize("/dev/gyr0"); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize l3gd20 sensor: %d\n", ret); - } + return stm32_bringup(); #endif - - return OK; } + +#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/stm32f429i-disco/src/stm32_boot.c b/configs/stm32f429i-disco/src/stm32_boot.c index cc1f669d056b93c07d865ff585eb5b6bbdf99a6a..8af811400a36cafede6a7118773accbb5cfc6c23 100644 --- a/configs/stm32f429i-disco/src/stm32_boot.c +++ b/configs/stm32f429i-disco/src/stm32_boot.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/stm32f429i-disco/src/stm32_boot.c * - * Copyright (C) 2011-2012, 2015-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012, 2015-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -159,7 +159,7 @@ void stm32_boardinitialize(void) * If CONFIG_BOARD_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a * function called board_initialize(). board_initialize() will be - * called immediately after up_initialize() is called and just before the + * called immediately after up_intiialize() is called and just before the * initial application is started. This additional initialization phase * may be used, for example, to initialize board-specific device drivers. * @@ -168,25 +168,8 @@ void stm32_boardinitialize(void) #ifdef CONFIG_BOARD_INITIALIZE void board_initialize(void) { -#ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE - /* Initialize the framebuffer driver */ + /* Perform board-specific initialization */ - up_fbinitialize(0); -#endif - -#ifdef CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE - /* Initialize the SPI-based LCD early */ - - board_lcd_initialize(); -#endif - -#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL) - /* Perform NSH initialization here instead of from the NSH. This - * alternative NSH initialization is necessary when NSH is ran in user-space - * but the initialization function must run in kernel space. - */ - - (void)board_app_initialize(0); -#endif + (void)stm32_bringup(); } #endif diff --git a/configs/stm32f429i-disco/src/stm32_bringup.c b/configs/stm32f429i-disco/src/stm32_bringup.c new file mode 100644 index 0000000000000000000000000000000000000000..3ba8a5c21336a266ec2316455136ff7395b8c50e --- /dev/null +++ b/configs/stm32f429i-disco/src/stm32_bringup.c @@ -0,0 +1,358 @@ +/**************************************************************************** + * config/stm32f429i-disco/src/stm32_bringup.c + * + * Copyright (C) 2012, 2015-2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_STM32_SPI4 +# include +#endif + +#ifdef CONFIG_MTD_SST25XX +# include +#endif + +#ifdef CONFIG_VIDEO_FB +# include +#endif + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifndef CONFIG_STM32F429I_DISCO_FLASH_MINOR +#define CONFIG_STM32F429I_DISCO_FLASH_MINOR 0 +#endif + +#ifdef CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART +#ifdef CONFIG_PLATFORM_CONFIGDATA +# include +#endif +#endif + +#ifdef CONFIG_STM32_OTGHS +# include "stm32_usbhost.h" +#endif + +#include "stm32.h" +#include "stm32f429i-disco.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#if defined(CONFIG_STM32_SPI4) + FAR struct spi_dev_s *spi; + FAR struct mtd_dev_s *mtd; + FAR struct mtd_geometry_s geo; +#endif +#if defined(CONFIG_MTD_PARTITION_NAMES) + FAR const char *partname = CONFIG_STM32F429I_DISCO_FLASH_PART_NAMES; +#endif + int ret; + +#ifdef HAVE_PROC + /* mount the proc filesystem */ + + ret = mount(NULL, CONFIG_NSH_PROC_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount the PROC filesystem: %d (%d)\n", + ret, errno); + return ret; + } +#endif + + /* Configure SPI-based devices */ + +#ifdef CONFIG_STM32_SPI4 + /* Get the SPI port */ + + syslog(LOG_INFO, "Initializing SPI port 4\n"); + + spi = stm32_spibus_initialize(4); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 4\n"); + return -ENODEV; + } + + syslog(LOG_INFO, "Successfully initialized SPI port 4\n"); + + /* Now bind the SPI interface to the SST25F064 SPI FLASH driver. This + * is a FLASH device that has been added external to the board (i.e. + * the board does not ship from STM with any on-board FLASH. + */ + +#if defined(CONFIG_MTD) && defined(CONFIG_MTD_SST25XX) + syslog(LOG_INFO, "Bind SPI to the SPI flash driver\n"); + + mtd = sst25xx_initialize(spi); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: Failed to bind SPI port 4 to the SPI FLASH driver\n"); + } + else + { + syslog(LOG_INFO, "Successfully bound SPI port 4 to the SPI FLASH driver\n"); + + /* Get the geometry of the FLASH device */ + + ret = mtd->ioctl(mtd, MTDIOC_GEOMETRY, (unsigned long)((uintptr_t)&geo)); + if (ret < 0) + { + ferr("ERROR: mtd->ioctl failed: %d\n", ret); + return ret; + } + +#ifdef CONFIG_STM32F429I_DISCO_FLASH_PART + { + int partno; + int partsize; + int partoffset; + int partszbytes; + int erasesize; + const char *partstring = CONFIG_STM32F429I_DISCO_FLASH_PART_LIST; + const char *ptr; + FAR struct mtd_dev_s *mtd_part; + char partref[4]; + + /* Now create a partition on the FLASH device */ + + partno = 0; + ptr = partstring; + partoffset = 0; + + /* Get the Flash erase size */ + + erasesize = geo.erasesize; + + while (*ptr != '\0') + { + /* Get the partition size */ + + partsize = atoi(ptr); + partszbytes = (partsize << 10); /* partsize is defined in KB */ + + /* Check if partition size is bigger then erase block */ + + if (partszbytes < erasesize) + { + ferr("ERROR: Partition size is lesser than erasesize!\n"); + return -1; + } + + /* Check if partition size is multiple of erase block */ + + if ((partszbytes % erasesize) != 0) + { + ferr("ERROR: Partition size is not multiple of erasesize!\n"); + return -1; + } + + mtd_part = mtd_partition(mtd, partoffset, partszbytes / erasesize); + partoffset += partszbytes / erasesize; + +#ifdef CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART + /* Test if this is the config partition */ + + if (CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART_NUMBER == partno) + { + /* Register the partition as the config device */ + + mtdconfig_register(mtd_part); + } + else +#endif + { + /* Now initialize a SMART Flash block device and bind it + * to the MTD device. + */ + +#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) + sprintf(partref, "p%d", partno); + smart_initialize(CONFIG_STM32F429I_DISCO_FLASH_MINOR, mtd_part, partref); +#endif + } + +#if defined(CONFIG_MTD_PARTITION_NAMES) + /* Set the partition name */ + + if (mtd_part == NULL) + { + ferr("ERROR: failed to create partition %s\n", partname); + return -1; + } + + mtd_setpartitionname(mtd_part, partname); + + /* Now skip to next name. We don't need to split the string here + * because the MTD partition logic will only display names up to + * the comma, thus allowing us to use a single static name + * in the code. + */ + + while (*partname != ',' && *partname != '\0') + { + /* Skip to next ',' */ + + partname++; + } + + if (*partname == ',') + { + partname++; + } +#endif + + /* Update the pointer to point to the next size in the list */ + + while ((*ptr >= '0') && (*ptr <= '9')) + { + ptr++; + } + + if (*ptr == ',') + { + ptr++; + } + + /* Increment the part number */ + + partno++; + } + } +#else /* CONFIG_STM32F429I_DISCO_FLASH_PART */ + + /* Configure the device with no partition support */ + + smart_initialize(CONFIG_STM32F429I_DISCO_FLASH_MINOR, mtd, NULL); + +#endif /* CONFIG_STM32F429I_DISCO_FLASH_PART */ + } + +#endif /* CONFIG_MTD */ +#endif /* CONFIG_STM32_SPI4 */ + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_RAMMTD) && defined(CONFIG_STM32F429I_DISCO_RAMMTD) + /* Create a RAM MTD device if configured */ + + { + uint8_t *start = (uint8_t *) kmm_malloc(CONFIG_STM32F429I_DISCO_RAMMTD_SIZE * 1024); + mtd = rammtd_initialize(start, CONFIG_STM32F429I_DISCO_RAMMTD_SIZE * 1024); + mtd->ioctl(mtd, MTDIOC_BULKERASE, 0); + + /* Now initialize a SMART Flash block device and bind it to the MTD device */ + +#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) + smart_initialize(CONFIG_STM32F429I_DISCO_RAMMTD_MINOR, mtd, NULL); +#endif + } + +#endif /* CONFIG_RAMMTD && CONFIG_STM32F429I_DISCO_RAMMTD */ + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a thread + * will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_L3GD20 + ret = stm32_l3gd20initialize("/dev/gyr0"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize l3gd20 sensor: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/configs/stm32f429i-disco/src/stm32_lcd.c b/configs/stm32f429i-disco/src/stm32_lcd.c index bfce19f342a2f882cef09dc10b43e42a1a0001e1..ab4d43ae38941781394eecc9a23a7e9d58981309 100644 --- a/configs/stm32f429i-disco/src/stm32_lcd.c +++ b/configs/stm32f429i-disco/src/stm32_lcd.c @@ -47,7 +47,6 @@ #include #include -#include #include #include "up_arch.h" diff --git a/configs/stm32f429i-disco/src/stm32f429i-disco.h b/configs/stm32f429i-disco/src/stm32f429i-disco.h index e9408e3355b1f3b7ec84699b73a2d3be5e54ca62..46355dcdc112a50be3ff8c90407c74a342dfe4b9 100644 --- a/configs/stm32f429i-disco/src/stm32f429i-disco.h +++ b/configs/stm32f429i-disco/src/stm32f429i-disco.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * configs/stm32f429i-disco/src/stm32f429i-disco.h * * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. @@ -32,14 +32,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __CONFIGS_STM32F429I_DISCO_SRC_STM32F429I_DISCO__H #define __CONFIGS_STM32F429I_DISCO_SRC_STM32F429I_DISCO__H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include @@ -49,10 +49,57 @@ #include #endif -/**************************************************************************************************** +#include + +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ -/* Configuration ************************************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_PROC 1 +#define HAVE_USBDEV 1 +#define HAVE_USBHOST 1 +#define HAVE_USBMONITOR 1 + +/* Can't support USB host or device features if USB OTG HS is not enabled */ + +#ifndef CONFIG_STM32_OTGHS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +# undef HAVE_USBMONITOR +#endif + +/* Can't support USB device monitor if USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +# undef HAVE_USBMONITOR +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/* Check if we should enable the USB monitor before starting NSH */ + +#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_USBMONITOR) +# undef HAVE_USBMONITOR +#endif + +/* Check if we have the procfs file system */ + +#if !defined(CONFIG_FS_PROCFS) +# undef HAVE_PROC +#endif + +#if defined(HAVE_PROC) && defined(CONFIG_DISABLE_MOUNTPOINT) +# warning Mountpoints disabled. No procfs support +# undef HAVE_PROC +#endif + /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 @@ -76,7 +123,7 @@ #define GPIO_IO_EXPANDER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN15) -/* STM32F429 Discovery GPIOs **************************************************************************/ +/* STM32F429 Discovery GPIOs ************************************************/ /* LEDs */ #define GPIO_LED1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ @@ -136,102 +183,127 @@ # define GPIO_OTGHS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5) #endif -/**************************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************************/ + ****************************************************************************/ + +/**************************************************************************** -/**************************************************************************************************** * Public data - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/**************************************************************************************************** +/**************************************************************************** + * Public Functions - ****************************************************************************************************/ + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ -/**************************************************************************************************** +int stm32_bringup(void); + +/**************************************************************************** * Name: stm32_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the stm32f429i-disco board. + * Called to configure SPI chip select GPIO pins for the stm32f429i-disco + * board. * - ****************************************************************************************************/ + ****************************************************************************/ void weak_function stm32_spidev_initialize(void); -/**************************************************************************************************** +/**************************************************************************** * Name: stm32_usbinitialize * * Description: * Called from stm32_usbinitialize very early in inialization to setup USB-related * GPIO pins for the STM32F429Discovery board. * - ****************************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_STM32_OTGHS void weak_function stm32_usbinitialize(void); #endif -/**************************************************************************************************** +/**************************************************************************** * Name: stm32_usbhost_initialize * * Description: - * Called at application startup time to initialize the USB host functionality. This function will - * start a thread that will monitor for device connection/disconnection events. + * Called at application startup time to initialize the USB host + * functionality. This function will start a thread that will monitor for + * device connection/disconnection events. * - ****************************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_STM32_OTGHS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif -/**************************************************************************************************** +/**************************************************************************** + * Name: stm32_enablefsmc * * Description: * enable clocking to the FSMC module * - ****************************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_STM32_FSMC void stm32_enablefsmc(void); #endif -/**************************************************************************************************** +/**************************************************************************** + * Name: stm32_disablefsmc * * Description: * enable clocking to the FSMC module * - ****************************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_STM32_FSMC void stm32_disablefsmc(void); #endif -/**************************************************************************************************** +/**************************************************************************** * Name: stm32_ledpminitialize * * Description: - * Enable logic to use the LEDs on the STM32F429Discovery to support power management testing + * Enable logic to use the LEDs on the STM32F429Discovery to support + * power management testing * - ****************************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_PM void stm32_ledpminitialize(void); #endif -/**************************************************************************************************** +/**************************************************************************** + * Name: stm32_pmbuttons * * Description: * Configure the user button of the STM32F429I-DISCO board as EXTI, * so it is able to wakeup the MCU from the PM_STANDBY mode * - ****************************************************************************************************/ + ****************************************************************************/ -#if defined(CONFIG_PM) && defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) +#if defined(CONFIG_PM) && defined(CONFIG_ARCH_IDLE_CUSTOM) && \ + defined(CONFIG_PM_BUTTONS) void stm32_pmbuttons(void); #endif @@ -245,8 +317,8 @@ void stm32_pmbuttons(void); * * Returned Value: * On success, this function returns a reference to the LCD control object - * for the specified ILI9341 LCD Single chip driver connected as 4 wire serial - * (spi). NULL is returned on any failure. + * for the specified ILI9341 LCD Single chip driver connected as 4 wire + * serial (spi). NULL is returned on any failure. * ****************************************************************************/ @@ -264,9 +336,9 @@ FAR struct ili9341_lcd_s *stm32_ili93414ws_initialize(void); * register, it isn't safe to disable the spi device outside of the nuttx * spi interface structure. But this has to be done as long as the nuttx * spi interface doesn't support bidirectional data transfer for multiple - * devices share one spi bus. This wrapper does nothing else than store the - * initialized state of the spi device after the first initializing and - * should be used by each driver who shares the spi5 bus. + * devices share one spi bus. This wrapper does nothing else than store + * the initialized state of the spi device after the first initializing + * and should be used by each driver who shares the spi5 bus. * * Input Parameter: * None @@ -301,4 +373,3 @@ int stm32_l3gd20initialize(FAR const char *devpath); #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_STM32F429I_DISCO_SRC_STM32F429I_DISCO_H */ - diff --git a/configs/stm32f429i-disco/usbmsc/defconfig b/configs/stm32f429i-disco/usbmsc/defconfig index ed9ff1bfde499118106c894d0f2aa1425512ef9d..7f6e1cd8e5ff8b2f930864f276d4270c38738f1e 100644 --- a/configs/stm32f429i-disco/usbmsc/defconfig +++ b/configs/stm32f429i-disco/usbmsc/defconfig @@ -16,6 +16,7 @@ CONFIG_DISABLE_POLL=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y CONFIG_EXAMPLES_NSH=y CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HEAP2_BASE=0xD0000000 diff --git a/configs/stm32f429i-disco/usbnsh/defconfig b/configs/stm32f429i-disco/usbnsh/defconfig index 67ff0112e9697943b1643e0dcd0bc8e82da18a3a..9d2c2356fceea1c9540527fabcb52b5f7fb1cdb3 100644 --- a/configs/stm32f429i-disco/usbnsh/defconfig +++ b/configs/stm32f429i-disco/usbnsh/defconfig @@ -23,6 +23,7 @@ CONFIG_DISABLE_POLL=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y CONFIG_EXAMPLES_NSH=y CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HEAP2_BASE=0xD0000000 diff --git a/configs/stm32f4discovery/Kconfig b/configs/stm32f4discovery/Kconfig index d243b30d8bfadaa117d14e6385e3cc05a8232aff..a33d3345db4d3f1833920dfc311e72dc50ed4ea3 100644 --- a/configs/stm32f4discovery/Kconfig +++ b/configs/stm32f4discovery/Kconfig @@ -47,7 +47,7 @@ config STM32F4DISCO_USBHOST_PRIO config STM32F4DISCO_QETIMER int "Timer to use with QE encoder" default 2 - depends on QENCODER + depends on SENSORS_QENCODER config STM32F4DISCO_LIS3DSH bool "Enable LIS3DSH driver for the IMU on STM32F4Discovery (rev. MB997C)" diff --git a/configs/stm32f4discovery/README.txt b/configs/stm32f4discovery/README.txt index ccad49bab81c8149416bdeb9d301a018f715895b..1cead4669e6f1277f4b791f337528cae2bcfef63 100644 --- a/configs/stm32f4discovery/README.txt +++ b/configs/stm32f4discovery/README.txt @@ -33,6 +33,7 @@ Contents - PWM - UARTs - Timer Inputs/Outputs + - Nintendo Wii Nunchuck - Quadrature Encoder - FPU - STM32F4DIS-BB @@ -218,6 +219,39 @@ TIM14 free I/O pins. ** Port H pins are not supported by the MCU +Nintendo Wii Nunchuck: +====================== + + There is a driver on NuttX to support Nintendo Wii Nunchuck Joystick. If you + want to use it please select these options: + + - Enable the I2C1 at System Type -> STM32 Peripheral Support, it will enable: + + CONFIG_STM32_I2C1=y + + - Enable to Custom board/driver initialization at RTOS Features -> RTOS hooks + + CONFIG_BOARD_INITIALIZE=y + + - Enable the I2C Driver Support at Device Drivers, it will enable this symbol: + + CONFIG_I2C=y + + - Nintendo Wii Nunchuck Joystick at Device Drivers -> [*] Input Device Support + + CONFIG_INPUT=y + CONFIG_INPUT_NUNCHUCK=y + + - Enable the Nunchuck joystick example at Application Configuration -> Examples + + CONFIG_EXAMPLES_NUNCHUCK=y + CONFIG_EXAMPLES_NUNCHUCK_DEVNAME="/dev/nunchuck0" + + You need to connect GND and +3.3V pins from Nunchuck connector to GND and 3V + of stm32f4discovery respectively (Nunchuck also can work connected to 5V, but + I don't recommend it). Connect I2C Clock from Nunchuck to SCK (PB6) and the + I2C Data to SDA (PB9). + Quadrature Encoder: =================== diff --git a/configs/stm32f4discovery/include/board.h b/configs/stm32f4discovery/include/board.h index 273c8945b2d0bebfe6a0aa7bea4df469e72573e4..1d546599eec96ac9c078c60af69ac0e7fd388663 100644 --- a/configs/stm32f4discovery/include/board.h +++ b/configs/stm32f4discovery/include/board.h @@ -47,12 +47,6 @@ # include #endif -#ifdef __KERNEL__ -# include "stm32_rcc.h" -# include "stm32_sdio.h" -# include "stm32.h" -#endif - /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -319,13 +313,6 @@ #define DMACHAN_I2S3_RX DMAMAP_SPI3_RX_2 #define DMACHAN_I2S3_TX DMAMAP_SPI3_TX_2 -/* I2C config to use with Nunchuk PB7 (SDA) and PB8 (SCL) */ - -#if 0 -#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 -#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 -#endif - /* I2C. Only I2C1 is available on the stm32f4discovery. I2C1_SCL and I2C1_SDA are * available on the following pins: * @@ -379,41 +366,4 @@ #define DMAMAP_SDIO DMAMAP_SDIO_1 -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_STM32F4DISCOVERY_INCLUDE_BOARD_H */ diff --git a/configs/stm32f4discovery/nxlines/defconfig b/configs/stm32f4discovery/nxlines/defconfig index 16c0c06c6f331972e4843ee3f1d351ea4e14b13b..835c2f692e406a23a745c3bc5be004f369e80a86 100644 --- a/configs/stm32f4discovery/nxlines/defconfig +++ b/configs/stm32f4discovery/nxlines/defconfig @@ -2,6 +2,7 @@ # CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set # CONFIG_NX_DISABLE_16BPP is not set # CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BOARD="stm32f4discovery" diff --git a/configs/stm32f4discovery/rndis/defconfig b/configs/stm32f4discovery/rndis/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..072f3cf4a5804cfc868b584b00360360cf9c43ac --- /dev/null +++ b/configs/stm32f4discovery/rndis/defconfig @@ -0,0 +1,102 @@ +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_ERROR=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_NET_ERROR=y +CONFIG_DEBUG_NET=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_WARN=y +CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y +CONFIG_EXAMPLES_NSH=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HAVE_CXX=y +CONFIG_HOST_WINDOWS=y +CONFIG_INTELHEX_BINARY=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +# CONFIG_MMCSD_MMCSUPPORT is not set +CONFIG_MMCSD_MULTIBLOCK_DISABLE=y +CONFIG_MMCSD_SDIO=y +# CONFIG_MMCSD_SPI is not set +CONFIG_MMCSD=y +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BROADCAST=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 +CONFIG_NETDEVICES=y +CONFIG_NET_ICMP=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_ARGCAT is not set +CONFIG_NSH_BUILTIN_APPS=y +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_NSH_DHCPC=y +# CONFIG_NSH_DISABLE_DATE is not set +CONFIG_NSH_DRIPADDR=0x0 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=128 +CONFIG_NSH_MACADDR=0x00e0deadcafe +CONFIG_NSH_NETINIT_THREAD=y +CONFIG_NSH_NETMASK=0x0 +CONFIG_NSH_NOMAC=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RNDIS=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SENSORS=y +CONFIG_START_DAY=13 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2014 +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32F4DISBB=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +# CONFIG_STM32_SDIO_DMA is not set +CONFIG_STM32_SDIO=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y +CONFIG_USART6_RXBUFSIZE=64 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USART6_TXBUFSIZE=64 +CONFIG_USBDEV=y +CONFIG_USER_ENTRYPOINT="nsh_main" diff --git a/configs/stm32f4discovery/src/Makefile b/configs/stm32f4discovery/src/Makefile index e6ef059bfaa2dfbb8546e61f650bfc15b6b7fa04..535440d6e52683e28a397310db81ba60d5c1beea 100644 --- a/configs/stm32f4discovery/src/Makefile +++ b/configs/stm32f4discovery/src/Makefile @@ -68,6 +68,14 @@ ifeq ($(CONFIG_SENSORS_BMP180),y) CSRCS += stm32_bmp180.c endif +ifeq ($(CONFIG_LCD_ST7567),y) + CSRCS += stm32_st7567.c +endif + +ifeq ($(CONFIG_INPUT_NUNCHUCK),y) + CSRCS += stm32_nunchuck.c +endif + ifeq ($(CONFIG_SENSORS_MAX31855),y) CSRCS += stm32_max31855.c endif @@ -168,4 +176,10 @@ ifeq ($(CONFIG_USBMSC),y) CSRCS += stm32_usbmsc.c endif +ifneq ($(CONFIG_STM32_ETHMAC),y) +ifeq ($(CONFIG_NETDEVICES),y) +CSRCS += stm32_netinit.c +endif +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/stm32f4discovery/src/stm32_boot.c b/configs/stm32f4discovery/src/stm32_boot.c index 483f5edd13bf72eafb3231950944752ca52c6847..dff5e62ca2a031dc3d8314b3822dc8a3d361634c 100644 --- a/configs/stm32f4discovery/src/stm32_boot.c +++ b/configs/stm32f4discovery/src/stm32_boot.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * configs/stm32f4discovery/src/stm32_boot.c * * Copyright (C) 2011-2012, 2015 Gregory Nutt. All rights reserved. @@ -31,11 +31,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -45,27 +45,30 @@ #include #include "up_arch.h" + +#include "stm32.h" #include "stm32f4discovery.h" -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: stm32_boardinitialize * * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. * - ************************************************************************************/ + ****************************************************************************/ void stm32_boardinitialize(void) { #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function - * stm32_spidev_initialize() has been brought into the link. + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. */ if (stm32_spidev_initialize) diff --git a/configs/stm32f4discovery/src/stm32_bringup.c b/configs/stm32f4discovery/src/stm32_bringup.c index 22fbf97830bdadd1b2ddbd2ba10f2c1f383f4f59..16349a413c32fcaa1d50254540dcda92570af735 100644 --- a/configs/stm32f4discovery/src/stm32_bringup.c +++ b/configs/stm32f4discovery/src/stm32_bringup.c @@ -66,6 +66,10 @@ # include #endif +#ifdef CONFIG_RNDIS +# include +#endif + #include "stm32f4discovery.h" /* Conditional logic in stm32f4discovery.h will determine if certain features @@ -129,6 +133,16 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + #ifdef HAVE_SDIO /* Initialize the SDIO block driver */ @@ -194,6 +208,16 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_INPUT_NUNCHUCK + /* Register the Nunchuck driver */ + + ret = nunchuck_initialize("/dev/nunchuck0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: nunchuck_initialize() failed: %d\n", ret); + } +#endif + #ifdef CONFIG_SENSORS_QENCODER /* Initialize and register the qencoder driver */ @@ -315,5 +339,16 @@ int stm32_bringup(void) } #endif +#if defined(CONFIG_RNDIS) && defined(CONFIG_NSH_MACADDR) + uint8_t mac[6]; + mac[0] = 0xaa; /* TODO */ + mac[1] = (CONFIG_NSH_MACADDR >> (8 * 4)) & 0xff; + mac[2] = (CONFIG_NSH_MACADDR >> (8 * 3)) & 0xff; + mac[3] = (CONFIG_NSH_MACADDR >> (8 * 2)) & 0xff; + mac[4] = (CONFIG_NSH_MACADDR >> (8 * 1)) & 0xff; + mac[5] = (CONFIG_NSH_MACADDR >> (8 * 0)) & 0xff; + usbdev_rndis_initialize(mac); +#endif + return ret; } diff --git a/configs/stm32f4discovery/src/stm32_buttons.c b/configs/stm32f4discovery/src/stm32_buttons.c index 2b805075e003450329f24abcca24d59dde9214d8..5a8d4d5dc2545cd5220ec87c778fd30a17ecadc0 100644 --- a/configs/stm32f4discovery/src/stm32_buttons.c +++ b/configs/stm32f4discovery/src/stm32_buttons.c @@ -46,6 +46,7 @@ #include #include +#include "stm32.h" #include "stm32f4discovery.h" #ifdef CONFIG_ARCH_BUTTONS diff --git a/configs/stm32f4discovery/src/stm32_extmem.c b/configs/stm32f4discovery/src/stm32_extmem.c index 3717317fd5fbcdc96b03a38dae10fdf59f4e4c6d..f5f531e06801f1b94aacbff336cef5671d0e1e97 100644 --- a/configs/stm32f4discovery/src/stm32_extmem.c +++ b/configs/stm32f4discovery/src/stm32_extmem.c @@ -48,8 +48,6 @@ #include "chip.h" #include "up_arch.h" -#include "stm32_fsmc.h" -#include "stm32_gpio.h" #include "stm32.h" #include "stm32f4discovery.h" diff --git a/configs/stm32f4discovery/src/stm32_lis3dsh.c b/configs/stm32f4discovery/src/stm32_lis3dsh.c index e6c6de1645363b78d3e2ee08efaaeef3630c5781..b48a5614fa5a106e68491ac8f34bf19aea7ecdb4 100644 --- a/configs/stm32f4discovery/src/stm32_lis3dsh.c +++ b/configs/stm32f4discovery/src/stm32_lis3dsh.c @@ -47,8 +47,6 @@ #include "stm32.h" #include "stm32f4discovery.h" -#include -#include #if defined(CONFIG_STM32F4DISCO_LIS3DSH) && defined(CONFIG_LIS3DSH) diff --git a/configs/stm32f4discovery/src/stm32_netinit.c b/configs/stm32f4discovery/src/stm32_netinit.c new file mode 100644 index 0000000000000000000000000000000000000000..5cc73b4a5390a769ef4b0ddfe81651075bab7aab --- /dev/null +++ b/configs/stm32f4discovery/src/stm32_netinit.c @@ -0,0 +1,52 @@ +/************************************************************************************ + * config/stm32f4discovery/src/stm32_netinit.c + * + * Copyright (C) 2017 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: up_netinitialize + ************************************************************************************/ + +void up_netinitialize(void) +{ +} diff --git a/configs/stm32f4discovery/src/stm32_nunchuck.c b/configs/stm32f4discovery/src/stm32_nunchuck.c new file mode 100644 index 0000000000000000000000000000000000000000..1a38c059772e96b767ba9eda2a587046ad49cff2 --- /dev/null +++ b/configs/stm32f4discovery/src/stm32_nunchuck.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * configs/stm32f4discovery/src/stm32_nunchuck.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32_i2c.h" +#include "stm32f4discovery.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NUNCHUCK_I2C_PORTNO 1 /* On I2C1 */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nunchuck_initialize + * + * Description: + * Initialize and register the Nunchuck joystick driver + * + ****************************************************************************/ + +int nunchuck_initialize(FAR char *devname) +{ + FAR struct i2c_master_s *i2c; + int ret; + + iinfo("Initializing Wii Nunchuck!\n"); + + /* Initialize I2C */ + + i2c = stm32_i2cbus_initialize(NUNCHUCK_I2C_PORTNO); + if (i2c == NULL) + { + return -ENODEV; + } + + /* Register the joystick device as /dev/nunchuck0 */ + + iinfo("Initialize joystick driver: %s\n", devname); + + ret = nunchuck_register(devname, i2c); + if (ret < 0) + { + ierr("ERROR: nunchuck_register failed: %d\n", ret); + } + + return ret; +} diff --git a/configs/stm32f4discovery/src/stm32_spi.c b/configs/stm32f4discovery/src/stm32_spi.c index 9744fdf7451ea4e81f378580e0f287ff60ff4de9..b6c583c403ea4e04398523861b6ce69b27aab63a 100644 --- a/configs/stm32f4discovery/src/stm32_spi.c +++ b/configs/stm32f4discovery/src/stm32_spi.c @@ -75,6 +75,9 @@ void weak_function stm32_spidev_initialize(void) #if defined(CONFIG_STM32_SPI2) && defined(CONFIG_SENSORS_MAX31855) (void)stm32_configgpio(GPIO_MAX31855_CS); /* MAX31855 chip select */ #endif +#if defined(CONFIG_LCD_ST7567) + (void)stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ +#endif #if defined(CONFIG_STM32_SPI2) && defined(CONFIG_SENSORS_MAX6675) (void)stm32_configgpio(GPIO_MAX6675_CS); /* MAX6675 chip select */ #endif @@ -120,6 +123,12 @@ void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +#ifdef CONFIG_LCD_ST7567 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } +#endif #if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) || \ defined(CONFIG_LCD_SSD1351) if (devid == SPIDEV_DISPLAY(0)) @@ -203,6 +212,18 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) #ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) { +#ifdef CONFIG_LCD_ST7567 + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + (void)stm32_gpiowrite(STM32_LCD_RS, !cmd); + + return OK; + } +#endif #if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) || \ defined(CONFIG_LCD_SSD1351) if (devid == SPIDEV_DISPLAY(0)) diff --git a/configs/stm32f4discovery/src/stm32_st7567.c b/configs/stm32f4discovery/src/stm32_st7567.c new file mode 100644 index 0000000000000000000000000000000000000000..e1f9d0262f65a4883ee0b54306bcee566ad2d98b --- /dev/null +++ b/configs/stm32f4discovery/src/stm32_st7567.c @@ -0,0 +1,153 @@ +/**************************************************************************** + * configs/stm32f4discovery/src/stm32_st7567.c + * + * Copyright (C) 2016 Uniquix Tecnologia. All rights reserved. + * Author: Alan Carvalho de Assis + * + * I used the JLX12864G-086 LCD module based on ST7567 controller. + * + * Based on configs/zkit-arm-1769/src/lpc17_lcd.c + * + * Copyright (C) 2013 Zilogic Systems. All rights reserved. + * Author: Manikandan + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "stm32_gpio.h" +#include "stm32_spi.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_LCD_ST7567 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LCD_SPI_PORTNO 1 /* On SPI1 */ + +#ifndef CONFIG_LCD_CONTRAST +# define CONFIG_LCD_CONTRAST 0x1f +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +FAR struct spi_dev_s *g_spidev; +FAR struct lcd_dev_s *g_lcddev; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + stm32_configgpio(STM32_LCD_RST); + stm32_configgpio(STM32_LCD_RS); + stm32_gpiowrite(STM32_LCD_RST, 1); + stm32_gpiowrite(STM32_LCD_RS, 1); + + g_spidev = stm32_spibus_initialize(LCD_SPI_PORTNO); + + if (!g_spidev) + { + lcderr("ERROR: Failed to initialize SPI port %d\n", LCD_SPI_PORTNO); + return 0; + } + + stm32_gpiowrite(STM32_LCD_RST, 0); + up_mdelay(1); + stm32_gpiowrite(STM32_LCD_RST, 1); + return 1; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +FAR struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + g_lcddev = st7567_initialize(g_spidev, lcddev); + if (!g_lcddev) + { + lcderr("ERROR: Failed to bind SPI port 1 to LCD %d: %d\n", lcddev); + } + else + { + lcdinfo("SPI port 1 bound to LCD %d\n", lcddev); + + /* And turn the LCD on (CONFIG_LCD_MAXPOWER should be 1) */ + + (void)g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER); + + /* Set contrast to right value, otherwise background too dark */ + + (void)g_lcddev->setcontrast(g_lcddev, CONFIG_LCD_CONTRAST); + + return g_lcddev; + } + + return NULL; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} + +#endif /* CONFIG_LCD_ST7567 */ diff --git a/configs/stm32f4discovery/src/stm32_userleds.c b/configs/stm32f4discovery/src/stm32_userleds.c index 392b14f73e6b23e89a9c5a482d282c4748ab3de8..d5e301f5d465a3194536ef75659637ae6d050840 100644 --- a/configs/stm32f4discovery/src/stm32_userleds.c +++ b/configs/stm32f4discovery/src/stm32_userleds.c @@ -50,6 +50,7 @@ #include "chip.h" #include "up_arch.h" #include "up_internal.h" + #include "stm32.h" #include "stm32f4discovery.h" diff --git a/configs/stm32f4discovery/src/stm32_zerocross.c b/configs/stm32f4discovery/src/stm32_zerocross.c index aff78fba2b1b82c7b4d397f0ea67ca9ff4bb7728..d0e74c6a01cbcb812e8c16ecaccbe37403459e74 100644 --- a/configs/stm32f4discovery/src/stm32_zerocross.c +++ b/configs/stm32f4discovery/src/stm32_zerocross.c @@ -51,14 +51,6 @@ #ifdef CONFIG_SENSORS_ZEROCROSS -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - /**************************************************************************** * Private Function Prototypes ****************************************************************************/ diff --git a/configs/stm32f4discovery/src/stm32f4discovery.h b/configs/stm32f4discovery/src/stm32f4discovery.h index d3e135975e90272589676ceff4b4c990aa04821e..51936d9485a0269a50351e62cd441e851dba3200 100644 --- a/configs/stm32f4discovery/src/stm32f4discovery.h +++ b/configs/stm32f4discovery/src/stm32f4discovery.h @@ -322,6 +322,17 @@ # define GPIO_OLED_DC GPIO_OLED_A0 #endif +/* Display JLX12864G */ + +#define STM32_LCD_RST (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN6) + +#define STM32_LCD_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN7) + +#define STM32_LCD_RS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) + /* STM32F4DIS-BB MicroSD * * ---------- ------------- ------------------------------ @@ -381,6 +392,22 @@ * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void); + /**************************************************************************** * Name: stm32_spidev_initialize * @@ -443,20 +470,16 @@ int stm32_lis3dshinitialize(FAR const char *devpath); #endif /**************************************************************************** - * Name: stm32_bringup + * Name: nunchuck_initialize * * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_INITIALIZE=y : - * Called from board_initialize(). - * - * CONFIG_BOARD_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : - * Called from the NSH library + * Initialize and register the button joystick driver * ****************************************************************************/ -int stm32_bringup(void); +#ifdef CONFIG_INPUT_NUNCHUCK +int nunchuck_initialize(FAR char *devname); +#endif /**************************************************************************** * Name: stm32_usbinitialize diff --git a/configs/stm32f746-ws/include/board.h b/configs/stm32f746-ws/include/board.h index d8c80f0677c46e6f36453c133e912763b66d8842..55b0cf97a7cc4917dc887afd4f6065ccd07c66bc 100644 --- a/configs/stm32f746-ws/include/board.h +++ b/configs/stm32f746-ws/include/board.h @@ -293,41 +293,4 @@ # define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #endif -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_STM32F746_WS_INCLUDE_BOARD_H */ diff --git a/configs/stm32f746g-disco/include/board.h b/configs/stm32f746g-disco/include/board.h index aed8171455d97951219fd064190a2348ef04fad6..cdc55a28b6560c1ee8a6a883c5d695d87d6c38bc 100644 --- a/configs/stm32f746g-disco/include/board.h +++ b/configs/stm32f746g-disco/include/board.h @@ -358,40 +358,4 @@ #define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2 #define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_2 -/************************************************************************************ - * Public Data - ************************************************************************************/ -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_STM32F746G_DISCO_INCLUDE_BOARD_H */ diff --git a/configs/stm32f769i-disco/include/board.h b/configs/stm32f769i-disco/include/board.h index 6cdef6b7c1d9ef0e1de4ffa6c4cf43504a2a6b9d..8473261767133fbfd25ce3e95840ee2431be1fe0 100644 --- a/configs/stm32f769i-disco/include/board.h +++ b/configs/stm32f769i-disco/include/board.h @@ -473,47 +473,4 @@ #define BOARD_LTDC_GCR_VSPOL 0 #define BOARD_LTDC_GCR_HSPOL 0 -// #define BOARD_LTDC_OUTPUT_BPP 16 - -//#define BOARD_LTDC_GCR_DEN -//#define BOARD_LTDC_GCR_DBW -//#define BOARD_LTDC_GCR_DGW -//#define BOARD_LTDC_GCR_DRW - -/************************************************************************************ - * Public Data - ************************************************************************************/ -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_STM32F769I_DISCO_INCLUDE_BOARD_H */ diff --git a/configs/stm32l476-mdk/README.txt b/configs/stm32l476-mdk/README.txt index 8b60f0d0db12891918c69e354d22564d1e9d7d74..68d1b803580ad6a7585226d780ac203a8d7051f1 100644 --- a/configs/stm32l476-mdk/README.txt +++ b/configs/stm32l476-mdk/README.txt @@ -1,8 +1,9 @@ README ====== -This README discusses issues unique to NuttX configurations for Motorola -MDK. +This README discusses issues unique to NuttX configurations for STM32L476ME +part in the Motorola MDK. This is referred to as the MuC in Motorola +technical documentation. STM32L476ME: @@ -24,12 +25,86 @@ STM32L476ME: CRC calculation unit RTC -Flashing: +Acronyms +======== -The MDK has a builtin FTDI to support flashing from openocd. There are a few extensions -to openocd that haven't been integrated upstream yet. To flash (or debug) the MDK, you -will need the code from: - git clone https://github.com/MotorolaMobilityLLC/openocd + MDK is, of course, the Motorola Development Kit. + MuC is the acronym that is used to refer to the STM32L476ME on the MDK + board. + MHB is the acronym given to Toshiba Interface Bridge, part number T6WV7XBG. + See https://toshiba.semicon-storage.com/us/product/assp/interface-bridge.html + NuttX runs the MuC. -After building, you can flash with the following command: - openocd -f board/moto_mdk_muc.cfg -c "program nuttx.bin 0x08000000 reset exit" +Flashing +======== + +The MDK has a built-in FTDI to support flashing from openocd. There are a +few extensions to openocd that haven't been integrated upstream yet. To +flash (or debug) the MDK, you will need the code from: + + $ git clone https://github.com/MotorolaMobilityLLC/openocd + +Refer to detailed OpenOCD build instructions at developer.motorola.com + +After building, you can flash the STM32L476 (MuC) with the following +command: + + $ openocd -f board/moto_mdk_muc.cfg -c "program nuttx.bin 0x08000000 reset exit" + +You may need to be super-user in order access the USB device. + +NOTE: In order for the debug Type C connector to power the phone, the DIP +Switch B4 must be in the ON position. See the MDK User Guide at +developer.motorola.com for more information on the hardware including the DIP +switches. + +Or you can use the GDB server. To start the GDB server: + + $ openocd -f board/moto_mdk_mu_reset.cfg & + +Then start GDB: + + $ arm-none-linux-gdb + (gdb) target extended-remote localhost:3333 + (gdb) set can-use-hw-watchpoints 1 + +You can load code into FLASH like: + + (gdb) mon halt + (gdb) load nuttx + (gdb) file nuttx + (gdb) mon reset + +NOTE: There is a special version of GDB 7.11 available with some additional, +MDK-specific features. It is available in a MotorolaMobilityLLC github.com +repository. + +Serial Console +============== + +The serial console is configured on USART3 using MUC_UART3_TX (PC10) and +MUC_UART_RX (PC11). This connects to the FT4232 part which supports 4 +CDC/ACM serial ports. The MuC console is on port C which will probably be +/dev/ttyUSB2 on your Linux host. Port A (ttyUSB0) is the MuC SWD debug +interface. Ports B and D are the MHB debug and console ports, respectively. + +The serial terminal that you use must be configured to use the /dev/ttyUSB2 +device at 11500 baud, no parity, 8 bits of data, 1 stop bit (115200 8N1 in +minicom-speak) and with no flow control. Minicom works well. + +You will probably need to be super-user in order access the /dev/ttyUSB2 +device: + + $ sudo minicom mdk + +When mdk is the name of my saved configuration using the above serial +configuration. + +The Motorola documentation also mentions picocom. NSH also works well with +picocom: + + $ sudo apt install picocom + $ sudo picocom -b 115200 /dev/ttyUSB2 + +Everything else defaults correctly. Ctrl-A then Ctrl-X will terminate +either the minicom or the picocom session. diff --git a/configs/stm32l476-mdk/include/board.h b/configs/stm32l476-mdk/include/board.h index 771b43e798db0cc90664b9c02cbb6be185af4d1f..82632eef8dc97a6b921948275baa27b7451c5153 100644 --- a/configs/stm32l476-mdk/include/board.h +++ b/configs/stm32l476-mdk/include/board.h @@ -45,10 +45,8 @@ # include #endif -#include - /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Clocking *************************************************************************/ @@ -74,40 +72,99 @@ /* USART */ -#define GPIO_USART1_CTS GPIO_USART1_CTS_3 /* PG11 */ +#define GPIO_USART1_CTS GPIO_USART1_CTS_3 /* PG11 */ #define GPIO_USART1_RTS GPIO_USART1_RTS_DE_2 /* PB3 */ -#define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */ -#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */ +#define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */ +#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */ -#define GPIO_USART2_CTS GPIO_USART2_CTS_1 /* PA0 */ -#define GPIO_USART2_RTS GPIO_USART2_RTS_DE_1 /* PA1 */ -#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ -#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */ +#define GPIO_USART2_CTS GPIO_USART2_CTS_1 /* PA0 */ +#define GPIO_USART2_RTS GPIO_USART2_RTS_DE_1 /* PA1 */ +#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ +#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */ -#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PC11 */ -#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PC10 */ +#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PC11 */ +#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PC10 */ /* I2C */ -#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1 /* PB10 */ -#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1 /* PB11 */ +#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1 /* PB10 */ +#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1 /* PB11 */ -#define GPIO_I2C3_SCL GPIO_I2C3_SCL_1 /* PC0 */ -#define GPIO_I2C3_SDA GPIO_I2C3_SDA_1 /* PC1 */ +#define GPIO_I2C3_SCL GPIO_I2C3_SCL_1 /* PC0 */ +#define GPIO_I2C3_SDA GPIO_I2C3_SDA_1 /* PC1 */ /* SPI */ -#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */ -#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 /* PA7 */ -#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 /* PA5 */ -#define GPIO_SPI1_NSS GPIO_SPI1_NSS_1 /* PA4 */ +#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */ +#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 /* PA7 */ +#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 /* PA5 */ +#define GPIO_SPI1_NSS GPIO_SPI1_NSS_1 /* PA4 */ #define DMACHAN_SPI1_RX DMACHAN_SPI1_RX_1 #define DMACHAN_SPI1_TX DMACHAN_SPI1_TX_1 -#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 /* PB14 */ -#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */ -#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2 /* PB13 */ -#define GPIO_SPI2_NSS GPIO_SPI2_NSS_2 /* PB12 */ +#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 /* PB14 */ +#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */ +#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2 /* PB13 */ +#define GPIO_SPI2_NSS GPIO_SPI2_NSS_2 /* PB12 */ + +/* LED definitions ******************************************************************/ +/* The Reference Moto Mod contains three LEDs. Two LEDs, are by convention, used to + * indicate the Reference Moto Mod battery state of charge, and the other is + * available for you to use in your applications. + * + * 1. The red LED on PD7. Part of the (rear-firing) red/green LED. + * 2. The green LED on PE7. Part of the (rear-firing) red/green LED. + * 3. The white (top-firing) LED on PE8 + * + * When the I/O is HIGH value, the LED is OFF. + * When the I/O is LOW, the LED is ON. + * + * Following this convention, only the white LED is made available even though they + * all could be user-application controlled if desired. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_RED_LED 0 +#define BOARD_GREEN_LED 1 +#ifndef CONFIG_ARCH_LEDS +# define BOARD_WHITE_LED 2 +# define BOARD_NLEDS 3 +#else +# define BOARD_NLEDS 2 +#endif + +/* LED bits for use with board_userled_all() */ + +#define BOARD_RED_LED_BIT (1 << BOARD_RED_LED) +#define BOARD_GREEN_LED_BIT (1 << BOARD_GREEN_LED) +#ifndef CONFIG_ARCH_LEDS +# define BOARD_WHITE_LED_BIT (1 << BOARD_WHITE_LED) +#endif + +/* None of the LEDs are used by the board port unless CONFIG_ARCH_LEDS is defined. + * In that case, the white LED (only) will be controlled. Usage by the board port + * is defined in include/board.h and src/stm32_autoleds.c. The white LED will be + * used to encode OS-related events as follows: + * + * ------------------- ---------------------------- ------ + * SYMBOL Meaning LED + * ------------------- ---------------------------- ------ */ + +#define LED_STARTED 0 /* NuttX has been started OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON */ +#define LED_INIRQ 2 /* In an interrupt N/C */ +#define LED_SIGNAL 2 /* In a signal handler N/C */ +#define LED_ASSERTION 2 /* An assertion failed N/C */ +#define LED_PANIC 3 /* The system has crashed FLASH */ +#undef LED_IDLE /* MCU is is sleep mode Not used */ + +/* Thus if the white LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If white LED is flashing at approximately 2Hz, + * then a fatal error has been detected and the system has halted. + */ /* Buttons **************************************************************************/ /* The board only has one button */ diff --git a/configs/stm32l476-mdk/nsh/defconfig b/configs/stm32l476-mdk/nsh/defconfig index aa32ff0d7e9abebdb8feec18e252814fdd3a682b..cf72907385c84560b31e7b79c8b4012a77097459 100644 --- a/configs/stm32l476-mdk/nsh/defconfig +++ b/configs/stm32l476-mdk/nsh/defconfig @@ -1,7 +1,5 @@ # CONFIG_ARCH_FPU is not set -# CONFIG_ARCH_LEDS is not set # CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_DF_H is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_NSH_CMDPARMS is not set CONFIG_ARCH_BOARD_STM32L476_MDK=y @@ -64,4 +62,6 @@ CONFIG_STM32L4_USART3=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_USERLED_LOWER=y +CONFIG_USERLED=y CONFIG_WDOG_INTRESERVE=1 diff --git a/configs/stm32l476-mdk/scripts/Make.defs b/configs/stm32l476-mdk/scripts/Make.defs index 15def1ef26b9e9221daec171c6b2b34acae3b849..b6cb7df4cc6e160228cef9547492b35f7d475960 100644 --- a/configs/stm32l476-mdk/scripts/Make.defs +++ b/configs/stm32l476-mdk/scripts/Make.defs @@ -105,10 +105,6 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y) LDFLAGS += -g endif -LDFLAGS += -Map=${TOPDIR}/nuttx.map -#CFLAGS += -Wa,-adhln -#CXXFLAGS += -Wa,-adhln - HOSTCC = gcc HOSTINCLUDES = -I. HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe diff --git a/configs/stm32l476-mdk/src/Makefile b/configs/stm32l476-mdk/src/Makefile index f74969e08b10646cef3d38a61618244e1cc403db..c5bf4f43cd3354fa349665d9d5b6c86d2e3c6d75 100644 --- a/configs/stm32l476-mdk/src/Makefile +++ b/configs/stm32l476-mdk/src/Makefile @@ -36,14 +36,18 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = stm32_boot.c stm32_spi.c +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c stm32_userleds.c ifeq ($(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG),y) CSRCS += stm32_clockconfig.c endif +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +endif + ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c +CSRCS += stm32_buttons.c endif ifeq ($(CONFIG_LIB_BOARDCTL),y) diff --git a/configs/stm32l476-mdk/src/stm32_appinit.c b/configs/stm32l476-mdk/src/stm32_appinit.c index 4e9a08b48535e4cc0995adde36e7291c5a3819f9..b03dbe964f52e997b7c05da93031303c907bc0a3 100644 --- a/configs/stm32l476-mdk/src/stm32_appinit.c +++ b/configs/stm32l476-mdk/src/stm32_appinit.c @@ -1,7 +1,7 @@ /**************************************************************************** * configs/stm32l476-mdk/src/stm32_appinit.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -39,40 +39,11 @@ #include -#include -#include -#include -#include -#include -#include -#include -#include - -#include #include -#include -#include - -#include - -#include - #include "stm32l476-mdk.h" -/* Conditional logic in stm32l476-mdk.h will determine if certain features - * are supported. Tests for these features need to be made after including - * stm32l476-mdk.h. - */ - -#ifdef HAVE_RTC_DRIVER -# include -# include "stm32l4_rtc.h" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ +#ifdef CONFIG_LIB_BOARDCTL /**************************************************************************** * Public Functions @@ -103,68 +74,17 @@ * ****************************************************************************/ -#ifdef CONFIG_LIB_BOARDCTL int board_app_initialize(uintptr_t arg) { -#ifdef HAVE_RTC_DRIVER - FAR struct rtc_lowerhalf_s *rtclower; -#endif - int ret; - - (void)ret; - -#ifdef HAVE_PROC - /* mount the proc filesystem */ +#ifdef CONFIG_BOARD_INITIALIZE + /* Board initialization already performed by board_initialize() */ - syslog(LOG_INFO, "Mounting procfs to /proc\n"); - - ret = mount(NULL, CONFIG_NSH_PROC_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to mount the PROC filesystem: %d (%d)\n", - ret, errno); - return ret; - } -#endif - -#ifdef HAVE_RTC_DRIVER - /* Instantiate the STM32 lower-half RTC driver */ - - rtclower = stm32l4_rtc_lowerhalf(); - if (!rtclower) - { - serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); - return -ENOMEM; - } - else - { - /* Bind the lower half driver and register the combined RTC driver - * as /dev/rtc0 - */ + return OK; +#else + /* Perform board-specific initialization */ - ret = rtc_initialize(0, rtclower); - if (ret < 0) - { - serr("ERROR: Failed to bind/register the RTC driver: %d\n", ret); - return ret; - } - } + return stm32_bringup(); #endif - - return OK; } -#endif /* CONFIG_LIB_BOARDCTL */ - -#if defined(CONFIG_BOARDCTL_UNIQUEID) -int board_uniqueid(uint8_t *uniqueid) -{ - if (uniqueid == 0) - { - return -EINVAL; - } - stm32l4_get_uniqueid(uniqueid); - return OK; -} -#endif +#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/stm32l476-mdk/src/stm32_autoleds.c b/configs/stm32l476-mdk/src/stm32_autoleds.c new file mode 100644 index 0000000000000000000000000000000000000000..85efaa990d0ff52293e4cdeabf8faf6d97b128e2 --- /dev/null +++ b/configs/stm32l476-mdk/src/stm32_autoleds.c @@ -0,0 +1,133 @@ +/**************************************************************************** + * configs/stm32l476-mdk/src/sam_autoleds.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The Reference Moto Mod contains three LEDs. Two LEDs, are by convention, + * used to indicate the Reference Moto Mod battery state of charge, and the + * other is available for you to use in your applications. + * + * 1. The red LED on PD7. Part of the (rear-firing) red/green LED. + * 2. The green LED on PE7. Part of the (rear-firing) red/green LED. + * 3. The white (top-firing) LED on PE8 + * + * When the I/O is HIGH value, the LED is OFF. + * When the I/O is LOW, the LED is ON. + * + * Following this convention, only the white LED is made available even though + * they all could be user-application controlled if desired. + * + * None of the LEDs are used by the board port unless CONFIG_ARCH_LEDS is defined. + * In that case, the white LED (only) will be controlled. Usage by the board port + * is defined in include/board.h and src/stm32_autoleds.c. The white LED will be + * used to encode OS-related events as follows: + * + * ------------------ ------------------------ ------ + * SYMBOL Meaning LED + * ------------------ ------------------------ ------ + * + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt N/C + * LED_SIGNAL In a signal handler N/C + * LED_ASSERTION An assertion failed N/C + * LED_PANIC The system has crashed FLASH + * LED_IDLE MCU is is sleep mode Not used + * + * Thus if the white LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If white LED is flashing at approximately 2Hz, + * then a fatal error has been detected and the system has halted. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32l4_gpio.h" +#include "stm32l476-mdk.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32l4_configgpio(GPIO_LED_RED); + stm32l4_configgpio(GPIO_LED_GREEN); + stm32l4_configgpio(GPIO_LED_WHITE); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1 || led == 3) + { + stm32l4_gpiowrite(GPIO_LED_WHITE, false); /* Low illuminates */ + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 3) + { + stm32l4_gpiowrite(GPIO_LED_WHITE, true); /* High extinguishes */ + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/stm32l476-mdk/src/stm32_boot.c b/configs/stm32l476-mdk/src/stm32_boot.c index 55b3f6af75b25207b7340a03a9cd17ac21297716..271fa28cb46365f50423f5da51229e37ab1a268c 100644 --- a/configs/stm32l476-mdk/src/stm32_boot.c +++ b/configs/stm32l476-mdk/src/stm32_boot.c @@ -67,17 +67,17 @@ void stm32l4_board_initialize(void) { +#ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ -#ifdef CONFIG_ARCH_LEDS board_autoled_initialize(); #endif +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak function * stm32_spiinitialize() has been brought into the link. */ -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) stm32l4_spiinitialize(); #endif } @@ -98,13 +98,8 @@ void stm32l4_board_initialize(void) #ifdef CONFIG_BOARD_INITIALIZE void board_initialize(void) { - /* Perform NSH initialization here instead of from the NSH. This - * alternative NSH initialization is necessary when NSH is ran in user-space - * but the initialization function must run in kernel space. - */ + /* Perform board-specific initialization */ -#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_NSH_ARCHINIT) - board_app_initialize(0); -#endif + (void)stm32_bringup(); } #endif diff --git a/configs/stm32l476-mdk/src/stm32_bringup.c b/configs/stm32l476-mdk/src/stm32_bringup.c new file mode 100644 index 0000000000000000000000000000000000000000..e3f7458d4ee2cb9bb6ad6cd3cd9b0150bc69fcd1 --- /dev/null +++ b/configs/stm32l476-mdk/src/stm32_bringup.c @@ -0,0 +1,182 @@ +/**************************************************************************** + * configs/stm32l476-mdk/src/stm32_bringup.c + * + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "stm32l4.h" +#include "stm32l4_uid.h" +#include "stm32l476-mdk.h" + +/* Conditional logic in stm32l476-mdk.h will determine if certain features + * are supported. Tests for these features need to be made after including + * stm32l476-mdk.h. + */ + +#ifdef HAVE_RTC_DRIVER +# include +# include "stm32l4_rtc.h" +#endif + +#ifdef HAVE_USERLED_DRIVER +# include +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_LIB_BOARDCTL +int board_app_initialize(uintptr_t arg) +{ +#ifdef HAVE_RTC_DRIVER + FAR struct rtc_lowerhalf_s *rtclower; +#endif + int ret; + +#ifdef HAVE_PROC + /* mount the proc filesystem */ + + syslog(LOG_INFO, "Mounting procfs to /proc\n"); + + ret = mount(NULL, CONFIG_NSH_PROC_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount the PROC filesystem: %d (%d)\n", + ret, errno); + return ret; + } +#endif + +#ifdef HAVE_RTC_DRIVER + /* Instantiate the STM32 lower-half RTC driver */ + + rtclower = stm32l4_rtc_lowerhalf(); + if (!rtclower) + { + syslog(LOG_ERR, + "ERROR: Failed to instantiate the RTC lower-half driver\n"); + return -ENOMEM; + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, rtclower); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to bind/register the RTC driver: %d\n", + ret); + return ret; + } + } +#endif + +#ifdef HAVE_USERLED_DRIVER + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", + ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} +#endif /* CONFIG_LIB_BOARDCTL */ + +#if defined(CONFIG_BOARDCTL_UNIQUEID) +int board_uniqueid(uint8_t *uniqueid) +{ + if (uniqueid == 0) + { + return -EINVAL; + } + + stm32l4_get_uniqueid(uniqueid); + return OK; +} +#endif diff --git a/configs/stm32l476-mdk/src/stm32_buttons.c b/configs/stm32l476-mdk/src/stm32_buttons.c index 58e9079153ddc209b1ecd62c6613497256bb384a..e36c284d54667434bc50cd08fc24a3671d902eec 100644 --- a/configs/stm32l476-mdk/src/stm32_buttons.c +++ b/configs/stm32l476-mdk/src/stm32_buttons.c @@ -46,17 +46,15 @@ #include #include +#include "stm32l4_gpio.h" #include "stm32l476-mdk.h" #ifdef CONFIG_ARCH_BUTTONS -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - /**************************************************************************** * Private Data ****************************************************************************/ + /* Pin configuration for each button. This array is indexed by * the BUTTON_* definitions in board.h */ @@ -66,10 +64,6 @@ static const uint32_t g_buttons[NUM_BUTTONS] = GPIO_BTN_POWER }; -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/configs/stm32l476-mdk/src/stm32_userleds.c b/configs/stm32l476-mdk/src/stm32_userleds.c new file mode 100644 index 0000000000000000000000000000000000000000..a2840abb52aac0e1922780e82d147a3ff5cd120e --- /dev/null +++ b/configs/stm32l476-mdk/src/stm32_userleds.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * configs/stm32l476-mdk/src/sam_userleds.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32l4_gpio.h" +#include "stm32l476-mdk.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ +#ifndef CONFIG_ARCH_LEDS + /* Configure LED GPIOs for output */ + + stm32l4_configgpio(GPIO_LED_RED); + stm32l4_configgpio(GPIO_LED_GREEN); + stm32l4_configgpio(GPIO_LED_WHITE); +#endif +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_RED_LED) + { + stm32l4_gpiowrite(GPIO_LED_RED, !ledon); /* Low illuminates */ + } + else if (led == BOARD_GREEN_LED) + { + stm32l4_gpiowrite(GPIO_LED_GREEN, !ledon); /* Low illuminates */ + } +#ifndef CONFIG_ARCH_LEDS + else if (led == BOARD_WHITE_LED) + { + stm32l4_gpiowrite(GPIO_LED_WHITE, !ledon); /* Low illuminates */ + } +#endif +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + /* Low illuminates */ + + stm32l4_gpiowrite(GPIO_LED_RED, (ledset & BOARD_RED_LED_BIT) == 0); + stm32l4_gpiowrite(GPIO_LED_GREEN, (ledset & BOARD_GREEN_LED_BIT) == 0); +#ifndef CONFIG_ARCH_LEDS + stm32l4_gpiowrite(GPIO_LED_WHITE, (ledset & BOARD_WHITE_LED_BIT) == 0); +#endif +} diff --git a/configs/stm32l476-mdk/src/stm32l476-mdk.h b/configs/stm32l476-mdk/src/stm32l476-mdk.h index 51e883907eff10a8791cf7860743d1078477ccc1..e2fd1f1cee8669469d3b42be0a2ca2f3f6a427f8 100644 --- a/configs/stm32l476-mdk/src/stm32l476-mdk.h +++ b/configs/stm32l476-mdk/src/stm32l476-mdk.h @@ -55,6 +55,7 @@ #define HAVE_PROC 1 #define HAVE_RTC_DRIVER 1 +#define HAVE_USERLED_DRIVER 1 #if !defined(CONFIG_FS_PROCFS) # undef HAVE_PROC @@ -71,20 +72,35 @@ # undef HAVE_RTC_DRIVER #endif -/* LED. - * LD4: the red LED on PB2 - * LD5: the green LED on PE8 +/* Check if we have the LED driver */ + +#if !defined(CONFIG_USERLED) || !defined(CONFIG_USERLED_LOWER) +# undef HAVE_USERLED_DRIVER +#endif + +/* LEDs. + * The Reference Moto Mod contains three LEDs. Two LEDs, are by convention, + * used to indicate the Reference Moto Mod battery state of charge, and the + * other is available for you to use in your applications. + * + * 1. The red LED on PD7. Part of the (rear-firing) red/green LED. + * 2. The green LED on PE7. Part of the (rear-firing) red/green LED. + * 3. The white (top-firing) LED on PE8 * - * - When the I/O is HIGH value, the LED is on. - * - When the I/O is LOW, the LED is off. + * When the I/O is HIGH value, the LED is OFF. + * When the I/O is LOW, the LED is ON. */ #define GPIO_LED_RED \ - (GPIO_PORTB | GPIO_PIN2 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PUSHPULL | \ + (GPIO_PORTD | GPIO_PIN7 | GPIO_OUTPUT_SET | GPIO_OUTPUT | GPIO_PUSHPULL | \ GPIO_PULLUP | GPIO_SPEED_50MHz) -#define GPIO_LED_GRN \ - (GPIO_PORTE | GPIO_PIN8 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PUSHPULL | \ +#define GPIO_LED_GREEN \ + (GPIO_PORTE | GPIO_PIN7 | GPIO_OUTPUT_SET | GPIO_OUTPUT | GPIO_PUSHPULL | \ + GPIO_PULLUP | GPIO_SPEED_50MHz) + +#define GPIO_LED_WHITE \ + (GPIO_PORTE | GPIO_PIN8 | GPIO_OUTPUT_SET | GPIO_OUTPUT | GPIO_PUSHPULL | \ GPIO_PULLUP | GPIO_SPEED_50MHz) /* BUTTONS -- NOTE that all have EXTI interrupts configured */ @@ -96,6 +112,7 @@ #define GPIO_BTN_POWER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTD|GPIO_PIN2) /* SPI1 off */ + #define GPIO_SPI1_MOSI_OFF (GPIO_INPUT | GPIO_PULLDOWN | \ GPIO_PORTE | GPIO_PIN15) #define GPIO_SPI1_MISO_OFF (GPIO_INPUT | GPIO_PULLDOWN | \ @@ -127,6 +144,22 @@ extern struct spi_dev_s *g_spi2; * Public Functions ************************************************************************************/ +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void); + /************************************************************************************ * Name: stm32_spiinitialize * diff --git a/configs/stm32ldiscovery/Kconfig b/configs/stm32ldiscovery/Kconfig index 34e1f833880d0e0bb2656aab37cf0b357347e13a..ea61f463bfd914bd41b452021304019b7c3bee64 100644 --- a/configs/stm32ldiscovery/Kconfig +++ b/configs/stm32ldiscovery/Kconfig @@ -8,6 +8,6 @@ if ARCH_BOARD_STM32FL_DISCOVERY config STM32LDISCO_QETIMER int "Timer to use with QE encoder" default 3 - depends on QENCODER + depends on SENSORS_QENCODER endif diff --git a/configs/stm32ldiscovery/README.txt b/configs/stm32ldiscovery/README.txt index 92fdb4311141d52be18ff0326cebcd5d64a2820a..40a3917dfd2ee176c9ea1f05adfec347c97e852d 100644 --- a/configs/stm32ldiscovery/README.txt +++ b/configs/stm32ldiscovery/README.txt @@ -23,12 +23,6 @@ Contents - Status - GPIO Pin Usage - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - LEDs - Serial Console - Debugging @@ -185,235 +179,6 @@ GPIO Pin Usage LCD_SEG43/LCD_COM7 ----- --------------------- -------------------------------- ---------------- -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. - -GNU Toolchain Options -===================== - - Toolchain Configurations - ------------------------ - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The Atollic Toolchain, - 3. The devkitARM GNU toolchain, - 4. Raisonance GNU toolchain, or - 5. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the CodeSourcery toolchain for Windows. To use - the Atollic, devkitARM, Raisonance GNU, or NuttX buildroot toolchain, you simply need to - add one of the following configuration options to your .config (or defconfig) - file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : The Atollic toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE=y : Raisonance RIDE7 under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - NOTE: the CodeSourcery (for Windows), Atollic, devkitARM, and Raisonance toolchains are - Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - The CodeSourcery Toolchain (2009q1) - ----------------------------------- - The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - The Atollic "Pro" and "Lite" Toolchain - -------------------------------------- - One problem that I had with the Atollic toolchains is that the provide a gcc.exe - and g++.exe in the same bin/ file as their ARM binaries. If the Atollic bin/ path - appears in your PATH variable before /usr/bin, then you will get the wrong gcc - when you try to build host executables. This will cause to strange, uninterpretable - errors build some host binaries in tools/ when you first make. - - Also, the Atollic toolchains are the only toolchains that have built-in support for - the FPU in these configurations. If you plan to use the Cortex-M4 FPU, you will - need to use the Atollic toolchain for now. See the FPU section below for more - information. - - The Atollic "Lite" Toolchain - ---------------------------- - The free, "Lite" version of the Atollic toolchain does not support C++ nor - does it support ar, nm, objdump, or objdcopy. If you use the Atollic "Lite" - toolchain, you will have to set: - - CONFIG_HAVE_CXX=n - - In order to compile successfully. Otherwise, you will get errors like: - - "C++ Compiler only available in TrueSTUDIO Professional" - - The make may then fail in some of the post link processing because of some of - the other missing tools. The Make.defs file replaces the ar and nm with - the default system x86 tool versions and these seem to work okay. Disable all - of the following to avoid using objcopy: - - CONFIG_RRLOAD_BINARY=n - CONFIG_INTELHEX_BINARY=n - CONFIG_MOTOROLA_SREC=n - CONFIG_RAW_BINARY=n - - devkitARM - --------- - The devkitARM toolchain includes a version of MSYS make. Make sure that the - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/stm32, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by RIDE. - -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh stm32ldiscovery/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - LEDs ==== diff --git a/configs/stm32ldiscovery/include/board.h b/configs/stm32ldiscovery/include/board.h index acb33b45ec8c8cd893716bb6dcb40a325837f38b..fa3f7c59aa0d8bad23a34e48edd8c0107d331e86 100644 --- a/configs/stm32ldiscovery/include/board.h +++ b/configs/stm32ldiscovery/include/board.h @@ -1,8 +1,7 @@ /************************************************************************************ * configs/stm32ldiscovery/include/board.h - * include/arch/board/board.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -34,8 +33,8 @@ * ************************************************************************************/ -#ifndef __CONFIG_STM32LDISCOVERY_INCLUDE_BOARD_H -#define __CONFIG_STM32LDISCOVERY_INCLUDE_BOARD_H +#ifndef __CONFIGS_STM32LDISCOVERY_INCLUDE_BOARD_H +#define __CONFIGS_STM32LDISCOVERY_INCLUDE_BOARD_H /************************************************************************************ * Included Files @@ -276,36 +275,20 @@ #endif /************************************************************************************ - * Public Data + * Public Function Prototypes ************************************************************************************/ #ifndef __ASSEMBLY__ #undef EXTERN #if defined(__cplusplus) -#define EXTERN extern "C" +# define EXTERN extern "C" extern "C" { #else -#define EXTERN extern +# define EXTERN extern #endif -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - /**************************************************************************** * Name: stm32_slcd_initialize * @@ -325,4 +308,4 @@ int stm32_slcd_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __CONFIG_STM32LDISCOVERY_INCLUDE_BOARD_H */ +#endif /* __CONFIGS_STM32LDISCOVERY_INCLUDE_BOARD_H */ diff --git a/configs/stm32vldiscovery/README.txt b/configs/stm32vldiscovery/README.txt index 8d4923be7179b29d03aa0cf9d1ad837fbefae801..d2f8af10bb6748fdcb3aa6a8414d3bcb4d81054c 100644 --- a/configs/stm32vldiscovery/README.txt +++ b/configs/stm32vldiscovery/README.txt @@ -7,241 +7,11 @@ STM32VLDiscovery (Value Line Discovery) board. Contents ======== - - Development Environment - - GNU Toolchain Options - - IDEs - - NuttX EABI "buildroot" Toolchain - - NuttX OABI "buildroot" Toolchain - - NXFLAT Toolchain - LEDs - UARTs - "STMicro STM32F100RC generic" specific Configuration Options - Configurations -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. - -GNU Toolchain Options -===================== - - Toolchain Configurations - ------------------------ - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The Atollic Toolchain, - 3. The devkitARM GNU toolchain, - 4. Raisonance GNU toolchain, or - 5. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the CodeSourcery toolchain for Windows. To use - the Atollic, devkitARM, Raisonance GNU, or NuttX buildroot toolchain, you simply need to - add one of the following configuration options to your .config (or defconfig) - file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : The Atollic toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE=y : Raisonance RIDE7 under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - NOTE: the CodeSourcery (for Windows), Atollic, devkitARM, and Raisonance toolchains are - Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - The CodeSourcery Toolchain (2009q1) - ----------------------------------- - The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - The Atollic "Pro" and "Lite" Toolchain - -------------------------------------- - One problem that I had with the Atollic toolchains is that the provide a gcc.exe - and g++.exe in the same bin/ file as their ARM binaries. If the Atollic bin/ path - appears in your PATH variable before /usr/bin, then you will get the wrong gcc - when you try to build host executables. This will cause to strange, uninterpretable - errors build some host binaries in tools/ when you first make. - - The Atollic "Lite" Toolchain - ---------------------------- - The free, "Lite" version of the Atollic toolchain does not support C++ nor - does it support ar, nm, objdump, or objdcopy. If you use the Atollic "Lite" - toolchain, you will have to set: - - CONFIG_HAVE_CXX=n - - In order to compile successfully. Otherwise, you will get errors like: - - "C++ Compiler only available in TrueSTUDIO Professional" - - The make may then fail in some of the post link processing because of some of - the other missing tools. The Make.defs file replaces the ar and nm with - the default system x86 tool versions and these seem to work okay. Disable all - of the following to avoid using objcopy: - - CONFIG_RRLOAD_BINARY=n - CONFIG_INTELHEX_BINARY=n - CONFIG_MOTOROLA_SREC=n - CONFIG_RAW_BINARY=n - - devkitARM - --------- - The devkitARM toolchain includes a version of MSYS make. Make sure that the - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/stm32, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX - one time from the Cygwin command line in order to obtain the pre-built - startup object needed by RIDE. - -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh stm32vldiscovery/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - LEDs ==== diff --git a/configs/stm32vldiscovery/include/board.h b/configs/stm32vldiscovery/include/board.h index 19e167309d3a02b136d511bffa63b4f31183048b..b72b2b5846f3a090fb986b9814d988f49662c5a0 100644 --- a/configs/stm32vldiscovery/include/board.h +++ b/configs/stm32vldiscovery/include/board.h @@ -144,40 +144,4 @@ #define BUTTON_0_BIT (1 << BUTTON_0) -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIG_STM32VLDISCOVERY_INCLUDE_BOARD_H */ diff --git a/configs/teensy-3.x/include/board.h b/configs/teensy-3.x/include/board.h index 0a0eae99142902fba19d906935a13ae4369f69c3..fa7f38f784da7b1b09bcb4f955b63df49bb058be 100644 --- a/configs/teensy-3.x/include/board.h +++ b/configs/teensy-3.x/include/board.h @@ -296,41 +296,4 @@ #endif #endif -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -/************************************************************************************ - * Name: kinetis_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void kinetis_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_TEENSY_3X_INCLUDE_BOARD_H */ diff --git a/configs/teensy-lc/include/board.h b/configs/teensy-lc/include/board.h index a1a9173b7e9c29eaed2c96c6c4c216f6b9ef2acf..1fccc6adaffb314abde24ffcd21b0303fbffde75 100644 --- a/configs/teensy-lc/include/board.h +++ b/configs/teensy-lc/include/board.h @@ -138,40 +138,4 @@ #define PIN_SPI1_MISO (PIN_SPI1_MISO_2 | PIN_ALT2_PULLUP) // Pin 1: PTB17 #define PIN_SPI1_MOSI (PIN_SPI0_MOSI_1 | PIN_ALT2_PULLUP) // Pin 0: PTB16 -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: kl_boardinitialize - * - * Description: - * All Kinetis L architectures must provide the following entry point. This entry - * point is called early in the initialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void kl_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/tm4c123g-launchpad/README.txt b/configs/tm4c123g-launchpad/README.txt index b5c097a79a250975a696a1c2011cff15cc49f357..1912056a61a71a60a4df3407671145ee6c3cf1d3 100644 --- a/configs/tm4c123g-launchpad/README.txt +++ b/configs/tm4c123g-launchpad/README.txt @@ -9,12 +9,6 @@ Contents ======== On-Board GPIO Usage - Development Environment - GNU Toolchain Options - IDEs - NuttX EABI "buildroot" Toolchain - NuttX OABI "buildroot" Toolchain - NXFLAT Toolchain LEDs Serial Console USB Device Controller Functions @@ -334,195 +328,6 @@ Using OpenOCD and GDB with an FT2232 JTAG emulator 2. Reset will restart the processor after loading code. 3. The 'monitor' command can be abbreviated as just 'mon'. -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -===================== - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The NuttX buildroot Toolchain (default, see below), - 2. The CodeSourcery GNU toolchain, - 3. The devkitARM GNU toolchain, - 4. The Atollic toolchain, or - 5. The Code Red toolchain - - All testing has been conducted using the Buildroot toolchain for Cygwin/Linux. - To use a different toolchain, you simply need to add one of the following - configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows or Cygwin - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : The Atollic toolchain under Windows or Cygwin - CONFIG_ARMV7M_TOOLCHAIN_CODEREDW=y : The Code Red toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODEREDL=y : The Code Red toolchain under Linux - - CONFIG_ARMV7M_OABI_TOOLCHAIN=y : If you use an older, OABI buildroot toolchain - - NOTE: the CodeSourcery (for Windows), Atollic, devkitARM, and Code Red (for Windows) - toolchains are Windows native toolchains. The CodeSourcey (for Linux) and NuttX - buildroot toolchains are Cygwin and/or Linux native toolchains. There are several - limitations to using a Windows based toolchain in a Cygwin environment. The three - biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include paths: You will need include/, arch/arm/src/tiva, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/tiva/tiva_vectors.S. - -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M3 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh tm4c123g-launchpad/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you - are building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh tm4c123g-launchpad/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - LEDs ==== The TM4C123G has a single RGB LED. If CONFIG_ARCH_LEDS is defined, then diff --git a/configs/tm4c123g-launchpad/include/board.h b/configs/tm4c123g-launchpad/include/board.h index e74db2d27bbd41ccf13e1ec8d19fb517e10f280d..bd8301bd686f456337192393c904de54c724e9a7 100644 --- a/configs/tm4c123g-launchpad/include/board.h +++ b/configs/tm4c123g-launchpad/include/board.h @@ -184,23 +184,4 @@ #define GPIO_UART1_RX GPIO_UART1_RX_1 #define GPIO_UART1_TX GPIO_UART1_TX_1 -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Name: tiva_boardinitialize - * - * Description: - * All Tiva architectures must provide the following entry point. This entry - * point is called early in the intitialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void tiva_boardinitialize(void); - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_TMC4C123G_LAUNCHPAD_INCLUDE_BOARD_H */ diff --git a/configs/tm4c1294-launchpad/include/board.h b/configs/tm4c1294-launchpad/include/board.h index 99b018a2217e92735bbd8d1a3eb7f4c638446d64..6057ffbdd772381461ebf2af654bb1109e754329 100644 --- a/configs/tm4c1294-launchpad/include/board.h +++ b/configs/tm4c1294-launchpad/include/board.h @@ -188,23 +188,4 @@ #define GPIO_EN0_LED1 GPIO_EN0_LED1_1 #define GPIO_EN0_LED2 GPIO_EN0_LED2_1 -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Name: tiva_boardinitialize - * - * Description: - * All Tiva architectures must provide the following entry point. This entry - * point is called early in the initialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void tiva_boardinitialize(void); - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_TM4C1294_LAUNCHPAD_INCLUDE_BOARD_H */ diff --git a/configs/twr-k60n512/README.txt b/configs/twr-k60n512/README.txt index bf7ff26db39ec6bf825f61c3b47c56369fe23bb6..d8c06294a36ff0918c0018368a6d59d380528391 100644 --- a/configs/twr-k60n512/README.txt +++ b/configs/twr-k60n512/README.txt @@ -20,12 +20,8 @@ Contents - Connections via the Tower Primary Connector Side B - TWR-SER Serial Board Connection o LEDs - o Development Environment - o GNU Toolchain Options - o IDEs - o NuttX EABI "buildroot" Toolchain - o NuttX OABI "buildroot" Toolchain - o NXFLAT Toolchain + o TWR-K60N512-specific Configuration Options + o Configurations Kinetis TWR-K60N512 Features: ============================= @@ -285,190 +281,6 @@ as follows: on a small proportion of the time. *** LED2 may also flicker normally if signals are processed. -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -===================== - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The devkitARM GNU toolchain, - 3. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the CodeSourcery Windows toolchain. To - use the devkitARM or the NuttX GNU toolchain, you simply need to change the - the following configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - - NOTE: the CodeSourcery (for Windows) and devkitARM toolchains are - Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/k40, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/kinetis/k40_vectors.S. - -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M4 GCC toolchain (if - different from the default in your PATH variable). - - If you have no Cortex-M4 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - NOTE: The NuttX toolchain may not include optimizations for Cortex-M4 (ARMv7E-M). - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh twr-k60n512/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M4 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - TWR-K60N512-specific Configuration Options ========================================== diff --git a/configs/twr-k60n512/include/board.h b/configs/twr-k60n512/include/board.h index ea464c0d439ec572d4083401bfbacb335539c4cf..9e91659b25121255c235932c70c427e4126b912c 100644 --- a/configs/twr-k60n512/include/board.h +++ b/configs/twr-k60n512/include/board.h @@ -369,39 +369,4 @@ * B80 EBI_D0 PTC15 */ -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: kinetis_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -EXTERN void kinetis_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/twr-k64f120m/README.txt b/configs/twr-k64f120m/README.txt index d09425d04a577a741072e2e7a6dccc17cf05ed5b..18fc8240d37f8c390154726ebf5650d5249c60a4 100644 --- a/configs/twr-k64f120m/README.txt +++ b/configs/twr-k64f120m/README.txt @@ -22,12 +22,8 @@ Contents - Connections via the Tower Primary Connector Side B - TWR-SER Serial Board Connection o LEDs - o Development Environment - o GNU Toolchain Options - o IDEs - o NuttX EABI "buildroot" Toolchain - o NuttX OABI "buildroot" Toolchain - o NXFLAT Toolchain + o TWR-K64F120M-specific Configuration Options + o Configurations Kinetis TWR-K64F120M Features: ============================= @@ -413,191 +409,6 @@ as follows: illuminated on a small proportion of the time. *** LED3 may even glow faintlier then LED2 while signals are processed. -Development Environment -======================= - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Linux - environment. - -GNU Toolchain Options -===================== - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The CodeSourcery GNU toolchain, - 2. The devkitARM GNU toolchain, - 3. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the CodeSourcery Windows toolchain. To - use the devkitARM or the NuttX GNU toolchain, you simply need to change the - the following configuration options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_IARL=y : IAR - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y : GCC (default) - - NOTE: the CodeSourcery (for Windows) and devkitARM toolchains are - Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot - toolchains are Cygwin and/or Linux native toolchains. There are several limitations - to using a Windows based toolchain in a Cygwin environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -IDEs -==== - - NuttX is built using command-line make. It can be used with an IDE, but some - effort will be required to create the project. - - Makefile Build - -------------- - Under Eclipse, it is pretty easy to set up an "empty makefile project" and - simply use the NuttX makefile to build the system. That is almost for free - under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty - makefile project in order to work with Windows (Google for "Eclipse Cygwin" - - there is a lot of help on the internet). - - Native Build - ------------ - Here are a few tips before you start that effort: - - 1) Select the toolchain that you will be using in your .config file - 2) Start the NuttX build at least one time from the Cygwin command line - before trying to create your project. This is necessary to create - certain auto-generated files and directories that will be needed. - 3) Set up include pathes: You will need include/, arch/arm/src/k40, - arch/arm/src/common, arch/arm/src/armv7-m, and sched/. - 4) All assembly files need to have the definition option -D __ASSEMBLY__ - on the command line. - - Startup files will probably cause you some headaches. The NuttX startup file - is arch/arm/src/kinetis/k40_vectors.S. - -NuttX EABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The PATH environment variable should - be modified to point to the correct path to the Cortex-M4 GCC toolchain. - - If you have no Cortex-M4 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - NOTE: The NuttX toolchain may not include optimizations for Cortex-M4 (ARMv7E-M). - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh twr-k64f120m/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-eabi-defconfig-4.6.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M4 toolchain for Cygwin under Windows. - - NOTE: Unfortunately, the 4.6.3 EABI toolchain is not compatible with the - the NXFLAT tools. See the top-level TODO file (under "Binary loaders") for - more information about this problem. If you plan to use NXFLAT, please do not - use the GCC 4.6.3 EABI toochain; instead use the GCC 4.3.3 OABI toolchain. - See instructions below. - -NuttX OABI "buildroot" Toolchain -================================ - - The older, OABI buildroot toolchain is also available. To use the OABI - toolchain: - - 1. When building the buildroot toolchain, either (1) modify the cortexm3-eabi-defconfig-4.6.3 - configuration to use EABI (using 'make menuconfig'), or (2) use an exising OABI - configuration such as cortexm3-defconfig-4.3.3 - - 2. Modify the Make.defs file to use the OABI conventions: - - +CROSSDEV = arm-nuttx-elf- - +ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections - -CROSSDEV = arm-nuttx-eabi- - -ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft - -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -NXFLAT Toolchain -================ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh lpcxpresso-lpc1768/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - TWR-K64F120M-specific Configuration Options ========================================== diff --git a/configs/twr-k64f120m/include/board.h b/configs/twr-k64f120m/include/board.h index 5cbedfbb38b58f2d6c96802b174a0efffab9e092..d479e10085a0d64a0d122f5392122a50e233a24d 100644 --- a/configs/twr-k64f120m/include/board.h +++ b/configs/twr-k64f120m/include/board.h @@ -161,40 +161,4 @@ # define CONFIG_KINETIS_NENET 1 #endif -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: kinetis_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void kinetis_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_TWR_K64F120M_INCLUDE_BOARCH_H */ diff --git a/configs/u-blox-c027/include/board.h b/configs/u-blox-c027/include/board.h index 41f94eb53509166d02906a747cb27c7347c24e65..6d2d407a50bf04a064fdffa8525bb4d0861c8dfc 100644 --- a/configs/u-blox-c027/include/board.h +++ b/configs/u-blox-c027/include/board.h @@ -252,44 +252,4 @@ #define GPIO_PWM1p5 GPIO_PWM1p5_2 #define GPIO_PWM1p6 GPIO_PWM1p6_2 -/************************************************************************************ - * Public Types - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: lpc17_boardinitialize - * - * Description: - * All LPC17xx architectures must provide the following entry point. This entry - * point is called early in the intitialization -- after all memory has been - * configured and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void lpc17_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_U_BLOX_C027_INCLUDE_BOARD_H */ diff --git a/configs/ubw32/nsh/defconfig b/configs/ubw32/nsh/defconfig index 1e72cdf3423b424f43858f3e64b7e591ae569f4a..f462066f626b3e5201d28a8d2db701dcedb8890f 100644 --- a/configs/ubw32/nsh/defconfig +++ b/configs/ubw32/nsh/defconfig @@ -1,5 +1,5 @@ # CONFIG_ARCH_RAMFUNCS is not set -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set diff --git a/configs/viewtool-stm32f107/README.txt b/configs/viewtool-stm32f107/README.txt index 09c5248bd40ef68c0df380283063b6504812f03b..3bb13a31662fe44d58a9e6d8a65299d7e258174e 100644 --- a/configs/viewtool-stm32f107/README.txt +++ b/configs/viewtool-stm32f107/README.txt @@ -276,7 +276,7 @@ microSD Card Interface Device Drivers -> MMC/SD Driver Support CONFIG_MMCSD=y : Enable MMC/SD support CONFIG_MMSCD_NSLOTS=1 : One slot per driver instance - CONFIG_MMCSD_HAVECARDDETECT=y : Supports card-detect PIOs + CONFIG_MMCSD_HAVE_CARDDETECT=y : Supports card-detect PIOs CONFIG_MMCSD_MMCSUPPORT=n : Interferes with some SD cards CONFIG_MMCSD_SPI=n : No SPI-based MMC/SD support CONFIG_MMCSD_SDIO=y : SDIO-based MMC/SD support diff --git a/configs/viewtool-stm32f107/include/board.h b/configs/viewtool-stm32f107/include/board.h index 2fea6a29daebe6447b242bfd1e439008e7cdb031..e04edfa9ada14c7c800fcbd047831df46eecfb3c 100644 --- a/configs/viewtool-stm32f107/include/board.h +++ b/configs/viewtool-stm32f107/include/board.h @@ -130,39 +130,4 @@ #define BUTTON_SW3_BIT (1 << BUTTON_SW3) #define BUTTON_SW4_BIT (1 << BUTTON_SW4) -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ -/************************************************************************************ - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void stm32_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_VIEWTOOL_STM32F107_INCLUDE_BOARD_H */ diff --git a/configs/xmc4500-relax/README.txt b/configs/xmc4500-relax/README.txt index e5bba52c69dc876afd86b83e7ad88b5777e03814..14eae34dc8546f33a5182741eb8bf1e56b8c5572 100644 --- a/configs/xmc4500-relax/README.txt +++ b/configs/xmc4500-relax/README.txt @@ -11,7 +11,7 @@ Status ====== 2017-03-21: The XMC4500 Relax boots into NSH, provides the NSH prompt, - and the LEDs are working. But there is a problem with sserial input. + and the LEDs are working. But there is a problem with serial input. The most likely reason for this is there are no serial RX interripts. Serial Console @@ -81,9 +81,10 @@ Configurations Each XMC4500 Relax configuration is maintained in a sub-directory and can be selected as follow: - cd tools - ./configure.sh xmc5400-relax/ - cd - + .tools/configure.sh xmc5400-relax/ + + See '.tools/configure.sh -h' for a list of all options. The most typical + are -l to select the Linux host or -c to select the Windows Cygwin host. Before starting the build, make sure that your PATH environment variable includes the correct path to your toolchain. @@ -91,7 +92,6 @@ Configurations And then build NuttX by simply typing the following. At the conclusion of the make, the nuttx binary will reside in an ELF file called, simply, nuttx. - make oldconfig make The that is provided above as an argument to the tools/configure.sh @@ -128,21 +128,21 @@ Configurations CONFIG_UART0_2STOP=0 - 3. All of these configurations are set up to build under Windows using the - "GNU Tools for ARM Embedded Processors" that is maintained by ARM - (unless stated otherwise in the description of the configuration). + 3. All of these configurations are set up to build under Windows using + the "GNU Tools for ARM Embedded Processors" that is maintained by + ARM (unless stated otherwise in the description of the configuration). - https://developer.arm.com/open-source/gnu-toolchain/gnu-rm + https://developer.arm.com/open-source/gnu-toolchain/gnu-rm - That toolchain selection can easily be reconfigured using - 'make menuconfig'. Here are the relevant current settings: + That toolchain selection can easily be reconfigured using + 'make menuconfig'. Here are the relevant current settings: - Build Setup: - CONFIG_HOST_WINDOWS=y : Window environment - CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows + Build Setup: + CONFIG_HOST_WINDOWS=y : Window environment + CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows - System Type -> Toolchain: - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain + System Type -> Toolchain: + CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain Configuration sub-directories ----------------------------- diff --git a/configs/xmc4500-relax/include/board.h b/configs/xmc4500-relax/include/board.h index 751e80317032082028f876fa9fcfca8dcaf402fa..7190d1c9394207a94fefc239799bc7fa0b4035aa 100644 --- a/configs/xmc4500-relax/include/board.h +++ b/configs/xmc4500-relax/include/board.h @@ -52,6 +52,38 @@ ************************************************************************************/ /* Clocking *************************************************************************/ + +/* The maximum frequency for the XMC4500 is 120MHz. */ + +#undef BOARD_FCPU_144MHZ +#define BOARD_FCPU_120MHZ 1 + +/* Watchdog clock source selection */ + +#define WDT_CLKSRC_FOFI 0 /* fOFI clock */ +#define WDT_CLKSRC_FSTDY 1 /* fSTDY clock */ +#define WDT_CLKSRC_FPLL 2 /* fPLL clock */ + +/* External Clock source selection */ + +#define EXT_CLKSRC_FSYS 0 /* fSYS clock */ +#define EXT_CLKSRC_FUSB 2 /* fUSB clock divided by ECKDIV */ +#define EXT_CLKSRC_FPLL 3 /* fPLL clock divided by ECKDIV */ + +/* Factory Calibration */ + +#undef BOARD_FOFI_CALIBRATION /* Enable factory calibration */ + +/* On-board crystals + * + * NOTE: Only the XMC4500 Relax Kit-V1 provides the 32.768KHz RTC crystal. It + * is not available on XMC4500 Relax Lite Kit-V1. + */ + +#define BOARD_XTAL_FREQUENCY 12000000 /* 12MHz XTAL */ +#undef BOARD_RTC_XTAL_FRQUENCY /* 32.768KHz RTC XTAL not available on the Relax Lite */ + +#if defined(BOARD_FCPU_144MHZ) /* Default clock initialization * * fXTAL = 12Mhz @@ -70,50 +102,137 @@ * -> fWDT = 24MHz (REVISIT) */ -#undef BOARD_FOFI_CALIBRATION /* Enable factory calibration */ +/* Select the external crystal as the PLL clock source */ -/* On-board crystals +# define BOARD_PLL_CLOCKSRC_XTAL 1 /* PLL Clock source == external crystal */ +# undef BOARD_PLL_CLOCKSRC_OFI /* PLL Clock source != internal fast oscillator */ + +/* PLL Configuration: * - * NOTE: Only the XMC4500 Relax Kit-V1 provides the 32.768KHz RTC crystal. It - * is not available on XMC4500 Relax Lite Kit-V1. + * fPLL = (fPLLSRC / (pdiv * k2div) * ndiv + * + * fPLL = (12000000 / (2 * 1)) * 48 + * = 288MHz */ -#define BOARD_XTAL_FREQUENCY 12000000 /* 12MHz XTAL */ -#undef BOARD_RTC_XTAL_FRQUENCY /* 32.768KHz RTC XTAL not available */ +# define BOARD_ENABLE_PLL 1 +# define BOARD_PLL_PDIV 2 +# define BOARD_PLL_NDIV 48 +# define BOARD_PLL_K2DIV 1 +# define BOARD_PLL_FREQUENCY 288000000 + +/* System frequency, fSYS, is divided down from PLL output */ + +# define BOARD_SYSDIV 1 /* PLL Output divider to get fSYS */ +# define BOARD_SYS_FREQUENCY 288000000 + +/* CPU frequency, fCPU, may be divided down from system frequency */ + +# define BOARD_CPUDIV_ENABLE 1 /* Enable PLL divide by 2 for fCPU */ +# define BOARD_CPU_FREQUENCY 144000000 + +/* CCU frequency may be divided down from system frequency */ + +# define BOARD_CCUDIV_ENABLE 1 /* Enable PLL div by 2 */ +# define BOARD_CCU_FREQUENCY 144000000 + +/* Watchdog clock settings */ + +# define BOARD_WDT_SOURCE WDT_CLKSRC_FOFI +# define BOARD_WDTDIV 1 +# define BOARD_WDT_FREQUENCY 24000000 + +/* EBU frequency may be divided down from system frequency */ + +# define BOARD_EBUDIV 2 /* fSYS / 2 */ +# define BOARD_EBU_FREQUENCY 72000000 + +/* EXT clock settings */ + +# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL +# define BOARD_EXTDIV 289 /* REVISIT */ +# define BOARD_EXT_FREQUENCY 498270 /* REVISIT */ + +/* The peripheral clock, fPERIPH, derives from fCPU with no division */ + +# define BOARD_PBDIV 1 /* No division */ +# define BOARD_PERIPH_FREQUENCY 144000000 + +#elif defined(BOARD_FCPU_120MHZ) +/* Default clock initialization + * + * fXTAL = 12Mhz + * -> fPLL = (fXTAL / (2 * 4) * 80) = 120 + * -> fSYS = (fPLL / 1) = 120MHz + * -> fCPU = (fSYS / 1) = 120MHz + * -> fPERIPH = (fCPU / 1) = 120MHz + * -> fCCU = (fSYS / 1) = 120MHz + * -> fETH = 60MHz (REVISIT) + * -> fUSB = 48MHz (REVISIT) + * -> fEBU = 60MHz (REVISIT) + * + * fUSBPLL Disabled, only enabled if SCU_CLK_USBCLKCR_USBSEL_USBPLL is selected + * + * fOFI = 24MHz + * -> fWDT = 24MHz (REVISIT) + */ /* Select the external crystal as the PLL clock source */ -#define BOARD_PLL_CLOCKSRC_XTAL 1 /* PLL Clock source == extnernal crystal */ -#undef BOARD_PLL_CLOCKSRC_OFI /* PLL Clock source != internal fast oscillator */ +# define BOARD_PLL_CLOCKSRC_XTAL 1 /* PLL Clock source == extnernal crystal */ +# undef BOARD_PLL_CLOCKSRC_OFI /* PLL Clock source != internal fast oscillator */ /* PLL Configuration: * * fPLL = (fPLLSRC / (pdiv * k2div) * ndiv * - * fPLL = (12000000 / (2 * 1)) * 48 - * = 288MHz + * fPLL = (12000000 / (2 * 4)) * 80 + * = 120MHz */ -#define BOARD_ENABLE_PLL 1 -#define BOARD_PLL_PDIV 2 -#define BOARD_PLL_NDIV 48 -#define BOARD_PLL_K2DIV 1 -#define BOARD_PLL_FREQUENCY 288000000 +# define BOARD_ENABLE_PLL 1 +# define BOARD_PLL_PDIV 2 +# define BOARD_PLL_NDIV 80 +# define BOARD_PLL_K2DIV 4 +# define BOARD_PLL_FREQUENCY 120000000 /* System frequency, fSYS, is divided down from PLL output */ -#define BOARD_SYSDIV 1 /* PLL Output divider to get fSYS */ -#define BOARD_SYS_FREQUENCY 288000000 +# define BOARD_SYSDIV 1 /* No division */ +# define BOARD_SYS_FREQUENCY 120000000 /* CPU frequency, fCPU, may be divided down from system frequency */ -#define BOARD_CPUDIV_ENABLE 1 /* Enable PLL dive by 2 for fCPU */ -#define BOARD_CPU_FREQUENCY 144000000 +# define BOARD_CPUDIV_ENABLE 0 /* No divison */ +# define BOARD_CPU_FREQUENCY 120000000 + +/* CCU frequency may be divided down from system frequency */ + +# define BOARD_CCUDIV_ENABLE 0 /* No divison */ +# define BOARD_CCU_FREQUENCY 120000000 + +/* Watchdog clock setting */ + +# define BOARD_WDT_SOURCE WDT_CLKSRC_FOFI +# define BOARD_WDTDIV 1 +# define BOARD_WDT_FREQUENCY 24000000 + +/* EBU frequency may be divided down from system frequency */ + +# define BOARD_EBUDIV 2 /* fSYS/2 */ +# define BOARD_EBU_FREQUENCY 60000000 + +/* EXT clock settings */ + +# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL +# define BOARD_EXTDIV 289 /* REVISIT */ +# define BOARD_EXT_FREQUENCY 415225 /* REVISIT */ /* The peripheral clock, fPERIPH, derives from fCPU with no division */ -#define BOARD_PBDIV 1 /* No division */ -#define BOARD_PERIPH_FREQUENCY 144000000 +# define BOARD_PBDIV 1 /* No division */ +# define BOARD_PERIPH_FREQUENCY 120000000 +#endif /* Standby clock source selection * @@ -208,8 +327,18 @@ */ #define BOARD_UART0_DX USIC_DXB -#define GPIO_UART0_RXD0 GPIO_U0C0_DX0B -#define GPIO_UART0_TXD0 (GPIO_U0C0_DOUT0_3 | GPIO_PADA1P_STRONGSOFT | GPIO_OUTPUT_SET) +#define GPIO_UART0_RXD GPIO_U0C0_DX0B +#define GPIO_UART0_TXD (GPIO_U0C0_DOUT0_3 | GPIO_PADA1P_STRONGSOFT | GPIO_OUTPUT_SET) + +/* USIC1 CH1 is used as UART3 + * + * RX - P0.0 + * TX - P0.1 + */ + +#define BOARD_UART3_DX USIC_DXD +#define GPIO_UART3_RXD (GPIO_U1C1_DX0D | GPIO_INPUT_PULLUP) +#define GPIO_UART3_TXD (GPIO_U1C1_DOUT0_2 | GPIO_PADA1P_STRONGSOFT | GPIO_OUTPUT_SET) /************************************************************************************ * Public Data diff --git a/configs/xmc4500-relax/src/Makefile b/configs/xmc4500-relax/src/Makefile index f7a63f463090a4f9d5060c785c6f21c164e09f68..f7459f807e92615156e2351854afc6c9a38c5b97 100644 --- a/configs/xmc4500-relax/src/Makefile +++ b/configs/xmc4500-relax/src/Makefile @@ -52,4 +52,8 @@ ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += xmc4_appinit.c endif +ifeq ($(CONFIG_EXAMPLES_OSTEST),y) +CSRCS += xmc4_ostest.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/xmc4500-relax/src/xmc4_ostest.c b/configs/xmc4500-relax/src/xmc4_ostest.c new file mode 100644 index 0000000000000000000000000000000000000000..02d41ca603bbb0edbbf2bd180877c248adcc259d --- /dev/null +++ b/configs/xmc4500-relax/src/xmc4_ostest.c @@ -0,0 +1,111 @@ +/************************************************************************************ + * configs/xmc4500-relax/src/xmc4_ostest.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" +#include "xmc4500-relax.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration ********************************************************************/ + +#undef HAVE_FPU +#if defined(CONFIG_ARCH_FPU) && !defined(CONFIG_EXAMPLES_OSTEST_FPUTESTDISABLE) && \ + defined(CONFIG_EXAMPLES_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID) && \ + !defined(CONFIG_DISABLE_SIGNALS) +# define HAVE_FPU 1 +#endif + +#ifdef HAVE_FPU + +#if CONFIG_EXAMPLES_OSTEST_FPUSIZE != (4*SW_FPU_REGS) +# error "CONFIG_EXAMPLES_OSTEST_FPUSIZE has the wrong size" +#endif + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +static uint32_t g_saveregs[XCPTCONTEXT_REGS]; + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/* Given an array of size CONFIG_EXAMPLES_OSTEST_FPUSIZE, this function will return + * the current FPU registers. + */ + +void arch_getfpu(FAR uint32_t *fpusave) +{ + irqstate_t flags; + + /* Take a snapshot of the thread context right now */ + + flags = enter_critical_section(); + up_saveusercontext(g_saveregs); + + /* Return only the floating register values */ + + memcpy(fpusave, &g_saveregs[REG_S0], (4*SW_FPU_REGS)); + leave_critical_section(flags); +} + +/* Given two arrays of size CONFIG_EXAMPLES_OSTEST_FPUSIZE this function + * will compare them and return true if they are identical. + */ + +bool arch_cmpfpu(FAR const uint32_t *fpusave1, FAR const uint32_t *fpusave2) +{ + return memcmp(fpusave1, fpusave2, (4*SW_FPU_REGS)) == 0; +} + +#endif /* HAVE_FPU */ diff --git a/configs/xtrs/README.txt b/configs/xtrs/README.txt deleted file mode 100644 index c8f876998743a10edb240e47482d69373a091a80..0000000000000000000000000000000000000000 --- a/configs/xtrs/README.txt +++ /dev/null @@ -1,242 +0,0 @@ -xtrs README -^^^^^^^^^^^^^ - -Current status -^^^^^^^^^^^^^^ - -The xtrs port is not operational yet; some work still needs to be done. - -Contents -^^^^^^^^ - - o Getting a TRS80 emulator and DOS disks - o Loading an executable into xtrs - o Configuring NuttX - o Reconfiguring NuttX - o Reconfiguring for Linux, OSX, or Cygwin - o SDCC - o Building the SDCC toolchain - -Getting a TRS80 emulator and DOS disks -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -This port uses a vintage computer based on the Z80, the TRS80. -There's a main page describing the different models of TRS80. -See: http://www.trs-80.com - -An emulator for this computer is available to run TRS80 programs on a -linux platform (http://www.tim-mann.org/xtrs.html). - -Other emulators are available for other platforms. -See http://www.trs-80.com, click on the link Emulators. - -TRSDOS, LDOS and other softwares are available at: -http://discover-net.net/~dmkeil/trs80/software/trs-dos.htm - -Or you can get TRSDOS 1.3 and 6.1 from this site; it's included with the emulator. -http://discover-net.net/~dmkeil/trs80/model4.htm - -The SDCC toolchain is available from http://sdcc.sourceforge.net/. All -testing has been performed using version 2.7.0 of the SDCC toolchain. - -Loading an executable into xtrs -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -At http://www.trs-80.com click on the link: Getting a Software Onto an Emulator. - -Configuring NuttX -^^^^^^^^^^^^^^^^^ - - ostest - - This configuration performs a simple, minimal OS test using - examples/ostest. This can be configurated as follows: - - 1) From a POSIX window: - cd tools - ./configure.sh xtrs/ostest - 2) Modify your PATH environment variable to include the path to the - SDCC toolchain. - 3) From a CMD.exe window - make - - If this is a Windows native build, then configure.bat should be used - in step 1) instead of configure.sh: - - configure.bat xtrs\ostest - - NOTES: - - 1. This configuration uses the mconf-based configuration tool. See the - "Reconfiguring" section below for information about changing this - configuration. - - 2. The default setup for this configuration uses a windows native build. - See the section entitled "Reconfiguring for Linux, OSX, or Cygwin" - which will give you the steps you would need to do to convert this - configuration to build in other, Unix-like environments. - - 3. The current build requires ca. 3.2.1 SDCC. - - nsh - - This configuration file builds NSH (examples/nsh). This - configuration is not functional due to issues with use of the - simulated serial driver (see the TODO list). - - This configuration can be selected by: - - 1) From a POSIX window: - cd tools - ./configure.sh xtrs/nsh - 2) Modify your PATH environment variable to include the path to the - SDCC toolchain. - 3) From a CMD.exe window - make - - If this is a Windows native build, then configure.bat should be used - in step 1) instead of configure.sh: - - configure.bat xtrs\nsh - - NOTES: - - 1. This configuration uses the mconf-based configuration tool. See the - "Reconfiguring" section below for information about changing this - configuration. - - 2. The default setup for this configuration uses a windows native build. - See the section entitled "Reconfiguring for Linux, OSX, or Cygwin" - which will give you the steps you would need to do to convert this - configuration to build in other, Unix-like environments. - - 3. The current build requires ca. 3.2.1 SDCC. - - 4. This configuration depends on configs/xtrs/src/xtrs_serial.c which - is incomplete. At compile time, the following symbols are undefined: - - ctrl, baud, rs232_xmtisr, rs232_recvisr, ch - - pashello - - Configures to use examples/pashello for execution from FLASH - See examples/README.txt for information about pashello. - - This configuration is not usable because the resulting binary - is too large for the z80 address space. - - This configuration can be selected by: - - 1) From a POSIX window: - cd tools - ./configure.sh xtrs/pashello - 2) Modify your PATH environment variable to include the path to the - SDCC toolchain. - 3) From a CMD.exe window - make - - If this is a Windows native build, then configure.bat should be used - in step 1) instead of configure.sh: - - configure.bat xtrs\pashello - - NOTES: - - 1. This configuration uses the mconf-based configuration tool. See the - "Reconfiguring" section below for information about changing this - configuration. - - 2. The default setup for this configuration uses a windows native build. - See the section entitled "Reconfiguring for Linux, OSX, or Cygwin" - which will give you the steps you would need to do to convert this - configuration to build in other, Unix-like environments. - - 3. The current build requires ca. 3.2.1 SDCC. - -Reconfiguring NuttX -^^^^^^^^^^^^^^^^^^^ - -These configurations all use the kconfig-frontends, mconf-based configuration -tool. To change this configuration using that tool, you should: - - a. Build and install the kconfig-mconf tool. See nuttx/README.txt and - additional README.txt files in the NuttX tools repository. - - b. Execute 'make menuconfig' in nuttx/ in order to start the reconfiguration - process. - -Reconfiguring for Linux, OSX, or Cygwin -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -All of the z80 configurations in this this directory are set up to build in a -Windows CMD.exe shell. This configuration requires the MinGW host compiler -and severl GNUWin32 tools (see discussion in the top-level NuttX/README.txt -file). - -These configurations can be converted to run under Linux (or Cygwin or OSX), -by modifying the configuration file as follows: - - -CONFIG_HOST_WINDOWS=y - -CONFIG_WINDOWS_NATIVE=y - +CONFIG_HOST_LINUX=y - - -CONFIG_Z80_TOOLCHAIN_SDCCW=y - +CONFIG_Z80_TOOLCHAIN_SDCCL=y - -You may need to first manually change the CONFIG_APPS_DIR="..\apps" definition -in the .config file because the backslash may upset some Unix-based tools. - -This configuration will require a recent version of SDCC (ca. 3.2.1) for Linux -or custom built for Cygwin (see below). - -SDCC -^^^^ - -These z80 configurations all use the SDCC toolchain (http://sdcc.sourceforge.net/). -Source and pre-built SDCC binaries can be downloaded from the SDCC SourceForge -site: http://sourceforge.net/projects/sdcc/files/ . Pre-built binaries are -available for Linux, MAC OSX, and for Win32. Various SDCC options can be -selected with: - - CONFIG_Z80_TOOLCHAIN_SDCCL=y : SDCC for Linux, MAC OSX or Cygwin (see below) - CONFIG_Z80_TOOLCHAIN_SDCCW=y : SDCC for Win32 - -SDCC versions 3.2.0 or higher are recommended. - -Building the SDCC toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -You may also want to build your own SDCC toolchain. You might want to do this, -for example, if you are running under Cygwin and want a Cygwin compatible -SDCC toolchain. - -The SDCC toolchain is built with the standard configure/make/make install -sequence. However, some special actions are required to generate libraries -compatible with this build. First start with the usual steps - - download - unpack - cd sdcc - ./configure - -Note if you do not have the gputils packet installed, newer version of the -SDCC configure will fail. You will have to either install the gputils -package or if you don't need PIC14 or PIC16 support: - - ./configure --disable-pic14-port --disable-pic16-port - -But before making, we need to apply a patch to the SDCC 2.6.0 source -so that the z80 assembler can handle long symbol names. This is not -needed with later versions. - - Apply sdcc-2.6.0-asz80-symlen.patch - cd sdcc/device/lib - -Then make the SDCC binaries - - make - -and install SDCC: - - sudo make install - diff --git a/configs/xtrs/include/trs80-m3.h b/configs/xtrs/include/trs80-m3.h deleted file mode 100644 index 889c209f339436e9be33aad67259c1b74255be99..0000000000000000000000000000000000000000 --- a/configs/xtrs/include/trs80-m3.h +++ /dev/null @@ -1,185 +0,0 @@ -/**************************************************************************** - * configs/xtrs/include/trs80-m3.h - * - * Copyright (C) 2008 Jacques Pelletier. All rights reserved. - * Author: Jacques Pelletier - * - * This file is a part of NuttX and hence - * - * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/* Information from http://www.trs-80.com */ - -#ifndef __TRS80_M3_H -#define __TRS80_M3_H - -/* Outputs a byte to a logical device or FCB. DE = FCB and A = byte. - * Don't confuse with CTL at 0023. - */ - -#define _TRS80_M3_PUT 0x001B - -/* Outputs a control byte to a logical device or FCB. DE = FCB and A = control byte. */ - -#define _TRS80_M3_CTL 0x0023 - -/* Scan keyboard and return with accumulator containing result. DE is used. */ - -#define _TRS80_M3_KBDSCN 0x002B - -/* Displays a character at current cursor location. */ - -#define _TRS80_M3_VDCHAR 0x0033 - -/* "Waits until printer is ready then prints character. A = ASCII character. - * If BREAK is pressed, a return to caller is made." - */ - -#define _TRS80_M3_PRCHAR 0x003B - -/* Call Input a line from the keyboard. B = max length of line. HL points at buffer. - * Buffer should be the length of B plus 1. To terminate, hit BREAK or ENTER. - * On exit, HL points at buffer and B = number of characters entered. - * Carry will be set if BREAK was pressed. - */ - -#define _TRS80_M3_KBLINE 0x0040 - -/* "Scans the keyboard until a key is pressed. If BREAK is pressed, it is returned - * like other keys." - */ - -#define _TRS80_M3_KBWAIT 0x0049 - -/* "Receive a character from RS-232. No entry conditions. On exit, memory location - * 16872 contains character received. DE is altered. This routine honors wait status." - */ - -#define _TRS80_M3_RSRCV 0x0050 - -/* "Transmit character to RS-232. On entry, Accumulator or memory location 16880 - * contains character. On exit, 16880 = 0 if no character sent. Wait status honored." - */ - -#define _TRS80_M3_RSTX 0x0055 - -/* Initialize RS-232 interface. On entry, memory location 16888 = send/receive baud - * rate code, location 16890 = wait/don't wait switch, location 16889 = RS-232 - * characteristics switch. On exit, DE is altered. For more detail, consult Model 3 - * reference manual. - */ - -#define _TRS80_M3_RSINIT 0x005A - -/* This is the routine that is Basic's SET, RESET, and POINT functions. Here's how - * to use it. Load HL with return address and push. Load register A with one of the - * following: 00H = POINT, 01H = RESET, and 80H = SET. Push AF onto stack. Load A with - * X coordinate and push onto stack. Load A with Y coordinate and JP GRAPH. - */ - -#define _TRS80_M3_GRAPH 0x0150 - -/* Clear screen. */ - -#define _TRS80_M3_CLS 0x01C9 - -/* Randomize. */ - -#define _TRS80_M3_RANDOM 0x01D3 - -/* This routine turns off the cassette drive. */ - -#define _TRS80_M3_CSOFF 0x01F8 - -#ifdef TRS80_MODEL1 - -/* A register contains a 0 or 1 which is the cassette number. This routine defines - * cassette number and turns on cassette. Model I only. - */ - -#define _TRS80_M3_DEFCAS 0x0212 - -#endif /* TRS80_MODEL1 */ - -/* Inputs data one byte at a time from cassette after you use CSHIN. A = the data - * byte. - */ - -#define _TRS80_M3_CSIN 0x0235 - -/* Outputs data one byte at a time to cassette after you use CSHWR. A = the - * output byte. - */ - -#define _TRS80_M3_CSOUT 0x0264 - -/* Turns on the cassette and writes the header. */ - -#define _TRS80_M3_CSHWR 0x0287 - -/* Finds the cassette header info at the beggining of cassette file. */ - -#define _TRS80_M3_CSHIN 0x0296 - -/* Ouput character in register A; OUTSEL (409CH) selects device. See OUTSEL for - * device values. - */ - -#define _TRS80_M3_OUTCHR 0x032A - -/* Displays character in A on screen at next print position. Uses AF. */ - -#define _TRS80_M3_DISPA 0x033A - -/* Calls keyboard scan routine. */ - -#define _TRS80_M3_keyb_scan 0x0358 - -/* Reads keyboard into buffer until a carriage return is entered. 40A7H contains - * the address of the buffer. - */ - -#define _TRS80_M3_KIBUFF 0x0361 - -/* Same as KBLINE. See 0040. */ - -#define _TRS80_M3_KLINE 0x05D9 - -/* "Get date in ASCII format. Mod III TRSDOS, LDOS, & MULTIDOS." */ - -#define _TRS80_M3_GETDAT 0x3033 - -/* "Get time in ASCII format. Mod III TRSDOS, LDOS, & MULTIDOS." */ - -#define _TRS80_M3_GETTIM 0x3036 - -#endif /* __TRS80_M3_H */ diff --git a/configs/xtrs/nsh/defconfig b/configs/xtrs/nsh/defconfig deleted file mode 100644 index 57c2b3c6292cc0727ae53b5b9575fca717f9613d..0000000000000000000000000000000000000000 --- a/configs/xtrs/nsh/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# CONFIG_NSH_DISABLE_DD is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -CONFIG_ARCH_BOARD_XTRS=y -CONFIG_ARCH_BOARD="xtrs" -CONFIG_ARCH_CHIP_Z80=y -CONFIG_ARCH_Z80=y -CONFIG_ARCH="z80" -CONFIG_BOARD_LOOPSPERMSEC=100 -CONFIG_DEFAULT_SMALL=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POLL=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_EXAMPLES_NSH=y -CONFIG_HOST_WINDOWS=y -CONFIG_LINKER_CODE_AREA=0x5300 -CONFIG_LINKER_HOME_AREA=0x5200 -CONFIG_LINKER_ROM_AT_0000=y -CONFIG_MAX_TASKS=8 -CONFIG_MAX_WDOGPARMS=2 -CONFIG_NFILE_DESCRIPTORS=6 -CONFIG_NFILE_STREAMS=6 -CONFIG_NOPRINTF_FIELDWIDTH=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_NSH_LINELEN=40 -CONFIG_NUNGET_CHARS=0 -CONFIG_PREALLOC_TIMERS=0 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x0000 -CONFIG_SDCLONE_DISABLE=y -CONFIG_START_DAY=9 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2012 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_UART_RXBUFSIZE=64 -CONFIG_UART_TXBUFSIZE=64 -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_USERMAIN_STACKSIZE=1024 -CONFIG_WDOG_INTRESERVE=0 -CONFIG_WINDOWS_NATIVE=y diff --git a/configs/xtrs/ostest/defconfig b/configs/xtrs/ostest/defconfig deleted file mode 100644 index 8a4c66f3e0d76b17d7341cdb8d89daa41f776313..0000000000000000000000000000000000000000 --- a/configs/xtrs/ostest/defconfig +++ /dev/null @@ -1,43 +0,0 @@ -# CONFIG_DEV_CONSOLE is not set -CONFIG_ARCH_BOARD_XTRS=y -CONFIG_ARCH_BOARD="xtrs" -CONFIG_ARCH_CHIP_Z80=y -CONFIG_ARCH_Z80=y -CONFIG_ARCH="z80" -CONFIG_BOARD_LOOPSPERMSEC=100 -CONFIG_DEFAULT_SMALL=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POLL=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=4 -CONFIG_EXAMPLES_OSTEST_STACKSIZE=1024 -CONFIG_EXAMPLES_OSTEST=y -CONFIG_HOST_WINDOWS=y -CONFIG_LINKER_CODE_AREA=0x5300 -CONFIG_LINKER_HOME_AREA=0x5200 -CONFIG_LINKER_ROM_AT_0000=y -CONFIG_MAX_TASKS=8 -CONFIG_MAX_WDOGPARMS=2 -CONFIG_NFILE_DESCRIPTORS=0 -CONFIG_NFILE_STREAMS=0 -CONFIG_NOPRINTF_FIELDWIDTH=y -CONFIG_NUNGET_CHARS=0 -CONFIG_PREALLOC_TIMERS=0 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x0000 -CONFIG_SDCLONE_DISABLE=y -CONFIG_START_DAY=21 -CONFIG_START_MONTH=2 -CONFIG_START_YEAR=2008 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_UART_RXBUFSIZE=64 -CONFIG_UART_SERIAL_CONSOLE=y -CONFIG_UART_TXBUFSIZE=64 -CONFIG_USER_ENTRYPOINT="ostest_main" -CONFIG_USERMAIN_STACKSIZE=1024 -CONFIG_WDOG_INTRESERVE=0 -CONFIG_WINDOWS_NATIVE=y diff --git a/configs/xtrs/pashello/defconfig b/configs/xtrs/pashello/defconfig deleted file mode 100644 index fb66a95171896aa067afc82e45ae3f22322769fb..0000000000000000000000000000000000000000 --- a/configs/xtrs/pashello/defconfig +++ /dev/null @@ -1,45 +0,0 @@ -# CONFIG_DISABLE_ENVIRON is not set -CONFIG_ARCH_BOARD_XTRS=y -CONFIG_ARCH_BOARD="xtrs" -CONFIG_ARCH_CHIP_Z80=y -CONFIG_ARCH_Z80=y -CONFIG_ARCH="z80" -CONFIG_BOARD_LOOPSPERMSEC=100 -CONFIG_DEFAULT_SMALL=y -CONFIG_DEV_LOWCONSOLE=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POLL=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_DISABLE_SIGNALS=y -CONFIG_EXAMPLES_PASHELLO=y -CONFIG_HOST_WINDOWS=y -CONFIG_INTERPRETERS_PCODE=y -CONFIG_LINKER_CODE_AREA=0x5300 -CONFIG_LINKER_HOME_AREA=0x5200 -CONFIG_LINKER_ROM_AT_0000=y -CONFIG_MAX_TASKS=8 -CONFIG_MAX_WDOGPARMS=2 -CONFIG_NFILE_DESCRIPTORS=4 -CONFIG_NFILE_STREAMS=4 -CONFIG_NOPRINTF_FIELDWIDTH=y -CONFIG_NUNGET_CHARS=0 -CONFIG_PREALLOC_TIMERS=0 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x0000 -CONFIG_SDCLONE_DISABLE=y -CONFIG_START_DAY=9 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2012 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_SYSTEM_PRUN=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_UART_RXBUFSIZE=64 -CONFIG_UART_SERIAL_CONSOLE=y -CONFIG_UART_TXBUFSIZE=64 -CONFIG_USER_ENTRYPOINT="pashello_main" -CONFIG_USERMAIN_STACKSIZE=1024 -CONFIG_WDOG_INTRESERVE=0 -CONFIG_WINDOWS_NATIVE=y diff --git a/configs/xtrs/scripts/Make.defs b/configs/xtrs/scripts/Make.defs deleted file mode 100644 index b61a8b3b65c67a411e41036a91d8829be79844cb..0000000000000000000000000000000000000000 --- a/configs/xtrs/scripts/Make.defs +++ /dev/null @@ -1,171 +0,0 @@ -############################################################################ -# configs/xtrs/scripts/Make.defs -# -# Copyright (C) 2007, 2008, 2012, 2017 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk - -# These are the directories where the SDCC toolchain is installed. NOTE -# that short 8.3 path names are used in order to avoid spaces. On my machine -# I have: -# -# C:\PROGRA~1\ = C:\Profram Files\ -# C:\PROGRA~2\ = C:\Program Files (x86)\ -# -# Your PC may be configured differently. - -ifeq ($(CONFIG_WINDOWS_NATIVE),y) - SDCC_INSTALLDIR = C:\PROGRA~2\SDCC - SDCC_BINDIR = $(SDCC_INSTALLDIR)\bin - SDCC_LIBDIR = $(SDCC_INSTALLDIR)\lib\z80 -else - SDCC_INSTALLDIR = /usr/local - SDCC_BINDIR = $(SDCC_INSTALLDIR)/bin - SDCC_LIBDIR = $(SDCC_INSTALLDIR)/share/sdcc/lib/z80 -endif - -CROSSDEV = -CC = sdcc -CPP = sdcpp -LD = sdldz80 -AS = sdasz80 -AR = sdar -r -ARCHCPUFLAGS = -mz80 - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = --debug -else - ARCHOPTIMIZATION = -endif - -ARCHPICFLAGS = -ARCHWARNINGS = -ARCHDEFINES = -ARCHINCLUDES = -I. -I$(TOPDIR)$(DELIM)include - -CFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -AFLAGS = -x -a -l -o -s -g - -SDCCLIB = z80.lib - -ASMEXT = .asm -OBJEXT = .rel -LIBEXT = .lib -EXEEXT = .cmd - -# Custom ASSEMBLE definition. The most common toolchain, GCC, uses the -# compiler to assemble files because this has the advantage of running the C -# Pre-Processor against. This is not possible with other SDCC; we need to -# define AS and over-ride the common definition in order to use the assembler -# directly. - -define ASSEMBLE - @echo "AS: $1" - $(Q) $(AS) $(AFLAGS) $2 $1 -endef - -# Custom CLEAN definition - -ifeq ($(CONFIG_WINDOWS_NATIVE),y) -define CLEAN - $(Q) if exist *.o (del /f /q *.o) - $(Q) if exist *.asm (del /f /q *.asm) - $(Q) if exist *.rel (del /f /q *.rel) - $(Q) if exist *.lst (del /f /q *.lst) - $(Q) if exist *.rst (del /f /q *.rst) - $(Q) if exist *.sym (del /f /q *.sym) - $(Q) if exist *.adb (del /f /q *.adb) - $(Q) if exist *.lnk (del /f /q *.lnk) - $(Q) if exist *.map (del /f /q *.map) - $(Q) if exist *.mem (del /f /q *.mem) - $(Q) if exist *.hex (del /f /q *.hex) - $(Q) if exist *.cmd (del /f /q *.cmd) -endef -else -define CLEAN - $(Q) rm -f *.o *.asm *.rel *.lst *.rst *.sym *.adb *.lnk *.map *.mem *.hex *.cmd -endef -endif - -# Windows native host tool definitions - -ifeq ($(CONFIG_WINDOWS_NATIVE),y) - HOSTCC = mingw32-gcc.exe - HOSTINCLUDES = -I. - HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe - HOSTLDFLAGS = - HOSTEXEEXT = .exe - - # Windows-native host tools - - MKDEP = $(TOPDIR)\tools\mkdeps$(HOSTEXEEXT) --winnative - - # Use NTFS links or directory copies - -ifeq ($(CONFIG_WINDOWS_MKLINK),y) - DIRLINK = $(TOPDIR)$(DELIM)tools$(DELIM)link.bat -else - DIRLINK = $(TOPDIR)$(DELIM)tools$(DELIM)copydir.bat -endif -DIRUNLINK = $(TOPDIR)$(DELIM)tools$(DELIM)unlink.bat - -else - -# Linux/Cygwin host tool definitions - - HOSTCC = gcc - HOSTINCLUDES = -I. - HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe - HOSTLDFLAGS = - - # This is the tool to use for dependencies - - ifeq ($(WINTOOL),y) - MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mkwindeps.sh - else - MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) - endif - - # SDCC for Linux, OSX, or Cygwin understands symbolic links. Windows SDCC - # running under Cygwin does not - -ifeq ($(WINTOOL),y) - DIRLINK = $(TOPDIR)$(DELIM)tools$(DELIM)copydir.sh -else - DIRLINK = $(TOPDIR)$(DELIM)tools$(DELIM)link.sh -endif -DIRUNLINK = $(TOPDIR)$(DELIM)tools$(DELIM)unlink.sh - -endif diff --git a/configs/xtrs/src/.gitignore b/configs/xtrs/src/.gitignore deleted file mode 100644 index 91e29681eea74930dc7a35a0427623c938739152..0000000000000000000000000000000000000000 --- a/configs/xtrs/src/.gitignore +++ /dev/null @@ -1,13 +0,0 @@ -/Make.dep -/.depend -/*.sym -/*.rel -/*.lst -/*.adb -/*.rst -/*.lib -/*.lnk -/*.map -/*.mem -/*.ihx -/*.hex diff --git a/configs/xtrs/src/xtr_serial.c b/configs/xtrs/src/xtr_serial.c deleted file mode 100644 index ed2ef03fa800a58dd6f504750d5f6ebda03aa529..0000000000000000000000000000000000000000 --- a/configs/xtrs/src/xtr_serial.c +++ /dev/null @@ -1,413 +0,0 @@ -/**************************************************************************** - * config/xtrs/src/xtr_serial.c - * - * Copyright (C) 2008 Jacques Pelletier. All rights reserved. - * Author: Jacques Pelletier - * - * This file is a part of NuttX and hence - * - * Copyright (C) 2008-2009, 2012 Gregory Nutt. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "up_arch.h" -#include "up_internal.h" - -#ifdef USE_SERIALDRIVER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -#define TRSDOS 0 /* TRSDOS 1.3 */ -#define LDOS 1 /* LDOS 5.3.1 */ - -#define MODEM_STATUS 0xe8 -#define RESET 0xe8 -#define BAUD 0xe9 -#define STATUS 0xea -#define CONTROL 0xea -#define RECV_REG 0xeb -#define XMIT_REG 0xeb - -#define XMIT_REG_EMPTY 0x40 - -#define WRINTMASK 0xe0 - -#define MASK_XMIT_INT 0x10 -#define MASK_RECV_INT 0x20 -#define MASK_ERR_INT 0x40 - -#if TRSDOS -#define WRINTMASK_SHADOW 0x4213 -#define XMIT_INT_VECTOR 0x4207 -#define RECV_INT_VECTOR 0x420a -#endif - -#if LDOS -#define WRINTMASK_SHADOW 0x4474 -#define XMIT_INT_VECTOR 0x447D -#define RECV_INT_VECTOR 0x447F -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int up_setup(FAR struct uart_dev_s *dev); -static void up_shutdown(FAR struct uart_dev_s *dev); -static int up_attach(FAR struct uart_dev_s *dev); -static void up_detach(FAR struct uart_dev_s *dev); -static int up_ioctl(FAR struct file *filep, int cmd, unsigned long arg); -static int up_receive(FAR struct uart_dev_s *dev, unsigned int *status); -static void up_rxint(FAR struct uart_dev_s *dev, bool enable); -static bool up_rxavailable(FAR struct uart_dev_s *dev); -static void up_send(FAR struct uart_dev_s *dev, int ch); -static void up_txint(FAR struct uart_dev_s *dev, bool enable); -static bool up_txready(FAR struct uart_dev_s *dev); -static bool up_txempty(FAR struct uart_dev_s *dev); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct uart_ops_s g_uart_ops = -{ - up_setup, /* setup */ - up_shutdown, /* shutdown */ - up_attach, /* attach */ - up_detach, /* detach */ - up_ioctl, /* ioctl */ - up_receive, /* receive */ - up_rxint, /* rxint */ - up_rxavailable, /* rxavailable */ -#ifdef CONFIG_SERIAL_IFLOWCONTROL - NULL, /* rxflowcontrol */ -#endif - up_send, /* send */ - up_txint, /* txint */ - up_txready, /* txready */ - up_txempty, /* txempty */ -}; - -/* I/O buffers */ - -static char g_uartrxbuffer[CONFIG_UART_RXBUFSIZE]; -static char g_uarttxbuffer[CONFIG_UART_TXBUFSIZE]; - -/* This describes the state of the fake UART port. */ - -static uart_dev_t g_uartport = -{ - 0, /* open_count */ - false, /* xmitwaiting */ - false, /* recvwaiting */ - false, /* isconsole */ - { 1 }, /* closesem */ - { 0 }, /* xmitsem */ - { 0 }, /* recvsem */ - { /* xmit */ - { 1 }, /* sem */ - 0, /* head */ - 0, /* tail */ - CONFIG_UART_TXBUFSIZE, /* size */ - g_uarttxbuffer, /* buffer */ - }, - { /* recv */ - { 1 }, /* sem */ - 0, /* head */ - 0, /* tail */ - CONFIG_UART_RXBUFSIZE, /* size */ - g_uartrxbuffer, /* buffer */ - }, - &g_uart_ops, /* ops */ - NULL, /* priv */ -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_setup - * - * Description: - * Configure the UART baud, bits, parity, fifos, etc. This - * method is called the first time that the serial port is - * opened. - * - ****************************************************************************/ - -static int up_setup(FAR struct uart_dev_s *dev) -{ - outp(RESET, 0); - outp(CONTROL, ctrl); - outp(BAUD, baud); - - return OK; -} - -/**************************************************************************** - * Name: up_shutdown - * - * Description: - * Disable the UART. This method is called when the serial - * port is closed - * - ****************************************************************************/ - -static void up_shutdown(FAR struct uart_dev_s *dev) -{ -} - -/**************************************************************************** - * Name: up_attach - * - * Description: - * Configure the UART to operation in interrupt driven mode. This method is - * called when the serial port is opened. Normally, this is just after the - * setup() method is called, however, the serial console may operate in a - * non-interrupt driven mode during the boot phase. - * - * RX and TX interrupts are not enabled by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. - * - ****************************************************************************/ - -static int up_attach(FAR struct uart_dev_s *dev) -{ -// SDCC complains here -// *((void (*)()) XMIT_INT_VECTOR) = rs232_xmitisr; -// *((void (*)()) RECV_INT_VECTOR) = rs232_recvisr; - *((int *) XMIT_INT_VECTOR) = (int) rs232_xmitisr; - *((int *) RECV_INT_VECTOR) = (int) rs232_recvisr; - - *(char *)WRINTMASK_SHADOW &= ~(MASK_ERR_INT | MASK_XMIT_INT); - outp(WRINTMASK, *(char *)WRINTMASK_SHADOW |= MASK_RECV_INT); - - return OK; -} - -/**************************************************************************** - * Name: up_detach - * - * Description: - * Detach UART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The exception is - * the serial console which is never shutdown. - * - ****************************************************************************/ - -static void up_detach(FAR struct uart_dev_s *dev) -{ - outp(WRINTMASK, *(char *)WRINTMASK_SHADOW &= ~(MASK_ERR_INT | MASK_RECV_INT | MASK_XMIT_INT)); - *((int *) XMIT_INT_VECTOR) = 0x35fa; - *((int *) RECV_INT_VECTOR) = 0x35fa; -} - -/**************************************************************************** - * Name: up_ioctl - * - * Description: - * All ioctl calls will be routed through this method - * - ****************************************************************************/ - -static int up_ioctl(FAR struct file *filep, int cmd, unsigned long arg) -{ - return -ENOTTY; -} - -/**************************************************************************** - * Name: up_receive - * - * Description: - * Called (usually) from the interrupt level to receive one - * character from the UART. Error bits associated with the - * receipt are provided in the return 'status'. - * - ****************************************************************************/ - -static int up_receive(FAR struct uart_dev_s *dev, unsigned int *status) -{ -// uint8_t ch = z80_lowputc(); - - *status = 0; - return ch; -} - -/**************************************************************************** - * Name: up_rxint - * - * Description: - * Call to enable or disable RX interrupts - * - ****************************************************************************/ - -static void up_rxint(FAR struct uart_dev_s *dev, bool enable) -{ -} - -/**************************************************************************** - * Name: up_rxavailable - * - * Description: - * Return true if the receive fifo is not empty - * - ****************************************************************************/ - -static bool up_rxavailable(FAR struct uart_dev_s *dev) -{ - return true; -} - -/**************************************************************************** - * Name: up_send - * - * Description: - * This method will send one byte on the UART - * - ****************************************************************************/ - -static void up_send(FAR struct uart_dev_s *dev, int ch) -{ - z80_lowputc(ch); -} - -/**************************************************************************** - * Name: up_txint - * - * Description: - * Call to enable or disable TX interrupts - * - ****************************************************************************/ - -static void up_txint(FAR struct uart_dev_s *dev, bool enable) -{ -} - -/**************************************************************************** - * Name: up_txready - * - * Description: - * Return true if the transmit fifo is not full - * - ****************************************************************************/ - -static bool up_txready(FAR struct uart_dev_s *dev) -{ - return true; -} - -/**************************************************************************** - * Name: up_txempty - * - * Description: - * Return true if the transmit fifo is empty - * - ****************************************************************************/ - -static bool up_txempty(FAR struct uart_dev_s *dev) -{ - return true; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_serialinit - * - * Description: - * Performs the low level UART initialization early in - * debug so that the serial console will be available - * during bootup. This must be called before up_serialinit. - * - ****************************************************************************/ - -void up_earlyserialinit(void) -{ -} - -/**************************************************************************** - * Name: up_serialinit - * - * Description: - * Register serial ports. This assumes - * that up_earlyserialinit was called previously. - * - ****************************************************************************/ - -void up_serialinit(void) -{ - (void)uart_register("/dev/console", &g_uartport); - (void)uart_register("/dev/ttyS0", &g_uartport); -} -#endif /* USE_SERIALDRIVER */ - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug - * writes - * - ****************************************************************************/ - -int up_putc(int ch) -{ - z80_lowputc(ch); - return 0; -} diff --git a/configs/xtrs/src/xtrs_head.asm b/configs/xtrs/src/xtrs_head.asm deleted file mode 100644 index db717ef097b22a495a3e34f291c4bcbd7372ae91..0000000000000000000000000000000000000000 --- a/configs/xtrs/src/xtrs_head.asm +++ /dev/null @@ -1,296 +0,0 @@ -;************************************************************************** -; configs/xtrs/src/xtrs_head.asm -; -; Copyright (C) 2008-2009, 2012 Gregory Nutt. All rights reserved. -; Author: Gregory Nutt -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions -; are met: -; -; 1. Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in -; the documentation and/or other materials provided with the -; distribution. -; 3. Neither the name NuttX nor the names of its contributors may be -; used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; -;************************************************************************** - - .title NuttX for the Z80 - .module xtrs_head - -;************************************************************************** -; Constants -;************************************************************************** - - ; Register save area layout - - XCPT_I == 0 ; Offset 0: Saved I w/interrupt state in parity - XCPT_BC == 2 ; Offset 1: Saved BC register - XCPT_DE == 4 ; Offset 2: Saved DE register - XCPT_IX == 6 ; Offset 3: Saved IX register - XCPT_IY == 8 ; Offset 4: Saved IY register - XCPT_SP == 10 ; Offset 5: Offset to SP at time of interrupt - XCPT_HL == 12 ; Offset 6: Saved HL register - XCPT_AF == 14 ; Offset 7: Saved AF register - XCPT_PC == 16 ; Offset 8: Offset to PC at time of interrupt - - ; Default stack base (needs to be fixed) - - .include "asm_mem.h" - -;************************************************************************** -; Global symbols used -;************************************************************************** - - .globl _os_start ; OS entry point - .globl _up_doirq ; Interrupt decoding logic - -;************************************************************************** -; System start logic -;************************************************************************** - -_up_reset: - ; Set up the stack pointer at the location determined the Makefile - ; and stored in asm_mem.h - - ld SP, #CONFIG_STACK_END ; Set stack pointer - - ; Performed initialization unique to the SDCC toolchain - - call gsinit ; Initialize the data section - - ; Copy the reset vectors - - ld hl, #_up_rstvectors ; code for RAM - ld de, #0x4000 ; move it here - ld bc, #3*7 ; 7 vectors / 3 bytes each - ldir - - ; Then start NuttX - - call _os_start ; jump to the OS entry point - - ; NuttX will never return, but just in case... - -_up_halt:: - halt ; We should never get here - jp _up_halt - - ; Data to copy to address 0x4000 - -_up_rstvectors: - jp _up_rst1 ; 0x4000 : RST 1 - jp _up_rst2 ; 0x4003 : RST 2 - jp _up_rst3 ; 0x4006 : RST 3 - jp _up_rst4 ; 0x4009 : RST 4 - jp _up_rst5 ; 0x400c : RST 5 - jp _up_rst6 ; 0x400f : RST 6 - jp _up_rst7 ; 0x4012 : RST 7 - -;************************************************************************** -; Other reset handlers -; -; Interrupt mode 1 behavior: -; -; 1. M1 cycle: 7 ticks -; Acknowledge interrupt and decrements SP -; 2. M2 cycle: 3 ticks -; Writes the MS byte of the PC onto the stack and decrements SP -; 3. M3 cycle: 3 ticks -; Writes the LS byte of the PC onto the stack and sets the PC to 0x0038. -; -;************************************************************************** - -_up_rst1: ; RST 1 - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #1 ; 1 = Z80_RST1 - jr _up_rstcommon ; Remaining RST handling is common - -_up_rst2: ; RST 2 - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #2 ; 2 = Z80_RST2 - jr _up_rstcommon ; Remaining RST handling is common - -_up_rst3: ; RST 3 - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #3 ; 1 = Z80_RST3 - jr _up_rstcommon ; Remaining RST handling is common - -_up_rst4: ; RST 4 - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #4 ; 1 = Z80_RST4 - jr _up_rstcommon ; Remaining RST handling is common - -_up_rst5: ; RST 5 - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #5 ; 1 = Z80_RST5 - jr _up_rstcommon ; Remaining RST handling is common - -_up_rst6: ; RST 6 - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #6 ; 1 = Z80_RST6 - jr _up_rstcommon ; Remaining RST handling is common - -_up_rst7: ; RST 7 - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #7 ; 7 = Z80_RST7 - jr _up_rstcommon ; Remaining RST handling is common - -;************************************************************************** -; Common Interrupt handler -;************************************************************************** - -_up_rstcommon: - ; Create a register frame. SP points to top of frame + 4, pushes - ; decrement the stack pointer. Already have - ; - ; Offset 8: Return PC is already on the stack - ; Offset 7: AF (retaining flags) - ; - ; IRQ number is in A - - push hl ; Offset 6: HL - ld hl, #(3*2) ; HL is the value of the stack pointer before - add hl, sp ; the interrupt occurred - push hl ; Offset 5: Stack pointer - push iy ; Offset 4: IY - push ix ; Offset 3: IX - push de ; Offset 2: DE - push bc ; Offset 1: BC - - ld b, a ; Save the reset number in B - ld a, i ; Parity bit holds interrupt state - push af ; Offset 0: I with interrupt state in parity - di - - ; Call the interrupt decode logic. SP points to the beggining of the reg structure - - ld hl, #0 ; Argument #2 is the beginning of the reg structure - add hl, sp ; - push hl ; Place argument #2 at the top of stack - push bc ; Argument #1 is the Reset number - inc sp ; (make byte sized) - call _up_doirq ; Decode the IRQ - - ; On return, HL points to the beginning of the reg structure to restore - ; Note that (1) the arguments pushed on the stack are not popped, and (2) the - ; original stack pointer is lost. In the normal case (no context switch), - ; HL will contain the value of the SP before the arguments wer pushed. - - ld sp, hl ; Use the new stack pointer - - ; Restore registers. HL points to the beginning of the reg structure to restore - - ex af, af' ; Select alternate AF - pop af ; Offset 0: AF' = I with interrupt state in parity - ex af, af' ; Restore original AF - pop bc ; Offset 1: BC - pop de ; Offset 2: DE - pop ix ; Offset 3: IX - pop iy ; Offset 4: IY - exx ; Use alternate BC/DE/HL - ld hl, #-2 ; Offset of SP to account for ret addr on stack - pop de ; Offset 5: HL' = Stack pointer after return - add hl, de ; HL = Stack pointer value before return - exx ; Restore original BC/DE/HL - pop hl ; Offset 6: HL - pop af ; Offset 7: AF - - ; Restore the stack pointer - - exx ; Use alternate BC/DE/HL - ld sp, hl ; Set SP = saved stack pointer value before return - exx ; Restore original BC/DE/HL - - ; Restore interrupt state - - ex af, af' ; Recover interrupt state - jp po, nointenable ; Odd parity, IFF2=0, means disabled - ex af, af' ; Restore AF (before enabling interrupts) - ei ; yes - reti -nointenable:: - ex af, af' ; Restore AF - reti - -;************************************************************************** -; Ordering of segments for the linker (SDCC only) -;************************************************************************** - - .area _HOME - .area _CODE - .area _INITIALIZER - .area _GSINIT - .area _GSFINAL - - .area _DATA - .area _INITIALIZED - .area _BSEG - .area _BSS - .area _HEAP - -;************************************************************************** -; Global data initialization logic (SDCC only) -;************************************************************************** - - .area _GSINIT -gsinit:: - ld bc, #l__INITIALIZER - ld a, b - or a, c - jr Z, gsinit_next - ld de, #s__INITIALIZED - ld hl, #s__INITIALIZER - ldir -gsinit_next: - - .area _GSFINAL - ret - -;************************************************************************** -; The start of the heap (SDCC only). Note that is actually resides in -; the _CODE area (which may be FLASH or ROM) -;************************************************************************** - - .area _CODE -_g_heapbase:: - .dw #s__HEAP diff --git a/configs/zkit-arm-1769/README.txt b/configs/zkit-arm-1769/README.txt index 3a26764bba8bd2fed60636a7ed9af23a7bbe27fb..615c67f5be075dcce1a5170939cd3bbb0fd8ec18 100644 --- a/configs/zkit-arm-1769/README.txt +++ b/configs/zkit-arm-1769/README.txt @@ -8,9 +8,6 @@ Contents ^^^^^^^^ ZKit-ARM LPC1769 Board - Development Environment - GNU Toolchain Options - NuttX buildroot Toolchain LEDs ZKit-ARM Configuration Options Configurations @@ -139,147 +136,6 @@ USB Device P1.25/MCOA1/MAT1.1 | LCD-RST LCD Reset (RSTB) - Resets Everything in LCD ----------------------------+--------------- ------------------------------------------- -Development Environment -^^^^^^^^^^^^^^^^^^^^^^^ - - Either Linux or Cygwin on Windows can be used for the development environment. - The source has been built only using the GNU toolchain (see below). Other - toolchains will likely cause problems. Testing was performed using the Cygwin - environment. - -GNU Toolchain Options -^^^^^^^^^^^^^^^^^^^^^ - - The NuttX make system has been modified to support the following different - toolchain options. - - 1. The Code Red GNU toolchain - 2. The CodeSourcery GNU toolchain, - 3. The devkitARM GNU toolchain, - 4. The NuttX buildroot Toolchain (see below). - - All testing has been conducted using the Code Red toolchain and the - make system is setup to default to use the Code Red Linux toolchain. To use - the other toolchain, you simply need add one of the following configuration - options to your .config (or defconfig) file: - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux - CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM=y : devkitARM under Windows - CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default) - CONFIG_ARMV7M_TOOLCHAIN_CODEREDW=y : Code Red toolchain under Windows - CONFIG_ARMV7M_TOOLCHAIN_CODEREDL=y : Code Red toolchain under Linux - CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : The Atollic toolchain - - NOTE: the CodeSourcery (for Windows), devkitARM, and Code Red (for Windoes) - are Windows native toolchains. The CodeSourcey (for Linux), Code Red (for Linux) - and NuttX buildroot toolchains are Cygwin and/or Linux native toolchains. There - are several limitations to using a Windows based toolchain in a Cygwin - environment. The three biggest are: - - 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are - performed automatically in the Cygwin makefiles using the 'cygpath' utility - but you might easily find some new path problems. If so, check out 'cygpath -w' - - 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links - are used in Nuttx (e.g., include/arch). The make system works around these - problems for the Windows tools by copying directories instead of linking them. - But this can also cause some confusion for you: For example, you may edit - a file in a "linked" directory and find that your changes had no effect. - That is because you are building the copy of the file in the "fake" symbolic - directory. If you use a Windows toolchain, you should get in the habit of - making like this: - - make clean_context all - - An alias in your .bashrc file might make that less painful. - - NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization - level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with - -Os. - - NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that - the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM - path or will get the wrong version of make. - -NuttX buildroot Toolchain -^^^^^^^^^^^^^^^^^^^^^^^^^ - - A GNU GCC-based toolchain is assumed. The PATH variable should be modified to - point to the correct path to the Cortex-M3 GCC toolchain (if different from the - default in your PATH variable). - - If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/nuttx/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh zkit-arm-1769/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-4.3.3 .config - - 6. make oldconfig - - 7. make - - 8. Make sure that your PATH variable includes the path to the newly built - binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - detailed PLUS some special instructions that you will need to follow if you - are building a Cortex-M3 toolchain for Cygwin under Windows. - - NOTE: The cortexm3-defconfig-4.3.3 produces an older-style is OABI toolchain. - There is another configuration, cortexm3-eabi-defconfig-4.6.3, that will - build a newer, EABI, toolchain. Unfortunately, the 4.6.3 EABI toolchain is - not compatible with the NXFLAT tools. See the top-level TODO file (under - "Binary loaders") for more information about this problem. If you plan to - use NXFLAT, please do not use the GCC 4.6.3 EABI toochain; instead use the - GCC 4.3.3 OABI toolchain. - -NXFLAT Toolchain -^^^^^^^^^^^^^^^^ - - If you are *not* using the NuttX buildroot toolchain and you want to use - the NXFLAT tools, then you will still have to build a portion of the buildroot - tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can - be downloaded from the NuttX Bitbucket download site - (https://bitbucket.org/nuttx/nuttx/downloads/). - - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh zkit-arm-1769/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/cortexm3-defconfig-nxflat .config - - 6. make oldconfig - - 7. make - - 8. Make sure that the PATH variable includes the path to the newly built - NXFLAT binaries. - LEDs ^^^^ diff --git a/configs/zkit-arm-1769/include/board.h b/configs/zkit-arm-1769/include/board.h index 5003145d5228fc13de6293d999fb19f3b7c83050..0e69f32971b43a79e35a30a94db900515200540e 100644 --- a/configs/zkit-arm-1769/include/board.h +++ b/configs/zkit-arm-1769/include/board.h @@ -194,7 +194,7 @@ #define BOARD_BUTTON_3 2 #define BOARD_BUTTON_4 3 #define BOARD_BUTTON_5 4 -#define BOARD_NUM_BUTTONS 5 +#define NUM_BUTTONS 5 #define BOARD_BUTTON1_BIT (1 << BOARD_BUTTON_1) #define BOARD_BUTTON2_BIT (1 << BOARD_BUTTON_2) @@ -330,17 +330,6 @@ extern "C" { /************************************************************************************ * Public Function Prototypes ************************************************************************************/ -/************************************************************************************ - * Name: lpc17_boardinitialize - * - * Description: - * All LPC17xx architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void lpc17_boardinitialize(void); /************************************************************************************ * Name: lpc17_led diff --git a/configs/zkit-arm-1769/nsh/defconfig b/configs/zkit-arm-1769/nsh/defconfig index 3dcfabe078c01606ad70b4482378a91ac71f06ae..b6157e5acbdc14a476cc33d8ea2671c6d5321744 100644 --- a/configs/zkit-arm-1769/nsh/defconfig +++ b/configs/zkit-arm-1769/nsh/defconfig @@ -1,4 +1,4 @@ -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_DF_H is not set diff --git a/configs/zkit-arm-1769/nxhello/defconfig b/configs/zkit-arm-1769/nxhello/defconfig index 2ab4c5a1761f194423214d7d48a57c689aef037c..732573cceb507913fc6a1858669f5529f200601a 100644 --- a/configs/zkit-arm-1769/nxhello/defconfig +++ b/configs/zkit-arm-1769/nxhello/defconfig @@ -1,5 +1,5 @@ # CONFIG_EXAMPLES_NXHELLO_DEFAULT_COLORS is not set -# CONFIG_MMCSD_HAVECARDDETECT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set diff --git a/configs/zkit-arm-1769/src/lpc17_buttons.c b/configs/zkit-arm-1769/src/lpc17_buttons.c index e93f27734f735dc48dbe6ac4b7061a6d0a95732e..0c0de7dedd4302aecb7156a57d6bbaa5ac10613a 100644 --- a/configs/zkit-arm-1769/src/lpc17_buttons.c +++ b/configs/zkit-arm-1769/src/lpc17_buttons.c @@ -68,10 +68,10 @@ * Private Data ****************************************************************************/ /* Pin configuration for each zkit-arm-1769 button. This array is indexed by - * BOARD_NUM_BUTTONS in board.h + * NUM_BUTTONS in board.h */ -static const uint16_t g_buttons[BOARD_NUM_BUTTONS] = +static const uint16_t g_buttons[NUM_BUTTONS] = { ZKITARM_KEY1, ZKITARM_KEY2, ZKITARM_KEY3, ZKITARM_KEY4, ZKITARM_KEY5 }; @@ -99,7 +99,7 @@ void board_button_initialize(void) * configured for some pins but NOT used in this file */ - for (i = 0; i < BOARD_NUM_BUTTONS; i++) + for (i = 0; i < NUM_BUTTONS; i++) { lpc17_configgpio(g_buttons[i]); } @@ -117,7 +117,7 @@ uint32_t board_buttons(void) /* Check that state of each key */ - for (i = 0; i < BOARD_NUM_BUTTONS; i++) + for (i = 0; i < NUM_BUTTONS; i++) { released = lpc17_gpioread(g_buttons[i]); diff --git a/configs/zp214xpa/README.txt b/configs/zp214xpa/README.txt index ca4f79038eeafe9d49c9690d7ea872e0816c71c2..d2943d62df16af22e7c2f96df704615938aa3bf9 100644 --- a/configs/zp214xpa/README.txt +++ b/configs/zp214xpa/README.txt @@ -236,7 +236,7 @@ Using OpenOCD and GDB with an FT2232 JTAG emulator configs/zp214xpa/tools/oocd.sh $PWD - If you add that path to your PATH environment variable, ithe commandi + If you add that path to your PATH environment variable, the command simplifies to just: oocd.sh $PWD @@ -309,9 +309,9 @@ Configurations: 2. Default platform/toolchain: - CONFIG_HOST_LINUX=y : Linux (Cygwin under Windows okay too). + CONFIG_HOST_LINUX=y : Linux (Cygwin under Windows okay too). CONFIG_ARM_TOOLCHAIN_GNU_EABIL=y : Buildroot (arm-nuttx-elf-gcc) - CONFIG_RAW_BINARY=y : Output formats: ELF and raw binary + CONFIG_RAW_BINARY=y : Output formats: ELF and raw binary nxlines: -------- @@ -333,8 +333,16 @@ Configurations: 2. Default platform/toolchain: - CONFIG_HOST_LINUX=y : Linux (Cygwin under Windows okay too). + CONFIG_HOST_LINUX=y : Linux (Cygwin under Windows okay too). CONFIG_ARM_TOOLCHAIN_GNU_EABIL=y : Buildroot (arm-nuttx-elf-gcc) - CONFIG_RAW_BINARY=y : Output formats: ELF and raw binary + CONFIG_RAW_BINARY=y : Output formats: ELF and raw binary + + STATUS: + 2012-12-30: Configuration verified. + + 2017-11-25: Grrr... This configuration no longer works. Some serious bit + rot has set in. Now only random garbage appears on the OLED. Certainly + a lot has changed since 2012, but I cannot see any change to either this + configuration, to the LCD driver, or to the LPC2148 support that would + affect the operation of the LCD. The nsh configuration is still functional. - 3. Verified as of this writing (2012-12-30). diff --git a/configs/zp214xpa/src/lpc2148_appinit.c b/configs/zp214xpa/src/lpc2148_appinit.c index 8d526323333f2e879b82d0a73fa49f47afc24630..8652e9134c4fe198b9b55425438ebc763ae4218a 100644 --- a/configs/zp214xpa/src/lpc2148_appinit.c +++ b/configs/zp214xpa/src/lpc2148_appinit.c @@ -1,7 +1,7 @@ /**************************************************************************** * config/zp214xpa/src/lpc2148_appinit.c * - * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -40,7 +40,11 @@ #include #include -#include +#include + +#ifdef CONFIG_VIDEO_FB +# include +#endif #ifdef CONFIG_LIB_BOARDCTL @@ -75,6 +79,29 @@ int board_app_initialize(uintptr_t arg) { + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + + UNUSED(ret); return OK; } diff --git a/drivers/audio/Kconfig b/drivers/audio/Kconfig index aad77e7ea5fe4dbcc32fb103d510301c48194932..a8d9fa82c11e807e5e45df547f35f42633fa5146 100644 --- a/drivers/audio/Kconfig +++ b/drivers/audio/Kconfig @@ -155,6 +155,34 @@ config CS43L22_CLKDEBUG endif # AUDIO_CS43L22 +config AUDIO_WM8776 + bool "WM8776 audio chip" + default n + depends on AUDIO + ---help--- + Select to enable support for the WM8776 Audio codec by Wolfson + Microelectonics. + +if AUDIO_WM8776 + +config WM8776_INFLIGHT + int "WM8776 maximum in-flight audio buffers" + default 2 + +config WM8776_MSG_PRIO + int "WM8776 message priority" + default 1 + +config WM8776_WORKER_STACKSIZE + int "WM8776 worker thread stack size" + default 768 + +config WM8776_SWAP_HPOUT + bool "Swap WM8776 HP out signals" + default n + +endif # AUDIO_WM8776 + config AUDIO_WM8904 bool "WM8904 audio chip" default n diff --git a/drivers/audio/Make.defs b/drivers/audio/Make.defs index acba0d1a8efcad80af2db013689131297084adfc..5dfca4c3dec7ed40ddca3104e24f6d98a848134a 100644 --- a/drivers/audio/Make.defs +++ b/drivers/audio/Make.defs @@ -65,6 +65,10 @@ endif endif endif +ifeq ($(CONFIG_AUDIO_WM8776),y) +CSRCS += wm8776.c +endif + ifeq ($(CONFIG_AUDIO_NULL),y) CSRCS += audio_null.c endif diff --git a/drivers/audio/wm8776.c b/drivers/audio/wm8776.c new file mode 100644 index 0000000000000000000000000000000000000000..c9a9ebebcc88e804afcad37dd2f049780e594e3c --- /dev/null +++ b/drivers/audio/wm8776.c @@ -0,0 +1,1360 @@ +/**************************************************************************** + * drivers/audio/wm8776.c + * + * Copyright (C) 2017 Sony Corporation. All rights reserved. + * Author: Masayuki Ishikawa + * + * Based on drivers/audio/wm8904.c + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm8776.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static void wm8776_writereg(FAR struct wm8776_dev_s *priv, + uint8_t regaddr, uint16_t regval); + +static void wm8776_takesem(sem_t *sem); +#define wm8776_givesem(s) nxsem_post(s) + +static int wm8776_getcaps(FAR struct audio_lowerhalf_s *dev, int type, + FAR struct audio_caps_s *caps); +#ifdef CONFIG_AUDIO_MULTI_SESSION +static int wm8776_configure(FAR struct audio_lowerhalf_s *dev, + FAR void *session, FAR const struct audio_caps_s *caps); +#else +static int wm8776_configure(FAR struct audio_lowerhalf_s *dev, + FAR const struct audio_caps_s *caps); +#endif +static int wm8776_shutdown(FAR struct audio_lowerhalf_s *dev); +static void wm8776_senddone(FAR struct i2s_dev_s *i2s, + FAR struct ap_buffer_s *apb, FAR void *arg, int result); +static void wm8776_returnbuffers(FAR struct wm8776_dev_s *priv); +static int wm8776_sendbuffer(FAR struct wm8776_dev_s *priv); + +#ifdef CONFIG_AUDIO_MULTI_SESSION +static int wm8776_start(FAR struct audio_lowerhalf_s *dev, + FAR void *session); +#else +static int wm8776_start(FAR struct audio_lowerhalf_s *dev); +#endif +#ifndef CONFIG_AUDIO_EXCLUDE_STOP +#ifdef CONFIG_AUDIO_MULTI_SESSION +static int wm8776_stop(FAR struct audio_lowerhalf_s *dev, + FAR void *session); +#else +static int wm8776_stop(FAR struct audio_lowerhalf_s *dev); +#endif +#endif +#ifndef CONFIG_AUDIO_EXCLUDE_PAUSE_RESUME +#ifdef CONFIG_AUDIO_MULTI_SESSION +static int wm8776_pause(FAR struct audio_lowerhalf_s *dev, + FAR void *session); +static int wm8776_resume(FAR struct audio_lowerhalf_s *dev, + FAR void *session); +#else +static int wm8776_pause(FAR struct audio_lowerhalf_s *dev); +static int wm8776_resume(FAR struct audio_lowerhalf_s *dev); +#endif +#endif +static int wm8776_enqueuebuffer(FAR struct audio_lowerhalf_s *dev, + FAR struct ap_buffer_s *apb); +static int wm8776_cancelbuffer(FAR struct audio_lowerhalf_s *dev, + FAR struct ap_buffer_s *apb); +static int wm8776_ioctl(FAR struct audio_lowerhalf_s *dev, int cmd, + unsigned long arg); +#ifdef CONFIG_AUDIO_MULTI_SESSION +static int wm8776_reserve(FAR struct audio_lowerhalf_s *dev, + FAR void **session); +#else +static int wm8776_reserve(FAR struct audio_lowerhalf_s *dev); +#endif +#ifdef CONFIG_AUDIO_MULTI_SESSION +static int wm8776_release(FAR struct audio_lowerhalf_s *dev, + FAR void *session); +#else +static int wm8776_release(FAR struct audio_lowerhalf_s *dev); +#endif + +static void *wm8776_workerthread(pthread_addr_t pvarg); + +/* Initialization */ + +static void wm8776_audio_output(FAR struct wm8776_dev_s *priv); +#if 0 /* Not used */ +static void wm8776_audio_input(FAR struct wm8776_dev_s *priv); +#endif +static void wm8776_hw_reset(FAR struct wm8776_dev_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct audio_ops_s g_audioops = +{ + wm8776_getcaps, /* getcaps */ + wm8776_configure, /* configure */ + wm8776_shutdown, /* shutdown */ + wm8776_start, /* start */ +#ifndef CONFIG_AUDIO_EXCLUDE_STOP + wm8776_stop, /* stop */ +#endif +#ifndef CONFIG_AUDIO_EXCLUDE_PAUSE_RESUME + wm8776_pause, /* pause */ + wm8776_resume, /* resume */ +#endif + NULL, /* allocbuffer */ + NULL, /* freebuffer */ + wm8776_enqueuebuffer, /* enqueue_buffer */ + wm8776_cancelbuffer, /* cancel_buffer */ + wm8776_ioctl, /* ioctl */ + NULL, /* read */ + NULL, /* write */ + wm8776_reserve, /* reserve */ + wm8776_release /* release */ +}; + +/************************************************************************************ + * Name: wm8776_writereg + * + * Description: + * Write the specified 16-bit register to the WM8776 device. + * + ************************************************************************************/ + +static void wm8776_writereg(FAR struct wm8776_dev_s *priv, + uint8_t regaddr, + uint16_t regval) +{ + struct i2c_config_s config; + uint8_t data[2]; + int ret; + + /* Setup up the I2C configuration */ + + config.frequency = priv->lower->frequency; + config.address = priv->lower->address; + config.addrlen = 7; + + /* Set up the data to write */ + + data[0] = (regaddr << 1) + ((regval >> 8) & 0x1); + data[1] = (regval & 0xff); + + ret = i2c_write(priv->i2c, &config, data, sizeof(data)); + if (ret < 0) + { + auderr("ERROR: I2C_TRANSFER failed: %d\n", ret); + } +} + +/************************************************************************************ + * Name: wm8776_takesem + * + * Description: + * Take a semaphore count, handling the nasty EINTR return if we are interrupted + * by a signal. + * + ************************************************************************************/ + +static void wm8776_takesem(sem_t *sem) +{ + int ret; + + do + { + /* Take the semaphore (perhaps waiting) */ + + ret = nxsem_wait(sem); + + /* The only case that an error should occur here is if the wait was + * awakened by a signal. + */ + + DEBUGASSERT(ret == OK || ret == -EINTR); + } + while (ret == -EINTR); +} + +/************************************************************************************ + * Name: wm8776_setvolume + * + * Description: + * Set the right and left volume values in the WM8776 device based on the current + * volume and balance settings. + * + ************************************************************************************/ + +#ifndef CONFIG_AUDIO_EXCLUDE_VOLUME +static void wm8776_setvolume(FAR struct wm8776_dev_s *priv, uint16_t volume, + bool mute) +{ + uint16_t regval; + uint16_t tmp_vol; + + /* TODO: balance */ + + if (mute) + { + tmp_vol = 0; + } + else + { + tmp_vol = volume; + } + + /* limit the max vol */ + + if (tmp_vol > 0x69) + { + tmp_vol = 0x69; /* -10db */ + } + + regval = WM8776_UPDATE | WM8776_HPOUT_VOL(tmp_vol); + + wm8776_writereg(priv, WM8776_MASTER_ATT, regval); + + audinfo("volume=%d mute=%d tmp_vol=%d (regval=0x%x) \n", + volume, mute, tmp_vol, regval); + + /* Remember the volume level and mute settings */ + + priv->volume = volume; + priv->mute = mute; +} +#endif /* CONFIG_AUDIO_EXCLUDE_VOLUME */ + +/**************************************************************************** + * Name: wm8776_getcaps + * + * Description: + * Get the audio device capabilities + * + ****************************************************************************/ + +static int wm8776_getcaps(FAR struct audio_lowerhalf_s *dev, int type, + FAR struct audio_caps_s *caps) +{ + /* Validate the structure */ + + DEBUGASSERT(caps && caps->ac_len >= sizeof(struct audio_caps_s)); + audinfo("type=%d ac_type=%d\n", type, caps->ac_type); + + /* Fill in the caller's structure based on requested info */ + + caps->ac_format.hw = 0; + caps->ac_controls.w = 0; + + switch (caps->ac_type) + { + /* Caller is querying for the types of units we support */ + + case AUDIO_TYPE_QUERY: + + /* Provide our overall capabilities. The interfacing software + * must then call us back for specific info for each capability. + */ + + caps->ac_channels = 2; /* Stereo output */ + + switch (caps->ac_subtype) + { + case AUDIO_TYPE_QUERY: + /* We don't decode any formats! Only something above us in + * the audio stream can perform decoding on our behalf. + */ + + /* The types of audio units we implement */ + + caps->ac_controls.b[0] = AUDIO_TYPE_OUTPUT | AUDIO_TYPE_FEATURE | + AUDIO_TYPE_PROCESSING; + + break; + + default: + caps->ac_controls.b[0] = AUDIO_SUBFMT_END; + break; + } + + break; + + /* Provide capabilities of our OUTPUT unit */ + + case AUDIO_TYPE_OUTPUT: + + caps->ac_channels = 2; + + switch (caps->ac_subtype) + { + case AUDIO_TYPE_QUERY: + + /* Report the Sample rates we support */ + + caps->ac_controls.b[0] = AUDIO_SAMP_RATE_44K; + break; + + case AUDIO_FMT_MP3: + case AUDIO_FMT_WMA: + case AUDIO_FMT_PCM: + default: + break; + } + + break; + + /* All others we don't support */ + + default: + + /* Zero out the fields to indicate no support */ + + caps->ac_subtype = 0; + caps->ac_channels = 0; + + break; + } + + /* Return the length of the audio_caps_s struct for validation of + * proper Audio device type. + */ + + return caps->ac_len; +} + +/**************************************************************************** + * Name: wm8776_configure + * + * Description: + * Configure the audio device for the specified mode of operation. + * + ****************************************************************************/ + +#ifdef CONFIG_AUDIO_MULTI_SESSION +static int wm8776_configure(FAR struct audio_lowerhalf_s *dev, + FAR void *session, + FAR const struct audio_caps_s *caps) +#else +static int wm8776_configure(FAR struct audio_lowerhalf_s *dev, + FAR const struct audio_caps_s *caps) +#endif +{ +#if !defined(CONFIG_AUDIO_EXCLUDE_VOLUME) || !defined(CONFIG_AUDIO_EXCLUDE_TONE) + FAR struct wm8776_dev_s *priv = (FAR struct wm8776_dev_s *)dev; +#endif + int ret = OK; + + DEBUGASSERT(priv && caps); + audinfo("ac_type: %d\n", caps->ac_type); + + /* Process the configure operation */ + + switch (caps->ac_type) + { + case AUDIO_TYPE_FEATURE: + audinfo(" AUDIO_TYPE_FEATURE\n"); + + /* Process based on Feature Unit */ + + switch (caps->ac_format.hw) + { +#ifndef CONFIG_AUDIO_EXCLUDE_VOLUME + case AUDIO_FU_VOLUME: + { + /* Set the volume */ + + uint16_t volume = caps->ac_controls.hw[0]; + audinfo(" Volume: %d\n", volume); + + if (volume >= 0 && volume <= 1000) + { + /* Scale the volume setting to the range {0x2f .. 0x79} */ + + wm8776_setvolume(priv, (0x4a * volume / 1000) + 0x2f, priv->mute); + } + else + { + ret = -EDOM; + } + } + break; +#endif /* CONFIG_AUDIO_EXCLUDE_VOLUME */ + + default: + auderr(" ERROR: Unrecognized feature unit\n"); + ret = -ENOTTY; + break; + } + break; + + case AUDIO_TYPE_OUTPUT: + { + audinfo(" AUDIO_TYPE_OUTPUT:\n"); + audinfo(" Number of channels: %u\n", caps->ac_channels); + audinfo(" Sample rate: %u\n", caps->ac_controls.hw[0]); + audinfo(" Sample width: %u\n", caps->ac_controls.b[2]); + + /* Verify that all of the requested values are supported */ + + ret = -ERANGE; + if (caps->ac_channels != 1 && caps->ac_channels != 2) + { + auderr("ERROR: Unsupported number of channels: %d\n", + caps->ac_channels); + break; + } + + if (caps->ac_controls.b[2] != 8 && caps->ac_controls.b[2] != 16) + { + auderr("ERROR: Unsupported bits per sample: %d\n", + caps->ac_controls.b[2]); + break; + } + + /* Save the current stream configuration */ + + priv->samprate = caps->ac_controls.hw[0]; + priv->nchannels = caps->ac_channels; + priv->bpsamp = caps->ac_controls.b[2]; + + /* TODO : channels, bits per sample, bitrate */ + + ret = OK; + } + break; + + case AUDIO_TYPE_PROCESSING: + break; + } + + return ret; +} + +/**************************************************************************** + * Name: wm8776_shutdown + * + * Description: + * Shutdown the WM8776 chip and put it in the lowest power state possible. + * + ****************************************************************************/ + +static int wm8776_shutdown(FAR struct audio_lowerhalf_s *dev) +{ + FAR struct wm8776_dev_s *priv = (FAR struct wm8776_dev_s *)dev; + + DEBUGASSERT(priv); + + /* Now issue a software reset. This puts all WM8776 registers back in + * their default state. + */ + + wm8776_hw_reset(priv); + return OK; +} + +/**************************************************************************** + * Name: wm8776_senddone + * + * Description: + * This is the I2S callback function that is invoked when the transfer + * completes. + * + ****************************************************************************/ + +static void wm8776_senddone(FAR struct i2s_dev_s *i2s, + FAR struct ap_buffer_s *apb, FAR void *arg, + int result) +{ + FAR struct wm8776_dev_s *priv = (FAR struct wm8776_dev_s *)arg; + struct audio_msg_s msg; + irqstate_t flags; + int ret; + + DEBUGASSERT(i2s && priv && priv->running && apb); + audinfo("apb=%p inflight=%d result=%d\n", apb, priv->inflight, result); + + /* We do not place any restriction on the context in which this function + * is called. It may be called from an interrupt handler. Therefore, the + * doneq and in-flight values might be accessed from the interrupt level. + * Not the best design. But we will use interrupt controls to protect + * against that possibility. + */ + + flags = spin_lock_irqsave(); + + /* Add the completed buffer to the end of our doneq. We do not yet + * decrement the reference count. + */ + + dq_addlast((FAR dq_entry_t *)apb, &priv->doneq); + + /* And decrement the number of buffers in-flight */ + + DEBUGASSERT(priv->inflight > 0); + priv->inflight--; + + /* Save the result of the transfer */ + /* REVISIT: This can be overwritten */ + + priv->result = result; + spin_unlock_irqrestore(flags); + + /* Now send a message to the worker thread, informing it that there are + * buffers in the done queue that need to be cleaned up. + */ + + msg.msgId = AUDIO_MSG_COMPLETE; + ret = mq_send(priv->mq, (FAR const char *)&msg, sizeof(msg), + CONFIG_WM8776_MSG_PRIO); + if (ret < 0) + { + auderr("ERROR: mq_send failed: %d\n", errno); + } +} + +/**************************************************************************** + * Name: wm8776_returnbuffers + * + * Description: + * This function is called after the complete of one or more data + * transfers. This function will empty the done queue and release our + * reference to each buffer. + * + ****************************************************************************/ + +static void wm8776_returnbuffers(FAR struct wm8776_dev_s *priv) +{ + FAR struct ap_buffer_s *apb; + irqstate_t flags; + + /* The doneq and in-flight values might be accessed from the interrupt + * level in some implementations. Not the best design. But we will + * use interrupt controls to protect against that possibility. + */ + + flags = spin_lock_irqsave(); + while (dq_peek(&priv->doneq) != NULL) + { + /* Take the next buffer from the queue of completed transfers */ + + apb = (FAR struct ap_buffer_s *)dq_remfirst(&priv->doneq); + spin_unlock_irqrestore(flags); + + audinfo("Returning: apb=%p curbyte=%d nbytes=%d flags=%04x\n", + apb, apb->curbyte, apb->nbytes, apb->flags); + + /* Are we returning the final buffer in the stream? */ + + if ((apb->flags & AUDIO_APB_FINAL) != 0) + { + /* Both the pending and the done queues should be empty and there + * should be no buffers in-flight. + */ + + DEBUGASSERT(dq_empty(&priv->doneq) && dq_empty(&priv->pendq) && + priv->inflight == 0); + + /* Set the terminating flag. This will, eventually, cause the + * worker thread to exit (if it is not already terminating). + */ + + audinfo("Terminating\n"); + priv->terminating = true; + } + + /* Release our reference to the audio buffer */ + + apb_free(apb); + + /* Send the buffer back up to the previous level. */ + +#ifdef CONFIG_AUDIO_MULTI_SESSION + priv->dev.upper(priv->dev.priv, AUDIO_CALLBACK_DEQUEUE, apb, OK, NULL); +#else + priv->dev.upper(priv->dev.priv, AUDIO_CALLBACK_DEQUEUE, apb, OK); +#endif + flags = spin_lock_irqsave(); + } + + spin_unlock_irqrestore(flags); +} + +/**************************************************************************** + * Name: wm8776_sendbuffer + * + * Description: + * Start the transfer an audio buffer to the WM8776 via I2S. This + * will not wait for the transfer to complete but will return immediately. + * the wmd8776_senddone called will be invoked when the transfer + * completes, stimulating the worker thread to call this function again. + * + ****************************************************************************/ + +static int wm8776_sendbuffer(FAR struct wm8776_dev_s *priv) +{ + FAR struct ap_buffer_s *apb; + irqstate_t flags; + uint32_t timeout; + int shift; + int ret = OK; + + /* Loop while there are audio buffers to be sent and we have few than + * CONFIG_WM8776_INFLIGHT then "in-flight" + * + * The 'inflight' value might be modified from the interrupt level in some + * implementations. We will use interrupt controls to protect against + * that possibility. + * + * The 'pendq', on the other hand, is protected via a semaphore. Let's + * hold the semaphore while we are busy here and disable the interrupts + * only while accessing 'inflight'. + */ + + wm8776_takesem(&priv->pendsem); + while (priv->inflight < CONFIG_WM8776_INFLIGHT && + dq_peek(&priv->pendq) != NULL && !priv->paused) + { + /* Take next buffer from the queue of pending transfers */ + + apb = (FAR struct ap_buffer_s *)dq_remfirst(&priv->pendq); + audinfo("Sending apb=%p, size=%d inflight=%d\n", + apb, apb->nbytes, priv->inflight); + + /* Increment the number of buffers in-flight before sending in order + * to avoid a possible race condition. + */ + + flags = spin_lock_irqsave(); + priv->inflight++; + spin_unlock_irqrestore(flags); + + shift = (priv->bpsamp == 8) ? 14 - 3 : 14 - 4; + shift -= (priv->nchannels > 1) ? 1 : 0; + + timeout = MSEC2TICK(((uint32_t)(apb->nbytes - apb->curbyte) << shift) / + (uint32_t)priv->samprate); + + ret = I2S_SEND(priv->i2s, apb, wm8776_senddone, priv, timeout); + if (ret < 0) + { + auderr("ERROR: I2S_SEND failed: %d\n", ret); + break; + } + } + + wm8776_givesem(&priv->pendsem); + return ret; +} + +/**************************************************************************** + * Name: wm8776_start + * + * Description: + * Start the configured operation (audio streaming, volume enabled, etc.). + * + ****************************************************************************/ + +#ifdef CONFIG_AUDIO_MULTI_SESSION +static int wm8776_start(FAR struct audio_lowerhalf_s *dev, FAR void *session) +#else +static int wm8776_start(FAR struct audio_lowerhalf_s *dev) +#endif +{ + FAR struct wm8776_dev_s *priv = (FAR struct wm8776_dev_s *)dev; + struct sched_param sparam; + struct mq_attr attr; + pthread_attr_t tattr; + FAR void *value; + int ret; + + audinfo("Entry\n"); + + /* Exit reduced power modes of operation */ + /* REVISIT */ + + /* Create a message queue for the worker thread */ + + snprintf(priv->mqname, sizeof(priv->mqname), "/tmp/%X", priv); + + attr.mq_maxmsg = 16; + attr.mq_msgsize = sizeof(struct audio_msg_s); + attr.mq_curmsgs = 0; + attr.mq_flags = 0; + + priv->mq = mq_open(priv->mqname, O_RDWR | O_CREAT, 0644, &attr); + if (priv->mq == NULL) + { + /* Error creating message queue! */ + + auderr("ERROR: Couldn't allocate message queue\n"); + return -ENOMEM; + } + + /* Join any old worker thread we had created to prevent a memory leak */ + + if (priv->threadid != 0) + { + audinfo("Joining old thread\n"); + pthread_join(priv->threadid, &value); + } + + /* Start our thread for sending data to the device */ + + pthread_attr_init(&tattr); + sparam.sched_priority = sched_get_priority_max(SCHED_FIFO) - 3; + (void)pthread_attr_setschedparam(&tattr, &sparam); + (void)pthread_attr_setstacksize(&tattr, CONFIG_WM8776_WORKER_STACKSIZE); + + audinfo("Starting worker thread\n"); + ret = pthread_create(&priv->threadid, &tattr, wm8776_workerthread, + (pthread_addr_t)priv); + if (ret != OK) + { + auderr("ERROR: pthread_create failed: %d\n", ret); + } + else + { + pthread_setname_np(priv->threadid, "wm8776"); + audinfo("Created worker thread\n"); + } + + return ret; +} + +/**************************************************************************** + * Name: wm8776_stop + * + * Description: Stop the configured operation (audio streaming, volume + * disabled, etc.). + * + ****************************************************************************/ + +#ifndef CONFIG_AUDIO_EXCLUDE_STOP +#ifdef CONFIG_AUDIO_MULTI_SESSION +static int wm8776_stop(FAR struct audio_lowerhalf_s *dev, FAR void *session) +#else +static int wm8776_stop(FAR struct audio_lowerhalf_s *dev) +#endif +{ + FAR struct wm8776_dev_s *priv = (FAR struct wm8776_dev_s *)dev; + struct audio_msg_s term_msg; + FAR void *value; + + /* Send a message to stop all audio streaming */ + + term_msg.msgId = AUDIO_MSG_STOP; + term_msg.u.data = 0; + mq_send(priv->mq, (FAR const char *)&term_msg, sizeof(term_msg), + CONFIG_WM8776_MSG_PRIO); + + /* Join the worker thread */ + + pthread_join(priv->threadid, &value); + priv->threadid = 0; + + /* Enter into a reduced power usage mode */ + /* REVISIT: */ + + return OK; +} +#endif + +/**************************************************************************** + * Name: wm8776_pause + * + * Description: Pauses the playback. + * + ****************************************************************************/ + +#ifndef CONFIG_AUDIO_EXCLUDE_PAUSE_RESUME +#ifdef CONFIG_AUDIO_MULTI_SESSION +static int wm8776_pause(FAR struct audio_lowerhalf_s *dev, FAR void *session) +#else +static int wm8776_pause(FAR struct audio_lowerhalf_s *dev) +#endif +{ + FAR struct wm8776_dev_s *priv = (FAR struct wm8776_dev_s *)dev; + + if (priv->running && !priv->paused) + { + priv->paused = true; + wm8776_setvolume(priv, priv->volume, true); + } + + return OK; +} +#endif /* CONFIG_AUDIO_EXCLUDE_PAUSE_RESUME */ + +/**************************************************************************** + * Name: wm8776_resume + * + * Description: Resumes the playback. + * + ****************************************************************************/ + +#ifndef CONFIG_AUDIO_EXCLUDE_PAUSE_RESUME +#ifdef CONFIG_AUDIO_MULTI_SESSION +static int wm8776_resume(FAR struct audio_lowerhalf_s *dev, FAR void *session) +#else +static int wm8776_resume(FAR struct audio_lowerhalf_s *dev) +#endif +{ + FAR struct wm8776_dev_s *priv = (FAR struct wm8776_dev_s *)dev; + + if (priv->running && priv->paused) + { + priv->paused = false; + wm8776_setvolume(priv, priv->volume, false); + wm8776_sendbuffer(priv); + } + + return OK; +} +#endif /* CONFIG_AUDIO_EXCLUDE_PAUSE_RESUME */ + +/**************************************************************************** + * Name: wm8776_enqueuebuffer + * + * Description: Enqueue an Audio Pipeline Buffer for playback/ processing. + * + ****************************************************************************/ + +static int wm8776_enqueuebuffer(FAR struct audio_lowerhalf_s *dev, + FAR struct ap_buffer_s *apb) +{ + FAR struct wm8776_dev_s *priv = (FAR struct wm8776_dev_s *)dev; + struct audio_msg_s term_msg; + int ret; + + audinfo("Enqueueing: apb=%p curbyte=%d nbytes=%d flags=%04x\n", + apb, apb->curbyte, apb->nbytes, apb->flags); + + /* Take a reference on the new audio buffer */ + + apb_reference(apb); + + /* Add the new buffer to the tail of pending audio buffers */ + + wm8776_takesem(&priv->pendsem); + apb->flags |= AUDIO_APB_OUTPUT_ENQUEUED; + dq_addlast(&apb->dq_entry, &priv->pendq); + wm8776_givesem(&priv->pendsem); + + /* Send a message to the worker thread indicating that a new buffer has been + * enqueued. If mq is NULL, then the playing has not yet started. In that + * case we are just "priming the pump" and we don't need to send any message. + */ + + ret = OK; + if (priv->mq != NULL) + { + term_msg.msgId = AUDIO_MSG_ENQUEUE; + term_msg.u.data = 0; + + ret = mq_send(priv->mq, (FAR const char *)&term_msg, sizeof(term_msg), + CONFIG_WM8776_MSG_PRIO); + if (ret < 0) + { + int errcode = errno; + DEBUGASSERT(errcode > 0); + + auderr("ERROR: mq_send failed: %d\n", errcode); + UNUSED(errcode); + } + } + + return ret; +} + +/**************************************************************************** + * Name: wm8776_cancelbuffer + * + * Description: Called when an enqueued buffer is being cancelled. + * + ****************************************************************************/ + +static int wm8776_cancelbuffer(FAR struct audio_lowerhalf_s *dev, + FAR struct ap_buffer_s *apb) +{ + audinfo("apb=%p\n", apb); + return OK; +} + +/**************************************************************************** + * Name: wm8776_ioctl + * + * Description: Perform a device ioctl + * + ****************************************************************************/ + +static int wm8776_ioctl(FAR struct audio_lowerhalf_s *dev, int cmd, + unsigned long arg) +{ +#ifdef CONFIG_AUDIO_DRIVER_SPECIFIC_BUFFERS + FAR struct ap_buffer_info_s *bufinfo; +#endif + + /* Deal with ioctls passed from the upper-half driver */ + + switch (cmd) + { + /* Check for AUDIOIOC_HWRESET ioctl. This ioctl is passed straight + * through from the upper-half audio driver. + */ + + case AUDIOIOC_HWRESET: + { + /* REVISIT: Should we completely re-initialize the chip? We + * can't just issue a software reset; that would puts all WM8776 + * registers back in their default state. + */ + + audinfo("AUDIOIOC_HWRESET:\n"); + } + break; + + /* Report our preferred buffer size and quantity */ + +#ifdef CONFIG_AUDIO_DRIVER_SPECIFIC_BUFFERS + case AUDIOIOC_GETBUFFERINFO: + { + audinfo("AUDIOIOC_GETBUFFERINFO:\n"); + bufinfo = (FAR struct ap_buffer_info_s *) arg; + bufinfo->buffer_size = CONFIG_WM8776_BUFFER_SIZE; + bufinfo->nbuffers = CONFIG_WM8776_NUM_BUFFERS; + } + break; +#endif + + default: + audinfo("Ignored\n"); + break; + } + + return OK; +} + +/**************************************************************************** + * Name: wm8776_reserve + * + * Description: Reserves a session (the only one we have). + * + ****************************************************************************/ + +#ifdef CONFIG_AUDIO_MULTI_SESSION +static int wm8776_reserve(FAR struct audio_lowerhalf_s *dev, + FAR void **session) +#else +static int wm8776_reserve(FAR struct audio_lowerhalf_s *dev) +#endif +{ + FAR struct wm8776_dev_s *priv = (FAR struct wm8776_dev_s *) dev; + int ret = OK; + + /* Borrow the APBQ semaphore for thread sync */ + + wm8776_takesem(&priv->pendsem); + if (priv->reserved) + { + ret = -EBUSY; + } + else + { + /* Initialize the session context */ + +#ifdef CONFIG_AUDIO_MULTI_SESSION + *session = NULL; +#endif + priv->inflight = 0; + priv->running = false; + priv->paused = false; +#ifndef CONFIG_AUDIO_EXCLUDE_STOP + priv->terminating = false; +#endif + priv->reserved = true; + } + + wm8776_givesem(&priv->pendsem); + + return ret; +} + +/**************************************************************************** + * Name: wm8776_release + * + * Description: Releases the session (the only one we have). + * + ****************************************************************************/ + +#ifdef CONFIG_AUDIO_MULTI_SESSION +static int wm8776_release(FAR struct audio_lowerhalf_s *dev, + FAR void *session) +#else +static int wm8776_release(FAR struct audio_lowerhalf_s *dev) +#endif +{ + FAR struct wm8776_dev_s *priv = (FAR struct wm8776_dev_s *)dev; + void *value; + + /* Join any old worker thread we had created to prevent a memory leak */ + + if (priv->threadid != 0) + { + pthread_join(priv->threadid, &value); + priv->threadid = 0; + } + + /* Borrow the APBQ semaphore for thread sync */ + + wm8776_takesem(&priv->pendsem); + + /* Really we should free any queued buffers here */ + + priv->reserved = false; + wm8776_givesem(&priv->pendsem); + + return OK; +} + +/**************************************************************************** + * Name: wm8776_audio_output + * + * Description: + * Initialize and configure the WM8776 device as an audio output device. + * + * Input Parameters: + * priv - A reference to the driver state structure + * + * Returned Value: + * None. No failures are detected. + * + ****************************************************************************/ + +static void wm8776_audio_output(FAR struct wm8776_dev_s *priv) +{ + wm8776_writereg(priv, WM8776_MASTER_ATT, WM8776_UPDATE | 0x58); /* -33db */ + wm8776_writereg(priv, WM8776_DAC_IF, 0x32); /* 32bit, I2S, standard pol */ + +#ifdef CONFIG_WM8776_SWAP_HPOUT + wm8776_writereg(priv, WM8776_DAC_CC, 0x62); /* Swap HPOUT L/R */ +#endif + + wm8776_writereg(priv, WM8776_MASTER_MODE, 0x00); /* slave mode, 128fs */ + wm8776_writereg(priv, WM8776_PWR_DOWN, 0x12); /* AINPD, ADCPD */ +} + +/**************************************************************************** + * Name: wm8776_hw_reset + * + * Description: + * Reset and re-initialize the WM8776 + * + * Input Parameters: + * priv - A reference to the driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wm8776_hw_reset(FAR struct wm8776_dev_s *priv) +{ + /* Put audio output back to its initial configuration */ + + priv->samprate = WM8776_DEFAULT_SAMPRATE; + priv->nchannels = WM8776_DEFAULT_NCHANNELS; + priv->bpsamp = WM8776_DEFAULT_BPSAMP; +#if !defined(CONFIG_AUDIO_EXCLUDE_VOLUME) && !defined(CONFIG_AUDIO_EXCLUDE_BALANCE) + priv->balance = b16HALF; /* Center balance */ +#endif + + /* Software reset. This puts all WM8776 registers back in their + * default state. + */ + + wm8776_writereg(priv, WM8776_SOFT_RESET, 0x00); + + /* Configure the WM8776 hardware as an audio input device */ + + wm8776_audio_output(priv); + +} + +/**************************************************************************** + * Name: wm8776_workerthread + * + * This is the thread that feeds data to the chip and keeps the audio + * stream going. + * + ****************************************************************************/ + +static void *wm8776_workerthread(pthread_addr_t pvarg) +{ + FAR struct wm8776_dev_s *priv = (struct wm8776_dev_s *) pvarg; + struct audio_msg_s msg; + FAR struct ap_buffer_s *apb; + int msglen; + int prio; + struct mq_attr attr; + + audinfo("Entry\n"); + +#ifndef CONFIG_AUDIO_EXCLUDE_STOP + priv->terminating = false; +#endif + + priv->running = true; + wm8776_setvolume(priv, priv->volume, false); + + /* Loop as long as we are supposed to be running and as long as we have + * buffers in-flight. + */ + + while (priv->running || priv->inflight > 0) + { + /* Check if we have been asked to terminate. We have to check if we + * still have buffers in-flight. If we do, then we can't stop until + * birds come back to roost. + */ + + if (priv->terminating && priv->inflight <= 0) + { + /* We are IDLE. Break out of the loop and exit. */ + + break; + } + else + { + /* Check if we can send more audio buffers to the WM8776 */ + + wm8776_sendbuffer(priv); + } + +repeat: + + /* Wait for messages from our message queue */ + + msglen = mq_receive(priv->mq, (FAR char *)&msg, sizeof(msg), &prio); + + /* Handle the case when we return with no message */ + + if (msglen < sizeof(struct audio_msg_s)) + { + auderr("ERROR: Message too small: %d\n", msglen); + continue; + } + + /* Process the message */ + + switch (msg.msgId) + { + /* The ISR has requested more data. We will catch this case at + * the top of the loop. + */ + + case AUDIO_MSG_DATA_REQUEST: + audinfo("AUDIO_MSG_DATA_REQUEST\n"); + break; + + /* Stop the playback */ + +#ifndef CONFIG_AUDIO_EXCLUDE_STOP + case AUDIO_MSG_STOP: + /* Indicate that we are terminating */ + + audinfo("AUDIO_MSG_STOP: Terminating\n"); + priv->terminating = true; + break; +#endif + + /* We have a new buffer to send. We will catch this case at + * the top of the loop. + */ + + case AUDIO_MSG_ENQUEUE: + audinfo("AUDIO_MSG_ENQUEUE\n"); + break; + + /* We will wake up from the I2S callback with this message */ + + case AUDIO_MSG_COMPLETE: + audinfo("AUDIO_MSG_COMPLETE\n"); + wm8776_returnbuffers(priv); + break; + + default: + auderr("ERROR: Ignoring message ID %d\n", msg.msgId); + break; + } + + (void)mq_getattr(priv->mq, &attr); + + /* If there is a message in the queue, process it */ + + if (0 < attr.mq_curmsgs) + { + goto repeat; + } + + } + + /* Reset the WM8776 hardware */ + + wm8776_hw_reset(priv); + + /* Return any pending buffers in our pending queue */ + + wm8776_takesem(&priv->pendsem); + while ((apb = (FAR struct ap_buffer_s *)dq_remfirst(&priv->pendq)) != NULL) + { + /* Release our reference to the buffer */ + + apb_free(apb); + + /* Send the buffer back up to the previous level. */ + +#ifdef CONFIG_AUDIO_MULTI_SESSION + priv->dev.upper(priv->dev.priv, AUDIO_CALLBACK_DEQUEUE, apb, OK, NULL); +#else + priv->dev.upper(priv->dev.priv, AUDIO_CALLBACK_DEQUEUE, apb, OK); +#endif + } + + wm8776_givesem(&priv->pendsem); + + /* Return any pending buffers in our done queue */ + + wm8776_returnbuffers(priv); + + /* Close the message queue */ + + mq_close(priv->mq); + mq_unlink(priv->mqname); + priv->mq = NULL; + + /* Send an AUDIO_MSG_COMPLETE message to the client */ + +#ifdef CONFIG_AUDIO_MULTI_SESSION + priv->dev.upper(priv->dev.priv, AUDIO_CALLBACK_COMPLETE, NULL, OK, NULL); +#else + priv->dev.upper(priv->dev.priv, AUDIO_CALLBACK_COMPLETE, NULL, OK); +#endif + + audinfo("Exit\n"); + return NULL; +} + + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: wm8776_initialize + * + * Description: + * Initialize the WM8776 device. + * + * Input Parameters: + * i2c - An I2C driver instance + * i2s - An I2S driver instance + * lower - Persistent board configuration data + * + * Returned Value: + * A new lower half audio interface for the WM8776 device is returned on + * success; NULL is returned on failure. + * + ****************************************************************************/ + +FAR struct audio_lowerhalf_s * + wm8776_initialize(FAR struct i2c_master_s *i2c, + FAR struct i2s_dev_s *i2s, + FAR const struct wm8776_lower_s *lower) +{ + FAR struct wm8776_dev_s *priv; + + /* Sanity check */ + + DEBUGASSERT(i2c && i2s && lower); + + /* Allocate a WM8776 device structure */ + + priv = (FAR struct wm8776_dev_s *)kmm_zalloc(sizeof(struct wm8776_dev_s)); + + if (priv) + { + priv->dev.ops = &g_audioops; + priv->lower = lower; + priv->i2c = i2c; + priv->i2s = i2s; + + nxsem_init(&priv->pendsem, 0, 1); + dq_init(&priv->pendq); + dq_init(&priv->doneq); + + /* Reset and reconfigure the WM8776 hardwaqre */ + + wm8776_hw_reset(priv); + return &priv->dev; + } + + return NULL; +} diff --git a/drivers/audio/wm8776.h b/drivers/audio/wm8776.h new file mode 100644 index 0000000000000000000000000000000000000000..ec3ecaee644dea3ea5fed585fe6a2cb8c6f418a3 --- /dev/null +++ b/drivers/audio/wm8776.h @@ -0,0 +1,126 @@ +/**************************************************************************** + * drivers/audio/wm8776.h + * + * Copyright (C) 2017 Sony Corporation. All rights reserved. + * Author: Masayuki Ishikawa + * + * Based on drivers/audio/wm8904.h + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __DRIVERS_AUDIO_WM8776_H +#define __DRIVERS_AUDIO_WM8776_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include +#include + +#ifdef CONFIG_AUDIO + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define WM8776_MASTER_ATT 0x02 +#define WM8776_DAC_CC 0x07 +#define WM8776_DAC_IF 0x0a +#define WM8776_MASTER_MODE 0x0c +#define WM8776_PWR_DOWN 0x0d +#define WM8776_SOFT_RESET 0x17 + +#define WM8776_DEFAULT_SAMPRATE 44100 /* Initial sample rate */ +#define WM8776_DEFAULT_NCHANNELS 2 /* Initial number of channels */ +#define WM8776_DEFAULT_BPSAMP 16 /* Initial bits per sample */ + +#define WM8776_HPLZCEN (0x1 << 7) +#define WM8776_UPDATE (0x1 << 8) + +#define WM8776_HPOUT_VOL_SHIFT (0) /* Bits 0-6: Headphone output volume */ +#define WM8776_HPOUT_VOL_MASK (0x7f << WM8776_HPOUT_VOL_SHIFT) +# define WM8776_HPOUT_VOL(n) ((uint16_t)(n) << WM8776_HPOUT_VOL_SHIFT) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct wm8776_dev_s +{ + /* We are an audio lower half driver (We are also the upper "half" of + * the WM8776 driver with respect to the board lower half driver). + * + * Terminology: Our "lower" half audio instances will be called dev for the + * publicly visible version and "priv" for the version that only this driver + * knows. From the point of view of this driver, it is the board lower + * "half" that is referred to as "lower". + */ + + struct audio_lowerhalf_s dev; /* WM8776 audio lower half (this device) */ + + const FAR struct wm8776_lower_s *lower; /* Pointer to the board lower functions */ + FAR struct i2c_master_s *i2c; /* I2C driver to use */ + FAR struct i2s_dev_s *i2s; /* I2S driver to use */ + struct dq_queue_s pendq; /* Queue of pending buffers to be sent */ + struct dq_queue_s doneq; /* Queue of sent buffers to be returned */ + mqd_t mq; /* Message queue for receiving messages */ + char mqname[16]; /* Our message queue name */ + pthread_t threadid; /* ID of our thread */ + uint32_t bitrate; /* Actual programmed bit rate */ + sem_t pendsem; /* Protect pendq */ + uint16_t samprate; /* Configured samprate (samples/sec) */ +#ifndef CONFIG_AUDIO_EXCLUDE_VOLUME +#ifndef CONFIG_AUDIO_EXCLUDE_BALANCE + uint16_t balance; /* Current balance level (b16) */ +#endif /* CONFIG_AUDIO_EXCLUDE_BALANCE */ + uint8_t volume; /* Current volume level {0..63} */ +#endif /* CONFIG_AUDIO_EXCLUDE_VOLUME */ + uint8_t nchannels; /* Number of channels (1 or 2) */ + uint8_t bpsamp; /* Bits per sample (8 or 16) */ + volatile uint8_t inflight; /* Number of audio buffers in-flight */ + bool running; /* True: Worker thread is running */ + bool paused; /* True: Playing is paused */ + bool mute; /* True: Output is muted */ +#ifndef CONFIG_AUDIO_EXCLUDE_STOP + bool terminating; /* True: Stop requested */ +#endif + bool reserved; /* True: Device is reserved */ + volatile int result; /* The result of the last transfer */ +}; + +#endif /* CONFIG_AUDIO */ +#endif /* __DRIVERS_AUDIO_WM8776_H */ diff --git a/drivers/dev_urandom.c b/drivers/dev_urandom.c index d5090ffc5f2aab3ae9d5d85b5494f68f9ac0a1dd..6deb9949499e47fbcad22b17ff73b346ce0df086 100644 --- a/drivers/dev_urandom.c +++ b/drivers/dev_urandom.c @@ -53,6 +53,7 @@ #include #include +#include #include #include #include diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index 69d77e62d2fd39fac08d008b498f92dc2a42b544..a190c49428ce321dd0b1e83ac56ce02f104fe225 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -37,7 +37,7 @@ config INPUT_TSC2007 if INPUT_TSC2007 config TSC2007_8BIT - bool "8-bit Conversions" + bool "TSC2007 8-bit Conversions" default n ---help--- Use faster, but less accurate, 8-bit conversions. Default: 12-bit conversions. @@ -49,13 +49,87 @@ config TSC2007_MULTIPLE Can be defined to support multiple TSC2007 devices on board. config TSC2007_NPOLLWAITERS - int "Number poll waiters" + int "Number TSC2007 poll waiters" default 4 depends on !DISABLE_POLL ---help--- Maximum number of threads that can be waiting on poll() -endif +endif # INPUT_TSC2007 + +config INPUT_FT5X06 + bool "FocalTech FT5x06 multi-touch, capacitive touch panel controller" + default n + select I2C + ---help--- + Enable support for the FocalTech FT5x06 multi-touch, capacitive + touch panel controller + +config INPUT_FT5336 + bool "FocalTech FT5336 multi-touch, capacitive touch panel controller" + default n + select I2C + select INPUT_FT5X06 + depends on EXPERIMENTAL + ---help--- + Enable support for the FocalTech FT5x06 multi-touch, capacitive + touch panel controller + +if INPUT_FT5X06 + +config FT5X06_POLLMODE + bool "Polled mode" + default n + ---help--- + Run the FT5x06 in a non-interrupt driven polled mode. Events will + not be driven by interrupts but rather based on a timed poll. + + This is a non-optimal design both because (1) it will lead to delays + in detecting touch related events and (2) it will consume a + significant amount of CPU time to perform the polling. + +config FT5X06_SWAPXY + bool "Swap X/Y" + default n + ---help--- + Reverse the meaning of X and Y to handle different LCD orientations. + +config FT5X06_SINGLEPOINT + bool "Single point" + default n + ---help--- + Do no report multi-touch events + +if FT5X06_SINGLEPOINT + +config FT5X06_THRESHX + int "X threshold" + default 12 + ---help--- + New touch positions will only be reported when the X or Y data changes by these + thresholds. This trades reduced data rates for some loss in dragging accuracy. For + 12-bit values the raw ranges are 0-4095. So for example, if your display is + 320x240, then THRESHX=13 and THRESHY=17 would correspond to one pixel. Default: 12 + +config FT5X06_THRESHY + int "Y threshold" + default 12 + ---help--- + New touch positions will only be reported when the X or Y data changes by these + thresholds. This trades reduced data rates for some loss in dragging accuracy. For + 12-bit values the raw ranges are 0-4095. So for example, if your display is + 320x240, then THRESHX=13 and THRESHY=17 would correspond to one pixel. Default: 12 + +endif # FT5X06_SINGLEPOINT + +config FT5X06_NPOLLWAITERS + int "Number FT5336/FT5x06 poll waiters" + default 4 + depends on !DISABLE_POLL + ---help--- + Maximum number of threads that can be waiting on poll() + +endif # INPUT_FT5X06 config INPUT_ADS7843E bool "TI ADS7843/TSC2046 touchscreen controller" @@ -426,3 +500,22 @@ config AJOYSTICK_NPOLLWAITERS depends on !DISABLE_POLL endif # AJOYSTICK + +config INPUT_NUNCHUCK + bool "Nintendo Wii Nunchuck Joystick (White Model)" + default n + select I2C + ---help--- + Enable a Nintendo Wii Nunchuck joystick upper half driver. The + nunchuck joystick provides position data as an integer value.The + analog positional data may also be accompanied by discrete + button data. + +if INPUT_NUNCHUCK + +config NUNCHUCK_NPOLLWAITERS + int "Max Number of Poll Waiters" + default 2 + depends on !DISABLE_POLL + +endif # INPUT_NUNCHUCK diff --git a/drivers/input/Make.defs b/drivers/input/Make.defs index af98782596b0d1a9e6128a4c390d0b3417874db8..18f456030fd0f6f4992758dc8fe57b7947031912 100644 --- a/drivers/input/Make.defs +++ b/drivers/input/Make.defs @@ -43,6 +43,10 @@ ifeq ($(CONFIG_INPUT_TSC2007),y) CSRCS += tsc2007.c endif +ifeq ($(CONFIG_INPUT_FT5X06),y) + CSRCS += ft5x06.c +endif + ifeq ($(CONFIG_INPUT_ADS7843E),y) CSRCS += ads7843e.c endif @@ -91,6 +95,10 @@ ifeq ($(CONFIG_AJOYSTICK),y) CSRCS += ajoystick.c endif +ifeq ($(CONFIG_INPUT_NUNCHUCK),y) + CSRCS += nunchuck.c +endif + # Include input device driver build support DEPPATH += --dep-path input diff --git a/drivers/input/djoystick.c b/drivers/input/djoystick.c index c0de969bf3c37ba0bcf00fc2218726dff72970c0..6ada3f76e1ebdda0f1bcbadf942de1dfc8948a30 100644 --- a/drivers/input/djoystick.c +++ b/drivers/input/djoystick.c @@ -404,9 +404,9 @@ static int djoy_open(FAR struct file *filep) { FAR struct inode *inode; FAR struct djoy_upperhalf_s *priv; - FAR const struct djoy_lowerhalf_s *lower; FAR struct djoy_open_s *opriv; #ifndef CONFIG_DISABLE_POLL + FAR const struct djoy_lowerhalf_s *lower; djoy_buttonset_t supported; #endif int ret; diff --git a/drivers/input/ft5x06.c b/drivers/input/ft5x06.c new file mode 100644 index 0000000000000000000000000000000000000000..25bd5f1551403291a1fb61898ce5991eb02d2a20 --- /dev/null +++ b/drivers/input/ft5x06.c @@ -0,0 +1,1295 @@ +/**************************************************************************** + * drivers/input/ft5x06.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: + * "FT5x06", FocalTech Systems Co., Ltd, D-FT5x06-1212-V4.0, Revised + * Dec. 18, 2012 + * + * Some of this driver was developed with input from NXP sample code for + * the LPCXpresso-LPC54628 baord. That sample code as a compatible BSD + * license: + * + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The FT5x06 Series ICs are single-chip capacitive touch panel controller + * ICs with a built-in 8 bit Micro-controller unit (MCU). They adopt the + * mutual capacitance approach, which supports true multi-touch capability. + * In conjunction with a mutual capacitive touch panel, the FT5x06 have + * user-friendly input functions, which can be applied on many portable + * devices, such as cellular phones, MIDs, netbook and notebook personal + * computers. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "ft5x06.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Driver support ***********************************************************/ +/* This format is used to construct the /dev/input[n] device driver path. It + * defined here so that it will be used consistently in all places. + */ + +#define DEV_FORMAT "/dev/input%d" +#define DEV_NAMELEN 16 + +/* In polled mode, the polling rate will decrease when there is no touch + * activity. These definitions represent the maximum and the minimum + * polling rates. + */ + +#define POLL_MINDELAY MSEC2TICK(50) +#define POLL_MAXDELAY MSEC2TICK(200) +#define POLL_INCREMENT MSEC2TICK(10) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure describes the state of one FT5x06 driver instance */ + +struct ft5x06_dev_s +{ + uint8_t crefs; /* Number of times the device + * has been opened */ + uint8_t nwaiters; /* Number of threads waiting for + * FT5x06 data */ + volatile bool valid; /* True: New, valid touch data in + * touchbuf[] */ +#ifdef CONFIG_FT5X06_SINGLEPOINT + uint8_t lastid; /* Last reported touch id */ + uint8_t lastevent; /* Last reported event */ + int16_t lastx; /* Last reported X position */ + int16_t lasty; /* Last reported Y position */ +#endif + sem_t devsem; /* Manages exclusive access to this + * structure */ + sem_t waitsem; /* Used to wait for the + * availability of data */ + uint32_t frequency; /* Current I2C frequency */ +#ifdef CONFIG_FT5X06_POLLMODE + uint32_t delay; /* Current poll delay */ +#endif + + FAR const struct ft5x06_config_s *config; /* Board configuration data */ + FAR struct i2c_master_s *i2c; /* Saved I2C driver instance */ + struct work_s work; /* Supports the interrupt handling + * "bottom half" */ +#ifdef CONFIG_FT5X06_POLLMODE + WDOG_ID polltimer; /* Poll timer */ +#endif + uint8_t touchbuf[FT5x06_TOUCH_DATA_LEN]; /* Raw touch data */ + +#ifndef CONFIG_DISABLE_POLL + /* The following is a list if poll structures of threads waiting for + * driver events. The 'struct pollfd' reference for each open is also + * retained in the f_priv field of the 'struct file'. + */ + + struct pollfd *fds[CONFIG_FT5X06_NPOLLWAITERS]; +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void ft5x06_notify(FAR struct ft5x06_dev_s *priv); +static void ft5x06_data_worker(FAR void *arg); +#ifdef CONFIG_FT5X06_POLLMODE +static void ft5x06_poll_timeout(int argc, wdparm_t arg1, ...); +#else +static int ft5x06_data_interrupt(int irq, FAR void *context, FAR void *arg); +#endif +static ssize_t ft5x06_sample(FAR struct ft5x06_dev_s *priv, FAR char *buffer, + size_t len); +static ssize_t ft5x06_waitsample(FAR struct ft5x06_dev_s *priv, + FAR char *buffer, size_t len); +static int ft5x06_bringup(FAR struct ft5x06_dev_s *priv); +static void ft5x06_shutdown(FAR struct ft5x06_dev_s *priv); + +/* Character driver methods */ + +static int ft5x06_open(FAR struct file *filep); +static int ft5x06_close(FAR struct file *filep); +static ssize_t ft5x06_read(FAR struct file *filep, FAR char *buffer, + size_t len); +static int ft5x06_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); +#ifndef CONFIG_DISABLE_POLL +static int ft5x06_poll(FAR struct file *filep, struct pollfd *fds, + bool setup); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This the vtable that supports the character driver interface */ + +static const struct file_operations ft5x06_fops = +{ + ft5x06_open, /* open */ + ft5x06_close, /* close */ + ft5x06_read, /* read */ + NULL, /* write */ + NULL, /* seek */ + ft5x06_ioctl /* ioctl */ +#ifndef CONFIG_DISABLE_POLL + , ft5x06_poll /* poll */ +#endif +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + , NULL /* unlink */ +#endif +}; + +/* Maps FT5x06 touch events into bit encoded representation used by NuttX */ + +static const uint8_t g_event_map[4] = +{ + (TOUCH_DOWN | TOUCH_ID_VALID | TOUCH_POS_VALID), /* FT5x06_DOWN */ + (TOUCH_UP | TOUCH_ID_VALID), /* FT5x06_UP */ + (TOUCH_MOVE | TOUCH_ID_VALID | TOUCH_POS_VALID), /* FT5x06_CONTACT */ + TOUCH_ID_VALID /* FT5x06_INVALID */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ft5x06_notify + ****************************************************************************/ + +static void ft5x06_notify(FAR struct ft5x06_dev_s *priv) +{ +#ifndef CONFIG_DISABLE_POLL + int i; +#endif + + /* If there are threads waiting for read data, then signal one of them + * that the read data is available. + */ + + if (priv->nwaiters > 0) + { + /* After posting this semaphore, we need to exit because the FT5x06 + * is no longer available. + */ + + nxsem_post(&priv->waitsem); + } + +#ifndef CONFIG_DISABLE_POLL + /* If there are threads waiting on poll() for FT5x06 data to become available, + * then wake them up now. NOTE: we wake up all waiting threads because we + * do not know that they are going to do. If they all try to read the data, + * then some make end up blocking after all. + */ + + for (i = 0; i < CONFIG_FT5X06_NPOLLWAITERS; i++) + { + struct pollfd *fds = priv->fds[i]; + if (fds) + { + fds->revents |= POLLIN; + iinfo("Report events: %02x\n", fds->revents); + nxsem_post(fds->sem); + } + } +#endif +} + +/**************************************************************************** + * Name: ft5x06_data_worker + ****************************************************************************/ + +static void ft5x06_data_worker(FAR void *arg) +{ + FAR struct ft5x06_dev_s *priv = (FAR struct ft5x06_dev_s *)arg; + FAR const struct ft5x06_config_s *config; + FAR struct ft5x06_touch_data_s *sample; + struct i2c_msg_s msg[2]; + uint8_t regaddr; + int ret; + + /* Get a pointer the callbacks for convenience */ + + DEBUGASSERT(priv != NULL && priv->config != NULL); + config = priv->config; + + /* We need to have exclusive access to the touchbuf so that we do not + * corrupt any read operation that is in place. + */ + + do + { + ret = nxsem_wait(&priv->devsem); + DEBUGASSERT(ret >= 0 || ret == -EINTR); + } + while (ret < 0); + + /* Read touch data */ + /* Set up the address write operation */ + + regaddr = FT5x06_TOUCH_DATA_STARTREG; + + msg[0].frequency = priv->frequency; /* I2C frequency */ + msg[0].addr = config->address; /* 7-bit address */ + msg[0].flags = 0; /* Write transaction with START */ + msg[0].buffer = ®addr; /* Send one byte of data (no STOP) */ + msg[0].length = 1; + + /* Set up the data read operation. + * + * REVISIT: If CONFIG_FT5X06_SINGLEPOINT is selected, could we not just + * set the length for one sample? Or is there some reason why we have to + * read all of the points? + */ + + msg[1].frequency = priv->frequency; /* I2C frequency */ + msg[1].addr = config->address; /* 7-bit address */ + msg[1].flags = I2C_M_READ; /* Read transaction with Re-START */ + msg[1].buffer = priv->touchbuf; /* Read all touch data */ + msg[1].length = FT5x06_TOUCH_DATA_LEN; + + ret = I2C_TRANSFER(priv->i2c, msg, 2); + if (ret >= 0) + { + /* In polled mode, we may read invalid touch data. If there is + * no touch data, the FT5x06 returns all 0xff the very first time. + * After that, it returns the same old stale data when there is + * no touch data. + */ + + sample = (FAR struct ft5x06_touch_data_s *)priv->touchbuf; + + /* Notify waiters (only if we ready some valid data). + * + * REVISIT: For improved performance consider moving the duplicate + * report and thresholding logic from ft5x06_sample() to here. That + * would save a context switch. + */ + + if (sample->tdstatus <= FT5x06_MAX_TOUCHES) + { + /* Notify any waiters that new FT5x06 data is available */ + + priv->valid = true; + ft5x06_notify(priv); + } + +#ifdef CONFIG_FT5X06_POLLMODE + /* Update the poll rate */ + + if (sample->tdstatus > 0 && sample->tdstatus <= FT5x06_MAX_TOUCHES) + { + /* Keep it at the minimum if touches are detected. */ + + priv->delay = POLL_MINDELAY; + } + else if (priv->delay < POLL_MAXDELAY) + { + /* Otherwise, let the poll rate rise gradually up to the maximum + * if there is no touch. + */ + + priv->delay += POLL_INCREMENT; + } +#endif + } + +#ifdef CONFIG_FT5X06_POLLMODE + /* Exit, re-starting the poll (unless there is no longer any task waiting + * for touch data). + */ + + if (priv->nwaiters > 0) + { + (void)wd_start(priv->polltimer, priv->delay, ft5x06_poll_timeout, 1, + priv); + } + +#else + /* Exit, re-enabling FT5x06 interrupts */ + + config->enable(config, true); +#endif + + nxsem_post(&priv->devsem); +} + +/**************************************************************************** + * Name: ft5x06_poll_timeout + ****************************************************************************/ + +#ifdef CONFIG_FT5X06_POLLMODE +static void ft5x06_poll_timeout(int argc, wdparm_t arg1, ...) +{ + FAR struct ft5x06_dev_s *priv = (FAR struct ft5x06_dev_s *)arg1; + int ret; + + /* Transfer processing to the worker thread. Since FT5x06 poll timer is + * disabled while the work is pending, no special action should be + * required to protected the work queue. + */ + + if (priv->nwaiters > 0) + { + DEBUGASSERT(priv->work.worker == NULL); + ret = work_queue(HPWORK, &priv->work, ft5x06_data_worker, priv, 0); + if (ret != 0) + { + ierr("ERROR: Failed to queue work: %d\n", ret); + } + } +} +#endif + +/**************************************************************************** + * Name: ft5x06_data_interrupt + ****************************************************************************/ + +#ifndef CONFIG_FT5X06_POLLMODE +static int ft5x06_data_interrupt(int irq, FAR void *context, FAR void *arg) +{ + FAR struct ft5x06_dev_s *priv = (FAR struct ft5x06_dev_s *)arg; + FAR const struct ft5x06_config_s *config; + int ret; + + /* Get a pointer the callbacks for convenience (and so the code is not so + * ugly). + */ + + config = priv->config; + DEBUGASSERT(config != NULL); + + /* Disable further interrupts */ + + config->enable(config, false); + + /* Transfer processing to the worker thread. Since FT5x06 interrupts are + * disabled while the work is pending, no special action should be required + * to protected the work queue. + */ + + DEBUGASSERT(priv->work.worker == NULL); + ret = work_queue(HPWORK, &priv->work, ft5x06_data_worker, priv, 0); + if (ret != 0) + { + ierr("ERROR: Failed to queue work: %d\n", ret); + } + + /* Clear any pending interrupts and return success */ + + config->clear(config); + return OK; +} +#endif + +/**************************************************************************** + * Name: ft5x06_sample + ****************************************************************************/ + +#ifdef CONFIG_FT5X06_SINGLEPOINT +static ssize_t ft5x06_sample(FAR struct ft5x06_dev_s *priv, FAR char *buffer, + size_t len) +{ + FAR struct ft5x06_touch_data_s *raw; + FAR struct ft5x06_touch_point_s *touch; + FAR struct touch_sample_s *sample; + FAR struct touch_point_s *point; + int16_t x; + int16_t y; + uint8_t event; + uint8_t id; + + if (!priv->valid) + { + return 0; /* Nothing to read */ + } + + /* Raw data pointers (source) */ + + raw = (FAR struct ft5x06_touch_data_s *)priv->touchbuf; + touch = raw->touch; + + /* Get the reported X and Y positions */ + + #ifdef CONFIG_FT5X06_SWAPXY + y = TOUCH_POINT_GET_X(touch[0]); + x = TOUCH_POINT_GET_Y(touch[0]); +#else + x = TOUCH_POINT_GET_X(touch[0]); + y = TOUCH_POINT_GET_Y(touch[0]); +#endif + + /* Get the touch point ID and event */ + + event = TOUCH_POINT_GET_EVENT(touch[0]); + id = TOUCH_POINT_GET_ID(touch[0]); + + if (event == FT5x06_INVALID) + { + priv->lastevent = FT5x06_INVALID; + goto reset_and_drop; + } + + if (id == priv->lastid && event == priv->lastevent) + { + /* Same ID and event.. Is there positional data? */ + + if (raw->tdstatus == 0 || event == FT5x06_UP) + { + /* No... no new touch data */ + + goto reset_and_drop; + } + else + { + int16_t deltax; + int16_t deltay; + + /* Compare the change in position from the last report. */ + + deltax = (x - priv->lastx); + if (deltax < 0) + { + deltax = -deltax; + } + + if (deltax < CONFIG_FT5X06_THRESHX) + { + /* There as been no significant change in X, try Y */ + + deltay = (y - priv->lasty); + if (deltay < 0) + { + deltay = -deltay; + } + + if (deltax < CONFIG_FT5X06_THRESHX) + { + /* Ignore... no significant change in Y either */ + + goto drop; + } + } + } + } + + priv->lastid = id; + priv->lastevent = event; + priv->lastx = x; + priv->lasty = y; + + /* User data buffer points (sink) */ + + /* Return the number of touches read */ + + sample = (FAR struct touch_sample_s *)buffer; + sample->npoints = 1; + + /* Decode and return the single touch point */ + + point = sample->point; + point[0].id = id; + point[0].flags = g_event_map[event]; + point[0].x = x; + point[0].y = y; + point[0].h = 0; + point[0].w = 0; + point[0].pressure = 0; + + priv->valid = false; + return SIZEOF_TOUCH_SAMPLE_S(1); + +reset_and_drop: + priv->lastx = 0; + priv->lasty = 0; +drop: + priv->valid = false; + return 0; /* No new touches read. */ +} +#else +static ssize_t ft5x06_sample(FAR struct ft5x06_dev_s *priv, FAR char *buffer, + size_t len) +{ + FAR struct ft5x06_touch_data_s *raw; + FAR struct ft5x06_touch_point_s *touch; + FAR struct touch_sample_s *sample; + FAR struct touch_point_s *point; + unsigned int maxtouches; + unsigned int ntouches; + int i; + + maxtouches = (len - sizeof(int)) / sizeof(struct touch_point_s); + DEBUGASSERT(maxtouches > 0); /* Already verified */ + + if (!priv->valid) + { + return 0; /* Nothing to read */ + } + + /* Raw data pointers (source) */ + + raw = (FAR struct ft5x06_touch_data_s *)priv->touchbuf; + touch = raw->touch; + + /* Decode number of touches */ + + ntouches = raw->tdstatus; + DEBUGASSERT(ntouches <= FT5x06_MAX_TOUCHES); + + if (ntouches > maxtouches) + { + ntouches = maxtouches; + } + + if (ntouches < 1) + { + priv->valid = false; + return 0; /* No touches read. */ + } + + /* User data buffer points (sink) */ + + sample = (FAR struct touch_sample_s *)buffer; + point = sample->point; + + /* Return the number of touches read */ + + sample->npoints = ntouches; + + /* Decode and return the touch points */ + + for (i = 0; i < ntouches; i++) + { + int event = TOUCH_POINT_GET_EVENT(touch[i]); + + point[i].id = TOUCH_POINT_GET_ID(touch[i]); + point[i].flags = g_event_map[event]; +#ifdef CONFIG_FT5X06_SWAPXY + point[i].y = TOUCH_POINT_GET_X(touch[i]); + point[i].x = TOUCH_POINT_GET_Y(touch[i]); +#else + point[i].x = TOUCH_POINT_GET_X(touch[i]); + point[i].y = TOUCH_POINT_GET_Y(touch[i]); +#endif + point[i].h = 0; + point[i].w = 0; + point[i].pressure = 0; + } + + priv->valid = false; + return SIZEOF_TOUCH_SAMPLE_S(ntouches); +} +#endif /* CONFIG_FT5X06_SINGLEPOINT */ + +/**************************************************************************** + * Name: ft5x06_waitsample + ****************************************************************************/ + +static ssize_t ft5x06_waitsample(FAR struct ft5x06_dev_s *priv, + FAR char *buffer, size_t len) +{ + int ret; + + /* Disable pre-emption to prevent other threads from getting control while + * we muck with the semaphores. + */ + + sched_lock(); + + /* Now release the semaphore that manages mutually exclusive access to + * the device structure. This may cause other tasks to become ready to + * run, but they cannot run yet because pre-emption is disabled. + */ + + nxsem_post(&priv->devsem); + + /* Try to get the a sample... if we cannot, then wait on the semaphore + * that is posted when new sample data is available. + */ + + while (!priv->valid) + { + /* Increment the count of waiters */ + + priv->nwaiters++; + +#ifdef CONFIG_FT5X06_POLLMODE + /* The poll timer is stopped when there are no waiters. So we may + * need to restart with at the maximum rate. + */ + + if (priv->nwaiters == 1) + { + priv->delay = POLL_MINDELAY; + + ret = wd_start(priv->polltimer, priv->delay, ft5x06_poll_timeout, + 1, priv); + if (ret < 0) + { + ierr("ERROR: nxsem_wait failed: %d\n", ret); + goto errout; + } + } +#endif + + /* Wait for a change in the FT5x06 state */ + + ret = nxsem_wait(&priv->waitsem); + priv->nwaiters--; + + if (ret < 0) + { + /* If we are awakened by a signal, then we need to return + * the failure now. + */ + + ierr("ERROR: nxsem_wait failed: %d\n", ret); + DEBUGASSERT(ret == -EINTR); + goto errout; + } + } + + /* Re-acquire the semaphore that manages mutually exclusive access to + * the device structure. We may have to wait here. But we have our sample. + * Interrupts and pre-emption will be re-enabled while we wait. + */ + + ret = nxsem_wait(&priv->devsem); + if (ret >= 0) + { + /* Now sample the data. + * + * REVISIT: Is it safe to assume that priv->valid will always be + * true? I think that sched_lock() whould protect the setting. + */ + + ret = ft5x06_sample(priv, buffer, len); + } + +errout: + /* Restore pre-emption. We might get suspended here but that is okay + * because we already have our sample. Note: this means that if there + * were two threads reading from the FT5x06 for some reason, the data + * might be read out of order. + */ + + sched_unlock(); + return ret; +} + +/**************************************************************************** + * Name: ft5x06_bringup + ****************************************************************************/ + +static int ft5x06_bringup(FAR struct ft5x06_dev_s *priv) +{ + FAR const struct ft5x06_config_s *config; + struct i2c_msg_s msg; + uint8_t data[2]; + int ret; + + /* Get a pointer the callbacks for convenience (and so the code is not so + * ugly). + */ + + config = priv->config; + DEBUGASSERT(config != NULL); + + /* Set device mode to normal operation */ + + data[0] = FT5x06_TOUCH_MODE_REG; /* Register address */ + data[1] = FT5x06_DEV_MODE_WORKING; /* Normal mode */ + + msg.frequency = priv->frequency; /* I2C frequency */ + msg.addr = config->address; /* 7-bit address */ + msg.flags = 0; /* Write transaction with START */ + msg.buffer = data; /* Send two bytes followed by STOP */ + msg.length = 2; + + ret = I2C_TRANSFER(priv->i2c, &msg, 1); + if (ret < 0) + { + return ret; + } + +#ifndef CONFIG_FT5X06_POLLMODE + /* Enable FT5x06 interrupts */ + + config->clear(config); + config->enable(config, true); +#endif + return OK; +} + +/**************************************************************************** + * Name: ft5x06_shutdown + ****************************************************************************/ + +static void ft5x06_shutdown(FAR struct ft5x06_dev_s *priv) +{ +#ifdef CONFIG_FT5X06_POLLMODE + /* Stop the poll timer */ + + (void)wd_cancel(priv->polltimer); + +#else + FAR const struct ft5x06_config_s *config = priv->config; + + /* Make sure that the FT5x06 interrupt is disabled */ + + config->clear(config); + config->enable(config, false); + + /* Attach the interrupt handler */ + + (void)config->attach(config, NULL, NULL); +#endif +} + +/**************************************************************************** + * Name: ft5x06_open + ****************************************************************************/ + +static int ft5x06_open(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct ft5x06_dev_s *priv; + uint8_t tmp; + int ret; + + DEBUGASSERT(filep); + inode = filep->f_inode; + + DEBUGASSERT(inode && inode->i_private); + priv = (FAR struct ft5x06_dev_s *)inode->i_private; + + /* Get exclusive access to the driver data structure */ + + ret = nxsem_wait(&priv->devsem); + if (ret < 0) + { + /* This should only happen if the wait was cancelled by an signal */ + + ierr("ERROR: nxsem_wait failed: %d\n", ret); + DEBUGASSERT(ret == -EINTR); + return ret; + } + + /* Increment the reference count */ + + tmp = priv->crefs + 1; + if (tmp == 0) + { + /* More than 255 opens; uint8_t overflows to zero */ + + ret = -EMFILE; + goto errout_with_sem; + } + + /* When the reference increments to 1, this is the first open event + * on the driver.. and the time when we must initialize the driver. + */ + + if (tmp == 1) + { + ret = ft5x06_bringup(priv); + if (ret < 0) + { + ierr("ERROR: ft5x06_bringup failed: %d\n", ret); + goto errout_with_sem; + } + } + + /* Save the new open count on success */ + + priv->crefs = tmp; + +errout_with_sem: + nxsem_post(&priv->devsem); + return ret; +} + +/**************************************************************************** + * Name: ft5x06_close + ****************************************************************************/ + +static int ft5x06_close(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct ft5x06_dev_s *priv; + int ret; + + DEBUGASSERT(filep); + inode = filep->f_inode; + + DEBUGASSERT(inode && inode->i_private); + priv = (FAR struct ft5x06_dev_s *)inode->i_private; + + /* Get exclusive access to the driver data structure */ + + ret = nxsem_wait(&priv->devsem); + if (ret < 0) + { + /* This should only happen if the wait was cancelled by an signal */ + + ierr("ERROR: nxsem_wait failed: %d\n", ret); + DEBUGASSERT(ret == -EINTR); + return ret; + } + + /* Decrement the reference count unless it would decrement a negative + * value. + */ + + if (priv->crefs >= 1) + { + priv->crefs--; + } + + /* When the count decrements to zero, there are no further open references + * to the driver and it can be uninitialized. + */ + + if (priv->crefs == 0) + { + ft5x06_shutdown(priv); + } + + nxsem_post(&priv->devsem); + return OK; +} + +/**************************************************************************** + * Name: ft5x06_read + ****************************************************************************/ + +static ssize_t ft5x06_read(FAR struct file *filep, FAR char *buffer, + size_t len) +{ + FAR struct inode *inode; + FAR struct ft5x06_dev_s *priv; + int ret; + + DEBUGASSERT(filep); + inode = filep->f_inode; + + DEBUGASSERT(inode && inode->i_private); + priv = (FAR struct ft5x06_dev_s *)inode->i_private; + + /* Verify that the caller has provided a buffer large enough to receive + * the touch data. + */ + + if (len < SIZEOF_TOUCH_SAMPLE_S(1)) + { + /* We could provide logic to break up a touch report into segments and + * handle smaller reads... but why? + */ + + return -ENOSYS; + } + + /* Get exclusive access to the driver data structure */ + + ret = nxsem_wait(&priv->devsem); + if (ret < 0) + { + /* This should only happen if the wait was cancelled by an signal */ + + ierr("ERROR: nxsem_wait failed: %d\n", ret); + DEBUGASSERT(ret == -EINTR); + return ret; + } + + /* Try to read sample data. */ + + ret = ft5x06_sample(priv, buffer, len); + while (ret == 0) + { + /* Sample data is not available now. We would have to wait to receive + * sample data. If the user has specified the O_NONBLOCK option, then + * just return an error. + */ + + if (filep->f_oflags & O_NONBLOCK) + { + ret = -EAGAIN; + goto errout; + } + + /* Wait for sample data */ + + ret = ft5x06_waitsample(priv, buffer, len); + if (ret < 0) + { + /* We might have been awakened by a signal */ + + goto errout; + } + } + + ret = SIZEOF_TOUCH_SAMPLE_S(1); + +errout: + nxsem_post(&priv->devsem); + return ret; +} + +/**************************************************************************** + * Name:ft5x06_ioctl + ****************************************************************************/ + +static int ft5x06_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + FAR struct inode *inode; + FAR struct ft5x06_dev_s *priv; + int ret; + + iinfo("cmd: %d arg: %ld\n", cmd, arg); + DEBUGASSERT(filep); + inode = filep->f_inode; + + DEBUGASSERT(inode && inode->i_private); + priv = (FAR struct ft5x06_dev_s *)inode->i_private; + + /* Get exclusive access to the driver data structure */ + + ret = nxsem_wait(&priv->devsem); + if (ret < 0) + { + /* This should only happen if the wait was cancelled by an signal */ + + ierr("ERROR: nxsem_wait failed: %d\n", ret); + DEBUGASSERT(ret == -EINTR); + return ret; + } + + /* Process the IOCTL by command */ + + switch (cmd) + { + case TSIOC_SETFREQUENCY: /* arg: Pointer to uint32_t frequency value */ + { + FAR uint32_t *ptr = (FAR uint32_t *)((uintptr_t)arg); + DEBUGASSERT(priv->config != NULL && ptr != NULL); + priv->frequency = *ptr; + } + break; + + case TSIOC_GETFREQUENCY: /* arg: Pointer to uint32_t frequency value */ + { + FAR uint32_t *ptr = (FAR uint32_t *)((uintptr_t)arg); + DEBUGASSERT(priv->config != NULL && ptr != NULL); + *ptr = priv->frequency; + } + break; + + default: + ret = -ENOTTY; + break; + } + + nxsem_post(&priv->devsem); + return ret; +} + +/**************************************************************************** + * Name: ft5x06_poll + ****************************************************************************/ + +#ifndef CONFIG_DISABLE_POLL +static int ft5x06_poll(FAR struct file *filep, FAR struct pollfd *fds, + bool setup) +{ + FAR struct inode *inode; + FAR struct ft5x06_dev_s *priv; + int ret; + int i; + + iinfo("setup: %d\n", (int)setup); + DEBUGASSERT(filep && fds); + inode = filep->f_inode; + + DEBUGASSERT(inode && inode->i_private); + priv = (FAR struct ft5x06_dev_s *)inode->i_private; + + /* Are we setting up the poll? Or tearing it down? */ + + ret = nxsem_wait(&priv->devsem); + if (ret < 0) + { + /* This should only happen if the wait was cancelled by an signal */ + + ierr("ERROR: nxsem_wait failed: %d\n", ret); + DEBUGASSERT(ret == -EINTR); + return ret; + } + + if (setup) + { + /* Ignore waits that do not include POLLIN */ + + if ((fds->events & POLLIN) == 0) + { + ierr("ERROR: Missing POLLIN: revents: %08x\n", fds->revents); + ret = -EDEADLK; + goto errout; + } + + /* This is a request to set up the poll. Find an available + * slot for the poll structure reference + */ + + for (i = 0; i < CONFIG_FT5X06_NPOLLWAITERS; i++) + { + /* Find an available slot */ + + if (!priv->fds[i]) + { + /* Bind the poll structure and this slot */ + + priv->fds[i] = fds; + fds->priv = &priv->fds[i]; + break; + } + } + + if (i >= CONFIG_FT5X06_NPOLLWAITERS) + { + ierr("ERROR: No available slot found: %d\n", i); + fds->priv = NULL; + ret = -EBUSY; + goto errout; + } + + /* Should we immediately notify on any of the requested events? */ + + if (priv->valid) + { + ft5x06_notify(priv); + } + } + else if (fds->priv) + { + /* This is a request to tear down the poll. */ + + struct pollfd **slot = (struct pollfd **)fds->priv; + DEBUGASSERT(slot != NULL); + + /* Remove all memory of the poll setup */ + + *slot = NULL; + fds->priv = NULL; + } + +errout: + nxsem_post(&priv->devsem); + return ret; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ft5x06_register + * + * Description: + * Configure the FT5x06 to use the provided I2C device instance. This + * will register the driver as /dev/inputN where N is the minor device + * number + * + * Input Parameters: + * dev - An I2C driver instance + * config - Persistant board configuration data + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int ft5x06_register(FAR struct i2c_master_s *i2c, + FAR const struct ft5x06_config_s *config, int minor) +{ + FAR struct ft5x06_dev_s *priv; + char devname[DEV_NAMELEN]; + int ret; + + iinfo("i2c: %p minor: %d\n", i2c, minor); + + /* Debug-only sanity checks */ + + DEBUGASSERT(i2c != NULL && config != NULL && minor >= 0 && minor < 100); +#ifdef CONFIG_FT5X06_POLLMODE + DEBUGASSERT(config->wakeup != NULL && config->nreset != NULL); +#else + DEBUGASSERT(config->attach != NULL && config->enable != NULL && + config->clear != NULL && config->wakeup != NULL && + config->nreset != NULL); +#endif + + /* Create and initialize a FT5x06 device driver instance */ + + priv = (FAR struct ft5x06_dev_s *)kmm_zalloc(sizeof(struct ft5x06_dev_s)); + if (!priv) + { + ierr("ERROR: kmm_malloc(%d) failed\n", sizeof(struct ft5x06_dev_s)); + return -ENOMEM; + } + + /* Initialize the FT5x06 device driver instance */ + + priv->i2c = i2c; /* Save the I2C device handle */ + priv->config = config; /* Save the board configuration */ + priv->frequency = config->frequency; /* Set the current I2C frequency */ + + nxsem_init(&priv->devsem, 0, 1); /* Initialize device structure semaphore */ + nxsem_init(&priv->waitsem, 0, 0); /* Initialize pen event wait semaphore */ + + /* The event wait semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + + nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + +#ifdef CONFIG_FT5X06_POLLMODE + /* Allocate a timer for polling the FT5x06 */ + + priv->delay = POLL_MAXDELAY; + priv->polltimer = wd_create(); + if (priv->polltimer == NULL) + { + ierr("ERROR: Failed to allocate polltimer\n"); + ret = -EBUSY; + goto errout_with_priv; + } +#else + /* Make sure that the FT5x06 interrupt interrupt is disabled */ + + config->clear(config); + config->enable(config, false); + + /* Attach the interrupt handler */ + + ret = config->attach(config, ft5x06_data_interrupt, + priv); + if (ret < 0) + { + ierr("ERROR: Failed to attach interrupt\n"); + goto errout_with_timer; + } +#endif + + /* Register the device as an input device */ + + (void)snprintf(devname, DEV_NAMELEN, DEV_FORMAT, minor); + iinfo("Registering %s\n", devname); + + ret = register_driver(devname, &ft5x06_fops, 0666, priv); + if (ret < 0) + { + ierr("ERROR: register_driver() failed: %d\n", ret); + goto errout_with_timer; + } + + /* Schedule work to perform the initial sampling and to set the data + * availability conditions. + */ + + ret = work_queue(HPWORK, &priv->work, ft5x06_data_worker, priv, 0); + if (ret < 0) + { + ierr("ERROR: Failed to queue work: %d\n", ret); + goto errout_with_timer; + } + + /* And return success */ + + return OK; + +errout_with_timer: +#ifdef CONFIG_FT5X06_POLLMODE + (void)wd_delete(priv->polltimer); + +errout_with_priv: +#endif + nxsem_destroy(&priv->devsem); + kmm_free(priv); + return ret; +} diff --git a/drivers/input/ft5x06.h b/drivers/input/ft5x06.h new file mode 100644 index 0000000000000000000000000000000000000000..b309f8dc1f0804d50e0e44f2cb062bafb7e92286 --- /dev/null +++ b/drivers/input/ft5x06.h @@ -0,0 +1,196 @@ +/**************************************************************************** + * drivers/input/ft5x06.h + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: + * "FT5x06", FocalTech Systems Co., Ltd, D-FT5x06-1212-V4.0, Revised + * Dec. 18, 2012 + * + * Some of this driver was developed with input from NXP sample code for + * the LPCXpresso-LPC54628 baord. That sample code as a compatible BSD + * license: + * + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The FT5x06 Series ICs are single-chip capacitive touch panel controller + * ICs with a built-in 8 bit Micro-controller unit (MCU). They adopt the + * mutual capacitance approach, which supports true multi-touch capability. + * In conjunction with a mutual capacitive touch panel, the FT5x06 have + * user-friendly input functions, which can be applied on many portable + * devices, such as cellular phones, MIDs, netbook and notebook personal + * computers. + */ + +#ifndef __DRIVERS_INPUT_FT5X06_H +#define __DRIVERS_INPUT_FT5X06_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* WARNING: Some definitions may apply only to the FT5336 */ +/* FT5x06 maximum number of simultaneously detected touches. */ + +#define FT5x06_MAX_TOUCHES (5) + +/* FT5x06 raw touch data length. */ + +#define FT5x06_TOUCH_DATA_LEN (0x20) + +/* FT5x06 register addresses */ + +#define FT5x06_TOUCH_MODE_REG (0x00) /* Mode register */ +#define FT5x06_TOUCH_GESTID_REG (0x01) /* Gesture ID register */ +#define FT5x06_TOUCH_STAT_REG (0x02) /* Touch data status */ + /* See struct ft5x06_touch_point_s */ +#define FT5x06_TH_GROUP_REG (0x80) /* Threshold for touch detection */ +#define FT5x06_TH_DIFF_REG (0x85) /* Filter function coefficients */ +#define FT5x06_CTRL_REG (0x86) /* Control register */ +#define FT5x06_TIMEENTERMONITOR_REG (0x87) /* Time switching Active to Monitor */ +#define FT5x06_PERIODACTIVE_REG (0x88) /* Report rate in Active mode */ +#define FT5x06_PERIODMONITOR_REG (0x89) /* Report rate in Monitor mode */ +#define FT5x06_RADIAN_VALUE_REG (0x91) /* Minimum allowing angle */ +#define FT5x06_OFFSET_LEFT_RIGHT_REG (0x92) /* Mimimum offset */ +#define FT5x06_OFFSET_UP_DOWN_REG (0x93) /* Maximum offset */ +#define FT5x06_DISTANCE_LEFT_RIGHT_REG (0x94) /* Minimum distance */ +#define FT5x06_DISTANCE_UP_DOWN_REG (0x95) /* Minimum distance */ +#define FT5x06_DISTANCE_ZOOM_REG (0x96) /* Maximum distance */ +#define FT5x06_LIB_VER_H_REG (0xa1) /* MS LIB version */ +#define FT5x06_LIB_VER_L_REG (0xa2) /* LS LIB version */ +#define FT5x06_CIPHER_REG (0xa3) /* Chip selecting */ +#define FT5x06_GMODE_REG (0xa4) /* Interrupt mode */ +#define FT5x06_PWR_MODE_REG (0xa5) /* Power mode */ +#define FT5x06_FIRMID_REG (0xa6) /* Firmware version */ +#define FT5x06_CHIP_ID_REG (0xa8) /* Chip ID */ +#define FT5x06_RELEASE_CODE_ID_REG (0xaf) /* Release code version */ +#define FT5x06_STATE_REG (0xbc) /* Current operating mode */ + +#define FT5x06_TOUCH_DATA_STARTREG (1) /* Address where data begins */ + +/* Possible values of the DEV_MODE register */ + +#define FT5x06_DEV_MODE_WORKING (0x00) +#define FT5x06_DEV_MODE_FACTORY (0x04) + +/* Possible values of the GEST_ID register */ + +#define FT5x06_GEST_ID_NO_GESTURE (0x00) +#define FT5x06_GEST_ID_MOVE_UP (0x10) +#define FT5x06_GEST_ID_MOVE_RIGHT (0x14) +#define FT5x06_GEST_ID_MOVE_DOWN (0x18) +#define FT5x06_GEST_ID_MOVE_LEFT (0x1C) +#define FT5x06_GEST_ID_SINGLE_CLICK (0x20) +#define FT5x06_GEST_ID_DOUBLE_CLICK (0x22) +#define FT5x06_GEST_ID_ROTATE_CLOCKWISE (0x28) +#define FT5x06_GEST_ID_ROTATE_C_CLOCKWISE (0x29) +#define FT5x06_GEST_ID_ZOOM_IN (0x40) +#define FT5x06_GEST_ID_ZOOM_OUT (0x49) + +/* Values related to FT5x06_CTRL_REG */ + +#define FT5x06_CTRL_KEEP_ACTIVE_MODE (0x00) +#define FT5x06_CTRL_KEEP_AUTO_SWITCH_MONITOR_MODE (0x01) + +/* Possible values of FT5x06_GMODE_REG */ + +#define FT5x06_G_MODE_INTERRUPT_POLLING (0x00) +#define FT5x06_G_MODE_INTERRUPT_TRIGGER (0x01) + +/* Possible values of FT5x06_CHIP_ID_REG */ + +#define FT5x06_ID_VALUE (0x51) + +/* Operations on struct ft5x06_touch_point_s */ + +#define TOUCH_POINT_GET_EVENT(t) ((t).xh >> 6) +#define TOUCH_POINT_GET_ID(t) ((t).yh >> 4) +#define TOUCH_POINT_GET_X(t) ((((t).xh & 0x0f) << 8) | (t).xl) +#define TOUCH_POINT_GET_Y(t) ((((t).yh & 0x0f) << 8) | (t).yl) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum touch_event_e +{ + FT5x06_DOWN = 0, /* The state changed to touched */ + FT5x06_UP = 1, /* The state changed to not touched */ + FT5x06_CONTACT = 2, /* There is a continuous touch being detected */ + FT5x06_INVALID = 3 /* No touch information available */ +}; + +/* Describes on touchpoint returned by the FT5x06 */ + +struct ft5x06_touch_point_s +{ + uint8_t xh; + uint8_t xl; + uint8_t yh; + uint8_t yl; + uint8_t weight; + uint8_t area; +}; + +/* Describes all touch data returned by the FT5x06 */ + +struct ft5x06_touch_data_s +{ + uint8_t gestid; /* Gesture ID */ + uint8_t tdstatus; /* Touch status */ + struct ft5x06_touch_point_s touch[FT5x06_MAX_TOUCHES]; +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __DRIVERS_INPUT_FT5X06_H */ diff --git a/drivers/input/nunchuck.c b/drivers/input/nunchuck.c new file mode 100644 index 0000000000000000000000000000000000000000..ccd591802a637a4cbb40423be9326ed01d963bf6 --- /dev/null +++ b/drivers/input/nunchuck.c @@ -0,0 +1,619 @@ +/**************************************************************************** + * drivers/input/nunchuck.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2017 Alan Carvalho de Assis. All rights reserved. + * Author: Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file provides a driver for a Nintendo Wii Nunchuck joystick device. + * The nunchuck joystick provides X/Y positional data as integer values. + * The analog positional data may also be accompanied by discrete button data. + * + * The nunchuck joystick driver exports a standard character driver + * interface. By convention, the nunchuck joystick is registered as an input + * device at /dev/nunchuckN where N uniquely identifies the driver instance. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure provides the state of one nunchuck joystick driver */ + +struct nunchuck_dev_s +{ + FAR struct i2c_master_s *i2c_dev; /* I2C interface connected to Nunchuck */ + nunchuck_buttonset_t nck_sample; /* Last sampled button states */ + sem_t nck_exclsem; /* Supports exclusive access to the device */ + + /* The following is a singly linked list of open references to the + * joystick device. + */ + + FAR struct nunchuck_open_s *nck_open; +}; + +/* This structure describes the state of one open joystick driver instance */ + +struct nunchuck_open_s +{ + /* Supports a singly linked list */ + + FAR struct nunchuck_open_s *nck_flink; + + /* The following will be true if we are closing */ + + volatile bool nck_closing; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Semaphore helpers */ + +static inline int nunchuck_takesem(sem_t *sem); +#define nunchuck_givesem(s) nxsem_post(s); + +/* Character driver methods */ + +static int nunchuck_open(FAR struct file *filep); +static int nunchuck_close(FAR struct file *filep); +static ssize_t nunchuck_read(FAR struct file *filep, FAR char *buffer, + size_t buflen); +static int nunchuck_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); +/* I2C Helpers */ +static int nunchuck_i2c_read(FAR struct nunchuck_dev_s *priv, + FAR uint8_t *regval, int len); +static int nunchuck_i2c_write(FAR struct nunchuck_dev_s *priv, + uint8_t const *data, int len); +static int nunchuck_sample(FAR struct nunchuck_dev_s *priv, + FAR struct nunchuck_sample_s *buffer); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct file_operations nunchuck_fops = +{ + nunchuck_open, /* open */ + nunchuck_close, /* close */ + nunchuck_read, /* read */ + NULL, /* write */ + NULL, /* seek */ + nunchuck_ioctl /* ioctl */ +#ifndef CONFIG_DISABLE_POLL + , NULL /* poll */ +#endif +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + , NULL /* unlink */ +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nunchuck_i2c_read + ****************************************************************************/ + +static int nunchuck_i2c_read(FAR struct nunchuck_dev_s *priv, + FAR uint8_t *regval, int len) +{ + struct i2c_config_s config; + int ret = -1; + + /* Set up the I2C configuration */ + + config.frequency = NUNCHUCK_I2C_FREQ; + config.address = NUNCHUCK_ADDR; + config.addrlen = 7; + + /* Read "len" bytes from regaddr */ + + ret = i2c_read(priv->i2c_dev, &config, regval, len); + if (ret < 0) + { + ierr ("i2c_read failed: %d\n", ret); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: nunchuck_i2c_write + ****************************************************************************/ + +static int nunchuck_i2c_write(FAR struct nunchuck_dev_s *priv, + uint8_t const *data, int len) +{ + struct i2c_config_s config; + int ret; + + /* Set up the I2C configuration */ + + config.frequency = NUNCHUCK_I2C_FREQ; + config.address = NUNCHUCK_ADDR; + config.addrlen = 7; + + /* Write the data */ + + ret = i2c_write(priv->i2c_dev, &config, data, len); + if (ret < 0) + { + ierr("ERROR: i2c_write failed: %d\n", ret); + } + + return ret; +} + +static int nunchuck_sample(FAR struct nunchuck_dev_s *priv, + FAR struct nunchuck_sample_s *buffer) +{ + uint8_t cmd[2]; + uint8_t data[6]; + static bool initialized = false; + + if (!initialized) + { + /* Start device */ + + cmd[0] = 0x40; + cmd[1] = 0x00; + nunchuck_i2c_write(priv, cmd, 2); + + /* Delay 20ms */ + + nxsig_usleep(20*1000); + + initialized = true; + } + + /* Prepare to read */ + + cmd[0] = 0x00; + nunchuck_i2c_write(priv, cmd, 1); + + /* Wait */ + + nxsig_usleep(1000); + + /* Read data */ + + nunchuck_i2c_read(priv, &data[0], 1); + + /* Wait */ + + nxsig_usleep(1000); + + /* Wait */ + + nxsig_usleep(1000); + + nunchuck_i2c_read(priv, &data[1], 1); + + /* Wait */ + + nxsig_usleep(1000); + + nunchuck_i2c_read(priv, &data[2], 1); + + /* Wait */ + + nxsig_usleep(1000); + + nunchuck_i2c_read(priv, &data[3], 1); + + /* Wait */ + + nxsig_usleep(1000); + + nunchuck_i2c_read(priv, &data[4], 1); + + /* Wait */ + + nxsig_usleep(1000); + + nunchuck_i2c_read(priv, &data[5], 1); + + /* Save the sample */ + + buffer->js_x = (uint16_t) data[0]; + buffer->js_y = (uint16_t) data[1]; + buffer->acc_x = (uint16_t) data[2]; + buffer->acc_y = (uint16_t) data[3]; + buffer->acc_z = (uint16_t) data[4]; + buffer->nck_buttons = (uint8_t) ((data[5]+1) & 0x03); + + iinfo("X: %03d | Y: %03d | AX: %03d AY: %03d AZ: %03d | B: %d\n", + data[0], data[1], data[2], data[3], data[4], ((data[5]+1) & 0x03)); + + return OK; +} + +/**************************************************************************** + * Name: nunchuck_takesem + ****************************************************************************/ + +static inline int nunchuck_takesem(sem_t *sem) +{ + int ret; + + /* Take a count from the semaphore, possibly waiting */ + + ret = nxsem_wait(sem); + + /* The only case that an error should occur here is if the wait + * was awakened by a signal + */ + + DEBUGASSERT(ret == OK || ret == -EINTR); + return ret; +} + +/**************************************************************************** + * Name: nunchuck_open + ****************************************************************************/ + +static int nunchuck_open(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct nunchuck_dev_s *priv; + FAR struct nunchuck_open_s *opriv; + int ret; + + DEBUGASSERT(filep && filep->f_inode); + inode = filep->f_inode; + DEBUGASSERT(inode->i_private); + priv = (FAR struct nunchuck_dev_s *)inode->i_private; + + /* Get exclusive access to the driver structure */ + + ret = nunchuck_takesem(&priv->nck_exclsem); + if (ret < 0) + { + ierr("ERROR: nunchuck_takesem failed: %d\n", ret); + return ret; + } + + /* Allocate a new open structure */ + + opriv = (FAR struct nunchuck_open_s *)kmm_zalloc(sizeof(struct nunchuck_open_s)); + if (!opriv) + { + ierr("ERROR: Failled to allocate open structure\n"); + ret = -ENOMEM; + goto errout_with_sem; + } + + /* Attach the open structure to the device */ + + opriv->nck_flink = priv->nck_open; + priv->nck_open = opriv; + + /* Attach the open structure to the file structure */ + + filep->f_priv = (FAR void *)opriv; + ret = OK; + +errout_with_sem: + nunchuck_givesem(&priv->nck_exclsem); + return ret; +} + +/**************************************************************************** + * Name: nunchuck_close + ****************************************************************************/ + +static int nunchuck_close(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct nunchuck_dev_s *priv; + FAR struct nunchuck_open_s *opriv; + FAR struct nunchuck_open_s *curr; + FAR struct nunchuck_open_s *prev; + irqstate_t flags; + bool closing; + int ret; + + DEBUGASSERT(filep && filep->f_priv && filep->f_inode); + opriv = filep->f_priv; + inode = filep->f_inode; + DEBUGASSERT(inode->i_private); + priv = (FAR struct nunchuck_dev_s *)inode->i_private; + + /* Handle an improbable race conditions with the following atomic test + * and set. + * + * This is actually a pretty feeble attempt to handle this. The + * improbable race condition occurs if two different threads try to + * close the joystick driver at the same time. The rule: don't do + * that! It is feeble because we do not really enforce stale pointer + * detection anyway. + */ + + flags = enter_critical_section(); + closing = opriv->nck_closing; + opriv->nck_closing = true; + leave_critical_section(flags); + + if (closing) + { + /* Another thread is doing the close */ + + return OK; + } + + /* Get exclusive access to the driver structure */ + + ret = nunchuck_takesem(&priv->nck_exclsem); + if (ret < 0) + { + ierr("ERROR: nunchuck_takesem failed: %d\n", ret); + return ret; + } + + /* Find the open structure in the list of open structures for the device */ + + for (prev = NULL, curr = priv->nck_open; + curr && curr != opriv; + prev = curr, curr = curr->nck_flink); + + DEBUGASSERT(curr); + if (!curr) + { + ierr("ERROR: Failed to find open entry\n"); + ret = -ENOENT; + goto errout_with_exclsem; + } + + /* Remove the structure from the device */ + + if (prev) + { + prev->nck_flink = opriv->nck_flink; + } + else + { + priv->nck_open = opriv->nck_flink; + } + + /* And free the open structure */ + + kmm_free(opriv); + + ret = OK; + +errout_with_exclsem: + nunchuck_givesem(&priv->nck_exclsem); + return ret; +} + +/**************************************************************************** + * Name: nunchuck_read + ****************************************************************************/ + +static ssize_t nunchuck_read(FAR struct file *filep, FAR char *buffer, + size_t len) +{ + FAR struct inode *inode; + FAR struct nunchuck_dev_s *priv; + int ret; + + DEBUGASSERT(filep && filep->f_inode); + inode = filep->f_inode; + DEBUGASSERT(inode->i_private); + priv = (FAR struct nunchuck_dev_s *)inode->i_private; + + /* Make sure that the buffer is sufficiently large to hold at least one + * complete sample. + * + * REVISIT: Should also check buffer alignment. + */ + + if (len < sizeof(struct nunchuck_sample_s)) + { + ierr("ERROR: buffer too small: %lu\n", (unsigned long)len); + return -EINVAL; + } + + /* Get exclusive access to the driver structure */ + + ret = nunchuck_takesem(&priv->nck_exclsem); + if (ret < 0) + { + ierr("ERROR: nunchuck_takesem failed: %d\n", ret); + return ret; + } + + /* Read and return the current state of the joystick buttons */ + + ret = nunchuck_sample(priv, (FAR struct nunchuck_sample_s *)buffer); + if (ret >= 0) + { + ret = sizeof(struct nunchuck_sample_s); + } + + nunchuck_givesem(&priv->nck_exclsem); + return (ssize_t)ret; +} + +/**************************************************************************** + * Name: nunchuck_ioctl + ****************************************************************************/ + +static int nunchuck_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + FAR struct inode *inode; + FAR struct nunchuck_dev_s *priv; + int ret; + + DEBUGASSERT(filep && filep->f_priv && filep->f_inode); + inode = filep->f_inode; + DEBUGASSERT(inode->i_private); + priv = (FAR struct nunchuck_dev_s *)inode->i_private; + + /* Get exclusive access to the driver structure */ + + ret = nunchuck_takesem(&priv->nck_exclsem); + if (ret < 0) + { + ierr("ERROR: nunchuck_takesem failed: %d\n", ret); + return ret; + } + + /* Handle the ioctl command */ + + ret = -EINVAL; + switch (cmd) + { + /* Command: NUNCHUCKIOC_SUPPORTED + * Description: Report the set of button events supported by the hardware; + * Argument: A pointer to writeable integer value in which to return the + * set of supported buttons. + * Return: Zero (OK) on success. Minus one will be returned on failure + * with the errno value set appropriately. + */ + + case NUNCHUCKIOC_SUPPORTED: + { + FAR int *supported = (FAR int *)((uintptr_t)arg); + + if (supported) + { + *supported = (NUNCHUCK_BUTTON_Z_BIT | NUNCHUCK_BUTTON_C_BIT); + ret = OK; + } + } + break; + + default: + ierr("ERROR: Unrecognized command: %ld\n", cmd); + ret = -ENOTTY; + break; + } + + nunchuck_givesem(&priv->nck_exclsem); + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nunchuck_register + * + * Description: + * Register the Nunchuck character driver as the specified device. + * + * Input Parameters: + * devname - The name of the Nunchuck joystick device to be registered. + * This should be a string of the form "/dev/nunchuckN" where N is the + * minor device number. + * i2c - An instance of the platform-specific I2C connected to Nunchuck. + * + * Returned Values: + * Zero (OK) is returned on success. Otherwise a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int nunchuck_register(FAR const char *devname, FAR struct i2c_master_s *i2c) +{ + FAR struct nunchuck_dev_s *priv; + int ret; + + iinfo("Enter\n"); + + DEBUGASSERT(devname && i2c); + + /* Allocate a new nunchuck driver instance */ + + priv = (FAR struct nunchuck_dev_s *) + kmm_zalloc(sizeof(struct nunchuck_dev_s)); + + if (!priv) + { + ierr("ERROR: Failed to allocate device structure\n"); + return -ENOMEM; + } + + /* Save the i2c device */ + + priv->i2c_dev = i2c; + + /* Initialize the new nunchuck driver instance */ + + nxsem_init(&priv->nck_exclsem, 0, 1); + + /* And register the nunchuck driver */ + + ret = register_driver(devname, &nunchuck_fops, 0666, priv); + if (ret < 0) + { + ierr("ERROR: register_driver failed: %d\n", ret); + goto errout_with_priv; + } + + return OK; + +errout_with_priv: + nxsem_destroy(&priv->nck_exclsem); + kmm_free(priv); + return ret; +} diff --git a/drivers/input/stmpe811_gpio.c b/drivers/input/stmpe811_gpio.c index 907c250debae41c3cc81cbbc90f7267cab4703e7..c4a18095c702ec19c0cfb76c3c6bdf81745088be 100644 --- a/drivers/input/stmpe811_gpio.c +++ b/drivers/input/stmpe811_gpio.c @@ -172,22 +172,29 @@ int stmpe811_gpioconfig(STMPE811_HANDLE handle, uint8_t pinconfig) { /* The pin is an output */ - regval = stmpe811_getreg8(priv, STMPE811_GPIO_DIR); - regval &= ~pinmask; - stmpe811_putreg8(priv, STMPE811_GPIO_DIR, regval); + regval = stmpe811_getreg8(priv, STMPE811_GPIO_DIR_REG); + regval |= pinmask; + stmpe811_putreg8(priv, STMPE811_GPIO_DIR_REG, regval); /* Set its initial output value */ - - stmpe811_gpiowrite(handle, pinconfig, - (pinconfig & STMPE811_GPIO_VALUE) != STMPE811_GPIO_ZERO); + if ((pinconfig & STMPE811_GPIO_VALUE) != STMPE811_GPIO_ZERO) + { + /* Set the output valu(s)e by writing to the SET register */ + stmpe811_putreg8(priv, STMPE811_GPIO_SETPIN, (1 << pin)); + } + else + { + /* Clear the output value(s) by writing to the CLR register */ + stmpe811_putreg8(priv, STMPE811_GPIO_CLRPIN, (1 << pin)); + } } else { /* It is an input */ - regval = stmpe811_getreg8(priv, STMPE811_GPIO_DIR); - regval |= pinmask; - stmpe811_putreg8(priv, STMPE811_GPIO_DIR, regval); + regval = stmpe811_getreg8(priv, STMPE811_GPIO_DIR_REG); + regval &= ~pinmask; + stmpe811_putreg8(priv, STMPE811_GPIO_DIR_REG, regval); /* Set up the falling edge detection */ diff --git a/drivers/input/tsc2007.c b/drivers/input/tsc2007.c index edf07764f7fd6fc47085d5fee146812998839344..65c57304b01c81db52553d4fc05218d76ce355d5 100644 --- a/drivers/input/tsc2007.c +++ b/drivers/input/tsc2007.c @@ -945,9 +945,9 @@ static ssize_t tsc2007_read(FAR struct file *filep, FAR char *buffer, size_t len ret = tsc2007_sample(priv, &sample); if (ret < 0) { - /* Sample data is not available now. We would ave to wait to get - * receive sample data. If the user has specified the O_NONBLOCK - * option, then just return an error. + /* Sample data is not available now. We would ave to wait to receive + * sample data. If the user has specified the O_NONBLOCK option, then + * just return an error. */ if (filep->f_oflags & O_NONBLOCK) @@ -1259,11 +1259,18 @@ int tsc2007_register(FAR struct i2c_master_s *dev, /* Initialize the TSC2007 device driver instance */ memset(priv, 0, sizeof(struct tsc2007_dev_s)); - priv->i2c = dev; /* Save the I2C device handle */ - priv->config = config; /* Save the board configuration */ + priv->i2c = dev; /* Save the I2C device handle */ + priv->config = config; /* Save the board configuration */ + nxsem_init(&priv->devsem, 0, 1); /* Initialize device structure semaphore */ nxsem_init(&priv->waitsem, 0, 0); /* Initialize pen event wait semaphore */ + /* The event wait semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + + nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + /* Make sure that interrupts are disabled */ config->clear(config); diff --git a/drivers/ioexpander/pcf8574.c b/drivers/ioexpander/pcf8574.c index 56baaa7e8ad15f8111862f3b2e294d6a47f4908f..ba8bca8c1ff9871fc0a515aa6815dcd9714f6b42 100644 --- a/drivers/ioexpander/pcf8574.c +++ b/drivers/ioexpander/pcf8574.c @@ -777,6 +777,7 @@ static FAR void *pcf8574_attach(FAR struct ioexpander_dev_s *dev, * ****************************************************************************/ +#ifdef CONFIG_PCF8574_INT_ENABLE static int pcf8574_detach(FAR struct ioexpander_dev_s *dev, FAR void *handle) { FAR struct pcf8574_dev_s *priv = (FAR struct pcf8574_dev_s *)dev; @@ -792,6 +793,7 @@ static int pcf8574_detach(FAR struct ioexpander_dev_s *dev, FAR void *handle) cb->cbarg = NULL; return OK; } +#endif /**************************************************************************** * Name: pcf8574_int_update diff --git a/drivers/lcd/Kconfig b/drivers/lcd/Kconfig index bbc9d654ad74579dcc87f1389c7f483ae2ad4a6a..3cb4769d14da70a011670e5788ee922503826277 100644 --- a/drivers/lcd/Kconfig +++ b/drivers/lcd/Kconfig @@ -19,12 +19,21 @@ menuconfig LCD if LCD +config LCD_PACKEDMSFIRST + bool + default n + +config LCD_UPDATE + bool + default n + select NX_UPDATE if NX + comment "Common Graphic LCD Settings" config LCD_FRAMEBUFFER bool "LCD framebuffer front end" default n - select NX_UPDATE if NX + select LCD_UPDATE ---help--- Enable a "front end" that converts an sequential LCD driver into a standard, NuttX frame buffer driver. @@ -36,6 +45,17 @@ config LCD_FRAMEBUFFER disabled because this external commone framebuffer interface will provide the necessary buffering. +config LCD_EXTERNINIT + bool "External LCD Initialization" + default n + depends on LCD_FRAMEBUFFER + ---help--- + Define to support external LCD initialization by platform-specific + code. This this option is defined, then the LCD framebuffer + emulation will call board_graphics_setup() to initialize the + graphics device. This option is necessary if display is used that + cannot be initialized using the standard LCD interfaces. + menu "LCD driver selection" config LCD_CONSOLE @@ -246,6 +266,42 @@ config NOKIA6100_RGBORD endif +config LCD_MAX7219 + bool "Matrix of 8x8 LEDs controlled by MAX7219" + default n + ---help--- + Matrix of LEDs (8x8) controlled by MAX7219. + You can use cluster of 8x8 chained together. + +if LCD_MAX7219 + +config MAX7219_NHORIZONTALBLKS + int "Number of 8x8 LEDs matrices in the horizontal (width)!" + default 1 + ---help--- + Specifies the number of physical 8x8 LED matrices that are + connected together in the horizontal. In fact we have only + a single strip, but it can be arranged in blocks creating + physically horizontal/vertical columns/rows. + +config MAX7219_NVERTICALBLKS + int "Number of 8x8 LEDs matrices in the vertical (height)!" + default 1 + ---help--- + Specifies the number of physical 8x8 LED matrices that are + connected together in the vertical. In fact we have only + a single strip, but it can be arranged in blocks creating + physically horizontal/vertical columns/rows. + +config MAX7219_INTENSITY + int "Default LED Matrix bright intensity" + default 10 + range 0 15 + ---help--- + Specifies the default LEDs bright intensity to use. + +endif # LCD_MAX7219 + config LCD_MIO283QT2 bool "MIO283QT-2 TFT LCD Display Module" default n diff --git a/drivers/lcd/Make.defs b/drivers/lcd/Make.defs index 658d48d807b6eb958d4823c019c9b754bc0ed8fd..a1239afb2fbc65f37603fe9531ae7c28da01614a 100644 --- a/drivers/lcd/Make.defs +++ b/drivers/lcd/Make.defs @@ -83,6 +83,10 @@ ifeq ($(CONFIG_LCD_MIO283QT2),y) CSRCS += mio283qt2.c endif +ifeq ($(CONFIG_LCD_MAX7219),y) + CSRCS += max7219.c +endif + ifeq ($(CONFIG_LCD_MIO283QT9A),y) CSRCS += mio283qt9a.c endif @@ -110,7 +114,7 @@ endif ifeq ($(CONFIG_LCD_RA8875),y) CSRCS += ra8875.c endif -endif # CONFIG_NX_LCDDRIVER +endif # CONFIG_LCD ifeq ($(CONFIG_SLCD),y) diff --git a/drivers/lcd/lcd_framebuffer.c b/drivers/lcd/lcd_framebuffer.c index f8bffbd642639214de2f586c8c179be1d3a20a87..369d774a214b9e754a9224b4e5c4b91bbaea7032 100644 --- a/drivers/lcd/lcd_framebuffer.c +++ b/drivers/lcd/lcd_framebuffer.c @@ -201,8 +201,6 @@ static void lcdfb_update(FAR struct lcdfb_dev_s *priv, endx = priv->xres-1; } - width = endx - startx + 1; - starty = rect->pt1.y; if (starty < 0) { @@ -215,6 +213,18 @@ static void lcdfb_update(FAR struct lcdfb_dev_s *priv, endy = priv->yres-1; } + /* If the display uses a value of BPP < 8, then we may have to extend the + * rectangle on the left so that it is byte aligned. Works for BPP={1,2,4} + */ + + if (pinfo->bpp < 8) + { + unsigned int pixperbyte = 8 / pinfo->bpp; + startx &= ~(pixperbyte - 1); + } + + width = endx - startx + 1; + /* Get the starting position in the framebuffer */ run = priv->fbmem + starty * priv->stride; @@ -486,6 +496,16 @@ int up_fbinitialize(int display) priv->vtable.setcursor = lcdfb_setcursor, #endif +#ifdef CONFIG_LCD_EXTERNINIT + /* Use external graphics driver initialization */ + + lcd = board_graphics_setup(display); + if (lcd == NULL) + { + gerr("ERROR: board_graphics_setup failed, devno=%d\n", display); + return EXIT_FAILURE; + } +#else /* Initialize the LCD device */ ret = board_lcd_initialize(); @@ -504,6 +524,7 @@ int up_fbinitialize(int display) ret = -ENODEV; goto errout_with_lcd; } +#endif priv->lcd = lcd; @@ -561,9 +582,11 @@ int up_fbinitialize(int display) return OK; errout_with_lcd: +#ifndef CONFIG_LCD_EXTERNINIT board_lcd_uninitialize(); errout_with_state: +#endif kmm_free(priv); return ret; } @@ -646,9 +669,11 @@ void up_fbuninitialize(int display) g_lcdfb = priv->flink; } +#ifndef CONFIG_LCD_EXTERNINIT /* Uninitialize the LCD */ board_lcd_uninitialize(); +#endif /* Free the frame buffer allocation */ @@ -666,7 +691,7 @@ void up_fbuninitialize(int display) * Name: nx_notify_rectangle * * Description: - * When CONFIG_NX_UPDATE=y, then the graphics system will callout to + * When CONFIG_LCD_UPDATE=y, then the graphics system will callout to * inform some external module that the display has been updated. This * would be useful in a couple for cases. * @@ -677,13 +702,17 @@ void up_fbuninitialize(int display) * - When VNC is enabled. This is case, this callout is necessary to * update the remote frame buffer to match the local framebuffer. * - * When this feature is enabled, some external logic must provide this - * interface. This is the function that will handle the notification. It - * receives the rectangular region that was updated on the provided plane. + * When this feature is enabled, some external logic must provide this + * interface. This is the function that will handle the notification. It + * receives the rectangular region that was updated on the provided plane. + * + * NOTE: This function is also required for use with the LCD framebuffer + * driver front end when CONFIG_LCD_UPDATE=y, although that use does not + * depend on CONFIG_NX (and this function seems misnamed in that case). * ****************************************************************************/ -#ifdef CONFIG_NX_UPDATE +#if defined(CONFIG_LCD_UPDATE) || defined(CONFIG_NX_UPDATE) void nx_notify_rectangle(FAR NX_PLANEINFOTYPE *pinfo, FAR const struct nxgl_rect_s *rect) { @@ -706,4 +735,4 @@ void nx_notify_rectangle(FAR NX_PLANEINFOTYPE *pinfo, } #endif -#endif /* CONFIG_LCD_FRAMEBUFFER */ \ No newline at end of file +#endif /* CONFIG_LCD_FRAMEBUFFER */ diff --git a/drivers/lcd/max7219.c b/drivers/lcd/max7219.c new file mode 100644 index 0000000000000000000000000000000000000000..3f3a39bc8346aadaf225f63a3715366025db29a5 --- /dev/null +++ b/drivers/lcd/max7219.c @@ -0,0 +1,913 @@ +/**************************************************************************** + * drivers/lcd/max7219.c + * Driver for the Maxim MAX7219 used for driver 8x8 LED display chains. + * + * Copyright (C) 2017 Alan Carvalho de Assis. All rights reserved. + * Author: Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ +/* MAX7219 Configuration Settings: + * + * CONFIG_MAX7219_NHORIZONTALBLKS - Specifies the number of physical + * MAX7219 devices that are connected together horizontally. + * + * CONFIG_MAX7219_NVERTICALBLKS - Specifies the number of physical + * MAX7219 devices that are connected together vertically. + * + * CONFIG_LCD_INTENSITY - Defines the default bright of LEDs. + * + * Required LCD driver settings: + * CONFIG_LCD_MAX7219 - Enable MAX7219 support + * + */ + +/* Verify that all configuration requirements have been met */ + +/* SPI frequency */ + +#ifndef CONFIG_MAX7219_FREQUENCY +# define CONFIG_MAX7219_FREQUENCY 10000000 +#endif + +/* MAX7219_NHORIZONTALBLKS determines the number of physical 8x8 LEDs + * matrices that are used connected horizontally. + */ + +#ifndef CONFIG_MAX7219_NHORIZONTALBLKS +# define CONFIG_MAX7219_NHORIZONTALBLKS 1 +#endif + +/* MAX7219_NVERTICALBLKS determines the number of physical 8x8 LEDs + * matrices that are used connected vertically. + */ + +#ifndef CONFIG_MAX7219_NVERTICALBLKS +# define CONFIG_MAX7219_NVERTICALBLKS 1 +#endif + +#if CONFIG_LCD_MAXCONTRAST > 15 +# undef CONFIG_LCD_MAXCONTRAST +# define CONFIG_LCD_MAXCONTRAST 15 +#endif + +/* Color Properties *********************************************************/ +/* The MAX7219 chip can handle resolution of 8x8, 16x8, 8x16, 16x16, 24x8, + * etc. + */ + +/* Display Resolution */ + +#define MAX7219_XRES (8 * CONFIG_MAX7219_NHORIZONTALBLKS) +#define MAX7219_YRES (8 * CONFIG_MAX7219_NVERTICALBLKS) + +/* Color depth and format */ + +#define MAX7219_BPP 1 +#define MAX7219_COLORFMT FB_FMT_Y1 + +/* Bytes per logical row and actual device row */ + +#define MAX7219_XSTRIDE (MAX7219_XRES >> 3) /* Pixels arrange "horizontally for user" */ +#define MAX7219_YSTRIDE (MAX7219_YRES >> 3) /* Pixels arrange "vertically for user" */ + +/* The size of the shadow frame buffer */ + +#define MAX7219_FBSIZE (MAX7219_XRES * MAX7219_YSTRIDE) + 1 + +/* Bit helpers */ + +#define LS_BIT (1 << 0) +#define MS_BIT (1 << 7) + +#define BIT(nr) (1 << (nr)) +#define BITS_PER_BYTE 8 +#define BIT_MASK(nr) (1 << ((nr) % BITS_PER_BYTE)) +#define BIT_BYTE(nr) ((nr) / BITS_PER_BYTE) + +/**************************************************************************** + * Private Type Definition + ****************************************************************************/ + +/* This structure describes the state of this driver */ + +struct max7219_dev_s +{ + /* Publically visible device structure */ + + struct lcd_dev_s dev; + + /* Private LCD-specific information follows */ + + FAR struct spi_dev_s *spi; + uint8_t contrast; + uint8_t powered; + + /* The MAX7219 does not support reading from the display memory in SPI mode. + * Since there is 1 BPP and access is byte-by-byte, it is necessary to keep + * a shadow copy of the framebuffer memory. + */ + + uint8_t fb[MAX7219_FBSIZE]; +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* SPI helpers */ + +static void max7219_select(FAR struct spi_dev_s *spi); +static void max7219_deselect(FAR struct spi_dev_s *spi); + +/* LCD Data Transfer Methods */ + +static int max7219_putrun(fb_coord_t row, fb_coord_t col, + FAR const uint8_t *buffer, size_t npixels); +static int max7219_getrun(fb_coord_t row, fb_coord_t col, + FAR uint8_t *buffer, size_t npixels); + +/* LCD Configuration */ + +static int max7219_getvideoinfo(FAR struct lcd_dev_s *dev, + FAR struct fb_videoinfo_s *vinfo); +static int max7219_getplaneinfo(FAR struct lcd_dev_s *dev, + unsigned int planeno, FAR struct lcd_planeinfo_s *pinfo); + +/* LCD RGB Mapping */ + +#ifdef CONFIG_FB_CMAP +# error "RGB color mapping not supported by this driver" +#endif + +/* Cursor Controls */ + +#ifdef CONFIG_FB_HWCURSOR +# error "Cursor control not supported by this driver" +#endif + +/* LCD Specific Controls */ + +static int max7219_getpower(FAR struct lcd_dev_s *dev); +static int max7219_setpower(FAR struct lcd_dev_s *dev, int power); +static int max7219_getcontrast(FAR struct lcd_dev_s *dev); +static int max7219_setcontrast(FAR struct lcd_dev_s *dev, + unsigned int contrast); + +/* Initialization */ + +static inline void up_clear(FAR struct max7219_dev_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is working memory allocated by the LCD driver for each LCD device + * and for each color plane. This memory will hold one raster line of data. + * The size of the allocated run buffer must therefore be at least + * (bpp * xres / 8). Actual alignment of the buffer must conform to the + * bitwidth of the underlying pixel type. + * + * If there are multiple planes, they may share the same working buffer + * because different planes will not be operate on concurrently. However, + * if there are multiple LCD devices, they must each have unique run buffers. + */ + +static uint8_t g_runbuffer[MAX7219_XSTRIDE + 1]; + +/* This structure describes the overall LCD video controller */ + +static const struct fb_videoinfo_s g_videoinfo = +{ + MAX7219_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ + MAX7219_XRES, /* Horizontal resolution in pixel columns */ + MAX7219_YRES, /* Vertical resolution in pixel rows */ + 1, /* Number of color planes supported */ +}; + +/* This is the standard, NuttX Plane information object */ + +static const struct lcd_planeinfo_s g_planeinfo = +{ + max7219_putrun, /* Put a run into LCD memory */ + max7219_getrun, /* Get a run from LCD memory */ + (FAR uint8_t *)g_runbuffer, /* Run scratch buffer */ + MAX7219_BPP, /* Bits-per-pixel */ +}; + +/* This is the standard, NuttX LCD driver object */ + +static struct max7219_dev_s g_max7219dev = +{ + /* struct lcd_dev_s */ + { + /* LCD Configuration */ + + max7219_getvideoinfo, + max7219_getplaneinfo, + +#ifdef CONFIG_FB_CMAP + /* LCD RGB Mapping -- Not supported */ + + NULL, + NULL, +#endif + +#ifdef CONFIG_FB_HWCURSOR + /* Cursor Controls -- Not supported */ + + NULL, + NULL, +#endif + + /* LCD Specific Controls */ + + max7219_getpower, + max7219_setpower, + max7219_getcontrast, + max7219_setcontrast, + }, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * __set_bit - Set a bit in memory + * + * nr - The bit to set + * addr - The address to start counting from + * + * Unlike set_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + * + ****************************************************************************/ + +static inline void __set_bit(int nr, uint8_t * addr) +{ + uint8_t mask = BIT_MASK(nr); + uint8_t *p = ((uint8_t *) addr) + BIT_BYTE(nr); + *p |= mask; +} + +static inline void __clear_bit(int nr, uint8_t * addr) +{ + uint8_t mask = BIT_MASK(nr); + uint8_t *p = ((uint8_t *) addr) + BIT_BYTE(nr); + *p &= ~mask; +} + +static inline int __test_bit(int nr, const volatile uint8_t * addr) +{ + return 1 & (addr[BIT_BYTE(nr)] >> (nr & (BITS_PER_BYTE - 1))); +} + +/**************************************************************************** + * Name: max7219_powerstring + * + * Description: + * Convert the power setting to a string. + * + ****************************************************************************/ + +static inline FAR const char *max7219_powerstring(uint8_t power) +{ + if (power == MAX7219_POWER_OFF) + { + return "OFF"; + } + else if (power == MAX7219_POWER_ON) + { + return "ON"; + } + else + { + return "ERROR"; + } +} + +/**************************************************************************** + * Name: max7219_select + * + * Description: + * Select the SPI, locking and re-configuring if necessary + * + * Parameters: + * spi - Reference to the SPI driver structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void max7219_select(FAR struct spi_dev_s *spi) +{ + /* Select MAX7219 chip (locking the SPI bus in case there are multiple + * devices competing for the SPI bus + */ + + SPI_LOCK(spi, true); + SPI_SELECT(spi, SPIDEV_DISPLAY(0), true); + + /* Now make sure that the SPI bus is configured for the MAX7219 (it + * might have gotten configured for a different device while unlocked) + */ + + SPI_SETMODE(spi, SPIDEV_MODE0); + SPI_SETBITS(spi, 8); + (void)SPI_HWFEATURES(spi, 0); + (void)SPI_SETFREQUENCY(spi, CONFIG_MAX7219_FREQUENCY); +} + +/**************************************************************************** + * Name: max7219_deselect + * + * Description: + * De-select the SPI + * + * Parameters: + * spi - Reference to the SPI driver structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void max7219_deselect(FAR struct spi_dev_s *spi) +{ + /* De-select MAX7219 chip and relinquish the SPI bus. */ + + SPI_SELECT(spi, SPIDEV_DISPLAY(0), false); + SPI_LOCK(spi, false); +} + +/**************************************************************************** + * Name: max7219_putrun + * + * Description: + * This method can be used to write a partial raster line to the LCD: + * + * row - Starting row to write to (range: 0 <= row < yres) + * col - Starting column to write to (range: 0 <= col <= xres-npixels) + * buffer - The buffer containing the run to be written to the LCD + * npixels - The number of pixels to write to the LCD + * (range: 0 < npixels <= xres-col) + * + ****************************************************************************/ + +static int max7219_putrun(fb_coord_t row, fb_coord_t col, + FAR const uint8_t *buffer, size_t npixels) +{ + /* Because of this line of code, we will only be able to support a single + * MAX7219 device . + */ + + FAR struct max7219_dev_s *priv = &g_max7219dev; + FAR uint8_t *fbptr; + FAR uint8_t *ptr; + uint16_t data; + uint8_t usrmask; + int i; + int pixlen; + int newrow; + + ginfo("row: %d col: %d npixels: %d\n", row, col, npixels); + DEBUGASSERT(buffer); + + /* Clip the run to the display */ + + pixlen = npixels; + if ((unsigned int)col + (unsigned int)pixlen > (unsigned int)MAX7219_XRES) + { + pixlen = (int)MAX7219_XRES - (int)col; + } + + /* Verify that some portion of the run remains on the display */ + + if (pixlen <= 0 || row > MAX7219_YRES) + { + return OK; + } + + /* Get real row position in the strip */ + + newrow = (int) (row % 8); + + /* Divide row by 8 */ + + row = (row >> 3); + + col = col + (row * MAX7219_XRES); + + row = newrow; + +#ifdef CONFIG_LCD_PACKEDMSFIRST + usrmask = MS_BIT; +#else + usrmask = LS_BIT; +#endif + +#ifdef CONFIG_LCD_PACKEDMSFIRST + usrmask = MS_BIT; +#else + usrmask = LS_BIT; +#endif + + fbptr = &priv->fb[row * MAX7219_XSTRIDE * MAX7219_YSTRIDE]; + ptr = fbptr + (col >> 3); + + for (i = 0; i < pixlen; i++) + { + if ((*buffer & usrmask) != 0) + { + __set_bit(col % 8 + i, ptr); + } + else + { + __clear_bit(col % 8 + i, ptr); + } + +#ifdef CONFIG_LCD_PACKEDMSFIRST + if (usrmask == LS_BIT) + { + buffer++; + usrmask = MS_BIT; + } + else + { + usrmask >>= 1; + } +#else + if (usrmask == MS_BIT) + { + buffer++; + usrmask = LS_BIT; + } + else + { + usrmask <<= 1; + } +#endif + } + + /* Lock and select the device */ + + max7219_select(priv->spi); + + /* We need to send last row/column first to avoid mirror image */ + + for (i = (MAX7219_XSTRIDE * MAX7219_YSTRIDE) - 1; i >= 0; i--) + { + /* Setup the row data */ + + data = (8 - row) | (*(fbptr + i) << 8); + + /* Then transfer all 8 columns of data */ + + (void)SPI_SNDBLOCK(priv->spi, &data, 2); + } + + /* Unlock */ + + max7219_deselect(priv->spi); + + return OK; +} + +/**************************************************************************** + * Name: max7219_getrun + * + * Description: + * This method can be used to read a partial raster line from the LCD: + * + * row - Starting row to read from (range: 0 <= row < yres) + * col - Starting column to read read (range: 0 <= col <= xres-npixels) + * buffer - The buffer in which to return the run read from the LCD + * npixels - The number of pixels to read from the LCD + * (range: 0 < npixels <= xres-col) + * + ****************************************************************************/ + +static int max7219_getrun(fb_coord_t row, fb_coord_t col, + FAR uint8_t *buffer, size_t npixels) +{ + /* Because of this line of code, we will only be able to support a single + * MAX7219 device. + */ + + FAR struct max7219_dev_s *priv = &g_max7219dev; + FAR uint8_t *fbptr; + FAR uint8_t *ptr; + uint8_t usrmask; + int i; + int pixlen; + + ginfo("row: %d col: %d npixels: %d\n", row, col, npixels); + DEBUGASSERT(buffer); + + /* Clip the run to the display */ + + pixlen = npixels; + if ((unsigned int)col + (unsigned int)pixlen > (unsigned int)MAX7219_XRES) + { + pixlen = (int)MAX7219_XRES - (int)col; + } + + /* Verify that some portion of the run is actually the display */ + + if (pixlen <= 0 || row > MAX7219_YRES) + { + return -EINVAL; + } + +#ifdef CONFIG_LCD_PACKEDMSFIRST + usrmask = MS_BIT; +#else + usrmask = LS_BIT; +#endif + + fbptr = &priv->fb[row * MAX7219_XSTRIDE]; + ptr = fbptr + (col >> 3); + + for (i = 0; i < pixlen; i++) + { + if (__test_bit(col % 8 + i, ptr)) + { + *buffer |= usrmask; + } + else + { + *buffer &= ~usrmask; + } + +#ifdef CONFIG_LCD_PACKEDMSFIRST + if (usrmask == LS_BIT) + { + buffer++; + usrmask = MS_BIT; + } + else + { + usrmask >>= 1; + } +#else + if (usrmask == MS_BIT) + { + buffer++; + usrmask = LS_BIT; + } + else + { + usrmask <<= 1; + } +#endif + } + + return OK; +} + +/**************************************************************************** + * Name: max7219_getvideoinfo + * + * Description: + * Get information about the LCD video controller configuration. + * + ****************************************************************************/ + +static int max7219_getvideoinfo(FAR struct lcd_dev_s *dev, + FAR struct fb_videoinfo_s *vinfo) +{ + DEBUGASSERT(dev && vinfo); + + ginfo("fmt: %d xres: %d yres: %d nplanes: %d\n", + g_videoinfo.fmt, g_videoinfo.xres, g_videoinfo.yres, + g_videoinfo.nplanes); + + memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); + return OK; +} + +/**************************************************************************** + * Name: max7219_getplaneinfo + * + * Description: + * Get information about the configuration of each LCD color plane. + * + ****************************************************************************/ + +static int max7219_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno, + FAR struct lcd_planeinfo_s *pinfo) +{ + DEBUGASSERT(dev && pinfo && planeno == 0); + + ginfo("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp); + + memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s)); + return OK; +} + +/**************************************************************************** + * Name: max7219_getpower + * + * Description: + * Get the LCD panel power status (0: full off - CONFIG_LCD_MAXPOWER: full + * on). On backlit LCDs, this setting may correspond to the backlight + * setting. + * + ****************************************************************************/ + +static int max7219_getpower(struct lcd_dev_s *dev) +{ + struct max7219_dev_s *priv = (struct max7219_dev_s *)dev; + + DEBUGASSERT(priv); + ginfo("powered: %s\n", max7219_powerstring(priv->powered)); + + return priv->powered; +} + +/**************************************************************************** + * Name: max7219_setpower + * + * Description: + * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: full on). On + * backlit LCDs, this setting may correspond to the backlight setting. + * + ****************************************************************************/ + +static int max7219_setpower(struct lcd_dev_s *dev, int power) +{ + struct max7219_dev_s *priv = (struct max7219_dev_s *)dev; + uint16_t data; + + DEBUGASSERT(priv && (unsigned)power <= CONFIG_LCD_MAXPOWER); + ginfo("power: %s powered: %s\n", + max7219_powerstring(power), max7219_powerstring(priv->powered)); + + /* Select and lock the device */ + + max7219_select(priv->spi); + + if (power <= MAX7219_POWER_OFF) + { + data = (MAX7219_SHUTDOWN) | (MAX7219_POWER_OFF << 8); + + /* Turn the display off (power-down) */ + + (void)SPI_SNDBLOCK(priv->spi, &data, 2); + + priv->powered = MAX7219_POWER_OFF; + } + else + { + data = (MAX7219_SHUTDOWN) | (MAX7219_POWER_ON << 8); + + /* Leave the power-down */ + + (void)SPI_SNDBLOCK(priv->spi, &data, 2); + + priv->powered = MAX7219_POWER_ON; + } + + /* Let go of the SPI lock and de-select the device */ + + max7219_deselect(priv->spi); + return OK; +} + +/**************************************************************************** + * Name: max7219_getcontrast + * + * Description: + * Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static int max7219_getcontrast(struct lcd_dev_s *dev) +{ + struct max7219_dev_s *priv = (struct max7219_dev_s *)dev; + + DEBUGASSERT(priv); + return (int)priv->contrast; +} + +/**************************************************************************** + * Name: max7219_setcontrast + * + * Description: + * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static int max7219_setcontrast(struct lcd_dev_s *dev, unsigned int contrast) +{ + struct max7219_dev_s *priv = (struct max7219_dev_s *)dev; + uint16_t data; + + ginfo("contrast: %d\n", contrast); + DEBUGASSERT(priv); + + if (contrast > 15) + { + return -EINVAL; + } + + /* Save the contrast */ + + priv->contrast = contrast; + + /* Select and lock the device */ + + max7219_select(priv->spi); + + /* Configure the contrast/intensity */ + + data = (MAX7219_INTENSITY) | (DISPLAY_INTENSITY(contrast) << 8); + + /* Set the contrast */ + + (void)SPI_SNDBLOCK(priv->spi, &data, 2); + + /* Let go of the SPI lock and de-select the device */ + + max7219_deselect(priv->spi); + return OK; +} + +/**************************************************************************** + * Name: up_clear + * + * Description: + * Clear the display. + * + ****************************************************************************/ + +static inline void up_clear(FAR struct max7219_dev_s *priv) +{ + FAR struct spi_dev_s *spi = priv->spi; + uint16_t data; + int row; + int i; + + /* Clear the framebuffer */ + + memset(priv->fb, MAX7219_BLACK, MAX7219_FBSIZE); + + /* Go throw max7219 all 8 rows */ + + for (row = 0, i = 0; i < 8; i++) + { + /* Select and lock the device */ + + max7219_select(priv->spi); + + /* Setup the row data */ + + data = (row + 1) | (priv->fb[row] << 8); + + /* Then transfer all 8 columns of data */ + + (void)SPI_SNDBLOCK(priv->spi, &data, 2); + + /* Unlock and de-select the device */ + + max7219_deselect(spi); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: max7219_initialize + * + * Description: + * Initialize the MAX7219 device as a LCD interface. + * + * Input Parameters: + * spi - An instance of the SPI interface to use to communicate + * with the MAX7219. + * devno - Device number to identify current display. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +FAR struct lcd_dev_s *max7219_initialize(FAR struct spi_dev_s *spi, + unsigned int devno) +{ + /* Configure and enable LCD */ + + FAR struct max7219_dev_s *priv = &g_max7219dev; + uint16_t data; + + ginfo("Initializing\n"); + DEBUGASSERT(spi && devno == 0); + + /* Save the reference to the SPI device */ + + priv->spi = spi; + + /* Select and lock the device */ + + max7219_select(spi); + + /* Leave the shutdown mode */ + + data = (MAX7219_SHUTDOWN) | (MAX7219_POWER_ON << 8); + + (void)SPI_SNDBLOCK(priv->spi, &data, 2); + + max7219_deselect(spi); + + max7219_select(spi); + + /* Disable 7 segment decoding */ + + data = (MAX7219_DECODE_MODE) | (DISABLE_DECODE << 8); + + (void)SPI_SNDBLOCK(priv->spi, &data, 2); + + max7219_deselect(spi); + + max7219_select(spi); + + /* Set scan limit for all digits */ + + data = (MAX7219_SCAN_LIMIT) | (DEFAULT_SCAN_LIMIT << 8); + + (void)SPI_SNDBLOCK(priv->spi, &data, 2); + + max7219_deselect(spi); + + max7219_select(spi); + + /* Set intensity level configured by the user */ + + data = (MAX7219_INTENSITY) | (DISPLAY_INTENSITY(CONFIG_LCD_MAXCONTRAST) << 8); + + (void)SPI_SNDBLOCK(priv->spi, &data, 2); + + /* Let go of the SPI lock and de-select the device */ + + max7219_deselect(spi); + + /* Clear the framebuffer */ + + up_clear(priv); + return &priv->dev; +} diff --git a/drivers/lcd/memlcd.c b/drivers/lcd/memlcd.c index 7cd379ca5b033028369e506987b0f9837a42e78f..f5c2917ad89138d3d6b785f8d4a59c06ba1bbe70 100644 --- a/drivers/lcd/memlcd.c +++ b/drivers/lcd/memlcd.c @@ -419,7 +419,7 @@ static int memlcd_putrun(fb_coord_t row, fb_coord_t col, DEBUGASSERT(buffer); lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST usrmask = MS_BIT; #else usrmask = LS_BIT; @@ -438,7 +438,7 @@ static int memlcd_putrun(fb_coord_t row, fb_coord_t col, __clear_bit(col % 8 + i, p); } -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST if (usrmask == LS_BIT) { buffer++; @@ -510,7 +510,7 @@ static int memlcd_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t * buffer, DEBUGASSERT(buffer); lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST usrmask = MS_BIT; #else usrmask = LS_BIT; @@ -529,7 +529,7 @@ static int memlcd_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t * buffer, *buffer &= ~usrmask; } -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST if (usrmask == LS_BIT) { buffer++; diff --git a/drivers/lcd/nokia6100.c b/drivers/lcd/nokia6100.c index cc28e027f74b915b6b468f874a9932bb959b74e1..ae28409347dbb5370a4b5ad7df72fa33adae3333 100644 --- a/drivers/lcd/nokia6100.c +++ b/drivers/lcd/nokia6100.c @@ -138,20 +138,6 @@ # endif #endif -#if CONFIG_NOKIA6100_BPP == 8 -# ifdef CONFIG_NX_DISABLE_8BPP -# warning "8-bit pixel support needed" -# endif -#elif CONFIG_NOKIA6100_BPP == 12 -# if defined(CONFIG_NX_DISABLE_12BPP) || !defined(CONFIG_NX_PACKEDMSFIRST) -# warning "12-bit, big-endian pixel support needed" -# endif -#elif CONFIG_NOKIA6100_BPP == 16 -# ifdef CONFIG_NX_DISABLE_16BPP -# warning "16-bit pixel support needed" -# endif -#endif - /* Exactly one LCD controller must be selected. "The Olimex boards have both display * controllers possible; if the LCD has a GE-12 sticker on it, it’s a Philips PCF8833. * If it has a GE-8 sticker, it’s an Epson controller." diff --git a/drivers/lcd/p14201.c b/drivers/lcd/p14201.c index 4461502c4fbd5fe90a7450e3463d2d2ddc1fc337..87f48d94b728f75b6dee85022e4788f7d81c7d99 100644 --- a/drivers/lcd/p14201.c +++ b/drivers/lcd/p14201.c @@ -135,12 +135,6 @@ # define CONFIG_LCD_MAXPOWER 1 #endif -/* Color is 4bpp greyscale with leftmost column contained in bits 7:4 */ - -#if defined(CONFIG_NX_DISABLE_4BPP) || !defined(CONFIG_NX_PACKEDMSFIRST) -# warning "4-bit, big-endian pixel support needed" -#endif - /* Define the CONFIG_LCD_RITDEBUG to enable detailed debug output (stuff you would * never want to see unless you are debugging this file). * diff --git a/drivers/lcd/pcd8544.c b/drivers/lcd/pcd8544.c index c5d3c86fa1c5453f1fe9d6a349d0b79481c52f0a..b3818792da4bfd261f3e140e07739d373f575b3f 100644 --- a/drivers/lcd/pcd8544.c +++ b/drivers/lcd/pcd8544.c @@ -156,12 +156,6 @@ # error "CONFIG_SPI_CMDDATA must be defined in your NuttX configuration" #endif -/* Color is 1bpp monochrome with leftmost column contained in bits 0 */ - -#ifdef CONFIG_NX_DISABLE_1BPP -# warning "1 bit-per-pixel support needed" -#endif - /* Color Properties *******************************************************************/ /* The PCD8544 display controller can handle a resolution of 84x48. */ @@ -503,7 +497,7 @@ static int pcd8544_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buf fbmask = 1 << (row & 7); fbptr = &priv->fb[page * PCD8544_XRES + col]; ptr = fbptr; -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST usrmask = MS_BIT; #else usrmask = LS_BIT; @@ -524,7 +518,7 @@ static int pcd8544_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buf /* Inc/Decrement to the next source pixel */ -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST if (usrmask == LS_BIT) { buffer++; @@ -650,7 +644,7 @@ static int pcd8544_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, fbmask = 1 << (row & 7); fbptr = &priv->fb[page * PCD8544_XRES + col]; -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST usrmask = MS_BIT; #else usrmask = LS_BIT; @@ -672,7 +666,7 @@ static int pcd8544_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, * this! */ -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST if (usrmask == LS_BIT) { buffer++; diff --git a/drivers/lcd/ssd1306_base.c b/drivers/lcd/ssd1306_base.c index 536cbbb67e7c79993beb80d0afd78b4c621fd34c..9c3817f6067f5c9cbb73846455aaaa94c83ccc5c 100644 --- a/drivers/lcd/ssd1306_base.c +++ b/drivers/lcd/ssd1306_base.c @@ -361,7 +361,7 @@ static int ssd1306_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buf ptr = fbptr; #endif -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST usrmask = MS_BIT; #else usrmask = LS_BIT; @@ -393,7 +393,7 @@ static int ssd1306_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buf /* Inc/Decrement to the next source pixel */ -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST if (usrmask == LS_BIT) { buffer++; @@ -564,7 +564,7 @@ static int ssd1306_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, fbmask = 1 << (row & 7); fbptr = &priv->fb[page * SSD1306_DEV_XRES + col]; -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST usrmask = MS_BIT; #else usrmask = LS_BIT; @@ -590,7 +590,7 @@ static int ssd1306_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, /* Inc/Decrement to the next destination pixel. */ -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST if (usrmask == LS_BIT) { buffer++; diff --git a/drivers/lcd/ssd1351.c b/drivers/lcd/ssd1351.c index 791040eee5d5d74e9cef1a3a1ff609864f488f46..6c375e012e4a353cadf40ad6aa10ac39e9d13419 100644 --- a/drivers/lcd/ssd1351.c +++ b/drivers/lcd/ssd1351.c @@ -100,19 +100,8 @@ * CONFIG_SPI - enables support for SPI * CONFIG_SPI_CMDDATA - enables support for cmd/data selection * (if using 4-wire SPI) - * - * NX settings that must be undefined: - * CONFIG_NX_DISABLE_16BPP - disables 16 bpp support */ -/* Verify that all configuration requirements have been met */ - -/* Number of bits per pixel */ - -#ifdef CONFIG_NX_DISABLE_16BPP -# error "Requires support for 16 bits per pixel" -#endif - /* Max power */ #if CONFIG_LCD_MAXPOWER != 1 diff --git a/drivers/lcd/st7565.c b/drivers/lcd/st7565.c index d25583a74520866032a1edadc4e3fb14764dc326..3ae17f199c2a338eb716c1057dd5293251c499d7 100644 --- a/drivers/lcd/st7565.c +++ b/drivers/lcd/st7565.c @@ -128,14 +128,6 @@ # warning "Optimal setting of CONFIG_LCD_MAXCONTRAST is 255" #endif -/* Check power setting */ - -/* Color is 1bpp monochrome with leftmost column contained in bits 0 */ - -#ifdef CONFIG_NX_DISABLE_1BPP -# warning "1 bit-per-pixel support needed" -#endif - /* Color Properties *******************************************************************/ /* The ST7565 display controller can handle a resolution of 128x64. @@ -515,7 +507,7 @@ static int st7565_putrun(fb_coord_t row, fb_coord_t col, fbmask = 1 << (row & 7); fbptr = &priv->fb[page * ST7565_XRES + col]; ptr = fbptr; -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST usrmask = MS_BIT; #else usrmask = LS_BIT; @@ -536,7 +528,7 @@ static int st7565_putrun(fb_coord_t row, fb_coord_t col, /* Inc/Decrement to the next source pixel */ -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST if (usrmask == LS_BIT) { buffer++; @@ -667,7 +659,7 @@ static int st7565_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t * buffer, fbmask = 1 << (row & 7); fbptr = &priv->fb[page * ST7565_XRES + col]; -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST usrmask = MS_BIT; #else usrmask = LS_BIT; @@ -688,7 +680,7 @@ static int st7565_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t * buffer, * logic could write past the end of the user buffer. Revisit this! */ -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST if (usrmask == LS_BIT) { buffer++; diff --git a/drivers/lcd/st7567.c b/drivers/lcd/st7567.c index 5de10bb7c3d6c7a86114af42767e394f2974e1c4..14f732fe5ddc505c0edc540955dbe6f576c776c7 100644 --- a/drivers/lcd/st7567.c +++ b/drivers/lcd/st7567.c @@ -164,12 +164,6 @@ # error "CONFIG_SPI_CMDDATA must be defined in your NuttX configuration" #endif -/* Color is 1bpp monochrome with leftmost column contained in bits 0 */ - -#ifdef CONFIG_NX_DISABLE_1BPP -# warning "1 bit-per-pixel support needed" -#endif - /* Color Properties *******************************************************************/ /* The ST7567 display controller can handle a resolution of 128x64. */ @@ -480,7 +474,7 @@ static int st7567_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buff fbmask = 1 << (row & 7); fbptr = &priv->fb[page * ST7567_XRES + col]; ptr = fbptr; -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST usrmask = MS_BIT; #else usrmask = LS_BIT; @@ -501,7 +495,7 @@ static int st7567_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buff /* Inc/Decrement to the next source pixel */ -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST if (usrmask == LS_BIT) { buffer++; @@ -628,7 +622,7 @@ static int st7567_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, fbmask = 1 << (row & 7); fbptr = &priv->fb[page * ST7567_XRES + col]; -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST usrmask = MS_BIT; #else usrmask = LS_BIT; @@ -650,7 +644,7 @@ static int st7567_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, * this! */ -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST if (usrmask == LS_BIT) { buffer++; diff --git a/drivers/lcd/ug-2864ambag01.c b/drivers/lcd/ug-2864ambag01.c index 1e6484f2561792e58ac2b99eb763672e404a5bc5..b1633d1e2be1172bef68fd29f82373b9ad2ce56b 100644 --- a/drivers/lcd/ug-2864ambag01.c +++ b/drivers/lcd/ug-2864ambag01.c @@ -558,7 +558,7 @@ static int ug2864ambag01_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_ ptr = fbptr; #endif -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST usrmask = MS_BIT; #else usrmask = LS_BIT; @@ -590,7 +590,7 @@ static int ug2864ambag01_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_ /* Inc/Decrement to the next source pixel */ -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST if (usrmask == LS_BIT) { buffer++; @@ -763,7 +763,7 @@ static int ug2864ambag01_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buf fbmask = 1 << (row & 7); fbptr = &priv->fb[page * UG2864AMBAG01_XRES + col]; -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST usrmask = MS_BIT; #else usrmask = LS_BIT; @@ -789,7 +789,7 @@ static int ug2864ambag01_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buf * this! */ -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST if (usrmask == LS_BIT) { buffer++; diff --git a/drivers/lcd/ug-9664hswag01.c b/drivers/lcd/ug-9664hswag01.c index 96d09aea9991a680cc5b5f9b72145ccc9e3edf4e..d644ec03840768899a72dead90ecb63903afbaf0 100644 --- a/drivers/lcd/ug-9664hswag01.c +++ b/drivers/lcd/ug-9664hswag01.c @@ -155,12 +155,6 @@ # error "CONFIG_SPI_CMDDATA must be defined in your NuttX configuration" #endif -/* Color is 1bpp monochrome with leftmost column contained in bits 0 */ - -#ifdef CONFIG_NX_DISABLE_1BPP -# warning "1 bit-per-pixel support needed" -#endif - /* Color Properties *******************************************************************/ /* The SSD1305 display controller can handle a resolution of 132x64. The OLED * on the base board is 96x64. @@ -547,7 +541,7 @@ static int ug_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffer, ptr = fbptr; #endif -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST usrmask = MS_BIT; #else usrmask = LS_BIT; @@ -579,7 +573,7 @@ static int ug_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffer, /* Inc/Decrement to the next source pixel */ -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST if (usrmask == LS_BIT) { buffer++; @@ -739,7 +733,7 @@ static int ug_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, fbmask = 1 << (row & 7); fbptr = &priv->fb[page * UG_XRES + col]; -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST usrmask = MS_BIT; #else usrmask = LS_BIT; @@ -766,7 +760,7 @@ static int ug_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, * this! */ -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_LCD_PACKEDMSFIRST if (usrmask == LS_BIT) { buffer++; diff --git a/drivers/loop/loop.c b/drivers/loop/loop.c index 19cd75d62cf194da9a66baae79d32b319a534105..4fa9bd18ce590c37435e9cbc65af9be4ea98763e 100644 --- a/drivers/loop/loop.c +++ b/drivers/loop/loop.c @@ -93,7 +93,8 @@ static ssize_t loop_read(FAR struct file *filep, FAR char *buffer, size_t len) * Name: loop_write ****************************************************************************/ -static ssize_t loop_write(FAR struct file *filep, FAR const char *buffer, size_t len) +static ssize_t loop_write(FAR struct file *filep, FAR const char *buffer, + size_t len) { return len; /* Say that everything was written */ } @@ -125,7 +126,7 @@ static int loop_ioctl(FAR struct file *filep, int cmd, unsigned long arg) else { ret = losetup(setup->devname, setup->filename, setup->sectsize, - setup->offset, setup->readonly); + setup->offset, setup->readonly); } } break; diff --git a/drivers/loop/losetup.c b/drivers/loop/losetup.c index e62c7860415c791a843b7defffc1c494b96e9cde..32c2f4d4374ac00b4e134492fcc4273e2a713c41 100644 --- a/drivers/loop/losetup.c +++ b/drivers/loop/losetup.c @@ -82,7 +82,7 @@ struct loop_struct_s #ifdef CONFIG_FS_WRITABLE bool writeenabled; /* true: can write to device */ #endif - int fd; /* Descriptor of char device/file */ + struct file devfile; /* File struct of char device/file */ }; /**************************************************************************** @@ -143,7 +143,7 @@ static int loop_semtake(FAR struct loop_struct_s *dev) * awakened by a signal. */ - DEBUGASSERT(ret == -EINTR); + DEBUGASSERT(ret == OK || ret == -EINTR); return ret; } @@ -241,17 +241,18 @@ static ssize_t loop_read(FAR struct inode *inode, FAR unsigned char *buffer, if (start_sector + nsectors > dev->nsectors) { - _err("ERROR: Read past end of file\n"); + ferr("ERROR: Read past end of file\n"); return -EIO; } /* Calculate the offset to read the sectors and seek to the position */ offset = start_sector * dev->sectsize + dev->offset; - ret = lseek(dev->fd, offset, SEEK_SET); + ret = file_seek(&dev->devfile, offset, SEEK_SET); if (ret == (off_t)-1) { - _err("ERROR: Seek failed for offset=%d: %d\n", (int)offset, get_errno()); + ferr("ERROR: Seek failed for offset=%d: %d\n", + (int)offset, get_errno()); return -EIO; } @@ -259,10 +260,11 @@ static ssize_t loop_read(FAR struct inode *inode, FAR unsigned char *buffer, do { - nbytesread = nx_read(dev->fd, buffer, nsectors * dev->sectsize); + nbytesread = file_read(&dev->devfile, buffer, + nsectors * dev->sectsize); if (nbytesread < 0 && nbytesread != -EINTR) { - _err("ERROR: Read failed: %d\n", nbytesread); + ferr("ERROR: Read failed: %d\n", nbytesread); return (int)nbytesread; } } @@ -296,10 +298,10 @@ static ssize_t loop_write(FAR struct inode *inode, /* Calculate the offset to write the sectors and seek to the position */ offset = start_sector * dev->sectsize + dev->offset; - ret = lseek(dev->fd, offset, SEEK_SET); + ret = file_seek(&dev->devfile, offset, SEEK_SET); if (ret == (off_t)-1) { - _err("ERROR: Seek failed for offset=%d: %d\n", + ferr("ERROR: Seek failed for offset=%d: %d\n", (int)offset, get_errno()); } @@ -307,10 +309,11 @@ static ssize_t loop_write(FAR struct inode *inode, do { - nbyteswritten = nx_write(dev->fd, buffer, nsectors * dev->sectsize); + nbyteswritten = file_write(&dev->devfile, buffer, + nsectors * dev->sectsize); if (nbyteswritten < 0 && nbyteswritten != -EINTR) { - _err("ERROR: nx_write failed: %d\n", nbyteswritten); + ferr("ERROR: nx_write failed: %d\n", nbyteswritten); return nbyteswritten; } } @@ -372,11 +375,12 @@ int losetup(FAR const char *devname, FAR const char *filename, FAR struct loop_struct_s *dev; struct stat sb; int ret; + int fd = -1; /* Sanity check */ #ifdef CONFIG_DEBUG_FEATURES - if (!devname || !filename || !sectsize) + if (devname == NULL || filename == NULL || sectsize == 0) { return -EINVAL; } @@ -387,7 +391,7 @@ int losetup(FAR const char *devname, FAR const char *filename, ret = stat(filename, &sb); if (ret < 0) { - _err("ERROR: Failed to stat %s: %d\n", filename, get_errno()); + ferr("ERROR: Failed to stat %s: %d\n", filename, get_errno()); return -get_errno(); } @@ -395,14 +399,15 @@ int losetup(FAR const char *devname, FAR const char *filename, if (sb.st_size - offset < sectsize) { - _err("ERROR: File is too small for blocksize\n"); + ferr("ERROR: File is too small for blocksize\n"); return -ERANGE; } /* Allocate a loop device structure */ - dev = (FAR struct loop_struct_s *)kmm_zalloc(sizeof(struct loop_struct_s)); - if (!dev) + dev = (FAR struct loop_struct_s *) + kmm_zalloc(sizeof(struct loop_struct_s)); + if (dev == NULL) { return -ENOMEM; } @@ -417,19 +422,16 @@ int losetup(FAR const char *devname, FAR const char *filename, /* Open the file. */ #ifdef CONFIG_FS_WRITABLE - dev->writeenabled = false; /* Assume failure */ - dev->fd = -1; - /* First try to open the device R/W access (unless we are asked * to open it readonly). */ if (!readonly) { - dev->fd = open(filename, O_RDWR); + fd = open(filename, O_RDWR); } - if (dev->fd >= 0) + if (fd >= 0) { dev->writeenabled = true; /* Success */ } @@ -438,28 +440,39 @@ int losetup(FAR const char *devname, FAR const char *filename, { /* If that fails, then try to open the device read-only */ - dev->fd = open(filename, O_RDWR); - if (dev->fd < 0) + fd = open(filename, O_RDWR); + if (fd < 0) { - _err("ERROR: Failed to open %s: %d\n", filename, get_errno()); ret = -get_errno(); + ferr("ERROR: Failed to open %s: %d\n", filename, ret); goto errout_with_dev; } } + /* Detach the file from the file descriptor */ + + ret = file_detach(fd, &dev->devfile); + if (ret < 0) + { + ferr("ERROR: Failed to open %s: %d\n", filename, ret); + close(fd); + goto errout_with_dev; + } + /* Inode private data will be reference to the loop device structure */ ret = register_blockdriver(devname, &g_bops, 0, dev); if (ret < 0) { ferr("ERROR: register_blockdriver failed: %d\n", -ret); - goto errout_with_fd; + goto errout_with_file; } return OK; -errout_with_fd: - close(dev->fd); +errout_with_file: + file_close_detached(&dev->devfile); + errout_with_dev: kmm_free(dev); return ret; @@ -482,7 +495,7 @@ int loteardown(FAR const char *devname) /* Sanity check */ #ifdef CONFIG_DEBUG_FEATURES - if (!devname) + if (devname == NULL) { return -EINVAL; } @@ -495,7 +508,7 @@ int loteardown(FAR const char *devname) ret = open_blockdriver(devname, MS_RDONLY, &inode); if (ret < 0) { - _err("ERROR: Failed to open %s: %d\n", devname, -ret); + ferr("ERROR: Failed to open %s: %d\n", devname, -ret); return ret; } @@ -504,7 +517,7 @@ int loteardown(FAR const char *devname) dev = (FAR struct loop_struct_s *)inode->i_private; close_blockdriver(inode); - DEBUGASSERT(dev); + DEBUGASSERT(dev != NULL); /* Are there still open references to the device */ @@ -519,9 +532,9 @@ int loteardown(FAR const char *devname) /* Release the device structure */ - if (dev->fd >= 0) + if (dev->devfile.f_inode != NULL) { - (void)close(dev->fd); + (void)file_close_detached(&dev->devfile); } kmm_free(dev); diff --git a/drivers/mmcsd/Kconfig b/drivers/mmcsd/Kconfig index 4d4485e0d40db5549f38816f03044ad5a20a1d9a..74a11d0b0275e618ca07d7675f2883f06e6d9065 100755 --- a/drivers/mmcsd/Kconfig +++ b/drivers/mmcsd/Kconfig @@ -31,12 +31,17 @@ config MMCSD_MMCSUPPORT ---help--- Enable support for MMC cards -config MMCSD_HAVECARDDETECT - bool "MMC/SD card detection" +config MMCSD_HAVE_CARDDETECT + bool "MMC/SD card detect pin" default y ---help--- - SDIO driver card detection is - 100% accurate + SDIO driver card present detection is supported. + +config MMCSD_HAVE_WRITEPROTECT + bool "MMC/SD write protect pin" + default y + ---help--- + SDIO driver write protection detection is supported. config MMCSD_SPI bool "MMC/SD SPI transfer support" diff --git a/drivers/mmcsd/mmcsd_sdio.c b/drivers/mmcsd/mmcsd_sdio.c index b1b87c27e35e3fd8bffa4044fa71630c45692b99..3d89028701010345b3e1c48a1ba48659df40af4c 100644 --- a/drivers/mmcsd/mmcsd_sdio.c +++ b/drivers/mmcsd/mmcsd_sdio.c @@ -3011,7 +3011,7 @@ static int mmcsd_probe(FAR struct mmcsd_state_s *priv) * else */ -#ifdef CONFIG_MMCSD_HAVECARDDETECT +#ifdef CONFIG_MMCSD_HAVE_CARDDETECT if (priv->probed && SDIO_PRESENT(priv->dev)) { return OK; @@ -3038,7 +3038,7 @@ static int mmcsd_probe(FAR struct mmcsd_state_s *priv) if (ret != OK) { ferr("ERROR: Failed to initialize card: %d\n", ret); -#ifdef CONFIG_MMCSD_HAVECARDDETECT +#ifdef CONFIG_MMCSD_HAVE_CARDDETECT SDIO_CALLBACKENABLE(priv->dev, SDIOMEDIA_INSERTED); #endif } @@ -3075,7 +3075,7 @@ static int mmcsd_probe(FAR struct mmcsd_state_s *priv) finfo("Capacity: %lu Kbytes\n", (unsigned long)(priv->capacity / 1024)); priv->mediachanged = true; -#ifdef CONFIG_MMCSD_HAVECARDDETECT +#ifdef CONFIG_MMCSD_HAVE_CARDDETECT /* Set up to receive asynchronous, media removal events */ SDIO_CALLBACKENABLE(priv->dev, SDIOMEDIA_EJECTED); @@ -3096,7 +3096,7 @@ static int mmcsd_probe(FAR struct mmcsd_state_s *priv) /* There is no card in the slot */ finfo("No card\n"); -#ifdef CONFIG_MMCSD_HAVECARDDETECT +#ifdef CONFIG_MMCSD_HAVE_CARDDETECT SDIO_CALLBACKENABLE(priv->dev, SDIOMEDIA_INSERTED); #endif ret = -ENODEV; diff --git a/drivers/mmcsd/mmcsd_sdio.h b/drivers/mmcsd/mmcsd_sdio.h index 900c40b7b15e4421b0cd403ae4ff649bea21cc1d..d7a3f1d0c9ddd74ad13adaf0ede4ff593c096da8 100644 --- a/drivers/mmcsd/mmcsd_sdio.h +++ b/drivers/mmcsd/mmcsd_sdio.h @@ -324,7 +324,8 @@ struct mmcsd_scr_s #undef EXTERN #if defined(__cplusplus) #define EXTERN extern "C" -extern "C" { +extern "C" +{ #else #define EXTERN extern #endif diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index da4a934832113db694656d01975de5a22ad2d400..78bdefd9168da3c2977f2758c79891ee2ca2eeca 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -497,6 +497,27 @@ config MX25L_DEBUG endif # MTD_MX25L +config MTD_MX35 + bool "SPI-based MX35LF1GE4AB / MX35LF2GE4AB" + default n + select SPI + ---help--- + SPI-based driver for Macronix MX35LF1GE4AB or MX35LF2GE4AB. + +if MTD_MX35 + +config MX35_SPIMODE + int "MX35 SPI mode" + default 0 + +config MX35_SPIFREQUENCY + int "MX35 SPI Frequency" + default 104000000 + ---help--- + SPI frequency for MX35 is 104 MHz. + +endif # MTD_MX35 + config MTD_S25FL1 bool "QuadSPI-based S25FL1 FLASH" default n diff --git a/drivers/mtd/Make.defs b/drivers/mtd/Make.defs index 8ed31c7b9b227b02f66a4784f9299e577f7fde6c..9deab1955166554bd2f5d90809e80dda59e89bba 100644 --- a/drivers/mtd/Make.defs +++ b/drivers/mtd/Make.defs @@ -120,6 +120,10 @@ ifeq ($(CONFIG_MTD_MX25L),y) CSRCS += mx25lx.c endif +ifeq ($(CONFIG_MTD_MX35),y) +CSRCS += mx35.c +endif + ifeq ($(CONFIG_MTD_S25FL1),y) CSRCS += s25fl1.c endif diff --git a/drivers/mtd/filemtd.c b/drivers/mtd/filemtd.c index a5d3d68de5625510e009e87760f254f10bb4b1c4..d1ca98e2caf7b599a43076edc5d7973b623fc137 100644 --- a/drivers/mtd/filemtd.c +++ b/drivers/mtd/filemtd.c @@ -97,7 +97,7 @@ struct file_dev_s { struct mtd_dev_s mtd; /* MTD device */ - int fd; /* File descriptor of underlying file */ + struct file mtdfile; size_t nblocks; /* Number of erase blocks */ size_t offset; /* Offset from start of file */ size_t erasesize; /* Offset from start of file */ @@ -161,8 +161,8 @@ static ssize_t filemtd_write(FAR struct file_dev_s *priv, size_t offset, { /* Read more data from the file */ - lseek(priv->fd, seekpos, SEEK_SET); - buflen = nx_read(priv->fd, buf, sizeof(buf)); + file_seek(&priv->mtdfile, seekpos, SEEK_SET); + buflen = file_read(&priv->mtdfile, buf, sizeof(buf)); pout = (FAR uint8_t *) buf; } @@ -204,8 +204,8 @@ static ssize_t filemtd_write(FAR struct file_dev_s *priv, size_t offset, if (buflen == 0) { - lseek(priv->fd, seekpos, SEEK_SET); - (void)nx_write(priv->fd, buf, sizeof(buf)); + file_seek(&priv->mtdfile, seekpos, SEEK_SET); + (void)file_write(&priv->mtdfile, buf, sizeof(buf)); seekpos += sizeof(buf); } } @@ -214,8 +214,8 @@ static ssize_t filemtd_write(FAR struct file_dev_s *priv, size_t offset, if (buflen != 0) { - lseek(priv->fd, seekpos, SEEK_SET); - (void)nx_write(priv->fd, buf, sizeof(buf)); + file_seek(&priv->mtdfile, seekpos, SEEK_SET); + (void)file_write(&priv->mtdfile, buf, sizeof(buf)); } return len; @@ -231,9 +231,9 @@ static ssize_t filemtd_read(FAR struct file_dev_s *priv, { /* Set the starting location in the file */ - (void)lseek(priv->fd, priv->offset + offsetbytes, SEEK_SET); + (void)file_seek(&priv->mtdfile, priv->offset + offsetbytes, SEEK_SET); - return nx_read(priv->fd, buffer, nbytes); + return file_read(&priv->mtdfile, buffer, nbytes); } /**************************************************************************** @@ -278,11 +278,11 @@ static int filemtd_erase(FAR struct mtd_dev_s *dev, off_t startblock, /* Then erase the data in the file */ - lseek(priv->fd, priv->offset + offset, SEEK_SET); + file_seek(&priv->mtdfile, priv->offset + offset, SEEK_SET); memset(buffer, CONFIG_FILEMTD_ERASESTATE, sizeof(buffer)); while (nbytes) { - (void)nx_write(priv->fd, buffer, sizeof(buffer)); + (void)file_write(&priv->mtdfile, buffer, sizeof(buffer)); nbytes -= sizeof(buffer); } @@ -492,7 +492,9 @@ FAR struct mtd_dev_s *blockmtd_initialize(FAR const char *path, size_t offset, { FAR struct file_dev_s *priv; size_t nblocks; - int mode; + int mode; + int ret; + int fd; /* Create an instance of the FILE MTD device state structure */ @@ -514,14 +516,25 @@ FAR struct mtd_dev_s *blockmtd_initialize(FAR const char *path, size_t offset, * driver proxy. */ - priv->fd = open(path, mode); - if (priv->fd == -1) + fd = open(path, mode); + if (fd <0) { ferr("ERROR: Failed to open the FILE MTD file %s\n", path); kmm_free(priv); return NULL; } + /* Detach the file descriptor from the open file */ + + ret = file_detach(fd, &priv->mtdfile); + if (ret < 0) + { + ferr("ERROR: Failed to detail the FILE MTD file %s\n", path); + close(fd); + kmm_free(priv); + return NULL; + } + /* Set the block size based on the provided sectsize parameter */ if (sectsize <= 0) @@ -550,6 +563,7 @@ FAR struct mtd_dev_s *blockmtd_initialize(FAR const char *path, size_t offset, if (nblocks < 3) { ferr("ERROR: Need to provide at least three full erase block\n"); + file_close_detached(&priv->mtdfile); kmm_free(priv); return NULL; } @@ -596,7 +610,7 @@ void blockmtd_teardown(FAR struct mtd_dev_s *dev) /* Close the enclosed file */ priv = (FAR struct file_dev_s *) dev; - close(priv->fd); + file_close_detached(&priv->mtdfile); #ifdef CONFIG_MTD_REGISTRATION /* Un-register the MTD with the procfs system if enabled */ diff --git a/drivers/mtd/mtd_progmem.c b/drivers/mtd/mtd_progmem.c index 9785a4c3607095ebc702b8f8db65ddc32df1a818..d46bed5ac5b483cae161e0423198635d9fe7d4fe 100644 --- a/drivers/mtd/mtd_progmem.c +++ b/drivers/mtd/mtd_progmem.c @@ -49,9 +49,7 @@ #include #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ +#ifdef CONFIG_ARCH_HAVE_PROGMEM /**************************************************************************** * Private Types @@ -102,6 +100,7 @@ static int progmem_ioctl(FAR struct mtd_dev_s *dev, int cmd, /**************************************************************************** * Private Data ****************************************************************************/ + /* This structure holds the state of the MTD driver */ static struct progmem_dev_s g_progmem = @@ -411,3 +410,5 @@ FAR struct mtd_dev_s *progmem_initialize(void) return (FAR struct mtd_dev_s *)priv; } + +#endif /* CONFIG_ARCH_HAVE_PROGMEM */ diff --git a/drivers/mtd/mx35.c b/drivers/mtd/mx35.c new file mode 100644 index 0000000000000000000000000000000000000000..862e54410627be59dcd950e731b6dc7d4bb06886 --- /dev/null +++ b/drivers/mtd/mx35.c @@ -0,0 +1,958 @@ +/************************************************************************************ + * drivers/mtd/mx35.c + * Driver for SPI-based MX35LFxGE4AB parts of 1 or 2GBit. + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Ekaterina Kovylova + * + * Copied from / based on mx25lx.c driver written by + * Aleksandr Vyhovanec + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration ********************************************************************/ +/* Per the data sheet, MX35 parts can be driven with either SPI mode 0 (CPOL=0 and + * CPHA=0) or mode 3 (CPOL=1 and CPHA=1). If CONFIG_MX35_SPIMODE is not defined, + * mode 0 will be used. + */ + +#ifndef CONFIG_MX35_SPIMODE +# define CONFIG_MX35_SPIMODE SPIDEV_MODE0 +#endif + +#ifndef CONFIG_MX35_SPIFREQUENCY +# define CONFIG_MX35_SPIFREQUENCY 104000000 +#endif + +#ifndef CONFIG_MX35_MANUFACTURER +# define CONFIG_MX35_MANUFACTURER 0xC2 +#endif + +/* Debug ****************************************************************************/ + +#ifdef CONFIG_MX35_DEBUG +# define mx35err(format, ...) _err(format, ##__VA_ARGS__) +# define mx35info(format, ...) _info(format, ##__VA_ARGS__) +#else +# define mx35err(x...) +# define mx35info(x...) +#endif + +/* Indentification register values **************************************************/ + +#define MX35_MANUFACTURER CONFIG_MX35_MANUFACTURER +#define MX35_MX35LF1GE4AB_CAPACITY 0x12 /* 1 Gb */ +#define MX35_MX35LF2GE4AB_CAPACITY 0x22 /* 2 Gb */ + +/* Chip Geometries ******************************************************************/ + +/* MX35LF1GE4AB capacity is 1 G-bit */ + +#define MX35_MX35LF1GE4AB_SECTOR_SHIFT 17 /* Sector size 1 << 17 = 128 Kb */ +#define MX35_MX35LF1GE4AB_NSECTORS 1024 +#define MX35_MX35LF1GE4AB_PAGE_SHIFT 11 /* Page size 1 << 11 = 2 Kb */ + +/* MX35LF2GE4AB capacity is 2 G-bit */ + +#define MX35_MX35LF2GE4AB_SECTOR_SHIFT 17 /* Sector size 1 << 17 = 128 Kb */ +#define MX35_MX35LF2GE4AB_NSECTORS 2048 +#define MX35_MX35LF2GE4AB_PAGE_SHIFT 11 /* Page size 1 << 11 = 2 Kb */ + +/* MX35 Instructions ****************************************************************/ +/* Command Value Description Addr Data */ +/* Dummy */ +#define MX35_GET_FEATURE 0x0F /* Get features 1 0 1 */ +#define MX35_SET_FEATURE 0x1F /* Set features 1 0 1 */ +#define MX35_PAGE_READ 0x13 /* Array read 3 0 0 */ +#define MX35_READ_FROM_CACHE 0x03 /* Output cache data + on SO 2 1 1-2112 */ +#define MX35_READ_FROM_CACHE_X1 0x0B /* Output cache data + on SO 2 1 1-2112 */ +#define MX35_READ_FROM_CACHE_X2 0x3B /* Output cache data + on SI and SO 2 1 1-2112 */ +#define MX35_READ_FROM_CACHE_X4 0x6B /* Output cache data + on SI, SO, WP, HOLD 2 1 1-2112 */ +#define MX35_READ_ID 0x9F /* Read device ID 0 1 2 */ +#define MX35_ECC_STATUS_READ 0x7C /* Internal ECC status + output 0 1 1 */ +#define MX35_BLOCK_ERASE 0xD8 /* Block erase 3 0 0 */ +#define MX35_PROGRAM_EXECUTE 0x10 /* Enter block/page + address, execute 3 0 0 */ +#define MX35_PROGRAM_LOAD 0x02 /* Load program data with + cache reset first 2 0 1-2112 */ +#define MX35_PROGRAM_LOAD_RANDOM 0x84 /* Load program data + without cache reset 2 0 1-2112 */ +#define MX35_PROGRAM_LOAD_X4 0x32 /* Program load operation + with x4 data input 2 0 1-2112 */ +#define MX35_PROGRAM_LOAD_RANDOM_X4 0x34 /* Load random operation + with x4 data input 2 0 1-2112 */ +#define MX35_WRITE_ENABLE 0x06 /* 0 0 0 */ +#define MX35_WRITE_DISABLE 0x04 /* 0 0 0 */ +#define MX35_RESET 0xFF /* Reset the device 0 0 0 */ + +#define MX35_DUMMY 0x00 /* No Operation 0 0 0 */ + +/* Feature register *****************************************************************/ + +/* Register address */ + +#define MX35_SECURE_OTP 0xB0 +#define MX35_STATUS 0xC0 +#define MX35_BLOCK_PROTECTION 0xA0 + +/* Bit definitions */ + +/* Secure OTP (On-Time-Programmable) register*/ + +#define MX35_SOTP_QE (1 << 0) /* Bit 0: Quad Enable */ +#define MX35_SOTP_ECC (1 << 4) /* Bit 4: ECC enabled */ +#define MX35_SOTP_SOTP_EN (1 << 6) /* Bit 6: Secure OTP Enable */ +#define MX35_SOTP_SOTP_PROT (1 << 7) /* Bit 7: Secure OTP Protect */ + +/* Status register */ + +#define MX35_SR_OIP (1 << 0) /* Bit 0: Operation in progress */ +#define MX35_SR_WEL (1 << 1) /* Bit 1: Write enable latch */ +#define MX35_SR_E_FAIL (1 << 2) /* Bit 2: Erase fail */ +#define MX35_SR_P_FAIL (1 << 3) /* Bit 3: Program Fail */ +#define MX35_SR_ECC_S0 (1 << 4) /* Bit 4-5: ECC Status */ +#define MX35_SR_ECC_S1 (1 << 5) + +/* Block Protection register*/ + +#define MX35_BP_SP (1 << 0) /* Bit 0: Solid-protection (1Gb only) */ +#define MX35_BP_COMPL (1 << 1) /* Bit 1: Complementary (1Gb only) */ +#define MX35_BP_INV (1 << 2) /* Bit 2: Invert (1Gb only) */ +#define MX35_BP_BP0 (1 << 3) /* Bit 3: Block Protection 0 */ +#define MX35_BP_BP1 (1 << 4) /* Bit 4: Block Protection 1 */ +#define MX35_BP_BP2 (1 << 5) /* Bit 5: Block Protection 2 */ +#define MX35_BP_BPRWD (1 << 7) /* Bit 7: Block Protection Register + Write Disable */ + +/* ECC Status register */ + +#define MX35_FEATURE_ECC_MASK (0x03 << 4) +#define MX35_FEATURE_ECC_INCORRECTABLE (0x02 << 4) +#define MX35_FEATURE_ECC_OFFSET 4 +#define MX35_ECC_STATUS_MASK 0x0F +#define MX35_ECC_INCORRECTABLE 0x0F + +/************************************************************************************ + * Private Types + ************************************************************************************/ + +/* This type represents the state of the MTD device. The struct mtd_dev_s + * must appear at the beginning of the definition so that you can freely + * cast between pointers to struct mtd_dev_s and struct m25p_dev_s. + */ + +struct mx35_dev_s +{ + struct mtd_dev_s mtd; /* MTD interface */ + FAR struct spi_dev_s *dev; /* Saved SPI interface instance */ + uint8_t highCapacity; + uint8_t sectorshift; /* 17 */ + uint16_t nsectors; /* 1024 or 2048 */ + uint8_t pageshift; /* 11 */ + uint8_t eccstatus; /* Internal ECC status */ +}; + +/************************************************************************************ + * Private Function Prototypes + ************************************************************************************/ + +static inline void mx35_lock(FAR struct spi_dev_s *dev); +static inline void mx35_unlock(FAR struct spi_dev_s *dev); + +static int mx35_readid(FAR struct mx35_dev_s *priv); +static bool mx35_waitstatus(FAR struct mx35_dev_s *priv, uint8_t mask, + bool successif); +static inline void mx35_writeenable(struct mx35_dev_s *priv); +static inline void mx35_writedisable(struct mx35_dev_s *priv); +static inline uint32_t mx35_addresstorow(FAR struct mx35_dev_s *priv, + uint32_t address); +static inline uint32_t mx35_addresstocolumn(FAR struct mx35_dev_s *priv, + uint32_t address); + +static bool mx35_sectorerase(FAR struct mx35_dev_s *priv, off_t startsector); +static int mx35_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks); + +static void mx35_readbuffer(FAR struct mx35_dev_s *priv, uint32_t address, + uint8_t *buffer, size_t length); +static bool mx35_read_page(FAR struct mx35_dev_s *priv, uint32_t position); +static ssize_t mx35_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, + FAR uint8_t *buffer); + +static void mx35_write_to_cache(FAR struct mx35_dev_s *priv, uint32_t address, + const uint8_t *buffer, size_t length); +static bool mx35_execute_write(FAR struct mx35_dev_s *priv, uint32_t position); +static ssize_t mx35_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, + FAR const uint8_t *buffer); + +static int mx35_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg); +static inline void mx35_eccstatusread(struct mx35_dev_s *priv); +static inline void mx35_enableECC(struct mx35_dev_s *priv); +static inline void mx35_unlockblocks(struct mx35_dev_s *priv); + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: mx35_lock + ************************************************************************************/ + +static inline void mx35_lock(FAR struct spi_dev_s *dev) +{ + /* On SPI busses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the busses for a sequence of + * transfers. The bus should be locked before the chip is selected. + * + * This is a blocking call and will not return until we have exclusive access to + * the SPI buss. We will retain that exclusive access until the bus is unlocked. + */ + + (void)SPI_LOCK(dev, true); + + /* After locking the SPI bus, the we also need call the setfrequency, setbits, and + * setmode methods to make sure that the SPI is properly configured for the device. + * If the SPI buss is being shared, then it may have been left in an incompatible + * state. + */ + + SPI_SETMODE(dev, CONFIG_MX35_SPIMODE); + SPI_SETBITS(dev, 8); + (void)SPI_HWFEATURES(dev, 0); + (void)SPI_SETFREQUENCY(dev, CONFIG_MX35_SPIFREQUENCY); +} + +/************************************************************************************ + * Name: mx35_unlock + ************************************************************************************/ + +static inline void mx35_unlock(FAR struct spi_dev_s *dev) +{ + (void)SPI_LOCK(dev, false); +} + +/************************************************************************************ + * Name: m25p_readid + ************************************************************************************/ + +static int mx35_readid(struct mx35_dev_s *priv) +{ + uint16_t manufacturer; + uint16_t capacity; + + mx35info("priv: %p\n", priv); + + /* Lock the SPI bus, configure the bus, and select this FLASH part. */ + + mx35_lock(priv->dev); + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true); + + /* Send the "Read ID" command and read two ID bytes */ + + (void)SPI_SEND(priv->dev, MX35_READ_ID); + (void)SPI_SEND(priv->dev, MX35_DUMMY); + manufacturer = SPI_SEND(priv->dev, MX35_DUMMY); + capacity = SPI_SEND(priv->dev, MX35_DUMMY); + + /* Deselect the FLASH and unlock the bus */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), false); + mx35_unlock(priv->dev); + + mx35info("manufacturer: %02x capacity: %02x\n", + manufacturer, capacity); + + /* Check for a valid manufacturer */ + + if (manufacturer == MX35_MANUFACTURER) + { + /* Okay.. is it a FLASH capacity that we understand? */ + + if (capacity == MX35_MX35LF1GE4AB_CAPACITY) + { + /* Save the FLASH geometry */ + + priv->highCapacity = 0; + priv->sectorshift = MX35_MX35LF1GE4AB_SECTOR_SHIFT; + priv->nsectors = MX35_MX35LF1GE4AB_NSECTORS; + priv->pageshift = MX35_MX35LF1GE4AB_PAGE_SHIFT; + return OK; + } + else if (capacity == MX35_MX35LF2GE4AB_CAPACITY) + { + /* Save the FLASH geometry */ + + priv->highCapacity = 1; + priv->sectorshift = MX35_MX35LF2GE4AB_SECTOR_SHIFT; + priv->nsectors = MX35_MX35LF2GE4AB_NSECTORS; + priv->pageshift = MX35_MX35LF2GE4AB_PAGE_SHIFT; + return OK; + } + } + + return -ENODEV; +} + +/************************************************************************************ + * Name: mx35_waitstatus + ************************************************************************************/ + +static bool mx35_waitstatus(FAR struct mx35_dev_s *priv, uint8_t mask, bool successif) +{ + uint8_t status; + + /* Loop as long as the memory is busy with a write cycle */ + + do + { + /* Select this FLASH part */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true); + + /* Get feature command */ + + (void)SPI_SEND(priv->dev, MX35_GET_FEATURE); + (void)SPI_SEND(priv->dev, MX35_STATUS); + status = SPI_SEND(priv->dev, MX35_DUMMY); + + /* Deselect the FLASH */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), false); + + /* Given that writing could take up to few tens of milliseconds, and erasing + * could take more. The following short delay in the "busy" case will allow + * other peripherals to access the SPI bus. + */ + } + while (((status & MX35_SR_OIP) != 0) && (!usleep(1000))); + + mx35info("Complete\n"); + return successif ? ((status & mask) != 0) : ((status & mask) == 0); +} + +/************************************************************************************ + * Name: mx35_writeenable + ************************************************************************************/ + +static inline void mx35_writeenable(struct mx35_dev_s *priv) +{ + /* Select this FLASH part */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true); + + /* Send Write Enable command */ + + (void)SPI_SEND(priv->dev, MX35_WRITE_ENABLE); + + /* Deselect the FLASH */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), false); +} + +/************************************************************************************ + * Name: mx35_writedisable + ************************************************************************************/ + +static inline void mx35_writedisable(struct mx35_dev_s *priv) +{ + /* Select this FLASH part */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true); + + /* Send Write Enable command */ + + (void)SPI_SEND(priv->dev, MX35_WRITE_DISABLE); + + /* Deselect the FLASH */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), false); +} + +/************************************************************************************ + * Name: mx35_addresstorow + ************************************************************************************/ + +static inline uint32_t mx35_addresstorow(FAR struct mx35_dev_s *priv, + uint32_t address) +{ + /* Convert to page */ + + uint32_t row = address >> priv->pageshift; + + if (priv->highCapacity) + { + const uint32_t plane = (row >> (16 - 6)) & 0x40; + + /* Shift block address */ + + row = ((row & ~0x3F) << 1) | (row & 0x3F); + + /* Insert plane select bit */ + + row = row | plane; + } + + return row; +} + +/************************************************************************************ + * Name: mx35_addresstocolumn + ************************************************************************************/ + +static inline uint32_t mx35_addresstocolumn(FAR struct mx35_dev_s *priv, + uint32_t address) +{ + uint32_t column = address % (1 << priv->pageshift); + + if (priv->highCapacity) + { + /* Convert to page */ + + const uint32_t row = address >> priv->pageshift; + const uint32_t plane = (row >> (16 - 12)) & 0x1000; + + /* Insert plane select bit */ + + column = column | plane; + } + else + { + uint16_t wraplength = 0x00; + column |= (wraplength & 0xC000); + } + + return column; +} + +/************************************************************************************ + * Name: mx35_sectorerase (128K) + ************************************************************************************/ + +static bool mx35_sectorerase(FAR struct mx35_dev_s *priv, off_t startsector) +{ + off_t address = (off_t)startsector << priv->sectorshift; + const uint32_t block = mx35_addresstorow(priv, address); + + mx35info("sector: %08lx\n", (long)startsector); + + /* Send write enable instruction */ + + mx35_writeenable(priv); + + /* Select this FLASH part */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true); + + /* Send the Block Erase instruction */ + + (void)SPI_SEND(priv->dev, MX35_BLOCK_ERASE); + (void)SPI_SEND(priv->dev, (block >> 16) & 0xff); + (void)SPI_SEND(priv->dev, (block >> 8) & 0xff); + (void)SPI_SEND(priv->dev, block & 0xff); + + /* Deselect the FLASH */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), false); + + mx35info("Erased\n"); + return mx35_waitstatus(priv, MX35_SR_E_FAIL, false); +} + +/************************************************************************************ + * Name: mx35_erase + ************************************************************************************/ + +static int mx35_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks) +{ + FAR struct mx35_dev_s *priv = (FAR struct mx35_dev_s *)dev; + size_t blocksleft = nblocks; + + mx35info("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks); + + /* Lock access to the SPI bus until we complete the erase */ + + mx35_lock(priv->dev); + + /* Wait all operations complete */ + + mx35_waitstatus(priv, MX35_SR_OIP, false); + + while (blocksleft-- > 0) + { + mx35_sectorerase(priv, startblock); + startblock++; + } + + mx35_unlock(priv->dev); + return (int)nblocks; +} + +/************************************************************************************ + * Name: mx35_readbuffer + ************************************************************************************/ + +static void mx35_readbuffer(FAR struct mx35_dev_s *priv, uint32_t address, + uint8_t *buffer, size_t length) +{ + const uint16_t offset = mx35_addresstocolumn(priv, address); + + /* Select the FLASH */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true); + + (void)SPI_SEND(priv->dev, MX35_READ_FROM_CACHE); + + /* Send the address high byte first. */ + + (void)SPI_SEND(priv->dev, (offset >> 8) & 0xff); + (void)SPI_SEND(priv->dev, (offset) & 0xff); + + /* Send a dummy byte */ + + (void)SPI_SEND(priv->dev, MX35_DUMMY); + + /* Then read all of the requested bytes */ + + SPI_RECVBLOCK(priv->dev, buffer, length); + + /* Deselect the FLASH */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), false); +} + +/************************************************************************************ + * Name: mx35_read_page + ************************************************************************************/ + +static bool mx35_read_page(FAR struct mx35_dev_s *priv, uint32_t pageaddress) +{ + const uint32_t row = mx35_addresstorow(priv, pageaddress); + + /* Select this FLASH part */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true); + + /* Send the Read Page instruction */ + + (void)SPI_SEND(priv->dev, MX35_PAGE_READ); + (void)SPI_SEND(priv->dev, (row >> 16) & 0xff); + (void)SPI_SEND(priv->dev, (row >> 8) & 0xff); + (void)SPI_SEND(priv->dev, row & 0xff); + + /* Deselect the FLASH */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), false); + + mx35_waitstatus(priv, MX35_SR_OIP, false); + + mx35_eccstatusread(priv); + if ((priv->eccstatus & MX35_FEATURE_ECC_MASK) == MX35_FEATURE_ECC_INCORRECTABLE) + { + return false; + } + + return true; +} + +/************************************************************************************ + * Name: mx35_read + ************************************************************************************/ + +static ssize_t mx35_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, + FAR uint8_t *buffer) +{ + FAR struct mx35_dev_s *priv = (FAR struct mx35_dev_s *)dev; + size_t bytesleft = nbytes; + uint32_t position = offset; + + mx35info("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes); + + /* Lock the SPI bus and select this FLASH part */ + + mx35_lock(priv->dev); + + /* Wait all operations complete */ + + mx35_waitstatus(priv, MX35_SR_OIP, false); + + while(bytesleft) + { + const uint32_t pageaddress = (position >> priv->pageshift) << priv->pageshift; + const uint32_t spaceleft = pageaddress + (1 << priv->pageshift) - position; + const size_t chunklength = bytesleft < spaceleft ? bytesleft : spaceleft; + + if (!mx35_read_page(priv, pageaddress)) + { + break; + } + + mx35_readbuffer(priv, position, buffer, chunklength); + + position += chunklength; + buffer += chunklength; + bytesleft -= chunklength; + } + + + mx35_unlock(priv->dev); + + mx35info("return nbytes: %d\n", (int)(nbytes - bytesleft)); + return nbytes - bytesleft; +} + +/************************************************************************************ + * Name: mx35_write_to_cache + ************************************************************************************/ + +static void mx35_write_to_cache(FAR struct mx35_dev_s *priv, uint32_t address, + const uint8_t *buffer, size_t length) +{ + const uint16_t offset = mx35_addresstocolumn(priv, address); + + /* Select the FLASH */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true); + + /* Send the Program Load command */ + + (void)SPI_SEND(priv->dev, MX35_PROGRAM_LOAD); + + /* Send the address high byte first. */ + + (void)SPI_SEND(priv->dev, (offset >> 8) & 0xff); + (void)SPI_SEND(priv->dev, (offset) & 0xff); + + /* Send block of bytes */ + + SPI_SNDBLOCK(priv->dev, buffer, length); + + /* Deselect the FLASH */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), false); +} + +/************************************************************************************ + * Name: mx35_write_to_cache + ************************************************************************************/ + +static bool mx35_execute_write(FAR struct mx35_dev_s *priv, uint32_t pageaddress) +{ + const uint32_t row = mx35_addresstorow(priv, pageaddress); + + /* Select this FLASH part */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true); + + /* Send the Pragram Execute instruction */ + + (void)SPI_SEND(priv->dev, MX35_PROGRAM_EXECUTE); + (void)SPI_SEND(priv->dev, (row >> 16) & 0xff); + (void)SPI_SEND(priv->dev, (row >> 8) & 0xff); + (void)SPI_SEND(priv->dev, row & 0xff); + + /* Deselect the FLASH */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), false); + + return mx35_waitstatus(priv, MX35_SR_P_FAIL, false); +} + +/************************************************************************************ + * Name: mx35_write + ************************************************************************************/ + +static ssize_t mx35_write(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes, + FAR const uint8_t *buffer) +{ + FAR struct mx35_dev_s *priv = (FAR struct mx35_dev_s *)dev; + size_t bytesleft = nbytes; + uint32_t position = offset; + + mx35_lock(priv->dev); + + /* Wait all operations complete */ + + mx35_waitstatus(priv, MX35_SR_OIP, false); + + while(bytesleft) + { + const uint32_t pageaddress = (position >> priv->pageshift) << priv->pageshift; + const uint32_t spaceleft = pageaddress + (1 << priv->pageshift) - position; + const size_t chunklength = bytesleft < spaceleft ? bytesleft : spaceleft; + + mx35_writeenable(priv); + mx35_write_to_cache(priv, position, buffer, chunklength); + if (!mx35_execute_write(priv, pageaddress)) + { + continue; + } + + position += chunklength; + buffer += chunklength; + bytesleft -= chunklength; + } + + mx35_unlock(priv->dev); + + return nbytes - bytesleft; +} + +/************************************************************************************ + * Name: mx25l_ioctl + ************************************************************************************/ + +static int mx35_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg) +{ + FAR struct mx35_dev_s *priv = (FAR struct mx35_dev_s *)dev; + int ret = -EINVAL; /* Assume good command with bad parameters */ + + mx35info("cmd: %d \n", cmd); + + switch (cmd) + { + case MTDIOC_GEOMETRY: + { + FAR struct mtd_geometry_s *geo = + (FAR struct mtd_geometry_s *)((uintptr_t)arg); + if (geo) + { + /* Populate the geometry structure with information need to know + * the capacity and how to access the device. + * + * NOTE: that the device is treated as though it where just an array + * of fixed size blocks. That is most likely not true, but the client + * will expect the device logic to do whatever is necessary to make it + * appear so. + */ + + geo->blocksize = (1 << priv->pageshift); + geo->erasesize = (1 << priv->sectorshift); + geo->neraseblocks = priv->nsectors; + + ret = OK; + + mx35info("blocksize: %d erasesize: %d neraseblocks: %d\n", + geo->blocksize, geo->erasesize, geo->neraseblocks); + } + } + break; + + case MTDIOC_BULKERASE: + { + /* Erase the entire device */ + ret = mx35_erase(dev, 0, priv->nsectors); + } + break; + + case MTDIOC_ECCSTATUS: + { + uint8_t *result = (uint8_t *)arg; + *result = + (priv->eccstatus & MX35_FEATURE_ECC_MASK) >> MX35_FEATURE_ECC_OFFSET; + + ret = OK; + } + break; + + default: + ret = -ENOTTY; /* Bad command */ + break; + } + + mx35info("return %d\n", ret); + return ret; +} + +/************************************************************************************ + * Name: mx35_eccstatusread + ************************************************************************************/ + +static inline void mx35_eccstatusread(struct mx35_dev_s *priv) +{ + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true); + (void)SPI_SEND(priv->dev, MX35_GET_FEATURE); + (void)SPI_SEND(priv->dev, MX35_STATUS); + priv->eccstatus = SPI_SEND(priv->dev, MX35_DUMMY); + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), false); +} + +/************************************************************************************ + * Name: mx35_enableECC + ************************************************************************************/ + +static inline void mx35_enableECC(struct mx35_dev_s *priv) +{ + uint8_t secureOTP = MX35_SOTP_ECC; + + mx35_lock(priv->dev); + mx35_writeenable(priv); + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true); + (void)SPI_SEND(priv->dev, MX35_SET_FEATURE); + (void)SPI_SEND(priv->dev, MX35_SECURE_OTP); + (void)SPI_SEND(priv->dev, secureOTP); + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), false); + + mx35_writedisable(priv); + mx35_unlock(priv->dev); +} + +/************************************************************************************ + * Name: mx35_unlockblocks + ************************************************************************************/ + +static inline void mx35_unlockblocks(struct mx35_dev_s *priv) +{ + uint8_t blockprotection = 0x00; + + mx35_lock(priv->dev); + mx35_writeenable(priv); + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true); + (void)SPI_SEND(priv->dev, MX35_SET_FEATURE); + (void)SPI_SEND(priv->dev, MX35_BLOCK_PROTECTION); + (void)SPI_SEND(priv->dev, blockprotection); + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), false); + + mx35_writedisable(priv); + mx35_unlock(priv->dev); +} + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: mx35_initialize + * + * Description: + * Create an initialize MTD device instance. MTD devices are not registered + * in the file system, but are created as instances that can be bound to + * other functions (such as a block or character driver front end). + * + ************************************************************************************/ + +FAR struct mtd_dev_s *mx35_initialize(FAR struct spi_dev_s *dev) +{ + FAR struct mx35_dev_s *priv; + int ret; + + mx35info("dev: %p\n", dev); + + /* Allocate a state structure (we allocate the structure instead of using + * a fixed, static allocation so that we can handle multiple FLASH devices. + * The current implementation would handle only one FLASH part per SPI + * device (only because of the SPIDEV_FLASH(0) definition) and so would have + * to be extended to handle multiple FLASH parts on the same SPI bus. + */ + + priv = (FAR struct mx35_dev_s *)kmm_zalloc(sizeof(struct mx35_dev_s)); + if (priv) + { + /* Initialize the allocated structure. (unsupported methods were + * nullified by kmm_zalloc). + */ + + priv->mtd.erase = mx35_erase; + priv->mtd.read = mx35_read; + priv->mtd.write = mx35_write; + priv->mtd.ioctl = mx35_ioctl; + priv->dev = dev; + + /* Deselect the FLASH */ + + SPI_SELECT(dev, SPIDEV_FLASH(0), false); + + /* Reset the flash */ + + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true); + (void)SPI_SEND(priv->dev, MX35_RESET); + SPI_SELECT(priv->dev, SPIDEV_FLASH(0), false); + + /* Wait reset complete */ + + mx35_waitstatus(priv, MX35_SR_OIP, false); + + /* Identify the FLASH chip and get its capacity */ + + ret = mx35_readid(priv); + if (ret != OK) + { + /* Unrecognized! Discard all of that work we just did and return NULL */ + + mx35err("ERROR: Unrecognized\n"); + kmm_free(priv); + return NULL; + } + else + { + +#ifdef CONFIG_MTD_REGISTRATION + /* Register the MTD with the procfs system if enabled */ + + mtd_register(&priv->mtd, "mx35"); +#endif + } + + mx35_enableECC(priv); + mx35_unlockblocks(priv); + } + + /* Return the implementation-specific state structure as the MTD device */ + + mx35info("Return %p\n", priv); + return (FAR struct mtd_dev_s *)priv; +} diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index b976953331e4afada8cd7b63ceca04a5a3c3f7bb..eec94fdd506e002e26460e82bfb5ffb6997c5853 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -14,26 +14,6 @@ config NETDEV_LOOPBACK Add support for the local network loopback device, lo. if NETDEV_LOOPBACK - -choice - prompt "Work queue" - default LOOPBACK_LPWORK if SCHED_LPWORK - default LOOPBACK_HPWORK if !SCHED_LPWORK && SCHED_HPWORK - depends on SCHED_WORKQUEUE - ---help--- - Work queue support is required to use the loopback driver. If the - low priority work queue is available, then it should be used by the - loopback driver. - -config LOOPBACK_HPWORK - bool "High priority" - depends on SCHED_HPWORK - -config LOOPBACK_LPWORK - bool "Low priority" - depends on SCHED_LPWORK - -endchoice # Work queue endif # NETDEV_LOOPBACK config NETDEV_TELNET @@ -61,6 +41,14 @@ config TELNET_DUMPBUFFER default n depends on DEBUG_NET +config TELNET_CHARACTER_MODE + bool "Character mode" + default n + ---help--- + The Telnet daemon works in character mode. In this case, the deamon + will echo a character which telnet client sent. By default, it works + in line mode. + endif # NETDEV_TELNET config ARCH_HAVE_NETDEV_STATISTICS diff --git a/drivers/net/loopback.c b/drivers/net/loopback.c index 10e2408d09eff422a490704b1defff13246dba4c..9d051d684d7c21693cf02aa418180a243c79c94d 100644 --- a/drivers/net/loopback.c +++ b/drivers/net/loopback.c @@ -38,7 +38,6 @@ ****************************************************************************/ #include -#if defined(CONFIG_NET) && defined(CONFIG_NETDEV_LOOPBACK) #include #include @@ -63,6 +62,8 @@ # include #endif +#ifdef CONFIG_NETDEV_LOOPBACK + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -71,14 +72,6 @@ #if !defined(CONFIG_SCHED_WORKQUEUE) # error Worker thread support is required (CONFIG_SCHED_WORKQUEUE) -#else -# if defined(CONFIG_LOOPBACK_HPWORK) -# define LPBKWORK HPWORK -# elif defined(CONFIG_LOOPBACK_LPWORK) -# define LPBKWORK LPWORK -# else -# error Neither CONFIG_LOOPBACK_HPWORK nor CONFIG_LOOPBACK_LPWORK defined -# endif #endif /* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */ @@ -283,7 +276,7 @@ static void lo_poll_expiry(int argc, wdparm_t arg, ...) /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(LPBKWORK, &priv->lo_work, lo_poll_work, priv, 0); + work_queue(LPWORK, &priv->lo_work, lo_poll_work, priv, 0); } /**************************************************************************** @@ -429,7 +422,7 @@ static int lo_txavail(FAR struct net_driver_s *dev) { /* Schedule to serialize the poll on the worker thread. */ - work_queue(LPBKWORK, &priv->lo_work, lo_txavail_work, priv, 0); + work_queue(LPWORK, &priv->lo_work, lo_txavail_work, priv, 0); } return OK; @@ -558,4 +551,4 @@ int localhost_initialize(void) return lo_ifup(&priv->lo_dev); } -#endif /* CONFIG_NET && CONFIG_NETDEV_LOOPBACK */ +#endif /* CONFIG_NETDEV_LOOPBACK */ diff --git a/drivers/net/skeleton.c b/drivers/net/skeleton.c index 9a8c8a0a8ffe1a9d02c64d3db151a32733da5455..fb2d084b51f8cb6a7e094c2c2689560550aed71f 100644 --- a/drivers/net/skeleton.c +++ b/drivers/net/skeleton.c @@ -1,7 +1,7 @@ /**************************************************************************** * drivers/net/skeleton.c * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -38,7 +38,6 @@ ****************************************************************************/ #include -#if defined(CONFIG_NET) && defined(CONFIG_NET_skeleton) #include #include @@ -61,6 +60,8 @@ # include #endif +#ifdef CONFIG_NET_skeleton + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -71,16 +72,11 @@ # error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) #else - /* Use the selected work queue */ +/* The low priority work queue is preferred. If it is not enabled, LPWORK + * will be the same as HPWORK. + */ -# if defined(CONFIG_skeleton_HPWORK) -# define ETHWORK HPWORK -# elif defined(CONFIG_skeleton_LPWORK) -# define ETHWORK LPWORK -# else -# error Neither CONFIG_skeleton_HPWORK nor CONFIG_skeleton_LPWORK defined -# endif -#endif +#define ETHWORK LPWORK /* CONFIG_skeleton_NINTERFACES determines the number of physical interfaces * that will be supported. @@ -115,7 +111,7 @@ struct skel_driver_s bool sk_bifup; /* true:ifup false:ifdown */ WDOG_ID sk_txpoll; /* TX poll timer */ WDOG_ID sk_txtimeout; /* TX timeout timer */ - struct work_s sk_irqwork; /* For deferring interupt work to the work queue */ + struct work_s sk_irqwork; /* For deferring interrupt work to the work queue */ struct work_s sk_pollwork; /* For deferring poll work to the work queue */ /* This holds the information visible to the NuttX network */ @@ -127,17 +123,20 @@ struct skel_driver_s * Private Data ****************************************************************************/ -/* These statically allocated structur would mean that only a single +/* These statically allocated structures would mean that only a single * instance of the device could be supported. In order to support multiple * devices instances, this data would have to be allocated dynamically. */ -/* A single packet buffer per device is used here. There might be multiple - * packet buffers in a more complex, pipelined design. +/* A single packet buffer per device is used in this example. There might + * be multiple packet buffers in a more complex, pipelined design. Many + * contemporary Ethernet interfaces, for example, use multiple, linked DMA + * descriptors in rings to implement such a pipeline. This example assumes + * much simpler hardware that simply handles one packet at a time. * * NOTE that if CONFIG_skeleton_NINTERFACES were greater than 1, you would - * need a minimum on one packetbuffer per instance. Much better to be - * allocated dynamically. + * need a minimum on one packet buffer per instance. Much better to be + * allocated dynamically in cases where more than one are needed. */ static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; @@ -157,6 +156,7 @@ static int skel_txpoll(FAR struct net_driver_s *dev); /* Interrupt handling */ +static void skel_reply(struct skel_driver_s *priv) static void skel_receive(FAR struct skel_driver_s *priv); static void skel_txdone(FAR struct skel_driver_s *priv); @@ -192,7 +192,7 @@ static void skel_ipv6multicast(FAR struct skel_driver_s *priv); #endif #ifdef CONFIG_NETDEV_IOCTL static int skel_ioctl(FAR struct net_driver_s *dev, int cmd, - unsigned long arg); + unsigned long arg); #endif /**************************************************************************** @@ -213,8 +213,7 @@ static int skel_ioctl(FAR struct net_driver_s *dev, int cmd, * OK on success; a negated errno on failure * * Assumptions: - * May or may not be called from an interrupt handler. In either case, - * the network is locked. + * The network is locked. * ****************************************************************************/ @@ -259,8 +258,7 @@ static int skel_transmit(FAR struct skel_driver_s *priv) * OK on success; a negated errno on failure * * Assumptions: - * May or may not be called from an interrupt handler. In either case, - * the network is locked. + * The network is locked. * ****************************************************************************/ @@ -312,6 +310,63 @@ static int skel_txpoll(FAR struct net_driver_s *dev) return 0; } +/**************************************************************************** + * Name: skel_reply + * + * Description: + * After a packet has been received and dispatched to the network, it + * may return return with an outgoing packet. This function checks for + * that case and performs the transmission if necessary. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static void skel_reply(struct skel_driver_s *priv) +{ + /* If the packet dispatch resulted in data that should be sent out on the + * network, the field d_len will set to a value > 0. + */ + + if (priv->sk_dev.d_len > 0) + { + /* Update the Ethernet header with the correct MAC address */ + +#ifdef CONFIG_NET_IPv4 +#ifdef CONFIG_NET_IPv6 + /* Check for an outgoing IPv4 packet */ + + if (IFF_IS_IPv4(priv->sk_dev.d_flags)) +#endif + { + arp_out(&priv->sk_dev); + } +#endif + +#ifdef CONFIG_NET_IPv6 +#ifdef CONFIG_NET_IPv4 + /* Otherwise, it must be an outgoing IPv6 packet */ + + else +#endif + { + neighbor_out(&skel->sk_dev); + } +#endif + + /* And send the packet */ + + skel_transmit(priv); + } +} + /**************************************************************************** * Name: skel_receive * @@ -357,38 +412,16 @@ static void skel_receive(FAR struct skel_driver_s *priv) ninfo("IPv4 frame\n"); NETDEV_RXIPV4(&priv->sk_dev); - /* Handle ARP on input then give the IPv4 packet to the network - * layer + /* Handle ARP on input, then dispatch IPv4 packet to the network + * layer. */ arp_ipin(&priv->sk_dev); ipv4_input(&priv->sk_dev); - /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. - */ + /* Check for a reply to the IPv4 packet */ - if (priv->sk_dev.d_len > 0) - { - /* Update the Ethernet header with the correct MAC address */ - -#ifdef CONFIG_NET_IPv6 - if (IFF_IS_IPv4(priv->sk_dev.d_flags)) -#endif - { - arp_out(&priv->sk_dev); - } -#ifdef CONFIG_NET_IPv6 - else - { - neighbor_out(&kel->sk_dev); - } -#endif - - /* And send the packet */ - - skel_transmit(priv); - } + skel_reply(priv); } else #endif @@ -398,41 +431,21 @@ static void skel_receive(FAR struct skel_driver_s *priv) ninfo("Iv6 frame\n"); NETDEV_RXIPV6(&priv->sk_dev); - /* Give the IPv6 packet to the network layer */ + /* Dispatch IPv6 packet to the network layer */ ipv6_input(&priv->sk_dev); - /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. - */ - - if (priv->sk_dev.d_len > 0) - { - /* Update the Ethernet header with the correct MAC address */ + /* Check for a reply to the IPv6 packet */ -#ifdef CONFIG_NET_IPv4 - if (IFF_IS_IPv4(priv->sk_dev.d_flags)) - { - arp_out(&priv->sk_dev); - } - else -#endif -#ifdef CONFIG_NET_IPv6 - { - neighbor_out(&priv->sk_dev); - } -#endif - - /* And send the packet */ - - skel_transmit(priv); - } + skel_reply(priv); } else #endif #ifdef CONFIG_NET_ARP if (BUF->type == htons(ETHTYPE_ARP)) { + /* Dispatch ARP packet to the network layer */ + arp_arpin(&priv->sk_dev); NETDEV_RXARP(&priv->sk_dev); @@ -507,7 +520,7 @@ static void skel_txdone(FAR struct skel_driver_s *priv) * OK on success * * Assumptions: - * The network is locked. + * Runs on a worker thread. * ****************************************************************************/ @@ -560,6 +573,8 @@ static void skel_interrupt_work(FAR void *arg) * OK on success * * Assumptions: + * Runs in the context of a the Ethernet interrupt handler. Local + * interrupts are disabled by the interrupt logic. * ****************************************************************************/ @@ -605,9 +620,6 @@ static int skel_interrupt(int irq, FAR void *context, FAR void *arg) * Returned Value: * OK on success * - * Assumptions: - * The network is locked. - * ****************************************************************************/ static void skel_txtimeout_work(FAR void *arg) @@ -649,7 +661,8 @@ static void skel_txtimeout_work(FAR void *arg) * None * * Assumptions: - * Global interrupts are disabled by the watchdog logic. + * Runs in the context of a the timer interrupt handler. Local + * interrupts are disabled by the interrupt logic. * ****************************************************************************/ @@ -669,27 +682,6 @@ static void skel_txtimeout_expiry(int argc, wdparm_t arg, ...) work_queue(ETHWORK, &priv->sk_irqwork, skel_txtimeout_work, priv, 0); } -/**************************************************************************** - * Name: skel_poll_process - * - * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. - * - * Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static inline void skel_poll_process(FAR struct skel_driver_s *priv) -{ -} - /**************************************************************************** * Name: skel_poll_work * @@ -703,7 +695,7 @@ static inline void skel_poll_process(FAR struct skel_driver_s *priv) * OK on success * * Assumptions: - * The network is locked. + * Run on a work queue thread. * ****************************************************************************/ @@ -753,7 +745,8 @@ static void skel_poll_work(FAR void *arg) * None * * Assumptions: - * Global interrupts are disabled by the watchdog logic. + * Runs in the context of a the timer interrupt handler. Local + * interrupts are disabled by the interrupt logic. * ****************************************************************************/ @@ -780,6 +773,7 @@ static void skel_poll_expiry(int argc, wdparm_t arg, ...) * None * * Assumptions: + * The network is locked. * ****************************************************************************/ @@ -834,6 +828,7 @@ static int skel_ifup(FAR struct net_driver_s *dev) * None * * Assumptions: + * The network is locked. * ****************************************************************************/ @@ -877,7 +872,7 @@ static int skel_ifdown(FAR struct net_driver_s *dev) * None * * Assumptions: - * Called on the higher priority worker thread. + * Runs on a work queue thread. * ****************************************************************************/ @@ -922,7 +917,7 @@ static void skel_txavail_work(FAR void *arg) * None * * Assumptions: - * Called in normal user mode + * The network is locked. * ****************************************************************************/ @@ -1086,6 +1081,7 @@ static void skel_ipv6multicast(FAR struct skel_driver_s *priv) * OK on success; Negated errno on failure. * * Assumptions: + * The network is locked. * ****************************************************************************/ @@ -1129,6 +1125,7 @@ static int skel_ioctl(FAR struct net_driver_s *dev, int cmd, * OK on success; Negated errno on failure. * * Assumptions: + * Called early in initialization before multi-tasking is initiated. * ****************************************************************************/ @@ -1168,7 +1165,7 @@ int skel_initialize(int intf) #endif priv->sk_dev.d_private = (FAR void *)g_skel; /* Used to recover private state from dev */ - /* Create a watchdog for timing polling for and timing of transmisstions */ + /* Create a watchdog for timing polling for and timing of transmissions */ priv->sk_txpoll = wd_create(); /* Create periodic poll timer */ priv->sk_txtimeout = wd_create(); /* Create TX timeout timer */ @@ -1179,7 +1176,9 @@ int skel_initialize(int intf) * the device and/or calling skel_ifdown(). */ - /* Read the MAC address from the hardware into priv->sk_dev.d_mac.ether.ether_addr_octet */ + /* Read the MAC address from the hardware into priv->sk_dev.d_mac.ether.ether_addr_octet + * Applies only if the Ethernet MAC has its own internal address. + */ /* Register the device with the OS so that socket IOCTLs can be performed */ @@ -1187,4 +1186,4 @@ int skel_initialize(int intf) return OK; } -#endif /* CONFIG_NET && CONFIG_NET_skeleton */ +#endif /* CONFIG_NET_skeleton */ diff --git a/drivers/net/telnet.c b/drivers/net/telnet.c index 8ec933c9751f6195abdd11f225ea7cfa17594268..9dbded1e1ef940f1df335de2b14b5a9404d4cfbd 100644 --- a/drivers/net/telnet.c +++ b/drivers/net/telnet.c @@ -84,6 +84,9 @@ #define ISO_nl 0x0a #define ISO_cr 0x0d +#define TELNET_SGA 0x03 /* Suppress Go Ahead */ +#define TELNET_ECHO 0x01 + #define TELNET_IAC 255 #define TELNET_WILL 251 #define TELNET_WONT 252 @@ -251,9 +254,11 @@ static void telnet_getchar(FAR struct telnet_dev_s *priv, uint8_t ch, { register int index; +#ifndef CONFIG_TELNET_CHARACTER_MODE /* Ignore carriage returns */ if (ch != ISO_cr) +#endif { /* Add all other characters to the destination buffer */ @@ -334,9 +339,32 @@ static ssize_t telnet_receive(FAR struct telnet_dev_s *priv, FAR const char *src break; case STATE_DO: +#ifdef CONFIG_TELNET_CHARACTER_MODE + if (ch == TELNET_SGA) + { + /* If it received 'Suppress Go Ahead', reply with a WILL */ + + telnet_sendopt(priv, TELNET_WILL, ch); + + /* Also, send 'WILL ECHO' */ + + telnet_sendopt(priv, TELNET_WILL, TELNET_ECHO); + } + else if (ch == TELNET_ECHO) + { + /* If it received 'ECHO', then do nothing */ + } + else + { + /* Reply with a WONT */ + + telnet_sendopt(priv, TELNET_WONT, ch); + } +#else /* Reply with a WONT */ telnet_sendopt(priv, TELNET_WONT, ch); +#endif priv->td_state = STATE_NORMAL; break; diff --git a/drivers/pipes/pipe_common.c b/drivers/pipes/pipe_common.c index 03509461e356a5e265d1876b66bccb0c49e6411b..532e705671864363c9e8eb3c09f56a30be1effb5 100644 --- a/drivers/pipes/pipe_common.c +++ b/drivers/pipes/pipe_common.c @@ -704,7 +704,7 @@ int pipecommon_poll(FAR struct file *filep, FAR struct pollfd *fds, } else { - nbytes = (dev->d_bufsize - 1) + dev->d_wrndx - dev->d_rdndx; + nbytes = dev->d_bufsize + dev->d_wrndx - dev->d_rdndx; } /* Notify the POLLOUT event if the pipe is not full, but only if diff --git a/drivers/power/battery_charger.c b/drivers/power/battery_charger.c index aa5b0c0fa9c674d0f7d3a42a959093384beec48e..0bacbd90e3769331da1909aec9375fd13a315ef2 100644 --- a/drivers/power/battery_charger.c +++ b/drivers/power/battery_charger.c @@ -41,10 +41,10 @@ #include #include -#include #include #include +#include #include #include #include diff --git a/drivers/power/bq2429x.c b/drivers/power/bq2429x.c index 46bc65ebbb6d17e25747d13f5e8cf8eb0afb7a5d..218f6f4541cbf54bed5cc76beb57a7115b63b1cb 100644 --- a/drivers/power/bq2429x.c +++ b/drivers/power/bq2429x.c @@ -428,6 +428,27 @@ static int bq2429x_sysoff(FAR struct bq2429x_dev_s *priv) return ret; } +/**************************************************************************** + * Name: bq2429x_syson + * + * Description: + * Turn the internal battery FET on. + * + ****************************************************************************/ + +static int bq2429x_syson(FAR struct bq2429x_dev_s *priv) +{ + int ret; + uint8_t value = 0; + + ret = bq2429x_getreg8(priv, BQ2429X_REG07, &value, 1); + batdbg("REG7 read value: 0x%08X\n", value); + value &= ~BQ2429XR7_BATFET_DISABLE; + ret |= bq2429x_putreg8(priv, BQ2429X_REG07, value); + + return ret; +} + /**************************************************************************** * Name: bq2429x_en_term * @@ -947,15 +968,48 @@ static inline int bq2429x_setcurr(FAR struct bq2429x_dev_s *priv, { uint8_t regval; int ret, idx; + bool force_20pct = false; - /* Verify if voltage is in the acceptable range */ + /* If requested current is below the minimum for fast charge, + * configure for trickle charging. Trickle charging uses 20% + * of current programmed to ICHG bits, so we multiply by five. + */ + + if (req_current < BQ2429X_CURRCHG_MIN) + { + force_20pct = true; + req_current *= 5; + } + + /* Verify if current is in the acceptable range. */ if (req_current < BQ2429X_CURRCHG_MIN || req_current > BQ2429X_CURRCHG_MAX) { - baterr("ERROR: Current %d mA is out of range.\n", req_current); + baterr("ERROR: Current %d mA is out of range.\n", + force_20pct ? req_current / 5 : req_current); return -EINVAL; } + /* According to the "Termination when REG02[0] = 1" section of + * the bq24296M datasheet, the trickle charge could be less than + * the termination current so it is recommended to turn off the + * termination function. + * + * This means that the user will have to manually turn off the + * charging when in 20% mode. Otherwise there could be battery + * damage if we continuously trickle charge full battery until + * safety timer finally stops it after 10 hours (timer is running + * in half speed in 20% mode.) + */ + + ret = bq2429x_en_term(priv, !force_20pct); + if (ret < 0) + { + return ret; + } + + /* Read previous current and charge type. */ + ret = bq2429x_getreg8(priv, BQ2429X_REG02, ®val, 1); if (ret < 0) { @@ -963,16 +1017,25 @@ static inline int bq2429x_setcurr(FAR struct bq2429x_dev_s *priv, return ret; } - /* Current starts at _MIN mV and increases in steps of 64mA */ + /* Current starts at _MIN mA and increases in steps of 64mA. */ idx = req_current - BQ2429X_CURRCHG_MIN; idx = idx / 64; - /* Clear previous current and set new value */ + /* Clear previous current and charge type and set new values. */ regval &= ~(BQ2429XR2_ICHG_MASK); regval |= (idx << BQ2429XR2_ICHG_SHIFT); + if (force_20pct) + { + regval |= BQ2429XR2_FORCE_20PCT; + } + else + { + regval &= ~BQ2429XR2_FORCE_20PCT; + } + ret = bq2429x_putreg8(priv, BQ2429X_REG02, regval); if (ret < 0) { @@ -1061,12 +1124,13 @@ static int bq2429x_input_current(FAR struct battery_charger_dev_s *dev, * Name: bq2429x_operate * * Description: - * Do miscellaneous battery ioctl(). + * Do miscellaneous battery operation. There are numerous options that are + * configurable on the bq2429x that go beyond what the NuttX battery charger + * API provide access to. This operate() function allows changing some of them. * - * Set the battery charger current rate for charging * REG00 EN_HIZ - * REG01 BOOST - * REG01 CHARGE + * REG01[1] BOOST_LIM 1A/1.5A Default:1.5A + * REG01 CHG_CONFIG * REG02[1] BCOLD * REG02[1] FORCE_20PCT * REG05[1] EN_TERM Charging Termination Enable @@ -1080,14 +1144,13 @@ static int bq2429x_input_current(FAR struct battery_charger_dev_s *dev, * REG07[1] INT_MASK1 - Allow INT on CHRG_FAULT Default: 1 Allow * REG07[1] INT_MASK0 - Allow INT on BAT_FAULT Default: 1 Allow * - * _provision + * Set by other battery charger methods: * REG00[3] InputCurrent Limit 100mA 3000mA with PSEL - * REG01[1] BOOST_LIM 1A/1.5A Default:1.5A * REG02[1] ICHG Fast Charge Current Limit, 512-3008mA Default 2048mA * REG03[4] IPRECHG Pre-charge current Limit 128-2048mA Default: 128mA * REG03[3] ITERM Termination Current Limit 128-1024mA Default: 256mA * - * also System output voltage + * System output voltage related: * REG00[4] VINDPM 3.88-5.08V Default:4.36V * REG01[3] Min Sys Voltage Range3.0-3.7V * REG04[6] Charge Voltage Limit 3504-4400mV Default: 4208mV @@ -1107,25 +1170,6 @@ static int bq2429x_operate(FAR struct battery_charger_dev_s *dev, bq2429x_dump_regs(priv); -#if 0 - static bool wdg_disabled = 0; - - /* Tickle watchdog periodically or disable */ - - if (!wdg_disabled) - { - wdg_disabled = true; - bq2429x_reset(priv); - - ret = bq2429x_watchdog(priv, false); /* Disable */ - if (ret < 0) - { - baterr("ERROR: Failed to disable BQ2429x watchdog: %d\n", ret); - return ret; - } - } -#endif - op = msg->operate_type; value = (int)msg->u32; switch (op) @@ -1153,6 +1197,10 @@ static int bq2429x_operate(FAR struct battery_charger_dev_s *dev, ret = bq2429x_sysoff(priv); break; + case BATIO_OPRTN_SYSON: + ret = bq2429x_syson(priv); + break; + case BATIO_OPRTN_RESET: ret = bq2429x_reset(priv); break; diff --git a/drivers/power/smps.c b/drivers/power/smps.c index c17cdd5fe1123030db1ecb6b2f4454b08f4cd236..f019949d72503d73913299bb18c8b5c1c2358f9a 100644 --- a/drivers/power/smps.c +++ b/drivers/power/smps.c @@ -421,7 +421,7 @@ static int smps_ioctl(FAR struct file *filep, int cmd, unsigned long arg) if (smps->limits.v_out > 0 && params->v_out > smps->limits.v_out) { - pwrerr("ERROR: params->v_out > limits.v_out: %d > %d\n", + pwrerr("ERROR: params->v_out > limits.v_out: %.2f > %.2f\n", params->v_out, smps->limits.v_out); ret = -EPERM; @@ -432,7 +432,7 @@ static int smps_ioctl(FAR struct file *filep, int cmd, unsigned long arg) if (smps->limits.i_out > 0 && params->i_out > smps->limits.i_out) { - pwrerr("ERROR: params->i_out > limits.i_out: %d > %d\n", + pwrerr("ERROR: params->i_out > limits.i_out: %.2f > %.2f\n", params->i_out, smps->limits.i_out); ret = -EPERM; @@ -443,7 +443,7 @@ static int smps_ioctl(FAR struct file *filep, int cmd, unsigned long arg) if (smps->limits.p_out > 0 && params->p_out > smps->limits.p_out) { - pwrerr("ERROR: params->p_out > limits.p_out: %d > %d\n", + pwrerr("ERROR: params->p_out > limits.p_out: %.2f > %.2f\n", params->p_out, smps->limits.p_out); ret = -EPERM; diff --git a/drivers/ramdisk.c b/drivers/ramdisk.c index 4473a41ad1d1485c8b636f82401fdacbc3310d4c..b31e1f0dd9dd8f01a12487230045766bb7e1bbbf 100644 --- a/drivers/ramdisk.c +++ b/drivers/ramdisk.c @@ -303,7 +303,7 @@ static ssize_t rd_write(FAR struct inode *inode, const unsigned char *buffer, else if (start_sector < dev->rd_nsectors && start_sector + nsectors <= dev->rd_nsectors) { - finfo("Transfer %d bytes from %p\n", + finfo("Transfer %d bytes to %p\n", nsectors * dev->rd_sectsize, &dev->rd_buffer[start_sector * dev->rd_sectsize]); diff --git a/drivers/sensors/Kconfig b/drivers/sensors/Kconfig index 688d9d4113c244bc74d2d4895f3fc6dcede78ed0..cfff74ff632e8f28a35a59ebd471c7d3dd3bc897 100644 --- a/drivers/sensors/Kconfig +++ b/drivers/sensors/Kconfig @@ -19,7 +19,7 @@ config SENSORS_AS5048B bool "AMS AS5048B Magnetic Rotary Encoder support" default n select I2C - select QENCODER + select SENSORS_QENCODER ---help--- Enable driver support for the AMS AS5048B magnetic rotary encoder. diff --git a/drivers/sensors/hts221.c b/drivers/sensors/hts221.c index b4dbc6dab6bca23d42c7bedb720ef059a8f8f08f..2c3ec4cfe33b0e9ba46703b0edaac2274ff6b38c 100644 --- a/drivers/sensors/hts221.c +++ b/drivers/sensors/hts221.c @@ -321,7 +321,7 @@ static int hts221_config_ctrl_reg3(FAR struct hts221_dev_s *priv, uint8_t data_to_write[2] = { 0 }; ret = hts221_read_reg(priv, &addr, ®val); - hts221_dbg("CTRL_REG3: 0x%02X\n", regval); + hts221_dbg("CTRL_REG%d: 0x%02X\n", 3, regval); if (ret < 0) { return ERROR; @@ -336,6 +336,15 @@ static int hts221_config_ctrl_reg3(FAR struct hts221_dev_s *priv, data_to_write[1] = regval; ret = hts221_write_reg8(priv, data_to_write); + if (ret >= 0) + { + ret = hts221_read_reg(priv, &addr, ®val); + if (ret >= 0) + { + hts221_dbg("wrote 0x%02X => CTRL_REG%d: 0x%02X\n", + data_to_write[1], 3, regval); + } + } return ret; } @@ -348,21 +357,65 @@ static int hts221_config_ctrl_reg2(FAR struct hts221_dev_s *priv, uint8_t addr = HTS221_CTRL_REG2; const uint8_t mask = 0x80; uint8_t data_to_write[2] = { 0 }; + int retries = 5; + + if (!settings->is_boot) + { + return OK; + } ret = hts221_read_reg(priv, &addr, ®val); - hts221_dbg("CTRL_REG2: 0x%02X\n", regval); + hts221_dbg("CTRL_REG%d: 0x%02X\n", 2, regval); + if (ret < 0) { return ERROR; } regval &= ~mask; - regval |= (uint8_t)(settings->is_boot ? HTS221_CTRL_REG2_BOOT : 0); + regval |= HTS221_CTRL_REG2_BOOT; data_to_write[0] = addr; data_to_write[1] = regval; ret = hts221_write_reg8(priv, data_to_write); + if (ret >= 0) + { + /* Wait until boot bit is cleared. */ + + do + { + ret = hts221_read_reg(priv, &addr, ®val); + if (ret >= 0) + { + hts221_dbg("wrote 0x%02X => CTRL_REG%d: 0x%02X\n", + data_to_write[1], 2, regval); + } + else + { + break; + } + + if ((regval & HTS221_CTRL_REG2_BOOT) == 0) + { + /* After boot bit is cleared, wait additional 5 msec as + * recommended in HTS221 application note. + */ + + up_mdelay(5); + break; + } + + usleep(10 * 1000); + retries--; + } + while (retries); + + if (ret >= 0 && (regval & HTS221_CTRL_REG2_BOOT) != 0) + { + ret = -ETIMEDOUT; + } + } return ret; } @@ -377,7 +430,7 @@ static int hts221_config_ctrl_reg1(FAR struct hts221_dev_s *priv, uint8_t data_to_write[2] = { 0 }; ret = hts221_read_reg(priv, &addr, ®val); - hts221_dbg("CTRL_REG1: 0x%02X\n", regval); + hts221_dbg("CTRL_REG%d: 0x%02X\n", 1, regval); if (ret < 0) { return ERROR; @@ -391,6 +444,15 @@ static int hts221_config_ctrl_reg1(FAR struct hts221_dev_s *priv, data_to_write[1] = regval; ret = hts221_write_reg8(priv, data_to_write); + if (ret >= 0) + { + ret = hts221_read_reg(priv, &addr, ®val); + if (ret >= 0) + { + hts221_dbg("wrote 0x%02X => CTRL_REG%d: 0x%02X\n", + data_to_write[1], 1, regval); + } + } return ret; } @@ -403,7 +465,7 @@ static int hts221_power_on_off(FAR struct hts221_dev_s *priv, bool on) uint8_t data_to_write[2]; ret = hts221_read_reg(priv, &addr, ®val); - hts221_dbg("CTRL_REG1: 0x%02X\n", regval); + hts221_dbg("CTRL_REG%d: 0x%02X\n", 1, regval); if (ret < 0) { return ret; @@ -421,6 +483,15 @@ static int hts221_power_on_off(FAR struct hts221_dev_s *priv, bool on) data_to_write[1] = regval; ret = hts221_write_reg8(priv, data_to_write); + if (ret >= 0) + { + ret = hts221_read_reg(priv, &addr, ®val); + if (ret >= 0) + { + hts221_dbg("wrote 0x%02X => CTRL_REG%d: 0x%02X\n", + data_to_write[1], 1, regval); + } + } return ret; } @@ -430,19 +501,19 @@ static int hts221_config(FAR struct hts221_dev_s *priv, { int ret = OK; - ret = hts221_cfgr_resolution(priv, cfgr); + ret = hts221_config_ctrl_reg2(priv, cfgr); /* Performs sensor reset. */ if (ret < 0) { return ERROR; } - ret = hts221_config_ctrl_reg3(priv, cfgr); + ret = hts221_cfgr_resolution(priv, cfgr); if (ret < 0) { return ERROR; } - ret = hts221_config_ctrl_reg2(priv, cfgr); + ret = hts221_config_ctrl_reg3(priv, cfgr); if (ret < 0) { return ERROR; @@ -511,7 +582,7 @@ static int hts221_read_raw_data(FAR struct hts221_dev_s *priv, uint8_t addr_humid_high = HTS221_HUM_OUT_H; uint8_t addr_temp_low = HTS221_TEMP_OUT_L; uint8_t addr_temp_high = HTS221_TEMP_OUT_H; - uint32_t flags; + irqstate_t flags; ret = hts221_read_reg(priv, &addr_humid_low, &data->humid_low_bits); if (ret < 0) @@ -1033,7 +1104,7 @@ static int hts221_poll(FAR struct file *filep, FAR struct pollfd *fds, { FAR struct inode *inode; FAR struct hts221_dev_s *priv; - uint32_t flags; + irqstate_t flags; int ret; int i; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index f44613d391ddf72efbff39b90c7f03fbccc4e0df..fccab900fc508a4bb91a84f84cca5b8c0a772718 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -461,6 +461,11 @@ config USART8_SERIALDRIVER default n select MCU_SERIAL +config USART9_SERIALDRIVER + bool + default n + select MCU_SERIAL + config OTHER_UART_SERIALDRIVER bool default n @@ -667,6 +672,11 @@ config USART8_SERIAL_CONSOLE depends on USART8_SERIALDRIVER select SERIAL_CONSOLE +config USART9_SERIAL_CONSOLE + bool "USART8" + depends on USART9_SERIALDRIVER + select SERIAL_CONSOLE + config SCI0_SERIAL_CONSOLE bool "SCI0" depends on SCI0_SERIALDRIVER @@ -1924,6 +1934,71 @@ config UART8_DMA endmenu +menu "USART9 Configuration" + depends on USART9_SERIALDRIVER + +config USART9_RXBUFSIZE + int "Receive buffer size" + default 256 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. + +config USART9_TXBUFSIZE + int "Transmit buffer size" + default 256 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. + +config USART9_BAUD + int "BAUD rate" + default 115200 + ---help--- + The configured BAUD of the USART. + +config USART9_BITS + int "Character size" + default 8 + ---help--- + The number of bits. Must be either 7 or 8. + +config USART9_PARITY + int "Parity setting" + default 0 + range 0 2 + ---help--- + 0=no parity, 1=odd parity, 2=even parity + +config USART9_2STOP + int "Uses 2 stop bits" + default 0 + ---help--- + 1=Two stop bits + +config USART9_IFLOWCONTROL + bool "USART9 RTS flow control" + default n + select SERIAL_IFLOWCONTROL + ---help--- + Enable USART9 RTS flow control + +config USART9_OFLOWCONTROL + bool "USART9 CTS flow control" + default n + select SERIAL_OFLOWCONTROL + ---help--- + Enable USART9 CTS flow control + +config USART9_DMA + bool "USART9 DMA support" + default n + select SERIAL_DMA + ---help--- + Enable DMA transfers on USART9 + +endmenu + menu "SCI0 Configuration" depends on SCI0_SERIALDRIVER diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index ecf21006a2ca9b7343802e4a792db31ebbe02398..8ec8350b8cb8ef55776870445a1c3c4feb771ca2 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -88,8 +88,8 @@ /* Timing */ -#define HALF_SECOND_MSEC 500 -#define HALF_SECOND_USEC 500000L +#define POLL_DELAY_MSEC 1 +#define POLL_DELAY_USEC 1000 /************************************************************************************ * Private Types @@ -471,9 +471,9 @@ static int uart_tcdrain(FAR uart_dev_t *dev) while (!uart_txempty(dev)) { #ifndef CONFIG_DISABLE_SIGNALS - nxsig_usleep(HALF_SECOND_USEC); + nxsig_usleep(POLL_DELAY_USEC); #else - up_mdelay(HALF_SECOND_MSEC); + up_mdelay(POLL_DELAY_MSEC); #endif } } diff --git a/drivers/usbdev/cdcacm_desc.c b/drivers/usbdev/cdcacm_desc.c index 9dbf4c0f30201003c6fcb928d05521f1f73d2cca..6e97a1dca2d73af5472d5196389dec109c81430e 100644 --- a/drivers/usbdev/cdcacm_desc.c +++ b/drivers/usbdev/cdcacm_desc.c @@ -236,8 +236,7 @@ int cdcacm_copy_epdesc(enum cdcacm_epdesc_e epid, bool hispeed) { #ifndef CONFIG_USBDEV_DUALSPEED - /* unused */ - (void)hispeed; + UNUSED(hispeed); #endif switch (epid) @@ -255,7 +254,7 @@ int cdcacm_copy_epdesc(enum cdcacm_epdesc_e epid, /* Maximum packet size (high speed) */ epdesc->mxpacketsize[0] = LSBYTE(CONFIG_CDCACM_EPINTIN_HSSIZE); - epdesc->mxpacketsize[1] = MSBYTE(CONFIG_CDCACM_EPINTIN_HSSIZE); + epdesc->mxpacketsize[1] = MSBYTE(CONFIG_CDCACM_EPINTIN_HSSIZE); } else #endif diff --git a/drivers/usbdev/rndis.c b/drivers/usbdev/rndis.c index 4a060f0fd2704129388d06923b2543f556710a8a..3e1baf2e08a0a5295c425612318f4607190fd714 100644 --- a/drivers/usbdev/rndis.c +++ b/drivers/usbdev/rndis.c @@ -80,6 +80,7 @@ #define RNDIS_PACKET_HDR_SIZE (sizeof(struct rndis_packet_msg)) #define CONFIG_RNDIS_BULKIN_REQLEN (CONFIG_NET_ETH_MTU + RNDIS_PACKET_HDR_SIZE) +#define CONFIG_RNDIS_BULKOUT_REQLEN CONFIG_RNDIS_BULKIN_REQLEN #define RNDIS_NCONFIGS (1) #define RNDIS_CONFIGID (1) @@ -158,6 +159,7 @@ struct rndis_dev_s size_t current_rx_received; /* Number of bytes of current RX datagram received over USB */ size_t current_rx_datagram_size; /* Total number of bytes of the current RX datagram */ size_t current_rx_datagram_offset; /* Offset of current RX datagram */ + size_t current_rx_msglen; /* Length of the entire message to be received */ bool rdreq_submitted; /* Indicates if the read request is submitted */ bool rx_blocked; /* Indicates if we can receive packets on bulk in endpoint */ bool ctrlreq_has_encap_response; /* Indicates if ctrlreq buffer holds a response */ @@ -216,6 +218,7 @@ struct rndis_oid_value_s static int rndis_ifup(FAR struct net_driver_s *dev); static int rndis_ifdown(FAR struct net_driver_s *dev); static int rndis_txavail(FAR struct net_driver_s *dev); +static int rndis_transmit(FAR struct rndis_dev_s *priv); static int rndis_txpoll(FAR struct net_driver_s *dev); static void rndis_polltimer(int argc, uint32_t arg, ...); @@ -328,16 +331,26 @@ const static struct rndis_cfgdesc_s g_rndis_cfgdesc = .type = USB_DESC_TYPE_ENDPOINT, .addr = RNDIS_EPBULKIN_ADDR, .attr = USB_EP_ATTR_XFER_BULK, +#ifdef CONFIG_USBDEV_DUALSPEED + .mxpacketsize = { LSBYTE(512), MSBYTE(512) }, + .interval = 0 +#else .mxpacketsize = { LSBYTE(64), MSBYTE(64) }, .interval = 1 +#endif }, { .len = USB_SIZEOF_EPDESC, .type = USB_DESC_TYPE_ENDPOINT, .addr = RNDIS_EPBULKOUT_ADDR, .attr = USB_EP_ATTR_XFER_BULK, +#ifdef CONFIG_USBDEV_DUALSPEED + .mxpacketsize = { LSBYTE(512), MSBYTE(512) }, + .interval = 0 +#else .mxpacketsize = { LSBYTE(64), MSBYTE(64) }, .interval = 1 +#endif } }; @@ -389,7 +402,11 @@ static const struct rndis_oid_value_s g_rndis_oid_values[] = { {RNDIS_OID_GEN_SUPPORTED_LIST, sizeof(g_rndis_supported_oids), 0, g_rndis_supported_oids}, {RNDIS_OID_GEN_MAXIMUM_FRAME_SIZE, 4, CONFIG_NET_ETH_MTU, NULL}, +#ifdef CONFIG_USBDEV_DUALSPEED {RNDIS_OID_GEN_LINK_SPEED, 4, 100000, NULL}, +#else + {RNDIS_OID_GEN_LINK_SPEED, 4, 2000000, NULL}, +#endif {RNDIS_OID_GEN_TRANSMIT_BLOCK_SIZE, 4, CONFIG_NET_ETH_MTU, NULL}, {RNDIS_OID_GEN_RECEIVE_BLOCK_SIZE, 4, CONFIG_NET_ETH_MTU, NULL}, {RNDIS_OID_GEN_VENDOR_ID, 4, 0x00FFFFFF, NULL}, @@ -824,7 +841,6 @@ static void rndis_rxdispatch(FAR void *arg) #ifdef CONFIG_NET_IPv4 if (hdr->type == HTONS(ETHTYPE_IP)) { - uinfo("IPv4 frame\n"); NETDEV_RXIPV4(&priv->netdev); /* Handle ARP on input then give the IPv4 packet to the network @@ -833,28 +849,77 @@ static void rndis_rxdispatch(FAR void *arg) arp_ipin(&priv->netdev); ipv4_input(&priv->netdev); + + if (priv->netdev.d_len > 0) + { + /* Update the Ethernet header with the correct MAC address */ + +#ifdef CONFIG_NET_IPv6 + if (IFF_IS_IPv4(priv->netdev.d_flags)) +#endif + { + arp_out(&priv->netdev); + } +#ifdef CONFIG_NET_IPv6 + else + { + neighbor_out(&priv->netdev); + } +#endif + + /* And send the packet */ + + rndis_transmit(priv); + } } else #endif #ifdef CONFIG_NET_IPv6 if (hdr->type == HTONS(ETHTYPE_IP6)) { - uinfo("IPv6 frame\n"); NETDEV_RXIPV6(&priv->netdev); /* Give the IPv6 packet to the network layer */ + arp_ipin(&priv->netdev); ipv6_input(&priv->netdev); + + if (priv->netdev.d_len > 0) + { + /* Update the Ethernet header with the correct MAC address */ + +#ifdef CONFIG_NET_IPv4 + if (IFF_IS_IPv4(priv->netdev.d_flags)) + { + arp_out(&priv->netdev); + } + else +#endif +#ifdef CONFIG_NET_IPv6 + { + neighbor_out(&priv->netdev); + } +#endif + + /* And send the packet */ + + rndis_transmit(priv); + } + } else #endif #ifdef CONFIG_NET_ARP if (hdr->type == htons(ETHTYPE_ARP)) { - uinfo("ARP packet received (%02x)\n", hdr->type); NETDEV_RXARP(&priv->netdev); arp_arpin(&priv->netdev); + + if (priv->netdev.d_len > 0) + { + rndis_transmit(priv); + } } else #endif @@ -864,7 +929,6 @@ static void rndis_rxdispatch(FAR void *arg) priv->netdev.d_len = 0; } - rndis_txpoll(&priv->netdev); priv->current_rx_datagram_size = 0; rndis_unblock_rx(priv); @@ -894,6 +958,7 @@ static void rndis_rxdispatch(FAR void *arg) static int rndis_txpoll(FAR struct net_driver_s *dev) { FAR struct rndis_dev_s *priv = (FAR struct rndis_dev_s *)dev->d_private; + int ret = OK; if (!priv->connected) { @@ -904,7 +969,7 @@ static int rndis_txpoll(FAR struct net_driver_s *dev) * the field d_len is set to a value > 0. */ - uinfo("Poll result: d_len=%d\n", priv->netdev.d_len); + ninfo("Poll result: d_len=%d\n", priv->netdev.d_len); if (priv->netdev.d_len > 0) { /* Look up the destination MAC address and add it to the Ethernet @@ -929,22 +994,40 @@ static int rndis_txpoll(FAR struct net_driver_s *dev) } #endif /* CONFIG_NET_IPv6 */ - /* Queue the packet */ - - rndis_fillrequest(priv, priv->net_req->req); - rndis_sendnetreq(priv); + ret = rndis_transmit(priv); - if (!rndis_allocnetreq(priv)) - { - return -EBUSY; - } } /* If zero is returned, the polling will continue until all connections have * been examined. */ - return OK; + return ret; +} + +/**************************************************************************** + * Name: rndis_transmit + * + * Description: + * Start hardware transmission. + * + ****************************************************************************/ + +static int rndis_transmit(FAR struct rndis_dev_s *priv) +{ + int ret = OK; + + /* Queue the packet */ + + rndis_fillrequest(priv, priv->net_req->req); + rndis_sendnetreq(priv); + + if (!rndis_allocnetreq(priv)) + { + ret = -EBUSY; + } + + return ret; } /**************************************************************************** @@ -1123,6 +1206,17 @@ static inline int rndis_recvpacket(FAR struct rndis_dev_s *priv, { priv->current_rx_received = reqlen; priv->current_rx_datagram_size = msg->datalen; + priv->current_rx_msglen = msg->msglen; + + /* According to RNDIS-over-USB send, if the message length is a + * multiple of endpoint max packet size, the host must send an + * additional single-byte zero packet. Take that in account here. + */ + + if ((priv->current_rx_msglen % priv->epbulkout->maxpacket) == 0) + { + priv->current_rx_msglen += 1; + } /* Data offset is defined as an offset from the beginning of the * offset field itself @@ -1142,51 +1236,56 @@ static inline int rndis_recvpacket(FAR struct rndis_dev_s *priv, } } } - else if (priv->current_rx_received >= priv->current_rx_datagram_offset && - priv->current_rx_received < priv->current_rx_datagram_size + - priv->current_rx_datagram_offset) - { - size_t index = priv->current_rx_received - priv->current_rx_datagram_offset; - size_t copysize = min(reqlen, priv->current_rx_datagram_size + - priv->current_rx_datagram_offset - - priv->current_rx_received); - memcpy(&priv->rx_req->req->buf[RNDIS_PACKET_HDR_SIZE + index], reqbuf, - copysize); - priv->current_rx_received += reqlen; - - if (priv->current_rx_received >= priv->current_rx_datagram_size + - priv->current_rx_datagram_offset) + else + { + if (priv->current_rx_received >= priv->current_rx_datagram_offset && + priv->current_rx_received <= priv->current_rx_datagram_size + + priv->current_rx_datagram_offset) { - /* Check for a usable packet length (4 added for the CRC) */ + size_t index = priv->current_rx_received - priv->current_rx_datagram_offset; + size_t copysize = min(reqlen, priv->current_rx_datagram_size - index); + + /* Check if the received packet exceeds request buffer */ - if (priv->current_rx_datagram_size > (CONFIG_NET_ETH_MTU + 4) || - priv->current_rx_datagram_size <= (ETH_HDRLEN + 4)) + if ((RNDIS_PACKET_HDR_SIZE + index + copysize) <= CONFIG_NET_ETH_MTU) { - uerr("ERROR: Bad packet size dropped (%d)\n", - priv->current_rx_datagram_size); - NETDEV_RXERRORS(&priv->netdev); + memcpy(&priv->rx_req->req->buf[RNDIS_PACKET_HDR_SIZE + index], reqbuf, + copysize); } else { - int ret; - - DEBUGASSERT(work_available(&priv->rxwork)); - ret = work_queue(ETHWORK, &priv->rxwork, rndis_rxdispatch, - priv, 0); - DEBUGASSERT(ret == 0); - UNUSED(ret); - - rndis_block_rx(priv); - priv->rndis_host_tx_count++; - return -EBUSY; + uerr("The packet exceeds request buffer (reqlen=%d) \n", reqlen); } } + priv->current_rx_received += reqlen; } - else + + if (priv->current_rx_received >= priv->current_rx_msglen) { - /* Ignore the packet */ + /* Check for a usable packet length (4 added for the CRC) */ - priv->current_rx_received += reqlen; + if (priv->current_rx_datagram_size > (CONFIG_NET_ETH_MTU + 4) || + priv->current_rx_datagram_size <= (ETH_HDRLEN + 4)) + { + uerr("ERROR: Bad packet size dropped (%d)\n", + priv->current_rx_datagram_size); + NETDEV_RXERRORS(&priv->netdev); + priv->current_rx_datagram_size = 0; + } + else + { + int ret; + + DEBUGASSERT(work_available(&priv->rxwork)); + ret = work_queue(ETHWORK, &priv->rxwork, rndis_rxdispatch, + priv, 0); + DEBUGASSERT(ret == 0); + UNUSED(ret); + + rndis_block_rx(priv); + priv->rndis_host_tx_count++; + return -EBUSY; + } } return OK; @@ -1286,7 +1385,7 @@ static int rndis_handle_control_message(FAR struct rndis_dev_s *priv, resp->devflags = RNDIS_DEVICEFLAGS; resp->medium = RNDIS_MEDIUM_802_3; resp->pktperxfer = 1; - resp->xfrsize = 36 + RNDIS_BUFFER_SIZE; + resp->xfrsize = (4 + 44 + 22) + RNDIS_BUFFER_SIZE; resp->pktalign = 2; rndis_send_encapsulated_response(priv); @@ -1859,6 +1958,11 @@ static int usbclass_bind(FAR struct usbdevclass_driver_s *driver, reqlen = 64; + if (CONFIG_RNDIS_BULKOUT_REQLEN > reqlen) + { + reqlen = CONFIG_RNDIS_BULKOUT_REQLEN; + } + priv->rdreq = usbclass_allocreq(priv->epbulkout, reqlen); if (priv->rdreq == NULL) { @@ -2086,8 +2190,8 @@ static int usbclass_setup(FAR struct usbdevclass_driver_s *driver, value = GETUINT16(ctrl->value); len = GETUINT16(ctrl->len); - uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n", - ctrl->type, ctrl->req, value, index, len); + uinfo("type=%02x req=%02x value=%04x len=%04x\n", + ctrl->type, ctrl->req, value, len); switch (ctrl->type & USB_REQ_TYPE_MASK) { diff --git a/drivers/usbdev/usbmsc_desc.c b/drivers/usbdev/usbmsc_desc.c index bd9497b0c930d64754c67cdc35b461c7c036bd0f..be2e10e0ead5f7531dc03551acaf59c71b7bec2a 100644 --- a/drivers/usbdev/usbmsc_desc.c +++ b/drivers/usbdev/usbmsc_desc.c @@ -230,9 +230,7 @@ int usbmsc_copy_epdesc(enum usbmsc_epdesc_e epid, bool hispeed) { #ifndef CONFIG_USBDEV_DUALSPEED - /* unused */ - - (void)hispeed; + UNUSED(hispeed); #endif switch (epid) diff --git a/drivers/usbhost/usbhost_hidmouse.c b/drivers/usbhost/usbhost_hidmouse.c index 6e6b545710871df891357e5caf78e900e6b7eb0f..043adb3183a2eec1c7fc77e8afb61e8e0cfdf6e8 100644 --- a/drivers/usbhost/usbhost_hidmouse.c +++ b/drivers/usbhost/usbhost_hidmouse.c @@ -1159,7 +1159,7 @@ static int usbhost_mouse_poll(int argc, char *argv[]) if (buttons != priv->buttons || usbhost_threshold(priv)) #endif { - /* We get here when either there is a meaning button + /* We get here when either there is a meaningful button * change and/or a significant movement of the mouse. We * are going to report the mouse event. * diff --git a/drivers/video/fb.c b/drivers/video/fb.c index d696b815bfea06bfe9014d7a10385c30cf1f7eee..30baae0bf1839408bcf176f9ffe5f6c18d7748e3 100644 --- a/drivers/video/fb.c +++ b/drivers/video/fb.c @@ -404,8 +404,8 @@ static int fb_ioctl(FAR struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_NX_UPDATE - case FBIO_UPDATE: /* Get video plane info */ +#ifdef CONFIG_LCD_UPDATE + case FBIO_UPDATE: /* Update the LCD with the modified framebuffer data */ { FAR struct nxgl_rect_s *rect = (FAR struct nxgl_rect_s *)((uintptr_t)arg); @@ -441,7 +441,7 @@ static int fb_ioctl(FAR struct file *filep, int cmd, unsigned long arg) * Register the framebuffer character device at /dev/fbN where N is the * display number if the devices supports only a single plane. If the * hardware supports multiple color planes, then the device will be - * registered at /dev/fbN-M where N is the again display number but M + * registered at /dev/fbN.M where N is the again display number but M * is the display plane. * * Input Parameters: @@ -530,7 +530,7 @@ int fb_register(int display, int plane) } else { - (void)snprintf(devname, 16, "/dev/fb%d-%d", display, plane); + (void)snprintf(devname, 16, "/dev/fb%d.%d", display, plane); } ret = register_driver(devname, &fb_fops, 0666, (FAR void *)fb); diff --git a/drivers/wireless/ieee80211/bcmf_netdev.c b/drivers/wireless/ieee80211/bcmf_netdev.c index 455b15529bd923e9392a59e132120471b2e1fe55..cd2c919e37adea2db237013592193f0c3fb74a18 100644 --- a/drivers/wireless/ieee80211/bcmf_netdev.c +++ b/drivers/wireless/ieee80211/bcmf_netdev.c @@ -83,10 +83,10 @@ # if defined(CONFIG_IEEE80211_BROADCOM_HPWORK) # define BCMFWORK HPWORK -# elif defined(CONFIG_IEEE80211_BROADCOM_HLWORK) +# elif defined(CONFIG_IEEE80211_BROADCOM_LPWORK) # define BCMFWORK LPWORK # else -# error Neither CONFIG_IEEE80211_BROADCOM_HPWORK nor CONFIG_IEEE80211_BROADCOM_HLWORK defined +# error Neither CONFIG_IEEE80211_BROADCOM_HPWORK nor CONFIG_IEEE80211_BROADCOM_LPWORK defined # endif #endif @@ -926,7 +926,7 @@ static void bcmf_ipv6multicast(FAR struct bcmf_dev_s *priv) mac[0] = 0x33; mac[1] = 0x33; - dev = &priv->dev; + dev = &priv->bc_dev; tmp16 = dev->d_ipv6addr[6]; mac[2] = 0xff; mac[3] = tmp16 >> 8; @@ -1122,7 +1122,7 @@ int bcmf_netdev_register(FAR struct bcmf_dev_s *priv) priv->bc_txpoll = wd_create(); /* Create periodic poll timer */ - DEBUGASSERT(priv->bc_txpoll != NULL && priv->bc_txtimeout != NULL); + DEBUGASSERT(priv->bc_txpoll != NULL); /* Initialize network stack interface buffer */ diff --git a/drivers/wireless/ieee802154/mrf24j40/mrf24j40.c b/drivers/wireless/ieee802154/mrf24j40/mrf24j40.c index 48d194f021bf7771949437e7c4f2269547f036e0..36dd2201501293714f55c097428160c560f31735 100644 --- a/drivers/wireless/ieee802154/mrf24j40/mrf24j40.c +++ b/drivers/wireless/ieee802154/mrf24j40/mrf24j40.c @@ -429,8 +429,9 @@ void mrf24j40_setup_fifo(FAR struct mrf24j40_radio_s *dev, FAR const uint8_t *bu * ****************************************************************************/ -FAR struct ieee802154_radio_s *mrf24j40_init(FAR struct spi_dev_s *spi, - FAR const struct mrf24j40_lower_s *lower) +FAR struct ieee802154_radio_s * + mrf24j40_init(FAR struct spi_dev_s *spi, + FAR const struct mrf24j40_lower_s *lower) { FAR struct mrf24j40_radio_s *dev; diff --git a/drivers/wireless/ieee802154/mrf24j40/mrf24j40_interrupt.c b/drivers/wireless/ieee802154/mrf24j40/mrf24j40_interrupt.c index 6bb1f226fd1f8e58bba2e91a5237f8ef769dcafa..6a63918a6b91817ec2df62b1f0ce97b2118b95c2 100644 --- a/drivers/wireless/ieee802154/mrf24j40/mrf24j40_interrupt.c +++ b/drivers/wireless/ieee802154/mrf24j40/mrf24j40_interrupt.c @@ -117,7 +117,6 @@ static void mrf24j40_irqwork_txnorm(FAR struct mrf24j40_radio_s *dev) MRF24J40_TXNCON_FPSTAT); if (dev->txdelayed_busy) - { /* Inform the next layer of the transmission success/failure */ @@ -213,6 +212,7 @@ static void mrf24j40_irqwork_txgts(FAR struct mrf24j40_radio_s *dev, static void mrf24j40_irqwork_rx(FAR struct mrf24j40_radio_s *dev) { + FAR struct ieee802154_primitive_s *primitive; FAR struct ieee802154_data_ind_s *ind; uint32_t addr; uint32_t index; @@ -232,13 +232,24 @@ static void mrf24j40_irqwork_rx(FAR struct mrf24j40_radio_s *dev) /* Allocate a data_ind to put the frame in */ - ind = ieee802154_ind_allocate(); + primitive = ieee802154_primitive_allocate(); + ind = (FAR struct ieee802154_data_ind_s *)primitive; if (ind == NULL) { wlerr("ERROR: Unable to allocate data_ind. Discarding frame\n"); goto done; } + primitive->type = IEEE802154_PRIMITIVE_IND_DATA; + + /* Allocate an IOB to put the frame into */ + + ind->frame = iob_alloc(false); + ind->frame->io_flink = NULL; + ind->frame->io_len = 0; + ind->frame->io_pktlen = 0; + ind->frame->io_offset = 0; + /* Read packet */ addr = MRF24J40_RXBUF_BASE; diff --git a/drivers/wireless/ieee802154/xbee/Kconfig b/drivers/wireless/ieee802154/xbee/Kconfig index 5b28d40b63bf05ac0ea809ef61c772152b753455..5edea5770ccdb32a18f3bdbd01c736c1d9990a2f 100644 --- a/drivers/wireless/ieee802154/xbee/Kconfig +++ b/drivers/wireless/ieee802154/xbee/Kconfig @@ -11,24 +11,6 @@ config IEEE802154_XBEE_FREQUENCY ---help--- SPI SLCK frequency in Hz -config XBEE_NETDEV_RECVRPRIO - int "Priority of frame receiver registerd with the MAC layer" - default 1 - ---help--- - When the MAC layer receives an incoming data frame, it passes the frame - to registered receivers, in order of receiver priority, until one of the - receivers claim the frame. - - An example case would be when 6LoWPAN and the MAC character driver are - enabled. Both have receivers registered with the MAC. The 6LoWPAN layer - should get assigned a higher priority than the character driver. In this - case, the 6LoWPAN receiver will receive the frame first. If the frame is - a 6LoWPAN frame, it will claim the frame and the MAC will not pass the - frame to any additional receivers. If it does not claim the frame, the - MAC layer will call the next highest priority receiver, in this case, - the MAC character driver (which should always be lowest priority since - it is a "catch-all" type receiver). - choice prompt "Work queue" default XBEE_NETDEV_LPWORK if SCHED_LPWORK @@ -57,21 +39,22 @@ config XBEE_NETDEV_LPWORK endchoice # Work queue -config XBEE_NNOTIF - int "Number or notification structures" - default 3 +config XBEE_NETDEV_RECVRPRIO + int "Priority of frame receiver registerd with the MAC layer" + default 1 ---help--- - Configured number of notification strucures Default: 3 - - When various MAC management events occur, the MAC notifies the registered - receiver with an allocated notification structure indicating the event. The - events are primitives such as Association Indication etc. + When the MAC layer receives an incoming data frame, it passes the frame + to registered receivers, in order of receiver priority, until one of the + receivers claim the frame. -config XBEE_LOCK_VERBOSE - bool "Verbose logging related to XBee driver lock management" - default n - depends on DEBUG_WIRELESS_INFO - ---help--- - Enable verbose logging of XBee lock management. Default: false + An example case would be when 6LoWPAN and the MAC character driver are + enabled. Both have receivers registered with the MAC. The 6LoWPAN layer + should get assigned a higher priority than the character driver. In this + case, the 6LoWPAN receiver will receive the frame first. If the frame is + a 6LoWPAN frame, it will claim the frame and the MAC will not pass the + frame to any additional receivers. If it does not claim the frame, the + MAC layer will call the next highest priority receiver, in this case, + the MAC character driver (which should always be lowest priority since + it is a "catch-all" type receiver). endif # IEEE802154_XBEE diff --git a/drivers/wireless/ieee802154/xbee/Make.defs b/drivers/wireless/ieee802154/xbee/Make.defs index 241b6bc3221d23b891378942f0c9fcce5532839f..d4e7371d1c2b4b527a75f27af2aeeef997d04d29 100644 --- a/drivers/wireless/ieee802154/xbee/Make.defs +++ b/drivers/wireless/ieee802154/xbee/Make.defs @@ -37,7 +37,7 @@ ifeq ($(CONFIG_IEEE802154_XBEE),y) # Include XBee files into the build -CSRCS += xbee_dataind.c xbee_ioctl.c xbee_mac.c xbee_netdev.c xbee_notif.c xbee.c +CSRCS += xbee_ioctl.c xbee_mac.c xbee_netdev.c xbee.c # Include XBee build support diff --git a/drivers/wireless/ieee802154/xbee/xbee.c b/drivers/wireless/ieee802154/xbee/xbee.c index 6881f636b00281b040d6ad342958b5725cdcc995..c0a7fd0ca029227895ecd92242f2b67063066e85 100644 --- a/drivers/wireless/ieee802154/xbee/xbee.c +++ b/drivers/wireless/ieee802154/xbee/xbee.c @@ -60,6 +60,8 @@ * Pre-processor Definitions ****************************************************************************/ +#define XBEE_ATQUERY_TIMEOUT 100 + /**************************************************************************** * Private Types ****************************************************************************/ @@ -79,6 +81,10 @@ static void xbee_process_txstatus(FAR struct xbee_priv_s *priv, uint8_t frameid, static void xbee_process_rxframe(FAR struct xbee_priv_s *priv, FAR struct iob_s *frame, enum ieee802154_addrmode_e addrmode); +static void xbee_notify(FAR struct xbee_priv_s *priv, + FAR struct ieee802154_primitive_s *primitive); +static void xbee_notify_worker(FAR void *arg); +static void xbee_atquery_timeout(int argc, uint32_t arg, ...); /**************************************************************************** * Private Data @@ -355,6 +361,17 @@ static void xbee_attnworker(FAR void *arg) { xbee_process_apiframes(priv, iobhead); } + + /* If an interrupt occured while the worker was running, it was not + * scheduled since there is a good chance this function has already handled + * it as part of the previous ATTN assertion. Therefore, if the ATTN + * line is asserted again reschedule the work. + */ + + if (priv->attn_latched) + { + work_queue(HPWORK, &priv->attnwork, xbee_attnworker, (FAR void *)priv, 0); + } } /**************************************************************************** @@ -480,7 +497,7 @@ static bool xbee_verify_checksum(FAR const struct iob_s *iob) static void xbee_process_apiframes(FAR struct xbee_priv_s *priv, FAR struct iob_s *framelist) { - FAR struct ieee802154_notif_s *notif; + FAR struct ieee802154_primitive_s *primitive; FAR struct iob_s *frame; FAR struct iob_s *nextframe; FAR char *command; @@ -515,7 +532,7 @@ static void xbee_process_apiframes(FAR struct xbee_priv_s *priv, command = (FAR char *)&frame->io_data[frame->io_offset]; frame->io_offset += 2; - wlinfo("AT Repsonse Recevied: %.*s\n", 2, command); + wlinfo("AT Response Received: %.*s\n", 2, command); /* Make sure the command status is OK=0 */ @@ -532,8 +549,6 @@ static void xbee_process_apiframes(FAR struct xbee_priv_s *priv, { priv->addr.panid[1] = frame->io_data[frame->io_offset++]; priv->addr.panid[0] = frame->io_data[frame->io_offset++]; - - xbee_notify_respwaiter(priv, XBEE_RESP_AT_NETWORKID); } else if (memcmp(command, "SH", 2) == 0) { @@ -541,8 +556,6 @@ static void xbee_process_apiframes(FAR struct xbee_priv_s *priv, priv->addr.eaddr[6] = frame->io_data[frame->io_offset++]; priv->addr.eaddr[5] = frame->io_data[frame->io_offset++]; priv->addr.eaddr[4] = frame->io_data[frame->io_offset++]; - - xbee_notify_respwaiter(priv, XBEE_RESP_AT_SERIALHIGH); } else if (memcmp(command, "SL", 2) == 0) { @@ -550,27 +563,20 @@ static void xbee_process_apiframes(FAR struct xbee_priv_s *priv, priv->addr.eaddr[2] = frame->io_data[frame->io_offset++]; priv->addr.eaddr[1] = frame->io_data[frame->io_offset++]; priv->addr.eaddr[0] = frame->io_data[frame->io_offset++]; - - xbee_notify_respwaiter(priv, XBEE_RESP_AT_SERIALLOW); } else if (memcmp(command, "MY", 2) == 0) { priv->addr.saddr[1] = frame->io_data[frame->io_offset++]; priv->addr.saddr[0] = frame->io_data[frame->io_offset++]; - - xbee_notify_respwaiter(priv, XBEE_RESP_AT_SOURCEADDR); } else if (memcmp(command, "CH", 2) == 0) { priv->chan = frame->io_data[frame->io_offset++]; - xbee_notify_respwaiter(priv, XBEE_RESP_AT_CHAN); } else if (memcmp(command, "VR", 2) == 0) { priv->firmwareversion = frame->io_data[frame->io_offset++] << 8; priv->firmwareversion |= frame->io_data[frame->io_offset++]; - - xbee_notify_respwaiter(priv, XBEE_RESP_AT_FIRMWAREVERSION); } else if (memcmp(command, "AI", 2) == 0) { @@ -584,22 +590,19 @@ static void xbee_process_apiframes(FAR struct xbee_priv_s *priv, { wd_cancel(priv->assocwd); - xbee_lock(priv, false); - xbee_notif_alloc(priv, ¬if, false); - xbee_unlock(priv); - - notif->notiftype = IEEE802154_NOTIFY_CONF_ASSOC; + primitive = ieee802154_primitive_allocate(); + primitive->type = IEEE802154_PRIMITIVE_CONF_ASSOC; if (frame->io_data[frame->io_offset] == 0) { - notif->u.assocconf.status = IEEE802154_STATUS_SUCCESS; + primitive->u.assocconf.status = IEEE802154_STATUS_SUCCESS; } else { - notif->u.assocconf.status = IEEE802154_STATUS_FAILURE; + primitive->u.assocconf.status = IEEE802154_STATUS_FAILURE; } - xbee_notify(priv, notif); + xbee_notify(priv, primitive); } } else if (memcmp(command, "A1", 2) == 0) @@ -626,6 +629,15 @@ static void xbee_process_apiframes(FAR struct xbee_priv_s *priv, { wlwarn("Unhandled AT Response: %.*s\n", 2, command); } + + /* If this is the command we are querying for */ + + if ((priv->querycmd[0] == *command) && + (priv->querycmd[1] == *(command + 1))) + { + priv->querydone = true; + nxsem_post(&priv->atresp_sem); + } } } break; @@ -633,11 +645,13 @@ static void xbee_process_apiframes(FAR struct xbee_priv_s *priv, { xbee_process_txstatus(priv, frame->io_data[frame->io_offset], frame->io_data[frame->io_offset + 1]); + nxsem_post(&priv->txdone_sem); } break; case XBEE_APIFRAME_RX_EADDR: { nextframe = frame->io_flink; + frame->io_flink = NULL; xbee_process_rxframe(priv, frame, IEEE802154_ADDRMODE_EXTENDED); frame = nextframe; @@ -650,6 +664,7 @@ static void xbee_process_apiframes(FAR struct xbee_priv_s *priv, case XBEE_APIFRAME_RX_SADDR: { nextframe = frame->io_flink; + frame->io_flink = NULL; xbee_process_rxframe(priv, frame, IEEE802154_ADDRMODE_SHORT); frame = nextframe; @@ -670,7 +685,15 @@ static void xbee_process_apiframes(FAR struct xbee_priv_s *priv, break; } + /* IOB free logic assumes that a valid io_flink entry in the IOB that + * is being freed indicates that the IOB is a part of an IOB chain. Since + * that is not the case here and we are just using the io_flink field + * as a way of managing a list of independent frames, we set the io_flink + * to NULL prior to freeing it. + */ + nextframe = frame->io_flink; + frame->io_flink = NULL; iob_free(frame); frame = nextframe; } @@ -688,13 +711,15 @@ static void xbee_process_rxframe(FAR struct xbee_priv_s *priv, FAR struct iob_s *frame, enum ieee802154_addrmode_e addrmode) { + FAR struct ieee802154_primitive_s *primitive; FAR struct ieee802154_data_ind_s *dataind; - FAR struct xbee_maccb_s *cb; - int ret; - xbee_lock(priv, false); - xbee_dataind_alloc(priv, &dataind, false); - xbee_unlock(priv); + DEBUGASSERT(frame != NULL); + + primitive = ieee802154_primitive_allocate(); + dataind = &primitive->u.dataind; + + primitive->type = IEEE802154_PRIMITIVE_IND_DATA; dataind->frame = frame; @@ -742,34 +767,7 @@ static void xbee_process_rxframe(FAR struct xbee_priv_s *priv, frame->io_len--; /* Remove the checksum */ - /* If there are registered MCPS callback receivers registered, - * then forward the frame in priority order. If there are no - * registered receivers or if none of the receivers accept the - * data frame then drop the frame. - */ - - for (cb = priv->cb; cb != NULL; cb = cb->flink) - { - /* Does this MAC client want frames? */ - - if (cb->rxframe != NULL) - { - /* Yes.. Offer this frame to the receiver */ - - ret = cb->rxframe(cb, dataind); - if (ret >= 0) - { - /* The receiver accepted and disposed of the frame and - * its metadata. We are done. - */ - - return; - } - } - } - - xbee_dataind_free((XBEEHANDLE)priv, dataind); - iob_free(frame); + xbee_notify(priv, primitive); } /**************************************************************************** @@ -784,34 +782,188 @@ static void xbee_process_rxframe(FAR struct xbee_priv_s *priv, static void xbee_process_txstatus(FAR struct xbee_priv_s *priv, uint8_t frameid, uint8_t status) { - FAR struct ieee802154_notif_s *notif; + FAR struct ieee802154_primitive_s *primitive; - xbee_lock(priv, false); - xbee_notif_alloc(priv, ¬if, false); - xbee_unlock(priv); + primitive = ieee802154_primitive_allocate(); - notif->notiftype = IEEE802154_NOTIFY_CONF_DATA; + primitive->type = IEEE802154_PRIMITIVE_CONF_DATA; switch (status) { case 0x00: - notif->u.dataconf.status = IEEE802154_STATUS_SUCCESS; + primitive->u.dataconf.status = IEEE802154_STATUS_SUCCESS; break; case 0x01: case 0x21: - notif->u.dataconf.status = IEEE802154_STATUS_NO_ACK; + primitive->u.dataconf.status = IEEE802154_STATUS_NO_ACK; break; case 0x02: - notif->u.dataconf.status = IEEE802154_STATUS_CHANNEL_ACCESS_FAILURE; + primitive->u.dataconf.status = IEEE802154_STATUS_CHANNEL_ACCESS_FAILURE; break; default: - notif->u.dataconf.status = IEEE802154_STATUS_FAILURE; + primitive->u.dataconf.status = IEEE802154_STATUS_FAILURE; break; } wlinfo("TX done. Frame ID: %d Status: 0x%02X\n", frameid, status); - xbee_notify(priv, notif); + xbee_notify(priv, primitive); +} + +/**************************************************************************** + * Name: xbee_notify + * + * Description: + * Queue the primitive in the queue and queue work on the LPWORK + * queue if is not already scheduled. + * + * Assumptions: + * Called with the MAC locked + * + ****************************************************************************/ + +static void xbee_notify(FAR struct xbee_priv_s *priv, + FAR struct ieee802154_primitive_s *primitive) +{ + while (nxsem_wait(&priv->primitive_sem) < 0); + + sq_addlast((FAR sq_entry_t *)primitive, &priv->primitive_queue); + nxsem_post(&priv->primitive_sem); + + if (work_available(&priv->notifwork)) + { + work_queue(LPWORK, &priv->notifwork, xbee_notify_worker, + (FAR void *)priv, 0); + } +} + +/**************************************************************************** + * Name: xbee_notify_worker + * + * Description: + * Pop each primitive off the queue and call the registered + * callbacks. There is special logic for handling ieee802154_data_ind_s. + * + ****************************************************************************/ + +static void xbee_notify_worker(FAR void *arg) +{ + FAR struct xbee_priv_s *priv = (FAR struct xbee_priv_s *)arg; + FAR struct xbee_maccb_s *cb; + FAR struct ieee802154_primitive_s *primitive; + int ret; + + DEBUGASSERT(priv != NULL); + + while (nxsem_wait(&priv->primitive_sem) < 0); + primitive = + (FAR struct ieee802154_primitive_s *)sq_remfirst(&priv->primitive_queue); + nxsem_post(&priv->primitive_sem); + + while (primitive != NULL) + { + /* Data indications are a special case since the frame can only be passed to + * one place. The return value of the notify call is used to accept or reject + * the primitive. In the case of the data indication, there can only be one + * accept. Callbacks are stored in order of there receiver priority ordered + * when the callbacks are bound in mac802154_bind(). + */ + + if (primitive->type == IEEE802154_PRIMITIVE_IND_DATA) + { + bool dispose = true; + + primitive->nclients = 1; + + for (cb = priv->cb; cb != NULL; cb = cb->flink) + { + if (cb->notify != NULL) + { + ret = cb->notify(cb, primitive); + if (ret >= 0) + { + /* The receiver accepted and disposed of the frame and it's + * meta-data. We are done. + */ + + dispose = false; + break; + } + } + } + + if (dispose) + { + iob_free(primitive->u.dataind.frame); + ieee802154_primitive_free(primitive); + } + } + else + { + /* Set the number of clients count so that the primitive resources will be + * preserved until all clients are finished with it. + */ + + primitive->nclients = priv->nclients; + + /* Try to notify every registered MAC client */ + + for (cb = priv->cb; cb != NULL; cb = cb->flink) + { + if (cb->notify != NULL) + { + ret = cb->notify(cb, primitive); + if (ret < 0) + { + ieee802154_primitive_free(primitive); + } + } + else + { + ieee802154_primitive_free(primitive); + } + } + } + + /* Get the next primitive then loop */ + + while (nxsem_wait(&priv->primitive_sem) < 0); + primitive = + (FAR struct ieee802154_primitive_s *)sq_remfirst(&priv->primitive_queue); + nxsem_post(&priv->primitive_sem); + } +} + +/**************************************************************************** + * Name: xbee_atquery_timeout + * + * Description: + * This function runs when an AT Query has timed out waiting for a response + * from the XBee module. This really should never happen, but if it does, + * handle it gracefully by retrying the query. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void xbee_atquery_timeout(int argc, uint32_t arg, ...) +{ + FAR struct xbee_priv_s *priv = (FAR struct xbee_priv_s *)arg; + + DEBUGASSERT(priv != NULL); + + wlwarn("AT Query timeout\n"); + + /* Wake the pending query thread so it can retry */ + + nxsem_post(&priv->atresp_sem); } /**************************************************************************** @@ -860,26 +1012,28 @@ XBEEHANDLE xbee_init(FAR struct spi_dev_s *spi, return NULL; } - /* Allow exclusive access to the struct */ - - nxsem_init(&priv->exclsem, 0, 1); - - /* Initialize the data indication and notifcation allocation pools */ + priv->lower = lower; + priv->spi = spi; - xbee_notifpool_init(priv); - xbee_dataindpool_init(priv); + nxsem_init(&priv->primitive_sem, 0, 1); + nxsem_init(&priv->atquery_sem, 0, 1); + nxsem_init(&priv->tx_sem, 0, 1); + nxsem_init(&priv->txdone_sem, 0, 0); + nxsem_setprotocol(&priv->txdone_sem, SEM_PRIO_NONE); - sq_init(&priv->waiter_queue); + ieee802154_primitivepool_initialize(); - priv->assocwd = wd_create(); + sq_init(&priv->primitive_queue); - priv->lower = lower; - priv->spi = spi; + priv->assocwd = wd_create(); + priv->atquery_wd = wd_create(); priv->frameid = 0; /* Frame ID should never be 0, but it is incremented * in xbee_next_frameid before being used so it will be 1 */ + priv->querycmd[0] = 0; + priv->querycmd[1] = 0; - /* Reset the XBee */ + /* Reset the XBee radio */ priv->lower->reset(priv->lower); @@ -892,7 +1046,7 @@ XBEEHANDLE xbee_init(FAR struct spi_dev_s *spi, * when a valid SPI frame is received. */ - xbee_at_query(priv, "VR"); + xbee_send_atquery(priv, "VR"); return (XBEEHANDLE)priv; } @@ -1097,167 +1251,93 @@ void xbee_send_apiframe(FAR struct xbee_priv_s *priv, } /**************************************************************************** - * Name: xbee_at_query + * Name: xbee_atquery * * Description: - * Helper function to query a AT Command value. + * Sends AT Query and waits for response from device * ****************************************************************************/ -void xbee_at_query(FAR struct xbee_priv_s *priv, FAR const char *atcommand) +int xbee_atquery(FAR struct xbee_priv_s *priv, FAR const char *atcommand) { - uint8_t frame[8]; - - frame[0] = XBEE_STARTBYTE; - frame[1] = 0; - frame[2] = 4; - frame[3] = XBEE_APIFRAME_ATCOMMMAND; - frame[4] = 1; - frame[5] = *atcommand; - frame[6] = *(atcommand + 1); - - xbee_insert_checksum(frame, 8); - - xbee_send_apiframe(priv, frame, 8); -} - -/**************************************************************************** - * Name: xbee_query_firmwareversion - * - * Description: - * Sends API frame with AT command request in order to get the firmware version - * from the device. - * - ****************************************************************************/ - -void xbee_query_firmwareversion(FAR struct xbee_priv_s *priv) -{ - struct xbee_respwaiter_s respwaiter; - - respwaiter.resp_id = XBEE_RESP_AT_FIRMWAREVERSION; - nxsem_init(&respwaiter.sem, 0, 0); - nxsem_setprotocol(&respwaiter.sem, SEM_PRIO_NONE); - - xbee_register_respwaiter(priv, &respwaiter); - xbee_at_query(priv, "VR"); - - nxsem_wait(&respwaiter.sem); - - xbee_unregister_respwaiter(priv, &respwaiter); - - nxsem_destroy(&respwaiter.sem); -} - -/**************************************************************************** - * Name: xbee_query_panid - * - * Description: - * Sends API frame with AT command request in order to get the PAN ID - * (Network ID) from the device. - * - ****************************************************************************/ - -void xbee_query_panid(FAR struct xbee_priv_s *priv) -{ - struct xbee_respwaiter_s respwaiter; - - respwaiter.resp_id = XBEE_RESP_AT_NETWORKID; - nxsem_init(&respwaiter.sem, 0, 0); - nxsem_setprotocol(&respwaiter.sem, SEM_PRIO_NONE); - - xbee_register_respwaiter(priv, &respwaiter); - xbee_at_query(priv, "ID"); - - nxsem_wait(&respwaiter.sem); - - xbee_unregister_respwaiter(priv, &respwaiter); - - nxsem_destroy(&respwaiter.sem); -} - -/**************************************************************************** - * Name: xbee_query_eaddr - * - * Description: - * Sends API frame with AT command request in order to get the IEEE 802.15.4 - * Extended Address. (Serial Number) from the device. - * - ****************************************************************************/ - -void xbee_query_eaddr(FAR struct xbee_priv_s *priv) -{ - struct xbee_respwaiter_s respwaiter; + int ret; - respwaiter.resp_id = XBEE_RESP_AT_SERIALHIGH; - nxsem_init(&respwaiter.sem, 0, 0); - nxsem_setprotocol(&respwaiter.sem, SEM_PRIO_NONE); + /* Only allow one query at a time */ - xbee_register_respwaiter(priv, &respwaiter); - xbee_at_query(priv, "SH"); + ret = nxsem_wait(&priv->atquery_sem); + if (ret < 0) + { + DEBUGASSERT(ret == -EINTR); + return ret; + } - nxsem_wait(&respwaiter.sem); + priv->querydone = false; - respwaiter.resp_id = XBEE_RESP_AT_SERIALLOW; - xbee_at_query(priv, "SL"); + /* We reinitialize this every time, in case something gets out of phase with + * the timeout and the received response. + */ - nxsem_wait(&respwaiter.sem); + nxsem_init(&priv->atresp_sem, 0, 0); + nxsem_setprotocol(&priv->atresp_sem, SEM_PRIO_NONE); - xbee_unregister_respwaiter(priv, &respwaiter); - nxsem_destroy(&respwaiter.sem); -} + do + { + /* Setup a timeout */ -/**************************************************************************** - * Name: xbee_query_saddr - * - * Description: - * Sends API frame with AT command request in order to get the - * Short Address. (Source Address (MY)) from the device. - * - ****************************************************************************/ + (void)wd_start(priv->atquery_wd, XBEE_ATQUERY_TIMEOUT, xbee_atquery_timeout, + 1, (wdparm_t)priv); -void xbee_query_saddr(FAR struct xbee_priv_s *priv) -{ - struct xbee_respwaiter_s respwaiter; + /* Send the query */ - respwaiter.resp_id = XBEE_RESP_AT_SOURCEADDR; - nxsem_init(&respwaiter.sem, 0, 0); - nxsem_setprotocol(&respwaiter.sem, SEM_PRIO_NONE); + priv->querycmd[0] = *atcommand; + priv->querycmd[1] = *(atcommand + 1); + xbee_send_atquery(priv, atcommand); - xbee_register_respwaiter(priv, &respwaiter); - xbee_at_query(priv, "MY"); + /* Wait for the response to be received */ - nxsem_wait(&respwaiter.sem); + ret = nxsem_wait(&priv->atresp_sem); + if (ret < 0) + { + DEBUGASSERT(ret == -EINTR); + wd_cancel(priv->atquery_wd); + priv->querycmd[0] = 0; + priv->querycmd[1] = 0; + nxsem_post(&priv->atquery_sem); + return ret; + } + } + while (!priv->querydone); - xbee_unregister_respwaiter(priv, &respwaiter); + nxsem_post(&priv->atquery_sem); - nxsem_destroy(&respwaiter.sem); + return OK; } /**************************************************************************** - * Name: xbee_query_chan + * Name: xbee_send_atquery * * Description: - * Sends API frame with AT command request in order to get the RF Channel - * (Operating Channel) from the device. + * Helper function to send the AT query to the XBee * ****************************************************************************/ -void xbee_query_chan(FAR struct xbee_priv_s *priv) +void xbee_send_atquery(FAR struct xbee_priv_s *priv, FAR const char *atcommand) { - struct xbee_respwaiter_s respwaiter; - - respwaiter.resp_id = XBEE_RESP_AT_CHAN; - nxsem_init(&respwaiter.sem, 0, 0); - nxsem_setprotocol(&respwaiter.sem, SEM_PRIO_NONE); + uint8_t frame[8]; - xbee_register_respwaiter(priv, &respwaiter); - xbee_at_query(priv, "CH"); + wlinfo("AT Query: %c%c\n", *atcommand, *(atcommand + 1)); - nxsem_wait(&respwaiter.sem); + frame[0] = XBEE_STARTBYTE; + frame[1] = 0; + frame[2] = 4; + frame[3] = XBEE_APIFRAME_ATCOMMMAND; + frame[4] = 1; + frame[5] = *atcommand; + frame[6] = *(atcommand + 1); - xbee_unregister_respwaiter(priv, &respwaiter); + xbee_insert_checksum(frame, 8); - nxsem_destroy(&respwaiter.sem); + xbee_send_apiframe(priv, frame, 8); } /**************************************************************************** @@ -1470,8 +1550,8 @@ void xbee_regdump(FAR struct xbee_priv_s *priv) wlinfo("XBee Firmware Version: %04x\n", priv->firmwareversion); - xbee_at_query(priv, "CE"); - xbee_at_query(priv, "A1"); - xbee_at_query(priv, "A2"); - xbee_at_query(priv, "SP"); + xbee_send_atquery(priv, "CE"); + xbee_send_atquery(priv, "A1"); + xbee_send_atquery(priv, "A2"); + xbee_send_atquery(priv, "SP"); } diff --git a/drivers/wireless/ieee802154/xbee/xbee.h b/drivers/wireless/ieee802154/xbee/xbee.h index 92c73851471fc508f7475fc27017ecd982ba3e8c..b0627229b2c7912bd21b860643e6e192113534c2 100644 --- a/drivers/wireless/ieee802154/xbee/xbee.h +++ b/drivers/wireless/ieee802154/xbee/xbee.h @@ -49,19 +49,17 @@ #include #include +#include #include -#include "xbee_notif.h" -#include "xbee_dataind.h" - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ /* Configuration *************************************************************/ -#ifndef CONFIG_SCHED_HPWORK -# error High priority work queue required in this driver +#if !defined(CONFIG_SCHED_HPWORK) || !defined(CONFIG_SCHED_LPWORK) +# error Both Low and High priority work queues are required for this driver #endif #ifndef CONFIG_IEEE802154_XBEE_FREQUENCY @@ -72,16 +70,6 @@ # error CONFIG_SPI_EXCHANGE required for this driver #endif -#if !defined(CONFIG_XBEE_NNOTIF) || CONFIG_XBEE_NNOTIF <= 0 -# undef CONFIG_XBEE_NNOTIF -# define CONFIG_XBEE_NNOTIF 6 -#endif - -#if !defined(CONFIG_XBEE_NDATAIND) || CONFIG_XBEE_NDATAIND <= 0 -# undef CONFIG_XBEE_NDATAIND -# define CONFIG_XBEE_NDATAIND 8 -#endif - #define XBEE_APIFRAME_MODEMSTATUS 0x8A #define XBEE_APIFRAME_ATCOMMMAND 0x08 #define XBEE_APIFRAME_ATCOMMMANDQUEUED 0x09 @@ -166,22 +154,29 @@ struct xbee_priv_s FAR const struct xbee_lower_s *lower; FAR struct spi_dev_s *spi; /* Saved SPI interface instance */ - FAR struct xbee_maccb_s *cb; /* Head of a list of XBee MAC callbacks */ + /* Fields related to interface with next layer */ + FAR struct xbee_maccb_s *cb; /* Head of a list of XBee MAC callbacks */ + uint8_t nclients; /* Number of registered callbacks */ FAR struct iob_s *rx_apiframes; /* List of incoming API frames to process */ - + struct work_s notifwork; /* For deferring notifications to LPWORK queue*/ struct work_s attnwork; /* For deferring interrupt work to work queue */ - sem_t exclsem; /* Exclusive access to this struct */ - + volatile bool attn_latched; /* Latched state of ATTN */ + sem_t primitive_sem; /* Exclusive access to the primitive queue */ + sq_queue_t primitive_queue; /* Queue of primitives to pass via notify() + * callback to registered receivers */ WDOG_ID assocwd; /* Association watchdog */ struct work_s assocwork; /* For polling for association status */ - - volatile bool attn_latched; /* Latched state of ATTN */ - - sq_queue_t waiter_queue; /* List of response waiters */ - - sq_queue_t tx_queue; /* List of pending TX requests */ + sem_t atquery_sem; /* Only allow one AT query at a time */ + sem_t atresp_sem; /* For signaling pending AT response received */ + char querycmd[2]; /* Stores the pending AT Query command */ + bool querydone; /* Used to tell waiting thread query is done*/ + WDOG_ID atquery_wd; /* Support AT Query timeout and retry */ uint8_t frameid; /* For differentiating AT request/response */ + sem_t tx_sem; /* Support a single pending transmit */ + sem_t txdone_sem; /* For signalling tx is completed */ + + /******************* Fields related to Xbee radio ***************************/ uint16_t firmwareversion; @@ -190,32 +185,8 @@ struct xbee_priv_s /* Holds all address information (Extended, Short, and PAN ID) for the MAC. */ struct ieee802154_addr_s addr; - struct ieee802154_pandesc_s pandesc; - /******************* Fields related to notifications ************************/ - - /* Pre-allocated notifications to be passed to the registered callback. These - * need to be freed by the application using xbee_xxxxnotif_free when - * the callee layer is finished with it's use. - */ - - FAR struct xbee_notif_s *notif_free; - struct xbee_notif_s notif_pool[CONFIG_XBEE_NNOTIF]; - sem_t notif_sem; - uint8_t nclients; - - /******************* Fields related to data indications *********************/ - - /* Pre-allocated notifications to be passed to the registered callback. These - * need to be freed by the application using xbee_dataind_free when - * the callee layer is finished with it's use. - */ - - FAR struct xbee_dataind_s *dataind_free; - struct xbee_dataind_s dataind_pool[CONFIG_XBEE_NDATAIND]; - sem_t dataind_sem; - /****************** Uncategorized MAC PIB attributes ***********************/ /* What type of device is this node acting as */ @@ -235,123 +206,6 @@ struct xbee_priv_s * Inline Functions ****************************************************************************/ -#define xbee_givesem(s) nxsem_post(s) - -static inline int xbee_takesem(sem_t *sem, bool allowinterrupt) -{ - int ret; - do - { - /* Take a count from the semaphore, possibly waiting */ - - ret = nxsem_wait(sem); - if (ret < 0) - { - /* EINTR is the only error that we expect */ - - DEBUGASSERT(ret == -EINTR); - - if (allowinterrupt) - { - return ret; - } - } - } - while (ret == -EINTR); - - return ret; -} - -#ifdef CONFIG_XBEE_LOCK_VERBOSE -#define xbee_unlock(dev) \ - xbee_givesem(&dev->exclsem); \ - wlinfo("MAC unlocked\n"); -#else -#define xbee_unlock(dev) \ - xbee_givesem(&dev->exclsem); -#endif - -#define xbee_lock(dev, allowinterrupt) \ - xbee_lockpriv(dev, allowinterrupt, __FUNCTION__) - -static inline int xbee_lockpriv(FAR struct xbee_priv_s *dev, - bool allowinterrupt, FAR const char *funcname) -{ - int ret; - -#ifdef CONFIG_XBEE_LOCK_VERBOSE - wlinfo("Locking MAC: %s\n", funcname); -#endif - ret = xbee_takesem(&dev->exclsem, allowinterrupt); - if (ret < 0) - { - wlwarn("Failed to lock MAC\n"); - } - else - { -#ifdef CONFIG_XBEE_LOCK_VERBOSE - wlinfo("MAC locked\n"); -#endif - } - - return ret; -} - -/**************************************************************************** - * Name: xbee_register_respwaiter - * - * Description: - * Register a respone waiter - * - ****************************************************************************/ - -static inline void xbee_register_respwaiter(FAR struct xbee_priv_s *priv, - FAR struct xbee_respwaiter_s *waiter) -{ - sq_addlast((sq_entry_t *)waiter, &priv->waiter_queue); -} - -/**************************************************************************** - * Name: xbee_unregister_respwaiter - * - * Description: - * Unregister a respone waiter - * - ****************************************************************************/ - -static inline void xbee_unregister_respwaiter(FAR struct xbee_priv_s *priv, - FAR struct xbee_respwaiter_s *waiter) -{ - sq_rem((sq_entry_t *)waiter, &priv->waiter_queue); -} - -/**************************************************************************** - * Name: xbee_notify_respwaiter - * - * Description: - * Check to see if there are any respwaiters waiting for this response type. - * If so, signal them. - * - ****************************************************************************/ - -static inline void xbee_notify_respwaiter(FAR struct xbee_priv_s *priv, - enum xbee_response_e resp_id) -{ - FAR struct xbee_respwaiter_s *waiter; - - waiter = (FAR struct xbee_respwaiter_s *)sq_peek(&priv->waiter_queue); - - while (waiter != NULL) - { - if (waiter->resp_id == resp_id) - { - nxsem_post(&waiter->sem); - } - - waiter = (FAR struct xbee_respwaiter_s *)sq_next((FAR sq_entry_t *)waiter); - } -} - /**************************************************************************** * Name: xbee_next_frameid * @@ -418,14 +272,24 @@ void xbee_send_apiframe(FAR struct xbee_priv_s *priv, FAR const uint8_t *frame, uint16_t framelen); /**************************************************************************** - * Name: xbee_at_query + * Name: xbee_atquery + * + * Description: + * Sends AT Query and waits for response from device + * + ****************************************************************************/ + +int xbee_atquery(FAR struct xbee_priv_s *priv, FAR const char *atcommand); + +/**************************************************************************** + * Name: xbee_send_atquery * * Description: - * Helper function to query a AT Command value. + * Helper function to send the AT query to the XBee * ****************************************************************************/ -void xbee_at_query(FAR struct xbee_priv_s *priv, FAR const char *atcommand); +void xbee_send_atquery(FAR struct xbee_priv_s *priv, FAR const char *atcommand); /**************************************************************************** * Name: xbee_query_firmwareversion @@ -436,7 +300,7 @@ void xbee_at_query(FAR struct xbee_priv_s *priv, FAR const char *atcommand); * ****************************************************************************/ -void xbee_query_firmwareversion(FAR struct xbee_priv_s *priv); +#define xbee_query_firmwareversion(priv) xbee_atquery(priv, "VR") /**************************************************************************** * Name: xbee_query_panid @@ -447,7 +311,7 @@ void xbee_query_firmwareversion(FAR struct xbee_priv_s *priv); * ****************************************************************************/ -void xbee_query_panid(FAR struct xbee_priv_s *priv); +#define xbee_query_panid(priv) xbee_atquery(priv, "ID") /**************************************************************************** * Name: xbee_query_eaddr @@ -458,7 +322,8 @@ void xbee_query_panid(FAR struct xbee_priv_s *priv); * ****************************************************************************/ -void xbee_query_eaddr(FAR struct xbee_priv_s *priv); +#define xbee_query_eaddr(priv) xbee_atquery(priv, "SH"); \ + xbee_atquery(priv, "SL") /**************************************************************************** * Name: xbee_query_saddr @@ -469,7 +334,7 @@ void xbee_query_eaddr(FAR struct xbee_priv_s *priv); * ****************************************************************************/ -void xbee_query_saddr(FAR struct xbee_priv_s *priv); +#define xbee_query_saddr(priv) xbee_atquery(priv, "MY") /**************************************************************************** * Name: xbee_query_chan @@ -480,7 +345,7 @@ void xbee_query_saddr(FAR struct xbee_priv_s *priv); * ****************************************************************************/ -void xbee_query_chan(FAR struct xbee_priv_s *priv); +#define xbee_query_chan(priv) xbee_atquery(priv, "CH") /**************************************************************************** * Name: xbee_query_assoc @@ -491,7 +356,7 @@ void xbee_query_chan(FAR struct xbee_priv_s *priv); * ****************************************************************************/ -void xbee_query_assoc(FAR struct xbee_priv_s *priv); +#define xbee_query_assoc(priv) xbee_atquery(priv "AI") /**************************************************************************** * Name: xbee_set_panid diff --git a/drivers/wireless/ieee802154/xbee/xbee_dataind.c b/drivers/wireless/ieee802154/xbee/xbee_dataind.c deleted file mode 100644 index 9bf626dc7749264b37820cd8a09f8b6db57f2ef2..0000000000000000000000000000000000000000 --- a/drivers/wireless/ieee802154/xbee/xbee_dataind.c +++ /dev/null @@ -1,203 +0,0 @@ -/**************************************************************************** - * drivers/wireless/ieee802154/xbee/xbee_dataind.c - * - * Copyright (C) 2017 Verge Inc. All rights reserved. - * Author: Anthony Merlino - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "xbee.h" -#include "xbee_mac.h" -#include "xbee_notif.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: xbee_dataind_free - * - * Description: - * When the XBee driver calls the registered rxframe function, it passes a - * reference to a ieee802154_data_ind_s structure. This structure needs to be - * freed after the handler is done using it. - * - ****************************************************************************/ - -void xbee_dataind_free(XBEEHANDLE xbee, FAR struct ieee802154_data_ind_s *dataind) -{ - FAR struct xbee_priv_s *priv = (FAR struct xbee_priv_s *)xbee; - FAR struct xbee_dataind_s *privind = (FAR struct xbee_dataind_s *)dataind; - - xbee_lock(priv, false); - - privind->flink = priv->dataind_free; - priv->dataind_free = privind; - - xbee_givesem(&priv->dataind_sem); - - xbee_unlock(priv); -} - -/**************************************************************************** - * Name: xbee_datatindpool_init - * - * Description: - * This function initializes the data indication structure pool. It allows the - * XBee driver to pass received frames with meta data to the callee, where they - * can free them when the calle is done using them, saving copying the data - * when passing. - * - ****************************************************************************/ - -void xbee_dataindpool_init(FAR struct xbee_priv_s *priv) -{ - FAR struct xbee_dataind_s *pool = priv->dataind_pool; - int remaining = CONFIG_XBEE_NDATAIND; - - priv->dataind_free = NULL; - while (remaining > 0) - { - FAR struct xbee_dataind_s *dataind = pool; - - /* Add the next meta data structure from the pool to the list of - * general structures. - */ - - dataind->flink = priv->dataind_free; - priv->dataind_free = dataind; - - /* Set up for the next structure from the pool */ - - pool++; - remaining--; - } - - nxsem_init(&priv->dataind_sem, 0, CONFIG_XBEE_NDATAIND); -} - -/**************************************************************************** - * Name: xbee_dataind_alloc - * - * Description: - * This function allocates a free data indication structure from the free list - * to be used for passing to the registered rxframe callback. The callee software - * is responsible for freeing the data indication structure after it is done using - * it via xbee_data_ind_sfree. - * - * Assumptions: - * priv XBee struct is locked when calling. - * - * Notes: - * If any of the semaphore waits inside this function get interrupted, the - * function will release the MAC layer. If this function returns -EINTR, the - * calling code should NOT release the MAC semaphore. - * - ****************************************************************************/ - -int xbee_dataind_alloc(FAR struct xbee_priv_s *priv, - FAR struct ieee802154_data_ind_s **dataind, - bool allow_interrupt) -{ - int ret; - FAR struct xbee_dataind_s *privind; - - /* Try and take a count from the semaphore. If this succeeds, we have - * "reserved" the structure, but still need to unlink it from the free list. - * The MAC is already locked, so there shouldn't be any other conflicting calls - */ - - ret = nxsem_trywait(&priv->dataind_sem); - - if (ret == OK) - { - privind = priv->dataind_free; - priv->dataind_free = privind->flink; - } - else - { - wlinfo("waiting for dataind to be free\n"); - - /* Unlock XBee driver so that other work can be done to free a data indication */ - - xbee_unlock(priv); - - /* Take a count from the indication semaphore, waiting if necessary. We - * only return from here with an error if we are allowing interruptions - * and we received a signal */ - - ret = xbee_takesem(&priv->dataind_sem, allow_interrupt); - if (ret < 0) - { - /* MAC sem is already released */ - - return -EINTR; - } - - /* If we've taken a count from the semaphore, we have "reserved" the struct - * but now we need to pop it off of the free list. We need to re-lock the - * MAC in order to ensure this happens correctly. - */ - - ret = xbee_lock(priv, allow_interrupt); - if (ret < 0) - { - xbee_givesem(&priv->dataind_sem); - return -EINTR; - } - - /* We can now safely unlink the next free structure from the free list */ - - privind = priv->dataind_free; - priv->dataind_free = privind->flink; - - wlinfo("dataind allocated\n"); - } - - *dataind = (FAR struct ieee802154_data_ind_s *)privind; - - return OK; -} diff --git a/drivers/wireless/ieee802154/xbee/xbee_mac.c b/drivers/wireless/ieee802154/xbee/xbee_mac.c index 1d22695a78a910844625e0bbc94c7ff584d28304..edcf7b1043fe3e3d39f29ce053b1063cbd34ce03 100644 --- a/drivers/wireless/ieee802154/xbee/xbee_mac.c +++ b/drivers/wireless/ieee802154/xbee/xbee_mac.c @@ -128,7 +128,7 @@ static void xbee_assoctimer(int argc, uint32_t arg, ...) * Description: * Poll the device for the assosciation status. This function is indirectly * scheduled rom xbee_req_associate in order to poll the device for association - * progress. + * progress. * * Parameters: * arg - The reference to the driver structure (cast to void*) @@ -144,7 +144,7 @@ static void xbee_assocworker(FAR void *arg) { FAR struct xbee_priv_s *priv = (FAR struct xbee_priv_s *)arg; - xbee_at_query(priv, "AI"); + xbee_send_atquery(priv, "AI"); (void)wd_start(priv->assocwd, XBEE_ASSOC_POLLDELAY, xbee_assoctimer, 1, (wdparm_t)arg); } @@ -268,6 +268,10 @@ int xbee_req_data(XBEEHANDLE xbee, int prevoffs = frame->io_offset; #endif + /* Support one pending transmit at a time */ + + while (nxsem_wait(&priv->tx_sem) < 0); + /* Figure out how much room we need to place the API frame header */ if (meta->destaddr.mode == IEEE802154_ADDRMODE_EXTENDED) @@ -326,6 +330,11 @@ int xbee_req_data(XBEEHANDLE xbee, xbee_send_apiframe(priv, &frame->io_data[frame->io_offset], (frame->io_len - frame->io_offset)); + /* Wait for a transmit status to be received. Does not necessarily mean success */ + + while (nxsem_wait(&priv->txdone_sem) < 0); + + nxsem_post(&priv->tx_sem); iob_free(frame); return OK; } diff --git a/drivers/wireless/ieee802154/xbee/xbee_mac.h b/drivers/wireless/ieee802154/xbee/xbee_mac.h index 6da504f1175ebe04326d7c2511c744538eb06c22..6548a50ad51c42b03bb3e923f418edde0aa3433c 100644 --- a/drivers/wireless/ieee802154/xbee/xbee_mac.h +++ b/drivers/wireless/ieee802154/xbee/xbee_mac.h @@ -70,12 +70,18 @@ struct xbee_maccb_s FAR struct xbee_maccb_s *flink; /* Implements a singly linked list */ uint8_t prio; /* RX frame callback priority */ - /* Callback methods */ - - CODE void (*notify)(FAR struct xbee_maccb_s *maccb, - FAR struct ieee802154_notif_s *notif); - CODE int (*rxframe)(FAR struct xbee_maccb_s *maccb, - FAR struct ieee802154_data_ind_s *ind); + /* Callback for various MLME or MCPS service events. Return value represents + * whether the callback accepts the primitive. >= 0 means the callback has + * accepted the primitive and is responsible for calling + * ieee802154_primitive_free(). In the case of DATA.indication primitive, only + * one callback can accept the frame. The callbacks are stored in order of + * receiver priority defined by the 'prio' field above. All other + * notifications are offered to all callbacks and all can accept and free + * separately since the primitive will not be freed until the nclients count + * reaches 0. */ + + CODE int (*notify)(FAR struct xbee_maccb_s *maccb, + FAR struct ieee802154_primitive_s *primitive); }; /**************************************************************************** @@ -235,28 +241,4 @@ int xbee_req_associate(XBEEHANDLE xbee, FAR struct ieee802154_assoc_req_s *req); int xbee_req_reset(XBEEHANDLE xbee, bool resetattr); -/**************************************************************************** - * Name: xbee_notif_free - * - * Description: - * When the XBee driver calls the registered callback, it passes a reference - * to a ieee802154_notif_s structure. This structure needs to be freed - * after the callback handler is done using it. - * - ****************************************************************************/ - -void xbee_notif_free(XBEEHANDLE mac, FAR struct ieee802154_notif_s *notif); - -/**************************************************************************** - * Name: xbee_dataind_free - * - * Description: - * When the XBee driver calls the registered callback, it passes a reference - * to a ieee802154_data_ind_s structure. This structure needs to be freed - * after the callback handler is done using it. - * - ****************************************************************************/ - -void xbee_dataind_free(XBEEHANDLE mac, FAR struct ieee802154_data_ind_s *dataind); - #endif /* __DRIVERS_WIRELESS_IEEE802154_XBEE_MAC_H */ diff --git a/drivers/wireless/ieee802154/xbee/xbee_netdev.c b/drivers/wireless/ieee802154/xbee/xbee_netdev.c index 779dfcb5fe6c752838a77103700795b7fde7142a..d408d21ec34f7831882623e891b78107859b6edd 100644 --- a/drivers/wireless/ieee802154/xbee/xbee_netdev.c +++ b/drivers/wireless/ieee802154/xbee/xbee_netdev.c @@ -140,12 +140,12 @@ struct xbeenet_driver_s { /* This holds the information visible to the NuttX network */ - struct radio_driver_s xd_dev; /* Interface understood by the network */ - /* Cast compatible with struct xbeenet_driver_s */ + struct radio_driver_s xd_dev; /* Interface understood by the network + * Cast compatible with struct xbeenet_driver_s */ /* For internal use by this driver */ - sem_t xd_exclsem; /* Exclusive access to struct */ + sem_t xd_exclsem; /* Exclusive access to struct */ struct xbeenet_callback_s xd_cb; /* Callback information */ XBEEHANDLE xd_mac; /* Contained XBee MAC interface */ bool xd_bifup; /* true:ifup false:ifdown */ @@ -154,11 +154,10 @@ struct xbeenet_driver_s /* Hold a list of events */ - bool xd_enableevents : 1; /* Are events enabled? */ - bool xd_eventpending : 1; /* Is there a get event using the semaphore? */ - sem_t xd_eventsem; /* Signaling semaphore for waiting get event */ - FAR struct ieee802154_notif_s *xd_eventhead; - FAR struct ieee802154_notif_s *xd_eventtail; + bool xd_enableevents : 1; /* Are events enabled? */ + bool xd_eventpending : 1; /* Is there a get event using the semaphore? */ + sem_t xd_eventsem; /* Signaling semaphore for waiting get event */ + sq_queue_t primitive_queue; /* For holding primitives to pass along */ #ifndef CONFIG_DISABLE_SIGNALS /* MAC Service notification information */ @@ -178,23 +177,13 @@ struct xbeenet_driver_s static int xbeenet_set_ipaddress(FAR struct net_driver_s *dev); static inline void xbeenet_netmask(FAR struct net_driver_s *dev); -static inline void xbeenet_pushevent(FAR struct xbeenet_driver_s *priv, - FAR struct ieee802154_notif_s *notif); -static inline FAR struct ieee802154_notif_s * - xbeenet_popevent(FAR struct xbeenet_driver_s *priv); - - /* IEE802.15.4 MAC callback functions ***************************************/ -static void xbeenet_notify(FAR struct xbee_maccb_s *maccb, - FAR struct ieee802154_notif_s *notif); -static int xbeenet_rxframe(FAR struct xbee_maccb_s *maccb, +static int xbeenet_notify(FAR struct xbee_maccb_s *maccb, + FAR struct ieee802154_primitive_s *primitive); +static int xbeenet_rxframe(FAR struct xbeenet_driver_s *maccb, FAR struct ieee802154_data_ind_s *ind); -/* Asynchronous event indications, replied to synchronously with responses. - * (none are implemented). - */ - /* Network interface support ************************************************/ /* Common TX logic */ @@ -390,63 +379,6 @@ static inline void xbeenet_netmask(FAR struct net_driver_s *dev) #endif } -/**************************************************************************** - * Name: xbeenet_pushevent - * - * Description: - * Push event onto the event queue - * - * Assumptions: - * Called with the device struct locked. - * - ****************************************************************************/ - -static inline void xbeenet_pushevent(FAR struct xbeenet_driver_s *priv, - FAR struct ieee802154_notif_s *notif) -{ - notif->flink = NULL; - if (!priv->xd_eventhead) - { - priv->xd_eventhead = notif; - priv->xd_eventtail = notif; - } - else - { - priv->xd_eventtail->flink = notif; - priv->xd_eventtail = notif; - } -} - -/**************************************************************************** - * Name: xbeenet_popevent - * - * Description: - * Pop an event off of the event queue - * - * Assumptions: - * Called with the device struct locked. - * - ****************************************************************************/ - -static inline FAR struct ieee802154_notif_s * - xbeenet_popevent(FAR struct xbeenet_driver_s *priv) -{ - FAR struct ieee802154_notif_s *notif = priv->xd_eventhead; - - if (notif) - { - priv->xd_eventhead = notif->flink; - if (!priv->xd_eventhead) - { - priv->xd_eventhead = NULL; - } - - notif->flink = NULL; - } - - return notif; -} - /**************************************************************************** * Name: xbeenet_notify * @@ -454,8 +386,8 @@ static inline FAR struct ieee802154_notif_s * * ****************************************************************************/ -static void xbeenet_notify(FAR struct xbee_maccb_s *maccb, - FAR struct ieee802154_notif_s *notif) +static int xbeenet_notify(FAR struct xbee_maccb_s *maccb, + FAR struct ieee802154_primitive_s *primitive) { FAR struct xbeenet_callback_s *cb = (FAR struct xbeenet_callback_s *)maccb; @@ -464,20 +396,28 @@ static void xbeenet_notify(FAR struct xbee_maccb_s *maccb, DEBUGASSERT(cb != NULL && cb->mc_priv != NULL); priv = cb->mc_priv; - /* Get exclusive access to the driver structure. We don't care about any - * signals so if we see one, just go back to trying to get access again */ + /* Handle the special case for data indications or "incoming frames" */ - while (nxsem_wait(&priv->xd_exclsem) < 0); + if (primitive->type == IEEE802154_PRIMITIVE_IND_DATA) + { + return xbeenet_rxframe(priv, &primitive->u.dataind); + } - /* If there is a registered notification receiver, queue the event and signal + /* If there is a registered primitive receiver, queue the event and signal * the receiver. Events should be popped from the queue from the application * at a reasonable rate in order for the MAC layer to be able to allocate new - * notifications. + * primitives. */ if (priv->xd_enableevents) { - xbeenet_pushevent(priv, notif); + /* Get exclusive access to the driver structure. We don't care about any + * signals so if we see one, just go back to trying to get access again + */ + + while (nxsem_wait(&priv->xd_exclsem) < 0); + + sq_addlast((FAR sq_entry_t *)primitive, &priv->primitive_queue); /* Check if there is a read waiting for data */ @@ -494,26 +434,25 @@ static void xbeenet_notify(FAR struct xbee_maccb_s *maccb, { #ifdef CONFIG_CAN_PASS_STRUCTS union sigval value; - value.sival_int = (int)notif->notiftype; + value.sival_int = (int)primitive->type; (void)nxsig_queue(priv->xd_notify_pid, priv->xd_notify_signo, value); #else (void)nxsig_queue(priv->xd_notify_pid, priv->xd_notify_signo, - (FAR void *)notif->notiftype); + (FAR void *)primitive->type); #endif } #endif - } - else - { - /* Just free the event if the driver is closed and there isn't a registered - * signal number. - */ - xbee_notif_free(priv->xd_mac, notif); + nxsem_post(&priv->xd_exclsem); + return OK; } - nxsem_post(&priv->xd_exclsem); + /* By returning a negative value, we let the MAC know that we don't want the + * primitive and it will free it for us + */ + + return -1; } /**************************************************************************** @@ -529,18 +468,12 @@ static void xbeenet_notify(FAR struct xbee_maccb_s *maccb, * ****************************************************************************/ -static int xbeenet_rxframe(FAR struct xbee_maccb_s *maccb, +static int xbeenet_rxframe(FAR struct xbeenet_driver_s *priv, FAR struct ieee802154_data_ind_s *ind) { - FAR struct xbeenet_callback_s *cb = - (FAR struct xbeenet_callback_s *)maccb; - FAR struct xbeenet_driver_s *priv; FAR struct iob_s *iob; int ret; - DEBUGASSERT(cb != NULL && cb->mc_priv != NULL); - priv = cb->mc_priv; - /* Ignore the frame if the network is not up */ if (!priv->xd_bifup) @@ -558,6 +491,8 @@ static int xbeenet_rxframe(FAR struct xbee_maccb_s *maccb, ind->frame = NULL; + net_lock(); + /* Transfer the frame to the network logic */ #ifdef CONFIG_NET_IEEE802154 @@ -595,9 +530,11 @@ static int xbeenet_rxframe(FAR struct xbee_maccb_s *maccb, } } + if (ret < 0) #endif { + net_unlock(); ind->frame = iob; return ret; } @@ -607,11 +544,13 @@ static int xbeenet_rxframe(FAR struct xbee_maccb_s *maccb, NETDEV_RXPACKETS(&priv->xd_dev.r_dev); NETDEV_RXIPV6(&priv->xd_dev.r_dev); + net_unlock(); + /* sixlowpan_input() will free the IOB, but we must free the struct - * ieee802154_data_ind_s container here. + * ieee802154_primitive_s container here. */ - xbee_dataind_free(priv->xd_mac, ind); + ieee802154_primitive_free((FAR struct ieee802154_primitive_s *)ind); return OK; } @@ -1134,25 +1073,27 @@ static int xbeenet_ioctl(FAR struct net_driver_s *dev, int cmd, #endif case MAC802154IOC_GET_EVENT: { - FAR struct ieee802154_notif_s *notif; + FAR struct ieee802154_primitive_s *primitive; while (1) { /* Try popping an event off the queue */ - notif = xbeenet_popevent(priv); + primitive = (FAR struct ieee802154_primitive_s *) + sq_remfirst(&priv->primitive_queue); /* If there was an event to pop off, copy it into the user * data and free it from the MAC layer's memory. */ - if (notif != NULL) + if (primitive != NULL) { - memcpy(&netmac->u, notif, sizeof(struct ieee802154_notif_s)); + memcpy(&netmac->u, primitive, + sizeof(struct ieee802154_primitive_s)); - /* Free the notification */ + /* Free the primitive */ - xbee_notif_free(priv->xd_mac, notif); + ieee802154_primitive_free(primitive); ret = OK; break; } @@ -1478,8 +1419,7 @@ int xbee_netdev_register(XBEEHANDLE xbee) nxsem_init(&priv->xd_eventsem, 0, 0); nxsem_setprotocol(&priv->xd_eventsem, SEM_PRIO_NONE); - priv->xd_eventhead = NULL; - priv->xd_eventtail = NULL; + sq_init(&priv->primitive_queue); priv->xd_enableevents = false; priv->xd_notify_registered = false; @@ -1492,7 +1432,6 @@ int xbee_netdev_register(XBEEHANDLE xbee) maccb->flink = NULL; maccb->prio = CONFIG_XBEE_NETDEV_RECVRPRIO; maccb->notify = xbeenet_notify; - maccb->rxframe = xbeenet_rxframe; /* Bind the callback structure */ diff --git a/drivers/wireless/ieee802154/xbee/xbee_notif.c b/drivers/wireless/ieee802154/xbee/xbee_notif.c deleted file mode 100644 index d886d71007bda232c5e26119a18b9ea93d1f55c1..0000000000000000000000000000000000000000 --- a/drivers/wireless/ieee802154/xbee/xbee_notif.c +++ /dev/null @@ -1,284 +0,0 @@ -/**************************************************************************** - * drivers/wireless/ieee802154/xbee/xbee_notif.c - * - * Copyright (C) 2017 Verge Inc. All rights reserved. - * Author: Anthony Merlino - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include "xbee.h" -#include "xbee_mac.h" -#include "xbee_notif.h" - -#include -#include -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: xbee_notif_free - * - * Description: - * When the XBee driver calls the registered callback, it passes a reference - * to a ieee802154_notif_s structure. This structure needs to be freed - * after the callback handler is done using it. - * - ****************************************************************************/ - -void xbee_notif_free(XBEEHANDLE xbee, FAR struct ieee802154_notif_s *notif) -{ - FAR struct xbee_priv_s *priv = (FAR struct xbee_priv_s *)xbee; - - /* Lock the MAC */ - - xbee_lock(priv, false); - - /* Call the internal helper function to free the notification */ - - xbee_notif_free_locked(priv, notif); - - /* Unlock the MAC */ - - xbee_unlock(priv) -} - -/**************************************************************************** - * Internal MAC Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: xbee_notifpool_init - * - * Description: - * This function initializes the notification structure pool. It allows the - * XBee driver to pass notifications and for the callee to free them when they - * are done using them, saving copying the data when passing. - * - ****************************************************************************/ - -void xbee_notifpool_init(FAR struct xbee_priv_s *priv) -{ - FAR struct xbee_notif_s *pool = priv->notif_pool; - int remaining = CONFIG_XBEE_NNOTIF; - - priv->notif_free = NULL; - while (remaining > 0) - { - FAR struct xbee_notif_s *notif = pool; - - /* Add the next meta data structure from the pool to the list of - * general structures. - */ - - notif->flink = priv->notif_free; - priv->notif_free = notif; - - /* Set up for the next structure from the pool */ - - pool++; - remaining--; - } - - nxsem_init(&priv->notif_sem, 0, CONFIG_XBEE_NNOTIF); -} - -/**************************************************************************** - * Name: xbee_notif_alloc - * - * Description: - * This function allocates a free notification structure from the free list - * to be used for passing to the registered notify callback. The callee software - * is responsible for freeing the notification structure after it is done using - * it via xbee_notif_free. - * - * Assumptions: - * priv XBee struct is locked when calling. - * - * Notes: - * If any of the semaphore waits inside this function get interrupted, the - * function will release the MAC layer. If this function returns -EINTR, the - * calling code should NOT release the MAC semaphore. - * - ****************************************************************************/ - -int xbee_notif_alloc(FAR struct xbee_priv_s *priv, - FAR struct ieee802154_notif_s **notif, - bool allow_interrupt) -{ - int ret; - FAR struct xbee_notif_s *privnotif; - - /* Try and take a count from the semaphore. If this succeeds, we have - * "reserved" the structure, but still need to unlink it from the free list. - * The MAC is already locked, so there shouldn't be any other conflicting calls - */ - - ret = nxsem_trywait(&priv->notif_sem); - - if (ret == OK) - { - privnotif = priv->notif_free; - priv->notif_free = privnotif->flink; - privnotif->nclients = 0; - } - else - { - /* Unlock XBee driver so that other work can be done to free a notification */ - - xbee_unlock(priv) - - /* Take a count from the notification semaphore, waiting if necessary. We - * only return from here with an error if we are allowing interruptions - * and we received a signal */ - - ret = xbee_takesem(&priv->notif_sem, allow_interrupt); - if (ret < 0) - { - /* MAC sem is already released */ - - return -EINTR; - } - - /* If we've taken a count from the semaphore, we have "reserved" the struct - * but now we need to pop it off of the free list. We need to re-lock the - * MAC in order to ensure this happens correctly. - */ - - ret = xbee_lock(priv, allow_interrupt); - if (ret < 0) - { - xbee_givesem(&priv->notif_sem); - return -EINTR; - } - - /* We can now safely unlink the next free structure from the free list */ - - privnotif = priv->notif_free; - priv->notif_free = privnotif->flink; - privnotif->nclients = 0; - } - - *notif = (FAR struct ieee802154_notif_s *)privnotif; - - return OK; -} - -/**************************************************************************** - * Name: xbee_notif_free_locked - * - * Description: - * When the XBee driver calls the registered callback, it passes a reference - * to a ieee802154_notif_s structure. This structure needs to be freed - * after the callback handler is done using it. - * - * Internal version that already has XBee driver locked - * - ****************************************************************************/ - -void xbee_notif_free_locked(FAR struct xbee_priv_s * priv, - FAR struct ieee802154_notif_s *notif) -{ - FAR struct xbee_notif_s *privnotif = - (FAR struct xbee_notif_s *)notif; - - /* We know how many clients have registered for notifications. Each must - * call xbee_notif_free() before we can release the notification - * resource. - */ - - if (privnotif->nclients < 2) - { - /* This is the free from the last notification */ - - privnotif->flink = priv->notif_free; - priv->notif_free = privnotif; - privnotif->nclients = 0; - - xbee_givesem(&priv->notif_sem); - } - else - { - /* More calls are expected. Decrement the count of expected calls - * and preserve the notification resources. - */ - - privnotif->nclients--; - } -} - -/**************************************************************************** - * Name: xbee_notify - * - * Description: - * Notify every register XBee MAC client. - * - ****************************************************************************/ - -void xbee_notify(FAR struct xbee_priv_s *priv, - FAR struct ieee802154_notif_s *notif) -{ - FAR struct xbee_maccb_s *cb; - FAR struct xbee_notif_s *privnotif = (FAR struct xbee_notif_s *)notif; - - /* Set the notification count so that the notification resources will be - * preserved until the final notification. - */ - - privnotif->nclients = priv->nclients; - - /* Try to notify every registered XBee MAC client */ - - for (cb = priv->cb; cb != NULL; cb = cb->flink) - { - /* Does this client want notifications? */ - - if (cb->notify != NULL) - { - /* Yes.. Notify */ - - cb->notify(cb, notif); - } - } -} diff --git a/drivers/wireless/ieee802154/xbee/xbee_notif.h b/drivers/wireless/ieee802154/xbee/xbee_notif.h deleted file mode 100644 index 4a55b03dd0883b8f605362c2a0f450838d9afc85..0000000000000000000000000000000000000000 --- a/drivers/wireless/ieee802154/xbee/xbee_notif.h +++ /dev/null @@ -1,84 +0,0 @@ -/**************************************************************************** - * drivers/wireless/ieee802154/xbee/xbee_notif.h - * - * Copyright (C) 2017 Verge Inc. All rights reserved. - * - * Author: Anthony Merlino - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __DRIVERS_WIRELESS_IEEE802154_XBEE_NOTIF_H -#define __DRIVERS_WIRELESS_IEEE802154_XBEE_NOTIF_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Extend the public ieee802154_notif_s to include a private forward link to - * support a list to handle allocation - */ - -struct xbee_notif_s -{ - struct ieee802154_notif_s pub; /* Publically visible structure */ - FAR struct xbee_notif_s *flink; /* Supports a singly linked list */ - uint8_t nclients; -}; - -/**************************************************************************** - * Function Prototypes - ****************************************************************************/ - -struct xbee_priv_s; /* Forward Reference */ - -void xbee_notifpool_init(FAR struct xbee_priv_s *priv); - -int xbee_notif_alloc(FAR struct xbee_priv_s *priv, - FAR struct ieee802154_notif_s **notif, - bool allow_interrupt); - -void xbee_notify(FAR struct xbee_priv_s *priv, - FAR struct ieee802154_notif_s *notif); - -void xbee_notif_free_locked(FAR struct xbee_priv_s * priv, - FAR struct ieee802154_notif_s *notif); - -#endif /* __DRIVERS_WIRELESS_IEEE802154_XBEE_NOTIF_H */ \ No newline at end of file diff --git a/fs/Kconfig b/fs/Kconfig index cb9963187c049f2cfe78d0dbb46fa58d21f3299a..1bada41f4aa5efa6bbbad9f6f0d4ef9a3576faf5 100644 --- a/fs/Kconfig +++ b/fs/Kconfig @@ -86,4 +86,5 @@ source fs/smartfs/Kconfig source fs/binfs/Kconfig source fs/procfs/Kconfig source fs/unionfs/Kconfig +source fs/userfs/Kconfig source fs/hostfs/Kconfig diff --git a/fs/Makefile b/fs/Makefile index 6ab682d28f227d857110bb73917f66ccb26b4054..bba917231c39549f41b16b9550fab76467c5f227 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -1,7 +1,8 @@ ############################################################################ # fs/Makefile # -# Copyright (C) 2007, 2008, 2011-2014, 2016-2017 Gregory Nutt. All rights reserved. +# Copyright (C) 2007, 2008, 2011-2014, 2016-2017 Gregory Nutt. All rights +# reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -71,6 +72,7 @@ include smartfs/Make.defs include binfs/Make.defs include procfs/Make.defs include unionfs/Make.defs +include userfs/Make.defs include hostfs/Make.defs endif diff --git a/fs/binfs/fs_binfs.c b/fs/binfs/fs_binfs.c index f084710792c9abff84fe9f35fe8705982b42d813..5aa26300b8d81195d39bdba617d7ef92dd930b6e 100644 --- a/fs/binfs/fs_binfs.c +++ b/fs/binfs/fs_binfs.c @@ -1,7 +1,8 @@ /**************************************************************************** * fs/binfs/fs_binfs.c * - * Copyright (C) 2011-2013, 2015, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2013, 2015, 2017-2018 Gregory Nutt. All rights + * reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -110,6 +111,7 @@ const struct mountpt_operations binfs_operations = NULL, /* sync */ binfs_dup, /* dup */ binfs_fstat, /* fstat */ + NULL, /* truncate */ binfs_opendir, /* opendir */ NULL, /* closedir */ diff --git a/fs/fat/Kconfig b/fs/fat/Kconfig index 1c20a9ddd1c9c81e9da4c3208dda413880b859d2..f24e6772bcd8a98ec58ec34028c413202ec3fc20 100644 --- a/fs/fat/Kconfig +++ b/fs/fat/Kconfig @@ -34,6 +34,7 @@ config FAT_MAXFNAME int "FAT maximum file name size" depends on FAT_LFN default 32 + range 12 255 ---help--- If FAT_LFN is defined, then the default, maximum long file name is 255 bytes. This can eat up a lot of memory (especially stack @@ -42,6 +43,9 @@ config FAT_MAXFNAME good choice would be the same value as selected for NAME_MAX which will limit the visibility of longer file names anyway. + This setting may not exceed NAME_MAX. That will be verified at compile + time. The minimum values is 12 due to assumptions in internal logic. + config FS_FATTIME bool "FAT timestamps" default n diff --git a/fs/fat/fs_fat32.c b/fs/fat/fs_fat32.c index bbc0d0aa648527c1fcc130651853b544ba79b739..30c8ce1c3a83c1c09533aec6d0289745c96f02db 100644 --- a/fs/fat/fs_fat32.c +++ b/fs/fat/fs_fat32.c @@ -1,7 +1,8 @@ /**************************************************************************** * fs/fat/fs_fat32.c * - * Copyright (C) 2007-2009, 2011-2015, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011-2015, 2017-2018 Gregory Nutt. All rights + * reserved. * Author: Gregory Nutt * * References: @@ -86,6 +87,7 @@ static int fat_sync(FAR struct file *filep); static int fat_dup(FAR const struct file *oldp, FAR struct file *newp); static int fat_fstat(FAR const struct file *filep, FAR struct stat *buf); +static int fat_truncate(FAR struct file *filep, off_t length); static int fat_opendir(FAR struct inode *mountpt, FAR const char *relpath, FAR struct fs_dirent_s *dir); @@ -138,6 +140,7 @@ const struct mountpt_operations fat_operations = fat_sync, /* sync */ fat_dup, /* dup */ fat_fstat, /* fstat */ + fat_truncate, /* truncate */ fat_opendir, /* opendir */ NULL, /* closedir */ @@ -257,7 +260,7 @@ static int fat_open(FAR struct file *filep, FAR const char *relpath, { /* Truncate the file to zero length */ - ret = fat_dirtruncate(fs, &dirinfo); + ret = fat_dirtruncate(fs, direntry); if (ret < 0) { goto errout_with_semaphore; @@ -792,7 +795,7 @@ static ssize_t fat_write(FAR struct file *filep, FAR const char *buffer, ff->ff_sectorsincluster = fs->fs_fatsecperclus; } - /* The current sector can then be determined from the currentcluster + /* The current sector can then be determined from the current cluster * and the file offset. */ @@ -1068,10 +1071,13 @@ static off_t fat_seek(FAR struct file *filep, off_t offset, int whence) * also happen in other situation such as when SEEK_SET is used to assure * assure sequential access in a multi-threaded environment where there * may be are multiple users to the file descriptor. + * Effectively handles the situation when a new file position is within + * the current sector. */ - if (position == filep->f_pos) + if (position / fs->fs_hwsectorsize == filep->f_pos / fs->fs_hwsectorsize) { + filep->f_pos = position; return OK; } @@ -1620,7 +1626,7 @@ errout_with_semaphore: * * Description: * Obtain information about an open file associated with the file - * descriptor 'fd', and will write it to the area pointed to by 'buf'. + * structure 'filep', and will write it to the area pointed to by 'buf'. * ****************************************************************************/ @@ -1685,6 +1691,139 @@ errout_with_semaphore: return ret; } +/**************************************************************************** + * Name: fat_truncate + * + * Description: + * Set the length of the open, regular file associated with the file + * structure 'filep' to 'length'. + * + ****************************************************************************/ + +static int fat_truncate(FAR struct file *filep, off_t length) +{ + FAR struct inode *inode; + FAR struct fat_mountpt_s *fs; + FAR struct fat_file_s *ff; + off_t oldsize; + int ret; + + DEBUGASSERT(filep->f_priv != NULL && filep->f_inode != NULL); + + /* Recover our private data from the struct file instance */ + + ff = filep->f_priv; + + /* Check for the forced mount condition */ + + if ((ff->ff_bflags & UMOUNT_FORCED) != 0) + { + return -EPIPE; + } + + inode = filep->f_inode; + fs = inode->i_private; + + DEBUGASSERT(fs != NULL); + + /* Make sure that the mount is still healthy */ + + fat_semtake(fs); + ret = fat_checkmount(fs); + if (ret != OK) + { + goto errout_with_semaphore; + } + + /* Check if the file was opened for write access */ + + if ((ff->ff_oflags & O_WROK) == 0) + { + ret = -EACCES; + goto errout_with_semaphore; + } + + /* Are we shrinking the file? Or extending it? */ + + oldsize = ff->ff_size; + if (oldsize == length) + { + /* Do nothing but say that we did */ + + ret = OK; + } + else if (oldsize > length) + { + FAR uint8_t *direntry; + int ndx; + + /* We are shrinking the file. */ + /* Read the directory entry into the fs_buffer. */ + + ret = fat_fscacheread(fs, ff->ff_dirsector); + if (ret < 0) + { + goto errout_with_semaphore; + } + + /* Recover a pointer to the specific directory entry in the sector + * using the saved directory index. + */ + + ndx = (ff->ff_dirindex & DIRSEC_NDXMASK(fs)) * DIR_SIZE; + direntry = &fs->fs_buffer[ndx]; + + /* Handle the simple case where we are shrinking the file to zero + * length. + */ + + if (length == 0) + { + /* Shrink to length == 0 */ + + ret = fat_dirtruncate(fs, direntry); + } + else + { + /* Shrink to 0 < length < oldsize */ + + ret = fat_dirshrink(fs, direntry, length); + } + + if (ret >= 0) + { + /* The truncation has completed without error. Update the file + * size. + */ + + ff->ff_size = length; + ret = OK; + } + } + else + { + /* Otherwise we are extending the file. This is essentially the same + * as a write except that (1) we write zeros and (2) we don't update + * the file position. + */ + + ret = fat_dirextend(fs, ff, length); + if (ret >= 0) + { + /* The truncation has completed without error. Update the file + * size. + */ + + ff->ff_size = length; + ret = OK; + } + } + +errout_with_semaphore: + fat_semgive(fs); + return ret; +} + /**************************************************************************** * Name: fat_readdir * diff --git a/fs/fat/fs_fat32.h b/fs/fat/fs_fat32.h index 5b13b0a6c2a481a762148acc0a6bb352a80cc80f..84cf0751abc571af683ecb8ddc4da4bfcd39cd75 100644 --- a/fs/fat/fs_fat32.h +++ b/fs/fat/fs_fat32.h @@ -1,7 +1,7 @@ /**************************************************************************** * fs/fat/fs_fat32.h * - * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -58,8 +58,8 @@ /**************************************************************************** * These offsets describes the master boot record. * - * The folowing fields are common to FAT12/16/32 (but all value descriptions - * refer to the interpretation under FAT32. + * The following fields are common to FAT12/16/32 (but all value descriptions + * refer to the interpretation under FAT32). */ #define BS_JUMP 0 /* 3@0: Jump instruction to boot code (ignored) */ @@ -229,6 +229,17 @@ /* Sizes and limits */ +# if CONFIG_FAT_MAXFNAME > CONFIG_NAME_MAX && CONFIG_NAME_MAX >= 12 +# warning CONFIG_FAT_MAXFNAME may not exceed NAME_MAX (CONFIG_NAME_MAX) +# undef CONFIG_FAT_MAXFNAME +# define CONFIG_FAT_MAXFNAME CONFIG_NAME_MAX +# endif + +# if CONFIG_FAT_MAXFNAME < 12 +# undef CONFIG_FAT_MAXFNAME +# define CONFIG_FAT_MAXFNAME 12 +# endif + # ifndef CONFIG_FAT_MAXFNAME /* The maximum support filename can be limited */ # define LDIR_MAXFNAME 255 /* Max unicode characters in file name */ # elif CONFIG_FAT_MAXFNAME <= 255 @@ -916,7 +927,11 @@ EXTERN int fat_dirname2path(struct fat_mountpt_s *fs, struct fs_dirent_s *dir /* File creation and removal helpers */ -EXTERN int fat_dirtruncate(struct fat_mountpt_s *fs, struct fat_dirinfo_s *dirinfo); +EXTERN int fat_dirtruncate(struct fat_mountpt_s *fs, FAR uint8_t *direntry); +EXTERN int fat_dirshrink(struct fat_mountpt_s *fs, FAR uint8_t *direntry, + off_t length); +EXTERN int fat_dirextend(FAR struct fat_mountpt_s *fs, FAR struct fat_file_s *ff, + off_t length); EXTERN int fat_dircreate(struct fat_mountpt_s *fs, struct fat_dirinfo_s *dirinfo); EXTERN int fat_remove(struct fat_mountpt_s *fs, const char *relpath, bool directory); diff --git a/fs/fat/fs_fat32util.c b/fs/fat/fs_fat32util.c index ad4701c958b0632dbe32a38539080c67fb126d60..cdbfc2d4cb580718d24520b8a8545f8e66d5c528 100644 --- a/fs/fat/fs_fat32util.c +++ b/fs/fat/fs_fat32util.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/fat/fs_fat32util.c * - * Copyright (C) 2007-2009, 2011, 2013, 2015, 2017 Gregory Nutt. All + * Copyright (C) 2007-2009, 2011, 2013, 2015, 2017-2018 Gregory Nutt. All * rights reserved. * Author: Gregory Nutt * @@ -824,7 +824,7 @@ off_t fat_getcluster(struct fat_mountpt_s *fs, uint32_t clusterno) if (clusterno >= 2 && clusterno < fs->fs_nclusters) { /* Okay.. Read the next cluster from the FAT. The way we will do - * this depends on the type of FAT filesystm we are dealing with. + * this depends on the type of FAT filesystem we are dealing with. */ switch (fs->fs_type) @@ -1126,6 +1126,7 @@ int fat_removechain(struct fat_mountpt_s *fs, uint32_t cluster) if (nextcluster < 0) { /* Error! */ + return nextcluster; } @@ -1148,7 +1149,7 @@ int fat_removechain(struct fat_mountpt_s *fs, uint32_t cluster) /* Then set up to remove the next cluster */ cluster = nextcluster; - } + } return OK; } @@ -1415,7 +1416,7 @@ int fat_nextdirentry(struct fat_mountpt_s *fs, struct fs_fatdir_s *dir) * Name: fat_dirtruncate * * Description: - * Truncate an existing file to zero length + * Truncate an existing file to zero length. * * Assumptions: * The caller holds mountpoint semaphore, fs_buffer holds the directory @@ -1424,20 +1425,17 @@ int fat_nextdirentry(struct fat_mountpt_s *fs, struct fs_fatdir_s *dir) * ****************************************************************************/ -int fat_dirtruncate(struct fat_mountpt_s *fs, struct fat_dirinfo_s *dirinfo) +int fat_dirtruncate(struct fat_mountpt_s *fs, FAR uint8_t *direntry) { unsigned int startcluster; - uint32_t writetime; - uint8_t *direntry; - off_t savesector; - int ret; + uint32_t writetime; + off_t savesector; + int ret; /* Get start cluster of the file to truncate */ - direntry = &fs->fs_buffer[dirinfo->fd_seq.ds_offset]; - startcluster = - ((uint32_t)DIR_GETFSTCLUSTHI(direntry) << 16) | - DIR_GETFSTCLUSTLO(direntry); + startcluster = ((uint32_t)DIR_GETFSTCLUSTHI(direntry) << 16) | + DIR_GETFSTCLUSTLO(direntry); /* Clear the cluster start value in the directory and set the file size * to zero. This makes the file look empty but also have to dispose of @@ -1469,7 +1467,7 @@ int fat_dirtruncate(struct fat_mountpt_s *fs, struct fat_dirinfo_s *dirinfo) return ret; } - /* Setup FSINFO to reuse this cluster next */ + /* Setup FSINFO to reuse the old start cluster next */ fs->fs_fsinextfree = startcluster - 1; @@ -1478,6 +1476,280 @@ int fat_dirtruncate(struct fat_mountpt_s *fs, struct fat_dirinfo_s *dirinfo) return fat_fscacheread(fs, savesector); } +/**************************************************************************** + * Name: fat_dirshrink + * + * Description: + * Shrink the size existing file to a non-zero length + * + * Assumptions: + * The caller holds mountpoint semaphore, fs_buffer holds the directory + * entry. + * + ****************************************************************************/ + +int fat_dirshrink(struct fat_mountpt_s *fs, FAR uint8_t *direntry, + off_t length) +{ + off_t clustersize; + off_t remaining; + uint32_t writetime; + int32_t lastcluster; + int32_t cluster; + int ret; + + /* Get start cluster of the file to truncate */ + + lastcluster = ((uint32_t)DIR_GETFSTCLUSTHI(direntry) << 16) | + DIR_GETFSTCLUSTLO(direntry); + + /* Set the file size to the new length. */ + + DIR_PUTFILESIZE(direntry, length); + + /* Set the ARCHIVE attribute and update the write time */ + + DIR_PUTATTRIBUTES(direntry, FATATTR_ARCHIVE); + + writetime = fat_systime2fattime(); + DIR_PUTWRTTIME(direntry, writetime & 0xffff); + DIR_PUTWRTDATE(direntry, writetime > 16); + + /* This sector needs to be written back to disk eventually */ + + fs->fs_dirty = true; + + /* Now find the cluster change to be removed. Start with the cluster + * after the current one (which we know contains data). + */ + + cluster = fat_getcluster(fs, lastcluster); + if (cluster < 0) + { + return cluster; + } + + clustersize = fs->fs_fatsecperclus * fs->fs_hwsectorsize;; + remaining = length; + + while (cluster >= 2 && cluster < fs->fs_nclusters) + { + /* Will there be data in the next cluster after the shrinkage? */ + + if (remaining <= clustersize) + { + /* No.. then nullify next cluster -- removing it from the + * chain. + */ + + ret = fat_putcluster(fs, lastcluster, 0); + if (ret < 0) + { + return ret; + } + + /* Then free the remainder of the chain */ + + ret = fat_removechain(fs, cluster); + if (ret < 0) + { + return ret; + } + + /* Setup FSINFO to reuse the removed cluster next */ + + fs->fs_fsinextfree = cluster - 1; + break; + } + + /* Then set up to remove the next cluster */ + + lastcluster = cluster; + cluster = fat_getcluster(fs, cluster); + + if (cluster < 0) + { + return cluster; + } + + remaining -= clustersize; + } + + return OK; +} + +/**************************************************************************** + * Name: fat_dirextend + * + * Description: + * Zero-extend the length of a regular file to 'length'. + * + ****************************************************************************/ + +int fat_dirextend(FAR struct fat_mountpt_s *fs, FAR struct fat_file_s *ff, + off_t length) +{ + int32_t cluster; + off_t remaining; + off_t pos; + unsigned int zerosize; + int sectndx; + int ret; + + /* We are extending the file. This is essentially the same as a write + * except that (1) we write zeros and (2) we don't update the file + * position. + */ + + pos = ff->ff_size; + + /* Get the first sector to write to. */ + + if (!ff->ff_currentsector) + { + /* Has the starting cluster been defined? */ + + if (ff->ff_startcluster == 0) + { + /* No.. we have to create a new cluster chain */ + + ff->ff_startcluster = fat_createchain(fs); + ff->ff_currentcluster = ff->ff_startcluster; + ff->ff_sectorsincluster = fs->fs_fatsecperclus; + } + + /* The current sector can then be determined from the current cluster + * and the file offset. + */ + + ret = fat_currentsector(fs, ff, pos); + if (ret < 0) + { + return ret; + } + } + + /* Loop until either (1) the file has been fully extended with zeroed data + * or (2) an error occurs. We assume we start with the current sector in + * cache (ff_currentsector) + */ + + sectndx = pos & SEC_NDXMASK(fs); + remaining = length - pos; + + while (remaining > 0) + { + /* Check if the current write stream has incremented to the next + * cluster boundary + */ + + if (ff->ff_sectorsincluster < 1) + { + /* Extend the current cluster by one (unless lseek was used to + * move the file position back from the end of the file) + */ + + cluster = fat_extendchain(fs, ff->ff_currentcluster); + + /* Verify the cluster number */ + + if (cluster < 0) + { + return (int)cluster; + } + else if (cluster < 2 || cluster >= fs->fs_nclusters) + { + return -ENOSPC; + } + + /* Setup to zero the first sector from the new cluster */ + + ff->ff_currentcluster = cluster; + ff->ff_sectorsincluster = fs->fs_fatsecperclus; + ff->ff_currentsector = fat_cluster2sector(fs, cluster); + } + + /* Decide whether we are performing a read-modify-write + * operation, in which case we have to read the existing sector + * into the buffer first. + * + * There are two cases where we can avoid this read: + * + * - If we are performing a whole-sector clear that was rejected + * by fat_hwwrite(), i.e. sectndx == 0 and remaining >= sector size. + * + * - If the clear is aligned to the beginning of the sector and + * extends beyond the end of the file, i.e. sectndx == 0 and + * file pos + remaining >= file size. + */ + + if (sectndx == 0 && (remaining >= fs->fs_hwsectorsize || + (pos + remaining) >= ff->ff_size)) + { + /* Flush unwritten data in the sector cache. */ + + ret = fat_ffcacheflush(fs, ff); + if (ret < 0) + { + return ret; + } + + /* Now mark the clean cache buffer as the current sector. */ + + ff->ff_cachesector = ff->ff_currentsector; + } + else + { + /* Read the current sector into memory (perhaps first flushing the + * old, dirty sector to disk). + */ + + ret = fat_ffcacheread(fs, ff, ff->ff_currentsector); + if (ret < 0) + { + return ret; + } + } + + /* Copy the requested part of the sector from the user buffer */ + + zerosize = fs->fs_hwsectorsize - sectndx; + if (zerosize > remaining) + { + /* We will not zero to the end of the sector. */ + + zerosize = remaining; + } + else + { + /* We will zero to the end of the buffer (or beyond). Bump up + * the current sector number (actually the next sector number). + */ + + ff->ff_sectorsincluster--; + ff->ff_currentsector++; + } + + /* Zero the data into the cached sector and make sure that the cached + * sector is marked "dirty" so that it will be written back. + */ + + memset(&ff->ff_buffer[sectndx], 0, zerosize); + ff->ff_bflags |= (FFBUFF_DIRTY | FFBUFF_VALID | FFBUFF_MODIFIED); + + /* Set up for the next sector */ + + pos += zerosize; + remaining -= zerosize; + sectndx = pos & SEC_NDXMASK(fs); + } + + /* The truncation has completed without error. Update the file size */ + + ff->ff_size = length; + return OK; +} + /**************************************************************************** * Name: fat_fscacheflush * @@ -1509,9 +1781,10 @@ int fat_fscacheflush(struct fat_mountpt_s *fs) if (fs->fs_currentsector >= fs->fs_fatbase && fs->fs_currentsector < fs->fs_fatbase + fs->fs_nfatsects) { - /* Yes, then make the change in the FAT copy as well */ int i; + /* Yes, then make the change in the FAT copy as well */ + for (i = fs->fs_fatnumfats; i >= 2; i--) { fs->fs_currentsector += fs->fs_nfatsects; diff --git a/fs/mount/fs_gettype.c b/fs/mount/fs_gettype.c index 5db7a8d28628afefde18bc417a697e2643d60340..4c97c9d75b7f392cbae0fa48453e82ad2f00ed56 100644 --- a/fs/mount/fs_gettype.c +++ b/fs/mount/fs_gettype.c @@ -132,6 +132,12 @@ FAR const char *fs_gettype(FAR struct statfs *statbuf) break; #endif +#ifdef CONFIG_FS_USERFS + case USERFS_MAGIC: + fstype = "userfs"; + break; +#endif + default: fstype = "Unrecognized"; break; @@ -140,4 +146,4 @@ FAR const char *fs_gettype(FAR struct statfs *statbuf) return fstype; } -#endif /* !CONFIG_DISABLE_MOUNTPOINT && CONFIG_FS_PROCFS */ \ No newline at end of file +#endif /* !CONFIG_DISABLE_MOUNTPOINT && CONFIG_FS_PROCFS */ diff --git a/fs/mount/fs_mount.c b/fs/mount/fs_mount.c index 2fc9d7376fde13bbc8260978819b639e9bafeec1..62a982b40e8fdf15858117413be445511564cf03 100644 --- a/fs/mount/fs_mount.c +++ b/fs/mount/fs_mount.c @@ -79,7 +79,7 @@ #if defined(CONFIG_FS_NXFFS) || defined(CONFIG_FS_BINFS) || \ defined(CONFIG_FS_PROCFS) || defined(CONFIG_NFS) || \ - defined(CONFIG_FS_TMPFS) + defined(CONFIG_FS_TMPFS) || defined(CONFIG_FS_USERFS) # define NONBDFS_SUPPORT #endif @@ -139,6 +139,9 @@ extern const struct mountpt_operations binfs_operations; #ifdef CONFIG_FS_PROCFS extern const struct mountpt_operations procfs_operations; #endif +#ifdef CONFIG_FS_USERFS +extern const struct mountpt_operations userfs_operations; +#endif #ifdef CONFIG_FS_HOSTFS extern const struct mountpt_operations hostfs_operations; #endif @@ -160,6 +163,9 @@ static const struct fsmap_t g_nonbdfsmap[] = #ifdef CONFIG_FS_PROCFS { "procfs", &procfs_operations }, #endif +#ifdef CONFIG_FS_USERFS + { "userfs", &userfs_operations }, +#endif #ifdef CONFIG_FS_HOSTFS { "hostfs", &hostfs_operations }, #endif diff --git a/fs/nfs/nfs_vfsops.c b/fs/nfs/nfs_vfsops.c index 81fd43a3423751dd78153ecbeb2d170ea0730345..41fbfc46ff7215ffe1eca2548f0c57d28f844bd6 100644 --- a/fs/nfs/nfs_vfsops.c +++ b/fs/nfs/nfs_vfsops.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/nfs/nfs_vfsops.c * - * Copyright (C) 2012-2013, 2015, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013, 2015, 2017-2018 Gregory Nutt. All rights reserved. * Copyright (C) 2012 Jose Pablo Rojas Vargas. All rights reserved. * Author: Jose Pablo Rojas Vargas * Gregory Nutt @@ -135,11 +135,15 @@ struct nfsstats nfsstats; * Private Function Prototypes ****************************************************************************/ -static int nfs_filecreate(FAR struct nfsmount *nmp, struct nfsnode *np, - FAR const char *relpath, mode_t mode); -static int nfs_filetruncate(FAR struct nfsmount *nmp, struct nfsnode *np); -static int nfs_fileopen(FAR struct nfsmount *nmp, struct nfsnode *np, - FAR const char *relpath, int oflags, mode_t mode); +static int nfs_filecreate(FAR struct nfsmount *nmp, + FAR struct nfsnode *np, FAR const char *relpath, + mode_t mode); +static int nfs_filetruncate(FAR struct nfsmount *nmp, + FAR struct nfsnode *np, uint32_t length); +static int nfs_fileopen(FAR struct nfsmount *nmp, + FAR struct nfsnode *np, FAR const char *relpath, + int oflags, mode_t mode); + static int nfs_open(FAR struct file *filep, const char *relpath, int oflags, mode_t mode); static int nfs_close(FAR struct file *filep); @@ -148,6 +152,7 @@ static ssize_t nfs_write(FAR struct file *filep, const char *buffer, size_t buflen); static int nfs_dup(FAR const struct file *oldp, FAR struct file *newp); static int nfs_fstat(FAR const struct file *filep, FAR struct stat *buf); +static int nfs_truncate(FAR struct file *filep, off_t length); static int nfs_opendir(struct inode *mountpt, const char *relpath, struct fs_dirent_s *dir); static int nfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir); @@ -191,6 +196,7 @@ const struct mountpt_operations nfs_operations = NULL, /* sync */ nfs_dup, /* dup */ nfs_fstat, /* fstat */ + nfs_truncate, /* truncate */ nfs_opendir, /* opendir */ NULL, /* closedir */ @@ -224,7 +230,7 @@ const struct mountpt_operations nfs_operations = * ****************************************************************************/ -static int nfs_filecreate(FAR struct nfsmount *nmp, struct nfsnode *np, +static int nfs_filecreate(FAR struct nfsmount *nmp, FAR struct nfsnode *np, FAR const char *relpath, mode_t mode) { struct file_handle fhandle; @@ -407,7 +413,8 @@ static int nfs_filecreate(FAR struct nfsmount *nmp, struct nfsnode *np, * ****************************************************************************/ -static int nfs_filetruncate(FAR struct nfsmount *nmp, struct nfsnode *np) +static int nfs_filetruncate(FAR struct nfsmount *nmp, + FAR struct nfsnode *np, uint32_t length) { FAR uint32_t *ptr; int reqlen; @@ -435,7 +442,7 @@ static int nfs_filetruncate(FAR struct nfsmount *nmp, struct nfsnode *np) *ptr++ = nfs_false; /* Don't change uid */ *ptr++ = nfs_false; /* Don't change gid */ *ptr++ = nfs_true; /* Use the following size */ - *ptr++ = 0; /* Truncate to zero length */ + *ptr++ = length; /* Truncate to the specified length */ *ptr++ = 0; *ptr++ = HTONL(NFSV3SATTRTIME_TOSERVER); /* Use the server's time */ *ptr++ = HTONL(NFSV3SATTRTIME_TOSERVER); /* Use the server's time */ @@ -472,7 +479,7 @@ static int nfs_filetruncate(FAR struct nfsmount *nmp, struct nfsnode *np) * ****************************************************************************/ -static int nfs_fileopen(FAR struct nfsmount *nmp, struct nfsnode *np, +static int nfs_fileopen(FAR struct nfsmount *nmp, FAR struct nfsnode *np, FAR const char *relpath, int oflags, mode_t mode) { struct file_handle fhandle; @@ -549,7 +556,7 @@ static int nfs_fileopen(FAR struct nfsmount *nmp, struct nfsnode *np, * the SETATTR call by setting the length to zero. */ - return nfs_filetruncate(nmp, np); + return nfs_filetruncate(nmp, np, 0); } return OK; @@ -834,7 +841,7 @@ static ssize_t nfs_read(FAR struct file *filep, char *buffer, size_t buflen) { /* Make sure that the attempted read size does not exceed the RPC maximum */ - readsize = buflen; + readsize = buflen - bytesread; if (readsize > nmp->nm_rsize) { readsize = nmp->nm_rsize; @@ -1201,7 +1208,7 @@ static int nfs_dup(FAR const struct file *oldp, FAR struct file *newp) * * Description: * Obtain information about an open file associated with the file - * descriptor 'fd', and will write it to the area pointed to by 'buf'. + * structure 'filep', and will write it to the area pointed to by 'buf'. * ****************************************************************************/ @@ -1270,6 +1277,50 @@ errout_with_semaphore: return -error; } +/**************************************************************************** + * Name: nfs_truncate + * + * Description: + * Set the length of the open, regular file associated with the file + * structure 'filep' to 'length'. + * + ****************************************************************************/ + +static int nfs_truncate(FAR struct file *filep, off_t length) +{ + struct nfsmount *nmp; + struct nfsnode *np; + int error; + + finfo("Truncate to %ld bytes\n", (long)length); + DEBUGASSERT(filep->f_priv != NULL && filep->f_inode != NULL); + + /* Recover our private data from the struct file instance */ + + nmp = (FAR struct nfsmount *)filep->f_inode->i_private; + np = (FAR struct nfsnode *)filep->f_priv; + + DEBUGASSERT(nmp != NULL); + + /* Make sure that the mount is still healthy */ + + nfs_semtake(nmp); + error = nfs_checkmount(nmp); + if (error != OK) + { + ferr("ERROR: nfs_checkmount failed: %d\n", error); + goto errout_with_semaphore; + } + + /* Then perform the SETATTR RPC to set the new file size */ + + error = nfs_filetruncate(nmp, np, length); + +errout_with_semaphore: + nfs_semgive(nmp); + return -error; +} + /**************************************************************************** * Name: nfs_opendir * @@ -2638,7 +2689,7 @@ static void nfs_stat_common(FAR struct nfs_statinfo_s *info, /* Now OR in the file type */ - switch (info->ns_mode) + switch (info->ns_type) { default: case NFNON: /* Unknown type */ diff --git a/fs/nxffs/Make.defs b/fs/nxffs/Make.defs index a63d73937340341aea40f0a68d9187d08503c2dc..c82038dba339500cb8dd798a351a991737b7bdb7 100644 --- a/fs/nxffs/Make.defs +++ b/fs/nxffs/Make.defs @@ -34,11 +34,14 @@ ############################################################################ ifeq ($(CONFIG_FS_NXFFS),y) + ASRCS += -CSRCS += nxffs_block.c nxffs_blockstats.c nxffs_cache.c nxffs_dirent.c \ - nxffs_dump.c nxffs_initialize.c nxffs_inode.c nxffs_ioctl.c \ - nxffs_open.c nxffs_pack.c nxffs_read.c nxffs_reformat.c \ - nxffs_stat.c nxffs_unlink.c nxffs_util.c nxffs_write.c + +CSRCS += nxffs_block.c nxffs_blockstats.c nxffs_cache.c nxffs_dirent.c +CSRCS += nxffs_dump.c nxffs_initialize.c nxffs_inode.c nxffs_ioctl.c +CSRCS += nxffs_open.c nxffs_pack.c nxffs_read.c nxffs_reformat.c +CSRCS += nxffs_stat.c nxffs_truncate.c nxffs_unlink.c nxffs_util.c +CSRCS += nxffs_write.c # Include NXFFS build support diff --git a/fs/nxffs/README.txt b/fs/nxffs/README.txt index e7d38e4e634687a3d8462ad6824336ecd5c84b25..60e06219fe7a3044b0c2e19e9f6b5310a547f44a 100644 --- a/fs/nxffs/README.txt +++ b/fs/nxffs/README.txt @@ -177,4 +177,9 @@ Things to Do a good but empty state... all ready for file system re-organization. - And worse, when NXFSS reorganization the FLASH a power cycle can damage the file system content if it happens at the wrong time. +- The current design does not permit re-opening of files for write access + unless the file is truncated to zero length. This effectively prohibits + implementation of a proper turncate() method which should alter the + size of a previously written file. There is some fragmentray logic in + place but even this is conditioned out with __NO_TRUNCATE_SUPPORT__. diff --git a/fs/nxffs/nxffs.h b/fs/nxffs/nxffs.h index 30f84b1f328edfbc7004beabcfc243f555ee7b83..bc979a3050a1f726e3c90cdc98e9f8a8177ff08e 100644 --- a/fs/nxffs/nxffs.h +++ b/fs/nxffs/nxffs.h @@ -1,7 +1,8 @@ /**************************************************************************** * fs/nxffs/nxffs.h * - * Copyright (C) 2011, 2013, 2015, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013, 2015, 2017-2018 Gregory Nutt. All rights + * reserved. * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt @@ -870,6 +871,28 @@ int nxffs_wrinode(FAR struct nxffs_volume_s *volume, int nxffs_updateinode(FAR struct nxffs_volume_s *volume, FAR struct nxffs_entry_s *entry); +/**************************************************************************** + * Name: nxffs_wrextend + * + * Description: + * Zero-extend a file. + * + * Input parameters + * volume - Describes the NXFFS volume + * entry - Describes the new inode entry + * length - The new, extended length of the file + * + * Assumptions: + * The caller holds the NXFFS semaphore. + * The caller has verified that the file is writable. + * + ****************************************************************************/ + +#ifdef __NO_TRUNCATE_SUPPORT__ +int nxffs_wrextend(FAR struct nxffs_volume_s *volume, + FAR struct nxffs_wrfile_s *wrfile, off_t length); +#endif + /**************************************************************************** * Name: nxffs_wrreserve * @@ -1091,12 +1114,18 @@ ssize_t nxffs_read(FAR struct file *filep, FAR char *buffer, size_t buflen); ssize_t nxffs_write(FAR struct file *filep, FAR const char *buffer, size_t buflen); int nxffs_ioctl(FAR struct file *filep, int cmd, unsigned long arg); + int nxffs_dup(FAR const struct file *oldp, FAR struct file *newp); int nxffs_fstat(FAR const struct file *filep, FAR struct stat *buf); +#ifdef __NO_TRUNCATE_SUPPORT__ +int nxffs_truncate(FAR struct file *filep, off_t length); +#endif + int nxffs_opendir(FAR struct inode *mountpt, FAR const char *relpath, FAR struct fs_dirent_s *dir); int nxffs_readdir(FAR struct inode *mountpt, FAR struct fs_dirent_s *dir); int nxffs_rewinddir(FAR struct inode *mountpt, FAR struct fs_dirent_s *dir); + int nxffs_bind(FAR struct inode *blkdriver, FAR const void *data, FAR void **handle); int nxffs_unbind(FAR void *handle, FAR struct inode **blkdriver, diff --git a/fs/nxffs/nxffs_dirent.c b/fs/nxffs/nxffs_dirent.c index 9afe9848671cc8355babb3155dee4f60fc77639f..298238232b38a729b16280f75dd7eba9610c9de9 100644 --- a/fs/nxffs/nxffs_dirent.c +++ b/fs/nxffs/nxffs_dirent.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/nxffs/nxffs_dirent.c * - * Copyright (C) 2011, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt @@ -47,6 +47,7 @@ #include #include +#include #include #include #include diff --git a/fs/nxffs/nxffs_initialize.c b/fs/nxffs/nxffs_initialize.c index f2518569fe8a75c59aa7e478a220539fb00b62a5..0bd5aab2f5ff52bd662a4e31421cd922a4d45dbd 100644 --- a/fs/nxffs/nxffs_initialize.c +++ b/fs/nxffs/nxffs_initialize.c @@ -1,7 +1,8 @@ /**************************************************************************** * fs/nxffs/nxffs_initialize.c * - * Copyright (C) 2011, 2013, 2015, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013, 2015, 2017-2018 Gregory Nutt. All rights + * reserved. * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt @@ -74,6 +75,11 @@ const struct mountpt_operations nxffs_operations = NULL, /* sync -- No buffered data */ nxffs_dup, /* dup */ nxffs_fstat, /* fstat */ +#ifdef __NO_TRUNCATE_SUPPORT__ + nxffs_truncate, /* truncate */ +#else + NULL, /* truncate */ +#endif nxffs_opendir, /* opendir */ NULL, /* closedir */ diff --git a/fs/nxffs/nxffs_ioctl.c b/fs/nxffs/nxffs_ioctl.c index e80d4d265a96ec8cb8209dba75173136de99d290..03f6416d708f30c23bba56479d606f1d4caa48ee 100644 --- a/fs/nxffs/nxffs_ioctl.c +++ b/fs/nxffs/nxffs_ioctl.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/nxffs/nxffs_ioctl.c * - * Copyright (C) 2011, 2013, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013, 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt @@ -46,6 +46,7 @@ #include #include +#include #include #include #include diff --git a/fs/nxffs/nxffs_read.c b/fs/nxffs/nxffs_read.c index 49014d6144bf5f9297560fdd4fb8890f8bb63234..c2ae61348014d0e7ea16a147bb7b5ff9707b2544 100644 --- a/fs/nxffs/nxffs_read.c +++ b/fs/nxffs/nxffs_read.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/nxffs/nxffs_read.c * - * Copyright (C) 2011, 2013, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013, 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt @@ -48,6 +48,7 @@ #include #include +#include #include #include diff --git a/fs/nxffs/nxffs_stat.c b/fs/nxffs/nxffs_stat.c index 5d2ea2927c5538b1ebc5045df38a48e22d721824..0de686c0fe9ebdc690e793e429e7cc5ef0d52dba 100644 --- a/fs/nxffs/nxffs_stat.c +++ b/fs/nxffs/nxffs_stat.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/nxffs/nxffs_stat.c * - * Copyright (C) 2011, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt @@ -50,6 +50,7 @@ #include #include +#include #include #include diff --git a/fs/nxffs/nxffs_truncate.c b/fs/nxffs/nxffs_truncate.c new file mode 100644 index 0000000000000000000000000000000000000000..e4b1cbeaae4cb9b977f8398e3d1fc451d79e2e19 --- /dev/null +++ b/fs/nxffs/nxffs_truncate.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * fs/nxffs/nxffs_truncate.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: Linux/Documentation/filesystems/romfs.txt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "nxffs.h" + +#ifdef __NO_TRUNCATE_SUPPORT__ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nxffs_truncate + * + * Description: + * Set the length of the open, regular file associated with the file + * structure 'filep' to 'length'. + * + ****************************************************************************/ + +int nxffs_truncate(FAR struct file *filep, off_t length) +{ + FAR struct nxffs_volume_s *volume; + FAR struct nxffs_wrfile_s *wrfile; + off_t oldsize; + int ret; + + finfo("Write %d bytes to offset %d\n", buflen, filep->f_pos); + + /* Sanity checks */ + + DEBUGASSERT(filep->f_priv != NULL && filep->f_inode != NULL); + + /* Recover the open file state from the struct file instance */ + + wrfile = (FAR struct nxffs_wrfile_s *)filep->f_priv; + + /* Recover the volume state from the open file */ + + volume = (FAR struct nxffs_volume_s *)filep->f_inode->i_private; + DEBUGASSERT(volume != NULL); + + /* Get exclusive access to the volume. Note that the volume exclsem + * protects the open file list. + */ + + ret = nxsem_wait(&volume->exclsem); + if (ret < 0) + { + ferr("ERROR: nxsem_wait failed: %d\n", ret); + goto errout; + } + + /* Check if the file was opened with write access */ + + if ((wrfile->ofile.oflags & O_WROK) == 0) + { + ferr("ERROR: File not open for write access\n"); + ret = -EACCES; + goto errout_with_semaphore; + } + + /* Are we shrinking the file? Or extending it? */ + + oldsize = wrfile->ofile.entry.datlen; + if (oldsize == length) + { + ret = OK; + goto errout_with_semaphore; + } + else if (oldsize > length) + { + /* We are shrinking the file */ + /* REVISIT: Logic to shrink the file has not yet been implemented */ + + ret = -ENOSYS; + } + else + { + /* We are zero-extending the file. This essential amount to a write- + * append operation with zero data. + */ + + ret = nxffs_wrextend(volume, wrfile, length); + } + +errout_with_semaphore: + nxsem_post(&volume->exclsem); + +errout: + return ret; +} + +#endif /* __NO_TRUNCATE_SUPPORT__ */ diff --git a/fs/nxffs/nxffs_unlink.c b/fs/nxffs/nxffs_unlink.c index 786acc1682f283f4d8492c7b0b522a6583c5d9fa..e58850384663a85ab2b610a0b6c7b1ef01a2b66f 100644 --- a/fs/nxffs/nxffs_unlink.c +++ b/fs/nxffs/nxffs_unlink.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/nxffs/nxffs_unlink.c * - * Copyright (C) 2011, 2013, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013, 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt @@ -46,6 +46,7 @@ #include #include +#include #include #include diff --git a/fs/nxffs/nxffs_write.c b/fs/nxffs/nxffs_write.c index ba51895ccebfd62d012e1ff721b75d9bc906edd0..1fd761e4401dc0fc05797fe21d56e8830f0dd756 100644 --- a/fs/nxffs/nxffs_write.c +++ b/fs/nxffs/nxffs_write.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/nxffs/nxffs_write.c * - * Copyright (C) 2011, 2013, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013, 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt @@ -48,6 +48,7 @@ #include #include +#include #include #include @@ -289,7 +290,7 @@ static inline int nxffs_wralloc(FAR struct nxffs_volume_s *volume, ****************************************************************************/ static inline int nxffs_reverify(FAR struct nxffs_volume_s *volume, - FAR struct nxffs_wrfile_s *wrfile) + FAR struct nxffs_wrfile_s *wrfile) { uint32_t crc; off_t offset; @@ -299,13 +300,13 @@ static inline int nxffs_reverify(FAR struct nxffs_volume_s *volume, /* Get the offset to the start of the data */ offset = volume->iooffset + SIZEOF_NXFFS_DATA_HDR; - DEBUGASSERT(offset + wrfile->datlen < volume->geo.blocksize); + DEBUGASSERT(offset + wrfile->datlen <= volume->geo.blocksize); /* Calculate the CRC of the partial data block */ crc = crc32(&volume->cache[offset], wrfile->datlen); - /* It must match the previoulsy calculated CRC value */ + /* It must match the previously calculated CRC value */ if (crc != wrfile->crc) { @@ -327,7 +328,7 @@ static inline int nxffs_reverify(FAR struct nxffs_volume_s *volume, * volume - Describes the NXFFS volume * wrfile - Describes the open file to be written. * buffer - Address of buffer of data to be written. - * buflen - The number of bytes remaimining to be written + * buflen - The number of bytes remaining to be written * * Returned Value: * The number of bytes written is returned on success. Otherwise, a @@ -414,6 +415,98 @@ static inline ssize_t nxffs_wrappend(FAR struct nxffs_volume_s *volume, return nbytestowrite; } +/**************************************************************************** + * Name: nxffs_zappend + * + * Description: + * Zero-extend FLASH data to the data block. + * + * Input Parameters: + * volume - Describes the NXFFS volume + * wrfile - Describes the open file to be written. + * nzeros - The number of bytes of zeroed data to be written + * + * Returned Value: + * The number of zero bytes written is returned on success. Otherwise, a + * negated errno value is returned indicating the nature of the failure. + * + ****************************************************************************/ + +#ifdef __NO_TRUNCATE_SUPPORT__ +static inline ssize_t nxffs_zappend(FAR struct nxffs_volume_s *volume, + FAR struct nxffs_wrfile_s *wrfile, + off_t nzeros) +{ + ssize_t maxsize; + size_t nbytestoclear; + ssize_t nbytesleft; + off_t offset; + int ret; + + /* Get the offset to the start of unwritten data */ + + offset = volume->iooffset + wrfile->datlen + SIZEOF_NXFFS_DATA_HDR; + + /* Determine that maximum amount of data that can be written to this + * block. + */ + + maxsize = volume->geo.blocksize - offset; + DEBUGASSERT(maxsize > 0); + + /* Write as many bytes as we can into the data buffer */ + + nbytestoclear = MIN(maxsize, nzeros); + nbytesleft = maxsize - nbytestoclear; + + if (nbytestoclear > 0) + { + /* Zero the data into the volume write cache */ + + memset(&volume->cache[offset], 0, nbytestoclear); + + /* Increment the number of bytes written to the data block */ + + wrfile->datlen += nbytestoclear; + + /* Re-calculate the CRC */ + + offset = volume->iooffset + SIZEOF_NXFFS_DATA_HDR; + wrfile->crc = crc32(&volume->cache[offset], wrfile->datlen); + + /* And write the partial write block to FLASH -- unless the data + * block is full. In that case, the block will be written below. + */ + + if (nbytesleft > 0) + { + ret = nxffs_wrcache(volume); + if (ret < 0) + { + ferr("ERROR: nxffs_wrcache failed: %d\n", -ret); + return ret; + } + } + } + + /* Check if the data block is now full */ + + if (nbytesleft <= 0) + { + /* The data block is full, write the block to FLASH */ + + ret = nxffs_wrblkhdr(volume, wrfile); + if (ret < 0) + { + ferr("ERROR: nxffs_wrblkdhr failed: %d\n", -ret); + return ret; + } + } + + return nbytestoclear; +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -534,6 +627,93 @@ errout: return ret; } +/**************************************************************************** + * Name: nxffs_wrextend + * + * Description: + * Zero-extend a file. + * + * Input parameters + * volume - Describes the NXFFS volume + * entry - Describes the new inode entry + * length - The new, extended length of the file + * + * Assumptions: + * The caller holds the NXFFS semaphore. + * The caller has verified that the file is writable. + * + ****************************************************************************/ + +#ifdef __NO_TRUNCATE_SUPPORT__ +int nxffs_wrextend(FAR struct nxffs_volume_s *volume, + FAR struct nxffs_wrfile_s *wrfile, off_t length) +{ + ssize_t remaining; + ssize_t nwritten; + off_t oldsize; + int ret; + + finfo("Extend file to %ld bytes to offset %d\n", (long)length); + DEBUGASSERT(volume != NULL && wrfile != NULL); + + oldsize = wrfile->ofile.entry.datlen; + DEBUGASSERT(length > oldsize); + + /* Loop until we successfully appended all of the data to the file (or an + * error occurs) + */ + + remaining = length - oldsize; + while (remaining > 0) + { + /* Have we already allocated the data block? */ + + if (wrfile->doffset == 0) + { + /* No, allocate the data block now, re-packing if necessary. */ + + wrfile->datlen = 0; + ret = nxffs_wralloc(volume, wrfile, remaining); + if (ret < 0) + { + ferr("ERROR: Failed to allocate a data block: %d\n", -ret); + return ret; + } + } + + /* Seek to the FLASH block containing the data block */ + + nxffs_ioseek(volume, wrfile->doffset); + + /* Verify that the FLASH data that was previously written is still intact */ + + ret = nxffs_reverify(volume, wrfile); + if (ret < 0) + { + ferr("ERROR: Failed to verify FLASH data block: %d\n", -ret); + return ret; + } + + /* Append the data to the end of the data block and write the updated + * block to flash. + */ + + nwritten = nxffs_zappend(volume, wrfile, remaining); + if (nwritten < 0) + { + ferr("ERROR: Failed to zero extend FLASH data block: %d\n", -ret); + return (int)nwritten; + } + + /* Decrement the number of bytes remaining to be written */ + + remaining -= nwritten; + } + + return OK; +} +#endif + /**************************************************************************** * Name: nxffs_wrreserve * diff --git a/fs/procfs/Kconfig b/fs/procfs/Kconfig index 4e55b51f58065d11383fce4882675431514954e1..81e3f8345ca1e3b32cc244d7ba3d89068a8fb16d 100644 --- a/fs/procfs/Kconfig +++ b/fs/procfs/Kconfig @@ -75,10 +75,14 @@ config FS_PROCFS_EXCLUDE_CPULOAD default n depends on SCHED_CPULOAD -config FS_PROCFS_EXCLUDE_KMM - bool "Exclude kmm" +config FS_PROCFS_EXCLUDE_MEMINFO + bool "Exclude meminfo" default n - depends on MM_KERNEL_HEAP + +config FS_PROCFS_INCLUDE_PROGMEM + bool "Include prog mem" + default n + depends on ARCH_HAVE_PROGMEM && !FS_PROCFS_EXCLUDE_MEMINFO config FS_PROCFS_EXCLUDE_MOUNTS bool "Exclude mounts" @@ -90,11 +94,6 @@ config FS_PROCFS_EXCLUDE_NET depends on NET default n -config FS_PROCFS_EXCLUDE_ROUTE - bool "Exclude routing table" - depends on !FS_PROCFS_EXCLUDE_NET && NET_ROUTE - default n - config FS_PROCFS_EXCLUDE_MTD bool "Exclude mtd" depends on MTD @@ -105,6 +104,11 @@ config FS_PROCFS_EXCLUDE_PARTITIONS depends on MTD_PARTITION default n +config FS_PROCFS_EXCLUDE_ROUTE + bool "Exclude routing table" + depends on !FS_PROCFS_EXCLUDE_NET && NET_ROUTE + default n + config FS_PROCFS_EXCLUDE_SMARTFS bool "Exclude fs/smartfs" depends on FS_SMARTFS diff --git a/fs/procfs/Make.defs b/fs/procfs/Make.defs index 434e85799e8b6365f297f2888ee9348fd0829117..a9382de318db409d8d347d8ac64e3c7fdfe7f023 100644 --- a/fs/procfs/Make.defs +++ b/fs/procfs/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # fs/procfs/Make.defs # -# Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. +# Copyright (C) 2013, 2016-2017 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -38,7 +38,7 @@ ifeq ($(CONFIG_FS_PROCFS),y) ASRCS += CSRCS += fs_procfs.c fs_procfsutil.c fs_procfsproc.c fs_procfsuptime.c -CSRCS += fs_procfscpuload.c fs_procfskmm.c +CSRCS += fs_procfscpuload.c fs_procfsmeminfo.c # Include procfs build support diff --git a/fs/procfs/fs_procfs.c b/fs/procfs/fs_procfs.c index 07aaec449bd5b6010469cbdced2ed5fc7362c2f9..e269d873e3abbfa26db7f2eb69f42e6e97d35b22 100644 --- a/fs/procfs/fs_procfs.c +++ b/fs/procfs/fs_procfs.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/procfs/fs_procfs.c * - * Copyright (C) 2013-2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -78,7 +78,7 @@ extern const struct procfs_operations proc_operations; extern const struct procfs_operations cpuload_operations; -extern const struct procfs_operations kmm_operations; +extern const struct procfs_operations meminfo_operations; extern const struct procfs_operations module_operations; extern const struct procfs_operations uptime_operations; @@ -124,8 +124,8 @@ static const struct procfs_entry_s g_procfs_entries[] = { "cpuload", &cpuload_operations, PROCFS_FILE_TYPE }, #endif -#if defined(CONFIG_MM_KERNEL_HEAP) && !defined(CONFIG_FS_PROCFS_EXCLUDE_KMM) - { "kmm", &kmm_operations, PROCFS_FILE_TYPE }, +#ifndef CONFIG_FS_PROCFS_EXCLUDE_MEMINFO + { "meminfo", &meminfo_operations, PROCFS_FILE_TYPE }, #endif #if defined(CONFIG_MODULE) && !defined(CONFIG_FS_PROCFS_EXCLUDE_MODULE) @@ -148,6 +148,10 @@ static const struct procfs_entry_s g_procfs_entries[] = { "fs/smartfs**", &smartfs_procfsoperations, PROCFS_UNKOWN_TYPE }, #endif +#if defined(CONFIG_MTD) && !defined(CONFIG_FS_PROCFS_EXCLUDE_MTD) + { "mtd", &mtd_procfsoperations, PROCFS_FILE_TYPE }, +#endif + #if defined(CONFIG_NET) && !defined(CONFIG_FS_PROCFS_EXCLUDE_NET) { "net", &net_procfsoperations, PROCFS_DIR_TYPE }, #if defined(CONFIG_NET_ROUTE) && !defined(CONFIG_FS_PROCFS_EXCLUDE_ROUTE) @@ -157,10 +161,6 @@ static const struct procfs_entry_s g_procfs_entries[] = { "net/**", &net_procfsoperations, PROCFS_UNKOWN_TYPE }, #endif -#if defined(CONFIG_MTD) && !defined(CONFIG_FS_PROCFS_EXCLUDE_MTD) - { "mtd", &mtd_procfsoperations, PROCFS_FILE_TYPE }, -#endif - #if defined(CONFIG_MTD_PARTITION) && !defined(CONFIG_FS_PROCFS_EXCLUDE_PARTITIONS) { "partitions", &part_procfsoperations, PROCFS_FILE_TYPE }, #endif @@ -257,6 +257,7 @@ const struct mountpt_operations procfs_operations = NULL, /* sync */ procfs_dup, /* dup */ procfs_fstat, /* fstat */ + NULL, /* truncate */ procfs_opendir, /* opendir */ procfs_closedir, /* closedir */ diff --git a/fs/procfs/fs_procfskmm.c b/fs/procfs/fs_procfsmeminfo.c similarity index 52% rename from fs/procfs/fs_procfskmm.c rename to fs/procfs/fs_procfsmeminfo.c index d3c8699d19f706613b487e59c91063c742c32118..b6010aedc5b902f775f53ddb21bebf0bec8da967 100644 --- a/fs/procfs/fs_procfskmm.c +++ b/fs/procfs/fs_procfsmeminfo.c @@ -1,5 +1,5 @@ /**************************************************************************** - * fs/procfs/fs_procfskmm.c + * fs/procfs/fs_procfsmeminfo.c * * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -53,12 +53,12 @@ #include #include +#include #include #include #include -#if defined(CONFIG_MM_KERNEL_HEAP) && defined(CONFIG_FS_PROCFS) && \ - !defined(CONFIG_FS_PROCFS_EXCLUDE_KMM) +#ifndef CONFIG_FS_PROCFS_EXCLUDE_MEMINFO /**************************************************************************** * Pre-processor Definitions @@ -67,7 +67,7 @@ * to handle the longest line generated by this logic. */ -#define KMM_LINELEN 54 +#define MEMINFO_LINELEN 54 /**************************************************************************** * Private Types @@ -75,31 +75,42 @@ /* This structure describes one open "file" */ -struct kmm_file_s +struct meminfo_file_s { struct procfs_file_s base; /* Base open file structure */ unsigned int linesize; /* Number of valid characters in line[] */ - char line[KMM_LINELEN]; /* Pre-allocated buffer for formatted lines */ + char line[MEMINFO_LINELEN]; /* Pre-allocated buffer for formatted lines */ }; +#if defined(CONFIG_ARCH_HAVE_PROGMEM) && defined(CONFIG_FS_PROCFS_INCLUDE_PROGMEM) +struct progmem_info_s +{ + int arena; /* Total size of available progmem. */ + int ordblks; /* This is the number of free chunks */ + int mxordblk; /* Size of the largest free chunk */ + int uordblks; /* Total size of memory for allocated chunks */ + int fordblks; /* Total size of memory for free chunks.*/ +}; +#endif + /**************************************************************************** * Private Function Prototypes ****************************************************************************/ +#if defined(CONFIG_ARCH_HAVE_PROGMEM) && defined(CONFIG_FS_PROCFS_INCLUDE_PROGMEM) +static void meminfo_progmem(FAR struct progmem_info_s *progmem); +#endif + /* File system methods */ -static int kmm_open(FAR struct file *filep, FAR const char *relpath, +static int meminfo_open(FAR struct file *filep, FAR const char *relpath, int oflags, mode_t mode); -static int kmm_close(FAR struct file *filep); -static ssize_t kmm_read(FAR struct file *filep, FAR char *buffer, +static int meminfo_close(FAR struct file *filep); +static ssize_t meminfo_read(FAR struct file *filep, FAR char *buffer, size_t buflen); -static int kmm_dup(FAR const struct file *oldp, +static int meminfo_dup(FAR const struct file *oldp, FAR struct file *newp); -static int kmm_stat(FAR const char *relpath, FAR struct stat *buf); - -/**************************************************************************** - * Private Data - ****************************************************************************/ +static int meminfo_stat(FAR const char *relpath, FAR struct stat *buf); /**************************************************************************** * Public Data @@ -110,18 +121,18 @@ static int kmm_stat(FAR const char *relpath, FAR struct stat *buf); * with any compiler. */ -const struct procfs_operations kmm_operations = +const struct procfs_operations meminfo_operations = { - kmm_open, /* open */ - kmm_close, /* close */ - kmm_read, /* read */ + meminfo_open, /* open */ + meminfo_close, /* close */ + meminfo_read, /* read */ NULL, /* write */ - kmm_dup, /* dup */ + meminfo_dup, /* dup */ NULL, /* opendir */ NULL, /* closedir */ NULL, /* readdir */ NULL, /* rewinddir */ - kmm_stat /* stat */ + meminfo_stat /* stat */ }; /**************************************************************************** @@ -129,13 +140,75 @@ const struct procfs_operations kmm_operations = ****************************************************************************/ /**************************************************************************** - * Name: kmm_open + * Name: meminfo_progmem + * + * Description: + * The moral equivalent of mallinfo() for prog mem + * + * TODO Max block size only works on uniform prog mem + * ****************************************************************************/ -static int kmm_open(FAR struct file *filep, FAR const char *relpath, +#if defined(CONFIG_ARCH_HAVE_PROGMEM) && defined(CONFIG_FS_PROCFS_INCLUDE_PROGMEM) +static void meminfo_progmem(FAR struct progmem_info_s *progmem) +{ + size_t page = 0; + size_t stpage = 0xffff; + size_t pagesize = 0; + ssize_t status; + + progmem->arena = 0; + progmem->fordblks = 0; + progmem->uordblks = 0; + progmem->mxordblk = 0; + + for (status = 0, page = 0; status >= 0; page++) + { + status = up_progmem_ispageerased(page); + pagesize = up_progmem_pagesize(page); + + progmem->arena += pagesize; + + /* Is this beginning of new free space section */ + + if (status == 0) + { + if (stpage == 0xffff) + { + stpage = page; + } + + progmem->fordblks += pagesize; + } + else if (status != 0) + { + progmem->uordblks += pagesize; + + if (stpage != 0xffff && up_progmem_isuniform()) + { + stpage = page - stpage; + if (stpage > progmem->mxordblk) + { + progmem->mxordblk = stpage; + } + + stpage = 0xffff; + } + } + } + + progmem->mxordblk *= pagesize; +} +#endif + +/**************************************************************************** + * Name: meminfo_open + ****************************************************************************/ + +static int meminfo_open(FAR struct file *filep, FAR const char *relpath, int oflags, mode_t mode) { - FAR struct kmm_file_s *procfile; + FAR struct meminfo_file_s *procfile; finfo("Open '%s'\n", relpath); @@ -151,9 +224,9 @@ static int kmm_open(FAR struct file *filep, FAR const char *relpath, return -EACCES; } - /* "kmm" is the only acceptable value for the relpath */ + /* "meminfo" is the only acceptable value for the relpath */ - if (strcmp(relpath, "kmm") != 0) + if (strcmp(relpath, "meminfo") != 0) { ferr("ERROR: relpath is '%s'\n", relpath); return -ENOENT; @@ -161,7 +234,8 @@ static int kmm_open(FAR struct file *filep, FAR const char *relpath, /* Allocate a container to hold the file attributes */ - procfile = (FAR struct kmm_file_s *)kmm_zalloc(sizeof(struct kmm_file_s)); + procfile = (FAR struct meminfo_file_s *) + kmm_zalloc(sizeof(struct meminfo_file_s)); if (!procfile) { ferr("ERROR: Failed to allocate file attributes\n"); @@ -175,16 +249,16 @@ static int kmm_open(FAR struct file *filep, FAR const char *relpath, } /**************************************************************************** - * Name: kmm_close + * Name: meminfo_close ****************************************************************************/ -static int kmm_close(FAR struct file *filep) +static int meminfo_close(FAR struct file *filep) { - FAR struct kmm_file_s *procfile; + FAR struct meminfo_file_s *procfile; /* Recover our private data from the struct file instance */ - procfile = (FAR struct kmm_file_s *)filep->f_priv; + procfile = (FAR struct meminfo_file_s *)filep->f_priv; DEBUGASSERT(procfile); /* Release the file attributes structure */ @@ -195,13 +269,13 @@ static int kmm_close(FAR struct file *filep) } /**************************************************************************** - * Name: kmm_read + * Name: meminfo_read ****************************************************************************/ -static ssize_t kmm_read(FAR struct file *filep, FAR char *buffer, - size_t buflen) +static ssize_t meminfo_read(FAR struct file *filep, FAR char *buffer, + size_t buflen) { - FAR struct kmm_file_s *procfile; + FAR struct meminfo_file_s *procfile; struct mallinfo mem; size_t linesize; size_t copysize; @@ -215,38 +289,125 @@ static ssize_t kmm_read(FAR struct file *filep, FAR char *buffer, /* Recover our private data from the struct file instance */ - procfile = (FAR struct kmm_file_s *)filep->f_priv; + procfile = (FAR struct meminfo_file_s *)filep->f_priv; DEBUGASSERT(procfile); /* The first line is the headers */ - linesize = snprintf(procfile->line, KMM_LINELEN, + linesize = snprintf(procfile->line, MEMINFO_LINELEN, " total used free largest\n"); copysize = procfs_memcpy(procfile->line, linesize, buffer, buflen, &offset); totalsize = copysize; + /* Followed by information about the memory resources */ + +#ifdef CONFIG_MM_KERNEL_HEAP if (totalsize < buflen) { - buffer += copysize; - buflen -= copysize; + buffer += copysize; + buflen -= copysize; - /* The second line is the memory data */ + /* Show kernel heap information */ #ifdef CONFIG_CAN_PASS_STRUCTS - mem = kmm_mallinfo(); + mem = kmm_mallinfo(); #else (void)kmm_mallinfo(&mem); #endif - linesize = snprintf(procfile->line, KMM_LINELEN, - "Mem: %11d%11d%11d%11d\n", - mem.arena, mem.uordblks, mem.fordblks, - mem.mxordblk); + linesize = snprintf(procfile->line, MEMINFO_LINELEN, + "Kmem: %11lu%11lu%11lu%11lu\n", + (unsigned long)mem.arena, + (unsigned long)mem.uordblks, + (unsigned long)mem.fordblks, + (unsigned long)mem.mxordblk); copysize = procfs_memcpy(procfile->line, linesize, buffer, buflen, &offset); totalsize += copysize; } +#endif + +#if !defined(CONFIG_BUILD_KERNEL) + if (totalsize < buflen) + { + buffer += copysize; + buflen -= copysize; + + /* Show user heap information */ + +#ifdef CONFIG_CAN_PASS_STRUCTS + mem = kumm_mallinfo(); +#else + (void)kumm_mallinfo(&mem); +#endif + + linesize = snprintf(procfile->line, MEMINFO_LINELEN, + "Umem: %11lu%11lu%11lu%11lu\n", + (unsigned long)mem.arena, + (unsigned long)mem.uordblks, + (unsigned long)mem.fordblks, + (unsigned long)mem.mxordblk); + copysize = procfs_memcpy(procfile->line, linesize, buffer, buflen, + &offset); + totalsize += copysize; + } +#endif + +#ifdef CONFIG_MM_PGALLOC + if (totalsize < buflen) + { + struct pginfo_s pginfo; + unsigned long total; + unsigned long available; + unsigned long allocated; + unsigned long max; + + buffer += copysize; + buflen -= copysize; + + /* Show page allocator information */ + + mm_pginfo(&pginfo); + + total = (unsigned long)pginfo.ntotal << MM_PGSHIFT; + available = (unsigned long)pginfo.nfree << MM_PGSHIFT; + allocated = total - available; + max = (unsigned long)pginfo.mxfree << MM_PGSHIFT; + + linesize = snprintf(procfile->line, MEMINFO_LINELEN, + "Page: %11lu%11lu%11lu%11lu\n", + total, allocated, available, max); + + copysize = procfs_memcpy(procfile->line, linesize, buffer, buflen, + &offset); + totalsize += copysize; + } +#endif + +#if defined(CONFIG_ARCH_HAVE_PROGMEM) && defined(CONFIG_FS_PROCFS_INCLUDE_PROGMEM) + if (totalsize < buflen) + { + struct progmem_info_s progmem; + + buffer += copysize; + buflen -= copysize; + + /* The second line is the memory data */ + + meminfo_progmem(&progmem); + + linesize = snprintf(procfile->line, MEMINFO_LINELEN, + "Prog: %11lu%11lu%11lu%11lu\n", + (unsigned long)progmem.arena, + (unsigned long)progmem.uordblks, + (unsigned long)progmem.fordblks, + (unsigned long)progmem.mxordblk); + copysize = procfs_memcpy(procfile->line, linesize, buffer, buflen, + &offset); + totalsize += copysize; + } +#endif /* Update the file offset */ @@ -255,28 +416,29 @@ static ssize_t kmm_read(FAR struct file *filep, FAR char *buffer, } /**************************************************************************** - * Name: kmm_dup + * Name: meminfo_dup * * Description: * Duplicate open file data in the new file structure. * ****************************************************************************/ -static int kmm_dup(FAR const struct file *oldp, FAR struct file *newp) +static int meminfo_dup(FAR const struct file *oldp, FAR struct file *newp) { - FAR struct kmm_file_s *oldattr; - FAR struct kmm_file_s *newattr; + FAR struct meminfo_file_s *oldattr; + FAR struct meminfo_file_s *newattr; finfo("Dup %p->%p\n", oldp, newp); /* Recover our private data from the old struct file instance */ - oldattr = (FAR struct kmm_file_s *)oldp->f_priv; + oldattr = (FAR struct meminfo_file_s *)oldp->f_priv; DEBUGASSERT(oldattr); /* Allocate a new container to hold the task and attribute selection */ - newattr = (FAR struct kmm_file_s *)kmm_malloc(sizeof(struct kmm_file_s)); + newattr = (FAR struct meminfo_file_s *) + kmm_malloc(sizeof(struct meminfo_file_s)); if (!newattr) { ferr("ERROR: Failed to allocate file attributes\n"); @@ -285,7 +447,7 @@ static int kmm_dup(FAR const struct file *oldp, FAR struct file *newp) /* The copy the file attributes from the old attributes to the new */ - memcpy(newattr, oldattr, sizeof(struct kmm_file_s)); + memcpy(newattr, oldattr, sizeof(struct meminfo_file_s)); /* Save the new attributes in the new file structure */ @@ -294,23 +456,23 @@ static int kmm_dup(FAR const struct file *oldp, FAR struct file *newp) } /**************************************************************************** - * Name: kmm_stat + * Name: meminfo_stat * * Description: Return information about a file or directory * ****************************************************************************/ -static int kmm_stat(FAR const char *relpath, FAR struct stat *buf) +static int meminfo_stat(FAR const char *relpath, FAR struct stat *buf) { - /* "kmm" is the only acceptable value for the relpath */ + /* "meminfo" is the only acceptable value for the relpath */ - if (strcmp(relpath, "kmm") != 0) + if (strcmp(relpath, "meminfo") != 0) { ferr("ERROR: relpath is '%s'\n", relpath); return -ENOENT; } - /* "kmm" is the name for a read-only file */ + /* "meminfo" is the name for a read-only file */ memset(buf, 0, sizeof(struct stat)); buf->st_mode = S_IFREG | S_IROTH | S_IRGRP | S_IRUSR; @@ -321,4 +483,4 @@ static int kmm_stat(FAR const char *relpath, FAR struct stat *buf) * Public Functions ****************************************************************************/ -#endif /* CONFIG_MM_KERNEL_HEAP && CONFIG_FS_PROCFS && !CONFIG_FS_PROCFS_EXCLUDE_KMM */ +#endif /* !CONFIG_FS_PROCFS_EXCLUDE_MEMINFO */ diff --git a/fs/procfs/fs_procfsuptime.c b/fs/procfs/fs_procfsuptime.c index c39ade340746331ede86498db931fcb800c95f75..4e836e7e5db738dd591d5d1cf3cb4e50f366de66 100644 --- a/fs/procfs/fs_procfsuptime.c +++ b/fs/procfs/fs_procfsuptime.c @@ -240,7 +240,7 @@ static ssize_t uptime_read(FAR struct file *filep, FAR char *buffer, { /* System time */ - ticktime = clock_systimer(); + ticktime = clock_systimer() - INITIAL_SYSTEM_TIMER_TICKS; #if defined(CONFIG_HAVE_DOUBLE) && defined(CONFIG_LIBC_FLOATINGPOINT) /* Convert the system up time to a seconds + hundredths of seconds string */ diff --git a/fs/romfs/fs_romfs.c b/fs/romfs/fs_romfs.c index 8b4d11710992b46bc09b135c9eb4a1c241912169..c76e1407282b0d469c5c37baa1ada9a25de5494a 100644 --- a/fs/romfs/fs_romfs.c +++ b/fs/romfs/fs_romfs.c @@ -1,7 +1,8 @@ /**************************************************************************** * rm/romfs/fs_romfs.h * - * Copyright (C) 2008-2009, 2011, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2008-2009, 2011, 2017-2018 Gregory Nutt. All rights + * reserved. * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt @@ -122,6 +123,7 @@ const struct mountpt_operations romfs_operations = NULL, /* sync */ romfs_dup, /* dup */ romfs_fstat, /* fstat */ + NULL, /* truncate */ romfs_opendir, /* opendir */ NULL, /* closedir */ diff --git a/fs/smartfs/Kconfig b/fs/smartfs/Kconfig index 6beb521d4bb6108db4da390deb49bcf7f3059a0d..abd47855dbfeabe1607cbc6ef3d46817bbfd170f 100644 --- a/fs/smartfs/Kconfig +++ b/fs/smartfs/Kconfig @@ -16,6 +16,7 @@ if FS_SMARTFS config SMARTFS_ERASEDSTATE hex "FLASH erased state" default 0xff + range 0x00 0xff ---help--- The erased state of FLASH. This must have one of the values of 0xff or 0x00. diff --git a/fs/smartfs/smartfs.h b/fs/smartfs/smartfs.h index 36ed65b41b872602825ac6feca15a550193af287..b24199a7f383467f5a23e08a9bdc5927516a708f 100644 --- a/fs/smartfs/smartfs.h +++ b/fs/smartfs/smartfs.h @@ -209,12 +209,18 @@ #define SMARTFS_ERASEDSTATE_16BIT (uint16_t) ((CONFIG_SMARTFS_ERASEDSTATE << 8) | \ CONFIG_SMARTFS_ERASEDSTATE) +/* Size of temporary buffer used when a file is zero extended by ftruncate() + * logic. + */ + +#define SMARTFS_TRUNCBUFFER_SIZE 512 + #ifndef offsetof -#define offsetof(type, member) ( (size_t) &( ( (type *) 0)->member)) +# define offsetof(type, member) ((size_t) & (((type *)0)->member)) #endif -#define SMARTFS_NEXTSECTOR(h) ( *((uint16_t *) h->nextsector)) -#define SMARTFS_USED(h) ( *((uint16_t *) h->used)) +#define SMARTFS_NEXTSECTOR(h) (*((uint16_t *)h->nextsector)) +#define SMARTFS_USED(h) (*((uint16_t *)h->used)) #ifdef CONFIG_MTD_SMART_ENABLE_CRC #define CONFIG_SMARTFS_USE_SECTOR_BUFFER @@ -334,7 +340,7 @@ struct smartfs_mountpt_s ****************************************************************************/ /**************************************************************************** - * Internal function prototypes + * Public Functions ****************************************************************************/ /* Semaphore access for internal use */ @@ -348,28 +354,37 @@ struct smartfs_mountpt_s; /* Utility functions */ -int smartfs_mount(struct smartfs_mountpt_s *fs, bool writeable); +int smartfs_mount(FAR struct smartfs_mountpt_s *fs, bool writeable); -int smartfs_unmount(struct smartfs_mountpt_s *fs); +int smartfs_unmount(FAR struct smartfs_mountpt_s *fs); -int smartfs_finddirentry(struct smartfs_mountpt_s *fs, - struct smartfs_entry_s *direntry, const char *relpath, - uint16_t *parentdirsector, const char **filename); +int smartfs_finddirentry(FAR struct smartfs_mountpt_s *fs, + FAR struct smartfs_entry_s *direntry, FAR const char *relpath, + FAR uint16_t *parentdirsector, FAR const char **filename); -int smartfs_createentry(struct smartfs_mountpt_s *fs, - uint16_t parentdirsector, const char* filename, +int smartfs_createentry(FAR struct smartfs_mountpt_s *fs, + uint16_t parentdirsector, FAR const char* filename, uint16_t type, - mode_t mode, struct smartfs_entry_s *direntry, + mode_t mode, FAR struct smartfs_entry_s *direntry, uint16_t sectorno, FAR struct smartfs_ofile_s *sf); -int smartfs_deleteentry(struct smartfs_mountpt_s *fs, - struct smartfs_entry_s *entry); +int smartfs_deleteentry(FAR struct smartfs_mountpt_s *fs, + FAR struct smartfs_entry_s *entry); + +int smartfs_countdirentries(FAR struct smartfs_mountpt_s *fs, + FAR struct smartfs_entry_s *entry); + +int smartfs_sync_internal(FAR struct smartfs_mountpt_s *fs, + FAR struct smartfs_ofile_s *sf); + +off_t smartfs_seek_internal(FAR struct smartfs_mountpt_s *fs, + FAR struct smartfs_ofile_s *sf, off_t offset, int whence); -int smartfs_countdirentries(struct smartfs_mountpt_s *fs, - struct smartfs_entry_s *entry); +int smartfs_shrinkfile(FAR struct smartfs_mountpt_s *fs, + FAR struct smartfs_ofile_s *sf, off_t length); -int smartfs_truncatefile(struct smartfs_mountpt_s *fs, - struct smartfs_entry_s *entry, FAR struct smartfs_ofile_s *sf); +int smartfs_extendfile(FAR struct smartfs_mountpt_s *fs, + FAR struct smartfs_ofile_s *sf, off_t length); uint16_t smartfs_rdle16(FAR const void *val); diff --git a/fs/smartfs/smartfs_smart.c b/fs/smartfs/smartfs_smart.c index 3516c4b28f6808d8af5aa0d39935d652f001fc73..afde4f5c0c6f7a5e3da006db1ca45c41d8e7b191 100644 --- a/fs/smartfs/smartfs_smart.c +++ b/fs/smartfs/smartfs_smart.c @@ -83,6 +83,7 @@ static int smartfs_dup(FAR const struct file *oldp, FAR struct file *newp); static int smartfs_fstat(FAR const struct file *filep, FAR struct stat *buf); +static int smartfs_truncate(FAR struct file *filep, off_t length); static int smartfs_opendir(FAR struct inode *mountpt, FAR const char *relpath, @@ -117,10 +118,6 @@ static int smartfs_stat(FAR struct inode *mountpt, FAR const char *relpath, FAR struct stat *buf); -static off_t smartfs_seek_internal(struct smartfs_mountpt_s *fs, - struct smartfs_ofile_s *sf, - off_t offset, int whence); - /**************************************************************************** * Private Data ****************************************************************************/ @@ -149,6 +146,7 @@ const struct mountpt_operations smartfs_operations = smartfs_sync, /* sync */ smartfs_dup, /* dup */ smartfs_fstat, /* fstat */ + smartfs_truncate, /* truncate */ smartfs_opendir, /* opendir */ NULL, /* closedir */ @@ -270,7 +268,7 @@ static int smartfs_open(FAR struct file *filep, const char *relpath, { /* Truncate the file as part of the open */ - ret = smartfs_truncatefile(fs, &sf->entry, sf); + ret = smartfs_shrinkfile(fs, sf, 0); if (ret < 0) { goto errout_with_buffer; @@ -597,107 +595,6 @@ errout_with_semaphore: return ret; } -/**************************************************************************** - * Name: smartfs_sync_internal - * - * Description: Synchronize the file state on disk to match internal, in- - * memory state. - * - ****************************************************************************/ - -static int smartfs_sync_internal(struct smartfs_mountpt_s *fs, - struct smartfs_ofile_s *sf) -{ - struct smart_read_write_s readwrite; - struct smartfs_chain_header_s *header; - int ret = OK; - -#ifdef CONFIG_SMARTFS_USE_SECTOR_BUFFER - if (sf->bflags & SMARTFS_BFLAG_DIRTY) - { - /* Update the header with the number of bytes written */ - - header = (struct smartfs_chain_header_s *) sf->buffer; - if (*((uint16_t *) header->used) == SMARTFS_ERASEDSTATE_16BIT) - { - *((uint16_t *) header->used) = sf->byteswritten; - } - else - { - *((uint16_t *) header->used) += sf->byteswritten; - } - - /* Write the entire sector to FLASH */ - - readwrite.logsector = sf->currsector; - readwrite.offset = 0; - readwrite.count = fs->fs_llformat.availbytes; - readwrite.buffer = sf->buffer; - ret = FS_IOCTL(fs, BIOC_WRITESECT, (unsigned long) &readwrite); - if (ret < 0) - { - ferr("ERROR: Error %d writing used bytes for sector %d\n", - ret, sf->currsector); - goto errout; - } - - sf->byteswritten = 0; - sf->bflags = 0; - } -#else /* CONFIG_SMARTFS_USE_SECTOR_BUFFER */ - - /* Test if we have written bytes to the current sector that - * need to be recorded in the chain header's used bytes field. */ - - if (sf->byteswritten > 0) - { - finfo("Syncing sector %d\n", sf->currsector); - - /* Read the existing sector used bytes value */ - - readwrite.logsector = sf->currsector; - readwrite.offset = 0; - readwrite.buffer = (uint8_t *) fs->fs_rwbuffer; - readwrite.count = sizeof(struct smartfs_chain_header_s); - ret = FS_IOCTL(fs, BIOC_READSECT, (unsigned long) &readwrite); - if (ret < 0) - { - ferr("ERROR: Error %d reading sector %d data\n", - ret, sf->currsector); - goto errout; - } - - /* Add new byteswritten to existing value */ - - header = (struct smartfs_chain_header_s *) fs->fs_rwbuffer; - if (*((uint16_t *) header->used) == SMARTFS_ERASEDSTATE_16BIT) - { - *((uint16_t *) header->used) = sf->byteswritten; - } - else - { - *((uint16_t *) header->used) += sf->byteswritten; - } - - readwrite.offset = offsetof(struct smartfs_chain_header_s, used); - readwrite.count = sizeof(uint16_t); - readwrite.buffer = (uint8_t *) &fs->fs_rwbuffer[readwrite.offset]; - ret = FS_IOCTL(fs, BIOC_WRITESECT, (unsigned long) &readwrite); - if (ret < 0) - { - ferr("ERROR: Error %d writing used bytes for sector %d\n", - ret, sf->currsector); - goto errout; - } - - sf->byteswritten = 0; - } -#endif /* CONFIG_SMARTFS_USE_SECTOR_BUFFER */ - -errout: - return ret; -} - /**************************************************************************** * Name: smartfs_write ****************************************************************************/ @@ -773,7 +670,9 @@ static ssize_t smartfs_write(FAR struct file *filep, const char *buffer, /* Limit the write based on available data to write */ if (readwrite.count > buflen) - readwrite.count = buflen; + { + readwrite.count = buflen; + } /* Limit the write based on current file length */ @@ -994,161 +893,6 @@ errout_with_semaphore: return ret; } -/**************************************************************************** - * Name: smartfs_seek_internal - * - * Description: Performs the logic of the seek function. This is an internal - * function because it does not provide semaphore protection and - * therefore must be called from one of the other public - * interface routines (open, seek, etc.). - * - ****************************************************************************/ - -static off_t smartfs_seek_internal(struct smartfs_mountpt_s *fs, - struct smartfs_ofile_s *sf, - off_t offset, int whence) -{ - struct smart_read_write_s readwrite; - struct smartfs_chain_header_s *header; - int ret; - off_t newpos; - off_t sectorstartpos; - - /* Test if this is a seek to get the current file pos */ - - if ((whence == SEEK_CUR) && (offset == 0)) - { - return sf->filepos; - } - - /* Test if we need to sync the file */ - - if (sf->byteswritten > 0) - { - /* Perform a sync */ - - smartfs_sync_internal(fs, sf); - } - - /* Calculate the file position to seek to based on current position */ - - switch (whence) - { - case SEEK_SET: - default: - newpos = offset; - break; - - case SEEK_CUR: - newpos = sf->filepos + offset; - break; - - case SEEK_END: - newpos = sf->entry.datlen + offset; - break; - } - - /* Ensure newpos is in range */ - - if (newpos < 0) - { - newpos = 0; - } - - if (newpos > sf->entry.datlen) - { - newpos = sf->entry.datlen; - } - - /* Now perform the seek. Test if we are seeking within the current - * sector and can skip the search to save time. - */ - - sectorstartpos = sf->filepos - (sf->curroffset - sizeof(struct - smartfs_chain_header_s)); - if (newpos >= sectorstartpos && newpos < sectorstartpos + - fs->fs_llformat.availbytes - sizeof(struct smartfs_chain_header_s)) - { - /* Seeking within the current sector. Just update the offset */ - - sf->curroffset = sizeof(struct smartfs_chain_header_s) + newpos-sectorstartpos; - sf->filepos = newpos; - - return newpos; - } - - /* Nope, we have to search for the sector and offset. If the new pos is greater - * than the current pos, then we can start from the beginning of the current - * sector, otherwise we have to start from the beginning of the file. - */ - - if (newpos > sf->filepos) - { - sf->filepos = sectorstartpos; - } - else - { - sf->currsector = sf->entry.firstsector; - sf->filepos = 0; - } - - header = (struct smartfs_chain_header_s *) fs->fs_rwbuffer; - while ((sf->currsector != SMARTFS_ERASEDSTATE_16BIT) && - (sf->filepos + fs->fs_llformat.availbytes - - sizeof(struct smartfs_chain_header_s) < newpos)) - { - /* Read the sector's header */ - - readwrite.logsector = sf->currsector; - readwrite.offset = 0; - readwrite.count = sizeof(struct smartfs_chain_header_s); - readwrite.buffer = (uint8_t *) fs->fs_rwbuffer; - ret = FS_IOCTL(fs, BIOC_READSECT, (unsigned long) &readwrite); - if (ret < 0) - { - ferr("ERROR: Error %d reading sector %d header\n", - ret, sf->currsector); - goto errout; - } - - /* Point to next sector and update filepos */ - - sf->currsector = SMARTFS_NEXTSECTOR(header); - sf->filepos += SMARTFS_USED(header); - } - -#ifdef CONFIG_SMARTFS_USE_SECTOR_BUFFER - - /* When using sector buffering, we must read in the last buffer to our - * sf->buffer in case any changes are made. - */ - - if (sf->currsector != SMARTFS_ERASEDSTATE_16BIT) - { - readwrite.logsector = sf->currsector; - readwrite.offset = 0; - readwrite.count = fs->fs_llformat.availbytes; - readwrite.buffer = (uint8_t *) sf->buffer; - ret = FS_IOCTL(fs, BIOC_READSECT, (unsigned long) &readwrite); - if (ret < 0) - { - ferr("ERROR: Error %d reading sector %d header\n", - ret, sf->currsector); - goto errout; - } - } -#endif - - /* Now calculate the offset */ - - sf->curroffset = sizeof(struct smartfs_chain_header_s) + newpos - sf->filepos; - sf->filepos = newpos; - return newpos; - -errout: - return ret; -} - /**************************************************************************** * Name: smartfs_seek ****************************************************************************/ @@ -1307,6 +1051,79 @@ static int smartfs_fstat(FAR const struct file *filep, FAR struct stat *buf) return OK; } +/**************************************************************************** + * Name: smartfs_truncate + * + * Description: + * Set the length of the open, regular file associated with the file + * structure 'filep' to 'length'. + * + ****************************************************************************/ + +static int smartfs_truncate(FAR struct file *filep, off_t length) +{ + FAR struct inode *inode; + FAR struct smartfs_mountpt_s *fs; + FAR struct smartfs_ofile_s *sf; + off_t oldsize; + int ret; + + DEBUGASSERT(filep->f_priv != NULL && filep->f_inode != NULL); + + /* Recover our private data from the struct file instance */ + + sf = filep->f_priv; + inode = filep->f_inode; + fs = inode->i_private; + + DEBUGASSERT(fs != NULL); + + /* Take the semaphore */ + + smartfs_semtake(fs); + + /* Test the permissions. Only allow truncation if the file was opened with + * write flags. + */ + + if ((sf->oflags & O_WROK) == 0) + { + ret = -EACCES; + goto errout_with_semaphore; + } + + /* Are we shrinking the file? Or extending it? */ + + oldsize = sf->entry.datlen; + if (oldsize == length) + { + /* Let's not and say we did */ + + ret = OK; + } + else if (oldsize > length) + { + /* We are shrinking the file */ + + ret = smartfs_shrinkfile(fs, sf, length); + } + else + { + /* Otherwise we are extending the file. This is essentially the same + * as a write except that (1) we write zeros and (2) we don't update + * the file position. + */ + + ret = smartfs_extendfile(fs, sf, length); + } + +errout_with_semaphore: + /* Relinquish exclusive access */ + + smartfs_semgive(fs); + return ret; +} + /**************************************************************************** * Name: smartfs_opendir * diff --git a/fs/smartfs/smartfs_utils.c b/fs/smartfs/smartfs_utils.c index 8b97b70d5ef633d5922036c394c3f21893df22f2..da37b922124b7c3648c7cba15d61f2d4ca8b79af 100644 --- a/fs/smartfs/smartfs_utils.c +++ b/fs/smartfs/smartfs_utils.c @@ -711,9 +711,9 @@ int smartfs_finddirentry(struct smartfs_mountpt_s *fs, /* Add used bytes to the total and point to next sector */ - if (*((uint16_t *) header->used) != SMARTFS_ERASEDSTATE_16BIT) + if (*((uint16_t *)header->used) != SMARTFS_ERASEDSTATE_16BIT) { - direntry->datlen += *((uint16_t *) header->used); + direntry->datlen += *((uint16_t *)header->used); } dirsector = SMARTFS_NEXTSECTOR(header); @@ -936,7 +936,7 @@ int smartfs_createentry(FAR struct smartfs_mountpt_s *fs, /* Chain the next sector into this sector sector */ - *((uint16_t *) chainheader->nextsector) = nextsector; + *((FAR uint16_t *)chainheader->nextsector) = nextsector; readwrite.offset = offsetof(struct smartfs_chain_header_s, nextsector); readwrite.count = sizeof(uint16_t); @@ -1263,8 +1263,9 @@ int smartfs_deleteentry(struct smartfs_mountpt_s *fs, SMARTFS_NEXTSECTOR(header) = nextsector; readwrite.offset = offsetof(struct smartfs_chain_header_s, nextsector); - readwrite.count = sizeof(uint16_t); + readwrite.count = sizeof(uint16_t); readwrite.buffer = header->nextsector; + ret = FS_IOCTL(fs, BIOC_WRITESECT, (unsigned long) &readwrite); if (ret < 0) { @@ -1388,92 +1389,403 @@ errout: } /**************************************************************************** - * Name: smartfs_truncatefile + * Name: smartfs_sync_internal * - * Description: Truncates an existing file on the device so that it occupies - * zero bytes and can be completely re-written. + * Description: + * Synchronize the file state on disk to match internal, in-memory state. * ****************************************************************************/ -int smartfs_truncatefile(struct smartfs_mountpt_s *fs, - struct smartfs_entry_s *entry, FAR struct smartfs_ofile_s *sf) +int smartfs_sync_internal(FAR struct smartfs_mountpt_s *fs, + FAR struct smartfs_ofile_s *sf) { - int ret; - uint16_t nextsector; - uint16_t sector; - struct smartfs_chain_header_s *header; - struct smart_read_write_s readwrite; + FAR struct smartfs_chain_header_s *header; + struct smart_read_write_s readwrite; + int ret = OK; + +#ifdef CONFIG_SMARTFS_USE_SECTOR_BUFFER + if (sf->bflags & SMARTFS_BFLAG_DIRTY) + { + /* Update the header with the number of bytes written */ + + header = (struct smartfs_chain_header_s *)sf->buffer; + if (*((uint16_t *)header->used) == SMARTFS_ERASEDSTATE_16BIT) + { + *((uint16_t *)header->used) = sf->byteswritten; + } + else + { + *((uint16_t *)header->used) += sf->byteswritten; + } + + /* Write the entire sector to FLASH */ + + readwrite.logsector = sf->currsector; + readwrite.offset = 0; + readwrite.count = fs->fs_llformat.availbytes; + readwrite.buffer = sf->buffer; + + ret = FS_IOCTL(fs, BIOC_WRITESECT, (unsigned long) &readwrite); + if (ret < 0) + { + ferr("ERROR: Error %d writing used bytes for sector %d\n", + ret, sf->currsector); + goto errout; + } + + sf->byteswritten = 0; + sf->bflags = 0; + } +#else /* CONFIG_SMARTFS_USE_SECTOR_BUFFER */ + + /* Test if we have written bytes to the current sector that + * need to be recorded in the chain header's used bytes field. */ + + if (sf->byteswritten > 0) + { + finfo("Syncing sector %d\n", sf->currsector); + + /* Read the existing sector used bytes value */ + + readwrite.logsector = sf->currsector; + readwrite.offset = 0; + readwrite.buffer = (uint8_t *) fs->fs_rwbuffer; + readwrite.count = sizeof(struct smartfs_chain_header_s); + + ret = FS_IOCTL(fs, BIOC_READSECT, (unsigned long) &readwrite); + if (ret < 0) + { + ferr("ERROR: Error %d reading sector %d data\n", + ret, sf->currsector); + goto errout; + } + + /* Add new byteswritten to existing value */ + + header = (struct smartfs_chain_header_s *) fs->fs_rwbuffer; + if (*((uint16_t *) header->used) == SMARTFS_ERASEDSTATE_16BIT) + { + *((uint16_t *) header->used) = sf->byteswritten; + } + else + { + *((uint16_t *) header->used) += sf->byteswritten; + } + + readwrite.offset = offsetof(struct smartfs_chain_header_s, used); + readwrite.count = sizeof(uint16_t); + readwrite.buffer = (uint8_t *) &fs->fs_rwbuffer[readwrite.offset]; + + ret = FS_IOCTL(fs, BIOC_WRITESECT, (unsigned long) &readwrite); + if (ret < 0) + { + ferr("ERROR: Error %d writing used bytes for sector %d\n", + ret, sf->currsector); + goto errout; + } + + sf->byteswritten = 0; + } +#endif /* CONFIG_SMARTFS_USE_SECTOR_BUFFER */ + +errout: + return ret; +} + +/**************************************************************************** + * Name: smartfs_seek_internal + * + * Description: + * Performs the logic of the seek function. This is an internal function + * because it does not provide semaphore protection and therefore must be + * called from one of the other public interface routines (open, seek, + * etc.). + * + ****************************************************************************/ + +off_t smartfs_seek_internal(FAR struct smartfs_mountpt_s *fs, + FAR struct smartfs_ofile_s *sf, + off_t offset, int whence) +{ + FAR struct smartfs_chain_header_s *header; + struct smart_read_write_s readwrite; + off_t newpos; + off_t sectorstartpos; + int ret; + + /* Test if this is a seek to get the current file pos */ + + if ((whence == SEEK_CUR) && (offset == 0)) + { + return sf->filepos; + } + + /* Test if we need to sync the file */ + + if (sf->byteswritten > 0) + { + /* Perform a sync */ + + smartfs_sync_internal(fs, sf); + } + + /* Calculate the file position to seek to based on current position */ + + switch (whence) + { + case SEEK_SET: + default: + newpos = offset; + break; + + case SEEK_CUR: + newpos = sf->filepos + offset; + break; + + case SEEK_END: + newpos = sf->entry.datlen + offset; + break; + } + + /* Ensure newpos is in range */ + + if (newpos < 0) + { + newpos = 0; + } + + if (newpos > sf->entry.datlen) + { + newpos = sf->entry.datlen; + } + + /* Now perform the seek. Test if we are seeking within the current + * sector and can skip the search to save time. + */ + + sectorstartpos = sf->filepos - (sf->curroffset - sizeof(struct + smartfs_chain_header_s)); + + if (newpos >= sectorstartpos && newpos < sectorstartpos + + fs->fs_llformat.availbytes - sizeof(struct smartfs_chain_header_s)) + { + /* Seeking within the current sector. Just update the offset */ + + sf->curroffset = sizeof(struct smartfs_chain_header_s) + newpos-sectorstartpos; + sf->filepos = newpos; + + return newpos; + } + + /* Nope, we have to search for the sector and offset. If the new pos is greater + * than the current pos, then we can start from the beginning of the current + * sector, otherwise we have to start from the beginning of the file. + */ + + if (newpos > sf->filepos) + { + sf->filepos = sectorstartpos; + } + else + { + sf->currsector = sf->entry.firstsector; + sf->filepos = 0; + } + + header = (struct smartfs_chain_header_s *) fs->fs_rwbuffer; + while ((sf->currsector != SMARTFS_ERASEDSTATE_16BIT) && + (sf->filepos + fs->fs_llformat.availbytes - + sizeof(struct smartfs_chain_header_s) < newpos)) + { + /* Read the sector's header */ + + readwrite.logsector = sf->currsector; + readwrite.offset = 0; + readwrite.count = sizeof(struct smartfs_chain_header_s); + readwrite.buffer = (uint8_t *) fs->fs_rwbuffer; + + ret = FS_IOCTL(fs, BIOC_READSECT, (unsigned long) &readwrite); + if (ret < 0) + { + ferr("ERROR: Error %d reading sector %d header\n", + ret, sf->currsector); + goto errout; + } + + /* Point to next sector and update filepos */ + + sf->currsector = SMARTFS_NEXTSECTOR(header); + sf->filepos += SMARTFS_USED(header); + } + +#ifdef CONFIG_SMARTFS_USE_SECTOR_BUFFER + + /* When using sector buffering, we must read in the last buffer to our + * sf->buffer in case any changes are made. + */ + + if (sf->currsector != SMARTFS_ERASEDSTATE_16BIT) + { + readwrite.logsector = sf->currsector; + readwrite.offset = 0; + readwrite.count = fs->fs_llformat.availbytes; + readwrite.buffer = (uint8_t *) sf->buffer; + ret = FS_IOCTL(fs, BIOC_READSECT, (unsigned long) &readwrite); + if (ret < 0) + { + ferr("ERROR: Error %d reading sector %d header\n", + ret, sf->currsector); + goto errout; + } + } +#endif + + /* Now calculate the offset */ + + sf->curroffset = sizeof(struct smartfs_chain_header_s) + newpos - sf->filepos; + sf->filepos = newpos; + return newpos; + +errout: + return ret; +} + +/**************************************************************************** + * Name: smartfs_shrinkfile + * + * Description: + * Shrink the size existing file to to the specified length + * + ****************************************************************************/ + +int smartfs_shrinkfile(FAR struct smartfs_mountpt_s *fs, + FAR struct smartfs_ofile_s *sf, off_t length) +{ + FAR struct smartfs_chain_header_s *header; + FAR struct smartfs_entry_s *entry; + FAR uint8_t *dest; + struct smart_read_write_s readwrite; + uint16_t nextsector; + uint16_t sector; + off_t remaining; + off_t destsize; + off_t available; + off_t offset; + int ret; /* Walk through the directory's sectors and count entries */ + entry = &sf->entry; nextsector = entry->firstsector; - header = (struct smartfs_chain_header_s *) fs->fs_rwbuffer; + header = (struct smartfs_chain_header_s *)fs->fs_rwbuffer; + remaining = length; + available = fs->fs_llformat.availbytes - sizeof(struct smartfs_chain_header_s); while (nextsector != SMARTFS_ERASEDSTATE_16BIT) { - /* Read the next sector's header into our buffer */ + /* Read the next sector into our buffer */ readwrite.logsector = nextsector; - readwrite.offset = 0; - readwrite.count = sizeof(struct smartfs_chain_header_s); - readwrite.buffer = (uint8_t *) fs->fs_rwbuffer; + readwrite.offset = 0; + readwrite.count = fs->fs_llformat.availbytes; + readwrite.buffer = (FAR uint8_t *)fs->fs_rwbuffer; + ret = FS_IOCTL(fs, BIOC_READSECT, (unsigned long) &readwrite); if (ret < 0) { ferr("ERROR: Error reading sector %d header\n", nextsector); - goto errout; + return ret; } /* Get the next chained sector */ sector = SMARTFS_NEXTSECTOR(header); - /* If this is the 1st sector of the file, then just overwrite - * the sector data with the erased state value. The underlying - * SMART block driver will detect this and release the old - * sector and create a new one with the new (blank) data. +#ifdef CONFIG_SMARTFS_USE_SECTOR_BUFFER + /* When we have a sector buffer in use, simply skip the first sector. + * It will be handled below. */ if (nextsector == entry->firstsector) { -#ifdef CONFIG_SMARTFS_USE_SECTOR_BUFFER - - /* When we have a sector buffer in use, simply skip the first sector */ - - nextsector = sector; - continue; + if (remaining > available) + { + remaining -= available; + } + else + { + remaining = 0; + } + } + else +#endif + /* Are we retaining the sector it its entirety? */ -#else + if (remaining >= available) + { + /* Yes... skip to the next sector */ - /* Fill our buffer with erased data */ + remaining -= available; + } - memset(fs->fs_rwbuffer, CONFIG_SMARTFS_ERASEDSTATE, fs->fs_llformat.availbytes); - header->type = SMARTFS_SECTOR_TYPE_FILE; + /* Are we removing the sector it its entirety? */ - /* Now write the new sector data */ + else if (remaining <= 0 && nextsector != entry->firstsector) + { + /* Yes.. just release the sector */ - readwrite.count = fs->fs_llformat.availbytes; - ret = FS_IOCTL(fs, BIOC_WRITESECT, (unsigned long) &readwrite); + ret = FS_IOCTL(fs, BIOC_FREESECT, (unsigned long)nextsector); if (ret < 0) { - ferr("ERROR: Error blanking 1st sector (%d) of file\n", nextsector); - goto errout; + ferr("ERROR: Error freeing sector %d\n", nextsector); + return ret; } - - /* Set the entry's data length to zero ... we just truncated */ - - entry->datlen = 0; -#endif /* CONFIG_SMARTFS_USE_SECTOR_BUFFER */ } else { - /* Not the 1st sector -- release it */ + /* No.. Fill our buffer with erased data, retaining any still- + * valid bytes at the beginning of the buffer. + * + * Because of the preceding tests we know that + * 0 <= remaining < available. A special case is remaining == 0 + * and nextsector == firstsector. In that case, we need to + * overwrite the sector data with the erased state value. The + * underlying SMART block driver will detect this and release the + * old sector and create a new one with the new (blank) data. + * + * Otherwise, we need to preserve the header and overwrite some of + * the data. + */ + + if (remaining == 0) + { + dest = (FAR uint8_t *)fs->fs_rwbuffer; + destsize = fs->fs_llformat.availbytes; + } + else + { + offset = sizeof(struct smartfs_chain_header_s) + remaining; + dest = (FAR uint8_t *)&fs->fs_rwbuffer[offset]; + destsize = fs->fs_llformat.availbytes - offset; + + *((uint16_t *)header->used) = remaining; + *((uint16_t *)header->nextsector) = SMARTFS_ERASEDSTATE_16BIT; - ret = FS_IOCTL(fs, BIOC_FREESECT, (unsigned long) nextsector); + remaining = 0; + } + + memset(dest, CONFIG_SMARTFS_ERASEDSTATE, destsize); + header->type = SMARTFS_SECTOR_TYPE_FILE; + + /* Now write the new sector data */ + + readwrite.count = fs->fs_llformat.availbytes; + + ret = FS_IOCTL(fs, BIOC_WRITESECT, (unsigned long)&readwrite); if (ret < 0) { - ferr("ERROR: Error freeing sector %d\n", nextsector); - goto errout; + ferr("ERROR: Error blanking 1st sector (%d) of file\n", nextsector); + return ret; } } @@ -1482,34 +1794,292 @@ int smartfs_truncatefile(struct smartfs_mountpt_s *fs, nextsector = sector; } +#ifdef CONFIG_SMARTFS_USE_SECTOR_BUFFER /* Now deal with the first sector in the event we are using a sector buffer * like we would be if CRC is enabled. + * + * Using sector buffer and we have an open file context. Just update the + * sector buffer in the open file context. */ -#ifdef CONFIG_SMARTFS_USE_SECTOR_BUFFER - if (sf) + if (length < fs->fs_llformat.availbytes) { - /* Using sector buffer and we have an open file context. Just update - * the sector buffer in the open file context. - */ + /* Read the entire sector */ readwrite.logsector = entry->firstsector; - readwrite.offset = 0; - readwrite.count = sizeof(struct smartfs_chain_header_s); - readwrite.buffer = (uint8_t *) fs->fs_rwbuffer; - ret = FS_IOCTL(fs, BIOC_READSECT, (unsigned long) &readwrite); + readwrite.offset = 0; + readwrite.count = fs->fs_llformat.availbytes; + readwrite.buffer = (uint8_t *)sf->buffer; - memset(sf->buffer, CONFIG_SMARTFS_ERASEDSTATE, fs->fs_llformat.availbytes); - header = (struct smartfs_chain_header_s *) sf->buffer; - header->type = SMARTFS_SECTOR_TYPE_FILE; - sf->bflags = SMARTFS_BFLAG_DIRTY; - entry->datlen = 0; + ret = FS_IOCTL(fs, BIOC_READSECT, (unsigned long)&readwrite); + if (ret < 0) + { + return ret; + } + + /* Retain any valid data at the beginning of the sector, including the + * header. Special case length == 0 + */ + + if (length == 0) + { + dest = (FAR uint8_t *)&sf->buffer; + destsize = fs->fs_llformat.availbytes; + else + { + offset = sizeof(struct smartfs_chain_header_s) + length; + dest = (FAR uint8_t *)&sf->buffer[offset]; + destsize = fs->fs_llformat.availbytes - offset; + + header = (struct smartfs_chain_header_s *)sf->buffer; + *((uint16_t *)header->used) = length; + *((uint16_t *)header->nextsector) = SMARTFS_ERASEDSTATE_16BIT; + } + + memset(dest, CONFIG_SMARTFS_ERASEDSTATE, destsize); + + header = (struct smartfs_chain_header_s *)sf->buffer; + header->type = SMARTFS_SECTOR_TYPE_FILE; + sf->bflags = SMARTFS_BFLAG_DIRTY; } #endif + entry->datlen = length; + return OK; +} + +/**************************************************************************** + * Name: smartfs_extendfile + * + * Description: + * Zero-extend the length of a regular file to 'length'. + * + ****************************************************************************/ + +int smartfs_extendfile(FAR struct smartfs_mountpt_s *fs, + FAR struct smartfs_ofile_s *sf, off_t length) +{ + struct smart_read_write_s readwrite; + FAR struct smartfs_chain_header_s *header; +#ifndef CONFIG_SMARTFS_USE_SECTOR_BUFFER + FAR uint8_t *buffer; +#endif + off_t remaining; + off_t savepos; + off_t oldsize; + int ret; + + /* We are zero-extending the file. This is essentially the same as a + * write except that (1) we write zeros and (2) we don't update the file + * position. + */ + +#ifndef CONFIG_SMARTFS_USE_SECTOR_BUFFER + /* In order to perform the writes we will have to have a sector buffer. If + * SmartFS is not configured with a sector buffer then we will, then we + * will, unfortunately, need to allocate one. + */ + + buffer = (FAR uint8_t *)kmm_malloc(SMARTFS_TRUNCBUFFER_SIZE); + if (buffer == NULL) + { + return -ENOMEM; + } +#endif + + /* Loop until either (1) the file has been fully extended with zeroed data + * or (2) an error occurs. We assume we start with the current sector in + * cache (ff_currentsector) + */ + + oldsize = sf->entry.datlen; + remaining = length - oldsize; + DEBUGASSERT(length > oldsize); + + /* Seek to the end of the file for the append/write operation, remembering + * the current file position. It will be retored before returneding; the + * truncate operation must not alter the file position. + */ + + savepos = sf->filepos; + (void)smartfs_seek_internal(fs, sf, 0, SEEK_END); + + while (remaining > 0) + { + /* We will fill up the current sector. Write data to the current + * sector first. + */ + +#ifdef CONFIG_SMARTFS_USE_SECTOR_BUFFER + readwrite.count = fs->fs_llformat.availbytes - sf->curroffset; + if (readwrite.count > remaining) + { + readwrite.count = remaining; + } + + memset(&sf->buffer[sf->curroffset], 0, readwrite.count); + sf->bflags |= SMARTFS_BFLAG_DIRTY; + +#else /* CONFIG_SMARTFS_USE_SECTOR_BUFFER */ + readwrite.offset = sf->curroffset; + readwrite.logsector = sf->currsector; + readwrite.buffer = buffer; + + /* Select max size that available in the current sector */ + + readwrite.count = fs->fs_llformat.availbytes - sf->curroffset; + if (readwrite.count > remaining) + { + /* Limit the write to the size for our smaller working buffer*/ + + readwrite.count = SMARTFS_TRUNCBUFFER_SIZE; + } + + if (readwrite.count > remaining) + { + /* Futher limit the write to the remaining bytes to write */ + + readwrite.count = remaining; + } + + /* Perform the write */ + + if (readwrite.count > 0) + { + ret = FS_IOCTL(fs, BIOC_WRITESECT, (unsigned long) &readwrite); + if (ret < 0) + { + ferr("ERROR: Error %d writing sector %d data\n", + ret, sf->currsector); + goto errout_with_buffer; + } + } +#endif /* CONFIG_SMARTFS_USE_SECTOR_BUFFER */ + + /* Update our control variables */ + + sf->entry.datlen += readwrite.count; + sf->byteswritten += readwrite.count; + sf->curroffset += readwrite.count; + remaining -= readwrite.count; + + /* Test if we wrote a full sector of data */ + +#ifdef CONFIG_SMARTFS_USE_SECTOR_BUFFER + if (sf->curroffset == fs->fs_llformat.availbytes && remaining) + { + /* First get a new chained sector */ + + ret = FS_IOCTL(fs, BIOC_ALLOCSECT, 0xFFFF); + if (ret < 0) + { + ferr("ERROR: Error %d allocating new sector\n", ret); + goto errout_with_buffer; + } + + /* Copy the new sector to the old one and chain it */ + + header = (struct smartfs_chain_header_s *) sf->buffer; + *((uint16_t *)header->nextsector) = (uint16_t)ret; + + /* Now sync the file to write this sector out */ + + ret = smartfs_sync_internal(fs, sf); + if (ret != OK) + { + goto errout_with_buffer; + } + + /* Record the new sector in our tracking variables and reset the + * offset to "zero". + */ + + if (sf->currsector == SMARTFS_NEXTSECTOR(header)) + { + /* Error allocating logical sector! */ + + ferr("ERROR: Duplicate logical sector %d\n", sf->currsector); + } + + sf->bflags = SMARTFS_BFLAG_DIRTY; + sf->currsector = SMARTFS_NEXTSECTOR(header); + sf->curroffset = sizeof(struct smartfs_chain_header_s); + memset(sf->buffer, CONFIG_SMARTFS_ERASEDSTATE, fs->fs_llformat.availbytes); + header->type = SMARTFS_DIRENT_TYPE_FILE; + } +#else /* CONFIG_SMARTFS_USE_SECTOR_BUFFER */ + + if (sf->curroffset == fs->fs_llformat.availbytes) + { + /* Sync the file to write this sector out */ + + ret = smartfs_sync_internal(fs, sf); + if (ret != OK) + { + goto errout_with_buffer; + } + + /* Allocate a new sector if needed */ + + if (remaining > 0) + { + /* Allocate a new sector */ + + ret = FS_IOCTL(fs, BIOC_ALLOCSECT, 0xFFFF); + if (ret < 0) + { + ferr("ERROR: Error %d allocating new sector\n", ret); + goto errout_with_buffer; + } + + /* Copy the new sector to the old one and chain it */ + + header = (struct smartfs_chain_header_s *)fs->fs_rwbuffer; + *((FAR uint16_t *)header->nextsector) = (uint16_t)ret; + + readwrite.offset = offsetof(struct smartfs_chain_header_s, + nextsector); + readwrite.buffer = (FAR uint8_t *)header->nextsector; + readwrite.count = sizeof(uint16_t); + + ret = FS_IOCTL(fs, BIOC_WRITESECT, (unsigned long) &readwrite); + if (ret < 0) + { + ferr("ERROR: Error %d writing next sector\n", ret); + goto errout_with_buffer; + } + + /* Record the new sector in our tracking variables and + * reset the offset to "zero". + */ + + if (sf->currsector == SMARTFS_NEXTSECTOR(header)) + { + /* Error allocating logical sector! */ + + ferr("ERROR: Duplicate logical sector %d\n", sf->currsector); + } + + sf->currsector = SMARTFS_NEXTSECTOR(header); + sf->curroffset = sizeof(struct smartfs_chain_header_s); + } + } +#endif /* CONFIG_SMARTFS_USE_SECTOR_BUFFER */ + } + + /* The file was successfully extended with zeros */ + ret = OK; -errout: +errout_with_buffer: +#ifdef CONFIG_SMARTFS_USE_SECTOR_BUFFER + /* Release the allocated buffer */ + + kmm_free(buffer); +#endif + /* Restore the original file position */ + + (void)smartfs_seek_internal(fs, sf, savepos, SEEK_SET); return ret; } diff --git a/fs/tmpfs/fs_tmpfs.c b/fs/tmpfs/fs_tmpfs.c index 3725bd0cc43dccc20928b48ad5bb63f7f34e8631..fe5a44be13b40ba351f74b4349045cd6a444f5a2 100644 --- a/fs/tmpfs/fs_tmpfs.c +++ b/fs/tmpfs/fs_tmpfs.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/tmpfs/fs_tmpfs.c * - * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -140,6 +140,7 @@ static off_t tmpfs_seek(FAR struct file *filep, off_t offset, int whence); static int tmpfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg); static int tmpfs_dup(FAR const struct file *oldp, FAR struct file *newp); static int tmpfs_fstat(FAR const struct file *filep, FAR struct stat *buf); +static int tmpfs_truncate(FAR struct file *filep, off_t length); static int tmpfs_opendir(FAR struct inode *mountpt, FAR const char *relpath, FAR struct fs_dirent_s *dir); @@ -177,16 +178,21 @@ const struct mountpt_operations tmpfs_operations = tmpfs_write, /* write */ tmpfs_seek, /* seek */ tmpfs_ioctl, /* ioctl */ + NULL, /* sync */ tmpfs_dup, /* dup */ tmpfs_fstat, /* fstat */ + tmpfs_truncate, /* truncate */ + tmpfs_opendir, /* opendir */ tmpfs_closedir, /* closedir */ tmpfs_readdir, /* readdir */ tmpfs_rewinddir, /* rewinddir */ + tmpfs_bind, /* bind */ tmpfs_unbind, /* unbind */ tmpfs_statfs, /* statfs */ + tmpfs_unlink, /* unlink */ tmpfs_mkdir, /* mkdir */ tmpfs_rmdir, /* rmdir */ @@ -378,7 +384,7 @@ static int tmpfs_realloc_file(FAR struct tmpfs_file_s **tfo, size_t allocsize; size_t delta; - /* Check if the current allocation is sufficent */ + /* Check if the current allocation is sufficient */ objsize = SIZEOF_TMPFS_FILE(newsize); @@ -1619,7 +1625,7 @@ static ssize_t tmpfs_write(FAR struct file *filep, FAR const char *buffer, tmpfs_lock_file(tfo); - /* Handle attempts to read beyond the end of the file */ + /* Handle attempts to write beyond the end of the file */ startpos = filep->f_pos; nwritten = buflen; @@ -1691,7 +1697,7 @@ static off_t tmpfs_seek(FAR struct file *filep, off_t offset, int whence) return -EINVAL; } - /* Attempts to set the position beyound the end of file will + /* Attempts to set the position beyond the end of file will * work if the file is open for write access. * * REVISIT: This simple implementation has no per-open storage that @@ -1814,6 +1820,63 @@ static int tmpfs_fstat(FAR const struct file *filep, FAR struct stat *buf) return OK; } +/**************************************************************************** + * Name: tmpfs_truncate + ****************************************************************************/ + +static int tmpfs_truncate(FAR struct file *filep, off_t length) +{ + FAR struct tmpfs_file_s *tfo; + size_t oldsize; + int ret = OK; + + finfo("filep: %p length: %ld\n", filep, (long)length); + DEBUGASSERT(filep != NULL && length >= 0); + + /* Recover our private data from the struct file instance */ + + tfo = filep->f_priv; + + /* Get exclusive access to the file */ + + tmpfs_lock_file(tfo); + + /* Get the old size of the file. Do nothing if the file size is not + * changing. + */ + + oldsize = tfo->tfo_size; + if (oldsize != length) + { + /* The size is changing.. up or down. Reallocate the file memory. */ + + ret = tmpfs_realloc_file(&tfo, (size_t)length); + if (ret < 0) + { + goto errout_with_lock; + } + + filep->f_priv = tfo; + + /* If the size has increased, then we need to zero the newly added + * memory. + */ + + if (length > oldsize) + { + memset(&tfo->tfo_data[oldsize], 0, length - oldsize); + } + + ret = OK; + } + + /* Release the lock on the file */ + +errout_with_lock: + tmpfs_unlock_file(tfo); + return ret; +} + /**************************************************************************** * Name: tmpfs_opendir ****************************************************************************/ diff --git a/fs/unionfs/fs_unionfs.c b/fs/unionfs/fs_unionfs.c index 97717860b06a50c676cc293870ac152cc624bf05..0c61c2e7a0c79caaff46d912ccaf870ddabe361a 100644 --- a/fs/unionfs/fs_unionfs.c +++ b/fs/unionfs/fs_unionfs.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/unionfs/fs_unionfs.c * - * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -162,6 +162,7 @@ static int unionfs_dup(FAR const struct file *oldp, FAR struct file *newp); static int unionfs_fstat(FAR const struct file *filep, FAR struct stat *buf); +static int unionfs_truncate(FAR struct file *filep, off_t length); /* Operations on directories */ @@ -218,6 +219,7 @@ static const struct mountpt_operations g_unionfs_mops = unionfs_sync, /* sync */ unionfs_dup, /* dup */ unionfs_fstat, /* fstat */ + unionfs_truncate, /* truncate */ unionfs_opendir, /* opendir */ unionfs_closedir, /* closedir */ @@ -952,7 +954,7 @@ static int unionfs_close(FAR struct file *filep) /* Perform the lower level close operation */ - if (ops->close) + if (ops->close != NULL) { ret = ops->close(&uf->uf_file); } @@ -1012,9 +1014,9 @@ static ssize_t unionfs_read(FAR struct file *filep, FAR char *buffer, DEBUGASSERT(um != NULL && um->um_node != NULL && um->um_node->u.i_mops != NULL); ops = um->um_node->u.i_mops; - /* Perform the lower level write operation */ + /* Perform the lower level read operation */ - if (ops->read) + if (ops->read != NULL) { ret = ops->read(&uf->uf_file, buffer, buflen); } @@ -1062,7 +1064,7 @@ static ssize_t unionfs_write(FAR struct file *filep, FAR const char *buffer, /* Perform the lower level write operation */ - if (ops->write) + if (ops->write != NULL) { ret = ops->write(&uf->uf_file, buffer, buflen); } @@ -1109,7 +1111,7 @@ static off_t unionfs_seek(FAR struct file *filep, off_t offset, int whence) /* Invoke the file seek method if available */ - if (ops->seek) + if (ops->seek != NULL) { offset = ops->seek(&uf->uf_file, offset, whence); } @@ -1185,7 +1187,7 @@ static int unionfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg) /* Perform the lower level ioctl operation */ - if (ops->ioctl) + if (ops->ioctl != NULL) { ret = ops->ioctl(&uf->uf_file, cmd, arg); } @@ -1206,7 +1208,7 @@ static int unionfs_sync(FAR struct file *filep) FAR const struct mountpt_operations *ops; int ret = -EINVAL; - finfo("Entry\n"); + finfo("filep=%p\n", filep); /* Recover the open file data from the struct file instance */ @@ -1232,7 +1234,7 @@ static int unionfs_sync(FAR struct file *filep) /* Perform the lower level sync operation */ - if (ops->sync) + if (ops->sync != NULL) { ret = ops->sync(&uf->uf_file); } @@ -1254,7 +1256,7 @@ static int unionfs_dup(FAR const struct file *oldp, FAR struct file *newp) FAR const struct mountpt_operations *ops; int ret = -ENOMEM; - finfo("Entry\n"); + finfo("oldp=%p newp=%p\n", oldp, newp); /* Recover the open file data from the struct file instance */ @@ -1293,7 +1295,7 @@ static int unionfs_dup(FAR const struct file *oldp, FAR struct file *newp) /* Then perform the lower lowel dup operation */ ret = OK; - if (ops->dup) + if (ops->dup != NULL) { ret = ops->dup(&oldpriv->uf_file, &newpriv->uf_file); if (ret < 0) @@ -1328,7 +1330,7 @@ static int unionfs_fstat(FAR const struct file *filep, FAR struct stat *buf) FAR const struct mountpt_operations *ops; int ret = -EPERM; - finfo("Entry\n"); + finfo("filep=%p buf=%p\n"); /* Recover the open file data from the struct file instance */ @@ -1354,7 +1356,7 @@ static int unionfs_fstat(FAR const struct file *filep, FAR struct stat *buf) /* Perform the lower level write operation */ - if (ops->fstat) + if (ops->fstat != NULL) { ret = ops->fstat(&uf->uf_file, buf); } @@ -1363,6 +1365,57 @@ static int unionfs_fstat(FAR const struct file *filep, FAR struct stat *buf) return ret; } +/**************************************************************************** + * Name: unionfs_truncate + * + * Description: + * Set the size of the file references by 'filep' to 'length'. + * + ****************************************************************************/ + +static int unionfs_truncate(FAR struct file *filep, off_t length) +{ + FAR struct unionfs_inode_s *ui; + FAR struct unionfs_file_s *uf; + FAR struct unionfs_mountpt_s *um; + FAR const struct mountpt_operations *ops; + int ret = -EPERM; + + finfo("filep=%p length=%ld\n", filep, (long)length); + + /* Recover the open file data from the struct file instance */ + + DEBUGASSERT(filep != NULL && filep->f_inode != NULL); + ui = (FAR struct unionfs_inode_s *)filep->f_inode->i_private; + + /* Get exclusive access to the file system data structures */ + + ret = unionfs_semtake(ui, false); + if (ret < 0) + { + return ret; + } + + DEBUGASSERT(ui != NULL && filep->f_priv != NULL); + uf = (FAR struct unionfs_file_s *)filep->f_priv; + + DEBUGASSERT(uf->uf_ndx == 0 || uf->uf_ndx == 1); + um = &ui->ui_fs[uf->uf_ndx]; + + DEBUGASSERT(um != NULL && um->um_node != NULL && um->um_node->u.i_mops != NULL); + ops = um->um_node->u.i_mops; + + /* Perform the lower level write operation */ + + if (ops->truncate != NULL) + { + ret = ops->truncate(&uf->uf_file, length); + } + + unionfs_semgive(ui); + return ret; +} + /**************************************************************************** * Name: unionfs_opendir ****************************************************************************/ @@ -1508,7 +1561,7 @@ static int unionfs_opendir(FAR struct inode *mountpt, FAR const char *relpath, errout_with_fs2open: ops = ui->ui_fs[1].um_node->u.i_mops; DEBUGASSERT(ops != NULL); - if (ops->closedir) + if (ops->closedir != NULL) { ret = ops->closedir(um->um_node, fu->fu_lower[1]); } @@ -1540,7 +1593,7 @@ static int unionfs_closedir(FAR struct inode *mountpt, int ret = OK; int i; - finfo("Entry\n"); + finfo("mountpt=%p dir=%p\n", mountpt, dir); /* Recover the union file system data from the struct inode instance */ @@ -1569,7 +1622,7 @@ static int unionfs_closedir(FAR struct inode *mountpt, /* Perform the lower level closedir operation */ - if (ops->closedir) + if (ops->closedir != NULL) { ret = ops->closedir(um->um_node, fu->fu_lower[i]); } @@ -1696,7 +1749,7 @@ static int unionfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir) /* Perform the lower level readdir operation */ - if (ops->readdir) + if (ops->readdir != NULL) { /* Loop if we discard duplicate directory entries in filey system 2 */ @@ -1873,7 +1926,7 @@ static int unionfs_rewinddir(struct inode *mountpt, struct fs_dirent_s *dir) FAR struct fs_unionfsdir_s *fu; int ret; - finfo("Entry\n"); + finfo("mountpt=%p dir=%p\n", mountpt, dir); /* Recover the union file system data from the struct inode instance */ @@ -1937,7 +1990,7 @@ static int unionfs_unbind(FAR void *handle, FAR struct inode **blkdriver, { FAR struct unionfs_inode_s *ui; - finfo("Entry\n"); + finfo("handle=%p blkdriver=%p flags=%x\n", handle, blkdriver, flags); /* Recover the union file system data from the struct inode instance */ @@ -1983,7 +2036,7 @@ static int unionfs_statfs(FAR struct inode *mountpt, FAR struct statfs *buf) uint32_t ratiob16; int ret; - finfo("Entry\n"); + finfo("mountpt=%p buf=%p\n", mountpt, buf); /* Recover the union file system data from the struct inode instance */ diff --git a/fs/userfs/Kconfig b/fs/userfs/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..4a13140b8b2667cee0fa36a5e0c10d41e131e9ea --- /dev/null +++ b/fs/userfs/Kconfig @@ -0,0 +1,14 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +config FS_USERFS + bool "User file system" + default n + depends on NET_IPv4 && NET_UDP && NETDEV_LOOPBACK + ---help--- + Enable support for user file system. See include/nuttx/fs/userfs.h + +if FS_USERFS +endif diff --git a/configs/xtrs/src/Make.defs b/fs/userfs/Make.defs similarity index 86% rename from configs/xtrs/src/Make.defs rename to fs/userfs/Make.defs index e20f03a4e56bc78c328bfd4cc6c1984081fb026d..8432d8d3d03145b99c8d05d16233731c77b32b9c 100644 --- a/configs/xtrs/src/Make.defs +++ b/fs/userfs/Make.defs @@ -1,7 +1,7 @@ ############################################################################ -# configs/xtrs/src/Make.defs +# fs/userfs/Make.defs # -# Copyright (C) 2008 Gregory Nutt. All rights reserved. +# Copyright (C) 2017 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -33,5 +33,14 @@ # ############################################################################ -HEAD_ASRC = xtrs_head.asm +ifeq ($(CONFIG_FS_USERFS),y) +# Add the userfs C files to the build + +CSRCS += fs_userfs.c + +# Add the userfs directory to the build + +DEPPATH += --dep-path userfs +VPATH += :userfs +endif diff --git a/fs/userfs/fs_userfs.c b/fs/userfs/fs_userfs.c new file mode 100644 index 0000000000000000000000000000000000000000..bf91d58c1ec26d02afb0f07f3aaf22935d566fb8 --- /dev/null +++ b/fs/userfs/fs_userfs.c @@ -0,0 +1,2008 @@ +/**************************************************************************** + * fs/userfs/fs_userfs.c + * + * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IOBUFFER_SIZE(p) (USERFS_REQ_MAXSIZE + (p)->mxwrite) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure holds the internal state of the UserFS proxy */ + +struct userfs_state_s +{ + /* Fields copied from struct userfs_config_s */ + + size_t mxwrite; /* The max size of a write data */ + + /* Internal state */ + + struct socket psock; /* Client socket instance */ + struct sockaddr_in server; /* Server address */ + sem_t exclsem; /* Exclusive access for request-response sequence */ + + /* I/O Buffer (actual size depends on USERFS_REQ_MAXSIZE and the configured + * mxwrite). + */ + + uint8_t iobuffer[1]; +}; + +#define SIZEOF_USERFS_STATE_S(n) (sizeof(struct userfs_state_s) + (n) - 1) + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int userfs_open(FAR struct file *filep, const char *relpath, + int oflags, mode_t mode); +static int userfs_close(FAR struct file *filep); +static ssize_t userfs_read(FAR struct file *filep, char *buffer, + size_t buflen); +static ssize_t userfs_read(FAR struct file *filep, FAR char *buffer, + size_t buflen); +static ssize_t userfs_write(FAR struct file *filep, FAR const char *buffer, + size_t buflen); +static off_t userfs_seek(FAR struct file *filep, off_t offset, int whence); +static int userfs_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); + +static int userfs_sync(FAR struct file *filep); +static int userfs_dup(FAR const struct file *oldp, FAR struct file *newp); +static int userfs_fstat(FAR const struct file *filep, + FAR struct stat *buf); +static int userfs_truncate(FAR struct file *filep, off_t length); + +static int userfs_opendir(FAR struct inode *mountpt, + FAR const char *relpath, FAR struct fs_dirent_s *dir); +static int userfs_closedir(FAR struct inode *mountpt, + FAR struct fs_dirent_s *dir); +static int userfs_readdir(FAR struct inode *mountpt, + FAR struct fs_dirent_s *dir); +static int userfs_rewinddir(FAR struct inode *mountpt, + FAR struct fs_dirent_s *dir); + +static int userfs_bind(FAR struct inode *blkdriver, FAR const void *data, + FAR void **handle); +static int userfs_unbind(FAR void *handle, FAR struct inode **blkdriver, + unsigned int flags); +static int userfs_statfs(FAR struct inode *mountpt, + FAR struct statfs *buf); + +static int userfs_unlink(FAR struct inode *mountpt, + FAR const char *relpath); +static int userfs_mkdir(FAR struct inode *mountpt, + FAR const char *relpath, mode_t mode); +static int userfs_rmdir(FAR struct inode *mountpt, + FAR const char *relpath); +static int userfs_rename(FAR struct inode *mountpt, + FAR const char *oldrelpath, FAR const char *newrelpath); +static int userfs_stat(FAR struct inode *mountpt, FAR const char *relpath, + FAR struct stat *buf); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* See fs_mount.c -- this structure is explicitly extern'ed there. + * We use the old-fashioned kind of initializers so that this will compile + * with any compiler. + */ + +const struct mountpt_operations userfs_operations = +{ + userfs_open, /* open */ + userfs_close, /* close */ + userfs_read, /* read */ + userfs_write, /* write */ + userfs_seek, /* seek */ + userfs_ioctl, /* ioctl */ + + userfs_sync, /* sync */ + userfs_dup, /* dup */ + userfs_fstat, /* fstat */ + userfs_truncate, /* truncate */ + + userfs_opendir, /* opendir */ + userfs_closedir, /* closedir */ + userfs_readdir, /* readdir */ + userfs_rewinddir, /* rewinddir */ + + userfs_bind, /* bind */ + userfs_unbind, /* unbind */ + userfs_statfs, /* statfs */ + + userfs_unlink, /* unlink */ + userfs_mkdir, /* mkdir */ + userfs_rmdir, /* rmdir */ + userfs_rename, /* rename */ + userfs_stat /* stat */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: userfs_open + ****************************************************************************/ + +static int userfs_open(FAR struct file *filep, FAR const char *relpath, + int oflags, mode_t mode) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_open_request_s *req; + FAR struct userfs_open_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int pathlen; + int ret; + + finfo("Open '%s'\n", relpath); + + DEBUGASSERT(filep != NULL && + filep->f_inode != NULL && + filep->f_inode->i_private != NULL); + priv = filep->f_inode->i_private; + + /* Check the path length */ + + DEBUGASSERT(relpath != NULL); + pathlen = strlen(relpath); + if (pathlen > priv->mxwrite) + { + return -E2BIG; + } + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_open_request_s *)priv->iobuffer; + req->req = USERFS_REQ_OPEN; + req->oflags = oflags; + req->mode = mode; + + strncpy(req->relpath, relpath, priv->mxwrite); + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + SIZEOF_USERFS_OPEN_REQUEST_S(pathlen + 1), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_open_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + /* Save the returned openinfo as the filep private data. */ + + resp = (FAR struct userfs_open_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_OPEN) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + filep->f_priv = resp->openinfo; + return resp->ret; +} + +/**************************************************************************** + * Name: userfs_close + ****************************************************************************/ + +static int userfs_close(FAR struct file *filep) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_close_request_s *req; + FAR struct userfs_close_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int ret; + + DEBUGASSERT(filep != NULL && + filep->f_inode != NULL && + filep->f_inode->i_private != NULL); + priv = filep->f_inode->i_private; + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_close_request_s *)priv->iobuffer; + req->req = USERFS_REQ_CLOSE; + req->openinfo = filep->f_priv; + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + sizeof(struct userfs_close_request_s), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_close_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_close_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_CLOSE) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + if (resp->ret >= 0) + { + filep->f_priv = NULL; + } + + return resp->ret; +} + +/**************************************************************************** + * Name: userfs_read + ****************************************************************************/ + +static ssize_t userfs_read(FAR struct file *filep, char *buffer, + size_t buflen) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_read_request_s *req; + FAR struct userfs_read_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int respsize; + int ret; + + finfo("Read %d bytes from offset %d\n", buflen, filep->f_pos); + + DEBUGASSERT(filep != NULL && + filep->f_inode != NULL && + filep->f_inode->i_private != NULL); + priv = filep->f_inode->i_private; + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_read_request_s *)priv->iobuffer; + req->req = USERFS_REQ_READ; + req->openinfo = filep->f_priv; + req->readlen = buflen; + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + sizeof(struct userfs_read_request_s), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd < SIZEOF_USERFS_READ_RESPONSE_S(0)) + { + ferr("ERROR: Response too small: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_read_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_READ) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + if (resp->nread > buflen) + { + ferr("ERROR: Response size too large: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + respsize = SIZEOF_USERFS_READ_RESPONSE_S(resp->nread); + if (respsize != nrecvd) + { + ferr("ERROR: Incorrect response size: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + /* Copy the received data to the user buffer */ + + memcpy(buffer, resp->rddata, resp->nread); + return resp->nread; +} + +/**************************************************************************** + * Name: userfs_write + ****************************************************************************/ + +static ssize_t userfs_write(FAR struct file *filep, FAR const char *buffer, + size_t buflen) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_write_request_s *req; + FAR struct userfs_write_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int ret; + + finfo("Write %d bytes to offset %d\n", buflen, filep->f_pos); + + DEBUGASSERT(filep != NULL && + filep->f_inode != NULL && + filep->f_inode->i_private != NULL); + priv = filep->f_inode->i_private; + + /* Perform multiple writes if the write length exceeds the configured maximum (mxwrite). + */ + + if (buflen > priv->mxwrite) + { + return -E2BIG; /* No implememented yet */ + } + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_write_request_s *)priv->iobuffer; + req->req = USERFS_REQ_WRITE; + req->openinfo = filep->f_priv; + req->writelen = buflen; + memcpy(req->wrdata, buffer, buflen); + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + SIZEOF_USERFS_WRITE_REQUEST_S(buflen), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_write_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_write_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_WRITE) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + return resp->nwritten; +} + +/**************************************************************************** + * Name: userfs_seek + ****************************************************************************/ + +static off_t userfs_seek(FAR struct file *filep, off_t offset, int whence) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_seek_request_s *req; + FAR struct userfs_seek_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int ret; + + finfo("Offset %lu bytes to whence=%d\n", (unsigned long)offset, whence); + + DEBUGASSERT(filep != NULL && + filep->f_inode != NULL && + filep->f_inode->i_private != NULL); + priv = filep->f_inode->i_private; + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_seek_request_s *)priv->iobuffer; + req->req = USERFS_REQ_SEEK; + req->openinfo = filep->f_priv; + req->offset = offset; + req->whence = whence; + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + sizeof(struct userfs_seek_request_s), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_seek_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_seek_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_SEEK) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + return resp->ret; +} + +/**************************************************************************** + * Name: userfs_ioctl + ****************************************************************************/ + +static int userfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_ioctl_request_s *req; + FAR struct userfs_ioctl_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int ret; + + finfo("cmd: %d arg: %08lx\n", cmd, arg); + + DEBUGASSERT(filep != NULL && + filep->f_inode != NULL && + filep->f_inode->i_private != NULL); + priv = filep->f_inode->i_private; + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_ioctl_request_s *)priv->iobuffer; + req->req = USERFS_REQ_IOCTL; + req->openinfo = filep->f_priv; + req->cmd = cmd; + req->arg = arg; + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + sizeof(struct userfs_ioctl_request_s), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_ioctl_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_ioctl_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_IOCTL) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + return resp->ret; +} + +/**************************************************************************** + * Name: userfs_sync + ****************************************************************************/ + +static int userfs_sync(FAR struct file *filep) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_sync_request_s *req; + FAR struct userfs_sync_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int ret; + + DEBUGASSERT(filep != NULL && + filep->f_inode != NULL && + filep->f_inode->i_private != NULL); + priv = filep->f_inode->i_private; + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_sync_request_s *)priv->iobuffer; + req->req = USERFS_REQ_SYNC; + req->openinfo = filep->f_priv; + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + sizeof(struct userfs_sync_request_s), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_sync_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_sync_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_SYNC) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + return resp->ret; +} + +/**************************************************************************** + * Name: userfs_dup + * + * Description: + * Duplicate open file data in the new file structure. + * + ****************************************************************************/ + +static int userfs_dup(FAR const struct file *oldp, FAR struct file *newp) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_dup_request_s *req; + FAR struct userfs_dup_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int ret; + + finfo("Dup %p->%p\n", oldp, newp); + + DEBUGASSERT(oldp != NULL && + oldp->f_inode != NULL && + oldp->f_inode->i_private != NULL); + priv = oldp->f_inode->i_private; + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_dup_request_s *)priv->iobuffer; + req->req = USERFS_REQ_DUP; + req->openinfo = oldp->f_priv; + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + sizeof(struct userfs_dup_request_s), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_dup_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_dup_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_DUP) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + newp->f_priv = resp->openinfo; + return resp->ret; +} + +/**************************************************************************** + * Name: userfs_fstat + * + * Description: + * Obtain information about an open file associated with the file + * descriptor 'fd', and will write it to the area pointed to by 'buf'. + * + ****************************************************************************/ + +static int userfs_fstat(FAR const struct file *filep, FAR struct stat *buf) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_fstat_request_s *req; + FAR struct userfs_fstat_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int ret; + + DEBUGASSERT(filep != NULL && + filep->f_inode != NULL && + filep->f_inode->i_private != NULL); + priv = filep->f_inode->i_private; + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_fstat_request_s *)priv->iobuffer; + req->req = USERFS_REQ_FSTAT; + req->openinfo = filep->f_priv; + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + sizeof(struct userfs_fstat_request_s), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_fstat_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_fstat_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_FSTAT) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + /* Return the status of the directory entry */ + + DEBUGASSERT(buf != NULL); + memcpy(buf, &resp->buf, sizeof(struct stat)); + return resp->ret; +} + +/**************************************************************************** + * Name: userfs_truncate + * + * Description: + * Set the size of the regular file referred to by 'filep' to 'length' + * + ****************************************************************************/ + +static int userfs_truncate(FAR struct file *filep, off_t length) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_truncate_request_s *req; + FAR struct userfs_truncate_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int ret; + + DEBUGASSERT(filep != NULL && + filep->f_inode != NULL && + filep->f_inode->i_private != NULL); + priv = filep->f_inode->i_private; + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_truncate_request_s *)priv->iobuffer; + req->req = USERFS_REQ_FSTAT; + req->openinfo = filep->f_priv; + req->length = length; + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + sizeof(struct userfs_truncate_request_s), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_truncate_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_truncate_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_FSTAT) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + /* Return the result of truncate operation */ + + DEBUGASSERT(buf != NULL); + return resp->ret; +} + +/**************************************************************************** + * Name: userfs_opendir + * + * Description: + * Open a directory + * + ****************************************************************************/ + +static int userfs_opendir(FAR struct inode *mountpt, FAR const char *relpath, + FAR struct fs_dirent_s *dir) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_opendir_request_s *req; + FAR struct userfs_opendir_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int pathlen; + int ret; + + finfo("relpath: \"%s\"\n", relpath ? relpath : "NULL"); + + DEBUGASSERT(mountpt != NULL && + mountpt->i_private != NULL); + priv = mountpt->i_private; + + /* Check the path length */ + + DEBUGASSERT(relpath != NULL); + pathlen = strlen(relpath); + if (pathlen > priv->mxwrite) + { + return -E2BIG; + } + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_opendir_request_s *)priv->iobuffer; + req->req = USERFS_REQ_OPENDIR; + + strncpy(req->relpath, relpath, priv->mxwrite); + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + SIZEOF_USERFS_OPENDIR_REQUEST_S(pathlen + 1), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_opendir_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_opendir_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_OPENDIR) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + /* Save the opaque dir reference in struct fs_dirent_s */ + + DEBUGASSERT(dir != NULL); + dir->u.userfs.fs_dir = resp->dir; + return resp->ret; +} + +/**************************************************************************** + * Name: userfs_closedir + * + * Description: + * Close a directory + * + ****************************************************************************/ + +static int userfs_closedir(FAR struct inode *mountpt, + FAR struct fs_dirent_s *dir) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_closedir_request_s *req; + FAR struct userfs_closedir_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int ret; + + DEBUGASSERT(mountpt != NULL && + mountpt->i_private != NULL); + priv = mountpt->i_private; + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_closedir_request_s *)priv->iobuffer; + req->req = USERFS_REQ_CLOSEDIR; + req->dir = dir->u.userfs.fs_dir; + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + sizeof(struct userfs_closedir_request_s), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_closedir_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_closedir_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_CLOSEDIR) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + return resp->ret; +} + +/**************************************************************************** + * Name: userfs_readdir + * + * Description: Read the next directory entry + * + ****************************************************************************/ + +static int userfs_readdir(FAR struct inode *mountpt, + FAR struct fs_dirent_s *dir) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_readdir_request_s *req; + FAR struct userfs_readdir_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int ret; + + DEBUGASSERT(mountpt != NULL && + mountpt->i_private != NULL); + priv = mountpt->i_private; + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_readdir_request_s *)priv->iobuffer; + req->req = USERFS_REQ_READDIR; + req->dir = dir->u.userfs.fs_dir; + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + sizeof(struct userfs_readdir_request_s), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_readdir_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_readdir_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_READDIR) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + /* Return the dirent */ + + DEBUGASSERT(dir != NULL); + memcpy(&dir->fd_dir, &resp->entry, sizeof(struct dirent)); + return resp->ret; +} + +/**************************************************************************** + * Name: userfs_rewindir + * + * Description: Reset directory read to the first entry + * + ****************************************************************************/ + +static int userfs_rewinddir(FAR struct inode *mountpt, + FAR struct fs_dirent_s *dir) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_rewinddir_request_s *req; + FAR struct userfs_rewinddir_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int ret; + + DEBUGASSERT(mountpt != NULL && + mountpt->i_private != NULL); + priv = mountpt->i_private; + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_rewinddir_request_s *)priv->iobuffer; + req->req = USERFS_REQ_REWINDDIR; + req->dir = dir->u.userfs.fs_dir; + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + sizeof(struct userfs_rewinddir_request_s), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_rewinddir_response_s)) + { + ferr("ERROR: Response size incorrrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_rewinddir_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_REWINDDIR) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + return resp->ret; +} + +/**************************************************************************** + * Name: userfs_bind + * + * Description: This implements a portion of the mount operation. This + * function allocates and initializes the mountpoint private data and + * binds the blockdriver inode to the filesystem private data. The final + * binding of the private data (containing the blockdriver) to the + * mountpoint is performed by mount(). + * + ****************************************************************************/ + +static int userfs_bind(FAR struct inode *blkdriver, FAR const void *data, + FAR void **handle) +{ + FAR struct userfs_state_s *priv; + FAR const struct userfs_config_s *config; + struct sockaddr_in client; + unsigned int iolen; + int ret; + + DEBUGASSERT(data != NULL && handle != NULL); + config = (FAR const struct userfs_config_s *)data; + + /* Allocate an instance of the UserFS state structure */ + + iolen = USERFS_REQ_MAXSIZE + config->mxwrite; + priv = (FAR struct userfs_state_s *)kmm_malloc(SIZEOF_USERFS_STATE_S(iolen)); + if (priv == NULL) + { + ferr("ERROR: Failed to allocate state structure\n"); + return -ENOMEM; + } + + /* Initialize the semaphore that assures mutually exclusive access through + * the entire request-response sequence. + */ + + sem_init(&priv->exclsem, 0, 1); + + /* Copy the configuration data into the allocated structure. Why? First + * we can't be certain of the life time of the memory underlying the config + * reference. Also, in the KERNEL build, the config data will like in + * process-specific memory and cannot be shared across processes. + */ + + priv->mxwrite = config->mxwrite; + + /* Preset the server address */ + + priv->server.sin_family = AF_INET; + priv->server.sin_port = htons(config->portno); + priv->server.sin_addr.s_addr = HTONL(INADDR_LOOPBACK); + + /* Create a LocalHost UDP client socket */ + + ret = psock_socket(PF_INET, SOCK_DGRAM, 0, &priv->psock); + if (ret < 0) + { + printf("client: ERROR socket failure %d\n", ret); + goto errout_with_alloc; + } + + priv->psock.s_crefs = 1; + + /* Bind the socket to the client address */ + + client.sin_family = AF_INET; + client.sin_port = 0; + client.sin_addr.s_addr = HTONL(INADDR_LOOPBACK); + + ret = psock_bind(&priv->psock, (struct sockaddr*)&client, + sizeof(struct sockaddr_in)); + if (ret < 0) + { + ferr("ERROR: bind() failed: %d\n", ret); + goto errout_with_psock; + } + + priv->psock.s_crefs = 1; + + /* Mounted! */ + + *handle = (FAR void *)priv; + return OK; + +errout_with_psock: + psock_close(&priv->psock); + +errout_with_alloc: + kmm_free(priv); + return ret; +} + +/**************************************************************************** + * Name: userfs_unbind + * + * Description: This implements the filesystem portion of the umount + * operation. + * + ****************************************************************************/ + +static int userfs_unbind(FAR void *handle, FAR struct inode **blkdriver, + unsigned int flags) +{ + FAR struct userfs_state_s *priv = (FAR struct userfs_state_s *)handle; + FAR struct userfs_destroy_request_s *req; + FAR struct userfs_destroy_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int ret; + + DEBUGASSERT(priv != NULL); + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_destroy_request_s *)priv->iobuffer; + req->req = USERFS_REQ_DESTROY; + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + sizeof(struct userfs_destroy_request_s), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_destroy_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_destroy_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_DESTROY) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + /* If the destruction failed, then refuse to unmount at this time */ + + if (resp->ret < 0) + { + return resp->ret; + } + + /* Free resources and return success */ + + psock_close(&priv->psock); + kmm_free(priv); + return OK; +} + +/**************************************************************************** + * Name: userfs_statfs + * + * Description: + * Return filesystem statistics + * + ****************************************************************************/ + +static int userfs_statfs(FAR struct inode *mountpt, FAR struct statfs *buf) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_statfs_request_s *req; + FAR struct userfs_statfs_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int ret; + + DEBUGASSERT(mountpt != NULL && + mountpt->i_private != NULL); + priv = mountpt->i_private; + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_statfs_request_s *)priv->iobuffer; + req->req = USERFS_REQ_STATFS; + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + sizeof(struct userfs_statfs_request_s), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_statfs_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_statfs_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_STATFS) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + /* Return the status of the file system */ + + DEBUGASSERT(buf != NULL); + memcpy(buf, &resp->buf, sizeof(struct statfs)); + return resp->ret; +} + +/**************************************************************************** + * Name: userfs_unlink + * + * Description: + * Remove a directory entry + * + ****************************************************************************/ + +static int userfs_unlink(FAR struct inode *mountpt, + FAR const char *relpath) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_unlink_request_s *req; + FAR struct userfs_unlink_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int pathlen; + int ret; + + DEBUGASSERT(mountpt != NULL && + mountpt->i_private != NULL); + priv = mountpt->i_private; + + /* Check the path length */ + + DEBUGASSERT(relpath != NULL); + pathlen = strlen(relpath); + if (pathlen > priv->mxwrite) + { + return -E2BIG; + } + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_unlink_request_s *)priv->iobuffer; + req->req = USERFS_REQ_UNLINK; + + strncpy(req->relpath, relpath, priv->mxwrite); + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + SIZEOF_USERFS_UNLINK_REQUEST_S(pathlen + 1), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_unlink_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_unlink_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_UNLINK) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + return resp->ret; +} + +/**************************************************************************** + * Name: userfs_mkdir + * + * Description: + * Create a new directory + * + ****************************************************************************/ + +static int userfs_mkdir(FAR struct inode *mountpt, + FAR const char *relpath, mode_t mode) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_mkdir_request_s *req; + FAR struct userfs_mkdir_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int pathlen; + int ret; + + DEBUGASSERT(mountpt != NULL && + mountpt->i_private != NULL); + priv = mountpt->i_private; + + /* Check the path length */ + + DEBUGASSERT(relpath != NULL); + pathlen = strlen(relpath); + if (pathlen > priv->mxwrite) + { + return -E2BIG; + } + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_mkdir_request_s *)priv->iobuffer; + req->req = USERFS_REQ_MKDIR; + req->mode = mode; + + strncpy(req->relpath, relpath, priv->mxwrite); + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + SIZEOF_USERFS_MKDIR_REQUEST_S(pathlen + 1), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_mkdir_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_mkdir_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_MKDIR) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + return resp->ret; +} + +/**************************************************************************** + * Name: userfs_rmdir + * + * Description: + * Remove a directory + * + ****************************************************************************/ + +static int userfs_rmdir(FAR struct inode *mountpt, + FAR const char *relpath) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_rmdir_request_s *req; + FAR struct userfs_rmdir_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int pathlen; + int ret; + + DEBUGASSERT(mountpt != NULL && + mountpt->i_private != NULL); + priv = mountpt->i_private; + + /* Check the path length */ + + DEBUGASSERT(relpath != NULL); + pathlen = strlen(relpath); + if (pathlen > priv->mxwrite) + { + return -E2BIG; + } + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_rmdir_request_s *)priv->iobuffer; + req->req = USERFS_REQ_RMDIR; + + strncpy(req->relpath, relpath, priv->mxwrite); + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + SIZEOF_USERFS_RMDIR_REQUEST_S(pathlen + 1), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_rmdir_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_rmdir_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_RMDIR) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + return resp->ret; +} + +/**************************************************************************** + * Name: userfs_rename + * + * Description: + * Rename a directory entry + * + ****************************************************************************/ + +static int userfs_rename(FAR struct inode *mountpt, + FAR const char *oldrelpath, + FAR const char *newrelpath) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_rename_request_s *req; + FAR struct userfs_rename_response_s *resp; + int oldpathlen; + int newpathlen; + ssize_t nsent; + ssize_t nrecvd; + int ret; + + DEBUGASSERT(mountpt != NULL && + mountpt->i_private != NULL); + priv = mountpt->i_private; + + /* Check the path lengths */ + + DEBUGASSERT(oldrelpath != NULL && newrelpath != NULL); + oldpathlen = strlen(oldrelpath) + 1; + newpathlen = strlen(newrelpath) + 1; + + if ((oldpathlen + newpathlen) > priv->mxwrite) + { + return -E2BIG; + } + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_rename_request_s *)priv->iobuffer; + req->req = USERFS_REQ_RENAME; + req->newoffset = oldpathlen; + + strncpy(req->oldrelpath, oldrelpath, oldpathlen); + strncpy(&req->oldrelpath[oldpathlen], newrelpath, newpathlen); + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + SIZEOF_USERFS_RENAME_REQUEST_S(oldpathlen, newpathlen), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_rename_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_rename_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_RENAME) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + return resp->ret; +} + +/**************************************************************************** + * Name: userfs_stat + * + * Description: + * Return information about a file or directory + * + ****************************************************************************/ + +static int userfs_stat(FAR struct inode *mountpt, FAR const char *relpath, + FAR struct stat *buf) +{ + FAR struct userfs_state_s *priv; + FAR struct userfs_stat_request_s *req; + FAR struct userfs_stat_response_s *resp; + ssize_t nsent; + ssize_t nrecvd; + int pathlen; + int ret; + + DEBUGASSERT(mountpt != NULL && + mountpt->i_private != NULL); + priv = mountpt->i_private; + + /* Check the path length */ + + DEBUGASSERT(relpath != NULL); + pathlen = strlen(relpath); + if (pathlen > priv->mxwrite) + { + return -E2BIG; + } + + /* Get exclusive access */ + + ret = sem_wait(&priv->exclsem); + if (ret < 0) + { + return ret; + } + + /* Construct and send the request to the server */ + + req = (FAR struct userfs_stat_request_s *)priv->iobuffer; + req->req = USERFS_REQ_STAT; + + strncpy(req->relpath, relpath, priv->mxwrite); + + nsent = psock_sendto(&priv->psock, priv->iobuffer, + SIZEOF_USERFS_STAT_REQUEST_S(pathlen + 1), 0, + (FAR struct sockaddr *)&priv->server, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ferr("ERROR: psock_sendto failed: %d\n", (int)nsent); + sem_post(&priv->exclsem); + return (int)nsent; + } + + /* Then get the response from the server */ + + nrecvd = psock_recvfrom(&priv->psock, priv->iobuffer, IOBUFFER_SIZE(priv), + 0, NULL, NULL); + sem_post(&priv->exclsem); + + if (nrecvd < 0) + { + ferr("ERROR: psock_recvfrom failed: %d\n", (int)nrecvd); + return (int)nrecvd; + } + + if (nrecvd != sizeof(struct userfs_stat_response_s)) + { + ferr("ERROR: Response size incorrect: %u\n", (unsigned int)nrecvd); + return -EIO; + } + + resp = (FAR struct userfs_stat_response_s *)priv->iobuffer; + if (resp->resp != USERFS_RESP_STAT) + { + ferr("ERROR: Incorrect response: %u\n", resp->resp); + return -EIO; + } + + /* Return the directory entry status */ + + DEBUGASSERT(buf != NULL); + memcpy(buf, &resp->buf, sizeof(struct stat)); + return resp->ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/fs/userfs/userfs.h b/fs/userfs/userfs.h new file mode 100644 index 0000000000000000000000000000000000000000..5007eb385c82060f833a7ce043cf284305a83d8f --- /dev/null +++ b/fs/userfs/userfs.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * fs/userfs/userfs.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __FS_USERFS_USERFS_H +#define __FS_USERFS_USERFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_FS_USERFS + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* CONFIG_FS_USERFS */ +#endif /* __FS_USERFS_USERFS_H */ \ No newline at end of file diff --git a/fs/vfs/Make.defs b/fs/vfs/Make.defs index d80dca771d2f49047376c4cdbca438b5d6e3c162..a306b9297b820d52a1d1610613e8c9edc3199e45 100644 --- a/fs/vfs/Make.defs +++ b/fs/vfs/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # fs/vfs/Make.defs # -# Copyright (C) 2014-2015, 2017 Gregory Nutt. All rights reserved. +# Copyright (C) 2014-2015, 2017-2018 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -79,7 +79,7 @@ CSRCS += fs_rmdir.c fs_statfs.c fs_stat.c fs_select.c fs_unlink.c fs_write.c # Certain interfaces are not available if there is no mountpoint support ifneq ($(CONFIG_DISABLE_MOUNTPOINT),y) -CSRCS += fs_fsync.c +CSRCS += fs_fsync.c fs_truncate.c endif # Support for positional file access diff --git a/fs/vfs/fs_truncate.c b/fs/vfs/fs_truncate.c new file mode 100644 index 0000000000000000000000000000000000000000..3d383916b7d7e27cb43711516f66124424f61615 --- /dev/null +++ b/fs/vfs/fs_truncate.c @@ -0,0 +1,200 @@ +/**************************************************************************** + * fs/vfs/fs_truncate.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "inode/inode.h" + +#ifndef CONFIG_DISABLE_MOUNTPOINT + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: file_truncate + * + * Description: + * Equivalent to the standard ftruncate() function except that is accepts + * a struct file instance instead of a file descriptor and it does not set + * the errno variable. + * + ****************************************************************************/ + +int file_truncate(FAR struct file *filep, off_t length) +{ + struct inode *inode; + + /* Was this file opened for write access? */ + + if ((filep->f_oflags & O_WROK) == 0) + { + fwarn("WARNING: Cannot truncate a file opened read-only\n"); + return -EBADF; + } + + /* Is this inode a registered mountpoint? Does it support the + * truncate operations may be relevant to device drivers but only + * the mountpoint operations vtable contains a truncate method. + */ + + inode = filep->f_inode; + if (inode == NULL || !INODE_IS_MOUNTPT(inode) || inode->u.i_mops == NULL) + { + fwarn("WARNING: Not a (regular) file on a mounted file system.\n"); + return -EINVAL; + } + + /* A NULL write() method is an indicator of a read-only file system (but + * possible not the only indicator -- sufficient, but not necessary") + */ + + if (inode->u.i_mops->write == NULL) + { + fwarn("WARNING: File system is read-only\n"); + return -EROFS; + } + + /* Does the file system support the truncate method? It should if it is + * a write-able file system. + */ + + if (inode->u.i_mops->truncate == NULL) + { + fwarn("WARNING: File system does not support the truncate() method\n"); + return -ENOSYS; + } + + /* Yes, then tell the file system to truncate this file */ + + return inode->u.i_mops->truncate(filep, length); +} + +/**************************************************************************** + * Name: ftruncate + * + * Description: + * The ftruncate() function causes the regular file referenced by fd to + * have a size of length bytes. + * + * If the file previously was larger than length, the extra data is + * discarded. If it was previously shorter than length, it is unspecified + * whether the file is changed or its size increased. If the file is + * extended, the extended area appears as if it were zero-filled. If fd + * references a shared memory object, ftruncate() sets the size of the + * shared memory object to length. If the file is not a regular file or + * a shared memory object, the result is unspecified. + + * With ftruncate(), the file must be open for writing; for truncate(), + * the process must have write permission for the file. + * + * ftruncate() does not modify the file offset for any open file + * descriptions associated with the file. + * + * Input Parameters: + * fd - A reference to an open, regular file or shared memory object + * to be truncated. + * length - The new length of the file or shared memory object. + * + * Returned Value: + * Upon successful completion, ftruncate() return 0s. Otherwise a -1 is + * returned, and errno is set to indicate the error. + * + * EINTR + * - A signal was caught during execution. + * EINVAL + * - The length argument was less than 0. + * EFBIG or EINVAL + * - The length argument was greater than the maximum file size. + * EIO + * - An I/O error occurred while reading from or writing to a file + * system. + * EBADF or EINVAL + * - the fd argument is not a file descriptor open for writing. + * EFBIG + * - The file is a regular file and length is greater than the offset + * maximum established in the open file description associated with + * fd. + * EINVAL + * - The fd argument references a file that was opened without write + * permission. + * EROFS + * - The named file resides on a read-only file system. + * + ****************************************************************************/ + +int ftruncate(int fd, off_t length) +{ + FAR struct file *filep; + int ret; + + /* Get the file structure corresponding to the file descriptor. */ + + ret = fs_getfilep(fd, &filep); + if (ret < 0) + { + ferr("ERROR: Could no get file structure: %d\n", ret); + goto errout; + } + + DEBUGASSERT(filep != NULL); + + /* Perform the truncate operation */ + + ret = file_truncate(filep, length); + if (ret >= 0) + { + return 0; + } + + fwarn("WARNING: file_truncate() failed: %d\n", ret); + +errout: + set_errno(-ret); + return ERROR; +} + +#endif /* !CONFIG_DISABLE_MOUNTPOINT */ diff --git a/graphics/Kconfig b/graphics/Kconfig index 561c39a55832e744c303cf8ce4a7b997d53d69c1..b988ca0dd56059a214b2567dad452b065bba031f 100644 --- a/graphics/Kconfig +++ b/graphics/Kconfig @@ -6,6 +6,8 @@ config NX bool "NX Graphics" default n + select NXGLIB + select NXFONTS ---help--- Enables overall support for graphics library and NX @@ -85,6 +87,7 @@ menu "Supported Pixel Depths" config NX_DISABLE_1BPP bool "Disable 1 BPP" default y + select NXFONTS_DISABLE_1BPP if NXFONTS ---help--- NX supports a variety of pixel depths. You can save some memory by disabling support for unused color depths. The selection disables support for 1BPP @@ -93,6 +96,7 @@ config NX_DISABLE_1BPP config NX_DISABLE_2BPP bool "Disable 2 BPP" default y + select NXFONTS_DISABLE_2BPP ---help--- NX supports a variety of pixel depths. You can save some memory by disabling support for unused color depths. The selection disables support for 2BPP @@ -100,6 +104,7 @@ config NX_DISABLE_2BPP config NX_DISABLE_4BPP bool "Disable 4 BPP" + select NXFONTS_DISABLE_4BPP if NXFONTS default y ---help--- NX supports a variety of pixel depths. You can save some memory by disabling @@ -109,6 +114,7 @@ config NX_DISABLE_4BPP config NX_DISABLE_8BPP bool "Disable 8 BPP" default y + select NXFONTS_DISABLE_8BPP if NXFONTS ---help--- NX supports a variety of pixel depths. You can save some memory by disabling support for unused color depths. The selection disables support for 8BPP @@ -117,6 +123,7 @@ config NX_DISABLE_8BPP config NX_DISABLE_16BPP bool "Disable 16 BPP" default y + select NXFONTS_DISABLE_16BPP if NXFONTS ---help--- NX supports a variety of pixel depths. You can save some memory by disabling support for unused color depths. The selection disables support for 16BPP @@ -125,6 +132,7 @@ config NX_DISABLE_16BPP config NX_DISABLE_24BPP bool "Disable 24 BPP" default y + select NXFONTS_DISABLE_24BPP if NXFONTS ---help--- NX supports a variety of pixel depths. You can save some memory by disabling support for unused color depths. The selection disables support for 24BPP @@ -133,6 +141,7 @@ config NX_DISABLE_24BPP config NX_DISABLE_32BPP bool "Disable 32 BPP" default y + select NXFONTS_DISABLE_32BPP if NXFONTS ---help--- NX supports a variety of pixel depths. You can save some memory by disabling support for unused color depths. The selection disables support for 32BPP @@ -143,7 +152,8 @@ endmenu config NX_PACKEDMSFIRST bool "Packed MS First" default y - depends on NX_DISABLE_1BPP || NX_DISABLE_2BPP || NX_DISABLE_4BPP + select NXFONTS_PACKEDMSFIRST if NXFONTS + select LCD_PACKEDMSFIRST if LCD ---help--- If a pixel depth of less than 8-bits is used, then NX needs to know if the pixels pack from the MS to LS or from LS to MS @@ -252,318 +262,6 @@ config NXTK_AUTORAISE visible portion of the window. Default: A mouse button must be clicked over a visible portion of the window. -menu "Font Selections" - -config NXFONTS_CHARBITS - int "Bits in Character Set" - default 7 - range 7 8 - ---help--- - The number of bits in the character set. Current options are only 7 and 8. - The default is 7. - -config NXFONT_MONO5X8 - bool "Mono 5x8" - default n - ---help--- - Tiny mono-spaced 5x8 font (font ID FONTID_MONO5X8 = 18) - -config NXFONT_SANS17X22 - bool "Sans 17x22" - default n - ---help--- - This option enables support for a tiny, 17x22 san serif font - (font ID FONTID_SANS17X22 == 14). - -config NXFONT_SANS20X26 - bool "Sans 20x26" - default n - ---help--- - This option enables support for a tiny, 20x26 san serif font - (font ID FONTID_SANS20X26 == 15). - -config NXFONT_SANS23X27 - bool "Sans 23x27" - default n - ---help--- - This option enables support for a tiny, 23x27 san serif font - (font ID FONTID_SANS23X27 == 1). - -config NXFONT_SANS22X29 - bool "Sans 22x29" - default n - ---help--- - This option enables support for a small, 22x29 san serif font - (font ID FONTID_SANS22X29 == 2). - -config NXFONT_SANS28X37 - bool "Sans 28x37" - default n - ---help--- - This option enables support for a medium, 28x37 san serif font - (font ID FONTID_SANS28X37 == 3). - -config NXFONT_SANS39X48 - bool "Sans 39x48" - default n - ---help--- - This option enables support for a large, 39x48 san serif font - (font ID FONTID_SANS39X48 == 4). - -config NXFONT_SANS17X23B - bool "Sans 17x23 Bold" - default n - ---help--- - This option enables support for a tiny, 17x23 san serif bold font - (font ID FONTID_SANS17X23B == 16). - -config NXFONT_SANS20X27B - bool "Sans 20x27 Bold" - default n - ---help--- - This option enables support for a tiny, 20x27 san serif bold font - (font ID FONTID_SANS20X27B == 17). - -config NXFONT_SANS22X29B - bool "Sans 22x29 Bold" - default n - ---help--- - This option enables support for a small, 22x29 san serif bold font - (font ID FONTID_SANS22X29B == 5). - -config NXFONT_SANS28X37B - bool "Sans 28x37 Bold" - default n - ---help--- - This option enables support for a medium, 28x37 san serif bold font - (font ID FONTID_SANS28X37B == 6). - -config NXFONT_SANS40X49B - bool "Sans 40x49 Bold" - default n - ---help--- - This option enables support for a large, 40x49 san serif bold font - (font ID FONTID_SANS40X49B == 7). - -config NXFONT_SERIF22X29 - bool "Serif 22x29" - default n - ---help--- - This option enables support for a small, 22x29 font (with serifs) - (font ID FONTID_SERIF22X29 == 8). - -config NXFONT_SERIF29X37 - bool "Serif 29x37" - default n - ---help--- - This option enables support for a medium, 29x37 font (with serifs) - (font ID FONTID_SERIF29X37 == 9). - -config NXFONT_SERIF38X48 - bool "Serif 38x48" - default n - ---help--- - This option enables support for a large, 38x48 font (with serifs) - (font ID FONTID_SERIF38X48 == 10). - -config NXFONT_SERIF22X28B - bool "Serif 22x28 Bold" - default n - ---help--- - This option enables support for a small, 27x38 bold font (with serifs) - (font ID FONTID_SERIF22X28B == 11). - -config NXFONT_SERIF27X38B - bool "Serif 27x38 Bold" - default n - ---help--- - This option enables support for a medium, 27x38 bold font (with serifs) - (font ID FONTID_SERIF27X38B == 12). - -config NXFONT_SERIF38X49B - bool "Serif 38x49 Bold" - default n - ---help--- - This option enables support for a large, 38x49 bold font (with serifs) - (font ID FONTID_SERIF38X49B == 13). - -config NXFONT_PIXEL_UNICODE - bool "Pixel UniCode" - default n - ---help--- - This option enables support for a small LCD, The "Pixel UniCode" - (font ID FONTID_PIXEL_UNICODE == 19). - -config NXFONT_PIXEL_LCD_MACHINE - bool "Pixel lcd machine" - default n - ---help--- - This option enables support for a small LCD, The "Pixel lcd machine" - (font ID FONTID_PIXEL_LCD_MACHINE == 20). - -config NXFONT_X11_MISC_FIXED_4X6 - bool "x11 misc fixed 4x6" - default n - ---help--- - This option enables support for a "x11-misc-fixed-4x6". - (font ID FONTID_X11_MISC_FIXED_4X6 == 21). - -config NXFONT_X11_MISC_FIXED_5X7 - bool "x11 misc fixed 5x7" - default n - ---help--- - This option enables support for a "x11-misc-fixed-5x7". - (font ID FONTID_X11_MISC_FIXED_5X7 == 22). - -config NXFONT_X11_MISC_FIXED_5X8 - bool "x11 misc fixed 5x8" - default n - ---help--- - This option enables support for a "x11-misc-fixed-5x8". - (font ID FONTID_X11_MISC_FIXED_5X8 == 23). - -config NXFONT_X11_MISC_FIXED_6X9 - bool "x11 misc fixed 6x9" - default n - ---help--- - This option enables support for a "x11-misc-fixed-6x9". - (font ID FONTID_X11_MISC_FIXED_6X9 == 24). - -config NXFONT_X11_MISC_FIXED_6X10 - bool "x11 misc fixed 6x10" - default n - ---help--- - This option enables support for a "x11-misc-fixed-6x10". - (font ID FONTID_X11_MISC_FIXED_6X10 == 25). - -config NXFONT_X11_MISC_FIXED_6X12 - bool "x11 misc fixed 6x12" - default n - ---help--- - This option enables support for a "x11-misc-fixed-6x12". - (font ID FONTID_X11_MISC_FIXED_6X12 == 26). - -config NXFONT_X11_MISC_FIXED_6X13 - bool "x11 misc fixed 6x13" - default n - ---help--- - This option enables support for a "x11-misc-fixed-6x13". - (font ID FONTID_X11_MISC_FIXED_6X13 == 27). - -config NXFONT_X11_MISC_FIXED_6X13B - bool "x11 misc fixed 6x13B" - default n - ---help--- - This option enables support for a "x11-misc-fixed-6x13B". - (font ID FONTID_X11_MISC_FIXED_6X13B == 28). - -config NXFONT_X11_MISC_FIXED_6X13O - bool "x11 misc fixed 6x13O" - default n - ---help--- - This option enables support for a "x11-misc-fixed-6x13O". - (font ID FONTID_X11_MISC_FIXED_6X13O == 29). - -config NXFONT_X11_MISC_FIXED_7X13 - bool "x11 misc fixed 7x13" - default n - ---help--- - This option enables support for a "x11-misc-fixed-7x13". - (font ID FONTID_X11_MISC_FIXED_7X13 == 30). - -config NXFONT_X11_MISC_FIXED_7X13B - bool "x11 misc fixed 7x13B" - default n - ---help--- - This option enables support for a "x11-misc-fixed-7x13B". - (font ID FONTID_X11_MISC_FIXED_7X13B == 31). - -config NXFONT_X11_MISC_FIXED_7X13O - bool "x11 misc fixed 7x13O" - default n - ---help--- - This option enables support for a "x11-misc-fixed-7x13O". - (font ID FONTID_X11_MISC_FIXED_7X13O == 32). - -config NXFONT_X11_MISC_FIXED_7X14 - bool "x11 misc fixed 7x14" - default n - ---help--- - This option enables support for a "x11-misc-fixed-7x14". - (font ID FONTID_X11_MISC_FIXED_7X14 == 33). - -config NXFONT_X11_MISC_FIXED_7X14B - bool "x11 misc fixed 7x14B" - default n - ---help--- - This option enables support for a "x11-misc-fixed-7x14B". - (font ID FONTID_X11_MISC_FIXED_7X14B == 34). - -config NXFONT_X11_MISC_FIXED_8X13 - bool "x11 misc fixed 8x13" - default n - ---help--- - This option enables support for a "x11-misc-fixed-8x13". - (font ID FONTID_X11_MISC_FIXED_8X13 == 35). - -config NXFONT_X11_MISC_FIXED_8X13B - bool "x11 misc fixed 8x13B" - default n - ---help--- - This option enables support for a "x11-misc-fixed-8x13B". - (font ID FONTID_X11_MISC_FIXED_8X13B == 36). - -config NXFONT_X11_MISC_FIXED_8X13O - bool "x11 misc fixed 8x13O" - default n - ---help--- - This option enables support for a "x11-misc-fixed-8x13O". - (font ID FONTID_X11_MISC_FIXED_8X13O == 37). - -config NXFONT_X11_MISC_FIXED_9X15 - bool "x11 misc fixed 9x15" - default n - ---help--- - This option enables support for a "x11-misc-fixed-9x15". - (font ID FONTID_X11_MISC_FIXED_9X15 == 38). - -config NXFONT_X11_MISC_FIXED_9X15B - bool "x11 misc fixed 9x15B" - default n - ---help--- - This option enables support for a "x11-misc-fixed-9x15B". - (font ID FONTID_X11_MISC_FIXED_9X15B == 39). - -config NXFONT_X11_MISC_FIXED_9X18 - bool "x11 misc fixed 9x18" - default n - ---help--- - This option enables support for a "x11-misc-fixed-9x18". - (font ID FONTID_X11_MISC_FIXED_9X18 == 40). - -config NXFONT_X11_MISC_FIXED_9X18B - bool "x11 misc fixed 9x18B" - default n - ---help--- - This option enables support for a "x11-misc-fixed-9x18B". - (font ID FONTID_X11_MISC_FIXED_9X18B == 41). - -config NXFONT_X11_MISC_FIXED_10X20 - bool "x11 misc fixed 10x20" - default n - ---help--- - This option enables support for a "x11-misc-fixed-10x20". - (font ID FONTID_X11_MISC_FIXED_10X20 == 42). - -config NXFONT_TOM_THUMB_4X6 - bool "Tom Thumb Monospace 4x6" - default n - ---help--- - This option enables support for a small, 3x5 font (with blank space - padding to 4x6) (font ID FONTID_TOM_THUMB_4X6 == 43). - -endmenu - menuconfig NXTERM bool "NxTerm" default n @@ -691,8 +389,9 @@ config NX_MXCLIENTMSGS controls how many messages are pre-allocated). config NXSTART_EXTERNINIT - bool "External display Initialization" + bool "External Display Initialization" default n + select LCD_EXTERNINIT if NX_LCDDRIVER ---help--- Define to support external display initialization by platform- specific code. This this option is defined, then nx_start() will diff --git a/graphics/README.txt b/graphics/README.txt index 4055f638558344096d64a3406e7e2fa73d17b394..c7cc7e374061469810f80d28c972ff4b3d22094f 100644 --- a/graphics/README.txt +++ b/graphics/README.txt @@ -25,7 +25,7 @@ at the present, but here is the longer term roadmap: NXTOOLKIT - A set of C graphics tools that provide higher-level window drawing operations. The toolkit can be used for window-oriented graphics without NxWidgets and is built on top of NX. - NXFONTS - A set of C graphics tools for present (bitmap) font images. + NXFONTS - A set of C graphics tools for presenting (bitmap) font images. NX - The tiny NuttX windowing system. This includes the small-footprint multi-user implentation (NXMU as described below). NX can be used without NxWidgets and without NXTOOLKIT for raw access to window memory. @@ -103,138 +103,7 @@ graphics/vnc Installing New Fonts ^^^^^^^^^^^^^^^^^^^^ - There is a tool called bdf-converter in the directory tools/. The bdf-converter - program be used to convert fonts in Bitmap Distribution Format (BDF) - into fonts that can be used in the NX graphics system. - - Below are general instructions for creating and installing a new font - in the NX graphic system: - - 1. Locate a font in BDF format, - 2. Use the bdf-converter program to convert the BDF font to the NuttX - font format. This will result in a C header file containing - defintions. That header file should be installed at, for example, - graphics/nxfonts/nxfonts_myfont.h. - - Create a new NuttX configuration variable. For example, suppose - you define the following variable: CONFIG_NXFONT_MYFONT. Then - you would need to: - - 3. Define CONFIG_NXFONT_MYFONT=y in your NuttX configuration file. - - A font ID number has to be assigned for each new font. The font ID - is defined in the file include/nuttx/nx/nxfonts.h. Those definitions - have to be extended to support your new font. Look at how the font ID - enabled by CONFIG_NXFONT_SANS23X27 is defined and add an ID for your - new font in a similar fashion: - - 4. include/nuttx/nx/nxfonts.h. Add you new font as a possible system - default font: - - #if defined(CONFIG_NXFONT_SANS23X27) - # define NXFONT_DEFAULT FONTID_SANS23X27 - #elif defined(CONFIG_NXFONT_MYFONT) - # define NXFONT_DEFAULT FONTID_MYFONT - #endif - - Then define the actual font ID. Make sure that the font ID value - is unique: - - enum nx_fontid_e - { - FONTID_DEFAULT = 0 /* The default font */ - #ifdef CONFIG_NXFONT_SANS23X27 - , FONTID_SANS23X27 = 1 /* The 23x27 sans serif font */ - #endif - #ifdef CONFIG_NXFONT_MYFONT - , FONTID_MYFONT = 2 /* My shiny, new font */ - #endif - ... - - New Add the font to the NX build system. There are several files that - you have to modify to to this. Look how the build system uses the - font CONFIG_NXFONT_SANS23X27 for examaples: - - 5. nuttx/graphics/Makefile. This file needs logic to auto-generate - a C source file from the header file that you generated with the - the bdf-converter program. Notice NXFONTS_FONTID=2; this must be - set to the same font ID value that you defined in the - include/nuttx/nx/nxfonts.h file. - - genfontsources: - ifeq ($(CONFIG_NXFONT_SANS23X27),y) - @$(MAKE) -C nxfonts -f Makefile.sources TOPDIR=$(TOPDIR) NXFONTS_FONTID=1 EXTRADEFINES=$(EXTRADEFINES) - endif - ifeq ($(CONFIG_NXFONT_MYFONT),y) - @$(MAKE) -C nxfonts -f Makefile.sources TOPDIR=$(TOPDIR) NXFONTS_FONTID=2 EXTRADEFINES=$(EXTRADEFINES) - endif - - 6. nuttx/graphics/nxfonts/Make.defs. Set the make variable NXFSET_CSRCS. - NXFSET_CSRCS determines the name of the font C file to build when - NXFONTS_FONTID=2: - - ifeq ($(CONFIG_NXFONT_SANS23X27),y) - NXFSET_CSRCS += nxfonts_bitmaps_sans23x27.c - endif - ifeq ($(CONFIG_NXFONT_MYFONT),y) - NXFSET_CSRCS += nxfonts_bitmaps_myfont.c - endif - - 7. nuttx/graphics/nxfonts/Makefile.sources. This is the Makefile used - in step 5 that will actually generate the font C file. So, given - your NXFONTS_FONTID=2, it needs to determine a prefix to use for - auto-generated variable and function names and (again) the name of - the autogenerated file to create (this must be the same name that - was used in nuttx/graphics/nxfonts/Make.defs): - - ifeq ($(NXFONTS_FONTID),1) - NXFONTS_PREFIX := g_sans23x27_ - GEN_CSRC = nxfonts_bitmaps_sans23x27.c - endif - ifeq ($(NXFONTS_FONTID),2) - NXFONTS_PREFIX := g_myfont_ - GEN_CSRC = nxfonts_bitmaps_myfont.c - endif - - 8. graphics/nxfonts/nxfonts_bitmaps.c. This is the file that contains - the generic font structures. It is used as a "template" file by - nuttx/graphics/nxfonts/Makefile.sources to create your customized - font data set. - - #if NXFONTS_FONTID == 1 - # include "nxfonts_sans23x27.h" - #elif NXFONTS_FONTID == 2 - # include "nxfonts_myfont.h" - #else - # error "No font ID specified" - #endif - - Where nxfonts_myfont.h is the NuttX font file that we generated in - step 2 using the bdf-converter tool. - - 9. graphics/nxfonts/nxfonts_getfont.c. Finally, we need to extend the - logic that does the run-time font lookups so that can find our new - font. The lookup function is NXHANDLE nxf_getfonthandle(enum nx_fontid_e fontid). - The new font information needs to be added to data structures used by - that function: - - #ifdef CONFIG_NXFONT_SANS23X27 - extern const struct nx_fontpackage_s g_sans23x27_package; - #endif - #ifdef CONFIG_NXFONT_MYFONT - extern const struct nx_fontpackage_s g_myfont_package; - #endif - - static FAR const struct nx_fontpackage_s *g_fontpackages[] = - { - #ifdef CONFIG_NXFONT_SANS23X27 - &g_sans23x27_package, - #endif - #ifdef CONFIG_NXFONT_MYFONT - &g_myfont_package, - #endif - NULL - }; + [Refer to nuttx/libnx/nxfonts/README.txt] Configuration Settings ^^^^^^^^^^^^^^^^^^^^^^ @@ -278,66 +147,13 @@ CONFIG_NXTK_AUTORAISE If set, a window will be raised to the top if the mouse position is over a visible portion of the window. Default: A mouse button must be clicked over a visible portion of the window. -CONFIG_NXFONTS_CHARBITS - The number of bits in the character set. Current options are only 7 and 8. - The default is 7. CONFIG_VNCSERVER and CONFIG_VNCCLIENT Enable the VNC RFB server and client, respecitively. Font Selections --------------- -CONFIG_NXFONT_SANS17X22 - This option enables support for a tiny, 17x22 san serif font - (font ID FONTID_SANS17X22 == 14). -CONFIG_NXFONT_SANS20X26 - This option enables support for a tiny, 20x26 san serif font - (font ID FONTID_SANS20X26 == 15). -CONFIG_NXFONT_SANS23X27 - This option enables support for a tiny, 23x27 san serif font - (font ID FONTID_SANS23X27 == 1). -CONFIG_NXFONT_SANS22X29 - This option enables support for a small, 22x29 san serif font - (font ID FONTID_SANS22X29 == 2). -CONFIG_NXFONT_SANS28X37 - This option enables support for a medium, 28x37 san serif font - (font ID FONTID_SANS28X37 == 3). -CONFIG_NXFONT_SANS39X48 - This option enables support for a large, 39x48 san serif font - (font ID FONTID_SANS39X48 == 4). -CONFIG_NXFONT_SANS17X23B - This option enables support for a tiny, 17x23 san serif bold font - (font ID FONTID_SANS17X23B == 16). -CONFIG_NXFONT_SANS20X27B - This option enables support for a tiny, 20x27 san serif bold font - (font ID FONTID_SANS20X27B == 17). -CONFIG_NXFONT_SANS22X29B - This option enables support for a small, 22x29 san serif bold font - (font ID FONTID_SANS22X29B == 5). -CONFIG_NXFONT_SANS28X37B - This option enables support for a medium, 28x37 san serif bold font - (font ID FONTID_SANS28X37B == 6). -CONFIG_NXFONT_SANS40X49B - This option enables support for a large, 40x49 san serif bold font - (font ID FONTID_SANS40X49B == 7). -CONFIG_NXFONT_SERIF22X29 - This option enables support for a small, 22x29 font (with serifs) - (font ID FONTID_SERIF22X29 == 8). -CONFIG_NXFONT_SERIF29X37 - This option enables support for a medium, 29x37 font (with serifs) - (font ID FONTID_SERIF29X37 == 9). -CONFIG_NXFONT_SERIF38X48 - This option enables support for a large, 38x48 font (with serifs) - (font ID FONTID_SERIF38X48 == 10). -CONFIG_NXFONT_SERIF22X28B - This option enables support for a small, 27x38 bold font (with serifs) - (font ID FONTID_SERIF22X28B == 11). -CONFIG_NXFONT_SERIF27X38B - This option enables support for a medium, 27x38 bold font (with serifs) - (font ID FONTID_SERIF27X38B == 12). -CONFIG_NXFONT_SERIF38X49B - This option enables support for a large, 38x49 bold font (with serifs) - (font ID FONTID_SERIF38X49B == 13). + [Refer to nuttx/libnx/nxfonts/README.txt] NxTerm Configuration Settings -------------------------------- @@ -394,8 +210,8 @@ CONFIG_NXTERM_NPOLLWAITERS The number of threads that can be waiting for read data available. Default: 4 -NX Multi-user only options --------------------------- +NX Multi-user options +--------------------- CONFIG_NX_BLOCKING Open the client message queues in blocking mode. In this case, @@ -405,5 +221,3 @@ CONFIG_NX_MXSERVERMSGS and CONFIG_NX_MXCLIENTMSGS No additional resources are allocated, but this can be set to prevent flooding of the client or server with too many messages (CONFIG_PREALLOC_MQ_MSGS controls how many messages are pre-allocated). - - diff --git a/graphics/nxglib/fb/nxglib_copyrectangle.c b/graphics/nxglib/fb/nxglib_copyrectangle.c index e2d61aedfa9ff67cdc48baa9435df972c681de53..4b7270f1d06462b939951e75989cdaef0a3b99a0 100644 --- a/graphics/nxglib/fb/nxglib_copyrectangle.c +++ b/graphics/nxglib/fb/nxglib_copyrectangle.c @@ -91,8 +91,9 @@ void NXGL_FUNCNAME(nxgl_copyrectangle, NXGLIB_SUFFIX) rows = dest->pt2.y - dest->pt1.y + 1; #if NXGLIB_BITSPERPIXEL < 8 -# ifdef CONFIG_NX_PACKEDMSFIRST + /* REVISIT: Doesn't the following assume 8 pixels in a byte */ +# ifdef CONFIG_NX_PACKEDMSFIRST /* Get the mask for pixels that are ordered so that they pack from the * MS byte down. */ @@ -111,8 +112,11 @@ void NXGL_FUNCNAME(nxgl_copyrectangle, NXGLIB_SUFFIX) /* Then copy the image */ - sline = (FAR const uint8_t *)src + NXGL_SCALEX(dest->pt1.x - origin->x) + (dest->pt1.y - origin->y) * srcstride; - dline = pinfo->fbmem + dest->pt1.y * deststride + NXGL_SCALEX(dest->pt1.x); + sline = (FAR const uint8_t *)src + + NXGL_SCALEX(dest->pt1.x - origin->x) + + (dest->pt1.y - origin->y) * srcstride; + dline = pinfo->fbmem + dest->pt1.y * deststride + + NXGL_SCALEX(dest->pt1.x); while (rows--) { @@ -130,7 +134,7 @@ void NXGL_FUNCNAME(nxgl_copyrectangle, NXGLIB_SUFFIX) mask = 0xff; dptr++; sptr++; - lnlen--; + lnlen--; /* REVISIT: Is this correct? */ } /* Handle masking of the fractional final byte */ @@ -139,7 +143,7 @@ void NXGL_FUNCNAME(nxgl_copyrectangle, NXGLIB_SUFFIX) if (lnlen > 0 && mask) { dptr[lnlen-1] = (dptr[lnlen-1] & ~mask) | (sptr[lnlen-1] & mask); - lnlen--; + lnlen--; /* REVISIT: Is this correct? */ } /* Handle all of the unmasked bytes in-between */ diff --git a/graphics/nxmu/nx_start.c b/graphics/nxmu/nx_start.c index 36b40fad15167f8a02a077cf03f91084fa63c119..cfa39cc5236148cf93d991d4148b5b42e282c74f 100644 --- a/graphics/nxmu/nx_start.c +++ b/graphics/nxmu/nx_start.c @@ -79,7 +79,7 @@ static bool g_nxserver_started; * ****************************************************************************/ -int nx_server(int argc, char *argv[]) +static int nx_server(int argc, char *argv[]) { FAR NX_DRIVERTYPE *dev; int ret; diff --git a/graphics/nxmu/nxmu_mouse.c b/graphics/nxmu/nxmu_mouse.c index 18f6e03d9a45e96c0c1991ddee353784fc3b488c..66a6cfb8d149ef852d22995b54173b20465c7a98 100644 --- a/graphics/nxmu/nxmu_mouse.c +++ b/graphics/nxmu/nxmu_mouse.c @@ -49,14 +49,6 @@ #ifdef CONFIG_NX_XYINPUT -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - /**************************************************************************** * Private Data ****************************************************************************/ @@ -66,14 +58,6 @@ static struct nxgl_point_s g_mrange; static uint8_t g_mbutton; static struct nxbe_window_s *g_mwnd; -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/graphics/nxmu/nxmu_server.c b/graphics/nxmu/nxmu_server.c index ec5f68ccb914375e49f789b80ac93a5905b7a880..79cb140a3e5732319c6215b634a6e3204d20f5c3 100644 --- a/graphics/nxmu/nxmu_server.c +++ b/graphics/nxmu/nxmu_server.c @@ -346,7 +346,7 @@ int nx_runinstance(FAR const char *mqname, FAR NX_DRIVERTYPE *dev) /* Dispatch the message appropriately */ - DEBUGASSERT(nbytes >= sizeof(struct nxsvrmsg_s)); + DEBUGASSERT(nbytes >= sizeof(struct nxsvrmsg_releasebkgd_s)); msg = (FAR struct nxsvrmsg_s *)buffer; ginfo("Received opcode=%d nbytes=%d\n", msg->msgid, nbytes); diff --git a/include/limits.h b/include/limits.h index 0fdbd057181fa7acdce4d6b7ebc32f6ac253a385..56a9a945e0f1ea92e82d8c3a9be4040ae65013cc 100644 --- a/include/limits.h +++ b/include/limits.h @@ -236,4 +236,8 @@ #define SEM_NSEMS_MAX _POSIX_SEM_NSEMS_MAX #define SEM_VALUE_MAX _POSIX_SEM_VALUE_MAX +/* Required for readv() and writev() */ + +#define IOV_MAX INT_MAX + #endif /* __INCLUDE_LIMITS_H */ diff --git a/include/netinet/tcp.h b/include/netinet/tcp.h new file mode 100644 index 0000000000000000000000000000000000000000..a7784d72262152f87c4654be028d28116e6cdcd6 --- /dev/null +++ b/include/netinet/tcp.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * include/netinet/tcp.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NETINET_TCP_H +#define __INCLUDE_NETINET_TCP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* "The netinet/tcp.h header shall define the following macro for use as a + * socket option at the IPPROTO_TCP level:" -- OpenGroup.org + */ + +#define TCP_NODELAY __SO_PROTOCOL /* Avoid coalescing of small segments. */ + +/* "The macro shall be defined in the header. The implementation need not + * allow the value of the option to be set via setsockopt() or retrieved via + * getsockopt()." -- OpenGroup.org + */ + +#endif /* __INCLUDE_NETINET_TCP_H */ diff --git a/include/nuttx/audio/pcm.h b/include/nuttx/audio/pcm.h index 9b2ffad7418110c5c431f156d2befcdd4d73a5fa..10db4d9b379dfa2a99d42ffb7ddc6b6fdfde953f 100644 --- a/include/nuttx/audio/pcm.h +++ b/include/nuttx/audio/pcm.h @@ -61,10 +61,6 @@ # error CONFIG_AUDIO is required for PCM support #endif -#ifndef CONFIG_SCHED_WORKQUEUE -# error CONFIG_SCHED_WORKQUEUE is required by the PCM decoder -#endif - /* Default configuration values */ /* WAVE Header Definitions **************************************************/ diff --git a/include/nuttx/audio/wm8776.h b/include/nuttx/audio/wm8776.h new file mode 100644 index 0000000000000000000000000000000000000000..1fdf87bf6eb997aa90987957314b067b56ecbf91 --- /dev/null +++ b/include/nuttx/audio/wm8776.h @@ -0,0 +1,97 @@ +/**************************************************************************** + * include/nuttx/audio/wm8776.h + * + * Copyright (C) 2017 Sony Corporation. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_AUDIO_WM8776_H +#define __INCLUDE_NUTTX_AUDIO_WM8776_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#ifdef CONFIG_AUDIO_WM8776 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct wm8776_lower_s; + +struct wm8776_lower_s +{ + /* I2C characterization */ + + uint32_t frequency; /* Initial I2C frequency */ + uint8_t address; /* 7-bit I2C address (only bits 0-6 used) */ +}; + + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +struct i2c_master_s; +struct i2s_dev_s; +struct audio_lowerhalf_s; + +FAR struct audio_lowerhalf_s * + wm8776_initialize(FAR struct i2c_master_s *i2c, + FAR struct i2s_dev_s *i2s, + FAR const struct wm8776_lower_s *lower); + + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_AUDIO_WM8776 */ +#endif /* __INCLUDE_NUTTX_AUDIO_WM8776_H */ diff --git a/include/nuttx/board.h b/include/nuttx/board.h index 00fe5bb1654aff40434ad7863a208b08c9de7759..af120a8808e29e27619a90cf5bcd8b4bd70d3ec4 100644 --- a/include/nuttx/board.h +++ b/include/nuttx/board.h @@ -345,11 +345,12 @@ void board_tsc_teardown(void); * initialization, then this board interface should be provided. * * This is an internal OS interface. It is invoked by graphics sub-system - * initialization logic (nx_start()). + * initialization logic (nx_start()) or from the LCD framebuffer driver + * (when the NX server is not used). * ****************************************************************************/ -#ifdef CONFIG_NX_LCDDRIVER +#if defined(CONFIG_NX_LCDDRIVER) || defined(CONFIG_LCD_FRAMEBUFFER) struct lcd_dev_s; FAR struct lcd_dev_s *board_graphics_setup(unsigned int devno); #else @@ -388,6 +389,9 @@ int board_ioctl(unsigned int cmd, uintptr_t arg); * multiple LCD devices. * board_lcd_uninitialize - Uninitialize the LCD support * + * Alternatively, board_graphics_setup() may be used if external graphics + * initialization is configured. + * ****************************************************************************/ #ifdef CONFIG_LCD diff --git a/include/nuttx/clock.h b/include/nuttx/clock.h index 2c679deb735db790398fd8c36dd5ed3cc9c31bf8..d05d49a50eb3e52f00009a6cf0c0923a0e930a79 100644 --- a/include/nuttx/clock.h +++ b/include/nuttx/clock.h @@ -178,6 +178,19 @@ #define TICK2HSEC(tick) (((tick)+(TICK_PER_HSEC/2))/TICK_PER_HSEC) /* Rounds */ #define TICK2SEC(tick) (((tick)+(TICK_PER_SEC/2))/TICK_PER_SEC) /* Rounds */ +#if defined(CONFIG_DEBUG_FEATURES) && defined(CONFIG_SYSTEM_TIME64) && \ + defined(CONFIG_CLOCK_MONOTONIC) +/* Initial system timer ticks value close to maximum 32-bit value, to test + * 64-bit system-timer after going over 32-bit value. This is to make errors + * of casting 64-bit system-timer to 32-bit variables more visible. + */ + +# define INITIAL_SYSTEM_TIMER_TICKS \ + ((uint64_t)(UINT32_MAX - (TICK_PER_SEC * 5))) +#else +# define INITIAL_SYSTEM_TIMER_TICKS 0 +#endif + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/include/nuttx/fs/dirent.h b/include/nuttx/fs/dirent.h index f616f7347373fa0dda458576d12434104b5ad5e7..ae16f893422b77db65459590d7ceef9c5d905dbd 100644 --- a/include/nuttx/fs/dirent.h +++ b/include/nuttx/fs/dirent.h @@ -177,6 +177,17 @@ struct fs_unionfsdir_s }; #endif +#ifdef CONFIG_FS_USERFS +/* The UserFS uses an opaque representation since the actual userspace representation + * of the directory state structure is unknowable. + */ + +struct fs_userfsdir_s +{ + FAR void *fs_dir; /* Opaque pointer to UserFS DIR */ +}; +#endif + #ifdef CONFIG_FS_HOSTFS /* HOSTFS provides mapping to directories on the host machine in the * sim environment. @@ -184,7 +195,7 @@ struct fs_unionfsdir_s struct fs_hostfsdir_s { - FAR void *fs_dir; /* Opaque pointer to host DIR * */ + FAR void *fs_dir; /* Opaque pointer to host DIR */ }; #endif @@ -254,6 +265,9 @@ struct fs_dirent_s #ifdef CONFIG_FS_UNIONFS struct fs_unionfsdir_s unionfs; #endif +#ifdef CONFIG_FS_USERFS + struct fs_userfsdir_s userfs; +#endif #ifdef CONFIG_FS_HOSTFS struct fs_hostfsdir_s hostfs; #endif diff --git a/include/nuttx/fs/fs.h b/include/nuttx/fs/fs.h index 7058c8ca9522851d069d2184266bf48dfde50a39..bb3b989ab4ae270228d8c7af06cb333b4d58fb25 100644 --- a/include/nuttx/fs/fs.h +++ b/include/nuttx/fs/fs.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/nuttx/fs/fs.h * - * Copyright (C) 2007-2009, 2011-2013, 2015-2017 Gregory Nutt. All rights + * Copyright (C) 2007-2009, 2011-2013, 2015-2018 Gregory Nutt. All rights * reserved. * Author: Gregory Nutt * @@ -280,7 +280,7 @@ struct mountpt_operations int oflags, mode_t mode); /* The following methods must be identical in signature and position - * because the struct file_operations and struct mountp_operations are + * because the struct file_operations and struct mountpt_operations are * treated like unions. */ @@ -301,6 +301,7 @@ struct mountpt_operations int (*sync)(FAR struct file *filep); int (*dup)(FAR const struct file *oldp, FAR struct file *newp); int (*fstat)(FAR const struct file *filep, FAR struct stat *buf); + int (*truncate)(FAR struct file *filep, off_t length); /* Directory operations */ @@ -370,7 +371,7 @@ union inode_ops_u #endif }; -/* This structure represents one inode in the Nuttx pseudo-file system */ +/* This structure represents one inode in the NuttX pseudo-file system */ struct inode { @@ -416,10 +417,10 @@ struct filelist * * When buffering us used, the following described the usage of the I/O buffer. * The buffer can be used for reading or writing -- but not both at the same time. - * An fflush is implied between each change in directionof access. + * An fflush is implied between each change in direction of access. * * The field fs_bufread determines whether the buffer is being used for reading or - * for writing as fillows: + * for writing as follows: * * BUFFER * +----------------------+ <- fs_bufstart Points to the beginning of the buffer. @@ -431,7 +432,7 @@ struct filelist * | | RD: Points to next char to return * +----------------------+ * | WR: Available | <- fs_bufread Top+1 of buffered read data - * | RD: Available | WR: =bufstart buffer used for writing. + * | RD: Available | WR: bufstart buffer used for writing. * | | RD: Pointer to last buffered read char+1 * +----------------------+ * <- fs_bufend Points to end end of the buffer+1 @@ -498,7 +499,7 @@ void fs_initialize(void); * Input parameters: * path - The path to the inode to create * fops - The file operations structure - * mode - inmode priviledges (not used) + * mode - inmode privileges (not used) * priv - Private, user data that will be associated with the inode. * * Returned Value: @@ -525,7 +526,7 @@ int register_driver(FAR const char *path, * Input parameters: * path - The path to the inode to create * bops - The block driver operations structure - * mode - inmode priviledges (not used) + * mode - inmode privileges (not used) * priv - Private, user data that will be associated with the inode. * * Returned Value: @@ -624,7 +625,7 @@ int file_dup2(FAR struct file *filep1, FAR struct file *filep2); * Name: fs_dupfd OR dup * * Description: - * Clone a file descriptor 'fd' to an arbitray descriptor number (any value + * Clone a file descriptor 'fd' to an arbitrary descriptor number (any value * greater than or equal to 'minfd'). If socket descriptors are * implemented, then this is called by dup() for the case of file * descriptors. If socket descriptors are not implemented, then this @@ -670,7 +671,7 @@ int file_dup(FAR struct file *filep, int minfd); * then this function IS dup2(). * * This alternative naming is used when dup2 could operate on both file and - * socket descritors to avoid drawing unused socket support into the link. + * socket descriptors to avoid drawing unused socket support into the link. * * Returned Value: * fs_dupfd2 is sometimes an OS internal function and sometimes is a direct @@ -1021,10 +1022,24 @@ off_t file_seek(FAR struct file *filep, off_t offset, int whence); * ****************************************************************************/ -#if CONFIG_NFILE_DESCRIPTORS > 0 +#if CONFIG_NFILE_DESCRIPTORS > 0 && !defined(CONFIG_DISABLE_MOUNTPOINT) int file_fsync(FAR struct file *filep); #endif +/**************************************************************************** + * Name: file_truncate + * + * Description: + * Equivalent to the standard ftruncate() function except that is accepts + * a struct file instance instead of a file descriptor and it does not set + * the errno variable. + * + ****************************************************************************/ + +#if CONFIG_NFILE_DESCRIPTORS > 0 && !defined(CONFIG_DISABLE_MOUNTPOINT) +int file_truncate(FAR struct file *filep, off_t length); +#endif + /**************************************************************************** * Name: file_ioctl * diff --git a/include/nuttx/fs/ioctl.h b/include/nuttx/fs/ioctl.h index fb4bf6bdd745ee1ab51d44b98ea22ccd5922a919..12572001d626b22dacd1cd85b68fc41f1d3e4358 100644 --- a/include/nuttx/fs/ioctl.h +++ b/include/nuttx/fs/ioctl.h @@ -72,32 +72,34 @@ #define _WLCIOCBASE (0x1300) /* Wireless modules ioctl character driver commands */ #define _CFGDIOCBASE (0x1400) /* Config Data device (app config) ioctl commands */ #define _TCIOCBASE (0x1500) /* Timer ioctl commands */ -#define _DJOYBASE (0x1600) /* Discrete joystick ioctl commands */ -#define _AJOYBASE (0x1700) /* Analog joystick ioctl commands */ -#define _PIPEBASE (0x1800) /* FIFO/pipe ioctl commands */ -#define _RTCBASE (0x1900) /* RTC ioctl commands */ -#define _RELAYBASE (0x1a00) /* Relay devices ioctl commands */ -#define _CANBASE (0x1b00) /* CAN ioctl commands */ -#define _BTNBASE (0x1c00) /* Button ioctl commands */ -#define _ULEDBASE (0x1d00) /* User LED ioctl commands */ -#define _ZCBASE (0x1e00) /* Zero Cross ioctl commands */ -#define _LOOPBASE (0x1f00) /* Loop device commands */ -#define _MODEMBASE (0x2000) /* Modem ioctl commands */ -#define _I2CBASE (0x2100) /* I2C driver commands */ -#define _SPIBASE (0x2200) /* SPI driver commands */ -#define _GPIOBASE (0x2300) /* GPIO driver commands */ -#define _CLIOCBASE (0x2400) /* Contactless modules ioctl commands */ -#define _USBCBASE (0x2500) /* USB-C controller ioctl commands */ -#define _MAC802154BASE (0x2600) /* 802.15.4 MAC ioctl commands */ -#define _PWRBASE (0x2700) /* Power-related ioctl commands */ -#define _FBIOCBASE (0x2800) /* Frame buffer character driver ioctl commands */ -#define _GRIOCBASE (0x2900) /* Generic radio ioctl commands */ +#define _JOYBASE (0x1600) /* Joystick ioctl commands */ +#define _PIPEBASE (0x1700) /* FIFO/pipe ioctl commands */ +#define _RTCBASE (0x1800) /* RTC ioctl commands */ +#define _RELAYBASE (0x1900) /* Relay devices ioctl commands */ +#define _CANBASE (0x1a00) /* CAN ioctl commands */ +#define _BTNBASE (0x1b00) /* Button ioctl commands */ +#define _ULEDBASE (0x1c00) /* User LED ioctl commands */ +#define _ZCBASE (0x1d00) /* Zero Cross ioctl commands */ +#define _LOOPBASE (0x1e00) /* Loop device commands */ +#define _MODEMBASE (0x1f00) /* Modem ioctl commands */ +#define _I2CBASE (0x2000) /* I2C driver commands */ +#define _SPIBASE (0x2100) /* SPI driver commands */ +#define _GPIOBASE (0x2200) /* GPIO driver commands */ +#define _CLIOCBASE (0x2300) /* Contactless modules ioctl commands */ +#define _USBCBASE (0x2400) /* USB-C controller ioctl commands */ +#define _MAC802154BASE (0x2500) /* 802.15.4 MAC ioctl commands */ +#define _PWRBASE (0x2600) /* Power-related ioctl commands */ +#define _FBIOCBASE (0x2700) /* Frame buffer character driver ioctl commands */ +#define _GRIOCBASE (0x2800) /* Generic radio ioctl commands */ /* boardctl() commands share the same number space */ #define _BOARDBASE (0xff00) /* boardctl commands */ -/* Macros used to manage ioctl commands */ +/* Macros used to manage ioctl commands. IOCTL commands are divided into + * groups of 256 commands for major, broad functional areas. That makes + * them a limited resource. + */ #define _IOC_MASK (0x00ff) #define _IOC_TYPE(cmd) ((cmd) & ~_IOC_MASK) @@ -150,6 +152,11 @@ #define FIONSPACE _FIOC(0x0007) /* IN: Location to return value (int *) * OUT: Free space in send queue. */ +#define FIONUSERFS _FIOC(0x0008) /* IN: Pointer to struct usefs_config_s + * holding userfs configuration. + * OUT: Instance number is returned on + * success. + */ /* NuttX file system ioctl definitions **************************************/ @@ -331,17 +338,11 @@ #define _TCIOCVALID(c) (_IOC_TYPE(c)==_TCIOCBASE) #define _TCIOC(nr) _IOC(_TCIOCBASE,nr) -/* Discrete joystick driver ioctl definitions *******************************/ -/* (see nuttx/include/input/djoystick.h */ - -#define _DJOYIOCVALID(c) (_IOC_TYPE(c)==_DJOYBASE) -#define _DJOYIOC(nr) _IOC(_DJOYBASE,nr) - -/* Analog joystick driver ioctl definitions *********************************/ -/* (see nuttx/include/input/ajoystick.h */ +/* Joystick driver ioctl definitions ***************************************/ +/* Discrete Joystick (see nuttx/include/input/djoystick.h */ -#define _AJOYIOCVALID(c) (_IOC_TYPE(c)==_AJOYBASE) -#define _AJOYIOC(nr) _IOC(_AJOYBASE,nr) +#define _JOYIOCVALID(c) (_IOC_SMASK(c)==_JOYBASE) +#define _JOYIOC(nr) _IOC(_JOYBASE,nr) /* FIFOs and pipe driver ioctl definitions **********************************/ diff --git a/include/nuttx/fs/userfs.h b/include/nuttx/fs/userfs.h new file mode 100644 index 0000000000000000000000000000000000000000..29ad9d3d915d0f7ac47f26f1c5bf46d4ca82cbdc --- /dev/null +++ b/include/nuttx/fs/userfs.h @@ -0,0 +1,613 @@ +/**************************************************************************** + * include/nuttx/fs/userfs.h + * + * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_FS_USERFSFS_H +#define __INCLUDE_NUTTX_FS_USERFSFS_H + +/* UserFS is implemented by two components: + * + * 1. A component as part of the internal OS file system logic. This + * file system receives the file system requests and marshals the request + * as described by the following structures, and sends this marshaled + * request on a FIFO that was created by userfs_run(). It also receives + * the marshal led response by the application file system, unmarshals the + * response, and provides the file system response to the caller. + * 2. userfs_run() is part of the NuttX C library. It receives the marshaled + * operating system requests on the FIFO, unmarshals it, and calls the + * application file system methods on behalf of the OS. It the marshals + * the application response data and sends this back to the waiting + * OS file system logic. + * + * Overview of general operation flow: + * + * 1. The UserFS OS support will be instantiated when the UserFS is mounted + * based upon the configuration passed in the optional data of the + * mount command. + * 2. The UserFS server port number will be configured to communicate on a + * LocalHost UDP socket with the server portof 0x83nn where nn is the + * value that was provided when file system was created. + * 3. The UserFs will receive system file system requests and forward them + * on the the MqUfsReqN to the user-space file system server + * (userfs_run()). These requests may be accompanied by additional data in + * an provided request buffer that was provided when the UserFS was + * created. This buffer would hold, for example, the data to be + * written that would accompany a write request. + * 4. The user-space logic of userfs_run() listens at the other end of the + * LocalHost socket. It will receive the requests and forward them + * to the user file system implementation via the methods of struct + * userfs_operations_s + * 5. Responses generated by the struct userfs_operations_s method will be + * returned to UserFS via the LocalHost socket. + * 6. The UserFS kernel thread will listen on the LocalHost socket + * and will receive the user file system responses and forward them to + * the kernel-space file system client. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#ifdef CONFIG_FS_USERFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* UserFS IOCTLs are defined in included/nuttx/fs/ioctl.h. There is only one: + * + * FIONUSERFS. The is the IOCTL that is used with the dev/userfs factory to + * create a UserFS instance. + * + * Input: This function receives an pointer to a read-only instance of + * struct userfs_config_s that contains information needed to + * configure the UserFS instance. + * Output: On success the UserFS nn instance is created. nn is non-negative + * and will be provided as the IOCTL return value on success. On + * failure, ioctl() will return -1 with the errno variable set to + * indicate the cause of the failure. + */ + +/* This is the base value of the server port number. The actual range is + * 0x8300 through 0x83ff. + */ + +#define USERFS_SERVER_PORTBASE 0x8300 + +/* It looks like the maximum size of a request is 16 bytes. We will allow a + * little more for the maximum size of a request structure. + */ + +#define USERFS_REQ_MAXSIZE (32) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* This enumeration provides the type of each request sent from the OS file + * system client to the user file system. + */ + +enum userfs_req_e +{ + USERFS_REQ_OPEN = 0, + USERFS_REQ_CLOSE, + USERFS_REQ_READ, + USERFS_REQ_WRITE, + USERFS_REQ_SEEK, + USERFS_REQ_IOCTL, + USERFS_REQ_SYNC, + USERFS_REQ_DUP, + USERFS_REQ_FSTAT, + USERFS_REQ_TRUNCATE, + USERFS_REQ_OPENDIR, + USERFS_REQ_CLOSEDIR, + USERFS_REQ_READDIR, + USERFS_REQ_REWINDDIR, + USERFS_REQ_STATFS, + USERFS_REQ_UNLINK, + USERFS_REQ_MKDIR, + USERFS_REQ_RMDIR, + USERFS_REQ_RENAME, + USERFS_REQ_STAT, + USERFS_REQ_DESTROY +}; + +/* This enumeration provides the type of each response returned from the + * user file system to OS file system client. + */ + +enum userfs_resp_e +{ + USERFS_RESP_OPEN = 0, + USERFS_RESP_CLOSE, + USERFS_RESP_READ, + USERFS_RESP_WRITE, + USERFS_RESP_SEEK, + USERFS_RESP_IOCTL, + USERFS_RESP_SYNC, + USERFS_RESP_DUP, + USERFS_RESP_FSTAT, + USERFS_RESP_OPENDIR, + USERFS_RESP_CLOSEDIR, + USERFS_RESP_READDIR, + USERFS_RESP_REWINDDIR, + USERFS_RESP_STATFS, + USERFS_RESP_UNLINK, + USERFS_RESP_MKDIR, + USERFS_RESP_RMDIR, + USERFS_RESP_RENAME, + USERFS_RESP_STAT, + USERFS_RESP_DESTROY +}; + +/* These structures are used by internal UserFS implementation and should not + * be of interest to application level logic. + * + * This is passed to the mount() function as optional data when the UserFS + * file system is mounted. + */ + +struct userfs_config_s +{ + size_t mxwrite; /* The max size of a write data */ + uint16_t portno; /* The server port number (host order) */ +}; + +/* This structure identifies the user-space file system operations. */ + +struct stat; /* Forward reference */ +struct statfs; /* Forward reference */ + +struct userfs_operations_s +{ + int (*open)(FAR void *volinfo, FAR const char *relpath, + int oflags, mode_t mode, FAR void **openinfo); + int (*close)(FAR void *volinfo, FAR void *openinfo); + ssize_t (*read)(FAR void *volinfo, FAR void *openinfo, + FAR char *buffer, size_t buflen); + ssize_t (*write)(FAR void *volinfo, FAR void *openinfo, + FAR const char *buffer, size_t buflen); + off_t (*seek)(FAR void *volinfo, FAR void *openinfo, off_t offset, + int whence); + int (*ioctl)(FAR void *volinfo, FAR void *openinfo, int cmd, + unsigned long arg); + int (*sync)(FAR void *volinfo, FAR void *openinfo); + int (*dup)(FAR void *volinfo, FAR void *oldinfo, FAR void **newinfo); + int (*fstat)(FAR void *volinfo, FAR void *openinfo, + FAR struct stat *buf); + int (*truncate)(FAR void *volinfo, FAR void *openinfo, off_t length); + int (*opendir)(FAR void *volinfo, FAR const char *relpath, + FAR void **dir); + int (*closedir)(FAR void *volinfo, FAR void *dir); + int (*readdir)(FAR void *volinfo, FAR void *dir, + FAR struct dirent *entry); + int (*rewinddir)(FAR void *volinfo, FAR void *dir); + int (*statfs)(FAR void *volinfo, FAR struct statfs *buf); + int (*unlink)(FAR void *volinfo, FAR const char *relpath); + int (*mkdir)(FAR void *volinfo, FAR const char *relpath, mode_t mode); + int (*rmdir)(FAR void *volinfo, FAR const char *relpath); + int (*rename)(FAR void *volinfo, FAR const char *oldrelpath, + FAR const char *newrelpath); + int (*stat)(FAR void *volinfo, FAR const char *relpath, + FAR struct stat *buf); + int (*destroy)(FAR void *volinfo); +}; + +/* The following structures describe the header on the marshaled data sent + * on the FIFOs. See struct userfs_operations_s for the form of the + * marshaled function calls. + */ + +struct userfs_open_request_s +{ + uint8_t req; /* Must be USERFS_REQ_OPEN */ + int oflags; /* Open flags */ + mode_t mode; /* Open mode */ + char relpath[1]; /* Mountpoint relative path to the file to open */ +}; + +#define SIZEOF_USERFS_OPEN_REQUEST_S(n) (sizeof(struct userfs_open_request_s) + (n) - 1) + +struct userfs_open_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_OPEN */ + FAR void *openinfo; /* Open file info for use in other operations */ + int ret; /* Result of the operation */ +}; + +struct userfs_close_request_s +{ + uint8_t req; /* Must be USERFS_REQ_CLOSE */ + FAR void *openinfo; /* Open file info as returned by open() */ +}; + +struct userfs_close_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_CLOSE */ + int ret; /* Result of the operation */ +}; + +struct userfs_read_request_s +{ + uint8_t req; /* Must be USERFS_REQ_READ */ + FAR void *openinfo; /* Open file info as returned by open() */ + size_t readlen; /* Maximum number of bytes to read */ +}; + +struct userfs_read_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_READ */ + ssize_t nread; /* Result of the operation */ + char rddata[1]; /* Read data follows. Actual size is nread */ +}; + +#define SIZEOF_USERFS_READ_RESPONSE_S(n) (sizeof(struct userfs_read_response_s) + (n) - 1) + +struct userfs_write_request_s +{ + uint8_t req; /* Must be USERFS_REQ_WRITE */ + FAR void *openinfo; /* Open file info as returned by open() */ + size_t writelen; /* Number of bytes to write */ + char wrdata[1]; /* Read data follows. Actual size is wrsize */ +}; + +#define SIZEOF_USERFS_WRITE_REQUEST_S(n) (sizeof(struct userfs_write_request_s) + (n) - 1) + +struct userfs_write_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_WRITE */ + ssize_t nwritten; /* Result of the operation */ +}; + +struct userfs_seek_request_s +{ + uint8_t req; /* Must be USERFS_REQ_SEEK */ + FAR void *openinfo; /* Open file info as returned by open() */ + off_t offset; /* Seek offset */ + int whence; /* Determines how offset is interpreted */ +}; + +struct userfs_seek_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_SEEK */ + off_t ret; /* Result of the operation */ +}; + +struct userfs_ioctl_request_s +{ + uint8_t req; /* Must be USERFS_REQ_IOCTL */ + FAR void *openinfo; /* Open file info as returned by open() */ + int cmd; /* IOCTL command */ + unsigned long arg; /* Argument that accompanies the command */ +}; + +struct userfs_ioctl_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_IOCTL */ + int ret; /* Result of the operation */ +}; + +struct userfs_sync_request_s +{ + uint8_t req; /* Must be USERFS_REQ_SYNC */ + FAR void *openinfo; /* Open file info as returned by open() */ +}; + +struct userfs_sync_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_SYNC */ + int ret; /* Result of the operation */ +}; + +struct userfs_dup_request_s +{ + uint8_t req; /* Must be USERFS_REQ_DUP */ + FAR void *openinfo; /* Open file info as returned by open() */ +}; + +struct userfs_dup_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_DUP */ + FAR void *openinfo; /* Open file info for the dup'ed file */ + int ret; /* Result of the operation */ +}; + +struct userfs_fstat_request_s +{ + uint8_t req; /* Must be USERFS_REQ_FSTAT */ + FAR void *openinfo; /* Open file info as returned by open() */ +}; + +struct userfs_fstat_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_FSTAT */ + int ret; /* Result of the operation */ + FAR struct stat buf; /* Returned file system status */ +}; + +struct userfs_truncate_request_s +{ + uint8_t req; /* Must be USERFS_REQ_TRUNCATE */ + FAR void *openinfo; /* Open file info as returned by open() */ + off_t length; /* New length of the file */ +}; + +struct userfs_truncate_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_FSTAT */ + int ret; /* Result of the operation */ +}; + +struct userfs_opendir_request_s +{ + uint8_t req; /* Must be USERFS_REQ_OPENDIR */ + char relpath[1]; /* Mountpoint relative path to the directory to open */ +}; + +#define SIZEOF_USERFS_OPENDIR_REQUEST_S(n) (sizeof(struct userfs_opendir_request_s) + (n) - 1) + +struct userfs_opendir_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_OPENDIR */ + int ret; /* Result of the operation */ + FAR void *dir; /* Opaque pointer to directory information */ +}; + +struct userfs_closedir_request_s +{ + uint8_t req; /* Must be USERFS_REQ_CLOSEDIR */ + FAR void *dir; /* Opaque pointer to directory information */ +}; + +struct userfs_closedir_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_CLOSEDIR */ + int ret; /* Result of the operation */ +}; + +struct userfs_readdir_request_s +{ + uint8_t req; /* Must be USERFS_REQ_READDIR */ + FAR void *dir; /* Opaque pointer to directory information */ +}; + +struct userfs_readdir_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_READDIR */ + int ret; /* Result of the operation */ + struct dirent entry; /* Directory entry that was read */ +}; + +struct userfs_rewinddir_request_s +{ + uint8_t req; /* Must be USERFS_REQ_REWINDDIR */ + FAR void *dir; /* Opaque pointer to directory information */ +}; + +struct userfs_rewinddir_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_REWINDDIR */ + int ret; /* Result of the operation */ +}; + +struct userfs_statfs_request_s +{ + uint8_t req; /* Must be USERFS_REQ_STATFS */ +}; + +struct userfs_statfs_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_STATFS */ + int ret; /* Result of the operation */ + FAR struct statfs buf; /* Returned file system status */ +}; + +struct userfs_unlink_request_s +{ + uint8_t req; /* Must be USERFS_REQ_UNLINK */ + char relpath[1]; /* Relative path to the entry to unlink */ +}; + +#define SIZEOF_USERFS_UNLINK_REQUEST_S(n) (sizeof(struct userfs_unlink_request_s) + (n) - 1) + +struct userfs_unlink_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_UNLINK */ + int ret; /* Result of the operation */ +}; + +struct userfs_mkdir_request_s +{ + uint8_t req; /* Must be USERFS_REQ_MKDIR */ + mode_t mode; /* Directory mode flags */ + char relpath[1]; /* Relative path to the directory to create */ +}; + +#define SIZEOF_USERFS_MKDIR_REQUEST_S(n) (sizeof(struct userfs_mkdir_request_s) + (n) - 1) + +struct userfs_mkdir_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_MKDIR */ + int ret; /* Result of the operation */ +}; + +struct userfs_rmdir_request_s +{ + uint8_t req; /* Must be USERFS_REQ_RMDIR */ + char relpath[1]; /* Relative path to the directory to remove */ +}; + +#define SIZEOF_USERFS_RMDIR_REQUEST_S(n) (sizeof(struct userfs_rmdir_request_s) + (n) - 1) + +struct userfs_rmdir_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_RMDIR */ + int ret; /* Result of the operation */ +}; + +struct userfs_rename_request_s +{ + uint8_t req; /* Must be USERFS_REQ_RENAME */ + uint16_t newoffset; /* Offset from old to new relpath */ + char oldrelpath[1]; /* Old relative path to be renamed */ +}; + +#define SIZEOF_USERFS_RENAME_REQUEST_S(o,n) (sizeof(struct userfs_rename_request_s) + (o) + (n)) + +struct userfs_rename_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_RENAME */ + int ret; /* Result of the operation */ +}; + +struct userfs_stat_request_s +{ + uint8_t req; /* Must be USERFS_REQ_STAT */ + char relpath[1]; /* Relative path to the directory entry to be queried */ +}; + +#define SIZEOF_USERFS_STAT_REQUEST_S(n) (sizeof(struct userfs_stat_request_s) + (n) - 1) + +struct userfs_stat_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_STAT */ + int ret; /* Result of the operation */ + FAR struct stat buf; /* Returned status of the directory entry */ +}; + +struct userfs_destroy_request_s +{ + uint8_t req; /* Must be USERFS_REQ_DESTROY */ +}; + +struct userfs_destroy_response_s +{ + uint8_t resp; /* Must be USERFS_RESP_DESTROY */ + int ret; /* Result of the operation */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: userfs_register + * + * Description: + * Register the UserFS factory driver at dev/userfs. + * + * NOTE: This is an OS internal function that should not be called from + * appliation logic. + * + * Input parameters: + * None + * + * Returned Value: + * Zero (OK) is returned if the dev/userfs driver was intitialized and + * registered properly. Otherwise, a negated errno value is returned + * to indicate the nature of the failure. + * + ****************************************************************************/ + +int userfs_register(void); + +/**************************************************************************** + * Name: userfs_run + * + * Description: + * Start the UserFS server on the current thread. This function will mount + * the UserFS file system and will not return until that file system has + * been unmounted. + * + * userfs_run() implements the UserFS server. It performs there operations: + * + * 1. It configures and creates the UserFS file system and + * 2. Mounts the user file system at the provide mount point path. + * 2. Receives file system requests on the LocalHost socket with + * server port 0x83nn where nn is the same as above, + * 3. Received file system requests are marshaled and dispatch to the + * user file system via callbacks to the operations provided by + * "userops", and + * 3. Returns file system responses generated by the callbacks to the + * LocalHost client socket. + * + * NOTE: This is a user function that is implemented as part of the + * NuttX C library and is intended to be called by appliation logic. + * + * Input parameters: + * mountpt - Mountpoint path + * userops - The caller operations that implement the file system + * interface. + * volinfo - Private volume data that will be provided in all struct + * userfs_operations_s methods. + * mxwrite - The max size of a write data + * + * Returned Value: + * This function does not return unless the file system is unmounted (OK) + * or unless an error is encountered. In the event of an error, the + * returned value is a negated errno value indicating the nature of the + * error. + * + ****************************************************************************/ + +int userfs_run(FAR const char *mountpt, + FAR const struct userfs_operations_s *userops, + FAR void *volinfo, size_t mxwrite); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_FS_USERFS */ +#endif /* __INCLUDE_NUTTX_FS_USERFSFS_H */ diff --git a/include/nuttx/input/ajoystick.h b/include/nuttx/input/ajoystick.h index 9704943db6b99f06a705f1c0eae1c973d953304d..7cc7d384b0da90987e0164d05cd3bb3c4a85e6d1 100644 --- a/include/nuttx/input/ajoystick.h +++ b/include/nuttx/input/ajoystick.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/nuttx/input/ajoystick.h * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -56,7 +56,7 @@ ****************************************************************************/ #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/include/nuttx/input/djoystick.h b/include/nuttx/input/djoystick.h index 84dbf318aff5e74adcbe93b79b7a3e439010add5..3f0f1e0aa96f7bb37036a9e22e6896bc9ea9b759 100644 --- a/include/nuttx/input/djoystick.h +++ b/include/nuttx/input/djoystick.h @@ -56,7 +56,7 @@ ****************************************************************************/ #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/include/nuttx/input/ft5x06.h b/include/nuttx/input/ft5x06.h new file mode 100644 index 0000000000000000000000000000000000000000..791f13ee1054e87b35897dbc380230e9837a68de --- /dev/null +++ b/include/nuttx/input/ft5x06.h @@ -0,0 +1,170 @@ +/**************************************************************************** + * include/nuttx/input/ft5x06.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: + * "FT5x06", FocalTech Systems Co., Ltd, D-FT5x06-1212-V4.0, Revised + * Dec. 18, 2012 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The FT5x06 Series ICs are single-chip capacitive touch panel controller + * ICs with a built-in 8 bit Micro-controller unit (MCU). They adopt the + * mutual capacitance approach, which supports true multi-touch capability. + * In conjunction with a mutual capacitive touch panel, the FT5x06 have + * user-friendly input functions, which can be applied on many portable + * devices, such as cellular phones, MIDs, netbook and notebook personal + * computers. + */ + +#ifndef __INCLUDE_NUTTX_INPUT_FT5X06_H +#define __INCLUDE_NUTTX_INPUT_FT5X06_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#ifdef CONFIG_INPUT_FT5X06 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ +/* Maximum number of threads than can be waiting for POLL events */ + +#ifndef CONFIG_FT5X06_NPOLLWAITERS +# define CONFIG_FT5X06_NPOLLWAITERS 2 +#endif + +/* Check for some required settings. This can save the user a lot of time + * in getting the right configuration. + */ + +#ifdef CONFIG_DISABLE_SIGNALS +# error "Signals are required. CONFIG_DISABLE_SIGNALS must not be selected." +#endif + +#ifndef CONFIG_SCHED_WORKQUEUE +# error "Work queue support required. CONFIG_SCHED_WORKQUEUE must be selected." +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the FT5X06 + * driver. This structure provides information about the configuration + * of the FT5x06 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writeable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +struct ft5x06_config_s +{ + /* Device characterization */ + + uint8_t address; /* 7-bit I2C address (only bits 0-6 used) */ + uint32_t frequency; /* Default I2C frequency */ + + /* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the FT5X06 driver from differences in GPIO + * interrupt handling by varying boards and MCUs. + * + * attach - Attach an FT5x06 interrupt handler to a GPIO interrupt + * enable - Enable or disable a GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + * wakeup - Issue WAKE interrupt to FT5x06 to change the FT5x06 from + * Hibernate to Active mode. + * nreset - Control the chip reset pin (active low) + + */ + +#ifndef CONFIG_FT5X06_POLLMODE + int (*attach)(FAR const struct ft5x06_config_s *config, xcpt_t isr, + FAR void *arg); + void (*enable)(FAR const struct ft5x06_config_s *config, bool enable); + void (*clear)(FAR const struct ft5x06_config_s *config); +#endif + void (*wakeup)(FAR const struct ft5x06_config_s *config); + void (*nreset)(FAR const struct ft5x06_config_s *config, + bool state); +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: ft5x06_register + * + * Description: + * Configure the FT5x06 to use the provided I2C device instance. This + * will register the driver as /dev/inputN where N is the minor device + * number + * + * Input Parameters: + * i2c - An I2C driver instance + * config - Persistent board configuration data + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int ft5x06_register(FAR struct i2c_master_s *i2c, + FAR const struct ft5x06_config_s *config, int minor); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_INPUT_FT5X06 */ +#endif /* __INCLUDE_NUTTX_INPUT_FT5X06_H */ diff --git a/include/nuttx/input/ioctl.h b/include/nuttx/input/ioctl.h new file mode 100644 index 0000000000000000000000000000000000000000..bcf370d9616a84a95cd1c86324b05660836ed2e7 --- /dev/null +++ b/include/nuttx/input/ioctl.h @@ -0,0 +1,76 @@ +/************************************************************************************ + * include/nuttx/input/ioctl.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __INCLUDE_NUTTX_INPUT_IOCTL_H +#define __INCLUDE_NUTTX_INPUT_IOCTL_H 1 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define _JOYIOC_MASK (0x001f) +#define _JOYIOC_TYPE(cmd) ((cmd) & ~_JOYIOC_MASK) +#define _JOYIOC_NBR(cmd) ((cmd) & _JOYIOC_MASK) + +/* Discrete Joystick (see nuttx/include/input/djoystick.h */ + +#define _DJOYBASE (_JOYBASE | 0x0000) + +#define _DJOYIOCVALID(c) (_JOYIOC_MASK(c)==_DJOYBASE) +#define _DJOYIOC(nr) _IOC(_DJOYBASE,nr) + +/* Analog Joystick (see nuttx/include/input/ajoystick.h */ + +#define _AJOYBASE (_JOYBASE | 0x0020) + +#define _AJOYIOCVALID(c) (_JOYIOC_MASK(c)==_AJOYBASE) +#define _AJOYIOC(nr) _IOC(_AJOYBASE,nr) + +/* Nunchuck Wii controller */ + +#define _NUNCKIOCBASE (_JOYBASE | 0x0040) + +#define _NUNCHUCKIOCVALID(c) (_IOC_TYPE(c)==_NUNCKIOCBASE) +#define _NUNCHUCKIOC(nr) _IOC(_NUNCKIOCBASE,nr) + +#endif /* __INCLUDE_NUTTX_INPUT_IOCTL_H */ + diff --git a/include/nuttx/input/nunchuck.h b/include/nuttx/input/nunchuck.h new file mode 100644 index 0000000000000000000000000000000000000000..844b66abc2cf1eabc5362ca892d5372083261e94 --- /dev/null +++ b/include/nuttx/input/nunchuck.h @@ -0,0 +1,186 @@ +/**************************************************************************** + * include/nuttx/input/nunchuck.h + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This header file provides definition for Nintendo Wii Nunchuck joystick + * interface. The Nunchuck joystick provides X/Y positional data as integer + * values. The analog positional data may also be accompanied by discrete button + * data. + * + * The nunchuck joystick driver exports a standard character driver + * interface. By convention, the nunchuck joystick is registered as an input + * device at /dev/nunchuckN where N uniquely identifies the driver instance. + */ + +#ifndef __INCLUDE_NUTTX_INPUT_NUNCHUCK_H +#define __INCLUDE_NUTTX_INPUT_NUNCHUCK_H 1 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NUNCHUCK_ADDR 0x52 /* Nunchuck at address 0x52 */ +#define NUNCHUCK_I2C_FREQ 100000 /* 100Khz */ + +/* Joystick Interface *******************************************************/ +/* These definitions provide the meaning of all of the bits that may be + * reported in the nunchuck_buttonset_t bitset. + */ + +#define NUNCHUCK_BUTTON(n) ((n)-1) /* Bit n-1: Button n, n=1..2 */ +#define NUNCHUCK_BUTTON_Z (0) /* Bit 0: Button Z */ +#define NUNCHUCK_BUTTON_C (1) /* Bit 1: Button C */ +#define NUNCHUCK_NBUTTONS (2) /* Total number of buttons */ + +#define NUNCHUCK_BUTTON_Z_BIT (1 << NUNCHUCK_BUTTON_Z) /* 1:Button C pressed */ +#define NUNCHUCK_BUTTON_C_BIT (1 << NUNCHUCK_BUTTON_C) /* 1:Button Z pressed */ +#define NUNCHUCK_BUTTONS_ALL 0x3 /* Set of all buttons */ + +/* Typical usage */ + +#define NUNCHUCK_BUTTON_SELECT NUNCHUCK_BUTTON_C +#define NUNCHUCK_BUTTON_FIRE NUNCHUCK_BUTTON_Z +#define NUNCHUCK_BUTTON_JUMP 0 + +#define NUNCHUCK_BUTTON_SELECT_BIT NUNCHUCK_BUTTON_C_BIT +#define NUNCHUCK_BUTTON_FIRE_BIT NUNCHUCK_BUTTON_Z_BIT +#define NUNCHUCK_BUTTON_JUMP_BIT 0 + +/* IOCTL commands + * + * Nunchuck joystick drivers do not support the character driver write() or + * seek() methods. The remaining driver methods behave as follows: + * + * 1) The read() method will always return a single value of size + * struct nunchuck_sample_s represent the current joystick positional and the + * state of all joystick buttons. read() never blocks. X an Y position + * data is raw converted data. Zeroing and scaling must be performed by + * the application. + * 2) The ioctl() method supports the commands documented below: + */ + +/* Command: NUNCHUCKIOC_SUPPORTED + * Description: Report the set of button events supported by the hardware; + * Argument: A pointer to writeable integer value in which to return the + * set of supported buttons. + * Return: Zero (OK) on success. Minus one will be returned on failure + * with the errno value set appropriately. + */ + +#define NUNCHUCKIOC_SUPPORTED _NUNCHUCKIOC(0x0001) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* This type is a bit set that contains the state of all analog joystick + * buttons. + */ + +typedef uint8_t nunchuck_buttonset_t; + +/* This structure is returned by read() and provides the sample state of the + * nunchuck joystick. + * + * NOTE: that this structure is equivalent to the struct mouse_report_s + * structure (with no wheel) defined in include/nuttx/input/mouse.h and can + * be used interchangeably in certain contexts. + */ + +struct nunchuck_sample_s +{ + /* Compatible with analog joystick */ + + nunchuck_buttonset_t nck_buttons; /* State of all buttons */ + /* Possibly padded with 1 byte here */ + int16_t js_x; /* X/horizontal position */ + int16_t js_y; /* Y/vertical position */ + + /* Specific of the Nunchuck */ + + int8_t acc_x; /* Accelerometer X */ + int8_t acc_y; /* Accelerometer Y */ + int8_t acc_z; /* Accelerometer Z */ +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nunchuck_register + * + * Description: + * Register the Nunchuck character driver as the specified device. + * + * Input Parameters: + * devname - The name of the Nunchuck joystick device to be registered. + * This should be a string of the form "/dev/nunchuckN" where N is the + * minor device number. + * i2c - An instance of the platform-specific I2C connected to Nunchuck. + * + * Returned Values: + * Zero (OK) is returned on success. Otherwise a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +struct i2c_master_s; +int nunchuck_register(FAR const char *devname, FAR struct i2c_master_s *i2c); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_INPUT_NUNCHUCK_H */ diff --git a/include/nuttx/input/stmpe811.h b/include/nuttx/input/stmpe811.h index 861377e81e4cd1ca215c46e87d89afbb470e9cc3..9e0b98ada7c94947ef84eb04a081e25c7b83d56c 100644 --- a/include/nuttx/input/stmpe811.h +++ b/include/nuttx/input/stmpe811.h @@ -190,7 +190,7 @@ #define STMPE811_GPIO_SETPIN 0x10 /* GPIO set pin register */ #define STMPE811_GPIO_CLRPIN 0x11 /* GPIO clear pin register */ #define STMPE811_GPIO_MPSTA 0x12 /* GPIO monitor pin state register */ -#define STMPE811_GPIO_DIR 0x13 /* GPIO direction register */ +#define STMPE811_GPIO_DIR_REG 0x13 /* GPIO direction register */ #define STMPE811_GPIO_ED 0x14 /* GPIO edge detect register */ #define STMPE811_GPIO_RE 0x15 /* GPIO rising edge register */ #define STMPE811_GPIO_FE 0x16 /* GPIO falling edge register */ diff --git a/include/nuttx/input/touchscreen.h b/include/nuttx/input/touchscreen.h index 96041946cbafd0c5231e82dc19f2f4eb2adbab8d..b3c6210c1a33b00b2be9370a0746bd1ab4077a9f 100644 --- a/include/nuttx/input/touchscreen.h +++ b/include/nuttx/input/touchscreen.h @@ -100,7 +100,7 @@ #define TOUCH_DOWN (1 << 0) /* A new touch contact is established */ #define TOUCH_MOVE (1 << 1) /* Movement occurred with previously reported contact */ #define TOUCH_UP (1 << 2) /* The touch contact was lost */ -#define TOUCH_ID_VALID (1 << 3) /* Touch ID is uncertain */ +#define TOUCH_ID_VALID (1 << 3) /* Touch ID is certain */ #define TOUCH_POS_VALID (1 << 4) /* Hardware provided a valid X/Y position */ #define TOUCH_PRESSURE_VALID (1 << 5) /* Hardware provided a valid pressure */ #define TOUCH_SIZE_VALID (1 << 6) /* Hardware provided a valid H/W contact size */ diff --git a/include/nuttx/ioexpander/gpio.h b/include/nuttx/ioexpander/gpio.h index c0d091753c1a4e17e9c1f14e7b087337d75ac0bf..e8a0c44a4d4c58e9e8719cd8e72f004425ab9c4b 100644 --- a/include/nuttx/ioexpander/gpio.h +++ b/include/nuttx/ioexpander/gpio.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * include/nuttx/ioexpander/gpio.h * * Copyright (C) 2016 Gregory Nutt. All rights reserved. @@ -31,7 +31,7 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __INCLUDE_NUTTX_IOEXPANDER_GPIO_H #define __INCLUDE_NUTTX_IOEXPANDER_GPIO_H diff --git a/include/nuttx/irq.h b/include/nuttx/irq.h index a4bb107a2389f11c789af4a516480d32afc2472e..8f4ed3824f4631a2d8ee198cb49fdb46d674e92a 100644 --- a/include/nuttx/irq.h +++ b/include/nuttx/irq.h @@ -222,6 +222,65 @@ void leave_critical_section(irqstate_t flags); # define leave_critical_section(f) up_irq_restore(f) #endif +/**************************************************************************** + * Name: spin_lock_irqsave + * + * Description: + * If SMP and SPINLOCK_IRQ are enabled: + * Disable local interrupts and take the global spinlock (g_irq_spin) + * if the call counter (g_irq_spin_count[cpu]) equals to 0. Then the + * counter on the CPU is increment to allow nested call. + * + * NOTE: This API is very simple to protect data (e.g. H/W register + * or internal data structure) in SMP mode. But do not use this API + * with kernel APIs which suspend a caller thread. (e.g. nxsem_wait) + * + * If SMP and SPINLOCK_IRQ are not enabled: + * This function is equivalent to enter_critical_section(). + * + * Input Parameters: + * None + * + * Returned Value: + * An opaque, architecture-specific value that represents the state of + * the interrupts prior to the call to spin_lock_irqsave(); + * + ****************************************************************************/ + +#if defined (CONFIG_SMP) && defined (CONFIG_SPINLOCK_IRQ) +irqstate_t spin_lock_irqsave(void); +#else +# define spin_lock_irqsave(f) enter_critical_section(f) +#endif + +/**************************************************************************** + * Name: spin_unlock_irqrestore + * + * Description: + * If SMP and SPINLOCK_IRQ are enabled: + * Decrement the call counter (g_irq_spin_count[cpu]) and if it + * decrements to zero then release the spinlock (g_irq_spin) and + * restore the interrupt state as it was prior to the previous call to + * spin_lock_irqsave(). + * + * If SMP and SPINLOCK_IRQ are not enabled: + * This function is equivalent to leave_critical_section(). + * + * Input Parameters: + * flags - The architecture-specific value that represents the state of + * the interrupts prior to the call to spin_lock_irqsave(); + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined (CONFIG_SMP) && defined (CONFIG_SPINLOCK_IRQ) +void spin_unlock_irqrestore(irqstate_t flags); +#else +# define spin_unlock_irqrestore(f) leave_critical_section(f) +#endif + #undef EXTERN #ifdef __cplusplus } diff --git a/include/nuttx/kmalloc.h b/include/nuttx/kmalloc.h index 4734a264f61ccce8e9d71d5b99a3fe2ab617e4df..4809b849aba68970ec96a53c6451821bceca97aa 100644 --- a/include/nuttx/kmalloc.h +++ b/include/nuttx/kmalloc.h @@ -61,11 +61,11 @@ #undef KMALLOC_EXTERN #if defined(__cplusplus) -# define KMALLOC_EXTERN extern "C" +# define KMALLOC_EXTERN extern "C" extern "C" { #else -# define KMALLOC_EXTERN extern +# define KMALLOC_EXTERN extern #endif /**************************************************************************** @@ -94,6 +94,11 @@ extern "C" #define kumm_realloc(p,s) realloc(p,s) #define kumm_memalign(a,s) memalign(a,s) #define kumm_free(p) free(p) +#ifdef CONFIG_CAN_PASS_STRUCTS +# define kumm_mallinfo() mallinfo() +#else +# define kumm_mallinfo(i) mallinfo(i) +#endif /* This family of allocators is used to manage kernel protected memory */ @@ -102,16 +107,21 @@ extern "C" * as were used for the user-mode function. */ -# define kmm_initialize(h,s) /* Initialization done by kumm_initialize */ -# define kmm_addregion(h,s) umm_addregion(h,s) -# define kmm_trysemaphore() umm_trysemaphore() -# define kmm_givesemaphore() umm_givesemaphore() - -# define kmm_malloc(s) malloc(s) -# define kmm_zalloc(s) zalloc(s) -# define kmm_realloc(p,s) realloc(p,s) -# define kmm_memalign(a,s) memalign(a,s) -# define kmm_free(p) free(p) +# define kmm_initialize(h,s) /* Initialization done by kumm_initialize */ +# define kmm_addregion(h,s) umm_addregion(h,s) +# define kmm_trysemaphore() umm_trysemaphore() +# define kmm_givesemaphore() umm_givesemaphore() + +# define kmm_malloc(s) malloc(s) +# define kmm_zalloc(s) zalloc(s) +# define kmm_realloc(p,s) realloc(p,s) +# define kmm_memalign(a,s) memalign(a,s) +# define kmm_free(p) free(p) +#ifdef CONFIG_CAN_PASS_STRUCTS +# define kmm_mallinfo() mallinfo() +#else +# define kmm_mallinfo(i) mallinfo(i) +#endif #elif !defined(CONFIG_MM_KERNEL_HEAP) /* If this the kernel phase of a kernel build, and there are only user-space @@ -119,16 +129,21 @@ extern "C" * call into user-space via a header at the beginning of the user-space blob. */ -# define kmm_initialize(h,s) /* Initialization done by kumm_initialize */ -# define kmm_addregion(h,s) umm_addregion(h,s) -# define kmm_trysemaphore() umm_trysemaphore() -# define kmm_givesemaphore() umm_givesemaphore() - -# define kmm_malloc(s) umm_malloc(s) -# define kmm_zalloc(s) umm_zalloc(s) -# define kmm_realloc(p,s) umm_realloc(p,s) -# define kmm_memalign(a,s) umm_memalign(a,s) -# define kmm_free(p) umm_free(p) +# define kmm_initialize(h,s) /* Initialization done by kumm_initialize */ +# define kmm_addregion(h,s) umm_addregion(h,s) +# define kmm_trysemaphore() umm_trysemaphore() +# define kmm_givesemaphore() umm_givesemaphore() + +# define kmm_malloc(s) malloc(s) +# define kmm_zalloc(s) zalloc(s) +# define kmm_realloc(p,s) realloc(p,s) +# define kmm_memalign(a,s) memalign(a,s) +# define kmm_free(p) free(p) +#ifdef CONFIG_CAN_PASS_STRUCTS +# define kmm_mallinfo() mallinfo() +#else +# define kmm_mallinfo(i) mallinfo(i) +#endif #else /* Otherwise, the kernel-space allocators are declared in include/nuttx/mm/mm.h diff --git a/include/nuttx/lcd/max7219.h b/include/nuttx/lcd/max7219.h new file mode 100644 index 0000000000000000000000000000000000000000..ee027e99eb4af16c16d94dfdaea23fb9ac084cd2 --- /dev/null +++ b/include/nuttx/lcd/max7219.h @@ -0,0 +1,128 @@ +/**************************************************************************** + * include/nuttx/lcd/max7219.h + * + * Copyright (C) 2017 Alan Carvalho de Assis. All rights reserved. + * Author: Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_LCD_MAX7219_H +#define __INCLUDE_NUTTX_LCD_MAX7219_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/* Configuration + * CONFIG_SPI - Enables support for SPI drivers + * CONFIG_LCD_MAX7219 - Enables support for the MAX7219 driver + */ + +#if defined(CONFIG_SPI) && defined(CONFIG_LCD_MAX7219) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* MAX7219 register addresses */ + +#define MAX7219_NOOP (0x00) /* No Operation */ +#define MAX7219_DIGIT0 (0x01) /* Digit 0 register */ +#define MAX7219_DIGIT1 (0x02) /* Digit 1 register */ +#define MAX7219_DIGIT2 (0x03) /* Digit 2 register */ +#define MAX7219_DIGIT3 (0x04) /* Digit 3 register */ +#define MAX7219_DIGIT4 (0x05) /* Digit 4 register */ +#define MAX7219_DIGIT5 (0x06) /* Digit 5 register */ +#define MAX7219_DIGIT6 (0x07) /* Digit 6 register */ +#define MAX7219_DIGIT7 (0x08) /* Digit 7 register */ +#define MAX7219_DECODE_MODE (0x09) /* Decode Moder register */ +#define MAX7219_INTENSITY (0x0a) /* Intensity register */ +#define MAX7219_SCAN_LIMIT (0x0b) /* Scan Limit register */ +#define MAX7219_SHUTDOWN (0x0c) /* Shutdown register */ +#define MAX7219_DISPLAY_TEST (0x0f) /* Display Test register */ + +/* Default register values */ + +#define DISABLE_DECODE (0x00) /* Disable 7-seg decode */ +#define DEFAULT_SCAN_LIMIT (0x07) /* Display all digits */ +#define DISPLAY_INTENSITY(n) (n & 0xf) /* low nimble defines it */ + +/* Some important "colors" */ + +#define MAX7219_BLACK 0 +#define MAX7219_WHITE 1 + +/* Only two power settings are supported: */ + +#define MAX7219_POWER_OFF 0 +#define MAX7219_POWER_ON 1 + + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: max7219_initialize + * + * Description: + * Initialize the MAX7219 device as a LCD interface. + * + * Input Parameters: + * spi - An instance of the SPI interface to use to communicate + * with the MAX7219. + * devno - Device number to identify current display. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +FAR struct lcd_dev_s *max7219_initialize(FAR struct spi_dev_s *spi, + unsigned int devno); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_SPI && CONFIG_MAX7219 */ +#endif /* __INCLUDE_NUTTX_LCD_MAX7219_H */ diff --git a/include/nuttx/mm/gran.h b/include/nuttx/mm/gran.h index c2cbd75daa8934f8c5c70dbfeaa6ff79599406c8..1bbccb29738a7c085938f4671d74697e6dfd94e4 100644 --- a/include/nuttx/mm/gran.h +++ b/include/nuttx/mm/gran.h @@ -2,7 +2,7 @@ * include/nuttx/mm/gran.h * General purpose granule memory allocator. * - * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2014, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -51,12 +51,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ /* CONFIG_GRAN - Enable granule allocator support - * CONFIG_GRAN_SINGLE - Select if there is only one instance of the - * granule allocator (i.e., gran_initialize will be called only once. - * In this case, (1) there are a few optimizations that can can be done - * and (2) the GRAN_HANDLE is not needed. * CONFIG_GRAN_INTR - Normally mutual exclusive access to granule allocator * data is assured using a semaphore. If this option is set then, instead, * mutual exclusion logic will disable interrupts. While this options is @@ -70,9 +67,19 @@ * Public Types ****************************************************************************/ -#ifndef CONFIG_GRAN_SINGLE +/* An opaque reference to an instance of a granule allocator state */ + typedef FAR void *GRAN_HANDLE; -#endif + +/* Form in which the state of the granule allocator is returned */ + +struct graninfo_s +{ + uint8_t log2gran; /* Log base 2 of the size of one granule */ + uint16_t ngranules; /* The total number of (aligned) granules in the heap */ + uint16_t nfree; /* The number of free granules */ + uint16_t mxfree; /* The longest sequence of free granules */ +}; /**************************************************************************** * Public Function Prototypes @@ -110,8 +117,7 @@ extern "C" * * GRAN_HANDLE handle = gran_initialize(g_dmaheap, DMAHEAP_SIZE, 6, 4); * - * Then the GRAN_HANDLE can be used to allocate memory (There is no - * GRAN_HANDLE if CONFIG_GRAN_SINGLE=y): + * Then the GRAN_HANDLE can be used to allocate memory: * * FAR uint8_t *dma_memory = (FAR uint8_t *)gran_alloc(handle, 47); * @@ -140,13 +146,8 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_GRAN_SINGLE -int gran_initialize(FAR void *heapstart, size_t heapsize, uint8_t log2gran, - uint8_t log2align); -#else GRAN_HANDLE gran_initialize(FAR void *heapstart, size_t heapsize, uint8_t log2gran, uint8_t log2align); -#endif /**************************************************************************** * Name: gran_release @@ -163,11 +164,7 @@ GRAN_HANDLE gran_initialize(FAR void *heapstart, size_t heapsize, * ****************************************************************************/ -#ifdef CONFIG_GRAN_SINGLE -void gran_release(void); -#else void gran_release(GRAN_HANDLE handle); -#endif /**************************************************************************** * Name: gran_reserve @@ -191,11 +188,7 @@ void gran_release(GRAN_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_GRAN_SINGLE -void gran_reserve(uintptr_t start, size_t size); -#else void gran_reserve(GRAN_HANDLE handle, uintptr_t start, size_t size); -#endif /**************************************************************************** * Name: gran_alloc @@ -212,16 +205,12 @@ void gran_reserve(GRAN_HANDLE handle, uintptr_t start, size_t size); * size - The size of the memory region to allocate. * * Returned Value: - * On success, either a non-NULL pointer to the allocated memory (if - * CONFIG_GRAN_SINGLE) or zero (if !CONFIG_GRAN_SINGLE) is returned. + * On success, a non-NULL pointer to the allocated memory is returned; + * NULL is returned on failure. * ****************************************************************************/ -#ifdef CONFIG_GRAN_SINGLE -FAR void *gran_alloc(size_t size); -#else FAR void *gran_alloc(GRAN_HANDLE handle, size_t size); -#endif /**************************************************************************** * Name: gran_free @@ -238,11 +227,25 @@ FAR void *gran_alloc(GRAN_HANDLE handle, size_t size); * ****************************************************************************/ -#ifdef CONFIG_GRAN_SINGLE -void gran_free(FAR void *memory, size_t size); -#else void gran_free(GRAN_HANDLE handle, FAR void *memory, size_t size); -#endif + +/**************************************************************************** + * Name: gran_info + * + * Description: + * Return information about the granule heap. + * + * Input Parameters: + * handle - The handle previously returned by gran_initialize + * info - Memory location to return the gran allocator info. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is return on + * any failure. + * + ****************************************************************************/ + +void gran_info(GRAN_HANDLE handle, FAR struct graninfo_s *info); #undef EXTERN #ifdef __cplusplus diff --git a/include/nuttx/mm/mm.h b/include/nuttx/mm/mm.h index 40e777907ddc38b3ff19411f9080ca564c77a115..ff71ef23086b3c9b852cf5d328032b825710f2e7 100644 --- a/include/nuttx/mm/mm.h +++ b/include/nuttx/mm/mm.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/nuttx/mm/mm.h * - * Copyright (C) 2007-2009, 2013-2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2013-2014, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -49,6 +49,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ /* If the MCU has a small (16-bit) address capability, then we will use * a smaller chunk header that contains 16-bit size/offset information. @@ -58,7 +59,7 @@ */ #ifdef CONFIG_SMALL_MEMORY - /* If the MCU has a small addressing capability, then for the smaller + /* If the MCU has a small addressing capability, then force the smaller * chunk header. */ diff --git a/include/nuttx/mm/shm.h b/include/nuttx/mm/shm.h index 35f19c50d222fcf4b798947a598e1c60b2839191..558359c93d333230a6c787f27e2fe6fba14f2e8c 100644 --- a/include/nuttx/mm/shm.h +++ b/include/nuttx/mm/shm.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/nuttx/mm/shm.h * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -65,10 +65,6 @@ # error CONFIG_GRAN must be selected with CONFIG_MM_SHM #endif -#ifdef CONFIG_GRAN_SINGLE -# error CONFIG_GRAN_SINGLE must NOT be selected with CONFIG_MM_SHM -#endif - #ifndef CONFIG_MM_PGALLOC # error CONFIG_MM_PGALLOC must be selected with CONFIG_MM_SHM #endif diff --git a/include/nuttx/mtd/mtd.h b/include/nuttx/mtd/mtd.h index 91512e7e0aa1067fb4f76e85436aaf208e610dea..e834469866aeca00392147a1414fb74f12245f0a 100644 --- a/include/nuttx/mtd/mtd.h +++ b/include/nuttx/mtd/mtd.h @@ -80,6 +80,8 @@ * 0=Use normal memory region * 1=Use alternate/extended memory * OUT: None */ +#define MTDIOC_ECCSTATUS _MTDIOC(0x0008) /* IN: Pointer to uint8_t + * OUT: ECC status */ /* Macros to hide implementation */ @@ -424,6 +426,15 @@ FAR struct mtd_dev_s *is25xp_initialize(FAR struct spi_dev_s *dev); FAR struct mtd_dev_s *m25p_initialize(FAR struct spi_dev_s *dev); +/**************************************************************************** + * Name: mx35_initialize + * + * Description: + * + ****************************************************************************/ + +FAR struct mtd_dev_s *mx35_initialize(FAR struct spi_dev_s *dev); + /**************************************************************************** * Name: rammtd_initialize * diff --git a/include/nuttx/net/ethernet.h b/include/nuttx/net/ethernet.h index dbf8b7e8e72213265bd2458e991b2d0c30ebc7c2..08f9013c7758ffea3bdacfaa89ca683565a066af 100644 --- a/include/nuttx/net/ethernet.h +++ b/include/nuttx/net/ethernet.h @@ -57,13 +57,28 @@ /* Recognized values of the type bytes in the Ethernet header */ -#define ETHTYPE_ARP 0x0806 /* Address resolution protocol */ -#define ETHTYPE_IP 0x0800 /* IP protocol */ -#define ETHTYPE_IP6 0x86dd /* IP protocol version 6 */ +#define ETHTYPE_ARP 0x0806 /* Address resolution protocol */ +#define ETHTYPE_IP 0x0800 /* IP protocol */ +#define ETHTYPE_IP6 0x86dd /* IP protocol version 6 */ + +/* Tag protocol identifier (TPID) of 0x8100 identifies the frame as an + * IEEE 802.1Q-tagged frame. This field is located at the same position as + * the Ethernet type field in untagged frames and is thus used to + * distinguish the frame from untagged frames. + */ + +#define TPID_8021QVLAN 0x8100 + +/* These are some of the types then associated with withe QVLAN tagged + * Ethernet packets. + */ -/* Size of the Ethernet header */ +#define ETHTYPE_AVBTP 0x22f0 /* Audio/Video bridging type */ -#define ETH_HDRLEN 14 /* Minimum size: 2*6 + 2 */ +/* Size of the Ethernet headers */ + +#define ETH_HDRLEN 14 /* Header size: 2*6 + 2 */ +#define ETH_8021Q_HDRLEN 18 /* Header size: 2*6 + 4 + 2 */ /**************************************************************************** * Public Types @@ -81,6 +96,22 @@ struct eth_hdr_s uint16_t type; /* Type code (2 bytes) */ }; +/* IEEE 802.1Q adds a 32-bit field between the source MAC address and the + * type fields of the original Ethernet header. Two bytes are used for the + * tag protocol identifier (TPID), the other two bytes for tag control + * information TCI). The TCI field is further divided into PCP, DEI, and + * VID. + */ + +struct eth_8021qhdr_s +{ + uint8_t dest[6]; /* Ethernet destination address (6 bytes) */ + uint8_t src[6]; /* Ethernet source address (6 bytes) */ + uint16_t tpid; /* TCI: Tag protocol identifier (2 bytes) */ + uint16_t tci; /* TCI: Tag control information: PCP, DEI, VID (2 bytes) */ + uint16_t type; /* Type code (2 bytes) */ +}; + /**************************************************************************** * Public Data ****************************************************************************/ diff --git a/include/nuttx/net/ip.h b/include/nuttx/net/ip.h index 3a5c14212b7da3d96217117b364a9a4ee8977a83..2cdfeeb84b694c963d0d02c76d53e7a7879be2a8 100644 --- a/include/nuttx/net/ip.h +++ b/include/nuttx/net/ip.h @@ -508,6 +508,46 @@ bool net_ipv6addr_maskcmp(const net_ipv6addr_t addr1, const net_ipv6addr_t mask); #endif +/**************************************************************************** + * Name: net_ipv4addr_broadcast + * + * Description: + * Mask out the network part of an IP address, given the address and + * the netmask. + * + * Example: + * + * in_addr_t ipaddr; + * in_addr_t netmask; + * bool isbroadcast; + * + * net_ipaddr(&netmask, 255,255,255,0); + * net_ipaddr(&ipaddr, 192,16,1,255); + * isbroadcast = net_ipv4addr_broadcast(ipaddr, netmask); + * + * Will return isboadcast == true. + * + * net_ipaddr(&ipaddr, 192,16,1,2); + * isbroadcast = net_ipv4addr_broadcast(ipaddr, netmask); + * + * Will return isboadcast == false. + * + * NOTES: + * 1. This function does not check for the broadcast address + * 255.255.255.255. That must be performed as a seperate check. + * 2. You must also separately check if the ipaddress lies on the sub-net + * using, perhaps, net_ipv4addr_maskcmp(). + * + * Input Parameters: + * addr - The IPv4 address to check + * mask - The network mask + * + ****************************************************************************/ + +#define net_ipv4addr_broadcast(addr, mask) \ + (((in_addr_t)(addr) & ~(in_addr_t)(mask)) == \ + ((in_addr_t)(0xffffffff) & ~(in_addr_t)(mask))) + /**************************************************************************** * Name: net_ipv6addr_prefixcmp * @@ -587,36 +627,6 @@ bool net_ipv6addr_maskcmp(const net_ipv6addr_t addr1, #define net_is_addr_linklocal(a) ((a)[0] == HTONS(0xfe80)) -/**************************************************************************** - * Name: net_ipaddr_mask - * - * Description: - * Mask out the network part of an IP address, given the address and - * the netmask. - * - * Example: - * - * in_addr_t ipaddr1, ipaddr2, netmask; - * - * net_ipaddr(&ipaddr1, 192,16,1,2); - * net_ipaddr(&netmask, 255,255,255,0); - * net_ipaddr_mask(&ipaddr2, &ipaddr1, &netmask); - * - * In the example above, the variable "ipaddr2" will contain the IP - * address 192.168.1.0. - * - * Input Parameters: - * dest Where the result is to be placed. - * src The IP address. - * mask The netmask. - * - ****************************************************************************/ - -#define net_ipaddr_mask(dest, src, mask) \ - do { \ - (in_addr_t)(dest) = (in_addr_t)(src) & (in_addr_t)(mask); \ - } while (0) - #undef EXTERN #ifdef __cplusplus } diff --git a/include/nuttx/net/mii.h b/include/nuttx/net/mii.h index d595202738b9d6a38ddbd170474d44d1fb824c38..facd4c2f9d593591e88e7f0e01b305e4671b32c1 100644 --- a/include/nuttx/net/mii.h +++ b/include/nuttx/net/mii.h @@ -351,6 +351,24 @@ #define MII_PHYID1_LAN8720 0x0007 /* ID1 value for LAN8720 */ #define MII_PHYID2_LAN8720 0xc0f1 /* ID2 value for LAN8720 */ +/* SMSC LAN8720 SPSCR register bits */ + +#define MII_LAN8720_SPSCR_SCRMDIS (1 << 0) /* Bit 0: Scramble disable */ + /* Bit 1: Reserved */ +#define MII_LAN8720_SPSCR_MODE_SHIFT (2) /* Bits 2-4: Speed/duplex mode */ +#define MII_LAN8720_SPSCR_MODE_MASK (7 << MII_LAN8720_SPSCR_MODE_SHIFT) +# define MII_LAN8720_SPSCR_10MBPS (1 << 2) /* Bit 2: 10MBPS speed */ +# define MII_LAN8720_SPSCR_100MBPS (1 << 3) /* Bit 3: 100MBPS speed */ +# define MII_LAN8720_SPSCR_DUPLEX (1 << 4) /* Bit 4: Full duplex mode */ + /* Bit 5: Reserved */ +#define MII_LAN8720_SPSCR_ENAB4B5B (1 << 6) /* Bit 6: Enable 4B5B */ +#define MII_LAN8720_SPSCR_GPIO0 (1 << 7) /* Bit 7: GPIO0 */ +#define MII_LAN8720_SPSCR_GPIO1 (1 << 8) /* Bit 8: GPIO1 */ +#define MII_LAN8720_SPSCR_GPIO2 (1 << 9) /* Bit 9: GPIO2 */ + /* Bit 10-11: Reserved */ +#define MII_LAN8720_SPSCR_ANEGDONE (1 << 12) /* Bit 12: Autonegotiation complete */ + /* Bits 13-15: Reserved */ + /* SMSC LAN8740 MII ID1/2 register bits */ #define MII_PHYID1_LAN8740 0x0007 /* ID1 value for LAN8740 */ diff --git a/include/nuttx/net/rfc6775.h b/include/nuttx/net/rfc6775.h index cdfee0d6eec0188a0e4e709428b57e1739ba39b1..56c34fba50be1915359212d1c0c395bce8c036af 100644 --- a/include/nuttx/net/rfc6775.h +++ b/include/nuttx/net/rfc6775.h @@ -86,7 +86,7 @@ * Public Types ****************************************************************************/ -/* Table 1. alues for status field */ +/* Table 1. Values for status field */ enum sixlowpan_status_e { diff --git a/include/nuttx/nx/nx.h b/include/nuttx/nx/nx.h index 912f92b72361cce18bd6766bcb69c37d632fe3b1..aec345ac603a1f254ff003ec6f4d6945913aa8c4 100644 --- a/include/nuttx/nx/nx.h +++ b/include/nuttx/nx/nx.h @@ -843,13 +843,17 @@ int nx_bitmap(NXWINDOW hwnd, FAR const struct nxgl_rect_s *dest, * - When VNC is enabled. This is case, this callout is necessary to * update the remote frame buffer to match the local framebuffer. * - * When this feature is enabled, some external logic must provide this - * interface. This is the function that will handle the notification. It - * receives the rectangular region that was updated on the provided plane. + * When this feature is enabled, some external logic must provide this + * interface. This is the function that will handle the notification. It + * receives the rectangular region that was updated on the provided plane. + * + * NOTE: This function is also required for use with the LCD framebuffer + * driver front end when CONFIG_LCD_UPDATE=y, although that use does not + * depend on CONFIG_NX (and this function seems misnamed in that case). * ****************************************************************************/ -#ifdef CONFIG_NX_UPDATE +#if defined(CONFIG_NX_UPDATE) || defined(CONFIG_LCD_UPDATE) void nx_notify_rectangle(FAR NX_PLANEINFOTYPE *pinfo, FAR const struct nxgl_rect_s *rect); #endif diff --git a/include/nuttx/pgalloc.h b/include/nuttx/pgalloc.h index c4b6ecab0a2f0b46a7808e096247d2615064f387..30d57c5d3410d9ad80c65925dff2b7c4903d1a89 100644 --- a/include/nuttx/pgalloc.h +++ b/include/nuttx/pgalloc.h @@ -2,7 +2,7 @@ * include/nuttx/pgalloc.h * Page memory allocator. * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -95,6 +95,17 @@ * Public Types ****************************************************************************/ +/* Form in which the state of the granule allocator is returned, The size of + * each page is MM_PGSIZE/MM_PGSHIFT + */ + +struct pginfo_s +{ + uint16_t ntotal; /* The total number of pages */ + uint16_t nfree; /* The number of free pages */ + uint16_t mxfree; /* The longest sequence of free pages */ +}; + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -186,6 +197,24 @@ uintptr_t mm_pgalloc(unsigned int npages); void mm_pgfree(uintptr_t paddr, unsigned int npages); +/**************************************************************************** + * Name: mm_pginfo + * + * Description: + * Return information about the page allocator. + * + * Input Parameters: + * handle - The handle previously returned by gran_initialize + * info - Memory location to return the gran allocator info. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is return on + * any failure. + * + ****************************************************************************/ + +void mm_pginfo(FAR struct pginfo_s *info); + #undef EXTERN #ifdef __cplusplus } diff --git a/include/nuttx/power/battery_gauge.h b/include/nuttx/power/battery_gauge.h index e97f8a3d74c2b54bfbffa5e09d90321791acbf3c..24a8eb5055d99384c8c268c076c82e3c562401a7 100644 --- a/include/nuttx/power/battery_gauge.h +++ b/include/nuttx/power/battery_gauge.h @@ -200,7 +200,7 @@ int battery_gauge_register(FAR const char *devpath, #if defined(CONFIG_I2C) && defined(CONFIG_I2C_MAX1704X) struct i2c_master_s; /* Forward reference */ -FAR struct battery_gauge_dev_s *max1704x_initialize(FAR struct i2c_master_s *i2c +FAR struct battery_gauge_dev_s *max1704x_initialize(FAR struct i2c_master_s *i2c, uint8_t addr, uint32_t frequency); #endif diff --git a/include/nuttx/power/battery_ioctl.h b/include/nuttx/power/battery_ioctl.h index 3256f1c87f63d833045687fd666fc0c7994ef9b5..bf61c093c3272eea5697e82f354105b63811913d 100644 --- a/include/nuttx/power/battery_ioctl.h +++ b/include/nuttx/power/battery_ioctl.h @@ -85,6 +85,7 @@ enum batio_operate_e BATIO_OPRTN_EN_TERM, BATIO_OPRTN_HIZ, BATIO_OPRTN_SYSOFF, + BATIO_OPRTN_SYSON, BATIO_OPRTN_RESET, BATIO_OPRTN_WDOG, BATIO_OPRTN_END diff --git a/include/nuttx/power/bq2429x.h b/include/nuttx/power/bq2429x.h index e858ea93259a71c1b7fd01687880b3ad5df1cd08..a84b31636e14f0066be1bfd683e6dcb5bccd9373 100644 --- a/include/nuttx/power/bq2429x.h +++ b/include/nuttx/power/bq2429x.h @@ -110,7 +110,7 @@ #define BQ2429XR2_ICHG_MASK (0x3f << BQ2429XR2_ICHG_SHIFT) #define BQ2429XR2_BCOLD (1 << 1) /* Boost Mode temperature threshold config for boost disable 0=76% 1=79% */ -#define BQ2429XR2_FORCE_20PCT (1 << 0) /* Charge Configuration Threshold 0=Fast 1=less */ +#define BQ2429XR2_FORCE_20PCT (1 << 0) /* Charge type 0=Fast (default), 1=Trickle charge with 20% current */ /* REG03 Pre-charge Termination Control Register */ diff --git a/include/nuttx/power/smps.h b/include/nuttx/power/smps.h index 52fe6c5276edc57160e5152604fb613060e11eaa..3f54a51b0ae3086493c52ecdeb9307039ab44e26 100644 --- a/include/nuttx/power/smps.h +++ b/include/nuttx/power/smps.h @@ -121,15 +121,15 @@ struct smps_feedback_s #ifdef CONFIG_SMPS_HAVE_OUTPUT_VOLTAGE float v_out; /* Output Voltage */ #endif -#ifdef CONFIG_SMPS_HAVE_INPUT_CURRENT - float i_in; /* Input Current */ -#endif #ifdef CONFIG_SMPS_HAVE_INPUT_VOLTAGE float v_in; /* Input Voltage */ #endif #ifdef CONFIG_SMPS_HAVE_OUTPUT_CURRENT float i_out; /* Output Current */ #endif +#ifdef CONFIG_SMPS_HAVE_INPUT_CURRENT + float i_in; /* Input Current */ +#endif #ifdef CONFIG_SMPS_HAVE_INPUT_POWER float p_in; /* Input Power */ #endif diff --git a/include/nuttx/progmem.h b/include/nuttx/progmem.h index a5ed707a6134065eb296520e4d63cf7855ca828f..367f66af8ce1e618c52d901ab237934d6ac369f8 100644 --- a/include/nuttx/progmem.h +++ b/include/nuttx/progmem.h @@ -45,6 +45,8 @@ #include +#ifdef CONFIG_ARCH_HAVE_PROGMEM + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -207,4 +209,5 @@ ssize_t up_progmem_write(size_t addr, FAR const void *buf, size_t count); } #endif +#endif /* CONFIG_ARCH_HAVE_PROGMEM */ #endif /* __INCLUDE_NUTTX_PROGMEM_H */ diff --git a/include/nuttx/sdio.h b/include/nuttx/sdio.h index eb7498285a07e511221ae59d5537bfd22e1cfd8b..16ed1de685a57d43318358070758f3ecdbda49ee 100644 --- a/include/nuttx/sdio.h +++ b/include/nuttx/sdio.h @@ -84,7 +84,7 @@ /* Media events are used for enable/disable registered event callbacks */ -#define SDIOMEDIA_EJECTED (1 << 0) /* Bit 0: Mmedia removed */ +#define SDIOMEDIA_EJECTED (1 << 0) /* Bit 0: Media removed */ #define SDIOMEDIA_INSERTED (1 << 1) /* Bit 1: Media inserted */ /* Commands are bit-encoded to provide as much information to the SDIO driver as diff --git a/include/nuttx/timers/rtc.h b/include/nuttx/timers/rtc.h index b5c1a6bf4625d6fb79b0c3af2aab00023af76ce0..627ed904d5c2e7302da0a8ae4bdf885847616ff8 100644 --- a/include/nuttx/timers/rtc.h +++ b/include/nuttx/timers/rtc.h @@ -7,7 +7,7 @@ * With extensions, modifications by: * * Copyright (C) 2011-2012, 2015-2016 Gregory Nutt. All rights reserved. - * Author: Gregroy Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/include/nuttx/video/fb.h b/include/nuttx/video/fb.h index 101901b954e14e09d2d388efc36e086a7f5c90d5..4d6c7f1d49a1228c64cd53d6ba01a4dd232dbf4c 100644 --- a/include/nuttx/video/fb.h +++ b/include/nuttx/video/fb.h @@ -1,7 +1,8 @@ /**************************************************************************** * include/nuttx/video/fb.h * - * Copyright (C) 2008-2011, 2013, 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2008-2011, 2013, 2016-2017 Gregory Nutt. All rights + * reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -55,9 +56,10 @@ /* Monochrome Formats *******************************************************/ #define FB_FMT_Y1 0 /* BPP=1, monochrome */ -#define FB_FMT_Y4 1 /* BPP=4, 4-bit uncompressed greyscale */ -#define FB_FMT_Y8 2 /* BPP=8, 8-bit uncompressed greyscale */ -#define FB_FMT_Y16 3 /* BPP=16, 16-bit uncompressed greyscale */ +#define FB_FMT_Y2 1 /* BPP=2, 2-bit uncompressed greyscale */ +#define FB_FMT_Y4 2 /* BPP=4, 4-bit uncompressed greyscale */ +#define FB_FMT_Y8 3 /* BPP=8, 8-bit uncompressed greyscale */ +#define FB_FMT_Y16 4 /* BPP=16, 16-bit uncompressed greyscale */ #define FB_FMT_GREY FB_FMT_Y8 /* BPP=8 */ #define FB_FMT_Y800 FB_FMT_Y8 /* BPP=8 */ @@ -68,115 +70,115 @@ /* Standard RGB */ #define FB_FMT_RGB1 FB_FMT_Y1 /* BPP=1 */ -#define FB_FMT_RGB4 4 /* BPP=4 */ -#define FB_FMT_RGB8 5 /* BPP=8 RGB palette index */ -#define FB_FMT_RGB8_222 6 /* BPP=8 R=2, G=2, B=2 */ -#define FB_FMT_RGB8_332 7 /* BPP=8 R=3, G=3, B=2 */ -#define FB_FMT_RGB12_444 8 /* BPP=12 R=4, G=4, B=4 */ -#define FB_FMT_RGB16_555 9 /* BPP=16 R=5, G=5, B=5 (1 unused bit) */ -#define FB_FMT_RGB16_565 10 /* BPP=16 R=6, G=6, B=5 */ -#define FB_FMT_RGB24 11 /* BPP=24 */ -#define FB_FMT_RGB32 12 /* BPP=32 */ +#define FB_FMT_RGB4 5 /* BPP=4 */ +#define FB_FMT_RGB8 6 /* BPP=8 RGB palette index */ +#define FB_FMT_RGB8_222 7 /* BPP=8 R=2, G=2, B=2 */ +#define FB_FMT_RGB8_332 8 /* BPP=8 R=3, G=3, B=2 */ +#define FB_FMT_RGB12_444 9 /* BPP=12 R=4, G=4, B=4 */ +#define FB_FMT_RGB16_555 10 /* BPP=16 R=5, G=5, B=5 (1 unused bit) */ +#define FB_FMT_RGB16_565 11 /* BPP=16 R=6, G=6, B=5 */ +#define FB_FMT_RGB24 12 /* BPP=24 */ +#define FB_FMT_RGB32 13 /* BPP=32 */ /* Run length encoded RGB */ -#define FB_FMT_RGBRLE4 13 /* BPP=4 */ -#define FB_FMT_RGBRLE8 14 /* BPP=8 */ +#define FB_FMT_RGBRLE4 14 /* BPP=4 */ +#define FB_FMT_RGBRLE8 15 /* BPP=8 */ /* Raw RGB */ -#define FB_FMT_RGBRAW 15 /* BPP=? */ +#define FB_FMT_RGBRAW 16 /* BPP=? */ /* Raw RGB with arbitrary sample packing within a pixel. Packing and precision * of R, G and B components is determined by bit masks for each. */ -#define FB_FMT_RGBBTFLD16 16 /* BPP=16 */ -#define FB_FMT_RGBBTFLD24 17 /* BPP=24 */ -#define FB_FMT_RGBBTFLD32 18 /* BPP=32 */ -#define FB_FMT_RGBA16 19 /* BPP=16 Raw RGB with alpha */ -#define FB_FMT_RGBA32 20 /* BPP=32 Raw RGB with alpha */ +#define FB_FMT_RGBBTFLD16 17 /* BPP=16 */ +#define FB_FMT_RGBBTFLD24 18 /* BPP=24 */ +#define FB_FMT_RGBBTFLD32 19 /* BPP=32 */ +#define FB_FMT_RGBA16 20 /* BPP=16 Raw RGB with alpha */ +#define FB_FMT_RGBA32 21 /* BPP=32 Raw RGB with alpha */ /* Raw RGB with a transparency field. Layout is as for standard RGB at 16 and * 32 bits per pixel but the msb in each pixel indicates whether the pixel is * transparent or not. */ -#define FB_FMT_RGBT16 21 /* BPP=16 */ -#define FB_FMT_RGBT32 22 /* BPP=32 */ +#define FB_FMT_RGBT16 22 /* BPP=16 */ +#define FB_FMT_RGBT32 23 /* BPP=32 */ #define FB_ISRGB(f) ((f) >= FB_FMT_RGB1) && (f) <= FB_FMT_RGBT32) /* Packed YUV Formats *******************************************************/ -#define FB_FMT_AYUV 23 /* BPP=32 Combined YUV and alpha */ -#define FB_FMT_CLJR 24 /* BPP=8 4 pixels packed into a uint32_t. +#define FB_FMT_AYUV 24 /* BPP=32 Combined YUV and alpha */ +#define FB_FMT_CLJR 25 /* BPP=8 4 pixels packed into a uint32_t. * YUV 4:1:1 with l< 8 bits * per YUV sample */ -#define FB_FMT_CYUV 25 /* BPP=16 UYVY except that height is +#define FB_FMT_CYUV 26 /* BPP=16 UYVY except that height is * reversed */ -#define FB_FMT_IRAW 26 /* BPP=? Intel uncompressed YUV */ -#define FB_FMT_IUYV 27 /* BPP=16 Interlaced UYVY (line order +#define FB_FMT_IRAW 27 /* BPP=? Intel uncompressed YUV */ +#define FB_FMT_IUYV 28 /* BPP=16 Interlaced UYVY (line order * 0,2,4,.., 1,3,5...) */ -#define FB_FMT_IY41 28 /* BPP=12 Interlaced Y41P (line order +#define FB_FMT_IY41 29 /* BPP=12 Interlaced Y41P (line order * 0,2,4,.., 1,3,5...) */ -#define FB_FMT_IYU2 29 /* BPP=24 */ -#define FB_FMT_HDYC 30 /* BPP=16 UYVY except uses the BT709 +#define FB_FMT_IYU2 30 /* BPP=24 */ +#define FB_FMT_HDYC 31 /* BPP=16 UYVY except uses the BT709 * color space */ -#define FB_FMT_UYVP 31 /* BPP=24? YCbCr 4:2:2, 10-bits per +#define FB_FMT_UYVP 32 /* BPP=24? YCbCr 4:2:2, 10-bits per * component in U0Y0V0Y1 order */ -#define FB_FMT_UYVY 32 /* BPP=16 YUV 4:2:2 */ +#define FB_FMT_UYVY 33 /* BPP=16 YUV 4:2:2 */ #define FB_FMT_UYNV FB_FMT_UYVY /* BPP=16 */ #define FB_FMT_Y422 FB_FMT_UYVY /* BPP=16 */ -#define FB_FMT_V210 33 /* BPP=32 10-bit 4:2:2 YCrCb */ -#define FB_FMT_V422 34 /* BPP=16 Upside down version of UYVY */ -#define FB_FMT_V655 35 /* BPP=16? 16-bit YUV 4:2:2 */ -#define FB_FMT_VYUY 36 /* BPP=? ATI Packed YUV Data */ -#define FB_FMT_YUYV 37 /* BPP=16 YUV 4:2:2 */ +#define FB_FMT_V210 34 /* BPP=32 10-bit 4:2:2 YCrCb */ +#define FB_FMT_V422 35 /* BPP=16 Upside down version of UYVY */ +#define FB_FMT_V655 36 /* BPP=16? 16-bit YUV 4:2:2 */ +#define FB_FMT_VYUY 37 /* BPP=? ATI Packed YUV Data */ +#define FB_FMT_YUYV 38 /* BPP=16 YUV 4:2:2 */ #define FB_FMT_YUY2 FB_FMT_YUYV /* BPP=16 YUV 4:2:2 */ #define FB_FMT_YUNV FB_FMT_YUYV /* BPP=16 YUV 4:2:2 */ -#define FB_FMT_YVYU 38 /* BPP=16 YUV 4:2:2 */ -#define FB_FMT_Y41P 39 /* BPP=12 YUV 4:1:1 */ -#define FB_FMT_Y411 40 /* BPP=12 YUV 4:1:1 */ -#define FB_FMT_Y211 41 /* BPP=8 */ -#define FB_FMT_Y41T 42 /* BPP=12 Y41P LSB for transparency */ -#define FB_FMT_Y42T 43 /* BPP=16 UYVY LSB for transparency */ -#define FB_FMT_YUVP 44 /* BPP=24? YCbCr 4:2:2 Y0U0Y1V0 order */ +#define FB_FMT_YVYU 39 /* BPP=16 YUV 4:2:2 */ +#define FB_FMT_Y41P 40 /* BPP=12 YUV 4:1:1 */ +#define FB_FMT_Y411 41 /* BPP=12 YUV 4:1:1 */ +#define FB_FMT_Y211 42 /* BPP=8 */ +#define FB_FMT_Y41T 43 /* BPP=12 Y41P LSB for transparency */ +#define FB_FMT_Y42T 44 /* BPP=16 UYVY LSB for transparency */ +#define FB_FMT_YUVP 45 /* BPP=24? YCbCr 4:2:2 Y0U0Y1V0 order */ #define FB_ISYUVPACKED(f) ((f) >= FB_FMT_AYUV) && (f) <= FB_FMT_YUVP) /* Packed Planar YUV Formats ************************************************/ -#define FB_FMT_YVU9 45 /* BPP=9 8-bit Y followed by 8-bit +#define FB_FMT_YVU9 46 /* BPP=9 8-bit Y followed by 8-bit * 4x4 VU */ -#define FB_FMT_YUV9 46 /* BPP=9? */ -#define FB_FMT_IF09 47 /* BPP=9.5 YVU9 + 4x4 plane of delta +#define FB_FMT_YUV9 47 /* BPP=9? */ +#define FB_FMT_IF09 48 /* BPP=9.5 YVU9 + 4x4 plane of delta * relative to tframe. */ -#define FB_FMT_YV16 48 /* BPP=16 8-bit Y followed by 8-bit +#define FB_FMT_YV16 49 /* BPP=16 8-bit Y followed by 8-bit * 2x1 VU */ -#define FB_FMT_YV12 49 /* BPP=12 8-bit Y followed by 8-bit +#define FB_FMT_YV12 50 /* BPP=12 8-bit Y followed by 8-bit * 2x2 VU */ -#define FB_FMT_I420 50 /* BPP=12 8-bit Y followed by 8-bit +#define FB_FMT_I420 51 /* BPP=12 8-bit Y followed by 8-bit * 2x2 UV */ #define FB_FMT_IYUV FB_FMT_I420 /* BPP=12 */ -#define FB_FMT_NV12 51 /* BPP=12 8-bit Y followed by an +#define FB_FMT_NV12 52 /* BPP=12 8-bit Y followed by an * interleaved 2x2 UV */ -#define FB_FMT_NV21 52 /* BPP=12 NV12 with UV reversed */ -#define FB_FMT_IMC1 53 /* BPP=12 YV12 except UV planes same +#define FB_FMT_NV21 53 /* BPP=12 NV12 with UV reversed */ +#define FB_FMT_IMC1 54 /* BPP=12 YV12 except UV planes same * stride as Y */ -#define FB_FMT_IMC2 54 /* BPP=12 IMC1 except UV lines +#define FB_FMT_IMC2 55 /* BPP=12 IMC1 except UV lines * interleaved at half stride * boundaries */ -#define FB_FMT_IMC3 55 /* BPP=12 As IMC1 except that UV +#define FB_FMT_IMC3 56 /* BPP=12 As IMC1 except that UV * swapped */ -#define FB_FMT_IMC4 56 /* BPP=12 As IMC2 except that UV +#define FB_FMT_IMC4 57 /* BPP=12 As IMC2 except that UV * swapped */ -#define FB_FMT_CLPL 57 /* BPP=12 YV12 but including a level +#define FB_FMT_CLPL 58 /* BPP=12 YV12 but including a level * of indirection. */ -#define FB_FMT_Y41B 58 /* BPP=12? 4:1:1 planar. */ -#define FB_FMT_Y42B 59 /* BPP=16? YUV 4:2:2 planar. */ -#define FB_FMT_CXY1 60 /* BPP=12 */ -#define FB_FMT_CXY2 61 /* BPP=16 */ +#define FB_FMT_Y41B 59 /* BPP=12? 4:1:1 planar. */ +#define FB_FMT_Y42B 60 /* BPP=16? YUV 4:2:2 planar. */ +#define FB_FMT_CXY1 61 /* BPP=12 */ +#define FB_FMT_CXY2 62 /* BPP=16 */ #define FB_ISYUVPLANAR(f) (((f) >= FB_FMT_AYUV) && (f) <= FB_FMT_YUVP) #define FB_ISYUV(f) (FB_ISYUVPACKED(f) || FB_ISYUVPLANAR(f)) @@ -196,24 +198,34 @@ /* ioctls */ #define FBIOGET_VIDEOINFO _FBIOC(0x0001) /* Get color plane info */ - /* Argument: writable struct fb_videoinfo_s */ + /* Argument: writable struct + * fb_videoinfo_s */ #define FBIOGET_PLANEINFO _FBIOC(0x0002) /* Get video plane info */ - /* Argument: writable struct fb_planeinfo_s */ + /* Argument: writable struct + * fb_planeinfo_s */ #ifdef CONFIG_FB_CMAP # define FBIOGET_CMAP _FBIOC(0x0003) /* Get RGB color mapping */ - /* Argument: writable struct fb_cmap_s */ + /* Argument: writable struct + * fb_cmap_s */ # define FBIOPUT_CMAP _FBIOC(0x0004) /* Put RGB color mapping */ - /* Argument: read-only struct fb_cmap_s */ + /* Argument: read-only struct + * fb_cmap_s */ #endif + #ifdef CONFIG_FB_HWCURSOR # define FBIOGET_CURSOR _FBIOC(0x0005) /* Get cursor attributes */ - /* Argument: writable struct fb_cursorattrib_s */ + /* Argument: writable struct + * fb_cursorattrib_s */ # define FBIOPUT_CURSOR _FBIOC(0x0006) /* Set cursor attributes */ - /* Argument: read-only struct fb_setcursor_s */ + /* Argument: read-only struct + * fb_setcursor_s */ #endif -#ifdef CONFIG_NX_UPDATE -# define FBIO_UPDATE _FBIOC(0x0007) /* Update a rectangular region in the framebuffer */ - /* Argument: read-only struct nxgl_rect_s */ + +#ifdef CONFIG_LCD_UPDATE +# define FBIO_UPDATE _FBIOC(0x0007) /* Update a rectangular region in + * the framebuffer + * Argument: read-only struct + * nxgl_rect_s */ #endif /**************************************************************************** @@ -454,7 +466,7 @@ void up_fbuninitialize(int display); * Register the framebuffer character device at /dev/fbN where N is the * display number if the devices supports only a single plane. If the * hardware supports multiple color planes, then the device will be - * registered at /dev/fbN-M where N is the again display number but M + * registered at /dev/fbN.M where N is the again display number but M * is the display plane. * * Input Parameters: diff --git a/include/nuttx/wireless/ieee802154/ieee802154_device.h b/include/nuttx/wireless/ieee802154/ieee802154_device.h index f09e7075d17959b4fc6f71476213e35ab19b4db8..acbf8fe2e619a8d83d6e84f9b12c5344c3f1e08e 100644 --- a/include/nuttx/wireless/ieee802154/ieee802154_device.h +++ b/include/nuttx/wireless/ieee802154/ieee802154_device.h @@ -66,8 +66,15 @@ struct mac802154dev_txframe_s struct mac802154dev_rxframe_s { struct ieee802154_data_ind_s meta; - uint8_t payload[IEEE802154_MAX_MAC_PAYLOAD_SIZE]; - uint16_t length; + uint8_t payload[IEEE802154_MAX_PHY_PACKET_SIZE]; + uint8_t length; + + /* In promiscous mode, the entire frame is passed to the application inside + * the payload field. The offset field is used to specify the start of the + * actual payload, skipping the 802.15.4 header. + */ + + uint8_t offset; }; #endif /* CONFIG_WIRELESS_IEEE802154 */ diff --git a/include/nuttx/wireless/ieee802154/ieee802154_mac.h b/include/nuttx/wireless/ieee802154/ieee802154_mac.h index 87a387c3948ecc8224f61feb95d3e930496cf2a8..10647638485c002b28141166955db258df7b7038 100644 --- a/include/nuttx/wireless/ieee802154/ieee802154_mac.h +++ b/include/nuttx/wireless/ieee802154/ieee802154_mac.h @@ -756,6 +756,10 @@ struct ieee802154_frame_meta_s struct ieee802154_data_conf_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + uint8_t handle; /* Handle assoc. with MSDU */ /* The time, in symbols, at which the data were transmitted */ @@ -806,7 +810,9 @@ struct ieee802154_data_conf_s struct ieee802154_data_ind_s { - FAR struct ieee802154_data_ind_s *flink; + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; FAR struct iob_s *frame; @@ -883,6 +889,10 @@ struct ieee802154_data_ind_s struct ieee802154_purge_req_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + uint8_t msdu_handle; /* Handle assoc. with MSDU */ }; @@ -896,6 +906,10 @@ struct ieee802154_purge_req_s struct ieee802154_assoc_req_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + uint8_t chan; /* Channel number to attempt association */ uint8_t chpage; /* Channel page to attempt association */ @@ -954,6 +968,10 @@ struct ieee802154_assoc_req_s struct ieee802154_assoc_ind_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + /* Address of device requesting association. Always in extended mode */ uint8_t devaddr[IEEE802154_EADDRSIZE]; @@ -979,6 +997,10 @@ struct ieee802154_assoc_ind_s struct ieee802154_assoc_resp_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + /* Address of device requesting association. Always in extended mode */ uint8_t devaddr[IEEE802154_EADDRSIZE]; @@ -1009,6 +1031,10 @@ struct ieee802154_assoc_resp_s struct ieee802154_assoc_conf_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + /* Associated device address ALWAYS passed in short address mode. The * address will be IEEE802154_SADDR_UNSPEC if association was * unsuccessful. @@ -1039,6 +1065,10 @@ struct ieee802154_assoc_conf_s struct ieee802154_disassoc_req_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + /* Address of device to send disassociation notification */ struct ieee802154_addr_s dev_addr; @@ -1066,6 +1096,10 @@ struct ieee802154_disassoc_req_s struct ieee802154_disassoc_ind_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + /* Address of device requesting disassociation. Always extended mode */ struct ieee802154_addr_s dev_addr; @@ -1091,6 +1125,10 @@ struct ieee802154_disassoc_ind_s struct ieee802154_disassoc_conf_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + /* Status of the disassociation attempt */ enum ieee802154_status_e status; @@ -1114,6 +1152,10 @@ struct ieee802154_disassoc_conf_s struct ieee802154_beacon_ind_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + uint8_t bsn; /* Beacon sequence number */ /* PAN descriptor for the received beacon */ @@ -1137,6 +1179,10 @@ struct ieee802154_beacon_ind_s struct ieee802154_commstatus_ind_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + struct ieee802154_addr_s src_addr; struct ieee802154_addr_s dest_addr; enum ieee802154_status_e status; @@ -1160,6 +1206,10 @@ struct ieee802154_commstatus_ind_s struct ieee802154_gts_req_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + struct ieee802154_gts_info_s gts_info; #ifdef CONFIG_IEEE802154_SECURITY @@ -1180,6 +1230,10 @@ struct ieee802154_gts_req_s struct ieee802154_gts_conf_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + struct ieee802154_gts_info_s gts_info; enum ieee802154_status_e status; }; @@ -1195,6 +1249,10 @@ struct ieee802154_gts_conf_s struct ieee802154_gts_ind_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + uint16_t dev_addr; struct ieee802154_gts_info_s gts_info; @@ -1216,6 +1274,10 @@ struct ieee802154_gts_ind_s struct ieee802154_orphan_ind_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + uint8_t orphan_addr[8]; #ifdef CONFIG_IEEE802154_SECURITY @@ -1236,6 +1298,10 @@ struct ieee802154_orphan_ind_s struct ieee802154_orphan_resp_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + uint8_t orphan_addr[8]; #ifdef CONFIG_IEEE802154_SECURITY @@ -1256,6 +1322,10 @@ struct ieee802154_orphan_resp_s struct ieee802154_reset_req_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + bool resetattr; }; @@ -1270,6 +1340,10 @@ struct ieee802154_reset_req_s struct ieee802154_rxenable_req_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + /* Number of symbols measured from the start of the superframe before the * receiver is to be enabled or disabled. */ @@ -1295,6 +1369,10 @@ struct ieee802154_rxenable_req_s struct ieee802154_rxenable_conf_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + enum ieee802154_status_e status; }; @@ -1308,6 +1386,10 @@ struct ieee802154_rxenable_conf_s struct ieee802154_scan_req_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + enum ieee802154_scantype_e type; uint8_t duration; uint8_t chpage; @@ -1331,6 +1413,10 @@ struct ieee802154_scan_req_s struct ieee802154_scan_conf_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + enum ieee802154_status_e status; enum ieee802154_scantype_e type; uint8_t chpage; @@ -1351,6 +1437,10 @@ struct ieee802154_scan_conf_s struct ieee802154_get_req_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + enum ieee802154_attr_e attr; union ieee802154_attr_u attrval; }; @@ -1371,6 +1461,10 @@ struct ieee802154_get_req_s struct ieee802154_set_req_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + enum ieee802154_attr_e attr; union ieee802154_attr_u attrval; }; @@ -1388,6 +1482,10 @@ struct ieee802154_set_req_s struct ieee802154_start_req_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + uint8_t panid[IEEE802154_PANIDSIZE]; uint8_t chan; uint8_t chpage; @@ -1420,6 +1518,10 @@ struct ieee802154_start_req_s struct ieee802154_start_conf_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + enum ieee802154_status_e status; }; @@ -1434,6 +1536,10 @@ struct ieee802154_start_conf_s struct ieee802154_sync_req_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + uint8_t ch_num; uint8_t ch_page; bool track_beacon; @@ -1449,6 +1555,10 @@ struct ieee802154_sync_req_s struct ieee802154_syncloss_ind_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + enum ieee802154_status_e loss_reason; uint16_t pan_id; uint8_t ch_num; @@ -1471,6 +1581,10 @@ struct ieee802154_syncloss_ind_s struct ieee802154_poll_req_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + struct ieee802154_addr_s coordaddr; #ifdef CONFIG_IEEE802154_SECURITY @@ -1490,44 +1604,50 @@ struct ieee802154_poll_req_s struct ieee802154_poll_conf_s { + /* Each primitive must have a forward-link to a primitive to support lists */ + + FAR struct ieee802154_primitive_s *flink; + enum ieee802154_status_e status; }; -/* MAC Service Notifications */ +/* MAC Service Primitives */ -enum ieee802154_notify_e +enum ieee802154_primitive_e { /* MCPS Notifications */ - IEEE802154_NOTIFY_CONF_DATA = 0x00, + IEEE802154_PRIMITIVE_CONF_DATA = 0x00, + IEEE802154_PRIMITIVE_IND_DATA, /* MLME Notifications */ - IEEE802154_NOTIFY_CONF_ASSOC, - IEEE802154_NOTIFY_CONF_DISASSOC, - IEEE802154_NOTIFY_CONF_GTS, - IEEE802154_NOTIFY_CONF_RESET, - IEEE802154_NOTIFY_CONF_RXENABLE, - IEEE802154_NOTIFY_CONF_SCAN, - IEEE802154_NOTIFY_CONF_START, - IEEE802154_NOTIFY_CONF_POLL, - - IEEE802154_NOTIFY_IND_ASSOC, - IEEE802154_NOTIFY_IND_DISASSOC, - IEEE802154_NOTIFY_IND_BEACONNOTIFY, - IEEE802154_NOTIFY_IND_GTS, - IEEE802154_NOTIFY_IND_ORPHAN, - IEEE802154_NOTIFY_IND_COMMSTATUS, - IEEE802154_NOTIFY_IND_SYNCLOSS + IEEE802154_PRIMITIVE_CONF_ASSOC, + IEEE802154_PRIMITIVE_CONF_DISASSOC, + IEEE802154_PRIMITIVE_CONF_GTS, + IEEE802154_PRIMITIVE_CONF_RESET, + IEEE802154_PRIMITIVE_CONF_RXENABLE, + IEEE802154_PRIMITIVE_CONF_SCAN, + IEEE802154_PRIMITIVE_CONF_START, + IEEE802154_PRIMITIVE_CONF_POLL, + + IEEE802154_PRIMITIVE_IND_ASSOC, + IEEE802154_PRIMITIVE_IND_DISASSOC, + IEEE802154_PRIMITIVE_IND_BEACONNOTIFY, + IEEE802154_PRIMITIVE_IND_GTS, + IEEE802154_PRIMITIVE_IND_ORPHAN, + IEEE802154_PRIMITIVE_IND_COMMSTATUS, + IEEE802154_PRIMITIVE_IND_SYNCLOSS }; -union ieee802154_notif_u +union ieee802154_primitive_u { - /* MCPS Notifications */ + /* MCPS Primitives */ - struct ieee802154_data_conf_s dataconf; + struct ieee802154_data_conf_s dataconf; + struct ieee802154_data_ind_s dataind; - /* MLME Notifications */ + /* MLME Primitives */ struct ieee802154_assoc_conf_s assocconf; struct ieee802154_disassoc_conf_s disassocconf; @@ -1544,23 +1664,23 @@ union ieee802154_notif_u struct ieee802154_orphan_ind_s orphanind; struct ieee802154_commstatus_ind_s commstatusind; struct ieee802154_syncloss_ind_s synclossind; + + /* Foward link contained as first entry of all primitives */ + + FAR struct ieee802154_primitive_s *flink; }; -struct ieee802154_notif_s +struct ieee802154_primitive_s { /* Must be first member so that we can interchange between the actual - * notification and this extended struct. - */ - - union ieee802154_notif_u u; - enum ieee802154_notify_e notiftype; - - /* Support a singly linked list. For use by receivers. The MAC has it's own - * extended struct type with another forward link that the MAC uses internally - * to handle allocation and freeing. + * primitive and this extended struct. Note, all frames also have the first + * entry as a forward link to a primitive so that primitives can be contained + * in lists. */ - FAR struct ieee802154_notif_s *flink; + union ieee802154_primitive_u u; + enum ieee802154_primitive_e type; + int nclients; /* Number of clients to call ieee802154_primitive_free before freed */ }; /* A pointer to this structure is passed as the argument of each IOCTL @@ -1587,7 +1707,7 @@ union ieee802154_macarg_u /* To be determined */ /* MAC802154IOC_MLME_CALIBRATE_REQUEST */ uint8_t signo; /* MAC802154IOC_NOTIFY_REGISTER */ - struct ieee802154_notif_s notif; /* MAC802154IOC_GET_EVENT */ + struct ieee802154_primitive_s primitive; /* MAC802154IOC_GET_EVENT */ bool enable; /* MAC802154IOC_ENABLE_EVENTS */ }; @@ -1690,10 +1810,12 @@ int mac802154dev_register(MACHANDLE mac, int minor); int mac802154netdev_register(MACHANDLE mac); /**************************************************************************** - * Name: ieee802154_indpool_initialize + * Name: ieee802154_primitivepool_initialize * * Description: - * This function initializes the meta-data allocator. This function must + * This function initializes the primitive allocator. Primitives are defined + * in the standard and are used to pass information between the MAC layer and + * the next highest layer. They are a data type abstraction. This function must * be called early in the initialization sequence before any radios * begin operation. * @@ -1705,54 +1827,53 @@ int mac802154netdev_register(MACHANDLE mac); * ****************************************************************************/ -void ieee802154_indpool_initialize(void); +void ieee802154_primitivepool_initialize(void); /**************************************************************************** - * Name: ieee802154_ind_allocate + * Name: ieee802154_primitive_allocate * * Description: - * The ieee802154_ind_allocate function will get a free meta-data - * structure for use by the IEEE 802.15.4 MAC. + * The ieee802154_primitive_allocate function will get a free primitive + * structure from the pool, for use with the IEEE 802.15.4 MAC. * * Interrupt handling logic will first attempt to allocate from the - * g_indfree list. If that list is empty, it will attempt to allocate - * from its reserve, g_indfree_irq. If that list is empty, then the + * g_primfree list. If that list is empty, it will attempt to allocate + * from its reserve, g_primfree_irq. If that list is empty, then the * allocation fails (NULL is returned). * - * Non-interrupt handler logic will attempt to allocate from g_indfree - * list. If that the list is empty, then the meta-data structure will be + * Non-interrupt handler logic will attempt to allocate from g_primfree + * list. If that the list is empty, then the primitive structure will be * allocated from the dynamic memory pool. * * Inputs: * None * * Return Value: - * A reference to the allocated msg structure. All user fields in this + * A reference to the allocated primitive structure. All user fields in this * structure have been zeroed. On a failure to allocate, NULL is * returned. * ****************************************************************************/ -FAR struct ieee802154_data_ind_s *ieee802154_ind_allocate(void); +FAR struct ieee802154_primitive_s *ieee802154_primitive_allocate(void); /**************************************************************************** - * Name: ieee802154_ind_free + * Name: ieee802154_primitive_free * * Description: - * The ieee802154_ind_free function will return a meta-data structure to - * the free pool of messages if it was a pre-allocated meta-data - * structure. If the meta-data structure was allocated dynamically it will - * be deallocated. + * The ieee802154_primitive_free function will return a primitive structure to + * the free pool if it was a pre-allocated primitive structure. If the primitive + * was allocated dynamically it will be deallocated. * * Inputs: - * ind - meta-data structure to free + * prim - primitive structure to free * * Return Value: * None * ****************************************************************************/ -void ieee802154_ind_free(FAR struct ieee802154_data_ind_s *ind); +void ieee802154_primitive_free(FAR struct ieee802154_primitive_s *prim); #undef EXTERN #ifdef __cplusplus diff --git a/include/signal.h b/include/signal.h index 02e1e20122203678f72dfbf66fa16d1fa8dcc95b..b790c8dc16549cd29049f36b4d7bcf9845543011 100644 --- a/include/signal.h +++ b/include/signal.h @@ -1,7 +1,7 @@ /******************************************************************************** * include/signal.h * - * Copyright (C) 2007-2009, 2011, 2013-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011, 2013-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -308,6 +308,7 @@ int sigqueue(int pid, int signo, FAR void *sival_ptr); #endif int sigrelse(int signo); _sa_handler_t sigset(int signo, _sa_handler_t func); +int sigwait(FAR const sigset_t *set, FAR int *sig); int sigtimedwait(FAR const sigset_t *set, FAR struct siginfo *value, FAR const struct timespec *timeout); int sigsuspend(FAR const sigset_t *sigmask); diff --git a/include/sys/ioctl.h b/include/sys/ioctl.h index 6eaa35258252cdea7e1e0c2eccc67603b7d2bf28..cc697c040a3be115e88c5945fee1b9b1aaa091cf 100644 --- a/include/sys/ioctl.h +++ b/include/sys/ioctl.h @@ -58,6 +58,12 @@ #endif #endif /* CONFIG_NET */ +#ifdef CONFIG_INPUT +/* Include input driver IOCTL definitions */ + +# include +#endif + #ifdef CONFIG_DRIVERS_WIRELESS /* Include wireless character driver IOCTL definitions */ diff --git a/include/sys/socket.h b/include/sys/socket.h index b7c98c8018302fe8f6e01b775c687fe1f36ad972..5809e71136dead37c9e0e12618c9baae7526e179 100644 --- a/include/sys/socket.h +++ b/include/sys/socket.h @@ -110,44 +110,48 @@ #define MSG_NOSIGNAL 0x4000 /* Do not generate SIGPIPE. */ #define MSG_MORE 0x8000 /* Sender will send more. */ -/* Socket options */ +/* Protocol levels supported by get/setsockopt(): */ + +#define SOL_SOCKET 0 /* Only socket-level options supported */ -#define SO_DEBUG 0 /* Enables recording of debugging information (get/set). +/* Socket-level options */ + +#define SO_ACCEPTCONN 0 /* Reports whether socket listening is enabled (get only). * arg: pointer to integer containing a boolean value */ -#define SO_ACCEPTCONN 1 /* Reports whether socket listening is enabled (get only). +#define SO_BROADCAST 1 /* Permits sending of broadcast messages (get/set). * arg: pointer to integer containing a boolean value */ -#define SO_BROADCAST 2 /* Permits sending of broadcast messages (get/set). +#define SO_DEBUG 2 /* Enables recording of debugging information (get/set). * arg: pointer to integer containing a boolean value */ -#define SO_REUSEADDR 3 /* Allow reuse of local addresses (get/set) +#define SO_DONTROUTE 3 /* Requests that outgoing messages bypass standard routing (get/set) * arg: pointer to integer containing a boolean value */ -#define SO_KEEPALIVE 4 /* Keeps connections active by enabling the periodic transmission +#define SO_ERROR 4 /* Reports and clears error status (get only). arg: returns + * an integer value */ +#define SO_KEEPALIVE 5 /* Keeps connections active by enabling the periodic transmission * of messages (get/set). * arg: pointer to integer containing a boolean value */ -#define SO_LINGER 5 /* Lingers on a close() if data is present (get/set) +#define SO_LINGER 6 /* Lingers on a close() if data is present (get/set) * arg: struct linger */ -#define SO_OOBINLINE 6 /* Leaves received out-of-band data (data marked urgent) inline +#define SO_OOBINLINE 7 /* Leaves received out-of-band data (data marked urgent) inline * (get/set) arg: pointer to integer containing a boolean value */ -#define SO_SNDBUF 7 /* Sets send buffer size. arg: integer value (get/set). */ #define SO_RCVBUF 8 /* Sets receive buffer size. arg: integer value (get/set). */ -#define SO_ERROR 9 /* Reports and clears error status (get only). arg: returns - * an integer value */ -#define SO_TYPE 10 /* Reports the socket type (get only). return: int */ -#define SO_DONTROUTE 11 /* Requests that outgoing messages bypass standard routing (get/set) - * arg: pointer to integer containing a boolean value */ -#define SO_RCVLOWAT 12 /* Sets the minimum number of bytes to process for socket input +#define SO_RCVLOWAT 9 /* Sets the minimum number of bytes to process for socket input * (get/set). arg: integer value */ -#define SO_RCVTIMEO 13 /* Sets the timeout value that specifies the maximum amount of time +#define SO_RCVTIMEO 10 /* Sets the timeout value that specifies the maximum amount of time * an input function waits until it completes (get/set). * arg: struct timeval */ -#define SO_SNDLOWAT 14 /* Sets the minimum number of bytes to process for socket output +#define SO_REUSEADDR 11 /* Allow reuse of local addresses (get/set) + * arg: pointer to integer containing a boolean value */ +#define SO_SNDBUF 12 /* Sets send buffer size. arg: integer value (get/set). */ +#define SO_SNDLOWAT 13 /* Sets the minimum number of bytes to process for socket output * (get/set). arg: integer value */ -#define SO_SNDTIMEO 15 /* Sets the timeout value specifying the amount of time that an +#define SO_SNDTIMEO 14 /* Sets the timeout value specifying the amount of time that an * output function blocks because flow control prevents data from * being sent(get/set). arg: struct timeval */ +#define SO_TYPE 15 /* Reports the socket type (get only). return: int */ -/* Protocol levels supported by get/setsockopt(): */ +/* Protocol-level socket options may begin with this value */ -#define SOL_SOCKET 0 /* Only socket-level options supported */ +#define __SO_PROTOCOL 16 /* Values for the 'how' argument of shutdown() */ diff --git a/include/sys/statfs.h b/include/sys/statfs.h index 1d1786a3f81c53b2cd52e8aa470cf086bb24f92a..e33226e972cd5485502b58c86a00e113354d1611 100644 --- a/include/sys/statfs.h +++ b/include/sys/statfs.h @@ -104,6 +104,7 @@ #define SMARTFS_MAGIC 0x54524D53 #define UNIONFS_MAGIC 0x53464e55 #define HOSTFS_MAGIC 0x54534f48 +#define USERFS_MAGIC 0x52455355 /**************************************************************************** * Type Definitions diff --git a/include/sys/syscall.h b/include/sys/syscall.h index 8e6bd75941549ccaa9668868134e4d5ef6396b02..c79dca741bc9609de90c1e732773860997bfc328 100644 --- a/include/sys/syscall.h +++ b/include/sys/syscall.h @@ -227,7 +227,7 @@ # define SYS_sigsuspend (__SYS_signals+5) # define SYS_sigtimedwait (__SYS_signals+6) # define SYS_sigwaitinfo (__SYS_signals+7) -# define SYS_nanosleep (__SYS_signals+8) +# define SYS_clock_nanosleep (__SYS_signals+8) # define __SYS_clock (__SYS_signals+9) #else # define __SYS_clock __SYS_signals @@ -383,12 +383,13 @@ # define SYS_mount (__SYS_mountpoint+0) # endif # define SYS_fsync (__SYS_mountpoint+1) -# define SYS_mkdir (__SYS_mountpoint+2) -# define SYS_rename (__SYS_mountpoint+3) -# define SYS_rmdir (__SYS_mountpoint+4) -# define SYS_umount2 (__SYS_mountpoint+5) -# define SYS_unlink (__SYS_mountpoint+6) -# define __SYS_shm (__SYS_mountpoint+7) +# define SYS_ftruncate (__SYS_mountpoint+2) +# define SYS_mkdir (__SYS_mountpoint+3) +# define SYS_rename (__SYS_mountpoint+4) +# define SYS_rmdir (__SYS_mountpoint+5) +# define SYS_umount2 (__SYS_mountpoint+6) +# define SYS_unlink (__SYS_mountpoint+7) +# define __SYS_shm (__SYS_mountpoint+8) # else # define __SYS_shm __SYS_mountpoint # endif diff --git a/include/sys/uio.h b/include/sys/uio.h index d84bb2d2926d0fa15baf830292d9afb0fb4870d9..e1636282637dafdd95efee2439e7d31c2bc1f02b 100644 --- a/include/sys/uio.h +++ b/include/sys/uio.h @@ -1,8 +1,10 @@ /**************************************************************************** * include/sys/uio.h * + * Copyright (C) 2017 Grefory Nutt. All rights reserved. * Copyright (C) 2015 Stavros Polymenis. All rights reserved. * Author: Stavros Polymenis + * Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -50,9 +52,71 @@ struct iovec * Public Function Prototypes ****************************************************************************/ -#if 0 /* Not implemented */ -ssize_t readv(int, const struct iovec *, int); -ssize_t writev(int, const struct iovec *, int); -#endif +/**************************************************************************** + * Name: readv() + * + * Description: + * The readv() function is equivalent to read(), except as described below. + * The readv() function places the input data into the iovcnt buffers + * specified by the members of the iov array: iov[0], iov[1], ..., + * iov[iovcnt-1]. The iovcnt argument is valid if greater than 0 and less + * than or equal to IOV_MAX as defined in limits.h. + * + * Each iovec entry specifies the base address and length of an area in + * memory where data should be placed. The readv() function will always + * fill an area completely before proceeding to the next. + * + * Upon successful completion, readv() will mark for update the st_atime + * field of the file. + * + * Input Parameters: + * filedes - The open file descriptor for the file to be read + * iov - Array of read buffer descriptors + * iovcnt - Number of elements in iov[] + * + * Returned Value: + * Upon successful completion, readv() will return a non-negative integer + * indicating the number of bytes actually read. Otherwise, the functions + * will return -1 and set errno to indicate the error. See read(). + * + ****************************************************************************/ + +ssize_t readv(int fildes, FAR const struct iovec *iov, int iovcnt); + +/**************************************************************************** + * Name: writev() + * + * Description: + * The writev() function is equivalent to write(), except as described + * below. The writev() function will gather output data from the iovcnt + * buffers specified by the members of the iov array: iov[0], iov[1], ..., + * iov[iovcnt-1]. The iovcnt argument is valid if greater than 0 and less + * than or equal to IOV_MAX, as defined in limits.h. + * + * Each iovec entry specifies the base address and length of an area in + * memory from which data should be written. The writev() function always + * writes a complete area before proceeding to the next. + * + * If fildes refers to a regular file and all of the iov_len members in + * the array pointed to by iov are 0, writev() will return 0 and have no + * other effect. For other file types, the behavior is unspecified. + * + * If the sum of the iov_len values is greater than SSIZE_MAX, the + * operation will fail and no data will be transferred. + * + * Input Parameters: + * filedes - The open file descriptor for the file to be read + * iov - Array of read buffer descriptors + * iovcnt - Number of elements in iov[] + * + * Returned Value: + * Upon successful completion, writev() shall return the number of bytes + * actually written. Otherwise, it shall return a value of -1, the file- + * pointer shall remain unchanged, and errno shall be set to indicate an + * error. + * + ****************************************************************************/ + +ssize_t writev(int fildes, FAR const struct iovec *iov, int iovcnt); #endif /* __INCLUDE_SYS_UIO_H */ diff --git a/include/syslog.h b/include/syslog.h index 07374084a0bd03a5264cfa7e862c668891298ea9..59f1301fb49fb8627d7ecf5eb281944b8ba66dfe 100644 --- a/include/syslog.h +++ b/include/syslog.h @@ -125,7 +125,7 @@ /* Used with setlogmask() */ #define LOG_MASK(p) (1 << (p)) -#define LOG_UPTO(p) ((1 << (p)) - 1) +#define LOG_UPTO(p) ((1 << ((p)+1)) - 1) #define LOG_ALL 0xff /**************************************************************************** @@ -212,8 +212,8 @@ void closelog(void); * ****************************************************************************/ -int syslog(int priority, FAR const IPTR char *format, ...); -int vsyslog(int priority, FAR const IPTR char *src, va_list ap); +int syslog(int priority, FAR const IPTR char *fmt, ...); +int vsyslog(int priority, FAR const IPTR char *fmt, va_list ap); /**************************************************************************** * Name: setlogmask diff --git a/include/time.h b/include/time.h index f52435701374aa8700a2a12cda2dac637058b3a4..8c92a3b19108d36bc6031f36da87b14f72d81217 100644 --- a/include/time.h +++ b/include/time.h @@ -1,7 +1,7 @@ /******************************************************************************** * include/time.h * - * Copyright (C) 2007-2011, 2013-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2011, 2013-2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -90,15 +90,17 @@ # define CLOCK_MONOTONIC 1 #endif -/* This is a flag that may be passed to the timer_settime() function */ +/* This is a flag that may be passed to the timer_settime() and + * clock_nanosleep() functions. + */ #define TIMER_ABSTIME 1 #ifndef CONFIG_LIBC_LOCALTIME /* Local time is the same as gmtime in this implementation */ -# define localtime(c) gmtime(c) -# define localtime_r(c,r) gmtime_r(c,r) +# define localtime(c) gmtime(c) +# define localtime_r(c,r) gmtime_r(c,r) #endif /******************************************************************************** @@ -231,6 +233,9 @@ int timer_settime(timer_t timerid, int flags, int timer_gettime(timer_t timerid, FAR struct itimerspec *value); int timer_getoverrun(timer_t timerid); +int clock_nanosleep(clockid_t clockid, int flags, + FAR const struct timespec *rqtp, + FAR struct timespec *rmtp); int nanosleep(FAR const struct timespec *rqtp, FAR struct timespec *rmtp); #ifdef CONFIG_LIBC_LOCALTIME diff --git a/include/unistd.h b/include/unistd.h index a812533aadabe305607d2fdc3f08dc4417eb4688..93d5f63f3cba7ee47e4d6fe3754eed1bb907e19d 100644 --- a/include/unistd.h +++ b/include/unistd.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/unistd.h * - * Copyright (C) 2007-2009, 2013-2014, 2016-2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2013-2014, 2016-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -164,6 +164,7 @@ ssize_t read(int fd, FAR void *buf, size_t nbytes); ssize_t write(int fd, FAR const void *buf, size_t nbytes); ssize_t pread(int fd, FAR void *buf, size_t nbytes, off_t offset); ssize_t pwrite(int fd, FAR const void *buf, size_t nbytes, off_t offset); +int ftruncate(int fd, off_t length); /* Check if a file descriptor corresponds to a terminal I/O file */ @@ -190,6 +191,7 @@ FAR char *getcwd(FAR char *buf, size_t size); int access(FAR const char *path, int amode); int rmdir(FAR const char *pathname); int unlink(FAR const char *pathname); +int truncate(FAR const char *path, off_t length); #ifdef CONFIG_PSEUDOFS_SOFTLINKS int link(FAR const char *path1, FAR const char *path2); diff --git a/libc/Kconfig b/libc/Kconfig index 407e9dead786a5132d0101a1a56207ed52080916..0e558863dbfa57ac3e8f47338e20b3947eed4562 100644 --- a/libc/Kconfig +++ b/libc/Kconfig @@ -22,3 +22,4 @@ source libc/netdb/Kconfig source libc/misc/Kconfig source libc/wqueue/Kconfig source libc/hex2bin/Kconfig +source libc/userfs/Kconfig diff --git a/libc/Makefile b/libc/Makefile index 4b23e458c1b5f2774fefa50f80e185e0ed551711..09e3cbd81b1fa620b28f6c562af34fe92ae084ca 100644 --- a/libc/Makefile +++ b/libc/Makefile @@ -37,21 +37,13 @@ # CFLAGS -ifeq ($(CONFIG_BUILD_PROTECTED),y) -ifeq ($(CONFIG_WINDOWS_NATIVE),y) - KDEFINE = ${shell $(TOPDIR)\tools\define.bat "$(CC)" __KERNEL__} -else - KDEFINE = ${shell $(TOPDIR)/tools/define.sh "$(CC)" __KERNEL__} -endif -else -ifeq ($(CONFIG_BUILD_KERNEL),y) +ifneq ($(CONFIG_BUILD_FLAT),y) ifeq ($(CONFIG_WINDOWS_NATIVE),y) KDEFINE = ${shell $(TOPDIR)\tools\define.bat "$(CC)" __KERNEL__} else KDEFINE = ${shell $(TOPDIR)/tools/define.sh "$(CC)" __KERNEL__} endif endif -endif # Sources and paths @@ -90,7 +82,9 @@ include syslog/Make.defs include termios/Make.defs include time/Make.defs include tls/Make.defs +include uio/Make.defs include unistd/Make.defs +include userfs/Make.defs include wchar/Make.defs include wctype/Make.defs include wqueue/Make.defs @@ -152,11 +146,11 @@ endif # Dependencies .depend: Makefile $(SRCS) -ifeq ($(CONFIG_BUILD_PROTECTED),y) +ifeq ($(CONFIG_BUILD_FLAT),y) + $(Q) $(MKDEP) --obj-path bin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make_bin.dep +else $(Q) $(MKDEP) --obj-path ubin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make_ubin.dep $(Q) $(MKDEP) --obj-path kbin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) $(KDEFINE) -- $(SRCS) >Make_kbin.dep -else - $(Q) $(MKDEP) --obj-path bin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make_bin.dep endif ifeq ($(CONFIG_LIB_ZONEINFO_ROMFS),y) $(Q) $(MAKE) -C zoneinfo depend TOPDIR=$(TOPDIR) BIN=$(BIN) diff --git a/libc/README.txt b/libc/README.txt index 4184aa71a812744497f26e8aa8502c9240a37941..b80438c9b9158ab63f746f38f08275287f212834 100644 --- a/libc/README.txt +++ b/libc/README.txt @@ -35,9 +35,9 @@ we have: locale - locale.h fixedmath - fixedmath.h inttypes - inttypes.h - machine - Various architecture-specifica implementations. + machine - Various architecture-specific implementations. math - math.h - modlib - Part of module and shared libary logic: nuttx/lib/modlib.h + modlib - Part of module and shared library logic: nuttx/lib/modlib.h net - Various network-related header files: netinet/ether.h, arpa/inet.h pthread - pthread.h queue - queue.h @@ -47,6 +47,7 @@ we have: stdlib - stdlib.h string - string.h (and legacy strings.h) time - time.h + uio - sys/uio.h unistd - unistd.h wchar - wchar.h wctype - wctype.h diff --git a/libc/audio/lib_buffer.c b/libc/audio/lib_buffer.c index b1406da1c56ce3fdca28a275a54efbb29b614d51..8fe2fd51f3ebf7e7da38e568dc0203cf906cd918 100644 --- a/libc/audio/lib_buffer.c +++ b/libc/audio/lib_buffer.c @@ -70,6 +70,8 @@ static void apb_semtake(FAR struct ap_buffer_s *apb) { + int ret; + /* Take the semaphore (perhaps waiting) */ while (_SEM_WAIT(&apb->sem) < 0) @@ -79,6 +81,7 @@ static void apb_semtake(FAR struct ap_buffer_s *apb) */ DEBUGASSERT(_SEM_ERRNO(ret) == EINTR); + UNUSED(ret); } } diff --git a/libc/math.csv b/libc/math.csv index ec17f1cbdec8dcb53a2d9964e5f911ad8a1174ea..60a49821c97a8d6024678a69dd2d882d89697be0 100644 --- a/libc/math.csv +++ b/libc/math.csv @@ -57,6 +57,7 @@ "rint","math.h","defined(CONFIG_HAVE_DOUBLE) && (defined(CONFIG_LIBM) || defined(CONFIG_ARCH_MATH))","double","double" "rintf","math.h","defined(CONFIG_LIBM) || defined(CONFIG_ARCH_MATH)","float","float" "rintl","math.h","defined(CONFIG_HAVE_LONG_DOUBLE) && (defined(CONFIG_LIBM) || defined(CONFIG_ARCH_MATH))","long double","long double" +"readv","sys/uio.h","","ssize_t","int","FAR const struct iovec *","int" "round","math.h","defined(CONFIG_HAVE_DOUBLE) && (defined(CONFIG_LIBM) || defined(CONFIG_ARCH_MATH))","double","double" "roundf","math.h","defined(CONFIG_LIBM) || defined(CONFIG_ARCH_MATH)","float","float" "roundl","math.h","defined(CONFIG_HAVE_LONG_DOUBLE) && (defined(CONFIG_LIBM) || defined(CONFIG_ARCH_MATH))","long double","long double" @@ -75,3 +76,4 @@ "tanhf","math.h","defined(CONFIG_LIBM) || defined(CONFIG_ARCH_MATH)","float","float" "tanhl","math.h","defined(CONFIG_HAVE_LONG_DOUBLE) && (defined(CONFIG_LIBM) || defined(CONFIG_ARCH_MATH))","long double","long double" "tanl","math.h","defined(CONFIG_HAVE_LONG_DOUBLE) && (defined(CONFIG_LIBM) || defined(CONFIG_ARCH_MATH))","long double","long double" +"writev","sys/uio.h","","ssize_t","int","FAR const struct iovec *","int" diff --git a/libc/signal/Make.defs b/libc/signal/Make.defs index bedee1895e8be3d5701a87c1452cbb3fcdd30781..7fdb9cbd1d7884d6c277090a0434b1e6698459dd 100644 --- a/libc/signal/Make.defs +++ b/libc/signal/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # libc/signal/Make.defs # -# Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. +# Copyright (C) 2011-2012, 2016-2017 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -39,7 +39,7 @@ ifneq ($(CONFIG_DISABLE_SIGNALS),y) CSRCS += sig_addset.c sig_delset.c sig_emptyset.c sig_fillset.c CSRCS += sig_hold.c sig_ignore.c sig_ismember.c sig_pause.c sig_raise.c -CSRCS += sig_relse.c sig_set.c signal.c +CSRCS += sig_relse.c sig_set.c signal.c sigwait.c # Add the signal directory to the build diff --git a/libc/signal/sigwait.c b/libc/signal/sigwait.c new file mode 100644 index 0000000000000000000000000000000000000000..8a3eeb0375899db7090b8e50d02b73fdba09fa6a --- /dev/null +++ b/libc/signal/sigwait.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * libc/signal/sigwait.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sigwait + * + * Description: + * The sigwait() function selects a pending signal from set, atomically + * clears it from the system's set of pending signals, and returns that + * signal number in the location referenced by sig. If prior to the call + * to sigwait() there are multiple pending instances of a single signal + * number, it is implementation-dependent whether upon successful return + * there are any remaining pending signals for that signal number. If the + * implementation supports queued signals and there are multiple signals + * queued for the signal number selected, the first such queued signal + * causes a return from sigwait() and the remainder remain queued. If no + * signal in set is pending at the time of the call, the thread is + * suspended until one or more becomes pending. The signals defined by set + * will been blocked at the time of the call to sigwait(); otherwise the + * behavior is undefined. The effect of sigwait() on the signal actions + * for the signals in set is unspecified. + * + * If more than one thread is using sigwait() to wait for the same + * signal, no more than one of these threads will return from sigwait() + * with the signal number. Which thread returns from sigwait() if more + * than a single thread is waiting is unspecified. + * + * Should any of the multiple pending signals in the range SIGRTMIN to + * SIGRTMAX be selected, it shall be the lowest numbered one. The selection + * order between realtime and non-realtime signals, or between multiple + * pending non-realtime signals, is unspecified. + * + * Input Parameters: + * set - The set of pending signals to wait for + * sig - The location in which to return the pending signal number. + * + * Returned Value: + * Upon successful completion, sigwait() stores the signal number of the + * received signal at the location referenced by sig and returns zero. + * Otherwise, an error number is returned to indicate the error. + * + ****************************************************************************/ + +int sigwait(FAR const sigset_t *set, FAR int *sig) +{ + int signo; + + DEBUGASSERT(set != NULL && sig != NULL); + + /* The standard sigwait() function behaves that same as sigwainfo() with + * the info argument set to NULL. + */ + + signo = sigwaitinfo(set, NULL); + if (signo < 0) + { + /* If sigwaitinfo() fails, return the error number */ + + return get_errno(); + } + + /* Return the signal number in the user provided location */ + + *sig = signo; + return OK; +} diff --git a/libc/stdio/lib_freopen.c b/libc/stdio/lib_freopen.c index 830ea9a78f51a97dc66005b46473ff66cdbbfb48..0fffc1bd9618d4d7e53703ea285d12e782f4ff13 100644 --- a/libc/stdio/lib_freopen.c +++ b/libc/stdio/lib_freopen.c @@ -113,7 +113,7 @@ FAR FILE *freopen(FAR const char *path, FAR const char *mode, /* Convert the mode string into standard file open mode flags. */ oflags = lib_mode2oflags(mode); - if (oflags == 0) + if (oflags < 0) { return NULL; } diff --git a/libc/stdio/lib_sscanf.c b/libc/stdio/lib_sscanf.c index 72dca128bd929e240281dd3a0f552baa20c0137a..183b9b65357b858de5195cf0401620c830d75a38 100644 --- a/libc/stdio/lib_sscanf.c +++ b/libc/stdio/lib_sscanf.c @@ -574,7 +574,6 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) if (!noassign) { strncpy(tv, buf, width); - tv[width] = '\0'; count++; } diff --git a/libc/time/Make.defs b/libc/time/Make.defs index 68e62436871cc2106c9b65a1f312e3f9e55c0a65..f72fd4f99f1e298d4c1d4f05eafd6c61bd90d065 100644 --- a/libc/time/Make.defs +++ b/libc/time/Make.defs @@ -39,6 +39,10 @@ CSRCS += lib_strftime.c lib_calendar2utc.c lib_daysbeforemonth.c CSRCS += lib_gettimeofday.c lib_isleapyear.c lib_settimeofday.c lib_time.c CSRCS += lib_difftime.c +ifndef CONFIG_DISABLE_SIGNALS +CSRCS += lib_nanosleep.c +endif + ifdef CONFIG_LIBC_LOCALTIME CSRCS += lib_localtime.c lib_asctime.c lib_asctimer.c lib_ctime.c CSRCS += lib_ctimer.c diff --git a/libc/time/lib_nanosleep.c b/libc/time/lib_nanosleep.c new file mode 100644 index 0000000000000000000000000000000000000000..ad728de5b8c03188b533d91e2febf58e26c85804 --- /dev/null +++ b/libc/time/lib_nanosleep.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * libc/time/nanosleep.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nanosleep + * + * Description: + * The nanosleep() function causes the current thread to be suspended from + * execution until either the time interval specified by the rqtp argument + * has elapsed or a signal is delivered to the calling thread and its + * action is to invoke a signal-catching function or to terminate the + * process. The suspension time may be longer than requested because the + * argument value is rounded up to an integer multiple of the sleep + * resolution or because of the scheduling of other activity by the + * system. But, except for the case of being interrupted by a signal, the + * suspension time will not be less than the time specified by rqtp, as + * measured by the system clock, CLOCK_REALTIME. + * + * The use of the nanosleep() function has no effect on the action or + * blockage of any signal. + * + * Parameters: + * rqtp - The amount of time to be suspended from execution. + * rmtp - If the rmtp argument is non-NULL, the timespec structure + * referenced by it is updated to contain the amount of time + * remaining in the interval (the requested time minus the time + * actually slept) + * + * Returned Value: + * If the nanosleep() function returns because the requested time has + * elapsed, its return value is zero. + * + * If the nanosleep() function returns because it has been interrupted by + * a signal, the function returns a value of -1 and sets errno to indicate + * the interruption. If the rmtp argument is non-NULL, the timespec + * structure referenced by it is updated to contain the amount of time + * remaining in the interval (the requested time minus the time actually + * slept). If the rmtp argument is NULL, the remaining time is not + * returned. + * + * If nanosleep() fails, it returns a value of -1 and sets errno to + * indicate the error. The nanosleep() function will fail if: + * + * EINTR - The nanosleep() function was interrupted by a signal. + * EINVAL - The rqtp argument specified a nanosecond value less than + * zero or greater than or equal to 1000 million. + * ENOSYS - The nanosleep() function is not supported by this + * implementation. + * + ****************************************************************************/ + +int nanosleep(FAR const struct timespec *rqtp, FAR struct timespec *rmtp) +{ + /* Calling clock_nanosleep() with the value TIMER_ABSTIME not set in the + * flags argument and with a clock_id of CLOCK_REALTIME is equivalent t + * calling nanosleep() with the same rqtp and rmtp arguments. + */ + + return clock_nanosleep(CLOCK_REALTIME, 0, rqtp, rmtp); +} diff --git a/configs/xtrs/src/Makefile b/libc/uio/Make.defs similarity index 87% rename from configs/xtrs/src/Makefile rename to libc/uio/Make.defs index 4398bf214a7fd2af3647d101e9bf3baa33cd2ef3..30f72cccc7bd2e160e9a77a939c2e255455f0979 100644 --- a/configs/xtrs/src/Makefile +++ b/libc/uio/Make.defs @@ -1,7 +1,7 @@ ############################################################################ -# configs/xtrs/src/Makefile +# libc/uio/Make.defs # -# Copyright (C) 2008, 2012 Gregory Nutt. All rights reserved. +# Copyright (C) 2017 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -33,9 +33,11 @@ # ############################################################################ --include $(TOPDIR)/Make.defs +# Add the uio.h C files to the build -ASRCS = -CSRCS = xtr_irq.c xtr_serial.c xtr_timerisr.c xtr_lowputc.c +CSRCS += lib_readv.c lib_writev.c -include $(TOPDIR)/configs/Board.mk +# Add the uio.h directory to the build + +DEPPATH += --dep-path uio +VPATH += :uio diff --git a/libc/uio/lib_readv.c b/libc/uio/lib_readv.c new file mode 100644 index 0000000000000000000000000000000000000000..b791ce8c43392b4bc986d9d20c901b987fecb5d6 --- /dev/null +++ b/libc/uio/lib_readv.c @@ -0,0 +1,131 @@ +/**************************************************************************** + * libc/stdio/lib_readv.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: readv() + * + * Description: + * The readv() function is equivalent to read(), except as described below. + * The readv() function places the input data into the iovcnt buffers + * specified by the members of the iov array: iov[0], iov[1], ..., + * iov[iovcnt-1]. The iovcnt argument is valid if greater than 0 and less + * than or equal to IOV_MAX as defined in limits.h. + * + * Each iovec entry specifies the base address and length of an area in + * memory where data should be placed. The readv() function will always + * fill an area completely before proceeding to the next. + * + * Upon successful completion, readv() will mark for update the st_atime + * field of the file. + * + * Input Parameters: + * filedes - The open file descriptor for the file to be read + * iov - Array of read buffer descriptors + * iovcnt - Number of elements in iov[] + * + * Returned Value: + * Upon successful completion, readv() will return a non-negative integer + * indicating the number of bytes actually read. Otherwise, the functions + * will return -1 and set errno to indicate the error. See read(). + * + ****************************************************************************/ + +ssize_t readv(int fildes, FAR const struct iovec *iov, int iovcnt) +{ + ssize_t ntotal; + ssize_t nread; + size_t remaining; + FAR uint8_t *buffer; + int i; + + /* Process each entry in the struct iovec array */ + + for (i = 0, ntotal = 0; i < iovcnt; i++) + { + /* Ignore zero-length reads */ + + if (iov[i].iov_len > 0) + { + buffer = iov[i].iov_base; + remaining = iov[i].iov_len; + + /* Read repeatedly as necessary to fill buffer */ + + do + { + /* NOTE: read() is a cancellation point */ + + nread = read(fildes, buffer, remaining); + + /* Check for a read error */ + + if (nread < 0) + { + return nread; + } + + /* Check for an end-of-file condition */ + + else if (nread == 0) + { + return ntotal; + } + + /* Update pointers and counts in order to handle partial + * buffer reads. + */ + + buffer += nread; + remaining -= nread; + ntotal += nread; + } + while (remaining > 0); + } + } + + return ntotal; +} diff --git a/libc/uio/lib_writev.c b/libc/uio/lib_writev.c new file mode 100644 index 0000000000000000000000000000000000000000..eb28654be77e6766c7f321fccaf7a40b9c9db317 --- /dev/null +++ b/libc/uio/lib_writev.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * libc/stdio/lib_writev.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: writev() + * + * Description: + * The writev() function is equivalent to write(), except as described + * below. The writev() function will gather output data from the iovcnt + * buffers specified by the members of the iov array: iov[0], iov[1], ..., + * iov[iovcnt-1]. The iovcnt argument is valid if greater than 0 and less + * than or equal to IOV_MAX, as defined in limits.h. + * + * Each iovec entry specifies the base address and length of an area in + * memory from which data should be written. The writev() function always + * writes a complete area before proceeding to the next. + * + * If fildes refers to a regular file and all of the iov_len members in + * the array pointed to by iov are 0, writev() will return 0 and have no + * other effect. For other file types, the behavior is unspecified. + * + * If the sum of the iov_len values is greater than SSIZE_MAX, the + * operation will fail and no data will be transferred. + * + * Input Parameters: + * filedes - The open file descriptor for the file to be read + * iov - Array of read buffer descriptors + * iovcnt - Number of elements in iov[] + * + * Returned Value: + * Upon successful completion, writev() shall return the number of bytes + * actually written. Otherwise, it shall return a value of -1, the file- + * pointer shall remain unchanged, and errno shall be set to indicate an + * error. + * + ****************************************************************************/ + +ssize_t writev(int fildes, FAR const struct iovec *iov, int iovcnt) +{ + ssize_t ntotal; + ssize_t nwritten; + size_t remaining; + FAR uint8_t *buffer; + off_t pos; + int i; + + /* Get the current file position in case we have to reset it */ + + pos = lseek(fildes, 0, SEEK_CUR); + if (pos == (off_t)-1) + { + return ERROR; + } + + /* Process each entry in the struct iovec array */ + + for (i = 0, ntotal = 0; i < iovcnt; i++) + { + /* Ignore zero-length writes */ + + if (iov[i].iov_len > 0) + { + buffer = iov[i].iov_base; + remaining = iov[i].iov_len; + + /* Write repeatedly as necessary to write the entire buffer */ + + do + { + /* NOTE: write() is a cancellation point */ + + nwritten = write(fildes, buffer, remaining); + + /* Check for a write error */ + + if (nwritten < 0) + { + /* Save the errno value */ + + int save = get_errno(); + + /* Restore the file position */ + + (void)lseek(fildes, pos, SEEK_SET); + + /* Restore the errno value */ + + set_errno(save); + return ERROR; + } + + /* Update pointers and counts in order to handle partial + * buffer writes. + */ + + buffer += nwritten; + remaining -= nwritten; + ntotal += nwritten; + } + while (remaining > 0); + } + } + + return ntotal; +} diff --git a/libc/unistd/Make.defs b/libc/unistd/Make.defs index 3234a9f7fc5c40e22ebdb86d5aab198122255491..aa166bd0644da614c1029982432b0554e1dc1904 100644 --- a/libc/unistd/Make.defs +++ b/libc/unistd/Make.defs @@ -47,6 +47,10 @@ ifeq ($(CONFIG_LIBC_EXECFUNCS),y) CSRCS += lib_execl.c endif +ifneq ($(CONFIG_DISABLE_MOUNTPOINTS),y) +CSRCS += lib_truncate.c +endif + ifeq ($(CONFIG_PIPES),y) CSRCS += lib_pipe.c endif diff --git a/libc/unistd/lib_sleep.c b/libc/unistd/lib_sleep.c index cb188a9329ac58d26e1ce988272f33701f448fdd..b8a747b568488884b9704b75c827b13ae3e8acda 100644 --- a/libc/unistd/lib_sleep.c +++ b/libc/unistd/lib_sleep.c @@ -1,7 +1,8 @@ /**************************************************************************** * lib/lib_sleep.c * - * Copyright (C) 2007, 2009, 2012-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2007, 2009, 2012-2013, 2017 Gregory Nutt. All rights + * reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -117,14 +118,14 @@ unsigned int sleep(unsigned int seconds) if (seconds > 0) { - /* Let nanosleep() do all of the work. */ + /* Let clock_nanosleep() do all of the work. */ rqtp.tv_sec = seconds; rqtp.tv_nsec = 0; - ret = nanosleep(&rqtp, &rmtp); + ret = clock_nanosleep(CLOCK_REALTIME, 0, &rqtp, &rmtp); - /* nanosleep() should only fail if it was interrupted by a signal, + /* clock_nanosleep() should only fail if it was interrupted by a signal, * but we treat all errors the same, */ diff --git a/libc/unistd/lib_truncate.c b/libc/unistd/lib_truncate.c new file mode 100644 index 0000000000000000000000000000000000000000..bde28a30225b24f94a9c3d09aeb63a34f4a79667 --- /dev/null +++ b/libc/unistd/lib_truncate.c @@ -0,0 +1,134 @@ +/**************************************************************************** + * libc/unistd/lib_truncate.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#ifndef CONFIG_DISABLE_MOUNTPOINT + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: truncate + * + * Description: + * The truncate() function causes the regular file named by path to have + * a size of length bytes. + * + * If the file previously was larger than length, the extra data is + * discarded. If it was previously shorter than length, it is unspecified + * whether the file is changed or its size increased. If the file is + * extended, the extended area appears as if it were zero-filled. + + * With truncate(), the file must be open for writing; for truncate(), + * the process must have write permission for the file. + * + * truncate() does not modify the file offset for any open file + * descriptions associated with the file. + * + * Input Parameters: + * path - The path to the regular file to be truncated. + * length - The new length of the regular file. + * + * Returned Value: + * Upon successful completion, truncate() return 0s. Otherwise a -1 is + * returned, and errno is set to indicate the error. + + * EINTR + * - A signal was caught during execution. + * EINVAL + * - The length argument was less than 0. + * EFBIG or EINVAL + * - The length argument was greater than the maximum file size. + * EIO + * - An I/O error occurred while reading from or writing to a file + * system. + * EACCES + * - A component of the path prefix denies search permission, or write + * permission is denied on the file. + * EISDIR + * - The named file is a directory. + * ELOOP + * - Too many symbolic links were encountered in resolving path. + * ENAMETOOLONG + * - The length of the specified pathname exceeds PATH_MAX bytes, or + * the length of a component of the pathname exceeds NAME_MAX bytes. + * ENOENT + * - A component of path does not name an existing file or path is an + * empty string. + * ENOTDIR + * - A component of the path prefix of path is not a directory. + * EROFS + * - he named file resides on a read-only file system. + * ENAMETOOLONG + * - Pathname resolution of a symbolic link produced an intermediate + * result whose length exceeds PATH_MAX. + * + ****************************************************************************/ + +int truncate(FAR const char *path, off_t length) +{ + int fd; + int ret; + + DEBUGASSERT(path != NULL && length >= 0); + + /* Open the regular file at 'path' for write-only access */ + + fd = open(path, O_WRONLY); + if (fd < 0) + { + return ERROR; + } + + /* Then let ftruncate() do the work */ + + ret = ftruncate(fd, length); + + close(fd); + return ret; +} + +#endif /* !CONFIG_DISABLE_MOUNTPOINT */ diff --git a/libc/unistd/lib_usleep.c b/libc/unistd/lib_usleep.c index 4e3d4cdb0c4b44b9e97e7b1574585d0bb80738a5..8e6d8040e350d063dd47dcf5ed23ca09cf5102af 100644 --- a/libc/unistd/lib_usleep.c +++ b/libc/unistd/lib_usleep.c @@ -1,7 +1,8 @@ /**************************************************************************** * lib/lib_usleep.c * - * Copyright (C) 2007, 2009, 2012-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2007, 2009, 2012-2013, 2017 Gregory Nutt. All rights + * reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -114,13 +115,13 @@ int usleep(useconds_t usec) if (usec) { - /* Let nanosleep() do all of the work. */ + /* Let clock_nanosleep() do all of the work. */ sec = usec / 1000000; rqtp.tv_sec = sec; rqtp.tv_nsec = (usec - (sec * 1000000)) * 1000; - ret = nanosleep(&rqtp, NULL); + ret = clock_nanosleep(CLOCK_REALTIME, 0, &rqtp, NULL); } return ret; diff --git a/libc/userfs/.gitignore b/libc/userfs/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..91d1ddb7d02d65c013b294e51d78ae1648e94a8e --- /dev/null +++ b/libc/userfs/.gitignore @@ -0,0 +1,10 @@ +/.built +/.tzbuilt +/.tzunpack +/romfs_zoneinfo.img +/romfs_zoneinfo.h +/tzbin +/tzcode-latest.tar.gz +/tzcode +/tzdata-latest.tar.gz + diff --git a/configs/xtrs/Kconfig b/libc/userfs/Kconfig similarity index 100% rename from configs/xtrs/Kconfig rename to libc/userfs/Kconfig diff --git a/libc/userfs/Make.defs b/libc/userfs/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..6c34026c56f02bcd68b0493917fb457b17edf1cb --- /dev/null +++ b/libc/userfs/Make.defs @@ -0,0 +1,47 @@ +############################################################################ +# libc/userfs/Make.defs +# +# Copyright (C) 2017 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +ifeq ($(CONFIG_FS_USERFS),y) + +# Add the internal C files to the build + +CSRCS += lib_userfs.c + +# Add the userfs directory to the build + +DEPPATH += --dep-path userfs +VPATH += :userfs + +endif diff --git a/libc/userfs/lib_userfs.c b/libc/userfs/lib_userfs.c new file mode 100644 index 0000000000000000000000000000000000000000..8f04c21f1d914d41ecc42bc232152b83dc7fe024 --- /dev/null +++ b/libc/userfs/lib_userfs.c @@ -0,0 +1,1144 @@ +/**************************************************************************** + * libc/userfs/lib_userfs.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct userfs_info_s +{ + FAR const struct userfs_operations_s *userops; /* File system callbacks */ + FAR void *volinfo; /* Data that accompanies the user callbacks */ + struct sockaddr_in client; /* Client to send response back to */ + int16_t sockfd; /* Server socket */ + uint16_t iolen; /* Size of I/O buffer */ + uint16_t mxwrite; /* The max size of a write data */ + uint8_t iobuffer[1]; /* I/O buffer. Actual size is iolen. */ +}; + +#define SIZEOF_USERFS_INFO_S(n) (sizeof(struct userfs_info_s) + (n) - 1) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* REVISIT: This is insufficient in the KERNEL build. In that build mode, + * there will be multiple instances of these variables and the logic will + * not generate unique instance numbers. + */ + +static sem_t g_userfs_exclsem = SEM_INITIALIZER(1); +static uint8_t g_userfs_next_instance; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: userfs_server_portno + ****************************************************************************/ + +static inline uint16_t userfs_server_portno(void) +{ + int ret; + + ret = nxsem_wait(&g_userfs_exclsem); + if (ret >= 0) + { + /* Get the next instance number. + * + * REVISIT: Here we really should verify that other UserFs + * exists with the same instance number. That could + * happen if g_userfs_next_instance were to wrap around. + */ + + ret = USERFS_SERVER_PORTBASE | g_userfs_next_instance++; + nxsem_post(&g_userfs_exclsem); + } + + return ret; +} + +/**************************************************************************** + * Name: userfs_*_dispatch + ****************************************************************************/ + +static inline int userfs_open_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_open_request_s *req, size_t reqlen) +{ + struct userfs_open_response_s resp; + int pathlen; + size_t expected; + ssize_t nsent; + int ret; + + /* Verify the request size */ + + if (reqlen < SIZEOF_USERFS_OPEN_REQUEST_S(0)) + { + return -EINVAL; + } + + pathlen = strlen(req->relpath); + if (pathlen > info->mxwrite) + { + return -EINVAL; + } + + expected = SIZEOF_USERFS_OPEN_REQUEST_S(pathlen); + if (expected >= reqlen) + { + return -EINVAL; + } + + /* Dispatch the request. + * + * REVISIT: In the kernel build openinfo will be valid only in the + * context of this process. + */ + + DEBUGASSERT(info->userops != NULL && info->userops->open != NULL); + resp.ret = info->userops->open(info->volinfo, req->relpath, req->oflags, + req->mode, &resp.openinfo); + + /* Send the response */ + + resp.resp = USERFS_RESP_OPEN; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_open_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + ret = -errno; + ferr("ERROR: Send open response failed: %d\n", ret); + return ret; + } + + /* REVISIT: Partial sends are not supported */ + + DEBUGASSERT(nsent == sizeof(struct userfs_open_response_s)); + return OK; +} + +static inline int userfs_close_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_close_request_s *req, size_t reqlen) +{ + struct userfs_close_response_s resp; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen != sizeof(struct userfs_close_request_s)) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->close != NULL); + resp.ret = info->userops->close(info->volinfo, req->openinfo); + + /* Send the response */ + + resp.resp = USERFS_RESP_CLOSE; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_close_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_read_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_read_request_s *req, size_t reqlen) +{ + FAR struct userfs_read_response_s *resp; + size_t readlen; + size_t resplen; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen != sizeof(struct userfs_read_request_s)) + { + return -EINVAL; + } + + /* Dispatch the request */ + + readlen = req->readlen; + if (readlen > info->mxwrite) + { + readlen = info->mxwrite; + } + + resp = (FAR struct userfs_read_response_s *)info->iobuffer; + + DEBUGASSERT(info->userops != NULL && info->userops->read != NULL); + resp->nread = info->userops->read(info->volinfo, req->openinfo, + resp->rddata, readlen); + + /* Send the response */ + + resp->resp = USERFS_RESP_READ; + resplen = SIZEOF_USERFS_READ_RESPONSE_S(resp->nread); + nsent = sendto(info->sockfd, resp, resplen, 0, + (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_write_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_write_request_s *req, size_t reqlen) +{ + struct userfs_write_response_s resp; + size_t writelen; + size_t expected; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen < SIZEOF_USERFS_WRITE_REQUEST_S(0)) + { + return -EINVAL; + } + + writelen = req->writelen; + if (writelen > info->mxwrite) + { + return -EINVAL; + } + + expected = SIZEOF_USERFS_WRITE_REQUEST_S(writelen); + if (expected != reqlen) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->write != NULL); + resp.nwritten = info->userops->write(info->volinfo, req->openinfo, + req->wrdata, writelen); + + /* Send the response */ + + resp.resp = USERFS_RESP_WRITE; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_write_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_seek_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_seek_request_s *req, size_t reqlen) +{ + struct userfs_seek_response_s resp; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen != sizeof(struct userfs_seek_request_s)) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->seek != NULL); + resp.ret = info->userops->seek(info->volinfo, req->openinfo, req->offset, + req->whence); + + /* Send the response */ + + resp.resp = USERFS_RESP_SEEK; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_seek_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_ioctl_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_ioctl_request_s *req, size_t reqlen) +{ + struct userfs_ioctl_response_s resp; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen != sizeof(struct userfs_ioctl_request_s)) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->ioctl != NULL); + resp.ret = info->userops->ioctl(info->volinfo, req->openinfo, req->cmd, + req->arg); + + /* Send the response */ + + resp.resp = USERFS_RESP_IOCTL; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_ioctl_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_sync_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_sync_request_s *req, size_t reqlen) +{ + struct userfs_sync_response_s resp; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen != sizeof(struct userfs_sync_request_s)) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->sync != NULL); + resp.ret = info->userops->sync(info->volinfo, req->openinfo); + + /* Send the response */ + + resp.resp = USERFS_RESP_SYNC; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_sync_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_dup_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_dup_request_s *req, size_t reqlen) +{ + struct userfs_dup_response_s resp; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen != sizeof(struct userfs_dup_request_s)) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->dup != NULL); + resp.ret = info->userops->dup(info->volinfo, req->openinfo, &resp.openinfo); + + /* Send the response */ + + resp.resp = USERFS_RESP_DUP; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_dup_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_fstat_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_fstat_request_s *req, size_t reqlen) +{ + struct userfs_fstat_response_s resp; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen != sizeof(struct userfs_fstat_request_s)) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->fstat != NULL); + resp.ret = info->userops->fstat(info->volinfo, req->openinfo, &resp.buf); + + /* Send the response */ + + resp.resp = USERFS_RESP_FSTAT; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_fstat_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_truncate_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_truncate_request_s *req, size_t reqlen) +{ + struct userfs_truncate_response_s resp; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen != sizeof(struct userfs_truncate_request_s)) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->truncate != NULL); + resp.ret = info->userops->truncate(info->volinfo, req->openinfo, req->length); + + /* Send the response */ + + resp.resp = USERFS_RESP_FSTAT; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_truncate_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_opendir_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_opendir_request_s *req, size_t reqlen) +{ + struct userfs_opendir_response_s resp; + int pathlen; + size_t expected; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen < SIZEOF_USERFS_OPENDIR_REQUEST_S(0)) + { + return -EINVAL; + } + + pathlen = strlen(req->relpath); + if (pathlen > info->mxwrite) + { + return -EINVAL; + } + + expected = SIZEOF_USERFS_OPENDIR_REQUEST_S(pathlen); + if (expected >= reqlen) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->opendir != NULL); + resp.ret = info->userops->opendir(info->volinfo, req->relpath, &resp.dir); + + /* Send the response */ + + resp.resp = USERFS_RESP_OPENDIR; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_opendir_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_closedir_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_closedir_request_s *req, size_t reqlen) +{ + struct userfs_closedir_response_s resp; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen != sizeof(struct userfs_closedir_request_s)) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->closedir != NULL); + resp.ret = info->userops->closedir(info->volinfo, req->dir); + + /* Send the response */ + + resp.resp = USERFS_RESP_CLOSEDIR; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_closedir_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_readdir_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_readdir_request_s *req, size_t reqlen) +{ + struct userfs_readdir_response_s resp; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen != sizeof(struct userfs_readdir_request_s)) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->readdir != NULL); + resp.ret = info->userops->readdir(info->volinfo, req->dir, &resp.entry); + + /* Send the response */ + + resp.resp = USERFS_RESP_READDIR; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_readdir_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_rewinddir_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_rewinddir_request_s *req, size_t reqlen) +{ + struct userfs_rewinddir_response_s resp; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen != sizeof(struct userfs_rewinddir_request_s)) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->rewinddir != NULL); + resp.ret = info->userops->rewinddir(info->volinfo, req->dir); + + /* Send the response */ + + resp.resp = USERFS_RESP_REWINDDIR; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_rewinddir_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_statfs_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_statfs_request_s *req, size_t reqlen) +{ + struct userfs_statfs_response_s resp; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen != sizeof(struct userfs_statfs_request_s)) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->statfs != NULL); + resp.ret = info->userops->statfs(info->volinfo, &resp.buf); + + /* Send the response */ + + resp.resp = USERFS_RESP_STATFS; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_statfs_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_unlink_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_unlink_request_s *req, size_t reqlen) +{ + struct userfs_unlink_response_s resp; + int pathlen; + size_t expected; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen < SIZEOF_USERFS_UNLINK_REQUEST_S(0)) + { + return -EINVAL; + } + + pathlen = strlen(req->relpath); + if (pathlen > info->mxwrite) + { + return -EINVAL; + } + + expected = SIZEOF_USERFS_UNLINK_REQUEST_S(pathlen); + if (expected >= reqlen) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->unlink != NULL); + resp.ret = info->userops->unlink(info->volinfo, req->relpath); + + /* Send the response */ + + resp.resp = USERFS_RESP_UNLINK; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_unlink_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_mkdir_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_mkdir_request_s *req, size_t reqlen) +{ + struct userfs_mkdir_response_s resp; + int pathlen; + size_t expected; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen < SIZEOF_USERFS_MKDIR_REQUEST_S(0)) + { + return -EINVAL; + } + + pathlen = strlen(req->relpath); + if (pathlen > info->mxwrite) + { + return -EINVAL; + } + + expected = SIZEOF_USERFS_MKDIR_REQUEST_S(pathlen); + if (expected >= reqlen) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->mkdir != NULL); + resp.ret = info->userops->mkdir(info->volinfo, req->relpath, req->mode); + + /* Send the response */ + + resp.resp = USERFS_RESP_MKDIR; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_mkdir_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_rmdir_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_rmdir_request_s *req, size_t reqlen) +{ + struct userfs_rmdir_response_s resp; + int pathlen; + size_t expected; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen < SIZEOF_USERFS_MKDIR_REQUEST_S(0)) + { + return -EINVAL; + } + + pathlen = strlen(req->relpath); + if (pathlen > info->mxwrite) + { + return -EINVAL; + } + + expected = SIZEOF_USERFS_MKDIR_REQUEST_S(pathlen); + if (expected >= reqlen) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->rmdir != NULL); + resp.ret = info->userops->rmdir(info->volinfo, req->relpath); + + /* Send the response */ + + resp.resp = USERFS_RESP_RMDIR; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_rmdir_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_rename_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_rename_request_s *req, size_t reqlen) +{ + struct userfs_rename_response_s resp; + FAR char *newrelpath; + unsigned int newoffset; + int oldpathlen; + int newpathlen; + size_t expected; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen < SIZEOF_USERFS_RENAME_REQUEST_S(0,0)) + { + return -EINVAL; + } + + oldpathlen = strlen(req->oldrelpath); + newoffset = req->newoffset; + + if (oldpathlen >= newoffset) + { + return -EINVAL; + } + + newrelpath = &req->oldrelpath[newoffset]; + newpathlen = strlen(newrelpath); + + if ((newpathlen + newoffset) > info->mxwrite) + { + return -EINVAL; + } + + expected = SIZEOF_USERFS_RENAME_REQUEST_S(newoffset, newpathlen); + if (expected >= reqlen) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->rename != NULL); + resp.ret = info->userops->rename(info->volinfo, req->oldrelpath, + newrelpath); + + /* Send the response */ + + resp.resp = USERFS_RESP_RENAME; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_rename_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_stat_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_stat_request_s *req, size_t reqlen) +{ + struct userfs_stat_response_s resp; + int pathlen; + size_t expected; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen < SIZEOF_USERFS_STAT_REQUEST_S(0)) + { + return -EINVAL; + } + + pathlen = strlen(req->relpath); + if (pathlen > info->mxwrite) + { + return -EINVAL; + } + + expected = SIZEOF_USERFS_STAT_REQUEST_S(pathlen); + if (expected >= reqlen) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->stat != NULL); + resp.ret = info->userops->stat(info->volinfo, req->relpath, &resp.buf); + + /* Send the response */ + + resp.resp = USERFS_RESP_STAT; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_stat_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + return nsent < 0 ? nsent : OK; +} + +static inline int userfs_destroy_dispatch(FAR struct userfs_info_s *info, + FAR struct userfs_destroy_request_s *req, size_t reqlen) +{ + struct userfs_destroy_response_s resp; + ssize_t nsent; + + /* Verify the request size */ + + if (reqlen != sizeof(struct userfs_destroy_request_s)) + { + return -EINVAL; + } + + /* Dispatch the request */ + + DEBUGASSERT(info->userops != NULL && info->userops->destroy != NULL); + resp.ret = info->userops->destroy(info->volinfo); + + /* Send the response */ + + resp.resp = USERFS_RESP_DESTROY; + nsent = sendto(info->sockfd, &resp, + sizeof(struct userfs_destroy_response_s), + 0, (FAR struct sockaddr *)&info->client, + sizeof(struct sockaddr_in)); + if (nsent < 0) + { + int ret = -errno; + ferr("ERROR: sendto failed: %d\n", ret); + return ret; + } + + /* Speical case of resp.ret indicates an error, the destruction was + * refused. So we need to return success in this case so that we + * continue processing requests. + */ + + return resp.ret < 0 ? OK : -ENOTCONN; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: userfs_run + * + * Description: + * Start the UserFS server on the current thread. This function will mount + * the UserFS file system and will not return until that file system has + * been unmounted. + * + * userfs_run() implements the UserFS server. It performs there operations: + * + * 1. It configures and creates the UserFS file system and + * 2. Mounts the user file system at the provide mount point path. + * 2. Receives file system requests on the LocalHost socket with + * server port 0x83nn where nn is the same as above, + * 3. Received file system requests are marshaled and dispatch to the + * user file system via callbacks to the operations provided by + * "userops", and + * 3. Returns file system responses generated by the callbacks to the + * LocalHost client socket. + * + * NOTE: This is a user function that is implemented as part of the + * NuttX C library and is intended to be called by appliation logic. + * + * Input parameters: + * mountpt - Mountpoint path + * userops - The caller operations that implement the file system + * interface. + * volinfo - Private volume data that will be provided in all struct + * userfs_operations_s methods. + * mxwrite - The max size of a write data + * + * Returned Value: + * This function does not return unless the file system is unmounted (OK) + * or unless an error is encountered. In the event of an error, the + * returned value is a negated errno value indicating the nature of the + * error. + * + ****************************************************************************/ + +int userfs_run(FAR const char *mountpt, + FAR const struct userfs_operations_s *userops, + FAR void *volinfo, size_t mxwrite) +{ + FAR struct userfs_info_s *info; + FAR struct userfs_config_s config; + struct sockaddr_in server; + unsigned int iolen; + socklen_t addrlen; + ssize_t nread; + int ret; + + DEBUGASSERT(mountpt != NULL && userops != NULL && mxwrite <= UINT16_MAX); + DEBUGASSERT(mxwrite > 0 && mxwrite <= (UINT16_MAX - USERFS_REQ_MAXSIZE)); + + /* Allocate a state structure with an I/O buffer to receive UserFS requests */ + + iolen = USERFS_REQ_MAXSIZE + mxwrite; + info = (FAR struct userfs_info_s *)zalloc(SIZEOF_USERFS_INFO_S(iolen)); + if (info == NULL) + { + ferr("ERROR: Failed to allocate state structure\n"); + return -ENOMEM; + } + + /* Initialize the state structure */ + + info->userops = userops; + info->volinfo = volinfo; + info->iolen = iolen; + info->mxwrite = mxwrite; + + /* Create the UserFS configuration that will be provided as optional + * data when the UserFS is mounted. + */ + + config.mxwrite = mxwrite; + config.portno = userfs_server_portno(); + + /* Mounts the user file system at the provided mount point path. */ + + ret = mount(NULL, mountpt, "userfs", 0, (FAR const void *)&config); + if (ret < 0) + { + ret = -get_errno(); + ferr("ERROR: mount() failed: %d\n", ret); + goto errout_with_info; + } + + /* Create a new LocalHost UDP server socket */ + + info->sockfd = socket(PF_INET, SOCK_DGRAM, 0); + if (info->sockfd < 0) + { + ret = -get_errno(); + ferr("ERROR: socket() failed: %d\n", ret); + goto errout_with_info; + } + + /* Bind the socket to a server port number */ + + server.sin_family = AF_INET; + server.sin_port = htons(config.portno); + server.sin_addr.s_addr = HTONL(INADDR_LOOPBACK); + + ret = bind(info->sockfd, (struct sockaddr *)&server, + sizeof(struct sockaddr_in)); + if (ret < 0) + { + ret = -get_errno(); + ferr("ERROR: bind() failed: %d\n", ret); + goto errout_with_sockfd; + } + + /* Receive file system requests on the POSIX message queue as long + * as the mount persists. + */ + + do + { + /* Receive the next file system request */ + + finfo("Receiving up %u bytes\n", info->iolen); + addrlen = sizeof(struct sockaddr_in); + nread = recvfrom(info->sockfd, info->iobuffer, info->iolen, 0, + (FAR struct sockaddr *)&info->client, + &addrlen); + if (nread < 0) + { + ret = -get_errno(); + ferr("ERROR: recvfrom failed: %d\n", ret); + goto errout_with_sockfd; + } + + DEBUGASSERT(addrlen == sizeof(struct sockaddr_in)); + + /* Process the request according to its request ID */ + + DEBUGASSERT(nread >= sizeof(uint8_t)); + switch (*info->iobuffer) + { + case USERFS_REQ_OPEN: + ret = userfs_open_dispatch(info, + (FAR struct userfs_open_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_CLOSE: + ret = userfs_close_dispatch(info, + (FAR struct userfs_close_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_READ: + ret = userfs_read_dispatch(info, + (FAR struct userfs_read_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_WRITE: + ret = userfs_write_dispatch(info, + (FAR struct userfs_write_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_SEEK: + ret = userfs_seek_dispatch(info, + (FAR struct userfs_seek_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_IOCTL: + ret = userfs_ioctl_dispatch(info, + (FAR struct userfs_ioctl_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_SYNC: + ret = userfs_sync_dispatch(info, + (FAR struct userfs_sync_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_DUP: + ret = userfs_dup_dispatch(info, + (FAR struct userfs_dup_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_FSTAT: + ret = userfs_fstat_dispatch(info, + (FAR struct userfs_fstat_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_TRUNCATE: + ret = userfs_truncate_dispatch(info, + (FAR struct userfs_truncate_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_OPENDIR: + ret = userfs_opendir_dispatch(info, + (FAR struct userfs_opendir_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_CLOSEDIR: + ret = userfs_closedir_dispatch(info, + (FAR struct userfs_closedir_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_READDIR: + ret = userfs_readdir_dispatch(info, + (FAR struct userfs_readdir_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_REWINDDIR: + ret = userfs_rewinddir_dispatch(info, + (FAR struct userfs_rewinddir_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_STATFS: + ret = userfs_statfs_dispatch(info, + (FAR struct userfs_statfs_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_UNLINK: + ret = userfs_unlink_dispatch(info, + (FAR struct userfs_unlink_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_MKDIR: + ret = userfs_mkdir_dispatch(info, + (FAR struct userfs_mkdir_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_RMDIR: + ret = userfs_rmdir_dispatch(info, + (FAR struct userfs_rmdir_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_RENAME: + ret = userfs_rename_dispatch(info, + (FAR struct userfs_rename_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_STAT: + ret = userfs_stat_dispatch(info, + (FAR struct userfs_stat_request_s *)info->iobuffer, nread); + break; + + case USERFS_REQ_DESTROY: + ret = userfs_destroy_dispatch(info, + (FAR struct userfs_destroy_request_s *)info->iobuffer, nread); + break; + + default: + ferr("ERROR: Unrecognized request received: %u\n", *info->iobuffer); + ret = -EINVAL; + break; + } + } + while (ret == OK); + + /* Close the LocalHost socket */ + +errout_with_sockfd: + close(info->sockfd); + + /* Free the IO Buffer */ + +errout_with_info: + free(info); + return ret; +} diff --git a/libc/zoneinfo/README.txt b/libc/zoneinfo/README.txt index 9ceb5de809353fb44056004d2a856d053785f063..406d1cce58c363fc5176e40ac0259f5469db0753 100644 --- a/libc/zoneinfo/README.txt +++ b/libc/zoneinfo/README.txt @@ -1,4 +1,4 @@ -apps/system/zoninfo/README.txt +apps/system/zoneinfo/README.txt Author: Gregory Nutt Directory Contents diff --git a/libnx/Kconfig b/libnx/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..205d4d07c7c1bdc5a770b321d6b16c155f1a0479 --- /dev/null +++ b/libnx/Kconfig @@ -0,0 +1,10 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source libnx/nx/Kconfig +source libnx/nxfonts/Kconfig +source libnx/nxglib/Kconfig +source libnx/nxmu/Kconfig +source libnx/nxtk/Kconfig diff --git a/libnx/Makefile b/libnx/Makefile index af0da579f4271509d685f5fef996574384c1ed22..a34df4248996be693ac44d652b10eda7a3512b85 100644 --- a/libnx/Makefile +++ b/libnx/Makefile @@ -1,7 +1,7 @@ ############################################################################ # libnx/Makefile # -# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Copyright (C) 2013, 2017 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -37,7 +37,7 @@ # CFLAGS -ifeq ($(CONFIG_BUILD_PROTECTED),y) +ifneq ($(CONFIG_BUILD_FLAT),y) ifeq ($(CONFIG_WINDOWS_NATIVE),y) KDEFINE = ${shell $(TOPDIR)\tools\define.bat "$(CC)" __KERNEL__} else @@ -261,11 +261,11 @@ endif # Dependencies .depend: Makefile gensources $(SRCS) -ifeq ($(CONFIG_BUILD_PROTECTED),y) +ifeq ($(CONFIG_BUILD_FLAT),y) + $(Q) $(MKDEP) --obj-path bin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make_bin.dep +else $(Q) $(MKDEP) --obj-path ubin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make_ubin.dep $(Q) $(MKDEP) --obj-path kbin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) $(KDEFINE) -- $(SRCS) >Make_kbin.dep -else - $(Q) $(MKDEP) --obj-path bin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make_bin.dep endif $(Q) touch $@ diff --git a/libnx/nx/Kconfig b/libnx/nx/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..f72f3c094ce4c8f031445c514c343376e4e79e75 --- /dev/null +++ b/libnx/nx/Kconfig @@ -0,0 +1,4 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# diff --git a/libnx/nxfonts/Kconfig b/libnx/nxfonts/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..5acc2a8348ab3723ec288b9f6e5cd747a2cf7c3f --- /dev/null +++ b/libnx/nxfonts/Kconfig @@ -0,0 +1,407 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +config NXFONTS + bool "Bitmap Font Support" + default n + select NXGLIB + ---help--- + Enable support for bitmap fonts, the fonter rendering library, and a + font cache. + +menu "Font Selections" + depends on NXFONTS + +config NXFONTS_CHARBITS + int "Bits in Character Set" + default 7 + range 7 8 + ---help--- + The number of bits in the character set. Current options are only 7 and 8. + The default is 7. + +config NXFONT_MONO5X8 + bool "Mono 5x8" + default n + ---help--- + Tiny mono-spaced 5x8 font (font ID FONTID_MONO5X8 = 18) + +config NXFONT_SANS17X22 + bool "Sans 17x22" + default n + ---help--- + This option enables support for a tiny, 17x22 san serif font + (font ID FONTID_SANS17X22 == 14). + +config NXFONT_SANS20X26 + bool "Sans 20x26" + default n + ---help--- + This option enables support for a tiny, 20x26 san serif font + (font ID FONTID_SANS20X26 == 15). + +config NXFONT_SANS23X27 + bool "Sans 23x27" + default n + ---help--- + This option enables support for a tiny, 23x27 san serif font + (font ID FONTID_SANS23X27 == 1). + +config NXFONT_SANS22X29 + bool "Sans 22x29" + default n + ---help--- + This option enables support for a small, 22x29 san serif font + (font ID FONTID_SANS22X29 == 2). + +config NXFONT_SANS28X37 + bool "Sans 28x37" + default n + ---help--- + This option enables support for a medium, 28x37 san serif font + (font ID FONTID_SANS28X37 == 3). + +config NXFONT_SANS39X48 + bool "Sans 39x48" + default n + ---help--- + This option enables support for a large, 39x48 san serif font + (font ID FONTID_SANS39X48 == 4). + +config NXFONT_SANS17X23B + bool "Sans 17x23 Bold" + default n + ---help--- + This option enables support for a tiny, 17x23 san serif bold font + (font ID FONTID_SANS17X23B == 16). + +config NXFONT_SANS20X27B + bool "Sans 20x27 Bold" + default n + ---help--- + This option enables support for a tiny, 20x27 san serif bold font + (font ID FONTID_SANS20X27B == 17). + +config NXFONT_SANS22X29B + bool "Sans 22x29 Bold" + default n + ---help--- + This option enables support for a small, 22x29 san serif bold font + (font ID FONTID_SANS22X29B == 5). + +config NXFONT_SANS28X37B + bool "Sans 28x37 Bold" + default n + ---help--- + This option enables support for a medium, 28x37 san serif bold font + (font ID FONTID_SANS28X37B == 6). + +config NXFONT_SANS40X49B + bool "Sans 40x49 Bold" + default n + ---help--- + This option enables support for a large, 40x49 san serif bold font + (font ID FONTID_SANS40X49B == 7). + +config NXFONT_SERIF22X29 + bool "Serif 22x29" + default n + ---help--- + This option enables support for a small, 22x29 font (with serifs) + (font ID FONTID_SERIF22X29 == 8). + +config NXFONT_SERIF29X37 + bool "Serif 29x37" + default n + ---help--- + This option enables support for a medium, 29x37 font (with serifs) + (font ID FONTID_SERIF29X37 == 9). + +config NXFONT_SERIF38X48 + bool "Serif 38x48" + default n + ---help--- + This option enables support for a large, 38x48 font (with serifs) + (font ID FONTID_SERIF38X48 == 10). + +config NXFONT_SERIF22X28B + bool "Serif 22x28 Bold" + default n + ---help--- + This option enables support for a small, 27x38 bold font (with serifs) + (font ID FONTID_SERIF22X28B == 11). + +config NXFONT_SERIF27X38B + bool "Serif 27x38 Bold" + default n + ---help--- + This option enables support for a medium, 27x38 bold font (with serifs) + (font ID FONTID_SERIF27X38B == 12). + +config NXFONT_SERIF38X49B + bool "Serif 38x49 Bold" + default n + ---help--- + This option enables support for a large, 38x49 bold font (with serifs) + (font ID FONTID_SERIF38X49B == 13). + +config NXFONT_PIXEL_UNICODE + bool "Pixel UniCode" + default n + ---help--- + This option enables support for a small LCD, The "Pixel UniCode" + (font ID FONTID_PIXEL_UNICODE == 19). + +config NXFONT_PIXEL_LCD_MACHINE + bool "Pixel lcd machine" + default n + ---help--- + This option enables support for a small LCD, The "Pixel lcd machine" + (font ID FONTID_PIXEL_LCD_MACHINE == 20). + +config NXFONT_X11_MISC_FIXED_4X6 + bool "x11 misc fixed 4x6" + default n + ---help--- + This option enables support for a "x11-misc-fixed-4x6". + (font ID FONTID_X11_MISC_FIXED_4X6 == 21). + +config NXFONT_X11_MISC_FIXED_5X7 + bool "x11 misc fixed 5x7" + default n + ---help--- + This option enables support for a "x11-misc-fixed-5x7". + (font ID FONTID_X11_MISC_FIXED_5X7 == 22). + +config NXFONT_X11_MISC_FIXED_5X8 + bool "x11 misc fixed 5x8" + default n + ---help--- + This option enables support for a "x11-misc-fixed-5x8". + (font ID FONTID_X11_MISC_FIXED_5X8 == 23). + +config NXFONT_X11_MISC_FIXED_6X9 + bool "x11 misc fixed 6x9" + default n + ---help--- + This option enables support for a "x11-misc-fixed-6x9". + (font ID FONTID_X11_MISC_FIXED_6X9 == 24). + +config NXFONT_X11_MISC_FIXED_6X10 + bool "x11 misc fixed 6x10" + default n + ---help--- + This option enables support for a "x11-misc-fixed-6x10". + (font ID FONTID_X11_MISC_FIXED_6X10 == 25). + +config NXFONT_X11_MISC_FIXED_6X12 + bool "x11 misc fixed 6x12" + default n + ---help--- + This option enables support for a "x11-misc-fixed-6x12". + (font ID FONTID_X11_MISC_FIXED_6X12 == 26). + +config NXFONT_X11_MISC_FIXED_6X13 + bool "x11 misc fixed 6x13" + default n + ---help--- + This option enables support for a "x11-misc-fixed-6x13". + (font ID FONTID_X11_MISC_FIXED_6X13 == 27). + +config NXFONT_X11_MISC_FIXED_6X13B + bool "x11 misc fixed 6x13B" + default n + ---help--- + This option enables support for a "x11-misc-fixed-6x13B". + (font ID FONTID_X11_MISC_FIXED_6X13B == 28). + +config NXFONT_X11_MISC_FIXED_6X13O + bool "x11 misc fixed 6x13O" + default n + ---help--- + This option enables support for a "x11-misc-fixed-6x13O". + (font ID FONTID_X11_MISC_FIXED_6X13O == 29). + +config NXFONT_X11_MISC_FIXED_7X13 + bool "x11 misc fixed 7x13" + default n + ---help--- + This option enables support for a "x11-misc-fixed-7x13". + (font ID FONTID_X11_MISC_FIXED_7X13 == 30). + +config NXFONT_X11_MISC_FIXED_7X13B + bool "x11 misc fixed 7x13B" + default n + ---help--- + This option enables support for a "x11-misc-fixed-7x13B". + (font ID FONTID_X11_MISC_FIXED_7X13B == 31). + +config NXFONT_X11_MISC_FIXED_7X13O + bool "x11 misc fixed 7x13O" + default n + ---help--- + This option enables support for a "x11-misc-fixed-7x13O". + (font ID FONTID_X11_MISC_FIXED_7X13O == 32). + +config NXFONT_X11_MISC_FIXED_7X14 + bool "x11 misc fixed 7x14" + default n + ---help--- + This option enables support for a "x11-misc-fixed-7x14". + (font ID FONTID_X11_MISC_FIXED_7X14 == 33). + +config NXFONT_X11_MISC_FIXED_7X14B + bool "x11 misc fixed 7x14B" + default n + ---help--- + This option enables support for a "x11-misc-fixed-7x14B". + (font ID FONTID_X11_MISC_FIXED_7X14B == 34). + +config NXFONT_X11_MISC_FIXED_8X13 + bool "x11 misc fixed 8x13" + default n + ---help--- + This option enables support for a "x11-misc-fixed-8x13". + (font ID FONTID_X11_MISC_FIXED_8X13 == 35). + +config NXFONT_X11_MISC_FIXED_8X13B + bool "x11 misc fixed 8x13B" + default n + ---help--- + This option enables support for a "x11-misc-fixed-8x13B". + (font ID FONTID_X11_MISC_FIXED_8X13B == 36). + +config NXFONT_X11_MISC_FIXED_8X13O + bool "x11 misc fixed 8x13O" + default n + ---help--- + This option enables support for a "x11-misc-fixed-8x13O". + (font ID FONTID_X11_MISC_FIXED_8X13O == 37). + +config NXFONT_X11_MISC_FIXED_9X15 + bool "x11 misc fixed 9x15" + default n + ---help--- + This option enables support for a "x11-misc-fixed-9x15". + (font ID FONTID_X11_MISC_FIXED_9X15 == 38). + +config NXFONT_X11_MISC_FIXED_9X15B + bool "x11 misc fixed 9x15B" + default n + ---help--- + This option enables support for a "x11-misc-fixed-9x15B". + (font ID FONTID_X11_MISC_FIXED_9X15B == 39). + +config NXFONT_X11_MISC_FIXED_9X18 + bool "x11 misc fixed 9x18" + default n + ---help--- + This option enables support for a "x11-misc-fixed-9x18". + (font ID FONTID_X11_MISC_FIXED_9X18 == 40). + +config NXFONT_X11_MISC_FIXED_9X18B + bool "x11 misc fixed 9x18B" + default n + ---help--- + This option enables support for a "x11-misc-fixed-9x18B". + (font ID FONTID_X11_MISC_FIXED_9X18B == 41). + +config NXFONT_X11_MISC_FIXED_10X20 + bool "x11 misc fixed 10x20" + default n + ---help--- + This option enables support for a "x11-misc-fixed-10x20". + (font ID FONTID_X11_MISC_FIXED_10X20 == 42). + +config NXFONT_TOM_THUMB_4X6 + bool "Tom Thumb Monospace 4x6" + default n + ---help--- + This option enables support for a small, 3x5 font (with blank space + padding to 4x6) (font ID FONTID_TOM_THUMB_4X6 == 43). + +endmenu + +# NOTE the remaining selections all shadow NX-configurations of a similar +# name. If CONFIG_NX is enabled, then these options should exactly match +# the NX settings. The shadow copies allow the fonts to be configured and +# used on other contexts when the NX server is not initialized. + +menu "Font Cache Pixel Depths" + +config NXFONTS_DISABLE_1BPP + bool "Disable 1 BPP" + default y if NX_DISABLE_1BPP + default n if !NX_DISABLE_1BPP + ---help--- + NX supports a variety of pixel depths. You can save some memory by disabling + support for unused color depths. The selection disables support for 1BPP + pixel depth. + +config NXFONTS_DISABLE_2BPP + bool "Disable 2 BPP" + default y if NX_DISABLE_2BPP + default n if !NX_DISABLE_2BPP + ---help--- + NX supports a variety of pixel depths. You can save some memory by disabling + support for unused color depths. The selection disables support for 2BPP + pixel depth. + +config NXFONTS_DISABLE_4BPP + bool "Disable 4 BPP" + default y if NX_DISABLE_4BPP + default n if !NX_DISABLE_4BPP + ---help--- + NX supports a variety of pixel depths. You can save some memory by disabling + support for unused color depths. The selection disables support for 4BPP + pixel depth. + +config NXFONTS_DISABLE_8BPP + bool "Disable 8 BPP" + default y if NX_DISABLE_8BPP + default n if !NX_DISABLE_8BPP + ---help--- + NX supports a variety of pixel depths. You can save some memory by disabling + support for unused color depths. The selection disables support for 8BPP + pixel depth. + +config NXFONTS_DISABLE_16BPP + bool "Disable 16 BPP" + default y if NX_DISABLE_8BPP + default n if !NX_DISABLE_8BPP + ---help--- + NX supports a variety of pixel depths. You can save some memory by disabling + support for unused color depths. The selection disables support for 16BPP + pixel depth. + +config NXFONTS_DISABLE_24BPP + bool "Disable 24 BPP" + default y if NX_DISABLE_24BPP + default n if !NX_DISABLE_24BPP + ---help--- + NX supports a variety of pixel depths. You can save some memory by disabling + support for unused color depths. The selection disables support for 24BPP + pixel depth. + +config NXFONTS_DISABLE_32BPP + bool "Disable 32 BPP" + default y if NX_DISABLE_32BPP + default n if !NX_DISABLE_32BPP + ---help--- + NX supports a variety of pixel depths. You can save some memory by disabling + support for unused color depths. The selection disables support for 32BPP + pixel depth. + +config NXFONTS_PACKEDMSFIRST + bool "Packed MS First" + default y if !NX || NX_PACKEDMSFIRST + default n if NX && !NX_PACKEDMSFIRST + select LCD_PACKEDMSFIRST if LCD + ---help--- + If a pixel depth of less than 8-bits is used, then NX needs to know if the + pixels pack from the MS to LS or from LS to MS + +endmenu + diff --git a/libnx/nxfonts/Make.defs b/libnx/nxfonts/Make.defs index fee5f77baa554a2f1dc751cc5ddb08cb77a90832..fa3ddfee9e7d0100dab76de9d97efa66d5e9168b 100644 --- a/libnx/nxfonts/Make.defs +++ b/libnx/nxfonts/Make.defs @@ -35,7 +35,7 @@ # Expose NXFONT interfaces to applications -ifeq ($(CONFIG_NX),y) +ifeq ($(CONFIG_NXFONTS),y) CSRCS += nxfonts_getfont.c nxfonts_cache.c CSRCS += nxfonts_convert_1bpp.c nxfonts_convert_2bpp.c diff --git a/libnx/nxfonts/README.txt b/libnx/nxfonts/README.txt new file mode 100644 index 0000000000000000000000000000000000000000..457d290fd056deabcadf308ad4b97638f0c8f0e5 --- /dev/null +++ b/libnx/nxfonts/README.txt @@ -0,0 +1,218 @@ +README +^^^^^^ + +This directory contains font support for NuttX. The contents of this directory +are only build if CONFIG_NXFONTS is defined in the NuttX configuration file. + +Installing New Fonts +^^^^^^^^^^^^^^^^^^^^ + + There is a tool called bdf-converter in the directory tools/. The bdf-converter + program be used to convert fonts in Bitmap Distribution Format (BDF) + into fonts that can be used in the NX graphics system. + + Below are general instructions for creating and installing a new font + in the NX graphic system: + + 1. Locate a font in BDF format, + 2. Use the bdf-converter program to convert the BDF font to the NuttX + font format. This will result in a C header file containing + defintions. That header file should be installed at, for example, + graphics/nxfonts/nxfonts_myfont.h. + + Create a new NuttX configuration variable. For example, suppose + you define the following variable: CONFIG_NXFONT_MYFONT. Then + you would need to: + + 3. Define CONFIG_NXFONT_MYFONT=y in your NuttX configuration file. + + A font ID number has to be assigned for each new font. The font ID + is defined in the file include/nuttx/nx/nxfonts.h. Those definitions + have to be extended to support your new font. Look at how the font ID + enabled by CONFIG_NXFONT_SANS23X27 is defined and add an ID for your + new font in a similar fashion: + + 4. include/nuttx/nx/nxfonts.h. Add you new font as a possible system + default font: + + #if defined(CONFIG_NXFONT_SANS23X27) + # define NXFONT_DEFAULT FONTID_SANS23X27 + #elif defined(CONFIG_NXFONT_MYFONT) + # define NXFONT_DEFAULT FONTID_MYFONT + #endif + + Then define the actual font ID. Make sure that the font ID value + is unique: + + enum nx_fontid_e + { + FONTID_DEFAULT = 0 /* The default font */ + #ifdef CONFIG_NXFONT_SANS23X27 + , FONTID_SANS23X27 = 1 /* The 23x27 sans serif font */ + #endif + #ifdef CONFIG_NXFONT_MYFONT + , FONTID_MYFONT = 2 /* My shiny, new font */ + #endif + ... + + New Add the font to the NX build system. There are several files that + you have to modify to to this. Look how the build system uses the + font CONFIG_NXFONT_SANS23X27 for examaples: + + 5. nuttx/graphics/Makefile. This file needs logic to auto-generate + a C source file from the header file that you generated with the + the bdf-converter program. Notice NXFONTS_FONTID=2; this must be + set to the same font ID value that you defined in the + include/nuttx/nx/nxfonts.h file. + + genfontsources: + ifeq ($(CONFIG_NXFONT_SANS23X27),y) + @$(MAKE) -C nxfonts -f Makefile.sources TOPDIR=$(TOPDIR) NXFONTS_FONTID=1 EXTRADEFINES=$(EXTRADEFINES) + endif + ifeq ($(CONFIG_NXFONT_MYFONT),y) + @$(MAKE) -C nxfonts -f Makefile.sources TOPDIR=$(TOPDIR) NXFONTS_FONTID=2 EXTRADEFINES=$(EXTRADEFINES) + endif + + 6. nuttx/graphics/nxfonts/Make.defs. Set the make variable NXFSET_CSRCS. + NXFSET_CSRCS determines the name of the font C file to build when + NXFONTS_FONTID=2: + + ifeq ($(CONFIG_NXFONT_SANS23X27),y) + NXFSET_CSRCS += nxfonts_bitmaps_sans23x27.c + endif + ifeq ($(CONFIG_NXFONT_MYFONT),y) + NXFSET_CSRCS += nxfonts_bitmaps_myfont.c + endif + + 7. nuttx/graphics/nxfonts/Makefile.sources. This is the Makefile used + in step 5 that will actually generate the font C file. So, given + your NXFONTS_FONTID=2, it needs to determine a prefix to use for + auto-generated variable and function names and (again) the name of + the autogenerated file to create (this must be the same name that + was used in nuttx/graphics/nxfonts/Make.defs): + + ifeq ($(NXFONTS_FONTID),1) + NXFONTS_PREFIX := g_sans23x27_ + GEN_CSRC = nxfonts_bitmaps_sans23x27.c + endif + ifeq ($(NXFONTS_FONTID),2) + NXFONTS_PREFIX := g_myfont_ + GEN_CSRC = nxfonts_bitmaps_myfont.c + endif + + 8. graphics/nxfonts/nxfonts_bitmaps.c. This is the file that contains + the generic font structures. It is used as a "template" file by + nuttx/graphics/nxfonts/Makefile.sources to create your customized + font data set. + + #if NXFONTS_FONTID == 1 + # include "nxfonts_sans23x27.h" + #elif NXFONTS_FONTID == 2 + # include "nxfonts_myfont.h" + #else + # error "No font ID specified" + #endif + + Where nxfonts_myfont.h is the NuttX font file that we generated in + step 2 using the bdf-converter tool. + + 9. graphics/nxfonts/nxfonts_getfont.c. Finally, we need to extend the + logic that does the run-time font lookups so that can find our new + font. The lookup function is NXHANDLE nxf_getfonthandle(enum nx_fontid_e fontid). + The new font information needs to be added to data structures used by + that function: + + #ifdef CONFIG_NXFONT_SANS23X27 + extern const struct nx_fontpackage_s g_sans23x27_package; + #endif + #ifdef CONFIG_NXFONT_MYFONT + extern const struct nx_fontpackage_s g_myfont_package; + #endif + + static FAR const struct nx_fontpackage_s *g_fontpackages[] = + { + #ifdef CONFIG_NXFONT_SANS23X27 + &g_sans23x27_package, + #endif + #ifdef CONFIG_NXFONT_MYFONT + &g_myfont_package, + #endif + NULL + }; + +Configuration Settings +^^^^^^^^^^^^^^^^^^^^^^ + +NxFonts +------- + +CONFIG_NXFONTS + Enables font support +CONFIG_NXFONTS_CHARBITS + The number of bits in the character set. Current options are only 7 and 8. + The default is 7. +CONFIG_NXFONTS_DISABLE_1BPP, CONFIG_NXFONTS_DISABLE_2BPP, +CONFIG_NXFONTS_DISABLE_4BPP, CONFIG_NXFONTS_DISABLE_8BPP, +CONFIG_NXFONTS_DISABLE_16BPP, CONFIG_NXFONTS_DISABLE_24BPP, and +CONFIG_NXFONTS_DISABLE_32BPP + NX supports a variety of pixel depths. You can save some memory by disabling + support for unused color depths. +CONFIG_NXFONTS_PACKEDMSFIRST + If a pixel depth of less than 8-bits is used, then NX needs to know if the + pixels pack from the MS to LS or from LS to MS + +Font Selections +--------------- + +CONFIG_NXFONT_SANS17X22 + This option enables support for a tiny, 17x22 san serif font + (font ID FONTID_SANS17X22 == 14). +CONFIG_NXFONT_SANS20X26 + This option enables support for a tiny, 20x26 san serif font + (font ID FONTID_SANS20X26 == 15). +CONFIG_NXFONT_SANS23X27 + This option enables support for a tiny, 23x27 san serif font + (font ID FONTID_SANS23X27 == 1). +CONFIG_NXFONT_SANS22X29 + This option enables support for a small, 22x29 san serif font + (font ID FONTID_SANS22X29 == 2). +CONFIG_NXFONT_SANS28X37 + This option enables support for a medium, 28x37 san serif font + (font ID FONTID_SANS28X37 == 3). +CONFIG_NXFONT_SANS39X48 + This option enables support for a large, 39x48 san serif font + (font ID FONTID_SANS39X48 == 4). +CONFIG_NXFONT_SANS17X23B + This option enables support for a tiny, 17x23 san serif bold font + (font ID FONTID_SANS17X23B == 16). +CONFIG_NXFONT_SANS20X27B + This option enables support for a tiny, 20x27 san serif bold font + (font ID FONTID_SANS20X27B == 17). +CONFIG_NXFONT_SANS22X29B + This option enables support for a small, 22x29 san serif bold font + (font ID FONTID_SANS22X29B == 5). +CONFIG_NXFONT_SANS28X37B + This option enables support for a medium, 28x37 san serif bold font + (font ID FONTID_SANS28X37B == 6). +CONFIG_NXFONT_SANS40X49B + This option enables support for a large, 40x49 san serif bold font + (font ID FONTID_SANS40X49B == 7). +CONFIG_NXFONT_SERIF22X29 + This option enables support for a small, 22x29 font (with serifs) + (font ID FONTID_SERIF22X29 == 8). +CONFIG_NXFONT_SERIF29X37 + This option enables support for a medium, 29x37 font (with serifs) + (font ID FONTID_SERIF29X37 == 9). +CONFIG_NXFONT_SERIF38X48 + This option enables support for a large, 38x48 font (with serifs) + (font ID FONTID_SERIF38X48 == 10). +CONFIG_NXFONT_SERIF22X28B + This option enables support for a small, 27x38 bold font (with serifs) + (font ID FONTID_SERIF22X28B == 11). +CONFIG_NXFONT_SERIF27X38B + This option enables support for a medium, 27x38 bold font (with serifs) + (font ID FONTID_SERIF27X38B == 12). +CONFIG_NXFONT_SERIF38X49B + This option enables support for a large, 38x49 bold font (with serifs) + (font ID FONTID_SERIF38X49B == 13). +[REVISIT... this list is not complete] diff --git a/libnx/nxfonts/nxfonts_cache.c b/libnx/nxfonts/nxfonts_cache.c index 18ef67e262c80d462f37a3c9370bfef31ad9198b..fbf99eca87c8695a0df82950ae5f6a6f46dcd627 100644 --- a/libnx/nxfonts/nxfonts_cache.c +++ b/libnx/nxfonts/nxfonts_cache.c @@ -353,10 +353,13 @@ static inline void nxf_fillglyph(FAR struct nxfonts_fcache_s *priv, int row; int col; + UNUSED(row); /* Not used in all configurations */ + UNUSED(col); + /* Initialize the glyph memory to the background color. */ -#if !defined(CONFIG_NX_DISABLE_1BPP) || !defined(CONFIG_NX_DISABLE_2BPP) || \ - !defined(CONFIG_NX_DISABLE_4BPP) || !defined(CONFIG_NX_DISABLE_8BPP) +#if !defined(CONFIG_NXFONTS_DISABLE_1BPP) || !defined(CONFIG_NXFONTS_DISABLE_2BPP) || \ + !defined(CONFIG_NXFONTS_DISABLE_4BPP) || !defined(CONFIG_NXFONTS_DISABLE_8BPP) /* For pixel depths of 1, 2, 4, and 8, build up an 8-bit value containing * multiple background colored pixels. @@ -367,7 +370,7 @@ static inline void nxf_fillglyph(FAR struct nxfonts_fcache_s *priv, uint8_t pixel = (uint8_t)priv->bgcolor; FAR uint8_t *ptr; -#ifndef CONFIG_NX_DISABLE_1BPP +#ifndef CONFIG_NXFONTS_DISABLE_1BPP /* Pack a 1-bit pixel to 2 pixels */ if (priv->bpp < 2) @@ -379,7 +382,7 @@ static inline void nxf_fillglyph(FAR struct nxfonts_fcache_s *priv, } #endif -#if !defined(CONFIG_NX_DISABLE_1BPP) || !defined(CONFIG_NX_DISABLE_2BPP) +#if !defined(CONFIG_NXFONTS_DISABLE_1BPP) || !defined(CONFIG_NXFONTS_DISABLE_2BPP) /* Pack a 2-bit pixel to a 4-bit nibble */ if (priv->bpp < 4) @@ -391,8 +394,8 @@ static inline void nxf_fillglyph(FAR struct nxfonts_fcache_s *priv, } #endif -#if !defined(CONFIG_NX_DISABLE_1BPP) || !defined(CONFIG_NX_DISABLE_2BPP) || \ - !defined(CONFIG_NX_DISABLE_4BPP) +#if !defined(CONFIG_NXFONTS_DISABLE_1BPP) || !defined(CONFIG_NXFONTS_DISABLE_2BPP) || \ + !defined(CONFIG_NXFONTS_DISABLE_4BPP) /* Pack the 4-bit nibble into a byte */ if (priv->bpp < 8) @@ -418,7 +421,7 @@ static inline void nxf_fillglyph(FAR struct nxfonts_fcache_s *priv, else #endif -#if !defined(CONFIG_NX_DISABLE_16BPP) +#if !defined(CONFIG_NXFONTS_DISABLE_16BPP) if (priv->bpp == 16) { FAR uint16_t *ptr = (FAR uint16_t *)glyph->bitmap; @@ -436,7 +439,7 @@ static inline void nxf_fillglyph(FAR struct nxfonts_fcache_s *priv, else #endif -#ifndef CONFIG_NX_DISABLE_24BPP +#ifndef CONFIG_NXFONTS_DISABLE_24BPP if (priv->bpp == 24) { FAR uint32_t *ptr = (FAR uint32_t *)glyph->bitmap; @@ -446,7 +449,7 @@ static inline void nxf_fillglyph(FAR struct nxfonts_fcache_s *priv, pixel[0] = (uint32_t)priv->bgcolor << 8 | (uint32_t)priv->bgcolor >> 16; pixel[1] = (uint32_t)priv->bgcolor << 16 | (uint32_t)priv->bgcolor >> 8; - pixel[1] = (uint32_t)priv->bgcolor << 24 | (uint32_t)priv->bgcolor; + pixel[2] = (uint32_t)priv->bgcolor << 24 | (uint32_t)priv->bgcolor; for (row = 0; row < glyph->height; row++) { @@ -478,7 +481,7 @@ static inline void nxf_fillglyph(FAR struct nxfonts_fcache_s *priv, else #endif -#if !defined(CONFIG_NX_DISABLE_32BPP) +#if !defined(CONFIG_NXFONTS_DISABLE_32BPP) if (priv->bpp == 32) { FAR uint32_t *ptr = (FAR uint32_t *)glyph->bitmap; @@ -696,37 +699,37 @@ FCACHE nxf_cache_connect(enum nx_fontid_e fontid, switch (bpp) { -#ifndef CONFIG_NX_DISABLE_1BPP +#ifndef CONFIG_NXFONTS_DISABLE_1BPP case 1: priv->renderer = (nxf_renderer_t)nxf_convert_1bpp; break; #endif -#ifndef CONFIG_NX_DISABLE_2BPP +#ifndef CONFIG_NXFONTS_DISABLE_2BPP case 2: priv->renderer = (nxf_renderer_t)nxf_convert_2bpp; break; #endif -#ifndef CONFIG_NX_DISABLE_4BPP +#ifndef CONFIG_NXFONTS_DISABLE_4BPP case 4: priv->renderer = (nxf_renderer_t)nxf_convert_4bpp; break; #endif -#ifndef CONFIG_NX_DISABLE_8BPP +#ifndef CONFIG_NXFONTS_DISABLE_8BPP case 8: priv->renderer = (nxf_renderer_t)nxf_convert_8bpp; break; #endif -#ifndef CONFIG_NX_DISABLE_16BPP +#ifndef CONFIG_NXFONTS_DISABLE_16BPP case 16: priv->renderer = (nxf_renderer_t)nxf_convert_16bpp; break; #endif -#ifndef CONFIG_NX_DISABLE_24BPP +#ifndef CONFIG_NXFONTS_DISABLE_24BPP case 24: priv->renderer = (nxf_renderer_t)nxf_convert_24bpp; break; #endif -#ifndef CONFIG_NX_DISABLE_32BPP +#ifndef CONFIG_NXFONTS_DISABLE_32BPP case 32: priv->renderer = (nxf_renderer_t)nxf_convert_32bpp; break; diff --git a/libnx/nxfonts/nxfonts_convert.c b/libnx/nxfonts/nxfonts_convert.c index 6d3b5a71e2cb1e9eb46e97795c90c313eb4465de..19db61b27c648c7b2020708f24e2f8d3b3dc6187 100644 --- a/libnx/nxfonts/nxfonts_convert.c +++ b/libnx/nxfonts/nxfonts_convert.c @@ -104,7 +104,7 @@ #endif #if NXFONTS_BITSPERPIXEL < 8 -# ifdef CONFIG_NX_PACKEDMSFIRST +# ifdef CONFIG_NXFONTS_PACKEDMSFIRST # define NXF_INITMASK (NXF_PIXELMASK << (8 - NXFONTS_BITSPERPIXEL)) # else # define NXF_INITMASK NXF_PIXELMASK @@ -217,7 +217,7 @@ int NXF_FUNCNAME(nxf_convert,NXFONTS_SUFFIX) pixel = ((pixel & ~mask) | (mpixel & mask)); } -#ifdef CONFIG_NX_PACKEDMSFIRST +#ifdef CONFIG_NXFONTS_PACKEDMSFIRST mask >>= NXFONTS_BITSPERPIXEL; #else mask <<= NXFONTS_BITSPERPIXEL; diff --git a/libnx/nxfonts/nxfonts_getfont.c b/libnx/nxfonts/nxfonts_getfont.c index afe0f7bc68aff03f489f8cb22c31f0ac43d655d2..bcc6169929e3e07d7953aba6a51a26569ce74c54 100644 --- a/libnx/nxfonts/nxfonts_getfont.c +++ b/libnx/nxfonts/nxfonts_getfont.c @@ -480,7 +480,7 @@ static inline FAR const struct nx_fontset_s * { /* Someday, perhaps 16-bit fonts will go here */ - gerr("ERROR: 16-bit font not currently supported\n"); + gwarn("WARNING: 16-bit font not currently supported\n"); return NULL; } @@ -491,7 +491,15 @@ static inline FAR const struct nx_fontset_s * return fontset; } - gerr("ERROR: No bitmap for code %02x\n", ch); + /* Too much debug output for the case of space which never resides in the + * font. + */ + + if (ch != ' ') + { + gwarn("WARNING: No bitmap for code %02x\n", ch); + } + return NULL; } diff --git a/libnx/nxglib/Kconfig b/libnx/nxglib/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..574f6cf0a7ee1236dbb068a889c306532e225828 --- /dev/null +++ b/libnx/nxglib/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +config NXGLIB + bool + default n diff --git a/libnx/nxglib/Make.defs b/libnx/nxglib/Make.defs index 2f972ab2f8334c2dc1178c5e51e5d8aa0c61d71e..f1ffc8f668377fdd102492e6cf2242828e11181b 100644 --- a/libnx/nxglib/Make.defs +++ b/libnx/nxglib/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # libnx/nxglib/Make.defs # -# Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. +# Copyright (C) 2013-2014, 2017 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -35,13 +35,20 @@ # Expose NXGL interfaces to applications -ifeq ($(CONFIG_NX),y) +ifeq ($(CONFIG_NXGLIB),y) + +# Files needed by both NX and NXFONTS + +CSRCS += nxglib_rgbblend.c +# Files needed only by NX + +ifeq ($(CONFIG_NX),y) CSRCS += nxglib_circlepts.c nxglib_circletraps.c nxglib_intersecting.c CSRCS += nxglib_nonintersecting.c nxglib_nullrect.c nxglib_rectadd.c CSRCS += nxglib_rectcopy.c nxglib_rectinside.c nxglib_rectintersect.c CSRCS += nxglib_rectoffset.c nxglib_rectoverlap.c nxglib_rectsize.c -CSRCS += nxglib_rectunion.c nxglib_rgb2yuv.c nxglib_rgbblend.c +CSRCS += nxglib_rectunion.c nxglib_rgb2yuv.c CSRCS += nxglib_runcopy.c nxglib_runoffset.c nxglib_splitline.c CSRCS += nxglib_trapcopy.c nxglib_trapoffset.c nxglib_vectoradd.c CSRCS += nxglib_vectsubtract.c nxglib_yuv2rgb.c @@ -49,6 +56,7 @@ CSRCS += nxglib_vectsubtract.c nxglib_yuv2rgb.c ifneq ($(CONFIG_NX_NPLANES),1) CSRCS += nxglib_colorcmp.c nxglib_colorcopy.c endif +endif # Add the nxglib/ directory to the build diff --git a/libnx/nxglib/nxglib_circlepts.c b/libnx/nxglib/nxglib_circlepts.c index 9822b1248684f37df50143de99380657a45eb4d2..21d2340a71a1751a036e8958b0452e375d9bc4ef 100644 --- a/libnx/nxglib/nxglib_circlepts.c +++ b/libnx/nxglib/nxglib_circlepts.c @@ -77,22 +77,6 @@ #define POINT_337p5 15 #define NCIRCLE_POINTS 16 -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/libnx/nxglib/nxglib_circletraps.c b/libnx/nxglib/nxglib_circletraps.c index 6e49e4d836295a7aa8b4e92c47ec6777074518bd..f7038703ba61e360621bf453463ecd6b8202faba 100644 --- a/libnx/nxglib/nxglib_circletraps.c +++ b/libnx/nxglib/nxglib_circletraps.c @@ -57,22 +57,6 @@ #define SIN_45p0 46341 /* sin(45) = 46341 / 65536 */ #define COS_45p0 SIN_45p0 /* cos(45) = sin(45) */ -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/libnx/nxmu/Kconfig b/libnx/nxmu/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..f72f3c094ce4c8f031445c514c343376e4e79e75 --- /dev/null +++ b/libnx/nxmu/Kconfig @@ -0,0 +1,4 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# diff --git a/libnx/nxmu/nx_connect.c b/libnx/nxmu/nx_connect.c index 00b93934e3c2232f2b58a17761f1e52d4c8635c8..e69580bce81374762c7e4faa67162e94b0b0e7fb 100644 --- a/libnx/nxmu/nx_connect.c +++ b/libnx/nxmu/nx_connect.c @@ -60,8 +60,8 @@ ****************************************************************************/ /* Each client is assigned a unique ID using the g_nxcid counter. That - * counter increments as each new counter is created and is* protected for - * thread safefy with g_nxlibsem. Note that these are the only global values + * counter increments as each new counter is created and is protected for + * thread safety with g_nxlibsem. Note that these are the only global values * in the NX implementation. This is because the client ID must be unique * even across all server instances. * diff --git a/libnx/nxmu/nx_disconnect.c b/libnx/nxmu/nx_disconnect.c index d8cd4517e266579264f87465815708e48d17022d..6b1877efc3f110bb83ee0bbed59b2560d2fff392 100644 --- a/libnx/nxmu/nx_disconnect.c +++ b/libnx/nxmu/nx_disconnect.c @@ -39,6 +39,7 @@ #include +#include #include #include #include @@ -70,6 +71,7 @@ void nx_disconnect(NXHANDLE handle) { FAR struct nxfe_conn_s *conn = (FAR struct nxfe_conn_s *)handle; struct nxsvrmsg_s outmsg; + char climqname[NX_CLIENT_MXNAMELEN]; int ret; /* Inform the server that this client no longer exists */ @@ -84,4 +86,10 @@ void nx_disconnect(NXHANDLE handle) { gerr("ERROR: nxmu_sendserver() returned %d\n", ret); } + else + { + snprintf(climqname, sizeof(climqname), + NX_CLIENT_MQNAMEFMT, conn->cid); + (void)mq_unlink(climqname); + } } diff --git a/libnx/nxtk/Kconfig b/libnx/nxtk/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..f72f3c094ce4c8f031445c514c343376e4e79e75 --- /dev/null +++ b/libnx/nxtk/Kconfig @@ -0,0 +1,4 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# diff --git a/mm/Kconfig b/mm/Kconfig index 4c386022c4f24ba6857d881441e0f1e2b3948ce0..01d9ff3ab121637c7a516e0fb259089056f1ab7d 100644 --- a/mm/Kconfig +++ b/mm/Kconfig @@ -92,16 +92,6 @@ config GRAN allocation size to 32 granaules. That restriction could be eliminated with some additional coding effort. -config GRAN_SINGLE - bool "Single Granule Allocator" - default n - depends on GRAN - ---help--- - Select if there is only one instance of the granule allocator (i.e., - gran_initialize will be called only once. In this case, (1) there - are a few optimizations that can can be done and (2) the GRAN_HANDLE - is not needed. - config GRAN_INTR bool "Interrupt level support" default n diff --git a/mm/Makefile b/mm/Makefile index 6126ea1c64d43e90af42d37ea9e25cd334dd939f..a0eeeb1a213c1e6027e81e8c6d31b61f9b82e237 100644 --- a/mm/Makefile +++ b/mm/Makefile @@ -1,7 +1,7 @@ ############################################################################ # mm/Makefile # -# Copyright (C) 2007, 2012, 2013-2014 Gregory Nutt. All rights reserved. +# Copyright (C) 2007, 2012, 2013-2014, 2017 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -40,7 +40,7 @@ DELIM := $(strip /) # CFLAGS -ifeq ($(CONFIG_BUILD_PROTECTED),y) +ifneq ($(CONFIG_BUILD_FLAT),y) ifeq ($(CONFIG_WINDOWS_NATIVE),y) KDEFINE = ${shell $(TOPDIR)\tools\define.bat "$(CC)" __KERNEL__} else @@ -108,11 +108,11 @@ endif # Dependencies .depend: Makefile $(SRCS) -ifeq ($(CONFIG_BUILD_PROTECTED),y) +ifeq ($(CONFIG_BUILD_FLAT),y) + $(Q) $(MKDEP) --obj-path bin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make_bin.dep +else $(Q) $(MKDEP) --obj-path ubin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make_ubin.dep $(Q) $(MKDEP) --obj-path kbin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) $(KDEFINE) -- $(SRCS) >Make_kbin.dep -else - $(Q) $(MKDEP) --obj-path bin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make_bin.dep endif $(Q) touch $@ diff --git a/mm/README.txt b/mm/README.txt index 52e6c3cd3a4fff9f035a842f05a4d23fe564396a..234e2998b75d186c1968b9f66f336f20af731ee1 100644 --- a/mm/README.txt +++ b/mm/README.txt @@ -116,8 +116,7 @@ This directory contains the NuttX memory management logic. This include: GRAN_HANDLE handle = gran_initialize(g_dmaheap, DMAHEAP_SIZE, 6, 4); - Then the GRAN_HANDLE can be used to allocate memory (There is no - GRAN_HANDLE if CONFIG_GRAN_SINGLE=y): + Then the GRAN_HANDLE can be used to allocate memory: FAR uint8_t *dma_memory = (FAR uint8_t *)gran_alloc(handle, 47); diff --git a/mm/mm_gran/Make.defs b/mm/mm_gran/Make.defs index e80db7fd0019eb96280c7da4b7ca48792495f808..a146ef5e255fcdc057a9579e15926a42b75072a2 100644 --- a/mm/mm_gran/Make.defs +++ b/mm/mm_gran/Make.defs @@ -37,7 +37,7 @@ ifeq ($(CONFIG_GRAN),y) CSRCS += mm_graninit.c mm_granrelease.c mm_granreserve.c mm_granalloc.c -CSRCS += mm_granmark.c mm_granfree.c mm_grancritical.c +CSRCS += mm_granmark.c mm_granfree.c mm_graninfo.c mm_grancritical.c # A page allocator based on the granule allocator diff --git a/mm/mm_gran/mm_gran.h b/mm/mm_gran/mm_gran.h index dcc04c72178bb124e285e271ae7a47823288b76c..a252e6aff18b6ce7028bcfb0d60873d7cf379819 100644 --- a/mm/mm_gran/mm_gran.h +++ b/mm/mm_gran/mm_gran.h @@ -1,7 +1,7 @@ /**************************************************************************** * mm/mm_gran/mm_gran.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -102,16 +102,6 @@ struct gran_s uint32_t gat[1]; /* Start of the granule allocation table */ }; -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* State of the single GRAN allocator */ - -#ifdef CONFIG_GRAN_SINGLE -extern FAR struct gran_s *g_graninfo; -#endif - /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/mm/mm_gran/mm_granalloc.c b/mm/mm_gran/mm_granalloc.c index 79044ca3a16e52c1a9548fdda9a1916c6fa256e1..30794cd681d7eb1e4c5207659b448049fc8264ac 100644 --- a/mm/mm_gran/mm_granalloc.c +++ b/mm/mm_gran/mm_granalloc.c @@ -1,7 +1,7 @@ /**************************************************************************** * mm/mm_gran/mm_granalloc.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -48,26 +48,32 @@ #ifdef CONFIG_GRAN /**************************************************************************** - * Private Functions + * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: gran_common_alloc + * Name: gran_alloc * * Description: * Allocate memory from the granule heap. * + * NOTE: The current implementation also restricts the maximum allocation + * size to 32 granules. That restriction could be eliminated with some + * additional coding effort. + * * Input Parameters: - * priv - The granule heap state structure. - * size - The size of the memory region to allocate. + * handle - The handle previously returned by gran_initialize + * size - The size of the memory region to allocate. * * Returned Value: - * On success, a non-NULL pointer to the allocated memory is returned. + * On success, a non-NULL pointer to the allocated memory is returned; + * NULL is returned on failure. * ****************************************************************************/ -static inline FAR void *gran_common_alloc(FAR struct gran_s *priv, size_t size) +FAR void *gran_alloc(GRAN_HANDLE handle, size_t size) { + FAR struct gran_s *priv = (FAR struct gran_s *)handle; unsigned int ngranules; size_t tmpmask; uintptr_t alloc; @@ -79,9 +85,9 @@ static inline FAR void *gran_common_alloc(FAR struct gran_s *priv, size_t size) int bitidx; int shift; - DEBUGASSERT(priv && size <= 32 * (1 << priv->log2gran)); + DEBUGASSERT(priv != NULL && size <= 32 * (1 << priv->log2gran)); - if (priv && size > 0) + if (priv != NULL && size > 0) { /* Get exclusive access to the GAT */ @@ -231,7 +237,7 @@ static inline FAR void *gran_common_alloc(FAR struct gran_s *priv, size_t size) } /* Set up for the next time through the loop. Perform a 64 - * bit shift to move to the next gran position andi ncrement + * bit shift to move to the next gran position and increment * to the next candidate allocation address. */ @@ -248,40 +254,4 @@ static inline FAR void *gran_common_alloc(FAR struct gran_s *priv, size_t size) return NULL; } -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: gran_alloc - * - * Description: - * Allocate memory from the granule heap. - * - * NOTE: The current implementation also restricts the maximum allocation - * size to 32 granules. That restriction could be eliminated with some - * additional coding effort. - * - * Input Parameters: - * handle - The handle previously returned by gran_initialize - * size - The size of the memory region to allocate. - * - * Returned Value: - * On success, either a non-NULL pointer to the allocated memory (if - * CONFIG_GRAN_SINGLE) or zero (if !CONFIG_GRAN_SINGLE) is returned. - * - ****************************************************************************/ - -#ifdef CONFIG_GRAN_SINGLE -FAR void *gran_alloc(size_t size) -{ - return gran_common_alloc(g_graninfo, size); -} -#else -FAR void *gran_alloc(GRAN_HANDLE handle, size_t size) -{ - return gran_common_alloc((FAR struct gran_s *)handle, size); -} -#endif - #endif /* CONFIG_GRAN */ diff --git a/mm/mm_gran/mm_granfree.c b/mm/mm_gran/mm_granfree.c index a1b9db991717f63967299041661e64a72cb63e7c..3b35a508812028c4b6b47514f153fee75ef5d607 100644 --- a/mm/mm_gran/mm_granfree.c +++ b/mm/mm_gran/mm_granfree.c @@ -1,7 +1,7 @@ /**************************************************************************** * mm/mm_gran/mm_granfree.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -48,11 +48,11 @@ #ifdef CONFIG_GRAN /**************************************************************************** - * Pre-processor Definitions + * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: gran_common_free + * Name: gran_free * * Description: * Return memory to the granule heap. @@ -66,9 +66,9 @@ * ****************************************************************************/ -static inline void gran_common_free(FAR struct gran_s *priv, - FAR void *memory, size_t size) +void gran_free(GRAN_HANDLE handle, FAR void *memory, size_t size) { + FAR struct gran_s *priv = (FAR struct gran_s *)handle; unsigned int granno; unsigned int gatidx; unsigned int gatbit; @@ -77,7 +77,7 @@ static inline void gran_common_free(FAR struct gran_s *priv, unsigned int avail; uint32_t gatmask; - DEBUGASSERT(priv && memory && size <= 32 * (1 << priv->log2gran)); + DEBUGASSERT(priv != NULL && memory && size <= 32 * (1 << priv->log2gran)); /* Get exclusive access to the GAT */ @@ -136,35 +136,4 @@ static inline void gran_common_free(FAR struct gran_s *priv, gran_leave_critical(priv); } -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: gran_free - * - * Description: - * Return memory to the granule heap. - * - * Input Parameters: - * handle - The handle previously returned by gran_initialize - * memory - A pointer to memory previoiusly allocated by gran_alloc. - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_GRAN_SINGLE -void gran_free(FAR void *memory, size_t size) -{ - return gran_common_free(g_graninfo, memory, size); -} -#else -void gran_free(GRAN_HANDLE handle, FAR void *memory, size_t size) -{ - return gran_common_free((FAR struct gran_s *)handle, memory, size); -} -#endif - #endif /* CONFIG_GRAN */ diff --git a/mm/mm_gran/mm_graninfo.c b/mm/mm_gran/mm_graninfo.c new file mode 100644 index 0000000000000000000000000000000000000000..1ce4e45069bff1733809c02cba09ba9857509368 --- /dev/null +++ b/mm/mm_gran/mm_graninfo.c @@ -0,0 +1,570 @@ +/**************************************************************************** + * mm/mm_gran/mm_graninfo.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "mm_gran/mm_gran.h" + +#ifdef CONFIG_GRAN + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct nibble_info_s +{ + uint16_t nfree : 4; /* Total bits free in a nibble */ + uint16_t nlsfree : 4; /* Total contiguous LS bits free */ + uint16_t nmsfree : 4; /* Total contiguous MS bits free */ + uint16_t mxfree : 4; /* Largest internal contiguous bits free */ +}; + +struct valinfo_s +{ + uint8_t nfree; /* Total bits free in the byte/hword */ + uint8_t nlsfree; /* Total contiguous LS bits free */ + uint8_t nmsfree; /* Total contiguous MS bits free */ + uint8_t mxfree; /* Largest internal contiguous bits free */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct nibble_info_s g_0bit_info[1] = +{ + { 0, 0, 0, 0} /* 0 xxxx */ +}; + +static const struct nibble_info_s g_1bit_info[2] = +{ + { 1, 1, 0, 1}, /* 0 xxx0 */ + { 0, 0, 0, 0} /* 1 xxx1 */ +}; + +static const struct nibble_info_s g_2bit_info[4] = +{ + { 2, 2, 0, 0}, /* 0 xx00 */ + { 1, 0, 1, 0}, /* 1 xx01 */ + { 1, 1, 0, 0}, /* 2 xx10 */ + { 0, 0, 0, 0} /* 3 xx11 */ +}; + +static const struct nibble_info_s g_3bit_info[8] = +{ + { 3, 3, 0, 0}, /* 0 x000 */ + { 2, 0, 2, 0}, /* 1 x001 */ + { 2, 1, 1, 0}, /* 2 x010 */ + { 1, 0, 1, 0}, /* 3 x011 */ + { 2, 2, 0, 0}, /* 4 x100 */ + { 1, 0, 0, 1}, /* 5 x101 */ + { 1, 1, 0, 0}, /* 6 x110 */ + { 0, 0, 0, 0} /* 7 x111 */ +}; + +static const struct nibble_info_s g_4bit_info[16] = +{ + { 4, 4, 0, 0}, /* 0 0000 */ + { 3, 0, 3, 0}, /* 1 0001 */ + { 3, 1, 2, 0}, /* 2 0010 */ + { 2, 0, 2, 0}, /* 3 0011 */ + { 3, 2, 1, 0}, /* 4 0100 */ + { 2, 0, 1, 1}, /* 5 0101 */ + { 2, 1, 1, 0}, /* 6 0110 */ + { 1, 0, 1, 0}, /* 7 0111 */ + { 3, 3, 0, 0}, /* 8 1000 */ + { 2, 0, 0, 2}, /* 9 1001 */ + { 2, 1, 0, 1}, /* 10 1010 */ + { 1, 0, 0, 1}, /* 11 1011 */ + { 2, 2, 0, 0}, /* 12 1100 */ + { 1, 0, 0, 1}, /* 13 1101 */ + { 1, 1, 0, 0}, /* 14 1110 */ + { 0, 0, 0, 0} /* 15 1111 */ +}; + +static const struct nibble_info_s *g_info_table[5] = +{ + g_0bit_info, + g_1bit_info, + g_2bit_info, + g_3bit_info, + g_4bit_info +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gran_nibble_info + * + * Description: + * Return information a 4-bit value from the GAT. + * + * Input Parameters: + * value - The 4-bit value + * info - The location to return the hword info + * nbits - Number of valid bits in value + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gran_nibble_info(uint8_t value, FAR struct valinfo_s *info, + unsigned int nbits) +{ + FAR const struct nibble_info_s *table = g_info_table[nbits]; + FAR const struct nibble_info_s *nibinfo; + uint8_t mask; + + /* Look up the table entry */ + + mask = ((1 << nbits) - 1); + value &= mask; + nibinfo = &table[value]; + + /* Return expanded values */ + + info->nfree = nibinfo->nfree; + info->nlsfree = nibinfo->nlsfree; + info->nmsfree = nibinfo->nmsfree; + info->mxfree = nibinfo->mxfree; +} + +/**************************************************************************** + * Name: gran_info_combine + * + * Description: + * Combine new MS bit information with existing LS bit information. + * + * Input Parameters: + * msinfo - The new MS bit information + * msbits - Number of bits in MS piece + * lsinfo - The existing LS bit information + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gran_info_combine(FAR const struct valinfo_s *msinfo, unsigned int msbits, + FAR struct valinfo_s *lsinfo, unsigned int lsbits) +{ + unsigned int midfree; + + /* Is there a region of free space isolated in the middle of the two + * pieces? + */ + + if (lsinfo->nlsfree < lsbits && msinfo->nlsfree < msbits) + { + /* Yes... combine the MS free bits from the LS piece with the + * LS free bits from the MS piece. + */ + + midfree = lsinfo->nmsfree + msinfo->nlsfree; + } + else + { + midfree = 0; + } + + /* Update the total number of free bits in the combined pieces */ + + lsinfo->nfree += msinfo->nfree; + + /* Figure out how many MS bits will now be free. First, is the MS piece + * all free? + */ + + if (msinfo->nlsfree == msbits) + { + /* Yes.. is the LS piece also all free bits? */ + + if (lsinfo->nlsfree == lsbits) + { + /* Yes.. the there are no MS free bits (only LS) */ + + lsinfo->nmsfree = 0; + } + else + { + /* No.. then combine all of the bits from the MS piece with the + * MS bits of the LS piece. + */ + + lsinfo->nmsfree += msbits; + } + } + else + { + /* No.. then just replace the MS bits of the LS piece with the MS + * bits from the new MS piece. + */ + + lsinfo->nmsfree = msinfo->nmsfree; + } + + /* Figure out how many LS bits will now be free. First, is the LS piece + * all free? + */ + + if (lsinfo->nlsfree == lsbits) + { + /* Yes.. then combine all of the bits from the LS piece with the + * LS bits of the MS piece. + */ + + lsinfo->nlsfree += msinfo->nlsfree; + } + + /* Now, what is the longest internal sequence of the free bits? It might + * be original sequence of free bits in the LS piece. Or it might the + * section of middle bits that got above. + */ + + if (midfree > lsinfo->mxfree) + { + lsinfo->mxfree = midfree; + } + + /* Or it might the section of middle bits in the new MS piece */ + + if (msinfo->mxfree > lsinfo->mxfree) + { + lsinfo->mxfree = msinfo->mxfree; + } +} + +/**************************************************************************** + * Name: gran_byte_info + * + * Description: + * Return information a 8-bit value from the GAT. + * + * Input Parameters: + * value - The 16-bit value + * info - The location to return the hword info + * nbits - Number of valid bits in value + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gran_byte_info(uint8_t value, FAR struct valinfo_s *info, + unsigned int nbits) +{ + uint16_t mask; + + if (nbits < 8) + { + mask = ((1 << nbits) - 1); + value &= mask; + } + else + { + mask = 0xff; + } + + /* Handle special cases */ + + if (value == 0) + { + /* All free */ + + info->nfree = nbits; + info->nlsfree = nbits; + info->nmsfree = 0; + info->mxfree = 0; + } + else if (value == mask) + { + /* All allocated */ + + info->nfree = 0; + info->nlsfree = 0; + info->nmsfree = 0; + info->mxfree = 0; + } + else + { + /* Some allocated */ + + gran_nibble_info(value & 0x0f, info, nbits > 4 ? 4 : nbits); + if (nbits > 4) + { + struct valinfo_s msinfo; + unsigned int msbits = nbits - 4; + + gran_nibble_info(value >> 4, &msinfo, msbits); + gran_info_combine(&msinfo, msbits, info, 4); + } + } +} + +/**************************************************************************** + * Name: gran_hword_info + * + * Description: + * Return information a 16-bit value from the GAT. + * + * Input Parameters: + * value - The 16-bit value + * info - The location to return the hword info + * nbits - Number of valid bits in value + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gran_hword_info(uint16_t value, FAR struct valinfo_s *info, + unsigned int nbits) +{ + uint16_t mask; + + if (nbits < 16) + { + mask = ((1 << nbits) - 1); + value &= mask; + } + else + { + mask = 0xffff; + } + + /* Handle special cases */ + + if (value == 0) + { + /* All free */ + + info->nfree = nbits; + info->nlsfree = nbits; + info->nmsfree = 0; + info->mxfree = 0; + } + else if (value == mask) + { + /* All allocated */ + + info->nfree = 0; + info->nlsfree = 0; + info->nmsfree = 0; + info->mxfree = 0; + } + else + { + /* Some allocated */ + + gran_byte_info((uint8_t)(value & 0xff), info, nbits > 8 ? 8 : nbits); + if (nbits > 8) + { + struct valinfo_s msinfo; + unsigned int msbits = nbits - 8; + + gran_byte_info((uint8_t)(value >> 8), &msinfo, msbits); + gran_info_combine(&msinfo, msbits, info, 8); + } + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gran_info + * + * Description: + * Return information about the granule heap. + * + * Input Parameters: + * handle - The handle previously returned by gran_initialize + * info - Memory location to return the gran allocator info. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is return on + * any failure. + * + ****************************************************************************/ + +void gran_info(GRAN_HANDLE handle, FAR struct graninfo_s *info) +{ + FAR struct gran_s *priv = (FAR struct gran_s *)handle; + uint32_t mask; + uint32_t value; + uint16_t mxfree; + unsigned int nbits; + unsigned int granidx; + unsigned int gatidx; + + DEBUGASSERT(priv != NULL && info != NULL); + + info->log2gran = priv->log2gran; + info->ngranules = priv->ngranules; + info->nfree = 0; + info->mxfree = 0; + mxfree = 0; + + /* Get exclusive access to the GAT */ + + gran_enter_critical(priv); + + /* Travere the granule allocation */ + + for (granidx = 0; granidx < priv->ngranules; granidx += 32) + { + /* Get the GAT index associated with the granule table entry */ + + gatidx = granidx >> 5; + value = priv->gat[gatidx]; + + /* The final entry is a special case */ + + if ((granidx + 32) >= priv->ngranules) + { + nbits = priv->ngranules - granidx; + mask = ((1ul << nbits) - 1); + value &= mask; + } + else + { + nbits = 32; + mask = 0xffffffff; + } + + /* Handle the 32-bit cases */ + + if (value == mask) + { + /* All allocated. This will terminate any sequence of free + * granules. + */ + + if (mxfree > info->mxfree) + { + info->mxfree = mxfree; + } + + mxfree = 0; + } + else if (value == 0x00000000) + { + /* All free */ + + info->nfree += nbits; + mxfree += nbits; + } + else + { + struct valinfo_s hwinfo; + + /* Some allocated */ + + gran_hword_info((uint16_t)(value & 0xffff), &hwinfo, + nbits > 16 ? 16 : nbits); + if (nbits > 16) + { + struct valinfo_s msinfo; + unsigned int msbits = nbits - 16; + + gran_hword_info((uint16_t)(value >> 16), &msinfo, msbits); + gran_info_combine(&msinfo, msbits, &hwinfo, 16); + } + + /* Update the running free sequence of granules */ + + if (hwinfo.nlsfree > 0) + { + mxfree += hwinfo.nlsfree; + } + + /* If the entire word is not free, then update the maxfree free + * sequence. + */ + + if (hwinfo.nlsfree < nbits) + { + /* Is the sequence internally free bits in the 32-bit value + * longer than the running free sequence? + */ + + if (hwinfo.mxfree > mxfree) + { + mxfree = hwinfo.mxfree; + } + + /* Is the running free sequence longer than the last sequence + * that we saw? + */ + + if (mxfree > info->mxfree) + { + info->mxfree = mxfree; + } + + /* Then restart with the free MS granules */ + + mxfree = hwinfo.nmsfree; + } + + /* Update the total number of free granules */ + + info->nfree += hwinfo.nfree; + } + } + + /* Check if the last, unterminated sequence of free granules was the longest */ + + if (mxfree > info->mxfree) + { + info->mxfree = mxfree; + } + + gran_leave_critical(priv); +} + +#endif /* CONFIG_GRAN */ diff --git a/mm/mm_gran/mm_graninit.c b/mm/mm_gran/mm_graninit.c index 87a7992dd7544f688e4658e43e5a606d9c35da3d..fa1f186714588c62f782e9e626c3c6388968e200 100644 --- a/mm/mm_gran/mm_graninit.c +++ b/mm/mm_gran/mm_graninit.c @@ -1,7 +1,7 @@ /**************************************************************************** * mm/mm_gran/mm_graninit.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -50,46 +50,64 @@ #ifdef CONFIG_GRAN /**************************************************************************** - * Public Data - ****************************************************************************/ - -/* State of the single GRAN allocator */ - -#ifdef CONFIG_GRAN_SINGLE -FAR struct gran_s *g_graninfo; -#endif - -/**************************************************************************** - * Private Functions + * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: gran_common_initialize + * Name: gran_initialize * * Description: - * Perform common GRAN initialization. + * Set up one granule allocator instance. Allocations will be aligned to + * the alignment size (log2align; allocations will be in units of the + * granule size (log2gran). Larger granules will give better performance + * and less overhead but more losses of memory due to quantization waste. + * Additional memory waste can occur from alignment; log2align should be + * set to 0 unless you are using the granule allocator to manage DMA + * or page-aligned memory and your hardware has specific memory alignment + * requirements. + * + * General Usage Summary. This is an example using the GCC section + * attribute to position a DMA heap in memory (logic in the linker script + * would assign the section .dmaheap to the DMA memory. + * + * FAR uint32_t g_dmaheap[DMAHEAP_SIZE] __attribute__((section(.dmaheap))); + * + * The heap is created by calling gran_initialize(). Here the granule size + * is set to 64 bytes (2**6) and the alignment to 16 bytes (2**4): + * + * GRAN_HANDLE handle = gran_initialize(g_dmaheap, DMAHEAP_SIZE, 6, 4); + * + * Then the GRAN_HANDLE can be used to allocate memory: + * + * FAR uint8_t *dma_memory = (FAR uint8_t *)gran_alloc(handle, 47); + * + * The actual memory allocates will be 64 byte (wasting 17 bytes) and + * will be aligned at least to (1 << log2align). + * + * NOTE: The current implementation also restricts the maximum allocation + * size to 32 granules. That restriction could be eliminated with some + * additional coding effort. * * Input Parameters: * heapstart - Start of the granule allocation heap * heapsize - Size of heap in bytes * log2gran - Log base 2 of the size of one granule. 0->1 byte, - * 1->2 bytes, 2->4 bytes, 3-> 8 bytes, etc. + * 1->2 bytes, 2->4 bytes, 3->8 bytes, etc. * log2align - Log base 2 of required alignment. 0->1 byte, - * 1->2 bytes, 2->4 bytes, 3-> 8 bytes, etc. Note that + * 1->2 bytes, 2->4 bytes, 3->8 bytes, etc. Note that * log2gran must be greater than or equal to log2align * so that all contiguous granules in memory will meet * the minimum alignment requirement. A value of zero * would mean that no alignment is required. * * Returned Value: - * On success, a non-NULL info structure is returned that may be used with - * other granule allocator interfaces. + * On success, a non-NULL handle is returned that may be used with other + * granule allocator interfaces. * ****************************************************************************/ -static inline FAR struct gran_s * -gran_common_initialize(FAR void *heapstart, size_t heapsize, uint8_t log2gran, - uint8_t log2align) +GRAN_HANDLE gran_initialize(FAR void *heapstart, size_t heapsize, + uint8_t log2gran, uint8_t log2align) { FAR struct gran_s *priv; uintptr_t heapend; @@ -139,87 +157,7 @@ gran_common_initialize(FAR void *heapstart, size_t heapsize, uint8_t log2gran, #endif } - return priv; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: gran_initialize - * - * Description: - * Set up one granule allocator instance. Allocations will be aligned to - * the alignment size (log2align; allocations will be in units of the - * granule size (log2gran). Larger granules will give better performance - * and less overhead but more losses of memory due to quantization waste. - * Additional memory waste can occur from alignment; log2align should be - * set to 0 unless you are using the granule allocator to manage DMA - * or page-aligned memory and your hardware has specific memory alignment - * requirements. - * - * General Usage Summary. This is an example using the GCC section - * attribute to position a DMA heap in memory (logic in the linker script - * would assign the section .dmaheap to the DMA memory. - * - * FAR uint32_t g_dmaheap[DMAHEAP_SIZE] __attribute__((section(.dmaheap))); - * - * The heap is created by calling gran_initialize(). Here the granule size - * is set to 64 bytes (2**6) and the alignment to 16 bytes (2**4): - * - * GRAN_HANDLE handle = gran_initialize(g_dmaheap, DMAHEAP_SIZE, 6, 4); - * - * Then the GRAN_HANDLE can be used to allocate memory (There is no - * GRAN_HANDLE if CONFIG_GRAN_SINGLE=y): - * - * FAR uint8_t *dma_memory = (FAR uint8_t *)gran_alloc(handle, 47); - * - * The actual memory allocates will be 64 byte (wasting 17 bytes) and - * will be aligned at least to (1 << log2align). - * - * NOTE: The current implementation also restricts the maximum allocation - * size to 32 granules. That restriction could be eliminated with some - * additional coding effort. - * - * Input Parameters: - * heapstart - Start of the granule allocation heap - * heapsize - Size of heap in bytes - * log2gran - Log base 2 of the size of one granule. 0->1 byte, - * 1->2 bytes, 2->4 bytes, 3->8 bytes, etc. - * log2align - Log base 2 of required alignment. 0->1 byte, - * 1->2 bytes, 2->4 bytes, 3->8 bytes, etc. Note that - * log2gran must be greater than or equal to log2align - * so that all contiguous granules in memory will meet - * the minimum alignment requirement. A value of zero - * would mean that no alignment is required. - * - * Returned Value: - * On success, a non-NULL handle is returned that may be used with other - * granule allocator interfaces. - * - ****************************************************************************/ - -#ifdef CONFIG_GRAN_SINGLE -int gran_initialize(FAR void *heapstart, size_t heapsize, uint8_t log2gran, - uint8_t log2align) -{ - g_graninfo = gran_common_initialize(heapstart, heapsize, log2gran, - log2align); - if (!g_graninfo) - { - return -ENOMEM; - } - - return OK; -} -#else -GRAN_HANDLE gran_initialize(FAR void *heapstart, size_t heapsize, - uint8_t log2gran, uint8_t log2align) -{ - return (GRAN_HANDLE)gran_common_initialize(heapstart, heapsize, - log2gran, log2align); + return (GRAN_HANDLE)priv; } -#endif #endif /* CONFIG_GRAN */ diff --git a/mm/mm_gran/mm_granrelease.c b/mm/mm_gran/mm_granrelease.c index 3fb94c7afe26308628998d6634593ac63e00a306..b4e9ee8affc023f9bafe52f1ee99f58e1861493b 100644 --- a/mm/mm_gran/mm_granrelease.c +++ b/mm/mm_gran/mm_granrelease.c @@ -1,7 +1,7 @@ /**************************************************************************** * mm/mm_gran/mm_graninit.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -49,43 +49,6 @@ #ifdef CONFIG_GRAN -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* State of the single GRAN allocator */ - -#ifdef CONFIG_GRAN_SINGLE -FAR struct gran_s *g_graninfo; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: gran_release_common - * - * Description: - * Perform common GRAN initialization. - * - * Input Parameters: - * priv - Reference to the granule heap structure to be released. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void gran_release_common(FAR struct gran_s *priv) -{ - DEBUGASSERT(priv); -#ifndef CONFIG_GRAN_INTR - nxsem_destroy(&priv->exclsem); -#endif - kmm_free(priv); -} - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -105,17 +68,16 @@ static inline void gran_release_common(FAR struct gran_s *priv) * ****************************************************************************/ -#ifdef CONFIG_GRAN_SINGLE -void gran_release(void) -{ - gran_release_common(g_graninfo); - g_graninfo = NULL; -} -#else void gran_release(GRAN_HANDLE handle) { - gran_release_common(handle); -} + FAR struct gran_s *priv = (FAR struct gran_s *)handle; + + DEBUGASSERT(priv != NULL); + +#ifndef CONFIG_GRAN_INTR + nxsem_destroy(&priv->exclsem); #endif + kmm_free(priv); +} #endif /* CONFIG_GRAN */ diff --git a/mm/mm_gran/mm_granreserve.c b/mm/mm_gran/mm_granreserve.c index 99581279690a78ca9942501e14873ec1f9bbfc9b..c7fcfa6df9bd91adc28aa5de18205e640594c509 100644 --- a/mm/mm_gran/mm_granreserve.c +++ b/mm/mm_gran/mm_granreserve.c @@ -1,7 +1,7 @@ /**************************************************************************** * mm/mm_gran/mm_granreserve.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -48,11 +48,11 @@ #ifdef CONFIG_GRAN /**************************************************************************** - * Private Functions + * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: gran_common_reserve + * Name: gran_reserve * * Description: * Reserve memory in the granule heap. This will reserve the granules @@ -64,18 +64,21 @@ * essentially unreserves the memory). * * Input Parameters: - * priv - The granule heap state structure. - * start - The address of the beginning of the region to be reserved. - * size - The size of the region to be reserved + * handle - The handle previously returned by gran_initialize + * start - The address of the beginning of the region to be reserved. + * size - The size of the region to be reserved * * Returned Value: * None * ****************************************************************************/ -static inline void gran_common_reserve(FAR struct gran_s *priv, - uintptr_t start, size_t size) +void gran_reserve(GRAN_HANDLE handle, uintptr_t start, size_t size) { + FAR struct gran_s *priv = (FAR struct gran_s *)handle; + + DEBUGASSERT(priv != NULL); + if (size > 0) { uintptr_t mask = (1 << priv->log2gran) - 1; @@ -99,42 +102,4 @@ static inline void gran_common_reserve(FAR struct gran_s *priv, } } -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: gran_reserve - * - * Description: - * Reserve memory in the granule heap. This will reserve the granules - * that contain the start and end addresses plus all of the granules - * in between. This should be done early in the initialization sequence - * before any other allocations are made. - * - * Reserved memory can never be allocated (it can be freed however which - * essentially unreserves the memory). - * - * Input Parameters: - * handle - The handle previously returned by gran_initialize - * start - The address of the beginning of the region to be reserved. - * size - The size of the region to be reserved - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_GRAN_SINGLE -void gran_reserve(uintptr_t start, size_t size) -{ - return gran_common_reserve(g_graninfo, start, size); -} -#else -void gran_reserve(GRAN_HANDLE handle, uintptr_t start, size_t size) -{ - return gran_common_reserve((FAR struct gran_s *)handle, start, size); -} -#endif - #endif /* CONFIG_GRAN */ diff --git a/mm/mm_gran/mm_pgalloc.c b/mm/mm_gran/mm_pgalloc.c index 2574e20912bbdf71de764e451defb254b5e5d53a..69e52d03d3ae25f043bbf6c9a504c98cbb588745 100644 --- a/mm/mm_gran/mm_pgalloc.c +++ b/mm/mm_gran/mm_pgalloc.c @@ -1,7 +1,7 @@ /**************************************************************************** * mm/mm_gran/mm_pgalloc.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -90,11 +90,9 @@ * Private Data ****************************************************************************/ -#ifndef CONFIG_GRAN_SINGLE /* The state of the page allocator */ static GRAN_HANDLE g_pgalloc; -#endif /**************************************************************************** * Private Functions @@ -123,18 +121,8 @@ static GRAN_HANDLE g_pgalloc; void mm_pginitialize(FAR void *heap_start, size_t heap_size) { -#ifdef CONFIG_GRAN_SINGLE - int ret; - - ret = gran_initialize(heap_start, heap_size, MM_PGSHIFT, MM_PGSHIFT); - DEBUGASSERT(ret == OK); - UNUSED(ret); - -#else g_pgalloc = gran_initialize(heap_start, heap_size, MM_PGSHIFT, MM_PGSHIFT); DEBUGASSERT(pg_alloc != NULL); - -#endif } /**************************************************************************** @@ -160,11 +148,7 @@ void mm_pginitialize(FAR void *heap_start, size_t heap_size) void mm_pgreserve(uintptr_t start, size_t size) { -#ifdef CONFIG_GRAN_SINGLE - gran_reserve(start, size); -#else gran_reserve(g_pgalloc, start, size); -#endif } /**************************************************************************** @@ -185,11 +169,7 @@ void mm_pgreserve(uintptr_t start, size_t size) uintptr_t mm_pgalloc(unsigned int npages) { -#ifdef CONFIG_GRAN_SINGLE - return (uintptr_t)gran_alloc((size_t)1 << MM_PGSHIFT); -#else return (uintptr_t)gran_alloc(g_pgalloc, (size_t)1 << MM_PGSHIFT); -#endif } /**************************************************************************** @@ -211,11 +191,35 @@ uintptr_t mm_pgalloc(unsigned int npages) void mm_pgfree(uintptr_t paddr, unsigned int npages) { -#ifdef CONFIG_GRAN_SINGLE - gran_free((FAR void *)paddr, (size_t)npages << MM_PGSHIFT); -#else gran_free(g_pgalloc, (FAR void *)paddr, (size_t)npages << MM_PGSHIFT); -#endif +} + +/**************************************************************************** + * Name: mm_pginfo + * + * Description: + * Return information about the page allocator. + * + * Input Parameters: + * handle - The handle previously returned by gran_initialize + * info - Memory location to return the gran allocator info. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is return on + * any failure. + * + ****************************************************************************/ + +void mm_pginfo(FAR struct pginfo_s *info) +{ + struct graninfo_s graninfo; + + DEBUGASSERT(info != NULL); + gran_info(g_pgalloc, &graninfo); + + info->ntotal = graninfo.ngranules; + info->nfree = graninfo.nfree; + info->mxfree = graninfo.mxfree; } #endif /* CONFIG_MM_PGALLOC */ diff --git a/mm/mm_heap/mm_malloc.c b/mm/mm_heap/mm_malloc.c index 430b7ac5b84288ecac680688ac2dfbc5ec4367e2..cf72dc9931879d2d0d23aabbfc30eb2db527b373 100644 --- a/mm/mm_heap/mm_malloc.c +++ b/mm/mm_heap/mm_malloc.c @@ -71,12 +71,13 @@ FAR void *mm_malloc(FAR struct mm_heap_s *heap, size_t size) { FAR struct mm_freenode_s *node; + size_t alignsize; void *ret = NULL; int ndx; - /* Handle bad sizes */ + /* Ignore zero-length allocations */ - if (size < 1 || size > (MMSIZE_MAX - SIZEOF_MM_ALLOCNODE)) + if (size < 1) { return NULL; } @@ -85,7 +86,8 @@ FAR void *mm_malloc(FAR struct mm_heap_s *heap, size_t size) * (2) to make sure that it is an even multiple of our granule size. */ - size = MM_ALIGN_UP(size + SIZEOF_MM_ALLOCNODE); + alignsize = MM_ALIGN_UP(size + SIZEOF_MM_ALLOCNODE); + DEBUGASSERT(alignsize >= size); /* Check for integer overflow */ /* We need to hold the MM semaphore while we muck with the nodelist. */ @@ -95,7 +97,7 @@ FAR void *mm_malloc(FAR struct mm_heap_s *heap, size_t size) * really big allocations */ - if (size >= MM_MAX_CHUNK) + if (alignsize >= MM_MAX_CHUNK) { ndx = MM_NNODES-1; } @@ -103,7 +105,7 @@ FAR void *mm_malloc(FAR struct mm_heap_s *heap, size_t size) { /* Convert the request size into a nodelist index */ - ndx = mm_size2ndx(size); + ndx = mm_size2ndx(alignsize); } /* Search for a large enough chunk in the list of nodes. This list is @@ -112,7 +114,7 @@ FAR void *mm_malloc(FAR struct mm_heap_s *heap, size_t size) */ for (node = heap->mm_nodelist[ndx].flink; - node && node->size < size; + node && node->size < alignsize; node = node->flink); /* If we found a node with non-zero size, then this is one to use. Since @@ -144,7 +146,7 @@ FAR void *mm_malloc(FAR struct mm_heap_s *heap, size_t size) * allocation. */ - remaining = node->size - size; + remaining = node->size - alignsize; if (remaining >= SIZEOF_MM_FREENODE) { /* Get a pointer to the next node in physical memory */ @@ -153,13 +155,15 @@ FAR void *mm_malloc(FAR struct mm_heap_s *heap, size_t size) /* Create the remainder node */ - remainder = (FAR struct mm_freenode_s *)(((FAR char *)node) + size); - remainder->size = remaining; - remainder->preceding = size; + remainder = (FAR struct mm_freenode_s *) + (((FAR char *)node) + alignsize); + + remainder->size = remaining; + remainder->preceding = alignsize; /* Adjust the size of the node under consideration */ - node->size = size; + node->size = alignsize; /* Adjust the 'preceding' size of the (old) next node, preserving * the allocated flag. @@ -187,11 +191,11 @@ FAR void *mm_malloc(FAR struct mm_heap_s *heap, size_t size) #ifdef CONFIG_DEBUG_MM if (!ret) { - mwarn("WARNING: Allocation failed, size %d\n", size); + mwarn("WARNING: Allocation failed, size %d\n", alignsize); } else { - minfo("Allocated %p, size %d\n", ret, size); + minfo("Allocated %p, size %d\n", ret, alignsize); } #endif diff --git a/mm/shm/README.txt b/mm/shm/README.txt index 81bdfab86e1806878bd2af45572988d82e5bb8ed..f43bc62306e47b5b6336ba669d63dc9a11e64ada 100644 --- a/mm/shm/README.txt +++ b/mm/shm/README.txt @@ -12,9 +12,6 @@ Prerequisites regions must be provided by the MMU. CONFIG_GRAN=y - The granule allocation is the allocation underlying all paged allocations. - CONFIG_GRAN_SINGLE=n - Multiple granule allocators are needed: One for - the physical page allocation and one virtual page allocator for each - process. CONFIG_MM_PGALLOC=y - Enables the physical page allocator CONFIG_MM_PGSIZE - Determines the size of one page that can be mapped by the MMU. diff --git a/net/arp/arp_arpin.c b/net/arp/arp_arpin.c index b3350554f58f06a8ac0156c3b0b1c69ce1ebade3..fd8163a2e0bdf613f009d3435ac2c5445a0751de 100644 --- a/net/arp/arp_arpin.c +++ b/net/arp/arp_arpin.c @@ -70,8 +70,8 @@ * Name: arp_arpin * * Description: - * This function should be called by the Ethernet device driver when an ARP - * packet has been received. The function will act differently + * This function should be called by the Ethernet device driver when an + * ARP packet has been received. The function will act differently * depending on the ARP packet type: if it is a reply for a request * that we previously sent out, the ARP cache will be filled in with * the values from the ARP reply. If the incoming ARP packet is an ARP @@ -82,10 +82,11 @@ * Ethernet header is present in the d_buf buffer and that the length of * the packet is set in the d_len field. * - * When the function returns, the value of the field d_len indicates whether - * the device driver should send out the ARP reply packet or not. If d_len - * is zero, no packet should be sent; If d_len is non-zero, it contains the - * length of the outbound packet that is present in the d_buf buffer. + * When the function returns, the value of the field d_len indicates + * whether the device driver should send out the ARP reply packet or not. + * If d_len is zero, no packet should be sent; If d_len is non-zero, it + * contains the length of the outbound packet that is present in the + * d_buf buffer. * ****************************************************************************/ @@ -107,7 +108,7 @@ void arp_arpin(FAR struct net_driver_s *dev) switch (arp->ah_opcode) { case HTONS(ARP_REQUEST): - ninfo("ARP request for IP %04lx\n", (long)ipaddr); + ninfo("ARP request for IP %04lx\n", (unsigned long)ipaddr); /* ARP request. If it asked for our address, we send out a reply. */ @@ -139,7 +140,7 @@ void arp_arpin(FAR struct net_driver_s *dev) break; case HTONS(ARP_REPLY): - ninfo("ARP reply for IP %04lx\n", (long)ipaddr); + ninfo("ARP reply for IP %04lx\n", (unsigned long)ipaddr); /* ARP reply. We insert or update the ARP table if it was meant * for us. diff --git a/net/arp/arp_out.c b/net/arp/arp_out.c index 4d9b2ca8e0fb943427af1816de3adc84de266a61..70a2275837d8533356ed328238dde5749b65e4df 100644 --- a/net/arp/arp_out.c +++ b/net/arp/arp_out.c @@ -169,6 +169,7 @@ void arp_out(FAR struct net_driver_s *dev) if (net_ipv4addr_hdrcmp(pip->eh_destipaddr, g_broadcast_ipaddr)) { memcpy(peth->dest, g_broadcast_ethaddr.ether_addr_octet, ETHER_ADDR_LEN); + goto finish_header; } #ifdef CONFIG_NET_IGMP @@ -181,8 +182,8 @@ void arp_out(FAR struct net_driver_s *dev) * addresses=0xff (ff00::/8.) */ - else if (NTOHS(pip->eh_destipaddr[0]) >= 0xe000 && - NTOHS(pip->eh_destipaddr[0]) <= 0xefff) + if (NTOHS(pip->eh_destipaddr[0]) >= 0xe000 && + NTOHS(pip->eh_destipaddr[0]) <= 0xefff) { /* Build the well-known IPv4 IGMP Ethernet address. The first * three bytes are fixed; the final three variable come from the @@ -196,66 +197,79 @@ void arp_out(FAR struct net_driver_s *dev) peth->dest[0] = g_multicast_ethaddr[0]; peth->dest[1] = g_multicast_ethaddr[1]; peth->dest[2] = g_multicast_ethaddr[2]; - peth->dest[3] = ip[2] & 0x7f; - peth->dest[4] = ip[3]; - peth->dest[5] = ip[4]; + peth->dest[3] = ip[1] & 0x7f; + peth->dest[4] = ip[2]; + peth->dest[5] = ip[3]; + + goto finish_header; } #endif - else - { - /* Check if the destination address is on the local network. */ - destipaddr = net_ip4addr_conv32(pip->eh_destipaddr); - if (!net_ipv4addr_maskcmp(destipaddr, dev->d_ipaddr, dev->d_netmask)) - { - /* Destination address is not on the local network */ + /* Check if the destination address is on the local network. */ + + destipaddr = net_ip4addr_conv32(pip->eh_destipaddr); + if (!net_ipv4addr_maskcmp(destipaddr, dev->d_ipaddr, dev->d_netmask)) + { + /* Destination address is not on the local network */ #ifdef CONFIG_NET_ROUTE - /* We have a routing table.. find the correct router to use in - * this case (or, as a fall-back, use the device's default router - * address). We will use the router IP address instead of the - * destination address when determining the MAC address. - */ + /* We have a routing table.. find the correct router to use in + * this case (or, as a fall-back, use the device's default router + * address). We will use the router IP address instead of the + * destination address when determining the MAC address. + */ - netdev_ipv4_router(dev, destipaddr, &ipaddr); + netdev_ipv4_router(dev, destipaddr, &ipaddr); #else - /* Use the device's default router IP address instead of the - * destination address when determining the MAC address. - */ + /* Use the device's default router IP address instead of the + * destination address when determining the MAC address. + */ - net_ipv4addr_copy(ipaddr, dev->d_draddr); + net_ipv4addr_copy(ipaddr, dev->d_draddr); #endif - } - else - { - /* Else, we use the destination IP address. */ + } - net_ipv4addr_copy(ipaddr, destipaddr); - } + /* The destination address is on the local network. Check if it is + * the sub-net broadcast address. + */ - /* Check if we already have this destination address in the ARP table */ + else if (net_ipv4addr_broadcast(destipaddr, dev->d_netmask)) + { + /* Yes.. then we won't need to know the destination MAC address */ - tabptr = arp_find(ipaddr); - if (!tabptr) - { - ninfo("ARP request for IP %08lx\n", (unsigned long)ipaddr); + memcpy(peth->dest, g_broadcast_ethaddr.ether_addr_octet, ETHER_ADDR_LEN); + goto finish_header; + } + else + { + /* Else, we use the destination IP address. */ + + net_ipv4addr_copy(ipaddr, destipaddr); + } - /* The destination address was not in our ARP table, so we - * overwrite the IP packet with an ARP request. - */ + /* Check if we already have this destination address in the ARP table */ - arp_format(dev, ipaddr); - arp_dump(ARPBUF); - return; - } + tabptr = arp_find(ipaddr); + if (tabptr == NULL) + { + ninfo("ARP request for IP %08lx\n", (unsigned long)ipaddr); - /* Build an Ethernet header. */ + /* The destination address was not in our ARP table, so we overwrite + * the IP packet with an ARP request. + */ - memcpy(peth->dest, tabptr->at_ethaddr.ether_addr_octet, ETHER_ADDR_LEN); + arp_format(dev, ipaddr); + arp_dump(ARPBUF); + return; } + /* Build an Ethernet header. */ + + memcpy(peth->dest, tabptr->at_ethaddr.ether_addr_octet, ETHER_ADDR_LEN); + /* Finish populating the Ethernet header */ +finish_header: memcpy(peth->src, dev->d_mac.ether.ether_addr_octet, ETHER_ADDR_LEN); peth->type = HTONS(ETHTYPE_IP); dev->d_len += ETH_HDRLEN; diff --git a/net/arp/arp_send.c b/net/arp/arp_send.c index 4725cf8dfcd3df95420e5045f879477909c99aec..38405bb6061f0356fe047f96aa594bbdba111ab5 100644 --- a/net/arp/arp_send.c +++ b/net/arp/arp_send.c @@ -250,7 +250,6 @@ int arp_send(in_addr_t ipaddr) /* Destination address is not on the local network */ #ifdef CONFIG_NET_ROUTE - /* We have a routing table.. find the correct router to use in * this case (or, as a fall-back, use the device's default router * address). We will use the router IP address instead of the @@ -268,6 +267,17 @@ int arp_send(in_addr_t ipaddr) ipaddr = dripaddr; } + /* The destination address is on the local network. Check if it is + * the sub-net broadcast address. + */ + + else if (net_ipv4addr_broadcast(ipaddr, dev->d_netmask)) + { + /* Yes.. We don't need to send the ARP request */ + + return OK; + } + /* Allocate resources to receive a callback. This and the following * initialization is performed with the network lock because we don't * want anything to happen until we are ready. diff --git a/net/devif/devif_forward.c b/net/devif/devif_forward.c index 6f6faffdceaca724116b22b3eeea628e50bb0143..acfd782781bdab483dac52b899a2c7db1a4bf20c 100644 --- a/net/devif/devif_forward.c +++ b/net/devif/devif_forward.c @@ -86,10 +86,9 @@ void devif_forward(FAR struct forward_s *fwd) fwd->f_iob->io_pktlen, 0); DEBUGASSERT(ret == fwd->f_iob->io_pktlen); - offset += fwd->f_iob->io_pktlen; fwd->f_dev->d_sndlen = 0; - fwd->f_dev->d_len = offset; + fwd->f_dev->d_len = fwd->f_iob->io_pktlen; UNUSED(ret); } diff --git a/net/devif/ipv4_input.c b/net/devif/ipv4_input.c index f9dc601ec6182ef691bc2b4f2b8520928573eeb8..3e7a659a0edeeae28f9e72ce9b58e12946178e56 100644 --- a/net/devif/ipv4_input.c +++ b/net/devif/ipv4_input.c @@ -321,6 +321,7 @@ nullreturn: int ipv4_input(FAR struct net_driver_s *dev) { FAR struct ipv4_hdr_s *ipv4 = BUF; + in_addr_t destipaddr; uint16_t hdrlen; uint16_t iplen; @@ -395,6 +396,10 @@ int ipv4_input(FAR struct net_driver_s *dev) #endif /* CONFIG_NET_TCP_REASSEMBLY */ } + /* Get the destination IP address in a friendlier form */ + + destipaddr = net_ip4addr_conv32(ipv4->destipaddr); + #if defined(CONFIG_NET_BROADCAST) && defined(NET_UDP_HAVE_STACK) /* If IP broadcast support is configured, we check for a broadcast * UDP packet, which may be destined to us (even if there is no IP @@ -403,8 +408,7 @@ int ipv4_input(FAR struct net_driver_s *dev) */ if (ipv4->proto == IP_PROTO_UDP && - net_ipv4addr_cmp(net_ip4addr_conv32(ipv4->destipaddr), - INADDR_BROADCAST)) + net_ipv4addr_cmp(destipaddr, INADDR_BROADCAST)) { #ifdef CONFIG_NET_IPFORWARD_BROADCAST /* Forward broadcast packets */ @@ -413,74 +417,90 @@ int ipv4_input(FAR struct net_driver_s *dev) #endif return udp_ipv4_input(dev); } - - /* In other cases, the device must be assigned a non-zero IP address. */ - else #endif #ifdef CONFIG_NET_ICMP + /* In other cases, the device must be assigned a non-zero IP address. */ + if (net_ipv4addr_cmp(dev->d_ipaddr, INADDR_ANY)) { nwarn("WARNING: No IP address assigned\n"); goto drop; } - - /* Check if the packet is destined for our IP address */ else #endif +#if defined(CONFIG_NET_BROADCAST) && defined(NET_UDP_HAVE_STACK) + /* The address is not the broadcast address and we have been assigned a + * address. So there is also the possibility that the destination address + * is a sub-net broadcast address which we will need to handle just as for + * the broadcast address above. + */ + + if (ipv4->proto == IP_PROTO_UDP && + net_ipv4addr_maskcmp(destipaddr, dev->d_ipaddr, dev->d_netmask) && + net_ipv4addr_broadcast(destipaddr, dev->d_netmask)) { - /* Check if the packet is destined for our IP address. */ +#ifdef CONFIG_NET_IPFORWARD_BROADCAST + /* Forward broadcast packets */ - if (!net_ipv4addr_cmp(net_ip4addr_conv32(ipv4->destipaddr), - dev->d_ipaddr)) - { - /* Check for an IPv4 IGMP group address */ + ipv4_forward_broadcast(dev, ipv4); +#endif + return udp_ipv4_input(dev); + } + else +#endif + /* Check if the packet is destined for our IP address. */ + + if (!net_ipv4addr_cmp(destipaddr, dev->d_ipaddr)) + { + /* No.. This is not our IP address. Check for an IPv4 IGMP group + * address + */ #ifdef CONFIG_NET_IGMP - in_addr_t destip = net_ip4addr_conv32(ipv4->destipaddr); - if (igmp_grpfind(dev, &destip) != NULL) - { + in_addr_t destip = net_ip4addr_conv32(ipv4->destipaddr); + if (igmp_grpfind(dev, &destip) != NULL) + { #ifdef CONFIG_NET_IPFORWARD_BROADCAST - /* Forward multicast packets */ + /* Forward multicast packets */ - ipv4_forward_broadcast(dev, ipv4); + ipv4_forward_broadcast(dev, ipv4); #endif - } - else + } + else #endif - { - /* No.. The packet is not destined for us. */ + { + /* No.. The packet is not destined for us. */ #ifdef CONFIG_NET_IPFORWARD - /* Try to forward the packet */ + /* Try to forward the packet */ - int ret = ipv4_forward(dev, ipv4); - if (ret >= 0) - { - /* The packet was forwarded. Return success; d_len will - * be set appropriately by the forwarding logic: Cleared - * if the packet is forward via anoother device or non- - * zero if it will be forwarded by the same device that - * it was received on. - */ - - return OK; - } - else + int ret = ipv4_forward(dev, ipv4); + if (ret >= 0) + { + /* The packet was forwarded. Return success; d_len will + * be set appropriately by the forwarding logic: Cleared + * if the packet is forward via anoother device or non- + * zero if it will be forwarded by the same device that + * it was received on. + */ + + return OK; + } + else #endif - { - /* Not destined for us and not forwardable... Drop the - * packet. - */ + { + /* Not destined for us and not forwardable... Drop the + * packet. + */ - nwarn("WARNING: Not destined for us; not forwardable... " - "Dropping!\n"); + nwarn("WARNING: Not destined for us; not forwardable... " + "Dropping!\n"); #ifdef CONFIG_NET_STATISTICS - g_netstats.ipv4.drop++; + g_netstats.ipv4.drop++; #endif - goto drop; - } + goto drop; } } } diff --git a/net/icmp/icmp.h b/net/icmp/icmp.h index ebb2a23d9ae236d84dd05ee6467177c5a0d8d5f0..77aa832f8f4c4135723371d38811918f91229e72 100644 --- a/net/icmp/icmp.h +++ b/net/icmp/icmp.h @@ -90,10 +90,6 @@ struct icmp_conn_s struct iob_queue_s readahead; /* Read-ahead buffering */ #endif - - /* Defines the list of IPPROTO_ICMP callbacks */ - - struct devif_callback_s *list; }; #endif diff --git a/net/icmp/icmp_input.c b/net/icmp/icmp_input.c index 8d26f491ef3a4fbfb2d6fa163aa7e2954d93f80f..38937dad6427c5a5230cf4fd488ea2eaebf9500f 100644 --- a/net/icmp/icmp_input.c +++ b/net/icmp/icmp_input.c @@ -116,7 +116,7 @@ static uint16_t icmp_datahandler(FAR struct net_driver_s *dev, if (iob == NULL) { nerr("ERROR: Failed to create new I/O buffer chain\n"); - return 0; + goto drop; } /* Put the IPv4 address at the beginning of the read-ahead buffer */ @@ -143,8 +143,7 @@ static uint16_t icmp_datahandler(FAR struct net_driver_s *dev, */ nerr("ERROR: Failed to length to the I/O buffer chain: %d\n", ret); - (void)iob_free_chain(iob); - return 0; + goto drop_with_chain; } offset = sizeof(uint8_t); @@ -158,8 +157,7 @@ static uint16_t icmp_datahandler(FAR struct net_driver_s *dev, */ nerr("ERROR: Failed to source address to the I/O buffer chain: %d\n", ret); - (void)iob_free_chain(iob); - return 0; + goto drop_with_chain; } offset += sizeof(struct sockaddr_in); @@ -175,8 +173,7 @@ static uint16_t icmp_datahandler(FAR struct net_driver_s *dev, */ nerr("ERROR: Failed to add data to the I/O buffer chain: %d\n", ret); - (void)iob_free_chain(iob); - return 0; + goto drop_with_chain; } /* Add the new I/O buffer chain to the tail of the read-ahead queue (again @@ -187,12 +184,19 @@ static uint16_t icmp_datahandler(FAR struct net_driver_s *dev, if (ret < 0) { nerr("ERROR: Failed to queue the I/O buffer chain: %d\n", ret); - (void)iob_free_chain(iob); - return 0; + goto drop_with_chain; } ninfo("Buffered %d bytes\n", buflen + addrsize + 1); + dev->d_len = 0; return buflen; + +drop_with_chain: + (void)iob_free_chain(iob); + +drop: + dev->d_len = 0; + return 0; } #endif @@ -287,7 +291,7 @@ void icmp_input(FAR struct net_driver_s *dev) { uint16_t flags; - flags = devif_conn_event(dev, ipicmp, ICMP_ECHOREPLY, dev->d_conncb); + flags = devif_conn_event(dev, NULL, ICMP_ECHOREPLY, dev->d_conncb); if ((flags & ICMP_ECHOREPLY) != 0) { FAR struct icmp_conn_s *conn; diff --git a/net/icmp/icmp_netpoll.c b/net/icmp/icmp_netpoll.c index aad9f8f33d5ba6580ed5d05bdf4692d5ef750dd2..3903d64fc2799c2bbb23caef7ac800ac9309c06f 100644 --- a/net/icmp/icmp_netpoll.c +++ b/net/icmp/icmp_netpoll.c @@ -59,7 +59,8 @@ struct icmp_poll_s { - struct pollfd *fds; /* Needed to handle poll events */ + FAR struct socket *psock; /* IPPROTO_ICMP socket structure */ + FAR struct pollfd *fds; /* Needed to handle poll events */ FAR struct devif_callback_s *cb; /* Needed to teardown the poll */ }; @@ -92,20 +93,34 @@ static uint16_t icmp_poll_eventhandler(FAR struct net_driver_s *dev, FAR void *pvpriv, uint16_t flags) { FAR struct icmp_poll_s *info = (FAR struct icmp_poll_s *)pvpriv; - FAR struct icmp_conn_s *conn = (FAR struct icmp_conn_s *)pvconn; + FAR struct icmp_conn_s *conn; + FAR struct socket *psock; pollevent_t eventset; ninfo("flags: %04x\n", flags); - DEBUGASSERT(info == NULL || (info->fds != NULL && conn != NULL)); + DEBUGASSERT(info == NULL || info->fds != NULL); /* 'priv' might be null in some race conditions (?). Only process the * the event if this poll is from the same device that the request was * sent out on. */ - if (info != NULL && dev == conn->dev) + if (info != NULL) { + /* Is this a response on the same device that we sent the request out + * on? + */ + + psock = info->psock; + DEBUGASSERT(psock != NULL && psock->s_conn != NULL); + conn = psock->s_conn; + if (dev != conn->dev) + { + ninfo("Wrong device\n"); + return flags; + } + /* Check for data or connection availability events. */ eventset = 0; @@ -197,8 +212,9 @@ int icmp_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds) /* Initialize the poll info container */ - info->fds = fds; - info->cb = cb; + info->psock = psock; + info->fds = fds; + info->cb = cb; /* Initialize the callback structure. Save the reference to the info * structure as callback private data so that it will be available during diff --git a/net/icmpv6/Kconfig b/net/icmpv6/Kconfig index f78793e8b1f6a4023b1060ad2b916c055943d5f8..d7c1c6f547a6258e0b6f825f3c3d317cddad5754 100644 --- a/net/icmpv6/Kconfig +++ b/net/icmpv6/Kconfig @@ -93,6 +93,16 @@ config NET_ICMPv6_ROUTER if NET_ICMPv6_ROUTER +config NET_ICMPv6_ROUTER_MANUAL + bool "Manual router prefix" + default n + ---help--- + Select this to set the advertised router prefix manually. Otherwise, it + will be derived from the device IPv6 address and prefix length set in + the netdev structure. + +if NET_ICMPv6_ROUTER_MANUAL + config NET_ICMPv6_PREFLEN int "Prefix length" default 64 @@ -178,6 +188,7 @@ config NET_ICMPv6_PREFIX_8 Advertisement message. This is the last of the 8-values. The default for all eight values is fc00::0. +endif # NET_ICMPv6_ROUTER_MANUAL endif # NET_ICMPv6_ROUTER if NET_ICMPv6_SOCKET diff --git a/net/icmpv6/icmpv6.h b/net/icmpv6/icmpv6.h index 9353cbb20208d9a0f167e48d2342e62f4954c4b8..582712c5e532c3e7eab307eef036264fc8b79a7d 100644 --- a/net/icmpv6/icmpv6.h +++ b/net/icmpv6/icmpv6.h @@ -93,10 +93,6 @@ struct icmpv6_conn_s struct iob_queue_s readahead; /* Read-ahead buffering */ #endif - - /* Defines the list of IPPROTO_ICMP callbacks */ - - struct devif_callback_s *list; }; #endif diff --git a/net/icmpv6/icmpv6_advertise.c b/net/icmpv6/icmpv6_advertise.c index 703b3718a8604798f909f9580a87a9ed54931852..37c8c8ebb967120ff53015852934fafe6ec3c22a 100644 --- a/net/icmpv6/icmpv6_advertise.c +++ b/net/icmpv6/icmpv6_advertise.c @@ -53,6 +53,7 @@ #include #include #include +#include #include "netdev/netdev.h" #include "utils/utils.h" diff --git a/net/icmpv6/icmpv6_input.c b/net/icmpv6/icmpv6_input.c index 5fe32d6859007efff5d0dfac1c9b612aa25a3c0e..66030ad90106270b491a782d28170a6a5fda3698 100644 --- a/net/icmpv6/icmpv6_input.c +++ b/net/icmpv6/icmpv6_input.c @@ -126,7 +126,7 @@ static uint16_t icmpv6_datahandler(FAR struct net_driver_s *dev, if (iob == NULL) { nerr("ERROR: Failed to create new I/O buffer chain\n"); - return 0; + goto drop; } /* Put the IPv6 address at the beginning of the read-ahead buffer */ @@ -150,8 +150,7 @@ static uint16_t icmpv6_datahandler(FAR struct net_driver_s *dev, */ nerr("ERROR: Failed to length to the I/O buffer chain: %d\n", ret); - (void)iob_free_chain(iob); - return 0; + goto drop_with_chain; } offset = sizeof(uint8_t); @@ -165,8 +164,7 @@ static uint16_t icmpv6_datahandler(FAR struct net_driver_s *dev, */ nerr("ERROR: Failed to source address to the I/O buffer chain: %d\n", ret); - (void)iob_free_chain(iob); - return 0; + goto drop_with_chain; } offset += sizeof(struct sockaddr_in6); @@ -182,8 +180,7 @@ static uint16_t icmpv6_datahandler(FAR struct net_driver_s *dev, */ nerr("ERROR: Failed to add data to the I/O buffer chain: %d\n", ret); - (void)iob_free_chain(iob); - return 0; + goto drop_with_chain; } /* Add the new I/O buffer chain to the tail of the read-ahead queue (again @@ -194,12 +191,19 @@ static uint16_t icmpv6_datahandler(FAR struct net_driver_s *dev, if (ret < 0) { nerr("ERROR: Failed to queue the I/O buffer chain: %d\n", ret); - (void)iob_free_chain(iob); - return 0; + goto drop_with_chain; } ninfo("Buffered %d bytes\n", buflen + addrsize + 1); + dev->d_len = 0; return buflen; + +drop_with_chain: + (void)iob_free_chain(iob); + +drop: + dev->d_len = 0; + return 0; } #endif @@ -304,7 +308,7 @@ void icmpv6_input(FAR struct net_driver_s *dev) * response. */ - goto icmpv_send_nothing; + goto icmpv6_send_nothing; } } @@ -384,7 +388,7 @@ void icmpv6_input(FAR struct net_driver_s *dev) /* Yes.. Notify any waiting threads */ icmpv6_rnotify(dev, ipicmp->srcipaddr, opt->prefix, opt->preflen); - goto icmpv_send_nothing; + goto icmpv6_send_nothing; } /* Skip to the next option (units of octets) */ @@ -427,9 +431,9 @@ void icmpv6_input(FAR struct net_driver_s *dev) /* Dispatch the ECHO reply to the waiting thread */ - flags = devif_conn_event(dev, ipicmp, flags, dev->d_conncb); + flags = devif_conn_event(dev, NULL, flags, dev->d_conncb); - /* Wwas the ECHO reply consumed by any waiting thread? */ + /* Was the ECHO reply consumed by any waiting thread? */ if ((flags & ICMPv6_ECHOREPLY) != 0) { @@ -465,6 +469,8 @@ void icmpv6_input(FAR struct net_driver_s *dev) goto icmpv6_drop_packet; } } + + goto icmpv6_send_nothing; } break; #endif @@ -495,7 +501,7 @@ icmpv6_drop_packet: g_netstats.icmpv6.drop++; #endif -icmpv_send_nothing: +icmpv6_send_nothing: dev->d_len = 0; } diff --git a/net/icmpv6/icmpv6_netpoll.c b/net/icmpv6/icmpv6_netpoll.c index e646bbf4185616b668c8b3b403193d8812251bb7..6d9b39256716a033e0e856541e3152c1f9e68b42 100644 --- a/net/icmpv6/icmpv6_netpoll.c +++ b/net/icmpv6/icmpv6_netpoll.c @@ -59,7 +59,8 @@ struct icmpv6_poll_s { - struct pollfd *fds; /* Needed to handle poll events */ + FAR struct socket *psock; /* IPPROTO_ICMP6 socket structure */ + FAR struct pollfd *fds; /* Needed to handle poll events */ FAR struct devif_callback_s *cb; /* Needed to teardown the poll */ }; @@ -92,20 +93,34 @@ static uint16_t icmpv6_poll_eventhandler(FAR struct net_driver_s *dev, FAR void *pvpriv, uint16_t flags) { FAR struct icmpv6_poll_s *info = (FAR struct icmpv6_poll_s *)pvpriv; - FAR struct icmpv6_conn_s *conn = (FAR struct icmpv6_conn_s *)pvconn; + FAR struct icmpv6_conn_s *conn; + FAR struct socket *psock; pollevent_t eventset; ninfo("flags: %04x\n", flags); - DEBUGASSERT(info == NULL || (info->fds != NULL && conn != NULL)); + DEBUGASSERT(info == NULL || info->fds != NULL); /* 'priv' might be null in some race conditions (?). Only process the * the event if this poll is from the same device that the request was * sent out on. */ - if (info != NULL && dev == conn->dev) + if (info != NULL) { + /* Is this a response on the same device that we sent the request out + * on? + */ + + psock = info->psock; + DEBUGASSERT(psock != NULL && psock->s_conn != NULL); + conn = psock->s_conn; + if (dev != conn->dev) + { + ninfo("Wrong device\n"); + return flags; + } + /* Check for data or connection availability events. */ eventset = 0; @@ -197,8 +212,9 @@ int icmpv6_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds) /* Initialize the poll info container */ - info->fds = fds; - info->cb = cb; + info->psock = psock; + info->fds = fds; + info->cb = cb; /* Initialize the callback structure. Save the reference to the info * structure as callback private data so that it will be available during diff --git a/net/icmpv6/icmpv6_poll.c b/net/icmpv6/icmpv6_poll.c index 39af5d75c0b8c7e3dba57d309d2080e4760271dc..145dd62e69995cf825e129accdbec307f377237d 100644 --- a/net/icmpv6/icmpv6_poll.c +++ b/net/icmpv6/icmpv6_poll.c @@ -50,22 +50,6 @@ #include "devif/devif.h" #include "icmpv6/icmpv6.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/net/icmpv6/icmpv6_radvertise.c b/net/icmpv6/icmpv6_radvertise.c index 9c8464769abc52490d82e6399e67df7d499024c8..86c4f52430467119a905e6c2aca3054ce17b2e2b 100644 --- a/net/icmpv6/icmpv6_radvertise.c +++ b/net/icmpv6/icmpv6_radvertise.c @@ -74,6 +74,7 @@ * Private Data ****************************************************************************/ +#ifdef CONFIG_NET_ICMPv6_ROUTER_MANUAL static const net_ipv6addr_t g_ipv6_prefix = { HTONS(CONFIG_NET_ICMPv6_PREFIX_1), @@ -85,6 +86,7 @@ static const net_ipv6addr_t g_ipv6_prefix = HTONS(CONFIG_NET_ICMPv6_PREFIX_7), HTONS(CONFIG_NET_ICMPv6_PREFIX_8) }; +#endif /* CONFIG_NET_ICMPv6_ROUTER_MANUAL */ /**************************************************************************** * Private Functions @@ -106,6 +108,7 @@ static const net_ipv6addr_t g_ipv6_prefix = * ****************************************************************************/ +#ifndef CONFIG_NET_ICMPv6_ROUTER_MANUAL static inline void ipv6addr_mask(FAR uint16_t *dest, FAR const uint16_t *src, FAR const uint16_t *mask) { @@ -116,6 +119,7 @@ static inline void ipv6addr_mask(FAR uint16_t *dest, FAR const uint16_t *src, dest[i] = src[i] & mask[i]; } } +#endif /* !CONFIG_NET_ICMPv6_ROUTER_MANUAL */ /**************************************************************************** * Public Functions @@ -219,10 +223,17 @@ void icmpv6_radvertise(FAR struct net_driver_s *dev) prefix->reserved[0] = 0; prefix->reserved[1] = 0; +#ifdef CONFIG_NET_ICMPv6_ROUTER_MANUAL + /* Copy the configured prefex */ + + prefix->preflen = CONFIG_NET_ICMPv6_PREFLEN; + net_ipv6addr_copy(prefix->prefix, g_ipv6_prefix); +#else /* Set the prefix and prefix length based on net driver IP and netmask */ - prefix->preflen = net_ipv6_mask2pref(dev->d_ipv6netmask); + prefix->preflen = net_ipv6_mask2pref(dev->d_ipv6netmask); ipv6addr_mask(prefix->prefix, dev->d_ipv6addr, dev->d_ipv6netmask); +#endif /* CONFIG_NET_ICMPv6_ROUTER_MANUAL */ /* Calculate the checksum over both the ICMP header and payload */ diff --git a/net/icmpv6/icmpv6_sendto.c b/net/icmpv6/icmpv6_sendto.c index bd876e86de79585852c5f9b83d6e7c5a714a0361..cbff44a3ea70f4d83b1b22c670af8651a729513a 100644 --- a/net/icmpv6/icmpv6_sendto.c +++ b/net/icmpv6/icmpv6_sendto.c @@ -223,7 +223,7 @@ static void sendto_request(FAR struct net_driver_s *dev, * * Parameters: * dev The structure of the network driver that caused the interrupt - * conn The received packet, cast to void * + * pvconn The received packet, cast to void * * pvpriv An instance of struct icmpv6_sendto_s cast to void* * flags Set of events describing why the callback was invoked * @@ -236,7 +236,7 @@ static void sendto_request(FAR struct net_driver_s *dev, ****************************************************************************/ static uint16_t sendto_eventhandler(FAR struct net_driver_s *dev, - FAR void *conn, + FAR void *pvconn, FAR void *pvpriv, uint16_t flags) { FAR struct icmpv6_sendto_s *pstate = (struct icmpv6_sendto_s *)pvpriv; diff --git a/net/icmpv6/icmpv6_solicit.c b/net/icmpv6/icmpv6_solicit.c index d4a7824f77f272493075d5a93bbe935e6d4a3aed..7fa1a55d19f20a646cfe8fc7d1f9b726cd1cbe66 100644 --- a/net/icmpv6/icmpv6_solicit.c +++ b/net/icmpv6/icmpv6_solicit.c @@ -46,6 +46,7 @@ #include #include #include +#include #include "devif/devif.h" #include "netdev/netdev.h" diff --git a/net/inet/inet_close.c b/net/inet/inet_close.c index 66b798a305e20c5d88f001deca0e875068ca15ed..a36089e541716eec081452cbc9a07094174439e7 100644 --- a/net/inet/inet_close.c +++ b/net/inet/inet_close.c @@ -345,7 +345,18 @@ static inline int tcp_close_disconnect(FAR struct socket *psock) #ifdef CONFIG_NET_TCP_WRITE_BUFFERS /* If we have a semi-permanent write buffer callback in place, then - * release it now. + * is needs to be be nullifed. + * + * Commit f1ef2c6cdeb032eaa1833cc534a63b50c5058270: + * "When a socket is closed, it should make sure that any pending write + * data is sent before the FIN is sent. It already would wait for all + * sent data to be acked, however it would discard any pending write + * data that had not been sent at least once. + * + * "This change adds a check for pending write data in addition to unacked + * data. However, to be able to actually send any new data, the send + * callback must be left. The callback should be freed later when the + * socket is actually destroyed." */ psock->s_sndcb = NULL; diff --git a/net/ipforward/ipfwd_forward.c b/net/ipforward/ipfwd_forward.c index 67d0ce1c263b1d18fed2588d82eea4aee5e0dfe1..5ead791b6bf10c0013651dda2c89d10f66b044ec 100644 --- a/net/ipforward/ipfwd_forward.c +++ b/net/ipforward/ipfwd_forward.c @@ -171,8 +171,8 @@ static inline bool ipfwd_addrchk(FAR struct forward_s *fwd) else #endif { -#if !defined(CONFIG_NET_ICMPv6_NEIGHBOR) - FAR struct ipv6_hdr_s *ipv4 = (FAR struct ipv6_hdr_s *)fwd->f_iob->io_data; +#if defined(CONFIG_NET_ICMPv6_NEIGHBOR) + FAR struct ipv6_hdr_s *ipv6 = (FAR struct ipv6_hdr_s *)fwd->f_iob->io_data; return (neighbor_findentry(ipv6->destipaddr) != NULL); #else return true; diff --git a/net/local/local.h b/net/local/local.h index 6c1427d089dd1e2e2ef77cc47bcbf57d93d27ff3..b4ccfd9a8a038a2d373eda987e6197d71acfda55 100644 --- a/net/local/local.h +++ b/net/local/local.h @@ -51,6 +51,7 @@ #include #include +#include #include #ifdef CONFIG_NET_LOCAL @@ -143,8 +144,8 @@ struct local_conn_s uint8_t lc_proto; /* SOCK_STREAM or SOCK_DGRAM */ uint8_t lc_type; /* See enum local_type_e */ uint8_t lc_state; /* See enum local_state_e */ - int16_t lc_infd; /* File descriptor of read-only FIFO (peers) */ - int16_t lc_outfd; /* File descriptor of write-only FIFO (peers) */ + struct file lc_infile; /* File for read-only FIFO (peers) */ + struct file lc_outfile; /* File descriptor of write-only FIFO (peers) */ char lc_path[UNIX_PATH_MAX]; /* Path assigned by bind() */ int32_t lc_instance_id; /* Connection instance ID for stream * server<->client connection pair */ @@ -424,7 +425,7 @@ ssize_t psock_local_sendto(FAR struct socket *psock, FAR const void *buf, * Send a packet on the write-only FIFO. * * Parameters: - * fd File descriptor of write-only FIFO. + * filep File structure of write-only FIFO. * buf Data to send * len Length of data to send * @@ -434,7 +435,8 @@ ssize_t psock_local_sendto(FAR struct socket *psock, FAR const void *buf, * ****************************************************************************/ -int local_send_packet(int fd, FAR const uint8_t *buf, size_t len); +int local_send_packet(FAR struct file *filep, FAR const uint8_t *buf, + size_t len); /**************************************************************************** * Name: local_recvfrom @@ -475,10 +477,10 @@ ssize_t local_recvfrom(FAR struct socket *psock, FAR void *buf, * Read a data from the read-only FIFO. * * Parameters: - * fd - File descriptor of read-only FIFO. - * buf - Local to store the received data - * len - Length of data to receive [in] - * Length of data actually received [out] + * filep - File structure of write-only FIFO. + * buf - Local to store the received data + * len - Length of data to receive [in] + * Length of data actually received [out] * * Return: * Zero is returned on success; a negated errno value is returned on any @@ -488,7 +490,7 @@ ssize_t local_recvfrom(FAR struct socket *psock, FAR void *buf, * ****************************************************************************/ -int local_fifo_read(int fd, FAR uint8_t *buf, size_t *len); +int local_fifo_read(FAR struct file *filep, FAR uint8_t *buf, size_t *len); /**************************************************************************** * Name: local_getaddr @@ -517,7 +519,7 @@ int local_getaddr(FAR struct local_conn_s *conn, FAR struct sockaddr *addr, * Read a sync bytes until the start of the packet is found. * * Parameters: - * fd - File descriptor of read-only FIFO. + * filep - File structure of write-only FIFO. * * Return: * The non-zero size of the following packet is returned on success; a @@ -525,7 +527,7 @@ int local_getaddr(FAR struct local_conn_s *conn, FAR struct sockaddr *addr, * ****************************************************************************/ -int local_sync(int fd); +int local_sync(FAR struct file *filep); /**************************************************************************** * Name: local_create_fifos diff --git a/net/local/local_accept.c b/net/local/local_accept.c index db70ace1eec39ee8b735fdb78914fcefa96ddf5e..f8fb468ad5cab54589e7e5fd10c14e0a1982d417 100644 --- a/net/local/local_accept.c +++ b/net/local/local_accept.c @@ -201,7 +201,7 @@ int local_accept(FAR struct socket *psock, FAR struct sockaddr *addr, if (ret == OK) { - DEBUGASSERT(conn->lc_outfd >= 0); + DEBUGASSERT(conn->lc_outfile.f_inode != NULL); /* Open the server-side read-only FIFO. This should not * block because the client side has already opening it @@ -221,7 +221,7 @@ int local_accept(FAR struct socket *psock, FAR struct sockaddr *addr, if (ret == OK) { - DEBUGASSERT(conn->lc_infd >= 0); + DEBUGASSERT(conn->lc_infile.f_inode != NULL); /* Return the address family */ diff --git a/net/local/local_conn.c b/net/local/local_conn.c index ea7c482a60998120bc0ca8cb17043f87870c4563..5ec7f72dc3013b734cf75280b4da21cfefb8e1fa 100644 --- a/net/local/local_conn.c +++ b/net/local/local_conn.c @@ -91,8 +91,8 @@ FAR struct local_conn_s *local_alloc(void) { /* Initialize non-zero elements the new connection structure */ - conn->lc_infd = -1; - conn->lc_outfd = -1; + conn->lc_infile.f_inode = NULL; + conn->lc_outfile.f_inode = NULL; #ifdef CONFIG_NET_LOCAL_STREAM /* This semaphore is used for signaling and, hence, should not have @@ -126,18 +126,18 @@ void local_free(FAR struct local_conn_s *conn) /* Make sure that the read-only FIFO is closed */ - if (conn->lc_infd >= 0) + if (conn->lc_infile.f_inode != NULL) { - close(conn->lc_infd); - conn->lc_infd = -1; + file_close_detached(&conn->lc_infile); + conn->lc_infile.f_inode = NULL; } /* Make sure that the write-only FIFO is closed */ - if (conn->lc_outfd >= 0) + if (conn->lc_outfile.f_inode != NULL) { - close(conn->lc_outfd); - conn->lc_outfd = -1; + file_close_detached(&conn->lc_outfile); + conn->lc_outfile.f_inode = NULL; } #ifdef CONFIG_NET_LOCAL_STREAM diff --git a/net/local/local_connect.c b/net/local/local_connect.c index c37f5b34fe1fe80bd091f566ae58871a056b56ff..9a875b314b7e8425bdb6ff57bffe70a82186e039 100644 --- a/net/local/local_connect.c +++ b/net/local/local_connect.c @@ -182,7 +182,7 @@ static int inline local_stream_connect(FAR struct local_conn_s *client, goto errout_with_fifos; } - DEBUGASSERT(client->lc_outfd >= 0); + DEBUGASSERT(client->lc_outfile.f_inode != NULL); /* Add ourself to the list of waiting connections and notify the server. */ @@ -225,13 +225,13 @@ static int inline local_stream_connect(FAR struct local_conn_s *client, goto errout_with_outfd; } - DEBUGASSERT(client->lc_infd >= 0); + DEBUGASSERT(client->lc_infile.f_inode != NULL); client->lc_state = LOCAL_STATE_CONNECTED; return OK; errout_with_outfd: - (void)close(client->lc_outfd); - client->lc_outfd = -1; + (void)file_close_detached(&client->lc_outfile); + client->lc_outfile.f_inode = NULL; errout_with_fifos: (void)local_release_fifos(client); diff --git a/net/local/local_fifo.c b/net/local/local_fifo.c index ff53d400246be672c759705e1c9dd703cdb9123c..85d8769816a2edb2747ec2d4cd47c85ba5bb44f2 100644 --- a/net/local/local_fifo.c +++ b/net/local/local_fifo.c @@ -253,9 +253,11 @@ static int local_rx_open(FAR struct local_conn_s *conn, FAR const char *path, bool nonblock) { int oflags = nonblock ? O_RDONLY | O_NONBLOCK : O_RDONLY; + int ret; + int fd; - conn->lc_infd = open(path, oflags); - if (conn->lc_infd < 0) + fd = open(path, oflags); + if (fd < 0) { int errcode = get_errno(); DEBUGASSERT(errcode > 0); @@ -274,6 +276,15 @@ static int local_rx_open(FAR struct local_conn_s *conn, FAR const char *path, return errcode == ENOENT ? -EFAULT : -errcode; } + /* Detach the file descriptor from the open file instance */ + + ret = file_detach(fd, &conn->lc_infile); + if (ret < 0) + { + close(fd); + return ret; + } + return OK; } @@ -289,9 +300,11 @@ static int local_tx_open(FAR struct local_conn_s *conn, FAR const char *path, bool nonblock) { int oflags = nonblock ? O_WRONLY | O_NONBLOCK : O_WRONLY; + int ret; + int fd; - conn->lc_outfd = open(path, oflags); - if (conn->lc_outfd < 0) + fd = open(path, oflags); + if (fd < 0) { int errcode = get_errno(); DEBUGASSERT(errcode > 0); @@ -310,6 +323,15 @@ static int local_tx_open(FAR struct local_conn_s *conn, FAR const char *path, return errcode == ENOENT ? -EFAULT : -errcode; } + /* Detach the file descriptor from the open file instance */ + + ret = file_detach(fd, &conn->lc_outfile); + if (ret < 0) + { + close(fd); + return ret; + } + return OK; } @@ -324,23 +346,19 @@ static int local_tx_open(FAR struct local_conn_s *conn, FAR const char *path, * ****************************************************************************/ -static int local_set_policy(int fd, unsigned long policy) +static int local_set_policy(FAR struct file *filep, unsigned long policy) { int ret; /* Set the buffer policy */ - ret = ioctl(fd, PIPEIOC_POLICY, policy); + ret = file_ioctl(filep, PIPEIOC_POLICY, policy); if (ret < 0) { - int errcode = get_errno(); - DEBUGASSERT(errcode > 0); - - nerr("ERROR: Failed to set FIFO buffer policty: %d\n", errcode); - return -errcode; + nerr("ERROR: Failed to set FIFO buffer policty: %d\n", ret); } - return OK; + return ret; } /**************************************************************************** @@ -492,7 +510,7 @@ int local_open_client_rx(FAR struct local_conn_s *client, bool nonblock) { /* Policy: Free FIFO resources when the last reference is closed */ - ret = local_set_policy(client->lc_infd, 0); + ret = local_set_policy(&client->lc_infile, 0); } return ret; @@ -524,7 +542,7 @@ int local_open_client_tx(FAR struct local_conn_s *client, bool nonblock) { /* Policy: Free FIFO resources when the last reference is closed */ - ret = local_set_policy(client->lc_outfd, 0); + ret = local_set_policy(&client->lc_outfile, 0); } return ret; @@ -556,7 +574,7 @@ int local_open_server_rx(FAR struct local_conn_s *server, bool nonblock) { /* Policy: Free FIFO resources when the last reference is closed */ - ret = local_set_policy(server->lc_infd, 0); + ret = local_set_policy(&server->lc_infile, 0); } return ret; @@ -588,7 +606,7 @@ int local_open_server_tx(FAR struct local_conn_s *server, bool nonblock) { /* Policy: Free FIFO resources when the last reference is closed */ - ret = local_set_policy(server->lc_outfd, 0); + ret = local_set_policy(&server->lc_outfile, 0); } return ret; @@ -620,7 +638,7 @@ int local_open_receiver(FAR struct local_conn_s *conn, bool nonblock) { /* Policy: Free FIFO resources when the buffer is empty. */ - ret = local_set_policy(conn->lc_infd, 1); + ret = local_set_policy(&conn->lc_infile, 1); } return ret; @@ -653,7 +671,7 @@ int local_open_sender(FAR struct local_conn_s *conn, FAR const char *path, { /* Policy: Free FIFO resources when the buffer is empty. */ - ret = local_set_policy(conn->lc_outfd, 1); + ret = local_set_policy(&conn->lc_outfile, 1); } return ret; diff --git a/net/local/local_netpoll.c b/net/local/local_netpoll.c index a8d1c0ca04bd51ea7af26c7d0c032a7af2f23a50..81aff7c0517303dde3bb36d782a18808751ebea5 100644 --- a/net/local/local_netpoll.c +++ b/net/local/local_netpoll.c @@ -208,7 +208,8 @@ int local_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds) /* Poll wants to check state for both input and output. */ - if (conn->lc_infd < 0 || conn->lc_outfd < 0) + if (conn->lc_infile.f_inode == NULL || + conn->lc_outfile.f_inode == NULL) { fds->priv = NULL; goto pollerr; @@ -222,23 +223,23 @@ int local_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds) return -ENOMEM; } - shadowfds[0].fd = conn->lc_infd; - shadowfds[0].sem = fds->sem; + shadowfds[0].fd = 0; /* Does not matter */ + shadowfds[0].sem = fds->sem; shadowfds[0].events = fds->events & ~POLLOUT; - shadowfds[1].fd = conn->lc_outfd; - shadowfds[1].sem = fds->sem; + shadowfds[1].fd = 1; /* Does not matter */ + shadowfds[1].sem = fds->sem; shadowfds[1].events = fds->events & ~POLLIN; /* Setup poll for both shadow pollfds. */ - ret = fdesc_poll(conn->lc_infd, &shadowfds[0], true); + ret = file_poll(&conn->lc_infile, &shadowfds[0], true); if (ret >= 0) { - ret = fdesc_poll(conn->lc_outfd, &shadowfds[1], true); + ret = file_poll(&conn->lc_outfile, &shadowfds[1], true); if (ret < 0) { - (void)fdesc_poll(conn->lc_infd, &shadowfds[0], false); + (void)file_poll(&conn->lc_infile, &shadowfds[0], false); } } @@ -260,13 +261,13 @@ int local_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds) { /* Poll wants to check state for input only. */ - if (conn->lc_infd < 0) + if (conn->lc_infile.f_inode == NULL) { fds->priv = NULL; goto pollerr; } - ret = fdesc_poll(conn->lc_infd, fds, true); + ret = file_poll(&conn->lc_infile, fds, true); } break; @@ -274,13 +275,13 @@ int local_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds) { /* Poll wants to check state for output only. */ - if (conn->lc_outfd < 0) + if (conn->lc_outfile.f_inode == NULL) { fds->priv = NULL; goto pollerr; } - ret = fdesc_poll(conn->lc_outfd, fds, true); + ret = file_poll(&conn->lc_outfile, fds, true); } break; @@ -350,18 +351,15 @@ int local_pollteardown(FAR struct socket *psock, FAR struct pollfd *fds) return OK; } - DEBUGASSERT(shadowfds[0].fd == conn->lc_infd); - DEBUGASSERT(shadowfds[1].fd == conn->lc_outfd); - /* Teardown for both shadow pollfds. */ - ret = fdesc_poll(conn->lc_infd, &shadowfds[0], false); + ret = file_poll(&conn->lc_infile, &shadowfds[0], false); if (ret < 0) { status = ret; } - ret = fdesc_poll(conn->lc_outfd, &shadowfds[1], false); + ret = file_poll(&conn->lc_outfile, &shadowfds[1], false); if (ret < 0) { status = ret; @@ -380,7 +378,7 @@ int local_pollteardown(FAR struct socket *psock, FAR struct pollfd *fds) return OK; } - status = fdesc_poll(conn->lc_infd, fds, false); + status = file_poll(&conn->lc_infile, fds, false); } break; @@ -391,7 +389,7 @@ int local_pollteardown(FAR struct socket *psock, FAR struct pollfd *fds) return OK; } - status = fdesc_poll(conn->lc_outfd, fds, false); + status = file_poll(&conn->lc_outfile, fds, false); } break; diff --git a/net/local/local_recvfrom.c b/net/local/local_recvfrom.c index f9de54d6d1081a9df302bb73b33f113b824f0597..389739e190c9e35cf9f236c3810a0ee58ca32eec 100644 --- a/net/local/local_recvfrom.c +++ b/net/local/local_recvfrom.c @@ -79,7 +79,7 @@ static int psock_fifo_read(FAR struct socket *psock, FAR void *buf, FAR struct local_conn_s *conn = (FAR struct local_conn_s *)psock->s_conn; int ret; - ret = local_fifo_read(conn->lc_infd, buf, readlen); + ret = local_fifo_read(&conn->lc_infile, buf, readlen); if (ret < 0) { /* -ECONNRESET is a special case. We may or not have received @@ -161,7 +161,7 @@ psock_stream_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, /* The incoming FIFO should be open */ - DEBUGASSERT(conn->lc_infd >= 0); + DEBUGASSERT(conn->lc_infile.f_inode != NULL); /* Are there still bytes in the FIFO from the last packet? */ @@ -171,7 +171,7 @@ psock_stream_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, * the size of the next packet. */ - ret = local_sync(conn->lc_infd); + ret = local_sync(&conn->lc_infile); if (ret < 0) { nerr("ERROR: Failed to get packet length: %d\n", ret); @@ -265,7 +265,7 @@ psock_dgram_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, /* The incoming FIFO should not be open */ - DEBUGASSERT(conn->lc_infd < 0); + DEBUGASSERT(conn->lc_infile.f_inode == NULL); /* Make sure that half duplex FIFO has been created */ @@ -292,7 +292,7 @@ psock_dgram_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, * the next packet. */ - ret = local_sync(conn->lc_infd); + ret = local_sync(&conn->lc_infile); if (ret < 0) { nerr("ERROR: Failed to get packet length: %d\n", ret); @@ -348,8 +348,8 @@ psock_dgram_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, /* Now we can close the read-only file descriptor */ - close(conn->lc_infd); - conn->lc_infd = -1; + file_close_detached(&conn->lc_infile); + conn->lc_infile.f_inode = NULL; /* Release our reference to the half duplex FIFO */ @@ -371,8 +371,8 @@ psock_dgram_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, errout_with_infd: /* Close the read-only file descriptor */ - close(conn->lc_infd); - conn->lc_infd = -1; + file_close_detached(&conn->lc_infile); + conn->lc_infile.f_inode = NULL; errout_with_halfduplex: /* Release our reference to the half duplex FIFO */ diff --git a/net/local/local_recvutils.c b/net/local/local_recvutils.c index 5abf57483240258d9b6d14f1ce2d624dfc4bcfb0..91e185754f410bae2971b96aa87a3eea515951af 100644 --- a/net/local/local_recvutils.c +++ b/net/local/local_recvutils.c @@ -64,10 +64,10 @@ * Read a data from the read-only FIFO. * * Parameters: - * fd - File descriptor of read-only FIFO. - * buf - Local to store the received data - * len - Length of data to receive [in] - * Length of data actually received [out] + * filep - File structure of write-only FIFO. + * buf - Local to store the received data + * len - Length of data to receive [in] + * Length of data actually received [out] * * Return: * Zero is returned on success; a negated errno value is returned on any @@ -77,7 +77,7 @@ * ****************************************************************************/ -int local_fifo_read(int fd, FAR uint8_t *buf, size_t *len) +int local_fifo_read(FAR struct file *filep, FAR uint8_t *buf, size_t *len) { ssize_t remaining; ssize_t nread; @@ -88,7 +88,7 @@ int local_fifo_read(int fd, FAR uint8_t *buf, size_t *len) remaining = *len; while (remaining > 0) { - nread = nx_read(fd, buf, remaining); + nread = file_read(filep, buf, remaining); if (nread < 0) { if (nread != -EINTR) @@ -131,7 +131,7 @@ errout: * Read a sync bytes until the start of the packet is found. * * Parameters: - * fd - File descriptor of read-only FIFO. + * filep - File structure of write-only FIFO. * * Return: * The non-zero size of the following packet is returned on success; a @@ -139,7 +139,7 @@ errout: * ****************************************************************************/ -int local_sync(int fd) +int local_sync(FAR struct file *filep) { size_t readlen; uint16_t pktlen; @@ -157,7 +157,7 @@ int local_sync(int fd) do { readlen = sizeof(uint8_t); - ret = local_fifo_read(fd, &sync, &readlen); + ret = local_fifo_read(filep, &sync, &readlen); if (ret < 0) { nerr("ERROR: Failed to read sync bytes: %d\n", ret); @@ -171,7 +171,7 @@ int local_sync(int fd) do { readlen = sizeof(uint8_t); - ret = local_fifo_read(fd, &sync, &readlen); + ret = local_fifo_read(filep, &sync, &readlen); if (ret < 0) { nerr("ERROR: Failed to read sync bytes: %d\n", ret); @@ -185,7 +185,7 @@ int local_sync(int fd) /* Then read the packet length */ readlen = sizeof(uint16_t); - ret = local_fifo_read(fd, (FAR uint8_t *)&pktlen, &readlen); + ret = local_fifo_read(filep, (FAR uint8_t *)&pktlen, &readlen); return ret < 0 ? ret : pktlen; } diff --git a/net/local/local_send.c b/net/local/local_send.c index 4d37cbd9cc9669c5273f2f653f53e6bdea55b6ad..a305dac44116798e2d7ec316350d0187f42f32d5 100644 --- a/net/local/local_send.c +++ b/net/local/local_send.c @@ -87,7 +87,7 @@ ssize_t psock_local_send(FAR struct socket *psock, FAR const void *buf, */ if (peer->lc_state != LOCAL_STATE_CONNECTED || - peer->lc_outfd < 0) + peer->lc_outfile.f_inode == NULL) { nerr("ERROR: not connected\n"); return -ENOTCONN; @@ -95,7 +95,7 @@ ssize_t psock_local_send(FAR struct socket *psock, FAR const void *buf, /* Send the packet */ - ret = local_send_packet(peer->lc_outfd, (FAR uint8_t *)buf, len); + ret = local_send_packet(&peer->lc_outfile, (FAR uint8_t *)buf, len); /* If the send was successful, then the full packet will have been sent */ diff --git a/net/local/local_sendpacket.c b/net/local/local_sendpacket.c index e8491db58edf74a207af6423928a6b98d845de4a..fad305fd0b47b8d5a3bc00fcf9f7ed2d854cd307 100644 --- a/net/local/local_sendpacket.c +++ b/net/local/local_sendpacket.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/local/local_sendpacket.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -79,7 +79,7 @@ static const uint8_t g_preamble[LOCAL_PREAMBLE_SIZE] = * Write a data on the write-only FIFO. * * Parameters: - * fd File descriptor of write-only FIFO. + * filep File structure of write-only FIFO. * buf Data to send * len Length of data to send * @@ -89,13 +89,14 @@ static const uint8_t g_preamble[LOCAL_PREAMBLE_SIZE] = * ****************************************************************************/ -static int local_fifo_write(int fd, FAR const uint8_t *buf, size_t len) +static int local_fifo_write(FAR struct file *filep, FAR const uint8_t *buf, + size_t len) { ssize_t nwritten; while (len > 0) { - nwritten = nx_write(fd, buf, len); + nwritten = file_write(filep, buf, len); if (nwritten < 0) { if (nwritten != -EINTR) @@ -128,7 +129,7 @@ static int local_fifo_write(int fd, FAR const uint8_t *buf, size_t len) * Send a packet on the write-only FIFO. * * Parameters: - * fd File descriptor of write-only FIFO. + * filep File structure of write-only FIFO. * buf Data to send * len Length of data to send * @@ -138,25 +139,27 @@ static int local_fifo_write(int fd, FAR const uint8_t *buf, size_t len) * ****************************************************************************/ -int local_send_packet(int fd, FAR const uint8_t *buf, size_t len) +int local_send_packet(FAR struct file *filep, FAR const uint8_t *buf, + size_t len) { uint16_t len16; int ret; /* Send the packet preamble */ - ret = local_fifo_write(fd, g_preamble, LOCAL_PREAMBLE_SIZE); + ret = local_fifo_write(filep, g_preamble, LOCAL_PREAMBLE_SIZE); if (ret == OK) { /* Send the packet length */ len16 = len; - ret = local_fifo_write(fd, (FAR const uint8_t *)&len16, sizeof(uint16_t)); + ret = local_fifo_write(filep, (FAR const uint8_t *)&len16, + sizeof(uint16_t)); if (ret == OK) { /* Send the packet data */ - ret = local_fifo_write(fd, buf, len); + ret = local_fifo_write(filep, buf, len); } } diff --git a/net/local/local_sendto.c b/net/local/local_sendto.c index de59ee34f9e18bd9b7a718d17bbc402488233bf8..ec7509a0ec0adc90aa4e90830c3737c1262e7579 100644 --- a/net/local/local_sendto.c +++ b/net/local/local_sendto.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/local/local_sendto.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -112,7 +112,7 @@ ssize_t psock_local_sendto(FAR struct socket *psock, FAR const void *buf, /* The outgoing FIFO should not be open */ - DEBUGASSERT(conn->lc_outfd < 0); + DEBUGASSERT(conn->lc_outfile.f_inode == 0); /* At present, only standard pathname type address are support */ @@ -150,7 +150,7 @@ ssize_t psock_local_sendto(FAR struct socket *psock, FAR const void *buf, /* Send the packet */ - nsent = local_send_packet(conn->lc_outfd, buf, len); + nsent = local_send_packet(&conn->lc_outfile, buf, len); if (nsent < 0) { nerr("ERROR: Failed to send the packet: %d\n", ret); @@ -164,8 +164,8 @@ ssize_t psock_local_sendto(FAR struct socket *psock, FAR const void *buf, /* Now we can close the write-only socket descriptor */ - close(conn->lc_outfd); - conn->lc_outfd = -1; + file_close_detached(&conn->lc_outfile); + conn->lc_outfile.f_inode = NULL; errout_with_halfduplex: /* Release our reference to the half duplex FIFO */ diff --git a/net/netdev/netdev_ioctl.c b/net/netdev/netdev_ioctl.c index b4ba8e4553db8f42bdd5a409bbcfd498647b6502..e4b1e13a46314a7e6ad2aa54c54164011a6d036a 100644 --- a/net/netdev/netdev_ioctl.c +++ b/net/netdev/netdev_ioctl.c @@ -279,6 +279,30 @@ static void ioctl_get_ipv4addr(FAR struct sockaddr *outaddr, } #endif +/**************************************************************************** + * Name: ioctl_get_ipv4broadcast + * + * Description: + * Return the sub-net broadcast address to user memory. + * + * Input Parameters: + * outaddr - Pointer to the user-provided memory to receive the address. + * inaddr - The source IP address in the device structure. + * netmask - The netmask address mask in the device structure. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_IPv4 +static void inline ioctl_get_ipv4broadcast(FAR struct sockaddr *outaddr, + in_addr_t inaddr, in_addr_t netmask) +{ + FAR struct sockaddr_in *dest = (FAR struct sockaddr_in *)outaddr; + dest->sin_family = AF_INET; + dest->sin_port = 0; + dest->sin_addr.s_addr = net_ipv4addr_broadcast(inaddr, netmask); +} +#endif + /**************************************************************************** * Name: ioctl_get_ipv6addr * @@ -627,6 +651,19 @@ static int netdev_ifr_ioctl(FAR struct socket *psock, int cmd, #ifdef CONFIG_NET_IPv4 case SIOCGIFBRDADDR: /* Get broadcast IP address */ + { + dev = netdev_ifr_dev(req); + if (dev) + { + ioctl_get_ipv4broadcast(&req->ifr_broadaddr, dev->d_ipaddr, + dev->d_netmask); + ret = OK; + } + } + break; +#endif + +#ifdef CONFIG_NET_IPv4 case SIOCSIFBRDADDR: /* Set broadcast IP address */ { ret = -ENOSYS; diff --git a/net/pkt/pkt_conn.c b/net/pkt/pkt_conn.c index 95b08235f97b3c28b5ff075cf4582b5370233f5a..13f5c92dfe1992295d82973ff5440c833aad04d0 100644 --- a/net/pkt/pkt_conn.c +++ b/net/pkt/pkt_conn.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/pkt/pkt_conn.c * - * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Large parts of this file were leveraged from uIP logic: @@ -43,13 +43,13 @@ #include #if defined(CONFIG_NET) && defined(CONFIG_NET_PKT) -#include #include #include #include #include +#include #include #include #include diff --git a/net/pkt/pkt_finddev.c b/net/pkt/pkt_finddev.c index 69f53ec2cf2d00d2e7ba0003ae8976bab51aef78..a3f0c592e2341c8726e8629e61e25688c56a5bfd 100644 --- a/net/pkt/pkt_finddev.c +++ b/net/pkt/pkt_finddev.c @@ -65,8 +65,6 @@ FAR struct net_driver_s *pkt_find_device(FAR struct pkt_conn_s *conn) { - FAR struct net_driver_s *dev; - /* REVISIT: This is bogus. A better network device lookup is needed. */ return netdev_findbyname("eth0"); diff --git a/net/route/Kconfig b/net/route/Kconfig index 21026f61ce9e1e5d1f7590e417f7ea7f5eaf88f3..8c291a9edb65845405e6216bbc731661e5892a39 100644 --- a/net/route/Kconfig +++ b/net/route/Kconfig @@ -42,18 +42,6 @@ config ROUTE_IPv4_FILEROUTE ---help--- Select to used a IPv4 routing table in a file in a mounted file system. - REVISIT: There is a problem with the current design. NuttX does not - currently support truncate(). Therefore, it is not possible to delete - entries from the routing table file. - - In this current implementation, that leaves the last entry intact at - the end of the file. An alternative design might include a tag on - each record to indicate if the record is valid or not. That would work - but would add complexity to the other routing table functions. - - The existing 'delroute' implementation is available for testing purpose - only if CONFIG_EXPERIMENTAL=y. - endchoice # IPv4 routing table config ROUTE_MAX_IPv4_RAMROUTES @@ -111,18 +99,6 @@ config ROUTE_IPv6_FILEROUTE ---help--- Select to use a IPv6 routing table in a file in a mounted file system. - REVISIT: There is a problem with the current design. NuttX does not - currently support truncate(). Therefore, it is not possible to delete - entries from the routing table file. - - In this current implementation, that leaves the last entry intact at - the end of the file. An alternative design might include a tag on - each record to indicate if the record is valid or not. That would work - but would add complexity to the other routing table functions. - - The existing 'delroute' implementation is available for testing purpose - only if CONFIG_EXPERIMENTAL=y. - endchoice # IPv6 routing table config ROUTE_MAX_IPv6_RAMROUTES diff --git a/net/route/net_cacheroute.c b/net/route/net_cacheroute.c index 6c601ca5cfd6630dd5e45b6b2b288296bffcd04a..8050962d1eb29b9231180cdef00aa399f03333c3 100644 --- a/net/route/net_cacheroute.c +++ b/net/route/net_cacheroute.c @@ -45,6 +45,8 @@ #include #include +#include + #include "route/cacheroute.h" #include "route/route.h" @@ -177,8 +179,8 @@ static sem_t g_ipv6_cachelock; * ****************************************************************************/ -#define net_lock_ipv4_cache() mxsem_wait(&g_ipv4_cachelock); -#define net_lock_ipv6_cache() mxsem_wait(&g_ipv6_cachelock); +#define net_lock_ipv4_cache() nxsem_wait(&g_ipv4_cachelock); +#define net_lock_ipv6_cache() nxsem_wait(&g_ipv6_cachelock); /**************************************************************************** * Name: net_unlock_ipv4_cache and net_unlock_ipv6_cache diff --git a/net/route/net_del_fileroute.c b/net/route/net_del_fileroute.c index 6f57033762aab874145277d9df094778468035b2..992ff3e2f5ec5e2060ec8b8db2c770826ae11ae9 100644 --- a/net/route/net_del_fileroute.c +++ b/net/route/net_del_fileroute.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/route/net_del_fileroute.c * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -40,6 +40,7 @@ #include #include +#include #include #include #include @@ -56,26 +57,6 @@ #if defined(CONFIG_ROUTE_IPv4_FILEROUTE) || defined(CONFIG_ROUTE_IPv6_FILEROUTE) -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* REVISIT: There is a problem with this design. NuttX does not currently - * support truncate(). Therefore, it is not possible to delete entries from - * the routing table file. - * - * In this current implementation, that leaves the last entry intact at the - * end of the file. An alternative design might include a tag on each - * record to indicate if the record is valid or not. That would work but - * would add complexity to the other routing table functions. - * - * The existing implementation is available only if CONFIG_EXPERIMENTAL=y. - */ - -#ifdef CONFIG_EXPERIMENTAL -# warning The implementation of delroute is incomplete -#endif - /**************************************************************************** * Public Types ****************************************************************************/ @@ -117,7 +98,6 @@ struct route_match_ipv6_s * ****************************************************************************/ -#ifdef CONFIG_EXPERIMENTAL #ifdef CONFIG_ROUTE_IPv4_FILEROUTE static int net_match_ipv4(FAR struct net_route_ipv4_s *route, FAR void *arg) { @@ -187,7 +167,6 @@ static int net_match_ipv6(FAR struct net_route_ipv6_s *route, FAR void *arg) return 0; } #endif -#endif /* CONFIG_EXPERIMENTAL */ /**************************************************************************** * Public Functions @@ -209,10 +188,10 @@ static int net_match_ipv6(FAR struct net_route_ipv6_s *route, FAR void *arg) #ifdef CONFIG_ROUTE_IPv4_FILEROUTE int net_delroute_ipv4(in_addr_t target, in_addr_t netmask) { -#ifdef CONFIG_EXPERIMENTAL struct route_match_ipv4_s match; struct net_route_ipv4_s route; struct file fshandle; + off_t filesize; ssize_t nwritten; ssize_t nread; off_t pos; @@ -231,7 +210,7 @@ int net_delroute_ipv4(in_addr_t target, in_addr_t netmask) return ret; } - /* Get the size of the routing table entry (in entries) */ + /* Get the size of the routing table (in entries) */ nentries = net_routesize_ipv4(); if (nentries < 0) @@ -312,7 +291,7 @@ int net_delroute_ipv4(in_addr_t target, in_addr_t netmask) } else if (nread == 0) { - nerr("ERROR: Undexpected end of file\n"); + nerr("ERROR: Unexpected end of file\n"); ret = -EINVAL; goto errout_with_fshandle; } @@ -341,9 +320,9 @@ int net_delroute_ipv4(in_addr_t target, in_addr_t netmask) /* Now truncate the one duplicate entry at the end of the file. This may * result in a zero length file. */ -#warning Missing logic - ret = OK; + filesize = (nentries - 1) * sizeof(struct net_route_ipv4_s); + ret = file_truncate(&fshandle, filesize); errout_with_fshandle: (void)net_closeroute_ipv4(&fshandle); @@ -351,19 +330,16 @@ errout_with_fshandle: errout_with_lock: (void)net_unlockroute_ipv4(); return ret; -#else - return -ENOSYS; -#endif } #endif #ifdef CONFIG_ROUTE_IPv6_FILEROUTE int net_delroute_ipv6(net_ipv6addr_t target, net_ipv6addr_t netmask) { -#ifdef CONFIG_EXPERIMENTAL struct route_match_ipv6_s match; struct net_route_ipv6_s route; struct file fshandle; + off_t filesize; ssize_t nwritten; ssize_t nread; off_t pos; @@ -382,7 +358,7 @@ int net_delroute_ipv6(net_ipv6addr_t target, net_ipv6addr_t netmask) return ret; } - /* Get the size of the routing table entry (in entries) */ + /* Get the size of the routing table (in entries) */ nentries = net_routesize_ipv6(); if (nentries < 0) @@ -464,7 +440,7 @@ int net_delroute_ipv6(net_ipv6addr_t target, net_ipv6addr_t netmask) } else if (nread == 0) { - nerr("ERROR: Undexpected end of file\n"); + nerr("ERROR: Unexpected end of file\n"); ret = -EINVAL; goto errout_with_fshandle; } @@ -493,9 +469,9 @@ int net_delroute_ipv6(net_ipv6addr_t target, net_ipv6addr_t netmask) /* Now truncate the one duplicate entry at the end of the file. This may * result in a zero length file. */ -#warning Missing logic - ret = OK; + filesize = (nentries - 1) * sizeof(struct net_route_ipv6_s); + ret = file_truncate(&fshandle, filesize); errout_with_fshandle: (void)net_closeroute_ipv6(&fshandle); @@ -503,9 +479,6 @@ errout_with_fshandle: errout_with_lock: (void)net_unlockroute_ipv6(); return ret; -#else - return -ENOSYS; -#endif } #endif diff --git a/net/route/net_fileroute.c b/net/route/net_fileroute.c index 36a0e486b3b11821d9e3fe0dd21fd2b5ebc6ad79..32074efd85b93f92b4be8b56d0f8380c62d27a7a 100644 --- a/net/route/net_fileroute.c +++ b/net/route/net_fileroute.c @@ -47,6 +47,7 @@ #include #include +#include #include #include "route/fileroute.h" @@ -716,7 +717,7 @@ int net_lockroute_ipv6(void) ret = nxsem_wait(&g_ipv6_exclsem); if (ret < 0) { - nerr("ERROR: nxsem_wait() failed: %d\n", errcode); + nerr("ERROR: nxsem_wait() failed: %d\n", ret); } else { diff --git a/net/sixlowpan/Kconfig b/net/sixlowpan/Kconfig index 70620532a5b688460118b2a53a2b2c590f09feb1..c1889188a8786ab1cd8ac6eafb0285ac7e1f3b9a 100644 --- a/net/sixlowpan/Kconfig +++ b/net/sixlowpan/Kconfig @@ -91,7 +91,7 @@ config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_0 hex "Address context 0 Prefix 0" default 0xaa ---help--- - Prefix 0 for address context ze0ro (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 0) + Prefix 0 for address context zero (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 0) config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_1 hex "Address context 0 Prefix 1" @@ -99,6 +99,42 @@ config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_1 ---help--- Prefix 1 for address context 0 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 0) +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_2 + hex "Address context 0 Prefix 2" + default 0xaa + ---help--- + Prefix 2 for address context 0 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 0) + +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_3 + hex "Address context 0 Prefix 3" + default 0xaa + ---help--- + Prefix 3 for address context 0 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 0) + +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_4 + hex "Address context 0 Prefix 4" + default 0xaa + ---help--- + Prefix 4 for address context 0 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 0) + +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_5 + hex "Address context 0 Prefix 5" + default 0xaa + ---help--- + Prefix 5 for address context 0 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 0) + +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_6 + hex "Address context 0 Prefix 6" + default 0xaa + ---help--- + Prefix 6 for address context 0 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 0) + +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_7 + hex "Address context 0 Prefix 6" + default 0xaa + ---help--- + Prefix 7 for address context 0 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 0) + config NET_6LOWPAN_MAXADDRCONTEXT_PREINIT_1 bool "Pre-initialize address context 1" default n @@ -121,6 +157,42 @@ config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_1_1 ---help--- Prefix 1 for address context 1 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 1) +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_1_2 + hex "Address context 1 Prefix 2" + default 0xaa + ---help--- + Prefix 2 for address context 1 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 1) + +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_1_3 + hex "Address context 1 Prefix 3" + default 0xaa + ---help--- + Prefix 3 for address context 1 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 1) + +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_1_4 + hex "Address context 1 Prefix 4" + default 0xaa + ---help--- + Prefix 4 for address context 1 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 1) + +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_1_5 + hex "Address context 1 Prefix 5" + default 0xaa + ---help--- + Prefix 5 for address context 1 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 1) + +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_1_6 + hex "Address context 1 Prefix 6" + default 0xaa + ---help--- + Prefix 6 for address context 1 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 1) + +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_1_7 + hex "Address context 1 Prefix 7" + default 0xaa + ---help--- + Prefix 7 for address context 1 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 1) + endif # NET_6LOWPAN_MAXADDRCONTEXT_PREINIT_1 config NET_6LOWPAN_MAXADDRCONTEXT_PREINIT_2 @@ -146,7 +218,43 @@ config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_2_1 ---help--- Prefix 1 for address context 2 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 2) -endif # NET_6LOWPAN_MAXADDRCONTEXT_PREINIT_0 +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_2_2 + hex "Address context 2 Prefix 2" + default 0xaa + ---help--- + Prefix 2 for address context 2 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 2) + +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_2_3 + hex "Address context 2 Prefix 3" + default 0xaa + ---help--- + Prefix 3 for address context 2 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 2) + +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_2_4 + hex "Address context 2 Prefix 4" + default 0xaa + ---help--- + Prefix 4 for address context 2 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 2) + +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_2_5 + hex "Address context 2 Prefix 5" + default 0xaa + ---help--- + Prefix 5 for address context 2 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 2) + +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_2_6 + hex "Address context 2 Prefix 6" + default 0xaa + ---help--- + Prefix 6 for address context 2 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 2) + +config NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_2_7 + hex "Address context 2 Prefix 7" + default 0xaa + ---help--- + Prefix 7 for address context 2 (assumes CONFIG_NET_6LOWPAN_MAXADDRCONTEXT >= 2) + +endif # NET_6LOWPAN_MAXADDRCONTEXT_PREINIT_2 endif # NET_6LOWPAN_COMPRESSION_HC06 config NET_6LOWPAN_EXTENDEDADDR diff --git a/net/sixlowpan/sixlowpan_framer.c b/net/sixlowpan/sixlowpan_framer.c index 95d44d85597fc859be6a62ec0b052d0ff0328d50..666c6a3adf19209c679659033898bcfff0882b6a 100644 --- a/net/sixlowpan/sixlowpan_framer.c +++ b/net/sixlowpan/sixlowpan_framer.c @@ -182,7 +182,7 @@ int sixlowpan_meta_data(FAR struct radio_driver_s *radio, rcvrnull = sixlowpan_saddrnull(pktmeta->dest.nm_addr); } - if (rcvrnull) + if (!rcvrnull) { meta->flags.ackreq = TRUE; } diff --git a/net/sixlowpan/sixlowpan_hc06.c b/net/sixlowpan/sixlowpan_hc06.c index b084f7e96b31084638050a66f98061d3318b9842..c9e05410e1cd502d42d770b4f3b55de78ba9a135 100644 --- a/net/sixlowpan/sixlowpan_hc06.c +++ b/net/sixlowpan/sixlowpan_hc06.c @@ -301,8 +301,8 @@ static uint8_t compress_tagaddr(FAR const net_ipv6addr_t ipaddr, #ifdef CONFIG_DEBUG_NET_INFO ninfo("Compressing bitpos=%u addrlen=%u\n", bitpos, macaddr->nv_addrlen); ninfo(" ipaddr=%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", - ipaddr[0], ipaddr[1], ipaddr[2], ipaddr[3], - ipaddr[4], ipaddr[5], ipaddr[6], ipaddr[7]); + ntohs(ipaddr[0]), ntohs(ipaddr[1]), ntohs(ipaddr[2]), ntohs(ipaddr[3]), + ntohs(ipaddr[4]), ntohs(ipaddr[5]), ntohs(ipaddr[6]), ntohs(ipaddr[7])); switch (macaddr->nv_addrlen) { @@ -351,8 +351,9 @@ static uint8_t compress_laddr(FAR const net_ipv6addr_t srcipaddr, #ifdef CONFIG_DEBUG_NET_INFO ninfo("Compressing bitpos=%u\n", bitpos); ninfo(" srcipaddr=%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", - srcipaddr[0], srcipaddr[1], srcipaddr[2], srcipaddr[3], - srcipaddr[4], srcipaddr[5], srcipaddr[6], srcipaddr[7]); + ntohs(srcipaddr[0]), ntohs(srcipaddr[1]), ntohs(srcipaddr[2]), + ntohs(srcipaddr[3]), ntohs(srcipaddr[4]), ntohs(srcipaddr[5]), + ntohs(srcipaddr[6]), ntohs(srcipaddr[7])); switch (macaddr->nv_addrlen) { @@ -490,7 +491,7 @@ static void uncompress_addr(FAR const struct netdev_varaddr_s *addr, { /* Big-endian, network order */ - ipaddr[i] = (uint16_t)srcptr[0] << 8 | (uint16_t)srcptr[1]; + ipaddr[i] = (uint16_t)srcptr[1] << 8 | (uint16_t)srcptr[0]; srcptr += 2; } @@ -524,8 +525,8 @@ static void uncompress_addr(FAR const struct netdev_varaddr_s *addr, ninfo("Uncompressing %d + %d ipaddr=%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", prefcount, postcount, - ipaddr[0], ipaddr[1], ipaddr[2], ipaddr[3], - ipaddr[4], ipaddr[5], ipaddr[6], ipaddr[7]); + ntohs(ipaddr[0]), ntohs(ipaddr[1]), ntohs(ipaddr[2]), ntohs(ipaddr[3]), + ntohs(ipaddr[4]), ntohs(ipaddr[5]), ntohs(ipaddr[6]), ntohs(ipaddr[7])); } /**************************************************************************** @@ -567,6 +568,12 @@ void sixlowpan_hc06_initialize(void) g_hc06_addrcontexts[0].prefix[0] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_0; g_hc06_addrcontexts[0].prefix[1] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_1; + g_hc06_addrcontexts[0].prefix[2] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_2; + g_hc06_addrcontexts[0].prefix[3] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_3; + g_hc06_addrcontexts[0].prefix[4] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_4; + g_hc06_addrcontexts[0].prefix[5] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_5; + g_hc06_addrcontexts[0].prefix[6] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_6; + g_hc06_addrcontexts[0].prefix[7] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_7; #if CONFIG_NET_6LOWPAN_MAXADDRCONTEXT > 1 for (i = 1; i < CONFIG_NET_6LOWPAN_MAXADDRCONTEXT; i++) @@ -579,6 +586,12 @@ void sixlowpan_hc06_initialize(void) g_hc06_addrcontexts[1].prefix[0] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_1_0; g_hc06_addrcontexts[1].prefix[1] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_1_1; + g_hc06_addrcontexts[1].prefix[2] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_1_2; + g_hc06_addrcontexts[1].prefix[3] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_1_3; + g_hc06_addrcontexts[1].prefix[4] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_1_4; + g_hc06_addrcontexts[1].prefix[5] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_1_5; + g_hc06_addrcontexts[1].prefix[6] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_1_6; + g_hc06_addrcontexts[1].prefix[7] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_1_7; } else #ifdef CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREINIT_2 @@ -589,6 +602,12 @@ void sixlowpan_hc06_initialize(void) g_hc06_addrcontexts[2].prefix[0] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_2_0; g_hc06_addrcontexts[2].prefix[1] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_2_1; + g_hc06_addrcontexts[2].prefix[2] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_2_2; + g_hc06_addrcontexts[2].prefix[3] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_2_3; + g_hc06_addrcontexts[2].prefix[4] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_2_4; + g_hc06_addrcontexts[2].prefix[5] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_2_5; + g_hc06_addrcontexts[2].prefix[6] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_2_6; + g_hc06_addrcontexts[2].prefix[7] = CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_2_7; } else #endif /* SIXLOWPAN_CONF_ADDR_CONTEXT_2 */ @@ -846,9 +865,10 @@ int sixlowpan_compresshdr_hc06(FAR struct radio_driver_s *radio, /* Send the full source address ipaddr: SAC = 0, SAM = 00 */ ninfo("Uncompressable srcipaddr=%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", - ipv6->srcipaddr[0], ipv6->srcipaddr[1], ipv6->srcipaddr[2], - ipv6->srcipaddr[3], ipv6->srcipaddr[4], ipv6->srcipaddr[5], - ipv6->srcipaddr[6], ipv6->srcipaddr[7]); + ntohs(ipv6->srcipaddr[0]), ntohs(ipv6->srcipaddr[1]), + ntohs(ipv6->srcipaddr[2]), ntohs(ipv6->srcipaddr[3]), + ntohs(ipv6->srcipaddr[4]), ntohs(ipv6->srcipaddr[5]), + ntohs(ipv6->srcipaddr[6]), ntohs(ipv6->srcipaddr[7])); iphc1 |= SIXLOWPAN_IPHC_SAM_128; /* 128-bits */ memcpy(g_hc06ptr, ipv6->srcipaddr, 16); diff --git a/net/sixlowpan/sixlowpan_hc1.c b/net/sixlowpan/sixlowpan_hc1.c index 77a13a87124c64ef643ff05e50106d554e435b76..977c268caba0442293e80165aaafeb22bebf5232 100644 --- a/net/sixlowpan/sixlowpan_hc1.c +++ b/net/sixlowpan/sixlowpan_hc1.c @@ -414,9 +414,10 @@ int sixlowpan_uncompresshdr_hc1(FAR struct radio_driver_s *radio, } ninfo("srcipaddr=%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", - ipv6->srcipaddr[0], ipv6->srcipaddr[1], ipv6->srcipaddr[2], - ipv6->srcipaddr[3], ipv6->srcipaddr[4], ipv6->srcipaddr[5], - ipv6->srcipaddr[6], ipv6->srcipaddr[7]); + ntohs(ipv6->srcipaddr[0]), ntohs(ipv6->srcipaddr[1]), + ntohs(ipv6->srcipaddr[2]), ntohs(ipv6->srcipaddr[3]), + ntohs(ipv6->srcipaddr[4]), ntohs(ipv6->srcipaddr[5]), + ntohs(ipv6->srcipaddr[6]), ntohs(ipv6->srcipaddr[7])); if ((hc1[SIXLOWPAN_HC1_ENCODING] & SIXLOWPAN_HC1_DESTADDR_MASK) == SIXLOWPAN_HC1_DESTADDR_PCIC) @@ -438,9 +439,10 @@ int sixlowpan_uncompresshdr_hc1(FAR struct radio_driver_s *radio, } ninfo("destipaddr=%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", - ipv6->destipaddr[0], ipv6->destipaddr[1], ipv6->destipaddr[2], - ipv6->destipaddr[3], ipv6->destipaddr[4], ipv6->destipaddr[5], - ipv6->destipaddr[6], ipv6->destipaddr[7]); + ntohs(ipv6->destipaddr[0]), ntohs(ipv6->destipaddr[1]), + ntohs(ipv6->destipaddr[2]), ntohs(ipv6->destipaddr[3]), + ntohs(ipv6->destipaddr[4]), ntohs(ipv6->destipaddr[5]), + ntohs(ipv6->destipaddr[6]), ntohs(ipv6->destipaddr[7])); /* IP length field. */ diff --git a/net/sixlowpan/sixlowpan_icmpv6send.c b/net/sixlowpan/sixlowpan_icmpv6send.c index 2bb7a46165be5a5b5c8104f612a7875f80ddfc90..e62c617ed1ea27ba3c1fe133217ddc2b95ab3943 100644 --- a/net/sixlowpan/sixlowpan_icmpv6send.c +++ b/net/sixlowpan/sixlowpan_icmpv6send.c @@ -88,7 +88,7 @@ void sixlowpan_icmpv6_send(FAR struct net_driver_s *dev, /* Double check */ - DEBUGASSERT(dev != NULL && dev->d_len > 0); + DEBUGASSERT(dev != NULL && dev->d_len > 0 && fwddev != NULL); ninfo("d_len %u\n", dev->d_len); @@ -114,15 +114,13 @@ void sixlowpan_icmpv6_send(FAR struct net_driver_s *dev, uint16_t buflen; int ret; - /* Get the IEEE 802.15.4 MAC address of the destination. This - * assumes an encoding of the MAC address in the IPv6 address. - */ + /* Get the IEEE 802.15.4 MAC address of the next hop. */ - ret = sixlowpan_destaddrfromip((FAR struct radio_driver_s *)dev, - ipv6icmpv6->ipv6.destipaddr, &destmac); + ret = sixlowpan_nexthopaddr((FAR struct radio_driver_s *)fwddev, + ipv6icmpv6->ipv6.destipaddr, &destmac); if (ret < 0) { - nerr("ERROR: Failed to dest MAC address: %d\n", ret); + nerr("ERROR: Failed to get dest MAC address: %d\n", ret); goto drop; } diff --git a/net/sixlowpan/sixlowpan_input.c b/net/sixlowpan/sixlowpan_input.c index 7d3d9aa68ca88d9c564bc17083b400f5909a2111..e64becd9c1b355e3bc7408a5993ece845799f50c 100644 --- a/net/sixlowpan/sixlowpan_input.c +++ b/net/sixlowpan/sixlowpan_input.c @@ -438,6 +438,7 @@ static int sixlowpan_frame_process(FAR struct radio_driver_s *radio, DEBUGASSERT(radio->r_dev.d_buf != NULL); reass = (FAR struct sixlowpan_reassbuf_s *)radio->r_dev.d_buf; + reass->rb_pool = REASS_POOL_RADIO; bptr = reass->rb_buf; break; } @@ -735,9 +736,16 @@ int sixlowpan_input(FAR struct radio_driver_s *radio, ret = sixlowpan_frame_process(radio, metadata, iob); - /* Free the IOB the held the consumed frame */ + /* If the frame was a valid 6LoWPAN frame, free the IOB the held the + * consumed frame. Otherwise, the frame must stay allocated since the + * MAC layer will try and pass it to another receiver to see if that + * receiver wants it. + */ - iob_free(iob); + if (ret >= 0) + { + iob_free(iob); + } /* Was the frame successfully processed? Is the packet in d_buf fully * reassembled? @@ -774,11 +782,11 @@ int sixlowpan_input(FAR struct radio_driver_s *radio, * address. */ - ret = sixlowpan_destaddrfromip(radio, ipv6hdr->destipaddr, - &destmac); + ret = sixlowpan_nexthopaddr(radio, ipv6hdr->destipaddr, + &destmac); if (ret < 0) { - nerr("ERROR: Failed to dest MAC address: %d\n", ret); + nerr("ERROR: Failed to get dest MAC address: %d\n", ret); goto drop; } @@ -826,9 +834,9 @@ int sixlowpan_input(FAR struct radio_driver_s *radio, } } - if (hdrlen < radio->r_dev.d_len) + if (hdrlen > radio->r_dev.d_len) { - nwarn("WARNING: Packet to small: Have %u need >%u\n", + nwarn("WARNING: Packet too small: Have %u need >%u\n", radio->r_dev.d_len, hdrlen); ret = -ENOBUFS; goto drop; diff --git a/net/sixlowpan/sixlowpan_internal.h b/net/sixlowpan/sixlowpan_internal.h index b8332b5c1a5ce4537f429b3e0b3c6cf847f67908..7e527dae0df054269703e336a12a5941998a2609 100644 --- a/net/sixlowpan/sixlowpan_internal.h +++ b/net/sixlowpan/sixlowpan_internal.h @@ -122,6 +122,7 @@ #define REASS_POOL_PREALLOCATED 0 #define REASS_POOL_DYNAMIC 1 +#define REASS_POOL_RADIO 2 /* Debug ********************************************************************/ @@ -563,6 +564,22 @@ int sixlowpan_uncompresshdr_hc1(FAR struct radio_driver_s *radio, FAR uint8_t *bptr); #endif +/**************************************************************************** + * Name: sixlowpan_nexthopaddr + * + * Description: + * sixlowpan_nexthopaddr(): If the destination is on-link, extract the + * IEEE 802.15.14 destination address from the destination IP address. If the + * destination is not reachable directly, use the routing table (if available) + * or fall back to the default router IP address and use the router IP address + * to derive the IEEE 802.15.4 MAC address. + * + ****************************************************************************/ + +int sixlowpan_nexthopaddr(FAR struct radio_driver_s *radio, + FAR const net_ipv6addr_t ipaddr, + FAR struct netdev_varaddr_s *destaddr); + /**************************************************************************** * Name: sixlowpan_islinklocal, sixlowpan_destaddrfromip, and * sixlowpan_ismacbased diff --git a/net/sixlowpan/sixlowpan_reassbuf.c b/net/sixlowpan/sixlowpan_reassbuf.c index b308a04c8fd12a427d369f3deb71c7dce17ad572..c3ae7eeb8044152b84f3abf30a6bf1037a1f0a71 100644 --- a/net/sixlowpan/sixlowpan_reassbuf.c +++ b/net/sixlowpan/sixlowpan_reassbuf.c @@ -439,7 +439,7 @@ void sixlowpan_reass_free(FAR struct sixlowpan_reassbuf_s *reass) reass->rb_flink = g_free_reass; g_free_reass = reass; } - else + else if (reass->rb_pool == REASS_POOL_DYNAMIC) { #ifdef CONFIG_NET_6LOWPAN_REASS_STATIC DEBUGPANIC(); @@ -451,4 +451,8 @@ void sixlowpan_reass_free(FAR struct sixlowpan_reassbuf_s *reass) sched_kfree(reass); #endif } + + /* If the reassembly buffer structure was provided by the driver, nothing + * needs to be freed. + */ } diff --git a/net/sixlowpan/sixlowpan_tcpsend.c b/net/sixlowpan/sixlowpan_tcpsend.c index 4fa8788e2bc9f5c49d5b066777450c1cade870a4..df7eab7971c16b08170db0ed016dc1b466eccf04 100644 --- a/net/sixlowpan/sixlowpan_tcpsend.c +++ b/net/sixlowpan/sixlowpan_tcpsend.c @@ -838,12 +838,10 @@ ssize_t psock_6lowpan_tcp_send(FAR struct socket *psock, FAR const void *buf, } #endif - /* Get the IEEE 802.15.4 MAC address of the destination. This assumes - * an encoding of the MAC address in the IPv6 address. - */ + /* Get the IEEE 802.15.4 MAC address of the next hop. */ - ret = sixlowpan_destaddrfromip((FAR struct radio_driver_s *)dev, - conn->u.ipv6.raddr, &destmac); + ret = sixlowpan_nexthopaddr((FAR struct radio_driver_s *)dev, + conn->u.ipv6.raddr, &destmac); if (ret < 0) { nerr("ERROR: Failed to get dest MAC address: %d\n", ret); @@ -929,7 +927,7 @@ void sixlowpan_tcp_send(FAR struct net_driver_s *dev, sixlowpan_dumpbuffer("Outgoing TCP packet", (FAR const uint8_t *)ipv6, dev->d_len); - if (dev != NULL && dev->d_len > 0) + if (dev != NULL && dev->d_len > 0 && fwddev != NULL) { FAR struct ipv6tcp_hdr_s *ipv6hdr; @@ -957,12 +955,10 @@ void sixlowpan_tcp_send(FAR struct net_driver_s *dev, uint16_t buflen; int ret; - /* Get the IEEE 802.15.4 MAC address of the destination. This - * assumes an encoding of the MAC address in the IPv6 address. - */ + /* Get the IEEE 802.15.4 MAC address of the next hop. */ - ret = sixlowpan_destaddrfromip((FAR struct radio_driver_s *)dev, - ipv6hdr->ipv6.destipaddr, &destmac); + ret = sixlowpan_nexthopaddr((FAR struct radio_driver_s *)fwddev, + ipv6hdr->ipv6.destipaddr, &destmac); if (ret < 0) { nerr("ERROR: Failed to get dest MAC address: %d\n", ret); diff --git a/net/sixlowpan/sixlowpan_udpsend.c b/net/sixlowpan/sixlowpan_udpsend.c index be7dfce581b49bccf12f4c8e80851fc084b85209..e2f115eb09064843baf85fdbf38d02d5b41f65b4 100644 --- a/net/sixlowpan/sixlowpan_udpsend.c +++ b/net/sixlowpan/sixlowpan_udpsend.c @@ -292,12 +292,10 @@ ssize_t psock_6lowpan_udp_sendto(FAR struct socket *psock, g_netstats.udp.sent++; #endif - /* Get the IEEE 802.15.4 MAC address of the destination This assumes an - * encoding of the MAC address in the IPv6 address. - */ + /* Get the IEEE 802.15.4 MAC address of the next hop. */ - ret = sixlowpan_destaddrfromip((FAR struct radio_driver_s *)dev, - to6->sin6_addr.in6_u.u6_addr16, &destmac); + ret = sixlowpan_nexthopaddr((FAR struct radio_driver_s *)dev, + to6->sin6_addr.in6_u.u6_addr16, &destmac); if (ret < 0) { nerr("ERROR: Failed to get dest MAC address: %d\n", ret); @@ -441,11 +439,11 @@ void sixlowpan_udp_send(FAR struct net_driver_s *dev, /* Double check */ - DEBUGASSERT(dev != NULL && dev->d_len > 0); + DEBUGASSERT(dev != NULL && dev->d_len > 0 && fwddev != NULL); ninfo("d_len %u\n", dev->d_len); - if (dev != NULL && dev->d_len > 0) + if (dev != NULL && dev->d_len > 0 && fwddev != NULL) { sixlowpan_dumpbuffer("Outgoing UDP packet", @@ -468,12 +466,10 @@ void sixlowpan_udp_send(FAR struct net_driver_s *dev, uint16_t buflen; int ret; - /* Get the IEEE 802.15.4 MAC address of the destination. This - * assumes an encoding of the MAC address in the IPv6 address. - */ + /* Get the IEEE 802.15.4 MAC address of the next hop. */ - ret = sixlowpan_destaddrfromip((FAR struct radio_driver_s *)dev, - ipv6udp->ipv6.destipaddr, &destmac); + ret = sixlowpan_nexthopaddr((FAR struct radio_driver_s *)fwddev, + ipv6udp->ipv6.destipaddr, &destmac); if (ret < 0) { nerr("ERROR: Failed to get dest MAC address: %d\n", ret); diff --git a/net/sixlowpan/sixlowpan_utils.c b/net/sixlowpan/sixlowpan_utils.c index f4c27dc530d044c2e1f0b764af1c8454a7348ed1..696503b5a9398d168ff30c68fefe6de9011df66b 100644 --- a/net/sixlowpan/sixlowpan_utils.c +++ b/net/sixlowpan/sixlowpan_utils.c @@ -59,6 +59,7 @@ #include #include +#include "route/route.h" #include "inet/inet.h" #include "sixlowpan/sixlowpan_internal.h" @@ -166,6 +167,63 @@ static void sixlowpan_eaddrfromip(const net_ipv6addr_t ipaddr, FAR uint8_t *eadd * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: sixlowpan_nexthopaddr + * + * Description: + * sixlowpan_nexthopaddr(): If the destination is on-link, extract the + * IEEE 802.15.14 destination address from the destination IP address. If the + * destination is not reachable directly, use the routing table (if available) + * or fall back to the default router IP address and use the router IP address + * to derive the IEEE 802.15.4 MAC address. + * + ****************************************************************************/ + +int sixlowpan_nexthopaddr(FAR struct radio_driver_s *radio, + FAR const net_ipv6addr_t ipaddr, + FAR struct netdev_varaddr_s *destaddr) +{ + FAR net_ipv6addr_t router; + int ret; + + /* Try to get the IEEE 802.15.4 MAC address of the destination. This + * assumes an encoding of the MAC address in the IPv6 address. + */ + + ret = sixlowpan_destaddrfromip(radio, ipaddr, destaddr); + if (ret < 0) + { + /* Destination address is not on the local network */ + +#ifdef CONFIG_NET_ROUTE + /* We have a routing table.. find the correct router to use in + * this case (or, as a fall-back, use the device's default router + * address). We will use the router IPv6 address instead of the + * destination address when determining the MAC address. + */ + + netdev_ipv6_router(&radio->r_dev, ipaddr, router); +#else + /* Use the device's default router IPv6 address instead of the + * destination address when determining the MAC address. + */ + + net_ipv6addr_copy(router, radio->r_dev.d_ipv6draddr); +#endif + /* Get the IEEE 802.15.4 MAC address of the router. This + * assumes an encoding of the MAC address in the IPv6 address. + */ + + ret = sixlowpan_destaddrfromip(radio, router, destaddr); + if (ret < 0) + { + return ret; + } + } + + return OK; +} + /**************************************************************************** * Name: sixlowpan_destaddrfromip * @@ -250,14 +308,15 @@ int sixlowpan_destaddrfromip(FAR struct radio_driver_s *radio, return OK; } - /* Otherwise, the destination MAC address is encoded in the IP address */ + /* Otherwise, the destination MAC address is encoded in the IP address */ - /* Check for compressible link-local address. - * REVISIT: This should not restrict us to link-local addresses. - */ + /* If the address is link-local, or matches the prefix of the local address, + * the interface identifier can be extracted from the lower bits of the address. + */ - if (ipaddr[0] != HTONS(0xfe80) || ipaddr[1] != 0 || - ipaddr[2] != 0 || ipaddr[3] != 0) + if (!sixlowpan_islinklocal(ipaddr) && + !net_ipv6addr_maskcmp(radio->r_dev.d_ipv6addr, ipaddr, + radio->r_dev.d_ipv6netmask)) { return -EADDRNOTAVAIL; } diff --git a/net/socket/socket.c b/net/socket/socket.c index 6f9d64272e1bc8597eb4a32755f40e1f6e851143..539ef0b2160f4166dd747772da1f866505b81589 100644 --- a/net/socket/socket.c +++ b/net/socket/socket.c @@ -60,6 +60,11 @@ * socket() creates an endpoint for communication and returns a socket * structure. * + * NOTE: This function does not set the reference count on the socket + * structure. This down by the socket() front end when socket structure + * was allocated. Internal OS users of psock_socket() must set the s_crefs + * field to one if psock_socket() returns success. + * * Input Parameters: * domain (see sys/socket.h) * type (see sys/socket.h) diff --git a/net/socket/socket.h b/net/socket/socket.h index 0557709c08be6f12b349c42677364529b0a092f0..3c8eb02bc02668e12d41fca37628ded28709dec7 100644 --- a/net/socket/socket.h +++ b/net/socket/socket.h @@ -95,24 +95,24 @@ /* These define bit positions for each socket option (see sys/socket.h) */ -#define _SO_DEBUG _SO_BIT(SO_DEBUG) #define _SO_ACCEPTCONN _SO_BIT(SO_ACCEPTCONN) #define _SO_BROADCAST _SO_BIT(SO_BROADCAST) -#define _SO_REUSEADDR _SO_BIT(SO_REUSEADDR) +#define _SO_DEBUG _SO_BIT(SO_DEBUG) +#define _SO_DONTROUTE _SO_BIT(SO_DONTROUTE) +#define _SO_ERROR _SO_BIT(SO_ERROR) #define _SO_KEEPALIVE _SO_BIT(SO_KEEPALIVE) #define _SO_LINGER _SO_BIT(SO_LINGER) #define _SO_OOBINLINE _SO_BIT(SO_OOBINLINE) -#define _SO_SNDBUF _SO_BIT(SO_SNDBUF) #define _SO_RCVBUF _SO_BIT(SO_RCVBUF) -#define _SO_ERROR _SO_BIT(SO_ERROR) -#define _SO_TYPE _SO_BIT(SO_TYPE) -#define _SO_DONTROUTE _SO_BIT(SO_DONTROUTE) #define _SO_RCVLOWAT _SO_BIT(SO_RCVLOWAT) #define _SO_RCVTIMEO _SO_BIT(SO_RCVTIMEO) +#define _SO_REUSEADDR _SO_BIT(SO_REUSEADDR) +#define _SO_SNDBUF _SO_BIT(SO_SNDBUF) #define _SO_SNDLOWAT _SO_BIT(SO_SNDLOWAT) #define _SO_SNDTIMEO _SO_BIT(SO_SNDTIMEO) +#define _SO_TYPE _SO_BIT(SO_TYPE) -/* This is the larget option value */ +/* This is the largest option value. REVISIT: belongs in sys/socket.h */ #define _SO_MAXOPT (15) diff --git a/net/tcp/Kconfig b/net/tcp/Kconfig index fac41794dcf1bbdf8c299b8bb08e308bea0bba0f..77cebe81fbedc6e373a1578b58c12bf5460f83ff 100644 --- a/net/tcp/Kconfig +++ b/net/tcp/Kconfig @@ -192,4 +192,13 @@ config NET_SENDFILE files out a TCP connection. endif # NET_TCP && !NET_TCP_NO_STACK + +config NET_TCP_RWND_CONTROL + bool "Receive window control based on IOBuffer" + default n + depends on MM_IOB && EXPERIMENTAL + ---help--- + Support receive window control based on I/O buffer. This feature + is still experimental. + endmenu # TCP/IP Networking diff --git a/net/tcp/tcp_send.c b/net/tcp/tcp_send.c index 6797c9d279a8356649bba0b4ca4599a759c420e6..b4e833aa9b023dc4e432079d3d6375d44fd902bb 100644 --- a/net/tcp/tcp_send.c +++ b/net/tcp/tcp_send.c @@ -54,6 +54,10 @@ #include #include +#ifdef CONFIG_NET_TCP_RWND_CONTROL +# include +#endif + #include "devif/devif.h" #include "inet/inet.h" #include "tcp/tcp.h" @@ -309,6 +313,12 @@ static void tcp_sendcommon(FAR struct net_driver_s *dev, FAR struct tcp_conn_s *conn, FAR struct tcp_hdr_s *tcp) { +#ifdef CONFIG_NET_TCP_RWND_CONTROL + extern sem_t g_qentry_sem; + int qentry_sem_count; + uint32_t rwnd; +#endif + /* Copy the IP address into the IPv6 header */ #ifdef CONFIG_NET_IPv6 @@ -341,6 +351,19 @@ static void tcp_sendcommon(FAR struct net_driver_s *dev, tcp->srcport = conn->lport; tcp->destport = conn->rport; +#ifdef CONFIG_NET_TCP_RWND_CONTROL + /* Update the TCP received window based on I/O buffer */ + /* NOTE: This algorithm is still experimental */ + + if (OK == nxsem_getvalue(&g_qentry_sem, &qentry_sem_count)) + { + rwnd = (qentry_sem_count * CONFIG_NET_ETH_TCP_RECVWNDO) + / CONFIG_IOB_NCHAINS; + + NET_DEV_RCVWNDO(dev) = (uint16_t)rwnd; + } +#endif + /* Set the TCP window */ if (conn->tcpstateflags & TCP_STOPPED) diff --git a/sched/Kconfig b/sched/Kconfig index b2ff0bba452dc4e9a718488fa89173b34520f09c..6a50b93fe896d1f5165c8e18d654b6513936c431 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -186,7 +186,7 @@ config JULIAN_TIME config START_YEAR int "Start year" - default 2017 + default 2018 range 1970 2106 ---help--- NuttX uses an unsigned 32-bit integer for time_t which provides a @@ -249,6 +249,13 @@ config SPINLOCK Enables suppport for spinlocks. Spinlocks are current used only for SMP suppport. +config SPINLOCK_IRQ + bool "Support Spinlocks with IRQ control" + default n + ---help--- + Enables suppport for spinlocks with IRQ control. This feature can be + used to protect data in SMP mode. + config SMP bool "Symmetric Multi-Processing (SMP)" default n diff --git a/sched/clock/clock_initialize.c b/sched/clock/clock_initialize.c index 4d41071f475f7b7036268d42a14fe4a580f9bf8b..6edf41d90de6f4e30414979350f02c3920623424 100644 --- a/sched/clock/clock_initialize.c +++ b/sched/clock/clock_initialize.c @@ -68,19 +68,6 @@ #define SEC_PER_HOUR ((time_t)60 * SEC_PER_MIN) #define SEC_PER_DAY ((time_t)24 * SEC_PER_HOUR) -#if defined(CONFIG_DEBUG_FEATURES) && defined(CONFIG_SYSTEM_TIME64) && \ - defined(CONFIG_CLOCK_MONOTONIC) -/* Initial system timer ticks value close to maximum 32-bit value, to test - * 64-bit system-timer after going over 32-bit value. This is to make errors - * of casting 64-bit system-timer to 32-bit variables more visible. - */ - -# define INITIAL_SYSTEM_TIMER_TICKS \ - ((uint64_t)(UINT32_MAX - (TICK_PER_SEC * 5))) -#else -# define INITIAL_SYSTEM_TIMER_TICKS 0 -#endif - /**************************************************************************** * Public Data ****************************************************************************/ diff --git a/sched/irq/Make.defs b/sched/irq/Make.defs index 9b5b264d666aae170cab349334859f1695f4b34c..72636e3ea20aaeb547188fb54234d4742a65383e 100644 --- a/sched/irq/Make.defs +++ b/sched/irq/Make.defs @@ -37,6 +37,9 @@ CSRCS += irq_initialize.c irq_attach.c irq_dispatch.c irq_unexpectedisr.c ifeq ($(CONFIG_SMP),y) CSRCS += irq_csection.c +ifeq ($(CONFIG_SPINLOCK_IRQ),y) +CSRCS += irq_spinlock.c +endif else ifeq ($(CONFIG_SCHED_INSTRUMENTATION_CSECTION),y) CSRCS += irq_csection.c endif diff --git a/sched/irq/irq_attach.c b/sched/irq/irq_attach.c index a5aec08ca6cbf0ef59b0720713866aa8973bcd73..a55ba758e6057789b322476ddba4987caa61db2c 100644 --- a/sched/irq/irq_attach.c +++ b/sched/irq/irq_attach.c @@ -39,6 +39,8 @@ #include +#include + #include #include "irq/irq.h" @@ -59,7 +61,7 @@ int irq_attach(int irq, xcpt_t isr, FAR void *arg) { #if NR_IRQS > 0 - int ret = ERROR; + int ret = -EINVAL; if ((unsigned)irq < NR_IRQS) { diff --git a/sched/irq/irq_spinlock.c b/sched/irq/irq_spinlock.c new file mode 100644 index 0000000000000000000000000000000000000000..a6f1ee97d18df4f1bc4018ce6400daa9f24dc937 --- /dev/null +++ b/sched/irq/irq_spinlock.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * sched/irq/irq_spinlock.c + * + * Copyright (C) 2017 Sony Corporation. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include "sched/sched.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Used for access control */ + +static volatile spinlock_t g_irq_spin SP_SECTION = SP_UNLOCKED; + +/* Handles nested calls to spin_lock_irqsave and spin_unlock_irqrestore */ + +static volatile uint8_t g_irq_spin_count[CONFIG_SMP_NCPUS]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: spin_lock_irqsave + * + * Description: + * If SMP and SPINLOCK_IRQ are enabled: + * Disable local interrupts and take the global spinlock (g_irq_spin) + * if the call counter (g_irq_spin_count[cpu]) equals to 0. Then the + * counter on the CPU is increment to allow nested call. + * + * NOTE: This API is very simple to protect data (e.g. H/W register + * or internal data structure) in SMP mode. But do not use this API + * with kernel APIs which suspend a caller thread. (e.g. nxsem_wait) + * + * If SMP and SPINLOCK_IRQ are not enabled: + * This function is equivalent to enter_critical_section(). + * + * Input Parameters: + * None + * + * Returned Value: + * An opaque, architecture-specific value that represents the state of + * the interrupts prior to the call to spin_lock_irqsave(); + * + ****************************************************************************/ + +irqstate_t spin_lock_irqsave(void) +{ + irqstate_t ret; + ret = up_irq_save(); + + int me = this_cpu(); + if (0 == g_irq_spin_count[me]) + { + spin_lock(&g_irq_spin); + } + + g_irq_spin_count[me]++; + ASSERT(0 != g_irq_spin_count[me]); + return ret; +} + +/**************************************************************************** + * Name: spin_unlock_irqrestore + * + * Description: + * If SMP and SPINLOCK_IRQ are enabled: + * Decrement the call counter (g_irq_spin_count[cpu]) and if it + * decrements to zero then release the spinlock (g_irq_spin) and + * restore the interrupt state as it was prior to the previous call to + * spin_lock_irqsave(). + * + * If SMP and SPINLOCK_IRQ are not enabled: + * This function is equivalent to leave_critical_section(). + * + * Input Parameters: + * flags - The architecture-specific value that represents the state of + * the interrupts prior to the call to spin_lock_irqsave(); + * + * Returned Value: + * None + * + ****************************************************************************/ + +void spin_unlock_irqrestore(irqstate_t flags) +{ + int me = this_cpu(); + + ASSERT(0 < g_irq_spin_count[me]); + g_irq_spin_count[me]--; + + if (0 == g_irq_spin_count[me]) + { + spin_unlock(&g_irq_spin); + } + + up_irq_restore(flags); +} diff --git a/sched/sched/sched_cpuselect.c b/sched/sched/sched_cpuselect.c index efd5c8417bafc75b327c6a659ca7a9e93fc3555c..c995cb8764433cc4a290229bb6a077eb78898a84 100644 --- a/sched/sched/sched_cpuselect.c +++ b/sched/sched/sched_cpuselect.c @@ -113,6 +113,7 @@ int sched_cpu_select(cpu_set_t affinity) else if (rtcb->sched_priority < minprio) { DEBUGASSERT(rtcb->sched_priority > 0); + minprio = rtcb->sched_priority; cpu = i; } } diff --git a/sched/sched/sched_mergepending.c b/sched/sched/sched_mergepending.c index 15e87ce99c67af4ab0951506289a88ca4b7bcb04..39968e6e116c9bba4a4e8eee912f577ac388862e 100644 --- a/sched/sched/sched_mergepending.c +++ b/sched/sched/sched_mergepending.c @@ -235,7 +235,6 @@ bool sched_mergepending(void) /* Remove the task from the pending task list */ tcb = (FAR struct tcb_s *)dq_remfirst((FAR dq_queue_t *)&g_pendingtasks); - DEBUGASSERT(tcb == ptcb); /* Add the pending task to the correct ready-to-run list. */ diff --git a/sched/semaphore/spinlock.c b/sched/semaphore/spinlock.c index 349cdec57fcc49e08f87d5ec18788751a9e4d3d9..674ebb6b522ace304b42c3f38efe011760343f19 100644 --- a/sched/semaphore/spinlock.c +++ b/sched/semaphore/spinlock.c @@ -165,8 +165,9 @@ void spin_unlock(FAR volatile spinlock_t *lock) sched_note_spinunlock(this_task(), lock); #endif - *lock = SP_UNLOCKED; SP_DMB(); + *lock = SP_UNLOCKED; + SP_DSB(); } #endif @@ -405,8 +406,15 @@ void spin_setbit(FAR volatile cpu_set_t *set, unsigned int cpu, #ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS cpu_set_t prev; #endif + irqstate_t flags; - /* First, get the 'setlock' spinlock */ + /* Disable local interrupts to prevent being re-entered from an interrupt + * on the same CPU. This does not effect the behavior on other CPUs. + */ + + flags = up_irq_save(); + + /* Then, get the 'setlock' spinlock */ spin_lock(setlock); @@ -427,9 +435,10 @@ void spin_setbit(FAR volatile cpu_set_t *set, unsigned int cpu, } #endif - /* Release the 'setlock' */ + /* Release the 'setlock' and restore local interrupts */ spin_unlock(setlock); + up_irq_restore(flags); } /**************************************************************************** @@ -456,6 +465,13 @@ void spin_clrbit(FAR volatile cpu_set_t *set, unsigned int cpu, #ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS cpu_set_t prev; #endif + irqstate_t flags; + + /* Disable local interrupts to prevent being re-entered from an interrupt + * on the same CPU. This does not effect the behavior on other CPUs. + */ + + flags = up_irq_save(); /* First, get the 'setlock' spinlock */ @@ -480,9 +496,10 @@ void spin_clrbit(FAR volatile cpu_set_t *set, unsigned int cpu, } #endif - /* Release the 'setlock' */ + /* Release the 'setlock' and restore local interrupts */ spin_unlock(setlock); + up_irq_restore(flags); } #endif /* CONFIG_SPINLOCK */ diff --git a/sched/signal/sig_nanosleep.c b/sched/signal/sig_nanosleep.c index 6fdb51ae453bf9251e24e3f636516ea2955f4bb4..d248027bc2e2ec6dd973f565fd2267075e826690 100644 --- a/sched/signal/sig_nanosleep.c +++ b/sched/signal/sig_nanosleep.c @@ -199,35 +199,60 @@ int nxsig_nanosleep(FAR const struct timespec *rqtp, } /**************************************************************************** - * Name: nanosleep + * Name: clock_nanosleep * * Description: - * The nanosleep() function causes the current thread to be suspended from - * execution until either the time interval specified by the rqtp argument - * has elapsed or a signal is delivered to the calling thread and its - * action is to invoke a signal-catching function or to terminate the - * process. The suspension time may be longer than requested because the - * argument value is rounded up to an integer multiple of the sleep - * resolution or because of the scheduling of other activity by the + * If the flag TIMER_ABSTIME is not set in the flags argument, the + * clock_nanosleep() function will cause the current thread to be suspended + * from execution until either the time interval specified by the rqtp + * argument has elapsed, or a signal is delivered to the calling thread + * and its action is to invoke a signal-catching function, or the process + * is terminated. The clock used to measure the time will be the clock + * specified by clock_id. + * + * If the flag TIMER_ABSTIME is set in the flags argument, the + * clock_nanosleep() function will cause the current thread to be + * suspended from execution until either the time value of the clock + * specified by clock_id reaches the absolute time specified by the rqtp + * argument, or a signal is delivered to the calling thread and its action + * is to invoke a signal-catching function, or the process is terminated. If, + * at the time of the call, the time value specified by rqtp is less than + * or equal to the time value of the specified clock, then clock_nanosleep() + * will return immediately and the calling process will not be suspended. + * + * The suspension time caused by this function may be longer than requested + * because the argument value is rounded up to an integer multiple of the + * sleep resolution, or because of the scheduling of other activity by the * system. But, except for the case of being interrupted by a signal, the - * suspension time will not be less than the time specified by rqtp, as - * measured by the system clock, CLOCK_REALTIME. + * suspension time for the relative clock_nanosleep() function (that is, + * with the TIMER_ABSTIME flag not set) will not be less than the time + * interval specified by rqtp, as measured by the corresponding clock. The + * suspension for the absolute clock_nanosleep() function (that is, with + * the TIMER_ABSTIME flag set) will be in effect at least until the value + * of the corresponding clock reaches the absolute time specified by rqtp, + * except for the case of being interrupted by a signal. + * + * The use of the clock_nanosleep() function will have no effect on the + * action or blockage of any signal. * - * The use of the nanosleep() function has no effect on the action or - * blockage of any signal. + * The clock_nanosleep() function will fail if the clock_id argument refers + * to the CPU-time clock of the calling thread. It is unspecified whether + * clock_id values of other CPU-time clocks are allowed. * * Parameters: - * rqtp - The amount of time to be suspended from execution. - * rmtp - If the rmtp argument is non-NULL, the timespec structure - * referenced by it is updated to contain the amount of time - * remaining in the interval (the requested time minus the time - * actually slept) + * clockid - The clock to use to interpret the absolute time + * flags - Open flags. TIMER_ABSTIME is the only supported flag. + * rqtp - The amount of time to be suspended from execution. + * rmtp - If the rmtp argument is non-NULL, the timespec structure + * referenced by it is updated to contain the amount of time + * remaining in the interval (the requested time minus the time + * actually slept) * * Returned Value: - * If the nanosleep() function returns because the requested time has + * If the clock_nanosleep() function returns because the requested time has * elapsed, its return value is zero. * - * If the nanosleep() function returns because it has been interrupted by + * If the clock_nanosleep() function returns because it has been interrupted by * a signal, the function returns a value of -1 and sets errno to indicate * the interruption. If the rmtp argument is non-NULL, the timespec * structure referenced by it is updated to contain the amount of time @@ -235,30 +260,76 @@ int nxsig_nanosleep(FAR const struct timespec *rqtp, * slept). If the rmtp argument is NULL, the remaining time is not * returned. * - * If nanosleep() fails, it returns a value of -1 and sets errno to - * indicate the error. The nanosleep() function will fail if: + * If clock_nanosleep() fails, it returns a value of -1 and sets errno to + * indicate the error. The clock_nanosleep() function will fail if: * - * EINTR - The nanosleep() function was interrupted by a signal. + * EINTR - The clock_nanosleep() function was interrupted by a signal. * EINVAL - The rqtp argument specified a nanosecond value less than * zero or greater than or equal to 1000 million. - * ENOSYS - The nanosleep() function is not supported by this + * ENOSYS - The clock_nanosleep() function is not supported by this * implementation. * ****************************************************************************/ -int nanosleep(FAR const struct timespec *rqtp, FAR struct timespec *rmtp) +int clock_nanosleep(clockid_t clockid, int flags, + FAR const struct timespec *rqtp, + FAR struct timespec *rmtp) { int ret; - /* nanosleep() is a cancellation point */ + /* clock_nanosleep() is a cancellation point */ (void)enter_cancellation_point(); - /* Just a wrapper around nxsig_nanosleep() */ + /* Check if absolute time is selected */ + + if ((flags & TIMER_ABSTIME) != 0) + { + struct timespec reltime; + struct timespec now; + irqstate_t irqstate; + + /* Calculate the relative time delay. We need to enter a critical + * section early to assure the relative time is valid from this + * point in time. + */ + + irqstate = enter_critical_section(); + ret = clock_gettime(clockid, &now); + if (ret < 0) + { + /* clock_gettime() sets the errno variable */ + + leave_critical_section(irqstate); + leave_cancellation_point(); + return ERROR; + } + + clock_timespec_subtract(rqtp, &now, &reltime); + + /* Now that we have the relative time, the remaining operations + * are equivalent to nxsig_nanosleep(). + */ + + ret = nxsig_nanosleep(&reltime, rmtp); + leave_critical_section(irqstate); + } + else + { + /* In the relative time case, clock_nanosleep() is equivalent to + * nanosleep. In this case, it is a paper thin wrapper around + * nxsig_nanosleep(). + */ + + ret = nxsig_nanosleep(rqtp, rmtp); + } + + /* Check if nxsig_nanosleep() succeeded */ - ret = nxsig_nanosleep(rqtp, rmtp); if (ret < 0) { + /* If not set the errno variable and return -1 */ + set_errno(-ret); ret = ERROR; } diff --git a/sched/task/task_exithook.c b/sched/task/task_exithook.c index 7333526415662e3c40e45665f02989cb070c2cac..4e80b8964d77649aac19ae689051b1ce3bac428e 100644 --- a/sched/task/task_exithook.c +++ b/sched/task/task_exithook.c @@ -98,25 +98,31 @@ static inline void task_atexit(FAR struct tcb_s *tcb) { if (group->tg_atexitfunc[index]) { - /* Call the atexit function */ - - (*group->tg_atexitfunc[index])(); + atexitfunc_t func; /* Nullify the atexit function to prevent its reuse. */ + func = group->tg_atexitfunc[index]; group->tg_atexitfunc[index] = NULL; + + /* Call the atexit function */ + + (*func)(); } } #else if (group->tg_atexitfunc) { - /* Call the atexit function */ - - (*group->tg_atexitfunc)(); + atexitfunc_t func; /* Nullify the atexit function to prevent its reuse. */ + func = group->tg_atexitfunc; group->tg_atexitfunc = NULL; + + /* Call the atexit function */ + + (*func)(); } #endif } @@ -166,25 +172,31 @@ static inline void task_onexit(FAR struct tcb_s *tcb, int status) { if (group->tg_onexitfunc[index]) { - /* Call the on_exit function */ - - (*group->tg_onexitfunc[index])(status, group->tg_onexitarg[index]); + onexitfunc_t func; /* Nullify the on_exit function to prevent its reuse. */ + func = group->tg_onexitfunc[index]; group->tg_onexitfunc[index] = NULL; + + /* Call the on_exit function */ + + (*func)(status, group->tg_onexitarg[index]); } } #else if (group->tg_onexitfunc) { - /* Call the on_exit function */ - - (*group->tg_onexitfunc)(status, group->tg_onexitarg); + onexitfunc_t func; /* Nullify the on_exit function to prevent its reuse. */ + func = group->tg_onexitfunc; group->tg_onexitfunc = NULL; + + /* Call the on_exit function */ + + (*func)(status, group->tg_onexitarg); } #endif } @@ -215,7 +227,6 @@ static inline void task_exitstatus(FAR struct task_group_s *group, int status) /* No.. Find the exit status entry for this task in the parent TCB */ child = group_findchild(group, getpid()); - DEBUGASSERT(child); if (child) { #ifndef HAVE_GROUP_MEMBERS @@ -260,7 +271,6 @@ static inline void task_groupexit(FAR struct task_group_s *group) /* No.. Find the exit status entry for this task in the parent TCB */ child = group_findchild(group, getpid()); - DEBUGASSERT(child); if (child) { /* Mark that all members of the child task group has exited */ diff --git a/syscall/syscall.csv b/syscall/syscall.csv index 22e1f0490ae0affdd112777d6955613331a367e6..ccec8647edae4c011cfff941b87c64d577234377 100644 --- a/syscall/syscall.csv +++ b/syscall/syscall.csv @@ -11,6 +11,7 @@ "clearenv","stdlib.h","!defined(CONFIG_DISABLE_ENVIRON)","int" "clock_getres","time.h","","int","clockid_t","struct timespec*" "clock_gettime","time.h","","int","clockid_t","struct timespec*" +"clock_nanosleep","time.h","!defined(CONFIG_DISABLE_SIGNALS)","int","clockid_t","int","FAR const struct timespec *", "FAR struct timespec*" "clock_settime","time.h","","int","clockid_t","const struct timespec*" "clock_systimer","nuttx/clock.h","!defined(__HAVE_KERNEL_GLOBALS)","systime_t" "close","unistd.h","CONFIG_NSOCKET_DESCRIPTORS > 0 || CONFIG_NFILE_DESCRIPTORS > 0","int","int" @@ -27,6 +28,7 @@ "fstat","sys/stat.h","CONFIG_NFILE_DESCRIPTORS > 0","int","int","FAR struct stat*" "fstatfs","sys/statfs.h","CONFIG_NFILE_DESCRIPTORS > 0","int","int","FAR struct statfs*" "fsync","unistd.h","CONFIG_NFILE_DESCRIPTORS > 0 && !defined(CONFIG_DISABLE_MOUNTPOINT)","int","int" +"ftruncate","unistd.h","CONFIG_NFILE_DESCRIPTORS > 0 && !defined(CONFIG_DISABLE_MOUNTPOINT)","int","int","off_t" "get_errno","errno.h","!defined(__DIRECT_ERRNO_ACCESS)","int" "get_errno_ptr","errno.h","defined(__DIRECT_ERRNO_ACCESS)","FAR int*" "getenv","stdlib.h","!defined(CONFIG_DISABLE_ENVIRON)","FAR char*","FAR const char*" @@ -55,7 +57,6 @@ "mq_timedsend","mqueue.h","!defined(CONFIG_DISABLE_MQUEUE)","int","mqd_t","const char*","size_t","int","const struct timespec*" "mq_unlink","mqueue.h","!defined(CONFIG_DISABLE_MQUEUE)","int","const char*" "on_exit","stdlib.h","defined(CONFIG_SCHED_ONEXIT)","int","CODE void (*)(int, FAR void *)","FAR void *" -"nanosleep","time.h","!defined(CONFIG_DISABLE_SIGNALS)","int","FAR const struct timespec *", "FAR struct timespec*" "open","fcntl.h","CONFIG_NFILE_DESCRIPTORS > 0","int","const char*","int","..." "opendir","dirent.h","CONFIG_NFILE_DESCRIPTORS > 0","FAR DIR*","FAR const char*" "pgalloc", "nuttx/arch.h", "defined(CONFIG_BUILD_KERNEL)", "uintptr_t", "uintptr_t", "unsigned int" diff --git a/syscall/syscall_lookup.h b/syscall/syscall_lookup.h index 7153313de40cb96850ee6e3f889f1ea8a9c1040a..e9a920c4e39a240ccf2c444081dbfd012305a05c 100644 --- a/syscall/syscall_lookup.h +++ b/syscall/syscall_lookup.h @@ -157,7 +157,7 @@ SYSCALL_LOOKUP(up_assert, 2, STUB_up_assert) SYSCALL_LOOKUP(sigsuspend, 1, STUB_sigsuspend) SYSCALL_LOOKUP(sigtimedwait, 3, STUB_sigtimedwait) SYSCALL_LOOKUP(sigwaitinfo, 2, STUB_sigwaitinfo) - SYSCALL_LOOKUP(nanosleep, 2, STUB_nanosleep) + SYSCALL_LOOKUP(clock_nanosleep, 4, STUB_clock_nanosleep) #endif /* The following are only defined if the system clock is enabled in the @@ -269,6 +269,7 @@ SYSCALL_LOOKUP(up_assert, 2, STUB_up_assert) SYSCALL_LOOKUP(mount, 5, STUB_mount) # endif SYSCALL_LOOKUP(fsync, 1, STUB_fsync) + SYSCALL_LOOKUP(ftruncate, 2, STUB_ftruncate) SYSCALL_LOOKUP(mkdir, 2, STUB_mkdir) SYSCALL_LOOKUP(rename, 2, STUB_rename) SYSCALL_LOOKUP(rmdir, 1, STUB_rmdir) diff --git a/syscall/syscall_stublookup.c b/syscall/syscall_stublookup.c index d58ae5c103d92fdefd328cdb89ff557d3c2be8cc..3db4ab90a0d3f4238e08eb5df3bf5c3593c204ac 100644 --- a/syscall/syscall_stublookup.c +++ b/syscall/syscall_stublookup.c @@ -153,7 +153,8 @@ uintptr_t STUB_sigsuspend(int nbr, uintptr_t parm1); uintptr_t STUB_sigtimedwait(int nbr, uintptr_t parm1, uintptr_t parm2, uintptr_t parm3); uintptr_t STUB_sigwaitinfo(int nbr, uintptr_t parm1, uintptr_t parm2); -uintptr_t STUB_nanosleep(int nbr, uintptr_t parm1, uintptr_t parm2); +uintptr_t STUB_clock_nanosleep(int nbr, uintptr_t parm1, uintptr_t parm2, + uintptr_t parm3, uintptr_t parm4); /* The following are only defined if the system clock is enabled in the * NuttX configuration. @@ -257,6 +258,7 @@ uintptr_t STUB_sched_getstreams(int nbr); ssize_t sendfile(int outfd, int infd, FAR off_t *offset, size_t count); uintptr_t STUB_fsync(int nbr, uintptr_t parm1); +uintptr_t STUB_ftruncate(int nbr, uintptr_t parm1, uintptr_t parm2); uintptr_t STUB_mkdir(int nbr, uintptr_t parm1, uintptr_t parm2); uintptr_t STUB_mount(int nbr, uintptr_t parm1, uintptr_t parm2, uintptr_t parm3, uintptr_t parm4, uintptr_t parm5); diff --git a/tools/README.txt b/tools/README.txt index 8b7fa162d53682770cc43a88916e65bf3b3b14d1..b332d495a3ddd120ab11e8bdd2241be3a7579efd 100644 --- a/tools/README.txt +++ b/tools/README.txt @@ -472,9 +472,100 @@ define.bat ide_exporter.py --------------- - This Python script will help to create nuttx project in the IAR and + This Python script will help to create NuttX project in the IAR and uVision IDEs. These are few simple the steps to export the IDE - workspaces. See for example configs/stm3220g-eval/README.txt. + workspaces. + + 1) Start the NuttX build from the Cygwin command line before trying to + create your project by running: + + make V=1 |& tee build_log + + This is necessary to certain auto-generated files and directories that + will be needed. This will provide the build log to construct the IDE + project also. + + 2) Export the IDE project base on that make log. The script usage: + + usage: ide_exporter.py [-h] [-v] [-o OUT_DIR] [-d] build_log {iar,uvision_armcc,uvision_gcc} template_dir + + positional arguments: + build_log Log file from make V=1 + {iar,uvision_armcc,uvision_gcc} + The target IDE: iar, uvision_gcc, (uvision_armcc is experimental) + template_dir Directory that contains IDEs template projects + + optional arguments: + -h, --help show this help message and exit + -v, --version show program's version number and exit + -o OUT_DIR, --output OUT_DIR + Output directory + -d, --dump Dump project structure tree + + Example: + cd nuttx + make V=1 |& tee build_log + + ./tools/ide_exporter.py makelog_f2nsh_c iar ./configs//ide/template/iar -o ./configs//ide/nsh/iar + + or + + ./tools/ide_exporter.py makelog_f2nsh_c uvision_gcc ./configs//ide/template/uvision_gcc/ -o ./configs//ide/nsh/uvision + + 3) Limitations: + - IAR supports C only. Iar C++ does not compatible with g++ so disable + C++ if you want to use IAR. + - uvision_armcc : nuttx asm (inline and .asm) can't be compiled with + armcc so do not use this option. + - uvision_gcc : uvision project that uses gcc. Need to specify path to + gnu toolchain. + In uVison menu, select: + + Project/Manage/Project Items.../FolderExtension/Use GCC compiler/ PreFix, Folder + + 4) Template projects' constrains: + - mcu, core, link script shall be configured in template project + - Templates' name are fixed: + - template_nuttx.eww : IAR nuttx workspace template + - template_nuttx_lib.ewp : IAR nuttx library project template + - template_nuttx_main.ewp : IAR nuttx main project template + - template_nuttx.uvmpw : uVision workspace + - template_nuttx_lib.uvproj : uVision library project + - template_nuttx_main.uvproj : uVision main project + - iar: + - Library option shall be set to 'None' so that IAR could use nuttx + libc + - __ASSEMBLY__ symbol shall be defined in assembler + - uVision_gcc: + - There should be one fake .S file in projects that has been defined + __ASSEMBLY__ in assembler. + - In Option/CC tab : disable warning + - In Option/CC tab : select Compile thump code (or Misc control = + -mthumb) + - template_nuttx_lib.uvproj shall add 'Post build action' to copy .a + file to .\lib + - template_nuttx_main.uvproj Linker: + - Select 'Do not use Standard System Startup Files' and 'Do not + use Standard System Libraries' + - Do not select 'Use Math libraries' + - Misc control = --entry=__start + + 5) How to create template for other configurations: + 1) uVision with gcc toolchain: + - Copy 3 uVision project files + - Select the MCU for main and lib project + - Correct the path to ld script if needed + 2) iar: + - Check if the arch supportes IAR (only armv7-m is support IAR + now) + - Select the MCU for main and lib project + - Add new ld script file for IAR + + NOTE: Due to bit rot, the template files for the stm3220g-eval and for + the stm32f429-disco have been removed from the NuttX repository. For + reference, they be found in the Obsoleted repository at + Obsoleted/stm32f429i_disco/ltcd/template and at + Obsoleted/stm3220g-eval/template. incdir.sh incdir.bat diff --git a/tools/configure.c b/tools/configure.c index 4ada47924dbc92159e38395d847c631e6ffd8a5b..92cd7ce3274d140ed0378730d964fdc496a7c79a 100644 --- a/tools/configure.c +++ b/tools/configure.c @@ -65,7 +65,8 @@ #define HOST_NOCHANGE 0 #define HOST_LINUX 1 -#define HOST_WINDOWS 2 +#define HOST_MACOS 2 +#define HOST_WINDOWS 3 #define WINDOWS_NATIVE 1 #define WINDOWS_CYGWIN 2 @@ -127,7 +128,7 @@ static const char *g_optfiles[] = static void show_usage(const char *progname, int exitcode) { - fprintf(stderr, "\nUSAGE: %s [-d] [-b] [-f] [-l|c|u|n] [-a ] [%c]\n", progname, g_delim); + fprintf(stderr, "\nUSAGE: %s [-d] [-b] [-f] [-l|m|c|u|n] [-a ] [%c]\n", progname, g_delim); fprintf(stderr, "\nUSAGE: %s [-h]\n\n", progname); fprintf(stderr, "\nWhere:\n"); fprintf(stderr, " -d:\n"); @@ -150,13 +151,16 @@ static void show_usage(const char *progname, int exitcode) fprintf(stderr, " instead of Windows style paths like C:\\Program Files are used. POSIX\n"); fprintf(stderr, " style paths are used by default.\n"); #endif - fprintf(stderr, " -l:\n"); - fprintf(stderr, " Selects the Linux (l) host environment. The [-c|u|n] options\n"); - fprintf(stderr, " select one of the Windows environments. Default: Use host setup\n"); - fprintf(stderr, " in the defconfig file\n"); - fprintf(stderr, " [-c|u|n]\n"); - fprintf(stderr, " Selects the Windows host and a Windows host environment: Cygwin (c),\n"); - fprintf(stderr, " Ubuntu under Windows 10 (u), or Windows native (n). Default Cygwin\n"); + fprintf(stderr, " [-l|m|c|u|n]\n"); + fprintf(stderr, " Selects the host environment.\n"); + fprintf(stderr, " -l Selects the Linux (l) host environment.\n"); + fprintf(stderr, " -m Selects the macOS (m) host environment.\n"); + fprintf(stderr, " [-c|u|n] selects the Windows host and a Windows host environment:\n"); + fprintf(stderr, " -c Selects the Windows host and Cygwin (c) environment.\n"); + fprintf(stderr, " -u Selects the Windows host and Ubuntu under Windows 10 (u) environment.\n"); + fprintf(stderr, " -n Selects the Windows host and Windows native (n) environment.\n"); + fprintf(stderr, " Default: Use host setup in the defconfig file.\n"); + fprintf(stderr, " Default Windows: Cygwin.\n"); fprintf(stderr, " -a :\n"); fprintf(stderr, " Informs the configuration tool where the application build\n"); fprintf(stderr, " directory. This is a relative path from the top-level NuttX\n"); @@ -196,7 +200,7 @@ static void parse_args(int argc, char **argv) g_debug = false; - while ((ch = getopt(argc, argv, ":a:bcdfhlnu")) > 0) + while ((ch = getopt(argc, argv, ":a:bcdfhlmnu")) > 0) { switch (ch) { @@ -230,6 +234,10 @@ static void parse_args(int argc, char **argv) g_host = HOST_LINUX; break; + case 'm' : + g_host = HOST_MACOS; + break; + case 'n' : g_host = HOST_WINDOWS; g_windows = WINDOWS_NATIVE; @@ -569,6 +577,33 @@ static void check_configdir(void) } } +static void check_configured(void) +{ + /* If we are already configured then there will be a .config and a Make.defs + * file in the top-level directory. + */ + + snprintf(g_buffer, BUFFER_SIZE, "%s%c.config", g_topdir, g_delim); + debug("check_configured: Checking %s\n", g_buffer); + if (verify_file(g_buffer)) + { + fprintf(stderr, "ERROR: Found %s... Already configured\n", g_buffer); + fprintf(stderr, " Please 'make distclean' and try again\n"); + exit(EXIT_FAILURE); + } + + /* Try the Make.defs file */ + + snprintf(g_buffer, BUFFER_SIZE, "%s%cMake.defs", g_topdir, g_delim); + debug("check_configuration: Checking %s\n", g_buffer); + if (verify_file(g_buffer)) + { + fprintf(stderr, "ERROR: Found %s... Already configured\n", g_buffer); + fprintf(stderr, " Please 'make distclean' and try again\n"); + exit(EXIT_FAILURE); + } +} + static void read_configfile(void) { FILE *stream; @@ -946,14 +981,35 @@ static void disable_feature(const char *destconfig, const char *varname) static void set_host(const char *destconfig) { - if (g_host != HOST_NOCHANGE) + switch (g_host) { - if (g_host == HOST_LINUX) + case HOST_LINUX: { printf(" Select the Linux host\n"); enable_feature(destconfig, "CONFIG_HOST_LINUX"); disable_feature(destconfig, "CONFIG_HOST_WINDOWS"); + disable_feature(destconfig, "CONFIG_HOST_OSX"); + + disable_feature(destconfig, "CONFIG_WINDOWS_NATIVE"); + disable_feature(destconfig, "CONFIG_WINDOWS_CYGWIN"); + disable_feature(destconfig, "CONFIG_WINDOWS_UBUNTU"); + disable_feature(destconfig, "CONFIG_WINDOWS_MSYS"); + disable_feature(destconfig, "CONFIG_WINDOWS_OTHER"); + + enable_feature(destconfig, "CONFIG_SIM_X8664_SYSTEMV"); + disable_feature(destconfig, "CONFIG_SIM_X8664_MICROSOFT"); + disable_feature(destconfig, "CONFIG_SIM_M32"); + } + break; + + case HOST_MACOS: + { + printf(" Select the Linux host\n"); + + disable_feature(destconfig, "CONFIG_HOST_LINUX"); + disable_feature(destconfig, "CONFIG_HOST_WINDOWS"); + enable_feature(destconfig, "CONFIG_HOST_OSX"); disable_feature(destconfig, "CONFIG_WINDOWS_NATIVE"); disable_feature(destconfig, "CONFIG_WINDOWS_CYGWIN"); @@ -965,10 +1021,13 @@ static void set_host(const char *destconfig) disable_feature(destconfig, "CONFIG_SIM_X8664_MICROSOFT"); disable_feature(destconfig, "CONFIG_SIM_M32"); } - else if (g_host == HOST_WINDOWS) + break; + + case HOST_WINDOWS: { enable_feature(destconfig, "CONFIG_HOST_WINDOWS"); disable_feature(destconfig, "CONFIG_HOST_LINUX"); + disable_feature(destconfig, "CONFIG_HOST_OSX"); disable_feature(destconfig, "CONFIG_WINDOWS_MSYS"); disable_feature(destconfig, "CONFIG_WINDOWS_OTHER"); @@ -1002,12 +1061,18 @@ static void set_host(const char *destconfig) break; default: - fprintf(stderr, "ERROR: Unrecognized windows configuration: %d\n", + fprintf(stderr, + "ERROR: Unrecognized windows configuration: %d\n", g_windows); exit(EXIT_FAILURE); } } - else + break; + + case HOST_NOCHANGE: + break; + + default: { fprintf(stderr, "ERROR: Unrecognized host configuration: %d\n", g_host); exit(EXIT_FAILURE); @@ -1135,6 +1200,7 @@ int main(int argc, char **argv, char **envp) debug("main: Checking Nuttx Directories\n"); find_topdir(); check_configdir(); + check_configured(); debug("main: Reading the configuration/version files\n"); read_configfile(); diff --git a/tools/configure.sh b/tools/configure.sh index d40671992528c30223d871923519a758a866def8..e4a6c5f29c1ed184ec59096bb2505dd9d5f1634c 100755 --- a/tools/configure.sh +++ b/tools/configure.sh @@ -36,14 +36,16 @@ WD=`test -d ${0%/*} && cd ${0%/*}; pwd` TOPDIR="${WD}/.." USAGE=" -USAGE: ${0} [-d] [-l|c|u|n] [-a ] / +USAGE: ${0} [-d] [-l|m|c|u|n] [-a ] / Where: - -l selects the Linux (l) host environment. The [-c|u|n] options - select one of the Windows environments. Default: Use host setup - in the defconfig file - [-c|u|n] selects the Windows host and a Windows environment: Cygwin (c), - Ubuntu under Windows 10 (u), or Windows native (n). Default Cygwin + -l selects the Linux (l) host environment. + -m selects the macOS (m) host environment. + -c selects the Windows host and Cygwin (c) environment. + -u selects the Windows host and Ubuntu under Windows 10 (u) environment. + -n selects the Windows host and Windows native (n) environment. + Default: Use host setup in the defconfig file + Default Windows: Cygwin is the name of the board in the configs directory is the name of the board configuration sub-directory is the path to the apps/ directory, relative to the nuttx @@ -86,6 +88,9 @@ while [ ! -z "$1" ]; do -l ) host=linux ;; + -m ) + host=macos + ;; -n ) host=windows wenv=native @@ -279,31 +284,40 @@ if [ ! -z "$host" ]; then sed -i -e "/CONFIG_SIM_X8664_SYSTEMV/d" ${dest_config} sed -i -e "/CONFIG_SIM_M32/d" ${dest_config} - if [ "$host" == "linux" ]; then - echo " Select CONFIG_HOST_LINUX=y" - echo "CONFIG_HOST_LINUX=y" >> "${dest_config}" - echo "CONFIG_SIM_X8664_SYSTEMV=y" >> "${dest_config}" + case "$host" in + "linux") + echo " Select CONFIG_HOST_LINUX=y" + echo "CONFIG_HOST_LINUX=y" >> "${dest_config}" + echo "CONFIG_SIM_X8664_SYSTEMV=y" >> "${dest_config}" + ;; - else - echo " Select CONFIG_HOST_WINDOWS=y" - echo "CONFIG_HOST_WINDOWS=y" >> "${dest_config}" - echo "CONFIG_SIM_X8664_MICROSOFT=y" >> "${dest_config}" - - if [ "X$wenv" == "Xcygwin" ]; then - echo " Select CONFIG_WINDOWS_CYGWIN=y" - echo "CONFIG_WINDOWS_CYGWIN=y" >> "${dest_config}" - - else - if [ "X$wenv" == "Xubuntu" ]; then - echo " Select CONFIG_WINDOWS_UBUNTU=y" - echo "CONFIG_WINDOWS_UBUNTU=y" >> "${dest_config}" - - else - echo " Select CONFIG_WINDOWS_NATIVE=y" - echo "CONFIG_WINDOWS_NATIVE=y" >> "${dest_config}" - fi - fi - fi + "macos") + echo " Select CONFIG_HOST_OSX=y" + echo "CONFIG_HOST_OSX=y" >> "${dest_config}" + ;; + + "windows") + echo " Select CONFIG_HOST_WINDOWS=y" + echo "CONFIG_HOST_WINDOWS=y" >> "${dest_config}" + echo "CONFIG_SIM_X8664_MICROSOFT=y" >> "${dest_config}" + + case "$wenv" in + "cygwin") + echo " Select CONFIG_WINDOWS_CYGWIN=y" + echo "CONFIG_WINDOWS_CYGWIN=y" >> "${dest_config}" + ;; + + "ubuntu") + echo " Select CONFIG_WINDOWS_UBUNTU=y" + echo "CONFIG_WINDOWS_UBUNTU=y" >> "${dest_config}" + ;; + + *) + echo " Select CONFIG_WINDOWS_NATIVE=y" + echo "CONFIG_WINDOWS_NATIVE=y" >> "${dest_config}" + ;; + esac + esac fi # The saved defconfig files are all in compressed format and must be diff --git a/tools/csvparser.c b/tools/csvparser.c index 8553d29ce5a5ea616bb090b3bd08ac02b26623ef..259d7c76620a7618519f2760dba842da06ae7be4 100644 --- a/tools/csvparser.c +++ b/tools/csvparser.c @@ -213,6 +213,12 @@ int parse_csvline(char *ptr) do { + if (nparms >= MAX_FIELDS) + { + fprintf(stderr, "%d: Too many Parameters: \"%s\"\n", g_lineno, g_line); + exit(8); + } + ptr = copy_parm(ptr, &g_parm[nparms][0]); nparms++; ptr = find_parm(ptr); diff --git a/wireless/ieee802154/Kconfig b/wireless/ieee802154/Kconfig index cf96b1661690496a9b24646319455ad8c5d4b725..fd3e0cd56e1369ff681a2409e9abed53d3206a08 100644 --- a/wireless/ieee802154/Kconfig +++ b/wireless/ieee802154/Kconfig @@ -15,44 +15,61 @@ menuconfig WIRELESS_IEEE802154 if WIRELESS_IEEE802154 +config IEEE802154_PRIMITIVE_PREALLOC + int "Number of pre-allocated primitive structures" + default 20 + ---help--- + This specifies the total number of preallocated primitive structures. + A primitive is an abstracted data type that provides service information + between the MAC layer and the next highest layer. These may be allocated + from either from tasking logic or from interrupt level logic. + +config IEEE802154_PRIMITIVE_IRQRESERVE + int "Reserved pre-allocated primitive structures" + default 0 + depends on EXPERIMENTAL + ---help--- + If primitves can be allocated from interrupt handlers, then this + specifies the number of pre-allocatd meta-data structures that are + reserved for for use only by interrupt handlers. This may be zero to + reserve no meta-data structures for interrupt handlers. In that case, + the allocation will fail if tasking logic has allocated them all. + + Interrupt logic will first attempt to allocate from the general, + pre-allocated structure pool that will contain up to (size + CONFIG_IEEE802154_PRIMITIVE_PREALLOC - CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE) + entries. If that fails, then it will try to take a structure from + the reserve (size CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE). + + Non-interrupt logic will also first attempt to allocate from the + general, pre-allocated structure pool. If that fails, it will + dynamically allocate the primitive with an additional cost in performance. + + NOTE: Currently marked as experimental and with a default of zero + because there are no interrupt level allocations performed by the + current IEEE 802.15.4 MAC code. + config IEEE802154_DEFAULT_EADDR hex "IEEE 802.15.4 Default Extended Address" default 0x00fade00deadbeef ---help--- Set the default extended address to be used by MAC networks on init -choice - prompt "IEEE 802.15.4 work queue" - default MAC802154_HPWORK if SCHED_HPWORK - default MAC802154_LPWORK if !SCHED_HPWORK && SCHED_LPWORK - depends on SCHED_WORKQUEUE +config IEEE802154_MAC + bool "Software MAC layer" + default n ---help--- - Work queue support is required to use the IEEE 802.15.4 MAC layer. - If the high priority work queue is available, then it should be used by - the driver. - - WARNING!! The IEEE802.15.4 network device must never run on the same - work queue as does the IEEE 802.15.4 MAC. That configuration will - cause deadlocks: The network logic may be blocked on the work queue - waiting on resources that can only be freed by the MAC logic but the - MAC is unable to run because the work queue is blocked. The - recommended configuration is: Network on the LP work queue; MAC on HP - work queue. Blocking on the HP work queue is a very bad thing in - any case. + There are two types of IEEE 802.15.4 radios supported. Those that provide + all MAC functionality equivalent to the MAC802154 software implementation, + and radios that provide a lower half to the MAC802154 software layer. + This option enables the software MAC layer that can interface with + the lower-half radio drivers. -config MAC802154_HPWORK - bool "High priority" - depends on SCHED_HPWORK - -config MAC802154_LPWORK - bool "Low priority" - depends on SCHED_LPWORK - -endchoice # Work queue +if IEEE802154_MAC config MAC802154_NTXDESC int "Number or TX descriptors" - default 3 + default 5 ---help--- Configured number of Tx descriptors. Default: 3 @@ -63,16 +80,6 @@ config MAC802154_NTXDESC Then there should be the maximum pre-allocated buffers for each possible TX frame. -config MAC802154_NNOTIF - int "Number or notification structures" - default 3 - ---help--- - Configured number of notification strucures Default: 3 - - When various MAC management events occur, the MAC notifies the registered - receiver with an allocated notification structure indicating the event. The - events are primitives such as Association Indication etc. - config MAC802154_NPANDESC int "Number of PAN descriptors" default 5 @@ -97,40 +104,6 @@ config MAC802154_LOCK_VERBOSE ---help--- Enable verbose logging of MAC lock management. Default: false -config IEEE802154_IND_PREALLOC - int "Number of pre-allocated meta-data structures" - default 20 - ---help--- - This specifies the total number of preallocated meta data structures - must be allocated with each incoming packet. These may be allocated - from either from tasking logic or from interrupt level logic. - -config IEEE802154_IND_IRQRESERVE - int "Reserved pre-allocated meta-data structures" - default 0 - depends on EXPERIMENTAL - ---help--- - If meta-data structures can be allocated from interrupt handlers, - then this specifies the number of pre-allocatd meta-data structures - that are reserved for for use only by interrupt handlers. This may - be zero to reserve no meta-data structures for interrupt handlers. - In that case, the allocation will fail if tasking logic has - allocated them all. - - Interrupt logic will first attempt to allocate from the general, - pre-allocated structure pool that will contain up to (size - CONFIG_IEEE802154_IND_PREALLOC - CONFIG_IEEE802154_IND_IRQRESERVE) - entries. If that fails, then it will try to take a structure from - the reserve (size CONFIG_IEEE802154_IND_IRQRESERVE). - - Non-interrupt logic will also first attempt to allocate from the - general, pre-allocated structure pool. If that fails, it will - dynamically allocate the meta data structure with an additional cost - in performance. - - NOTE: Currently marked as experimental and with a default of zero - because there are no interrupt level allocations performed by the - current IEEE 802.15.4 MAC code. config IEEE802154_MACDEV bool "Character driver for IEEE 802.15.4 MAC layer" @@ -221,6 +194,8 @@ config IEEE802154_NETDEV_LPWORK endchoice # Work queue endif # IEEE802154_NETDEV +endif # IEEE802154_MACDEV + config IEEE802154_LOOPBACK bool "IEEE802154 6LoWPAN Loopback" default n diff --git a/wireless/ieee802154/Make.defs b/wireless/ieee802154/Make.defs index 18b52f2cf7e674baf149820da1c5a854f232b9f5..7de9c47d305ba0f9d26254430954331872e1a0d9 100644 --- a/wireless/ieee802154/Make.defs +++ b/wireless/ieee802154/Make.defs @@ -37,12 +37,16 @@ ifeq ($(CONFIG_WIRELESS_IEEE802154),y) # Include IEEE 802.15.4 support -CSRCS += ieee802154_indalloc.c mac802154.c mac802154_assoc.c mac802154_disassoc.c +CSRCS += ieee802154_primitive.c + +ifeq ($(CONFIG_IEEE802154_MAC),y) + +CSRCS += mac802154.c mac802154_assoc.c mac802154_disassoc.c CSRCS += mac802154_bind.c mac802154_data.c mac802154_get_mhrlen.c CSRCS += mac802154_getset.c mac802154_gts.c mac802154_ioctl.c -CSRCS += mac802154_notif.c mac802154_orphan.c mac802154_poll.c mac802154_purge.c -CSRCS += mac802154_reset.c mac802154_rxenable.c mac802154_scan.c mac802154_start.c -CSRCS += mac802154_sync.c +CSRCS += mac802154_orphan.c mac802154_poll.c mac802154_purge.c +CSRCS += mac802154_reset.c mac802154_rxenable.c mac802154_scan.c +CSRCS += mac802154_start.c mac802154_sync.c # Include wireless devices build support @@ -54,6 +58,8 @@ ifeq ($(CONFIG_IEEE802154_NETDEV),y) CSRCS += mac802154_netdev.c endif +endif + ifeq ($(CONFIG_IEEE802154_LOOPBACK),y) CSRCS += mac802154_loopback.c endif diff --git a/wireless/ieee802154/ieee802154_indalloc.c b/wireless/ieee802154/ieee802154_primitive.c similarity index 54% rename from wireless/ieee802154/ieee802154_indalloc.c rename to wireless/ieee802154/ieee802154_primitive.c index 03dcba8630896f293408f04ac3d00cba764e4a94..35db231fcd467e10497eabebc796630765b525e1 100644 --- a/wireless/ieee802154/ieee802154_indalloc.c +++ b/wireless/ieee802154/ieee802154_primitive.c @@ -1,5 +1,5 @@ /**************************************************************************** - * wireless/ieee802154/ieee802154_indalloc.c + * wireless/ieee802154/ieee802154_primitive.c * * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -43,9 +43,6 @@ #include #include - -#include - #include #include "mac802154.h" @@ -54,46 +51,46 @@ * Pre-processor Definitions ****************************************************************************/ -/* NOTE: The CONFIG_IEEE802154_IND_IRQRESERVE options is marked as marked +/* NOTE: The CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE options is marked as marked * 'experimental' and with the default 0 zero because there are no interrupt * level allocations performed by the current IEEE 802.15.4 MAC code. */ -#if !defined(CONFIG_IEEE802154_IND_PREALLOC) || \ - CONFIG_IEEE802154_IND_PREALLOC < 0 -# undef CONFIG_IEEE802154_IND_PREALLOC -# define CONFIG_IEEE802154_IND_PREALLOC 20 +#if !defined(CONFIG_IEEE802154_PRIMITIVE_PREALLOC) || \ + CONFIG_IEEE802154_PRIMITIVE_PREALLOC < 0 +# undef CONFIG_IEEE802154_PRIMITIVE_PREALLOC +# define CONFIG_IEEE802154_PRIMITIVE_PREALLOC 20 #endif -#if !defined(CONFIG_IEEE802154_IND_IRQRESERVE) || \ - CONFIG_IEEE802154_IND_IRQRESERVE < 0 -# undef CONFIG_IEEE802154_IND_IRQRESERVE -# define CONFIG_IEEE802154_IND_IRQRESERVE 0 +#if !defined(CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE) || \ + CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE < 0 +# undef CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE +# define CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE 0 #endif -#if CONFIG_IEEE802154_IND_IRQRESERVE > CONFIG_IEEE802154_IND_PREALLOC -# undef CONFIG_IEEE802154_IND_IRQRESERVE -# define CONFIG_IEEE802154_IND_IRQRESERVE CONFIG_IEEE802154_IND_PREALLOC +#if CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE > CONFIG_IEEE802154_PRIMITIVE_PREALLOC +# undef CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE +# define CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE CONFIG_IEEE802154_PRIMITIVE_PREALLOC #endif /* Memory Pools */ -#define POOL_IND_GENERAL 0 -#define POOL_IND_IRQ 1 -#define POOL_IND_DYNAMIC 2 +#define POOL_PRIMITIVE_GENERAL 0 +#define POOL_PRIMITIVE_IRQ 1 +#define POOL_PRIMITIVE_DYNAMIC 2 /**************************************************************************** * Private Data Types ****************************************************************************/ -/* Private data type that extends the ieee802154_data_ind_s struct */ +/* Private data type that extends the ieee802154_primitive_s struct */ -struct ieee802154_priv_ind_s +struct ieee802154_priv_primitive_s { /* Must be first member so we can cast to/from */ - struct ieee802154_data_ind_s pub; - FAR struct ieee802154_priv_ind_s *flink; + struct ieee802154_primitive_s pub; + FAR struct ieee802154_priv_primitive_s *flink; uint8_t pool; }; @@ -101,38 +98,40 @@ struct ieee802154_priv_ind_s * Private Data ****************************************************************************/ -#if CONFIG_IEEE802154_IND_PREALLOC > 0 -#if CONFIG_IEEE802154_IND_PREALLOC > CONFIG_IEEE802154_IND_IRQRESERVE -/* The g_indfree is a list of meta-data structures that are available for +#if CONFIG_IEEE802154_PRIMITIVE_PREALLOC > 0 +#if CONFIG_IEEE802154_PRIMITIVE_PREALLOC > CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE +/* The g_primfree is a list of primitive structures that are available for * general use. The number of messages in this list is a system configuration * item. */ -static struct ieee802154_priv_ind_s *g_indfree; +static struct ieee802154_priv_primitive_s *g_primfree; #endif -#if CONFIG_IEEE802154_IND_IRQRESERVE > 0 -/* The g_indfree_irq is a list of meta-data structures that are reserved for +#if CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE > 0 +/* The g_primfree_irq is a list of primitive structures that are reserved for * use by only by interrupt handlers. */ -static struct ieee802154_priv_ind_s *g_indfree_irq; +static struct ieee802154_priv_primitive_s *g_primfree_irq; #endif -/* Pool of pre-allocated meta-data stuctures */ +/* Pool of pre-allocated primitive stuctures */ + +static struct ieee802154_priv_primitive_s g_primpool[CONFIG_IEEE802154_PRIMITIVE_PREALLOC]; +#endif /* CONFIG_IEEE802154_PRIMITIVE_PREALLOC > 0 */ -static struct ieee802154_priv_ind_s g_indpool[CONFIG_IEEE802154_IND_PREALLOC]; -#endif /* CONFIG_IEEE802154_IND_PREALLOC > 0 */ +static bool g_poolinit = false; /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: ieee802154_indpool_initialize + * Name: ieee802154_primitivepool_initialize * * Description: - * This function initializes the meta-data allocator. This function must + * This function initializes the primitive allocator. This function must * be called early in the initialization sequence before any radios * begin operation. * @@ -144,28 +143,37 @@ static struct ieee802154_priv_ind_s g_indpool[CONFIG_IEEE802154_IND_PREALLOC]; * ****************************************************************************/ -void ieee802154_indpool_initialize(void) +void ieee802154_primitivepool_initialize(void) { -#if CONFIG_IEEE802154_IND_PREALLOC > 0 - FAR struct ieee802154_priv_ind_s *pool = g_indpool; - int remaining = CONFIG_IEEE802154_IND_PREALLOC; + /* Only allow the pool to be initialized once */ + + if (g_poolinit) + { + return; + } -#if CONFIG_IEEE802154_IND_PREALLOC > CONFIG_IEEE802154_IND_IRQRESERVE - /* Initialize g_indfree, thelist of meta-data structures that are available + g_poolinit = true; + +#if CONFIG_IEEE802154_PRIMITIVE_PREALLOC > 0 + FAR struct ieee802154_priv_primitive_s *pool = g_primpool; + int remaining = CONFIG_IEEE802154_PRIMITIVE_PREALLOC; + +#if CONFIG_IEEE802154_PRIMITIVE_PREALLOC > CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE + /* Initialize g_primfree, thelist of primitive structures that are available * for general use. */ - g_indfree = NULL; - while (remaining > CONFIG_IEEE802154_IND_IRQRESERVE) + g_primfree = NULL; + while (remaining > CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE) { - FAR struct ieee802154_priv_ind_s *ind = pool; + FAR struct ieee802154_priv_primitive_s *prim = pool; /* Add the next meta data structure from the pool to the list of * general structures. */ - ind->flink = g_indfree; - g_indfree = ind; + prim->flink = g_primfree; + g_primfree = prim; /* Set up for the next structure from the pool */ @@ -174,22 +182,22 @@ void ieee802154_indpool_initialize(void) } #endif -#if CONFIG_IEEE802154_IND_IRQRESERVE > 0 - /* Initialize g_indfree_irq is a list of meta-data structures reserved for +#if CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE > 0 + /* Initialize g_primfree_irq is a list of primitive structures reserved for * use by only by interrupt handlers. */ - g_indfree_irq = NULL; + g_primfree_irq = NULL; while (remaining > 0) { - FAR struct ieee802154_priv_ind_s *ind = pool; + FAR struct ieee802154_priv_primitive_s *prim = pool; /* Add the next meta data structure from the pool to the list of * general structures. */ - ind->flink = g_indfree_irq; - g_indfree_irq = ind; + prim->flink = g_primfree_irq; + g_primfree_irq = prim; /* Set up for the next structure from the pool */ @@ -197,39 +205,39 @@ void ieee802154_indpool_initialize(void) remaining--; } #endif -#endif /* CONFIG_IEEE802154_IND_PREALLOC > 0 */ +#endif /* CONFIG_IEEE802154_PRIMITIVE_PREALLOC > 0 */ } /**************************************************************************** - * Name: ieee802154_ind_allocate + * Name: ieee802154_primitive_allocate * * Description: - * The ieee802154_ind_allocate function will get a free meta-data + * The ieee802154_primitive_allocate function will get a free primitive * structure for use by the IEEE 802.15.4 MAC. * * Interrupt handling logic will first attempt to allocate from the - * g_indfree list. If that list is empty, it will attempt to allocate - * from its reserve, g_indfree_irq. If that list is empty, then the + * g_primfree list. If that list is empty, it will attempt to allocate + * from its reserve, g_primfree_irq. If that list is empty, then the * allocation fails (NULL is returned). * - * Non-interrupt handler logic will attempt to allocate from g_indfree - * list. If that the list is empty, then the meta-data structure will be + * Non-interrupt handler logic will attempt to allocate from g_primfree + * list. If that the list is empty, then the primitive structure will be * allocated from the dynamic memory pool. * * Inputs: * None * * Return Value: - * A reference to the allocated msg structure. All user fields in this + * A reference to the allocated primitive structure. All user fields in this * structure have been zeroed. On a failure to allocate, NULL is * returned. * ****************************************************************************/ -FAR struct ieee802154_data_ind_s *ieee802154_ind_allocate(void) +FAR struct ieee802154_primitive_s *ieee802154_primitive_allocate(void) { -#if CONFIG_IEEE802154_IND_PREALLOC > 0 - FAR struct ieee802154_priv_ind_s *ind; +#if CONFIG_IEEE802154_PRIMITIVE_PREALLOC > 0 + FAR struct ieee802154_priv_primitive_s *prim; irqstate_t flags; uint8_t pool; @@ -241,29 +249,29 @@ FAR struct ieee802154_data_ind_s *ieee802154_ind_allocate(void) flags = enter_critical_section(); /* Always necessary in SMP mode */ if (up_interrupt_context()) { -#if CONFIG_IEEE802154_IND_PREALLOC > CONFIG_IEEE802154_IND_IRQRESERVE +#if CONFIG_IEEE802154_PRIMITIVE_PREALLOC > CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE /* Try the general free list */ - if (g_indfree != NULL) + if (g_primfree != NULL) { - ind = g_indfree; - g_indfree = ind->flink; + prim = g_primfree; + g_primfree = prim->flink; leave_critical_section(flags); - pool = POOL_IND_GENERAL; + pool = POOL_PRIMITIVE_GENERAL; } else #endif -#if CONFIG_IEEE802154_IND_IRQRESERVE > 0 +#if CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE > 0 /* Try the list list reserved for interrupt handlers */ - if (g_indfree_irq != NULL) + if (g_primfree_irq != NULL) { - ind = g_indfree_irq; - g_indfree_irq = ind->flink; + prim = g_primfree_irq; + g_primfree_irq = prim->flink; leave_critical_section(flags); - pool = POOL_IND_IRQ; + pool = POOL_PRIMITIVE_IRQ; } else #endif @@ -277,136 +285,116 @@ FAR struct ieee802154_data_ind_s *ieee802154_ind_allocate(void) else { -#if CONFIG_IEEE802154_IND_PREALLOC > CONFIG_IEEE802154_IND_IRQRESERVE +#if CONFIG_IEEE802154_PRIMITIVE_PREALLOC > CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE /* Try the general free list */ - if (g_indfree != NULL) + if (g_primfree != NULL) { - ind = g_indfree; - g_indfree = ind->flink; + prim = g_primfree; + g_primfree = prim->flink; leave_critical_section(flags); - pool = POOL_IND_GENERAL; + pool = POOL_PRIMITIVE_GENERAL; } else #endif { - /* If we cannot a meta-data structure from the free list, then we + /* If we cannot a primitive structure from the free list, then we * will have to allocate one from the kernal memory pool. */ leave_critical_section(flags); - ind = (FAR struct ieee802154_priv_ind_s *) - kmm_malloc((sizeof (struct ieee802154_priv_ind_s))); + prim = (FAR struct ieee802154_priv_primitive_s *) + kmm_malloc((sizeof (struct ieee802154_priv_primitive_s))); - /* Check if we allocated the meta-data structure */ + /* Check if we allocated the primitive structure */ - if (ind != NULL) + if (prim != NULL) { - /* Yes... remember that this meta-data structure was dynamically allocated */ + /* Yes... remember that this primitive structure was dynamically allocated */ - pool = POOL_IND_DYNAMIC; + pool = POOL_PRIMITIVE_DYNAMIC; } } } /* We have successfully allocated memory from some source. - * Zero and tag the alloated meta-data structure. + * Zero and tag the alloated primitive structure. */ - ind->pool = pool; - memset(&ind->pub, 0, sizeof(struct ieee802154_data_ind_s)); - - /* Allocate the IOB for the frame */ - - ind->pub.frame = iob_alloc(true); - if (ind->pub.frame == NULL) - { - /* Deallocate the ind */ - - ieee802154_ind_free(&ind->pub); - - return NULL; - } - - ind->pub.frame->io_flink = NULL; - ind->pub.frame->io_len = 0; - ind->pub.frame->io_offset = 0; - ind->pub.frame->io_pktlen = 0; + prim->pool = pool; + memset(&prim->pub, 0, sizeof(struct ieee802154_primitive_s)); - return &ind->pub; + wlinfo("Primitive allocated: %p\n", prim); + return &prim->pub; #else return NULL; #endif } /**************************************************************************** - * Name: ieee802154_ind_free + * Name: ieee802154_primitive_free * * Description: - * The ieee802154_ind_free function will return a meta-data structure to - * the free pool of messages if it was a pre-allocated meta-data - * structure. If the meta-data structure was allocated dynamically it will + * The ieee802154_primitive_free function will return a primitive structure to + * the free pool of messages if it was a pre-allocated primitive + * structure. If the primitive structure was allocated dynamically it will * be deallocated. * * Inputs: - * ind - meta-data structure to free + * prim - primitive structure to free * * Return Value: * None * ****************************************************************************/ -void ieee802154_ind_free(FAR struct ieee802154_data_ind_s *ind) +void ieee802154_primitive_free(FAR struct ieee802154_primitive_s *prim) { -#if CONFIG_IEEE802154_IND_PREALLOC > 0 - irqstate_t flags; - FAR struct ieee802154_priv_ind_s *priv = - (FAR struct ieee802154_priv_ind_s *)ind; - - /* Check if the IOB is not NULL. The only time it should be NULL is if we - * allocated the data_ind, but the IOB allocation failed so we now have to - * free the data_ind but not the IOB. This really should happen rarely if at all. - */ - - if (ind->frame != NULL) + if (--prim->nclients > 0) { - iob_free(ind->frame); + wlinfo("Remaining Clients: %d\n", prim->nclients); + return; } -#if CONFIG_IEEE802154_IND_PREALLOC > CONFIG_IEEE802154_IND_IRQRESERVE - /* If this is a generally available pre-allocated meta-data structure, +#if CONFIG_IEEE802154_PRIMITIVE_PREALLOC > 0 + irqstate_t flags; + FAR struct ieee802154_priv_primitive_s *priv = + (FAR struct ieee802154_priv_primitive_s *)prim; + +#if CONFIG_IEEE802154_PRIMITIVE_PREALLOC > CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE + /* If this is a generally available pre-allocated primitive structure, * then just put it back in the free list. */ - if (priv->pool == POOL_IND_GENERAL) + if (priv->pool == POOL_PRIMITIVE_GENERAL) { /* Make sure we avoid concurrent access to the free * list from interrupt handlers. */ flags = enter_critical_section(); - priv->flink = g_indfree; - g_indfree = priv; + priv->flink = g_primfree; + g_primfree = priv; leave_critical_section(flags); } else #endif -#if CONFIG_IEEE802154_IND_IRQRESERVE > 0 - /* If this is a meta-data structure pre-allocated for interrupts, +#if CONFIG_IEEE802154_PRIMITIVE_IRQRESERVE > 0 + /* If this is a primitive structure pre-allocated for interrupts, * then put it back in the correct free list. */ - if (priv->pool == POOL_IND_IRQ) + if (priv->pool == POOL_PRIMITIVE_IRQ) { /* Make sure we avoid concurrent access to the free * list from interrupt handlers. */ flags = enter_critical_section(); - priv->flink = g_indfree_irq; - g_indfree_irq = priv; + priv->flink = g_primfree_irq; + g_primfree_irq = priv; leave_critical_section(flags); } else @@ -415,8 +403,10 @@ void ieee802154_ind_free(FAR struct ieee802154_data_ind_s *ind) { /* Otherwise, deallocate it. */ - DEBUGASSERT(priv->pool == POOL_IND_DYNAMIC); + DEBUGASSERT(priv->pool == POOL_PRIMITIVE_DYNAMIC); sched_kfree(priv); } #endif + + wlinfo("Primitive freed: %p\n", prim); } diff --git a/wireless/ieee802154/mac802154.c b/wireless/ieee802154/mac802154.c index c0221c04d836d1bd9004bef66eef2acd73310d32..552af9282f6e94996d5b35019264cbeb75d4d47d 100644 --- a/wireless/ieee802154/mac802154.c +++ b/wireless/ieee802154/mac802154.c @@ -57,7 +57,6 @@ #include #include "mac802154.h" -#include "mac802154_notif.h" #include "mac802154_internal.h" #include "mac802154_assoc.h" #include "mac802154_scan.h" @@ -100,6 +99,8 @@ static void mac802154_rxdataframe(FAR struct ieee802154_privmac_s *priv, static void mac802154_rxbeaconframe(FAR struct ieee802154_privmac_s *priv, FAR struct ieee802154_data_ind_s *ind); +static void mac802154_notify_worker(FAR void *arg); + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -122,6 +123,7 @@ static void mac802154_resetqueues(FAR struct ieee802154_privmac_s *priv) sq_init(&priv->gts_queue); sq_init(&priv->indirect_queue); sq_init(&priv->dataind_queue); + sq_init(&priv->primitive_queue); /* Initialize the tx descriptor allocation pool */ @@ -132,20 +134,15 @@ static void mac802154_resetqueues(FAR struct ieee802154_privmac_s *priv) } nxsem_init(&priv->txdesc_sem, 0, CONFIG_MAC802154_NTXDESC); - - /* Initialize the notifcation allocation pool */ - - mac802154_notifpool_init(priv); } /**************************************************************************** * Name: mac802154_txdesc_pool * * Description: - * This function allocates a tx descriptor and the dependent notification (data - * confirmation) from the free list. The notification and tx descriptor will - * be freed seperately, both by the MAC layer either directly, or through - * mac802154_notif_free in the case of the notification. + * This function allocates a tx descriptor and the dependent primitive (data + * confirmation) from the free list. The primitive and tx descriptor must be + * freed seperately. * * Assumptions: * priv MAC struct is locked when calling. @@ -162,7 +159,7 @@ int mac802154_txdesc_alloc(FAR struct ieee802154_privmac_s *priv, bool allow_interrupt) { int ret; - FAR struct ieee802154_notif_s *notif; + FAR struct ieee802154_primitive_s *primitive; /* Try and take a count from the semaphore. If this succeeds, we have * "reserved" the structure, but still need to unlink it from the free list. @@ -213,27 +210,16 @@ int mac802154_txdesc_alloc(FAR struct ieee802154_privmac_s *priv, } /* We have now successfully allocated the tx descriptor. Now we need to allocate - * the notification for the data confirmation that gets passed along with the + * the primitive for the data confirmation that gets passed along with the * tx descriptor. These are allocated together, but not freed together. */ - ret = mac802154_notif_alloc(priv, ¬if, allow_interrupt); - if (ret < 0) - { - /* The mac802154_notif_alloc function follows the same rules as this - * function. If it returns -EINTR, the MAC layer is already released - */ - - /* We need to free the txdesc */ - - mac802154_txdesc_free(priv, *txdesc); - return -EINTR; - } + primitive = ieee802154_primitive_allocate(); (*txdesc)->purgetime = 0; (*txdesc)->retrycount = priv->maxretries; - (*txdesc)->conf = ¬if->u.dataconf; + (*txdesc)->conf = &primitive->u.dataconf; return OK; } @@ -356,6 +342,126 @@ void mac802154_createdatareq(FAR struct ieee802154_privmac_s *priv, priv->cmd_desc = txdesc; } +/**************************************************************************** + * Name: mac802154_notify + * + * Description: + * Queue the primitive in the queue and queue work on the LPWORK + * queue if is not already scheduled. + * + * Assumptions: + * Called with the MAC locked + * + ****************************************************************************/ + +void mac802154_notify(FAR struct ieee802154_privmac_s *priv, + FAR struct ieee802154_primitive_s *primitive) +{ + sq_addlast((FAR sq_entry_t *)primitive, &priv->primitive_queue); + + if (work_available(&priv->notifwork)) + { + work_queue(LPWORK, &priv->notifwork, mac802154_notify_worker, + (FAR void *)priv, 0); + } +} + +/**************************************************************************** + * Name: mac802154_notify_worker + * + * Description: + * Pop each primitive off the queue and call the registered + * callbacks. There is special logic for handling ieee802154_data_ind_s. + * + ****************************************************************************/ + +static void mac802154_notify_worker(FAR void *arg) +{ + FAR struct ieee802154_privmac_s *priv = (FAR struct ieee802154_privmac_s *)arg; + FAR struct mac802154_maccb_s *cb; + FAR struct ieee802154_primitive_s *primitive; + int ret; + + + mac802154_lock(priv, false); + primitive = + (FAR struct ieee802154_primitive_s *)sq_remfirst(&priv->primitive_queue); + mac802154_unlock(priv); + + while (primitive != NULL) + { + /* Data indications are a special case since the frame can only be passed to + * one place. The return value of the notify call is used to accept or reject + * the primitive. In the case of the data indication, there can only be one + * accept. Callbacks are stored in order of there receiver priority ordered + * when the callbacks are bound in mac802154_bind(). + */ + + if (primitive->type == IEEE802154_PRIMITIVE_IND_DATA) + { + bool dispose = true; + + primitive->nclients = 1; + + for (cb = priv->cb; cb != NULL; cb = cb->flink) + { + if (cb->notify != NULL) + { + ret = cb->notify(cb, primitive); + if (ret >= 0) + { + /* The receiver accepted and disposed of the frame and it's + * meta-data. We are done. + */ + + dispose = false; + break; + } + } + } + + if (dispose) + { + iob_free(primitive->u.dataind.frame); + ieee802154_primitive_free(primitive); + } + } + else + { + /* Set the number of clients count so that the primitive resources will be + * preserved until all clients are finished with it. + */ + + primitive->nclients = priv->nclients; + + /* Try to notify every registered MAC client */ + + for (cb = priv->cb; cb != NULL; cb = cb->flink) + { + if (cb->notify != NULL) + { + ret = cb->notify(cb, primitive); + if (ret <= 0) + { + ieee802154_primitive_free(primitive); + } + } + else + { + ieee802154_primitive_free(primitive); + } + } + } + + /* Get the next primitive then loop */ + + mac802154_lock(priv, false); + primitive = + (FAR struct ieee802154_primitive_s *)sq_remfirst(&priv->primitive_queue); + mac802154_unlock(priv); + } +} + /**************************************************************************** * Name: mac802154_updatebeacon * @@ -579,7 +685,7 @@ void mac802154_setupindirect(FAR struct ieee802154_privmac_s *priv, if (work_available(&priv->purge_work)) { - work_queue(MAC802154_WORK, &priv->purge_work, mac802154_purge_worker, + work_queue(HPWORK, &priv->purge_work, mac802154_purge_worker, (FAR void *)priv, ticks); } } @@ -635,8 +741,7 @@ static void mac802154_purge_worker(FAR void *arg) /* Free the IOB, the notification, and the tx descriptor */ iob_free(txdesc->frame); - mac802154_notif_free_locked(priv, - (FAR struct ieee802154_notif_s *)txdesc->conf); + ieee802154_primitive_free((FAR struct ieee802154_primitive_s *)txdesc->conf); mac802154_txdesc_free(priv, txdesc); priv->beaconupdate = true; @@ -646,7 +751,7 @@ static void mac802154_purge_worker(FAR void *arg) { /* Reschedule the transaction for the next timeout */ - work_queue(MAC802154_WORK, &priv->purge_work, mac802154_purge_worker, + work_queue(HPWORK, &priv->purge_work, mac802154_purge_worker, (FAR void *)priv, txdesc->purgetime - clock_systimer()); break; } @@ -740,7 +845,7 @@ static void mac802154_txdone(FAR const struct ieee802154_radiocb_s *radiocb, if (work_available(&priv->tx_work)) { - work_queue(MAC802154_WORK, &priv->tx_work, mac802154_txdone_worker, + work_queue(HPWORK, &priv->tx_work, mac802154_txdone_worker, (FAR void *)priv, 0); } } @@ -760,7 +865,7 @@ static void mac802154_txdone_worker(FAR void *arg) FAR struct ieee802154_privmac_s *priv = (FAR struct ieee802154_privmac_s *)arg; FAR struct ieee802154_txdesc_s *txdesc; - FAR struct ieee802154_notif_s *notif; + FAR struct ieee802154_primitive_s *primitive; /* Get exclusive access to the driver structure. We don't care about any * signals so don't allow interruptions @@ -781,7 +886,7 @@ static void mac802154_txdone_worker(FAR void *arg) * notification structure to make it easier to use. */ - notif =(FAR struct ieee802154_notif_s *)txdesc->conf; + primitive =(FAR struct ieee802154_primitive_s *)txdesc->conf; wlinfo("Tx status: %s\n", IEEE802154_STATUS_STRING[txdesc->conf->status]); @@ -789,13 +894,8 @@ static void mac802154_txdone_worker(FAR void *arg) { case IEEE802154_FRAME_DATA: { - notif->notiftype = IEEE802154_NOTIFY_CONF_DATA; - - /* Release the MAC, call the callback, get exclusive access again */ - - mac802154_unlock(priv) - mac802154_notify(priv, notif); - mac802154_lock(priv, false); + primitive->type = IEEE802154_PRIMITIVE_CONF_DATA; + mac802154_notify(priv, primitive); } break; @@ -858,7 +958,7 @@ static void mac802154_txdone_worker(FAR void *arg) break; default: - mac802154_notif_free_locked(priv, notif); + ieee802154_primitive_free(primitive); break; } } @@ -866,7 +966,7 @@ static void mac802154_txdone_worker(FAR void *arg) default: { - mac802154_notif_free_locked(priv, notif); + ieee802154_primitive_free(primitive); } break; } @@ -922,7 +1022,7 @@ static void mac802154_rxframe(FAR const struct ieee802154_radiocb_s *radiocb, if (work_available(&priv->rx_work)) { - work_queue(MAC802154_WORK, &priv->rx_work, mac802154_rxframe_worker, + work_queue(HPWORK, &priv->rx_work, mac802154_rxframe_worker, (FAR void *)priv, 0); } } @@ -956,7 +1056,10 @@ static void mac802154_rxframe_worker(FAR void *arg) mac802154_lock(priv, false); - /* Pop the iob from the head of the frame list for processing */ + /* Pop the data indication from the head of the frame list for processing + * Note: dataind_queue contains ieee802154_primitive_s which is safe to + * cast directly to a data indication. + */ ind = (FAR struct ieee802154_data_ind_s *)sq_remfirst(&priv->dataind_queue); @@ -1040,6 +1143,16 @@ static void mac802154_rxframe_worker(FAR void *arg) } } + /* If the MAC is in promiscuous mode, just pass everything to the next layer + * assuming it is data + */ + + if (priv->promisc) + { + mac802154_notify(priv, (FAR struct ieee802154_primitive_s *)ind); + continue; + } + ftype = (*frame_ctrl & IEEE802154_FRAMECTRL_FTYPE) >> IEEE802154_FRAMECTRL_SHIFT_FTYPE; @@ -1073,7 +1186,7 @@ static void mac802154_rxframe_worker(FAR void *arg) break; case IEEE802154_CMD_DISASSOC_NOT: - wlinfo("Disassoc notif received\n"); + wlinfo("Disassoc primitive received\n"); break; case IEEE802154_CMD_DATA_REQ: @@ -1082,11 +1195,11 @@ static void mac802154_rxframe_worker(FAR void *arg) break; case IEEE802154_CMD_PANID_CONF_NOT: - wlinfo("PAN ID Conflict notif received\n"); + wlinfo("PAN ID Conflict primitive received\n"); break; case IEEE802154_CMD_ORPHAN_NOT: - wlinfo("Orphan notif received\n"); + wlinfo("Orphan primitive received\n"); break; case IEEE802154_CMD_BEACON_REQ: @@ -1104,7 +1217,7 @@ static void mac802154_rxframe_worker(FAR void *arg) /* Free the data indication struct from the pool */ - ieee802154_ind_free(ind); + ieee802154_primitive_free((FAR struct ieee802154_primitive_s *)ind); } break; @@ -1112,7 +1225,7 @@ static void mac802154_rxframe_worker(FAR void *arg) { wlinfo("Beacon frame received. BSN: 0x%02X\n", ind->dsn); mac802154_rxbeaconframe(priv, ind); - ieee802154_ind_free(ind); + ieee802154_primitive_free((FAR struct ieee802154_primitive_s *)ind); } break; @@ -1123,7 +1236,7 @@ static void mac802154_rxframe_worker(FAR void *arg) */ wlinfo("ACK received\n"); - ieee802154_ind_free(ind); + ieee802154_primitive_free((FAR struct ieee802154_primitive_s *)ind); } break; } @@ -1142,7 +1255,7 @@ static void mac802154_rxframe_worker(FAR void *arg) static void mac802154_rxdataframe(FAR struct ieee802154_privmac_s *priv, FAR struct ieee802154_data_ind_s *ind) { - FAR struct ieee802154_notif_s *notif; + FAR struct ieee802154_primitive_s *primitive; /* Get exclusive access to the MAC */ @@ -1178,46 +1291,46 @@ static void mac802154_rxdataframe(FAR struct ieee802154_privmac_s *priv, { if (!IEEE802154_PANIDCMP(ind->dest.panid, priv->addr.panid)) { - goto notify_with_lock; + mac802154_notify(priv, (FAR struct ieee802154_primitive_s *)ind); } if (ind->dest.mode == IEEE802154_ADDRMODE_SHORT && !IEEE802154_SADDRCMP(ind->dest.saddr, priv->addr.saddr)) { - goto notify_with_lock; + mac802154_notify(priv, (FAR struct ieee802154_primitive_s *)ind); } else if (ind->dest.mode == IEEE802154_ADDRMODE_EXTENDED && !IEEE802154_EADDRCMP(ind->dest.eaddr, priv->addr.eaddr)) { - goto notify_with_lock; + mac802154_notify(priv, (FAR struct ieee802154_primitive_s *)ind); } else { - goto notify_with_lock; + mac802154_notify(priv, (FAR struct ieee802154_primitive_s *)ind); } } /* If this was our extracted data, the source addressing field can only - * be NONE if we are trying to extract data from the PAN coordinator. - * A PAN coordinator shouldn't be sending us a frame if it wasn't - * our extracted data. Therefore just assume if the address mode is set - * to NONE, we process it as our extracted frame - */ + * be NONE if we are trying to extract data from the PAN coordinator. + * A PAN coordinator shouldn't be sending us a frame if it wasn't + * our extracted data. Therefore just assume if the address mode is set + * to NONE, we process it as our extracted frame + */ if (ind->src.mode != priv->cmd_desc->destaddr.mode) { - goto notify_with_lock; + mac802154_notify(priv, (FAR struct ieee802154_primitive_s *)ind); } if (ind->src.mode == IEEE802154_ADDRMODE_SHORT && !IEEE802154_SADDRCMP(ind->src.saddr, priv->cmd_desc->destaddr.saddr)) { - goto notify_with_lock; + mac802154_notify(priv, (FAR struct ieee802154_primitive_s *)ind); } else if (ind->src.mode == IEEE802154_ADDRMODE_EXTENDED && !IEEE802154_EADDRCMP(ind->src.eaddr, priv->cmd_desc->destaddr.eaddr)) { - goto notify_with_lock; + mac802154_notify(priv, (FAR struct ieee802154_primitive_s *)ind); } /* If we've gotten this far, the frame is our extracted data. Cancel the @@ -1231,20 +1344,19 @@ static void mac802154_rxdataframe(FAR struct ieee802154_privmac_s *priv, * MLME-POLL.confirm primitive with a status of NO_DATA. [1] pg. 111 */ - mac802154_notif_alloc(priv, ¬if, false); + primitive = ieee802154_primitive_allocate(); if (priv->curr_op == MAC802154_OP_POLL) { - notif->notiftype = IEEE802154_NOTIFY_CONF_POLL; + primitive->type = IEEE802154_PRIMITIVE_CONF_POLL; if (ind->frame->io_offset == ind->frame->io_len) { - ieee802154_ind_free(ind); - notif->u.pollconf.status = IEEE802154_STATUS_NO_DATA; + primitive->u.pollconf.status = IEEE802154_STATUS_NO_DATA; } else { - notif->u.pollconf.status = IEEE802154_STATUS_SUCCESS; + primitive->u.pollconf.status = IEEE802154_STATUS_SUCCESS; } } else if (priv->curr_op == MAC802154_OP_ASSOC) @@ -1253,8 +1365,8 @@ static void mac802154_rxdataframe(FAR struct ieee802154_privmac_s *priv, * association request, we assume it means there wasn't any data. */ - notif->notiftype = IEEE802154_NOTIFY_CONF_ASSOC; - notif->u.assocconf.status = IEEE802154_STATUS_NO_DATA; + primitive->type = IEEE802154_PRIMITIVE_CONF_ASSOC; + primitive->u.assocconf.status = IEEE802154_STATUS_NO_DATA; } /* We are no longer performing the association operation */ @@ -1263,63 +1375,27 @@ static void mac802154_rxdataframe(FAR struct ieee802154_privmac_s *priv, priv->cmd_desc = NULL; mac802154_givesem(&priv->opsem); - /* Release the MAC */ + /* Release the MAC and notify the next highest layer */ - mac802154_unlock(priv) - mac802154_notify(priv, notif); + mac802154_notify(priv, primitive); /* If there was data, pass it along */ if (ind->frame->io_len > ind->frame->io_offset) { - goto notify_without_lock; + mac802154_notify(priv, (FAR struct ieee802154_primitive_s *)ind); + } + else + { + ieee802154_primitive_free((FAR struct ieee802154_primitive_s *)ind); } } else { - FAR struct mac802154_maccb_s *cb; - -notify_with_lock: - - mac802154_unlock(priv) - -notify_without_lock: - - /* If there are registered MCPS callback receivers registered, - * then forward the frame in priority order. If there are no - * registered receivers or if none of the receivers accept the - * data frame then drop the frame. - */ - - for (cb = priv->cb; cb != NULL; cb = cb->flink) - { - int ret; - - /* Does this MAC client want frames? */ - - if (cb->rxframe != NULL) - { - /* Yes.. Offer this frame to the receiver */ - - ret = cb->rxframe(cb, ind); - if (ret >= 0) - { - /* The receiver accepted and disposed of the frame and - * its metadata. We are done. - */ - - return; - } - } - } - - /* We get here if the there are no registered receivers or if - * all of the registered receivers declined the frame. - * Free the data indication struct from the pool - */ - - ieee802154_ind_free(ind); + mac802154_notify(priv, (FAR struct ieee802154_primitive_s *)ind); } + + mac802154_unlock(priv) } /**************************************************************************** @@ -1554,7 +1630,7 @@ static void mac802154_sfevent(FAR const struct ieee802154_radiocb_s *radiocb, * Function called from the generic RX Frame worker to parse and handle the * reception of a beacon frame. * - * Assumptions: MAC is locked + * Assumptions: MAC is unlocked * ****************************************************************************/ @@ -1562,7 +1638,7 @@ static void mac802154_rxbeaconframe(FAR struct ieee802154_privmac_s *priv, FAR struct ieee802154_data_ind_s *ind) { FAR struct ieee802154_txdesc_s *respdesc; - FAR struct ieee802154_notif_s *notif; + FAR struct ieee802154_primitive_s *primitive; FAR struct ieee802154_beacon_ind_s *beacon; FAR struct iob_s *iob = ind->frame; uint8_t ngtsdesc; @@ -1571,15 +1647,15 @@ static void mac802154_rxbeaconframe(FAR struct ieee802154_privmac_s *priv, bool pending_eaddr = false; int i; - /* Even though we may not use the notification, we use a notification to - * hold all the parsed beacon information. Freeing the notification is quick, - * so it's worth saving a copy (If you were to parse all the info in locally, - * you would have to copy the data over in the case that you actually need - * to notify the next highest layer) + /* Even though we may not use the primitive, we allocate one to hold all the + * parsed beacon information. Freeing the primitive is quick, so it's worth + * worth saving a copy (If you were to parse all the info in locally, you + * would have to copy the data over in the case that you actually need to + * notify the next highest layer) */ - mac802154_notif_alloc(priv, ¬if, false); - beacon = ¬if->u.beaconind; + primitive = ieee802154_primitive_allocate(); + beacon = &primitive->u.beaconind; /* Make sure there is another 2 bytes to process */ @@ -1731,6 +1807,8 @@ static void mac802154_rxbeaconframe(FAR struct ieee802154_privmac_s *priv, /* At this point, we have extracted all relevant info from the incoming frame */ + mac802154_lock(priv, false); + if (priv->curr_op == MAC802154_OP_SCAN) { /* Check to see if we already have a frame from this coordinator */ @@ -1750,7 +1828,8 @@ static void mac802154_rxbeaconframe(FAR struct ieee802154_privmac_s *priv, /* The beacon is the same as another, so discard it */ - mac802154_notif_free_locked(priv, notif); + ieee802154_primitive_free(primitive); + mac802154_unlock(priv); return; } @@ -1829,11 +1908,7 @@ static void mac802154_rxbeaconframe(FAR struct ieee802154_privmac_s *priv, if (beacon->payloadlength > 0) { - /* Unlock the MAC, notify, then lock again */ - - mac802154_unlock(priv) - mac802154_notify(priv, notif); - mac802154_lock(priv, false); + mac802154_notify(priv, primitive); } /* If we have data pending for us, attempt to extract it. If for some @@ -1881,12 +1956,13 @@ static void mac802154_rxbeaconframe(FAR struct ieee802154_privmac_s *priv, priv->radio->txnotify(priv->radio, false); } - /* If there was a beacon payload, we used the notification, so - * return here to make sure we don't free the notification. + /* If there was a beacon payload, we used the primitive, so + * return here to make sure we don't free the primitive. */ if (beacon->payloadlength > 0) { + mac802154_unlock(priv); return; } } @@ -1897,22 +1973,20 @@ static void mac802154_rxbeaconframe(FAR struct ieee802154_privmac_s *priv, * by issuing the MLME-BEACON-NOTIFY.indication primitive. [1] pg. 38 */ - /* Unlock the MAC, notify, then lock again */ - - mac802154_unlock(priv) - mac802154_notify(priv, notif); - mac802154_lock(priv, false); - return; /* Return so that we don't free the notificaiton */ + mac802154_notify(priv, primitive); + mac802154_unlock(priv); + return; /* Return so that we don't free the primitive */ } } } - mac802154_notif_free_locked(priv, notif); + mac802154_unlock(priv); + ieee802154_primitive_free(primitive); return; errout: wlwarn("Received beacon with bad format\n"); - mac802154_notif_free_locked(priv, notif); + ieee802154_primitive_free(primitive); } /**************************************************************************** @@ -1990,7 +2064,7 @@ MACHANDLE mac802154_create(FAR struct ieee802154_radio_s *radiodev) /* Initialize our various data pools */ - ieee802154_indpool_initialize(); + ieee802154_primitivepool_initialize(); mac802154_resetqueues(mac); mac802154_req_reset((MACHANDLE)mac, true); diff --git a/wireless/ieee802154/mac802154.h b/wireless/ieee802154/mac802154.h index d1f3a6b63f69dea624de9a36aacc1ad7e156811e..ddd125a6e89026a0d6c30745e0b254f2b1010c97 100644 --- a/wireless/ieee802154/mac802154.h +++ b/wireless/ieee802154/mac802154.h @@ -68,12 +68,18 @@ struct mac802154_maccb_s FAR struct mac802154_maccb_s *flink; /* Implements a singly linked list */ uint8_t prio; /* RX frame callback priority */ - /* Callback methods */ - - CODE void (*notify)(FAR struct mac802154_maccb_s *maccb, - FAR struct ieee802154_notif_s *notif); - CODE int (*rxframe)(FAR struct mac802154_maccb_s *maccb, - FAR struct ieee802154_data_ind_s *ind); + /* Callback for various MLME or MCPS service events. Return value represents + * whether the callback accepts the primitive. >= 0 means the callback has + * accepted the primitive and is responsible for calling + * ieee802154_primitive_free(). In the case of DATA.indication primitive, only + * one callback can accept the frame. The callbacks are stored in order of + * receiver priority defined by the 'prio' field above. All other + * notifications are offered to all callbacks and all can accept and free + * separately since the primitive will not be freed until the nclients count + * reaches 0. */ + + CODE int (*notify)(FAR struct mac802154_maccb_s *maccb, + FAR struct ieee802154_primitive_s *primitive); }; /**************************************************************************** @@ -358,19 +364,6 @@ int mac802154_resp_associate(MACHANDLE mac, int mac802154_resp_orphan(MACHANDLE mac, FAR struct ieee802154_orphan_resp_s *resp); -/**************************************************************************** - * Name: mac802154_notif_free - * - * Description: - * When the MAC calls the registered callback, it passes a reference - * to a mac802154_notify_s structure. This structure needs to be freed - * after the callback handler is done using it. - * - ****************************************************************************/ - -void mac802154_notif_free(MACHANDLE mac, - FAR struct ieee802154_notif_s *notif); - #undef EXTERN #ifdef __cplusplus } diff --git a/wireless/ieee802154/mac802154_assoc.c b/wireless/ieee802154/mac802154_assoc.c index b72ba08556fb188ae06d68ef5f1554597055ecb5..56d32a9a3497e9ac525edd6eb1b8290963296c02 100644 --- a/wireless/ieee802154/mac802154_assoc.c +++ b/wireless/ieee802154/mac802154_assoc.c @@ -111,12 +111,12 @@ int mac802154_req_associate(MACHANDLE mac, /* Get exclusive access to the MAC */ - ret = mac802154_lock(priv, true); - if (ret < 0) - { - mac802154_givesem(&priv->opsem); - return ret; - } + ret = mac802154_lock(priv, true); + if (ret < 0) + { + mac802154_givesem(&priv->opsem); + return ret; + } /* Set the channel and channel page of the PHY layer */ @@ -452,8 +452,8 @@ void mac802154_txdone_assocreq(FAR struct ieee802154_privmac_s *priv, { enum ieee802154_status_e status; FAR struct ieee802154_txdesc_s *respdesc; - FAR struct ieee802154_notif_s *notif = - (FAR struct ieee802154_notif_s *)txdesc->conf; + FAR struct ieee802154_primitive_s *primitive = + (FAR struct ieee802154_primitive_s *)txdesc->conf; if(txdesc->conf->status != IEEE802154_STATUS_SUCCESS) { @@ -463,23 +463,23 @@ void mac802154_txdone_assocreq(FAR struct ieee802154_privmac_s *priv, */ /* We can actually high-jack the data conf notification since it - * is allocated as an ieee80215_notif_s anyway. Before we overwrite + * is allocated as an ieee80215_primitive_s anyway. Before we overwrite * any data though, we need to get the status from the data * confirmation as that is the method we use to get the reason * why the tx failed from the radio layer. */ status = txdesc->conf->status; - notif->notiftype = IEEE802154_NOTIFY_CONF_ASSOC; + primitive->type = IEEE802154_PRIMITIVE_CONF_ASSOC; - notif->u.assocconf.status = status; + primitive->u.assocconf.status = status; /* The short device address allocated by the coordinator on * successful association. This parameter will be equal to 0xffff * if the association attempt was unsuccessful. [1] pg. 81 */ - IEEE802154_SADDRCOPY(notif->u.assocconf.saddr, &IEEE802154_SADDR_UNSPEC); + IEEE802154_SADDRCOPY(primitive->u.assocconf.saddr, &IEEE802154_SADDR_UNSPEC); /* We are now done the operation, unlock the semaphore */ @@ -490,9 +490,7 @@ void mac802154_txdone_assocreq(FAR struct ieee802154_privmac_s *priv, /* Release the MAC, call the callback, get exclusive access again */ - mac802154_unlock(priv) - mac802154_notify(priv, notif); - mac802154_lock(priv, false); + mac802154_notify(priv, primitive); } else { @@ -564,7 +562,7 @@ void mac802154_txdone_assocreq(FAR struct ieee802154_privmac_s *priv, /* Deallocate the data conf notification as it is no longer needed. */ - mac802154_notif_free_locked(priv, notif); + ieee802154_primitive_free(primitive); } } @@ -585,8 +583,8 @@ void mac802154_txdone_datareq_assoc(FAR struct ieee802154_privmac_s *priv, FAR struct ieee802154_txdesc_s *txdesc) { enum ieee802154_status_e status; - FAR struct ieee802154_notif_s *notif = - (FAR struct ieee802154_notif_s *)txdesc->conf; + FAR struct ieee802154_primitive_s *primitive = + (FAR struct ieee802154_primitive_s *)txdesc->conf; /* If the data request failed to be sent, notify the next layer * that the association has failed. @@ -596,12 +594,12 @@ void mac802154_txdone_datareq_assoc(FAR struct ieee802154_privmac_s *priv, * pending at the coordinator. [1] pg. 43 */ - if (notif->u.dataconf.status != IEEE802154_STATUS_SUCCESS || + if (primitive->u.dataconf.status != IEEE802154_STATUS_SUCCESS || txdesc->framepending == 0) { - if (notif->u.dataconf.status != IEEE802154_STATUS_SUCCESS) + if (primitive->u.dataconf.status != IEEE802154_STATUS_SUCCESS) { - status = notif->u.dataconf.status; + status = primitive->u.dataconf.status; } else { @@ -615,15 +613,15 @@ void mac802154_txdone_datareq_assoc(FAR struct ieee802154_privmac_s *priv, status = IEEE802154_STATUS_NO_DATA; } - notif->notiftype = IEEE802154_NOTIFY_CONF_ASSOC; - notif->u.assocconf.status = status; + primitive->type = IEEE802154_PRIMITIVE_CONF_ASSOC; + primitive->u.assocconf.status = status; /* The short device address allocated by the coordinator on * successful association. This parameter will be equal to 0xffff * if the association attempt was unsuccessful. [1] pg. 81 */ - IEEE802154_SADDRCOPY(notif->u.assocconf.saddr, &IEEE802154_SADDR_UNSPEC); + IEEE802154_SADDRCOPY(primitive->u.assocconf.saddr, &IEEE802154_SADDR_UNSPEC); /* We are now done the operation, and can release the command */ @@ -631,11 +629,7 @@ void mac802154_txdone_datareq_assoc(FAR struct ieee802154_privmac_s *priv, priv->cmd_desc = NULL; mac802154_givesem(&priv->opsem); - /* Release the MAC, call the callback, get exclusive access again */ - - mac802154_unlock(priv) - mac802154_notify(priv, notif); - mac802154_lock(priv, false); + mac802154_notify(priv, primitive); } else { @@ -672,7 +666,7 @@ void mac802154_txdone_datareq_assoc(FAR struct ieee802154_privmac_s *priv, /* Deallocate the data conf notification as it is no longer needed. */ - mac802154_notif_free_locked(priv, notif); + ieee802154_primitive_free(primitive); } } @@ -690,17 +684,13 @@ void mac802154_rx_assocreq(FAR struct ieee802154_privmac_s *priv, FAR struct ieee802154_data_ind_s *ind) { FAR struct iob_s *frame = ind->frame; - FAR struct ieee802154_notif_s *notif; + FAR struct ieee802154_primitive_s *primitive; uint8_t cap; - /* Get exclusive access to the MAC */ - - mac802154_lock(priv, false); - /* Allocate a notification to pass to the next highest layer */ - mac802154_notif_alloc(priv, ¬if, false); - notif->notiftype = IEEE802154_NOTIFY_IND_ASSOC; + primitive = ieee802154_primitive_allocate(); + primitive->type = IEEE802154_PRIMITIVE_IND_ASSOC; /* Association Requests should always be sent from a device with source * addressing mode set to extended mode. Throw out any request received @@ -709,43 +699,39 @@ void mac802154_rx_assocreq(FAR struct ieee802154_privmac_s *priv, if (ind->src.mode != IEEE802154_ADDRMODE_EXTENDED) { - goto errout_with_sem; + return; } /* Copy the extended address of the requesting device */ - IEEE802154_EADDRCOPY(notif->u.assocind.devaddr, ind->src.eaddr); + IEEE802154_EADDRCOPY(primitive->u.assocind.devaddr, ind->src.eaddr); /* Copy in the capability information from the frame to the notification */ cap = frame->io_data[frame->io_offset++]; - notif->u.assocind.capabilities.devtype = + primitive->u.assocind.capabilities.devtype = (cap >> IEEE802154_CAPABILITY_SHIFT_DEVTYPE) & 0x01; - notif->u.assocind.capabilities.powersource = + primitive->u.assocind.capabilities.powersource = (cap >> IEEE802154_CAPABILITY_SHIFT_PWRSRC) & 0x01; - notif->u.assocind.capabilities.rxonidle = + primitive->u.assocind.capabilities.rxonidle = (cap >> IEEE802154_CAPABILITY_SHIFT_RXONIDLE) & 0x01; - notif->u.assocind.capabilities.security = + primitive->u.assocind.capabilities.security = (cap >> IEEE802154_CAPABILITY_SHIFT_SECURITY) & 0x01; - notif->u.assocind.capabilities.allocaddr = + primitive->u.assocind.capabilities.allocaddr = (cap >> IEEE802154_CAPABILITY_SHIFT_ALLOCADDR) & 0x01; #ifdef CONFIG_IEEE802154_SECURITY #error Missing security logic #endif - /* Unlock the MAC */ + /* Get exclusive access to the MAC */ - mac802154_unlock(priv) + mac802154_lock(priv, false); /* Notify the next highest layer of the association status */ - mac802154_notify(priv, notif); - return; - -errout_with_sem: + mac802154_notify(priv, primitive); mac802154_unlock(priv) - return; } /**************************************************************************** @@ -761,7 +747,7 @@ void mac802154_rx_assocresp(FAR struct ieee802154_privmac_s *priv, FAR struct ieee802154_data_ind_s *ind) { FAR struct iob_s *iob = ind->frame; - FAR struct ieee802154_notif_s *notif; + FAR struct ieee802154_primitive_s *primitive; /* Check if we are performing an Association operation, if not, we will just * ignore the frame. @@ -789,14 +775,14 @@ void mac802154_rx_assocresp(FAR struct ieee802154_privmac_s *priv, mac802154_timercancel(priv); - /* Get exclusive access to the MAC */ + /* Allocate a notification to pass to the next highest layer */ - mac802154_lock(priv, false); + primitive = ieee802154_primitive_allocate(); + primitive->type = IEEE802154_PRIMITIVE_CONF_ASSOC; - /* Allocate a notification to pass to the next highest layer */ + /* Get exclusive access to the MAC */ - mac802154_notif_alloc(priv, ¬if, false); - notif->notiftype = IEEE802154_NOTIFY_CONF_ASSOC; + mac802154_lock(priv, false); /* Parse the short address from the response */ @@ -822,9 +808,9 @@ void mac802154_rx_assocresp(FAR struct ieee802154_privmac_s *priv, /* Parse the status from the response */ - notif->u.assocconf.status = iob->io_data[iob->io_offset++]; + primitive->u.assocconf.status = iob->io_data[iob->io_offset++]; - if (notif->u.assocconf.status == IEEE802154_STATUS_SUCCESS) + if (primitive->u.assocconf.status == IEEE802154_STATUS_SUCCESS) { priv->isassoc = true; } @@ -833,7 +819,7 @@ void mac802154_rx_assocresp(FAR struct ieee802154_privmac_s *priv, priv->isassoc = false; } - IEEE802154_SADDRCOPY(notif->u.assocconf.saddr, priv->addr.saddr); + IEEE802154_SADDRCOPY(primitive->u.assocconf.saddr, priv->addr.saddr); /* We are no longer performing the association operation */ @@ -842,13 +828,10 @@ void mac802154_rx_assocresp(FAR struct ieee802154_privmac_s *priv, mac802154_givesem(&priv->opsem); mac802154_rxdisable(priv); - /* Unlock the MAC */ - - mac802154_unlock(priv) - /* Notify the next highest layer of the association status */ - mac802154_notify(priv, notif); + mac802154_notify(priv, primitive); + mac802154_unlock(priv) } /**************************************************************************** @@ -867,7 +850,7 @@ void mac802154_rx_assocresp(FAR struct ieee802154_privmac_s *priv, static void mac802154_assoctimeout(FAR void *arg) { FAR struct ieee802154_privmac_s *priv = (FAR struct ieee802154_privmac_s *)arg; - FAR struct ieee802154_notif_s *notif; + FAR struct ieee802154_primitive_s *primitive; /* If there is work scheduled for the rxframe_worker, we want to reschedule * this work, so that we make sure if the frame we were waiting for was just @@ -876,7 +859,7 @@ static void mac802154_assoctimeout(FAR void *arg) if (!work_available(&priv->rx_work)) { - work_queue(MAC802154_WORK, &priv->timer_work, mac802154_assoctimeout, priv, 0); + work_queue(HPWORK, &priv->timer_work, mac802154_assoctimeout, priv, 0); return; } @@ -893,8 +876,11 @@ static void mac802154_assoctimeout(FAR void *arg) * Don't allow EINTR to interrupt. */ - mac802154_lock(priv, false); - mac802154_notif_alloc(priv, ¬if, false); + primitive = ieee802154_primitive_allocate(); + primitive->type = IEEE802154_PRIMITIVE_CONF_ASSOC; + + primitive->u.assocconf.status = IEEE802154_STATUS_NO_DATA; + IEEE802154_SADDRCOPY(primitive->u.assocconf.saddr, &IEEE802154_SADDR_UNSPEC); /* We are no longer performing the association operation */ @@ -903,13 +889,7 @@ static void mac802154_assoctimeout(FAR void *arg) mac802154_givesem(&priv->opsem); mac802154_rxdisable(priv); - /* Release the MAC */ - + mac802154_lock(priv, false); + mac802154_notify(priv, primitive); mac802154_unlock(priv) - - notif->notiftype = IEEE802154_NOTIFY_CONF_ASSOC; - notif->u.assocconf.status = IEEE802154_STATUS_NO_DATA; - IEEE802154_SADDRCOPY(notif->u.assocconf.saddr, &IEEE802154_SADDR_UNSPEC); - - mac802154_notify(priv, notif); } diff --git a/wireless/ieee802154/mac802154_device.c b/wireless/ieee802154/mac802154_device.c index c5dc2b4e28c2082a7909191d1a214d6f5c6af060..3ab60e4a08f1e85feaa5c8d57c2ed1db61af31aa 100644 --- a/wireless/ieee802154/mac802154_device.c +++ b/wireless/ieee802154/mac802154_device.c @@ -99,11 +99,10 @@ struct mac802154_chardevice_s /* Hold a list of events */ - bool enableevents : 1; /* Are events enabled? */ - bool geteventpending : 1; /* Is there a get event using the semaphore? */ - sem_t geteventsem; /* Signaling semaphore for waiting get event */ - FAR struct ieee802154_notif_s *event_head; - FAR struct ieee802154_notif_s *event_tail; + bool enableevents : 1; /* Are events enabled? */ + bool geteventpending : 1; /* Is there a get event using the semaphore? */ + sem_t geteventsem; /* Signaling semaphore for waiting get event */ + sq_queue_t primitive_queue; /* For holding primitives to pass along */ /* The following is a singly linked list of open references to the * MAC device. @@ -136,15 +135,10 @@ struct mac802154_chardevice_s static inline int mac802154dev_takesem(sem_t *sem); #define mac802154dev_givesem(s) nxsem_post(s); -static inline void mac802154dev_pushevent(FAR struct mac802154_chardevice_s *dev, - FAR struct ieee802154_notif_s *notif); -static inline FAR struct ieee802154_notif_s * - mac802154dev_popevent(FAR struct mac802154_chardevice_s *dev); - -static void mac802154dev_notify(FAR struct mac802154_maccb_s *maccb, - FAR struct ieee802154_notif_s *notif); -static int mac802154dev_rxframe(FAR struct mac802154_maccb_s *maccb, - FAR struct ieee802154_data_ind_s *ind); +static int mac802154dev_notify(FAR struct mac802154_maccb_s *maccb, + FAR struct ieee802154_primitive_s *primitive); +static int mac802154dev_rxframe(FAR struct mac802154_chardevice_s *dev, + FAR struct ieee802154_data_ind_s *ind); static int mac802154dev_open(FAR struct file *filep); static int mac802154dev_close(FAR struct file *filep); @@ -203,63 +197,6 @@ static inline int mac802154dev_takesem(sem_t *sem) return ret; } -/**************************************************************************** - * Name: mac802154dev_pushevent - * - * Description: - * Push event onto the event queue - * - * Assumptions: - * Called with the char device struct locked. - * - ****************************************************************************/ - -static inline void mac802154dev_pushevent(FAR struct mac802154_chardevice_s *dev, - FAR struct ieee802154_notif_s *notif) -{ - notif->flink = NULL; - if (!dev->event_head) - { - dev->event_head = notif; - dev->event_tail = notif; - } - else - { - dev->event_tail->flink = notif; - dev->event_tail = notif; - } -} - -/**************************************************************************** - * Name: mac802154dev_popevent - * - * Description: - * Pop an event off of the event queue - * - * Assumptions: - * Called with the char device struct locked. - * - ****************************************************************************/ - -static inline FAR struct ieee802154_notif_s * - mac802154dev_popevent(FAR struct mac802154_chardevice_s *dev) -{ - FAR struct ieee802154_notif_s *notif = dev->event_head; - - if (notif) - { - dev->event_head = notif->flink; - if (!dev->event_head) - { - dev->event_head = NULL; - } - - notif->flink = NULL; - } - - return notif; -} - /**************************************************************************** * Name: mac802154dev_open * @@ -408,13 +345,16 @@ static int mac802154dev_close(FAR struct file *filep) if (dev->md_open) { - FAR struct ieee802154_notif_s *notif; + FAR struct ieee802154_primitive_s *primitive; + + primitive = + (FAR struct ieee802154_primitive_s *)sq_remfirst(&dev->primitive_queue); - while (dev->event_head != NULL) + while (primitive) { - notif = mac802154dev_popevent(dev); - DEBUGASSERT(notif != NULL); - mac802154_notif_free(dev->md_mac, notif); + ieee802154_primitive_free(primitive); + primitive = + (FAR struct ieee802154_primitive_s *)sq_remfirst(&dev->primitive_queue); } } @@ -440,6 +380,7 @@ static ssize_t mac802154dev_read(FAR struct file *filep, FAR char *buffer, FAR struct mac802154_chardevice_s *dev; FAR struct mac802154dev_rxframe_s *rx; FAR struct ieee802154_data_ind_s *ind; + struct ieee802154_get_req_s req; int ret; DEBUGASSERT(filep && filep->f_inode); @@ -513,12 +454,36 @@ static ssize_t mac802154dev_read(FAR struct file *filep, FAR char *buffer, */ } - rx->length = (ind->frame->io_len - ind->frame->io_offset); + /* Check if the MAC layer is in promiscuous mode. If it is, pass the entire + * frame, including IEEE 802.15.4 header and checksum by assuming the frame + * starts at the beginning of the IOB and goes 2 past the length to account + * for the FCS that the radio driver "removes" + */ - /* Copy the data from the IOB to the user supplied struct */ + req.attr = IEEE802154_ATTR_MAC_PROMISCUOUS_MODE; - memcpy(&rx->payload[0], &ind->frame->io_data[ind->frame->io_offset], - rx->length); + ret = mac802154_ioctl(dev->md_mac, MAC802154IOC_MLME_GET_REQUEST, + (unsigned long)&req); + + if (ret == 0 && req.attrval.mac.promisc_mode) + { + rx->length = ind->frame->io_len + 2; + rx->offset = ind->frame->io_offset; + + /* Copy the entire frame from the IOB to the user supplied struct */ + + memcpy(&rx->payload[0], &ind->frame->io_data[0], rx->length); + } + else + { + rx->length = (ind->frame->io_len - ind->frame->io_offset); + rx->offset = 0; + + /* Copy just the payload from the IOB to the user supplied struct */ + + memcpy(&rx->payload[0], &ind->frame->io_data[ind->frame->io_offset], + rx->length); + } memcpy(&rx->meta, ind, sizeof(struct ieee802154_data_ind_s)); @@ -527,9 +492,13 @@ static ssize_t mac802154dev_read(FAR struct file *filep, FAR char *buffer, rx->meta.flink = NULL; rx->meta.frame = NULL; + /* Free the IOB */ + + iob_free(ind->frame); + /* Deallocate the data indication */ - ieee802154_ind_free(ind); + ieee802154_primitive_free((FAR struct ieee802154_primitive_s *)ind); return OK; } @@ -666,25 +635,26 @@ static int mac802154dev_ioctl(FAR struct file *filep, int cmd, case MAC802154IOC_GET_EVENT: { - FAR struct ieee802154_notif_s *notif; + FAR struct ieee802154_primitive_s *primitive; while (1) { /* Try popping an event off the queue */ - notif = mac802154dev_popevent(dev); + primitive = (FAR struct ieee802154_primitive_s *) + sq_remfirst(&dev->primitive_queue); /* If there was an event to pop off, copy it into the user data and * free it from the MAC layer's memory. */ - if (notif != NULL) + if (primitive != NULL) { - memcpy(&macarg->notif, notif, sizeof(struct ieee802154_notif_s)); + memcpy(&macarg->primitive, primitive, sizeof(struct ieee802154_primitive_s)); /* Free the notification */ - mac802154_notif_free(dev->md_mac, notif); + ieee802154_primitive_free(primitive); ret = OK; break; } @@ -750,8 +720,8 @@ static int mac802154dev_ioctl(FAR struct file *filep, int cmd, return ret; } -static void mac802154dev_notify(FAR struct mac802154_maccb_s *maccb, - FAR struct ieee802154_notif_s *notif) +static int mac802154dev_notify(FAR struct mac802154_maccb_s *maccb, + FAR struct ieee802154_primitive_s *primitive) { FAR struct mac802154dev_callback_s *cb = (FAR struct mac802154dev_callback_s *)maccb; @@ -760,10 +730,12 @@ static void mac802154dev_notify(FAR struct mac802154_maccb_s *maccb, DEBUGASSERT(cb != NULL && cb->mc_priv != NULL); dev = cb->mc_priv; - /* Get exclusive access to the driver structure. We don't care about any - * signals so if we see one, just go back to trying to get access again */ + /* Handle the special case for data indications or "incoming frames" */ - while (mac802154dev_takesem(&dev->md_exclsem) != 0); + if (primitive->type == IEEE802154_PRIMITIVE_IND_DATA) + { + return mac802154dev_rxframe(dev, &primitive->u.dataind); + } /* If there is a registered notification receiver, queue the event and signal * the receiver. Events should be popped from the queue from the application @@ -773,7 +745,13 @@ static void mac802154dev_notify(FAR struct mac802154_maccb_s *maccb, if (dev->enableevents && (dev->md_open != NULL || dev->md_notify_registered)) { - mac802154dev_pushevent(dev, notif); + /* Get exclusive access to the driver structure. We don't care about any + * signals so if we see one, just go back to trying to get access again */ + + while (mac802154dev_takesem(&dev->md_exclsem) != 0); + + sq_addlast((FAR sq_entry_t *)primitive, &dev->primitive_queue); + /* Check if there is a read waiting for data */ @@ -791,28 +769,25 @@ static void mac802154dev_notify(FAR struct mac802154_maccb_s *maccb, #ifdef CONFIG_CAN_PASS_STRUCTS union sigval value; - value.sival_int = (int)notif->notiftype; + value.sival_int = (int)primitive->type; (void)nxsig_queue(dev->md_notify_pid, dev->md_notify_signo, value); #else (void)nxsig_queue(dev->md_notify_pid, dev->md_notify_signo, - (FAR void *)notif->notiftype); + (FAR void *)primitive->type); #endif } #endif - } - else - { - /* Just free the event if the driver is closed and there isn't a registered - * signal number. - */ - mac802154_notif_free(dev->md_mac, notif); + mac802154dev_givesem(&dev->md_exclsem); + return OK; } - /* Release the driver */ + /* By returning a negative value, we let the MAC know that we don't want the + * primitive and it will free it for us + */ - mac802154dev_givesem(&dev->md_exclsem); + return -1; } /**************************************************************************** @@ -827,16 +802,9 @@ static void mac802154dev_notify(FAR struct mac802154_maccb_s *maccb, * ****************************************************************************/ -static int mac802154dev_rxframe(FAR struct mac802154_maccb_s *maccb, +static int mac802154dev_rxframe(FAR struct mac802154_chardevice_s *dev, FAR struct ieee802154_data_ind_s *ind) { - FAR struct mac802154dev_callback_s *cb = - (FAR struct mac802154dev_callback_s *)maccb; - FAR struct mac802154_chardevice_s *dev; - - DEBUGASSERT(cb != NULL && cb->mc_priv != NULL); - dev = cb->mc_priv; - /* Get exclusive access to the driver structure. We don't care about any * signals so if we see one, just go back to trying to get access again */ @@ -914,8 +882,7 @@ int mac802154dev_register(MACHANDLE mac, int minor) nxsem_init(&dev->geteventsem, 0, 0); nxsem_setprotocol(&dev->geteventsem, SEM_PRIO_NONE); - dev->event_head = NULL; - dev->event_tail = NULL; + sq_init(&dev->primitive_queue); dev->enableevents = true; dev->md_notify_registered = false; @@ -928,7 +895,6 @@ int mac802154dev_register(MACHANDLE mac, int minor) maccb->flink = NULL; maccb->prio = CONFIG_IEEE802154_MACDEV_RECVRPRIO; maccb->notify = mac802154dev_notify; - maccb->rxframe = mac802154dev_rxframe; /* Bind the callback structure */ diff --git a/wireless/ieee802154/mac802154_getset.c b/wireless/ieee802154/mac802154_getset.c index d6a9ddf8891d44c6eb6254a712e54bd8d6e9465a..5d836842750990a2a3d60aa6392414d9ead9d91f 100644 --- a/wireless/ieee802154/mac802154_getset.c +++ b/wireless/ieee802154/mac802154_getset.c @@ -123,7 +123,13 @@ int mac802154_req_get(MACHANDLE mac, enum ieee802154_attr_e attr, { attrval->mac.resp_waittime = priv->resp_waittime; } - break;; + break; + + case IEEE802154_ATTR_MAC_PROMISCUOUS_MODE: + { + attrval->mac.promisc_mode = priv->promisc; + } + break; default: { @@ -198,10 +204,21 @@ int mac802154_req_set(MACHANDLE mac, enum ieee802154_attr_e attr, { priv->resp_waittime = attrval->mac.resp_waittime; } + break; case IEEE802154_ATTR_MAC_RX_ON_WHEN_IDLE: { mac802154_setrxonidle(priv, attrval->mac.rxonidle); } + break; + case IEEE802154_ATTR_MAC_PROMISCUOUS_MODE: + { + ret = priv->radio->setattr(priv->radio, attr, attrval); + if (ret == 0) + { + priv->promisc = attrval->mac.promisc_mode; + } + } + break; default: { /* The attribute may be handled soley in the radio driver, so pass diff --git a/wireless/ieee802154/mac802154_internal.h b/wireless/ieee802154/mac802154_internal.h index ade1f0e479338fe3af2472b7ff28217d094039b8..dbe22c0b6fcd64ae098cdd145b4204719f3c18b4 100644 --- a/wireless/ieee802154/mac802154_internal.h +++ b/wireless/ieee802154/mac802154_internal.h @@ -59,8 +59,6 @@ #include #include -#include "mac802154_notif.h" - #include #include @@ -73,33 +71,13 @@ * is required. */ -#if !defined(CONFIG_SCHED_WORKQUEUE) -# error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) -#else - - /* Use the low priority work queue if possible */ - -# if defined(CONFIG_MAC802154_HPWORK) -# define MAC802154_WORK HPWORK -# elif defined(CONFIG_MAC802154_LPWORK) -# define MAC802154_WORK LPWORK -# else -# error Neither CONFIG_MAC802154_HPWORK nor CONFIG_MAC802154_LPWORK defined -# endif -#endif - -#if !defined(CONFIG_MAC802154_NNOTIF) || CONFIG_MAC802154_NNOTIF <= 0 -# undef CONFIG_MAC802154_NNOTIF -# define CONFIG_MAC802154_NNOTIF 6 +#if !defined(CONFIG_SCHED_HPWORK) || !defined(CONFIG_SCHED_LPWORK) +# error Both Low and High priority work queues are required for this driver #endif #if !defined(CONFIG_MAC802154_NTXDESC) || CONFIG_MAC802154_NTXDESC <= 0 # undef CONFIG_MAC802154_NTXDESC -# define CONFIG_MAC802154_NTXDESC 3 -#endif - -#if CONFIG_MAC802154_NTXDESC > CONFIG_MAC802154_NNOTIF -# error CONFIG_MAC802154_NNOTIF must be greater than CONFIG_MAC802154_NTXDESC +# define CONFIG_MAC802154_NTXDESC 5 #endif #if !defined(CONFIG_IEEE802154_DEFAULT_EADDR) @@ -182,14 +160,9 @@ struct ieee802154_privmac_s /******************* Fields related to notifications ************************/ - /* Pre-allocated notifications to be passed to the registered callback. These - * need to be freed by the application using mac802154_xxxxnotif_free when - * the callee layer is finished with it's use. - */ - - FAR struct mac802154_notif_s *notif_free; - struct mac802154_notif_s notif_pool[CONFIG_MAC802154_NNOTIF]; - sem_t notif_sem; + sq_queue_t primitive_queue; /* Queue of primitives to pass via notify() + * callback to registered receivers */ + struct work_s notifwork; /* For deferring notifications to LPWORK queue*/ /******************* Tx descriptor queues and pools *************************/ @@ -356,20 +329,22 @@ struct ieee802154_privmac_s * Function Prototypes ****************************************************************************/ -int mac802154_txdesc_alloc(FAR struct ieee802154_privmac_s *priv, - FAR struct ieee802154_txdesc_s **txdesc, - bool allow_interrupt); +int mac802154_txdesc_alloc(FAR struct ieee802154_privmac_s *priv, + FAR struct ieee802154_txdesc_s **txdesc, bool allow_interrupt); void mac802154_setupindirect(FAR struct ieee802154_privmac_s *priv, - FAR struct ieee802154_txdesc_s *txdesc); + FAR struct ieee802154_txdesc_s *txdesc); void mac802154_createdatareq(FAR struct ieee802154_privmac_s *priv, - FAR struct ieee802154_addr_s *coordaddr, - enum ieee802154_addrmode_e srcmode, - FAR struct ieee802154_txdesc_s *txdesc); + FAR struct ieee802154_addr_s *coordaddr, + enum ieee802154_addrmode_e srcmode, + FAR struct ieee802154_txdesc_s *txdesc); void mac802154_updatebeacon(FAR struct ieee802154_privmac_s *priv); +void mac802154_notify(FAR struct ieee802154_privmac_s *priv, + FAR struct ieee802154_primitive_s *primitive); + /**************************************************************************** * Helper Macros/Inline Functions ****************************************************************************/ @@ -546,7 +521,7 @@ void mac802154_updatebeacon(FAR struct ieee802154_privmac_s *priv); /* General helpers **********************************************************/ -#define mac802154_givesem(s) sem_post(s) +#define mac802154_givesem(s) nxsem_post(s) static inline int mac802154_takesem(sem_t *sem, bool allowinterrupt) { @@ -682,7 +657,7 @@ static inline void mac802154_timerstart(FAR struct ieee802154_privmac_s *priv, /* Schedule the work, converting the number of symbols to the number of CPU ticks */ - work_queue(MAC802154_WORK, &priv->timer_work, worker, priv, + work_queue(HPWORK, &priv->timer_work, worker, priv, mac802154_symtoticks(priv, numsymbols)); } @@ -699,7 +674,7 @@ static inline void mac802154_timerstart(FAR struct ieee802154_privmac_s *priv, static inline int mac802154_timercancel(FAR struct ieee802154_privmac_s *priv) { - work_cancel(MAC802154_WORK, &priv->timer_work); + work_cancel(HPWORK, &priv->timer_work); wlinfo("Timer cancelled\n"); return OK; } diff --git a/wireless/ieee802154/mac802154_netdev.c b/wireless/ieee802154/mac802154_netdev.c index bda34e3d2b75ad6efff366bb38d3385a0e608cfc..953c37f26da1c2caff354a68394600b58a9d7723 100644 --- a/wireless/ieee802154/mac802154_netdev.c +++ b/wireless/ieee802154/mac802154_netdev.c @@ -140,8 +140,8 @@ struct macnet_driver_s { /* This holds the information visible to the NuttX network */ - struct radio_driver_s md_dev; /* Interface understood by the network */ - /* Cast compatible with struct macnet_driver_s */ + struct radio_driver_s md_dev; /* Interface understood by the network */ + /* Cast compatible with struct macnet_driver_s */ /* For internal use by this driver */ @@ -154,11 +154,10 @@ struct macnet_driver_s /* Hold a list of events */ - bool md_enableevents : 1; /* Are events enabled? */ - bool md_eventpending : 1; /* Is there a get event using the semaphore? */ - sem_t md_eventsem; /* Signaling semaphore for waiting get event */ - FAR struct ieee802154_notif_s *md_eventhead; - FAR struct ieee802154_notif_s *md_eventtail; + bool md_enableevents : 1; /* Are events enabled? */ + bool md_eventpending : 1; /* Is there a get event using the semaphore? */ + sem_t md_eventsem; /* Signaling semaphore for waiting get event */ + sq_queue_t primitive_queue; /* For holding primitives to pass along */ #ifndef CONFIG_DISABLE_SIGNALS /* MAC Service notification information */ @@ -178,22 +177,13 @@ struct macnet_driver_s static int macnet_advertise(FAR struct net_driver_s *dev); static inline void macnet_netmask(FAR struct net_driver_s *dev); -static inline void macnet_pushevent(FAR struct macnet_driver_s *priv, - FAR struct ieee802154_notif_s *notif); -static inline FAR struct ieee802154_notif_s * - macnet_popevent(FAR struct macnet_driver_s *priv); - /* IEE802.15.4 MAC callback functions ***************************************/ -static void macnet_notify(FAR struct mac802154_maccb_s *maccb, - FAR struct ieee802154_notif_s *notif); -static int macnet_rxframe(FAR struct mac802154_maccb_s *maccb, +static int macnet_notify(FAR struct mac802154_maccb_s *maccb, + FAR struct ieee802154_primitive_s *primitive); +static int macnet_rxframe(FAR struct macnet_driver_s *maccb, FAR struct ieee802154_data_ind_s *ind); -/* Asynchronous event indications, replied to synchronously with responses. - * (none are implemented). - */ - /* Network interface support ************************************************/ /* Common TX logic */ @@ -389,63 +379,6 @@ static inline void macnet_netmask(FAR struct net_driver_s *dev) #endif } -/**************************************************************************** - * Name: macnet_pushevent - * - * Description: - * Push event onto the event queue - * - * Assumptions: - * Called with the device struct locked. - * - ****************************************************************************/ - -static inline void macnet_pushevent(FAR struct macnet_driver_s *priv, - FAR struct ieee802154_notif_s *notif) -{ - notif->flink = NULL; - if (!priv->md_eventhead) - { - priv->md_eventhead = notif; - priv->md_eventtail = notif; - } - else - { - priv->md_eventtail->flink = notif; - priv->md_eventtail = notif; - } -} - -/**************************************************************************** - * Name: macnet_popevent - * - * Description: - * Pop an event off of the event queue - * - * Assumptions: - * Called with the device struct locked. - * - ****************************************************************************/ - -static inline FAR struct ieee802154_notif_s * - macnet_popevent(FAR struct macnet_driver_s *priv) -{ - FAR struct ieee802154_notif_s *notif = priv->md_eventhead; - - if (notif) - { - priv->md_eventhead = notif->flink; - if (!priv->md_eventhead) - { - priv->md_eventhead = NULL; - } - - notif->flink = NULL; - } - - return notif; -} - /**************************************************************************** * Name: macnet_notify * @@ -453,8 +386,8 @@ static inline FAR struct ieee802154_notif_s * * ****************************************************************************/ -static void macnet_notify(FAR struct mac802154_maccb_s *maccb, - FAR struct ieee802154_notif_s *notif) +static int macnet_notify(FAR struct mac802154_maccb_s *maccb, + FAR struct ieee802154_primitive_s *primitive) { FAR struct macnet_callback_s *cb = (FAR struct macnet_callback_s *)maccb; @@ -463,10 +396,12 @@ static void macnet_notify(FAR struct mac802154_maccb_s *maccb, DEBUGASSERT(cb != NULL && cb->mc_priv != NULL); priv = cb->mc_priv; - /* Get exclusive access to the driver structure. We don't care about any - * signals so if we see one, just go back to trying to get access again */ + /* Handle the special case for data indications or "incoming frames" */ - while (nxsem_wait(&priv->md_exclsem) < 0); + if (primitive->type == IEEE802154_PRIMITIVE_IND_DATA) + { + return macnet_rxframe(priv, &primitive->u.dataind); + } /* If there is a registered notification receiver, queue the event and signal * the receiver. Events should be popped from the queue from the application @@ -476,7 +411,13 @@ static void macnet_notify(FAR struct mac802154_maccb_s *maccb, if (priv->md_enableevents) { - macnet_pushevent(priv, notif); + /* Get exclusive access to the driver structure. We don't care about any + * signals so if we see one, just go back to trying to get access again + */ + + while (nxsem_wait(&priv->md_exclsem) < 0); + + sq_addlast((FAR sq_entry_t *)primitive, &priv->primitive_queue); /* Check if there is a read waiting for data */ @@ -493,26 +434,25 @@ static void macnet_notify(FAR struct mac802154_maccb_s *maccb, { #ifdef CONFIG_CAN_PASS_STRUCTS union sigval value; - value.sival_int = (int)notif->notiftype; + value.sival_int = (int)primitive->type; (void)nxsig_queue(priv->md_notify_pid, priv->md_notify_signo, value); #else (void)nxsig_queue(priv->md_notify_pid, priv->md_notify_signo, - (FAR void *)notif->notiftype); + (FAR void *)primitive->type); #endif } #endif - } - else - { - /* Just free the event if the driver is closed and there isn't a registered - * signal number. - */ - mac802154_notif_free(priv->md_mac, notif); + nxsem_post(&priv->md_exclsem); + return OK; } - nxsem_post(&priv->md_exclsem); + /* By returning a negative value, we let the MAC know that we don't want the + * primitive and it will free it for us + */ + + return -1; } /**************************************************************************** @@ -528,18 +468,12 @@ static void macnet_notify(FAR struct mac802154_maccb_s *maccb, * ****************************************************************************/ -static int macnet_rxframe(FAR struct mac802154_maccb_s *maccb, +static int macnet_rxframe(FAR struct macnet_driver_s *priv, FAR struct ieee802154_data_ind_s *ind) { - FAR struct macnet_callback_s *cb = - (FAR struct macnet_callback_s *)maccb; - FAR struct macnet_driver_s *priv; FAR struct iob_s *iob; int ret; - DEBUGASSERT(cb != NULL && cb->mc_priv != NULL); - priv = cb->mc_priv; - /* Ignore the frame if the network is not up */ if (!priv->md_bifup) @@ -557,6 +491,8 @@ static int macnet_rxframe(FAR struct mac802154_maccb_s *maccb, ind->frame = NULL; + net_lock(); + /* Transfer the frame to the network logic */ #ifdef CONFIG_NET_IEEE802154 @@ -597,6 +533,7 @@ static int macnet_rxframe(FAR struct mac802154_maccb_s *maccb, if (ret < 0) #endif { + net_unlock(); ind->frame = iob; return ret; } @@ -606,11 +543,13 @@ static int macnet_rxframe(FAR struct mac802154_maccb_s *maccb, NETDEV_RXPACKETS(&priv->md_dev.r_dev); NETDEV_RXIPV6(&priv->md_dev.r_dev); + net_unlock(); + /* sixlowpan_input() will free the IOB, but we must free the struct - * ieee802154_data_ind_s container here. + * ieee802154_primitive_s container here. */ - ieee802154_ind_free(ind); + ieee802154_primitive_free((FAR struct ieee802154_primitive_s *)ind); return OK; } @@ -1134,25 +1073,27 @@ static int macnet_ioctl(FAR struct net_driver_s *dev, int cmd, case MAC802154IOC_GET_EVENT: { - FAR struct ieee802154_notif_s *notif; + FAR struct ieee802154_primitive_s *primitive; while (1) { /* Try popping an event off the queue */ - notif = macnet_popevent(priv); + primitive = (FAR struct ieee802154_primitive_s *) + sq_remfirst(&priv->primitive_queue); /* If there was an event to pop off, copy it into the user * data and free it from the MAC layer's memory. */ - if (notif != NULL) + if (primitive != NULL) { - memcpy(&netmac->u, notif, sizeof(struct ieee802154_notif_s)); + memcpy(&netmac->u, primitive, + sizeof(struct ieee802154_primitive_s)); - /* Free the notification */ + /* Free the event */ - mac802154_notif_free(priv->md_mac, notif); + ieee802154_primitive_free(primitive); ret = OK; break; } @@ -1486,8 +1427,7 @@ int mac802154netdev_register(MACHANDLE mac) nxsem_init(&priv->md_eventsem, 0, 0); nxsem_setprotocol(&priv->md_eventsem, SEM_PRIO_NONE); - priv->md_eventhead = NULL; - priv->md_eventtail = NULL; + sq_init(&priv->primitive_queue); priv->md_enableevents = false; priv->md_notify_registered = false; @@ -1500,7 +1440,6 @@ int mac802154netdev_register(MACHANDLE mac) maccb->flink = NULL; maccb->prio = CONFIG_IEEE802154_NETDEV_RECVRPRIO; maccb->notify = macnet_notify; - maccb->rxframe = macnet_rxframe; /* Bind the callback structure */ diff --git a/wireless/ieee802154/mac802154_notif.c b/wireless/ieee802154/mac802154_notif.c deleted file mode 100644 index 9cc93a12d3eb371ecab6a7b3640bc340a6f1c9df..0000000000000000000000000000000000000000 --- a/wireless/ieee802154/mac802154_notif.c +++ /dev/null @@ -1,289 +0,0 @@ -/**************************************************************************** - * wireless/ieee802154/mac802154_notif.c - * - * Copyright (C) 2016 Sebastien Lorquet. All rights reserved. - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Copyright (C) 2017 Verge Inc. All rights reserved. - * - * Author: Sebastien Lorquet - * Author: Gregory Nutt - * Author: Anthony Merlino - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include - -#include "mac802154.h" -#include "mac802154_internal.h" - -#include - -/**************************************************************************** - * Public MAC Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: mac802154_notif_free - * - * Description: - * When the MAC calls the registered callback, it passes a reference - * to a mac802154_notify_s structure. This structure needs to be freed - * after the callback handler is done using it. - * - ****************************************************************************/ - -void mac802154_notif_free(MACHANDLE mac, FAR struct ieee802154_notif_s *notif) -{ - FAR struct ieee802154_privmac_s *priv = - (FAR struct ieee802154_privmac_s *)mac; - - /* Lock the MAC */ - - mac802154_lock(priv, false); - - /* Call the internal helper function to free the notification */ - - mac802154_notif_free_locked(priv, notif); - - /* Unlock the MAC */ - - mac802154_unlock(priv) -} - -/**************************************************************************** - * Internal MAC Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: mac802154_notifpool_init - * - * Description: - * This function initializes the notification structure pool. It allows the - * MAC to pass notifications and for the callee to free them when they are - * done using them, saving copying the data when passing. - * - ****************************************************************************/ - -void mac802154_notifpool_init(FAR struct ieee802154_privmac_s *priv) -{ - FAR struct mac802154_notif_s *pool = priv->notif_pool; - int remaining = CONFIG_MAC802154_NNOTIF; - - priv->notif_free = NULL; - while (remaining > 0) - { - FAR struct mac802154_notif_s *notif = pool; - - /* Add the next meta data structure from the pool to the list of - * general structures. - */ - - notif->flink = priv->notif_free; - priv->notif_free = notif; - - /* Set up for the next structure from the pool */ - - pool++; - remaining--; - } - - nxsem_init(&priv->notif_sem, 0, CONFIG_MAC802154_NNOTIF); -} - -/**************************************************************************** - * Name: mac802154_notif_alloc - * - * Description: - * This function allocates a free notification structure from the free list - * to be used for passing to the registered notify callback. The callee software - * is responsible for freeing the notification structure after it is done using - * it via mac802154_notif_free. - * - * Assumptions: - * priv MAC struct is locked when calling. - * - * Notes: - * If any of the semaphore waits inside this function get interrupted, the - * function will release the MAC layer. If this function returns -EINTR, the - * calling code should NOT release the MAC semaphore. - * - ****************************************************************************/ - -int mac802154_notif_alloc(FAR struct ieee802154_privmac_s *priv, - FAR struct ieee802154_notif_s **notif, - bool allow_interrupt) -{ - int ret; - FAR struct mac802154_notif_s *privnotif; - - /* Try and take a count from the semaphore. If this succeeds, we have - * "reserved" the structure, but still need to unlink it from the free list. - * The MAC is already locked, so there shouldn't be any other conflicting calls - */ - - ret = nxsem_trywait(&priv->notif_sem); - - if (ret == OK) - { - privnotif = priv->notif_free; - priv->notif_free = privnotif->flink; - privnotif->nclients = 0; - } - else - { - /* Unlock MAC so that other work can be done to free a notification */ - - mac802154_unlock(priv) - - /* Take a count from the notification semaphore, waiting if necessary. We - * only return from here with an error if we are allowing interruptions - * and we received a signal */ - - ret = mac802154_takesem(&priv->notif_sem, allow_interrupt); - if (ret < 0) - { - /* MAC sem is already released */ - - return -EINTR; - } - - /* If we've taken a count from the semaphore, we have "reserved" the struct - * but now we need to pop it off of the free list. We need to re-lock the - * MAC in order to ensure this happens correctly. - */ - - ret = mac802154_lock(priv, allow_interrupt); - if (ret < 0) - { - mac802154_givesem(&priv->notif_sem); - return -EINTR; - } - - /* We can now safely unlink the next free structure from the free list */ - - privnotif = priv->notif_free; - priv->notif_free = privnotif->flink; - privnotif->nclients = 0; - } - - *notif = (FAR struct ieee802154_notif_s *)privnotif; - - return OK; -} - -/**************************************************************************** - * Name: mac802154_notif_free_locked - * - * Description: - * When the MAC calls the registered callback, it passes a reference - * to a mac802154_notify_s structure. This structure needs to be freed - * after the callback handler is done using it. - * - * Internal version that already has MAC locked - * - ****************************************************************************/ - -void mac802154_notif_free_locked(FAR struct ieee802154_privmac_s * priv, - FAR struct ieee802154_notif_s *notif) -{ - FAR struct mac802154_notif_s *privnotif = - (FAR struct mac802154_notif_s *)notif; - - /* We know how many clients have registered for notifications. Each must - * call mac802154_notif_free() before we can release the notification - * resource. - */ - - if (privnotif->nclients < 2) - { - /* This is the free from the last notification */ - - privnotif->flink = priv->notif_free; - priv->notif_free = privnotif; - privnotif->nclients = 0; - - mac802154_givesem(&priv->notif_sem); - } - else - { - /* More calls are expected. Decrement the count of expected calls - * and preserve the notification resources. - */ - - privnotif->nclients--; - } -} - -/**************************************************************************** - * Name: mac802154_notify - * - * Description: - * Notify every register MAC client. - * - ****************************************************************************/ - -void mac802154_notify(FAR struct ieee802154_privmac_s *priv, - FAR struct ieee802154_notif_s *notif) -{ - FAR struct mac802154_maccb_s *cb; - FAR struct mac802154_notif_s *privnotif = (FAR struct mac802154_notif_s *)notif; - - /* Set the notification count so that the notification resources will be - * preserved until the final notification. - */ - - privnotif->nclients = priv->nclients; - - /* Try to notify every registered MAC client */ - - for (cb = priv->cb; cb != NULL; cb = cb->flink) - { - /* Does this client want notifications? */ - - if (cb->notify != NULL) - { - /* Yes.. Notify */ - - cb->notify(cb, notif); - } - } -} diff --git a/wireless/ieee802154/mac802154_poll.c b/wireless/ieee802154/mac802154_poll.c index c14b409dfddc3f4f2c2621dd47153127208a6293..7701bd7cd4bee4982a76d1cd13196a9540513a2d 100644 --- a/wireless/ieee802154/mac802154_poll.c +++ b/wireless/ieee802154/mac802154_poll.c @@ -189,9 +189,9 @@ int mac802154_req_poll(MACHANDLE mac, FAR struct ieee802154_poll_req_s *req) void mac802154_txdone_datareq_poll(FAR struct ieee802154_privmac_s *priv, FAR struct ieee802154_txdesc_s *txdesc) { + FAR struct ieee802154_primitive_s * primitive = + (FAR struct ieee802154_primitive_s *)txdesc->conf; enum ieee802154_status_e status; - FAR struct ieee802154_notif_s *notif = - (FAR struct ieee802154_notif_s *)txdesc->conf; /* If the data request failed to be sent, notify the next layer * that the poll has failed. @@ -201,20 +201,20 @@ void mac802154_txdone_datareq_poll(FAR struct ieee802154_privmac_s *priv, * pending at the coordinator. [1] pg. 43 */ - if (notif->u.dataconf.status != IEEE802154_STATUS_SUCCESS || + if (txdesc->conf->status != IEEE802154_STATUS_SUCCESS || txdesc->framepending == 0) { - if (notif->u.dataconf.status != IEEE802154_STATUS_SUCCESS) + if (txdesc->conf->status != IEEE802154_STATUS_SUCCESS) { - status = notif->u.dataconf.status; + status = txdesc->conf->status; } else { status = IEEE802154_STATUS_NO_DATA; } - notif->notiftype = IEEE802154_NOTIFY_CONF_POLL; - notif->u.pollconf.status = status; + primitive->type = IEEE802154_PRIMITIVE_CONF_POLL; + txdesc->conf->status = status; /* We are now done the operation, and can release the command */ @@ -222,11 +222,7 @@ void mac802154_txdone_datareq_poll(FAR struct ieee802154_privmac_s *priv, priv->cmd_desc = NULL; mac802154_givesem(&priv->opsem); - /* Release the MAC, call the callback, get exclusive access again */ - - mac802154_unlock(priv) - mac802154_notify(priv, notif); - mac802154_lock(priv, false); + mac802154_notify(priv, primitive); } else { @@ -246,9 +242,9 @@ void mac802154_txdone_datareq_poll(FAR struct ieee802154_privmac_s *priv, mac802154_timerstart(priv, priv->max_frame_waittime, mac802154_polltimeout); - /* Deallocate the data conf notification as it is no longer needed. */ + /* Deallocate the data conf primitive as it is no longer needed. */ - mac802154_notif_free_locked(priv, notif); + ieee802154_primitive_free(primitive); } } @@ -264,7 +260,7 @@ void mac802154_txdone_datareq_poll(FAR struct ieee802154_privmac_s *priv, void mac802154_polltimeout(FAR void *arg) { FAR struct ieee802154_privmac_s *priv = (FAR struct ieee802154_privmac_s *)arg; - FAR struct ieee802154_notif_s *notif; + FAR struct ieee802154_primitive_s *primitive; /* If there is work scheduled for the rxframe_worker, we want to reschedule * this work, so that we make sure if the frame we were waiting for was just @@ -273,30 +269,23 @@ void mac802154_polltimeout(FAR void *arg) if (!work_available(&priv->rx_work)) { - work_queue(MAC802154_WORK, &priv->timer_work, mac802154_polltimeout, priv, 0); + work_queue(HPWORK, &priv->timer_work, mac802154_polltimeout, priv, 0); return; } DEBUGASSERT(priv->curr_op == MAC802154_OP_POLL); - /* Allocate a notification struct to pass to the next highest layer. - * Don't allow EINTR to interrupt. - */ + primitive = ieee802154_primitive_allocate(); + primitive->type = IEEE802154_PRIMITIVE_CONF_POLL; + primitive->u.pollconf.status = IEEE802154_STATUS_NO_DATA; mac802154_lock(priv, false); - mac802154_notif_alloc(priv, ¬if, false); /* We are no longer performing the association operation */ priv->curr_op = MAC802154_OP_NONE; priv->cmd_desc = NULL; mac802154_givesem(&priv->opsem); - /* Release the MAC */ - - mac802154_unlock(priv) - - notif->notiftype = IEEE802154_NOTIFY_CONF_POLL; - notif->u.pollconf.status = IEEE802154_STATUS_NO_DATA; - - mac802154_notify(priv, notif); + mac802154_notify(priv, primitive); + mac802154_unlock(priv); } \ No newline at end of file diff --git a/wireless/ieee802154/mac802154_scan.c b/wireless/ieee802154/mac802154_scan.c index 0c6140b19262c731306bd35a567a1a2fb730fd87..1c131dc7d6730a8c5bd586e1bdf3d84d3db728ec 100644 --- a/wireless/ieee802154/mac802154_scan.c +++ b/wireless/ieee802154/mac802154_scan.c @@ -203,39 +203,41 @@ errout: void mac802154_scanfinish(FAR struct ieee802154_privmac_s *priv, enum ieee802154_status_e status) { - FAR struct ieee802154_notif_s * notif; + FAR struct ieee802154_primitive_s * primitive; + FAR struct ieee802154_scan_conf_s *scanconf; - mac802154_lock(priv, false); - mac802154_notif_alloc(priv, ¬if, false); - - priv->curr_op = MAC802154_OP_NONE; - mac802154_givesem(&priv->opsem); + primitive = ieee802154_primitive_allocate(); + scanconf = &primitive->u.scanconf; - notif->notiftype = IEEE802154_NOTIFY_CONF_SCAN; - notif->u.scanconf.type = priv->currscan.type; - notif->u.scanconf.chpage = priv->currscan.chpage; + primitive->type = IEEE802154_PRIMITIVE_CONF_SCAN; + scanconf->type = priv->currscan.type; + scanconf->chpage = priv->currscan.chpage; /* Copy in the channels that did not get scanned */ if (priv->scanindex != priv->currscan.numchan) { - notif->u.scanconf.numunscanned = priv->currscan.numchan - priv->scanindex; - memcpy(notif->u.scanconf.unscanned, &priv->currscan.channels[priv->scanindex], - notif->u.scanconf.numunscanned); + scanconf->numunscanned = priv->currscan.numchan - priv->scanindex; + memcpy(scanconf->unscanned, &priv->currscan.channels[priv->scanindex], + scanconf->numunscanned); } - notif->u.scanconf.numdesc = priv->npandesc; - memcpy(notif->u.scanconf.pandescs, priv->pandescs, + /* Copy the PAN descriptors into the primitive */ + + memcpy(scanconf->pandescs, priv->pandescs, sizeof(struct ieee802154_pandesc_s) * priv->npandesc); - notif->u.scanconf.status = status; + + scanconf->numdesc = priv->npandesc; + scanconf->status = status; /* Reset the PAN ID to the setting before the scan started */ mac802154_setpanid(priv, priv->panidbeforescan); - mac802154_unlock(priv) + priv->curr_op = MAC802154_OP_NONE; + mac802154_givesem(&priv->opsem); - mac802154_notify(priv, notif); + mac802154_notify(priv, primitive); } /**************************************************************************** @@ -256,6 +258,8 @@ static void mac802154_scantimeout(FAR void *arg) FAR struct ieee802154_privmac_s *priv = (FAR struct ieee802154_privmac_s *)arg; DEBUGASSERT(priv->curr_op == MAC802154_OP_SCAN); + mac802154_lock(priv, false); + /* If we got here it means we are done scanning that channel */ mac802154_rxdisable(priv); @@ -286,4 +290,5 @@ static void mac802154_scantimeout(FAR void *arg) mac802154_rxenable(priv); mac802154_timerstart(priv, priv->scansymdur, mac802154_scantimeout); + mac802154_unlock(priv); }