diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.h b/arch/arm/src/lpc17xx/lpc17_ethernet.h
new file mode 100755
index 0000000000000000000000000000000000000000..583a89d7a7a171e0c492e99b8b6ba4c2ba00bbc5
--- /dev/null
+++ b/arch/arm/src/lpc17xx/lpc17_ethernet.h
@@ -0,0 +1,279 @@
+/************************************************************************************
+ * arch/arm/src/lpc17xx/lpc17_ethernet.h
+ *
+ * Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_ETHERNET_H
+#define __ARCH_ARM_SRC_LPC17XX_LPC17_ETHERNET_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "lp17_memorymap.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+/* MAC registers */
+
+#define LPC17_ETH_MAC1_OFFSET 0x0000 /* MAC configuration register 1 */
+#define LPC17_ETH_MAC2_OFFSET 0x0004 /* MAC configuration register 2 */
+#define LPC17_ETH_IPGT_OFFSET 0x0008 /* Back-to-Back Inter-Packet-Gap register */
+#define LPC17_ETH_IPGR_OFFSET 0x000c /* Non Back-to-Back Inter-Packet-Gap register */
+#define LPC17_ETH_CLRT_OFFSET 0x0010 /* Collision window / Retry register */
+#define LPC17_ETH_MAXF_OFFSET 0x0014 /* Maximum Frame register */
+#define LPC17_ETH_SUPP_OFFSET 0x0018 /* PHY Support register */
+#define LPC17_ETH_TEST_OFFSET 0x001c /* Test register */
+#define LPC17_ETH_MCFG_OFFSET 0x0020 /* MII Mgmt Configuration register */
+#define LPC17_ETH_MCMD_OFFSET 0x0024 /* MII Mgmt Command register */
+#define LPC17_ETH_MADR_OFFSET 0x0028 /* MII Mgmt Address register */
+#define LPC17_ETH_MWTD_OFFSET 0x002c /* MII Mgmt Write Data register */
+#define LPC17_ETH_MRDD_OFFSET 0x0030 /* MII Mgmt Read Data register */
+#define LPC17_ETH_MIND_OFFSET 0x0034 /* MII Mgmt Indicators register */
+#define LPC17_ETH_SA0_OFFSET 0x0040 /* Station Address 0 register */
+#define LPC17_ETH_SA1_OFFSET 0x0044 /* Station Address 1 register */
+#define LPC17_ETH_SA2_OFFSET 0x0048 /* Station Address 2 register */
+
+/* Control registers */
+
+#define LPC17_ETH_COMMAND_OFFSET 0x0100 /* Command register */
+#define LPC17_ETH_STAT_OFFSET 0x0104 /* Status register */
+#define LPC17_ETH_RXDESC_OFFSET 0x0108 /* Receive descriptor base address register */
+#define LPC17_ETH_RXSTAT_OFFSET 0x010c /* Receive status base address register */
+#define LPC17_ETH_RXDESCNO_OFFSET 0x0110 /* Receive number of descriptors register */
+#define LPC17_ETH_RXPRODIDX_OFFSET 0x0114 /* Receive produce index register */
+#define LPC17_ETH_RXCONSIDX_OFFSET 0x0118 /* Receive consume index register */
+#define LPC17_ETH_TXDESC_OFFSET 0x011c /* Transmit descriptor base address register */
+#define LPC17_ETH_TXSTAT_OFFSET 0x0120 /* Transmit status base address register */
+#define LPC17_ETH_TXDESCRNO_OFFSET 0x0124 /* Transmit number of descriptors register */
+#define LPC17_ETH_TXPRODIDX_OFFSET 0x0128 /* Transmit produce index register */
+#define LPC17_ETH_TXCONSIDX_OFFSET 0x012c /* Transmit consume index register */
+#define LPC17_ETH_TSV0_OFFSET 0x0158 /* Transmit status vector 0 register */
+#define LPC17_ETH_TSV1_OFFSET 0x015c /* Transmit status vector 1 register */
+#define LPC17_ETH_RSV_OFFSET 0x0160 /* Receive status vector register */
+#define LPC17_ETH_FCCNTR_OFFSET 0x0170 /* Flow control counter register */
+#define LPC17_ETH_FCSTAT_OFFSET 0x0174 /* Flow control status register */
+
+/* Rx filter registers */
+
+#define LPC17_ETH_RXFLCTRL_OFFSET 0x0200 /* Receive filter control register */
+#define LPC17_ETH_RXFLWOLST_OFFSET 0x0204 /* Receive filter WoL status register */
+#define LPC17_ETH_RXFLWOLCLR_OFFSET 0x0208 /* Receive filter WoL clear register */
+#define LPC17_ETH_HASHFLL_OFFSET 0x0210 /* Hash filter table LSBs register */
+#define LPC17_ETH_HASHFLH_OFFSET 0x0214 /* Hash filter table MSBs register */
+
+/* Module control registers */
+
+#define LPC17_ETH_INTST_OFFSET 0x0fe0 /* Interrupt status register */
+#define LPC17_ETH_INTEN_OFFSET 0x0fe4 /* Interrupt enable register */
+#define LPC17_ETH_INTCLR_OFFSET 0x0fe8 /* Interrupt clear register */
+#define LPC17_ETH_INTSET_OFFSET 0x0fec /* Interrupt set register */
+#define LPC17_ETH_PWRDOWN_OFFSET 0x0ff4 /* Power-down register */
+
+/* Register addresses ***************************************************************/
+/* MAC registers */
+
+#define LPC17_ETH_MAC1 (LPC17_ETH_BASE+LPC17_ETH_MAC1_OFFSET)
+#define LPC17_ETH_MAC2 (LPC17_ETH_BASE+LPC17_ETH_MAC2_OFFSET)
+#define LPC17_ETH_IPGT (LPC17_ETH_BASE+LPC17_ETH_IPGT_OFFSET)
+#define LPC17_ETH_IPGR (LPC17_ETH_BASE+LPC17_ETH_IPGR_OFFSET)
+#define LPC17_ETH_CLRT (LPC17_ETH_BASE+LPC17_ETH_CLRT_OFFSET)
+#define LPC17_ETH_MAXF (LPC17_ETH_BASE+LPC17_ETH_MAXF_OFFSET)
+#define LPC17_ETH_SUPP (LPC17_ETH_BASE+LPC17_ETH_SUPP_OFFSET)
+#define LPC17_ETH_TEST (LPC17_ETH_BASE+LPC17_ETH_TEST_OFFSET)
+#define LPC17_ETH_MCFG (LPC17_ETH_BASE+LPC17_ETH_MCFG_OFFSET)
+#define LPC17_ETH_MCMD (LPC17_ETH_BASE+LPC17_ETH_MCMD_OFFSET)
+#define LPC17_ETH_MADR (LPC17_ETH_BASE+LPC17_ETH_MADR_OFFSET)
+#define LPC17_ETH_MWTD (LPC17_ETH_BASE+LPC17_ETH_MWTD_OFFSET)
+#define LPC17_ETH_MRDD (LPC17_ETH_BASE+LPC17_ETH_MRDD_OFFSET)
+#define LPC17_ETH_MIND (LPC17_ETH_BASE+LPC17_ETH_MIND_OFFSET)
+#define LPC17_ETH_SA0 (LPC17_ETH_BASE+LPC17_ETH_SA0_OFFSET)
+#define LPC17_ETH_SA1 (LPC17_ETH_BASE+LPC17_ETH_SA1_OFFSET)
+#define LPC17_ETH_SA2 (LPC17_ETH_BASE+LPC17_ETH_SA2_OFFSET)
+
+/* Control registers */
+
+#define LPC17_ETH_COMMAND (LPC17_ETH_BASE+LPC17_ETH_COMMAND_OFFSET)
+#define LPC17_ETH_STAT (LPC17_ETH_BASE+LPC17_ETH_STAT_OFFSET)
+#define LPC17_ETH_RXDESC (LPC17_ETH_BASE+LPC17_ETH_RXDESC_OFFSET)
+#define LPC17_ETH_RXSTAT (LPC17_ETH_BASE+LPC17_ETH_RXSTAT_OFFSET)
+#define LPC17_ETH_RXDESCNO (LPC17_ETH_BASE+LPC17_ETH_RXDESCNO_OFFSET)
+#define LPC17_ETH_RXPRODIDX (LPC17_ETH_BASE+LPC17_ETH_RXPRODIDX_OFFSET)
+#define LPC17_ETH_RXCONSIDX (LPC17_ETH_BASE+LPC17_ETH_RXCONSIDX_OFFSET)
+#define LPC17_ETH_TXDESC (LPC17_ETH_BASE+LPC17_ETH_TXDESC_OFFSET)
+#define LPC17_ETH_TXSTAT (LPC17_ETH_BASE+LPC17_ETH_TXSTAT_OFFSET)
+#define LPC17_ETH_TXDESCRNO (LPC17_ETH_BASE+LPC17_ETH_TXDESCRNO_OFFSET)
+#define LPC17_ETH_TXPRODIDX (LPC17_ETH_BASE+LPC17_ETH_TXPRODIDX_OFFSET)
+#define LPC17_ETH_TXCONSIDX (LPC17_ETH_BASE+LPC17_ETH_TXCONSIDX_OFFSET)
+#define LPC17_ETH_TSV0 (LPC17_ETH_BASE+LPC17_ETH_TSV0_OFFSET)
+#define LPC17_ETH_TSV1 (LPC17_ETH_BASE+LPC17_ETH_TSV1_OFFSET)
+#define LPC17_ETH_RSV (LPC17_ETH_BASE+LPC17_ETH_RSV_OFFSET)
+#define LPC17_ETH_FCCNTR (LPC17_ETH_BASE+LPC17_ETH_FCCNTR_OFFSET)
+#define LPC17_ETH_FCSTAT (LPC17_ETH_BASE+LPC17_ETH_FCSTAT_OFFSET)
+
+/* Rx filter registers */
+
+#define LPC17_ETH_RXFLCTRL (LPC17_ETH_BASE+LPC17_ETH_RXFLCTRL_OFFSET)
+#define LPC17_ETH_RXFLWOLST (LPC17_ETH_BASE+LPC17_ETH_RXFLWOLST_OFFSET)
+#define LPC17_ETH_RXFLWOLCLR (LPC17_ETH_BASE+LPC17_ETH_RXFLWOLCLR_OFFSET)
+#define LPC17_ETH_HASHFLL (LPC17_ETH_BASE+LPC17_ETH_HASHFLL_OFFSET)
+#define LPC17_ETH_HASHFLH (LPC17_ETH_BASE+LPC17_ETH_HASHFLH_OFFSET)
+
+/* Module control registers */
+
+#define LPC17_ETH_INTST (LPC17_ETH_BASE+LPC17_ETH_INTST_OFFSET)
+#define LPC17_ETH_INTEN (LPC17_ETH_BASE+LPC17_ETH_INTEN_OFFSET)
+#define LPC17_ETH_INTCLR (LPC17_ETH_BASE+LPC17_ETH_INTCLR_OFFSET)
+#define LPC17_ETH_INTSET (LPC17_ETH_BASE+LPC17_ETH_INTSET_OFFSET)
+#define LPC17_ETH_PWRDOWN (LPC17_ETH_BASE+LPC17_ETH_PWRDOWN_OFFSET)
+
+/* Register bit definitions *********************************************************/
+/* MAC registers */
+
+/* MAC configuration register 1 */
+#define ETH_MAC1_
+/* MAC configuration register 2 */
+#define ETH_MAC2_
+/* Back-to-Back Inter-Packet-Gap register */
+#define ETH_IPGT_
+/* Non Back-to-Back Inter-Packet-Gap register */
+#define ETH_IPGR_
+/* Collision window / Retry register */
+#define ETH_CLRT_
+/* Maximum Frame register */
+#define ETH_MAXF_
+/* PHY Support register */
+#define ETH_SUPP_
+/* Test register */
+#define ETH_TEST_
+/* MII Mgmt Configuration register */
+#define ETH_MCFG_
+/* MII Mgmt Command register */
+#define ETH_MCMD_
+/* MII Mgmt Address register */
+#define ETH_MADR_
+/* MII Mgmt Write Data register */
+#define ETH_MWTD_
+/* MII Mgmt Read Data register */
+#define ETH_MRDD_
+/* MII Mgmt Indicators register */
+#define ETH_MIND_
+/* Station Address 0 register */
+#define ETH_SA0_
+/* Station Address 1 register */
+#define ETH_SA1_
+/* Station Address 2 register */
+#define ETH_SA2_
+
+/* Control registers */
+
+/* Command register */
+#define ETH_COMMAND_
+/* Status register */
+#define ETH_STAT_
+/* Receive descriptor base address register */
+#define ETH_RXDESC_
+/* Receive status base address register */
+#define ETH_RXSTAT_
+/* Receive number of descriptors register */
+#define ETH_RXDESCNO_
+/* Receive produce index register */
+#define ETH_RXPRODIDX_
+/* Receive consume index register */
+#define ETH_RXCONSIDX_
+/* Transmit descriptor base address register */
+#define ETH_TXDESC_
+/* Transmit status base address register */
+#define ETH_TXSTAT_
+/* Transmit number of descriptors register */
+#define ETH_TXDESCRNO_
+/* Transmit produce index register */
+#define ETH_TXPRODIDX_
+/* Transmit consume index register */
+#define ETH_TXCONSIDX_
+/* Transmit status vector 0 register */
+#define ETH_TSV0_
+/* Transmit status vector 1 register */
+#define ETH_TSV1_
+/* Receive status vector register */
+#define ETH_RSV_
+/* Flow control counter register */
+#define ETH_FCCNTR_
+/* Flow control status register */
+#define ETH_FCSTAT_
+
+/* Rx filter registers */
+
+/* Receive filter control register */
+#define ETH_RXFLCTRL_
+/* Receive filter WoL status register */
+#define ETH_RXFLWOLST_
+/* Receive filter WoL clear register */
+#define ETH_RXFLWOLCLR_
+/* Hash filter table LSBs register */
+#define ETH_HASHFLL_
+/* Hash filter table MSBs register */
+#define ETH_HASHFLH_
+
+/* Module control registers */
+
+/* Interrupt status register */
+#define ETH_INTST_
+/* Interrupt enable register */
+#define ETH_INTEN_
+/* Interrupt clear register */
+#define ETH_INTCLR_
+/* Interrupt set register */
+#define ETH_INTSET_
+/* Power-down register */
+#define ETH_PWRDOWN_
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_ETHERNET_H */
diff --git a/arch/arm/src/lpc17xx/lpc17_usb.h b/arch/arm/src/lpc17xx/lpc17_usb.h
index b061c8f5da2750694b03e55de52bfc1f1c8942ce..4026c7a029acfaddbedd1d2c04f9fcdb7f9686e5 100755
--- a/arch/arm/src/lpc17xx/lpc17_usb.h
+++ b/arch/arm/src/lpc17xx/lpc17_usb.h
@@ -41,6 +41,7 @@
************************************************************************************/
#include <nuttx/config.h>
+#include <nuttx/ohci.h>
#include "chip.h"
#include "lp17_memorymap.h"
@@ -51,30 +52,8 @@
/* Register offsets *****************************************************************/
/* USB Host Controller (OHCI) *******************************************************/
+/* See include/nuttx/ohci.h */
-#define LPC17_USBHOST_HCIREV_OFFSET 0x0000 /* HcRevision: Version of HCI specification */
-#define LPC17_USBHOST_CTRL_OFFSET 0x0004 /* HcControl: HC control */
-#define LPC17_USBHOST_CMDST_OFFSET 0x0008 /* HcCommandStatus: HC command status */
-#define LPC17_USBHOST_INTST_OFFSET 0x000c /* HcInterruptStatus: HC interrupt status */
-#define LPC17_USBHOST_INTEN_OFFSET 0x0010 /* HcInterruptEnable: HC interrupt enable */
-#define LPC17_USBHOST_INTDIS_OFFSET 0x0014 /* HcInterruptDisable: HC interrupt disable */
-#define LPC17_USBHOST_HCCA_OFFSET 0x0018 /* HcHCCA: HC communication area */
-#define LPC17_USBHOST_IIED_OFFSET 0x001c /* HcPeriodCurrentED: Current isoc or int endpoint desc */
-#define LPC17_USBHOST_CTRLHEADED_OFFSET 0x0020 /* HcControlHeadED: First EP desc in the control list */
-#define LPC17_USBHOST_CTRLED_OFFSET 0x0024 /* HcControlCurrentED: Current EP desc in the control list */
-#define LPC17_USBHOST_BULKHEADED_OFFSET 0x0028 /* HcBulkHeadED: First EP desc in the bulk list */
-#define LPC17_USBHOST_BULKED_OFFSET 0x002c /* HcBulkCurrentED: Current EP desc in the bulk list */
-#define LPC17_USBHOST_DONEHEAD_OFFSET 0x0030 /* HcDoneHead: Last transfer desc added to DONE queue */
-#define LPC17_USBHOST_FMINT_OFFSET 0x0034 /* HcFmInterval: Bit time interval that would not cause overrun */
-#define LPC17_USBHOST_FMREM_OFFSET 0x0038 /* HcFmRemaining: Bit time remaining in current frame */
-#define LPC17_USBHOST_FMNO_OFFSET 0x003c /* HcFmNumber: Frame number counter */
-#define LPC17_USBHOST_PERSTART_OFFSET 0x0040 /* HcPeriodicStart: Time to start processing periodic list */
-#define LPC17_USBHOST_LSTHRES_OFFSET 0x0044 /* HcLSThreshold: Commit to transfer threshold */
-#define LPC17_USBHOST_RHDESCA_OFFSET 0x0048 /* HcRhDescriptorA: Describes root hub (part A) */
-#define LPC17_USBHOST_RHDESCB_OFFSET 0x004c /* HcRhDescriptorB: Describes root hub (part B) */
-#define LPC17_USBHOST_RHSTATUS_OFFSET 0x0050 /* HcRhStatus: Root hub status */
-#define LPC17_USBHOST_RHPORTST1_OFFSET 0x0054 /* HcRhPort1Status: Root hub port status 1 */
-#define LPC17_USBHOST_RHPORTST2_OFFSET 0x0058 /* HcRhPort2Status: Root hub port status 2 */
#define LPC17_USBHOST_MODID_OFFSET 0x00fc /* Module ID/Revision ID */
/* USB OTG Controller ***************************************************************/
@@ -166,30 +145,40 @@
/* Register addresses ***************************************************************/
/* USB Host Controller (OHCI) *******************************************************/
-
-#define LPC17_USBHOST_HCIREV (LPC17_USB_BASE+LPC17_USBHOST_HCIREV_OFFSET)
-#define LPC17_USBHOST_CTRL (LPC17_USB_BASE+LPC17_USBHOST_CTRL_OFFSET)
-#define LPC17_USBHOST_CMDST (LPC17_USB_BASE+LPC17_USBHOST_CMDST_OFFSET)
-#define LPC17_USBHOST_INTST (LPC17_USB_BASE+LPC17_USBHOST_INTST_OFFSET)
-#define LPC17_USBHOST_INTEN (LPC17_USB_BASE+LPC17_USBHOST_INTEN_OFFSET)
-#define LPC17_USBHOST_INTDIS (LPC17_USB_BASE+LPC17_USBHOST_INTDIS_OFFSET)
-#define LPC17_USBHOST_HCCA (LPC17_USB_BASE+LPC17_USBHOST_HCCA_OFFSET)
-#define LPC17_USBHOST_IIED (LPC17_USB_BASE+LPC17_USBHOST_IIED_OFFSET)
-#define LPC17_USBHOST_CTRLHEADED (LPC17_USB_BASE+LPC17_USBHOST_CTRLHEADED_OFFSET)
-#define LPC17_USBHOST_CTRLED (LPC17_USB_BASE+LPC17_USBHOST_CTRLED_OFFSET)
-#define LPC17_USBHOST_BULKHEADED (LPC17_USB_BASE+LPC17_USBHOST_BULKHEADED_OFFSET)
-#define LPC17_USBHOST_BULKED (LPC17_USB_BASE+LPC17_USBHOST_BULKED_OFFSET)
-#define LPC17_USBHOST_DONEHEAD (LPC17_USB_BASE+LPC17_USBHOST_DONEHEAD_OFFSET)
-#define LPC17_USBHOST_FMINT (LPC17_USB_BASE+LPC17_USBHOST_FMINT_OFFSET)
-#define LPC17_USBHOST_FMREM (LPC17_USB_BASE+LPC17_USBHOST_FMREM_OFFSET)
-#define LPC17_USBHOST_FMNO (LPC17_USB_BASE+LPC17_USBHOST_FMNO_OFFSET)
-#define LPC17_USBHOST_PERSTART (LPC17_USB_BASE+LPC17_USBHOST_PERSTART_OFFSET)
-#define LPC17_USBHOST_LSTHRES (LPC17_USB_BASE+LPC17_USBHOST_LSTHRES_OFFSET)
-#define LPC17_USBHOST_RHDESCA (LPC17_USB_BASE+LPC17_USBHOST_RHDESCA_OFFSET)
-#define LPC17_USBHOST_RHDESCB (LPC17_USB_BASE+LPC17_USBHOST_RHDESCB_OFFSET)
-#define LPC17_USBHOST_RHSTATUS (LPC17_USB_BASE+LPC17_USBHOST_RHSTATUS_OFFSET)
-#define LPC17_USBHOST_RHPORTST1 (LPC17_USB_BASE+LPC17_USBHOST_RHPORTST1_OFFSET)
-#define LPC17_USBHOST_RHPORTST2 (LPC17_USB_BASE+LPC17_USBHOST_RHPORTST2_OFFSET)
+/* Control and status registers (section 7.1) */
+
+#define LPC17_USBHOST_HCIREV (LPC17_USB_BASE+OHCI_HCIREV_OFFSET)
+#define LPC17_USBHOST_CTRL (LPC17_USB_BASE+OHCI_CTRL_OFFSET)
+#define LPC17_USBHOST_CMDST (LPC17_USB_BASE+OHCI_CMDST_OFFSET)
+#define LPC17_USBHOST_INTST (LPC17_USB_BASE+OHCI_INTST_OFFSET)
+#define LPC17_USBHOST_INTEN (LPC17_USB_BASE+OHCI_INTEN_OFFSET)
+#define LPC17_USBHOST_INTDIS (LPC17_USB_BASE+OHCI_INTDIS_OFFSET)
+
+/* Memory pointers (section 7.2) */
+
+#define LPC17_USBHOST_HCCA (LPC17_USB_BASE+OHCI_HCCA_OFFSET)
+#define LPC17_USBHOST_PERED (LPC17_USB_BASE+OHCI_PERED_OFFSET)
+#define LPC17_USBHOST_CTRLHEADED (LPC17_USB_BASE+OHCI_CTRLHEADED_OFFSET)
+#define LPC17_USBHOST_CTRLED (LPC17_USB_BASE+OHCI_CTRLED_OFFSET)
+#define LPC17_USBHOST_BULKHEADED (LPC17_USB_BASE+OHCI_BULKHEADED_OFFSET)
+#define LPC17_USBHOST_BULKED (LPC17_USB_BASE+OHCI_BULKED_OFFSET)
+#define LPC17_USBHOST_DONEHEAD (LPC17_USB_BASE+OHCI_DONEHEAD_OFFSET)
+
+/* Frame counters (section 7.3) */
+
+#define LPC17_USBHOST_FMINT (LPC17_USB_BASE+OHCI_FMINT_OFFSET)
+#define LPC17_USBHOST_FMREM (LPC17_USB_BASE+OHCI_FMREM_OFFSET)
+#define LPC17_USBHOST_FMNO (LPC17_USB_BASE+OHCI_FMNO_OFFSET)
+#define LPC17_USBHOST_PERSTART (LPC17_USB_BASE+OHCI_PERSTART_OFFSET)
+
+/* Root hub ports (section 7.4) */
+
+#define LPC17_USBHOST_LSTHRES (LPC17_USB_BASE+OHCI_LSTHRES_OFFSET)
+#define LPC17_USBHOST_RHDESCA (LPC17_USB_BASE+OHCI_RHDESCA_OFFSET)
+#define LPC17_USBHOST_RHDESCB (LPC17_USB_BASE+OHCI_RHDESCB_OFFSET)
+#define LPC17_USBHOST_RHSTATUS (LPC17_USB_BASE+OHCI_RHSTATUS_OFFSET)
+#define LPC17_USBHOST_RHPORTST1 (LPC17_USB_BASE+OHCI_RHPORTST1_OFFSET)
+#define LPC17_USBHOST_RHPORTST2 (LPC17_USB_BASE+OHCI_RHPORTST2_OFFSET)
#define LPC17_USBHOST_MODID (LPC17_USB_BASE+LPC17_USBHOST_MODID_OFFSET)
/* USB OTG Controller ***************************************************************/
@@ -212,8 +201,8 @@
/* SIE Command registers */
-#define LPC17_USBDEV_CMDCODE (LPC17_USB_BASE+LPC17_USBDEV_CMDCODE_OFFSET)
-#define LPC17_USBDEV_CMDDATA (LPC17_USB_BASE+LPC17_USBDEV_CMDDATA_OFFSET)
+#define LPC17_USBDEV_CMDCODE (LPC17_USB_BASE+LPC17_USBDEV_CMDCODE_OFFSET)
+#define LPC17_USBDEV_CMDDATA (LPC17_USB_BASE+LPC17_USBDEV_CMDDATA_OFFSET)
/* USB transfer registers */
@@ -281,9 +270,17 @@
/* Register bit definitions *********************************************************/
/* USB Host Controller (OHCI) *******************************************************/
-/* UM10360: "Refer to the OHCI specification document on the Compaq website for
- * register definitions"
- */
+/* See include/nuttx/ohci.h */
+
+/* Module ID/Revision ID */
+
+#define USBHOST_MODID_VER_SHIFT (0) /* Bits 0-7: Unique version number */
+#define USBHOST_MODID_VER_MASK (0xff << USBHOST_MODID_VER_SHIFT)
+#define USBHOST_MODID_REV_SHIFT (8) /* Bits 9-15: Unique revision number */
+#define USBHOST_MODID_REV_MASK (0xff << USBHOST_MODID_REV_SHIFT)
+#define USBHOST_MODID_3505_SHIFT (16) /* Bits 16-31: 0x3505 */
+#define USBHOST_MODID_3505_MASK (0xffff << USBHOST_MODID_3505_SHIFT)
+# define USBHOST_MODID_3505 (0x3505 << USBHOST_MODID_3505_SHIFT)
/* USB OTG Controller ***************************************************************/
/* OTG registers:
diff --git a/include/nuttx/ohci.h b/include/nuttx/ohci.h
new file mode 100755
index 0000000000000000000000000000000000000000..173ba0718245685691d64529e77a64610d65f70a
--- /dev/null
+++ b/include/nuttx/ohci.h
@@ -0,0 +1,430 @@
+/****************************************************************************
+ * include/nuttx/ohci.h
+ *
+ * Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * References: "OpenHCI Open Host Controller Interface Specification
+ * for USB," Release 1.0a, Compaq, Microsoft, National Semiconductor,
+ * September 14, 1999.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __INCLUDE_NUTTX_OHCI_H
+#define __INCLUDE_NUTTX_OHCI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register offsets *********************************************************/
+/* Control and status registers (section 7.1) */
+
+#define OHCI_HCIREV_OFFSET 0x0000 /* HcRevision: Version of HCI specification */
+#define OHCI_CTRL_OFFSET 0x0004 /* HcControl: HC control */
+#define OHCI_CMDST_OFFSET 0x0008 /* HcCommandStatus: HC command status */
+#define OHCI_INTST_OFFSET 0x000c /* HcInterruptStatus: HC interrupt status */
+#define OHCI_INTEN_OFFSET 0x0010 /* HcInterruptEnable: HC interrupt enable */
+#define OHCI_INTDIS_OFFSET 0x0014 /* HcInterruptDisable: HC interrupt disable */
+
+/* Memory pointer registers (section 7.2) */
+
+#define OHCI_HCCA_OFFSET 0x0018 /* HcHCCA: HC communication area */
+#define OHCI_PERED_OFFSET 0x001c /* HcPeriodCurrentED: Current isoc or int endpoint desc */
+#define OHCI_CTRLHEADED_OFFSET 0x0020 /* HcControlHeadED: First EP desc in the control list */
+#define OHCI_CTRLED_OFFSET 0x0024 /* HcControlCurrentED: Current EP desc in the control list */
+#define OHCI_BULKHEADED_OFFSET 0x0028 /* HcBulkHeadED: First EP desc in the bulk list */
+#define OHCI_BULKED_OFFSET 0x002c /* HcBulkCurrentED: Current EP desc in the bulk list */
+#define OHCI_DONEHEAD_OFFSET 0x0030 /* HcDoneHead: Last transfer desc added to DONE queue */
+
+/* Frame counter registers (section 7.3) */
+
+#define OHCI_FMINT_OFFSET 0x0034 /* HcFmInterval: Bit time interval that would not cause overrun */
+#define OHCI_FMREM_OFFSET 0x0038 /* HcFmRemaining: Bit time remaining in current frame */
+#define OHCI_FMNO_OFFSET 0x003c /* HcFmNumber: Frame number counter */
+#define OHCI_PERSTART_OFFSET 0x0040 /* HcPeriodicStart: Time to start processing periodic list */
+
+/* Root hub registers (section 7.4) */
+
+#define OHCI_LSTHRES_OFFSET 0x0044 /* HcLSThreshold: Commit to transfer threshold */
+#define OHCI_RHDESCA_OFFSET 0x0048 /* HcRhDescriptorA: Describes root hub (part A) */
+#define OHCI_RHDESCB_OFFSET 0x004c /* HcRhDescriptorB: Describes root hub (part B) */
+#define OHCI_RHSTATUS_OFFSET 0x0050 /* HcRhStatus: Root hub status */
+
+#define OHCI_MAX_RHPORT 15 /* Maximum number of OHCI root hub ports */
+
+#define OHCI_RHPORTST_OFFSET(n) (0x0054+(((n)-1) << 2))
+#define OHCI_RHPORTST1_OFFSET 0x0054 /* HcRhPort1Status: Root hub port status 1 */
+#define OHCI_RHPORTST2_OFFSET 0x0058 /* HcRhPort2Status: Root hub port status 2 */
+#define OHCI_RHPORTST3_OFFSET 0x005c /* HcRhPort3Status: Root hub port status 3 */
+#define OHCI_RHPORTST4_OFFSET 0x0060 /* HcRhPort4Status: Root hub port status 4 */
+#define OHCI_RHPORTST5_OFFSET 0x0064 /* HcRhPort5Status: Root hub port status 5 */
+#define OHCI_RHPORTST6_OFFSET 0x0068 /* HcRhPort6Status: Root hub port status 6 */
+#define OHCI_RHPORTST7_OFFSET 0x006c /* HcRhPort7Status: Root hub port status 7 */
+#define OHCI_RHPORTST8_OFFSET 0x0070 /* HcRhPort8Status: Root hub port status 8 */
+#define OHCI_RHPORTST9_OFFSET 0x0074 /* HcRhPort9Status: Root hub port status 9 */
+#define OHCI_RHPORTST10_OFFSET 0x0078 /* HcRhPort10Status: Root hub port status 10 */
+#define OHCI_RHPORTST11_OFFSET 0x007c /* HcRhPort11Status: Root hub port status 11 */
+#define OHCI_RHPORTST12_OFFSET 0x0080 /* HcRhPort12Status: Root hub port status 12 */
+#define OHCI_RHPORTST13_OFFSET 0x0084 /* HcRhPort13Status: Root hub port status 13 */
+#define OHCI_RHPORTST14_OFFSET 0x0088 /* HcRhPort14Status: Root hub port status 14 */
+#define OHCI_RHPORTST15_OFFSET 0x008c /* HcRhPort15Status: Root hub port status 15 */
+
+/* Register bit definitions *************************************************/
+
+/* HcRevision: Version of HCI specification (7.1.1) */
+
+#define OHCI_HCIREV_SHIFT (0) /* Bits 0-7: HCI spec version (BCD) */
+#define OHCI_HCIREV_MASK (0xff << OHCI_HCIREV_SHIFT)
+
+/* HcControl: HC control (7.1.2) */
+
+#define OHCI_CTRL_CBSR (3 << 0) /* Bit 0: Control/bulk service ratio */
+#define OHCI_CTRL_PLE (1 << 2) /* Bit 1: Periodic list enable */
+#define OHCI_CTRL_IE (1 << 3) /* Bit 2: Isochronous enable */
+#define OHCI_CTRL_CLE (1 << 4) /* Bit 3: Control list enable */
+#define OHCI_CTRL_BLE (1 << 5) /* Bit 4: Bulk list enable */
+#define OHCI_CTRL_HCFS_SHIFT (6) /* Bits 6-7: Host controller functional state */
+#define OHCI_CTRL_HCFS_MASK (3 << OHCI_CTRL_HCFS_MASK)
+# define OHCI_CTRL_HCFS_RESET (0 << OHCI_CTRL_HCFS_MASK)
+# define OHCI_CTRL_HCFS_RESUME (1 << OHCI_CTRL_HCFS_MASK)
+# define OHCI_CTRL_HCFS_OPER (2 << OHCI_CTRL_HCFS_MASK)
+# define OHCI_CTRL_HCFS_SUSPEND (3 << OHCI_CTRL_HCFS_MASK)
+#define OHCI_CTRL_IR (1 << 8) /* Bit 8: Interrupt routing */
+#define OHCI_CTRL_RWC (1 << 9) /* Bit 9: Remote wakeup connected */
+#define OHCI_CTRL_RWE (1 << 10) /* Bit 10: Remote wakeup enable */
+ /* Bits 11-31: Reserved */
+
+/* HcCommandStatus: HC command status (7.1.3) */
+#define OHCI_CMDST_
+
+#define OHCI_CMDST_HCR (1 << 0) /* Bit 0: Host controller reset */
+#define OHCI_CMDST_CLF (1 << 1) /* Bit 1: Control list filled */
+#define OHCI_CMDST_BLF (1 << 2) /* Bit 2: Bulk list filled */
+#define OHCI_CMDST_OCR (1 << 3) /* Bit 3: Ownership change request */
+ /* Bits 4-15: Reserved */
+#define OHCI_CMDST_SOC (3 << 16) /* Bit 16: Scheduling overrun count */
+ /* Bits 17-31: Reserved */
+
+/* HcInterruptStatus: HC interrupt status (7.1.4),
+ * HcInterruptEnable: HC interrupt enable (7.1.5), and
+ * HcInterruptDisable: HC interrupt disable (7.1.6)
+ */
+
+#define OHCI_INT_SO (1 << 0) /* Bit 0: Scheduling overrun */
+#define OHCI_INT_WDH (1 << 1) /* Bit 1: Writeback done head */
+#define OHCI_INT_SF (1 << 2) /* Bit 2: Start of frame */
+#define OHCI_INT_RD (1 << 3) /* Bit 3: Resume detected */
+#define OHCI_INT_UE (1 << 4) /* Bit 4: Unrecoverable error */
+#define OHCI_INT_FNO (1 << 5) /* Bit 5: Frame number overflow */
+#define OHCI_INT_RHSC (1 << 6) /* Bit 6: Root hub status change */
+ /* Bits 7-29: Reserved */
+#define OHCI_INT_OC (1 << 30) /* Bit 30: Ownership change */
+#define OHCI_INT_MIE (1 << 31) /* Bit 31: Master interrupt enable
+ * (Enable/disable only) */
+/* HcHCCA: HC communication area (7.2.1):
+ *
+ * 32-bits aligned to 256 byte boundary.
+ */
+
+/* HcPeriodCurrentED: Current isoc or int endpoint desc (7.2.2),
+ * HcControlHeadED: First EP desc in the control list (7.2.3),
+ * HcControlCurrentED: Current EP desc in the control list (7.2.4),
+ * HcBulkHeadED: First EP desc in the bulk list (7.2.5),
+ * HcBulkCurrentED: Current EP desc in the bulk list (7.2.6), and
+ * HcDoneHead: Last transfer desc added to DONE queue (7.2.7):
+ *
+ * All 32-bits aligned to an 8-byte boundary
+ */
+
+/* HcFmInterval: Bit time interval that would not cause overrun (7.3.1) */
+
+#define OHCI_FMINT_FI_SHIFT (0) /* Bits 0-13: Frame interval */
+#define OHCI_FMINT_FI_MASK (0x3fff << OHCI_FMINT_FI_SHIFT)
+ /* Bits 14-15: Reserved */
+#define OHCI_FMINT_FSMPS_SHIFT (16) /* Bits 16-30: FS largest packet data */
+#define OHCI_FMINT_FSMPS_MASK (0x7fff << OHCI_FMINT_FSMPS_SHIFT)
+#define OHCI_FMINT_FIT (1 << 31) /* Bit 31: Frame interval toggle */
+
+/* HcFmRemaining: Bit time remaining in current frame (7.3.2) */
+
+#define OHCI_FMREM_
+#define OHCI_FMREM_FR_SHIFT (0) /* Bits 0-13: Frame remaining */
+#define OHCI_FMREM_FR_MASK (0x3fff << OHCI_FMREM_FR_SHIFT)
+ /* Bits 16-30: Reserved */
+#define OHCI_FMINT_FRT (1 << 31) /* Bit 31: Frame remaining toggle */
+
+/* HcFmNumber: Frame number counter (7.3.3) */
+
+#define OHCI_FMNO_
+#define OHCI_FMNO_FI_SHIFT (0) /* Bits 0-15: Frame number */
+#define OHCI_FMNO_FI_MASK (0xffff << OHCI_FMINT_FI_SHIFT)
+ /* Bits 16-31: Reserved */
+/* HcPeriodicStart: Time to start processing periodic list (7.3.4) */
+
+#define OHCI_PERSTART_SHIFT (0) /* Bits 0-13: Periodic start */
+#define OHCI_PERSTART_MASK (0x3fff << OHCI_PERSTART_SHIFT)
+ /* Bits 14-31: Reserved */
+/* HcLSThreshold: Commit to transfer threshold (7.3.5) */
+
+#define OHCI_LSTHRES_SHIFT (0) /* Bits 0-11: LS threshold */
+#define OHCI_LSTHRES_MASK (0x0fff << OHCI_PERSTART_SHIFT)
+ /* Bits 12-31: Reserved */
+/* HcRhDescriptorN: Describes root hub (7.4.1) */
+
+#define OHCI_RHDESCA_NDP_SHIFT (0) /* Bits 0-7: Number downstream ports */
+#define OHCI_RHDESCA_NDP_MASK (0xff << OHCI_RHDESCA_NDP_SHIFT)
+#define OHCI_RHDESCA_PSM (1 << 8) /* Bit 8: Power switching mode */
+#define OHCI_RHDESCA_NPS (1 << 9) /* Bit 9: No power switching */
+#define OHCI_RHDESCA_DT (1 << 10) /* Bit 10: Device type */
+#define OHCI_RHDESCA_OCPM (1 << 11) /* Bit 11: Over current protection mode */
+#define OHCI_RHDESCA_NOCP (1 << 12) /* Bit 12: No over current protection */
+ /* Bits 13-23: Reserved */
+#define OHCI_RHDESCA_POTPGT_SHIFT (24) /* Bits 24-31: Power on to power good time */
+#define OHCI_RHDESCA_POTPGT_MASK (0xff << OHCI_RHDESCA_POTPGT_SHIFT)
+
+/* HcRhDescriptorB: Describes root hub (part B) (7.4.2) */
+
+#define OHCI_RHDESCB_DR_SHIFT (0) /* Bits 0-15: Device removable */
+#define OHCI_RHDESCB_DR_MASK (0xffff << OHCI_RHDESCB_DR_SHIFT)
+# define OHCI_RHDESCB_ATTACHED(n) (1 << (OHCI_RHDESCB_DR_SHIFT+(n)))
+#define OHCI_RHDESCB_PPCM_SHIFT (16) /* Bits 16-31: Port power control mask */
+#define OHCI_RHDESCB_PPCM_MASK (0xffff << OHCI_RHDESCB_PPCM_SHIFT)
+# define OHCI_RHDESCB_POWERED(n) (1 << (OHCI_RHDESCB_DR_SHIFT+(n)))
+
+/* HcRhStatus: Root hub status (7.4.3) */
+
+#define OHCI_RHSTATUS_
+#define OHCI_RHSTATUS_LPS (1 << 0) /* Bit 0: Local power status */
+#define OHCI_RHSTATUS_OCI (1 << 1) /* Bit 1: Over current indicator */
+ /* Bits 2-14: Reserved */
+#define OHCI_RHSTATUS_DRWE (1 << 15) /* Bit 15: Device remote wakeup enable */
+#define OHCI_RHSTATUS_LPSC (1 << 16) /* Bit 16: Local power status change */
+#define OHCI_RHSTATUS_OCIC (1 << 17) /* Bit 17: Overcurrent indicator change */
+ /* Bits 18-30: Reserved */
+#define OHCI_RHSTATUS_CRWE (1 << 31) /* Bit 31: Clear remote wakeup enable */
+
+/* HcRhPortStatus: Root hub port status (7.4.4) */
+
+#define OHCI_RHPORTST_LPS (1 << 0) /* Bit 0: Local power status */
+#define OHCI_RHPORTST_OCI (1 << 1) /* Bit 1: Over current indicator */
+ /* Bits 2-14: Reserved */
+#define OHCI_RHPORTST_DRWE (1 << 15) /* Bit 15: Device remote wakeup enable */
+#define OHCI_RHPORTST_LPSC (1 << 16) /* Bit 16: Local power status change */
+#define OHCI_RHPORTST_OCIC (1 << 17) /* Bit 17: Overcurrent indicator change */
+ /* Bits 18-30: Reserved */
+#define OHCI_RHPORTST_CRWE (1 << 31) /* Bit 31: Clear remote wakeup enable */
+
+#define OHCI_RHPORTST_CCS (1 << 0) /* Bit 0: Current connect status */
+#define OHCI_RHPORTST_PES (1 << 1) /* Bit 1: Port enable status*/
+#define OHCI_RHPORTST_PSS (1 << 2) /* Bit 2: Port suspend status */
+#define OHCI_RHPORTST_POCI (1 << 3) /* Bit 3: Port over current indicator */
+#define OHCI_RHPORTST_PRS (1 << 4) /* Bit 4: Port reset status */
+ /* Bits 5-7: Reserved */
+#define OHCI_RHPORTST_PPS (1 << 8) /* Bit 8: Port power status */
+#define OHCI_RHPORTST_LSDA (1 << 9) /* Bit 9: Low speed device attached */
+ /* Bits 10-15: Reserved */
+#define OHCI_RHPORTST_CSC (1 << 16) /* Bit 16: Connect status change */
+#define OHCI_RHPORTST_PESC (1 << 17) /* Bit 17: Port enable status change */
+#define OHCI_RHPORTST_PSSC (1 << 18) /* Bit 18: Port suspend status change */
+#define OHCI_RHPORTST_OCIC (1 << 19) /* Bit 19: Port over current indicator change */
+#define OHCI_RHPORTST_PRSC (1 << 20) /* Bit 20: Port reset status change */
+ /* Bits 21-31: Reserved */
+
+/* Transfer Descriptors *****************************************************/
+/* General Transfer Descriptor Offsets (4.3.1) */
+
+#define GTD_STATUS_OFFSET (0x00) /* TD status bits */
+#define GTD_CBP_OFFSET (0x04) /* Current Buffer Pointer (CBP) */
+#define GTD_NEXTTD_OFFSET (0x08) /* Next TD (NextTD) */
+#define GTD_BE_OFFSET (0x0c) /* Buffer End (BE) */
+
+/* General Transfer Descriptor Bit Definitions */
+ /* Bits 0-17: Reserved */
+#define GTD_STATUS_R (1 << 18) /* Bit 18: Buffer rounding */
+#define GTD_STATUS_DP_SHIFT (19) /* Bits 19-20: Direction/PID */
+#define GTD_STATUS_DP_MASK (3 << GTD_STATUS_DP_SHIFT)
+# define GTD_STATUS_DP_SETUP (0 << GTD_STATUS_DP_SHIFT) /* To endpoint */
+# define GTD_STATUS_DP_OUT (1 << GTD_STATUS_DP_SHIFT) /* To endpoint */
+# define GTD_STATUS_DP_IN (2 << GTD_STATUS_DP_SHIFT) /* From endpoint */
+#define GTD_STATUS_DI_SHIFT (21) /* Bits 21-23: Delay input */
+#define GTD_STATUS_DI_MASK (7 << GTD_STATUS_DI_SHIFT)
+#define GTD_STATUS_T_SHIFT (24) /* Bits 24-25: Data Toggle */
+#define GTD_STATUS_T_MASK (3 << GTD_STATUS_T_SHIFT)
+# define GTD_STATUS_T_TOGGLE (0 << GTD_STATUS_T_SHIFT)
+# define GTD_STATUS_T_DATA0 (2 << GTD_STATUS_T_SHIFT)
+# define GTD_STATUS_T_DATA1 (3 << GTD_STATUS_T_SHIFT)
+#define GTD_STATUS_EC_SHIFT (26) /* Bits 26-27: Error count */
+#define GTD_STATUS_EC_MASK (3 << GTD_STATUS_EC_SHIFT)
+#define GTD_STATUS_CC_SHIFT (28) /* Bits 28-31: Condition code */
+#define GTD_STATUS_CC_MASK (15 << GTD_STATUS_CC_SHIFT)
+
+/* Isochronous Transfer Descriptor Offsets (4.3.2) */
+
+#define ITD_STATUS_OFFSET (0x00) /* TD status bits */
+#define ITD_BP0_OFFSET (0x04) /* Buffer page 0 (BP0) */
+#define ITD_NEXTTD_OFFSET (0x08) /* Next TD (NextTD) */
+#define ITD_BE_OFFSET (0x0c) /* Buffer End (BE) */
+
+#define ITD_NPSW (8)
+#define ITD_PSW0_OFFSET (0x10) /* Offset0/PSW0 */
+#define ITD_PSW1_OFFSET (0x12) /* Offset1/PSW1 */
+#define ITD_PSW2_OFFSET (0x14) /* Offset2/PSW2 */
+#define ITD_PSW3_OFFSET (0x16) /* Offset3/PSW3 */
+#define ITD_PSW4_OFFSET (0x18) /* Offset4/PSW4 */
+#define ITD_PSW5_OFFSET (0x1a) /* Offset5/PSW5 */
+#define ITD_PSW6_OFFSET (0x1c) /* Offset6/PSW6 */
+#define ITD_PSW7_OFFSET (0x1e) /* Offset7/PSW7 */
+
+/* Condition codes (Table 4-7) */
+
+#define TD_CC_NOERROR 0x00
+#define TD_CC_CRC 0x01
+#define TD_CC_BITSTUFFING 0x02
+#define TD_CC_DATATOGGLEMISMATCH 0x03
+#define TD_CC_STALL 0x04
+#define TD_CC_DEVNOTRESPONDING 0x05
+#define TD_CC_PIDCHECKFAILURE 0x06
+#define TD_CC_UNEXPECTEDPID 0x07
+#define TD_CC_DATAOVERRUN 0x08
+#define TD_CC_DATAUNDERRUN 0x09
+#define TD_CC_BUFFEROVERRUN 0x0c
+#define TD_CC_BUFFERUNDERRUN 0x0d
+#define TD_CC_NOTACCESSED 0x0f
+
+/* Host Controller Communications Area Format (4.4.1) ***********************/
+
+/* HccaInterrruptTable: 32x32-bit pointers to interrupt EDs */
+
+#define HCCA_INTTBL_OFFSET (0x00)
+#define HCCA_INTTBL_WSIZE (32)
+#define HCCA_INTTBL_BSIZE (HCCA_INTTBL_WSIZE*4)
+
+/* HccaFrameNumber: Current frame number */
+
+#define HCCA_FMNO_OFFSET (0x80)
+#define HCCA_FMNO_BSIZE (2)
+
+/* HccaPad1: Zero when frame no. updated */
+
+#define HCCA_PAD1_OFFSET (0x82)
+#define HCCA_PAD1_BSIZE (2)
+
+/* HccaDoneHead: When the HC reaches the end of a frame and its deferred
+ * interrupt register is 0, it writes the current value of its HcDoneHead to
+ * this location and generates an interrupt.
+ */
+
+#define HCCA_DONEHEAD_OFFSET (0x84)
+#define HCCA_DONEHEAD_BSIZE (4)
+
+/* 0x88: 116 bytes reserved */
+
+#define HCCA_RESERVED_OFFSET (0x88)
+#define HCCA_RESERVED_BSIZE (116)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* General Transfer Descriptor (4.3.1) */
+
+struct ohci_gtd_s
+{
+ uint32_t status; /* TD status bits */
+ uint32_t cbp; /* Current Buffer Pointer (CBP) */
+ uint32_t nexttd; /* Next TD (NextTD) */
+ uint32_t be; /* Buffer End (BE) */
+};
+
+/* Isochronous Transfer Descriptor Offsets (4.3.2) */
+
+struct ohci_itd_s
+{
+ uint32_t status; /* TD status bits */
+ uint32_t bp0; /* Buffer page 0 (BP0 */
+ uint32_t nexttd; /* Next TD (NextTD) */
+ uint32_t be; /* Buffer End (BE) */
+ uint16_t psw[ITD_NPSW]; /* Offset/PSW */
+};
+
+/* Host Controller Communications Area Format (4.4.1) */
+
+struct ohci_hcca_s
+{
+ /* HccaInterrruptTable: 32x32-bit pointers to interrupt EDs */
+
+ uint32_t inttbl[HCCA_INTTBL_WSIZE];
+
+ /* HccaFrameNumber: Current frame number and
+ * HccaPad1: Zero when frame no. updated
+ */
+
+ uint16_t fmno;
+ uint16_t pad1;
+
+ /* HccaDoneHead: When the HC reaches the end of a frame and its deferred
+ * interrupt register is 0, it writes the current value of its HcDoneHead to
+ * this location and generates an interrupt.
+ */
+
+ uint32_t donehead;
+ uint8_t reserved[HCCA_RESERVED_BSIZE];
+ uint32_t extra;
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __INCLUDE_NUTTX_OHCI_H */