diff --git a/arch/arm/src/stm32/stm32_uart.h b/arch/arm/src/stm32/stm32_uart.h
index 37a157219502366a791858363313889e0e984344..6a1213ca10ddb4c8474f6c309fb2d15773557766 100755
--- a/arch/arm/src/stm32/stm32_uart.h
+++ b/arch/arm/src/stm32/stm32_uart.h
@@ -91,11 +91,21 @@
 #endif
 
 #if STM32_NUSART > 3
-#  warning "Check UART4 register definitions"
+#  define STM32_UART4_SR          (STM32_UART4_BASE+STM32_USART_SR_OFFSET)
+#  define STM32_UART4_DR          (STM32_UART4_BASE+STM32_USART_DR_OFFSET)
+#  define STM32_UART4_BRR         (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
+#  define STM32_UART4_CR1         (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
+#  define STM32_UART4_CR2         (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
+#  define STM32_UART4_CR3         (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
 #endif
 
 #if STM32_NUSART > 4
-#  warning "Check UART5 register definitions"
+#  define STM32_UART5_SR          (STM32_UART5_BASE+STM32_USART_SR_OFFSET)
+#  define STM32_UART5_DR          (STM32_UART5_BASE+STM32_USART_DR_OFFSET)
+#  define STM32_UART5_BRR         (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
+#  define STM32_UART5_CR1         (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
+#  define STM32_UART5_CR2         (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
+#  define STM32_UART5_CR3         (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
 #endif
 
 /* Register Bitfield Definitions ****************************************************/
diff --git a/configs/stm3210e-eval/ostest/defconfig b/configs/stm3210e-eval/ostest/defconfig
index 8822f6de904d0a6fef9d6a37bc2d7f6f186d9f14..49559dc1a0661bc33332514ee9852ca7108c7e79 100755
--- a/configs/stm3210e-eval/ostest/defconfig
+++ b/configs/stm3210e-eval/ostest/defconfig
@@ -112,27 +112,50 @@ CONFIG_STM32_BUILDROOT=y
 CONFIG_USART1_DISABLE=n
 CONFIG_USART2_DISABLE=y
 CONFIG_USART3_DISABLE=y
+CONFIG_USART4_DISABLE=y
+CONFIG_USART5_DISABLE=y
+
 CONFIG_USART1_SERIAL_CONSOLE=y
 CONFIG_USART2_SERIAL_CONSOLE=n
 CONFIG_USART3_SERIAL_CONSOLE=n
+CONFIG_USART4_SERIAL_CONSOLE=n
+CONFIG_USART5_SERIAL_CONSOLE=n
+
 CONFIG_USART1_TXBUFSIZE=256
 CONFIG_USART2_TXBUFSIZE=256
 CONFIG_USART3_TXBUFSIZE=256
+CONFIG_USART4_TXBUFSIZE=256
+CONFIG_USART5_TXBUFSIZE=256
+
 CONFIG_USART1_RXBUFSIZE=256
 CONFIG_USART2_RXBUFSIZE=256
 CONFIG_USART3_RXBUFSIZE=256
+CONFIG_USART4_RXBUFSIZE=256
+CONFIG_USART5_RXBUFSIZE=256
+
 CONFIG_USART1_BAUD=115200
 CONFIG_USART2_BAUD=115200
 CONFIG_USART3_BAUD=115200
+CONFIG_USART4_BAUD=115200
+CONFIG_USART5_BAUD=115200
+
 CONFIG_USART1_BITS=8
 CONFIG_USART2_BITS=8
 CONFIG_USART3_BITS=8
+CONFIG_USART4_BITS=8
+CONFIG_USART5_BITS=8
+
 CONFIG_USART1_PARITY=0
 CONFIG_USART2_PARITY=0
 CONFIG_USART3_PARITY=0
+CONFIG_USART4_PARITY=0
+CONFIG_USART5_PARITY=0
+
 CONFIG_USART1_2STOP=0
 CONFIG_USART2_2STOP=0
 CONFIG_USART3_2STOP=0
+CONFIG_USART4_2STOP=0
+CONFIG_USART5_2STOP=0
 
 #
 # STM32F103Z specific SSI device driver settings