diff --git a/arch/x86/include/i486/arch.h b/arch/x86/include/i486/arch.h
index 5910f08a15e00624830c7cfbe137ab3a6576597c..c5e4adad555e55f723699220dbeb29e2044bd186 100755
--- a/arch/x86/include/i486/arch.h
+++ b/arch/x86/include/i486/arch.h
@@ -55,31 +55,249 @@
/* FLAGS bits */
-#define X86_FLAGS_CF (1 << 0) /* Bit 0: Carry Flag */
- /* Bit 1: Reserved */
-#define X86_FLAGS_PF (1 << 2) /* Bit 2: Parity Flag */
- /* Bit 3: Reserved */
-#define X86_FLAGS_AF (1 << 4) /* Bit 4: Auxillary carry Flag */
- /* Bit 5: Reserved */
-#define X86_FLAGS_ZF (1 << 6) /* Bit 6: Zero Flag */
-#define X86_FLAGS_SF (1 << 7) /* Bit 7: Sign Flag */
-#define X86_FLAGS_TF (1 << 8) /* Bit 8: Trap Flag */
-#define X86_FLAGS_IF (1 << 9) /* Bit 9: Interrupt Flag */
-#define X86_FLAGS_DF (1 << 10) /* Bit 10: Direction Flag */
-#define X86_FLAGS_OF (1 << 11) /* Bit 11: Overflow Flag */
-#define X86_FLAGS_IOPL_SHIFT (12) /* Bits 12-13: IOPL mask (286+ only)*/
-#define X86_FLAGS_IOPL_MASK (3 << X86_FLAGS_IOPL_SHIFT)
-#define X86_FLAGS_NT (1 << 14) /* Bit 14: Nested Task */
- /* Bit 15: Reserved */
+#define X86_FLAGS_CF (1 << 0) /* Bit 0: Carry Flag */
+ /* Bit 1: Reserved */
+#define X86_FLAGS_PF (1 << 2) /* Bit 2: Parity Flag */
+ /* Bit 3: Reserved */
+#define X86_FLAGS_AF (1 << 4) /* Bit 4: Auxillary carry Flag */
+ /* Bit 5: Reserved */
+#define X86_FLAGS_ZF (1 << 6) /* Bit 6: Zero Flag */
+#define X86_FLAGS_SF (1 << 7) /* Bit 7: Sign Flag */
+#define X86_FLAGS_TF (1 << 8) /* Bit 8: Trap Flag */
+#define X86_FLAGS_IF (1 << 9) /* Bit 9: Interrupt Flag */
+#define X86_FLAGS_DF (1 << 10) /* Bit 10: Direction Flag */
+#define X86_FLAGS_OF (1 << 11) /* Bit 11: Overflow Flag */
+#define X86_FLAGS_IOPL_SHIFT (12) /* Bits 12-13: IOPL mask (286+ only)*/
+#define X86_FLAGS_IOPL_MASK (3 << X86_FLAGS_IOPL_SHIFT)
+#define X86_FLAGS_NT (1 << 14) /* Bit 14: Nested Task */
+ /* Bit 15: Reserved */
/* EFLAGS bits (Extend the basic FLAGS bit definitions) */
-#define X86_EFLAGS_RF (1 << 16) /* Bit 16: Resume Flag (386+ only) */
-#define X86_EFLAGS_VM (1 << 17) /* Bit 17: Virtual Mode (386+ only) */
-#define X86_EFLAGS_AC (1 << 18) /* Bit 18: Alignment Check (486SX+ only) */
-#define X86_EFLAGS_VIF (1 << 19) /* Bit 19: Virtual Interrupt Flag (Pentium+) */
-#define X86_EFLAGS_VIP (1 << 20) /* Bit 20: Virtual Interrupt Pending (Pentium+) */
-#define X86_EFLAGS_ID (1 << 21) /* Bit 21: CPUID detection flag (Pentium+) */
+#define X86_EFLAGS_RF (1 << 16) /* Bit 16: Resume Flag (386+ only) */
+#define X86_EFLAGS_VM (1 << 17) /* Bit 17: Virtual Mode (386+ only) */
+#define X86_EFLAGS_AC (1 << 18) /* Bit 18: Alignment Check (486SX+ only) */
+#define X86_EFLAGS_VIF (1 << 19) /* Bit 19: Virtual Interrupt Flag (Pentium+) */
+#define X86_EFLAGS_VIP (1 << 20) /* Bit 20: Virtual Interrupt Pending (Pentium+) */
+#define X86_EFLAGS_ID (1 << 21) /* Bit 21: CPUID detection flag (Pentium+) */
+
+/* Programmable Interrupt Controller (PIC) */
+
+/* Operational Control Words
+ *
+ * The first instruction the Operation Control Word 1 (OCW1) to set which
+ * IRQ's to mask and which IRQ's not to.
+ */
+
+#define PIC1_OCW1 0x20
+#define PIC2_OCW1 0xa0
+
+# define PIC1_OCW1_IRQ0 (1 << 0) /* IRQ0 System Timer */
+# define PIC1_OCW1_IRQ1 (1 << 1) /* IRQ1 Keyboard */
+# define PIC1_OCW1_IRQ2 (1 << 2) /* IRQ2 PIC2 */
+# define PIC1_OCW1_IRQ3 (1 << 3) /* IRQ3 Serial Port */
+# define PIC1_OCW1_IRQ4 (1 << 4) /* IRQ4 Serial Port */
+# define PIC1_OCW1_IRQ5 (1 << 5) /* IRQ5 Reserved/Sound Card */
+# define PIC1_OCW1_IRQ6 (1 << 6) /* IRQ6 Floppy Disk Controller */
+# define PIC1_OCW1_IRQ7 (1 << 7) /* IRQ7 Parallel Port */
+# define PIC1_OCW1_ALL
+
+# define PIC2_OCW1_IRQ8 (1 << 0) /* IRQ8 Real Time Clock */
+# define PIC2_OCW1_IRQ9 (1 << 1) /* IRQ9 Redirected IRQ2 */
+# define PIC2_OCW1_IRQ10 (1 << 2) /* IRQ10 Reserved */
+# define PIC2_OCW1_IRQ11 (1 << 3) /* IRQ11 Reserved */
+# define PIC2_OCW1_IRQ12 (1 << 4) /* IRQ12 PS/2 Mouse */
+# define PIC2_OCW1_IRQ13 (1 << 5) /* IRQ13 Maths Co-Processor */
+# define PIC2_OCW1_IRQ14 (1 << 6) /* IRQ14 Hard Disk Drive */
+# define PIC2_OCW1_IRQ15 (1 << 7) /* IRQ15 Reserved */
+# define PIC2_OCW1_ALL
+
+/* Operation Control Word 2 selects how the End of Interrupt (EOI) procedure
+ * works. The only thing of interest to us in this register is the non-
+ * specific EOI command, which we must send at the end of our ISR's.
+ */
+
+#define PIC1_OCW2 0x20
+#define PIC2_OCW2 0xa0
+
+# define PIC_OCW2_ACT_SHIFT (0)
+# define PIC_OCW2_ACT_SHIFT (7 << PIC_OCW2_ACT_SHIFT)
+# define PIC1_OCW2_ACT_IRQ0 (0 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 0 */
+# define PIC1_OCW2_ACT_IRQ1 (1 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 1 */
+# define PIC1_OCW2_ACT_IRQ2 (2 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 2 */
+# define PIC1_OCW2_ACT_IRQ3 (3 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 3 */
+# define PIC1_OCW2_ACT_IRQ4 (4 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 4 */
+# define PIC1_OCW2_ACT_IRQ5 (5 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 5 */
+# define PIC1_OCW2_ACT_IRQ6 (6 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 6 */
+# define PIC1_OCW2_ACT_IRQ7 (7 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 7 */
+
+# define PIC2_OCW2_ACT_IRQ8 (0 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 8 */
+# define PIC2_OCW2_ACT_IRQ9 (1 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 9 */
+# define PIC2_OCW2_ACT_IRQ10 (2 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 10 */
+# define PIC2_OCW2_ACT_IRQ11 (3 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 11 */
+# define PIC2_OCW2_ACT_IRQ12 (4 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 12 */
+# define PIC2_OCW2_ACT_IRQ13 (5 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 13 */
+# define PIC2_OCW2_ACT_IRQ14 (6 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 14 */
+# define PIC2_OCW2_ACT_IRQ15 (7 << PIC_OCW2_ACT_SHIFT) /* Act on IRQ 15 */
+
+# define PIC_OCW2_EOI_SHIFT (5)
+# define PIC_OCW2_EOI_SHIFT (7 << PIC_OCW2_EOI_SHIFT)
+# define PIC_OCW2_EOI_AUTO (0 << PIC_OCW2_EOI_SHIFT) /* Rotate in Auto EOI Mode (Clear) */
+# define PIC_OCW2_EOI_NONSPEC (1 << PIC_OCW2_EOI_SHIFT) /* Non Specific EOI */
+# define PIC_OCW2_EOI_SPEC (3 << PIC_OCW2_EOI_SHIFT) /* Specific EOI */
+# define PIC_OCW2_EOI_RAUTO (4 << PIC_OCW2_EOI_SHIFT) /* Rotate in Auto EOI Mode (Set) */
+# define PIC_OCW2_EOI_RNSPEC (5 << PIC_OCW2_EOI_SHIFT) /* Rotate on Non-Specific EOI */
+# define PIC_OCW2_EOI_PRIO (6 << PIC_OCW2_EOI_SHIFT) /* Set Priority Command (Use Bits 2:0) */
+# define PIC_OCW2_EOI_RSPEC (7 << PIC_OCW2_EOI_SHIFT) /* Rotate on Specific EOI (Use Bits 2:0) */
+
+/* Operation Control Word 3. Bits 0 and 1 bitsenable us to read the status
+ * of the Interrupt Request Register (IRR) and the In-Service Register (ISR).
+ * This is done by setting the appropriate bits correctly and reading the
+ * register at the Base Address.
+ *
+ * For example if we wanted to read the In-Service Register (ISR), then we
+ * would set both bits 1 and 0 to 1. The next read to the base register,
+ * (0x20 for PIC1 or 0xa0 for PIC2) will return the status of the In-Service
+ * Register.
+ */
+
+#define PIC1_OCW3 0x20
+#define PIC2_OCW3 0xa0
+
+# define PIC_OCW3_PCMD_SHIFT (0) /* Poll command */
+# define PIC_OCW3_PCMD_MASK (3 << PIC_OCW3_PCMD_SHIFT)
+# define PIC_OCW3_PCMD_IRR (2 << PIC_OCW3_PCMD_SHIFT) /* Next Read Returns Interrupt Request Register */
+# define PIC_OCW3_PCMD_ISR (3 << PIC_OCW3_PCMD_SHIFT) /* Next Read Returns In-Service Register */
+# define PIC_OCW3_POLLCMD (1 << 2) /* Poll command */
+# define PIC_OCW3_ONE (1 << 3) /* Must be set to 1 */
+# define PIC_OCW3_SM_SHIFT (5)
+# define PIC_OCW3_SM_SHIFT (3 << PIC_OCW3_SM_SHIFT)
+# define PIC_OCW3_RSM (2 << PIC_OCW3_SM_SHIFT) /* Reset Special Mask */
+# define PIC_OCW3_SSM (3 << PIC_OCW3_SM_SHIFT) /* Set Special Mask */
+
+/* If the PIC has been reset, it must be initialized with 2 to 4 Initialization
+ * Command Words (ICW) before it will accept and process Interrupt Requests. The
+ * following outlines the four possible Initialization Command Words.
+ */
+
+#define PIC1_ICW1 0x20
+#define PIC2_ICW1 0xa0
+
+# define PIC_ICW1_ICW4 (1 << 0) /* Will be Sending ICW4 (no ICW4) */
+# define PIC_ICW1_SINGLE (1 << 1) /* Single PIC (vs. Cascaded pics) */
+# define PIC_ICW1_INTERVAL (1 << 2) /* Call Address Interval of 4 (vs 8) */
+# define PIC_ICW1_LEVEL (1 << 3) /* Level Triggered Interrupts (vs Edge) */
+# define PIC_ICW1_ICW1 (1 << 4) /* Must be set to 1 for ICW1 */
+# define PIC_ICW1_VEC_SHIFT (5) /* Interrupt Vector Addresses for MCS-80/85 Mode */
+# define PIC_ICW1_VEC_MASK (7 << PIC_ICW1_VEC_SHIFT)
+
+/* Initialization Command Word 2 (ICW2) selects which vector information is
+ * released onto the bus, during the 2nd INTA Pulse. Using the 8086 mode,
+ * only bits 7:3 need to be used. This will be 00001000 (0x08) for PIC1 and
+ * 01110000 (0x70) for PIC2. If you wish to relocate the IRQ Vector Table,
+ * then you can use this register.
+ */
+
+#define PIC1_ICW2 0x21
+#define PIC2_ICW2 0xa1
+
+/* There are two different Initialization Command Word 3's. One is used, if
+ * the PIC is a master, while the other is used for slaves.
+ */
+
+#define PIC1_ICW3 0x21
+#define PIC2_ICW3 0xa1
+
+/* Master ICW3 */
+
+# define PIC1_ICW3_IRQ0 (1 << 0) /* IRQ0 is connected to a Slave */
+# define PIC1_ICW3_IRQ1 (1 << 1) /* IRQ1 is connected to a Slave */
+# define PIC1_ICW3_IRQ2 (1 << 2) /* IRQ2 is connected to a Slave */
+# define PIC1_ICW3_IRQ3 (1 << 3) /* IRQ3 is connected to a Slave */
+# define PIC1_ICW3_IRQ4 (1 << 4) /* IRQ4 is connected to a Slave */
+# define PIC1_ICW3_IRQ5 (1 << 5) /* IRQ5 is connected to a Slave */
+# define PIC1_ICW3_IRQ6 (1 << 6) /* IRQ6 is connected to a Slave */
+# define PIC1_ICW3_IRQ7 (1 << 7) /* IRQ7 is connected to a Slave */
+
+/* And for the slave device, the ICW3 below is used. */
+
+# define PIC_ICW3_SID_MASK (0) /* Slave ID */
+# define PIC_ICW3_SID_SHIFT (7 << PIC_ICW3_SID_MASK)
+# define PIC_ICW3_SID0 (0 << PIC_ICW3_SID_MASK) /* Slave 0 */
+# define PIC_ICW3_SID1 (1 << PIC_ICW3_SID_MASK) /* Slave 1 */
+# define PIC_ICW3_SID2 (2 << PIC_ICW3_SID_MASK) /* Slave 2 */
+# define PIC_ICW3_SID3 (3 << PIC_ICW3_SID_MASK) /* Slave 3 */
+# define PIC_ICW3_SID4 (4 << PIC_ICW3_SID_MASK) /* Slave 4 */
+# define PIC_ICW3_SID5 (5 << PIC_ICW3_SID_MASK) /* Slave 5 */
+# define PIC_ICW3_SID6 (6 << PIC_ICW3_SID_MASK) /* Slave 6 */
+# define PIC_ICW3_SID7 (7 << PIC_ICW3_SID_MASK) /* Slave 7 */
+
+#define PIC1_ICW4 0x21
+#define PIC2_ICW4 0xa1
+
+# define PIC_ICW4_FNM (1 << 4) /* Special Fully Nested Mode */
+# define PIC_ICW4_BMODE_SHIFT (2) /* Bufferd mode */
+# define PIC_ICW4_BMODE_MASK (3 << PIC_ICW4_BMODE_SHIFT)
+# define PIC_ICW4_BMODE_NON (0 << PIC_ICW4_BMODE_SHIFT) /* Non - Buffered Mode */
+# define PIC_ICW4_BMODE_SLAVE (2 << PIC_ICW4_BMODE_SHIFT) /* Buffered Mode - Slave */
+# define PIC_ICW4_BMODE_MSTR (3 << PIC_ICW4_BMODE_SHIFT) /* Buffered Mode - Master */
+# define PIC_ICW4_AEOI (1 << 1) /* Auto EOI */
+# define PIC_ICW4_808xMODE (1 << 0) /* 8086/8080 Mode (vs MCS-80/85) */
+
+/* Interrupt Mask Register */
+
+#define PIC1_IMR 0x21
+#define PIC2_IMR 0xa1
+
+# define PIC1_IMR_IRQ0 (1 << 0) /* IRQ0 System Timer */
+# define PIC1_IMR_IRQ1 (1 << 1) /* IRQ1 Keyboard */
+# define PIC1_IMR_IRQ2 (1 << 2) /* IRQ2 PIC2 */
+# define PIC1_IMR_IRQ3 (1 << 3) /* IRQ3 Serial Port */
+# define PIC1_IMR_IRQ4 (1 << 4) /* IRQ4 Serial Port */
+# define PIC1_IMR_IRQ5 (1 << 5) /* IRQ5 Reserved/Sound Card */
+# define PIC1_IMR_IRQ6 (1 << 6) /* IRQ6 Floppy Disk Controller */
+# define PIC1_IMR_IRQ7 (1 << 7) /* IRQ7 Parallel Port */
+# define PIC1_IMR_ALL 0xff
+
+# define PIC2_IMR_IRQ8 (1 << 0) /* IRQ8 Real Time Clock */
+# define PIC2_IMR_IRQ9 (1 << 1) /* IRQ9 Redirected IRQ2 */
+# define PIC2_IMR_IRQ10 (1 << 2) /* IRQ10 Reserved */
+# define PIC2_IMR_IRQ11 (1 << 3) /* IRQ11 Reserved */
+# define PIC2_IMR_IRQ12 (1 << 4) /* IRQ12 PS/2 Mouse */
+# define PIC2_IMR_IRQ13 (1 << 5) /* IRQ13 Maths Co-Processor */
+# define PIC2_IMR_IRQ14 (1 << 6) /* IRQ14 Hard Disk Drive */
+# define PIC2_IMR_IRQ15 (1 << 7) /* IRQ15 Reserved */
+# define PIC2_IMR_ALL 0xff
+
+/* Programmable Interrupt Timer Definitions */
+
+#define PIT_REG_COUNTER0 0x40
+#define PIT_REG_COUNTER1 0x41
+#define PIT_REG_COUNTER2 0x42
+#define PIT_REG_COMMAND 0x43
+
+/* PIT command bit defintions */
+
+# define PIT_OCW_BINCOUNT_BCD (1 << 0) /* vs binary */
+# define PIT_OCW_MODE_SHIFT (1)
+# define PIT_OCW_MODE_MASK (7 << PIT_OCW_MODE_SHIFT)
+# define PIT_OCW_MODE_TMCNT (0 << PIT_OCW_MODE_SHIFT) /* Terminal count */
+# define PIT_OCW_MODE_ONESHOT (1 << PIT_OCW_MODE_SHIFT) /* One shot */
+# define PIT_OCW_MODE_RATEGEN (2 << PIT_OCW_MODE_SHIFT) /* Rate gen */
+# define PIT_OCW_MODE_SQUARE (3 << PIT_OCW_MODE_SHIFT) /* Square wave generation */
+# define PIT_OCW_MODE_SWTRIG (4 << PIT_OCW_MODE_SHIFT) /* Software trigger */
+# define PIT_OCW_MODE_HWTRIG (5 << PIT_OCW_MODE_SHIFT) /* Hardware trigger */
+# define PIT_OCW_RL_SHIFT (4)
+# define PIT_OCW_RL_MASK (3 << PIT_OCW_RL_SHIFT)
+# define PIT_OCW_RL_LATCH (0 << PIT_OCW_RL_SHIFT)
+# define PIT_OCW_RL_LSBONLY (1 << PIT_OCW_RL_SHIFT)
+# define PIT_OCW_RL_MSBONLY (2 << PIT_OCW_RL_SHIFT)
+# define PIT_OCW_RL_DATA (3 << PIT_OCW_RL_SHIFT)
+# define PIT_OCW_COUNTER_SHIFT (6)
+# define PIT_OCW_COUNTER_MASK (3 << PIT_OCW_COUNTER_SHIFT)
+# define PIT_OCW_COUNTER_0 (0 << PIT_OCW_COUNTER_SHIFT)
+# define PIT_OCW_COUNTER_1 (1 << PIT_OCW_COUNTER_SHIFT)
+# define PIT_OCW_COUNTER_2 (2 << PIT_OCW_COUNTER_SHIFT)
/****************************************************************************
* Public Types
diff --git a/arch/x86/src/qemu/qemu_irq.c b/arch/x86/src/i486/up_irq.c
similarity index 70%
rename from arch/x86/src/qemu/qemu_irq.c
rename to arch/x86/src/i486/up_irq.c
index b92db7882263cbd98328fb70f4fc6f95debfc98a..33a9130d5314b42d3ab716e1104948ba62e4f665 100755
--- a/arch/x86/src/qemu/qemu_irq.c
+++ b/arch/x86/src/i486/up_irq.c
@@ -1,6 +1,6 @@
/****************************************************************************
- * arch/x86/src/qemu/qemu_irq.c
- * arch/x86/src/chip/qemu_irq.c
+ * arch/x86/src/i486/up_irq.c
+ * arch/x86/src/chip/up_irq.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -113,27 +113,31 @@ static void up_remappic(void)
{
/* Mask interrupts from PIC */
- idt_outb(0xff, 0x21);
- idt_outb(0xff, 0xA1);
+ idt_outb(PIC1_IMR_ALL, PIC1_IMR);
+ idt_outb(PIC2_IMR_ALL, PIC2_IMR);
- /* Remap the irq table for primary */
+ /* If the PIC has been reset, it must be initialized with 2 to 4 Initialization
+ * Command Words (ICW) before it will accept and process Interrupt Requests. The
+ * following outlines the four possible Initialization Command Words.
+ */
- idt_outb(0x11, 0x20);
- idt_outb(0x20, 0x21);
- idt_outb(0x04, 0x21);
- idt_outb(0x01, 0x21);
-
- /* Remap irq for slave */
+ /* Remap the irq table for primary:
+ *
+ * ICW1 - We will be sending ICW4
+ * ICW2 - Address
+ * ICW3 */
- idt_outb(0x11, 0xA0);
- idt_outb(0x28, 0xA1);
- idt_outb(0x02, 0xA1);
- idt_outb(0x01, 0xA1);
+ idt_outb(PIC_ICW1_ICW4|PIC_ICW1_ICW1, PIC1_ICW1);
+ idt_outb(0x20, PIC1_ICW2);
+ idt_outb(PIC1_ICW3_IRQ2, PIC1_ICW3);
+ idt_outb(PIC_ICW4_808xMODE, PIC1_ICW4);
- /* Enable IRQ0 on the master with the mask */
+ /* Remap irq for slave */
- idt_outb( 0xff, 0xA1);
- idt_outb( 0xfe, 0x21);
+ idt_outb(PIC_ICW1_ICW4|PIC_ICW1_ICW1, PIC2_ICW1);
+ idt_outb(0x28, PIC2_ICW2);
+ idt_outb(PIC_ICW3_SID2, PIC2_ICW3);
+ idt_outb(PIC_ICW4_808xMODE, PIC2_ICW4);
}
/****************************************************************************
@@ -147,8 +151,8 @@ static void up_remappic(void)
static void up_idtentry(struct idt_entry_s *entry, uint32_t base,
uint16_t sel, uint8_t flags)
{
- entry->lobase = base & 0xFFFF;
- entry->hibase = (base >> 16) & 0xFFFF;
+ entry->lobase = base & 0xffff;
+ entry->hibase = (base >> 16) & 0xffff;
entry->sel = sel;
entry->zero = 0;
@@ -214,16 +218,16 @@ static inline void up_idtinit(void)
up_idtentry(&idt_entries[29], (uint32_t)vector_isr29, 0x08, 0x8e);
up_idtentry(&idt_entries[30], (uint32_t)vector_isr30, 0x08, 0x8e);
up_idtentry(&idt_entries[31], (uint32_t)vector_isr31, 0x08, 0x8e);
- up_idtentry(&idt_entries[32], (uint32_t)vector_irq0, 0x08, 0x8e);
- up_idtentry(&idt_entries[33], (uint32_t)vector_irq1, 0x08, 0x8e);
- up_idtentry(&idt_entries[34], (uint32_t)vector_irq2, 0x08, 0x8e);
- up_idtentry(&idt_entries[35], (uint32_t)vector_irq3, 0x08, 0x8e);
- up_idtentry(&idt_entries[36], (uint32_t)vector_irq4, 0x08, 0x8e);
- up_idtentry(&idt_entries[37], (uint32_t)vector_irq5, 0x08, 0x8e);
- up_idtentry(&idt_entries[38], (uint32_t)vector_irq6, 0x08, 0x8e);
- up_idtentry(&idt_entries[39], (uint32_t)vector_irq7, 0x08, 0x8e);
- up_idtentry(&idt_entries[40], (uint32_t)vector_irq8, 0x08, 0x8e);
- up_idtentry(&idt_entries[41], (uint32_t)vector_irq9, 0x08, 0x8e);
+ up_idtentry(&idt_entries[32], (uint32_t)vector_irq0, 0x08, 0x8e);
+ up_idtentry(&idt_entries[33], (uint32_t)vector_irq1, 0x08, 0x8e);
+ up_idtentry(&idt_entries[34], (uint32_t)vector_irq2, 0x08, 0x8e);
+ up_idtentry(&idt_entries[35], (uint32_t)vector_irq3, 0x08, 0x8e);
+ up_idtentry(&idt_entries[36], (uint32_t)vector_irq4, 0x08, 0x8e);
+ up_idtentry(&idt_entries[37], (uint32_t)vector_irq5, 0x08, 0x8e);
+ up_idtentry(&idt_entries[38], (uint32_t)vector_irq6, 0x08, 0x8e);
+ up_idtentry(&idt_entries[39], (uint32_t)vector_irq7, 0x08, 0x8e);
+ up_idtentry(&idt_entries[40], (uint32_t)vector_irq8, 0x08, 0x8e);
+ up_idtentry(&idt_entries[41], (uint32_t)vector_irq9, 0x08, 0x8e);
up_idtentry(&idt_entries[42], (uint32_t)vector_irq10, 0x08, 0x8e);
up_idtentry(&idt_entries[43], (uint32_t)vector_irq11, 0x08, 0x8e);
up_idtentry(&idt_entries[44], (uint32_t)vector_irq12, 0x08, 0x8e);
@@ -258,3 +262,98 @@ void up_irqinitialize(void)
irqrestore(X86_FLAGS_IF);
#endif
}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ * Disable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+ unsigned int regaddr;
+ uint8_t regbit;
+
+ if ((unsigned)irq >= IRQ0)
+ {
+ /* Map the IRQ IMR regiser to a PIC and a bit number */
+
+ if ((unsigned)irq <= IRQ7)
+ {
+ regaddr = PIC1_IMR;
+ regbit = (1 << (irq - IRQ0));
+ }
+ else if ((unsigned)irq <= IRQ15)
+ {
+ regaddr = PIC2_IMR;
+ regbit = (1 << (irq - IRQ8));
+ }
+ else
+ {
+ return;
+ }
+
+ /* Disable the interrupt */
+
+ modifyreg8(regaddr, regbit, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ * Enable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+ unsigned int regaddr;
+ uint8_t regbit;
+
+ if ((unsigned)irq >= IRQ0)
+ {
+ /* Map the IRQ IMR regiser to a PIC and a bit number */
+
+ if ((unsigned)irq <= IRQ7)
+ {
+ regaddr = PIC1_IMR;
+ regbit = (1 << (irq - IRQ0));
+ }
+ else if ((unsigned)irq <= IRQ15)
+ {
+ regaddr = PIC2_IMR;
+ regbit = (1 << (irq - IRQ8));
+ }
+ else
+ {
+ return;
+ }
+
+ /* Enable the interrupt */
+
+ modifyreg8(regaddr, 0, regbit);
+ }
+}
+
+/****************************************************************************
+ * Name: up_prioritize_irq
+ *
+ * Description:
+ * Set the priority of an IRQ.
+ *
+ * Since this API is not supported on all architectures, it should be
+ * avoided in common implementations where possible.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_IRQPRIO
+int up_prioritize_irq(int irq, int priority)
+{
+#warning "Missing Logic"
+ return OK;
+}
+#endif
diff --git a/arch/x86/src/qemu/Make.defs b/arch/x86/src/qemu/Make.defs
index 4c3a83380d5b5d3c430d54ec3c6c1217a16278c8..3177f3db4d07f1f68189c35dfc0144f58b453718 100755
--- a/arch/x86/src/qemu/Make.defs
+++ b/arch/x86/src/qemu/Make.defs
@@ -42,7 +42,7 @@ HEAD_ASRC = qemu_head.S
CMN_ASRCS = i486_utils.S
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
up_createstack.c up_mdelay.c up_udelay.c up_exit.c\
- up_initialize.c up_initialstate.c up_interruptcontext.c \
+ up_initialize.c up_initialstate.c up_interruptcontext.c up_irq.c \
up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c up_regdump.c \
up_releasepending.c up_releasestack.c up_reprioritizertr.c \
up_sigdeliver.c up_schedulesigaction.c up_unblocktask.c \
@@ -51,7 +51,7 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
# Required QEMU files
CHIP_ASRCS = qemu_saveusercontext.S qemu_fullcontextrestore.S qemu_vectors.S
-CHIP_CSRCS = qemu_handlers.c qemu_idle.c qemu_irq.c qemu_lowputc.c \
- qemu_lowsetup.c qemu_serial.c qemu_timerisr.c
+CHIP_CSRCS = qemu_handlers.c qemu_idle.c qemu_lowputc.c qemu_lowsetup.c \
+ qemu_serial.c qemu_timerisr.c
# Configuration-dependent QEMU files
diff --git a/arch/x86/src/qemu/qemu_timerisr.c b/arch/x86/src/qemu/qemu_timerisr.c
index ddc4a5e740831ef6f7f2762b10d561bef3b8123a..ca51816af0fd5b884b12c8e15bfebc78b59c80b8 100755
--- a/arch/x86/src/qemu/qemu_timerisr.c
+++ b/arch/x86/src/qemu/qemu_timerisr.c
@@ -79,9 +79,6 @@
#define PIT_DIVISOR ((uint32_t)PIT_CLOCK/(uint32_t)CLK_TCK)
-#define PIT_MODE 0x43
-#define PIT_CH0 0x40
-
/****************************************************************************
* Private Types
****************************************************************************/
@@ -90,26 +87,13 @@
* Private Function Prototypes
****************************************************************************/
-static void pit_outb(uint8_t val, uint16_t addr) __attribute__((noinline));
+static void outb(uint8_t val, uint16_t addr) __attribute__((noinline));
static int up_timerisr(int irq, uint32_t *regs);
/****************************************************************************
* Private Functions
****************************************************************************/
-/****************************************************************************
- * Name pit_outb
- *
- * Description:
- * A slightly slower version of outb
- *
- ****************************************************************************/
-
-static void pit_outb(uint8_t val, uint16_t addr)
-{
- outb(val, addr);
-}
-
/****************************************************************************
* Function: up_timerisr
*
@@ -151,12 +135,16 @@ void up_timerinit(void)
(void)irq_attach(IRQ0, (xcpt_t)up_timerisr);
- /* Send the command byte */
+ /* Send the command byte to configure counter 0 */
- pit_outb(0x36, PIT_MODE);
+ outb(PIT_OCW_MODE_SQUARE|PIT_OCW_RL_DATA|PIT_OCW_COUNTER_0, PIT_REG_COMMAND);
/* Set the PIT input frequency divisor */
- pit_outb((uint8_t)(divisor & 0xff), PIT_CH0);
- pit_outb((uint8_t)((divisor >> 8) & 0xff), PIT_CH0);
+ outb((uint8_t)(divisor & 0xff), PIT_REG_COUNTER0);
+ outb((uint8_t)((divisor >> 8) & 0xff), PIT_REG_COUNTER0);
+
+ /* And enable IRQ0 */
+
+ up_enable_irq(IRQ0);
}
diff --git a/configs/qemu-i486/nsh/defconfig b/configs/qemu-i486/nsh/defconfig
index 8244e35bcae6c22305452ffc10ff803d6c34a0e7..3cec37a3b43d3e81dcd4f84f5b01cbf37b7bad1f 100644
--- a/configs/qemu-i486/nsh/defconfig
+++ b/configs/qemu-i486/nsh/defconfig
@@ -80,7 +80,7 @@ CONFIG_BOARD_LOOPSPERMSEC=999
CONFIG_DRAM_SIZE=0x00100000
CONFIG_DRAM_START=0x00100000
CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
-CONFIG_ARCH_NOINTC=y
+CONFIG_ARCH_NOINTC=n
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH_LEDS=n
CONFIG_ARCH_BUTTONS=n
diff --git a/configs/qemu-i486/ostest/defconfig b/configs/qemu-i486/ostest/defconfig
index 8b17c30b8d16db55304db4632cc8f995714031a4..c84f50822f7fb366aa6ab6e90724e026ef76e8b6 100644
--- a/configs/qemu-i486/ostest/defconfig
+++ b/configs/qemu-i486/ostest/defconfig
@@ -80,7 +80,7 @@ CONFIG_BOARD_LOOPSPERMSEC=999
CONFIG_DRAM_SIZE=0x00100000
CONFIG_DRAM_START=0x00100000
CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
-CONFIG_ARCH_NOINTC=y
+CONFIG_ARCH_NOINTC=n
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH_LEDS=n
CONFIG_ARCH_BUTTONS=n