diff --git a/arch/8051/include/arch.h b/arch/8051/include/arch.h index 1ca504fb814bd937ba2335a6541b713feefacdb2..4626662e42af322507a266d5ee2704e1ac1fad74 100644 --- a/arch/8051/include/arch.h +++ b/arch/8051/include/arch.h @@ -2,7 +2,7 @@ * arch.h * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/include/irq.h b/arch/8051/include/irq.h index 60f5d1c4749e3850275a3af6b77cc105661730ba..ce6334dd0cbd2ba1f6e8bbdafd5735757547cc7f 100644 --- a/arch/8051/include/irq.h +++ b/arch/8051/include/irq.h @@ -2,7 +2,7 @@ * irq.h * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/include/syscall.h b/arch/8051/include/syscall.h index de72d1edf44d245d61f28f2cca9989463a695519..2c85fb420190d50efc5460c5d3d9429786d1f4b7 100644 --- a/arch/8051/include/syscall.h +++ b/arch/8051/include/syscall.h @@ -2,7 +2,7 @@ * arch/8051/include/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/include/types.h b/arch/8051/include/types.h index 2d195631a1eab25b1bb401b4349cf097bf469ab5..4a528c7d04119ab11414536b6e249f68b75e7857 100644 --- a/arch/8051/include/types.h +++ b/arch/8051/include/types.h @@ -2,7 +2,7 @@ * arch/8051/include/types.h * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_allocateheap.c b/arch/8051/src/up_allocateheap.c index 6ef1a77dacaa403f009433c07ec6dafd86a47285..b797b44208794ceabfc07b960f23a8a0a605180a 100644 --- a/arch/8051/src/up_allocateheap.c +++ b/arch/8051/src/up_allocateheap.c @@ -2,7 +2,7 @@ * up_allocateheap.c * * Copyright (C) 2007 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_assert.c b/arch/8051/src/up_assert.c index 157b18ae518460e40f9309ffba9326556606edc9..10a5daf3562c5f9bed8a69c8f07a94fe930959d2 100644 --- a/arch/8051/src/up_assert.c +++ b/arch/8051/src/up_assert.c @@ -2,7 +2,7 @@ * up_assert.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_blocktask.c b/arch/8051/src/up_blocktask.c index 811955efa909a6c2838f43f7e2c1f45eb2587843..14dc371dde1e14c0ab721957c79f979e1ee1967f 100644 --- a/arch/8051/src/up_blocktask.c +++ b/arch/8051/src/up_blocktask.c @@ -2,7 +2,7 @@ * up_blocktask.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_debug.c b/arch/8051/src/up_debug.c index 9d9bce2a000188b94fb1a215efe8091e4be01012..27049f7f5e35ea05b8e7eccc5e1816488e2b9242 100644 --- a/arch/8051/src/up_debug.c +++ b/arch/8051/src/up_debug.c @@ -2,7 +2,7 @@ * up_assert.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_delay.c b/arch/8051/src/up_delay.c index 3403c69cc29452c328a43828cd509658f26d1d7a..ad8950e86ca35382fb4c51646ffd19eaaf4a6510 100644 --- a/arch/8051/src/up_delay.c +++ b/arch/8051/src/up_delay.c @@ -2,7 +2,7 @@ * up_delay.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_exit.c b/arch/8051/src/up_exit.c index 736fc71d54e27e5f71a7330cde72bfad6d801767..27b9fe13869fb601bd029366bc04da2363993157 100644 --- a/arch/8051/src/up_exit.c +++ b/arch/8051/src/up_exit.c @@ -2,7 +2,7 @@ * up_exit.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_head.S b/arch/8051/src/up_head.S index 44f8038c9ec14df03dcd47983d0088dd58f4fe58..47d270fc910f33186eb81ae6e31532471c79b458 100644 --- a/arch/8051/src/up_head.S +++ b/arch/8051/src/up_head.S @@ -2,7 +2,7 @@ * up_head.S * * Copyright (C) 2007 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_idle.c b/arch/8051/src/up_idle.c index 802e684bec7eb64348ef2e4c9197ef6d6519ba9e..4259f8a74b7d3f5788d2f8f2e21069ecbcbea3fa 100644 --- a/arch/8051/src/up_idle.c +++ b/arch/8051/src/up_idle.c @@ -2,7 +2,7 @@ * up_idle.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_initialize.c b/arch/8051/src/up_initialize.c index 8e74921476e5e133c026f6037e10d3ef5a1a8f7f..b4835f4d19994892dec22abb0467da168498f5e2 100644 --- a/arch/8051/src/up_initialize.c +++ b/arch/8051/src/up_initialize.c @@ -2,7 +2,7 @@ * up_initialize.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_initialstate.c b/arch/8051/src/up_initialstate.c index 5289d867c3b78843be320d1b51fbb2f1640c8b6f..85f172888bfe21d339a714ba13db80f0355a0608 100644 --- a/arch/8051/src/up_initialstate.c +++ b/arch/8051/src/up_initialstate.c @@ -2,7 +2,7 @@ * up_initialstate.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_internal.h b/arch/8051/src/up_internal.h index 75fe58c40f1a12940f1e4053ae860d363655d058..c213cc3d40654d8c650b7667a4f281ee2815f9f6 100644 --- a/arch/8051/src/up_internal.h +++ b/arch/8051/src/up_internal.h @@ -2,7 +2,7 @@ * up_internal.h * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_interruptcontext.c b/arch/8051/src/up_interruptcontext.c index 81426a94e4a16fc97c9d5be8aed71b558d908c58..bcc9e4cd9d87dabd699992761b55b6e4643a7b3a 100644 --- a/arch/8051/src/up_interruptcontext.c +++ b/arch/8051/src/up_interruptcontext.c @@ -2,7 +2,7 @@ * up_interruptcontext.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_irq.c b/arch/8051/src/up_irq.c index f40bdbf31bd492a342be99b7875f9c2ab0f8d58c..dee3120c8b864f55fcfe20b2a31c267a43ea831d 100644 --- a/arch/8051/src/up_irq.c +++ b/arch/8051/src/up_irq.c @@ -2,7 +2,7 @@ * up_irq.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_irqtest.c b/arch/8051/src/up_irqtest.c index 211f7e05f0e0b780059c8774ba2fd6121964fcf4..4889ccfd1774b63afabbbb2fcf86cb90deef7630 100644 --- a/arch/8051/src/up_irqtest.c +++ b/arch/8051/src/up_irqtest.c @@ -2,7 +2,7 @@ * up_irqtest.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_putc.c b/arch/8051/src/up_putc.c index a4b96e23f4a0393c93cca4bf96ac0d37772bf1e5..66979ce4af60e41c65b5686d70f4fcb04bde2036 100644 --- a/arch/8051/src/up_putc.c +++ b/arch/8051/src/up_putc.c @@ -2,7 +2,7 @@ * up_putc.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_releasepending.c b/arch/8051/src/up_releasepending.c index c35199bd58a2b82207fdc95f8b650432af09a151..55f46edae77242275d8cb8490beaca347155e41e 100644 --- a/arch/8051/src/up_releasepending.c +++ b/arch/8051/src/up_releasepending.c @@ -2,7 +2,7 @@ * up_releasepending.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_reprioritizertr.c b/arch/8051/src/up_reprioritizertr.c index 8810a8fe16581b1b4a19fb104fa3f4b91701e5d1..6d4a72487f23d51a34b8db30d527fd8bc44297d0 100644 --- a/arch/8051/src/up_reprioritizertr.c +++ b/arch/8051/src/up_reprioritizertr.c @@ -2,7 +2,7 @@ * up_reprioritizertr.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_restorecontext.c b/arch/8051/src/up_restorecontext.c index cf7fc103951caaed09682f1faff9db4af91b5298..d1aaae182075492f846b59fedcc67489288eff8d 100644 --- a/arch/8051/src/up_restorecontext.c +++ b/arch/8051/src/up_restorecontext.c @@ -2,7 +2,7 @@ * up_restorecontext.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_savecontext.c b/arch/8051/src/up_savecontext.c index 9a86faa94715f39a2dc35c6f6a8ca932f501d04c..c5d0ae1c766a1699e24e4dd7c912d092ef5b5e14 100644 --- a/arch/8051/src/up_savecontext.c +++ b/arch/8051/src/up_savecontext.c @@ -2,7 +2,7 @@ * up_savecontext.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_timerisr.c b/arch/8051/src/up_timerisr.c index 3ca2faad67a86419a290544f73b4ecea2a9b8861..e31c5e13fd2392129b4c23e41d7c7ac106b49a89 100644 --- a/arch/8051/src/up_timerisr.c +++ b/arch/8051/src/up_timerisr.c @@ -2,7 +2,7 @@ * up_timerisr.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/8051/src/up_unblocktask.c b/arch/8051/src/up_unblocktask.c index 9152eae0a14bc4f389eb63d9627e6cffe1bafda2..1c82236a5fac4e4bdb90d6a2804d673bec792982 100644 --- a/arch/8051/src/up_unblocktask.c +++ b/arch/8051/src/up_unblocktask.c @@ -2,7 +2,7 @@ * up_unblocktask.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/arch.h b/arch/arm/include/arch.h index dd750ad77a13d1b74d6ad812a95bffcbf8176b92..d0b2602eba0981e9dfe075ad679b66c3aaff70d4 100644 --- a/arch/arm/include/arch.h +++ b/arch/arm/include/arch.h @@ -2,7 +2,7 @@ * arch/arm/include/arch.h * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/arm/irq.h b/arch/arm/include/arm/irq.h index 6b4f05539ac5d66bccc1d3b2035132f319d5298c..a06abe88864f526f8439944715b407972659bc21 100644 --- a/arch/arm/include/arm/irq.h +++ b/arch/arm/include/arm/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/arm/irq.h * * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/arm/syscall.h b/arch/arm/include/arm/syscall.h index e06de1a3c223b8cd41cda009b11d78626c11bd06..3fc36c3db0d510f51b1d861c43929381c011de52 100644 --- a/arch/arm/include/arm/syscall.h +++ b/arch/arm/include/arm/syscall.h @@ -2,7 +2,7 @@ * arch/arm/include/arm/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/armv7-m/syscall.h b/arch/arm/include/armv7-m/syscall.h index 4c7b843021d2fcf8e3b4c0bd146509a2007e646a..4278c3a36bf91de505073bdd6dd9bc6a49596822 100644 --- a/arch/arm/include/armv7-m/syscall.h +++ b/arch/arm/include/armv7-m/syscall.h @@ -2,7 +2,7 @@ * arch/arm/include/armv7-m/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/c5471/irq.h b/arch/arm/include/c5471/irq.h index 7f6dcd3433e8d34d2a4d73a828e8022280bf5a74..97aa0352a34cd4fd916f8e5193d779f5cb9bc1b0 100644 --- a/arch/arm/include/c5471/irq.h +++ b/arch/arm/include/c5471/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/c5471/irq.h * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/dm320/irq.h b/arch/arm/include/dm320/irq.h index c8c89af5e1c8c72563486bcfd01f976c4e4f1d6a..320b56614e0e728f60a09fe29f6c266e8a0c8ea3 100644 --- a/arch/arm/include/dm320/irq.h +++ b/arch/arm/include/dm320/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/dm320/irq.h * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/imx/irq.h b/arch/arm/include/imx/irq.h index c2fd93d898f61e9ff6fc6a21a52d92ad086b6ae3..28158bb8d381714eb2e4c7c90dd3546cff3700f2 100644 --- a/arch/arm/include/imx/irq.h +++ b/arch/arm/include/imx/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/imx/irq.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/irq.h b/arch/arm/include/irq.h index 71493a9fed1c0d9b9b22e1ded6128bf8e15082fb..bde751b9908158b81a3b96aadd3d806269c53a34 100644 --- a/arch/arm/include/irq.h +++ b/arch/arm/include/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/irq.h * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/kinetis/irq.h b/arch/arm/include/kinetis/irq.h index af10ce6f4097f7c9864d4b746156ab2df097a230..8a020ea1b6fbfcc91483c02db34ca0a55946be7d 100644 --- a/arch/arm/include/kinetis/irq.h +++ b/arch/arm/include/kinetis/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/kinetis/irq.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/lm3s/irq.h b/arch/arm/include/lm3s/irq.h index 3eca0e0e83141f2037f94b37973c829a7fbb2fad..6ffc7dec09daccb7e1a1d3f74b65448a8a60e3b5 100644 --- a/arch/arm/include/lm3s/irq.h +++ b/arch/arm/include/lm3s/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/lm3s/irq.h * * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/lpc17xx/irq.h b/arch/arm/include/lpc17xx/irq.h index aebdc31596ad4ff1e1167a6175ab1165f57e22cc..a7eebb32c28ed299fdfa9458ac1ea525d737de86 100755 --- a/arch/arm/include/lpc17xx/irq.h +++ b/arch/arm/include/lpc17xx/irq.h @@ -2,7 +2,7 @@ * arch/lpc17xxx/irq.h * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/lpc214x/irq.h b/arch/arm/include/lpc214x/irq.h index 221644a0762eed2f428293b64195ec95600fa332..5652fc7a9c5af89a5aa191fdeb0d419e4f4ee6e9 100644 --- a/arch/arm/include/lpc214x/irq.h +++ b/arch/arm/include/lpc214x/irq.h @@ -2,7 +2,7 @@ * arch/lpc214x/irq.h * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/lpc2378/irq.h b/arch/arm/include/lpc2378/irq.h index 3ea09d7af1529957871badd93cb26b0e2da52c7f..807c9911949da2da3764439e9f4484ab3ff44b70 100755 --- a/arch/arm/include/lpc2378/irq.h +++ b/arch/arm/include/lpc2378/irq.h @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/lpc31xx/irq.h b/arch/arm/include/lpc31xx/irq.h index 5a701239b295d519f0136c9f4a9cafae2634969f..d3654a507fc5c5eaba04679d47a347e56b2a995e 100755 --- a/arch/arm/include/lpc31xx/irq.h +++ b/arch/arm/include/lpc31xx/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/lpc31xx/irq.h * * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/sam3u/irq.h b/arch/arm/include/sam3u/irq.h index 2c6940b68f510baf3ec067a8461216c2af725d58..481db74a2c09ba936f1f6b97fb34164b41bfb54d 100755 --- a/arch/arm/include/sam3u/irq.h +++ b/arch/arm/include/sam3u/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/sam3u/irq.h * * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/serial.h b/arch/arm/include/serial.h index 80eefb2b4ac33d6dce282b26bf64eade366bf84f..844f78a2b98c42d8de0d92b3306daecece418357 100644 --- a/arch/arm/include/serial.h +++ b/arch/arm/include/serial.h @@ -2,7 +2,7 @@ * arch/arm/include/serial.h * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/str71x/irq.h b/arch/arm/include/str71x/irq.h index bac58bb2a5043ff4b4b29159e8fbc05c5ce13cbf..5ce85416ae03a2a91b2dc5617e0539bc98793c89 100644 --- a/arch/arm/include/str71x/irq.h +++ b/arch/arm/include/str71x/irq.h @@ -2,7 +2,7 @@ * arch/arm/include/str71x/irq.h * * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/syscall.h b/arch/arm/include/syscall.h index 4c9eee63ef8b23d28f74a58f858daec5cdaa2c06..8b438200a86b452b159fddbbc4cbfa7c3ef4bc55 100644 --- a/arch/arm/include/syscall.h +++ b/arch/arm/include/syscall.h @@ -2,7 +2,7 @@ * arch/arm/include/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/types.h b/arch/arm/include/types.h index c3471ca59b55cc0f5ab54f66e6f1b23a64e73117..c06b289503ac1f608a560bd8bc4fb8a66e576052 100644 --- a/arch/arm/include/types.h +++ b/arch/arm/include/types.h @@ -2,7 +2,7 @@ * arch/arm/include/types.h * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/include/watchdog.h b/arch/arm/include/watchdog.h index f70b8d2e9a6a8ecfe23d68823656d892cf151a2b..43fbac2be85b4980cee604a49664d2ae7b0f2405 100644 --- a/arch/arm/include/watchdog.h +++ b/arch/arm/include/watchdog.h @@ -2,7 +2,7 @@ * arch/arm/include/watchdog.h * * Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/arm.h b/arch/arm/src/arm/arm.h index 4332838149f29e9fac6b2b3adb02a8b1fe9beee6..2ad31fc4696d3cebadb212ee1256a288c1260d4b 100644 --- a/arch/arm/src/arm/arm.h +++ b/arch/arm/src/arm/arm.h @@ -2,7 +2,7 @@ * arch/arm/src/arm/arm.h * * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/pg_macros.h b/arch/arm/src/arm/pg_macros.h index fc50f61460921049f1f809e6cfb4d0bed41c6895..dc65a5d06af7d7f7afe5eb2cb9c90e1dccf21403 100644 --- a/arch/arm/src/arm/pg_macros.h +++ b/arch/arm/src/arm/pg_macros.h @@ -2,7 +2,7 @@ * arch/arm/src/arm/pg_macros.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_allocpage.c b/arch/arm/src/arm/up_allocpage.c index c2a31d09c0af4f6d6646e4260e03295c4ce73f86..0284e48bc32043697c0112d9b4bc60e9ab0ad703 100755 --- a/arch/arm/src/arm/up_allocpage.c +++ b/arch/arm/src/arm/up_allocpage.c @@ -3,7 +3,7 @@ * Allocate a new page and map it to the fault address of a task. * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_assert.c b/arch/arm/src/arm/up_assert.c index f52dc1b94672495fd80c769f0c227d39ff544045..023e6e22d4468e8c492463d640aef3d33a9f12bc 100644 --- a/arch/arm/src/arm/up_assert.c +++ b/arch/arm/src/arm/up_assert.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_assert.c * * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_blocktask.c b/arch/arm/src/arm/up_blocktask.c index 36c8740d6635b72be7f7245c9ef7fb1fdb12ecbd..f72a0246538b900c55a8970786e4932a93f7cf46 100755 --- a/arch/arm/src/arm/up_blocktask.c +++ b/arch/arm/src/arm/up_blocktask.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_blocktask.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_cache.S b/arch/arm/src/arm/up_cache.S index 05926fbb4fc828900734eeceddafbea5d2bc6385..1d459e69306a98ed27a1661a8eaa1110486314c1 100644 --- a/arch/arm/src/arm/up_cache.S +++ b/arch/arm/src/arm/up_cache.S @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_cache.S * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_checkmapping.c b/arch/arm/src/arm/up_checkmapping.c index 370c94c9d5f11f3cdae559aaf257359e2b572e27..ca8c3a03230b29bf0858f69747195e70859bcbc1 100755 --- a/arch/arm/src/arm/up_checkmapping.c +++ b/arch/arm/src/arm/up_checkmapping.c @@ -4,7 +4,7 @@ * address space. * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_copystate.c b/arch/arm/src/arm/up_copystate.c index 44f027b3289f5a6390da547a391bd66daefbe62b..c76ee8e7073e9e16eac54acde748a02c1d758eb0 100644 --- a/arch/arm/src/arm/up_copystate.c +++ b/arch/arm/src/arm/up_copystate.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_copystate.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_dataabort.c b/arch/arm/src/arm/up_dataabort.c index c36970c1bef9b5ecbd5028ee74a026e790c1afe8..f019419685164172d58433f3961983f063a221cc 100644 --- a/arch/arm/src/arm/up_dataabort.c +++ b/arch/arm/src/arm/up_dataabort.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_dataabort.c * * Copyright (C) 2007-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_doirq.c b/arch/arm/src/arm/up_doirq.c index 1f1c774738d73291174397ab7f6174327e544da0..c82587fff09f4ef82cbbe4f3ee5317729a66a88c 100644 --- a/arch/arm/src/arm/up_doirq.c +++ b/arch/arm/src/arm/up_doirq.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_doirq.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_fullcontextrestore.S b/arch/arm/src/arm/up_fullcontextrestore.S index d0745ef5b46c96df7022c7ea0c999b00c8c49c60..44573a5f443bdd86a53ae779ed7a24682b388fab 100644 --- a/arch/arm/src/arm/up_fullcontextrestore.S +++ b/arch/arm/src/arm/up_fullcontextrestore.S @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_fullcontextrestore.S * * Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_head.S b/arch/arm/src/arm/up_head.S index c04dddf8aa3d0b46f0bed213f5a0acff82f32c6e..91d67fd15b4adb76b08011cf2be497453c24f6c4 100644 --- a/arch/arm/src/arm/up_head.S +++ b/arch/arm/src/arm/up_head.S @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_head.S * * Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_initialstate.c b/arch/arm/src/arm/up_initialstate.c index 4711c9f4444c99782584c2f903bf9a684a36bad3..fb672a2aca3d17687066c2601422c3e48f75a197 100644 --- a/arch/arm/src/arm/up_initialstate.c +++ b/arch/arm/src/arm/up_initialstate.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_initialstate.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_pginitialize.c b/arch/arm/src/arm/up_pginitialize.c index 1aea95113476c1245540e5e82968e0a985b17018..5470f73e3548182a37f07dc9fc806d7631300b21 100755 --- a/arch/arm/src/arm/up_pginitialize.c +++ b/arch/arm/src/arm/up_pginitialize.c @@ -3,7 +3,7 @@ * Initialize the MMU for on-demand paging support. * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_prefetchabort.c b/arch/arm/src/arm/up_prefetchabort.c index ed3dd91d332edd4556dc52ce0e63276cbe662902..9af644fc0ee70fd4d19c856fca419a758c67cac8 100644 --- a/arch/arm/src/arm/up_prefetchabort.c +++ b/arch/arm/src/arm/up_prefetchabort.c @@ -2,7 +2,7 @@ * arch/arm/src/src/up_prefetchabort.c * * Copyright (C) 2007-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_releasepending.c b/arch/arm/src/arm/up_releasepending.c index dcad401593821b72c460299cef38978113ffc917..8adeeb26d9077d4ac59fa90a24b4fa59a56e3ef7 100755 --- a/arch/arm/src/arm/up_releasepending.c +++ b/arch/arm/src/arm/up_releasepending.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_releasepending.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_reprioritizertr.c b/arch/arm/src/arm/up_reprioritizertr.c index 38bce2a72b4c4a75aa4a03bc10210e6e0d823798..02bc39d6250759ba65eb24b3c60e50267cf4b13f 100755 --- a/arch/arm/src/arm/up_reprioritizertr.c +++ b/arch/arm/src/arm/up_reprioritizertr.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_reprioritizertr.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_saveusercontext.S b/arch/arm/src/arm/up_saveusercontext.S index 8d154d18735f56671d566338980d4555b40bd5b3..43487cc42f7fa6e2fe5a1d43baf21282354bcccd 100644 --- a/arch/arm/src/arm/up_saveusercontext.S +++ b/arch/arm/src/arm/up_saveusercontext.S @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_saveusercontext.S * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_schedulesigaction.c b/arch/arm/src/arm/up_schedulesigaction.c index 0dfb6e540fbf9c919ea308e8743a0f8b106a1ba3..a76438f946ff2db290724231946c301473d5870d 100644 --- a/arch/arm/src/arm/up_schedulesigaction.c +++ b/arch/arm/src/arm/up_schedulesigaction.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_schedulesigaction.c * * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_sigdeliver.c b/arch/arm/src/arm/up_sigdeliver.c index f92f85e7e093a0158f0bca60baaba48b78853bf9..8684494483f0c882becd6ac19c20f12f0eaaa638 100644 --- a/arch/arm/src/arm/up_sigdeliver.c +++ b/arch/arm/src/arm/up_sigdeliver.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_sigdeliver.c * * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_syscall.c b/arch/arm/src/arm/up_syscall.c index f331a13146cf22d6433fa922170b1527c26f6003..1bcd66502f3430f99c74c750a22965452fcb24e1 100644 --- a/arch/arm/src/arm/up_syscall.c +++ b/arch/arm/src/arm/up_syscall.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_syscall.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_unblocktask.c b/arch/arm/src/arm/up_unblocktask.c index 73e292561fbae73f7a82222bf44c497f15a1ea94..633dc4e82127b363a8f8ffab01c850a3fa3ce765 100755 --- a/arch/arm/src/arm/up_unblocktask.c +++ b/arch/arm/src/arm/up_unblocktask.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_unblocktask.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_undefinedinsn.c b/arch/arm/src/arm/up_undefinedinsn.c index 4c50991b0f5eee8004761290602f01d746569868..d61abe11b7c5abcdbfa49feccd2dde0dedc60cb9 100644 --- a/arch/arm/src/arm/up_undefinedinsn.c +++ b/arch/arm/src/arm/up_undefinedinsn.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_undefinedinsn.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_va2pte.c b/arch/arm/src/arm/up_va2pte.c index 5f92ad8218739143a05a9bd618ecc04d60762ba7..eb5a4c56b46c80576778efc954d6c09a22122265 100755 --- a/arch/arm/src/arm/up_va2pte.c +++ b/arch/arm/src/arm/up_va2pte.c @@ -3,7 +3,7 @@ * Utility to map a virtual address to a L2 page table entry. * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_vectoraddrexcptn.S b/arch/arm/src/arm/up_vectoraddrexcptn.S index e034c394f68e8089506f6514c8d50fcf1e8b10be..ba5787cb91b163dcd13edd7ac15e0d337b57c60e 100644 --- a/arch/arm/src/arm/up_vectoraddrexcptn.S +++ b/arch/arm/src/arm/up_vectoraddrexcptn.S @@ -2,7 +2,7 @@ * arch/arm/src/src/up_vectoraddrexceptn.S * * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_vectors.S b/arch/arm/src/arm/up_vectors.S index 00c5d52b06f4d9c2058ec874f0e307db6922f567..bcf9c37d0f3c6cbe323d0e38505fd3d537496578 100644 --- a/arch/arm/src/arm/up_vectors.S +++ b/arch/arm/src/arm/up_vectors.S @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_vectors.S * * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/arm/up_vectortab.S b/arch/arm/src/arm/up_vectortab.S index a7972fa3c208e66ba9da56e37f3c2e12f02f3a07..8eae70055cde6aecc3a5a93cec62cc8a026c507d 100644 --- a/arch/arm/src/arm/up_vectortab.S +++ b/arch/arm/src/arm/up_vectortab.S @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_vectortab.S * * Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/armv7-m/psr.h b/arch/arm/src/armv7-m/psr.h index 30913f7c9e9c36c44bb104399a42e876517f821c..b8b33c80f6e5170f51ca5b147459148990ea55c4 100644 --- a/arch/arm/src/armv7-m/psr.h +++ b/arch/arm/src/armv7-m/psr.h @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/psr.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/armv7-m/svcall.h b/arch/arm/src/armv7-m/svcall.h index 51b5b9111ac142f3f54ad849915e328d6ad16f12..9a4db89b13dfcbf0e94e267d5cf62ccbfacad57d 100644 --- a/arch/arm/src/armv7-m/svcall.h +++ b/arch/arm/src/armv7-m/svcall.h @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/svcall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/armv7-m/up_assert.c b/arch/arm/src/armv7-m/up_assert.c index 77fd0b596fbf293e9bcf47084bbcaf40cdd8198b..2662cbe37f3df4f9e4da42ae6822e3d573ccfd4f 100644 --- a/arch/arm/src/armv7-m/up_assert.c +++ b/arch/arm/src/armv7-m/up_assert.c @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_assert.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/armv7-m/up_copystate.c b/arch/arm/src/armv7-m/up_copystate.c index a5ad312f5e7a5199e39c8914d3e6d4d2b950b5df..e9eede8f99e63b2ebe98fb689d6682c081633d61 100644 --- a/arch/arm/src/armv7-m/up_copystate.c +++ b/arch/arm/src/armv7-m/up_copystate.c @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_copystate.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/armv7-m/up_doirq.c b/arch/arm/src/armv7-m/up_doirq.c index 7ac1ec34dbf20f79ba30db72ca4c7b855ac8a315..375054fba6278666f61b73de0f47141fe2df8cae 100644 --- a/arch/arm/src/armv7-m/up_doirq.c +++ b/arch/arm/src/armv7-m/up_doirq.c @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_doirq.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/armv7-m/up_hardfault.c b/arch/arm/src/armv7-m/up_hardfault.c index a9eea810361df03a3d9fb368afdbebb14574f345..cb3ce9e8a9d16602413f4f3cdc12cc54f1679d4d 100644 --- a/arch/arm/src/armv7-m/up_hardfault.c +++ b/arch/arm/src/armv7-m/up_hardfault.c @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_hardfault.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/armv7-m/up_memfault.c b/arch/arm/src/armv7-m/up_memfault.c index bbe3f6573f5a3bf4f3f47e2d0d1c064a9dffa204..ab93c7697d722b3c744c76537eb29994f85ec38c 100644 --- a/arch/arm/src/armv7-m/up_memfault.c +++ b/arch/arm/src/armv7-m/up_memfault.c @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_memfault.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/armv7-m/up_mpu.c b/arch/arm/src/armv7-m/up_mpu.c index 27936562c9bce2f81b3b298a4dd050e516cb4bc1..4bb3f21d987a0df277f758b302101cfccde1bf63 100644 --- a/arch/arm/src/armv7-m/up_mpu.c +++ b/arch/arm/src/armv7-m/up_mpu.c @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_mpu.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/armv7-m/up_saveusercontext.S b/arch/arm/src/armv7-m/up_saveusercontext.S index c8da074303e720a7a3454b059ff1190765abc99f..06eb183d217f506cec95a5f5e7be973a9e1f9fae 100755 --- a/arch/arm/src/armv7-m/up_saveusercontext.S +++ b/arch/arm/src/armv7-m/up_saveusercontext.S @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_saveusercontext.S * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/armv7-m/up_sigdeliver.c b/arch/arm/src/armv7-m/up_sigdeliver.c index 3c340b8d3c9993f96079ef5dea2ad600cf3f2505..38673c41d4b1f2754bc859531d5ceecfc08d6ea9 100644 --- a/arch/arm/src/armv7-m/up_sigdeliver.c +++ b/arch/arm/src/armv7-m/up_sigdeliver.c @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_sigdeliver.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/armv7-m/up_switchcontext.S b/arch/arm/src/armv7-m/up_switchcontext.S index 854f6fa16297df2abfaf2e3c5ad201b39ca69d82..762e2066e8951339716827b10470f7f7630a44e8 100755 --- a/arch/arm/src/armv7-m/up_switchcontext.S +++ b/arch/arm/src/armv7-m/up_switchcontext.S @@ -2,7 +2,7 @@ * arch/arm/src/armv7-m/up_switchcontext.S * * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/c5471/Make.defs b/arch/arm/src/c5471/Make.defs index 636197f4e7a43cce42b1e52330a11df30ed7fa60..d1c2cf0ac7073f0fbc124b3ab79bab0791eb0982 100644 --- a/arch/arm/src/c5471/Make.defs +++ b/arch/arm/src/c5471/Make.defs @@ -2,7 +2,7 @@ # c5471/Make.defs # # Copyright (C) 2007 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/arm/src/c5471/c5471_ethernet.c b/arch/arm/src/c5471/c5471_ethernet.c index 507f63cf9f31ff8bdbc504b91fdfb424b7145d21..142e0f0848a91fc9f6a9b1fd687121204024da04 100644 --- a/arch/arm/src/c5471/c5471_ethernet.c +++ b/arch/arm/src/c5471/c5471_ethernet.c @@ -2,7 +2,7 @@ * arch/arm/src/c5471/c5471_ethernet.c * * Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Based one a C5471 Linux driver and released under this BSD license with * special permisson from the copyright holder of the Linux driver: diff --git a/arch/arm/src/c5471/c5471_lowputc.S b/arch/arm/src/c5471/c5471_lowputc.S index 096742a700e1905ef89cc1a54876c65e41a264d8..b56483b879f2a680ae26b4c068ed122c11b73bde 100644 --- a/arch/arm/src/c5471/c5471_lowputc.S +++ b/arch/arm/src/c5471/c5471_lowputc.S @@ -2,7 +2,7 @@ * c5471/c5471_lowputc.S * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/c5471/c5471_timerisr.c b/arch/arm/src/c5471/c5471_timerisr.c index c9ff790556967dcf2aab65f99fb67c14e56f945b..1a221674d572c44c67ceefcef80a9b2c3f3b5f54 100644 --- a/arch/arm/src/c5471/c5471_timerisr.c +++ b/arch/arm/src/c5471/c5471_timerisr.c @@ -2,7 +2,7 @@ * c5471/c5471_timerisr.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/c5471/c5471_vectors.S b/arch/arm/src/c5471/c5471_vectors.S index 34f9e1b237d00ad54059795a2c48d2659abd8f2e..aa514b03fa58ba191aa45349bd0c8b60ef3c4ef6 100644 --- a/arch/arm/src/c5471/c5471_vectors.S +++ b/arch/arm/src/c5471/c5471_vectors.S @@ -2,7 +2,7 @@ * arch/arm/src/c5471/c5471_vectors.S * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/c5471/chip.h b/arch/arm/src/c5471/chip.h index 7121fd2209a1a283b42bb0283591b9efb6e8e117..d465ba8340824f13a97d916431039c76bf73e3e4 100644 --- a/arch/arm/src/c5471/chip.h +++ b/arch/arm/src/c5471/chip.h @@ -2,7 +2,7 @@ * c5471/chip.h * * Copyright (C) 2007 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/calypso/Make.defs b/arch/arm/src/calypso/Make.defs index d8f1613b05edd5f3050e4d717ad767e378a2023f..1552f17d14d64dfa496175f67f90fe921979c663 100644 --- a/arch/arm/src/calypso/Make.defs +++ b/arch/arm/src/calypso/Make.defs @@ -2,7 +2,7 @@ # calypso/Make.defs # # Copyright (C) 2007 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Copyright (C) 2011 Stefan Richter. All rights reserved. # Author: Stefan Richter diff --git a/arch/arm/src/calypso/calypso_lowputc.S b/arch/arm/src/calypso/calypso_lowputc.S index 951ea03d50dc8541df869575d82706dc049c7e6b..16e5ef4c1a2a29adf00d30f53f9901785d92ff0f 100644 --- a/arch/arm/src/calypso/calypso_lowputc.S +++ b/arch/arm/src/calypso/calypso_lowputc.S @@ -6,7 +6,7 @@ * * based on: c5471/c5471_lowputc.S * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/calypso/calypso_serial.c b/arch/arm/src/calypso/calypso_serial.c index 5175d25bbd126674f5ad752cb44ea2f904a6dd19..62e20409b9b645c1683e70cf3abc0e7a8bd730fb 100644 --- a/arch/arm/src/calypso/calypso_serial.c +++ b/arch/arm/src/calypso/calypso_serial.c @@ -6,7 +6,7 @@ * * based on c5471/c5471_serial.c * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/calypso/chip.h b/arch/arm/src/calypso/chip.h index d190dbc225a4d4d59f3950ff40043c3b7247c32c..c607fc71869e89266421bef568a73145d94438da 100644 --- a/arch/arm/src/calypso/chip.h +++ b/arch/arm/src/calypso/chip.h @@ -6,7 +6,7 @@ * * based on: c5471/chip.h * Copyright (C) 2007 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/common/up_allocateheap.c b/arch/arm/src/common/up_allocateheap.c index fbd1421a7489a8bc14b1524ed89a833f942a13e2..d4b763196e1bf345ccbc3c7c4ed4384ec8d043d7 100644 --- a/arch/arm/src/common/up_allocateheap.c +++ b/arch/arm/src/common/up_allocateheap.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_allocateheap.c * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/common/up_arch.h b/arch/arm/src/common/up_arch.h index b612f6af2598693dad2bb2eb504cceccf3ff8389..af29bbf65289683c1b4442f6fa9b2a8f67605edd 100644 --- a/arch/arm/src/common/up_arch.h +++ b/arch/arm/src/common/up_arch.h @@ -2,7 +2,7 @@ * arch/arm/src/common/up_arch.h * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/common/up_checkstack.c b/arch/arm/src/common/up_checkstack.c index 6c13f63d13ee3b6e84375be3cd806b162c8f7c1e..ac8d9e7b91d168ec99b5d5ff9eb14a94573d4dbd 100644 --- a/arch/arm/src/common/up_checkstack.c +++ b/arch/arm/src/common/up_checkstack.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_checkstack.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/common/up_etherstub.c b/arch/arm/src/common/up_etherstub.c index 1c4a71ce6807f1e0cfed800ead5af5ce91b6031c..407e7b45bc2ffd117871626c9d845fe8dcca2c36 100755 --- a/arch/arm/src/common/up_etherstub.c +++ b/arch/arm/src/common/up_etherstub.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_etherstub.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/common/up_idle.c b/arch/arm/src/common/up_idle.c index 62557c3a8d5ddc5a221b34ce4e54a1d3d6f11dff..187af76e7d801a95c8b59b38b7d5051dcd350b69 100644 --- a/arch/arm/src/common/up_idle.c +++ b/arch/arm/src/common/up_idle.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_idle.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/common/up_interruptcontext.c b/arch/arm/src/common/up_interruptcontext.c index b67ad523a2c4f536051e45ff7b1a97520105b5c7..0039692bcd61f1b320d2964a803690ba2d10265e 100644 --- a/arch/arm/src/common/up_interruptcontext.c +++ b/arch/arm/src/common/up_interruptcontext.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_interruptcontext.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/common/up_lowputs.c b/arch/arm/src/common/up_lowputs.c index 8b2919a05e1b3f4a990bf0a5a9a1400d696b48a3..890167e0ef0507671cf3c95a7ec999e39c15e8c8 100644 --- a/arch/arm/src/common/up_lowputs.c +++ b/arch/arm/src/common/up_lowputs.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_lowputs.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/common/up_mdelay.c b/arch/arm/src/common/up_mdelay.c index b9b9ffc0e4e4eb6a7312ff19df8b0c4035fb21d8..2c04476206801344ede391a1eafea2ef1205f8de 100644 --- a/arch/arm/src/common/up_mdelay.c +++ b/arch/arm/src/common/up_mdelay.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_mdelay.c * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/common/up_modifyreg16.c b/arch/arm/src/common/up_modifyreg16.c index e488a6eee3c6d6d83b95e037c5b5c2e4dc47a99f..32ebd6f96a95cf98e6206f0e71a83b852244073f 100644 --- a/arch/arm/src/common/up_modifyreg16.c +++ b/arch/arm/src/common/up_modifyreg16.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_modifyreg16.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/common/up_modifyreg32.c b/arch/arm/src/common/up_modifyreg32.c index 8b93f6b84fa033fe31b01bb9d274798adb349ae0..a8787328475633dff04cfb1c168df2b75c36efdf 100644 --- a/arch/arm/src/common/up_modifyreg32.c +++ b/arch/arm/src/common/up_modifyreg32.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_modifyreg32.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/common/up_modifyreg8.c b/arch/arm/src/common/up_modifyreg8.c index 2c9dbac2504c3669d72b0f470ead9c8b50129d02..92ed48eff2b6db251526c39e3145b2a67798db57 100644 --- a/arch/arm/src/common/up_modifyreg8.c +++ b/arch/arm/src/common/up_modifyreg8.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_modifyreg8.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/common/up_puts.c b/arch/arm/src/common/up_puts.c index 4e74f0cdc3182364eddb2e9ed5dd69e27c168836..f56dbf07e5722ed65bf9f33514481068d245b3fa 100644 --- a/arch/arm/src/common/up_puts.c +++ b/arch/arm/src/common/up_puts.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_puts.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/common/up_releasestack.c b/arch/arm/src/common/up_releasestack.c index 407bd1b544f031d333f9fc4ee59c6ce417a2c9c9..82f5db88ff8ce87f1d1635fc9a66eb6286a7c18a 100644 --- a/arch/arm/src/common/up_releasestack.c +++ b/arch/arm/src/common/up_releasestack.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_releasestack.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/common/up_udelay.c b/arch/arm/src/common/up_udelay.c index d2d5b74d93bb2830b8561aefe1ee67a1d869d67a..8fcb93522350716af45cbfe930ebb0d84809cd05 100644 --- a/arch/arm/src/common/up_udelay.c +++ b/arch/arm/src/common/up_udelay.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_udelay.c * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/common/up_usestack.c b/arch/arm/src/common/up_usestack.c index f46be0cc9007a03e5c4eec72fb3e8582ba2e3638..a3f4f48163e0cf64ef36f3289fd59cec783bcb30 100644 --- a/arch/arm/src/common/up_usestack.c +++ b/arch/arm/src/common/up_usestack.c @@ -2,7 +2,7 @@ * arch/arm/src/common/up_usestack.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/Make.defs b/arch/arm/src/dm320/Make.defs index 7962d81789ced06e15eef92a62d52df28f8abd51..957196672192f91bd267b5c017cd047146788d26 100644 --- a/arch/arm/src/dm320/Make.defs +++ b/arch/arm/src/dm320/Make.defs @@ -2,7 +2,7 @@ # dm320/Make.defs # # Copyright (C) 2007, 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/chip.h b/arch/arm/src/dm320/chip.h index 102d6caa365aa8867ce384a7423e122c4c3f6648..7ac681e1141cf4b774addb64d07af10bb0f336de 100644 --- a/arch/arm/src/dm320/chip.h +++ b/arch/arm/src/dm320/chip.h @@ -2,7 +2,7 @@ * arch/arm/src/dm320/chip.h * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/dm320_ahb.h b/arch/arm/src/dm320/dm320_ahb.h index 7e238f54b7de36e17d9c4e3750fc52633080a7a4..6a3654666ba993d82672693b681e442ce72b32a0 100644 --- a/arch/arm/src/dm320/dm320_ahb.h +++ b/arch/arm/src/dm320/dm320_ahb.h @@ -2,7 +2,7 @@ * dm320/dm320_uart.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/dm320_allocateheap.c b/arch/arm/src/dm320/dm320_allocateheap.c index 19875276b0e771b5e3910507e0c92e7388879aeb..5d4b900935dc6f799658ac9d285d47349667f998 100644 --- a/arch/arm/src/dm320/dm320_allocateheap.c +++ b/arch/arm/src/dm320/dm320_allocateheap.c @@ -2,7 +2,7 @@ * dm320/dm320_allocateheap.c * * Copyright (C) 2007 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/dm320_busc.h b/arch/arm/src/dm320/dm320_busc.h index b7c3287e571bcf151cf02fb192038fcf43762ba3..8c359094678aaac83d872155901f7ad03d5fe9d6 100644 --- a/arch/arm/src/dm320/dm320_busc.h +++ b/arch/arm/src/dm320/dm320_busc.h @@ -2,7 +2,7 @@ * dm320/dm320_busc.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/dm320_clkc.h b/arch/arm/src/dm320/dm320_clkc.h index 1e8e7da91d31693be6c60a80c0cfcfc861aa2771..7019b11dcee83e63fa292e69b556941f4c37a05b 100644 --- a/arch/arm/src/dm320/dm320_clkc.h +++ b/arch/arm/src/dm320/dm320_clkc.h @@ -2,7 +2,7 @@ * dm320/dm320_clkc.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/dm320_decodeirq.c b/arch/arm/src/dm320/dm320_decodeirq.c index cb3efa5b97002d22c18c8ef30c4e7be57ca05742..c7032c4b1118c64d7fa0d25c60d418007e2583cc 100644 --- a/arch/arm/src/dm320/dm320_decodeirq.c +++ b/arch/arm/src/dm320/dm320_decodeirq.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/dm320_decodeirq.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/dm320_emif.h b/arch/arm/src/dm320/dm320_emif.h index 0675595d0680718f38391bf7fe2103cc7252db7f..653e20fe0d5532f4970971a19b48e8e653e0630f 100644 --- a/arch/arm/src/dm320/dm320_emif.h +++ b/arch/arm/src/dm320/dm320_emif.h @@ -2,7 +2,7 @@ * dm320/dm320_emif.h * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/dm320_framebuffer.c b/arch/arm/src/dm320/dm320_framebuffer.c index fc29fa007fe2d1a8142c83cf9fb6a0e282428ce4..1b1197d53279d49c327503c9b7b63f168b0aca11 100644 --- a/arch/arm/src/dm320/dm320_framebuffer.c +++ b/arch/arm/src/dm320/dm320_framebuffer.c @@ -2,7 +2,7 @@ * arch/arm/src/dm320/dm320_framebuffer.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/dm320_gio.h b/arch/arm/src/dm320/dm320_gio.h index da21c67558ca021d2e7742ba2d7da655d2cae408..4ad277047c10733aad745ffed593bd1b31350ce3 100644 --- a/arch/arm/src/dm320/dm320_gio.h +++ b/arch/arm/src/dm320/dm320_gio.h @@ -2,7 +2,7 @@ * dm320/dm320_gio.h * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/dm320_intc.h b/arch/arm/src/dm320/dm320_intc.h index 245eb30ca9ff2d9b7652c730ab9cbf693c6a8362..f05febb2f953ac5a118f0e6e5f23da64700cf27c 100644 --- a/arch/arm/src/dm320/dm320_intc.h +++ b/arch/arm/src/dm320/dm320_intc.h @@ -2,7 +2,7 @@ * dm320/dm320_intc.h * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/dm320_lowputc.S b/arch/arm/src/dm320/dm320_lowputc.S index 52953fc2c6aaf0f45148b3d8dc0a692052cfd851..e60fa952724d1720df172dc7db330f11b54bfd35 100644 --- a/arch/arm/src/dm320/dm320_lowputc.S +++ b/arch/arm/src/dm320/dm320_lowputc.S @@ -3,7 +3,7 @@ * arch/arm/src/chip/dm320_lowputc.S * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/dm320_memorymap.h b/arch/arm/src/dm320/dm320_memorymap.h index 8b8e9c447efb84076de0f64c7ee48d28fdf3a2e3..a8aafbb718682ffe65736bf61cf8da1b3fa5007f 100644 --- a/arch/arm/src/dm320/dm320_memorymap.h +++ b/arch/arm/src/dm320/dm320_memorymap.h @@ -2,7 +2,7 @@ * dm320/dm320_memorymap.h * * Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/dm320_osd.h b/arch/arm/src/dm320/dm320_osd.h index 496e49ff2ba3d964f3f3e10dc14712adb74614ed..199651e6929b51f1def9280ccad5d8a139dafc8d 100644 --- a/arch/arm/src/dm320/dm320_osd.h +++ b/arch/arm/src/dm320/dm320_osd.h @@ -2,7 +2,7 @@ * dm320/dm320_osd.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/dm320_restart.S b/arch/arm/src/dm320/dm320_restart.S index ccbdfc2d9d535144cd0c8d4ddcbe4195356d589a..7e25d8ff2accbc2de0dc8f79dd3de51e5f785397 100644 --- a/arch/arm/src/dm320/dm320_restart.S +++ b/arch/arm/src/dm320/dm320_restart.S @@ -2,7 +2,7 @@ * arch/arm/src/dm320/dm320_restart.S * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/dm320_timer.h b/arch/arm/src/dm320/dm320_timer.h index 31839a091c3504a1cb63071f3a3e5cb617afe624..2ef40790673b0e4e2a90cc2f6bf2641973d14c5e 100644 --- a/arch/arm/src/dm320/dm320_timer.h +++ b/arch/arm/src/dm320/dm320_timer.h @@ -2,7 +2,7 @@ * dm320/dm320_timer.h * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/dm320_timerisr.c b/arch/arm/src/dm320/dm320_timerisr.c index 18e88b448c2e516590c48bb7b32d534af23a62b4..59efa53d35355c28b2df37f2a2611b68a9ed4382 100644 --- a/arch/arm/src/dm320/dm320_timerisr.c +++ b/arch/arm/src/dm320/dm320_timerisr.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/dm320_timerisr.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/dm320_uart.h b/arch/arm/src/dm320/dm320_uart.h index f92a5ccdd67a979bf31641deac84a30ea93a8988..d668489412075518199c52a170475331f8e97dfd 100644 --- a/arch/arm/src/dm320/dm320_uart.h +++ b/arch/arm/src/dm320/dm320_uart.h @@ -2,7 +2,7 @@ * dm320/dm320_uart.h * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/dm320/dm320_usb.h b/arch/arm/src/dm320/dm320_usb.h index 229c2857e9a5fb9dca486c04ca8c67e942ac13fa..6db7aef3d6a800e455610e9318eec0125e48cf08 100644 --- a/arch/arm/src/dm320/dm320_usb.h +++ b/arch/arm/src/dm320/dm320_usb.h @@ -2,7 +2,7 @@ * dm320/dm320_uart.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/imx/Make.defs b/arch/arm/src/imx/Make.defs index f26bd057518483dd642b77b3ed57ce37847542f8..3b2e6ad77c3d4561b1ff7d6ca2793a2b52542e40 100644 --- a/arch/arm/src/imx/Make.defs +++ b/arch/arm/src/imx/Make.defs @@ -2,7 +2,7 @@ # arch/arm/src/imx/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/arm/src/imx/chip.h b/arch/arm/src/imx/chip.h index c8a6615d7e0523e600e7d9ea0ed9b4f9ef4b9def..94985efb66d4ef299038edcb111a4ef8b1befd33 100644 --- a/arch/arm/src/imx/chip.h +++ b/arch/arm/src/imx/chip.h @@ -2,7 +2,7 @@ * arch/arm/src/imx/chip.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/imx/imx_aitc.h b/arch/arm/src/imx/imx_aitc.h index fdd8a5cf352c393c1af60d1dc5d94ded44d8369a..5b83c5f46a11a154e751cca595419945245da8b5 100644 --- a/arch/arm/src/imx/imx_aitc.h +++ b/arch/arm/src/imx/imx_aitc.h @@ -2,7 +2,7 @@ * arch/arm/src/imx/imx_aitc.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/imx/imx_allocateheap.c b/arch/arm/src/imx/imx_allocateheap.c index a42b2fb85ebe4cf74cb411d80bf3a08d0606cf00..4831c8c8b92f4f18b2cab38b36a051d262a5a12c 100644 --- a/arch/arm/src/imx/imx_allocateheap.c +++ b/arch/arm/src/imx/imx_allocateheap.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/imx_allocateheap.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/imx/imx_cspi.h b/arch/arm/src/imx/imx_cspi.h index 421b6a4e31f8b18f8a1877d5ae67c08118171839..1a60730d573092fdb0bce0c5e455b3bf9ddef1c2 100755 --- a/arch/arm/src/imx/imx_cspi.h +++ b/arch/arm/src/imx/imx_cspi.h @@ -2,7 +2,7 @@ * arch/arm/src/imx/imx_cspi.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/imx/imx_decodeirq.c b/arch/arm/src/imx/imx_decodeirq.c index 55c72ed76f0fec275d35cb20c2dc00da904aa477..ba37a60a2e44b4715bae86be9f82719941ff308d 100644 --- a/arch/arm/src/imx/imx_decodeirq.c +++ b/arch/arm/src/imx/imx_decodeirq.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/imx_decodeirq.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/imx/imx_dma.h b/arch/arm/src/imx/imx_dma.h index bf3b03673d123e60598193683f36aacc39427842..2d5d553ce6cbc3dff6ed267cb80757bcdf0c8ed9 100755 --- a/arch/arm/src/imx/imx_dma.h +++ b/arch/arm/src/imx/imx_dma.h @@ -1,250 +1,250 @@ -/************************************************************************************ - * arch/arm/src/imx/imx_dma.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_IMX_DMA_H -#define __ARCH_ARM_IMX_DMA_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* DMA Register Offsets *************************************************************/ - -#define DMA_SYS_OFFSET 0x0000 -#define DMA_M2D_OFFSET 0x0040 -#define DMA_CH0_OFFSET 0x0080 -#define DMA_CH1_OFFSET 0x00c0 -#define DMA_CH2_OFFSET 0x0100 -#define DMA_CH3_OFFSET 0x0140 -#define DMA_CH4_OFFSET 0x0180 -#define DMA_CH5_OFFSET 0x01C0 -#define DMA_CH6_OFFSET 0x0200 -#define DMA_CH7_OFFSET 0x0240 -#define DMA_CH8_OFFSET 0x0280 -#define DMA_CH9_OFFSET 0x02c0 -#define DMA_CH10_OFFSET 0x0300 -#define DMA_CH_OFFSET(n) (DMA_CH0_OFFSET + (n)*0x0040) -#define DMA_TST_OFFSET 0x0340 - -#define DMA_DCR_OFFSET 0x0000 -#define DMA_ISR_OFFSET 0x0004 -#define DMA_IMR_OFFSET 0x0008 -#define DMA_BTOSR_OFFSET 0x000c -#define DMA_RTOSR_OFFSET 0x0010 -#define DMA_TESR_OFFSET 0x0014 -#define DMA_BOSR_OFFSET 0x0018 -#define DMA_BTOCR_OFFSET 0x001c - -#define DMA_WSRA_OFFSET 0x0000 -#define DMA_XSRA_OFFSET 0x0004 -#define DMA_YSRA_OFFSET 0x0008 -#define DMA_WSRB_OFFSET 0x000c -#define DMA_XSRB_OFFSET 0x0010 -#define DMA_YSRB_OFFSET 0x0014 - -#define DMA_SAR_OFFSET 0x0000 -#define DMA_DAR_OFFSET 0x0004 -#define DMA_CNTR_OFFSET 0x0008 -#define DMA_CCR_OFFSET 0x000c -#define DMA_RSSR_OFFSET 0x0010 -#define DMA_BLR_OFFSET 0x0014 -#define DMA_RTOR_OFFSET 0x0018 -#define DMA_BUCR_OFFSET 0x0018 - -#define DMA_TCR_OFFSET 0x0000 -#define DMA_TFIFOA_OFFSET 0x0004 -#define DMA_TDRR_OFFSET 0x0008 -#define DMA_TDIPR_OFFSET 0x000c -#define DMA_TFIFOB_OFFSET 0x0010 - -/* DMA Register Addresses ***********************************************************/ - -#define IMX_DMA_SYS_BASE (IMX_DMA_VBASE + DMA_SYS_OFFSET) -#define IMX_DMA_M2D_BASE (IMX_DMA_VBASE + DMA_M2D_OFFSET) -#define IMX_DMA_CH0_BASE (IMX_DMA_VBASE + DMA_CH0_OFFSET) -#define IMX_DMA_CH1_BASE (IMX_DMA_VBASE + DMA_CH1_OFFSET) -#define IMX_DMA_CH2_BASE (IMX_DMA_VBASE + DMA_CH2_OFFSET) -#define IMX_DMA_CH3_BASE (IMX_DMA_VBASE + DMA_CH3_OFFSET) -#define IMX_DMA_CH4_BASE (IMX_DMA_VBASE + DMA_CH4_OFFSET) -#define IMX_DMA_CH5_BASE (IMX_DMA_VBASE + DMA_CH5_OFFSET) -#define IMX_DMA_CH6_BASE (IMX_DMA_VBASE + DMA_CH6_OFFSET) -#define IMX_DMA_CH7_BASE (IMX_DMA_VBASE + DMA_CH7_OFFSET) -#define IMX_DMA_CH8_BASE (IMX_DMA_VBASE + DMA_CH8_OFFSET) -#define IMX_DMA_CH9_BASE (IMX_DMA_VBASE + DMA_CH9_OFFSET) -#define IMX_DMA_CH10_BASE (IMX_DMA_VBASE + DMA_CH10_OFFSET) -#define IMX_DMA_CH_BASE(n) (IMX_DMA_VBASE + DMA_CH_OFFSET(n)) -#define IMX_DMA_TST_BASE (IMX_DMA_VBASE + DMA_TST_OFFSET) - -#define IMX_DMA_DCR (DMA_SYS_BASE + DMA_DCR_OFFSET) -#define IMX_DMA_ISR (DMA_SYS_BASE + DMA_ISR_OFFSET) -#define IMX_DMA_IMR (DMA_SYS_BASE + DMA_IMR_OFFSET) -#define IMX_DMA_BTOSR (DMA_SYS_BASE + DMA_BTOSR_OFFSET) -#define IMX_DMA_RTOSR (DMA_SYS_BASE + DMA_RTOSR_OFFSET) -#define IMX_DMA_TESR (DMA_SYS_BASE + DMA_TESR_OFFSET) -#define IMX_DMA_BOSR (DMA_SYS_BASE + DMA_BOSR_OFFSET) -#define IMX_DMA_BTOCR (DMA_SYS_BASE + DMA_BTOCR_OFFSET) - -#define IMX_DMA_WSRA (DMA_M2D_BASE + DMA_WSRA_OFFSET) -#define IMX_DMA_XSRA (DMA_M2D_BASE + DMA_XSRA_OFFSET) -#define IMX_DMA_YSRA (DMA_M2D_BASE + DMA_YSRA_OFFSET) -#define IMX_DMA_WSRB (DMA_M2D_BASE + DMA_WSRB_OFFSET) -#define IMX_DMA_XSRB (DMA_M2D_BASE + DMA_XSRB_OFFSET) -#define IMX_DMA_YSRB (DMA_M2D_BASE + DMA_YSRB_OFFSET) - -#define IMX_DMA_SAR0 (DMA_CH0_BASE + DMA_SAR_OFFSET) -#define IMX_DMA_DAR0 (DMA_CH0_BASE + DMA_DAR_OFFSET) -#define IMX_DMA_CNTR0 (DMA_CH0_BASE + DMA_CNTR_OFFSET) -#define IMX_DMA_CCR0 (DMA_CH0_BASE + DMA_CCR_OFFSET) -#define IMX_DMA_RSSR0 (DMA_CH0_BASE + DMA_RSSR_OFFSET) -#define IMX_DMA_BLR0 (DMA_CH0_BASE + DMA_BLR_OFFSET) -#define IMX_DMA_RTOR0 (DMA_CH0_BASE + DMA_RTOR_OFFSET) -#define IMX_DMA_BUCR0 (DMA_CH0_BASE + DMA_BUCR_OFFSET) - -#define IMX_DMA_SAR1 (DMA_CH1_BASE + DMA_SAR_OFFSET) -#define IMX_DMA_DAR1 (DMA_CH1_BASE + DMA_DAR_OFFSET) -#define IMX_DMA_CNTR1 (DMA_CH1_BASE + DMA_CNTR_OFFSET) -#define IMX_DMA_CCR1 (DMA_CH1_BASE + DMA_CCR_OFFSET) -#define IMX_DMA_RSSR1 (DMA_CH1_BASE + DMA_RSSR_OFFSET) -#define IMX_DMA_BLR1 (DMA_CH1_BASE + DMA_BLR_OFFSET) -#define IMX_DMA_RTOR1 (DMA_CH1_BASE + DMA_RTOR_OFFSET) -#define IMX_DMA_BUCR1 (DMA_CH1_BASE + DMA_BUCR_OFFSET) - -#define IMX_DMA_SAR2 (DMA_CH2_BASE + DMA_SAR_OFFSET) -#define IMX_DMA_DAR2 (DMA_CH2_BASE + DMA_DAR_OFFSET) -#define IMX_DMA_CNTR2 (DMA_CH2_BASE + DMA_CNTR_OFFSET) -#define IMX_DMA_CCR2 (DMA_CH2_BASE + DMA_CCR_OFFSET) -#define IMX_DMA_RSSR2 (DMA_CH2_BASE + DMA_RSSR_OFFSET) -#define IMX_DMA_BLR2 (DMA_CH2_BASE + DMA_BLR_OFFSET) -#define IMX_DMA_RTOR2 (DMA_CH2_BASE + DMA_RTOR_OFFSET) -#define IMX_DMA_BUCR2 (DMA_CH2_BASE + DMA_BUCR_OFFSET) - -#define IMX_DMA_SAR3 (DMA_CH3_BASE + DMA_SAR_OFFSET) -#define IMX_DMA_DAR3 (DMA_CH3_BASE + DMA_DAR_OFFSET) -#define IMX_DMA_CNTR3 (DMA_CH3_BASE + DMA_CNTR_OFFSET) -#define IMX_DMA_CCR3 (DMA_CH3_BASE + DMA_CCR_OFFSET) -#define IMX_DMA_RSSR3 (DMA_CH3_BASE + DMA_RSSR_OFFSET) -#define IMX_DMA_BLR3 (DMA_CH3_BASE + DMA_BLR_OFFSET) -#define IMX_DMA_RTOR3 (DMA_CH3_BASE + DMA_RTOR_OFFSET) -#define IMX_DMA_BUCR3 (DMA_CH3_BASE + DMA_BUCR_OFFSET) - -#define IMX_DMA_SAR4 (DMA_CH4_BASE + DMA_SAR_OFFSET) -#define IMX_DMA_DAR4 (DMA_CH4_BASE + DMA_DAR_OFFSET) -#define IMX_DMA_CNTR4 (DMA_CH4_BASE + DMA_CNTR_OFFSET) -#define IMX_DMA_CCR4 (DMA_CH4_BASE + DMA_CCR_OFFSET) -#define IMX_DMA_RSSR4 (DMA_CH4_BASE + DMA_RSSR_OFFSET) -#define IMX_DMA_BLR4 (DMA_CH4_BASE + DMA_BLR_OFFSET) -#define IMX_DMA_RTOR4 (DMA_CH4_BASE + DMA_RTOR_OFFSET) -#define IMX_DMA_BUCR4 (DMA_CH4_BASE + DMA_BUCR_OFFSET) - -#define IMX_DMA_SAR5 (DMA_CH5_BASE + DMA_SAR_OFFSET) -#define IMX_DMA_DAR5 (DMA_CH5_BASE + DMA_DAR_OFFSET) -#define IMX_DMA_CNTR5 (DMA_CH5_BASE + DMA_CNTR_OFFSET) -#define IMX_DMA_CCR5 (DMA_CH5_BASE + DMA_CCR_OFFSET) -#define IMX_DMA_RSSR5 (DMA_CH5_BASE + DMA_RSSR_OFFSET) -#define IMX_DMA_BLR5 (DMA_CH5_BASE + DMA_BLR_OFFSET) -#define IMX_DMA_RTOR5 (DMA_CH5_BASE + DMA_RTOR_OFFSET) -#define IMX_DMA_BUCR5 (DMA_CH5_BASE + DMA_BUCR_OFFSET) - -#define IMX_DMA_SAR6 (DMA_CH6_BASE + DMA_SAR_OFFSET) -#define IMX_DMA_DAR6 (DMA_CH6_BASE + DMA_DAR_OFFSET) -#define IMX_DMA_CNTR6 (DMA_CH6_BASE + DMA_CNTR_OFFSET) -#define IMX_DMA_CCR6 (DMA_CH6_BASE + DMA_CCR_OFFSET) -#define IMX_DMA_RSSR6 (DMA_CH6_BASE + DMA_RSSR_OFFSET) -#define IMX_DMA_BLR6 (DMA_CH6_BASE + DMA_BLR_OFFSET) -#define IMX_DMA_RTOR6 (DMA_CH6_BASE + DMA_RTOR_OFFSET) -#define IMX_DMA_BUCR6 (DMA_CH6_BASE + DMA_BUCR_OFFSET) - -#define IMX_DMA_SAR7 (DMA_CH7_BASE + DMA_SAR_OFFSET) -#define IMX_DMA_DAR7 (DMA_CH7_BASE + DMA_DAR_OFFSET) -#define IMX_DMA_CNTR7 (DMA_CH7_BASE + DMA_CNTR_OFFSET) -#define IMX_DMA_CCR7 (DMA_CH7_BASE + DMA_CCR_OFFSET) -#define IMX_DMA_RSSR7 (DMA_CH7_BASE + DMA_RSSR_OFFSET) -#define IMX_DMA_BLR7 (DMA_CH7_BASE + DMA_BLR_OFFSET) -#define IMX_DMA_RTOR7 (DMA_CH7_BASE + DMA_RTOR_OFFSET) -#define IMX_DMA_BUCR7 (DMA_CH7_BASE + DMA_BUCR_OFFSET) - -#define IMX_DMA_SAR8 (DMA_CH8_BASE + DMA_SAR_OFFSET) -#define IMX_DMA_DAR8 (DMA_CH8_BASE + DMA_DAR_OFFSET) -#define IMX_DMA_CNTR8 (DMA_CH8_BASE + DMA_CNTR_OFFSET) -#define IMX_DMA_CCR8 (DMA_CH8_BASE + DMA_CCR_OFFSET) -#define IMX_DMA_RSSR8 (DMA_CH8_BASE + DMA_RSSR_OFFSET) -#define IMX_DMA_BLR8 (DMA_CH8_BASE + DMA_BLR_OFFSET) -#define IMX_DMA_RTOR8 (DMA_CH8_BASE + DMA_RTOR_OFFSET) -#define IMX_DMA_BUCR8 (DMA_CH8_BASE + DMA_BUCR_OFFSET) - -#define IMX_DMA_SAR9 (DMA_CH9_BASE + DMA_SAR_OFFSET) -#define IMX_DMA_DAR9 (DMA_CH9_BASE + DMA_DAR_OFFSET) -#define IMX_DMA_CNTR9 (DMA_CH9_BASE + DMA_CNTR_OFFSET) -#define IMX_DMA_CCR9 (DMA_CH9_BASE + DMA_CCR_OFFSET) -#define IMX_DMA_RSSR9 (DMA_CH9_BASE + DMA_RSSR_OFFSET) -#define IMX_DMA_BLR9 (DMA_CH9_BASE + DMA_BLR_OFFSET) -#define IMX_DMA_RTOR9 (DMA_CH9_BASE + DMA_RTOR_OFFSET) -#define IMX_DMA_BUCR9 (DMA_CH9_BASE + DMA_BUCR_OFFSET) - -#define IMX_DMA_SAR10 (DMA_CH10_BASE + DMA_SAR_OFFSET) -#define IMX_DMA_DAR10 (DMA_CH10_BASE + DMA_DAR_OFFSET) -#define IMX_DMA_CNTR10 (DMA_CH10_BASE + DMA_CNTR_OFFSET) -#define IMX_DMA_CCR10 (DMA_CH10_BASE + DMA_CCR_OFFSET) -#define IMX_DMA_RSSR10 (DMA_CH10_BASE + DMA_RSSR_OFFSET) -#define IMX_DMA_BLR10 (DMA_CH10_BASE + DMA_BLR_OFFSET) -#define IMX_DMA_RTOR10 (DMA_CH10_BASE + DMA_RTOR_OFFSET) -#define IMX_DMA_BUCR10 (DMA_CH10_BASE + DMA_BUCR_OFFSET) - -#define IMX_DMA_SAR(n) (DMA_CH_BASE(n) + DMA_SAR_OFFSET) -#define IMX_DMA_DAR(n) (DMA_CH_BASE(n) + DMA_DAR_OFFSET) -#define IMX_DMA_CNTR(n) (DMA_CH_BASE(n) + DMA_CNTR_OFFSET) -#define IMX_DMA_CCR(n) (DMA_CH_BASE(n) + DMA_CCR_OFFSET) -#define IMX_DMA_RSSR(n) (DMA_CH_BASE(n) + DMA_RSSR_OFFSET) -#define IMX_DMA_BLR(n) (DMA_CH_BASE(n) + DMA_BLR_OFFSET) -#define IMX_DMA_RTOR(n) (DMA_CH_BASE(n) + DMA_RTOR_OFFSET) -#define IMX_DMA_BUCR(n) (DMA_CH_BASE(n) + DMA_BUCR_OFFSET) - -#define IMX_DMA_TCR (DMA_TST_BASE + DMA_TCR_OFFSET) -#define IMX_DMA_TFIFOA (DMA_TST_BASE + DMA_TFIFOA_OFFSET) -#define IMX_DMA_TDRR (DMA_TST_BASE + DMA_TDRR_OFFSET) -#define IMX_DMA_TDIPR (DMA_TST_BASE + DMA_TDIPR_OFFSET) -#define IMX_DMA_TFIFOB (DMA_TST_BASE + DMA_TFIFOB_OFFSET) - -/* DMA Register Bit Definitions *****************************************************/ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_IMX_DMA_H */ +/************************************************************************************ + * arch/arm/src/imx/imx_dma.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_DMA_H +#define __ARCH_ARM_IMX_DMA_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* DMA Register Offsets *************************************************************/ + +#define DMA_SYS_OFFSET 0x0000 +#define DMA_M2D_OFFSET 0x0040 +#define DMA_CH0_OFFSET 0x0080 +#define DMA_CH1_OFFSET 0x00c0 +#define DMA_CH2_OFFSET 0x0100 +#define DMA_CH3_OFFSET 0x0140 +#define DMA_CH4_OFFSET 0x0180 +#define DMA_CH5_OFFSET 0x01C0 +#define DMA_CH6_OFFSET 0x0200 +#define DMA_CH7_OFFSET 0x0240 +#define DMA_CH8_OFFSET 0x0280 +#define DMA_CH9_OFFSET 0x02c0 +#define DMA_CH10_OFFSET 0x0300 +#define DMA_CH_OFFSET(n) (DMA_CH0_OFFSET + (n)*0x0040) +#define DMA_TST_OFFSET 0x0340 + +#define DMA_DCR_OFFSET 0x0000 +#define DMA_ISR_OFFSET 0x0004 +#define DMA_IMR_OFFSET 0x0008 +#define DMA_BTOSR_OFFSET 0x000c +#define DMA_RTOSR_OFFSET 0x0010 +#define DMA_TESR_OFFSET 0x0014 +#define DMA_BOSR_OFFSET 0x0018 +#define DMA_BTOCR_OFFSET 0x001c + +#define DMA_WSRA_OFFSET 0x0000 +#define DMA_XSRA_OFFSET 0x0004 +#define DMA_YSRA_OFFSET 0x0008 +#define DMA_WSRB_OFFSET 0x000c +#define DMA_XSRB_OFFSET 0x0010 +#define DMA_YSRB_OFFSET 0x0014 + +#define DMA_SAR_OFFSET 0x0000 +#define DMA_DAR_OFFSET 0x0004 +#define DMA_CNTR_OFFSET 0x0008 +#define DMA_CCR_OFFSET 0x000c +#define DMA_RSSR_OFFSET 0x0010 +#define DMA_BLR_OFFSET 0x0014 +#define DMA_RTOR_OFFSET 0x0018 +#define DMA_BUCR_OFFSET 0x0018 + +#define DMA_TCR_OFFSET 0x0000 +#define DMA_TFIFOA_OFFSET 0x0004 +#define DMA_TDRR_OFFSET 0x0008 +#define DMA_TDIPR_OFFSET 0x000c +#define DMA_TFIFOB_OFFSET 0x0010 + +/* DMA Register Addresses ***********************************************************/ + +#define IMX_DMA_SYS_BASE (IMX_DMA_VBASE + DMA_SYS_OFFSET) +#define IMX_DMA_M2D_BASE (IMX_DMA_VBASE + DMA_M2D_OFFSET) +#define IMX_DMA_CH0_BASE (IMX_DMA_VBASE + DMA_CH0_OFFSET) +#define IMX_DMA_CH1_BASE (IMX_DMA_VBASE + DMA_CH1_OFFSET) +#define IMX_DMA_CH2_BASE (IMX_DMA_VBASE + DMA_CH2_OFFSET) +#define IMX_DMA_CH3_BASE (IMX_DMA_VBASE + DMA_CH3_OFFSET) +#define IMX_DMA_CH4_BASE (IMX_DMA_VBASE + DMA_CH4_OFFSET) +#define IMX_DMA_CH5_BASE (IMX_DMA_VBASE + DMA_CH5_OFFSET) +#define IMX_DMA_CH6_BASE (IMX_DMA_VBASE + DMA_CH6_OFFSET) +#define IMX_DMA_CH7_BASE (IMX_DMA_VBASE + DMA_CH7_OFFSET) +#define IMX_DMA_CH8_BASE (IMX_DMA_VBASE + DMA_CH8_OFFSET) +#define IMX_DMA_CH9_BASE (IMX_DMA_VBASE + DMA_CH9_OFFSET) +#define IMX_DMA_CH10_BASE (IMX_DMA_VBASE + DMA_CH10_OFFSET) +#define IMX_DMA_CH_BASE(n) (IMX_DMA_VBASE + DMA_CH_OFFSET(n)) +#define IMX_DMA_TST_BASE (IMX_DMA_VBASE + DMA_TST_OFFSET) + +#define IMX_DMA_DCR (DMA_SYS_BASE + DMA_DCR_OFFSET) +#define IMX_DMA_ISR (DMA_SYS_BASE + DMA_ISR_OFFSET) +#define IMX_DMA_IMR (DMA_SYS_BASE + DMA_IMR_OFFSET) +#define IMX_DMA_BTOSR (DMA_SYS_BASE + DMA_BTOSR_OFFSET) +#define IMX_DMA_RTOSR (DMA_SYS_BASE + DMA_RTOSR_OFFSET) +#define IMX_DMA_TESR (DMA_SYS_BASE + DMA_TESR_OFFSET) +#define IMX_DMA_BOSR (DMA_SYS_BASE + DMA_BOSR_OFFSET) +#define IMX_DMA_BTOCR (DMA_SYS_BASE + DMA_BTOCR_OFFSET) + +#define IMX_DMA_WSRA (DMA_M2D_BASE + DMA_WSRA_OFFSET) +#define IMX_DMA_XSRA (DMA_M2D_BASE + DMA_XSRA_OFFSET) +#define IMX_DMA_YSRA (DMA_M2D_BASE + DMA_YSRA_OFFSET) +#define IMX_DMA_WSRB (DMA_M2D_BASE + DMA_WSRB_OFFSET) +#define IMX_DMA_XSRB (DMA_M2D_BASE + DMA_XSRB_OFFSET) +#define IMX_DMA_YSRB (DMA_M2D_BASE + DMA_YSRB_OFFSET) + +#define IMX_DMA_SAR0 (DMA_CH0_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR0 (DMA_CH0_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR0 (DMA_CH0_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR0 (DMA_CH0_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR0 (DMA_CH0_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR0 (DMA_CH0_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR0 (DMA_CH0_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR0 (DMA_CH0_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR1 (DMA_CH1_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR1 (DMA_CH1_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR1 (DMA_CH1_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR1 (DMA_CH1_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR1 (DMA_CH1_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR1 (DMA_CH1_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR1 (DMA_CH1_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR1 (DMA_CH1_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR2 (DMA_CH2_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR2 (DMA_CH2_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR2 (DMA_CH2_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR2 (DMA_CH2_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR2 (DMA_CH2_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR2 (DMA_CH2_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR2 (DMA_CH2_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR2 (DMA_CH2_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR3 (DMA_CH3_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR3 (DMA_CH3_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR3 (DMA_CH3_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR3 (DMA_CH3_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR3 (DMA_CH3_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR3 (DMA_CH3_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR3 (DMA_CH3_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR3 (DMA_CH3_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR4 (DMA_CH4_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR4 (DMA_CH4_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR4 (DMA_CH4_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR4 (DMA_CH4_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR4 (DMA_CH4_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR4 (DMA_CH4_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR4 (DMA_CH4_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR4 (DMA_CH4_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR5 (DMA_CH5_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR5 (DMA_CH5_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR5 (DMA_CH5_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR5 (DMA_CH5_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR5 (DMA_CH5_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR5 (DMA_CH5_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR5 (DMA_CH5_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR5 (DMA_CH5_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR6 (DMA_CH6_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR6 (DMA_CH6_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR6 (DMA_CH6_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR6 (DMA_CH6_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR6 (DMA_CH6_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR6 (DMA_CH6_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR6 (DMA_CH6_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR6 (DMA_CH6_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR7 (DMA_CH7_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR7 (DMA_CH7_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR7 (DMA_CH7_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR7 (DMA_CH7_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR7 (DMA_CH7_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR7 (DMA_CH7_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR7 (DMA_CH7_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR7 (DMA_CH7_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR8 (DMA_CH8_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR8 (DMA_CH8_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR8 (DMA_CH8_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR8 (DMA_CH8_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR8 (DMA_CH8_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR8 (DMA_CH8_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR8 (DMA_CH8_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR8 (DMA_CH8_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR9 (DMA_CH9_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR9 (DMA_CH9_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR9 (DMA_CH9_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR9 (DMA_CH9_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR9 (DMA_CH9_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR9 (DMA_CH9_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR9 (DMA_CH9_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR9 (DMA_CH9_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR10 (DMA_CH10_BASE + DMA_SAR_OFFSET) +#define IMX_DMA_DAR10 (DMA_CH10_BASE + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR10 (DMA_CH10_BASE + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR10 (DMA_CH10_BASE + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR10 (DMA_CH10_BASE + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR10 (DMA_CH10_BASE + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR10 (DMA_CH10_BASE + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR10 (DMA_CH10_BASE + DMA_BUCR_OFFSET) + +#define IMX_DMA_SAR(n) (DMA_CH_BASE(n) + DMA_SAR_OFFSET) +#define IMX_DMA_DAR(n) (DMA_CH_BASE(n) + DMA_DAR_OFFSET) +#define IMX_DMA_CNTR(n) (DMA_CH_BASE(n) + DMA_CNTR_OFFSET) +#define IMX_DMA_CCR(n) (DMA_CH_BASE(n) + DMA_CCR_OFFSET) +#define IMX_DMA_RSSR(n) (DMA_CH_BASE(n) + DMA_RSSR_OFFSET) +#define IMX_DMA_BLR(n) (DMA_CH_BASE(n) + DMA_BLR_OFFSET) +#define IMX_DMA_RTOR(n) (DMA_CH_BASE(n) + DMA_RTOR_OFFSET) +#define IMX_DMA_BUCR(n) (DMA_CH_BASE(n) + DMA_BUCR_OFFSET) + +#define IMX_DMA_TCR (DMA_TST_BASE + DMA_TCR_OFFSET) +#define IMX_DMA_TFIFOA (DMA_TST_BASE + DMA_TFIFOA_OFFSET) +#define IMX_DMA_TDRR (DMA_TST_BASE + DMA_TDRR_OFFSET) +#define IMX_DMA_TDIPR (DMA_TST_BASE + DMA_TDIPR_OFFSET) +#define IMX_DMA_TFIFOB (DMA_TST_BASE + DMA_TFIFOB_OFFSET) + +/* DMA Register Bit Definitions *****************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_DMA_H */ diff --git a/arch/arm/src/imx/imx_eim.h b/arch/arm/src/imx/imx_eim.h index 50849794a24dccf6b8d5a8ed7c00ec5341f8f8a5..decd54e46a7c124f93cf1f3c84bedb065a313054 100755 --- a/arch/arm/src/imx/imx_eim.h +++ b/arch/arm/src/imx/imx_eim.h @@ -1,85 +1,85 @@ -/************************************************************************************ - * arch/arm/src/imx/imx_eim.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_IMX_WIEM_H -#define __ARCH_ARM_IMX_WIEM_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* EIM Register Offsets ************************************************************/ - -#define EIM_CS0H_OFFSET 0x00 -#define EIM_CS0L_OFFSET 0x04 -#define EIM_CS1H_OFFSET 0x08 -#define EIM_CS1L_OFFSET 0x0c -#define EIM_CS2H_OFFSET 0x10 -#define EIM_CS2L_OFFSET 0x14 -#define EIM_CS3H_OFFSET 0x18 -#define EIM_CS3L_OFFSET 0x1c -#define EIM_CS4H_OFFSET 0x20 -#define EIM_CS4L_OFFSET 0x24 -#define EIM_CS5H_OFFSET 0x28 -#define EIM_CS5L_OFFSET 0x2c -#define EIM_WEIM_OFFSET 0x30 - -/* EIM Register Addresses ***********************************************************/ - -#define IMX_EIM_CS0H (EIM_BASE_ADDR + EIM_CS0H_OFFSET) -#define IMX_EIM_CS0L (EIM_BASE_ADDR + EIM_CS0L_OFFSET) -#define IMX_EIM_CS1H (EIM_BASE_ADDR + EIM_CS1H_OFFSET) -#define IMX_EIM_CS1L (EIM_BASE_ADDR + EIM_CS1L_OFFSET) -#define IMX_EIM_CS2H (EIM_BASE_ADDR + EIM_CS2H_OFFSET) -#define IMX_EIM_CS2L (EIM_BASE_ADDR + EIM_CS2L_OFFSET) -#define IMX_EIM_CS3H (EIM_BASE_ADDR + EIM_CS3H_OFFSET) -#define IMX_EIM_CS3L (EIM_BASE_ADDR + EIM_CS3L_OFFSET) -#define IMX_EIM_CS4H (EIM_BASE_ADDR + EIM_CS4H_OFFSET) -#define IMX_EIM_CS4L (EIM_BASE_ADDR + EIM_CS4L_OFFSET) -#define IMX_EIM_CS5H (EIM_BASE_ADDR + EIM_CS5H_OFFSET) -#define IMX_EIM_CS5L (EIM_BASE_ADDR + EIM_CS5L_OFFSET) -#define IMX_EIM_WEIM (EIM_BASE_ADDR + EIM_WEIM_OFFSET) - -/* EIM Register Bit Definitions *****************************************************/ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_IMX_EIM_H */ +/************************************************************************************ + * arch/arm/src/imx/imx_eim.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_WIEM_H +#define __ARCH_ARM_IMX_WIEM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* EIM Register Offsets ************************************************************/ + +#define EIM_CS0H_OFFSET 0x00 +#define EIM_CS0L_OFFSET 0x04 +#define EIM_CS1H_OFFSET 0x08 +#define EIM_CS1L_OFFSET 0x0c +#define EIM_CS2H_OFFSET 0x10 +#define EIM_CS2L_OFFSET 0x14 +#define EIM_CS3H_OFFSET 0x18 +#define EIM_CS3L_OFFSET 0x1c +#define EIM_CS4H_OFFSET 0x20 +#define EIM_CS4L_OFFSET 0x24 +#define EIM_CS5H_OFFSET 0x28 +#define EIM_CS5L_OFFSET 0x2c +#define EIM_WEIM_OFFSET 0x30 + +/* EIM Register Addresses ***********************************************************/ + +#define IMX_EIM_CS0H (EIM_BASE_ADDR + EIM_CS0H_OFFSET) +#define IMX_EIM_CS0L (EIM_BASE_ADDR + EIM_CS0L_OFFSET) +#define IMX_EIM_CS1H (EIM_BASE_ADDR + EIM_CS1H_OFFSET) +#define IMX_EIM_CS1L (EIM_BASE_ADDR + EIM_CS1L_OFFSET) +#define IMX_EIM_CS2H (EIM_BASE_ADDR + EIM_CS2H_OFFSET) +#define IMX_EIM_CS2L (EIM_BASE_ADDR + EIM_CS2L_OFFSET) +#define IMX_EIM_CS3H (EIM_BASE_ADDR + EIM_CS3H_OFFSET) +#define IMX_EIM_CS3L (EIM_BASE_ADDR + EIM_CS3L_OFFSET) +#define IMX_EIM_CS4H (EIM_BASE_ADDR + EIM_CS4H_OFFSET) +#define IMX_EIM_CS4L (EIM_BASE_ADDR + EIM_CS4L_OFFSET) +#define IMX_EIM_CS5H (EIM_BASE_ADDR + EIM_CS5H_OFFSET) +#define IMX_EIM_CS5L (EIM_BASE_ADDR + EIM_CS5L_OFFSET) +#define IMX_EIM_WEIM (EIM_BASE_ADDR + EIM_WEIM_OFFSET) + +/* EIM Register Bit Definitions *****************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_EIM_H */ diff --git a/arch/arm/src/imx/imx_gpio.c b/arch/arm/src/imx/imx_gpio.c index f6099310f63c8705853dbb9c18a3b2f7a3d64b44..94e87fdfef0c457ee5f306c1a121e2476a951a6a 100644 --- a/arch/arm/src/imx/imx_gpio.c +++ b/arch/arm/src/imx/imx_gpio.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/imx_gpio.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/imx/imx_gpio.h b/arch/arm/src/imx/imx_gpio.h index 26c1c43465e047418b3a33bac449428ccf21ad77..dcdf9c68e3170f7b8af79a3eaaee4ba36b58096a 100755 --- a/arch/arm/src/imx/imx_gpio.h +++ b/arch/arm/src/imx/imx_gpio.h @@ -1,562 +1,562 @@ -/************************************************************************************ - * arch/arm/src/imx/imx_gpio.h - * arch/arm/src/chip/imx_gpio.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_IMX_GPIO_H -#define __ARCH_ARM_IMX_GPIO_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#ifndef __ASSEMBLY__ -# include -#endif -#include "up_arch.h" /* getreg32(), putreg32() */ - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* GPIO Register Offsets ************************************************************/ - -#define GPIO_DDIR_OFFSET 0x0000 /* Data Direction Register */ -#define GPIO_OCR1_OFFSET 0x0004 /* Output Configuration Register 1 */ -#define GPIO_OCR2_OFFSET 0x0008 /* Output Configuration Register 2 */ -#define GPIO_ICONFA1_OFFSET 0x000c /* Input Configuration Register A1 */ -#define GPIO_ICONFA2_OFFSET 0x0010 /* Input Configuration Register A2 */ -#define GPIO_ICONFB1_OFFSET 0x0014 /* Input Configuration Register B1 */ -#define GPIO_ICONFB2_OFFSET 0x0018 /* Input Configuration Register B2 */ -#define GPIO_DR_OFFSET 0x001c /* Data Register */ -#define GPIO_GIUS_OFFSET 0x0020 /* GPIO In Use Register */ -#define GPIO_SSR_OFFSET 0x0024 /* Sample Status Register */ -#define GPIO_ICR1_OFFSET 0x0028 /* Interrupt Configuration Register 1 */ -#define GPIO_ICR2_OFFSET 0x002c /* Interrupt Configuration Register 2 */ -#define GPIO_IMR_OFFSET 0x0030 /* Interrupt Mask Register */ -#define GPIO_ISR_OFFSET 0x0034 /* Interrupt Status Register */ -#define GPIO_GPR_OFFSET 0x0038 /* General Purpose Register */ -#define GPIO_SWR_OFFSET 0x003c /* Software Reset Register */ -#define GPIO_PUEN_OFFSET 0x0040 /* Pull_Up Enable Register */ - -#define GPIO_PTA_OFFSET 0x0000 /* Port A offset */ -#define GPIO_PTB_OFFSET 0x0100 /* Port B offset */ -#define GPIO_PTC_OFFSET 0x0200 /* Port C offset */ -#define GPIO_PTD_OFFSET 0x0300 /* Port D offset */ - -#define GPIOA 0 /* Port A index */ -#define GPIOB 1 /* Port B index */ -#define GPIOC 2 /* Port C index */ -#define GPIOD 3 /* Port D index */ -#define GPIO_PT_OFFSET(n) (GPIO_PTA_OFFSET + (n)*0x0100) - -/* GPIO Register Addresses **********************************************************/ - -#define IMX_PTA_VBASE (IMX_GPIO_VBASE + GPIO_PTA_OFFSET) -#define IMX_PTB_VBASE (IMX_GPIO_VBASE + GPIO_PTB_OFFSET) -#define IMX_PTC_VBASE (IMX_GPIO_VBASE + GPIO_PTC_OFFSET) -#define IMX_PTD_VBASE (IMX_GPIO_VBASE + GPIO_PTD_OFFSET) -#define IMX_PT_VBASE(n) (IMX_GPIO_VBASE + GPIO_PT_OFFSET(n)) - -#define IMX_GPIOA_DDIR (IMX_PTA_VBASE + GPIO_DDIR_OFFSET) -#define IMX_GPIOA_OCR1 (IMX_PTA_VBASE + GPIO_OCR1_OFFSET) -#define IMX_GPIOA_OCR2 (IMX_PTA_VBASE + GPIO_OCR2_OFFSET) -#define IMX_GPIOA_ICONFA1 (IMX_PTA_VBASE + GPIO_ICONFA1_OFFSET) -#define IMX_GPIOA_ICONFA2 (IMX_PTA_VBASE + GPIO_ICONFA2_OFFSET) -#define IMX_GPIOA_ICONFB1 (IMX_PTA_VBASE + GPIO_ICONFB1_OFFSET) -#define IMX_GPIOA_ICONFB2 (IMX_PTA_VBASE + GPIO_ICONFB2_OFFSET) -#define IMX_GPIOA_DR (IMX_PTA_VBASE + GPIO_DR_OFFSET) -#define IMX_GPIOA_GIUS (IMX_PTA_VBASE + GPIO_GIUS_OFFSET) -#define IMX_GPIOA_SSR (IMX_PTA_VBASE + GPIO_SSR_OFFSET) -#define IMX_GPIOA_ICR1 (IMX_PTA_VBASE + GPIO_ICR1_OFFSET) -#define IMX_GPIOA_ICR2 (IMX_PTA_VBASE + GPIO_ICR2_OFFSET) -#define IMX_GPIOA_IMR (IMX_PTA_VBASE + GPIO_IMR_OFFSET) -#define IMX_GPIOA_ISR (IMX_PTA_VBASE + GPIO_ISR_OFFSET) -#define IMX_GPIOA_GPR (IMX_PTA_VBASE + GPIO_GPR_OFFSET) -#define IMX_GPIOA_SWR (IMX_PTA_VBASE + GPIO_SWR_OFFSET) -#define IMX_GPIOA_PUEN (IMX_PTA_VBASE + GPIO_PUEN_OFFSET) - -#define IMX_GPIOB_DDIR (IMX_PTB_VBASE + GPIO_DDIR_OFFSET) -#define IMX_GPIOB_OCR1 (IMX_PTB_VBASE + GPIO_OCR1_OFFSET) -#define IMX_GPIOB_OCR2 (IMX_PTB_VBASE + GPIO_OCR2_OFFSET) -#define IMX_GPIOB_ICONFA1 (IMX_PTB_VBASE + GPIO_ICONFA1_OFFSET) -#define IMX_GPIOB_ICONFA2 (IMX_PTB_VBASE + GPIO_ICONFA2_OFFSET) -#define IMX_GPIOB_ICONFB1 (IMX_PTB_VBASE + GPIO_ICONFB1_OFFSET) -#define IMX_GPIOB_ICONFB2 (IMX_PTB_VBASE + GPIO_ICONFB2_OFFSET) -#define IMX_GPIOB_DR (IMX_PTB_VBASE + GPIO_DR_OFFSET) -#define IMX_GPIOB_GIUS (IMX_PTB_VBASE + GPIO_GIUS_OFFSET) -#define IMX_GPIOB_SSR (IMX_PTB_VBASE + GPIO_SSR_OFFSET) -#define IMX_GPIOB_ICR1 (IMX_PTB_VBASE + GPIO_ICR1_OFFSET) -#define IMX_GPIOB_ICR2 (IMX_PTB_VBASE + GPIO_ICR2_OFFSET) -#define IMX_GPIOB_IMR (IMX_PTB_VBASE + GPIO_IMR_OFFSET) -#define IMX_GPIOB_ISR (IMX_PTB_VBASE + GPIO_ISR_OFFSET) -#define IMX_GPIOB_GPR (IMX_PTB_VBASE + GPIO_GPR_OFFSET) -#define IMX_GPIOB_SWR (IMX_PTB_VBASE + GPIO_SWR_OFFSET) -#define IMX_GPIOB_PUEN (IMX_PTB_VBASE + GPIO_PUEN_OFFSET) - -#define IMX_GPIOC_DDIR (IMX_PTC_VBASE + GPIO_DDIR_OFFSET) -#define IMX_GPIOC_OCR1 (IMX_PTC_VBASE + GPIO_OCR1_OFFSET) -#define IMX_GPIOC_OCR2 (IMX_PTC_VBASE + GPIO_OCR2_OFFSET) -#define IMX_GPIOC_ICONFA1 (IMX_PTC_VBASE + GPIO_ICONFA1_OFFSET) -#define IMX_GPIOC_ICONFA2 (IMX_PTC_VBASE + GPIO_ICONFA2_OFFSET) -#define IMX_GPIOC_ICONFB1 (IMX_PTC_VBASE + GPIO_ICONFB1_OFFSET) -#define IMX_GPIOC_ICONFB2 (IMX_PTC_VBASE + GPIO_ICONFB2_OFFSET) -#define IMX_GPIOC_DR (IMX_PTC_VBASE + GPIO_DR_OFFSET) -#define IMX_GPIOC_GIUS (IMX_PTC_VBASE + GPIO_GIUS_OFFSET) -#define IMX_GPIOC_SSR (IMX_PTC_VBASE + GPIO_SSR_OFFSET) -#define IMX_GPIOC_ICR1 (IMX_PTC_VBASE + GPIO_ICR1_OFFSET) -#define IMX_GPIOC_ICR2 (IMX_PTC_VBASE + GPIO_ICR2_OFFSET) -#define IMX_GPIOC_IMR (IMX_PTC_VBASE + GPIO_IMR_OFFSET) -#define IMX_GPIOC_ISR (IMX_PTC_VBASE + GPIO_ISR_OFFSET) -#define IMX_GPIOC_GPR (IMX_PTC_VBASE + GPIO_GPR_OFFSET) -#define IMX_GPIOC_SWR (IMX_PTC_VBASE + GPIO_SWR_OFFSET) -#define IMX_GPIOC_PUEN (IMX_PTC_VBASE + GPIO_PUEN_OFFSET) - -#define IMX_GPIOD_DDIR (IMX_PTD_VBASE + GPIO_DDIR_OFFSET) -#define IMX_GPIOD_OCR1 (IMX_PTD_VBASE + GPIO_OCR1_OFFSET) -#define IMX_GPIOD_OCR2 (IMX_PTD_VBASE + GPIO_OCR2_OFFSET) -#define IMX_GPIOD_ICONFA1 (IMX_PTD_VBASE + GPIO_ICONFA1_OFFSET) -#define IMX_GPIOD_ICONFA2 (IMX_PTD_VBASE + GPIO_ICONFA2_OFFSET) -#define IMX_GPIOD_ICONFB1 (IMX_PTD_VBASE + GPIO_ICONFB1_OFFSET) -#define IMX_GPIOD_ICONFB2 (IMX_PTD_VBASE + GPIO_ICONFB2_OFFSET) -#define IMX_GPIOD_DR (IMX_PTD_VBASE + GPIO_DR_OFFSET) -#define IMX_GPIOD_GIUS (IMX_PTD_VBASE + GPIO_GIUS_OFFSET) -#define IMX_GPIOD_SSR (IMX_PTD_VBASE + GPIO_SSR_OFFSET) -#define IMX_GPIOD_ICR1 (IMX_PTD_VBASE + GPIO_ICR1_OFFSET) -#define IMX_GPIOD_ICR2 (IMX_PTD_VBASE + GPIO_ICR2_OFFSET) -#define IMX_GPIOD_IMR (IMX_PTD_VBASE + GPIO_IMR_OFFSET) -#define IMX_GPIOD_ISR (IMX_PTD_VBASE + GPIO_ISR_OFFSET) -#define IMX_GPIOD_GPR (IMX_PTD_VBASE + GPIO_GPR_OFFSET) -#define IMX_GPIOD_SWR (IMX_PTD_VBASE + GPIO_SWR_OFFSET) -#define IMX_GPIOD_PUEN (IMX_PTD_VBASE + GPIO_PUEN_OFFSET) - -#define IMX_GPIO_DDIR(n) (IMX_PT_VBASE(n) + GPIO_DDIR_OFFSET) -#define IMX_GPIO_OCR1(n) (IMX_PT_VBASE(n) + GPIO_OCR1_OFFSET) -#define IMX_GPIO_OCR2(n) (IMX_PT_VBASE(n) + GPIO_OCR2_OFFSET) -#define IMX_GPIO_ICONFA1(n) (IMX_PT_VBASE(n) + GPIO_ICONFA1_OFFSET) -#define IMX_GPIO_ICONFA2(n) (IMX_PT_VBASE(n) + GPIO_ICONFA2_OFFSET) -#define IMX_GPIO_ICONFB1(n) (IMX_PT_VBASE(n) + GPIO_ICONFB1_OFFSET) -#define IMX_GPIO_ICONFB2(n) (IMX_PT_VBASE(n) + GPIO_ICONFB2_OFFSET) -#define IMX_GPIO_DR(n) (IMX_PT_VBASE(n) + GPIO_DR_OFFSET) -#define IMX_GPIO_GIUS(n) (IMX_PT_VBASE(n) + GPIO_GIUS_OFFSET) -#define IMX_GPIO_SSR(n) (IMX_PT_VBASE(n) + GPIO_SSR_OFFSET) -#define IMX_GPIO_ICR1(n) (IMX_PT_VBASE(n) + GPIO_ICR1_OFFSET) -#define IMX_GPIO_ICR2(n) (IMX_PT_VBASE(n) + GPIO_ICR2_OFFSET) -#define IMX_GPIO_IMR(n) (IMX_PT_VBASE(n) + GPIO_IMR_OFFSET) -#define IMX_GPIO_ISR(n) (IMX_PT_VBASE(n) + GPIO_ISR_OFFSET) -#define IMX_GPIO_GPR(n) (IMX_PT_VBASE(n) + GPIO_GPR_OFFSET) -#define IMX_GPIO_SWR(n) (IMX_PT_VBASE(n) + GPIO_SWR_OFFSET) -#define IMX_GPIO_PUEN(n) (IMX_PT_VBASE(n) + GPIO_PUEN_OFFSET) - -/* GPIO Register Bit Definitions ****************************************************/ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_IMX_GPIO_H */ - -#ifndef __ASSEMBLY__ - -/* Handler circular include... This file includes up_arch.h, but this file is - * included by up_arch.h (via chip.h) BEFORE getreg32 is defined. - */ - -#if !defined(__ARCH_ARM_IMX_GPIOHELPERS_H) && defined(getreg32) -#define __ARCH_ARM_IMX_GPIOHELPERS_H - -/* Select whether the pin is an input or output */ - -static inline void imxgpio_dirout(int port, int bit) -{ - uint32_t regval = getreg32(IMX_GPIO_DDIR(port)); - regval |= (1 << bit); - putreg32(regval, IMX_GPIO_DDIR(port)); -} - -static inline void imxgpio_dirin(int port, int bit) -{ - uint32_t regval = getreg32(IMX_GPIO_DDIR(port)); - regval &= ~(1 << bit); - putreg32(regval, IMX_GPIO_DDIR(port)); -} - -/* Select input configuration */ - -static inline void imxgpio_ocrain(int port, int bit) -{ - uint32_t regval; - uint32_t regaddr; - int shift; - - if (bit < 16) - { - regaddr = IMX_GPIO_OCR1(port); - shift = (bit << 1); - } - else - { - regaddr = IMX_GPIO_OCR2(port); - shift = ((bit - 16) << 1); - } - - regval = getreg32(regaddr); - regval &= ~(3 << shift); - putreg32(regval, regaddr); -} - -static inline void imxgpio_ocrbin(int port, int bit) -{ - uint32_t regval; - uint32_t regaddr; - int shift; - - if (bit < 16) - { - regaddr = IMX_GPIO_OCR1(port); - shift = (bit << 1); - } - else - { - regaddr = IMX_GPIO_OCR2(port); - shift = ((bit - 16) << 1); - } - - regval = getreg32(regaddr); - regval &= ~(3 << shift); - regval |= (1 << shift); - putreg32(regval, regaddr); -} - -static inline void imxgpio_ocrcin(int port, int bit) -{ - uint32_t regval; - uint32_t regaddr; - int shift; - - if (bit < 16) - { - regaddr = IMX_GPIO_OCR1(port); - shift = (bit << 1); - } - else - { - regaddr = IMX_GPIO_OCR2(port); - shift = ((bit - 16) << 1); - } - - regval = getreg32(regaddr); - regval &= ~(3 << shift); - regval |= (2 << shift); - putreg32(regval, regaddr); -} - -static inline void imxgpio_ocrodrin(int port, int bit) -{ - uint32_t regval; - uint32_t regaddr; - int shift; - - if (bit < 16) - { - regaddr = IMX_GPIO_OCR1(port); - shift = (bit << 1); - } - else - { - regaddr = IMX_GPIO_OCR2(port); - shift = ((bit - 16) << 1); - } - - regval = getreg32(regaddr); - regval |= (3 << shift); - putreg32(regval, regaddr); -} - -/* Input configuration */ - -static inline void imxgpio_aoutgpio(int port, int bit) -{ - uint32_t regval; - uint32_t regaddr; - int shift; - - if (bit < 16) - { - regaddr = IMX_GPIO_ICONFA1(port); - shift = (bit << 1); - } - else - { - regaddr = IMX_GPIO_ICONFA2(port); - shift = ((bit - 16) << 1); - } - - regval = getreg32(regaddr); - regval &= ~(3 << shift); - putreg32(regval, regaddr); -} - -static inline void imxgpio_aoutisr(int port, int bit) -{ - uint32_t regval; - uint32_t regaddr; - int shift; - - if (bit < 16) - { - regaddr = IMX_GPIO_ICONFA1(port); - shift = (bit << 1); - } - else - { - regaddr = IMX_GPIO_ICONFA2(port); - shift = ((bit - 16) << 1); - } - - regval = getreg32(regaddr); - regval &= ~(3 << shift); - regval |= (1 << shift); - putreg32(regval, regaddr); -} - -static inline void imxgpio_aout0(int port, int bit) -{ - uint32_t regval; - uint32_t regaddr; - int shift; - - if (bit < 16) - { - regaddr = IMX_GPIO_ICONFA1(port); - shift = (bit << 1); - } - else - { - regaddr = IMX_GPIO_ICONFA2(port); - shift = ((bit - 16) << 1); - } - - regval = getreg32(regaddr); - regval &= ~(3 << shift); - regval |= (2 << shift); - putreg32(regval, regaddr); -} - -static inline void imxgpio_aout1(int port, int bit) -{ - uint32_t regval; - uint32_t regaddr; - int shift; - - if (bit < 16) - { - regaddr = IMX_GPIO_ICONFA1(port); - shift = (bit << 1); - } - else - { - regaddr = IMX_GPIO_ICONFA2(port); - shift = ((bit - 16) << 1); - } - - regval = getreg32(regaddr); - regval |= (3 << shift); - putreg32(regval, regaddr); -} - -static inline void imxgpio_boutgpio(int port, int bit) -{ - uint32_t regval; - uint32_t regaddr; - int shift; - - if (bit < 16) - { - regaddr = IMX_GPIO_ICONFB1(port); - shift = (bit << 1); - } - else - { - regaddr = IMX_GPIO_ICONFB2(port); - shift = ((bit - 16) << 1); - } - - regval = getreg32(regaddr); - regval &= ~(3 << shift); - putreg32(regval, regaddr); -} - -static inline void imxgpio_boutisr(int port, int bit) -{ - uint32_t regval; - uint32_t regaddr; - int shift; - - if (bit < 16) - { - regaddr = IMX_GPIO_ICONFB1(port); - shift = (bit << 1); - } - else - { - regaddr = IMX_GPIO_ICONFB2(port); - shift = ((bit - 16) << 1); - } - - regval = getreg32(regaddr); - regval &= ~(3 << shift); - regval |= (1 << shift); - putreg32(regval, regaddr); -} - -static inline void imxgpio_bout0(int port, int bit) -{ - uint32_t regval; - uint32_t regaddr; - int shift; - - if (bit < 16) - { - regaddr = IMX_GPIO_ICONFB1(port); - shift = (bit << 1); - } - else - { - regaddr = IMX_GPIO_ICONFB2(port); - shift = ((bit - 16) << 1); - } - - regval = getreg32(regaddr); - regval &= ~(3 << shift); - regval |= (2 << shift); - putreg32(regval, regaddr); -} - -static inline void imxgpio_bout1(int port, int bit) -{ - uint32_t regval; - uint32_t regaddr; - int shift; - - if (bit < 16) - { - regaddr = IMX_GPIO_ICONFB1(port); - shift = (bit << 1); - } - else - { - regaddr = IMX_GPIO_ICONFB2(port); - shift = ((bit - 16) << 1); - } - - regval = getreg32(regaddr); - regval |= (3 << shift); - putreg32(regval, regaddr); -} - -/* Select whether the pin is used for its GPIO function or for - * its peripheral function. Also select the primary or alternate - * peripheral function. - */ - -static inline void imxgpio_gpiofunc(int port, int bit) -{ - uint32_t regval = getreg32(IMX_GPIO_GIUS(port)); - regval |= (1 << bit); - putreg32(regval, IMX_GPIO_GIUS(port)); -} - -static inline void imxgpio_peripheralfunc(int port, int bit) -{ - uint32_t regval = getreg32(IMX_GPIO_GIUS(port)); - regval &= ~(1 << bit); - putreg32(regval, IMX_GPIO_GIUS(port)); -} - -static inline void imxgpio_altperipheralfunc(int port, int bit) -{ - uint32_t regval = getreg32(IMX_GPIO_GPR(port)); - regval |= (1 << bit); - putreg32(regval, IMX_GPIO_GPR(port)); -} - -static inline void imxgpio_primaryperipheralfunc(int port, int bit) -{ - uint32_t regval = getreg32(IMX_GPIO_GPR(port)); - regval &= ~(1 << bit); - putreg32(regval, IMX_GPIO_GPR(port)); -} - -/* Enable/disable pullups */ - -static inline void imxgpio_pullupenable(int port, int bit) -{ - uint32_t regval = getreg32(IMX_GPIO_PUEN(port)); - regval |= (1 << bit); - putreg32(regval, IMX_GPIO_PUEN(port)); -} - -static inline void imxgpio_pullupdisable(int port, int bit) -{ - uint32_t regval = getreg32(IMX_GPIO_PUEN(port)); - regval &= ~(1 << bit); - putreg32(regval, IMX_GPIO_PUEN(port)); -} - -static inline void imxgpio_setoutput(int port, int bit) -{ - uint32_t regval = getreg32(IMX_GPIO_DR(port)); - regval |= (1 << bit); - putreg32(regval, IMX_GPIO_DR(port)); -} - -static inline void imxgpio_clroutput(int port, int bit) -{ - uint32_t regval = getreg32(IMX_GPIO_DR(port)); - regval &= ~(1 << bit); - putreg32(regval, IMX_GPIO_DR(port)); -} - -/* Useful functions for normal configurations */ - -extern void imxgpio_configoutput(int port, int bit, int value); -extern void imxgpio_configinput(int port, int bit); - -extern void imxgpio_configpfoutput(int port, int bit); -extern void imxgpio_configpfinput(int port, int bit); - -#endif - -#endif /* __ARCH_ARM_IMX_GPIOHELPERS_H */ +/************************************************************************************ + * arch/arm/src/imx/imx_gpio.h + * arch/arm/src/chip/imx_gpio.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_GPIO_H +#define __ARCH_ARM_IMX_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif +#include "up_arch.h" /* getreg32(), putreg32() */ + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* GPIO Register Offsets ************************************************************/ + +#define GPIO_DDIR_OFFSET 0x0000 /* Data Direction Register */ +#define GPIO_OCR1_OFFSET 0x0004 /* Output Configuration Register 1 */ +#define GPIO_OCR2_OFFSET 0x0008 /* Output Configuration Register 2 */ +#define GPIO_ICONFA1_OFFSET 0x000c /* Input Configuration Register A1 */ +#define GPIO_ICONFA2_OFFSET 0x0010 /* Input Configuration Register A2 */ +#define GPIO_ICONFB1_OFFSET 0x0014 /* Input Configuration Register B1 */ +#define GPIO_ICONFB2_OFFSET 0x0018 /* Input Configuration Register B2 */ +#define GPIO_DR_OFFSET 0x001c /* Data Register */ +#define GPIO_GIUS_OFFSET 0x0020 /* GPIO In Use Register */ +#define GPIO_SSR_OFFSET 0x0024 /* Sample Status Register */ +#define GPIO_ICR1_OFFSET 0x0028 /* Interrupt Configuration Register 1 */ +#define GPIO_ICR2_OFFSET 0x002c /* Interrupt Configuration Register 2 */ +#define GPIO_IMR_OFFSET 0x0030 /* Interrupt Mask Register */ +#define GPIO_ISR_OFFSET 0x0034 /* Interrupt Status Register */ +#define GPIO_GPR_OFFSET 0x0038 /* General Purpose Register */ +#define GPIO_SWR_OFFSET 0x003c /* Software Reset Register */ +#define GPIO_PUEN_OFFSET 0x0040 /* Pull_Up Enable Register */ + +#define GPIO_PTA_OFFSET 0x0000 /* Port A offset */ +#define GPIO_PTB_OFFSET 0x0100 /* Port B offset */ +#define GPIO_PTC_OFFSET 0x0200 /* Port C offset */ +#define GPIO_PTD_OFFSET 0x0300 /* Port D offset */ + +#define GPIOA 0 /* Port A index */ +#define GPIOB 1 /* Port B index */ +#define GPIOC 2 /* Port C index */ +#define GPIOD 3 /* Port D index */ +#define GPIO_PT_OFFSET(n) (GPIO_PTA_OFFSET + (n)*0x0100) + +/* GPIO Register Addresses **********************************************************/ + +#define IMX_PTA_VBASE (IMX_GPIO_VBASE + GPIO_PTA_OFFSET) +#define IMX_PTB_VBASE (IMX_GPIO_VBASE + GPIO_PTB_OFFSET) +#define IMX_PTC_VBASE (IMX_GPIO_VBASE + GPIO_PTC_OFFSET) +#define IMX_PTD_VBASE (IMX_GPIO_VBASE + GPIO_PTD_OFFSET) +#define IMX_PT_VBASE(n) (IMX_GPIO_VBASE + GPIO_PT_OFFSET(n)) + +#define IMX_GPIOA_DDIR (IMX_PTA_VBASE + GPIO_DDIR_OFFSET) +#define IMX_GPIOA_OCR1 (IMX_PTA_VBASE + GPIO_OCR1_OFFSET) +#define IMX_GPIOA_OCR2 (IMX_PTA_VBASE + GPIO_OCR2_OFFSET) +#define IMX_GPIOA_ICONFA1 (IMX_PTA_VBASE + GPIO_ICONFA1_OFFSET) +#define IMX_GPIOA_ICONFA2 (IMX_PTA_VBASE + GPIO_ICONFA2_OFFSET) +#define IMX_GPIOA_ICONFB1 (IMX_PTA_VBASE + GPIO_ICONFB1_OFFSET) +#define IMX_GPIOA_ICONFB2 (IMX_PTA_VBASE + GPIO_ICONFB2_OFFSET) +#define IMX_GPIOA_DR (IMX_PTA_VBASE + GPIO_DR_OFFSET) +#define IMX_GPIOA_GIUS (IMX_PTA_VBASE + GPIO_GIUS_OFFSET) +#define IMX_GPIOA_SSR (IMX_PTA_VBASE + GPIO_SSR_OFFSET) +#define IMX_GPIOA_ICR1 (IMX_PTA_VBASE + GPIO_ICR1_OFFSET) +#define IMX_GPIOA_ICR2 (IMX_PTA_VBASE + GPIO_ICR2_OFFSET) +#define IMX_GPIOA_IMR (IMX_PTA_VBASE + GPIO_IMR_OFFSET) +#define IMX_GPIOA_ISR (IMX_PTA_VBASE + GPIO_ISR_OFFSET) +#define IMX_GPIOA_GPR (IMX_PTA_VBASE + GPIO_GPR_OFFSET) +#define IMX_GPIOA_SWR (IMX_PTA_VBASE + GPIO_SWR_OFFSET) +#define IMX_GPIOA_PUEN (IMX_PTA_VBASE + GPIO_PUEN_OFFSET) + +#define IMX_GPIOB_DDIR (IMX_PTB_VBASE + GPIO_DDIR_OFFSET) +#define IMX_GPIOB_OCR1 (IMX_PTB_VBASE + GPIO_OCR1_OFFSET) +#define IMX_GPIOB_OCR2 (IMX_PTB_VBASE + GPIO_OCR2_OFFSET) +#define IMX_GPIOB_ICONFA1 (IMX_PTB_VBASE + GPIO_ICONFA1_OFFSET) +#define IMX_GPIOB_ICONFA2 (IMX_PTB_VBASE + GPIO_ICONFA2_OFFSET) +#define IMX_GPIOB_ICONFB1 (IMX_PTB_VBASE + GPIO_ICONFB1_OFFSET) +#define IMX_GPIOB_ICONFB2 (IMX_PTB_VBASE + GPIO_ICONFB2_OFFSET) +#define IMX_GPIOB_DR (IMX_PTB_VBASE + GPIO_DR_OFFSET) +#define IMX_GPIOB_GIUS (IMX_PTB_VBASE + GPIO_GIUS_OFFSET) +#define IMX_GPIOB_SSR (IMX_PTB_VBASE + GPIO_SSR_OFFSET) +#define IMX_GPIOB_ICR1 (IMX_PTB_VBASE + GPIO_ICR1_OFFSET) +#define IMX_GPIOB_ICR2 (IMX_PTB_VBASE + GPIO_ICR2_OFFSET) +#define IMX_GPIOB_IMR (IMX_PTB_VBASE + GPIO_IMR_OFFSET) +#define IMX_GPIOB_ISR (IMX_PTB_VBASE + GPIO_ISR_OFFSET) +#define IMX_GPIOB_GPR (IMX_PTB_VBASE + GPIO_GPR_OFFSET) +#define IMX_GPIOB_SWR (IMX_PTB_VBASE + GPIO_SWR_OFFSET) +#define IMX_GPIOB_PUEN (IMX_PTB_VBASE + GPIO_PUEN_OFFSET) + +#define IMX_GPIOC_DDIR (IMX_PTC_VBASE + GPIO_DDIR_OFFSET) +#define IMX_GPIOC_OCR1 (IMX_PTC_VBASE + GPIO_OCR1_OFFSET) +#define IMX_GPIOC_OCR2 (IMX_PTC_VBASE + GPIO_OCR2_OFFSET) +#define IMX_GPIOC_ICONFA1 (IMX_PTC_VBASE + GPIO_ICONFA1_OFFSET) +#define IMX_GPIOC_ICONFA2 (IMX_PTC_VBASE + GPIO_ICONFA2_OFFSET) +#define IMX_GPIOC_ICONFB1 (IMX_PTC_VBASE + GPIO_ICONFB1_OFFSET) +#define IMX_GPIOC_ICONFB2 (IMX_PTC_VBASE + GPIO_ICONFB2_OFFSET) +#define IMX_GPIOC_DR (IMX_PTC_VBASE + GPIO_DR_OFFSET) +#define IMX_GPIOC_GIUS (IMX_PTC_VBASE + GPIO_GIUS_OFFSET) +#define IMX_GPIOC_SSR (IMX_PTC_VBASE + GPIO_SSR_OFFSET) +#define IMX_GPIOC_ICR1 (IMX_PTC_VBASE + GPIO_ICR1_OFFSET) +#define IMX_GPIOC_ICR2 (IMX_PTC_VBASE + GPIO_ICR2_OFFSET) +#define IMX_GPIOC_IMR (IMX_PTC_VBASE + GPIO_IMR_OFFSET) +#define IMX_GPIOC_ISR (IMX_PTC_VBASE + GPIO_ISR_OFFSET) +#define IMX_GPIOC_GPR (IMX_PTC_VBASE + GPIO_GPR_OFFSET) +#define IMX_GPIOC_SWR (IMX_PTC_VBASE + GPIO_SWR_OFFSET) +#define IMX_GPIOC_PUEN (IMX_PTC_VBASE + GPIO_PUEN_OFFSET) + +#define IMX_GPIOD_DDIR (IMX_PTD_VBASE + GPIO_DDIR_OFFSET) +#define IMX_GPIOD_OCR1 (IMX_PTD_VBASE + GPIO_OCR1_OFFSET) +#define IMX_GPIOD_OCR2 (IMX_PTD_VBASE + GPIO_OCR2_OFFSET) +#define IMX_GPIOD_ICONFA1 (IMX_PTD_VBASE + GPIO_ICONFA1_OFFSET) +#define IMX_GPIOD_ICONFA2 (IMX_PTD_VBASE + GPIO_ICONFA2_OFFSET) +#define IMX_GPIOD_ICONFB1 (IMX_PTD_VBASE + GPIO_ICONFB1_OFFSET) +#define IMX_GPIOD_ICONFB2 (IMX_PTD_VBASE + GPIO_ICONFB2_OFFSET) +#define IMX_GPIOD_DR (IMX_PTD_VBASE + GPIO_DR_OFFSET) +#define IMX_GPIOD_GIUS (IMX_PTD_VBASE + GPIO_GIUS_OFFSET) +#define IMX_GPIOD_SSR (IMX_PTD_VBASE + GPIO_SSR_OFFSET) +#define IMX_GPIOD_ICR1 (IMX_PTD_VBASE + GPIO_ICR1_OFFSET) +#define IMX_GPIOD_ICR2 (IMX_PTD_VBASE + GPIO_ICR2_OFFSET) +#define IMX_GPIOD_IMR (IMX_PTD_VBASE + GPIO_IMR_OFFSET) +#define IMX_GPIOD_ISR (IMX_PTD_VBASE + GPIO_ISR_OFFSET) +#define IMX_GPIOD_GPR (IMX_PTD_VBASE + GPIO_GPR_OFFSET) +#define IMX_GPIOD_SWR (IMX_PTD_VBASE + GPIO_SWR_OFFSET) +#define IMX_GPIOD_PUEN (IMX_PTD_VBASE + GPIO_PUEN_OFFSET) + +#define IMX_GPIO_DDIR(n) (IMX_PT_VBASE(n) + GPIO_DDIR_OFFSET) +#define IMX_GPIO_OCR1(n) (IMX_PT_VBASE(n) + GPIO_OCR1_OFFSET) +#define IMX_GPIO_OCR2(n) (IMX_PT_VBASE(n) + GPIO_OCR2_OFFSET) +#define IMX_GPIO_ICONFA1(n) (IMX_PT_VBASE(n) + GPIO_ICONFA1_OFFSET) +#define IMX_GPIO_ICONFA2(n) (IMX_PT_VBASE(n) + GPIO_ICONFA2_OFFSET) +#define IMX_GPIO_ICONFB1(n) (IMX_PT_VBASE(n) + GPIO_ICONFB1_OFFSET) +#define IMX_GPIO_ICONFB2(n) (IMX_PT_VBASE(n) + GPIO_ICONFB2_OFFSET) +#define IMX_GPIO_DR(n) (IMX_PT_VBASE(n) + GPIO_DR_OFFSET) +#define IMX_GPIO_GIUS(n) (IMX_PT_VBASE(n) + GPIO_GIUS_OFFSET) +#define IMX_GPIO_SSR(n) (IMX_PT_VBASE(n) + GPIO_SSR_OFFSET) +#define IMX_GPIO_ICR1(n) (IMX_PT_VBASE(n) + GPIO_ICR1_OFFSET) +#define IMX_GPIO_ICR2(n) (IMX_PT_VBASE(n) + GPIO_ICR2_OFFSET) +#define IMX_GPIO_IMR(n) (IMX_PT_VBASE(n) + GPIO_IMR_OFFSET) +#define IMX_GPIO_ISR(n) (IMX_PT_VBASE(n) + GPIO_ISR_OFFSET) +#define IMX_GPIO_GPR(n) (IMX_PT_VBASE(n) + GPIO_GPR_OFFSET) +#define IMX_GPIO_SWR(n) (IMX_PT_VBASE(n) + GPIO_SWR_OFFSET) +#define IMX_GPIO_PUEN(n) (IMX_PT_VBASE(n) + GPIO_PUEN_OFFSET) + +/* GPIO Register Bit Definitions ****************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_GPIO_H */ + +#ifndef __ASSEMBLY__ + +/* Handler circular include... This file includes up_arch.h, but this file is + * included by up_arch.h (via chip.h) BEFORE getreg32 is defined. + */ + +#if !defined(__ARCH_ARM_IMX_GPIOHELPERS_H) && defined(getreg32) +#define __ARCH_ARM_IMX_GPIOHELPERS_H + +/* Select whether the pin is an input or output */ + +static inline void imxgpio_dirout(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_DDIR(port)); + regval |= (1 << bit); + putreg32(regval, IMX_GPIO_DDIR(port)); +} + +static inline void imxgpio_dirin(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_DDIR(port)); + regval &= ~(1 << bit); + putreg32(regval, IMX_GPIO_DDIR(port)); +} + +/* Select input configuration */ + +static inline void imxgpio_ocrain(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_OCR1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_OCR2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_ocrbin(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_OCR1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_OCR2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + regval |= (1 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_ocrcin(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_OCR1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_OCR2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + regval |= (2 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_ocrodrin(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_OCR1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_OCR2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval |= (3 << shift); + putreg32(regval, regaddr); +} + +/* Input configuration */ + +static inline void imxgpio_aoutgpio(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_ICONFA1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_ICONFA2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_aoutisr(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_ICONFA1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_ICONFA2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + regval |= (1 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_aout0(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_ICONFA1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_ICONFA2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + regval |= (2 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_aout1(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_ICONFA1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_ICONFA2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval |= (3 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_boutgpio(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_ICONFB1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_ICONFB2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_boutisr(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_ICONFB1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_ICONFB2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + regval |= (1 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_bout0(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_ICONFB1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_ICONFB2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval &= ~(3 << shift); + regval |= (2 << shift); + putreg32(regval, regaddr); +} + +static inline void imxgpio_bout1(int port, int bit) +{ + uint32_t regval; + uint32_t regaddr; + int shift; + + if (bit < 16) + { + regaddr = IMX_GPIO_ICONFB1(port); + shift = (bit << 1); + } + else + { + regaddr = IMX_GPIO_ICONFB2(port); + shift = ((bit - 16) << 1); + } + + regval = getreg32(regaddr); + regval |= (3 << shift); + putreg32(regval, regaddr); +} + +/* Select whether the pin is used for its GPIO function or for + * its peripheral function. Also select the primary or alternate + * peripheral function. + */ + +static inline void imxgpio_gpiofunc(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_GIUS(port)); + regval |= (1 << bit); + putreg32(regval, IMX_GPIO_GIUS(port)); +} + +static inline void imxgpio_peripheralfunc(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_GIUS(port)); + regval &= ~(1 << bit); + putreg32(regval, IMX_GPIO_GIUS(port)); +} + +static inline void imxgpio_altperipheralfunc(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_GPR(port)); + regval |= (1 << bit); + putreg32(regval, IMX_GPIO_GPR(port)); +} + +static inline void imxgpio_primaryperipheralfunc(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_GPR(port)); + regval &= ~(1 << bit); + putreg32(regval, IMX_GPIO_GPR(port)); +} + +/* Enable/disable pullups */ + +static inline void imxgpio_pullupenable(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_PUEN(port)); + regval |= (1 << bit); + putreg32(regval, IMX_GPIO_PUEN(port)); +} + +static inline void imxgpio_pullupdisable(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_PUEN(port)); + regval &= ~(1 << bit); + putreg32(regval, IMX_GPIO_PUEN(port)); +} + +static inline void imxgpio_setoutput(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_DR(port)); + regval |= (1 << bit); + putreg32(regval, IMX_GPIO_DR(port)); +} + +static inline void imxgpio_clroutput(int port, int bit) +{ + uint32_t regval = getreg32(IMX_GPIO_DR(port)); + regval &= ~(1 << bit); + putreg32(regval, IMX_GPIO_DR(port)); +} + +/* Useful functions for normal configurations */ + +extern void imxgpio_configoutput(int port, int bit, int value); +extern void imxgpio_configinput(int port, int bit); + +extern void imxgpio_configpfoutput(int port, int bit); +extern void imxgpio_configpfinput(int port, int bit); + +#endif + +#endif /* __ARCH_ARM_IMX_GPIOHELPERS_H */ diff --git a/arch/arm/src/imx/imx_i2c.h b/arch/arm/src/imx/imx_i2c.h index b2896b7eead7fac2f3df4314dbe2649814758aab..8b1c065e22dbc43ce0e9cbe63df63e895e6cc8cc 100755 --- a/arch/arm/src/imx/imx_i2c.h +++ b/arch/arm/src/imx/imx_i2c.h @@ -1,69 +1,69 @@ -/************************************************************************************ - * arch/arm/src/imx/imx_i2c.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_IMX_I2C_H -#define __ARCH_ARM_IMX_I2C_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* I2C Register Offsets *************************************************************/ - -#define I2C_IADR_OFFSET 0x0000 -#define I2C_IFDR_OFFSET 0x0004 -#define I2C_I2CR_OFFSET 0x0008 -#define I2C_I2SR_OFFSET 0x000c -#define I2C_I2DR_OFFSET 0x0010 - -/* I2C Register Addresses ***********************************************************/ - -#define IMX_I2C_IADR (IMX_I2C_VBASE + I2C_IADR_OFFSET) -#define IMX_I2C_IFDR (IMX_I2C_VBASE + I2C_IFDR_OFFSET) -#define IMX_I2C_I2CR (IMX_I2C_VBASE + I2C_I2CR_OFFSET) -#define IMX_I2C_I2SR (IMX_I2C_VBASE + I2C_I2SR_OFFSET) -#define IMX_I2C_I2DR (IMX_I2C_VBASE + I2C_I2DR_OFFSET) - -/* I2C Register Bit Definitions *****************************************************/ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_IMX_I2C_H */ +/************************************************************************************ + * arch/arm/src/imx/imx_i2c.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_I2C_H +#define __ARCH_ARM_IMX_I2C_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* I2C Register Offsets *************************************************************/ + +#define I2C_IADR_OFFSET 0x0000 +#define I2C_IFDR_OFFSET 0x0004 +#define I2C_I2CR_OFFSET 0x0008 +#define I2C_I2SR_OFFSET 0x000c +#define I2C_I2DR_OFFSET 0x0010 + +/* I2C Register Addresses ***********************************************************/ + +#define IMX_I2C_IADR (IMX_I2C_VBASE + I2C_IADR_OFFSET) +#define IMX_I2C_IFDR (IMX_I2C_VBASE + I2C_IFDR_OFFSET) +#define IMX_I2C_I2CR (IMX_I2C_VBASE + I2C_I2CR_OFFSET) +#define IMX_I2C_I2SR (IMX_I2C_VBASE + I2C_I2SR_OFFSET) +#define IMX_I2C_I2DR (IMX_I2C_VBASE + I2C_I2DR_OFFSET) + +/* I2C Register Bit Definitions *****************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_I2C_H */ diff --git a/arch/arm/src/imx/imx_irq.c b/arch/arm/src/imx/imx_irq.c index 934a60f0b58ba8b9a450080d9d7952a7a1af63f2..6715a4ad7016a38523c587b7d408859b27e21bda 100644 --- a/arch/arm/src/imx/imx_irq.c +++ b/arch/arm/src/imx/imx_irq.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/imx_irq.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/imx/imx_lowputc.S b/arch/arm/src/imx/imx_lowputc.S index c00955622088b7133d20b90b3786339102fc7571..b0c8163a3e239c689c95c0b67f77ad291d62eca0 100644 --- a/arch/arm/src/imx/imx_lowputc.S +++ b/arch/arm/src/imx/imx_lowputc.S @@ -3,7 +3,7 @@ * arch/arm/src/chip/imx_lowputc.S * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/imx/imx_memorymap.h b/arch/arm/src/imx/imx_memorymap.h index 7eafc908a56cdc9e1112a457d32ccd14501d6173..fd23aafc33d3193772c13d205400afcea0f5fa01 100644 --- a/arch/arm/src/imx/imx_memorymap.h +++ b/arch/arm/src/imx/imx_memorymap.h @@ -2,7 +2,7 @@ * arch/arm/src/imx/imx_memorymap.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/imx/imx_rtc.h b/arch/arm/src/imx/imx_rtc.h index 68f684fec52c20f100166c9402629e24fc5fa22d..249e7a40d224636837ef990c9502777add9b94d8 100755 --- a/arch/arm/src/imx/imx_rtc.h +++ b/arch/arm/src/imx/imx_rtc.h @@ -1,85 +1,85 @@ -/************************************************************************************ - * arch/arm/src/imx/imx_rtc.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_IMX_RTC_H -#define __ARCH_ARM_IMX_RTC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* RTC Register Offsets *************************************************************/ - -#define RTC_HOURMIN_OFFSET 0x0000 -#define RTC_SECOND_OFFSET 0x0004 -#define RTC_ALRM_HM_OFFSET 0x0008 -#define RTC_ALRM_SEC_OFFSET 0x000c -#define RTC_RTCCTL_OFFSET 0x0010 -#define RTC_RTCISR_OFFSET 0x0014 -#define RTC_RTCIENR_OFFSET 0x0018 -#define RTC_STPWCH_OFFSET 0x001c -#define RTC_DAYR_OFFSET 0x0020 -#define RTC_DAYALARM_OFFSET 0x0024 -#define RTC_TEST1_OFFSET 0x0028 -#define RTC_TEST2_OFFSET 0x002c -#define RTC_TEST3_OFFSET 0x0030 - -/* RTC Register Addresses ***********************************************************/ - -#define IMX_RTC_HOURMIN (IMX_RTC_VBASE + RTC_HOURMIN_OFFSET) -#define IMX_RTC_SECOND (IMX_RTC_VBASE + RTC_SECOND_OFFSET) -#define IMX_RTC_ALRM_HM (IMX_RTC_VBASE + RTC_ALRM_HM_OFFSET) -#define IMX_RTC_ALRM_SEC (IMX_RTC_VBASE + RTC_ALRM_SEC_OFFSET) -#define IMX_RTC_RTCCTL (IMX_RTC_VBASE + RTC_RTCCTL_OFFSET) -#define IMX_RTC_RTCISR (IMX_RTC_VBASE + RTC_RTCISR_OFFSET) -#define IMX_RTC_RTCIENR (IMX_RTC_VBASE + RTC_RTCIENR_OFFSET) -#define IMX_RTC_STPWCH (IMX_RTC_VBASE + RTC_STPWCH_OFFSET) -#define IMX_RTC_DAYR (IMX_RTC_VBASE + RTC_DAYR_OFFSET) -#define IMX_RTC_DAYALARM (IMX_RTC_VBASE + RTC_DAYALARM_OFFSET) -#define IMX_RTC_TEST1 (IMX_RTC_VBASE + RTC_TEST1_OFFSET) -#define IMX_RTC_TEST2 (IMX_RTC_VBASE + RTC_TEST2_OFFSET) -#define IMX_RTC_TEST3 (IMX_RTC_VBASE + RTC_TEST3_OFFSET) - -/* RTC Register Bit Definitions *****************************************************/ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_IMX_RTC_H */ +/************************************************************************************ + * arch/arm/src/imx/imx_rtc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_RTC_H +#define __ARCH_ARM_IMX_RTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* RTC Register Offsets *************************************************************/ + +#define RTC_HOURMIN_OFFSET 0x0000 +#define RTC_SECOND_OFFSET 0x0004 +#define RTC_ALRM_HM_OFFSET 0x0008 +#define RTC_ALRM_SEC_OFFSET 0x000c +#define RTC_RTCCTL_OFFSET 0x0010 +#define RTC_RTCISR_OFFSET 0x0014 +#define RTC_RTCIENR_OFFSET 0x0018 +#define RTC_STPWCH_OFFSET 0x001c +#define RTC_DAYR_OFFSET 0x0020 +#define RTC_DAYALARM_OFFSET 0x0024 +#define RTC_TEST1_OFFSET 0x0028 +#define RTC_TEST2_OFFSET 0x002c +#define RTC_TEST3_OFFSET 0x0030 + +/* RTC Register Addresses ***********************************************************/ + +#define IMX_RTC_HOURMIN (IMX_RTC_VBASE + RTC_HOURMIN_OFFSET) +#define IMX_RTC_SECOND (IMX_RTC_VBASE + RTC_SECOND_OFFSET) +#define IMX_RTC_ALRM_HM (IMX_RTC_VBASE + RTC_ALRM_HM_OFFSET) +#define IMX_RTC_ALRM_SEC (IMX_RTC_VBASE + RTC_ALRM_SEC_OFFSET) +#define IMX_RTC_RTCCTL (IMX_RTC_VBASE + RTC_RTCCTL_OFFSET) +#define IMX_RTC_RTCISR (IMX_RTC_VBASE + RTC_RTCISR_OFFSET) +#define IMX_RTC_RTCIENR (IMX_RTC_VBASE + RTC_RTCIENR_OFFSET) +#define IMX_RTC_STPWCH (IMX_RTC_VBASE + RTC_STPWCH_OFFSET) +#define IMX_RTC_DAYR (IMX_RTC_VBASE + RTC_DAYR_OFFSET) +#define IMX_RTC_DAYALARM (IMX_RTC_VBASE + RTC_DAYALARM_OFFSET) +#define IMX_RTC_TEST1 (IMX_RTC_VBASE + RTC_TEST1_OFFSET) +#define IMX_RTC_TEST2 (IMX_RTC_VBASE + RTC_TEST2_OFFSET) +#define IMX_RTC_TEST3 (IMX_RTC_VBASE + RTC_TEST3_OFFSET) + +/* RTC Register Bit Definitions *****************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_RTC_H */ diff --git a/arch/arm/src/imx/imx_spi.c b/arch/arm/src/imx/imx_spi.c index e07cd5d32e005887721ac92a8b01d4b7713714cb..5ee601263d172da7e6ef0cf63bd55bb5bdf7516a 100755 --- a/arch/arm/src/imx/imx_spi.c +++ b/arch/arm/src/imx/imx_spi.c @@ -2,7 +2,7 @@ * arch/arm/src/imx/imx_spi.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/imx/imx_system.h b/arch/arm/src/imx/imx_system.h index a3a4b4c54993c1252f3f3c3359ba3301351e492c..ad363f14a21f9153a21bd5debc43caad4cfa53c8 100755 --- a/arch/arm/src/imx/imx_system.h +++ b/arch/arm/src/imx/imx_system.h @@ -1,187 +1,187 @@ -/************************************************************************************ - * arch/arm/src/imx/imx_system.h - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_IMX_SYSTEM_H -#define __ARCH_ARM_IMX_SYSTEM_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* AIPI Register Offsets ************************************************************/ - -#define AIPI_PSR0_OFFSET 0x0000 /* Peripheral Size Register 0 */ -#define AIPI_PSR1_OFFSET 0x0004 /* Peripheral Size Register 1 */ -#define AIPI_PAR_OFFSET 0x0008 /* Peripheral Access Register */ - -/* AIPI Register Addresses **********************************************************/ - -#define IMX_AIPI1_PSR0 (IMX_AIPI1_VBASE + AIPI_PSR0_OFFSET) -#define IMX_AIPI1_PSR1 (IMX_AIPI1_VBASE + AIPI_PSR1_OFFSET) -#define IMX_AIPI1_PAR (IMX_AIPI1_VBASE + AIPI_PAR_OFFSET) - -#define IMX_AIPI2_PSR0 (IMX_AIP2_VBASE + AIPI_PSR0_OFFSET) -#define IMX_AIPI2_PSR1 (IMX_AIP2_VBASE + AIPI_PSR1_OFFSET) -#define IMX_AIPI2_PAR (IMX_AIP2_VBASE + 0xAIPI_PAR_OFFSET) - -/* AIPI Register Bit Definitions ****************************************************/ - -/* PLL Register Offsets *************************************************************/ - -#define PLL_CSCR_OFFSET 0x0000 /* Clock Source Control Register */ -#define PLL_MPCTL0_OFFSET 0x0004 /* MCU PLL Control Register 0 */ -#define PLL_MPCTL1_OFFSET 0x0008 /* MCU PLL & System Clock Control Register 1 */ -#define PLL_SPCTL0_OFFSET 0x000c /* System PLL Control Register 0 */ -#define PLL_SPCTL1_OFFSET 0x0010 /* System PLL Control Register 1 */ -#define PLL_PCDR_OFFSET 0x0020 /* Peripherial Clock Divider Register */ - -/* PLL Register Addresses ***********************************************************/ - -#define IMX_PLL_CSCR (IMX_PLL_VBASE + PLL_CSCR_OFFSET) -#define IMX_PLL_MPCTL0 (IMX_PLL_VBASE + PLL_MPCTL0_OFFSET) -#define IMX_PLL_MPCTL1 (IMX_PLL_VBASE + PLL_MPCTL1_OFFSET) -#define IMX_PLL_SPCTL0 (IMX_PLL_VBASE + PLL_SPCTL0_OFFSET) -#define IMX_PLL_SPCTL1 (IMX_PLL_VBASE + PLL_SPCTL1_OFFSET) -#define IMX_PLL_PCDR (IMX_PLL_VBASE + PLL_PCDR_OFFSET) - -/* PLL Register Bit Definitions *****************************************************/ - -#define PLL_CSCR_MPEN (1 << 0) /* Bit 0: 1 = MCU PLL enabled */ -#define PLL_CSCR_SPEN (1 << 1) /* Bit 1: System PLL Enable */ -#define PLL_CSCR_BCLKDIV_SHIFT 10 /* Bits 13–10: BClock Divider */ -#define PLL_CSCR_BCLKDIV_MASK (15 << PLL_CSCR_BCLK_DIV_SHIFT) -#define PLL_CSCR_PRESC (1 << 15) /* Bit 15: MPU PLL clock prescaler */ -#define PLL_CSCR_SYSTEM_SEL (1 << 16) /* Bit 16: System clock source select */ -#define PLL_CSCR_OSCEN (1 << 17) /* Bit 17: Ext. 16MHz oscillator enable */ -#define PLL_CSCR_CLK16_SEL (1 << 18) /* Bit 18: Select BT ref RFBTCLK16 */ -#define PLL_CSCR_MPLLRESTART (1 << 21) /* Bit 21: MPLL Restart */ -#define PLL_CSCR_SPLLRESTART (1 << 22) /* Bit 22: SPLL Restart */ -#define PLL_CSCR_SDCNT_SHIFT 24 /* Bits 25–24: Shut-Down Control */ -#define PLL_CSCR_SDCNT_MASK (3 << PLL_CSCR_SDCNT_SHIFT) -#define CSCR_SDCNT_2ndEDGE (1 << PLL_CSCR_SDCNT_SHIFT) -#define CSCR_SDCNT_3rdEDGE (2 << PLL_CSCR_SDCNT_SHIFT) -#define CSCR_SDCNT_4thEDGE (3 << PLL_CSCR_SDCNT_SHIFT) -#define PLL_CSCR_USBDIV_SHIFT 28 /* Bits 28–26: USB Divider */ -#define PLL_CSCR_USBDIV_MASK (7 << PLL_CSCR_USB_DIV_SHIFT) -#define PLL_CSCR_CLKOSEL_SHIFT 29 /* Bits 31–29: CLKO Select */ -#define PLL_CSCR_CLKOSEL_MASK (7 << PLL_CSCR_CLKOSEL_SHIFT) -#define CSCR_CLKOSEL_PERCLK1 (0 << PLL_CSCR_CLKOSEL_SHIFT) -#define CSCR_CLKOSEL_HCLK (1 << PLL_CSCR_CLKOSEL_SHIFT) -#define CSCR_CLKOSEL_CLK48M (2 << PLL_CSCR_CLKOSEL_SHIFT) -#define CSCR_CLKOSEL_CLK16M (3 << PLL_CSCR_CLKOSEL_SHIFT) -#define CSCR_CLKOSEL_PREMCLK (4 << PLL_CSCR_CLKOSEL_SHIFT) -#define CSCR_CLKOSEL_FCLK (5 << PLL_CSCR_CLKOSEL_SHIFT) - -#define PLL_MPCTL0_MFN_SHIFT 0 /* Bits 9–0: Multiplication Factor (Numerator) */ -#define PLL_MPCTL0_MFN_MASK (0x03ff << PLL_MPCTL0_MFN_SHIFT) -#define PLL_MPCTL0_MFI_SHIFT 10 /* Bits 13–10: Multiplication Factor (Integer) */ -#define PLL_MPCTL0_MFI_MASK (0x0f << PLL_MPCTL0_MFI_SHIFT) -#define PLL_MPCTL0_MFD_SHIFT 16 /* Bits 25–16: Multiplication Factor (Denominator) */ -#define PLL_MPCTL0_MFD_MASK (0x03ff << PLL_MPCTL0_MFD_SHIFT) -#define PLL_MPCTL0_PD_SHIFT 26 /* Bits 29–26: Predivider Factor */ -#define PLL_MPCTL0_PD_MASK (0x0f << PLL_MPCTL0_PD_SHIFT - -#define PLL_MPCTL1_BRMO (1 << 6) /* Bit 6: Controls the BRM order */ - -#define PLL_SPCTL0_MFN_SHIFT 0 /* Bits 9–0: Multiplication Factor (Numerator) */ -#define PLL_SPCTL0_MFN_MASK (0x03ff << PLL_SPCTL0_MFN_SHIFT) -#define PLL_SPCTL0_MFI_SHIFT 10 /* Bits 13–10: Multiplication Factor (Integer) */ -#define PLL_SPCTL0_MFI_MASK (0x0f << PLL_SPCTL0_MFI_SHIFT) -#define PLL_SPCTL0_MFD_SHIFT 16 /* Bits 25–16: Multiplication Factor (Denominator) */ -#define PLL_SPCTL0_MFD_MASK (0x03ff << PLL_SPCTL0_MFD_SHIFT) -#define PLL_SPCTL0_PD_SHIFT 26 /* Bits 29–26: Predivider Factor */ -#define PLL_SPCTL0_PD_MASK (0x0f << PLL_SPCTL0_PD_SHIFT) - -#define PLL_SPCTL1_BRMO (1 << 6) /* Bit 6: Controls the BRM order */ -#define PLL_SPCTL1_LF (1 << 15) /* Bit 15: Indicates if System PLL is locked */ - -#define PLL_PCDR_PCLKDIV1_SHIFT 0 /* Bits 3–0: Peripheral Clock Divider 1 */ -#define PLL_PCDR_PCLKDIV1_MASK (0x0f << PLL_PCDR_PCLKDIV1_SHIFT) -#define PLL_PCDR_PCLKDIV2_SHIFT 4 /* Bits 7–4: Peripheral Clock Divider 2 */ -#define PLL_PCDR_PCLKDIV2_MASK (0x0f << PLL_PCDR_PCLKDIV2_SHIFT) -#define PLL_PCDR_PCLKDIV3_SHIFT 16 /* Bits 22–16: Peripheral Clock Divider 3 */ -#define PLL_PCDR_PCLKDIV3_MASK (0x7f << PLL_PCDR_PCLKDIV3_SHIFT) - -/* PLL Helper Macros ****************************************************************/ - -/* SC Register Offsets **************************************************************/ - -#define SC_RSR_OFFSET 0x0000 /* Reset Source Register */ -#define SC_SIDR_OFFSET 0x0004 /* Silicon ID Register */ -#define SC_FMCR_OFFSET 0x0008 /* Function Muxing Control Register */ -#define SC_GPCR_OFFSET 0x000c /* Global Peripheral Control Regiser */ - -/* SC Register Addresses ************************************************************/ - -#define IMX_SC_RSR (IMX_SC_VBASE + SC_RSR_OFFSET) -#define IMX_SC_SIDR (IMX_SC_VBASE + SC_SIDR_OFFSET) -#define IMX_SC_FMCR (IMX_SC_VBASE + SC_FMCR_OFFSET) -#define IMX_SC_GPCR (IMX_SC_VBASE + SC_GPCR_OFFSET) - -/* SC Register Bit Definitions ******************************************************/ - - -#define FMCR_SDCS_SEL (1 << 0) /* Bit 0: 1:CSD0 selected */ -#define FMCR_SDCS1_SEL (1 << 1) /* Bit 1: 1:CSD1 selected */ -#define FMCR_EXT_BREN (1 << 2) /* Bit 2: 1:External bus request enabled */ -#define FMCR_SSI_TXCLKSEL (1 << 3) /* Bit 3: 1:Input from Port B[19] SIM_CLK pin */ -#define FMCR_SSI_TXFSSEL (1 << 4) /* Bit 4: 1:Input from Port B[18] SIM_RST pin */ -#define FMCR_SSI_RXDATSEL (1 << 5) /* Bit 5: 1:Input from Port B[16] SIM_TX pin */ -#define FMCR_SSI_RXCLKSEL (1 << 6) /* Bit 6: 1:Input from Port B[15] SIM_PD pin */ -#define FMCR_SSI_RXFSSEL (1 << 7) /* Bit 7: 1:Input from Port B[14] SIM_SVEN pin */ -#define FMCR_SPI2_RXDSEL (1 << 8) /* Bit 8: 1:Input from SPI2_RXD_1 pin - * (AOUT of Port D[9]) */ - -/* SDRAMC Register Offsets **********************************************************/ - -#define SDRAMC_SDCTL0_OFFSET 0x0000 -#define SDRAMC_SDCTL1_OFFSET 0x0004 - -/* SDRAMC Register Addresses ********************************************************/ - -#define IMX_SDRAMC_SDCTL0 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL0_OFFSET) -#define IMX_SDRAMC_SDCTL1 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL1_OFFSET)) - -/* SDRAMC Register Bit Definitions **************************************************/ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_IMX_SYSTEM_H */ +/************************************************************************************ + * arch/arm/src/imx/imx_system.h + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_SYSTEM_H +#define __ARCH_ARM_IMX_SYSTEM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* AIPI Register Offsets ************************************************************/ + +#define AIPI_PSR0_OFFSET 0x0000 /* Peripheral Size Register 0 */ +#define AIPI_PSR1_OFFSET 0x0004 /* Peripheral Size Register 1 */ +#define AIPI_PAR_OFFSET 0x0008 /* Peripheral Access Register */ + +/* AIPI Register Addresses **********************************************************/ + +#define IMX_AIPI1_PSR0 (IMX_AIPI1_VBASE + AIPI_PSR0_OFFSET) +#define IMX_AIPI1_PSR1 (IMX_AIPI1_VBASE + AIPI_PSR1_OFFSET) +#define IMX_AIPI1_PAR (IMX_AIPI1_VBASE + AIPI_PAR_OFFSET) + +#define IMX_AIPI2_PSR0 (IMX_AIP2_VBASE + AIPI_PSR0_OFFSET) +#define IMX_AIPI2_PSR1 (IMX_AIP2_VBASE + AIPI_PSR1_OFFSET) +#define IMX_AIPI2_PAR (IMX_AIP2_VBASE + 0xAIPI_PAR_OFFSET) + +/* AIPI Register Bit Definitions ****************************************************/ + +/* PLL Register Offsets *************************************************************/ + +#define PLL_CSCR_OFFSET 0x0000 /* Clock Source Control Register */ +#define PLL_MPCTL0_OFFSET 0x0004 /* MCU PLL Control Register 0 */ +#define PLL_MPCTL1_OFFSET 0x0008 /* MCU PLL & System Clock Control Register 1 */ +#define PLL_SPCTL0_OFFSET 0x000c /* System PLL Control Register 0 */ +#define PLL_SPCTL1_OFFSET 0x0010 /* System PLL Control Register 1 */ +#define PLL_PCDR_OFFSET 0x0020 /* Peripherial Clock Divider Register */ + +/* PLL Register Addresses ***********************************************************/ + +#define IMX_PLL_CSCR (IMX_PLL_VBASE + PLL_CSCR_OFFSET) +#define IMX_PLL_MPCTL0 (IMX_PLL_VBASE + PLL_MPCTL0_OFFSET) +#define IMX_PLL_MPCTL1 (IMX_PLL_VBASE + PLL_MPCTL1_OFFSET) +#define IMX_PLL_SPCTL0 (IMX_PLL_VBASE + PLL_SPCTL0_OFFSET) +#define IMX_PLL_SPCTL1 (IMX_PLL_VBASE + PLL_SPCTL1_OFFSET) +#define IMX_PLL_PCDR (IMX_PLL_VBASE + PLL_PCDR_OFFSET) + +/* PLL Register Bit Definitions *****************************************************/ + +#define PLL_CSCR_MPEN (1 << 0) /* Bit 0: 1 = MCU PLL enabled */ +#define PLL_CSCR_SPEN (1 << 1) /* Bit 1: System PLL Enable */ +#define PLL_CSCR_BCLKDIV_SHIFT 10 /* Bits 13–10: BClock Divider */ +#define PLL_CSCR_BCLKDIV_MASK (15 << PLL_CSCR_BCLK_DIV_SHIFT) +#define PLL_CSCR_PRESC (1 << 15) /* Bit 15: MPU PLL clock prescaler */ +#define PLL_CSCR_SYSTEM_SEL (1 << 16) /* Bit 16: System clock source select */ +#define PLL_CSCR_OSCEN (1 << 17) /* Bit 17: Ext. 16MHz oscillator enable */ +#define PLL_CSCR_CLK16_SEL (1 << 18) /* Bit 18: Select BT ref RFBTCLK16 */ +#define PLL_CSCR_MPLLRESTART (1 << 21) /* Bit 21: MPLL Restart */ +#define PLL_CSCR_SPLLRESTART (1 << 22) /* Bit 22: SPLL Restart */ +#define PLL_CSCR_SDCNT_SHIFT 24 /* Bits 25–24: Shut-Down Control */ +#define PLL_CSCR_SDCNT_MASK (3 << PLL_CSCR_SDCNT_SHIFT) +#define CSCR_SDCNT_2ndEDGE (1 << PLL_CSCR_SDCNT_SHIFT) +#define CSCR_SDCNT_3rdEDGE (2 << PLL_CSCR_SDCNT_SHIFT) +#define CSCR_SDCNT_4thEDGE (3 << PLL_CSCR_SDCNT_SHIFT) +#define PLL_CSCR_USBDIV_SHIFT 28 /* Bits 28–26: USB Divider */ +#define PLL_CSCR_USBDIV_MASK (7 << PLL_CSCR_USB_DIV_SHIFT) +#define PLL_CSCR_CLKOSEL_SHIFT 29 /* Bits 31–29: CLKO Select */ +#define PLL_CSCR_CLKOSEL_MASK (7 << PLL_CSCR_CLKOSEL_SHIFT) +#define CSCR_CLKOSEL_PERCLK1 (0 << PLL_CSCR_CLKOSEL_SHIFT) +#define CSCR_CLKOSEL_HCLK (1 << PLL_CSCR_CLKOSEL_SHIFT) +#define CSCR_CLKOSEL_CLK48M (2 << PLL_CSCR_CLKOSEL_SHIFT) +#define CSCR_CLKOSEL_CLK16M (3 << PLL_CSCR_CLKOSEL_SHIFT) +#define CSCR_CLKOSEL_PREMCLK (4 << PLL_CSCR_CLKOSEL_SHIFT) +#define CSCR_CLKOSEL_FCLK (5 << PLL_CSCR_CLKOSEL_SHIFT) + +#define PLL_MPCTL0_MFN_SHIFT 0 /* Bits 9–0: Multiplication Factor (Numerator) */ +#define PLL_MPCTL0_MFN_MASK (0x03ff << PLL_MPCTL0_MFN_SHIFT) +#define PLL_MPCTL0_MFI_SHIFT 10 /* Bits 13–10: Multiplication Factor (Integer) */ +#define PLL_MPCTL0_MFI_MASK (0x0f << PLL_MPCTL0_MFI_SHIFT) +#define PLL_MPCTL0_MFD_SHIFT 16 /* Bits 25–16: Multiplication Factor (Denominator) */ +#define PLL_MPCTL0_MFD_MASK (0x03ff << PLL_MPCTL0_MFD_SHIFT) +#define PLL_MPCTL0_PD_SHIFT 26 /* Bits 29–26: Predivider Factor */ +#define PLL_MPCTL0_PD_MASK (0x0f << PLL_MPCTL0_PD_SHIFT + +#define PLL_MPCTL1_BRMO (1 << 6) /* Bit 6: Controls the BRM order */ + +#define PLL_SPCTL0_MFN_SHIFT 0 /* Bits 9–0: Multiplication Factor (Numerator) */ +#define PLL_SPCTL0_MFN_MASK (0x03ff << PLL_SPCTL0_MFN_SHIFT) +#define PLL_SPCTL0_MFI_SHIFT 10 /* Bits 13–10: Multiplication Factor (Integer) */ +#define PLL_SPCTL0_MFI_MASK (0x0f << PLL_SPCTL0_MFI_SHIFT) +#define PLL_SPCTL0_MFD_SHIFT 16 /* Bits 25–16: Multiplication Factor (Denominator) */ +#define PLL_SPCTL0_MFD_MASK (0x03ff << PLL_SPCTL0_MFD_SHIFT) +#define PLL_SPCTL0_PD_SHIFT 26 /* Bits 29–26: Predivider Factor */ +#define PLL_SPCTL0_PD_MASK (0x0f << PLL_SPCTL0_PD_SHIFT) + +#define PLL_SPCTL1_BRMO (1 << 6) /* Bit 6: Controls the BRM order */ +#define PLL_SPCTL1_LF (1 << 15) /* Bit 15: Indicates if System PLL is locked */ + +#define PLL_PCDR_PCLKDIV1_SHIFT 0 /* Bits 3–0: Peripheral Clock Divider 1 */ +#define PLL_PCDR_PCLKDIV1_MASK (0x0f << PLL_PCDR_PCLKDIV1_SHIFT) +#define PLL_PCDR_PCLKDIV2_SHIFT 4 /* Bits 7–4: Peripheral Clock Divider 2 */ +#define PLL_PCDR_PCLKDIV2_MASK (0x0f << PLL_PCDR_PCLKDIV2_SHIFT) +#define PLL_PCDR_PCLKDIV3_SHIFT 16 /* Bits 22–16: Peripheral Clock Divider 3 */ +#define PLL_PCDR_PCLKDIV3_MASK (0x7f << PLL_PCDR_PCLKDIV3_SHIFT) + +/* PLL Helper Macros ****************************************************************/ + +/* SC Register Offsets **************************************************************/ + +#define SC_RSR_OFFSET 0x0000 /* Reset Source Register */ +#define SC_SIDR_OFFSET 0x0004 /* Silicon ID Register */ +#define SC_FMCR_OFFSET 0x0008 /* Function Muxing Control Register */ +#define SC_GPCR_OFFSET 0x000c /* Global Peripheral Control Regiser */ + +/* SC Register Addresses ************************************************************/ + +#define IMX_SC_RSR (IMX_SC_VBASE + SC_RSR_OFFSET) +#define IMX_SC_SIDR (IMX_SC_VBASE + SC_SIDR_OFFSET) +#define IMX_SC_FMCR (IMX_SC_VBASE + SC_FMCR_OFFSET) +#define IMX_SC_GPCR (IMX_SC_VBASE + SC_GPCR_OFFSET) + +/* SC Register Bit Definitions ******************************************************/ + + +#define FMCR_SDCS_SEL (1 << 0) /* Bit 0: 1:CSD0 selected */ +#define FMCR_SDCS1_SEL (1 << 1) /* Bit 1: 1:CSD1 selected */ +#define FMCR_EXT_BREN (1 << 2) /* Bit 2: 1:External bus request enabled */ +#define FMCR_SSI_TXCLKSEL (1 << 3) /* Bit 3: 1:Input from Port B[19] SIM_CLK pin */ +#define FMCR_SSI_TXFSSEL (1 << 4) /* Bit 4: 1:Input from Port B[18] SIM_RST pin */ +#define FMCR_SSI_RXDATSEL (1 << 5) /* Bit 5: 1:Input from Port B[16] SIM_TX pin */ +#define FMCR_SSI_RXCLKSEL (1 << 6) /* Bit 6: 1:Input from Port B[15] SIM_PD pin */ +#define FMCR_SSI_RXFSSEL (1 << 7) /* Bit 7: 1:Input from Port B[14] SIM_SVEN pin */ +#define FMCR_SPI2_RXDSEL (1 << 8) /* Bit 8: 1:Input from SPI2_RXD_1 pin + * (AOUT of Port D[9]) */ + +/* SDRAMC Register Offsets **********************************************************/ + +#define SDRAMC_SDCTL0_OFFSET 0x0000 +#define SDRAMC_SDCTL1_OFFSET 0x0004 + +/* SDRAMC Register Addresses ********************************************************/ + +#define IMX_SDRAMC_SDCTL0 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL0_OFFSET) +#define IMX_SDRAMC_SDCTL1 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL1_OFFSET)) + +/* SDRAMC Register Bit Definitions **************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_SYSTEM_H */ diff --git a/arch/arm/src/imx/imx_timer.h b/arch/arm/src/imx/imx_timer.h index d923a686d3fa7a52dca40b1905f9024e5eefe83b..9d91d3c0d2e0476e03d18da813e04859bb815227 100644 --- a/arch/arm/src/imx/imx_timer.h +++ b/arch/arm/src/imx/imx_timer.h @@ -2,7 +2,7 @@ * arch/arm/src/imx/imx_timer.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/imx/imx_timerisr.c b/arch/arm/src/imx/imx_timerisr.c index 30367e97c00d1fca3249c69d85a4df74ed4400ca..896dc86e52a9931155ad06d24c9bc40c34622de1 100644 --- a/arch/arm/src/imx/imx_timerisr.c +++ b/arch/arm/src/imx/imx_timerisr.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/imx_timerisr.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/imx/imx_uart.h b/arch/arm/src/imx/imx_uart.h index 89d40f543b2e8fac32188e5f3dd387600aff7aff..5646e83f7ef67a1c3f5acbe7aec6fe087b31d9b3 100644 --- a/arch/arm/src/imx/imx_uart.h +++ b/arch/arm/src/imx/imx_uart.h @@ -2,7 +2,7 @@ * arch/arm/src/imx/imx_uart.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/imx/imx_usbd.h b/arch/arm/src/imx/imx_usbd.h index be53f23584e5d70d5a22fa4590bf2505f2ab84df..8c810cacfb273c2768d37da945880c9d42e98206 100755 --- a/arch/arm/src/imx/imx_usbd.h +++ b/arch/arm/src/imx/imx_usbd.h @@ -1,320 +1,320 @@ -/************************************************************************************ - * arch/arm/src/imx/imx_usbd.h - * - * Copyright (c) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_IMX_USBD_H -#define __ARCH_ARM_IMX_USBD_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* USBD Register Offsets ************************************************************/ - -#define USBD_FRAME_OFFSET 0x0000 -#define USBD_SPEC_OFFSET 0x0004 -#define USBD_STAT_OFFSET 0x0008 -#define USBD_CTRL_OFFSET 0x000c -#define USBD_DADR_OFFSET 0x0010 -#define USBD_DDAT_OFFSET 0x0014 -#define USBD_INTR_OFFSET 0x0018 -#define USBD_MASK_OFFSET 0x001c -#define USBD_ENAB_OFFSET 0x0024 - -#define USBD_EP0_OFFSET 0x0030 -#define USBD_EP1_OFFSET 0x0060 -#define USBD_EP2_OFFSET 0x0090 -#define USBD_EP3_OFFSET 0x00c0 -#define USBD_EP4_OFFSET 0x00f0 -#define USBD_EP5_OFFSET 0x0120 -#define USBD_EP_OFFSET(n) (USBD_EP0_OFFSET + (n)*0x0030) - -#define USBD_EP_STAT_OFFSET 0x0000 -#define USBD_EP_INTR_OFFSET 0x0004 -#define USBD_EP_MASK_OFFSET 0x0008 -#define USBD_EP_FDAT_OFFSET 0x000c -#define USBD_EP_FSTAT_OFFSET 0x0010 -#define USBD_EP_FCTRL_OFFSET 0x0014 -#define USBD_EP_LRFP_OFFSET 0x0018 -#define USBD_EP_LRWP_OFFSET 0x001c -#define USBD_EP_FALRM_OFFSET 0x0020 -#define USBD_EP_FRDP_OFFSET 0x0024 -#define USBD_EP_FRWP_OFFSET 0x0028 - -/* USBD Register Addresses **********************************************************/ - -#define IMX_USBD_FRAME (IMX_USBD_VBASE + USBD_FRAME_OFFSET) -#define IMX_USBD_SPEC (IMX_USBD_VBASE + USBD_SPEC_OFFSET) -#define IMX_USBD_STAT (IMX_USBD_VBASE + USBD_STAT_OFFSET) -#define IMX_USBD_CTRL (IMX_USBD_VBASE + USBD_CTRL_OFFSET) -#define IMX_USBD_DADR (IMX_USBD_VBASE + USBD_DADR_OFFSET) -#define IMX_USBD_DDAT (IMX_USBD_VBASE + USBD_DDAT_OFFSET) -#define IMX_USBD_INTR (IMX_USBD_VBASE + USBD_INTR_OFFSET) -#define IMX_USBD_MASK (IMX_USBD_VBASE + USBD_MASK_OFFSET) -#define IMX_USBD_ENAB (IMX_USBD_VBASE + USBD_ENAB_OFFSET) - -#define IMX_USBD_EP0_BASE (IMX_USBD_VBASE + USBD_EP0_OFFSET) -#define IMX_USBD_EP1_BASE (IMX_USBD_VBASE + USBD_EP1_OFFSET) -#define IMX_USBD_EP2_BASE (IMX_USBD_VBASE + USBD_EP2_OFFSET) -#define IMX_USBD_EP3_BASE (IMX_USBD_VBASE + USBD_EP3_OFFSET) -#define IMX_USBD_EP4_BASE (IMX_USBD_VBASE + USBD_EP4_OFFSET) -#define IMX_USBD_EP5_BASE (IMX_USBD_VBASE + USBD_EP5_OFFSET) -#define IMX_USBD_EP_BASE(n) (IMX_USBD_VBASE + USBD_EP_OFFSET(n)) - -#define IMX_USBD_EP0_STAT (IMX_USBD_EP0_BASE + USBD_EP_STAT_OFFSET) -#define IMX_USBD_EP0_INTR (IMX_USBD_EP0_BASE + USBD_EP_INTR_OFFSET) -#define IMX_USBD_EP0_MASK (IMX_USBD_EP0_BASE + USBD_EP_MASK_OFFSET) -#define IMX_USBD_EP0_FDAT (IMX_USBD_EP0_BASE + USBD_EP_FDAT_OFFSET) -#define IMX_USBD_EP0_FSTAT (IMX_USBD_EP0_BASE + USBD_EP_FSTAT_OFFSET) -#define IMX_USBD_EP0_FCTRL (IMX_USBD_EP0_BASE + USBD_EP_FCTRL_OFFSET) -#define IMX_USBD_EP0_LRFP (IMX_USBD_EP0_BASE + USBD_EP_LRFP_OFFSET) -#define IMX_USBD_EP0_LRWP (IMX_USBD_EP0_BASE + USBD_EP_LRWP_OFFSET) -#define IMX_USBD_EP0_FALRM (IMX_USBD_EP0_BASE + USBD_EP_FALRM_OFFSET) -#define IMX_USBD_EP0_FRDP (IMX_USBD_EP0_BASE + USBD_EP_FRDP_OFFSET) -#define IMX_USBD_EP0_FRWP (IMX_USBD_EP0_BASE + USBD_EP_FRWP_OFFSET) - -#define IMX_USBD_EP1_STAT (IMX_USBD_EP1_BASE + USBD_EP_STAT_OFFSET) -#define IMX_USBD_EP1_INTR (IMX_USBD_EP1_BASE + USBD_EP_INTR_OFFSET) -#define IMX_USBD_EP1_MASK (IMX_USBD_EP1_BASE + USBD_EP_MASK_OFFSET) -#define IMX_USBD_EP1_FDAT (IMX_USBD_EP1_BASE + USBD_EP_FDAT_OFFSET) -#define IMX_USBD_EP1_FSTAT (IMX_USBD_EP1_BASE + USBD_EP_FSTAT_OFFSET) -#define IMX_USBD_EP1_FCTRL (IMX_USBD_EP1_BASE + USBD_EP_FCTRL_OFFSET) -#define IMX_USBD_EP1_LRFP (IMX_USBD_EP1_BASE + USBD_EP_LRFP_OFFSET) -#define IMX_USBD_EP1_LRWP (IMX_USBD_EP1_BASE + USBD_EP_LRWP_OFFSET) -#define IMX_USBD_EP1_FALRM (IMX_USBD_EP1_BASE + USBD_EP_FALRM_OFFSET) -#define IMX_USBD_EP1_FRDP (IMX_USBD_EP1_BASE + USBD_EP_FRDP_OFFSET) -#define IMX_USBD_EP1_FRWP (IMX_USBD_EP1_BASE + USBD_EP_FRWP_OFFSET) - -#define IMX_USBD_EP2_STAT (IMX_USBD_EP2_BASE + USBD_EP_STAT_OFFSET) -#define IMX_USBD_EP2_INTR (IMX_USBD_EP2_BASE + USBD_EP_INTR_OFFSET) -#define IMX_USBD_EP2_MASK (IMX_USBD_EP2_BASE + USBD_EP_MASK_OFFSET) -#define IMX_USBD_EP2_FDAT (IMX_USBD_EP2_BASE + USBD_EP_FDAT_OFFSET) -#define IMX_USBD_EP2_FSTAT (IMX_USBD_EP2_BASE + USBD_EP_FSTAT_OFFSET) -#define IMX_USBD_EP2_FCTRL (IMX_USBD_EP2_BASE + USBD_EP_FCTRL_OFFSET) -#define IMX_USBD_EP2_LRFP (IMX_USBD_EP2_BASE + USBD_EP_LRFP_OFFSET) -#define IMX_USBD_EP2_LRWP (IMX_USBD_EP2_BASE + USBD_EP_LRWP_OFFSET) -#define IMX_USBD_EP2_FALRM (IMX_USBD_EP2_BASE + USBD_EP_FALRM_OFFSET) -#define IMX_USBD_EP2_FRDP (IMX_USBD_EP2_BASE + USBD_EP_FRDP_OFFSET) -#define IMX_USBD_EP2_FRWP (IMX_USBD_EP2_BASE + USBD_EP_FRWP_OFFSET) - -#define IMX_USBD_EP3_STAT (IMX_USBD_EP3_BASE + USBD_EP_STAT_OFFSET) -#define IMX_USBD_EP3_INTR (IMX_USBD_EP3_BASE + USBD_EP_INTR_OFFSET) -#define IMX_USBD_EP3_MASK (IMX_USBD_EP3_BASE + USBD_EP_MASK_OFFSET) -#define IMX_USBD_EP3_FDAT (IMX_USBD_EP3_BASE + USBD_EP_FDAT_OFFSET) -#define IMX_USBD_EP3_FSTAT (IMX_USBD_EP3_BASE + USBD_EP_FSTAT_OFFSET) -#define IMX_USBD_EP3_FCTRL (IMX_USBD_EP3_BASE + USBD_EP_FCTRL_OFFSET) -#define IMX_USBD_EP3_LRFP (IMX_USBD_EP3_BASE + USBD_EP_LRFP_OFFSET) -#define IMX_USBD_EP3_LRWP (IMX_USBD_EP3_BASE + USBD_EP_LRWP_OFFSET) -#define IMX_USBD_EP3_FALRM (IMX_USBD_EP3_BASE + USBD_EP_FALRM_OFFSET) -#define IMX_USBD_EP3_FRDP (IMX_USBD_EP3_BASE + USBD_EP_FRDP_OFFSET) -#define IMX_USBD_EP3_FRWP (IMX_USBD_EP3_BASE + USBD_EP_FRWP_OFFSET) - -#define IMX_USBD_EP4_STAT (IMX_USBD_EP4_BASE + USBD_EP_STAT_OFFSET) -#define IMX_USBD_EP4_INTR (IMX_USBD_EP4_BASE + USBD_EP_INTR_OFFSET) -#define IMX_USBD_EP4_MASK (IMX_USBD_EP4_BASE + USBD_EP_MASK_OFFSET) -#define IMX_USBD_EP4_FDAT (IMX_USBD_EP4_BASE + USBD_EP_FDAT_OFFSET) -#define IMX_USBD_EP4_FSTAT (IMX_USBD_EP4_BASE + USBD_EP_FSTAT_OFFSET) -#define IMX_USBD_EP4_FCTRL (IMX_USBD_EP4_BASE + USBD_EP_FCTRL_OFFSET) -#define IMX_USBD_EP4_LRFP (IMX_USBD_EP4_BASE + USBD_EP_LRFP_OFFSET) -#define IMX_USBD_EP4_LRWP (IMX_USBD_EP4_BASE + USBD_EP_LRWP_OFFSET) -#define IMX_USBD_EP4_FALRM (IMX_USBD_EP4_BASE + USBD_EP_FALRM_OFFSET) -#define IMX_USBD_EP4_FRDP (IMX_USBD_EP4_BASE + USBD_EP_FRDP_OFFSET) -#define IMX_USBD_EP4_FRWP (IMX_USBD_EP4_BASE + USBD_EP_FRWP_OFFSET) - -#define IMX_USBD_EP5_STAT (IMX_USBD_EP5_BASE + USBD_EP_STAT_OFFSET) -#define IMX_USBD_EP5_INTR (IMX_USBD_EP5_BASE + USBD_EP_INTR_OFFSET) -#define IMX_USBD_EP5_MASK (IMX_USBD_EP5_BASE + USBD_EP_MASK_OFFSET) -#define IMX_USBD_EP5_FDAT (IMX_USBD_EP5_BASE + USBD_EP_FDAT_OFFSET) -#define IMX_USBD_EP5_FSTAT (IMX_USBD_EP5_BASE + USBD_EP_FSTAT_OFFSET) -#define IMX_USBD_EP5_FCTRL (IMX_USBD_EP5_BASE + USBD_EP_FCTRL_OFFSET) -#define IMX_USBD_EP5_LRFP (IMX_USBD_EP5_BASE + USBD_EP_LRFP_OFFSET) -#define IMX_USBD_EP5_LRWP (IMX_USBD_EP5_BASE + USBD_EP_LRWP_OFFSET) -#define IMX_USBD_EP5_FALRM (IMX_USBD_EP5_BASE + USBD_EP_FALRM_OFFSET) -#define IMX_USBD_EP5_FRDP (IMX_USBD_EP5_BASE + USBD_EP_FRDP_OFFSET) -#define IMX_USBD_EP5_FRWP (IMX_USBD_EP5_BASE + USBD_EP_FRWP_OFFSET) - -#define IMX_USBD_EP_STAT(n) (IMX_USBD_EP_BASE(n) + USBD_EP_STAT_OFFSET) -#define IMX_USBD_EP_INTR(n) (IMX_USBD_EP_BASE(n) + USBD_EP_INTR_OFFSET) -#define IMX_USBD_EP_MASK(n) (IMX_USBD_EP_BASE(n) + USBD_EP_MASK_OFFSET) -#define IMX_USBD_EP_FDAT(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FDAT_OFFSET) -#define IMX_USBD_EP_FSTAT(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FSTAT_OFFSET) -#define IMX_USBD_EP_FCTRL(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FCTRL_OFFSET) -#define IMX_USBD_EP_LRFP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_LRFP_OFFSET) -#define IMX_USBD_EP_LRWP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_LRWP_OFFSET) -#define IMX_USBD_EP_FALRM(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FALRM_OFFSET) -#define IMX_USBD_EP_FRDP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FRDP_OFFSET) -#define IMX_USBD_EP_FRWP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FRWP_OFFSET) - -/* USBD Register Bit Definitions ****************************************************/ - -/* USBD FRAME Register */ - -#define USBD_FRAME_FRAME_SHIFT 0 /* Bit 0-10: Frame Field */ -#define USBD_FRAME_FRAME_MASK (0x07ff << USBD_FRAME_FRAME_SHIFT) -#define USBD_FRAME_MATCH_SHIFT 16 /* Bit 16-26: Match Field */ -#define USBD_FRAME_MATCH_MASK (0x07ff << USBD_FRAME_MATCH_SHIFT) - -/* USBD STAT Register */ - -#define USBD_STAT_ALTSET_SHIFT 0 /* Bit 0-2: Alternate Setting */ -#define USBD_STAT_ALTSET_MASK (0x07 << USBD_FRAME_MATCH_SHIFT) -#define USBD_STAT_INTF_SHIFT 3 /* Bit 3-4: Interface */ -#define USBD_STAT_INTF_MASK (0x03 << USBD_FRAME_MATCH_SHIFT) -#define USBD_STAT_CFG_SHIFT 5 /* Bit 5-6: Configuration */ -#define USBD_STAT_CFG_MASK (0x03 << USBD_FRAME_MATCH_SHIFT) -#define USBD_STAT_SUSP (1 << 7) /* Bit 7: Suspend */ -#define USBD_STAT_RST (1 << 8) /* Bit 8: Reset Signaling */ - -/* USBD CTRL Register */ - -#define USBD_CTRL_RESUME (1 << 0) /* Bit 0: Resume */ -#define USBD_CTRL_AFEENA (1 << 1) /* Bit 1: Analog Front-End Enable */ -#define USBD_CTRL_UDCRST (1 << 2) /* Bit 2: UDC Reset */ -#define USBD_CTRL_USBENA (1 << 3) /* Bit 3: USB Enable */ -#define USBD_CTRL_USBSPD (1 << 4) /* Bit 4: USB Speed */ -#define USBD_CTRL_CMDERROR (1 << 5) /* Bit 5: Command Error */ -#define USBD_CTRL_CMDOVER (1 << 6) /* Bit 6: Command Over */ - -/* USBD DADR Register */ - -#define USBD_DADR_DADR_SHIFT 0 /* Bit 0-8: Desired RAM Address */ -#define USBD_DADR_DADR_MASK (0x1ff << USBD_DADR_DADR_SHIFT) -#define USBD_DADR_BSY (1 << 30) /* Bit 30: Busy */ -#define USBD_DADR_CFG (1 << 31) /* Bit 31: Configuration */ - -/* USBD DDAT Register */ - -#define USBD_DDAT_DDAT_SHIFT 0 /* Bit 0-7: Descriptor Data Buffer */ -#define USBD_DDAT_DDAT_MASK (0xff << USBD_DDAT_DDAT_SHIFT) - -/* USBD INTR Register */ - -#define USBD_INTR_CFGCHG (1 << 0) /* Bit 0: Configuration Change */ -#define USBD_INTR_FRAMEMATCH (1 << 1) /* Bit 1: FRAME_MATCH */ -#define USBD_INTR_SUSP (1 << 2) /* Bit 2: Active to Suspend */ -#define USBD_INTR_RES (1 << 3) /* Bit 3: Suspend to Resume */ -#define USBD_INTR_RESETSTART (1 << 4) /* Bit 4: Restart Signaling Start */ -#define USBD_INTR_RESETSTOP (1 << 5) /* Bit 5: Restart Signaling Stop */ -#define USBD_INTR_SOF (1 << 6) /* Bit 6: Start-of-Frame Interrupt */ -#define USBD_INTR_MSOF (1 << 7) /* Bit 7: Missed Start-of-Frame Interrupt */ -#define USBD_INTR_WAKEUP (1 << 31) /* Bit 31: Wakeup */ - -/* USBD MASK Register */ - -#define USBD_MASK_CFGCHG (1 << 0) /* Bit 0: Configuration Change */ -#define USBD_MASK_FRAMEMATCH (1 << 1) /* Bit 1: FRAME_MATCH */ -#define USBD_MASK_SUSP (1 << 2) /* Bit 2: Active to Suspend */ -#define USBD_MASK_RES (1 << 3) /* Bit 3: Suspend to Resume */ -#define USBD_MASK_RESETSTART (1 << 4) /* Bit 4: Restart Signaling Start */ -#define USBD_MASK_RESETSTOP (1 << 5) /* Bit 5: Restart Signaling Stop */ -#define USBD_MASK_SOF (1 << 6) /* Bit 6: Start-of-Frame Interrupt */ -#define USBD_MASK_MSOF (1 << 7) /* Bit 7: Missed Start-of-Frame Interrupt */ -#define USBD_MASK_WAKEUP (1 << 31) /* Bit 31: Wakeup */ - -/* USBD ENAB Register */ - -#define USBD_ENAB_PWDMD (1 << 0) /* Bit 0: Power Mode */ -#define USBD_ENAB_ENDIANMODE (1 << 28) /* Bit 28: Endian Mode Select */ -#define USBD_ENAB_SUSPEND (1 << 29) /* Bit 29: Suspend */ -#define USBD_ENAB_ENAB (1 << 30) /* Bit 30: Enable */ -#define USBD_ENAB_RST (1 << 31) /* Bit 31: Reset */ - -/* USBD EPSTAT Register */ - -#define USBD_EPSTAT_FORCESTALL (1 << 0) /* Bit 0: Force a Stall Condition */ -#define USBD_EPSTAT_FLUSH (1 << 1) /* Bit 1: Flush */ -#define USBD_EPSTAT_ZLPS (1 << 2) /* Bit 2: Zero Length Packet Send */ -#define USBD_EPSTAT_TYP_SHIFT 3 /* Bit 3-4: Endpoint Type */ -#define USBD_EPSTAT_TYP_MASK (0x03 << USBD_EPSTAT_TYP_SHIFT) -#define USBD_EPSTAT_MAX_SHIFT 5 /* Bit 5-6: Maximum Packet Size */ -#define USBD_EPSTAT_MAX_MASK (0x03 << USBD_EPSTAT_MAX_SHIFT) -#define USBD_EPSTAT_DIR (1 << 7) /* Bit 7: Transfer Direction */ -#define USBD_EPSTAT_SIP (1 << 8) /* Bit 8: Setup Packet in Progress */ -#define USBD_EPSTAT_BYTECOUNT_SHIFT 16 /* Bit 16-22: Byte Count */ -#define USBD_EPSTAT_BYTECOUNT_MASK (0x7f << USBD_EPSTAT_BYTECOUNT_SHIFT) - -/* USBD EPINTR Register */ - -#define USBD_EPINTR_EOF (1 << 0) /* Bit 0: End-of-Frame */ -#define USBD_EPINTR_DEVREQ (1 << 1) /* Bit 1: Device Request */ -#define USBD_EPINTR_EOT (1 << 2) /* Bit 2: End of Transfer */ -#define USBD_EPINTR_MDEVREQ (1 << 3) /* Bit 3: Multiple Device Request */ -#define USBD_EPINTR_FIFOLOW (1 << 4) /* Bit 4: FIFO Low */ -#define USBD_EPINTR_FIFOHIGH (1 << 5) /* Bit 5: FIFO High */ -#define USBD_EPINTR_FIFOERROR (1 << 6) /* Bit 6: FIFO Error */ -#define USBD_EPINTR_FIFOEMPTY (1 << 7) /* Bit 7: FIFO Empty */ -#define USBD_EPINTR_FIFOFULL (1 << 8) /* Bit 8: FIFO Full */ - -/* USBD EPMASK Register */ - -#define USBD_EPMASK_EOF (1 << 0) /* Bit 0: End-of-Frame */ -#define USBD_EPMASK_DEVREQ (1 << 1) /* Bit 1: Device Request */ -#define USBD_EPMASK_EOT (1 << 2) /* Bit 2: End of Transfer */ -#define USBD_EPMASK_MDEVREQ (1 << 3) /* Bit 3: Multiple Device Request */ -#define USBD_EPMASK_FIFOLOW (1 << 4) /* Bit 4: FIFO Low */ -#define USBD_EPMASK_FIFOHIGH (1 << 5) /* Bit 5: FIFO High */ -#define USBD_EPMASK_FIFOERROR (1 << 6) /* Bit 6: FIFO Error */ -#define USBD_EPMASK_FIFOEMPTY (1 << 7) /* Bit 7: FIFO Empty */ -#define USBD_EPMASK_FIFOFULL (1 << 8) /* Bit 8: FIFO Full */ - -/* USBD EPFSTAT Register */ - -#define USBD_EPFSTAT_EMPTY (1 << 16) /* Bit 16: FIFO Empty */ -#define USBD_EPFSTAT_ALARM (1 << 17) /* Bit 17: FIFO Alarm */ -#define USBD_EPFSTAT_FULL (1 << 18) /* Bit 18: FIFO Full */ -#define USBD_EPFSTAT_FR (1 << 19) /* Bit 19: FIFO Ready */ -#define USBD_EPFSTAT_OF (1 << 20) /* Bit 20: FIFO Overflow */ -#define USBD_EPFSTAT_UF (1 << 21) /* Bit 21: FIFO Underflow */ -#define USBD_EPFSTAT_ERROR (1 << 22) /* Bit 22: FIFO Error */ -#define USBD_EPFSTAT_FRAME3 (1 << 24) /* Bit 24: Frame Status Bit 3 */ -#define USBD_EPFSTAT_FRAME2 (1 << 25) /* Bit 25: Frame Status Bit 2 */ -#define USBD_EPFSTAT_FRAME1 (1 << 26) /* Bit 26: Frame Status Bit 1 */ -#define USBD_EPFSTAT_FRAME0 (1 << 27) /* Bit 27: Frame Status Bit 0 */ - -/* USBD EPFCTRL Register */ - -#define USBD_EPCTRL_GR_SHIFT 24 /* Bit 24-26: Granularity */ -#define USBD_EPCTRL_GR_MASK (0x07 << USBD_EPCTRL_GR_SHIFT) -#define USBD_EPCTRL_FRAME (1 << 27) /* Bit 27: Frame Mode */ -#define USBD_EPCTRL_WFR (1 << 28) /* Bit 29: Write Frame End */ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_IMX_USBD_H */ +/************************************************************************************ + * arch/arm/src/imx/imx_usbd.h + * + * Copyright (c) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_USBD_H +#define __ARCH_ARM_IMX_USBD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* USBD Register Offsets ************************************************************/ + +#define USBD_FRAME_OFFSET 0x0000 +#define USBD_SPEC_OFFSET 0x0004 +#define USBD_STAT_OFFSET 0x0008 +#define USBD_CTRL_OFFSET 0x000c +#define USBD_DADR_OFFSET 0x0010 +#define USBD_DDAT_OFFSET 0x0014 +#define USBD_INTR_OFFSET 0x0018 +#define USBD_MASK_OFFSET 0x001c +#define USBD_ENAB_OFFSET 0x0024 + +#define USBD_EP0_OFFSET 0x0030 +#define USBD_EP1_OFFSET 0x0060 +#define USBD_EP2_OFFSET 0x0090 +#define USBD_EP3_OFFSET 0x00c0 +#define USBD_EP4_OFFSET 0x00f0 +#define USBD_EP5_OFFSET 0x0120 +#define USBD_EP_OFFSET(n) (USBD_EP0_OFFSET + (n)*0x0030) + +#define USBD_EP_STAT_OFFSET 0x0000 +#define USBD_EP_INTR_OFFSET 0x0004 +#define USBD_EP_MASK_OFFSET 0x0008 +#define USBD_EP_FDAT_OFFSET 0x000c +#define USBD_EP_FSTAT_OFFSET 0x0010 +#define USBD_EP_FCTRL_OFFSET 0x0014 +#define USBD_EP_LRFP_OFFSET 0x0018 +#define USBD_EP_LRWP_OFFSET 0x001c +#define USBD_EP_FALRM_OFFSET 0x0020 +#define USBD_EP_FRDP_OFFSET 0x0024 +#define USBD_EP_FRWP_OFFSET 0x0028 + +/* USBD Register Addresses **********************************************************/ + +#define IMX_USBD_FRAME (IMX_USBD_VBASE + USBD_FRAME_OFFSET) +#define IMX_USBD_SPEC (IMX_USBD_VBASE + USBD_SPEC_OFFSET) +#define IMX_USBD_STAT (IMX_USBD_VBASE + USBD_STAT_OFFSET) +#define IMX_USBD_CTRL (IMX_USBD_VBASE + USBD_CTRL_OFFSET) +#define IMX_USBD_DADR (IMX_USBD_VBASE + USBD_DADR_OFFSET) +#define IMX_USBD_DDAT (IMX_USBD_VBASE + USBD_DDAT_OFFSET) +#define IMX_USBD_INTR (IMX_USBD_VBASE + USBD_INTR_OFFSET) +#define IMX_USBD_MASK (IMX_USBD_VBASE + USBD_MASK_OFFSET) +#define IMX_USBD_ENAB (IMX_USBD_VBASE + USBD_ENAB_OFFSET) + +#define IMX_USBD_EP0_BASE (IMX_USBD_VBASE + USBD_EP0_OFFSET) +#define IMX_USBD_EP1_BASE (IMX_USBD_VBASE + USBD_EP1_OFFSET) +#define IMX_USBD_EP2_BASE (IMX_USBD_VBASE + USBD_EP2_OFFSET) +#define IMX_USBD_EP3_BASE (IMX_USBD_VBASE + USBD_EP3_OFFSET) +#define IMX_USBD_EP4_BASE (IMX_USBD_VBASE + USBD_EP4_OFFSET) +#define IMX_USBD_EP5_BASE (IMX_USBD_VBASE + USBD_EP5_OFFSET) +#define IMX_USBD_EP_BASE(n) (IMX_USBD_VBASE + USBD_EP_OFFSET(n)) + +#define IMX_USBD_EP0_STAT (IMX_USBD_EP0_BASE + USBD_EP_STAT_OFFSET) +#define IMX_USBD_EP0_INTR (IMX_USBD_EP0_BASE + USBD_EP_INTR_OFFSET) +#define IMX_USBD_EP0_MASK (IMX_USBD_EP0_BASE + USBD_EP_MASK_OFFSET) +#define IMX_USBD_EP0_FDAT (IMX_USBD_EP0_BASE + USBD_EP_FDAT_OFFSET) +#define IMX_USBD_EP0_FSTAT (IMX_USBD_EP0_BASE + USBD_EP_FSTAT_OFFSET) +#define IMX_USBD_EP0_FCTRL (IMX_USBD_EP0_BASE + USBD_EP_FCTRL_OFFSET) +#define IMX_USBD_EP0_LRFP (IMX_USBD_EP0_BASE + USBD_EP_LRFP_OFFSET) +#define IMX_USBD_EP0_LRWP (IMX_USBD_EP0_BASE + USBD_EP_LRWP_OFFSET) +#define IMX_USBD_EP0_FALRM (IMX_USBD_EP0_BASE + USBD_EP_FALRM_OFFSET) +#define IMX_USBD_EP0_FRDP (IMX_USBD_EP0_BASE + USBD_EP_FRDP_OFFSET) +#define IMX_USBD_EP0_FRWP (IMX_USBD_EP0_BASE + USBD_EP_FRWP_OFFSET) + +#define IMX_USBD_EP1_STAT (IMX_USBD_EP1_BASE + USBD_EP_STAT_OFFSET) +#define IMX_USBD_EP1_INTR (IMX_USBD_EP1_BASE + USBD_EP_INTR_OFFSET) +#define IMX_USBD_EP1_MASK (IMX_USBD_EP1_BASE + USBD_EP_MASK_OFFSET) +#define IMX_USBD_EP1_FDAT (IMX_USBD_EP1_BASE + USBD_EP_FDAT_OFFSET) +#define IMX_USBD_EP1_FSTAT (IMX_USBD_EP1_BASE + USBD_EP_FSTAT_OFFSET) +#define IMX_USBD_EP1_FCTRL (IMX_USBD_EP1_BASE + USBD_EP_FCTRL_OFFSET) +#define IMX_USBD_EP1_LRFP (IMX_USBD_EP1_BASE + USBD_EP_LRFP_OFFSET) +#define IMX_USBD_EP1_LRWP (IMX_USBD_EP1_BASE + USBD_EP_LRWP_OFFSET) +#define IMX_USBD_EP1_FALRM (IMX_USBD_EP1_BASE + USBD_EP_FALRM_OFFSET) +#define IMX_USBD_EP1_FRDP (IMX_USBD_EP1_BASE + USBD_EP_FRDP_OFFSET) +#define IMX_USBD_EP1_FRWP (IMX_USBD_EP1_BASE + USBD_EP_FRWP_OFFSET) + +#define IMX_USBD_EP2_STAT (IMX_USBD_EP2_BASE + USBD_EP_STAT_OFFSET) +#define IMX_USBD_EP2_INTR (IMX_USBD_EP2_BASE + USBD_EP_INTR_OFFSET) +#define IMX_USBD_EP2_MASK (IMX_USBD_EP2_BASE + USBD_EP_MASK_OFFSET) +#define IMX_USBD_EP2_FDAT (IMX_USBD_EP2_BASE + USBD_EP_FDAT_OFFSET) +#define IMX_USBD_EP2_FSTAT (IMX_USBD_EP2_BASE + USBD_EP_FSTAT_OFFSET) +#define IMX_USBD_EP2_FCTRL (IMX_USBD_EP2_BASE + USBD_EP_FCTRL_OFFSET) +#define IMX_USBD_EP2_LRFP (IMX_USBD_EP2_BASE + USBD_EP_LRFP_OFFSET) +#define IMX_USBD_EP2_LRWP (IMX_USBD_EP2_BASE + USBD_EP_LRWP_OFFSET) +#define IMX_USBD_EP2_FALRM (IMX_USBD_EP2_BASE + USBD_EP_FALRM_OFFSET) +#define IMX_USBD_EP2_FRDP (IMX_USBD_EP2_BASE + USBD_EP_FRDP_OFFSET) +#define IMX_USBD_EP2_FRWP (IMX_USBD_EP2_BASE + USBD_EP_FRWP_OFFSET) + +#define IMX_USBD_EP3_STAT (IMX_USBD_EP3_BASE + USBD_EP_STAT_OFFSET) +#define IMX_USBD_EP3_INTR (IMX_USBD_EP3_BASE + USBD_EP_INTR_OFFSET) +#define IMX_USBD_EP3_MASK (IMX_USBD_EP3_BASE + USBD_EP_MASK_OFFSET) +#define IMX_USBD_EP3_FDAT (IMX_USBD_EP3_BASE + USBD_EP_FDAT_OFFSET) +#define IMX_USBD_EP3_FSTAT (IMX_USBD_EP3_BASE + USBD_EP_FSTAT_OFFSET) +#define IMX_USBD_EP3_FCTRL (IMX_USBD_EP3_BASE + USBD_EP_FCTRL_OFFSET) +#define IMX_USBD_EP3_LRFP (IMX_USBD_EP3_BASE + USBD_EP_LRFP_OFFSET) +#define IMX_USBD_EP3_LRWP (IMX_USBD_EP3_BASE + USBD_EP_LRWP_OFFSET) +#define IMX_USBD_EP3_FALRM (IMX_USBD_EP3_BASE + USBD_EP_FALRM_OFFSET) +#define IMX_USBD_EP3_FRDP (IMX_USBD_EP3_BASE + USBD_EP_FRDP_OFFSET) +#define IMX_USBD_EP3_FRWP (IMX_USBD_EP3_BASE + USBD_EP_FRWP_OFFSET) + +#define IMX_USBD_EP4_STAT (IMX_USBD_EP4_BASE + USBD_EP_STAT_OFFSET) +#define IMX_USBD_EP4_INTR (IMX_USBD_EP4_BASE + USBD_EP_INTR_OFFSET) +#define IMX_USBD_EP4_MASK (IMX_USBD_EP4_BASE + USBD_EP_MASK_OFFSET) +#define IMX_USBD_EP4_FDAT (IMX_USBD_EP4_BASE + USBD_EP_FDAT_OFFSET) +#define IMX_USBD_EP4_FSTAT (IMX_USBD_EP4_BASE + USBD_EP_FSTAT_OFFSET) +#define IMX_USBD_EP4_FCTRL (IMX_USBD_EP4_BASE + USBD_EP_FCTRL_OFFSET) +#define IMX_USBD_EP4_LRFP (IMX_USBD_EP4_BASE + USBD_EP_LRFP_OFFSET) +#define IMX_USBD_EP4_LRWP (IMX_USBD_EP4_BASE + USBD_EP_LRWP_OFFSET) +#define IMX_USBD_EP4_FALRM (IMX_USBD_EP4_BASE + USBD_EP_FALRM_OFFSET) +#define IMX_USBD_EP4_FRDP (IMX_USBD_EP4_BASE + USBD_EP_FRDP_OFFSET) +#define IMX_USBD_EP4_FRWP (IMX_USBD_EP4_BASE + USBD_EP_FRWP_OFFSET) + +#define IMX_USBD_EP5_STAT (IMX_USBD_EP5_BASE + USBD_EP_STAT_OFFSET) +#define IMX_USBD_EP5_INTR (IMX_USBD_EP5_BASE + USBD_EP_INTR_OFFSET) +#define IMX_USBD_EP5_MASK (IMX_USBD_EP5_BASE + USBD_EP_MASK_OFFSET) +#define IMX_USBD_EP5_FDAT (IMX_USBD_EP5_BASE + USBD_EP_FDAT_OFFSET) +#define IMX_USBD_EP5_FSTAT (IMX_USBD_EP5_BASE + USBD_EP_FSTAT_OFFSET) +#define IMX_USBD_EP5_FCTRL (IMX_USBD_EP5_BASE + USBD_EP_FCTRL_OFFSET) +#define IMX_USBD_EP5_LRFP (IMX_USBD_EP5_BASE + USBD_EP_LRFP_OFFSET) +#define IMX_USBD_EP5_LRWP (IMX_USBD_EP5_BASE + USBD_EP_LRWP_OFFSET) +#define IMX_USBD_EP5_FALRM (IMX_USBD_EP5_BASE + USBD_EP_FALRM_OFFSET) +#define IMX_USBD_EP5_FRDP (IMX_USBD_EP5_BASE + USBD_EP_FRDP_OFFSET) +#define IMX_USBD_EP5_FRWP (IMX_USBD_EP5_BASE + USBD_EP_FRWP_OFFSET) + +#define IMX_USBD_EP_STAT(n) (IMX_USBD_EP_BASE(n) + USBD_EP_STAT_OFFSET) +#define IMX_USBD_EP_INTR(n) (IMX_USBD_EP_BASE(n) + USBD_EP_INTR_OFFSET) +#define IMX_USBD_EP_MASK(n) (IMX_USBD_EP_BASE(n) + USBD_EP_MASK_OFFSET) +#define IMX_USBD_EP_FDAT(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FDAT_OFFSET) +#define IMX_USBD_EP_FSTAT(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FSTAT_OFFSET) +#define IMX_USBD_EP_FCTRL(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FCTRL_OFFSET) +#define IMX_USBD_EP_LRFP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_LRFP_OFFSET) +#define IMX_USBD_EP_LRWP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_LRWP_OFFSET) +#define IMX_USBD_EP_FALRM(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FALRM_OFFSET) +#define IMX_USBD_EP_FRDP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FRDP_OFFSET) +#define IMX_USBD_EP_FRWP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FRWP_OFFSET) + +/* USBD Register Bit Definitions ****************************************************/ + +/* USBD FRAME Register */ + +#define USBD_FRAME_FRAME_SHIFT 0 /* Bit 0-10: Frame Field */ +#define USBD_FRAME_FRAME_MASK (0x07ff << USBD_FRAME_FRAME_SHIFT) +#define USBD_FRAME_MATCH_SHIFT 16 /* Bit 16-26: Match Field */ +#define USBD_FRAME_MATCH_MASK (0x07ff << USBD_FRAME_MATCH_SHIFT) + +/* USBD STAT Register */ + +#define USBD_STAT_ALTSET_SHIFT 0 /* Bit 0-2: Alternate Setting */ +#define USBD_STAT_ALTSET_MASK (0x07 << USBD_FRAME_MATCH_SHIFT) +#define USBD_STAT_INTF_SHIFT 3 /* Bit 3-4: Interface */ +#define USBD_STAT_INTF_MASK (0x03 << USBD_FRAME_MATCH_SHIFT) +#define USBD_STAT_CFG_SHIFT 5 /* Bit 5-6: Configuration */ +#define USBD_STAT_CFG_MASK (0x03 << USBD_FRAME_MATCH_SHIFT) +#define USBD_STAT_SUSP (1 << 7) /* Bit 7: Suspend */ +#define USBD_STAT_RST (1 << 8) /* Bit 8: Reset Signaling */ + +/* USBD CTRL Register */ + +#define USBD_CTRL_RESUME (1 << 0) /* Bit 0: Resume */ +#define USBD_CTRL_AFEENA (1 << 1) /* Bit 1: Analog Front-End Enable */ +#define USBD_CTRL_UDCRST (1 << 2) /* Bit 2: UDC Reset */ +#define USBD_CTRL_USBENA (1 << 3) /* Bit 3: USB Enable */ +#define USBD_CTRL_USBSPD (1 << 4) /* Bit 4: USB Speed */ +#define USBD_CTRL_CMDERROR (1 << 5) /* Bit 5: Command Error */ +#define USBD_CTRL_CMDOVER (1 << 6) /* Bit 6: Command Over */ + +/* USBD DADR Register */ + +#define USBD_DADR_DADR_SHIFT 0 /* Bit 0-8: Desired RAM Address */ +#define USBD_DADR_DADR_MASK (0x1ff << USBD_DADR_DADR_SHIFT) +#define USBD_DADR_BSY (1 << 30) /* Bit 30: Busy */ +#define USBD_DADR_CFG (1 << 31) /* Bit 31: Configuration */ + +/* USBD DDAT Register */ + +#define USBD_DDAT_DDAT_SHIFT 0 /* Bit 0-7: Descriptor Data Buffer */ +#define USBD_DDAT_DDAT_MASK (0xff << USBD_DDAT_DDAT_SHIFT) + +/* USBD INTR Register */ + +#define USBD_INTR_CFGCHG (1 << 0) /* Bit 0: Configuration Change */ +#define USBD_INTR_FRAMEMATCH (1 << 1) /* Bit 1: FRAME_MATCH */ +#define USBD_INTR_SUSP (1 << 2) /* Bit 2: Active to Suspend */ +#define USBD_INTR_RES (1 << 3) /* Bit 3: Suspend to Resume */ +#define USBD_INTR_RESETSTART (1 << 4) /* Bit 4: Restart Signaling Start */ +#define USBD_INTR_RESETSTOP (1 << 5) /* Bit 5: Restart Signaling Stop */ +#define USBD_INTR_SOF (1 << 6) /* Bit 6: Start-of-Frame Interrupt */ +#define USBD_INTR_MSOF (1 << 7) /* Bit 7: Missed Start-of-Frame Interrupt */ +#define USBD_INTR_WAKEUP (1 << 31) /* Bit 31: Wakeup */ + +/* USBD MASK Register */ + +#define USBD_MASK_CFGCHG (1 << 0) /* Bit 0: Configuration Change */ +#define USBD_MASK_FRAMEMATCH (1 << 1) /* Bit 1: FRAME_MATCH */ +#define USBD_MASK_SUSP (1 << 2) /* Bit 2: Active to Suspend */ +#define USBD_MASK_RES (1 << 3) /* Bit 3: Suspend to Resume */ +#define USBD_MASK_RESETSTART (1 << 4) /* Bit 4: Restart Signaling Start */ +#define USBD_MASK_RESETSTOP (1 << 5) /* Bit 5: Restart Signaling Stop */ +#define USBD_MASK_SOF (1 << 6) /* Bit 6: Start-of-Frame Interrupt */ +#define USBD_MASK_MSOF (1 << 7) /* Bit 7: Missed Start-of-Frame Interrupt */ +#define USBD_MASK_WAKEUP (1 << 31) /* Bit 31: Wakeup */ + +/* USBD ENAB Register */ + +#define USBD_ENAB_PWDMD (1 << 0) /* Bit 0: Power Mode */ +#define USBD_ENAB_ENDIANMODE (1 << 28) /* Bit 28: Endian Mode Select */ +#define USBD_ENAB_SUSPEND (1 << 29) /* Bit 29: Suspend */ +#define USBD_ENAB_ENAB (1 << 30) /* Bit 30: Enable */ +#define USBD_ENAB_RST (1 << 31) /* Bit 31: Reset */ + +/* USBD EPSTAT Register */ + +#define USBD_EPSTAT_FORCESTALL (1 << 0) /* Bit 0: Force a Stall Condition */ +#define USBD_EPSTAT_FLUSH (1 << 1) /* Bit 1: Flush */ +#define USBD_EPSTAT_ZLPS (1 << 2) /* Bit 2: Zero Length Packet Send */ +#define USBD_EPSTAT_TYP_SHIFT 3 /* Bit 3-4: Endpoint Type */ +#define USBD_EPSTAT_TYP_MASK (0x03 << USBD_EPSTAT_TYP_SHIFT) +#define USBD_EPSTAT_MAX_SHIFT 5 /* Bit 5-6: Maximum Packet Size */ +#define USBD_EPSTAT_MAX_MASK (0x03 << USBD_EPSTAT_MAX_SHIFT) +#define USBD_EPSTAT_DIR (1 << 7) /* Bit 7: Transfer Direction */ +#define USBD_EPSTAT_SIP (1 << 8) /* Bit 8: Setup Packet in Progress */ +#define USBD_EPSTAT_BYTECOUNT_SHIFT 16 /* Bit 16-22: Byte Count */ +#define USBD_EPSTAT_BYTECOUNT_MASK (0x7f << USBD_EPSTAT_BYTECOUNT_SHIFT) + +/* USBD EPINTR Register */ + +#define USBD_EPINTR_EOF (1 << 0) /* Bit 0: End-of-Frame */ +#define USBD_EPINTR_DEVREQ (1 << 1) /* Bit 1: Device Request */ +#define USBD_EPINTR_EOT (1 << 2) /* Bit 2: End of Transfer */ +#define USBD_EPINTR_MDEVREQ (1 << 3) /* Bit 3: Multiple Device Request */ +#define USBD_EPINTR_FIFOLOW (1 << 4) /* Bit 4: FIFO Low */ +#define USBD_EPINTR_FIFOHIGH (1 << 5) /* Bit 5: FIFO High */ +#define USBD_EPINTR_FIFOERROR (1 << 6) /* Bit 6: FIFO Error */ +#define USBD_EPINTR_FIFOEMPTY (1 << 7) /* Bit 7: FIFO Empty */ +#define USBD_EPINTR_FIFOFULL (1 << 8) /* Bit 8: FIFO Full */ + +/* USBD EPMASK Register */ + +#define USBD_EPMASK_EOF (1 << 0) /* Bit 0: End-of-Frame */ +#define USBD_EPMASK_DEVREQ (1 << 1) /* Bit 1: Device Request */ +#define USBD_EPMASK_EOT (1 << 2) /* Bit 2: End of Transfer */ +#define USBD_EPMASK_MDEVREQ (1 << 3) /* Bit 3: Multiple Device Request */ +#define USBD_EPMASK_FIFOLOW (1 << 4) /* Bit 4: FIFO Low */ +#define USBD_EPMASK_FIFOHIGH (1 << 5) /* Bit 5: FIFO High */ +#define USBD_EPMASK_FIFOERROR (1 << 6) /* Bit 6: FIFO Error */ +#define USBD_EPMASK_FIFOEMPTY (1 << 7) /* Bit 7: FIFO Empty */ +#define USBD_EPMASK_FIFOFULL (1 << 8) /* Bit 8: FIFO Full */ + +/* USBD EPFSTAT Register */ + +#define USBD_EPFSTAT_EMPTY (1 << 16) /* Bit 16: FIFO Empty */ +#define USBD_EPFSTAT_ALARM (1 << 17) /* Bit 17: FIFO Alarm */ +#define USBD_EPFSTAT_FULL (1 << 18) /* Bit 18: FIFO Full */ +#define USBD_EPFSTAT_FR (1 << 19) /* Bit 19: FIFO Ready */ +#define USBD_EPFSTAT_OF (1 << 20) /* Bit 20: FIFO Overflow */ +#define USBD_EPFSTAT_UF (1 << 21) /* Bit 21: FIFO Underflow */ +#define USBD_EPFSTAT_ERROR (1 << 22) /* Bit 22: FIFO Error */ +#define USBD_EPFSTAT_FRAME3 (1 << 24) /* Bit 24: Frame Status Bit 3 */ +#define USBD_EPFSTAT_FRAME2 (1 << 25) /* Bit 25: Frame Status Bit 2 */ +#define USBD_EPFSTAT_FRAME1 (1 << 26) /* Bit 26: Frame Status Bit 1 */ +#define USBD_EPFSTAT_FRAME0 (1 << 27) /* Bit 27: Frame Status Bit 0 */ + +/* USBD EPFCTRL Register */ + +#define USBD_EPCTRL_GR_SHIFT 24 /* Bit 24-26: Granularity */ +#define USBD_EPCTRL_GR_MASK (0x07 << USBD_EPCTRL_GR_SHIFT) +#define USBD_EPCTRL_FRAME (1 << 27) /* Bit 27: Frame Mode */ +#define USBD_EPCTRL_WFR (1 << 28) /* Bit 29: Write Frame End */ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_USBD_H */ diff --git a/arch/arm/src/imx/imx_wdog.h b/arch/arm/src/imx/imx_wdog.h index 137e677541dcb292ffdf53681490536b84de4d6f..4ee6438b3666e4f50976d90b3a8639352be77aa0 100755 --- a/arch/arm/src/imx/imx_wdog.h +++ b/arch/arm/src/imx/imx_wdog.h @@ -1,81 +1,81 @@ -/************************************************************************************ - * arch/arm/src/imx/imx_wdog.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_IMX_WDOG_H -#define __ARCH_ARM_IMX_WDOG_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* WDOG Register Offsets ************************************************************/ - -#define WDOG_WCR_OFFSET 0x0000 /* Watchdog Control Register */ -#define WDOG_WSR_OFFSET 0x0004 /* Watchdog Service Register */ -#define WDOG_WSTR_OFFSET 0x0008 /* Watchdog Status Register */ - -/* WDOG Register Addresses **********************************************************/ - -#define IMX_WDOG_WCR (IMX_WDOG_VBASE + WDOG_WCR_OFFSET) -#define IMX_WDOG_WSR (IMX_WDOG_VBASE + WDOG_WSR_OFFSET) -#define IMX_WDOG_WSTRT (IMX_WDOG_VBASE + WDOG_WSTR_OFFSET) - -/* WDOG Register Bit Definitions ****************************************************/ - -/* Watchdog Control Register */ - -#define WDOG_WCR_WDE (1 << 0) /* Bit 0: Watchdog Enable */ -#define WDOG_WCR_WDEC (1 << 1) /* Bit 1: Watchdog Enable Control */ -#define WDOG_WCR_SWR (1 << 2) /* Bit 2: Software Reset Enable */ -#define WDOG_WCR_TMD (1 << 3) /* Bit 3: Test Mode Enable */ -#define WDOG_WCR_WIE (1 << 4) /* Bit 4: Watchdog Interrupt Enable */ -#define WDOG_WCR_WT_SHIFT 8 /* Bit 8-14: Watchdog Timeout */ -#define WDOG_WCR_WT_MASK (0x7f << WDOG_WCR_WT_SHIFT) -#define WDOG_WCR_WHALT (1 << 15) /* Bit 15: Watchdog Halt */ - -/* Watchdog Service Register */ - -#define WDOG_WSR_SHIFT 0 /* Bit 0-15: Watchdog Service Register */ -#define WDOG_WT_MASK (0xffff << WDOG_WSR_SHIFT) - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_IMX_WDOG_H */ +/************************************************************************************ + * arch/arm/src/imx/imx_wdog.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_IMX_WDOG_H +#define __ARCH_ARM_IMX_WDOG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* WDOG Register Offsets ************************************************************/ + +#define WDOG_WCR_OFFSET 0x0000 /* Watchdog Control Register */ +#define WDOG_WSR_OFFSET 0x0004 /* Watchdog Service Register */ +#define WDOG_WSTR_OFFSET 0x0008 /* Watchdog Status Register */ + +/* WDOG Register Addresses **********************************************************/ + +#define IMX_WDOG_WCR (IMX_WDOG_VBASE + WDOG_WCR_OFFSET) +#define IMX_WDOG_WSR (IMX_WDOG_VBASE + WDOG_WSR_OFFSET) +#define IMX_WDOG_WSTRT (IMX_WDOG_VBASE + WDOG_WSTR_OFFSET) + +/* WDOG Register Bit Definitions ****************************************************/ + +/* Watchdog Control Register */ + +#define WDOG_WCR_WDE (1 << 0) /* Bit 0: Watchdog Enable */ +#define WDOG_WCR_WDEC (1 << 1) /* Bit 1: Watchdog Enable Control */ +#define WDOG_WCR_SWR (1 << 2) /* Bit 2: Software Reset Enable */ +#define WDOG_WCR_TMD (1 << 3) /* Bit 3: Test Mode Enable */ +#define WDOG_WCR_WIE (1 << 4) /* Bit 4: Watchdog Interrupt Enable */ +#define WDOG_WCR_WT_SHIFT 8 /* Bit 8-14: Watchdog Timeout */ +#define WDOG_WCR_WT_MASK (0x7f << WDOG_WCR_WT_SHIFT) +#define WDOG_WCR_WHALT (1 << 15) /* Bit 15: Watchdog Halt */ + +/* Watchdog Service Register */ + +#define WDOG_WSR_SHIFT 0 /* Bit 0-15: Watchdog Service Register */ +#define WDOG_WT_MASK (0xffff << WDOG_WSR_SHIFT) + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_IMX_WDOG_H */ diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs index 2b978b6b50a7128de0f870713eb170fb6c932b7f..22d066828b026f2301ae57a04366066032852c4c 100644 --- a/arch/arm/src/kinetis/Make.defs +++ b/arch/arm/src/kinetis/Make.defs @@ -2,7 +2,7 @@ # arch/arm/src/kinetis/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/chip.h b/arch/arm/src/kinetis/chip.h index 253562a06ec07cdadbe274d5388b2f391a53c83d..6ad781c20825776ed74b086cc0064285ef262885 100644 --- a/arch/arm/src/kinetis/chip.h +++ b/arch/arm/src/kinetis/chip.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/chip.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_adc.h b/arch/arm/src/kinetis/kinetis_adc.h index 47bbdbd70618fc41345d4a35b64ce186f7f08dad..a17aa06c7f4274ca8a612e933cafec3c43c9bd71 100644 --- a/arch/arm/src/kinetis/kinetis_adc.h +++ b/arch/arm/src/kinetis/kinetis_adc.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_adc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_aips.h b/arch/arm/src/kinetis/kinetis_aips.h index 6e04401476015b45969c86435fb8dc5b674472df..8f460567f76125052a24664fdc02843624729dba 100644 --- a/arch/arm/src/kinetis/kinetis_aips.h +++ b/arch/arm/src/kinetis/kinetis_aips.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_aips.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_axbs.h b/arch/arm/src/kinetis/kinetis_axbs.h index 4a51360053b8f917d0a1aaa214776c520d139cc9..bf8543d4dac5a5dc5b13a4b110e447483d1dcdb7 100644 --- a/arch/arm/src/kinetis/kinetis_axbs.h +++ b/arch/arm/src/kinetis/kinetis_axbs.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_axbs.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_clockconfig.c b/arch/arm/src/kinetis/kinetis_clockconfig.c index f167a0328a5977e0462668d394e588a0afa2107d..31ea235d2cf311563bf51656bb538668be6ce013 100644 --- a/arch/arm/src/kinetis/kinetis_clockconfig.c +++ b/arch/arm/src/kinetis/kinetis_clockconfig.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/kinetis_clockconfig.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_clrpend.c b/arch/arm/src/kinetis/kinetis_clrpend.c index 98997bf2edb6bae4e027f65ada4b5cdd5745debb..2837d867f34d253735539d1920e8f77bd61bd36f 100644 --- a/arch/arm/src/kinetis/kinetis_clrpend.c +++ b/arch/arm/src/kinetis/kinetis_clrpend.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/kinetis_clrpend.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_cmp.h b/arch/arm/src/kinetis/kinetis_cmp.h index 207d8619724ba6ff14d58fc2ed0c7bb0e98746cd..822b7a339f5de9603af3e3236f03d1e5b47068ba 100644 --- a/arch/arm/src/kinetis/kinetis_cmp.h +++ b/arch/arm/src/kinetis/kinetis_cmp.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_cmp.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_cmt.h b/arch/arm/src/kinetis/kinetis_cmt.h index 34cd12177256d917930e7b64c5287c4028300ced..c3c47bb6761254a0ce4c86484a43e41809433cdf 100644 --- a/arch/arm/src/kinetis/kinetis_cmt.h +++ b/arch/arm/src/kinetis/kinetis_cmt.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_cmt.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_config.h b/arch/arm/src/kinetis/kinetis_config.h index 025ebc7a854fc5d34a924a0120e6f372e3b16115..4faa90ce7d26eae8ad8b0fc2d84adbc2af2dc8a3 100644 --- a/arch/arm/src/kinetis/kinetis_config.h +++ b/arch/arm/src/kinetis/kinetis_config.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_config.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_crc.h b/arch/arm/src/kinetis/kinetis_crc.h index 88e20f64c04a8c52fe3f2304a382f79d0389ec26..7b590cf3a9a0c39374982f0c8b747da54bb71ccf 100644 --- a/arch/arm/src/kinetis/kinetis_crc.h +++ b/arch/arm/src/kinetis/kinetis_crc.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_crc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_dac.h b/arch/arm/src/kinetis/kinetis_dac.h index fbc2fd697315b09a2bed61987abc20341faff32c..5c3b5c0c037503fc669c2427f5581f6b2322285d 100644 --- a/arch/arm/src/kinetis/kinetis_dac.h +++ b/arch/arm/src/kinetis/kinetis_dac.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_dac.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_dma.h b/arch/arm/src/kinetis/kinetis_dma.h index efe586345a20a51b80ae55ee9747fb1879b668a7..9876a46a0f0fdc794f55676c284e2f446ea5dd8a 100644 --- a/arch/arm/src/kinetis/kinetis_dma.h +++ b/arch/arm/src/kinetis/kinetis_dma.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_dma.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_dmamux.h b/arch/arm/src/kinetis/kinetis_dmamux.h index 0db25305d0f17c3b9d41465b0ffd2c4b9a2a956f..b83579180ea0ca53d2d0b99d55ac6de604ab51e8 100644 --- a/arch/arm/src/kinetis/kinetis_dmamux.h +++ b/arch/arm/src/kinetis/kinetis_dmamux.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_dmamux.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_dspi.h b/arch/arm/src/kinetis/kinetis_dspi.h index a2ead5852c5829570df71f2e69d886a61748c08c..e682ef23e8555ab5f706903846579803d7c16e39 100644 --- a/arch/arm/src/kinetis/kinetis_dspi.h +++ b/arch/arm/src/kinetis/kinetis_dspi.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_dspi.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_enet.h b/arch/arm/src/kinetis/kinetis_enet.h index d610f15c3a47f8cd4670e86f2d2af668db855555..0a5e78ea92e8391f965674b6b90a50049c8200e6 100644 --- a/arch/arm/src/kinetis/kinetis_enet.h +++ b/arch/arm/src/kinetis/kinetis_enet.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_enet.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_ewm.h b/arch/arm/src/kinetis/kinetis_ewm.h index 4e6113e817b7226958d11105259a40b9ca0d2fd7..e259a3cf29af2f891e40532f4afd01ff3e5626bc 100644 --- a/arch/arm/src/kinetis/kinetis_ewm.h +++ b/arch/arm/src/kinetis/kinetis_ewm.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_ewm.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_flexbus.h b/arch/arm/src/kinetis/kinetis_flexbus.h index e4936949ad5e747e0d9a0591608de2a726e7072a..37992320fb18804f50c1d985bcfe5a3e13a85bef 100644 --- a/arch/arm/src/kinetis/kinetis_flexbus.h +++ b/arch/arm/src/kinetis/kinetis_flexbus.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_flexbus.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_flexcan.h b/arch/arm/src/kinetis/kinetis_flexcan.h index f129c95773b43481245dc00fd078327747655db9..db151d5403474d7dd1dc48ee249a8043846ae774 100644 --- a/arch/arm/src/kinetis/kinetis_flexcan.h +++ b/arch/arm/src/kinetis/kinetis_flexcan.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_flexcan.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_fmc.h b/arch/arm/src/kinetis/kinetis_fmc.h index 2a318e3dece50a01a68aab203afcd715a06eaa01..66f3a390926777330a36fed3374cc2a7632741d7 100644 --- a/arch/arm/src/kinetis/kinetis_fmc.h +++ b/arch/arm/src/kinetis/kinetis_fmc.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_fmc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_ftfl.h b/arch/arm/src/kinetis/kinetis_ftfl.h index 27746ab023a85b0a03948a9422e481769cb8e423..92e53b650d03d2cfbaf6ba3b3cd9427304069d8d 100644 --- a/arch/arm/src/kinetis/kinetis_ftfl.h +++ b/arch/arm/src/kinetis/kinetis_ftfl.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_ftfl.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_ftm.h b/arch/arm/src/kinetis/kinetis_ftm.h index a318ddfeebb40a43051be7eb93236aa6e94e6abf..52f782855b7c82cd239ed8ece5204db7852488c4 100644 --- a/arch/arm/src/kinetis/kinetis_ftm.h +++ b/arch/arm/src/kinetis/kinetis_ftm.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_ftm.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_gpio.h b/arch/arm/src/kinetis/kinetis_gpio.h index 8a87aa72aa76db6080bd15b00929b553bfd90f27..1d3d10553fbe93dae7787f8b953291e1df3299a8 100644 --- a/arch/arm/src/kinetis/kinetis_gpio.h +++ b/arch/arm/src/kinetis/kinetis_gpio.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_gpio.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_i2c.h b/arch/arm/src/kinetis/kinetis_i2c.h index 353882eff23cb9cee89499dc9f43a2d04c693b61..bee9ef92db16c19ffe2dc0eb1815140211295345 100644 --- a/arch/arm/src/kinetis/kinetis_i2c.h +++ b/arch/arm/src/kinetis/kinetis_i2c.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_i2c.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_i2s.h b/arch/arm/src/kinetis/kinetis_i2s.h index f69aa854369b443d8ada92af88fc305820f09bba..11bcc0995562bbb550a7380bf8191bf8534e2c42 100644 --- a/arch/arm/src/kinetis/kinetis_i2s.h +++ b/arch/arm/src/kinetis/kinetis_i2s.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_i2s.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_idle.c b/arch/arm/src/kinetis/kinetis_idle.c index 8fc914f3f48ffab039eadfd7dd3bd0b57eb92198..bcf8218cb4c58cdfdf6ebdfd3e8c38b0159e288f 100644 --- a/arch/arm/src/kinetis/kinetis_idle.c +++ b/arch/arm/src/kinetis/kinetis_idle.c @@ -1,104 +1,104 @@ -/**************************************************************************** - * arch/arm/src/kinetis/kinetis_idle.c - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include "up_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Does the board support an IDLE LED to indicate that the board is in the - * IDLE state? - */ - -#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() up_ledon(LED_IDLE) -# define END_IDLE() up_ledoff(LED_IDLE) -#else -# define BEGIN_IDLE() -# define END_IDLE() -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idle - * - * Description: - * up_idle() is the logic that will be executed when their is no other - * ready-to-run task. This is processor idle time and will continue until - * some interrupt occurs to cause a context switch from the idle task. - * - * Processing in this state may be processor-specific. e.g., this is where - * power management operations might be performed. - * - ****************************************************************************/ - -void up_idle(void) -{ -#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) - /* If the system is idle and there are no timer interrupts, then process - * "fake" timer interrupts. Hopefully, something will wake up. - */ - - sched_process_timer(); -#else - - /* Sleep until an interrupt occurs to save power */ - - BEGIN_IDLE(); - asm("WFI"); - END_IDLE(); -#endif -} - +/**************************************************************************** + * arch/arm/src/kinetis/kinetis_idle.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() up_ledon(LED_IDLE) +# define END_IDLE() up_ledoff(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + sched_process_timer(); +#else + + /* Sleep until an interrupt occurs to save power */ + + BEGIN_IDLE(); + asm("WFI"); + END_IDLE(); +#endif +} + diff --git a/arch/arm/src/kinetis/kinetis_internal.h b/arch/arm/src/kinetis/kinetis_internal.h index c05032678802e752b42387ddda1ce57ddda28bc8..8d7baaaf1b16c861ecaece5562e0b4b58563444a 100644 --- a/arch/arm/src/kinetis/kinetis_internal.h +++ b/arch/arm/src/kinetis/kinetis_internal.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_internal.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_irq.c b/arch/arm/src/kinetis/kinetis_irq.c index 308afcb974d980cd653fbfc115422b9e63743344..6fb58c6bf984f59a9a08fa58189c7b9704a2404f 100644 --- a/arch/arm/src/kinetis/kinetis_irq.c +++ b/arch/arm/src/kinetis/kinetis_irq.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/kinetis_irq.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_k40pinmux.h b/arch/arm/src/kinetis/kinetis_k40pinmux.h index 13a4da4213c19819a245bc8dd553c4dd9164f549..9798eda6be1522e19bf0b7fc2bc1d176a61a0fed 100644 --- a/arch/arm/src/kinetis/kinetis_k40pinmux.h +++ b/arch/arm/src/kinetis/kinetis_k40pinmux.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_k40pinmux.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_k60pinmux.h b/arch/arm/src/kinetis/kinetis_k60pinmux.h index dee0d15d67aea5c975c23da4f28eb5ef5664d27e..2c77dd4ba79ecfd6ccb6be97eca266099dc29223 100644 --- a/arch/arm/src/kinetis/kinetis_k60pinmux.h +++ b/arch/arm/src/kinetis/kinetis_k60pinmux.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_k60pinset.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_llwu.h b/arch/arm/src/kinetis/kinetis_llwu.h index 60fa2fed746ca2582382dfb2961da2c46675f7d1..4324a76251b412e0a542816025f408c85514f8a2 100644 --- a/arch/arm/src/kinetis/kinetis_llwu.h +++ b/arch/arm/src/kinetis/kinetis_llwu.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_llwu.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_lowputc.c b/arch/arm/src/kinetis/kinetis_lowputc.c index 96d9d69897c72201928654b4be6fe0c1f60385cb..f52d3ba35c08c1860ed967d7f97ebce460c9e0c7 100644 --- a/arch/arm/src/kinetis/kinetis_lowputc.c +++ b/arch/arm/src/kinetis/kinetis_lowputc.c @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_lowputc.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_lptmr.h b/arch/arm/src/kinetis/kinetis_lptmr.h index 42e251f3018653cd07d9faa87f8a6acb8d13e8cb..863b24108eacec47e4808534cc2a7e93ff602132 100644 --- a/arch/arm/src/kinetis/kinetis_lptmr.h +++ b/arch/arm/src/kinetis/kinetis_lptmr.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_lptmr.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_mcg.h b/arch/arm/src/kinetis/kinetis_mcg.h index 6f0ba652cc12b056c23a3064babed392ec5c3fec..60f13cd2a0b788ef8e897b0c9adbeee28387aae0 100644 --- a/arch/arm/src/kinetis/kinetis_mcg.h +++ b/arch/arm/src/kinetis/kinetis_mcg.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_mcg.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_mcm.h b/arch/arm/src/kinetis/kinetis_mcm.h index 8424587aac40a2dbad3939b76d546da22add6479..d899b77027ac135150314bfaf214ef3cc7ba6c29 100644 --- a/arch/arm/src/kinetis/kinetis_mcm.h +++ b/arch/arm/src/kinetis/kinetis_mcm.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_mcm.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_memorymap.h b/arch/arm/src/kinetis/kinetis_memorymap.h index be0b2295432a74677ba11f1ba5d4ee9cc6a5dcef..7253717bd2fa94a54a9b87b3ea21df5ceda736f6 100644 --- a/arch/arm/src/kinetis/kinetis_memorymap.h +++ b/arch/arm/src/kinetis/kinetis_memorymap.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_memorymap.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_mmcau.h b/arch/arm/src/kinetis/kinetis_mmcau.h index f1ba0e76903a82afefd0659870c71324a8c519fb..7468a1d0bfe3b3563918e57adf8a99bdfb0aed86 100644 --- a/arch/arm/src/kinetis/kinetis_mmcau.h +++ b/arch/arm/src/kinetis/kinetis_mmcau.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_mmcau.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_mpu.h b/arch/arm/src/kinetis/kinetis_mpu.h index 9db2570b9d0aea5becc0974102b0b67a69799d5a..f2b1bf914338bc5c94ca0baff83c7fff5faf2260 100644 --- a/arch/arm/src/kinetis/kinetis_mpu.h +++ b/arch/arm/src/kinetis/kinetis_mpu.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_mpu.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_osc.h b/arch/arm/src/kinetis/kinetis_osc.h index fef1e0ae71e7b13ac94f3b99e3a1b30ce1a446e4..16efcf328266055cf0ac411838a8b948dd520f93 100644 --- a/arch/arm/src/kinetis/kinetis_osc.h +++ b/arch/arm/src/kinetis/kinetis_osc.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_osc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_pdb.h b/arch/arm/src/kinetis/kinetis_pdb.h index 525efc73889f9f7f9b8f03f4c9ed1a7598c9b8e6..9cfab9b99f187b3dbe0440f2c486d32c84784ce5 100644 --- a/arch/arm/src/kinetis/kinetis_pdb.h +++ b/arch/arm/src/kinetis/kinetis_pdb.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_pdb.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_pin.c b/arch/arm/src/kinetis/kinetis_pin.c index cdd9e19c1ef5912e9c7136d8703d56463cad1ea7..43bfae61eff607fdff07f1fdbb7d681223b53ae5 100644 --- a/arch/arm/src/kinetis/kinetis_pin.c +++ b/arch/arm/src/kinetis/kinetis_pin.c @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_pin.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_pindma.c b/arch/arm/src/kinetis/kinetis_pindma.c index 00d9a07e69015b37eabf0a7cce392cd0b203593f..91132a6a749c142b74886357005dffe76bafb950 100644 --- a/arch/arm/src/kinetis/kinetis_pindma.c +++ b/arch/arm/src/kinetis/kinetis_pindma.c @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_pindma.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_pingpio.c b/arch/arm/src/kinetis/kinetis_pingpio.c index 23829c6d7eee6d32aa38876055497aeef6d0211d..fe25f0df0fc5b246f6fd88ac61d971a3a80b84e7 100644 --- a/arch/arm/src/kinetis/kinetis_pingpio.c +++ b/arch/arm/src/kinetis/kinetis_pingpio.c @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_pingpio.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_pinirq.c b/arch/arm/src/kinetis/kinetis_pinirq.c index 1ed9092e2899b0359071c299f0c7e782294af07b..537e7be9f24aeeb18fe4d60b6309d5b216746c6f 100644 --- a/arch/arm/src/kinetis/kinetis_pinirq.c +++ b/arch/arm/src/kinetis/kinetis_pinirq.c @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_pinirq.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_pinmux.h b/arch/arm/src/kinetis/kinetis_pinmux.h index 04d956e4ea1ea5f15aefdfbf828cec90ee8f38c5..9c791539f69722812284d1e950586938dc7dedcf 100644 --- a/arch/arm/src/kinetis/kinetis_pinmux.h +++ b/arch/arm/src/kinetis/kinetis_pinmux.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_pinmux.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_pit.h b/arch/arm/src/kinetis/kinetis_pit.h index 6771f6310943559754d86f37d1796bf31ec0c0e5..808508f8fedd17be9e6af540338c248095be02fc 100644 --- a/arch/arm/src/kinetis/kinetis_pit.h +++ b/arch/arm/src/kinetis/kinetis_pit.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_pit.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_pmc.h b/arch/arm/src/kinetis/kinetis_pmc.h index 2525a936c76284af55a241df19c13810c3297144..065847da3d5a6f5bc702e8f7f44b8b1d7273ccad 100644 --- a/arch/arm/src/kinetis/kinetis_pmc.h +++ b/arch/arm/src/kinetis/kinetis_pmc.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_pmc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_port.h b/arch/arm/src/kinetis/kinetis_port.h index 2f72f4874361a2f630e562cc2024e3a5db026958..a256fc5c656842d84e2e08be67090feca49cd5ea 100644 --- a/arch/arm/src/kinetis/kinetis_port.h +++ b/arch/arm/src/kinetis/kinetis_port.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_port.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_rngb.h b/arch/arm/src/kinetis/kinetis_rngb.h index f55b37843e4f42bbef64a27ff4b59d7e25608133..a4f677555030cd5be5f25fd5898407986aeeb40e 100644 --- a/arch/arm/src/kinetis/kinetis_rngb.h +++ b/arch/arm/src/kinetis/kinetis_rngb.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_rngb.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_rtc.h b/arch/arm/src/kinetis/kinetis_rtc.h index 2a3c57e59da99a04b6d0003e04a7bde0bfec8244..69c097a7c950627992f577b40e61cede1480ccf4 100644 --- a/arch/arm/src/kinetis/kinetis_rtc.h +++ b/arch/arm/src/kinetis/kinetis_rtc.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_rtc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_sdhc.h b/arch/arm/src/kinetis/kinetis_sdhc.h index cf96faabeccd406ded9cdbd3926db625f4c04977..5d122315a9d2efa426865fd396748ac3e0372434 100644 --- a/arch/arm/src/kinetis/kinetis_sdhc.h +++ b/arch/arm/src/kinetis/kinetis_sdhc.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_sdhc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_sim.h b/arch/arm/src/kinetis/kinetis_sim.h index bdbf4dc026adcc254d866defd825f855999b1bd4..aad17e923e80c2bc7513fba4ff707c3825e2d5a3 100644 --- a/arch/arm/src/kinetis/kinetis_sim.h +++ b/arch/arm/src/kinetis/kinetis_sim.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_sim.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_slcd.h b/arch/arm/src/kinetis/kinetis_slcd.h index 6849af423c8e3d579bac9675f923d9552e197cc7..d56ee5c41eac0e547aeb67874a94d8b76bf95d34 100644 --- a/arch/arm/src/kinetis/kinetis_slcd.h +++ b/arch/arm/src/kinetis/kinetis_slcd.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_slcd.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_smc.h b/arch/arm/src/kinetis/kinetis_smc.h index b596164b05727a09b9dc8f53ef59147bb77d36b3..213ea80775972d3f6537b77ec3b36e492b1a0e2d 100644 --- a/arch/arm/src/kinetis/kinetis_smc.h +++ b/arch/arm/src/kinetis/kinetis_smc.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_smc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_timerisr.c b/arch/arm/src/kinetis/kinetis_timerisr.c index 62758ee9c3355fafc8be4209e1caa30e6b8d41a4..9f9f14ba6cbdd0f7a6ef5a4ce51b4ce662520c49 100644 --- a/arch/arm/src/kinetis/kinetis_timerisr.c +++ b/arch/arm/src/kinetis/kinetis_timerisr.c @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_timerisr.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_tsi.h b/arch/arm/src/kinetis/kinetis_tsi.h index df96a0d8c75992ef5ab9eb2c47660bbe1941837c..5e1dd9976b78714c5dcbc521f36842ede837838c 100644 --- a/arch/arm/src/kinetis/kinetis_tsi.h +++ b/arch/arm/src/kinetis/kinetis_tsi.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_tsi.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_uart.h b/arch/arm/src/kinetis/kinetis_uart.h index 2983aaf0db22f73cfe5ca4677cdaddfd1ec06c75..fbdf7a3192a86cb4536100ef092b38beed3256a8 100644 --- a/arch/arm/src/kinetis/kinetis_uart.h +++ b/arch/arm/src/kinetis/kinetis_uart.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_uart.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_usbdcd.h b/arch/arm/src/kinetis/kinetis_usbdcd.h index cfbb28a97e90249de1fb24147447c4e6d5a74c2b..fad76d1500e8771666c3dc123a676dd905d72712 100644 --- a/arch/arm/src/kinetis/kinetis_usbdcd.h +++ b/arch/arm/src/kinetis/kinetis_usbdcd.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_usbdcd.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_usbotg.h b/arch/arm/src/kinetis/kinetis_usbotg.h index 9219398e792b570bcfe63e04a02915ca5e3f5772..127c718312d629bc98bd5c45cb983f650a53f6e8 100644 --- a/arch/arm/src/kinetis/kinetis_usbotg.h +++ b/arch/arm/src/kinetis/kinetis_usbotg.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_usbotg.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_vectors.S b/arch/arm/src/kinetis/kinetis_vectors.S index ff252c91a132e6c672f4317e3ef0b2df7da4b14c..faa1ce7a780be11b3b755010e23ed175853b2c34 100644 --- a/arch/arm/src/kinetis/kinetis_vectors.S +++ b/arch/arm/src/kinetis/kinetis_vectors.S @@ -3,7 +3,7 @@ * arch/arm/src/chip/kinetis_vectors.S * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_vrefv1.h b/arch/arm/src/kinetis/kinetis_vrefv1.h index 01789e21252ab56a5f632fe6d70c3fae485b70f1..ed9a1ff95c5dc51779b89864f9ac29f5f73f371c 100644 --- a/arch/arm/src/kinetis/kinetis_vrefv1.h +++ b/arch/arm/src/kinetis/kinetis_vrefv1.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_vrefv1.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/kinetis/kinetis_wdog.c b/arch/arm/src/kinetis/kinetis_wdog.c index 9ba49306faee5e7826c8de8b670cd27584307763..19b6b1d59b0e1608affd1cb4f9595413d1e514f3 100644 --- a/arch/arm/src/kinetis/kinetis_wdog.c +++ b/arch/arm/src/kinetis/kinetis_wdog.c @@ -1,117 +1,117 @@ -/**************************************************************************** - * arch/arm/src/kinetis/kinetis_wdog.c - * arch/arm/src/chip/kinetis_wdog.c - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "up_arch.h" -#include "kinetis_internal.h" -#include "kinetis_wdog.h" - -/**************************************************************************** - * Private Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: kinetis_wdunlock - * - * Description: - * Watchdog timer unlock routine. Writing 0xc520 followed by 0xd928 will - * unlock the write once registers in the WDOG so they are writable - * within the WCT period. - * - ****************************************************************************/ - -static void kinetis_wdunlock(void) -{ - irqstate_t flags; - - /* This sequence must execute within 20 clock cycles. Disable interrupts - * to assure that the following steps are atomic. - */ - - flags = irqsave(); - - /* Write 0xC520 followed by 0xD928 to the unlock register */ - - putreg16(0xc520, KINETIS_WDOG_UNLOCK); - putreg16(0xd928, KINETIS_WDOG_UNLOCK); - irqrestore(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: kinetis_wddisable - * - * Description: - * Disable the watchdog timer - * - ****************************************************************************/ - -void kinetis_wddisable(void) -{ - uint16_t regval; - - /* Unlock the watchdog so that we can write to registers */ - - kinetis_wdunlock(); - - /* Clear the WDOGEN bit to disable the watchdog */ - - regval = getreg16(KINETIS_WDOG_STCTRLH); - regval &= ~WDOG_STCTRLH_WDOGEN; - putreg16(regval, KINETIS_WDOG_STCTRLH); -} +/**************************************************************************** + * arch/arm/src/kinetis/kinetis_wdog.c + * arch/arm/src/chip/kinetis_wdog.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "up_arch.h" +#include "kinetis_internal.h" +#include "kinetis_wdog.h" + +/**************************************************************************** + * Private Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: kinetis_wdunlock + * + * Description: + * Watchdog timer unlock routine. Writing 0xc520 followed by 0xd928 will + * unlock the write once registers in the WDOG so they are writable + * within the WCT period. + * + ****************************************************************************/ + +static void kinetis_wdunlock(void) +{ + irqstate_t flags; + + /* This sequence must execute within 20 clock cycles. Disable interrupts + * to assure that the following steps are atomic. + */ + + flags = irqsave(); + + /* Write 0xC520 followed by 0xD928 to the unlock register */ + + putreg16(0xc520, KINETIS_WDOG_UNLOCK); + putreg16(0xd928, KINETIS_WDOG_UNLOCK); + irqrestore(flags); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: kinetis_wddisable + * + * Description: + * Disable the watchdog timer + * + ****************************************************************************/ + +void kinetis_wddisable(void) +{ + uint16_t regval; + + /* Unlock the watchdog so that we can write to registers */ + + kinetis_wdunlock(); + + /* Clear the WDOGEN bit to disable the watchdog */ + + regval = getreg16(KINETIS_WDOG_STCTRLH); + regval &= ~WDOG_STCTRLH_WDOGEN; + putreg16(regval, KINETIS_WDOG_STCTRLH); +} diff --git a/arch/arm/src/kinetis/kinetis_wdog.h b/arch/arm/src/kinetis/kinetis_wdog.h index 0432802b7ca6867ba105f7f25a56bcbb430aa58b..326c2cf628fe360fc904dc2f51ebe09008fd24ed 100644 --- a/arch/arm/src/kinetis/kinetis_wdog.h +++ b/arch/arm/src/kinetis/kinetis_wdog.h @@ -2,7 +2,7 @@ * arch/arm/src/kinetis/kinetis_wdog.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/Make.defs b/arch/arm/src/lm3s/Make.defs index 01fceaaa8b73076fa1ee6a2b7e258a25bf5e67ae..574526f181acdb84f576f7db37cc36b470655fc8 100644 --- a/arch/arm/src/lm3s/Make.defs +++ b/arch/arm/src/lm3s/Make.defs @@ -2,7 +2,7 @@ # arch/arm/src/lm3s/Make.defs # # Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/chip.h b/arch/arm/src/lm3s/chip.h index 7be4cba5166b063b073fd56d36bbbe58521e8db4..1e22f6221ca78f41b22f90f52c19cd4b2de3fe0c 100644 --- a/arch/arm/src/lm3s/chip.h +++ b/arch/arm/src/lm3s/chip.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/chip.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/lm3s_dumpgpio.c b/arch/arm/src/lm3s/lm3s_dumpgpio.c index 631fc7e8030a4748995946960d0f6686cb06b88d..334a3930f9898724e836f02da1a6f8c17e46f255 100644 --- a/arch/arm/src/lm3s/lm3s_dumpgpio.c +++ b/arch/arm/src/lm3s/lm3s_dumpgpio.c @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_dumpgpio.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/lm3s_ethernet.c b/arch/arm/src/lm3s/lm3s_ethernet.c index be38a7b26a22a59ba7fc803f9ed571ea2176314c..f7bbedb20c6b6d1900dbad1c1425f407867a2ebe 100644 --- a/arch/arm/src/lm3s/lm3s_ethernet.c +++ b/arch/arm/src/lm3s/lm3s_ethernet.c @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_ethernet.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/lm3s_flash.h b/arch/arm/src/lm3s/lm3s_flash.h index 53b0e685aada4ddc031f0266f4c915de212c98d4..83e38892147079b45875f30b150965e5b6a81f2c 100644 --- a/arch/arm/src/lm3s/lm3s_flash.h +++ b/arch/arm/src/lm3s/lm3s_flash.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_flash.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/lm3s_gpio.c b/arch/arm/src/lm3s/lm3s_gpio.c index a57b792ab2abf2e6f3e7eb71ddc01903cb561fd8..c345d113c6ca3c6086b92898f670265a056864d5 100644 --- a/arch/arm/src/lm3s/lm3s_gpio.c +++ b/arch/arm/src/lm3s/lm3s_gpio.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/lm3s_gpio.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/lm3s_gpio.h b/arch/arm/src/lm3s/lm3s_gpio.h index 4b045691300a1fb5f761e6deeae6e24eddd5e506..0666664329f56fe220377351325cd28d89e98338 100644 --- a/arch/arm/src/lm3s/lm3s_gpio.h +++ b/arch/arm/src/lm3s/lm3s_gpio.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_gpio.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/lm3s_i2c.h b/arch/arm/src/lm3s/lm3s_i2c.h index f306328e351651ad7b564c6abb5918c39c3e5dfd..a5f0567b98bb6c6ecf746720ccf7996a08e8b9cd 100644 --- a/arch/arm/src/lm3s/lm3s_i2c.h +++ b/arch/arm/src/lm3s/lm3s_i2c.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_i2c.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/lm3s_internal.h b/arch/arm/src/lm3s/lm3s_internal.h index 2ecc9c14af4d429b00b4c3f58bdd07aa5c56aa82..9bfd67a5e41113ac4272f5190f3d52493573dd5b 100644 --- a/arch/arm/src/lm3s/lm3s_internal.h +++ b/arch/arm/src/lm3s/lm3s_internal.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_internal.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/lm3s_irq.c b/arch/arm/src/lm3s/lm3s_irq.c index d129f50cf04863999ee076db88373234d76b3c4a..aa0ed6c87926e89780d2ee675d56dc1c468845a6 100644 --- a/arch/arm/src/lm3s/lm3s_irq.c +++ b/arch/arm/src/lm3s/lm3s_irq.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/lm3s_irq.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/lm3s_lowputc.c b/arch/arm/src/lm3s/lm3s_lowputc.c index 81e312cf1434107654274f039961b08d82a31e4b..69ac56a9d3e46f87998976b4784ac9ed33e22bae 100644 --- a/arch/arm/src/lm3s/lm3s_lowputc.c +++ b/arch/arm/src/lm3s/lm3s_lowputc.c @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_lowputc.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/lm3s_memorymap.h b/arch/arm/src/lm3s/lm3s_memorymap.h index 0bc420ff1fe591b5599b7c547d9b2a9b7904786f..be0d8b58d75f74cede4e054f56c7712d84a7e0b2 100644 --- a/arch/arm/src/lm3s/lm3s_memorymap.h +++ b/arch/arm/src/lm3s/lm3s_memorymap.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_memorymap.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/lm3s_ssi.c b/arch/arm/src/lm3s/lm3s_ssi.c index 3b6abab2c91870d90fba0fc1997133c55d59c8f7..c756e2b6ad30bf54156dd097cb7393c91cebb69a 100755 --- a/arch/arm/src/lm3s/lm3s_ssi.c +++ b/arch/arm/src/lm3s/lm3s_ssi.c @@ -2,7 +2,7 @@ * arch/arm/src/lm32/lm3s_ssi.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/lm3s_ssi.h b/arch/arm/src/lm3s/lm3s_ssi.h index 10832dda11166a3692d01cb5d3392031c15db93e..482dab326916db9fd5a6eec52f1cb6277bead6f8 100644 --- a/arch/arm/src/lm3s/lm3s_ssi.h +++ b/arch/arm/src/lm3s/lm3s_ssi.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_ssi.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/lm3s_syscontrol.c b/arch/arm/src/lm3s/lm3s_syscontrol.c index bd67a6ae19db1cbd46ca983b718030ccff16fd16..e26789d32fde1976e7e745b5ba2b1efffa744bc1 100644 --- a/arch/arm/src/lm3s/lm3s_syscontrol.c +++ b/arch/arm/src/lm3s/lm3s_syscontrol.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/lm3s_syscontrol.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/lm3s_syscontrol.h b/arch/arm/src/lm3s/lm3s_syscontrol.h index 773d3338f8b1c443860f583be7343f15601ea00c..c59b921c4828b4184df1063a6704e1a5ec070679 100644 --- a/arch/arm/src/lm3s/lm3s_syscontrol.h +++ b/arch/arm/src/lm3s/lm3s_syscontrol.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_syscontrol.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/lm3s_timerisr.c b/arch/arm/src/lm3s/lm3s_timerisr.c index ad5aa279deb455f89f210aadc44ef3934087c8a3..4d42af5971be88570107adb0d378f90e04184524 100644 --- a/arch/arm/src/lm3s/lm3s_timerisr.c +++ b/arch/arm/src/lm3s/lm3s_timerisr.c @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_timerisr.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/lm3s_uart.h b/arch/arm/src/lm3s/lm3s_uart.h index f807f0a2a9205b4659d663062c6f3092ec2041fa..91bfb2266a2265d006e4d751c7b0c6cd56035ab4 100644 --- a/arch/arm/src/lm3s/lm3s_uart.h +++ b/arch/arm/src/lm3s/lm3s_uart.h @@ -2,7 +2,7 @@ * arch/arm/src/lm3s/lm3s_uart.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lm3s/lm3s_vectors.S b/arch/arm/src/lm3s/lm3s_vectors.S index 518685f42e7b22c0d684f2958d4d023f88b06fc5..71db122a0d4995271ec40ae1f11d752480c593e1 100644 --- a/arch/arm/src/lm3s/lm3s_vectors.S +++ b/arch/arm/src/lm3s/lm3s_vectors.S @@ -3,7 +3,7 @@ * arch/arm/src/chip/lm3s_vectors.S * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc17xx/chip.h b/arch/arm/src/lpc17xx/chip.h index ab671cf6d3c22c035e2751819f2a4d686e0564c7..98248201756b8fa32b041e03e96a665c40ef157a 100644 --- a/arch/arm/src/lpc17xx/chip.h +++ b/arch/arm/src/lpc17xx/chip.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc17xx/chip.h * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc17xx/lpc17_clockconfig.c b/arch/arm/src/lpc17xx/lpc17_clockconfig.c index 7f41371bf89aa5097bad32f7b4eb6cd645a90375..635090e9f186ec136456d4363bc9edee17dd9d7b 100644 --- a/arch/arm/src/lpc17xx/lpc17_clockconfig.c +++ b/arch/arm/src/lpc17xx/lpc17_clockconfig.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/lpc17_clockconfig.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc17xx/lpc17_clrpend.c b/arch/arm/src/lpc17xx/lpc17_clrpend.c index d8f27e4db1e41195ef37108c0f6ff8c5f7455e4e..242f7ac4ff95700033549b52258850b9badaca36 100644 --- a/arch/arm/src/lpc17xx/lpc17_clrpend.c +++ b/arch/arm/src/lpc17xx/lpc17_clrpend.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/lpc17_clrpend.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc17xx/lpc17_dac.h b/arch/arm/src/lpc17xx/lpc17_dac.h index e1e7c1b40ca6c9f27edaf382b9abd621f2eb5c6b..a35e16eae4603dacba501d5336380e5e83900cfd 100644 --- a/arch/arm/src/lpc17xx/lpc17_dac.h +++ b/arch/arm/src/lpc17xx/lpc17_dac.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc17xx/lpc17_dac.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc17xx/lpc17_emacram.h b/arch/arm/src/lpc17xx/lpc17_emacram.h index 3561b72ba8a35af15e13f2de0239c9720c09889d..700ad7ec320af2ec6a8d17f1da426f25bab90e4f 100644 --- a/arch/arm/src/lpc17xx/lpc17_emacram.h +++ b/arch/arm/src/lpc17xx/lpc17_emacram.h @@ -1,242 +1,242 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_emacram.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Default, no-EMAC Case ************************************************************/ -/* Assume that all of AHB SRAM will be available for heap. If this is not true, then - * LPC17_BANK0_HEAPSIZE will be undefined and redefined below. - */ - -#undef LPC17_BANK0_HEAPBASE -#undef LPC17_BANK0_HEAPSIZE -#ifdef LPC17_HAVE_BANK0 -# define LPC17_BANK0_HEAPBASE LPC17_SRAM_BANK0 -# define LPC17_BANK0_HEAPSIZE LPC17_BANK0_SIZE -#endif - -/* Is networking enabled? Is the LPC17xx Ethernet device enabled? Does this chip have - * and Ethernet controlloer? Yes... then we will replace the above default definitions. - */ - -#if defined(CONFIG_NET) && defined(CONFIG_LPC17_ETHERNET) && LPC17_NETHCONTROLLERS > 0 - -/* EMAC RAM Configuration ***********************************************************/ -/* Is AHB SRAM available? */ - -#ifndef LPC17_HAVE_BANK0 -# error "AHB SRAM Bank0 is not available for EMAC RAM" -#endif - -/* Number of Tx descriptors */ - -#ifndef CONFIG_NET_NTXDESC -# define CONFIG_NET_NTXDESC 18 -#endif - -/* Number of Rx descriptors */ - -#ifndef CONFIG_NET_NRXDESC -# define CONFIG_NET_NRXDESC 18 -#endif - -/* Size of the region at the beginning of AHB SRAM 0 set set aside for the EMAC. - * This size must fit within AHB SRAM Bank 0 and also be a multiple of 32-bit - * words. - */ - -#ifndef CONFIG_NET_EMACRAM_SIZE -# define CONFIG_NET_EMACRAM_SIZE LPC17_BANK0_SIZE -#endif - -#if CONFIG_NET_EMACRAM_SIZE > LPC17_BANK0_SIZE -# error "EMAC RAM size cannot exceed the size of AHB SRAM Bank 0" -#endif - -#if (CONFIG_NET_EMACRAM_SIZE & 3) != 0 -# error "EMAC RAM size must be in multiples of 32-bit words" -#endif - -/* Determine is there is any meaningful space left at the end of AHB Bank 0 that - * could be added to the heap. - */ - -#undef LPC17_BANK0_HEAPBASE -#undef LPC17_BANK0_HEAPSIZE -#if CONFIG_NET_EMACRAM_SIZE < (LPC17_BANK0_SIZE-128) -# define LPC17_BANK0_HEAPBASE (LPC17_SRAM_BANK0 + CONFIG_NET_EMACRAM_SIZE) -# define LPC17_BANK0_HEAPSIZE (LPC17_BANK0_SIZE - CONFIG_NET_EMACRAM_SIZE) -#endif - -/* Memory at the beginning of AHB SRAM, Bank 0 is set aside for EMAC Tx and Rx - * descriptors. The position is not controllable, only the size of the region - * is controllable. - */ - -#define LPC17_EMACRAM_BASE LPC17_SRAM_BANK0 -#define LPC17_EMACRAM_SIZE CONFIG_NET_EMACRAM_SIZE - -/* Descriptor Memory Layout *********************************************************/ -/* EMAC DMA RAM and descriptor definitions. The configured number of descriptors - * will determine the organization and the size of the descriptor and status tables. - * There is a complex interaction between the maximum packet size (CONFIG_NET_BUFSIZE) - * and the number of Rx and Tx descriptors that can be suppored (CONFIG_NET_NRXDESC - * and CONFIG_NET_NTXDESC): Small buffers -> more packets. This is something that - * needs to be tuned for you system. - * - * For a 16Kb SRAM region, here is the relationship: - * - * 16384 <= ntx * (pktsize + 8 + 4) + nrx * (pktsize + 8 + 8) - * - * If ntx == nrx and pktsize == 424, then you could have - * ntx = nrx = 18. - * - * An example with all of the details: - * - * NTXDESC=18 NRXDESC=18 CONFIG_NET_EMACRAM_SIZE=16Kb CONFIG_NET_BUFSIZE=420: - * LPC17_TXDESCTAB_SIZE = 18*8 = 144 - * LPC17_TXSTATTAB_SIZE = 18*4 = 72 - * LPC17_TXTAB_SIZE = 216 - * - * LPC17_RXDESCTAB_SIZE = 16*8 = 144 - * LPC17_RXSTATTAB_SIZE = 16*8 = 144 - * LPC17_TXTAB_SIZE = 288 - * - * LPC17_DESCTAB_SIZE = 504 - * LPC17_DESC_BASE = LPC17_SRAM_BANK0 + 0x00004000 - 504 - * = LPC17_SRAM_BANK0 + 0x00003e08 - * LPC17_TXDESC_BASE = LPC17_SRAM_BANK0 + 0x00003e08 - * LPC17_TXSTAT_BASE = LPC17_SRAM_BANK0 + 0x00003e98 - * LPC17_RXDESC_BASE = LPC17_SRAM_BANK0 + 0x00003ee0 - * LPC17_RXSTAT_BASE = LPC17_SRAM_BANK0 + 0x00003f70 - * - * LPC17_PKTMEM_BASE = LPC17_SRAM_BANK0 - * LPC17_PKTMEM_SIZE = 0x00004000-504 = 0x00003e40 - * LPC17_PKTMEM_END = LPC17_SRAM_BANK0 + 0x00003e08 - - * LPC17_MAXPACKET_SIZE = ((420 + 3 + 2) & ~3) = 424 - * LPC17_NTXPKTS = 18 - * LPC17_NRXPKTS = 18 - - * LPC17_TXBUFFER_SIZE = 18 * 424 = 0x00001dd0 - * LPC17_RXBUFFER_SIZE = 18 * 424 = 0x00001dd0 - * LPC17_BUFFER_SIZE = 0x00003ba0 - - * LPC17_BUFFER_BASE = LPC17_SRAM_BANK0 - * LPC17_TXBUFFER_BASE = LPC17_SRAM_BANK0 - * LPC17_RXBUFFER_BASE = LPC17_SRAM_BANK0 + 0x00001dd0 - * LPC17_BUFFER_END = LPC17_SRAM_BANK0 + 0x00003ba0 - * - * Then the check LPC17_BUFFER_END < LPC17_PKTMEM_END passes. The amount of - * unused memory is small: 0x00003e08-0x00003ba0 or about 616 bytes -- not - * enough for two more packets. - * - * [It is also possible, with some effort, to reclaim any unused - * SRAM for the use in the heap. But that has not yet been pursued.] - */ - -#define LPC17_TXDESCTAB_SIZE (CONFIG_NET_NTXDESC*LPC17_TXDESC_SIZE) -#define LPC17_TXSTATTAB_SIZE (CONFIG_NET_NTXDESC*LPC17_TXSTAT_SIZE) -#define LPC17_TXTAB_SIZE (LPC17_TXDESCTAB_SIZE+LPC17_TXSTATTAB_SIZE) - -#define LPC17_RXDESCTAB_SIZE (CONFIG_NET_NRXDESC*LPC17_RXDESC_SIZE) -#define LPC17_RXSTATTAB_SIZE (CONFIG_NET_NRXDESC*LPC17_RXSTAT_SIZE) -#define LPC17_RXTAB_SIZE (LPC17_RXDESCTAB_SIZE+LPC17_RXSTATTAB_SIZE) - -#define LPC17_DESCTAB_SIZE (LPC17_TXTAB_SIZE+LPC17_RXTAB_SIZE) - -/* Descriptor table memory organization. Descriptor tables are packed at - * the end of AHB SRAM, Bank 0. The beginning of bank 0 is reserved for - * packet memory. - */ - -#define LPC17_DESC_BASE (LPC17_EMACRAM_BASE+LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE) -#define LPC17_TXDESC_BASE LPC17_DESC_BASE -#define LPC17_TXSTAT_BASE (LPC17_TXDESC_BASE+LPC17_TXDESCTAB_SIZE) -#define LPC17_RXDESC_BASE (LPC17_TXSTAT_BASE+LPC17_TXSTATTAB_SIZE) -#define LPC17_RXSTAT_BASE (LPC17_RXDESC_BASE + LPC17_RXDESCTAB_SIZE) - -/* Now carve up the beginning of SRAM for packet memory. The size of a - * packet buffer is related to the size of the MTU. We'll round sizes up - * to multiples of 256 bytes. - */ - -#define LPC17_PKTMEM_BASE LPC17_EMACRAM_BASE -#define LPC17_PKTMEM_SIZE (LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE) -#define LPC17_PKTMEM_END (LPC17_EMACRAM_BASE+LPC17_PKTMEM_SIZE) - -#define LPC17_MAXPACKET_SIZE ((CONFIG_NET_BUFSIZE + CONFIG_NET_GUARDSIZE + 3) & ~3) -#define LPC17_NTXPKTS CONFIG_NET_NTXDESC -#define LPC17_NRXPKTS CONFIG_NET_NRXDESC - -#define LPC17_TXBUFFER_SIZE (LPC17_NTXPKTS * LPC17_MAXPACKET_SIZE) -#define LPC17_RXBUFFER_SIZE (LPC17_NRXPKTS * LPC17_MAXPACKET_SIZE) -#define LPC17_BUFFER_SIZE (LPC17_TXBUFFER_SIZE + LPC17_RXBUFFER_SIZE) - -#define LPC17_BUFFER_BASE LPC17_PKTMEM_BASE -#define LPC17_TXBUFFER_BASE LPC17_BUFFER_BASE -#define LPC17_RXBUFFER_BASE (LPC17_TXBUFFER_BASE + LPC17_TXBUFFER_SIZE) -#define LPC17_BUFFER_END (LPC17_BUFFER_BASE + LPC17_BUFFER_SIZE) - -#if LPC17_BUFFER_END > LPC17_PKTMEM_END -# error "Packet memory overlaps descriptor tables" -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* CONFIG_NET && CONFIG_LPC17_ETHERNET && LPC17_NETHCONTROLLERS > 0*/ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_emacram.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Default, no-EMAC Case ************************************************************/ +/* Assume that all of AHB SRAM will be available for heap. If this is not true, then + * LPC17_BANK0_HEAPSIZE will be undefined and redefined below. + */ + +#undef LPC17_BANK0_HEAPBASE +#undef LPC17_BANK0_HEAPSIZE +#ifdef LPC17_HAVE_BANK0 +# define LPC17_BANK0_HEAPBASE LPC17_SRAM_BANK0 +# define LPC17_BANK0_HEAPSIZE LPC17_BANK0_SIZE +#endif + +/* Is networking enabled? Is the LPC17xx Ethernet device enabled? Does this chip have + * and Ethernet controlloer? Yes... then we will replace the above default definitions. + */ + +#if defined(CONFIG_NET) && defined(CONFIG_LPC17_ETHERNET) && LPC17_NETHCONTROLLERS > 0 + +/* EMAC RAM Configuration ***********************************************************/ +/* Is AHB SRAM available? */ + +#ifndef LPC17_HAVE_BANK0 +# error "AHB SRAM Bank0 is not available for EMAC RAM" +#endif + +/* Number of Tx descriptors */ + +#ifndef CONFIG_NET_NTXDESC +# define CONFIG_NET_NTXDESC 18 +#endif + +/* Number of Rx descriptors */ + +#ifndef CONFIG_NET_NRXDESC +# define CONFIG_NET_NRXDESC 18 +#endif + +/* Size of the region at the beginning of AHB SRAM 0 set set aside for the EMAC. + * This size must fit within AHB SRAM Bank 0 and also be a multiple of 32-bit + * words. + */ + +#ifndef CONFIG_NET_EMACRAM_SIZE +# define CONFIG_NET_EMACRAM_SIZE LPC17_BANK0_SIZE +#endif + +#if CONFIG_NET_EMACRAM_SIZE > LPC17_BANK0_SIZE +# error "EMAC RAM size cannot exceed the size of AHB SRAM Bank 0" +#endif + +#if (CONFIG_NET_EMACRAM_SIZE & 3) != 0 +# error "EMAC RAM size must be in multiples of 32-bit words" +#endif + +/* Determine is there is any meaningful space left at the end of AHB Bank 0 that + * could be added to the heap. + */ + +#undef LPC17_BANK0_HEAPBASE +#undef LPC17_BANK0_HEAPSIZE +#if CONFIG_NET_EMACRAM_SIZE < (LPC17_BANK0_SIZE-128) +# define LPC17_BANK0_HEAPBASE (LPC17_SRAM_BANK0 + CONFIG_NET_EMACRAM_SIZE) +# define LPC17_BANK0_HEAPSIZE (LPC17_BANK0_SIZE - CONFIG_NET_EMACRAM_SIZE) +#endif + +/* Memory at the beginning of AHB SRAM, Bank 0 is set aside for EMAC Tx and Rx + * descriptors. The position is not controllable, only the size of the region + * is controllable. + */ + +#define LPC17_EMACRAM_BASE LPC17_SRAM_BANK0 +#define LPC17_EMACRAM_SIZE CONFIG_NET_EMACRAM_SIZE + +/* Descriptor Memory Layout *********************************************************/ +/* EMAC DMA RAM and descriptor definitions. The configured number of descriptors + * will determine the organization and the size of the descriptor and status tables. + * There is a complex interaction between the maximum packet size (CONFIG_NET_BUFSIZE) + * and the number of Rx and Tx descriptors that can be suppored (CONFIG_NET_NRXDESC + * and CONFIG_NET_NTXDESC): Small buffers -> more packets. This is something that + * needs to be tuned for you system. + * + * For a 16Kb SRAM region, here is the relationship: + * + * 16384 <= ntx * (pktsize + 8 + 4) + nrx * (pktsize + 8 + 8) + * + * If ntx == nrx and pktsize == 424, then you could have + * ntx = nrx = 18. + * + * An example with all of the details: + * + * NTXDESC=18 NRXDESC=18 CONFIG_NET_EMACRAM_SIZE=16Kb CONFIG_NET_BUFSIZE=420: + * LPC17_TXDESCTAB_SIZE = 18*8 = 144 + * LPC17_TXSTATTAB_SIZE = 18*4 = 72 + * LPC17_TXTAB_SIZE = 216 + * + * LPC17_RXDESCTAB_SIZE = 16*8 = 144 + * LPC17_RXSTATTAB_SIZE = 16*8 = 144 + * LPC17_TXTAB_SIZE = 288 + * + * LPC17_DESCTAB_SIZE = 504 + * LPC17_DESC_BASE = LPC17_SRAM_BANK0 + 0x00004000 - 504 + * = LPC17_SRAM_BANK0 + 0x00003e08 + * LPC17_TXDESC_BASE = LPC17_SRAM_BANK0 + 0x00003e08 + * LPC17_TXSTAT_BASE = LPC17_SRAM_BANK0 + 0x00003e98 + * LPC17_RXDESC_BASE = LPC17_SRAM_BANK0 + 0x00003ee0 + * LPC17_RXSTAT_BASE = LPC17_SRAM_BANK0 + 0x00003f70 + * + * LPC17_PKTMEM_BASE = LPC17_SRAM_BANK0 + * LPC17_PKTMEM_SIZE = 0x00004000-504 = 0x00003e40 + * LPC17_PKTMEM_END = LPC17_SRAM_BANK0 + 0x00003e08 + + * LPC17_MAXPACKET_SIZE = ((420 + 3 + 2) & ~3) = 424 + * LPC17_NTXPKTS = 18 + * LPC17_NRXPKTS = 18 + + * LPC17_TXBUFFER_SIZE = 18 * 424 = 0x00001dd0 + * LPC17_RXBUFFER_SIZE = 18 * 424 = 0x00001dd0 + * LPC17_BUFFER_SIZE = 0x00003ba0 + + * LPC17_BUFFER_BASE = LPC17_SRAM_BANK0 + * LPC17_TXBUFFER_BASE = LPC17_SRAM_BANK0 + * LPC17_RXBUFFER_BASE = LPC17_SRAM_BANK0 + 0x00001dd0 + * LPC17_BUFFER_END = LPC17_SRAM_BANK0 + 0x00003ba0 + * + * Then the check LPC17_BUFFER_END < LPC17_PKTMEM_END passes. The amount of + * unused memory is small: 0x00003e08-0x00003ba0 or about 616 bytes -- not + * enough for two more packets. + * + * [It is also possible, with some effort, to reclaim any unused + * SRAM for the use in the heap. But that has not yet been pursued.] + */ + +#define LPC17_TXDESCTAB_SIZE (CONFIG_NET_NTXDESC*LPC17_TXDESC_SIZE) +#define LPC17_TXSTATTAB_SIZE (CONFIG_NET_NTXDESC*LPC17_TXSTAT_SIZE) +#define LPC17_TXTAB_SIZE (LPC17_TXDESCTAB_SIZE+LPC17_TXSTATTAB_SIZE) + +#define LPC17_RXDESCTAB_SIZE (CONFIG_NET_NRXDESC*LPC17_RXDESC_SIZE) +#define LPC17_RXSTATTAB_SIZE (CONFIG_NET_NRXDESC*LPC17_RXSTAT_SIZE) +#define LPC17_RXTAB_SIZE (LPC17_RXDESCTAB_SIZE+LPC17_RXSTATTAB_SIZE) + +#define LPC17_DESCTAB_SIZE (LPC17_TXTAB_SIZE+LPC17_RXTAB_SIZE) + +/* Descriptor table memory organization. Descriptor tables are packed at + * the end of AHB SRAM, Bank 0. The beginning of bank 0 is reserved for + * packet memory. + */ + +#define LPC17_DESC_BASE (LPC17_EMACRAM_BASE+LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE) +#define LPC17_TXDESC_BASE LPC17_DESC_BASE +#define LPC17_TXSTAT_BASE (LPC17_TXDESC_BASE+LPC17_TXDESCTAB_SIZE) +#define LPC17_RXDESC_BASE (LPC17_TXSTAT_BASE+LPC17_TXSTATTAB_SIZE) +#define LPC17_RXSTAT_BASE (LPC17_RXDESC_BASE + LPC17_RXDESCTAB_SIZE) + +/* Now carve up the beginning of SRAM for packet memory. The size of a + * packet buffer is related to the size of the MTU. We'll round sizes up + * to multiples of 256 bytes. + */ + +#define LPC17_PKTMEM_BASE LPC17_EMACRAM_BASE +#define LPC17_PKTMEM_SIZE (LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE) +#define LPC17_PKTMEM_END (LPC17_EMACRAM_BASE+LPC17_PKTMEM_SIZE) + +#define LPC17_MAXPACKET_SIZE ((CONFIG_NET_BUFSIZE + CONFIG_NET_GUARDSIZE + 3) & ~3) +#define LPC17_NTXPKTS CONFIG_NET_NTXDESC +#define LPC17_NRXPKTS CONFIG_NET_NRXDESC + +#define LPC17_TXBUFFER_SIZE (LPC17_NTXPKTS * LPC17_MAXPACKET_SIZE) +#define LPC17_RXBUFFER_SIZE (LPC17_NRXPKTS * LPC17_MAXPACKET_SIZE) +#define LPC17_BUFFER_SIZE (LPC17_TXBUFFER_SIZE + LPC17_RXBUFFER_SIZE) + +#define LPC17_BUFFER_BASE LPC17_PKTMEM_BASE +#define LPC17_TXBUFFER_BASE LPC17_BUFFER_BASE +#define LPC17_RXBUFFER_BASE (LPC17_TXBUFFER_BASE + LPC17_TXBUFFER_SIZE) +#define LPC17_BUFFER_END (LPC17_BUFFER_BASE + LPC17_BUFFER_SIZE) + +#if LPC17_BUFFER_END > LPC17_PKTMEM_END +# error "Packet memory overlaps descriptor tables" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* CONFIG_NET && CONFIG_LPC17_ETHERNET && LPC17_NETHCONTROLLERS > 0*/ +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.c b/arch/arm/src/lpc17xx/lpc17_gpdma.c index 1fb27ccc97f97efc6d952b9652e46c97bf8a71a0..f567d52c092c602c97a55f9e3e71309cf1457ccb 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpdma.c +++ b/arch/arm/src/lpc17xx/lpc17_gpdma.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc17xx/lpc17_gpdma.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.h b/arch/arm/src/lpc17xx/lpc17_gpdma.h index d4803eba5e20d0dc640662d058e6ed340e4e74d4..c0e70efa5fdea609593e9c24cf023faf59db72ff 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpdma.h +++ b/arch/arm/src/lpc17xx/lpc17_gpdma.h @@ -1,417 +1,417 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_gpdma.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_GPDMA_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_GPDMA_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -/* General registers (see also LPC17_SYSCON_DMAREQSEL_OFFSET in lpc17_syscon.h) */ - -#define LPC17_DMA_INTST_OFFSET 0x0000 /* DMA Interrupt Status Register */ -#define LPC17_DMA_INTTCST_OFFSET 0x0004 /* DMA Interrupt Terminal Count Request Status Register */ -#define LPC17_DMA_INTTCCLR_OFFSET 0x0008 /* DMA Interrupt Terminal Count Request Clear Register */ -#define LPC17_DMA_INTERRST_OFFSET 0x000c /* DMA Interrupt Error Status Register */ -#define LPC17_DMA_INTERRCLR_OFFSET 0x0010 /* DMA Interrupt Error Clear Register */ -#define LPC17_DMA_RAWINTTCST_OFFSET 0x0014 /* DMA Raw Interrupt Terminal Count Status Register */ -#define LPC17_DMA_RAWINTERRST_OFFSET 0x0018 /* DMA Raw Error Interrupt Status Register */ -#define LPC17_DMA_ENBLDCHNS_OFFSET 0x001c /* DMA Enabled Channel Register */ -#define LPC17_DMA_SOFTBREQ_OFFSET 0x0020 /* DMA Software Burst Request Register */ -#define LPC17_DMA_SOFTSREQ_OFFSET 0x0024 /* DMA Software Single Request Register */ -#define LPC17_DMA_SOFTLBREQ_OFFSET 0x0028 /* DMA Software Last Burst Request Register */ -#define LPC17_DMA_SOFTLSREQ_OFFSET 0x002c /* DMA Software Last Single Request Register */ -#define LPC17_DMA_CONFIG_OFFSET 0x0030 /* DMA Configuration Register */ -#define LPC17_DMA_SYNC_OFFSET 0x0034 /* DMA Synchronization Register */ - -/* Channel Registers */ - -#define LPC17_DMA_CHAN_OFFSET(n) (0x0100 + ((n) << 5)) /* n=0,1,...7 */ - -#define LPC17_DMACH_SRCADDR_OFFSET 0x0000 /* DMA Channel Source Address Register */ -#define LPC17_DMACH_DESTADDR_OFFSET 0x0004 /* DMA Channel Destination Address Register */ -#define LPC17_DMACH_LLI_OFFSET 0x0008 /* DMA Channel Linked List Item Register */ -#define LPC17_DMACH_CONTROL_OFFSET 0x000c /* DMA Channel Control Register */ -#define LPC17_DMACH_CONFIG_OFFSET 0x0010 /* DMA Channel Configuration Register */ - -#define LPC17_DMACH0_SRCADDR_OFFSET (0x100+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH0_DESTADDR_OFFSET (0x100+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH0_LLI_OFFSET (0x100+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH0_CONTROL_OFFSET (0x100+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH0_CONFIG_OFFSET (0x100+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH1_SRCADDR_OFFSET (0x120+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH1_DESTADDR_OFFSET (0x120+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH1_LLI_OFFSET (0x120+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH1_CONTROL_OFFSET (0x120+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH1_CONFIG_OFFSET (0x120+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH2_SRCADDR_OFFSET (0x140+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH2_DESTADDR_OFFSET (0x140+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH2_LLI_OFFSET (0x140+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH2_CONTROL_OFFSET (0x140+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH2_CONFIG_OFFSET (0x140+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH3_SRCADDR_OFFSET (0x160+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH3_DESTADDR_OFFSET (0x160+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH3_LLI_OFFSET (0x160+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH3_CONTROL_OFFSET (0x160+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH3_CONFIG_OFFSET (0x160+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH4_SRCADDR_OFFSET (0x180+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH4_DESTADDR_OFFSET (0x180+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH4_LLI_OFFSET (0x180+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH4_CONTROL_OFFSET (0x180+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH4_CONFIG_OFFSET (0x180+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH5_SRCADDR_OFFSET (0x1a0+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH5_DESTADDR_OFFSET (0x1a0+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH5_LLI_OFFSET (0x1a0+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH5_CONTROL_OFFSET (0x1a0+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH5_CONFIG_OFFSET (0x1a0+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH6_SRCADDR_OFFSET (0x1c0+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH6_DESTADDR_OFFSET (0x1c0+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH6_LLI_OFFSET (0x1c0+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH6_CONTROL_OFFSET (0x1c0+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH6_CONFIG_OFFSET (0x1c0+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH7_SRCADDR_OFFSET (0x1e0+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH7_DESTADDR_OFFSET (0x1e0+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH7_LLI_OFFSET (0x1e0+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH7_CONTROL_OFFSET (0x1e0+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH7_CONFIG_OFFSET (0x1e0+LPC17_DMACH_CONFIG_OFFSET) - -/* Register addresses ***************************************************************/ -/* General registers (see also LPC17_SYSCON_DMAREQSEL in lpc17_syscon.h) */ - -#define LPC17_DMA_INTST (LPC17_GPDMA_BASE+LPC17_DMA_INTST_OFFSET) -#define LPC17_DMA_INTTCST (LPC17_GPDMA_BASE+LPC17_DMA_INTTCST_OFFSET) -#define LPC17_DMA_INTTCCLR (LPC17_GPDMA_BASE+LPC17_DMA_INTTCCLR_OFFSET) -#define LPC17_DMA_INTERRST (LPC17_GPDMA_BASE+LPC17_DMA_INTERRST_OFFSET) -#define LPC17_DMA_INTERRCLR (LPC17_GPDMA_BASE+LPC17_DMA_INTERRCLR_OFFSET) -#define LPC17_DMA_RAWINTTCST (LPC17_GPDMA_BASE+LPC17_DMA_RAWINTTCST_OFFSET) -#define LPC17_DMA_RAWINTERRST (LPC17_GPDMA_BASE+LPC17_DMA_RAWINTERRST_OFFSET) -#define LPC17_DMA_ENBLDCHNS (LPC17_GPDMA_BASE+LPC17_DMA_ENBLDCHNS_OFFSET) -#define LPC17_DMA_SOFTBREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTBREQ_OFFSET) -#define LPC17_DMA_SOFTSREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTSREQ_OFFSET) -#define LPC17_DMA_SOFTLBREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTLBREQ_OFFSET) -#define LPC17_DMA_SOFTLSREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTLSREQ_OFFSET) -#define LPC17_DMA_CONFIG (LPC17_GPDMA_BASE+LPC17_DMA_CONFIG_OFFSET) -#define LPC17_DMA_SYNC (LPC17_GPDMA_BASE+LPC17_DMA_SYNC_OFFSET) - -/* Channel Registers */ - -#define LPC17_DMACH_BASE(n) (LPC17_GPDMA_BASE+LPC17_DMA_CHAN_OFFSET(n)) - -#define LPC17_DMACH_SRCADDR(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_SRCADDR_OFFSET) -#define LPC17_DMACH_DESTADDR(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_DESTADDR_OFFSET) -#define LPC17_DMACH_LLI(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_LLI_OFFSET) -#define LPC17_DMACH_CONTROL(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_CONTROL_OFFSET) -#define LPC17_DMACH_CONFIG(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_CONFIG_OFFSET) - -#define LPC17_DMACH0_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH0_SRCADDR_OFFSET) -#define LPC17_DMACH0_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH0_DESTADDR_OFFSET) -#define LPC17_DMACH0_LLI (LPC17_GPDMA_BASE+LPC17_DMACH0_LLI_OFFSET) -#define LPC17_DMACH0_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH0_CONTROL_OFFSET) -#define LPC17_DMACH0_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH0_CONFIG_OFFSET) - -#define LPC17_DMACH1_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH1_SRCADDR_OFFSET) -#define LPC17_DMACH1_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH1_DESTADDR_OFFSET) -#define LPC17_DMACH1_LLI (LPC17_GPDMA_BASE+LPC17_DMACH1_LLI_OFFSET) -#define LPC17_DMACH1_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH1_CONTROL_OFFSET) -#define LPC17_DMACH1_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH1_CONFIG_OFFSET) - -#define LPC17_DMACH2_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH2_SRCADDR_OFFSET) -#define LPC17_DMACH2_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH2_DESTADDR_OFFSET) -#define LPC17_DMACH2_LLI (LPC17_GPDMA_BASE+LPC17_DMACH2_LLI_OFFSET) -#define LPC17_DMACH2_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH2_CONTROL_OFFSET) -#define LPC17_DMACH2_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH2_CONFIG_OFFSET) - -#define LPC17_DMACH3_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH3_SRCADDR_OFFSET) -#define LPC17_DMACH3_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH3_DESTADDR_OFFSET) -#define LPC17_DMACH3_LLI (LPC17_GPDMA_BASE+LPC17_DMACH3_LLI_OFFSET) -#define LPC17_DMACH3_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH3_CONTROL_OFFSET) -#define LPC17_DMACH3_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH3_CONFIG_OFFSET) - -#define LPC17_DMACH4_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH4_SRCADDR_OFFSET) -#define LPC17_DMACH4_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH4_DESTADDR_OFFSET) -#define LPC17_DMACH4_LLI (LPC17_GPDMA_BASE+LPC17_DMACH4_LLI_OFFSET) -#define LPC17_DMACH4_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH4_CONTROL_OFFSET) -#define LPC17_DMACH4_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH4_CONFIG_OFFSET) - -#define LPC17_DMACH5_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH5_SRCADDR_OFFSET) -#define LPC17_DMACH5_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH5_DESTADDR_OFFSET) -#define LPC17_DMACH5_LLI (LPC17_GPDMA_BASE+LPC17_DMACH5_LLI_OFFSET) -#define LPC17_DMACH5_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH5_CONTROL_OFFSET) -#define LPC17_DMACH5_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH5_CONFIG_OFFSET) - -#define LPC17_DMACH6_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH6_SRCADDR_OFFSET) -#define LPC17_DMACH6_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH6_DESTADDR_OFFSET) -#define LPC17_DMACH6_LLI (LPC17_GPDMA_BASE+LPC17_DMACH6_LLI_OFFSET) -#define LPC17_DMACH6_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH6_CONTROL_OFFSET) -#define LPC17_DMACH6_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH6_CONFIG_OFFSET) - -#define LPC17_DMACH7_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH7_SRCADDR_OFFSET) -#define LPC17_DMACH7_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH7_DESTADDR_OFFSET) -#define LPC17_DMACH7_LLI (LPC17_GPDMA_BASE+LPC17_DMACH7_LLI_OFFSET) -#define LPC17_DMACH7_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH7_CONTROL_OFFSET) -#define LPC17_DMACH7_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH7_CONFIG_OFFSET) - -/* Register bit definitions *********************************************************/ -/* DMA request connections */ - -#define DMA_REQ_SSP0TX (0) -#define DMA_REQ_SSP0RX (1) -#define DMA_REQ_SSP1TX (2) -#define DMA_REQ_SSP1RX (3) -#define DMA_REQ_ADC (4) -#define DMA_REQ_I2SCH0 (5) -#define DMA_REQ_I2SCH1 (6) -#define DMA_REQ_DAC (7) - -#define DMA_REQ_UART0TX (8) -#define DMA_REQ_UART0RX (9) -#define DMA_REQ_UART1TX (10) -#define DMA_REQ_UART1RX (11) -#define DMA_REQ_UART2TX (12) -#define DMA_REQ_UART2RX (13) -#define DMA_REQ_UART3TX (14) -#define DMA_REQ_UART3RX (15) - -#define DMA_REQ_MAT0p0 (8) -#define DMA_REQ_MAT0p1 (9) -#define DMA_REQ_MAT1p0 (10) -#define DMA_REQ_MAT1p1 (11) -#define DMA_REQ_MAT2p0 (12) -#define DMA_REQ_MAT2p1 (13) -#define DMA_REQ_MAT3p0 (14) -#define DMA_REQ_MAT3p1 (15) - -/* General registers (see also LPC17_SYSCON_DMAREQSEL in lpc17_syscon.h) */ -/* Fach of the following registers, bits 0-7 controls DMA channels 9-7, - * respectively. Bits 8-31 are reserved. - * - * DMA Interrupt Status Register - * DMA Interrupt Terminal Count Request Status Register - * DMA Interrupt Terminal Count Request Clear Register - * DMA Interrupt Error Status Register - * DMA Interrupt Error Clear Register - * DMA Raw Interrupt Terminal Count Status Register - * DMA Raw Error Interrupt Status Register - * DMA Enabled Channel Register - */ - -#define DMACH(n) (1 << (n)) /* n=0,1,...7 */ - -/* For each of the following registers, bits 0-15 represent a set of encoded - * DMA sources. Bits 16-31 are reserved in each case. - * - * DMA Software Burst Request Register - * DMA Software Single Request Register - * DMA Software Last Burst Request Register - * DMA Software Last Single Request Register - * DMA Synchronization Register - */ - -#define DMA_REQ_SSP0TX_BIT (1 << DMA_REQ_SSP0TX) -#define DMA_REQ_SSP0RX_BIT (1 << DMA_REQ_SSP0RX) -#define DMA_REQ_SSP1TX_BIT (1 << DMA_REQ_SSP1TX) -#define DMA_REQ_SSP1RX_BIT (1 << DMA_REQ_SSP0RX) -#define DMA_REQ_ADC_BIT (1 << DMA_REQ_ADC) -#define DMA_REQ_I2SCH0_BIT (1 << DMA_REQ_I2SCH0) -#define DMA_REQ_I2SCH1_BIT (1 << DMA_REQ_I2SCH1) -#define DMA_REQ_DAC_BIT (1 << DMA_REQ_DAC) - -#define DMA_REQ_UART0TX_BIT (1 << DMA_REQ_UART0TX) -#define DMA_REQ_UART0RX_BIT (1 << DMA_REQ_UART0RX) -#define DMA_REQ_UART1TX_BIT (1 << DMA_REQ_UART1TX) -#define DMA_REQ_UART1RX_BIT (1 << DMA_REQ_UART1RX) -#define DMA_REQ_UART2TX_BIT (1 << DMA_REQ_UART2TX) -#define DMA_REQ_UART2RX_BIT (1 << DMA_REQ_UART2RX) -#define DMA_REQ_UART3TX_BIT (1 << DMA_REQ_UART3TX) -#define DMA_REQ_UART3RX_BIT (1 << DMA_REQ_UART3RX) - -#define DMA_REQ_MAT0p0_BIT (1 << DMA_REQ_MAT0p0) -#define DMA_REQ_MAT0p1_BIT (1 << DMA_REQ_MAT0p1) -#define DMA_REQ_MAT1p0_BIT (1 << DMA_REQ_MAT1p0) -#define DMA_REQ_MAT1p1_BIT (1 << DMA_REQ_MAT1p1) -#define DMA_REQ_MAT2p0_BIT (1 << DMA_REQ_MAT2p0) -#define DMA_REQ_MAT2p1_BIT (1 << DMA_REQ_MAT2p1) -#define DMA_REQ_MAT3p0_BIT (1 << DMA_REQ_MAT3p0) -#define DMA_REQ_MAT3p1_BIT (1 << DMA_REQ_MAT3p1) - -/* DMA Configuration Register */ - -#define DMA_CONFIG_E (1 << 0) /* Bit 0: DMA Controller enable */ -#define DMA_CONFIG_M (1 << 1) /* Bit 1: AHB Master endianness configuration */ - /* Bits 2-31: Reserved */ -/* Channel Registers */ - -/* DMA Channel Source Address Register (Bits 0-31: Source Address) */ -/* DMA Channel Destination Address Register Bits 0-31: Destination Address) */ -/* DMA Channel Linked List Item Register (Bits 0-31: Address of next link list - * item. Bits 0-1 must be zero. - */ - -/* DMA Channel Control Register */ - -#define DMACH_CONTROL_XFRSIZE_SHIFT (0) /* Bits 0-11: Transfer size */ -#define DMACH_CONTROL_XFRSIZE_MASK (0x0fff << DMACH_CONTROL_XFRSIZE_SHIFT) -#define DMACH_CONTROL_SBSIZE_SHIFT (12) /* Bits 12-14: Source burst size */ -#define DMACH_CONTROL_SBSIZE_MASK (7 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_1 (0 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_4 (1 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_8 (2 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_16 (3 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_32 (4 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_64 (5 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_128 (6 << DMACH_CONTROL_SBSIZE_SHIFT) -# define DMACH_CONTROL_SBSIZE_256 (7 << DMACH_CONTROL_SBSIZE_SHIFT) -#define DMACH_CONTROL_DBSIZE_SHIFT (15) /* Bits 15-17: Destination burst size */ -#define DMACH_CONTROL_DBSIZE_MASK (7 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_1 (0 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_4 (1 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_8 (2 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_16 (3 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_32 (4 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_64 (5 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_128 (6 << DMACH_CONTROL_DBSIZE_SHIFT) -# define DMACH_CONTROL_DBSIZE_256 (7 << DMACH_CONTROL_DBSIZE_SHIFT) -#define DMACH_CONTROL_SWIDTH_SHIFT (18) /* Bits 18-20: Source transfer width */ -#define DMACH_CONTROL_SWIDTH_MASK (7 << DMACH_CONTROL_SWIDTH_SHIFT) -#define DMACH_CONTROL_DWIDTH_SHIFT (21) /* Bits 21-23: Destination transfer width */ -#define DMACH_CONTROL_DWIDTH_MASK (7 << DMACH_CONTROL_DWIDTH_SHIFT) -#define DMACH_CONTROL_SI (1 << 26) /* Bit 26: Source increment */ -#define DMACH_CONTROL_DI (1 << 27) /* Bit 27: Destination increment */ -#define DMACH_CONTROL_PROT1 (1 << 28) /* Bit 28: User/priviledged mode */ -#define DMACH_CONTROL_PROT2 (1 << 29) /* Bit 29: Bufferable */ -#define DMACH_CONTROL_PROT3 (1 << 30) /* Bit 30: Cacheable */ -#define DMACH_CONTROL_I (1 << 31) /* Bit 31: Terminal count interrupt enable */ - -/* DMA Channel Configuration Register */ - - -#define DMACH_CONFIG_E (1 << 0) /* Bit 0: Channel enable */ -#define DMACH_CONFIG_SRCPER_SHIFT (1) /* Bits 1-5: Source peripheral */ -#define DMACH_CONFIG_SRCPER_MASK (31 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_SSP0TX (DMA_REQ_SSP0TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_SSP0RX (DMA_REQ_SSP0RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_SSP1TX (DMA_REQ_SSP1TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_SSP1RX (DMA_REQ_SSP0RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_ADC (DMA_REQ_ADC << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_I2SCH0 (DMA_REQ_I2SCH0 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_I2SCH1 (DMA_REQ_I2SCH1 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_DAC (DMA_REQ_DAC << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT0p0 (DMA_REQ_MAT0p0 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT0p1 (DMA_REQ_MAT0p1 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT1p0 (DMA_REQ_MAT1p0 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT1p1 (DMA_REQ_MAT1p1 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT2p0 (DMA_REQ_MAT2p0 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT2p1 (DMA_REQ_MAT2p1 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT3p0 (DMA_REQ_MAT3p0 << DMACH_CONFIG_SRCPER_SHIFT) -# define DMACH_CONFIG_SRCPER_MAT3p1 (DMA_REQ_MAT3p1 << DMACH_CONFIG_SRCPER_SHIFT) -#define DMACH_CONFIG_DSTPER_SHIFT (6) /* Bits 6-10: Source peripheral */ -#define DMACH_CONFIG_DSTPER_MASK (31 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_SSP0TX (DMA_REQ_SSP0TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_SSP0RX (DMA_REQ_SSP0RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_SSP1TX (DMA_REQ_SSP1TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_SSP1RX (DMA_REQ_SSP0RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_ADC (DMA_REQ_ADC << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_I2SCH0 (DMA_REQ_I2SCH0 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_I2SCH1 (DMA_REQ_I2SCH1 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_DAC (DMA_REQ_DAC << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT0p0 (DMA_REQ_MAT0p0 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT0p1 (DMA_REQ_MAT0p1 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT1p0 (DMA_REQ_MAT1p0 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT1p1 (DMA_REQ_MAT1p1 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT2p0 (DMA_REQ_MAT2p0 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT2p1 (DMA_REQ_MAT2p1 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT3p0 (DMA_REQ_MAT3p0 << DMACH_CONFIG_DSTPER_SHIFT) -# define DMACH_CONFIG_DSTPER_MAT3p1 (DMA_REQ_MAT3p1 << DMACH_CONFIG_DSTPER_SHIFT) -#define DMACH_CONFIG_XFRTYPE_SHIFT (11) /* Bits 11-13: Type of transfer */ -#define DMACH_CONFIG_XFRTYPE_MASK (7 << DMACH_CONFIG_XFRTYPE_SHIFT) -# define DMACH_CONFIG_XFRTYPE_M2M (0 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to memory DMA */ -# define DMACH_CONFIG_XFRTYPE_M2P (1 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to peripheral DMA */ -# define DMACH_CONFIG_XFRTYPE_P2M (2 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to memory DMA */ -# define DMACH_CONFIG_XFRTYPE_P2P (3 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to peripheral DMA */ -#define DMACH_CONFIG_IE (1 << 14) /* Bit 14: Interrupt error mask */ -#define DMACH_CONFIG_ ITC (1 << 15) /* Bit 15: Terminal count interrupt mask */ -#define DMACH_CONFIG_L (1 << 16) /* Bit 16: Lock */ -#define DMACH_CONFIG_A (1 << 17) /* Bit 17: Active */ -#define DMACH_CONFIG_H (1 << 18) /* Bit 18: Halt */ - /* Bits 19-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_GPDMA_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_gpdma.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_GPDMA_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_GPDMA_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +/* General registers (see also LPC17_SYSCON_DMAREQSEL_OFFSET in lpc17_syscon.h) */ + +#define LPC17_DMA_INTST_OFFSET 0x0000 /* DMA Interrupt Status Register */ +#define LPC17_DMA_INTTCST_OFFSET 0x0004 /* DMA Interrupt Terminal Count Request Status Register */ +#define LPC17_DMA_INTTCCLR_OFFSET 0x0008 /* DMA Interrupt Terminal Count Request Clear Register */ +#define LPC17_DMA_INTERRST_OFFSET 0x000c /* DMA Interrupt Error Status Register */ +#define LPC17_DMA_INTERRCLR_OFFSET 0x0010 /* DMA Interrupt Error Clear Register */ +#define LPC17_DMA_RAWINTTCST_OFFSET 0x0014 /* DMA Raw Interrupt Terminal Count Status Register */ +#define LPC17_DMA_RAWINTERRST_OFFSET 0x0018 /* DMA Raw Error Interrupt Status Register */ +#define LPC17_DMA_ENBLDCHNS_OFFSET 0x001c /* DMA Enabled Channel Register */ +#define LPC17_DMA_SOFTBREQ_OFFSET 0x0020 /* DMA Software Burst Request Register */ +#define LPC17_DMA_SOFTSREQ_OFFSET 0x0024 /* DMA Software Single Request Register */ +#define LPC17_DMA_SOFTLBREQ_OFFSET 0x0028 /* DMA Software Last Burst Request Register */ +#define LPC17_DMA_SOFTLSREQ_OFFSET 0x002c /* DMA Software Last Single Request Register */ +#define LPC17_DMA_CONFIG_OFFSET 0x0030 /* DMA Configuration Register */ +#define LPC17_DMA_SYNC_OFFSET 0x0034 /* DMA Synchronization Register */ + +/* Channel Registers */ + +#define LPC17_DMA_CHAN_OFFSET(n) (0x0100 + ((n) << 5)) /* n=0,1,...7 */ + +#define LPC17_DMACH_SRCADDR_OFFSET 0x0000 /* DMA Channel Source Address Register */ +#define LPC17_DMACH_DESTADDR_OFFSET 0x0004 /* DMA Channel Destination Address Register */ +#define LPC17_DMACH_LLI_OFFSET 0x0008 /* DMA Channel Linked List Item Register */ +#define LPC17_DMACH_CONTROL_OFFSET 0x000c /* DMA Channel Control Register */ +#define LPC17_DMACH_CONFIG_OFFSET 0x0010 /* DMA Channel Configuration Register */ + +#define LPC17_DMACH0_SRCADDR_OFFSET (0x100+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH0_DESTADDR_OFFSET (0x100+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH0_LLI_OFFSET (0x100+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH0_CONTROL_OFFSET (0x100+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH0_CONFIG_OFFSET (0x100+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH1_SRCADDR_OFFSET (0x120+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH1_DESTADDR_OFFSET (0x120+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH1_LLI_OFFSET (0x120+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH1_CONTROL_OFFSET (0x120+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH1_CONFIG_OFFSET (0x120+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH2_SRCADDR_OFFSET (0x140+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH2_DESTADDR_OFFSET (0x140+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH2_LLI_OFFSET (0x140+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH2_CONTROL_OFFSET (0x140+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH2_CONFIG_OFFSET (0x140+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH3_SRCADDR_OFFSET (0x160+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH3_DESTADDR_OFFSET (0x160+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH3_LLI_OFFSET (0x160+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH3_CONTROL_OFFSET (0x160+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH3_CONFIG_OFFSET (0x160+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH4_SRCADDR_OFFSET (0x180+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH4_DESTADDR_OFFSET (0x180+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH4_LLI_OFFSET (0x180+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH4_CONTROL_OFFSET (0x180+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH4_CONFIG_OFFSET (0x180+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH5_SRCADDR_OFFSET (0x1a0+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH5_DESTADDR_OFFSET (0x1a0+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH5_LLI_OFFSET (0x1a0+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH5_CONTROL_OFFSET (0x1a0+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH5_CONFIG_OFFSET (0x1a0+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH6_SRCADDR_OFFSET (0x1c0+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH6_DESTADDR_OFFSET (0x1c0+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH6_LLI_OFFSET (0x1c0+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH6_CONTROL_OFFSET (0x1c0+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH6_CONFIG_OFFSET (0x1c0+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH7_SRCADDR_OFFSET (0x1e0+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH7_DESTADDR_OFFSET (0x1e0+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH7_LLI_OFFSET (0x1e0+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH7_CONTROL_OFFSET (0x1e0+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH7_CONFIG_OFFSET (0x1e0+LPC17_DMACH_CONFIG_OFFSET) + +/* Register addresses ***************************************************************/ +/* General registers (see also LPC17_SYSCON_DMAREQSEL in lpc17_syscon.h) */ + +#define LPC17_DMA_INTST (LPC17_GPDMA_BASE+LPC17_DMA_INTST_OFFSET) +#define LPC17_DMA_INTTCST (LPC17_GPDMA_BASE+LPC17_DMA_INTTCST_OFFSET) +#define LPC17_DMA_INTTCCLR (LPC17_GPDMA_BASE+LPC17_DMA_INTTCCLR_OFFSET) +#define LPC17_DMA_INTERRST (LPC17_GPDMA_BASE+LPC17_DMA_INTERRST_OFFSET) +#define LPC17_DMA_INTERRCLR (LPC17_GPDMA_BASE+LPC17_DMA_INTERRCLR_OFFSET) +#define LPC17_DMA_RAWINTTCST (LPC17_GPDMA_BASE+LPC17_DMA_RAWINTTCST_OFFSET) +#define LPC17_DMA_RAWINTERRST (LPC17_GPDMA_BASE+LPC17_DMA_RAWINTERRST_OFFSET) +#define LPC17_DMA_ENBLDCHNS (LPC17_GPDMA_BASE+LPC17_DMA_ENBLDCHNS_OFFSET) +#define LPC17_DMA_SOFTBREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTBREQ_OFFSET) +#define LPC17_DMA_SOFTSREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTSREQ_OFFSET) +#define LPC17_DMA_SOFTLBREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTLBREQ_OFFSET) +#define LPC17_DMA_SOFTLSREQ (LPC17_GPDMA_BASE+LPC17_DMA_SOFTLSREQ_OFFSET) +#define LPC17_DMA_CONFIG (LPC17_GPDMA_BASE+LPC17_DMA_CONFIG_OFFSET) +#define LPC17_DMA_SYNC (LPC17_GPDMA_BASE+LPC17_DMA_SYNC_OFFSET) + +/* Channel Registers */ + +#define LPC17_DMACH_BASE(n) (LPC17_GPDMA_BASE+LPC17_DMA_CHAN_OFFSET(n)) + +#define LPC17_DMACH_SRCADDR(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_SRCADDR_OFFSET) +#define LPC17_DMACH_DESTADDR(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_DESTADDR_OFFSET) +#define LPC17_DMACH_LLI(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_LLI_OFFSET) +#define LPC17_DMACH_CONTROL(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_CONTROL_OFFSET) +#define LPC17_DMACH_CONFIG(n) (LPC17_DMACH_BASE(n)+LPC17_DMACH_CONFIG_OFFSET) + +#define LPC17_DMACH0_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH0_SRCADDR_OFFSET) +#define LPC17_DMACH0_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH0_DESTADDR_OFFSET) +#define LPC17_DMACH0_LLI (LPC17_GPDMA_BASE+LPC17_DMACH0_LLI_OFFSET) +#define LPC17_DMACH0_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH0_CONTROL_OFFSET) +#define LPC17_DMACH0_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH0_CONFIG_OFFSET) + +#define LPC17_DMACH1_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH1_SRCADDR_OFFSET) +#define LPC17_DMACH1_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH1_DESTADDR_OFFSET) +#define LPC17_DMACH1_LLI (LPC17_GPDMA_BASE+LPC17_DMACH1_LLI_OFFSET) +#define LPC17_DMACH1_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH1_CONTROL_OFFSET) +#define LPC17_DMACH1_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH1_CONFIG_OFFSET) + +#define LPC17_DMACH2_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH2_SRCADDR_OFFSET) +#define LPC17_DMACH2_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH2_DESTADDR_OFFSET) +#define LPC17_DMACH2_LLI (LPC17_GPDMA_BASE+LPC17_DMACH2_LLI_OFFSET) +#define LPC17_DMACH2_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH2_CONTROL_OFFSET) +#define LPC17_DMACH2_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH2_CONFIG_OFFSET) + +#define LPC17_DMACH3_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH3_SRCADDR_OFFSET) +#define LPC17_DMACH3_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH3_DESTADDR_OFFSET) +#define LPC17_DMACH3_LLI (LPC17_GPDMA_BASE+LPC17_DMACH3_LLI_OFFSET) +#define LPC17_DMACH3_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH3_CONTROL_OFFSET) +#define LPC17_DMACH3_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH3_CONFIG_OFFSET) + +#define LPC17_DMACH4_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH4_SRCADDR_OFFSET) +#define LPC17_DMACH4_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH4_DESTADDR_OFFSET) +#define LPC17_DMACH4_LLI (LPC17_GPDMA_BASE+LPC17_DMACH4_LLI_OFFSET) +#define LPC17_DMACH4_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH4_CONTROL_OFFSET) +#define LPC17_DMACH4_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH4_CONFIG_OFFSET) + +#define LPC17_DMACH5_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH5_SRCADDR_OFFSET) +#define LPC17_DMACH5_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH5_DESTADDR_OFFSET) +#define LPC17_DMACH5_LLI (LPC17_GPDMA_BASE+LPC17_DMACH5_LLI_OFFSET) +#define LPC17_DMACH5_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH5_CONTROL_OFFSET) +#define LPC17_DMACH5_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH5_CONFIG_OFFSET) + +#define LPC17_DMACH6_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH6_SRCADDR_OFFSET) +#define LPC17_DMACH6_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH6_DESTADDR_OFFSET) +#define LPC17_DMACH6_LLI (LPC17_GPDMA_BASE+LPC17_DMACH6_LLI_OFFSET) +#define LPC17_DMACH6_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH6_CONTROL_OFFSET) +#define LPC17_DMACH6_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH6_CONFIG_OFFSET) + +#define LPC17_DMACH7_SRCADDR (LPC17_GPDMA_BASE+LPC17_DMACH7_SRCADDR_OFFSET) +#define LPC17_DMACH7_DESTADDR (LPC17_GPDMA_BASE+LPC17_DMACH7_DESTADDR_OFFSET) +#define LPC17_DMACH7_LLI (LPC17_GPDMA_BASE+LPC17_DMACH7_LLI_OFFSET) +#define LPC17_DMACH7_CONTROL (LPC17_GPDMA_BASE+LPC17_DMACH7_CONTROL_OFFSET) +#define LPC17_DMACH7_CONFIG (LPC17_GPDMA_BASE+LPC17_DMACH7_CONFIG_OFFSET) + +/* Register bit definitions *********************************************************/ +/* DMA request connections */ + +#define DMA_REQ_SSP0TX (0) +#define DMA_REQ_SSP0RX (1) +#define DMA_REQ_SSP1TX (2) +#define DMA_REQ_SSP1RX (3) +#define DMA_REQ_ADC (4) +#define DMA_REQ_I2SCH0 (5) +#define DMA_REQ_I2SCH1 (6) +#define DMA_REQ_DAC (7) + +#define DMA_REQ_UART0TX (8) +#define DMA_REQ_UART0RX (9) +#define DMA_REQ_UART1TX (10) +#define DMA_REQ_UART1RX (11) +#define DMA_REQ_UART2TX (12) +#define DMA_REQ_UART2RX (13) +#define DMA_REQ_UART3TX (14) +#define DMA_REQ_UART3RX (15) + +#define DMA_REQ_MAT0p0 (8) +#define DMA_REQ_MAT0p1 (9) +#define DMA_REQ_MAT1p0 (10) +#define DMA_REQ_MAT1p1 (11) +#define DMA_REQ_MAT2p0 (12) +#define DMA_REQ_MAT2p1 (13) +#define DMA_REQ_MAT3p0 (14) +#define DMA_REQ_MAT3p1 (15) + +/* General registers (see also LPC17_SYSCON_DMAREQSEL in lpc17_syscon.h) */ +/* Fach of the following registers, bits 0-7 controls DMA channels 9-7, + * respectively. Bits 8-31 are reserved. + * + * DMA Interrupt Status Register + * DMA Interrupt Terminal Count Request Status Register + * DMA Interrupt Terminal Count Request Clear Register + * DMA Interrupt Error Status Register + * DMA Interrupt Error Clear Register + * DMA Raw Interrupt Terminal Count Status Register + * DMA Raw Error Interrupt Status Register + * DMA Enabled Channel Register + */ + +#define DMACH(n) (1 << (n)) /* n=0,1,...7 */ + +/* For each of the following registers, bits 0-15 represent a set of encoded + * DMA sources. Bits 16-31 are reserved in each case. + * + * DMA Software Burst Request Register + * DMA Software Single Request Register + * DMA Software Last Burst Request Register + * DMA Software Last Single Request Register + * DMA Synchronization Register + */ + +#define DMA_REQ_SSP0TX_BIT (1 << DMA_REQ_SSP0TX) +#define DMA_REQ_SSP0RX_BIT (1 << DMA_REQ_SSP0RX) +#define DMA_REQ_SSP1TX_BIT (1 << DMA_REQ_SSP1TX) +#define DMA_REQ_SSP1RX_BIT (1 << DMA_REQ_SSP0RX) +#define DMA_REQ_ADC_BIT (1 << DMA_REQ_ADC) +#define DMA_REQ_I2SCH0_BIT (1 << DMA_REQ_I2SCH0) +#define DMA_REQ_I2SCH1_BIT (1 << DMA_REQ_I2SCH1) +#define DMA_REQ_DAC_BIT (1 << DMA_REQ_DAC) + +#define DMA_REQ_UART0TX_BIT (1 << DMA_REQ_UART0TX) +#define DMA_REQ_UART0RX_BIT (1 << DMA_REQ_UART0RX) +#define DMA_REQ_UART1TX_BIT (1 << DMA_REQ_UART1TX) +#define DMA_REQ_UART1RX_BIT (1 << DMA_REQ_UART1RX) +#define DMA_REQ_UART2TX_BIT (1 << DMA_REQ_UART2TX) +#define DMA_REQ_UART2RX_BIT (1 << DMA_REQ_UART2RX) +#define DMA_REQ_UART3TX_BIT (1 << DMA_REQ_UART3TX) +#define DMA_REQ_UART3RX_BIT (1 << DMA_REQ_UART3RX) + +#define DMA_REQ_MAT0p0_BIT (1 << DMA_REQ_MAT0p0) +#define DMA_REQ_MAT0p1_BIT (1 << DMA_REQ_MAT0p1) +#define DMA_REQ_MAT1p0_BIT (1 << DMA_REQ_MAT1p0) +#define DMA_REQ_MAT1p1_BIT (1 << DMA_REQ_MAT1p1) +#define DMA_REQ_MAT2p0_BIT (1 << DMA_REQ_MAT2p0) +#define DMA_REQ_MAT2p1_BIT (1 << DMA_REQ_MAT2p1) +#define DMA_REQ_MAT3p0_BIT (1 << DMA_REQ_MAT3p0) +#define DMA_REQ_MAT3p1_BIT (1 << DMA_REQ_MAT3p1) + +/* DMA Configuration Register */ + +#define DMA_CONFIG_E (1 << 0) /* Bit 0: DMA Controller enable */ +#define DMA_CONFIG_M (1 << 1) /* Bit 1: AHB Master endianness configuration */ + /* Bits 2-31: Reserved */ +/* Channel Registers */ + +/* DMA Channel Source Address Register (Bits 0-31: Source Address) */ +/* DMA Channel Destination Address Register Bits 0-31: Destination Address) */ +/* DMA Channel Linked List Item Register (Bits 0-31: Address of next link list + * item. Bits 0-1 must be zero. + */ + +/* DMA Channel Control Register */ + +#define DMACH_CONTROL_XFRSIZE_SHIFT (0) /* Bits 0-11: Transfer size */ +#define DMACH_CONTROL_XFRSIZE_MASK (0x0fff << DMACH_CONTROL_XFRSIZE_SHIFT) +#define DMACH_CONTROL_SBSIZE_SHIFT (12) /* Bits 12-14: Source burst size */ +#define DMACH_CONTROL_SBSIZE_MASK (7 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_1 (0 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_4 (1 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_8 (2 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_16 (3 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_32 (4 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_64 (5 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_128 (6 << DMACH_CONTROL_SBSIZE_SHIFT) +# define DMACH_CONTROL_SBSIZE_256 (7 << DMACH_CONTROL_SBSIZE_SHIFT) +#define DMACH_CONTROL_DBSIZE_SHIFT (15) /* Bits 15-17: Destination burst size */ +#define DMACH_CONTROL_DBSIZE_MASK (7 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_1 (0 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_4 (1 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_8 (2 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_16 (3 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_32 (4 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_64 (5 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_128 (6 << DMACH_CONTROL_DBSIZE_SHIFT) +# define DMACH_CONTROL_DBSIZE_256 (7 << DMACH_CONTROL_DBSIZE_SHIFT) +#define DMACH_CONTROL_SWIDTH_SHIFT (18) /* Bits 18-20: Source transfer width */ +#define DMACH_CONTROL_SWIDTH_MASK (7 << DMACH_CONTROL_SWIDTH_SHIFT) +#define DMACH_CONTROL_DWIDTH_SHIFT (21) /* Bits 21-23: Destination transfer width */ +#define DMACH_CONTROL_DWIDTH_MASK (7 << DMACH_CONTROL_DWIDTH_SHIFT) +#define DMACH_CONTROL_SI (1 << 26) /* Bit 26: Source increment */ +#define DMACH_CONTROL_DI (1 << 27) /* Bit 27: Destination increment */ +#define DMACH_CONTROL_PROT1 (1 << 28) /* Bit 28: User/priviledged mode */ +#define DMACH_CONTROL_PROT2 (1 << 29) /* Bit 29: Bufferable */ +#define DMACH_CONTROL_PROT3 (1 << 30) /* Bit 30: Cacheable */ +#define DMACH_CONTROL_I (1 << 31) /* Bit 31: Terminal count interrupt enable */ + +/* DMA Channel Configuration Register */ + + +#define DMACH_CONFIG_E (1 << 0) /* Bit 0: Channel enable */ +#define DMACH_CONFIG_SRCPER_SHIFT (1) /* Bits 1-5: Source peripheral */ +#define DMACH_CONFIG_SRCPER_MASK (31 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP0TX (DMA_REQ_SSP0TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP0RX (DMA_REQ_SSP0RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP1TX (DMA_REQ_SSP1TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_SSP1RX (DMA_REQ_SSP0RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_ADC (DMA_REQ_ADC << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_I2SCH0 (DMA_REQ_I2SCH0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_I2SCH1 (DMA_REQ_I2SCH1 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_DAC (DMA_REQ_DAC << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT0p0 (DMA_REQ_MAT0p0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT0p1 (DMA_REQ_MAT0p1 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT1p0 (DMA_REQ_MAT1p0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT1p1 (DMA_REQ_MAT1p1 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT2p0 (DMA_REQ_MAT2p0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT2p1 (DMA_REQ_MAT2p1 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT3p0 (DMA_REQ_MAT3p0 << DMACH_CONFIG_SRCPER_SHIFT) +# define DMACH_CONFIG_SRCPER_MAT3p1 (DMA_REQ_MAT3p1 << DMACH_CONFIG_SRCPER_SHIFT) +#define DMACH_CONFIG_DSTPER_SHIFT (6) /* Bits 6-10: Source peripheral */ +#define DMACH_CONFIG_DSTPER_MASK (31 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP0TX (DMA_REQ_SSP0TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP0RX (DMA_REQ_SSP0RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP1TX (DMA_REQ_SSP1TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_SSP1RX (DMA_REQ_SSP0RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_ADC (DMA_REQ_ADC << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_I2SCH0 (DMA_REQ_I2SCH0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_I2SCH1 (DMA_REQ_I2SCH1 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_DAC (DMA_REQ_DAC << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART0TX (DMA_REQ_UART0TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART0RX (DMA_REQ_UART0RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART1TX (DMA_REQ_UART1TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART1RX (DMA_REQ_UART1RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART2TX (DMA_REQ_UART2TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART2RX (DMA_REQ_UART2RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART3TX (DMA_REQ_UART3TX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_UART3RX (DMA_REQ_UART3RX << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT0p0 (DMA_REQ_MAT0p0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT0p1 (DMA_REQ_MAT0p1 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT1p0 (DMA_REQ_MAT1p0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT1p1 (DMA_REQ_MAT1p1 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT2p0 (DMA_REQ_MAT2p0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT2p1 (DMA_REQ_MAT2p1 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT3p0 (DMA_REQ_MAT3p0 << DMACH_CONFIG_DSTPER_SHIFT) +# define DMACH_CONFIG_DSTPER_MAT3p1 (DMA_REQ_MAT3p1 << DMACH_CONFIG_DSTPER_SHIFT) +#define DMACH_CONFIG_XFRTYPE_SHIFT (11) /* Bits 11-13: Type of transfer */ +#define DMACH_CONFIG_XFRTYPE_MASK (7 << DMACH_CONFIG_XFRTYPE_SHIFT) +# define DMACH_CONFIG_XFRTYPE_M2M (0 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to memory DMA */ +# define DMACH_CONFIG_XFRTYPE_M2P (1 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Memory to peripheral DMA */ +# define DMACH_CONFIG_XFRTYPE_P2M (2 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to memory DMA */ +# define DMACH_CONFIG_XFRTYPE_P2P (3 << DMACH_CONFIG_XFRTYPE_SHIFT) /* Peripheral to peripheral DMA */ +#define DMACH_CONFIG_IE (1 << 14) /* Bit 14: Interrupt error mask */ +#define DMACH_CONFIG_ ITC (1 << 15) /* Bit 15: Terminal count interrupt mask */ +#define DMACH_CONFIG_L (1 << 16) /* Bit 16: Lock */ +#define DMACH_CONFIG_A (1 << 17) /* Bit 17: Active */ +#define DMACH_CONFIG_H (1 << 18) /* Bit 18: Halt */ + /* Bits 19-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_GPDMA_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_gpio.h b/arch/arm/src/lpc17xx/lpc17_gpio.h index 39fa161fc8ed999866393fff6cc8ad591e78f4d5..002ef3fafe0911e8160e54b611bf025ff5ad5a97 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpio.h +++ b/arch/arm/src/lpc17xx/lpc17_gpio.h @@ -1,196 +1,196 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_gpio.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ -/* GPIO block register offsets ******************************************************/ - -#define LPC17_FIO0_OFFSET 0x0000 -#define LPC17_FIO1_OFFSET 0x0020 -#define LPC17_FIO2_OFFSET 0x0040 -#define LPC17_FIO3_OFFSET 0x0060 -#define LPC17_FIO4_OFFSET 0x0080 - -#define LPC17_FIO_DIR_OFFSET 0x0000 /* Fast GPIO Port Direction control */ -#define LPC17_FIO_MASK_OFFSET 0x0010 /* Fast Mask register for ports */ -#define LPC17_FIO_PIN_OFFSET 0x0014 /* Fast Port Pin value registers */ -#define LPC17_FIO_SET_OFFSET 0x0018 /* Fast Port Output Set registers */ -#define LPC17_FIO_CLR_OFFSET 0x001c /* Fast Port Output Clear register */ - -/* GPIO interrupt block register offsets ********************************************/ - -#define LPC17_GPIOINT_OFFSET(n) (0x10*(n) + 0x80) -#define LPC17_GPIOINT0_OFFSET 0x0080 -#define LPC17_GPIOINT2_OFFSET 0x00a0 - -#define LPC17_GPIOINT_IOINTSTATUS_OFFSET 0x0000 /* GPIO overall Interrupt Status */ -#define LPC17_GPIOINT_INTSTATR_OFFSET 0x0004 /* GPIO Interrupt Status Rising edge */ -#define LPC17_GPIOINT_INTSTATF_OFFSET 0x0008 /* GPIO Interrupt Status Falling edge */ -#define LPC17_GPIOINT_INTCLR_OFFSET 0x000c /* GPIO Interrupt Clear */ -#define LPC17_GPIOINT_INTENR_OFFSET 0x0010 /* GPIO Interrupt Enable Rising edge */ -#define LPC17_GPIOINT_INTENF_OFFSET 0x0014 /* GPIO Interrupt Enable Falling edge */ - -/* Register addresses ***************************************************************/ -/* GPIO block register addresses ****************************************************/ - -#define LPC17_FIO_BASE(n) (LPC17_GPIO_BASE+LPC17_GPIOINT_OFFSET(n)) -#define LPC17_FIO0_BASE (LPC17_GPIO_BASE+LPC17_FIO0_OFFSET) -#define LPC17_FIO1_BASE (LPC17_GPIO_BASE+LPC17_FIO1_OFFSET) -#define LPC17_FIO2_BASE (LPC17_GPIO_BASE+LPC17_FIO2_OFFSET) -#define LPC17_FIO3_BASE (LPC17_GPIO_BASE+LPC17_FIO3_OFFSET) -#define LPC17_FIO4_BASE (LPC17_GPIO_BASE+LPC17_FIO4_OFFSET) - -#define LPC17_FIO_DIR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO_MASK(n) (LPC17_FIO_BASE(n)+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO_PIN(n) (LPC17_FIO_BASE(n)+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO_SET(n) (LPC17_FIO_BASE(n)+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO_CLR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_CLR_OFFSET) - -#define LPC17_FIO0_DIR (LPC17_FIO0_BASE+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO0_MASK (LPC17_FIO0_BASE+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO0_PIN (LPC17_FIO0_BASE+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO0_SET (LPC17_FIO0_BASE+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO0_CLR (LPC17_FIO0_BASE+LPC17_FIO_CLR_OFFSET) - -#define LPC17_FIO1_DIR (LPC17_FIO1_BASE+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO1_MASK (LPC17_FIO1_BASE+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO1_PIN (LPC17_FIO1_BASE+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO1_SET (LPC17_FIO1_BASE+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO1_CLR (LPC17_FIO1_BASE+LPC17_FIO_CLR_OFFSET) - -#define LPC17_FIO2_DIR (LPC17_FIO2_BASE+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO2_MASK (LPC17_FIO2_BASE+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO2_PIN (LPC17_FIO2_BASE+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO2_SET (LPC17_FIO2_BASE+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO2_CLR (LPC17_FIO2_BASE+LPC17_FIO_CLR_OFFSET) - -#define LPC17_FIO3_DIR (LPC17_FIO3_BASE+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO3_MASK (LPC17_FIO3_BASE+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO3_PIN (LPC17_FIO3_BASE+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO3_SET (LPC17_FIO3_BASE+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO3_CLR (LPC17_FIO3_BASE+LPC17_FIO_CLR_OFFSET) - -#define LPC17_FIO4_DIR (LPC17_FIO4_BASE+LPC17_FIO_DIR_OFFSET) -#define LPC17_FIO4_MASK (LPC17_FIO4_BASE+LPC17_FIO_MASK_OFFSET) -#define LPC17_FIO4_PIN (LPC17_FIO4_BASE+LPC17_FIO_PIN_OFFSET) -#define LPC17_FIO4_SET (LPC17_FIO4_BASE+LPC17_FIO_SET_OFFSET) -#define LPC17_FIO4_CLR (LPC17_FIO4_BASE+LPC17_FIO_CLR_OFFSET) - -/* GPIO interrupt block register addresses ******************************************/ - -#define LPC17_GPIOINTn_BASE(n) (LPC17_GPIOINT_BASE+LPC17_GPIOINT_OFFSET(n)) -#define LPC17_GPIOINT0_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT0_OFFSET) -#define LPC17_GPIOINT2_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT2_OFFSET) - -#define LPC17_GPIOINT_IOINTSTATUS (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_IOINTSTATUS_OFFSET) - -#define LPC17_GPIOINT_INTSTATR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATR_OFFSET) -#define LPC17_GPIOINT_INTSTATF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATF_OFFSET) -#define LPC17_GPIOINT_INTCLR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTCLR_OFFSET) -#define LPC17_GPIOINT_INTENR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENR_OFFSET) -#define LPC17_GPIOINT_INTENF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENF_OFFSET) - -/* Pins P0.0-31 (P0.12-14 nad P0.31 are reserved) */ - -#define LPC17_GPIOINT0_INTSTATR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATR_OFFSET) -#define LPC17_GPIOINT0_INTSTATF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATF_OFFSET) -#define LPC17_GPIOINT0_INTCLR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTCLR_OFFSET) -#define LPC17_GPIOINT0_INTENR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENR_OFFSET) -#define LPC17_GPIOINT0_INTENF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENF_OFFSET) - -/* Pins P2.0-13 (P0.14-31 are reserved) */ - -#define LPC17_GPIOINT2_INTSTATR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATR_OFFSET) -#define LPC17_GPIOINT2_INTSTATF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATF_OFFSET) -#define LPC17_GPIOINT2_INTCLR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTCLR_OFFSET) -#define LPC17_GPIOINT2_INTENR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENR_OFFSET) -#define LPC17_GPIOINT2_INTENF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENF_OFFSET) - -/* Register bit definitions *********************************************************/ -/* GPIO block register bit definitions **********************************************/ - -/* Fast GPIO Port Direction control registers (FIODIR) */ -/* Fast Mask register for ports (FIOMASK) */ -/* Fast Port Pin value registers using FIOMASK (FIOPIN) */ -/* Fast Port Output Set registers using FIOMASK (FIOSET) */ -/* Fast Port Output Clear register using FIOMASK (FIOCLR) */ - -#define FIO(n) (1 << (n)) /* n=0,1,..31 */ - -/* GPIO interrupt block register bit definitions ************************************/ - -/* GPIO overall Interrupt Status (IOINTSTATUS) */ -#define GPIOINT_IOINTSTATUS_P0INT (1 << 0) /* Bit 0: Port 0 GPIO interrupt pending */ - /* Bit 1: Reserved */ -#define GPIOINT_IOINTSTATUS_P2INT (1 << 2) /* Bit 2: Port 2 GPIO interrupt pending */ - /* Bits 3-31: Reserved */ - -/* GPIO Interrupt Status for Rising edge (INTSTATR) - * GPIO Interrupt Status for Falling edge (INTSTATF) - * GPIO Interrupt Clear (INTCLR) - * GPIO Interrupt Enable for Rising edge (INTENR) - * GPIO Interrupt Enable for Falling edge (INTENF) - */ - -#define GPIOINT(n) (1 << (n)) /* n=0,1,..31 */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_gpio.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* GPIO block register offsets ******************************************************/ + +#define LPC17_FIO0_OFFSET 0x0000 +#define LPC17_FIO1_OFFSET 0x0020 +#define LPC17_FIO2_OFFSET 0x0040 +#define LPC17_FIO3_OFFSET 0x0060 +#define LPC17_FIO4_OFFSET 0x0080 + +#define LPC17_FIO_DIR_OFFSET 0x0000 /* Fast GPIO Port Direction control */ +#define LPC17_FIO_MASK_OFFSET 0x0010 /* Fast Mask register for ports */ +#define LPC17_FIO_PIN_OFFSET 0x0014 /* Fast Port Pin value registers */ +#define LPC17_FIO_SET_OFFSET 0x0018 /* Fast Port Output Set registers */ +#define LPC17_FIO_CLR_OFFSET 0x001c /* Fast Port Output Clear register */ + +/* GPIO interrupt block register offsets ********************************************/ + +#define LPC17_GPIOINT_OFFSET(n) (0x10*(n) + 0x80) +#define LPC17_GPIOINT0_OFFSET 0x0080 +#define LPC17_GPIOINT2_OFFSET 0x00a0 + +#define LPC17_GPIOINT_IOINTSTATUS_OFFSET 0x0000 /* GPIO overall Interrupt Status */ +#define LPC17_GPIOINT_INTSTATR_OFFSET 0x0004 /* GPIO Interrupt Status Rising edge */ +#define LPC17_GPIOINT_INTSTATF_OFFSET 0x0008 /* GPIO Interrupt Status Falling edge */ +#define LPC17_GPIOINT_INTCLR_OFFSET 0x000c /* GPIO Interrupt Clear */ +#define LPC17_GPIOINT_INTENR_OFFSET 0x0010 /* GPIO Interrupt Enable Rising edge */ +#define LPC17_GPIOINT_INTENF_OFFSET 0x0014 /* GPIO Interrupt Enable Falling edge */ + +/* Register addresses ***************************************************************/ +/* GPIO block register addresses ****************************************************/ + +#define LPC17_FIO_BASE(n) (LPC17_GPIO_BASE+LPC17_GPIOINT_OFFSET(n)) +#define LPC17_FIO0_BASE (LPC17_GPIO_BASE+LPC17_FIO0_OFFSET) +#define LPC17_FIO1_BASE (LPC17_GPIO_BASE+LPC17_FIO1_OFFSET) +#define LPC17_FIO2_BASE (LPC17_GPIO_BASE+LPC17_FIO2_OFFSET) +#define LPC17_FIO3_BASE (LPC17_GPIO_BASE+LPC17_FIO3_OFFSET) +#define LPC17_FIO4_BASE (LPC17_GPIO_BASE+LPC17_FIO4_OFFSET) + +#define LPC17_FIO_DIR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO_MASK(n) (LPC17_FIO_BASE(n)+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO_PIN(n) (LPC17_FIO_BASE(n)+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO_SET(n) (LPC17_FIO_BASE(n)+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO_CLR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_CLR_OFFSET) + +#define LPC17_FIO0_DIR (LPC17_FIO0_BASE+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO0_MASK (LPC17_FIO0_BASE+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO0_PIN (LPC17_FIO0_BASE+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO0_SET (LPC17_FIO0_BASE+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO0_CLR (LPC17_FIO0_BASE+LPC17_FIO_CLR_OFFSET) + +#define LPC17_FIO1_DIR (LPC17_FIO1_BASE+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO1_MASK (LPC17_FIO1_BASE+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO1_PIN (LPC17_FIO1_BASE+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO1_SET (LPC17_FIO1_BASE+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO1_CLR (LPC17_FIO1_BASE+LPC17_FIO_CLR_OFFSET) + +#define LPC17_FIO2_DIR (LPC17_FIO2_BASE+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO2_MASK (LPC17_FIO2_BASE+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO2_PIN (LPC17_FIO2_BASE+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO2_SET (LPC17_FIO2_BASE+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO2_CLR (LPC17_FIO2_BASE+LPC17_FIO_CLR_OFFSET) + +#define LPC17_FIO3_DIR (LPC17_FIO3_BASE+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO3_MASK (LPC17_FIO3_BASE+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO3_PIN (LPC17_FIO3_BASE+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO3_SET (LPC17_FIO3_BASE+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO3_CLR (LPC17_FIO3_BASE+LPC17_FIO_CLR_OFFSET) + +#define LPC17_FIO4_DIR (LPC17_FIO4_BASE+LPC17_FIO_DIR_OFFSET) +#define LPC17_FIO4_MASK (LPC17_FIO4_BASE+LPC17_FIO_MASK_OFFSET) +#define LPC17_FIO4_PIN (LPC17_FIO4_BASE+LPC17_FIO_PIN_OFFSET) +#define LPC17_FIO4_SET (LPC17_FIO4_BASE+LPC17_FIO_SET_OFFSET) +#define LPC17_FIO4_CLR (LPC17_FIO4_BASE+LPC17_FIO_CLR_OFFSET) + +/* GPIO interrupt block register addresses ******************************************/ + +#define LPC17_GPIOINTn_BASE(n) (LPC17_GPIOINT_BASE+LPC17_GPIOINT_OFFSET(n)) +#define LPC17_GPIOINT0_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT0_OFFSET) +#define LPC17_GPIOINT2_BASE (LPC17_GPIOINT_BASE+LPC17_GPIOINT2_OFFSET) + +#define LPC17_GPIOINT_IOINTSTATUS (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_IOINTSTATUS_OFFSET) + +#define LPC17_GPIOINT_INTSTATR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATR_OFFSET) +#define LPC17_GPIOINT_INTSTATF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTSTATF_OFFSET) +#define LPC17_GPIOINT_INTCLR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTCLR_OFFSET) +#define LPC17_GPIOINT_INTENR(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENR_OFFSET) +#define LPC17_GPIOINT_INTENF(n) (LPC17_GPIOINTn_BASE(n)+LPC17_GPIOINT_INTENF_OFFSET) + +/* Pins P0.0-31 (P0.12-14 nad P0.31 are reserved) */ + +#define LPC17_GPIOINT0_INTSTATR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATR_OFFSET) +#define LPC17_GPIOINT0_INTSTATF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTSTATF_OFFSET) +#define LPC17_GPIOINT0_INTCLR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTCLR_OFFSET) +#define LPC17_GPIOINT0_INTENR (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENR_OFFSET) +#define LPC17_GPIOINT0_INTENF (LPC17_GPIOINT0_BASE+LPC17_GPIOINT_INTENF_OFFSET) + +/* Pins P2.0-13 (P0.14-31 are reserved) */ + +#define LPC17_GPIOINT2_INTSTATR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATR_OFFSET) +#define LPC17_GPIOINT2_INTSTATF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTSTATF_OFFSET) +#define LPC17_GPIOINT2_INTCLR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTCLR_OFFSET) +#define LPC17_GPIOINT2_INTENR (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENR_OFFSET) +#define LPC17_GPIOINT2_INTENF (LPC17_GPIOINT2_BASE+LPC17_GPIOINT_INTENF_OFFSET) + +/* Register bit definitions *********************************************************/ +/* GPIO block register bit definitions **********************************************/ + +/* Fast GPIO Port Direction control registers (FIODIR) */ +/* Fast Mask register for ports (FIOMASK) */ +/* Fast Port Pin value registers using FIOMASK (FIOPIN) */ +/* Fast Port Output Set registers using FIOMASK (FIOSET) */ +/* Fast Port Output Clear register using FIOMASK (FIOCLR) */ + +#define FIO(n) (1 << (n)) /* n=0,1,..31 */ + +/* GPIO interrupt block register bit definitions ************************************/ + +/* GPIO overall Interrupt Status (IOINTSTATUS) */ +#define GPIOINT_IOINTSTATUS_P0INT (1 << 0) /* Bit 0: Port 0 GPIO interrupt pending */ + /* Bit 1: Reserved */ +#define GPIOINT_IOINTSTATUS_P2INT (1 << 2) /* Bit 2: Port 2 GPIO interrupt pending */ + /* Bits 3-31: Reserved */ + +/* GPIO Interrupt Status for Rising edge (INTSTATR) + * GPIO Interrupt Status for Falling edge (INTSTATF) + * GPIO Interrupt Clear (INTCLR) + * GPIO Interrupt Enable for Rising edge (INTENR) + * GPIO Interrupt Enable for Falling edge (INTENF) + */ + +#define GPIOINT(n) (1 << (n)) /* n=0,1,..31 */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_i2c.c b/arch/arm/src/lpc17xx/lpc17_i2c.c index ccff276e56e804d3e19ef263d19043479e11b5d7..48d6fefce17c63a98fb80d6a55f7366ddb1dba48 100644 --- a/arch/arm/src/lpc17xx/lpc17_i2c.c +++ b/arch/arm/src/lpc17xx/lpc17_i2c.c @@ -1,545 +1,545 @@ -/******************************************************************************* - * arch/arm/src/lpc17xx/lpc17_i2c.c - * - * Copyright (C) 2011 Li Zhuoyi. All rights reserved. - * Author: Li Zhuoyi - * History: 0.1 2011-08-20 initial version - * - * Derived from arch/arm/src/lpc31xx/lpc31_i2c.c - * - * Author: David Hewson - * - * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -/******************************************************************************* - * Included Files - *******************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include "wdog.h" -#include "chip.h" -#include "up_arch.h" -#include "up_internal.h" -#include "os_internal.h" - - -#include "lpc17_internal.h" -#include "lpc17_syscon.h" -#include "lpc17_pinconn.h" -#include "lpc17_i2c.h" - -#if defined(CONFIG_LPC17_I2C0) || defined(CONFIG_LPC17_I2C1) || defined(CONFIG_LPC17_I2C2) - -#ifndef GPIO_I2C1_SCL - #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 - #define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 -#endif -#ifndef CONFIG_I2C0_FREQ - #define CONFIG_I2C0_FREQ 100000 -#endif -#ifndef CONFIG_I2C1_FREQ - #define CONFIG_I2C1_FREQ 100000 -#endif -#ifndef CONFIG_I2C2_FREQ - #define CONFIG_I2C2_FREQ 100000 -#endif - -/******************************************************************************* - * Definitions - *******************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define I2C_TIMEOUT ((20 * CLK_TCK) / 1000) /* 20 mS */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ -struct lpc17_i2cdev_s -{ - struct i2c_dev_s dev; /* Generic I2C device */ - struct i2c_msg_s msg; /* a single message for legacy read/write */ - unsigned int base; /* Base address of registers */ - uint16_t irqid; /* IRQ for this device */ - - sem_t mutex; /* Only one thread can access at a time */ - sem_t wait; /* Place to wait for state machine completion */ - volatile uint8_t state; /* State of state machine */ - WDOG_ID timeout; /* watchdog to timeout when bus hung */ - - uint16_t wrcnt; /* number of bytes sent to tx fifo */ - uint16_t rdcnt; /* number of bytes read from rx fifo */ -}; - -static struct lpc17_i2cdev_s i2cdevices[3]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ -static int i2c_start (struct lpc17_i2cdev_s *priv); -static void i2c_stop (struct lpc17_i2cdev_s *priv); -static int i2c_interrupt (int irq, FAR void *context); -static void i2c_timeout (int argc, uint32_t arg, ...); - -/**************************************************************************** - * I2C device operations - ****************************************************************************/ - -static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency); -static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits); -static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int buflen); -static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen); -static int i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count); - -struct i2c_ops_s lpc17_i2c_ops = -{ - .setfrequency = i2c_setfrequency, - .setaddress = i2c_setaddress, - .write = i2c_write, - .read = i2c_read, -#ifdef CONFIG_I2C_TRANSFER - .transfer = i2c_transfer -#endif -}; - -/******************************************************************************* - * Name: lpc17_i2c_setfrequency - * - * Description: - * Set the frequence for the next transfer - * - *******************************************************************************/ - -static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency) -{ - struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev; - - if (frequency > 100000) - { - /* asymetric per 400Khz I2C spec */ - putreg32 ( LPC17_CCLK / (83 + 47) * 47 / frequency, priv->base + LPC17_I2C_SCLH_OFFSET); - putreg32 ( LPC17_CCLK / (83 + 47) * 83 / frequency, priv->base + LPC17_I2C_SCLL_OFFSET); - } - else - { - /* 50/50 mark space ratio */ - putreg32 (LPC17_CCLK / 100 * 50 / frequency, priv->base + LPC17_I2C_SCLH_OFFSET); - putreg32 (LPC17_CCLK / 100 * 50 / frequency, priv->base + LPC17_I2C_SCLL_OFFSET); - } - - /* FIXME: This function should return the actual selected frequency */ - return frequency; -} - -/******************************************************************************* - * Name: lpc17_i2c_setaddress - * - * Description: - * Set the I2C slave address for a subsequent read/write - * - *******************************************************************************/ -static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits) -{ - struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(nbits == 7 ); - - priv->msg.addr = addr<<1; - priv->msg.flags = 0 ; - - return OK; -} - -/******************************************************************************* - * Name: lpc17_i2c_write - * - * Description: - * Send a block of data on I2C using the previously selected I2C - * frequency and slave address. - * - *******************************************************************************/ -static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int buflen) -{ - struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev; - int ret; - - DEBUGASSERT (dev != NULL); - - priv->wrcnt=0; - priv->rdcnt=0; - priv->msg.addr &= ~0x01; - priv->msg.buffer = (uint8_t*)buffer; - priv->msg.length = buflen; - - ret = i2c_start (priv); - - return ret >0 ? OK : -ETIMEDOUT; -} - -/******************************************************************************* - * Name: lpc17_i2c_read - * - * Description: - * Receive a block of data on I2C using the previously selected I2C - * frequency and slave address. - * - *******************************************************************************/ -static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen) -{ - struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev; - int ret; - - DEBUGASSERT (dev != NULL); - - priv->wrcnt=0; - priv->rdcnt=0; - priv->msg.addr |= 0x01; - priv->msg.buffer = buffer; - priv->msg.length = buflen; - - ret = i2c_start (priv); - - return ret >0 ? OK : -ETIMEDOUT; -} - -/******************************************************************************* - * Name: i2c_start - * - * Description: - * Perform a I2C transfer start - * - *******************************************************************************/ -static int i2c_start (struct lpc17_i2cdev_s *priv) -{ - int ret=-1; - sem_wait (&priv->mutex); - - putreg32(I2C_CONCLR_STAC|I2C_CONCLR_SIC,priv->base+LPC17_I2C_CONCLR_OFFSET); - putreg32(I2C_CONSET_STA,priv->base+LPC17_I2C_CONSET_OFFSET); - - wd_start (priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (uint32_t)priv); - sem_wait(&priv->wait); - wd_cancel (priv->timeout); - sem_post (&priv->mutex); - - if( priv-> state == 0x18 || priv->state == 0x28) - ret=priv->wrcnt; - else if( priv-> state == 0x50 || priv->state == 0x58) - ret=priv->rdcnt; - return ret; -} - -/******************************************************************************* - * Name: i2c_stop - * - * Description: - * Perform a I2C transfer stop - * - *******************************************************************************/ -static void i2c_stop (struct lpc17_i2cdev_s *priv) -{ - if(priv->state!=0x38) - putreg32(I2C_CONSET_STO|I2C_CONSET_AA,priv->base+LPC17_I2C_CONSET_OFFSET); - sem_post (&priv->wait); -} - -/******************************************************************************* - * Name: i2c_timeout - * - * Description: - * Watchdog timer for timeout of I2C operation - * - *******************************************************************************/ - -static void i2c_timeout (int argc, uint32_t arg, ...) -{ - struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) arg; - - irqstate_t flags = irqsave(); - priv->state = 0xff; - sem_post (&priv->wait); - irqrestore (flags); -} - -/******************************************************************************* - * Name: i2c_interrupt - * - * Description: - * The I2C Interrupt Handler - * - *******************************************************************************/ - -static int i2c_interrupt (int irq, FAR void *context) -{ - struct lpc17_i2cdev_s *priv; -#ifdef CONFIG_LPC17_I2C0 - if (irq == LPC17_IRQ_I2C0) - { - priv=&i2cdevices[0]; - } - else -#endif -#ifdef CONFIG_LPC17_I2C1 - if (irq == LPC17_IRQ_I2C1) - { - priv=&i2cdevices[1]; - } - else -#endif -#ifdef CONFIG_LPC17_I2C2 - if (irq == LPC17_IRQ_I2C2) - { - priv=&i2cdevices[2]; - } - else -#endif - { - PANIC(OSERR_INTERNAL); - } -/* - * refrence UM10360 19.10.5 - */ - uint32_t state = getreg32(priv->base+LPC17_I2C_STAT_OFFSET); - putreg32(I2C_CONCLR_SIC,priv->base+LPC17_I2C_CONCLR_OFFSET); - priv->state=state; - state &=0xf8; - switch (state) - { - case 0x00: //Bus Error - case 0x20: - case 0x30: - case 0x38: - case 0x48: - i2c_stop(priv); - break; - case 0x08: //START - case 0x10: //Repeat START - putreg32(priv->msg.addr,priv->base+LPC17_I2C_DAT_OFFSET); - putreg32(I2C_CONCLR_STAC,priv->base+LPC17_I2C_CONCLR_OFFSET); - break; - case 0x18: - priv->wrcnt=0; - putreg32(priv->msg.buffer[0],priv->base+LPC17_I2C_DAT_OFFSET); - break; - case 0x28: - priv->wrcnt++; - if(priv->wrcntmsg.length) - putreg32(priv->msg.buffer[priv->wrcnt],priv->base+LPC17_I2C_DAT_OFFSET); - else - i2c_stop(priv); - break; - case 0x40: - priv->rdcnt=-1; - putreg32(I2C_CONSET_AA,priv->base+LPC17_I2C_CONSET_OFFSET); - break; - case 0x50: - priv->rdcnt++; - if(priv->rdcntmsg.length) - priv->msg.buffer[priv->rdcnt]=getreg32(priv->base+LPC17_I2C_BUFR_OFFSET); - if(priv->rdcnt>=priv->msg.length-1) - putreg32(I2C_CONCLR_AAC|I2C_CONCLR_SIC,priv->base+LPC17_I2C_CONCLR_OFFSET); - break; - case 0x58: - i2c_stop(priv); - break; - default: - i2c_stop(priv); - break; - } - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - - -/******************************************************************************* - * Name: up_i2cinitialize - * - * Description: - * Initialise an I2C device - * - *******************************************************************************/ - -struct i2c_dev_s *up_i2cinitialize(int port) -{ - struct lpc17_i2cdev_s *priv; - - if (port>2) - { - dbg("lpc I2C Only support 0,1,2\n"); - return NULL; - } - - irqstate_t flags; - uint32_t regval; - - flags = irqsave(); - - priv= &i2cdevices[port]; -#ifdef CONFIG_LPC17_I2C0 - if (port==0) - { - priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[0]; - priv->base = LPC17_I2C0_BASE; - priv->irqid = LPC17_IRQ_I2C0; - - regval = getreg32(LPC17_SYSCON_PCONP); - regval |= SYSCON_PCONP_PCI2C0; - putreg32(regval, LPC17_SYSCON_PCONP); - - regval = getreg32(LPC17_SYSCON_PCLKSEL0); - regval &= ~SYSCON_PCLKSEL0_I2C0_MASK; - regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL0_I2C0_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL0); - - lpc17_configgpio(GPIO_I2C0_SCL); - lpc17_configgpio(GPIO_I2C0_SDA); - - putreg32 (LPC17_CCLK/CONFIG_I2C0_FREQ/2, priv->base + LPC17_I2C_SCLH_OFFSET); - putreg32 (LPC17_CCLK/CONFIG_I2C0_FREQ/2, priv->base + LPC17_I2C_SCLL_OFFSET); - - } - else -#endif -#ifdef CONFIG_LPC17_I2C1 - if(port==1) - { - priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[1]; - priv->base = LPC17_I2C1_BASE; - priv->irqid = LPC17_IRQ_I2C1; - - regval = getreg32(LPC17_SYSCON_PCONP); - regval |= SYSCON_PCONP_PCI2C1; - putreg32(regval, LPC17_SYSCON_PCONP); - - regval = getreg32(LPC17_SYSCON_PCLKSEL1); - regval &= ~SYSCON_PCLKSEL1_I2C1_MASK; - regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C1_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL1); - - lpc17_configgpio(GPIO_I2C1_SCL); - lpc17_configgpio(GPIO_I2C1_SDA); - - putreg32 (LPC17_CCLK/CONFIG_I2C1_FREQ/2, priv->base + LPC17_I2C_SCLH_OFFSET); - putreg32 (LPC17_CCLK/CONFIG_I2C1_FREQ/2, priv->base + LPC17_I2C_SCLL_OFFSET); - } - else -#endif -#ifdef CONFIG_LPC17_I2C2 - if(port==2) - { - priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[2]; - priv->base = LPC17_I2C2_BASE; - priv->irqid = LPC17_IRQ_I2C2; - - regval = getreg32(LPC17_SYSCON_PCONP); - regval |= SYSCON_PCONP_PCI2C2; - putreg32(regval, LPC17_SYSCON_PCONP); - - regval = getreg32(LPC17_SYSCON_PCLKSEL1); - regval &= ~SYSCON_PCLKSEL1_I2C2_MASK; - regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C2_SHIFT); - putreg32(regval, LPC17_SYSCON_PCLKSEL1); - - lpc17_configgpio(GPIO_I2C2_SCL); - lpc17_configgpio(GPIO_I2C2_SDA); - - putreg32 (LPC17_CCLK/CONFIG_I2C2_FREQ/2, priv->base + LPC17_I2C_SCLH_OFFSET); - putreg32 (LPC17_CCLK/CONFIG_I2C2_FREQ/2, priv->base + LPC17_I2C_SCLL_OFFSET); - } - else -#endif - { - return NULL; - } - putreg32(I2C_CONSET_I2EN,priv->base+LPC17_I2C_CONSET_OFFSET); - - sem_init (&priv->mutex, 0, 1); - sem_init (&priv->wait, 0, 0); - - /* Allocate a watchdog timer */ - priv->timeout = wd_create(); - - DEBUGASSERT(priv->timeout != 0); - - /* Attach Interrupt Handler */ - irq_attach (priv->irqid, i2c_interrupt); - - /* Enable Interrupt Handler */ - up_enable_irq(priv->irqid); - - /* Install our operations */ - priv->dev.ops = &lpc17_i2c_ops; - - return &priv->dev; -} - -/******************************************************************************* - * Name: up_i2cuninitalize - * - * Description: - * Uninitialise an I2C device - * - *******************************************************************************/ - -int up_i2cuninitialize(FAR struct i2c_dev_s * dev) -{ - struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev; - - putreg32(I2C_CONCLRT_I2ENC,priv->base+LPC17_I2C_CONCLR_OFFSET); - up_disable_irq(priv->irqid); - irq_detach (priv->irqid); - return OK; -} - -#endif +/******************************************************************************* + * arch/arm/src/lpc17xx/lpc17_i2c.c + * + * Copyright (C) 2011 Li Zhuoyi. All rights reserved. + * Author: Li Zhuoyi + * History: 0.1 2011-08-20 initial version + * + * Derived from arch/arm/src/lpc31xx/lpc31_i2c.c + * + * Author: David Hewson + * + * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +/******************************************************************************* + * Included Files + *******************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "wdog.h" +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" +#include "os_internal.h" + + +#include "lpc17_internal.h" +#include "lpc17_syscon.h" +#include "lpc17_pinconn.h" +#include "lpc17_i2c.h" + +#if defined(CONFIG_LPC17_I2C0) || defined(CONFIG_LPC17_I2C1) || defined(CONFIG_LPC17_I2C2) + +#ifndef GPIO_I2C1_SCL + #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 + #define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 +#endif +#ifndef CONFIG_I2C0_FREQ + #define CONFIG_I2C0_FREQ 100000 +#endif +#ifndef CONFIG_I2C1_FREQ + #define CONFIG_I2C1_FREQ 100000 +#endif +#ifndef CONFIG_I2C2_FREQ + #define CONFIG_I2C2_FREQ 100000 +#endif + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define I2C_TIMEOUT ((20 * CLK_TCK) / 1000) /* 20 mS */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ +struct lpc17_i2cdev_s +{ + struct i2c_dev_s dev; /* Generic I2C device */ + struct i2c_msg_s msg; /* a single message for legacy read/write */ + unsigned int base; /* Base address of registers */ + uint16_t irqid; /* IRQ for this device */ + + sem_t mutex; /* Only one thread can access at a time */ + sem_t wait; /* Place to wait for state machine completion */ + volatile uint8_t state; /* State of state machine */ + WDOG_ID timeout; /* watchdog to timeout when bus hung */ + + uint16_t wrcnt; /* number of bytes sent to tx fifo */ + uint16_t rdcnt; /* number of bytes read from rx fifo */ +}; + +static struct lpc17_i2cdev_s i2cdevices[3]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ +static int i2c_start (struct lpc17_i2cdev_s *priv); +static void i2c_stop (struct lpc17_i2cdev_s *priv); +static int i2c_interrupt (int irq, FAR void *context); +static void i2c_timeout (int argc, uint32_t arg, ...); + +/**************************************************************************** + * I2C device operations + ****************************************************************************/ + +static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency); +static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits); +static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int buflen); +static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen); +static int i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count); + +struct i2c_ops_s lpc17_i2c_ops = +{ + .setfrequency = i2c_setfrequency, + .setaddress = i2c_setaddress, + .write = i2c_write, + .read = i2c_read, +#ifdef CONFIG_I2C_TRANSFER + .transfer = i2c_transfer +#endif +}; + +/******************************************************************************* + * Name: lpc17_i2c_setfrequency + * + * Description: + * Set the frequence for the next transfer + * + *******************************************************************************/ + +static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency) +{ + struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev; + + if (frequency > 100000) + { + /* asymetric per 400Khz I2C spec */ + putreg32 ( LPC17_CCLK / (83 + 47) * 47 / frequency, priv->base + LPC17_I2C_SCLH_OFFSET); + putreg32 ( LPC17_CCLK / (83 + 47) * 83 / frequency, priv->base + LPC17_I2C_SCLL_OFFSET); + } + else + { + /* 50/50 mark space ratio */ + putreg32 (LPC17_CCLK / 100 * 50 / frequency, priv->base + LPC17_I2C_SCLH_OFFSET); + putreg32 (LPC17_CCLK / 100 * 50 / frequency, priv->base + LPC17_I2C_SCLL_OFFSET); + } + + /* FIXME: This function should return the actual selected frequency */ + return frequency; +} + +/******************************************************************************* + * Name: lpc17_i2c_setaddress + * + * Description: + * Set the I2C slave address for a subsequent read/write + * + *******************************************************************************/ +static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits) +{ + struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev; + + DEBUGASSERT(dev != NULL); + DEBUGASSERT(nbits == 7 ); + + priv->msg.addr = addr<<1; + priv->msg.flags = 0 ; + + return OK; +} + +/******************************************************************************* + * Name: lpc17_i2c_write + * + * Description: + * Send a block of data on I2C using the previously selected I2C + * frequency and slave address. + * + *******************************************************************************/ +static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int buflen) +{ + struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev; + int ret; + + DEBUGASSERT (dev != NULL); + + priv->wrcnt=0; + priv->rdcnt=0; + priv->msg.addr &= ~0x01; + priv->msg.buffer = (uint8_t*)buffer; + priv->msg.length = buflen; + + ret = i2c_start (priv); + + return ret >0 ? OK : -ETIMEDOUT; +} + +/******************************************************************************* + * Name: lpc17_i2c_read + * + * Description: + * Receive a block of data on I2C using the previously selected I2C + * frequency and slave address. + * + *******************************************************************************/ +static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen) +{ + struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev; + int ret; + + DEBUGASSERT (dev != NULL); + + priv->wrcnt=0; + priv->rdcnt=0; + priv->msg.addr |= 0x01; + priv->msg.buffer = buffer; + priv->msg.length = buflen; + + ret = i2c_start (priv); + + return ret >0 ? OK : -ETIMEDOUT; +} + +/******************************************************************************* + * Name: i2c_start + * + * Description: + * Perform a I2C transfer start + * + *******************************************************************************/ +static int i2c_start (struct lpc17_i2cdev_s *priv) +{ + int ret=-1; + sem_wait (&priv->mutex); + + putreg32(I2C_CONCLR_STAC|I2C_CONCLR_SIC,priv->base+LPC17_I2C_CONCLR_OFFSET); + putreg32(I2C_CONSET_STA,priv->base+LPC17_I2C_CONSET_OFFSET); + + wd_start (priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (uint32_t)priv); + sem_wait(&priv->wait); + wd_cancel (priv->timeout); + sem_post (&priv->mutex); + + if( priv-> state == 0x18 || priv->state == 0x28) + ret=priv->wrcnt; + else if( priv-> state == 0x50 || priv->state == 0x58) + ret=priv->rdcnt; + return ret; +} + +/******************************************************************************* + * Name: i2c_stop + * + * Description: + * Perform a I2C transfer stop + * + *******************************************************************************/ +static void i2c_stop (struct lpc17_i2cdev_s *priv) +{ + if(priv->state!=0x38) + putreg32(I2C_CONSET_STO|I2C_CONSET_AA,priv->base+LPC17_I2C_CONSET_OFFSET); + sem_post (&priv->wait); +} + +/******************************************************************************* + * Name: i2c_timeout + * + * Description: + * Watchdog timer for timeout of I2C operation + * + *******************************************************************************/ + +static void i2c_timeout (int argc, uint32_t arg, ...) +{ + struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) arg; + + irqstate_t flags = irqsave(); + priv->state = 0xff; + sem_post (&priv->wait); + irqrestore (flags); +} + +/******************************************************************************* + * Name: i2c_interrupt + * + * Description: + * The I2C Interrupt Handler + * + *******************************************************************************/ + +static int i2c_interrupt (int irq, FAR void *context) +{ + struct lpc17_i2cdev_s *priv; +#ifdef CONFIG_LPC17_I2C0 + if (irq == LPC17_IRQ_I2C0) + { + priv=&i2cdevices[0]; + } + else +#endif +#ifdef CONFIG_LPC17_I2C1 + if (irq == LPC17_IRQ_I2C1) + { + priv=&i2cdevices[1]; + } + else +#endif +#ifdef CONFIG_LPC17_I2C2 + if (irq == LPC17_IRQ_I2C2) + { + priv=&i2cdevices[2]; + } + else +#endif + { + PANIC(OSERR_INTERNAL); + } +/* + * refrence UM10360 19.10.5 + */ + uint32_t state = getreg32(priv->base+LPC17_I2C_STAT_OFFSET); + putreg32(I2C_CONCLR_SIC,priv->base+LPC17_I2C_CONCLR_OFFSET); + priv->state=state; + state &=0xf8; + switch (state) + { + case 0x00: //Bus Error + case 0x20: + case 0x30: + case 0x38: + case 0x48: + i2c_stop(priv); + break; + case 0x08: //START + case 0x10: //Repeat START + putreg32(priv->msg.addr,priv->base+LPC17_I2C_DAT_OFFSET); + putreg32(I2C_CONCLR_STAC,priv->base+LPC17_I2C_CONCLR_OFFSET); + break; + case 0x18: + priv->wrcnt=0; + putreg32(priv->msg.buffer[0],priv->base+LPC17_I2C_DAT_OFFSET); + break; + case 0x28: + priv->wrcnt++; + if(priv->wrcntmsg.length) + putreg32(priv->msg.buffer[priv->wrcnt],priv->base+LPC17_I2C_DAT_OFFSET); + else + i2c_stop(priv); + break; + case 0x40: + priv->rdcnt=-1; + putreg32(I2C_CONSET_AA,priv->base+LPC17_I2C_CONSET_OFFSET); + break; + case 0x50: + priv->rdcnt++; + if(priv->rdcntmsg.length) + priv->msg.buffer[priv->rdcnt]=getreg32(priv->base+LPC17_I2C_BUFR_OFFSET); + if(priv->rdcnt>=priv->msg.length-1) + putreg32(I2C_CONCLR_AAC|I2C_CONCLR_SIC,priv->base+LPC17_I2C_CONCLR_OFFSET); + break; + case 0x58: + i2c_stop(priv); + break; + default: + i2c_stop(priv); + break; + } + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + + +/******************************************************************************* + * Name: up_i2cinitialize + * + * Description: + * Initialise an I2C device + * + *******************************************************************************/ + +struct i2c_dev_s *up_i2cinitialize(int port) +{ + struct lpc17_i2cdev_s *priv; + + if (port>2) + { + dbg("lpc I2C Only support 0,1,2\n"); + return NULL; + } + + irqstate_t flags; + uint32_t regval; + + flags = irqsave(); + + priv= &i2cdevices[port]; +#ifdef CONFIG_LPC17_I2C0 + if (port==0) + { + priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[0]; + priv->base = LPC17_I2C0_BASE; + priv->irqid = LPC17_IRQ_I2C0; + + regval = getreg32(LPC17_SYSCON_PCONP); + regval |= SYSCON_PCONP_PCI2C0; + putreg32(regval, LPC17_SYSCON_PCONP); + + regval = getreg32(LPC17_SYSCON_PCLKSEL0); + regval &= ~SYSCON_PCLKSEL0_I2C0_MASK; + regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL0_I2C0_SHIFT); + putreg32(regval, LPC17_SYSCON_PCLKSEL0); + + lpc17_configgpio(GPIO_I2C0_SCL); + lpc17_configgpio(GPIO_I2C0_SDA); + + putreg32 (LPC17_CCLK/CONFIG_I2C0_FREQ/2, priv->base + LPC17_I2C_SCLH_OFFSET); + putreg32 (LPC17_CCLK/CONFIG_I2C0_FREQ/2, priv->base + LPC17_I2C_SCLL_OFFSET); + + } + else +#endif +#ifdef CONFIG_LPC17_I2C1 + if(port==1) + { + priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[1]; + priv->base = LPC17_I2C1_BASE; + priv->irqid = LPC17_IRQ_I2C1; + + regval = getreg32(LPC17_SYSCON_PCONP); + regval |= SYSCON_PCONP_PCI2C1; + putreg32(regval, LPC17_SYSCON_PCONP); + + regval = getreg32(LPC17_SYSCON_PCLKSEL1); + regval &= ~SYSCON_PCLKSEL1_I2C1_MASK; + regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C1_SHIFT); + putreg32(regval, LPC17_SYSCON_PCLKSEL1); + + lpc17_configgpio(GPIO_I2C1_SCL); + lpc17_configgpio(GPIO_I2C1_SDA); + + putreg32 (LPC17_CCLK/CONFIG_I2C1_FREQ/2, priv->base + LPC17_I2C_SCLH_OFFSET); + putreg32 (LPC17_CCLK/CONFIG_I2C1_FREQ/2, priv->base + LPC17_I2C_SCLL_OFFSET); + } + else +#endif +#ifdef CONFIG_LPC17_I2C2 + if(port==2) + { + priv= (FAR struct lpc17_i2cdev_s *)&i2cdevices[2]; + priv->base = LPC17_I2C2_BASE; + priv->irqid = LPC17_IRQ_I2C2; + + regval = getreg32(LPC17_SYSCON_PCONP); + regval |= SYSCON_PCONP_PCI2C2; + putreg32(regval, LPC17_SYSCON_PCONP); + + regval = getreg32(LPC17_SYSCON_PCLKSEL1); + regval &= ~SYSCON_PCLKSEL1_I2C2_MASK; + regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C2_SHIFT); + putreg32(regval, LPC17_SYSCON_PCLKSEL1); + + lpc17_configgpio(GPIO_I2C2_SCL); + lpc17_configgpio(GPIO_I2C2_SDA); + + putreg32 (LPC17_CCLK/CONFIG_I2C2_FREQ/2, priv->base + LPC17_I2C_SCLH_OFFSET); + putreg32 (LPC17_CCLK/CONFIG_I2C2_FREQ/2, priv->base + LPC17_I2C_SCLL_OFFSET); + } + else +#endif + { + return NULL; + } + putreg32(I2C_CONSET_I2EN,priv->base+LPC17_I2C_CONSET_OFFSET); + + sem_init (&priv->mutex, 0, 1); + sem_init (&priv->wait, 0, 0); + + /* Allocate a watchdog timer */ + priv->timeout = wd_create(); + + DEBUGASSERT(priv->timeout != 0); + + /* Attach Interrupt Handler */ + irq_attach (priv->irqid, i2c_interrupt); + + /* Enable Interrupt Handler */ + up_enable_irq(priv->irqid); + + /* Install our operations */ + priv->dev.ops = &lpc17_i2c_ops; + + return &priv->dev; +} + +/******************************************************************************* + * Name: up_i2cuninitalize + * + * Description: + * Uninitialise an I2C device + * + *******************************************************************************/ + +int up_i2cuninitialize(FAR struct i2c_dev_s * dev) +{ + struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev; + + putreg32(I2C_CONCLRT_I2ENC,priv->base+LPC17_I2C_CONCLR_OFFSET); + up_disable_irq(priv->irqid); + irq_detach (priv->irqid); + return OK; +} + +#endif diff --git a/arch/arm/src/lpc17xx/lpc17_i2c.h b/arch/arm/src/lpc17xx/lpc17_i2c.h index f8e098959f65a6d599ac470aa264d11b749454c3..10e1fbeac61e19be9ef282646ab386ca79426e57 100644 --- a/arch/arm/src/lpc17xx/lpc17_i2c.h +++ b/arch/arm/src/lpc17xx/lpc17_i2c.h @@ -1,208 +1,208 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_i2c.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_I2C_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_I2C_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_I2C_CONSET_OFFSET 0x0000 /* I2C Control Set Register */ -#define LPC17_I2C_STAT_OFFSET 0x0004 /* I2C Status Register */ -#define LPC17_I2C_DAT_OFFSET 0x0008 /* I2C Data Register */ -#define LPC17_I2C_ADR0_OFFSET 0x000c /* I2C Slave Address Register 0 */ -#define LPC17_I2C_SCLH_OFFSET 0x0010 /* SCH Duty Cycle Register High Half Word */ -#define LPC17_I2C_SCLL_OFFSET 0x0014 /* SCL Duty Cycle Register Low Half Word */ -#define LPC17_I2C_CONCLR_OFFSET 0x0018 /* I2C Control Clear Register */ -#define LPC17_I2C_MMCTRL_OFFSET 0x001c /* Monitor mode control register */ -#define LPC17_I2C_ADR1_OFFSET 0x0020 /* I2C Slave Address Register 1 */ -#define LPC17_I2C_ADR2_OFFSET 0x0024 /* I2C Slave Address Register 2 */ -#define LPC17_I2C_ADR3_OFFSET 0x0028 /* I2C Slave Address Register 3 */ -#define LPC17_I2C_BUFR_OFFSET 0x002c /* Data buffer register */ -#define LPC17_I2C_MASK0_OFFSET 0x0030 /* I2C Slave address mask register 0 */ -#define LPC17_I2C_MASK1_OFFSET 0x0034 /* I2C Slave address mask register 1 */ -#define LPC17_I2C_MASK2_OFFSET 0x0038 /* I2C Slave address mask register 2 */ -#define LPC17_I2C_MASK3_OFFSET 0x003c /* I2C Slave address mask register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_I2C0_CONSET (LPC17_I2C0_BASE+LPC17_I2C_CONSET_OFFSET) -#define LPC17_I2C0_STAT (LPC17_I2C0_BASE+LPC17_I2C_STAT_OFFSET) -#define LPC17_I2C0_DAT (LPC17_I2C0_BASE+LPC17_I2C_DAT_OFFSET) -#define LPC17_I2C0_ADR0 (LPC17_I2C0_BASE+LPC17_I2C_ADR0_OFFSET) -#define LPC17_I2C0_SCLH (LPC17_I2C0_BASE+LPC17_I2C_SCLH_OFFSET) -#define LPC17_I2C0_SCLL (LPC17_I2C0_BASE+LPC17_I2C_SCLL_OFFSET) -#define LPC17_I2C0_CONCLR (LPC17_I2C0_BASE+LPC17_I2C_CONCLR_OFFSET) -#define LPC17_I2C0_MMCTRL (LPC17_I2C0_BASE+LPC17_I2C_MMCTRL_OFFSET) -#define LPC17_I2C0_ADR1 (LPC17_I2C0_BASE+LPC17_I2C_ADR1_OFFSET) -#define LPC17_I2C0_ADR2 (LPC17_I2C0_BASE+LPC17_I2C_ADR2_OFFSET) -#define LPC17_I2C0_ADR3 (LPC17_I2C0_BASE+LPC17_I2C_ADR3_OFFSET) -#define LPC17_I2C0_BUFR (LPC17_I2C0_BASE+LPC17_I2C_BUFR_OFFSET) -#define LPC17_I2C0_MASK0 (LPC17_I2C0_BASE+LPC17_I2C_MASK0_OFFSET) -#define LPC17_I2C0_MASK1 (LPC17_I2C0_BASE+LPC17_I2C_MASK1_OFFSET) -#define LPC17_I2C0_MASK2 (LPC17_I2C0_BASE+LPC17_I2C_MASK2_OFFSET) -#define LPC17_I2C0_MASK3 (LPC17_I2C0_BASE+LPC17_I2C_MASK3_OFFSET) - -#define LPC17_I2C1_CONSET (LPC17_I2C1_BASE+LPC17_I2C_CONSET_OFFSET) -#define LPC17_I2C1_STAT (LPC17_I2C1_BASE+LPC17_I2C_STAT_OFFSET) -#define LPC17_I2C1_DAT (LPC17_I2C1_BASE+LPC17_I2C_DAT_OFFSET) -#define LPC17_I2C1_ADR0 (LPC17_I2C1_BASE+LPC17_I2C_ADR0_OFFSET) -#define LPC17_I2C1_SCLH (LPC17_I2C1_BASE+LPC17_I2C_SCLH_OFFSET) -#define LPC17_I2C1_SCLL (LPC17_I2C1_BASE+LPC17_I2C_SCLL_OFFSET) -#define LPC17_I2C1_CONCLR (LPC17_I2C1_BASE+LPC17_I2C_CONCLR_OFFSET) -#define LPC17_I2C1_MMCTRL (LPC17_I2C1_BASE+LPC17_I2C_MMCTRL_OFFSET) -#define LPC17_I2C1_ADR1 (LPC17_I2C1_BASE+LPC17_I2C_ADR1_OFFSET) -#define LPC17_I2C1_ADR2 (LPC17_I2C1_BASE+LPC17_I2C_ADR2_OFFSET) -#define LPC17_I2C1_ADR3 (LPC17_I2C1_BASE+LPC17_I2C_ADR3_OFFSET) -#define LPC17_I2C1_BUFR (LPC17_I2C1_BASE+LPC17_I2C_BUFR_OFFSET) -#define LPC17_I2C1_MASK0 (LPC17_I2C1_BASE+LPC17_I2C_MASK0_OFFSET) -#define LPC17_I2C1_MASK1 (LPC17_I2C1_BASE+LPC17_I2C_MASK1_OFFSET) -#define LPC17_I2C1_MASK2 (LPC17_I2C1_BASE+LPC17_I2C_MASK2_OFFSET) -#define LPC17_I2C1_MASK3 (LPC17_I2C1_BASE+LPC17_I2C_MASK3_OFFSET) - -#define LPC17_I2C2_CONSET (LPC17_I2C2_BASE+LPC17_I2C_CONSET_OFFSET) -#define LPC17_I2C2_STAT (LPC17_I2C2_BASE+LPC17_I2C_STAT_OFFSET) -#define LPC17_I2C2_DAT (LPC17_I2C2_BASE+LPC17_I2C_DAT_OFFSET) -#define LPC17_I2C2_ADR0 (LPC17_I2C2_BASE+LPC17_I2C_ADR0_OFFSET) -#define LPC17_I2C2_SCLH (LPC17_I2C2_BASE+LPC17_I2C_SCLH_OFFSET) -#define LPC17_I2C2_SCLL (LPC17_I2C2_BASE+LPC17_I2C_SCLL_OFFSET) -#define LPC17_I2C2_CONCLR (LPC17_I2C2_BASE+LPC17_I2C_CONCLR_OFFSET) -#define LPC17_I2C2_MMCTRL (LPC17_I2C2_BASE+LPC17_I2C_MMCTRL_OFFSET) -#define LPC17_I2C2_ADR1 (LPC17_I2C2_BASE+LPC17_I2C_ADR1_OFFSET) -#define LPC17_I2C2_ADR2 (LPC17_I2C2_BASE+LPC17_I2C_ADR2_OFFSET) -#define LPC17_I2C2_ADR3 (LPC17_I2C2_BASE+LPC17_I2C_ADR3_OFFSET) -#define LPC17_I2C2_BUFR (LPC17_I2C2_BASE+LPC17_I2C_BUFR_OFFSET) -#define LPC17_I2C2_MASK0 (LPC17_I2C2_BASE+LPC17_I2C_MASK0_OFFSET) -#define LPC17_I2C2_MASK1 (LPC17_I2C2_BASE+LPC17_I2C_MASK1_OFFSET) -#define LPC17_I2C2_MASK2 (LPC17_I2C2_BASE+LPC17_I2C_MASK2_OFFSET) -#define LPC17_I2C2_MASK3 (LPC17_I2C2_BASE+LPC17_I2C_MASK3_OFFSET) - -/* Register bit definitions *********************************************************/ -/* I2C Control Set Register */ - /* Bits 0-1: Reserved */ -#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */ -#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */ -#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */ -#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */ -#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */ - /* Bits 7-31: Reserved */ -/* I2C Control Clear Register */ - /* Bits 0-1: Reserved */ -#define I2C_CONCLR_AAC (1 << 2) /* Bit 2: Assert acknowledge Clear bit */ -#define I2C_CONCLR_SIC (1 << 3) /* Bit 3: I2C interrupt Clear bit */ - /* Bit 4: Reserved */ -#define I2C_CONCLR_STAC (1 << 5) /* Bit 5: START flag Clear bit */ -#define I2C_CONCLRT_I2ENC (1 << 6) /* Bit 6: I2C interface Disable bit */ - /* Bits 7-31: Reserved */ -/* I2C Status Register - * - * See tables 399-402 in the "LPC17xx User Manual" (UM10360), Rev. 01, 4 January - * 2010, NXP for definitions of status codes. - */ - -#define I2C_STAT_MASK (0xff) /* Bits 0-7: I2C interface status - * Bits 0-1 always zero */ - /* Bits 8-31: Reserved */ -/* I2C Data Register */ - -#define I2C_DAT_MASK (0xff) /* Bits 0-7: I2C data */ - /* Bits 8-31: Reserved */ -/* Monitor mode control register */ - -#define I2C_MMCTRL_MMENA (1 << 0) /* Bit 0: Monitor mode enable */ -#define I2C_MMCTRL_ENASCL (1 << 1) /* Bit 1: SCL output enable */ -#define I2C_MMCTRL_MATCHALL (1 << 2) /* Bit 2: Select interrupt register match */ - /* Bits 3-31: Reserved */ -/* Data buffer register */ - -#define I2C_BUFR_MASK (0xff) /* Bits 0-7: 8 MSBs of the I2DAT shift register */ - /* Bits 8-31: Reserved */ -/* I2C Slave address registers: - * - * I2C Slave Address Register 0 - * I2C Slave Address Register 1 - * I2C Slave Address Register 2 - * I2C Slave Address Register 3 - */ - -#define I2C_ADR_GC (1 << 0) /* Bit 0: GC General Call enable bit */ -#define I2C_ADR_ADDR_SHIFT (1) /* Bits 1-7: I2C slave address */ -#define I2C_ADR_ADDR_MASK (0x7f << I2C_ADR_ADDR_SHIFT) - /* Bits 8-31: Reserved */ -/* I2C Slave address mask registers: - * - * I2C Slave address mask register 0 - * I2C Slave address mask register 1 - * I2C Slave address mask register 2 - * I2C Slave address mask register 3 - */ - /* Bit 0: Reserved */ -#define I2C_MASK_SHIFT (1) /* Bits 1-7: I2C mask bits */ -#define I2C_MASK_MASK (0x7f << I2C_ADR_ADDR_SHIFT) - /* Bits 8-31: Reserved */ -/* SCH Duty Cycle Register High Half Word */ - -#define I2C_SCLH_MASK (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */ - /* Bits 16-31: Reserved */ -/* SCL Duty Cycle Register Low Half Word */ - -#define I2C_SCLL_MASK (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */ - /* Bits 16-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_I2C_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_i2c.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_I2C_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_I2C_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_I2C_CONSET_OFFSET 0x0000 /* I2C Control Set Register */ +#define LPC17_I2C_STAT_OFFSET 0x0004 /* I2C Status Register */ +#define LPC17_I2C_DAT_OFFSET 0x0008 /* I2C Data Register */ +#define LPC17_I2C_ADR0_OFFSET 0x000c /* I2C Slave Address Register 0 */ +#define LPC17_I2C_SCLH_OFFSET 0x0010 /* SCH Duty Cycle Register High Half Word */ +#define LPC17_I2C_SCLL_OFFSET 0x0014 /* SCL Duty Cycle Register Low Half Word */ +#define LPC17_I2C_CONCLR_OFFSET 0x0018 /* I2C Control Clear Register */ +#define LPC17_I2C_MMCTRL_OFFSET 0x001c /* Monitor mode control register */ +#define LPC17_I2C_ADR1_OFFSET 0x0020 /* I2C Slave Address Register 1 */ +#define LPC17_I2C_ADR2_OFFSET 0x0024 /* I2C Slave Address Register 2 */ +#define LPC17_I2C_ADR3_OFFSET 0x0028 /* I2C Slave Address Register 3 */ +#define LPC17_I2C_BUFR_OFFSET 0x002c /* Data buffer register */ +#define LPC17_I2C_MASK0_OFFSET 0x0030 /* I2C Slave address mask register 0 */ +#define LPC17_I2C_MASK1_OFFSET 0x0034 /* I2C Slave address mask register 1 */ +#define LPC17_I2C_MASK2_OFFSET 0x0038 /* I2C Slave address mask register 2 */ +#define LPC17_I2C_MASK3_OFFSET 0x003c /* I2C Slave address mask register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_I2C0_CONSET (LPC17_I2C0_BASE+LPC17_I2C_CONSET_OFFSET) +#define LPC17_I2C0_STAT (LPC17_I2C0_BASE+LPC17_I2C_STAT_OFFSET) +#define LPC17_I2C0_DAT (LPC17_I2C0_BASE+LPC17_I2C_DAT_OFFSET) +#define LPC17_I2C0_ADR0 (LPC17_I2C0_BASE+LPC17_I2C_ADR0_OFFSET) +#define LPC17_I2C0_SCLH (LPC17_I2C0_BASE+LPC17_I2C_SCLH_OFFSET) +#define LPC17_I2C0_SCLL (LPC17_I2C0_BASE+LPC17_I2C_SCLL_OFFSET) +#define LPC17_I2C0_CONCLR (LPC17_I2C0_BASE+LPC17_I2C_CONCLR_OFFSET) +#define LPC17_I2C0_MMCTRL (LPC17_I2C0_BASE+LPC17_I2C_MMCTRL_OFFSET) +#define LPC17_I2C0_ADR1 (LPC17_I2C0_BASE+LPC17_I2C_ADR1_OFFSET) +#define LPC17_I2C0_ADR2 (LPC17_I2C0_BASE+LPC17_I2C_ADR2_OFFSET) +#define LPC17_I2C0_ADR3 (LPC17_I2C0_BASE+LPC17_I2C_ADR3_OFFSET) +#define LPC17_I2C0_BUFR (LPC17_I2C0_BASE+LPC17_I2C_BUFR_OFFSET) +#define LPC17_I2C0_MASK0 (LPC17_I2C0_BASE+LPC17_I2C_MASK0_OFFSET) +#define LPC17_I2C0_MASK1 (LPC17_I2C0_BASE+LPC17_I2C_MASK1_OFFSET) +#define LPC17_I2C0_MASK2 (LPC17_I2C0_BASE+LPC17_I2C_MASK2_OFFSET) +#define LPC17_I2C0_MASK3 (LPC17_I2C0_BASE+LPC17_I2C_MASK3_OFFSET) + +#define LPC17_I2C1_CONSET (LPC17_I2C1_BASE+LPC17_I2C_CONSET_OFFSET) +#define LPC17_I2C1_STAT (LPC17_I2C1_BASE+LPC17_I2C_STAT_OFFSET) +#define LPC17_I2C1_DAT (LPC17_I2C1_BASE+LPC17_I2C_DAT_OFFSET) +#define LPC17_I2C1_ADR0 (LPC17_I2C1_BASE+LPC17_I2C_ADR0_OFFSET) +#define LPC17_I2C1_SCLH (LPC17_I2C1_BASE+LPC17_I2C_SCLH_OFFSET) +#define LPC17_I2C1_SCLL (LPC17_I2C1_BASE+LPC17_I2C_SCLL_OFFSET) +#define LPC17_I2C1_CONCLR (LPC17_I2C1_BASE+LPC17_I2C_CONCLR_OFFSET) +#define LPC17_I2C1_MMCTRL (LPC17_I2C1_BASE+LPC17_I2C_MMCTRL_OFFSET) +#define LPC17_I2C1_ADR1 (LPC17_I2C1_BASE+LPC17_I2C_ADR1_OFFSET) +#define LPC17_I2C1_ADR2 (LPC17_I2C1_BASE+LPC17_I2C_ADR2_OFFSET) +#define LPC17_I2C1_ADR3 (LPC17_I2C1_BASE+LPC17_I2C_ADR3_OFFSET) +#define LPC17_I2C1_BUFR (LPC17_I2C1_BASE+LPC17_I2C_BUFR_OFFSET) +#define LPC17_I2C1_MASK0 (LPC17_I2C1_BASE+LPC17_I2C_MASK0_OFFSET) +#define LPC17_I2C1_MASK1 (LPC17_I2C1_BASE+LPC17_I2C_MASK1_OFFSET) +#define LPC17_I2C1_MASK2 (LPC17_I2C1_BASE+LPC17_I2C_MASK2_OFFSET) +#define LPC17_I2C1_MASK3 (LPC17_I2C1_BASE+LPC17_I2C_MASK3_OFFSET) + +#define LPC17_I2C2_CONSET (LPC17_I2C2_BASE+LPC17_I2C_CONSET_OFFSET) +#define LPC17_I2C2_STAT (LPC17_I2C2_BASE+LPC17_I2C_STAT_OFFSET) +#define LPC17_I2C2_DAT (LPC17_I2C2_BASE+LPC17_I2C_DAT_OFFSET) +#define LPC17_I2C2_ADR0 (LPC17_I2C2_BASE+LPC17_I2C_ADR0_OFFSET) +#define LPC17_I2C2_SCLH (LPC17_I2C2_BASE+LPC17_I2C_SCLH_OFFSET) +#define LPC17_I2C2_SCLL (LPC17_I2C2_BASE+LPC17_I2C_SCLL_OFFSET) +#define LPC17_I2C2_CONCLR (LPC17_I2C2_BASE+LPC17_I2C_CONCLR_OFFSET) +#define LPC17_I2C2_MMCTRL (LPC17_I2C2_BASE+LPC17_I2C_MMCTRL_OFFSET) +#define LPC17_I2C2_ADR1 (LPC17_I2C2_BASE+LPC17_I2C_ADR1_OFFSET) +#define LPC17_I2C2_ADR2 (LPC17_I2C2_BASE+LPC17_I2C_ADR2_OFFSET) +#define LPC17_I2C2_ADR3 (LPC17_I2C2_BASE+LPC17_I2C_ADR3_OFFSET) +#define LPC17_I2C2_BUFR (LPC17_I2C2_BASE+LPC17_I2C_BUFR_OFFSET) +#define LPC17_I2C2_MASK0 (LPC17_I2C2_BASE+LPC17_I2C_MASK0_OFFSET) +#define LPC17_I2C2_MASK1 (LPC17_I2C2_BASE+LPC17_I2C_MASK1_OFFSET) +#define LPC17_I2C2_MASK2 (LPC17_I2C2_BASE+LPC17_I2C_MASK2_OFFSET) +#define LPC17_I2C2_MASK3 (LPC17_I2C2_BASE+LPC17_I2C_MASK3_OFFSET) + +/* Register bit definitions *********************************************************/ +/* I2C Control Set Register */ + /* Bits 0-1: Reserved */ +#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */ +#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */ +#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */ +#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */ +#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */ + /* Bits 7-31: Reserved */ +/* I2C Control Clear Register */ + /* Bits 0-1: Reserved */ +#define I2C_CONCLR_AAC (1 << 2) /* Bit 2: Assert acknowledge Clear bit */ +#define I2C_CONCLR_SIC (1 << 3) /* Bit 3: I2C interrupt Clear bit */ + /* Bit 4: Reserved */ +#define I2C_CONCLR_STAC (1 << 5) /* Bit 5: START flag Clear bit */ +#define I2C_CONCLRT_I2ENC (1 << 6) /* Bit 6: I2C interface Disable bit */ + /* Bits 7-31: Reserved */ +/* I2C Status Register + * + * See tables 399-402 in the "LPC17xx User Manual" (UM10360), Rev. 01, 4 January + * 2010, NXP for definitions of status codes. + */ + +#define I2C_STAT_MASK (0xff) /* Bits 0-7: I2C interface status + * Bits 0-1 always zero */ + /* Bits 8-31: Reserved */ +/* I2C Data Register */ + +#define I2C_DAT_MASK (0xff) /* Bits 0-7: I2C data */ + /* Bits 8-31: Reserved */ +/* Monitor mode control register */ + +#define I2C_MMCTRL_MMENA (1 << 0) /* Bit 0: Monitor mode enable */ +#define I2C_MMCTRL_ENASCL (1 << 1) /* Bit 1: SCL output enable */ +#define I2C_MMCTRL_MATCHALL (1 << 2) /* Bit 2: Select interrupt register match */ + /* Bits 3-31: Reserved */ +/* Data buffer register */ + +#define I2C_BUFR_MASK (0xff) /* Bits 0-7: 8 MSBs of the I2DAT shift register */ + /* Bits 8-31: Reserved */ +/* I2C Slave address registers: + * + * I2C Slave Address Register 0 + * I2C Slave Address Register 1 + * I2C Slave Address Register 2 + * I2C Slave Address Register 3 + */ + +#define I2C_ADR_GC (1 << 0) /* Bit 0: GC General Call enable bit */ +#define I2C_ADR_ADDR_SHIFT (1) /* Bits 1-7: I2C slave address */ +#define I2C_ADR_ADDR_MASK (0x7f << I2C_ADR_ADDR_SHIFT) + /* Bits 8-31: Reserved */ +/* I2C Slave address mask registers: + * + * I2C Slave address mask register 0 + * I2C Slave address mask register 1 + * I2C Slave address mask register 2 + * I2C Slave address mask register 3 + */ + /* Bit 0: Reserved */ +#define I2C_MASK_SHIFT (1) /* Bits 1-7: I2C mask bits */ +#define I2C_MASK_MASK (0x7f << I2C_ADR_ADDR_SHIFT) + /* Bits 8-31: Reserved */ +/* SCH Duty Cycle Register High Half Word */ + +#define I2C_SCLH_MASK (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */ + /* Bits 16-31: Reserved */ +/* SCL Duty Cycle Register Low Half Word */ + +#define I2C_SCLL_MASK (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */ + /* Bits 16-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_I2C_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_mcpwm.h b/arch/arm/src/lpc17xx/lpc17_mcpwm.h index 0d562854fd9bfcc4678e9429483619f0cd1e4c7d..370aa42de3abf9554681ed36ec2733ea9dda8cdc 100644 --- a/arch/arm/src/lpc17xx/lpc17_mcpwm.h +++ b/arch/arm/src/lpc17xx/lpc17_mcpwm.h @@ -1,280 +1,280 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_mcpwm.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_MCPWM_CON_OFFSET 0x0000 /* PWM Control read address */ -#define LPC17_MCPWM_CONSET_OFFSET 0x0004 /* PWM Control set address */ -#define LPC17_MCPWM_CONCLR_OFFSET 0x0008 /* PWM Control clear address */ -#define LPC17_MCPWM_CAPCON_OFFSET 0x000c /* Capture Control read address */ -#define LPC17_MCPWM_CAPCONSET_OFFSET 0x0010 /* Capture Control set address */ -#define LPC17_MCPWM_CAPCONCLR_OFFSET 0x0014 /* Event Control clear address */ -#define LPC17_MCPWM_TC0_OFFSET 0x0018 /* Timer Counter register, channel 0 */ -#define LPC17_MCPWM_TC1_OFFSET 0x001c /* Timer Counter register, channel 1 */ -#define LPC17_MCPWM_TC2_OFFSET 0x0020 /* Timer Counter register, channel 2 */ -#define LPC17_MCPWM_LIM0_OFFSET 0x0024 /* Limit register, channel 0 */ -#define LPC17_MCPWM_LIM1_OFFSET 0x0028 /* Limit register, channel 1 */ -#define LPC17_MCPWM_LIM2_OFFSET 0x002c /* Limit register, channel 2 */ -#define LPC17_MCPWM_MAT0_OFFSET 0x0030 /* Match register, channel 0 */ -#define LPC17_MCPWM_MAT1_OFFSET 0x0034 /* Match register, channel 1 */ -#define LPC17_MCPWM_MAT2_OFFSET 0x0038 /* Match register, channel 2 */ -#define LPC17_MCPWM_DT_OFFSET 0x003c /* Dead time register */ -#define LPC17_MCPWM_CP_OFFSET 0x0040 /* Commutation Pattern register */ -#define LPC17_MCPWM_CAP0_OFFSET 0x0044 /* Capture register, channel 0 */ -#define LPC17_MCPWM_CAP1_OFFSET 0x0048 /* Capture register, channel 1 */ -#define LPC17_MCPWM_CAP2_OFFSET 0x004c /* Capture register, channel 2 */ -#define LPC17_MCPWM_INTEN_OFFSET 0x0050 /* Interrupt Enable read address */ -#define LPC17_MCPWM_INTENSET_OFFSET 0x0054 /* Interrupt Enable set address */ -#define LPC17_MCPWM_INTENCLR_OFFSET 0x0058 /* Interrupt Enable clear address */ -#define LPC17_MCPWM_CNTCON_OFFSET 0x005c /* Count Control read address */ -#define LPC17_MCPWM_CNTCONSET_OFFSET 0x0060 /* Count Control set address */ -#define LPC17_MCPWM_CNTCONCLR_OFFSET 0x0064 /* Count Control clear address */ -#define LPC17_MCPWM_INTF_OFFSET 0x0068 /* Interrupt flags read address */ -#define LPC17_MCPWM_INTFSET_OFFSET 0x006c /* Interrupt flags set address */ -#define LPC17_MCPWM_INTFCLR_OFFSET 0x0070 /* Interrupt flags clear address */ -#define LPC17_MCPWM_CAPCLR_OFFSET 0x0074 /* Capture clear address */ - -/* Register addresses ***************************************************************/ - -#define LPC17_MCPWM_CON (LPC17_MCPWM_BASE+LPC17_MCPWM_CON_OFFSET) -#define LPC17_MCPWM_CONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CONSET_OFFSET) -#define LPC17_MCPWM_CONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CONCLR_OFFSET) -#define LPC17_MCPWM_CAPCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCON_OFFSET) -#define LPC17_MCPWM_CAPCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONSET_OFFSET) -#define LPC17_MCPWM_CAPCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONCLR_OFFSET) -#define LPC17_MCPWM_TC0 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC0_OFFSET) -#define LPC17_MCPWM_TC1 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC1_OFFSET) -#define LPC17_MCPWM_TC2 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC2_OFFSET) -#define LPC17_MCPWM_LIM0 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM0_OFFSET) -#define LPC17_MCPWM_LIM1 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM1_OFFSET) -#define LPC17_MCPWM_LIM2 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM2_OFFSET) -#define LPC17_MCPWM_MAT0 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT0_OFFSET) -#define LPC17_MCPWM_MAT1 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT1_OFFSET) -#define LPC17_MCPWM_MAT2 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT2_OFFSET) -#define LPC17_MCPWM_DT (LPC17_MCPWM_BASE+LPC17_MCPWM_DT_OFFSET) -#define LPC17_MCPWM_CP (LPC17_MCPWM_BASE+LPC17_MCPWM_CP_OFFSET) -#define LPC17_MCPWM_CAP0 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP0_OFFSET) -#define LPC17_MCPWM_CAP1 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP1_OFFSET) -#define LPC17_MCPWM_CAP2 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP2_OFFSET) -#define LPC17_MCPWM_INTEN (LPC17_MCPWM_BASE+LPC17_MCPWM_INTEN_OFFSET) -#define LPC17_MCPWM_INTENSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENSET_OFFSET) -#define LPC17_MCPWM_INTENCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENCLR_OFFSET) -#define LPC17_MCPWM_CNTCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCON_OFFSET) -#define LPC17_MCPWM_CNTCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONSET_OFFSET) -#define LPC17_MCPWM_CNTCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONCLR_OFFSET) -#define LPC17_MCPWM_INTF (LPC17_MCPWM_BASE+LPC17_MCPWM_INTF_OFFSET) -#define LPC17_MCPWM_INTFSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFSET_OFFSET) -#define LPC17_MCPWM_INTFCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFCLR_OFFSET) -#define LPC17_MCPWM_CAPCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCLR_OFFSET) - -/* Register bit definitions *********************************************************/ -/* There are no bit field definitions for the following registers because they support - * 32-bit values: - * - * - Timer Counter register, channel 0 (TC0), Timer Counter register, channel 1 (TC1), - * and Timer Counter register, channel 2 (TC2): 32-bit Timer/Counter values for - * channels 0, 1, 2 (no bit field definitions) - * - * - Limit register, channel 0 (LIM0), Limit register, channel 1 (LIM1), and Limit - * register, channel 2 (LIM2): 32-bit Limit values for TC0, 1, 2 (no bit field - * definitions) - * - * - Match register, channel 0 MAT0), Match register, channel 1 (MAT1), and Match - * register, channel 2 (MAT2): 32-bit Match values for TC0, 1, 2 (no bit field - * definitions). - * - * - Capture register, channel 0 (CAP0), Capture register, channel 1 (CAP1), and - * Capture register, channel 2 (CAP2): 32-bit TC value at a capture event for - * channels 0, 1, 2 (no bit field definitions) - */ - -/* PWM Control read address (CON), PWM Control set address (CONSET), and PWM Control - * clear address (CONCLR) common regiser bit definitions. - */ - -#define MCPWM_CON_RUN0 (1 << 0) /* Bit 0: Stops/starts timer channel 0 */ -#define MCPWM_CON_CENTER0 (1 << 1) /* Bit 1: Chan 0 edge/center aligned operation */ -#define MCPWM_CON_POLA0 (1 << 2) /* Bit 2: Polarity of MCOA0 and MCOB0 */ -#define MCPWM_CON_DTE0 (1 << 3) /* Bit 3: Dead time feature control */ -#define MCPWM_CON_DISUP0 (1 << 4) /* Bit 4: Enable/disable register updates */ - /* Bits 5-7: Reserved */ -#define MCPWM_CON_RUN1 (1 << 8) /* Bit 8: Stops/starts timer channel 1 */ -#define MCPWM_CON_CENTER1 (1 << 9) /* Bit 9: Chan 1 edge/center aligned operation */ -#define MCPWM_CON_POLA1 (1 << 10) /* Bit 10: Polarity of MCOA1 and MCOB1 */ -#define MCPWM_CON_DTE1 (1 << 11) /* Bit 11: Dead time feature control */ -#define MCPWM_CON_DISUP1 (1 << 12) /* Bit 12: Enable/disable register updates */ - /* Bits 13-15: Reserved */ -#define MCPWM_CON_RUN2 (1 << 16) /* Bit 16: Stops/starts timer channel 2 */ -#define MCPWM_CON_CENTER2 (1 << 17) /* Bit 17: Chan 2 edge/center aligned operation */ -#define MCPWM_CON_POLA2 (1 << 18) /* Bit 18: Polarity of MCOA1 and MCOB1 */ -#define MCPWM_CON_DTE2 (1 << 19) /* Bit 19: Dead time feature control */ -#define MCPWM_CON_DISUP2 (1 << 20) /* Bit 20: Enable/disable register updates */ - /* Bits 21-28: Reserved */ -#define MCPWM_CON_INVBDC (1 << 29) /* Bit 29: Polarity of MCOB outputs (all channels) */ -#define MCPWM_CON_ACMODE (1 << 30) /* Bit 30: 3-phase AC mode select */ -#define MCPWM_CON_DCMODE (1 << 31) /* Bit 31: 3-phase DC mode select */ - -/* Capture Control read address (CAPCON), Capture Control set address (CAPCONSET), - * and Event Control clear address (CAPCONCLR) common register bit defintions - */ - -#define MCPWM_CAPCON_CAP0MCI0RE (1 << 0) /* Bit 0: Enable chan0 rising edge capture MCI0 */ -#define MCPWM_CAPCON_CAP0MCI0FE (1 << 1) /* Bit 1: Enable chan 0 falling edge capture MCI0 */ -#define MCPWM_CAPCON_CAP0MCI1RE (1 << 2) /* Bit 2: Enable chan 0 rising edge capture MCI1 */ -#define MCPWM_CAPCON_CAP0MCI1FE (1 << 3) /* Bit 3: Enable chan 0 falling edge capture MCI1 */ -#define MCPWM_CAPCON_CAP0MCI2RE (1 << 4) /* Bit 4: Enable chan 0 rising edge capture MCI2 */ -#define MCPWM_CAPCON_CAP0MCI2FE (1 << 5) /* Bit 5: Enable chan 0 falling edge capture MCI2 */ -#define MCPWM_CAPCON_CAP1MCI0RE (1 << 6) /* Bit 6: Enable chan 1 rising edge capture MCI0 */ -#define MCPWM_CAPCON_CAP1MCI0FE (1 << 7) /* Bit 7: Enable chan 1 falling edge capture MCI0 */ -#define MCPWM_CAPCON_CAP1MCI1RE (1 << 8) /* Bit 8: Enable chan 1 rising edge capture MCI1 */ -#define MCPWM_CAPCON_CAP1MCI1FE (1 << 9) /* Bit 9: Enable chan 1 falling edge capture MCI1 */ -#define MCPWM_CAPCON_CAP1MCI2RE (1 << 10) /* Bit 10: Enable chan 1 rising edge capture MCI2 */ -#define MCPWM_CAPCON_CAP1MCI2FE (1 << 11) /* Bit 11: Enable chan 1 falling edge capture MCI2 */ -#define MCPWM_CAPCON_CAP2MCI0RE (1 << 12) /* Bit 12: Enable chan 2 rising edge capture MCI0 */ -#define MCPWM_CAPCON_CAP2MCI0FE (1 << 13) /* Bit 13: Enable chan 2 falling edge capture MCI0 */ -#define MCPWM_CAPCON_CAP2MCI1RE (1 << 14) /* Bit 14: Enable chan 2 rising edge capture MCI1 */ -#define MCPWM_CAPCON_CAP2MCI1FE (1 << 15) /* Bit 15: Enable chan 2 falling edge capture MCI1 */ -#define MCPWM_CAPCON_CAP2MCI2RE (1 << 16) /* Bit 16: Enable chan 2 rising edge capture MCI2 */ -#define MCPWM_CAPCON_CAP2MCI2FE (1 << 17) /* Bit 17: Enable chan 2 falling edge capture MCI2 */ -#define MCPWM_CAPCON_RT0 (1 << 18) /* Bit 18: TC0 reset by chan 0 capture event */ -#define MCPWM_CAPCON_RT1 (1 << 19) /* Bit 19: TC1 reset by chan 1 capture event */ -#define MCPWM_CAPCON_RT2 (1 << 20) /* Bit 20: TC2 reset by chan 2 capture event */ -#define MCPWM_CAPCON_HNFCAP0 (1 << 21) /* Bit 21: Hardware noise filter */ -#define MCPWM_CAPCON_HNFCAP1 (1 << 22) /* Bit 22: Hardware noise filter */ -#define MCPWM_CAPCON_HNFCAP2 (1 << 23) /* Bit 23: Hardware noise filter */ - /* Bits 24-31: Reserved -/* Dead time register */ - -#define MCPWM_DT_DT0_SHIFT (0) /* Bits 0-9: Dead time for channel 0 */ -#define MCPWM_DT_DT0_MASK (0x03ff << MCPWM_DT_DT0_SHIFT) -#define MCPWM_DT_DT1_SHIFT (10) /* Bits 10-19: Dead time for channel 1 */ -#define MCPWM_DT_DT1_MASK (0x03ff << MCPWM_DT_DT1_SHIFT) -#define MCPWM_DT_DT2_SHIFT (20) /* Bits 20-29: Dead time for channel 2 */ -#define MCPWM_DT_DT2_MASK (0x03ff << MCPWM_DT_DT2_SHIFT) - /* Bits 30-31: reserved */ -/* Commutation Pattern register */ - -#define MCPWM_CP_CCPA0 (1 << 0) /* Bit 0: Iinternal MCOA0 */ -#define MCPWM_CP_CCPB0 (1 << 1) /* Bit 1: MCOB0 tracks internal MCOA0 */ -#define MCPWM_CP_CCPA1 (1 << 2) /* Bit 2: MCOA1 tracks internal MCOA0 */ -#define MCPWM_CP_CCPB1 (1 << 3) /* Bit 3: MCOB1 tracks internal MCOA0 */ -#define MCPWM_CP_CCPA2 (1 << 4) /* Bit 4: MCOA2 tracks internal MCOA0 */ -#define MCPWM_CP_CCPB2 (1 << 5) /* Bit 5: MCOB2 tracks internal MCOA0 */ - /* Bits 6-31: reserved */ - -/* Interrupt Enable read address (INTEN), Interrupt Enable set address (INTENSET), - * Interrupt Enable clear address (INTENCLR), Interrupt flags read address (INTF), - * Interrupt flags set address (INTFSET), and Interrupt flags clear address (INTFCLR) - * common bit field definitions - */ - -#define MCPWM_INT_ILIM0 (1 << 0) /* Bit 0: Limit interrupts for channel 0 */ -#define MCPWM_INT_IMAT0 (1 << 1) /* Bit 1: Match interrupts for channel 0 */ -#define MCPWM_INT_ICAP0 (1 << 2) /* Bit 2: Capture interrupts for channel 0 */ - /* Bit 3: Reserved */ -#define MCPWM_INT_ILIM1 (1 << 4) /* Bit 4: Limit interrupts for channel 1 */ -#define MCPWM_INT_IMAT1 (1 << 5) /* Bit 5: Match interrupts for channel 1 */ -#define MCPWM_INT_ICAP1 (1 << 6) /* Bit 6: Capture interrupts for channel 1 */ - /* Bit 7: Reserved */ -#define MCPWM_INT_ILIM2 (1 << 8) /* Bit 8: Limit interrupts for channel 2 */ -#define MCPWM_INT_IMAT2 (1 << 9) /* Bit 9: Match interrupts for channel 2 */ -#define MCPWM_INT_ICAP2 (1 << 10) /* Bit 10: Capture interrupts for channel 2 */ - /* Bits 11-14: Reserved */ -#define MCPWM_INT_ABORT (1 << 15) /* Bit 15: Fast abort interrupt */ - /* Bits 16-31: Reserved */ - -/* Count Control read address (CNTCON), Count Control set address (CNTCONSET), and - * Count Control clear address (CNTCONCLR) common register bit definitions. - */ - -#define MCPWM_CNTCON_TC0MCI0RE (1 << 0) /* Bit 0: Counter 0 incr on rising edge MCI0 */ -#define MCPWM_CNTCON_TC0MCI0FE (1 << 1) /* Bit 1: Counter 0 incr onfalling edge MCI0 */ -#define MCPWM_CNTCON_TC0MCI1RE (1 << 2) /* Bit 2: Counter 0 incr onrising edge MCI1 */ -#define MCPWM_CNTCON_TC0MCI1FE (1 << 3) /* Bit 3: Counter 0 incr onfalling edge MCI1 */ -#define MCPWM_CNTCON_TC0MCI2RE (1 << 4) /* Bit 4: Counter 0 incr onrising edge MCI2 */ -#define MCPWM_CNTCON_TC0MCI2FE (1 << 5) /* Bit 5: Counter 0 incr onfalling edge MCI2 */ -#define MCPWM_CNTCON_TC1MCI0RE (1 << 6) /* Bit 6: Counter 1 incr onrising edge MCI0 */ -#define MCPWM_CNTCON_TC1MCI0FE (1 << 7) /* Bit 7: Counter 1 incr onfalling edge MCI0 */ -#define MCPWM_CNTCON_TC1MCI1RE (1 << 8) /* Bit 8: Counter 1 incr onrising edge MCI1 */ -#define MCPWM_CNTCON_TC1MCI1FE (1 << 9) /* Bit 9: Counter 1 incr onfalling edge MCI1 */ -#define MCPWM_CNTCON_TC1MCI2RE (1 << 10) /* Bit 10: Counter 1 incr onrising edge MCI2 */ -#define MCPWM_CNTCON_TC1MCI2FE (1 << 11) /* Bit 11: Counter 1 incr onfalling edge MCI2 */ -#define MCPWM_CNTCON_TC2MCI0RE (1 << 12) /* Bit 12: Counter 2 incr onrising edge MCI0 */ -#define MCPWM_CNTCON_TC2MCI0FE (1 << 13) /* Bit 13: Counter 2 incr onfalling edge MCI0 */ -#define MCPWM_CNTCON_TC2MCI1RE (1 << 14) /* Bit 14: Counter 2 incr onrising edge MCI1 */ -#define MCPWM_CNTCON_TC2MCI1FE (1 << 15) /* Bit 15: Counter 2 incr onfalling edge MCI1 */ -#define MCPWM_CNTCON_TC2MCI2RE (1 << 16) /* Bit 16: Counter 2 incr onrising edge MCI2 */ -#define MCPWM_CNTCON_TC2MCI2FE (1 << 17) /* Bit 17: Counter 2 incr onfalling edge MCI2 */ - /* Bits 28-28: Reserved */ -#define MCPWM_CNTCON_CNTR0 (1 << 29) /* Bit 29: Channel 0 counter mode */ -#define MCPWM_CNTCON_CNTR1 (1 << 30) /* Bit 30: Channel 1 counter mode */ -#define MCPWM_CNTCON_CNTR2 (1 << 31) /* Bit 31: Channel 2 counter mode */ - -/* Capture clear address */ - -#define MCPWM_CAPCLR_MCCLR0 (1 << 0) /* Bit 0: Clear MCCAP0 register */ -#define MCPWM_CAPCLR_MCCLR1 (1 << 1) /* Bit 1: Clear MCCAP1 register */ -#define MCPWM_CAPCLR_MCCLR2 (1 << 2) /* Bit 2: Clear MCCAP2 register */ - /* Bits 2-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_mcpwm.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_MCPWM_CON_OFFSET 0x0000 /* PWM Control read address */ +#define LPC17_MCPWM_CONSET_OFFSET 0x0004 /* PWM Control set address */ +#define LPC17_MCPWM_CONCLR_OFFSET 0x0008 /* PWM Control clear address */ +#define LPC17_MCPWM_CAPCON_OFFSET 0x000c /* Capture Control read address */ +#define LPC17_MCPWM_CAPCONSET_OFFSET 0x0010 /* Capture Control set address */ +#define LPC17_MCPWM_CAPCONCLR_OFFSET 0x0014 /* Event Control clear address */ +#define LPC17_MCPWM_TC0_OFFSET 0x0018 /* Timer Counter register, channel 0 */ +#define LPC17_MCPWM_TC1_OFFSET 0x001c /* Timer Counter register, channel 1 */ +#define LPC17_MCPWM_TC2_OFFSET 0x0020 /* Timer Counter register, channel 2 */ +#define LPC17_MCPWM_LIM0_OFFSET 0x0024 /* Limit register, channel 0 */ +#define LPC17_MCPWM_LIM1_OFFSET 0x0028 /* Limit register, channel 1 */ +#define LPC17_MCPWM_LIM2_OFFSET 0x002c /* Limit register, channel 2 */ +#define LPC17_MCPWM_MAT0_OFFSET 0x0030 /* Match register, channel 0 */ +#define LPC17_MCPWM_MAT1_OFFSET 0x0034 /* Match register, channel 1 */ +#define LPC17_MCPWM_MAT2_OFFSET 0x0038 /* Match register, channel 2 */ +#define LPC17_MCPWM_DT_OFFSET 0x003c /* Dead time register */ +#define LPC17_MCPWM_CP_OFFSET 0x0040 /* Commutation Pattern register */ +#define LPC17_MCPWM_CAP0_OFFSET 0x0044 /* Capture register, channel 0 */ +#define LPC17_MCPWM_CAP1_OFFSET 0x0048 /* Capture register, channel 1 */ +#define LPC17_MCPWM_CAP2_OFFSET 0x004c /* Capture register, channel 2 */ +#define LPC17_MCPWM_INTEN_OFFSET 0x0050 /* Interrupt Enable read address */ +#define LPC17_MCPWM_INTENSET_OFFSET 0x0054 /* Interrupt Enable set address */ +#define LPC17_MCPWM_INTENCLR_OFFSET 0x0058 /* Interrupt Enable clear address */ +#define LPC17_MCPWM_CNTCON_OFFSET 0x005c /* Count Control read address */ +#define LPC17_MCPWM_CNTCONSET_OFFSET 0x0060 /* Count Control set address */ +#define LPC17_MCPWM_CNTCONCLR_OFFSET 0x0064 /* Count Control clear address */ +#define LPC17_MCPWM_INTF_OFFSET 0x0068 /* Interrupt flags read address */ +#define LPC17_MCPWM_INTFSET_OFFSET 0x006c /* Interrupt flags set address */ +#define LPC17_MCPWM_INTFCLR_OFFSET 0x0070 /* Interrupt flags clear address */ +#define LPC17_MCPWM_CAPCLR_OFFSET 0x0074 /* Capture clear address */ + +/* Register addresses ***************************************************************/ + +#define LPC17_MCPWM_CON (LPC17_MCPWM_BASE+LPC17_MCPWM_CON_OFFSET) +#define LPC17_MCPWM_CONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CONSET_OFFSET) +#define LPC17_MCPWM_CONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CONCLR_OFFSET) +#define LPC17_MCPWM_CAPCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCON_OFFSET) +#define LPC17_MCPWM_CAPCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONSET_OFFSET) +#define LPC17_MCPWM_CAPCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCONCLR_OFFSET) +#define LPC17_MCPWM_TC0 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC0_OFFSET) +#define LPC17_MCPWM_TC1 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC1_OFFSET) +#define LPC17_MCPWM_TC2 (LPC17_MCPWM_BASE+LPC17_MCPWM_TC2_OFFSET) +#define LPC17_MCPWM_LIM0 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM0_OFFSET) +#define LPC17_MCPWM_LIM1 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM1_OFFSET) +#define LPC17_MCPWM_LIM2 (LPC17_MCPWM_BASE+LPC17_MCPWM_LIM2_OFFSET) +#define LPC17_MCPWM_MAT0 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT0_OFFSET) +#define LPC17_MCPWM_MAT1 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT1_OFFSET) +#define LPC17_MCPWM_MAT2 (LPC17_MCPWM_BASE+LPC17_MCPWM_MAT2_OFFSET) +#define LPC17_MCPWM_DT (LPC17_MCPWM_BASE+LPC17_MCPWM_DT_OFFSET) +#define LPC17_MCPWM_CP (LPC17_MCPWM_BASE+LPC17_MCPWM_CP_OFFSET) +#define LPC17_MCPWM_CAP0 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP0_OFFSET) +#define LPC17_MCPWM_CAP1 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP1_OFFSET) +#define LPC17_MCPWM_CAP2 (LPC17_MCPWM_BASE+LPC17_MCPWM_CAP2_OFFSET) +#define LPC17_MCPWM_INTEN (LPC17_MCPWM_BASE+LPC17_MCPWM_INTEN_OFFSET) +#define LPC17_MCPWM_INTENSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENSET_OFFSET) +#define LPC17_MCPWM_INTENCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTENCLR_OFFSET) +#define LPC17_MCPWM_CNTCON (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCON_OFFSET) +#define LPC17_MCPWM_CNTCONSET (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONSET_OFFSET) +#define LPC17_MCPWM_CNTCONCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CNTCONCLR_OFFSET) +#define LPC17_MCPWM_INTF (LPC17_MCPWM_BASE+LPC17_MCPWM_INTF_OFFSET) +#define LPC17_MCPWM_INTFSET (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFSET_OFFSET) +#define LPC17_MCPWM_INTFCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_INTFCLR_OFFSET) +#define LPC17_MCPWM_CAPCLR (LPC17_MCPWM_BASE+LPC17_MCPWM_CAPCLR_OFFSET) + +/* Register bit definitions *********************************************************/ +/* There are no bit field definitions for the following registers because they support + * 32-bit values: + * + * - Timer Counter register, channel 0 (TC0), Timer Counter register, channel 1 (TC1), + * and Timer Counter register, channel 2 (TC2): 32-bit Timer/Counter values for + * channels 0, 1, 2 (no bit field definitions) + * + * - Limit register, channel 0 (LIM0), Limit register, channel 1 (LIM1), and Limit + * register, channel 2 (LIM2): 32-bit Limit values for TC0, 1, 2 (no bit field + * definitions) + * + * - Match register, channel 0 MAT0), Match register, channel 1 (MAT1), and Match + * register, channel 2 (MAT2): 32-bit Match values for TC0, 1, 2 (no bit field + * definitions). + * + * - Capture register, channel 0 (CAP0), Capture register, channel 1 (CAP1), and + * Capture register, channel 2 (CAP2): 32-bit TC value at a capture event for + * channels 0, 1, 2 (no bit field definitions) + */ + +/* PWM Control read address (CON), PWM Control set address (CONSET), and PWM Control + * clear address (CONCLR) common regiser bit definitions. + */ + +#define MCPWM_CON_RUN0 (1 << 0) /* Bit 0: Stops/starts timer channel 0 */ +#define MCPWM_CON_CENTER0 (1 << 1) /* Bit 1: Chan 0 edge/center aligned operation */ +#define MCPWM_CON_POLA0 (1 << 2) /* Bit 2: Polarity of MCOA0 and MCOB0 */ +#define MCPWM_CON_DTE0 (1 << 3) /* Bit 3: Dead time feature control */ +#define MCPWM_CON_DISUP0 (1 << 4) /* Bit 4: Enable/disable register updates */ + /* Bits 5-7: Reserved */ +#define MCPWM_CON_RUN1 (1 << 8) /* Bit 8: Stops/starts timer channel 1 */ +#define MCPWM_CON_CENTER1 (1 << 9) /* Bit 9: Chan 1 edge/center aligned operation */ +#define MCPWM_CON_POLA1 (1 << 10) /* Bit 10: Polarity of MCOA1 and MCOB1 */ +#define MCPWM_CON_DTE1 (1 << 11) /* Bit 11: Dead time feature control */ +#define MCPWM_CON_DISUP1 (1 << 12) /* Bit 12: Enable/disable register updates */ + /* Bits 13-15: Reserved */ +#define MCPWM_CON_RUN2 (1 << 16) /* Bit 16: Stops/starts timer channel 2 */ +#define MCPWM_CON_CENTER2 (1 << 17) /* Bit 17: Chan 2 edge/center aligned operation */ +#define MCPWM_CON_POLA2 (1 << 18) /* Bit 18: Polarity of MCOA1 and MCOB1 */ +#define MCPWM_CON_DTE2 (1 << 19) /* Bit 19: Dead time feature control */ +#define MCPWM_CON_DISUP2 (1 << 20) /* Bit 20: Enable/disable register updates */ + /* Bits 21-28: Reserved */ +#define MCPWM_CON_INVBDC (1 << 29) /* Bit 29: Polarity of MCOB outputs (all channels) */ +#define MCPWM_CON_ACMODE (1 << 30) /* Bit 30: 3-phase AC mode select */ +#define MCPWM_CON_DCMODE (1 << 31) /* Bit 31: 3-phase DC mode select */ + +/* Capture Control read address (CAPCON), Capture Control set address (CAPCONSET), + * and Event Control clear address (CAPCONCLR) common register bit defintions + */ + +#define MCPWM_CAPCON_CAP0MCI0RE (1 << 0) /* Bit 0: Enable chan0 rising edge capture MCI0 */ +#define MCPWM_CAPCON_CAP0MCI0FE (1 << 1) /* Bit 1: Enable chan 0 falling edge capture MCI0 */ +#define MCPWM_CAPCON_CAP0MCI1RE (1 << 2) /* Bit 2: Enable chan 0 rising edge capture MCI1 */ +#define MCPWM_CAPCON_CAP0MCI1FE (1 << 3) /* Bit 3: Enable chan 0 falling edge capture MCI1 */ +#define MCPWM_CAPCON_CAP0MCI2RE (1 << 4) /* Bit 4: Enable chan 0 rising edge capture MCI2 */ +#define MCPWM_CAPCON_CAP0MCI2FE (1 << 5) /* Bit 5: Enable chan 0 falling edge capture MCI2 */ +#define MCPWM_CAPCON_CAP1MCI0RE (1 << 6) /* Bit 6: Enable chan 1 rising edge capture MCI0 */ +#define MCPWM_CAPCON_CAP1MCI0FE (1 << 7) /* Bit 7: Enable chan 1 falling edge capture MCI0 */ +#define MCPWM_CAPCON_CAP1MCI1RE (1 << 8) /* Bit 8: Enable chan 1 rising edge capture MCI1 */ +#define MCPWM_CAPCON_CAP1MCI1FE (1 << 9) /* Bit 9: Enable chan 1 falling edge capture MCI1 */ +#define MCPWM_CAPCON_CAP1MCI2RE (1 << 10) /* Bit 10: Enable chan 1 rising edge capture MCI2 */ +#define MCPWM_CAPCON_CAP1MCI2FE (1 << 11) /* Bit 11: Enable chan 1 falling edge capture MCI2 */ +#define MCPWM_CAPCON_CAP2MCI0RE (1 << 12) /* Bit 12: Enable chan 2 rising edge capture MCI0 */ +#define MCPWM_CAPCON_CAP2MCI0FE (1 << 13) /* Bit 13: Enable chan 2 falling edge capture MCI0 */ +#define MCPWM_CAPCON_CAP2MCI1RE (1 << 14) /* Bit 14: Enable chan 2 rising edge capture MCI1 */ +#define MCPWM_CAPCON_CAP2MCI1FE (1 << 15) /* Bit 15: Enable chan 2 falling edge capture MCI1 */ +#define MCPWM_CAPCON_CAP2MCI2RE (1 << 16) /* Bit 16: Enable chan 2 rising edge capture MCI2 */ +#define MCPWM_CAPCON_CAP2MCI2FE (1 << 17) /* Bit 17: Enable chan 2 falling edge capture MCI2 */ +#define MCPWM_CAPCON_RT0 (1 << 18) /* Bit 18: TC0 reset by chan 0 capture event */ +#define MCPWM_CAPCON_RT1 (1 << 19) /* Bit 19: TC1 reset by chan 1 capture event */ +#define MCPWM_CAPCON_RT2 (1 << 20) /* Bit 20: TC2 reset by chan 2 capture event */ +#define MCPWM_CAPCON_HNFCAP0 (1 << 21) /* Bit 21: Hardware noise filter */ +#define MCPWM_CAPCON_HNFCAP1 (1 << 22) /* Bit 22: Hardware noise filter */ +#define MCPWM_CAPCON_HNFCAP2 (1 << 23) /* Bit 23: Hardware noise filter */ + /* Bits 24-31: Reserved +/* Dead time register */ + +#define MCPWM_DT_DT0_SHIFT (0) /* Bits 0-9: Dead time for channel 0 */ +#define MCPWM_DT_DT0_MASK (0x03ff << MCPWM_DT_DT0_SHIFT) +#define MCPWM_DT_DT1_SHIFT (10) /* Bits 10-19: Dead time for channel 1 */ +#define MCPWM_DT_DT1_MASK (0x03ff << MCPWM_DT_DT1_SHIFT) +#define MCPWM_DT_DT2_SHIFT (20) /* Bits 20-29: Dead time for channel 2 */ +#define MCPWM_DT_DT2_MASK (0x03ff << MCPWM_DT_DT2_SHIFT) + /* Bits 30-31: reserved */ +/* Commutation Pattern register */ + +#define MCPWM_CP_CCPA0 (1 << 0) /* Bit 0: Iinternal MCOA0 */ +#define MCPWM_CP_CCPB0 (1 << 1) /* Bit 1: MCOB0 tracks internal MCOA0 */ +#define MCPWM_CP_CCPA1 (1 << 2) /* Bit 2: MCOA1 tracks internal MCOA0 */ +#define MCPWM_CP_CCPB1 (1 << 3) /* Bit 3: MCOB1 tracks internal MCOA0 */ +#define MCPWM_CP_CCPA2 (1 << 4) /* Bit 4: MCOA2 tracks internal MCOA0 */ +#define MCPWM_CP_CCPB2 (1 << 5) /* Bit 5: MCOB2 tracks internal MCOA0 */ + /* Bits 6-31: reserved */ + +/* Interrupt Enable read address (INTEN), Interrupt Enable set address (INTENSET), + * Interrupt Enable clear address (INTENCLR), Interrupt flags read address (INTF), + * Interrupt flags set address (INTFSET), and Interrupt flags clear address (INTFCLR) + * common bit field definitions + */ + +#define MCPWM_INT_ILIM0 (1 << 0) /* Bit 0: Limit interrupts for channel 0 */ +#define MCPWM_INT_IMAT0 (1 << 1) /* Bit 1: Match interrupts for channel 0 */ +#define MCPWM_INT_ICAP0 (1 << 2) /* Bit 2: Capture interrupts for channel 0 */ + /* Bit 3: Reserved */ +#define MCPWM_INT_ILIM1 (1 << 4) /* Bit 4: Limit interrupts for channel 1 */ +#define MCPWM_INT_IMAT1 (1 << 5) /* Bit 5: Match interrupts for channel 1 */ +#define MCPWM_INT_ICAP1 (1 << 6) /* Bit 6: Capture interrupts for channel 1 */ + /* Bit 7: Reserved */ +#define MCPWM_INT_ILIM2 (1 << 8) /* Bit 8: Limit interrupts for channel 2 */ +#define MCPWM_INT_IMAT2 (1 << 9) /* Bit 9: Match interrupts for channel 2 */ +#define MCPWM_INT_ICAP2 (1 << 10) /* Bit 10: Capture interrupts for channel 2 */ + /* Bits 11-14: Reserved */ +#define MCPWM_INT_ABORT (1 << 15) /* Bit 15: Fast abort interrupt */ + /* Bits 16-31: Reserved */ + +/* Count Control read address (CNTCON), Count Control set address (CNTCONSET), and + * Count Control clear address (CNTCONCLR) common register bit definitions. + */ + +#define MCPWM_CNTCON_TC0MCI0RE (1 << 0) /* Bit 0: Counter 0 incr on rising edge MCI0 */ +#define MCPWM_CNTCON_TC0MCI0FE (1 << 1) /* Bit 1: Counter 0 incr onfalling edge MCI0 */ +#define MCPWM_CNTCON_TC0MCI1RE (1 << 2) /* Bit 2: Counter 0 incr onrising edge MCI1 */ +#define MCPWM_CNTCON_TC0MCI1FE (1 << 3) /* Bit 3: Counter 0 incr onfalling edge MCI1 */ +#define MCPWM_CNTCON_TC0MCI2RE (1 << 4) /* Bit 4: Counter 0 incr onrising edge MCI2 */ +#define MCPWM_CNTCON_TC0MCI2FE (1 << 5) /* Bit 5: Counter 0 incr onfalling edge MCI2 */ +#define MCPWM_CNTCON_TC1MCI0RE (1 << 6) /* Bit 6: Counter 1 incr onrising edge MCI0 */ +#define MCPWM_CNTCON_TC1MCI0FE (1 << 7) /* Bit 7: Counter 1 incr onfalling edge MCI0 */ +#define MCPWM_CNTCON_TC1MCI1RE (1 << 8) /* Bit 8: Counter 1 incr onrising edge MCI1 */ +#define MCPWM_CNTCON_TC1MCI1FE (1 << 9) /* Bit 9: Counter 1 incr onfalling edge MCI1 */ +#define MCPWM_CNTCON_TC1MCI2RE (1 << 10) /* Bit 10: Counter 1 incr onrising edge MCI2 */ +#define MCPWM_CNTCON_TC1MCI2FE (1 << 11) /* Bit 11: Counter 1 incr onfalling edge MCI2 */ +#define MCPWM_CNTCON_TC2MCI0RE (1 << 12) /* Bit 12: Counter 2 incr onrising edge MCI0 */ +#define MCPWM_CNTCON_TC2MCI0FE (1 << 13) /* Bit 13: Counter 2 incr onfalling edge MCI0 */ +#define MCPWM_CNTCON_TC2MCI1RE (1 << 14) /* Bit 14: Counter 2 incr onrising edge MCI1 */ +#define MCPWM_CNTCON_TC2MCI1FE (1 << 15) /* Bit 15: Counter 2 incr onfalling edge MCI1 */ +#define MCPWM_CNTCON_TC2MCI2RE (1 << 16) /* Bit 16: Counter 2 incr onrising edge MCI2 */ +#define MCPWM_CNTCON_TC2MCI2FE (1 << 17) /* Bit 17: Counter 2 incr onfalling edge MCI2 */ + /* Bits 28-28: Reserved */ +#define MCPWM_CNTCON_CNTR0 (1 << 29) /* Bit 29: Channel 0 counter mode */ +#define MCPWM_CNTCON_CNTR1 (1 << 30) /* Bit 30: Channel 1 counter mode */ +#define MCPWM_CNTCON_CNTR2 (1 << 31) /* Bit 31: Channel 2 counter mode */ + +/* Capture clear address */ + +#define MCPWM_CAPCLR_MCCLR0 (1 << 0) /* Bit 0: Clear MCCAP0 register */ +#define MCPWM_CAPCLR_MCCLR1 (1 << 1) /* Bit 1: Clear MCCAP1 register */ +#define MCPWM_CAPCLR_MCCLR2 (1 << 2) /* Bit 2: Clear MCCAP2 register */ + /* Bits 2-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_MCPWM_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_memorymap.h b/arch/arm/src/lpc17xx/lpc17_memorymap.h index da69f1481e3e28b40079940c2a75500c85887ac3..ae66b684cbdd5b3972c4f9ed1a4d6fc85c43157a 100644 --- a/arch/arm/src/lpc17xx/lpc17_memorymap.h +++ b/arch/arm/src/lpc17xx/lpc17_memorymap.h @@ -1,136 +1,136 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_memorymap.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Memory Map ***********************************************************************/ - -#define LPC17_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */ -#define LPC17_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */ -#define LPC17_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */ -#define LPC17_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */ -# define LPC17_SRAM_BANK0 0x2007c000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */ -# define LPC17_SRAM_BANK1 0x20080000 /* -0x2008ffff: On-chip AHB SRAM Bank1 (devices 64Kb) */ -#define LPC17_GPIO_BASE 0x2009c000 /* -0x2009ffff: GPIO */ -#define LPC17_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */ -# define LPC17_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */ -# define LPC17_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */ -# define LPC17_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */ -#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */ -#define LPC17_SCS_BASE 0xe000e000 -#define LPC17_DEBUGMCU_BASE 0xe0042000 - -/* AHB SRAM Bank sizes **************************************************************/ - -#define LPC17_BANK0_SIZE (16*1024) /* Size of AHB SRAM Bank0 (if present) */ -#define LPC17_BANK1_SIZE (16*1024) /* Size of AHB SRAM Bank1 (if present) */ - -/* APB0 Peripherals *****************************************************************/ - -#define LPC17_WDT_BASE 0x40000000 /* -0x40003fff: Watchdog timer */ -#define LPC17_TMR0_BASE 0x40004000 /* -0x40007fff: Timer 0 */ -#define LPC17_TMR1_BASE 0x40008000 /* -0x4000bfff: Timer 1 */ -#define LPC17_UART0_BASE 0x4000c000 /* -0x4000ffff: UART 0 */ -#define LPC17_UART1_BASE 0x40010000 /* -0x40013fff: UART 1 */ - /* -0x40017fff: Reserved */ -#define LPC17_PWM1_BASE 0x40018000 /* -0x4001bfff: PWM 1 */ -#define LPC17_I2C0_BASE 0x4001c000 /* -0x4001ffff: I2C 0 */ -#define LPC17_SPI_BASE 0x40020000 /* -0x40023fff: SPI */ -#define LPC17_RTC_BASE 0x40024000 /* -0x40027fff: RTC + backup registers */ -#define LPC17_GPIOINT_BASE 0x40028000 /* -0x4002bfff: GPIO interrupts */ -#define LPC17_PINCONN_BASE 0x4002c000 /* -0x4002ffff: Pin connect block */ -#define LPC17_SSP1_BASE 0x40030000 /* -0x40033fff: SSP 1 */ -#define LPC17_ADC_BASE 0x40034000 /* -0x40037fff: ADC */ -#define LPC17_CANAFRAM_BASE 0x40038000 /* -0x4003bfff: CAN acceptance filter (AF) RAM */ -#define LPC17_CANAF_BASE 0x4003c000 /* -0x4003ffff: CAN acceptance filter (AF) registers */ -#define LPC17_CAN_BASE 0x40040000 /* -0x40043fff: CAN common registers */ -#define LPC17_CAN1_BASE 0x40044000 /* -0x40047fff: CAN controller l */ -#define LPC17_CAN2_BASE 0x40048000 /* -0x4004bfff: CAN controller 2 */ - /* -0x4005bfff: Reserved */ -#define LPC17_I2C1_BASE 0x4005c000 /* -0x4005ffff: I2C 1 */ - /* -0x4007ffff: Reserved */ - -/* APB1 Peripherals *****************************************************************/ - - /* -0x40087fff: Reserved */ -#define LPC17_SSP0_BASE 0x40088000 /* -0x4008bfff: SSP 0 */ -#define LPC17_DAC_BASE 0x4008c000 /* -0x4008ffff: DAC */ -#define LPC17_TMR2_BASE 0x40090000 /* -0x40093fff: Timer 2 */ -#define LPC17_TMR3_BASE 0x40094000 /* -0x40097fff: Timer 3 */ -#define LPC17_UART2_BASE 0x40098000 /* -0x4009bfff: UART 2 */ -#define LPC17_UART3_BASE 0x4009c000 /* -0x4009ffff: UART 3 */ -#define LPC17_I2C2_BASE 0x400a0000 /* -0x400a3fff: I2C 2 */ - /* -0x400a7fff: Reserved */ -#define LPC17_I2S_BASE 0x400a8000 /* -0x400abfff: I2S */ - /* -0x400affff: Reserved */ -#define LPC17_RIT_BASE 0x400b0000 /* -0x400b3fff: Repetitive interrupt timer */ - /* -0x400b7fff: Reserved */ -#define LPC17_MCPWM_BASE 0x400b8000 /* -0x400bbfff: Motor control PWM */ -#define LPC17_QEI_BASE 0x400bc000 /* -0x400bffff: Quadrature encoder interface */ - /* -0x400fbfff: Reserved */ -#define LPC17_SYSCON_BASE 0x400fc000 /* -0x400fffff: System control */ - -/* AHB Peripherals ******************************************************************/ - -#define LPC17_ETH_BASE 0x50000000 /* -0x50003fff: Ethernet controller */ -#define LPC17_GPDMA_BASE 0x50004000 /* -0x50007fff: GPDMA controller */ -#define LPC17_USB_BASE 0x5000c000 /* -0x5000cfff: USB controller */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_memorymap.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory Map ***********************************************************************/ + +#define LPC17_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */ +#define LPC17_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */ +#define LPC17_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */ +#define LPC17_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */ +# define LPC17_SRAM_BANK0 0x2007c000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */ +# define LPC17_SRAM_BANK1 0x20080000 /* -0x2008ffff: On-chip AHB SRAM Bank1 (devices 64Kb) */ +#define LPC17_GPIO_BASE 0x2009c000 /* -0x2009ffff: GPIO */ +#define LPC17_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */ +# define LPC17_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */ +# define LPC17_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */ +# define LPC17_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */ +#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */ +#define LPC17_SCS_BASE 0xe000e000 +#define LPC17_DEBUGMCU_BASE 0xe0042000 + +/* AHB SRAM Bank sizes **************************************************************/ + +#define LPC17_BANK0_SIZE (16*1024) /* Size of AHB SRAM Bank0 (if present) */ +#define LPC17_BANK1_SIZE (16*1024) /* Size of AHB SRAM Bank1 (if present) */ + +/* APB0 Peripherals *****************************************************************/ + +#define LPC17_WDT_BASE 0x40000000 /* -0x40003fff: Watchdog timer */ +#define LPC17_TMR0_BASE 0x40004000 /* -0x40007fff: Timer 0 */ +#define LPC17_TMR1_BASE 0x40008000 /* -0x4000bfff: Timer 1 */ +#define LPC17_UART0_BASE 0x4000c000 /* -0x4000ffff: UART 0 */ +#define LPC17_UART1_BASE 0x40010000 /* -0x40013fff: UART 1 */ + /* -0x40017fff: Reserved */ +#define LPC17_PWM1_BASE 0x40018000 /* -0x4001bfff: PWM 1 */ +#define LPC17_I2C0_BASE 0x4001c000 /* -0x4001ffff: I2C 0 */ +#define LPC17_SPI_BASE 0x40020000 /* -0x40023fff: SPI */ +#define LPC17_RTC_BASE 0x40024000 /* -0x40027fff: RTC + backup registers */ +#define LPC17_GPIOINT_BASE 0x40028000 /* -0x4002bfff: GPIO interrupts */ +#define LPC17_PINCONN_BASE 0x4002c000 /* -0x4002ffff: Pin connect block */ +#define LPC17_SSP1_BASE 0x40030000 /* -0x40033fff: SSP 1 */ +#define LPC17_ADC_BASE 0x40034000 /* -0x40037fff: ADC */ +#define LPC17_CANAFRAM_BASE 0x40038000 /* -0x4003bfff: CAN acceptance filter (AF) RAM */ +#define LPC17_CANAF_BASE 0x4003c000 /* -0x4003ffff: CAN acceptance filter (AF) registers */ +#define LPC17_CAN_BASE 0x40040000 /* -0x40043fff: CAN common registers */ +#define LPC17_CAN1_BASE 0x40044000 /* -0x40047fff: CAN controller l */ +#define LPC17_CAN2_BASE 0x40048000 /* -0x4004bfff: CAN controller 2 */ + /* -0x4005bfff: Reserved */ +#define LPC17_I2C1_BASE 0x4005c000 /* -0x4005ffff: I2C 1 */ + /* -0x4007ffff: Reserved */ + +/* APB1 Peripherals *****************************************************************/ + + /* -0x40087fff: Reserved */ +#define LPC17_SSP0_BASE 0x40088000 /* -0x4008bfff: SSP 0 */ +#define LPC17_DAC_BASE 0x4008c000 /* -0x4008ffff: DAC */ +#define LPC17_TMR2_BASE 0x40090000 /* -0x40093fff: Timer 2 */ +#define LPC17_TMR3_BASE 0x40094000 /* -0x40097fff: Timer 3 */ +#define LPC17_UART2_BASE 0x40098000 /* -0x4009bfff: UART 2 */ +#define LPC17_UART3_BASE 0x4009c000 /* -0x4009ffff: UART 3 */ +#define LPC17_I2C2_BASE 0x400a0000 /* -0x400a3fff: I2C 2 */ + /* -0x400a7fff: Reserved */ +#define LPC17_I2S_BASE 0x400a8000 /* -0x400abfff: I2S */ + /* -0x400affff: Reserved */ +#define LPC17_RIT_BASE 0x400b0000 /* -0x400b3fff: Repetitive interrupt timer */ + /* -0x400b7fff: Reserved */ +#define LPC17_MCPWM_BASE 0x400b8000 /* -0x400bbfff: Motor control PWM */ +#define LPC17_QEI_BASE 0x400bc000 /* -0x400bffff: Quadrature encoder interface */ + /* -0x400fbfff: Reserved */ +#define LPC17_SYSCON_BASE 0x400fc000 /* -0x400fffff: System control */ + +/* AHB Peripherals ******************************************************************/ + +#define LPC17_ETH_BASE 0x50000000 /* -0x50003fff: Ethernet controller */ +#define LPC17_GPDMA_BASE 0x50004000 /* -0x50007fff: GPDMA controller */ +#define LPC17_USB_BASE 0x5000c000 /* -0x5000cfff: USB controller */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_MEMORYMAP_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_ohciram.h b/arch/arm/src/lpc17xx/lpc17_ohciram.h index 7601fefca677d9daf685fee7ae2ee59dea50cd84..1e0564a87426ceab37896986de4a87f14766bd1f 100644 --- a/arch/arm/src/lpc17xx/lpc17_ohciram.h +++ b/arch/arm/src/lpc17xx/lpc17_ohciram.h @@ -1,263 +1,263 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_ohciram.h - * - * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Default, no-OHCI Case ************************************************************/ -/* Assume that all of AHB SRAM will be available for heap. If this is not true, then - * LPC17_BANK1_HEAPSIZE will be undefined but redefined below. - */ - -#undef LPC17_BANK1_HEAPBASE -#undef LPC17_BANK1_HEAPSIZE -#ifdef LPC17_HAVE_BANK1 -# define LPC17_BANK1_HEAPBASE LPC17_SRAM_BANK1 -# define LPC17_BANK1_HEAPSIZE LPC17_BANK1_SIZE -#endif - -/* Is networking enabled? Is the LPC17xx Ethernet device enabled? Does this chip have - * and Ethernet controlloer? Yes... then we will replace the above default definitions. - */ - -#if defined(CONFIG_USBHOST) && defined(CONFIG_LPC17_USBHOST) && LPC17_NUSBHOST > 0 - -/* OHCI RAM Configuration ***********************************************************/ -/* Is AHB SRAM available? */ - -#ifndef LPC17_HAVE_BANK1 -# error "AHB SRAM Bank1 is not available for OHCI RAM" -#endif - -/* OHCI/Heap Memory Allocation ******************************************************/ -/* Configured Size of the region at the end of AHB SRAM BANK1 set set aside for the - * OHCI. This size must fit within AHB SRAM Bank 1 and also be a multiple of 256 - * bytes. - */ - -#ifndef CONFIG_USBHOST_OHCIRAM_SIZE -# define CONFIG_USBHOST_OHCIRAM_SIZE LPC17_BANK1_SIZE -#endif - -#if CONFIG_USBHOST_OHCIRAM_SIZE > LPC17_BANK1_SIZE -# error "OHCI RAM size cannot exceed the size of AHB SRAM Bank 1" -#endif - -#if (CONFIG_USBHOST_OHCIRAM_SIZE & 0xff) != 0 -# error "OHCI RAM size must be in multiples of 256 bytes" -#endif - -/* Then position the OHCI RAM at the end of AHB SRAM Bank 1 */ - -#define LPC17_OHCIRAM_END (LPC17_SRAM_BANK1 + LPC17_BANK1_SIZE) -#define LPC17_OHCIRAM_BASE (LPC17_OHCIRAM_END - CONFIG_USBHOST_OHCIRAM_SIZE) -#define LPC17_OHCIRAM_SIZE CONFIG_USBHOST_OHCIRAM_SIZE - -/* Determine is there is any meaningful space left at the beginning of AHB Bank 1 - * that could be added to the heap. - */ - -#undef LPC17_BANK1_HEAPBASE -#undef LPC17_BANK1_HEAPSIZE -#if LPC17_OHCIRAM_SIZE < (LPC17_BANK1_SIZE-128) -# define LPC17_BANK1_HEAPBASE LPC17_SRAM_BANK1 -# define LPC17_BANK1_HEAPSIZE (LPC17_BANK1_SIZE - LPC17_OHCIRAM_SIZE) -#endif - -/* Numbers and Sizes of Things ******************************************************/ -/* Fixed size of the OHCI control area */ - -#define LPC17_HCCA_SIZE 256 - -/* Fixed endpoint descriptor size. The actual size required by the hardware is only - * 16 bytes, however, we set aside an additional 16 bytes for for internal use by - * the OHCI host driver. 16-bytes is set aside because the EDs must still be - * aligned to 16-byte boundaries. - */ - -#define LPC17_ED_SIZE 32 - -/* Configurable number of user endpoint descriptors (EDs). This number excludes - * the control endpoint that is always allocated. - */ - -#ifndef CONFIG_USBHOST_NEDS -# define CONFIG_USBHOST_NEDS 2 -#endif - -/* Derived size of user endpoint descriptor (ED) memory. */ - -#define LPC17_EDFREE_SIZE (CONFIG_USBHOST_NEDS * LPC17_ED_SIZE) - -/* Fixed transfer descriptor size. The actual size required by the hardware is only - * 16 bytes, however, we set aside an additional 16 bytes for for internal use by - * the OHCI host driver. 16-bytes is set aside because the TDs must still be - * aligned to 16-byte boundaries. - */ - -#define LPC17_TD_SIZE 32 - -/* Configurable number of user transfer descriptors (TDs). */ - -#ifndef CONFIG_USBHOST_NTDS -# define CONFIG_USBHOST_NTDS 3 -#endif - -#if CONFIG_USBHOST_NTDS < 2 -# error "Insufficent TDs" -#endif - -/* Derived size of user trasnfer descriptor (TD) memory. */ - -#define LPC17_TDFREE_SIZE (CONFIG_USBHOST_NTDS * LPC17_TD_SIZE) - -/* Configurable number of request/descriptor buffers (TDBUFFER) */ - -#ifndef CONFIG_USBHOST_TDBUFFERS -# define CONFIG_USBHOST_TDBUFFERS 2 -#endif - -#if CONFIG_USBHOST_TDBUFFERS < 2 -# error "At least two TD buffers are required" -#endif - -/* Configurable size of a TD buffer */ - -#if CONFIG_USBHOST_TDBUFFERS > 0 && !defined(CONFIG_USBHOST_TDBUFSIZE) -# define CONFIG_USBHOST_TDBUFSIZE 128 -#endif - -#if (CONFIG_USBHOST_TDBUFSIZE & 3) != 0 -# error "TD buffer size must be an even number of 32-bit words" -#endif - -#define LPC17_TBFREE_SIZE (CONFIG_USBHOST_TDBUFFERS * CONFIG_USBHOST_TDBUFSIZE) - -/* Configurable size of an IO buffer. The number of IO buffers will be determined - * by what is left at the end of the BANK1 memory setup aside of OHCI RAM. - */ - -#ifndef CONFIG_USBHOST_IOBUFSIZE -# define CONFIG_USBHOST_IOBUFSIZE 512 -#endif - -#if (CONFIG_USBHOST_IOBUFSIZE & 3) != 0 -# error "IO buffer size must be an even number of 32-bit words" -#endif - -/* OHCI Memory Layout ***************************************************************/ -/* Example: - * Hardware: - * LPC17_SRAM_BANK1 0x20008000 - * LPC17_BANK1_SIZE 16384 - * - * Configuration: - * CONFIG_USBHOST_OHCIRAM_SIZE 1536 - * CONFIG_USBHOST_NEDS 2 - * CONFIG_USBHOST_NTDS 3 - * CONFIG_USBHOST_TDBUFFERS 3 - * CONFIG_USBHOST_TDBUFSIZE 128 - * CONFIG_USBHOST_IOBUFSIZE 512 - * - * Sizes of things - * LPC17_EDFREE_SIZE 64 0x00000040 - * LPC17_TDFREE_SIZE 96 0x00000060 - * LPC17_TBFREE_SIZE 384 0x00000100 - * LPC17_IOFREE_SIZE 512 0x00000200 - * - * Memory Layout - * LPC17_OHCIRAM_END (0x20008000 + 16384) = 0x20084000 - * LPC17_OHCIRAM_BASE (0x2000c000 - 1536) = 0x2000ba00 - * LPC17_OHCIRAM_SIZE 1280 - * LPC17_BANK1_HEAPBASE 0x20008000 - * LPC17_BANK1_HEAPSIZE (16384 - 1280) = 15104 - * - * LPC17_HCCA_BASE 0x20083a00 -- Communications area - * LPC17_TDTAIL_ADDR 0x20083b00 -- Common. pre-allocated tail TD - * LPC17_EDCTRL_ADDR 0x20083b20 -- Pre-allocated ED for EP0 - * LPC17_EDFREE_BASE 0x20083b40 -- Free EDs - * LPC17_TDFREE_BASE 0x20083b80 -- Free TDs - * LPC17_TBFREE_BASE 0x20083be0 -- Free request/descriptor buffers - * LPC17_IOFREE_BASE 0x20083d60 -- Free large I/O buffers - * LPC17_IOBUFFERS (0x20084000 - 0x20083d60) / 512 = 672/512 = 1 - * - * Wasted memory: 672-512 = 160 bytes - */ - -#define LPC17_HCCA_BASE (LPC17_OHCIRAM_BASE) -#define LPC17_TDTAIL_ADDR (LPC17_HCCA_BASE + LPC17_HCCA_SIZE) -#define LPC17_EDCTRL_ADDR (LPC17_TDTAIL_ADDR + LPC17_TD_SIZE) -#define LPC17_EDFREE_BASE (LPC17_EDCTRL_ADDR + LPC17_ED_SIZE) -#define LPC17_TDFREE_BASE (LPC17_EDFREE_BASE + LPC17_EDFREE_SIZE) -#define LPC17_TBFREE_BASE (LPC17_TDFREE_BASE + LPC17_TDFREE_SIZE) -#define LPC17_IOFREE_BASE (LPC17_TBFREE_BASE + LPC17_TBFREE_SIZE) - -#if LPC17_IOFREE_BASE > LPC17_OHCIRAM_END -# error "Insufficient OHCI RAM allocated" -#endif - -/* Finally, use the remainder of the allocated OHCI for IO buffers */ - -#if CONFIG_USBHOST_IOBUFSIZE > 0 -# define LPC17_IOBUFFERS ((LPC17_OHCIRAM_END - LPC17_IOFREE_BASE) / CONFIG_USBHOST_IOBUFSIZE) -#else -# define LPC17_IOBUFFERS 0 -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* CONFIG_USBHOST && CONFIG_LPC17_USBHOST && LPC17_NUSBHOST > 0*/ -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_ohciram.h + * + * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Default, no-OHCI Case ************************************************************/ +/* Assume that all of AHB SRAM will be available for heap. If this is not true, then + * LPC17_BANK1_HEAPSIZE will be undefined but redefined below. + */ + +#undef LPC17_BANK1_HEAPBASE +#undef LPC17_BANK1_HEAPSIZE +#ifdef LPC17_HAVE_BANK1 +# define LPC17_BANK1_HEAPBASE LPC17_SRAM_BANK1 +# define LPC17_BANK1_HEAPSIZE LPC17_BANK1_SIZE +#endif + +/* Is networking enabled? Is the LPC17xx Ethernet device enabled? Does this chip have + * and Ethernet controlloer? Yes... then we will replace the above default definitions. + */ + +#if defined(CONFIG_USBHOST) && defined(CONFIG_LPC17_USBHOST) && LPC17_NUSBHOST > 0 + +/* OHCI RAM Configuration ***********************************************************/ +/* Is AHB SRAM available? */ + +#ifndef LPC17_HAVE_BANK1 +# error "AHB SRAM Bank1 is not available for OHCI RAM" +#endif + +/* OHCI/Heap Memory Allocation ******************************************************/ +/* Configured Size of the region at the end of AHB SRAM BANK1 set set aside for the + * OHCI. This size must fit within AHB SRAM Bank 1 and also be a multiple of 256 + * bytes. + */ + +#ifndef CONFIG_USBHOST_OHCIRAM_SIZE +# define CONFIG_USBHOST_OHCIRAM_SIZE LPC17_BANK1_SIZE +#endif + +#if CONFIG_USBHOST_OHCIRAM_SIZE > LPC17_BANK1_SIZE +# error "OHCI RAM size cannot exceed the size of AHB SRAM Bank 1" +#endif + +#if (CONFIG_USBHOST_OHCIRAM_SIZE & 0xff) != 0 +# error "OHCI RAM size must be in multiples of 256 bytes" +#endif + +/* Then position the OHCI RAM at the end of AHB SRAM Bank 1 */ + +#define LPC17_OHCIRAM_END (LPC17_SRAM_BANK1 + LPC17_BANK1_SIZE) +#define LPC17_OHCIRAM_BASE (LPC17_OHCIRAM_END - CONFIG_USBHOST_OHCIRAM_SIZE) +#define LPC17_OHCIRAM_SIZE CONFIG_USBHOST_OHCIRAM_SIZE + +/* Determine is there is any meaningful space left at the beginning of AHB Bank 1 + * that could be added to the heap. + */ + +#undef LPC17_BANK1_HEAPBASE +#undef LPC17_BANK1_HEAPSIZE +#if LPC17_OHCIRAM_SIZE < (LPC17_BANK1_SIZE-128) +# define LPC17_BANK1_HEAPBASE LPC17_SRAM_BANK1 +# define LPC17_BANK1_HEAPSIZE (LPC17_BANK1_SIZE - LPC17_OHCIRAM_SIZE) +#endif + +/* Numbers and Sizes of Things ******************************************************/ +/* Fixed size of the OHCI control area */ + +#define LPC17_HCCA_SIZE 256 + +/* Fixed endpoint descriptor size. The actual size required by the hardware is only + * 16 bytes, however, we set aside an additional 16 bytes for for internal use by + * the OHCI host driver. 16-bytes is set aside because the EDs must still be + * aligned to 16-byte boundaries. + */ + +#define LPC17_ED_SIZE 32 + +/* Configurable number of user endpoint descriptors (EDs). This number excludes + * the control endpoint that is always allocated. + */ + +#ifndef CONFIG_USBHOST_NEDS +# define CONFIG_USBHOST_NEDS 2 +#endif + +/* Derived size of user endpoint descriptor (ED) memory. */ + +#define LPC17_EDFREE_SIZE (CONFIG_USBHOST_NEDS * LPC17_ED_SIZE) + +/* Fixed transfer descriptor size. The actual size required by the hardware is only + * 16 bytes, however, we set aside an additional 16 bytes for for internal use by + * the OHCI host driver. 16-bytes is set aside because the TDs must still be + * aligned to 16-byte boundaries. + */ + +#define LPC17_TD_SIZE 32 + +/* Configurable number of user transfer descriptors (TDs). */ + +#ifndef CONFIG_USBHOST_NTDS +# define CONFIG_USBHOST_NTDS 3 +#endif + +#if CONFIG_USBHOST_NTDS < 2 +# error "Insufficent TDs" +#endif + +/* Derived size of user trasnfer descriptor (TD) memory. */ + +#define LPC17_TDFREE_SIZE (CONFIG_USBHOST_NTDS * LPC17_TD_SIZE) + +/* Configurable number of request/descriptor buffers (TDBUFFER) */ + +#ifndef CONFIG_USBHOST_TDBUFFERS +# define CONFIG_USBHOST_TDBUFFERS 2 +#endif + +#if CONFIG_USBHOST_TDBUFFERS < 2 +# error "At least two TD buffers are required" +#endif + +/* Configurable size of a TD buffer */ + +#if CONFIG_USBHOST_TDBUFFERS > 0 && !defined(CONFIG_USBHOST_TDBUFSIZE) +# define CONFIG_USBHOST_TDBUFSIZE 128 +#endif + +#if (CONFIG_USBHOST_TDBUFSIZE & 3) != 0 +# error "TD buffer size must be an even number of 32-bit words" +#endif + +#define LPC17_TBFREE_SIZE (CONFIG_USBHOST_TDBUFFERS * CONFIG_USBHOST_TDBUFSIZE) + +/* Configurable size of an IO buffer. The number of IO buffers will be determined + * by what is left at the end of the BANK1 memory setup aside of OHCI RAM. + */ + +#ifndef CONFIG_USBHOST_IOBUFSIZE +# define CONFIG_USBHOST_IOBUFSIZE 512 +#endif + +#if (CONFIG_USBHOST_IOBUFSIZE & 3) != 0 +# error "IO buffer size must be an even number of 32-bit words" +#endif + +/* OHCI Memory Layout ***************************************************************/ +/* Example: + * Hardware: + * LPC17_SRAM_BANK1 0x20008000 + * LPC17_BANK1_SIZE 16384 + * + * Configuration: + * CONFIG_USBHOST_OHCIRAM_SIZE 1536 + * CONFIG_USBHOST_NEDS 2 + * CONFIG_USBHOST_NTDS 3 + * CONFIG_USBHOST_TDBUFFERS 3 + * CONFIG_USBHOST_TDBUFSIZE 128 + * CONFIG_USBHOST_IOBUFSIZE 512 + * + * Sizes of things + * LPC17_EDFREE_SIZE 64 0x00000040 + * LPC17_TDFREE_SIZE 96 0x00000060 + * LPC17_TBFREE_SIZE 384 0x00000100 + * LPC17_IOFREE_SIZE 512 0x00000200 + * + * Memory Layout + * LPC17_OHCIRAM_END (0x20008000 + 16384) = 0x20084000 + * LPC17_OHCIRAM_BASE (0x2000c000 - 1536) = 0x2000ba00 + * LPC17_OHCIRAM_SIZE 1280 + * LPC17_BANK1_HEAPBASE 0x20008000 + * LPC17_BANK1_HEAPSIZE (16384 - 1280) = 15104 + * + * LPC17_HCCA_BASE 0x20083a00 -- Communications area + * LPC17_TDTAIL_ADDR 0x20083b00 -- Common. pre-allocated tail TD + * LPC17_EDCTRL_ADDR 0x20083b20 -- Pre-allocated ED for EP0 + * LPC17_EDFREE_BASE 0x20083b40 -- Free EDs + * LPC17_TDFREE_BASE 0x20083b80 -- Free TDs + * LPC17_TBFREE_BASE 0x20083be0 -- Free request/descriptor buffers + * LPC17_IOFREE_BASE 0x20083d60 -- Free large I/O buffers + * LPC17_IOBUFFERS (0x20084000 - 0x20083d60) / 512 = 672/512 = 1 + * + * Wasted memory: 672-512 = 160 bytes + */ + +#define LPC17_HCCA_BASE (LPC17_OHCIRAM_BASE) +#define LPC17_TDTAIL_ADDR (LPC17_HCCA_BASE + LPC17_HCCA_SIZE) +#define LPC17_EDCTRL_ADDR (LPC17_TDTAIL_ADDR + LPC17_TD_SIZE) +#define LPC17_EDFREE_BASE (LPC17_EDCTRL_ADDR + LPC17_ED_SIZE) +#define LPC17_TDFREE_BASE (LPC17_EDFREE_BASE + LPC17_EDFREE_SIZE) +#define LPC17_TBFREE_BASE (LPC17_TDFREE_BASE + LPC17_TDFREE_SIZE) +#define LPC17_IOFREE_BASE (LPC17_TBFREE_BASE + LPC17_TBFREE_SIZE) + +#if LPC17_IOFREE_BASE > LPC17_OHCIRAM_END +# error "Insufficient OHCI RAM allocated" +#endif + +/* Finally, use the remainder of the allocated OHCI for IO buffers */ + +#if CONFIG_USBHOST_IOBUFSIZE > 0 +# define LPC17_IOBUFFERS ((LPC17_OHCIRAM_END - LPC17_IOFREE_BASE) / CONFIG_USBHOST_IOBUFSIZE) +#else +# define LPC17_IOBUFFERS 0 +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* CONFIG_USBHOST && CONFIG_LPC17_USBHOST && LPC17_NUSBHOST > 0*/ +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_OHCIRAM_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_pinconn.h b/arch/arm/src/lpc17xx/lpc17_pinconn.h index e41bdb8deee4d00e4d60ef59fd66f3e61224656d..c0e0ec91605938dffb2e0a9c4fd7512e8c05497b 100644 --- a/arch/arm/src/lpc17xx/lpc17_pinconn.h +++ b/arch/arm/src/lpc17xx/lpc17_pinconn.h @@ -1,635 +1,635 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_pinconn.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_PINCONN_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_PINCONN_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_PINCONN_PINSEL0_OFFSET 0x0000 /* Pin function select register 0 */ -#define LPC17_PINCONN_PINSEL1_OFFSET 0x0004 /* Pin function select register 1 */ -#define LPC17_PINCONN_PINSEL2_OFFSET 0x0008 /* Pin function select register 2 */ -#define LPC17_PINCONN_PINSEL3_OFFSET 0x000c /* Pin function select register 3 */ -#define LPC17_PINCONN_PINSEL4_OFFSET 0x0010 /* Pin function select register 4 */ -#define LPC17_PINCONN_PINSEL7_OFFSET 0x001c /* Pin function select register 7 */ -#define LPC17_PINCONN_PINSEL8_OFFSET 0x0020 /* Pin function select register 8 */ -#define LPC17_PINCONN_PINSEL9_OFFSET 0x0024 /* Pin function select register 9 */ -#define LPC17_PINCONN_PINSEL10_OFFSET 0x0028 /* Pin function select register 10 */ -#define LPC17_PINCONN_PINMODE0_OFFSET 0x0040 /* Pin mode select register 0 */ -#define LPC17_PINCONN_PINMODE1_OFFSET 0x0044 /* Pin mode select register 1 */ -#define LPC17_PINCONN_PINMODE2_OFFSET 0x0048 /* Pin mode select register 2 */ -#define LPC17_PINCONN_PINMODE3_OFFSET 0x004c /* Pin mode select register 3 */ -#define LPC17_PINCONN_PINMODE4_OFFSET 0x0050 /* Pin mode select register 4 */ -#define LPC17_PINCONN_PINMODE5_OFFSET 0x0054 /* Pin mode select register 5 */ -#define LPC17_PINCONN_PINMODE6_OFFSET 0x0058 /* Pin mode select register 6 */ -#define LPC17_PINCONN_PINMODE7_OFFSET 0x005c /* Pin mode select register 7 */ -#define LPC17_PINCONN_PINMODE9_OFFSET 0x0064 /* Pin mode select register 9 */ -#define LPC17_PINCONN_ODMODE0_OFFSET 0x0068 /* Open drain mode control register 0 */ -#define LPC17_PINCONN_ODMODE1_OFFSET 0x006c /* Open drain mode control register 1 */ -#define LPC17_PINCONN_ODMODE2_OFFSET 0x0070 /* Open drain mode control register 2 */ -#define LPC17_PINCONN_ODMODE3_OFFSET 0x0074 /* Open drain mode control register 3 */ -#define LPC17_PINCONN_ODMODE4_OFFSET 0x0078 /* Open drain mode control register 4 */ -#define LPC17_PINCONN_I2CPADCFG_OFFSET 0x007c /* I2C Pin Configuration register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_PINCONN_PINSEL0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL0_OFFSET) -#define LPC17_PINCONN_PINSEL1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL1_OFFSET) -#define LPC17_PINCONN_PINSEL2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL2_OFFSET) -#define LPC17_PINCONN_PINSEL3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL3_OFFSET) -#define LPC17_PINCONN_PINSEL4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL4_OFFSET) -#define LPC17_PINCONN_PINSEL7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL7_OFFSET) -#define LPC17_PINCONN_PINSEL8 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL8_OFFSET) -#define LPC17_PINCONN_PINSEL9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL9_OFFSET) -#define LPC17_PINCONN_PINSEL10 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL10_OFFSET) -#define LPC17_PINCONN_PINMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE0_OFFSET) -#define LPC17_PINCONN_PINMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE1_OFFSET) -#define LPC17_PINCONN_PINMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE2_OFFSET) -#define LPC17_PINCONN_PINMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE3_OFFSET) -#define LPC17_PINCONN_PINMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE4_OFFSET) -#define LPC17_PINCONN_PINMODE5 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE5_OFFSET) -#define LPC17_PINCONN_PINMODE6 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE6_OFFSET) -#define LPC17_PINCONN_PINMODE7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE7_OFFSET) -#define LPC17_PINCONN_PINMODE9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE9_OFFSET) -#define LPC17_PINCONN_ODMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE0_OFFSET) -#define LPC17_PINCONN_ODMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE1_OFFSET) -#define LPC17_PINCONN_ODMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE2_OFFSET) -#define LPC17_PINCONN_ODMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE3_OFFSET) -#define LPC17_PINCONN_ODMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE4_OFFSET) -#define LPC17_PINCONN_I2CPADCFG (LPC17_PINCONN_BASE+LPC17_PINCONN_I2CPADCFG_OFFSET) - -/* Register bit definitions *********************************************************/ -/* Pin Function Select register 0 (PINSEL0: 0x4002c000) */ - -#define PINCONN_PINSEL_GPIO (0) -#define PINCONN_PINSEL_ALT1 (1) -#define PINCONN_PINSEL_ALT2 (2) -#define PINCONN_PINSEL_ALT3 (3) -#define PINCONN_PINSEL_MASK (3) - -#define PINCONN_PINSELL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ -#define PINCONN_PINSELL_MASK(n) (3 << PINCONN_PINSELL_SHIFT(n)) -#define PINCONN_PINSELH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ -#define PINCONN_PINSELH_MASK(n) (3 << PINCONN_PINSELH_SHIFT(n)) - -#define PINCONN_PINSEL0_P0_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINSEL0_P0_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINSEL0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 00=GPIO 01=RD1 10=TXD3 11=SDA1 */ -#define PINCONN_PINSEL0_P0p0_MASK (3 << PINCONN_PINSEL0_P0p0_SHIFT) -#define PINCONN_PINSEL0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 00=GPIO 01=TD1 10=RXD3 11=SCL1 */ -#define PINCONN_PINSEL0_P0p1_MASK (3 << PINCONN_PINSEL0_P0p1_SHIFT) -#define PINCONN_PINSEL0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 00=GPIO 01=TXD0 10=AD0.7 11=Reserved */ -#define PINCONN_PINSEL0_P0p2_MASK (3 << PINCONN_PINSEL0_P0p2_SHIFT) -#define PINCONN_PINSEL0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 00=GPIO 01=RXD0 10=AD0.6 11=Reserved */ -#define PINCONN_PINSEL0_P0p3_MASK (3 << PINCONN_PINSEL0_P0p3_SHIFT) -#define PINCONN_PINSEL0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 00=GPIO 01=I2SRX_CLK 10=RD2 11=CAP2.0 */ -#define PINCONN_PINSEL0_P0p4_MASK (3 << PINCONN_PINSEL0_P0p4_SHIFT) -#define PINCONN_PINSEL0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 00=GPIO 01=I2SRX_WS 10=TD2 11=CAP2.1 */ -#define PINCONN_PINSEL0_P0p5_MASK (3 << PINCONN_PINSEL0_P0p5_SHIFT) -#define PINCONN_PINSEL0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 00=GPIO 01=I2SRX_SDA 10=SSEL1 11=MAT2.0 */ -#define PINCONN_PINSEL0_P0p6_MASK (3 << PINCONN_PINSEL0_P0p6_SHIFT) -#define PINCONN_PINSEL0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 00=GPIO 01=I2STX_CLK 10=SCK1 11=MAT2.1 */ -#define PINCONN_PINSEL0_P0p7_MASK (3 << PINCONN_PINSEL0_P0p7_SHIFT) -#define PINCONN_PINSEL0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 00=GPIO 01=I2STX_WS 10=MISO1 11=MAT2.2 */ -#define PINCONN_PINSEL0_P0p8_MASK (3 << PINCONN_PINSEL0_P0p8_SHIFT) -#define PINCONN_PINSEL0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 00=GPIO 01=I2STX_SDA 10=MOSI1 11=MAT2.3 */ -#define PINCONN_PINSEL0_P0p9_MASK (3 << PINCONN_PINSEL0_P0p9_SHIFT) -#define PINCONN_PINSEL0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 00=GPIO 01=TXD2 10=SDA2 11=MAT3.0 */ -#define PINCONN_PINSEL0_P0p10_MASK (3 << PINCONN_PINSEL0_P0p10_SHIFT) -#define PINCONN_PINSEL0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 00=GPIO 01=RXD2 10=SCL2 11=MAT3.1 */ -#define PINCONN_PINSEL0_P0p11_MASK (3 << PINCONN_PINSEL0_P0p11_SHIFT) - /* Bits 24-29: Reserved */ -#define PINCONN_PINSEL0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 00=GPIO 01=TXD1 10=SCK0 11=SCK */ -#define PINCONN_PINSEL0_P0p15_MASK (3 << PINCONN_PINSEL0_P0p15_SHIFT) - -/* Pin Function Select Register 1 (PINSEL1: 0x4002c004) */ - -#define PINCONN_PINSEL1_P0_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINSEL1_P0_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINSEL1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 00=GPIO 01=RXD1 10=SSEL0 11=SSEL */ -#define PINCONN_PINSEL1_P0p16_MASK (3 << PINCONN_PINSEL1_P0p16_SHIFT) -#define PINCONN_PINSEL1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 00=GPIO 01=CTS1 10=MISO0 11=MISO */ -#define PINCONN_PINSEL1_P0p17_MASK (3 << PINCONN_PINSEL1_P0p17_SHIFT) -#define PINCONN_PINSEL1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 00=GPIO 01=DCD1 10=MOSI0 11=MOSI */ -#define PINCONN_PINSEL1_P0p18_MASK (3 << PINCONN_PINSEL1_P0p18_SHIFT) -#define PINCONN_PINSEL1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 00=GPIO 01=DSR1 10=Reserved 11=SDA1 */ -#define PINCONN_PINSEL1_P0p19_MASK (3 << PINCONN_PINSEL1_P0p19_SHIFT) -#define PINCONN_PINSEL1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 00=GPIO 01=DTR1 10=Reserved 11=SCL1 */ -#define PINCONN_PINSEL1_P0p20_MASK (3 << PINCONN_PINSEL1_P0p20_SHIFT) -#define PINCONN_PINSEL1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 00=GPIO 01=RI1 10=Reserved 11=RD1 */ -#define PINCONN_PINSEL1_P0p21_MASK (3 << PINCONN_PINSEL1_P0p21_SHIFT) -#define PINCONN_PINSEL1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 00=GPIO 01=RTS1 10=Reserved 11=TD1 */ -#define PINCONN_PINSEL1_P0p22_MASK (3 << PINCONN_PINSEL1_P0p22_SHIFT) -#define PINCONN_PINSEL1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 00=GPIO 01=AD0.0 10=I2SRX_CLK 11=CAP3.0 */ -#define PINCONN_PINSEL1_P0p23_MASK (3 << PINCONN_PINSEL1_P0p23_SHIFT) -#define PINCONN_PINSEL1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 00=GPIO 01=AD0.1 10=I2SRX_WS 11=CAP3.1 */ -#define PINCONN_PINSEL1_P0p24_MASK (3 << PINCONN_PINSEL1_P0p24_SHIFT) -#define PINCONN_PINSEL1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 00=GPIO 01=AD0.2 10=I2SRX_SDA 11=TXD3 */ -#define PINCONN_PINSEL1_P0p25_MASK (3 << PINCONN_PINSEL1_P0p25_SHIFT) -#define PINCONN_PINSEL1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 00=GPIO 01=AD0.3 10=AOUT 11=RXD3 */ -#define PINCONN_PINSEL1_P0p26_MASK (3 << PINCONN_PINSEL1_P0p26_SHIFT) -#define PINCONN_PINSEL1_P0p27_SHIFT (22) /* Bits 22-23: P0.27 00=GPIO 01=SDA0 10=USB_SDA 11=Reserved */ -#define PINCONN_PINSEL1_P0p27_MASK (3 << PINCONN_PINSEL1_P0p27_SHIFT) -#define PINCONN_PINSEL1_P0p28_SHIFT (24) /* Bits 24-25: P0.28 00=GPIO 01=SCL0 10=USB_SCL 11=Reserved */ -#define PINCONN_PINSEL1_P0p28_MASK (3 << PINCONN_PINSEL1_P0p28_SHIFT) -#define PINCONN_PINSEL1_P0p29_SHIFT (26) /* Bits 26-27: P0.29 00=GPIO 01=USB_D+ 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL1_P0p29_MASK (3 << PINCONN_PINSEL1_P0p29_SHIFT) -#define PINCONN_PINSEL1_P0p30_SHIFT (28) /* Bits 28-29: P0.30 00=GPIO 01=USB_D- 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL1_P0p30_MASK (3 << PINCONN_PINSEL1_P0p30_SHIFT) - /* Bits 30-31: Reserved */ -/* Pin Function Select register 2 (PINSEL2: 0x4002c008) */ - -#define PINCONN_PINSEL2_P1_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINSEL2_P1_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINSEL2_P1p0_SHIFT (0) /* Bits 0-1: P1.0 00=GPIO 01=ENET_TXD0 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p0_MASK (3 << PINCONN_PINSEL2_P1p0_SHIFT) -#define PINCONN_PINSEL2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 00=GPIO 01=ENET_TXD1 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p1_MASK (3 << PINCONN_PINSEL2_P1p1_SHIFT) - /* Bits 4-7: Reserved */ -#define PINCONN_PINSEL2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 00=GPIO 01=ENET_TX_EN 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p4_MASK (3 << PINCONN_PINSEL2_P1p4_SHIFT) - /* Bits 10-15: Reserved */ -#define PINCONN_PINSEL2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 00=GPIO 01=ENET_CRS 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p8_MASK (3 << PINCONN_PINSEL2_P1p8_SHIFT) -#define PINCONN_PINSEL2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 00=GPIO 01=ENET_RXD0 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p9_MASK (3 << PINCONN_PINSEL2_P1p9_SHIFT) -#define PINCONN_PINSEL2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 00=GPIO 01=ENET_RXD1 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p10_MASK (3 << PINCONN_PINSEL2_P1p10_SHIFT) - /* Bits 22-27: Reserved */ -#define PINCONN_PINSEL2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 00=GPIO 01=ENET_RX_ER 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p14_MASK (3 << PINCONN_PINSEL2_P1p14_SHIFT) -#define PINCONN_PINSEL2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 00=GPIO 01=ENET_REF_CLK 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL2_P1p15_MASK (3 << PINCONN_PINSEL2_P1p15_SHIFT) - -/* Pin Function Select Register 3 (PINSEL3: 0x4002c00c) */ - -#define PINCONN_PINSEL3_P1_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINSEL3_P1_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINSEL3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 00=GPIO 01=ENET_MDC 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL3_P1p16_MASK (3 << PINCONN_PINSEL3_P1p16_SHIFT) -#define PINCONN_PINSEL3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 00=GPIO 01=ENET_MDIO 10=Reserved 11=Reserved */ -#define PINCONN_PINSEL3_P1p17_MASK (3 << PINCONN_PINSEL3_P1p17_SHIFT) -#define PINCONN_PINSEL3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 00=GPIO 01=USB_UP_LED 10=PWM1.1 11=CAP1.0 */ -#define PINCONN_PINSEL3_P1p18_MASK (3 << PINCONN_PINSEL3_P1p18_SHIFT) -#define PINCONN_PINSEL3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 00=GPIO 01=MCOA0 10=USB_PPWR 11=CAP1.1 */ -#define PINCONN_PINSEL3_P1p19_MASK (3 << PINCONN_PINSEL3_P1p19_SHIFT) -#define PINCONN_PINSEL3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 00=GPIO 01=MCI0 10=PWM1.2 11=SCK0 */ -#define PINCONN_PINSEL3_P1p20_MASK (3 << PINCONN_PINSEL3_P1p20_SHIFT) -#define PINCONN_PINSEL3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 00=GPIO 01=MCABORT 10=PWM1.3 11=SSEL0 */ -#define PINCONN_PINSEL3_P1p21_MASK (3 << PINCONN_PINSEL3_P1p21_SHIFT) -#define PINCONN_PINSEL3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 00=GPIO 01=MCOB0 10=USB_PWRD 11=MAT1.0 */ -#define PINCONN_PINSEL3_P1p22_MASK (3 << PINCONN_PINSEL3_P1p22_SHIFT) -#define PINCONN_PINSEL3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 00=GPIO 01=MCI1 10=PWM1.4 11=MISO0 */ -#define PINCONN_PINSEL3_P1p23_MASK (3 << PINCONN_PINSEL3_P1p23_SHIFT) -#define PINCONN_PINSEL3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 00=GPIO 01=MCI2 10=PWM1.5 11=MOSI0 */ -#define PINCONN_PINSEL3_P1p24_MASK (3 << PINCONN_PINSEL3_P1p24_SHIFT) -#define PINCONN_PINSEL3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 00=GPIO 01=MCOA1 10=Reserved 11=MAT1.1 */ -#define PINCONN_PINSEL3_P1p25_MASK (3 << PINCONN_PINSEL3_P1p25_SHIFT) -#define PINCONN_PINSEL3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 00=GPIO 01=MCOB1 10=PWM1.6 11=CAP0.0 */ -#define PINCONN_PINSEL3_P1p26_MASK (3 << PINCONN_PINSEL3_P1p26_SHIFT) -#define PINCONN_PINSEL3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 00=GPIO 01=CLKOUT 10=USB_OVRCR 11=CAP0.1 */ -#define PINCONN_PINSEL3_P1p27_MASK (3 << PINCONN_PINSEL3_P1p27_SHIFT) -#define PINCONN_PINSEL3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 00=GPIO 01=MCOA2 10=PCAP1.0 11=MAT0.0 */ -#define PINCONN_PINSEL3_P1p28_MASK (3 << PINCONN_PINSEL3_P1p28_SHIFT) -#define PINCONN_PINSEL3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 00=GPIO 01=MCOB2 10=PCAP1.1 11=MAT0.1 */ -#define PINCONN_PINSEL3_P1p29_MASK (3 << PINCONN_PINSEL3_P1p29_SHIFT) -#define PINCONN_PINSEL3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 00=GPIO 01=Reserved 10=VBUS 11=AD0.4 */ -#define PINCONN_PINSEL3_P1p30_MASK (3 << PINCONN_PINSEL3_P1p30_SHIFT) -#define PINCONN_PINSEL3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 00=GPIO 01=Reserved 10=SCK1 11=AD0.5 */ -#define PINCONN_PINSEL3_P1p31_MASK (3 << PINCONN_PINSEL3_P1p31_SHIFT) - -/* Pin Function Select Register 4 (PINSEL4: 0x4002c010) */ - -#define PINCONN_PINSEL4_P2_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINSEL4_P2_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINSEL4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 00=GPIO 01=PWM1.1 10=TXD1 11=Reserved */ -#define PINCONN_PINSEL4_P2p0_MASK (3 << PINCONN_PINSEL4_P2p0_SHIFT) -#define PINCONN_PINSEL4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 00=GPIO 01=PWM1.2 10=RXD1 11=Reserved */ -#define PINCONN_PINSEL4_P2p1_MASK (3 << PINCONN_PINSEL4_P2p1_SHIFT) -#define PINCONN_PINSEL4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 00=GPIO 01=PWM1.3 10=CTS1 11=Reserved */ -#define PINCONN_PINSEL4_P2p2_MASK (3 << PINCONN_PINSEL4_P2p2_SHIFT) -#define PINCONN_PINSEL4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 00=GPIO 01=PWM1.4 10=DCD1 11=Reserved */ -#define PINCONN_PINSEL4_P2p3_MASK (3 << PINCONN_PINSEL4_P2p3_SHIFT) -#define PINCONN_PINSEL4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 00=GPIO 01=PWM1.5 10=DSR1 11=Reserved */ -#define PINCONN_PINSEL4_P2p4_MASK (3 << PINCONN_PINSEL4_P2p4_SHIFT) -#define PINCONN_PINSEL4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 00=GPIO 01=PWM1.6 10=DTR1 11=Reserved */ -#define PINCONN_PINSEL4_P2p5_MASK (3 << PINCONN_PINSEL4_P2p5_SHIFT) -#define PINCONN_PINSEL4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 00=GPIO 01=PCAP1.0 10=RI1 11=Reserved */ -#define PINCONN_PINSEL4_P2p6_MASK (3 << PINCONN_PINSEL4_P2p6_SHIFT) -#define PINCONN_PINSEL4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 00=GPIO 01=RD2 10=RTS1 11=Reserved */ -#define PINCONN_PINSEL4_P2p7_MASK (3 << PINCONN_PINSEL4_P2p7_SHIFT) -#define PINCONN_PINSEL4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 00=GPIO 01=TD2 10=TXD2 11=ENET_MDC */ -#define PINCONN_PINSEL4_P2p8_MASK (3 << PINCONN_PINSEL4_P2p8_SHIFT) -#define PINCONN_PINSEL4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 00=GPIO 01=USB_CONNECT 10=RXD2 11=ENET_MDIO */ -#define PINCONN_PINSEL4_P2p9_MASK (3 << PINCONN_PINSEL4_P2p9_SHIFT) -#define PINCONN_PINSEL4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 00=GPIO 01=EINT0 10=NMI 11=Reserved */ -#define PINCONN_PINSEL4_P2p10_MASK (3 << PINCONN_PINSEL4_P2p10_SHIFT) -#define PINCONN_PINSEL4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 00=GPIO 01=EINT1 10=Reserved 11=I2STX_CLK */ -#define PINCONN_PINSEL4_P2p11_MASK (3 << PINCONN_PINSEL4_P2p11_SHIFT) -#define PINCONN_PINSEL4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 00=GPIO 01=PEINT2 10=Reserved 11=I2STX_WS */ -#define PINCONN_PINSEL4_P2p12_MASK (3 << PINCONN_PINSEL4_P2p12_SHIFT) -#define PINCONN_PINSEL4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 00=GPIO 01=EINT3 10=Reserved 11=I2STX_SDA */ -#define PINCONN_PINSEL4_P2p13_MASK (3 << PINCONN_PINSEL4_P2p13_SHIFT) - /* Bits 28-31: Reserved */ -/* Pin Function Select Register 7 (PINSEL7: 0x4002c01c) */ - -#define PINCONN_PINSEL7_P3_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINSEL7_P3_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ - - /* Bits 0-17: Reserved */ -#define PINCONN_PINSEL7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 00=GPIO 01=Reserved 10=MAT0.0 11=PWM1.2 */ -#define PINCONN_PINSEL7_P3p25_MASK (3 << PINCONN_PINSEL7_P3p25_SHIFT) -#define PINCONN_PINSEL7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 00=GPIO 01=STCLK 10=MAT0.1 11=PWM1.3 */ -#define PINCONN_PINSEL7_P3p26_MASK (3 << PINCONN_PINSEL7_P3p26_SHIFT) - /* Bits 22-31: Reserved */ - -/* Pin Function Select Register 8 (PINSEL8: 0x4002c020) */ -/* No description of bits -- Does this register exist? */ - -/* Pin Function Select Register 9 (PINSEL9: 0x4002c024) */ - -#define PINCONN_PINSEL9_P4_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINSEL9_P4_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ - - /* Bits 0-23: Reserved */ -#define PINCONN_PINSEL9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 00=GPIO 01=RX_MCLK 10=MAT2.0 11=TXD3 */ -#define PINCONN_PINSEL9_P4p28_MASK (3 << PINCONN_PINSEL9_P4p28_SHIFT) -#define PINCONN_PINSEL9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 00=GPIO 01=TX_MCLK 10=MAT2.1 11=RXD3 */ -#define PINCONN_PINSEL9_P4p29_MASK (3 << PINCONN_PINSEL9_P4p29_SHIFT) - /* Bits 28-31: Reserved */ -/* Pin Function Select Register 10 (PINSEL10: 0x4002c028) */ - /* Bits 0-2: Reserved */ -#define PINCONN_PINSEL10_TPIU (1 << 3) /* Bit 3: 0=TPIU interface disabled; 1=TPIU interface enabled */ - /* Bits 4-31: Reserved */ -/* Pin Mode select register 0 (PINMODE0: 0x4002c040) */ - -#define PINCONN_PINMODE_PU (0) /* 00: pin has a pull-up resistor enabled */ -#define PINCONN_PINMODE_RM (1) /* 01: pin has repeater mode enabled */ -#define PINCONN_PINMODE_FLOAT (2) /* 10: pin has neither pull-up nor pull-down */ -#define PINCONN_PINMODE_PD (3) /* 11: pin has a pull-down resistor enabled */ -#define PINCONN_PINMODE_MASK (3) - -#define PINCONN_PINMODEL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ -#define PINCONN_PINMODEL_MASK(n) (3 << PINCONN_PINMODEL_SHIFT(n)) -#define PINCONN_PINMODEH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ -#define PINCONN_PINMODEH_MASK(n) (3 << PINCONN_PINMODEH_SHIFT(n)) - -#define PINCONN_PINMODE0_P0_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINMODE0_P0_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINMODE0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 mode control */ -#define PINCONN_PINMODE0_P0p0_MASK (3 << PINCONN_PINMODE0_P0p0_SHIFT) -#define PINCONN_PINMODE0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 mode control */ -#define PINCONN_PINMODE0_P0p1_MASK (3 << PINCONN_PINMODE0_P0p1_SHIFT) -#define PINCONN_PINMODE0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 mode control */ -#define PINCONN_PINMODE0_P0p2_MASK (3 << PINCONN_PINMODE0_P0p2_SHIFT) -#define PINCONN_PINMODE0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 mode control */ -#define PINCONN_PINMODE0_P0p3_MASK (3 << PINCONN_PINMODE0_P0p3_SHIFT) -#define PINCONN_PINMODE0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 mode control */ -#define PINCONN_PINMODE0_P0p4_MASK (3 << PINCONN_PINMODE0_P0p4_SHIFT) -#define PINCONN_PINMODE0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 mode control */ -#define PINCONN_PINMODE0_P0p5_MASK (3 << PINCONN_PINMODE0_P0p5_SHIFT) -#define PINCONN_PINMODE0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 mode control */ -#define PINCONN_PINMODE0_P0p6_MASK (3 << PINCONN_PINMODE0_P0p6_SHIFT) -#define PINCONN_PINMODE0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 mode control */ -#define PINCONN_PINMODE0_P0p7_MASK (3 << PINCONN_PINMODE0_P0p7_SHIFT) -#define PINCONN_PINMODE0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 mode control */ -#define PINCONN_PINMODE0_P0p8_MASK (3 << PINCONN_PINMODE0_P0p8_SHIFT) -#define PINCONN_PINMODE0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 mode control */ -#define PINCONN_PINMODE0_P0p9_MASK (3 << PINCONN_PINMODE0_P0p9_SHIFT) -#define PINCONN_PINMODE0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 mode control */ -#define PINCONN_PINMODE0_P0p10_MASK (3 << PINCONN_PINMODE0_P0p10_SHIFT) -#define PINCONN_PINMODE0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 mode control */ -#define PINCONN_PINMODE0_P0p11_MASK (3 << PINCONN_PINMODE0_P0p11_SHIFT) - /* Bits 24-29: Reserved */ -#define PINCONN_PINMODE0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 mode control */ -#define PINCONN_PINMODE0_P0p15_MASK (3 << PINCONN_PINMODE0_P0p15_SHIFT) - -/* Pin Mode select register 1 (PINMODE1: 0x4002c044) */ - -#define PINCONN_PINMODE1_P0_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE1_P0_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINMODE1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 mode control */ -#define PINCONN_PINMODE1_P0p16_MASK (3 << PINCONN_PINMODE1_P0p16_SHIFT) -#define PINCONN_PINMODE1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 mode control */ -#define PINCONN_PINMODE1_P0p17_MASK (3 << PINCONN_PINMODE1_P0p17_SHIFT) -#define PINCONN_PINMODE1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 mode control */ -#define PINCONN_PINMODE1_P0p18_MASK (3 << PINCONN_PINMODE1_P0p18_SHIFT) -#define PINCONN_PINMODE1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 mode control */ -#define PINCONN_PINMODE1_P0p19_MASK (3 << PINCONN_PINMODE1_P0p19_SHIFT) -#define PINCONN_PINMODE1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 mode control */ -#define PINCONN_PINMODE1_P0p20_MASK (3 << PINCONN_PINMODE1_P0p20_SHIFT) -#define PINCONN_PINMODE1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 mode control */ -#define PINCONN_PINMODE1_P0p21_MASK (3 << PINCONN_PINMODE1_P0p21_SHIFT) -#define PINCONN_PINMODE1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 mode control */ -#define PINCONN_PINMODE1_P0p22_MASK (3 << PINCONN_PINMODE1_P0p22_SHIFT) -#define PINCONN_PINMODE1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 mode control */ -#define PINCONN_PINMODE1_P0p23_MASK (3 << PINCONN_PINMODE1_P0p23_SHIFT) -#define PINCONN_PINMODE1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 mode control */ -#define PINCONN_PINMODE1_P0p24_MASK (3 << PINCONN_PINMODE1_P0p24_SHIFT) -#define PINCONN_PINMODE1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 mode control */ -#define PINCONN_PINMODE1_P0p25_MASK (3 << PINCONN_PINMODE1_P0p25_SHIFT) -#define PINCONN_PINMODE1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 mode control */ -#define PINCONN_PINMODE1_P0p26_MASK (3 << PINCONN_PINMODE1_P0p26_SHIFT) - /* Bits 22-31: Reserved */ - -/* Pin Mode select register 2 (PINMODE2: 0x4002c048) */ - -#define PINCONN_PINMODE2_P1_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINMODE2_P1_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINMODE2_P1p0_SHIFT (0) /* Bits 2-1: P1.0 mode control */ -#define PINCONN_PINMODE2_P1p0_MASK (3 << PINCONN_PINMODE2_P1p0_SHIFT) -#define PINCONN_PINMODE2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 mode control */ -#define PINCONN_PINMODE2_P1p1_MASK (3 << PINCONN_PINMODE2_P1p1_SHIFT) - /* Bits 4-7: Reserved */ -#define PINCONN_PINMODE2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 mode control */ -#define PINCONN_PINMODE2_P1p4_MASK (3 << PINCONN_PINMODE2_P1p4_SHIFT) - /* Bits 10-15: Reserved */ -#define PINCONN_PINMODE2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 mode control */ -#define PINCONN_PINMODE2_P1p8_MASK (3 << PINCONN_PINMODE2_P1p8_SHIFT) -#define PINCONN_PINMODE2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 mode control */ -#define PINCONN_PINMODE2_P1p9_MASK (3 << PINCONN_PINMODE2_P1p9_SHIFT) -#define PINCONN_PINMODE2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 mode control */ -#define PINCONN_PINMODE2_P1p10_MASK (3 << PINCONN_PINMODE2_P1p10_SHIFT) - /* Bits 22-27: Reserved */ -#define PINCONN_PINMODE2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 mode control */ -#define PINCONN_PINMODE2_P1p14_MASK (3 << PINCONN_PINMODE2_P1p14_SHIFT) -#define PINCONN_PINMODE2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 mode control */ -#define PINCONN_PINMODE2_P1p15_MASK (3 << PINCONN_PINMODE2_P1p15_SHIFT) - -/* Pin Mode select register 3 (PINMODE3: 0x4002c04c) */ - -#define PINCONN_PINMODE3_P1_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE3_P1_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINMODE3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 mode control */ -#define PINCONN_PINMODE3_P1p16_MASK (3 << PINCONN_PINMODE3_P1p16_SHIFT) -#define PINCONN_PINMODE3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 mode control */ -#define PINCONN_PINMODE3_P1p17_MASK (3 << PINCONN_PINMODE3_P1p17_SHIFT) -#define PINCONN_PINMODE3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 mode control */ -#define PINCONN_PINMODE3_P1p18_MASK (3 << PINCONN_PINMODE3_P1p18_SHIFT) -#define PINCONN_PINMODE3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 mode control */ -#define PINCONN_PINMODE3_P1p19_MASK (3 << PINCONN_PINMODE3_P1p19_SHIFT) -#define PINCONN_PINMODE3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 mode control */ -#define PINCONN_PINMODE3_P1p20_MASK (3 << PINCONN_PINMODE3_P1p20_SHIFT) -#define PINCONN_PINMODE3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 mode control */ -#define PINCONN_PINMODE3_P1p21_MASK (3 << PINCONN_PINMODE3_P1p21_SHIFT) -#define PINCONN_PINMODE3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 mode control */ -#define PINCONN_PINMODE3_P1p22_MASK (3 << PINCONN_PINMODE3_P1p22_SHIFT) -#define PINCONN_PINMODE3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 mode control */ -#define PINCONN_PINMODE3_P1p23_MASK (3 << PINCONN_PINMODE3_P1p23_SHIFT) -#define PINCONN_PINMODE3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 mode control */ -#define PINCONN_PINMODE3_P1p24_MASK (3 << PINCONN_PINMODE3_P1p24_SHIFT) -#define PINCONN_PINMODE3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 mode control */ -#define PINCONN_PINMODE3_P1p25_MASK (3 << PINCONN_PINMODE3_P1p25_SHIFT) -#define PINCONN_PINMODE3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 mode control */ -#define PINCONN_PINMODE3_P1p26_MASK (3 << PINCONN_PINMODE3_P1p26_SHIFT) -#define PINCONN_PINMODE3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 mode control */ -#define PINCONN_PINMODE3_P1p27_MASK (3 << PINCONN_PINMODE3_P1p27_SHIFT) -#define PINCONN_PINMODE3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 mode control */ -#define PINCONN_PINMODE3_P1p28_MASK (3 << PINCONN_PINMODE3_P1p28_SHIFT) -#define PINCONN_PINMODE3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 mode control */ -#define PINCONN_PINMODE3_P1p29_MASK (3 << PINCONN_PINMODE3_P1p29_SHIFT) -#define PINCONN_PINMODE3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 mode control */ -#define PINCONN_PINMODE3_P1p30_MASK (3 << PINCONN_PINMODE3_P1p30_SHIFT) -#define PINCONN_PINMODE3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 mode control */ -#define PINCONN_PINMODE3_P1p31_MASK (3 << PINCONN_PINMODE3_P1p31_SHIFT) - -/* Pin Mode select register 4 (PINMODE4: 0x4002c050) */ - -#define PINCONN_PINMODE4_P2_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINMODE4_P2_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ - -#define PINCONN_PINMODE4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 mode control */ -#define PINCONN_PINMODE4_P2p0_MASK (3 << PINCONN_PINMODE4_P2p0_SHIFT) -#define PINCONN_PINMODE4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 mode control */ -#define PINCONN_PINMODE4_P2p1_MASK (3 << PINCONN_PINMODE4_P2p1_SHIFT) -#define PINCONN_PINMODE4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 mode control */ -#define PINCONN_PINMODE4_P2p2_MASK (3 << PINCONN_PINMODE4_P2p2_SHIFT) -#define PINCONN_PINMODE4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 mode control */ -#define PINCONN_PINMODE4_P2p3_MASK (3 << PINCONN_PINMODE4_P2p3_SHIFT) -#define PINCONN_PINMODE4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 mode control */ -#define PINCONN_PINMODE4_P2p4_MASK (3 << PINCONN_PINMODE4_P2p4_SHIFT) -#define PINCONN_PINMODE4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 mode control */ -#define PINCONN_PINMODE4_P2p5_MASK (3 << PINCONN_PINMODE4_P2p5_SHIFT) -#define PINCONN_PINMODE4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 mode control */ -#define PINCONN_PINMODE4_P2p6_MASK (3 << PINCONN_PINMODE4_P2p6_SHIFT) -#define PINCONN_PINMODE4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 mode control */ -#define PINCONN_PINMODE4_P2p7_MASK (3 << PINCONN_PINMODE4_P2p7_SHIFT) -#define PINCONN_PINMODE4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 mode control */ -#define PINCONN_PINMODE4_P2p8_MASK (3 << PINCONN_PINMODE4_P2p8_SHIFT) -#define PINCONN_PINMODE4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 mode control */ -#define PINCONN_PINMODE4_P2p9_MASK (3 << PINCONN_PINMODE4_P2p9_SHIFT) -#define PINCONN_PINMODE4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 mode control */ -#define PINCONN_PINMODE4_P2p10_MASK (3 << PINCONN_PINMODE4_P2p10_SHIFT) -#define PINCONN_PINMODE4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 mode control */ -#define PINCONN_PINMODE4_P2p11_MASK (3 << PINCONN_PINMODE4_P2p11_SHIFT) -#define PINCONN_PINMODE4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 mode control */ -#define PINCONN_PINMODE4_P2p12_MASK (3 << PINCONN_PINMODE4_P2p12_SHIFT) -#define PINCONN_PINMODE4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 mode control */ -#define PINCONN_PINMODE4_P2p13_MASK (3 << PINCONN_PINMODE4_P2p13_SHIFT) - /* Bits 28-31: Reserved */ -/* Pin Mode select register 5 (PINMODE5: 0x4002c054) - * Pin Mode select register 6 (PINMODE6: 0x4002c058) - * No bit definitions -- do these registers exist? - */ - -#define PINCONN_PINMODE5_P2_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE5_P2_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - -#define PINCONN_PINMODE6_P3_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ -#define PINCONN_PINMODE6_P3_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ - -/* Pin Mode select register 7 (PINMODE7: 0x4002c05c) */ - -#define PINCONN_PINMODE7_P3_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE7_P3_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - /* Bits 0-17: Reserved */ -#define PINCONN_PINMODE7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 mode control */ -#define PINCONN_PINMODE7_P3p25_MASK (3 << PINCONN_PINMODE7_P3p25_SHIFT) -#define PINCONN_PINMODE7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 mode control */ -#define PINCONN_PINMODE7_P3p26_MASK (3 << PINCONN_PINMODE7_P3p26_SHIFT) - /* Bits 22-31: Reserved */ -/* Pin Mode select register 9 (PINMODE9: 0x4002c064) */ - -#define PINCONN_PINMODE9_P4_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ -#define PINCONN_PINMODE9_P4_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ - /* Bits 0-23: Reserved */ -#define PINCONN_PINMODE9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 mode control */ -#define PINCONN_PINMODE9_P4p28_MASK (3 << PINCONN_PINMODE9_P4p28_SHIFT) -#define PINCONN_PINMODE9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 mode control */ -#define PINCONN_PINMODE9_P4p29_MASK (3 << PINCONN_PINMODE9_P4p29_SHIFT) - /* Bits 28-31: Reserved */ -/* Open Drain Pin Mode select register 0 (PINMODE_OD0: 0x4002c068) */ - -#define PINCONN_ODMODE0_P0(n) (1 << (n)) - -#define PINCONN_ODMODE0_P0p0 (1 << 0) /* Bit 0: P0.0 open drain mode */ -#define PINCONN_ODMODE0_P0p1 (1 << 1) /* Bit 1: P0.1 open drain mode */ -#define PINCONN_ODMODE0_P0p2 (1 << 2) /* Bit 2: P0.2 open drain mode */ -#define PINCONN_ODMODE0_P0p3 (1 << 3) /* Bit 3: P0.3 open drain mode */ -#define PINCONN_ODMODE0_P0p4 (1 << 4) /* Bit 4: P0.4 open drain mode */ -#define PINCONN_ODMODE0_P0p5 (1 << 5) /* Bit 5: P0.5 open drain mode */ -#define PINCONN_ODMODE0_P0p6 (1 << 6) /* Bit 6: P0.6 open drain mode */ -#define PINCONN_ODMODE0_P0p7 (1 << 7) /* Bit 7: P0.7 open drain mode */ -#define PINCONN_ODMODE0_P0p8 (1 << 8) /* Bit 8: P0.8 open drain mode */ -#define PINCONN_ODMODE0_P0p9 (1 << 9) /* Bit 9: P0.9 open drain mode */ -#define PINCONN_ODMODE0_P0p10 (1 << 10) /* Bit 10: P0.10 open drain mode */ -#define PINCONN_ODMODE0_P0p11 (1 << 11) /* Bit 11: P0.11 open drain mode */ - /* Bits 12-14: Reserved */ -#define PINCONN_ODMODE0_P0p15 (1 << 15) /* Bit 15: P0.15 open drain mode */ -#define PINCONN_ODMODE0_P0p16 (1 << 16) /* Bit 16: P0.16 open drain mode */ -#define PINCONN_ODMODE0_P0p17 (1 << 17) /* Bit 17: P0.17 open drain mode */ -#define PINCONN_ODMODE0_P0p18 (1 << 18) /* Bit 18: P0.18 open drain mode */ -#define PINCONN_ODMODE0_P0p19 (1 << 19) /* Bit 19: P0.19 open drain mode */ -#define PINCONN_ODMODE0_P0p20 (1 << 20) /* Bit 20: P0.20 open drain mode */ -#define PINCONN_ODMODE0_P0p21 (1 << 21) /* Bit 21: P0.21 open drain mode */ -#define PINCONN_ODMODE0_P0p22 (1 << 22) /* Bit 22: P0.22 open drain mode */ -#define PINCONN_ODMODE0_P0p23 (1 << 23) /* Bit 23: P0.23 open drain mode */ -#define PINCONN_ODMODE0_P0p24 (1 << 24) /* Bit 24: P0.24 open drain mode */ -#define PINCONN_ODMODE0_P0p25 (1 << 25) /* Bit 25: P0.25 open drain mode */ -#define PINCONN_ODMODE0_P0p26 (1 << 25) /* Bit 26: P0.26 open drain mode */ - /* Bits 27-28: Reserved */ -#define PINCONN_ODMODE0_P0p29 (1 << 29) /* Bit 29: P0.29 open drain mode */ -#define PINCONN_ODMODE0_P0p30 (1 << 30) /* Bit 30: P0.30 open drain mode */ - /* Bit 31: Reserved */ -/* Open Drain Pin Mode select register 1 (PINMODE_OD1: 0x4002c06c) */ - -#define PINCONN_ODMODE1_P1(n) (1 << (n)) - -#define PINCONN_ODMODE1_P1p0 (1 << 0) /* Bit 0: P1.0 open drain mode */ -#define PINCONN_ODMODE1_P1p1 (1 << 1) /* Bit 1: P1.1 open drain mode */ - /* Bits 2-3: Reserved */ -#define PINCONN_ODMODE1_P1p4 (1 << 4) /* Bit 4: P1.4 open drain mode */ - /* Bits 5-7: Reserved */ -#define PINCONN_ODMODE1_P1p8 (1 << 8) /* Bit 8: P1.8 open drain mode */ -#define PINCONN_ODMODE1_P1p9 (1 << 9) /* Bit 9: P1.9 open drain mode */ -#define PINCONN_ODMODE1_P1p10 (1 << 10) /* Bit 10: P1.10 open drain mode */ - /* Bits 11-13: Reserved */ -#define PINCONN_ODMODE1_P1p14 (1 << 14) /* Bit 14: P1.14 open drain mode */ -#define PINCONN_ODMODE1_P1p15 (1 << 15) /* Bit 15: P1.15 open drain mode */ -#define PINCONN_ODMODE1_P1p16 (1 << 16) /* Bit 16: P1.16 open drain mode */ -#define PINCONN_ODMODE1_P1p17 (1 << 17) /* Bit 17: P1.17 open drain mode */ -#define PINCONN_ODMODE1_P1p18 (1 << 18) /* Bit 18: P1.18 open drain mode */ -#define PINCONN_ODMODE1_P1p19 (1 << 19) /* Bit 19: P1.19 open drain mode */ -#define PINCONN_ODMODE1_P1p20 (1 << 20) /* Bit 20: P1.20 open drain mode */ -#define PINCONN_ODMODE1_P1p21 (1 << 21) /* Bit 21: P1.21 open drain mode */ -#define PINCONN_ODMODE1_P1p22 (1 << 22) /* Bit 22: P1.22 open drain mode */ -#define PINCONN_ODMODE1_P1p23 (1 << 23) /* Bit 23: P1.23 open drain mode */ -#define PINCONN_ODMODE1_P1p24 (1 << 24) /* Bit 24: P1.24 open drain mode */ -#define PINCONN_ODMODE1_P1p25 (1 << 25) /* Bit 25: P1.25 open drain mode */ -#define PINCONN_ODMODE1_P1p26 (1 << 25) /* Bit 26: P1.26 open drain mode */ -#define PINCONN_ODMODE1_P1p27 (1 << 27) /* Bit 27: P1.27 open drain mode */ -#define PINCONN_ODMODE1_P1p28 (1 << 28) /* Bit 28: P1.28 open drain mode */ -#define PINCONN_ODMODE1_P1p29 (1 << 29) /* Bit 29: P1.29 open drain mode */ -#define PINCONN_ODMODE1_P1p30 (1 << 30) /* Bit 30: P1.30 open drain mode */ -#define PINCONN_ODMODE1_P1p31 (1 << 31) /* Bit 31: P1.31 open drain mode */ - -/* Open Drain Pin Mode select register 2 (PINMODE_OD2: 0x4002c070) */ - -#define PINCONN_ODMODE2_P2(n) (1 << (n)) - -#define PINCONN_ODMODE2_P2p0 (1 << 0) /* Bit 0: P2.0 open drain mode */ -#define PINCONN_ODMODE2_P2p1 (1 << 1) /* Bit 1: P2.1 open drain mode */ -#define PINCONN_ODMODE2_P2p2 (1 << 2) /* Bit 2: P2.2 open drain mode */ -#define PINCONN_ODMODE2_P2p3 (1 << 3) /* Bit 3: P2.3 open drain mode */ -#define PINCONN_ODMODE2_P2p4 (1 << 4) /* Bit 4: P2.4 open drain mode */ -#define PINCONN_ODMODE2_P2p5 (1 << 5) /* Bit 5: P2.5 open drain mode */ -#define PINCONN_ODMODE2_P2p6 (1 << 6) /* Bit 6: P2.6 open drain mode */ -#define PINCONN_ODMODE2_P2p7 (1 << 7) /* Bit 7: P2.7 open drain mode */ -#define PINCONN_ODMODE2_P2p8 (1 << 8) /* Bit 8: P2.8 open drain mode */ -#define PINCONN_ODMODE2_P2p9 (1 << 9) /* Bit 9: P2.9 open drain mode */ -#define PINCONN_ODMODE2_P2p10 (1 << 10) /* Bit 10: P2.10 open drain mode */ -#define PINCONN_ODMODE2_P2p11 (1 << 11) /* Bit 11: P2.11 open drain mode */ -#define PINCONN_ODMODE2_P2p12 (1 << 12) /* Bit 12: P2.12 open drain mode */ -#define PINCONN_ODMODE2_P2p13 (1 << 13) /* Bit 13: P2.13 open drain mode */ - /* Bits 14-31: Reserved */ -/* Open Drain Pin Mode select register 3 (PINMODE_OD3: 0x4002c074) */ - -#define PINCONN_ODMODE3_P3(n) (1 << (n)) - /* Bits 0-24: Reserved */ -#define PINCONN_ODMODE3_P3p25 (1 << 25) /* Bit 25: P3.25 open drain mode */ -#define PINCONN_ODMODE3_P3p26 (1 << 25) /* Bit 26: P3.26 open drain mode */ - /* Bits 17-31: Reserved */ -/* Open Drain Pin Mode select register 4 (PINMODE_OD4: 0x4002c078) */ - -#define PINCONN_ODMODE4_P4(n) (1 << (n)) - /* Bits 0-27: Reserved */ -#define PINCONN_ODMODE4_P4p28 (1 << 28) /* Bit 28: P4.28 open drain mode */ -#define PINCONN_ODMODE4_P4p29 (1 << 29) /* Bit 29: P4.29 open drain mode */ - /* Bits 30-31: Reserved */ -/* I2C Pin Configuration register (I2CPADCFG: 0x4002c07c) */ - -#define PINCONN_I2CPADCFG_SDADRV0 (1 << 0) /* Bit 0: SDA0 pin, P0.27 in Fast Mode Plus */ -#define PINCONN_I2CPADCFG_SDAI2C0 (1 << 1) /* Bit 1: SDA0 pin, P0.27 I2C glitch - * filtering/slew rate control */ -#define PINCONN_I2CPADCFG_SCLDRV0 (1 << 2) /* Bit 2: SCL0 pin, P0.28 in Fast Mode Plus */ -#define PINCONN_I2CPADCFG_SCLI2C0 (1 << 3) /* Bit 3: SCL0 pin, P0.28 I2C glitch - * filtering/slew rate control */ - /* Bits 4-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_PINCONN_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_pinconn.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_PINCONN_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_PINCONN_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_PINCONN_PINSEL0_OFFSET 0x0000 /* Pin function select register 0 */ +#define LPC17_PINCONN_PINSEL1_OFFSET 0x0004 /* Pin function select register 1 */ +#define LPC17_PINCONN_PINSEL2_OFFSET 0x0008 /* Pin function select register 2 */ +#define LPC17_PINCONN_PINSEL3_OFFSET 0x000c /* Pin function select register 3 */ +#define LPC17_PINCONN_PINSEL4_OFFSET 0x0010 /* Pin function select register 4 */ +#define LPC17_PINCONN_PINSEL7_OFFSET 0x001c /* Pin function select register 7 */ +#define LPC17_PINCONN_PINSEL8_OFFSET 0x0020 /* Pin function select register 8 */ +#define LPC17_PINCONN_PINSEL9_OFFSET 0x0024 /* Pin function select register 9 */ +#define LPC17_PINCONN_PINSEL10_OFFSET 0x0028 /* Pin function select register 10 */ +#define LPC17_PINCONN_PINMODE0_OFFSET 0x0040 /* Pin mode select register 0 */ +#define LPC17_PINCONN_PINMODE1_OFFSET 0x0044 /* Pin mode select register 1 */ +#define LPC17_PINCONN_PINMODE2_OFFSET 0x0048 /* Pin mode select register 2 */ +#define LPC17_PINCONN_PINMODE3_OFFSET 0x004c /* Pin mode select register 3 */ +#define LPC17_PINCONN_PINMODE4_OFFSET 0x0050 /* Pin mode select register 4 */ +#define LPC17_PINCONN_PINMODE5_OFFSET 0x0054 /* Pin mode select register 5 */ +#define LPC17_PINCONN_PINMODE6_OFFSET 0x0058 /* Pin mode select register 6 */ +#define LPC17_PINCONN_PINMODE7_OFFSET 0x005c /* Pin mode select register 7 */ +#define LPC17_PINCONN_PINMODE9_OFFSET 0x0064 /* Pin mode select register 9 */ +#define LPC17_PINCONN_ODMODE0_OFFSET 0x0068 /* Open drain mode control register 0 */ +#define LPC17_PINCONN_ODMODE1_OFFSET 0x006c /* Open drain mode control register 1 */ +#define LPC17_PINCONN_ODMODE2_OFFSET 0x0070 /* Open drain mode control register 2 */ +#define LPC17_PINCONN_ODMODE3_OFFSET 0x0074 /* Open drain mode control register 3 */ +#define LPC17_PINCONN_ODMODE4_OFFSET 0x0078 /* Open drain mode control register 4 */ +#define LPC17_PINCONN_I2CPADCFG_OFFSET 0x007c /* I2C Pin Configuration register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_PINCONN_PINSEL0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL0_OFFSET) +#define LPC17_PINCONN_PINSEL1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL1_OFFSET) +#define LPC17_PINCONN_PINSEL2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL2_OFFSET) +#define LPC17_PINCONN_PINSEL3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL3_OFFSET) +#define LPC17_PINCONN_PINSEL4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL4_OFFSET) +#define LPC17_PINCONN_PINSEL7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL7_OFFSET) +#define LPC17_PINCONN_PINSEL8 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL8_OFFSET) +#define LPC17_PINCONN_PINSEL9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL9_OFFSET) +#define LPC17_PINCONN_PINSEL10 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINSEL10_OFFSET) +#define LPC17_PINCONN_PINMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE0_OFFSET) +#define LPC17_PINCONN_PINMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE1_OFFSET) +#define LPC17_PINCONN_PINMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE2_OFFSET) +#define LPC17_PINCONN_PINMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE3_OFFSET) +#define LPC17_PINCONN_PINMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE4_OFFSET) +#define LPC17_PINCONN_PINMODE5 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE5_OFFSET) +#define LPC17_PINCONN_PINMODE6 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE6_OFFSET) +#define LPC17_PINCONN_PINMODE7 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE7_OFFSET) +#define LPC17_PINCONN_PINMODE9 (LPC17_PINCONN_BASE+LPC17_PINCONN_PINMODE9_OFFSET) +#define LPC17_PINCONN_ODMODE0 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE0_OFFSET) +#define LPC17_PINCONN_ODMODE1 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE1_OFFSET) +#define LPC17_PINCONN_ODMODE2 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE2_OFFSET) +#define LPC17_PINCONN_ODMODE3 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE3_OFFSET) +#define LPC17_PINCONN_ODMODE4 (LPC17_PINCONN_BASE+LPC17_PINCONN_ODMODE4_OFFSET) +#define LPC17_PINCONN_I2CPADCFG (LPC17_PINCONN_BASE+LPC17_PINCONN_I2CPADCFG_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Pin Function Select register 0 (PINSEL0: 0x4002c000) */ + +#define PINCONN_PINSEL_GPIO (0) +#define PINCONN_PINSEL_ALT1 (1) +#define PINCONN_PINSEL_ALT2 (2) +#define PINCONN_PINSEL_ALT3 (3) +#define PINCONN_PINSEL_MASK (3) + +#define PINCONN_PINSELL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ +#define PINCONN_PINSELL_MASK(n) (3 << PINCONN_PINSELL_SHIFT(n)) +#define PINCONN_PINSELH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ +#define PINCONN_PINSELH_MASK(n) (3 << PINCONN_PINSELH_SHIFT(n)) + +#define PINCONN_PINSEL0_P0_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINSEL0_P0_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINSEL0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 00=GPIO 01=RD1 10=TXD3 11=SDA1 */ +#define PINCONN_PINSEL0_P0p0_MASK (3 << PINCONN_PINSEL0_P0p0_SHIFT) +#define PINCONN_PINSEL0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 00=GPIO 01=TD1 10=RXD3 11=SCL1 */ +#define PINCONN_PINSEL0_P0p1_MASK (3 << PINCONN_PINSEL0_P0p1_SHIFT) +#define PINCONN_PINSEL0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 00=GPIO 01=TXD0 10=AD0.7 11=Reserved */ +#define PINCONN_PINSEL0_P0p2_MASK (3 << PINCONN_PINSEL0_P0p2_SHIFT) +#define PINCONN_PINSEL0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 00=GPIO 01=RXD0 10=AD0.6 11=Reserved */ +#define PINCONN_PINSEL0_P0p3_MASK (3 << PINCONN_PINSEL0_P0p3_SHIFT) +#define PINCONN_PINSEL0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 00=GPIO 01=I2SRX_CLK 10=RD2 11=CAP2.0 */ +#define PINCONN_PINSEL0_P0p4_MASK (3 << PINCONN_PINSEL0_P0p4_SHIFT) +#define PINCONN_PINSEL0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 00=GPIO 01=I2SRX_WS 10=TD2 11=CAP2.1 */ +#define PINCONN_PINSEL0_P0p5_MASK (3 << PINCONN_PINSEL0_P0p5_SHIFT) +#define PINCONN_PINSEL0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 00=GPIO 01=I2SRX_SDA 10=SSEL1 11=MAT2.0 */ +#define PINCONN_PINSEL0_P0p6_MASK (3 << PINCONN_PINSEL0_P0p6_SHIFT) +#define PINCONN_PINSEL0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 00=GPIO 01=I2STX_CLK 10=SCK1 11=MAT2.1 */ +#define PINCONN_PINSEL0_P0p7_MASK (3 << PINCONN_PINSEL0_P0p7_SHIFT) +#define PINCONN_PINSEL0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 00=GPIO 01=I2STX_WS 10=MISO1 11=MAT2.2 */ +#define PINCONN_PINSEL0_P0p8_MASK (3 << PINCONN_PINSEL0_P0p8_SHIFT) +#define PINCONN_PINSEL0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 00=GPIO 01=I2STX_SDA 10=MOSI1 11=MAT2.3 */ +#define PINCONN_PINSEL0_P0p9_MASK (3 << PINCONN_PINSEL0_P0p9_SHIFT) +#define PINCONN_PINSEL0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 00=GPIO 01=TXD2 10=SDA2 11=MAT3.0 */ +#define PINCONN_PINSEL0_P0p10_MASK (3 << PINCONN_PINSEL0_P0p10_SHIFT) +#define PINCONN_PINSEL0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 00=GPIO 01=RXD2 10=SCL2 11=MAT3.1 */ +#define PINCONN_PINSEL0_P0p11_MASK (3 << PINCONN_PINSEL0_P0p11_SHIFT) + /* Bits 24-29: Reserved */ +#define PINCONN_PINSEL0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 00=GPIO 01=TXD1 10=SCK0 11=SCK */ +#define PINCONN_PINSEL0_P0p15_MASK (3 << PINCONN_PINSEL0_P0p15_SHIFT) + +/* Pin Function Select Register 1 (PINSEL1: 0x4002c004) */ + +#define PINCONN_PINSEL1_P0_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL1_P0_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINSEL1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 00=GPIO 01=RXD1 10=SSEL0 11=SSEL */ +#define PINCONN_PINSEL1_P0p16_MASK (3 << PINCONN_PINSEL1_P0p16_SHIFT) +#define PINCONN_PINSEL1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 00=GPIO 01=CTS1 10=MISO0 11=MISO */ +#define PINCONN_PINSEL1_P0p17_MASK (3 << PINCONN_PINSEL1_P0p17_SHIFT) +#define PINCONN_PINSEL1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 00=GPIO 01=DCD1 10=MOSI0 11=MOSI */ +#define PINCONN_PINSEL1_P0p18_MASK (3 << PINCONN_PINSEL1_P0p18_SHIFT) +#define PINCONN_PINSEL1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 00=GPIO 01=DSR1 10=Reserved 11=SDA1 */ +#define PINCONN_PINSEL1_P0p19_MASK (3 << PINCONN_PINSEL1_P0p19_SHIFT) +#define PINCONN_PINSEL1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 00=GPIO 01=DTR1 10=Reserved 11=SCL1 */ +#define PINCONN_PINSEL1_P0p20_MASK (3 << PINCONN_PINSEL1_P0p20_SHIFT) +#define PINCONN_PINSEL1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 00=GPIO 01=RI1 10=Reserved 11=RD1 */ +#define PINCONN_PINSEL1_P0p21_MASK (3 << PINCONN_PINSEL1_P0p21_SHIFT) +#define PINCONN_PINSEL1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 00=GPIO 01=RTS1 10=Reserved 11=TD1 */ +#define PINCONN_PINSEL1_P0p22_MASK (3 << PINCONN_PINSEL1_P0p22_SHIFT) +#define PINCONN_PINSEL1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 00=GPIO 01=AD0.0 10=I2SRX_CLK 11=CAP3.0 */ +#define PINCONN_PINSEL1_P0p23_MASK (3 << PINCONN_PINSEL1_P0p23_SHIFT) +#define PINCONN_PINSEL1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 00=GPIO 01=AD0.1 10=I2SRX_WS 11=CAP3.1 */ +#define PINCONN_PINSEL1_P0p24_MASK (3 << PINCONN_PINSEL1_P0p24_SHIFT) +#define PINCONN_PINSEL1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 00=GPIO 01=AD0.2 10=I2SRX_SDA 11=TXD3 */ +#define PINCONN_PINSEL1_P0p25_MASK (3 << PINCONN_PINSEL1_P0p25_SHIFT) +#define PINCONN_PINSEL1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 00=GPIO 01=AD0.3 10=AOUT 11=RXD3 */ +#define PINCONN_PINSEL1_P0p26_MASK (3 << PINCONN_PINSEL1_P0p26_SHIFT) +#define PINCONN_PINSEL1_P0p27_SHIFT (22) /* Bits 22-23: P0.27 00=GPIO 01=SDA0 10=USB_SDA 11=Reserved */ +#define PINCONN_PINSEL1_P0p27_MASK (3 << PINCONN_PINSEL1_P0p27_SHIFT) +#define PINCONN_PINSEL1_P0p28_SHIFT (24) /* Bits 24-25: P0.28 00=GPIO 01=SCL0 10=USB_SCL 11=Reserved */ +#define PINCONN_PINSEL1_P0p28_MASK (3 << PINCONN_PINSEL1_P0p28_SHIFT) +#define PINCONN_PINSEL1_P0p29_SHIFT (26) /* Bits 26-27: P0.29 00=GPIO 01=USB_D+ 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL1_P0p29_MASK (3 << PINCONN_PINSEL1_P0p29_SHIFT) +#define PINCONN_PINSEL1_P0p30_SHIFT (28) /* Bits 28-29: P0.30 00=GPIO 01=USB_D- 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL1_P0p30_MASK (3 << PINCONN_PINSEL1_P0p30_SHIFT) + /* Bits 30-31: Reserved */ +/* Pin Function Select register 2 (PINSEL2: 0x4002c008) */ + +#define PINCONN_PINSEL2_P1_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINSEL2_P1_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINSEL2_P1p0_SHIFT (0) /* Bits 0-1: P1.0 00=GPIO 01=ENET_TXD0 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p0_MASK (3 << PINCONN_PINSEL2_P1p0_SHIFT) +#define PINCONN_PINSEL2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 00=GPIO 01=ENET_TXD1 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p1_MASK (3 << PINCONN_PINSEL2_P1p1_SHIFT) + /* Bits 4-7: Reserved */ +#define PINCONN_PINSEL2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 00=GPIO 01=ENET_TX_EN 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p4_MASK (3 << PINCONN_PINSEL2_P1p4_SHIFT) + /* Bits 10-15: Reserved */ +#define PINCONN_PINSEL2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 00=GPIO 01=ENET_CRS 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p8_MASK (3 << PINCONN_PINSEL2_P1p8_SHIFT) +#define PINCONN_PINSEL2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 00=GPIO 01=ENET_RXD0 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p9_MASK (3 << PINCONN_PINSEL2_P1p9_SHIFT) +#define PINCONN_PINSEL2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 00=GPIO 01=ENET_RXD1 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p10_MASK (3 << PINCONN_PINSEL2_P1p10_SHIFT) + /* Bits 22-27: Reserved */ +#define PINCONN_PINSEL2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 00=GPIO 01=ENET_RX_ER 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p14_MASK (3 << PINCONN_PINSEL2_P1p14_SHIFT) +#define PINCONN_PINSEL2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 00=GPIO 01=ENET_REF_CLK 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL2_P1p15_MASK (3 << PINCONN_PINSEL2_P1p15_SHIFT) + +/* Pin Function Select Register 3 (PINSEL3: 0x4002c00c) */ + +#define PINCONN_PINSEL3_P1_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL3_P1_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINSEL3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 00=GPIO 01=ENET_MDC 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL3_P1p16_MASK (3 << PINCONN_PINSEL3_P1p16_SHIFT) +#define PINCONN_PINSEL3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 00=GPIO 01=ENET_MDIO 10=Reserved 11=Reserved */ +#define PINCONN_PINSEL3_P1p17_MASK (3 << PINCONN_PINSEL3_P1p17_SHIFT) +#define PINCONN_PINSEL3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 00=GPIO 01=USB_UP_LED 10=PWM1.1 11=CAP1.0 */ +#define PINCONN_PINSEL3_P1p18_MASK (3 << PINCONN_PINSEL3_P1p18_SHIFT) +#define PINCONN_PINSEL3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 00=GPIO 01=MCOA0 10=USB_PPWR 11=CAP1.1 */ +#define PINCONN_PINSEL3_P1p19_MASK (3 << PINCONN_PINSEL3_P1p19_SHIFT) +#define PINCONN_PINSEL3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 00=GPIO 01=MCI0 10=PWM1.2 11=SCK0 */ +#define PINCONN_PINSEL3_P1p20_MASK (3 << PINCONN_PINSEL3_P1p20_SHIFT) +#define PINCONN_PINSEL3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 00=GPIO 01=MCABORT 10=PWM1.3 11=SSEL0 */ +#define PINCONN_PINSEL3_P1p21_MASK (3 << PINCONN_PINSEL3_P1p21_SHIFT) +#define PINCONN_PINSEL3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 00=GPIO 01=MCOB0 10=USB_PWRD 11=MAT1.0 */ +#define PINCONN_PINSEL3_P1p22_MASK (3 << PINCONN_PINSEL3_P1p22_SHIFT) +#define PINCONN_PINSEL3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 00=GPIO 01=MCI1 10=PWM1.4 11=MISO0 */ +#define PINCONN_PINSEL3_P1p23_MASK (3 << PINCONN_PINSEL3_P1p23_SHIFT) +#define PINCONN_PINSEL3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 00=GPIO 01=MCI2 10=PWM1.5 11=MOSI0 */ +#define PINCONN_PINSEL3_P1p24_MASK (3 << PINCONN_PINSEL3_P1p24_SHIFT) +#define PINCONN_PINSEL3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 00=GPIO 01=MCOA1 10=Reserved 11=MAT1.1 */ +#define PINCONN_PINSEL3_P1p25_MASK (3 << PINCONN_PINSEL3_P1p25_SHIFT) +#define PINCONN_PINSEL3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 00=GPIO 01=MCOB1 10=PWM1.6 11=CAP0.0 */ +#define PINCONN_PINSEL3_P1p26_MASK (3 << PINCONN_PINSEL3_P1p26_SHIFT) +#define PINCONN_PINSEL3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 00=GPIO 01=CLKOUT 10=USB_OVRCR 11=CAP0.1 */ +#define PINCONN_PINSEL3_P1p27_MASK (3 << PINCONN_PINSEL3_P1p27_SHIFT) +#define PINCONN_PINSEL3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 00=GPIO 01=MCOA2 10=PCAP1.0 11=MAT0.0 */ +#define PINCONN_PINSEL3_P1p28_MASK (3 << PINCONN_PINSEL3_P1p28_SHIFT) +#define PINCONN_PINSEL3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 00=GPIO 01=MCOB2 10=PCAP1.1 11=MAT0.1 */ +#define PINCONN_PINSEL3_P1p29_MASK (3 << PINCONN_PINSEL3_P1p29_SHIFT) +#define PINCONN_PINSEL3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 00=GPIO 01=Reserved 10=VBUS 11=AD0.4 */ +#define PINCONN_PINSEL3_P1p30_MASK (3 << PINCONN_PINSEL3_P1p30_SHIFT) +#define PINCONN_PINSEL3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 00=GPIO 01=Reserved 10=SCK1 11=AD0.5 */ +#define PINCONN_PINSEL3_P1p31_MASK (3 << PINCONN_PINSEL3_P1p31_SHIFT) + +/* Pin Function Select Register 4 (PINSEL4: 0x4002c010) */ + +#define PINCONN_PINSEL4_P2_SHIFT(n) PINCONN_PINSELL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINSEL4_P2_MASK(n) PINCONN_PINSELL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINSEL4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 00=GPIO 01=PWM1.1 10=TXD1 11=Reserved */ +#define PINCONN_PINSEL4_P2p0_MASK (3 << PINCONN_PINSEL4_P2p0_SHIFT) +#define PINCONN_PINSEL4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 00=GPIO 01=PWM1.2 10=RXD1 11=Reserved */ +#define PINCONN_PINSEL4_P2p1_MASK (3 << PINCONN_PINSEL4_P2p1_SHIFT) +#define PINCONN_PINSEL4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 00=GPIO 01=PWM1.3 10=CTS1 11=Reserved */ +#define PINCONN_PINSEL4_P2p2_MASK (3 << PINCONN_PINSEL4_P2p2_SHIFT) +#define PINCONN_PINSEL4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 00=GPIO 01=PWM1.4 10=DCD1 11=Reserved */ +#define PINCONN_PINSEL4_P2p3_MASK (3 << PINCONN_PINSEL4_P2p3_SHIFT) +#define PINCONN_PINSEL4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 00=GPIO 01=PWM1.5 10=DSR1 11=Reserved */ +#define PINCONN_PINSEL4_P2p4_MASK (3 << PINCONN_PINSEL4_P2p4_SHIFT) +#define PINCONN_PINSEL4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 00=GPIO 01=PWM1.6 10=DTR1 11=Reserved */ +#define PINCONN_PINSEL4_P2p5_MASK (3 << PINCONN_PINSEL4_P2p5_SHIFT) +#define PINCONN_PINSEL4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 00=GPIO 01=PCAP1.0 10=RI1 11=Reserved */ +#define PINCONN_PINSEL4_P2p6_MASK (3 << PINCONN_PINSEL4_P2p6_SHIFT) +#define PINCONN_PINSEL4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 00=GPIO 01=RD2 10=RTS1 11=Reserved */ +#define PINCONN_PINSEL4_P2p7_MASK (3 << PINCONN_PINSEL4_P2p7_SHIFT) +#define PINCONN_PINSEL4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 00=GPIO 01=TD2 10=TXD2 11=ENET_MDC */ +#define PINCONN_PINSEL4_P2p8_MASK (3 << PINCONN_PINSEL4_P2p8_SHIFT) +#define PINCONN_PINSEL4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 00=GPIO 01=USB_CONNECT 10=RXD2 11=ENET_MDIO */ +#define PINCONN_PINSEL4_P2p9_MASK (3 << PINCONN_PINSEL4_P2p9_SHIFT) +#define PINCONN_PINSEL4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 00=GPIO 01=EINT0 10=NMI 11=Reserved */ +#define PINCONN_PINSEL4_P2p10_MASK (3 << PINCONN_PINSEL4_P2p10_SHIFT) +#define PINCONN_PINSEL4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 00=GPIO 01=EINT1 10=Reserved 11=I2STX_CLK */ +#define PINCONN_PINSEL4_P2p11_MASK (3 << PINCONN_PINSEL4_P2p11_SHIFT) +#define PINCONN_PINSEL4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 00=GPIO 01=PEINT2 10=Reserved 11=I2STX_WS */ +#define PINCONN_PINSEL4_P2p12_MASK (3 << PINCONN_PINSEL4_P2p12_SHIFT) +#define PINCONN_PINSEL4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 00=GPIO 01=EINT3 10=Reserved 11=I2STX_SDA */ +#define PINCONN_PINSEL4_P2p13_MASK (3 << PINCONN_PINSEL4_P2p13_SHIFT) + /* Bits 28-31: Reserved */ +/* Pin Function Select Register 7 (PINSEL7: 0x4002c01c) */ + +#define PINCONN_PINSEL7_P3_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL7_P3_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + + /* Bits 0-17: Reserved */ +#define PINCONN_PINSEL7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 00=GPIO 01=Reserved 10=MAT0.0 11=PWM1.2 */ +#define PINCONN_PINSEL7_P3p25_MASK (3 << PINCONN_PINSEL7_P3p25_SHIFT) +#define PINCONN_PINSEL7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 00=GPIO 01=STCLK 10=MAT0.1 11=PWM1.3 */ +#define PINCONN_PINSEL7_P3p26_MASK (3 << PINCONN_PINSEL7_P3p26_SHIFT) + /* Bits 22-31: Reserved */ + +/* Pin Function Select Register 8 (PINSEL8: 0x4002c020) */ +/* No description of bits -- Does this register exist? */ + +/* Pin Function Select Register 9 (PINSEL9: 0x4002c024) */ + +#define PINCONN_PINSEL9_P4_SHIFT(n) PINCONN_PINSELH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINSEL9_P4_MASK(n) PINCONN_PINSELH_MASK(n) /* n=16,17,..31 */ + + /* Bits 0-23: Reserved */ +#define PINCONN_PINSEL9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 00=GPIO 01=RX_MCLK 10=MAT2.0 11=TXD3 */ +#define PINCONN_PINSEL9_P4p28_MASK (3 << PINCONN_PINSEL9_P4p28_SHIFT) +#define PINCONN_PINSEL9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 00=GPIO 01=TX_MCLK 10=MAT2.1 11=RXD3 */ +#define PINCONN_PINSEL9_P4p29_MASK (3 << PINCONN_PINSEL9_P4p29_SHIFT) + /* Bits 28-31: Reserved */ +/* Pin Function Select Register 10 (PINSEL10: 0x4002c028) */ + /* Bits 0-2: Reserved */ +#define PINCONN_PINSEL10_TPIU (1 << 3) /* Bit 3: 0=TPIU interface disabled; 1=TPIU interface enabled */ + /* Bits 4-31: Reserved */ +/* Pin Mode select register 0 (PINMODE0: 0x4002c040) */ + +#define PINCONN_PINMODE_PU (0) /* 00: pin has a pull-up resistor enabled */ +#define PINCONN_PINMODE_RM (1) /* 01: pin has repeater mode enabled */ +#define PINCONN_PINMODE_FLOAT (2) /* 10: pin has neither pull-up nor pull-down */ +#define PINCONN_PINMODE_PD (3) /* 11: pin has a pull-down resistor enabled */ +#define PINCONN_PINMODE_MASK (3) + +#define PINCONN_PINMODEL_SHIFT(n) ((n) << 1) /* n=0,1,..,15 */ +#define PINCONN_PINMODEL_MASK(n) (3 << PINCONN_PINMODEL_SHIFT(n)) +#define PINCONN_PINMODEH_SHIFT(n) (((n)-16) << 1) /* n=16,17,..31 */ +#define PINCONN_PINMODEH_MASK(n) (3 << PINCONN_PINMODEH_SHIFT(n)) + +#define PINCONN_PINMODE0_P0_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE0_P0_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINMODE0_P0p0_SHIFT (0) /* Bits 0-1: P0.0 mode control */ +#define PINCONN_PINMODE0_P0p0_MASK (3 << PINCONN_PINMODE0_P0p0_SHIFT) +#define PINCONN_PINMODE0_P0p1_SHIFT (2) /* Bits 2-3: P0.1 mode control */ +#define PINCONN_PINMODE0_P0p1_MASK (3 << PINCONN_PINMODE0_P0p1_SHIFT) +#define PINCONN_PINMODE0_P0p2_SHIFT (4) /* Bits 4-5: P0.2 mode control */ +#define PINCONN_PINMODE0_P0p2_MASK (3 << PINCONN_PINMODE0_P0p2_SHIFT) +#define PINCONN_PINMODE0_P0p3_SHIFT (6) /* Bits 6-7: P0.3 mode control */ +#define PINCONN_PINMODE0_P0p3_MASK (3 << PINCONN_PINMODE0_P0p3_SHIFT) +#define PINCONN_PINMODE0_P0p4_SHIFT (8) /* Bits 8-9: P0.4 mode control */ +#define PINCONN_PINMODE0_P0p4_MASK (3 << PINCONN_PINMODE0_P0p4_SHIFT) +#define PINCONN_PINMODE0_P0p5_SHIFT (10) /* Bits 10-11: P0.5 mode control */ +#define PINCONN_PINMODE0_P0p5_MASK (3 << PINCONN_PINMODE0_P0p5_SHIFT) +#define PINCONN_PINMODE0_P0p6_SHIFT (12) /* Bits 12-13: P0.6 mode control */ +#define PINCONN_PINMODE0_P0p6_MASK (3 << PINCONN_PINMODE0_P0p6_SHIFT) +#define PINCONN_PINMODE0_P0p7_SHIFT (14) /* Bits 14-15: P0.7 mode control */ +#define PINCONN_PINMODE0_P0p7_MASK (3 << PINCONN_PINMODE0_P0p7_SHIFT) +#define PINCONN_PINMODE0_P0p8_SHIFT (16) /* Bits 16-17: P0.8 mode control */ +#define PINCONN_PINMODE0_P0p8_MASK (3 << PINCONN_PINMODE0_P0p8_SHIFT) +#define PINCONN_PINMODE0_P0p9_SHIFT (18) /* Bits 18-19: P0.9 mode control */ +#define PINCONN_PINMODE0_P0p9_MASK (3 << PINCONN_PINMODE0_P0p9_SHIFT) +#define PINCONN_PINMODE0_P0p10_SHIFT (20) /* Bits 20-21: P0.10 mode control */ +#define PINCONN_PINMODE0_P0p10_MASK (3 << PINCONN_PINMODE0_P0p10_SHIFT) +#define PINCONN_PINMODE0_P0p11_SHIFT (22) /* Bits 22-23: P0.11 mode control */ +#define PINCONN_PINMODE0_P0p11_MASK (3 << PINCONN_PINMODE0_P0p11_SHIFT) + /* Bits 24-29: Reserved */ +#define PINCONN_PINMODE0_P0p15_SHIFT (30) /* Bits 30-31: P0.15 mode control */ +#define PINCONN_PINMODE0_P0p15_MASK (3 << PINCONN_PINMODE0_P0p15_SHIFT) + +/* Pin Mode select register 1 (PINMODE1: 0x4002c044) */ + +#define PINCONN_PINMODE1_P0_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE1_P0_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINMODE1_P0p16_SHIFT (0) /* Bits 0-1: P0.16 mode control */ +#define PINCONN_PINMODE1_P0p16_MASK (3 << PINCONN_PINMODE1_P0p16_SHIFT) +#define PINCONN_PINMODE1_P0p17_SHIFT (2) /* Bits 2-3: P0.17 mode control */ +#define PINCONN_PINMODE1_P0p17_MASK (3 << PINCONN_PINMODE1_P0p17_SHIFT) +#define PINCONN_PINMODE1_P0p18_SHIFT (4) /* Bits 4-5: P0.18 mode control */ +#define PINCONN_PINMODE1_P0p18_MASK (3 << PINCONN_PINMODE1_P0p18_SHIFT) +#define PINCONN_PINMODE1_P0p19_SHIFT (6) /* Bits 6-7: P0.19 mode control */ +#define PINCONN_PINMODE1_P0p19_MASK (3 << PINCONN_PINMODE1_P0p19_SHIFT) +#define PINCONN_PINMODE1_P0p20_SHIFT (8) /* Bits 8-9: P0.20 mode control */ +#define PINCONN_PINMODE1_P0p20_MASK (3 << PINCONN_PINMODE1_P0p20_SHIFT) +#define PINCONN_PINMODE1_P0p21_SHIFT (10) /* Bits 10-11: P0.21 mode control */ +#define PINCONN_PINMODE1_P0p21_MASK (3 << PINCONN_PINMODE1_P0p21_SHIFT) +#define PINCONN_PINMODE1_P0p22_SHIFT (12) /* Bits 12-13: P0.22 mode control */ +#define PINCONN_PINMODE1_P0p22_MASK (3 << PINCONN_PINMODE1_P0p22_SHIFT) +#define PINCONN_PINMODE1_P0p23_SHIFT (14) /* Bits 14-15: P0.23 mode control */ +#define PINCONN_PINMODE1_P0p23_MASK (3 << PINCONN_PINMODE1_P0p23_SHIFT) +#define PINCONN_PINMODE1_P0p24_SHIFT (16) /* Bits 16-17: P0.24 mode control */ +#define PINCONN_PINMODE1_P0p24_MASK (3 << PINCONN_PINMODE1_P0p24_SHIFT) +#define PINCONN_PINMODE1_P0p25_SHIFT (18) /* Bits 18-19: P0.25 mode control */ +#define PINCONN_PINMODE1_P0p25_MASK (3 << PINCONN_PINMODE1_P0p25_SHIFT) +#define PINCONN_PINMODE1_P0p26_SHIFT (20) /* Bits 20-21: P0.26 mode control */ +#define PINCONN_PINMODE1_P0p26_MASK (3 << PINCONN_PINMODE1_P0p26_SHIFT) + /* Bits 22-31: Reserved */ + +/* Pin Mode select register 2 (PINMODE2: 0x4002c048) */ + +#define PINCONN_PINMODE2_P1_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE2_P1_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINMODE2_P1p0_SHIFT (0) /* Bits 2-1: P1.0 mode control */ +#define PINCONN_PINMODE2_P1p0_MASK (3 << PINCONN_PINMODE2_P1p0_SHIFT) +#define PINCONN_PINMODE2_P1p1_SHIFT (2) /* Bits 2-3: P1.1 mode control */ +#define PINCONN_PINMODE2_P1p1_MASK (3 << PINCONN_PINMODE2_P1p1_SHIFT) + /* Bits 4-7: Reserved */ +#define PINCONN_PINMODE2_P1p4_SHIFT (8) /* Bits 8-9: P1.4 mode control */ +#define PINCONN_PINMODE2_P1p4_MASK (3 << PINCONN_PINMODE2_P1p4_SHIFT) + /* Bits 10-15: Reserved */ +#define PINCONN_PINMODE2_P1p8_SHIFT (16) /* Bits 16-17: P1.8 mode control */ +#define PINCONN_PINMODE2_P1p8_MASK (3 << PINCONN_PINMODE2_P1p8_SHIFT) +#define PINCONN_PINMODE2_P1p9_SHIFT (18) /* Bits 18-19: P1.9 mode control */ +#define PINCONN_PINMODE2_P1p9_MASK (3 << PINCONN_PINMODE2_P1p9_SHIFT) +#define PINCONN_PINMODE2_P1p10_SHIFT (20) /* Bits 20-21: P1.10 mode control */ +#define PINCONN_PINMODE2_P1p10_MASK (3 << PINCONN_PINMODE2_P1p10_SHIFT) + /* Bits 22-27: Reserved */ +#define PINCONN_PINMODE2_P1p14_SHIFT (28) /* Bits 28-29: P1.14 mode control */ +#define PINCONN_PINMODE2_P1p14_MASK (3 << PINCONN_PINMODE2_P1p14_SHIFT) +#define PINCONN_PINMODE2_P1p15_SHIFT (30) /* Bits 30-31: P1.15 mode control */ +#define PINCONN_PINMODE2_P1p15_MASK (3 << PINCONN_PINMODE2_P1p15_SHIFT) + +/* Pin Mode select register 3 (PINMODE3: 0x4002c04c) */ + +#define PINCONN_PINMODE3_P1_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE3_P1_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINMODE3_P1p16_SHIFT (0) /* Bits 0-1: P1.16 mode control */ +#define PINCONN_PINMODE3_P1p16_MASK (3 << PINCONN_PINMODE3_P1p16_SHIFT) +#define PINCONN_PINMODE3_P1p17_SHIFT (2) /* Bits 2-3: P1.17 mode control */ +#define PINCONN_PINMODE3_P1p17_MASK (3 << PINCONN_PINMODE3_P1p17_SHIFT) +#define PINCONN_PINMODE3_P1p18_SHIFT (4) /* Bits 4-5: P1.18 mode control */ +#define PINCONN_PINMODE3_P1p18_MASK (3 << PINCONN_PINMODE3_P1p18_SHIFT) +#define PINCONN_PINMODE3_P1p19_SHIFT (6) /* Bits 6-7: P1.19 mode control */ +#define PINCONN_PINMODE3_P1p19_MASK (3 << PINCONN_PINMODE3_P1p19_SHIFT) +#define PINCONN_PINMODE3_P1p20_SHIFT (8) /* Bits 8-9: P1.20 mode control */ +#define PINCONN_PINMODE3_P1p20_MASK (3 << PINCONN_PINMODE3_P1p20_SHIFT) +#define PINCONN_PINMODE3_P1p21_SHIFT (10) /* Bits 10-11: P1.21 mode control */ +#define PINCONN_PINMODE3_P1p21_MASK (3 << PINCONN_PINMODE3_P1p21_SHIFT) +#define PINCONN_PINMODE3_P1p22_SHIFT (12) /* Bits 12-13: P1.22 mode control */ +#define PINCONN_PINMODE3_P1p22_MASK (3 << PINCONN_PINMODE3_P1p22_SHIFT) +#define PINCONN_PINMODE3_P1p23_SHIFT (14) /* Bits 14-15: P1.23 mode control */ +#define PINCONN_PINMODE3_P1p23_MASK (3 << PINCONN_PINMODE3_P1p23_SHIFT) +#define PINCONN_PINMODE3_P1p24_SHIFT (16) /* Bits 16-17: P1.24 mode control */ +#define PINCONN_PINMODE3_P1p24_MASK (3 << PINCONN_PINMODE3_P1p24_SHIFT) +#define PINCONN_PINMODE3_P1p25_SHIFT (18) /* Bits 18-19: P1.25 mode control */ +#define PINCONN_PINMODE3_P1p25_MASK (3 << PINCONN_PINMODE3_P1p25_SHIFT) +#define PINCONN_PINMODE3_P1p26_SHIFT (20) /* Bits 20-21: P1.26 mode control */ +#define PINCONN_PINMODE3_P1p26_MASK (3 << PINCONN_PINMODE3_P1p26_SHIFT) +#define PINCONN_PINMODE3_P1p27_SHIFT (22) /* Bits 22-23: P1.27 mode control */ +#define PINCONN_PINMODE3_P1p27_MASK (3 << PINCONN_PINMODE3_P1p27_SHIFT) +#define PINCONN_PINMODE3_P1p28_SHIFT (24) /* Bits 24-25: P1.28 mode control */ +#define PINCONN_PINMODE3_P1p28_MASK (3 << PINCONN_PINMODE3_P1p28_SHIFT) +#define PINCONN_PINMODE3_P1p29_SHIFT (26) /* Bits 26-27: P1.29 mode control */ +#define PINCONN_PINMODE3_P1p29_MASK (3 << PINCONN_PINMODE3_P1p29_SHIFT) +#define PINCONN_PINMODE3_P1p30_SHIFT (28) /* Bits 28-29: P1.30 mode control */ +#define PINCONN_PINMODE3_P1p30_MASK (3 << PINCONN_PINMODE3_P1p30_SHIFT) +#define PINCONN_PINMODE3_P1p31_SHIFT (30) /* Bits 30-31: P1.31 mode control */ +#define PINCONN_PINMODE3_P1p31_MASK (3 << PINCONN_PINMODE3_P1p31_SHIFT) + +/* Pin Mode select register 4 (PINMODE4: 0x4002c050) */ + +#define PINCONN_PINMODE4_P2_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE4_P2_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +#define PINCONN_PINMODE4_P2p0_SHIFT (0) /* Bits 0-1: P2.0 mode control */ +#define PINCONN_PINMODE4_P2p0_MASK (3 << PINCONN_PINMODE4_P2p0_SHIFT) +#define PINCONN_PINMODE4_P2p1_SHIFT (2) /* Bits 2-3: P2.1 mode control */ +#define PINCONN_PINMODE4_P2p1_MASK (3 << PINCONN_PINMODE4_P2p1_SHIFT) +#define PINCONN_PINMODE4_P2p2_SHIFT (4) /* Bits 4-5: P2.2 mode control */ +#define PINCONN_PINMODE4_P2p2_MASK (3 << PINCONN_PINMODE4_P2p2_SHIFT) +#define PINCONN_PINMODE4_P2p3_SHIFT (6) /* Bits 6-7: P2.3 mode control */ +#define PINCONN_PINMODE4_P2p3_MASK (3 << PINCONN_PINMODE4_P2p3_SHIFT) +#define PINCONN_PINMODE4_P2p4_SHIFT (8) /* Bits 8-9: P2.4 mode control */ +#define PINCONN_PINMODE4_P2p4_MASK (3 << PINCONN_PINMODE4_P2p4_SHIFT) +#define PINCONN_PINMODE4_P2p5_SHIFT (10) /* Bits 10-11: P2.5 mode control */ +#define PINCONN_PINMODE4_P2p5_MASK (3 << PINCONN_PINMODE4_P2p5_SHIFT) +#define PINCONN_PINMODE4_P2p6_SHIFT (12) /* Bits 12-13: P2.6 mode control */ +#define PINCONN_PINMODE4_P2p6_MASK (3 << PINCONN_PINMODE4_P2p6_SHIFT) +#define PINCONN_PINMODE4_P2p7_SHIFT (14) /* Bits 14-15: P2.7 mode control */ +#define PINCONN_PINMODE4_P2p7_MASK (3 << PINCONN_PINMODE4_P2p7_SHIFT) +#define PINCONN_PINMODE4_P2p8_SHIFT (16) /* Bits 16-17: P2.8 mode control */ +#define PINCONN_PINMODE4_P2p8_MASK (3 << PINCONN_PINMODE4_P2p8_SHIFT) +#define PINCONN_PINMODE4_P2p9_SHIFT (18) /* Bits 18-19: P2.9 mode control */ +#define PINCONN_PINMODE4_P2p9_MASK (3 << PINCONN_PINMODE4_P2p9_SHIFT) +#define PINCONN_PINMODE4_P2p10_SHIFT (20) /* Bits 20-21: P2.10 mode control */ +#define PINCONN_PINMODE4_P2p10_MASK (3 << PINCONN_PINMODE4_P2p10_SHIFT) +#define PINCONN_PINMODE4_P2p11_SHIFT (22) /* Bits 22-23: P2.11 mode control */ +#define PINCONN_PINMODE4_P2p11_MASK (3 << PINCONN_PINMODE4_P2p11_SHIFT) +#define PINCONN_PINMODE4_P2p12_SHIFT (24) /* Bits 24-25: P2.12 mode control */ +#define PINCONN_PINMODE4_P2p12_MASK (3 << PINCONN_PINMODE4_P2p12_SHIFT) +#define PINCONN_PINMODE4_P2p13_SHIFT (26) /* Bits 26-27: P2.13 mode control */ +#define PINCONN_PINMODE4_P2p13_MASK (3 << PINCONN_PINMODE4_P2p13_SHIFT) + /* Bits 28-31: Reserved */ +/* Pin Mode select register 5 (PINMODE5: 0x4002c054) + * Pin Mode select register 6 (PINMODE6: 0x4002c058) + * No bit definitions -- do these registers exist? + */ + +#define PINCONN_PINMODE5_P2_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE5_P2_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + +#define PINCONN_PINMODE6_P3_SHIFT(n) PINCONN_PINMODEL_SHIFT(n) /* n=0,1,..,15 */ +#define PINCONN_PINMODE6_P3_MASK(n) PINCONN_PINMODEL_MASK(n) /* n=0,1,..,15 */ + +/* Pin Mode select register 7 (PINMODE7: 0x4002c05c) */ + +#define PINCONN_PINMODE7_P3_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE7_P3_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + /* Bits 0-17: Reserved */ +#define PINCONN_PINMODE7_P3p25_SHIFT (18) /* Bits 18-19: P3.25 mode control */ +#define PINCONN_PINMODE7_P3p25_MASK (3 << PINCONN_PINMODE7_P3p25_SHIFT) +#define PINCONN_PINMODE7_P3p26_SHIFT (20) /* Bits 20-21: P3.26 mode control */ +#define PINCONN_PINMODE7_P3p26_MASK (3 << PINCONN_PINMODE7_P3p26_SHIFT) + /* Bits 22-31: Reserved */ +/* Pin Mode select register 9 (PINMODE9: 0x4002c064) */ + +#define PINCONN_PINMODE9_P4_SHIFT(n) PINCONN_PINMODEH_SHIFT(n) /* n=16,17,..31 */ +#define PINCONN_PINMODE9_P4_MASK(n) PINCONN_PINMODEH_MASK(n) /* n=16,17,..31 */ + /* Bits 0-23: Reserved */ +#define PINCONN_PINMODE9_P4p28_SHIFT (24) /* Bits 24-25: P4.28 mode control */ +#define PINCONN_PINMODE9_P4p28_MASK (3 << PINCONN_PINMODE9_P4p28_SHIFT) +#define PINCONN_PINMODE9_P4p29_SHIFT (26) /* Bits 26-27: P4.29 mode control */ +#define PINCONN_PINMODE9_P4p29_MASK (3 << PINCONN_PINMODE9_P4p29_SHIFT) + /* Bits 28-31: Reserved */ +/* Open Drain Pin Mode select register 0 (PINMODE_OD0: 0x4002c068) */ + +#define PINCONN_ODMODE0_P0(n) (1 << (n)) + +#define PINCONN_ODMODE0_P0p0 (1 << 0) /* Bit 0: P0.0 open drain mode */ +#define PINCONN_ODMODE0_P0p1 (1 << 1) /* Bit 1: P0.1 open drain mode */ +#define PINCONN_ODMODE0_P0p2 (1 << 2) /* Bit 2: P0.2 open drain mode */ +#define PINCONN_ODMODE0_P0p3 (1 << 3) /* Bit 3: P0.3 open drain mode */ +#define PINCONN_ODMODE0_P0p4 (1 << 4) /* Bit 4: P0.4 open drain mode */ +#define PINCONN_ODMODE0_P0p5 (1 << 5) /* Bit 5: P0.5 open drain mode */ +#define PINCONN_ODMODE0_P0p6 (1 << 6) /* Bit 6: P0.6 open drain mode */ +#define PINCONN_ODMODE0_P0p7 (1 << 7) /* Bit 7: P0.7 open drain mode */ +#define PINCONN_ODMODE0_P0p8 (1 << 8) /* Bit 8: P0.8 open drain mode */ +#define PINCONN_ODMODE0_P0p9 (1 << 9) /* Bit 9: P0.9 open drain mode */ +#define PINCONN_ODMODE0_P0p10 (1 << 10) /* Bit 10: P0.10 open drain mode */ +#define PINCONN_ODMODE0_P0p11 (1 << 11) /* Bit 11: P0.11 open drain mode */ + /* Bits 12-14: Reserved */ +#define PINCONN_ODMODE0_P0p15 (1 << 15) /* Bit 15: P0.15 open drain mode */ +#define PINCONN_ODMODE0_P0p16 (1 << 16) /* Bit 16: P0.16 open drain mode */ +#define PINCONN_ODMODE0_P0p17 (1 << 17) /* Bit 17: P0.17 open drain mode */ +#define PINCONN_ODMODE0_P0p18 (1 << 18) /* Bit 18: P0.18 open drain mode */ +#define PINCONN_ODMODE0_P0p19 (1 << 19) /* Bit 19: P0.19 open drain mode */ +#define PINCONN_ODMODE0_P0p20 (1 << 20) /* Bit 20: P0.20 open drain mode */ +#define PINCONN_ODMODE0_P0p21 (1 << 21) /* Bit 21: P0.21 open drain mode */ +#define PINCONN_ODMODE0_P0p22 (1 << 22) /* Bit 22: P0.22 open drain mode */ +#define PINCONN_ODMODE0_P0p23 (1 << 23) /* Bit 23: P0.23 open drain mode */ +#define PINCONN_ODMODE0_P0p24 (1 << 24) /* Bit 24: P0.24 open drain mode */ +#define PINCONN_ODMODE0_P0p25 (1 << 25) /* Bit 25: P0.25 open drain mode */ +#define PINCONN_ODMODE0_P0p26 (1 << 25) /* Bit 26: P0.26 open drain mode */ + /* Bits 27-28: Reserved */ +#define PINCONN_ODMODE0_P0p29 (1 << 29) /* Bit 29: P0.29 open drain mode */ +#define PINCONN_ODMODE0_P0p30 (1 << 30) /* Bit 30: P0.30 open drain mode */ + /* Bit 31: Reserved */ +/* Open Drain Pin Mode select register 1 (PINMODE_OD1: 0x4002c06c) */ + +#define PINCONN_ODMODE1_P1(n) (1 << (n)) + +#define PINCONN_ODMODE1_P1p0 (1 << 0) /* Bit 0: P1.0 open drain mode */ +#define PINCONN_ODMODE1_P1p1 (1 << 1) /* Bit 1: P1.1 open drain mode */ + /* Bits 2-3: Reserved */ +#define PINCONN_ODMODE1_P1p4 (1 << 4) /* Bit 4: P1.4 open drain mode */ + /* Bits 5-7: Reserved */ +#define PINCONN_ODMODE1_P1p8 (1 << 8) /* Bit 8: P1.8 open drain mode */ +#define PINCONN_ODMODE1_P1p9 (1 << 9) /* Bit 9: P1.9 open drain mode */ +#define PINCONN_ODMODE1_P1p10 (1 << 10) /* Bit 10: P1.10 open drain mode */ + /* Bits 11-13: Reserved */ +#define PINCONN_ODMODE1_P1p14 (1 << 14) /* Bit 14: P1.14 open drain mode */ +#define PINCONN_ODMODE1_P1p15 (1 << 15) /* Bit 15: P1.15 open drain mode */ +#define PINCONN_ODMODE1_P1p16 (1 << 16) /* Bit 16: P1.16 open drain mode */ +#define PINCONN_ODMODE1_P1p17 (1 << 17) /* Bit 17: P1.17 open drain mode */ +#define PINCONN_ODMODE1_P1p18 (1 << 18) /* Bit 18: P1.18 open drain mode */ +#define PINCONN_ODMODE1_P1p19 (1 << 19) /* Bit 19: P1.19 open drain mode */ +#define PINCONN_ODMODE1_P1p20 (1 << 20) /* Bit 20: P1.20 open drain mode */ +#define PINCONN_ODMODE1_P1p21 (1 << 21) /* Bit 21: P1.21 open drain mode */ +#define PINCONN_ODMODE1_P1p22 (1 << 22) /* Bit 22: P1.22 open drain mode */ +#define PINCONN_ODMODE1_P1p23 (1 << 23) /* Bit 23: P1.23 open drain mode */ +#define PINCONN_ODMODE1_P1p24 (1 << 24) /* Bit 24: P1.24 open drain mode */ +#define PINCONN_ODMODE1_P1p25 (1 << 25) /* Bit 25: P1.25 open drain mode */ +#define PINCONN_ODMODE1_P1p26 (1 << 25) /* Bit 26: P1.26 open drain mode */ +#define PINCONN_ODMODE1_P1p27 (1 << 27) /* Bit 27: P1.27 open drain mode */ +#define PINCONN_ODMODE1_P1p28 (1 << 28) /* Bit 28: P1.28 open drain mode */ +#define PINCONN_ODMODE1_P1p29 (1 << 29) /* Bit 29: P1.29 open drain mode */ +#define PINCONN_ODMODE1_P1p30 (1 << 30) /* Bit 30: P1.30 open drain mode */ +#define PINCONN_ODMODE1_P1p31 (1 << 31) /* Bit 31: P1.31 open drain mode */ + +/* Open Drain Pin Mode select register 2 (PINMODE_OD2: 0x4002c070) */ + +#define PINCONN_ODMODE2_P2(n) (1 << (n)) + +#define PINCONN_ODMODE2_P2p0 (1 << 0) /* Bit 0: P2.0 open drain mode */ +#define PINCONN_ODMODE2_P2p1 (1 << 1) /* Bit 1: P2.1 open drain mode */ +#define PINCONN_ODMODE2_P2p2 (1 << 2) /* Bit 2: P2.2 open drain mode */ +#define PINCONN_ODMODE2_P2p3 (1 << 3) /* Bit 3: P2.3 open drain mode */ +#define PINCONN_ODMODE2_P2p4 (1 << 4) /* Bit 4: P2.4 open drain mode */ +#define PINCONN_ODMODE2_P2p5 (1 << 5) /* Bit 5: P2.5 open drain mode */ +#define PINCONN_ODMODE2_P2p6 (1 << 6) /* Bit 6: P2.6 open drain mode */ +#define PINCONN_ODMODE2_P2p7 (1 << 7) /* Bit 7: P2.7 open drain mode */ +#define PINCONN_ODMODE2_P2p8 (1 << 8) /* Bit 8: P2.8 open drain mode */ +#define PINCONN_ODMODE2_P2p9 (1 << 9) /* Bit 9: P2.9 open drain mode */ +#define PINCONN_ODMODE2_P2p10 (1 << 10) /* Bit 10: P2.10 open drain mode */ +#define PINCONN_ODMODE2_P2p11 (1 << 11) /* Bit 11: P2.11 open drain mode */ +#define PINCONN_ODMODE2_P2p12 (1 << 12) /* Bit 12: P2.12 open drain mode */ +#define PINCONN_ODMODE2_P2p13 (1 << 13) /* Bit 13: P2.13 open drain mode */ + /* Bits 14-31: Reserved */ +/* Open Drain Pin Mode select register 3 (PINMODE_OD3: 0x4002c074) */ + +#define PINCONN_ODMODE3_P3(n) (1 << (n)) + /* Bits 0-24: Reserved */ +#define PINCONN_ODMODE3_P3p25 (1 << 25) /* Bit 25: P3.25 open drain mode */ +#define PINCONN_ODMODE3_P3p26 (1 << 25) /* Bit 26: P3.26 open drain mode */ + /* Bits 17-31: Reserved */ +/* Open Drain Pin Mode select register 4 (PINMODE_OD4: 0x4002c078) */ + +#define PINCONN_ODMODE4_P4(n) (1 << (n)) + /* Bits 0-27: Reserved */ +#define PINCONN_ODMODE4_P4p28 (1 << 28) /* Bit 28: P4.28 open drain mode */ +#define PINCONN_ODMODE4_P4p29 (1 << 29) /* Bit 29: P4.29 open drain mode */ + /* Bits 30-31: Reserved */ +/* I2C Pin Configuration register (I2CPADCFG: 0x4002c07c) */ + +#define PINCONN_I2CPADCFG_SDADRV0 (1 << 0) /* Bit 0: SDA0 pin, P0.27 in Fast Mode Plus */ +#define PINCONN_I2CPADCFG_SDAI2C0 (1 << 1) /* Bit 1: SDA0 pin, P0.27 I2C glitch + * filtering/slew rate control */ +#define PINCONN_I2CPADCFG_SCLDRV0 (1 << 2) /* Bit 2: SCL0 pin, P0.28 in Fast Mode Plus */ +#define PINCONN_I2CPADCFG_SCLI2C0 (1 << 3) /* Bit 3: SCL0 pin, P0.28 I2C glitch + * filtering/slew rate control */ + /* Bits 4-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_PINCONN_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_pwm.h b/arch/arm/src/lpc17xx/lpc17_pwm.h index 6db271a47e6e37fa61b7c68074f423a900171ac7..6555ce6166a569dfdec317c3a717e1535217d325 100644 --- a/arch/arm/src/lpc17xx/lpc17_pwm.h +++ b/arch/arm/src/lpc17xx/lpc17_pwm.h @@ -1,223 +1,223 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_pwm.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_PWM_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_PWM_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_PWM_IR_OFFSET 0x0000 /* Interrupt Register */ -#define LPC17_PWM_TCR_OFFSET 0x0004 /* Timer Control Register */ -#define LPC17_PWM_TC_OFFSET 0x0008 /* Timer Counter */ -#define LPC17_PWM_PR_OFFSET 0x000c /* Prescale Register */ -#define LPC17_PWM_PC_OFFSET 0x0010 /* Prescale Counter */ -#define LPC17_PWM_MCR_OFFSET 0x0014 /* Match Control Register */ -#define LPC17_PWM_MR0_OFFSET 0x0018 /* Match Register 0 */ -#define LPC17_PWM_MR1_OFFSET 0x001c /* Match Register 1 */ -#define LPC17_PWM_MR2_OFFSET 0x0020 /* Match Register 2 */ -#define LPC17_PWM_MR3_OFFSET 0x0024 /* Match Register 3 */ -#define LPC17_PWM_CCR_OFFSET 0x0028 /* Capture Control Register */ -#define LPC17_PWM_CR0_OFFSET 0x002c /* Capture Register 0 */ -#define LPC17_PWM_CR1_OFFSET 0x0030 /* Capture Register 1 */ -#define LPC17_PWM_CR2_OFFSET 0x0034 /* Capture Register 2 */ -#define LPC17_PWM_CR3_OFFSET 0x0038 /* Capture Register 3 */ -#define LPC17_PWM_MR4_OFFSET 0x0040 /* Match Register 4 */ -#define LPC17_PWM_MR5_OFFSET 0x0044 /* Match Register 5 */ -#define LPC17_PWM_MR6_OFFSET 0x0048 /* Match Register 6 */ -#define LPC17_PWM_PCR_OFFSET 0x004c /* PWM Control Register */ -#define LPC17_PWM_LER_OFFSET 0x0050 /* Load Enable Register */ -#define LPC17_PWM_CTCR_OFFSET 0x0070 /* Counter/Timer Control Register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_PWM1_IR (LPC17_PWM1_BASE+LPC17_PWM_IR_OFFSET) -#define LPC17_PWM1_TCR (LPC17_PWM1_BASE+LPC17_PWM_TCR_OFFSET) -#define LPC17_PWM1_TC (LPC17_PWM1_BASE+LPC17_PWM_TC_OFFSET) -#define LPC17_PWM1_PR (LPC17_PWM1_BASE+LPC17_PWM_PR_OFFSET) -#define LPC17_PWM1_PC (LPC17_PWM1_BASE+LPC17_PWM_PC_OFFSET) -#define LPC17_PWM1_MCR (LPC17_PWM1_BASE+LPC17_PWM_MCR_OFFSET) -#define LPC17_PWM1_MR0 (LPC17_PWM1_BASE+LPC17_PWM_MR0_OFFSET) -#define LPC17_PWM1_MR1 (LPC17_PWM1_BASE+LPC17_PWM_MR1_OFFSET) -#define LPC17_PWM1_MR2 (LPC17_PWM1_BASE+LPC17_PWM_MR2_OFFSET) -#define LPC17_PWM1_MR3 (LPC17_PWM1_BASE+LPC17_PWM_MR3_OFFSET) -#define LPC17_PWM1_MR4 (LPC17_PWM1_BASE+LPC17_PWM_MR4_OFFSET) -#define LPC17_PWM1_MR5 (LPC17_PWM1_BASE+LPC17_PWM_MR5_OFFSET) -#define LPC17_PWM1_MR6 (LPC17_PWM1_BASE+LPC17_PWM_MR6_OFFSET) -#define LPC17_PWM1_CCR (LPC17_PWM1_BASE+LPC17_PWM_CCR_OFFSET) -#define LPC17_PWM1_CR0 (LPC17_PWM1_BASE+LPC17_PWM_CR0_OFFSET) -#define LPC17_PWM1_CR1 (LPC17_PWM1_BASE+LPC17_PWM_CR1_OFFSET) -#define LPC17_PWM1_CR2 (LPC17_PWM1_BASE+LPC17_PWM_CR2_OFFSET) -#define LPC17_PWM1_CR3 (LPC17_PWM1_BASE+LPC17_PWM_CR3_OFFSET) -#define LPC17_PWM1_PCR (LPC17_PWM1_BASE+LPC17_PWM_PCR_OFFSET) -#define LPC17_PWM1_LER (LPC17_PWM1_BASE+LPC17_PWM_LER_OFFSET) -#define LPC17_PWM1_CTCR (LPC17_PWM1_BASE+LPC17_PWM_CTCR_OFFSET) - -/* Register bit definitions *********************************************************/ -/* Registers holding 32-bit numeric values (no bit field definitions): - * - * Timer Counter (TC) - * Prescale Register (PR) - * Prescale Counter (PC) - * Match Register 0 (MR0) - * Match Register 1 (MR1) - * Match Register 2 (MR2) - * Match Register 3 (MR3) - * Match Register 4 (MR3) - * Match Register 5 (MR3) - * Match Register 6 (MR3) - * Capture Register 0 (CR0) - * Capture Register 1 (CR1) - * Capture Register 1 (CR2) - * Capture Register 1 (CR3) - */ - -/* Interrupt Register */ - -#define PWM_IR_MR0 (1 << 0) /* Bit 0: PWM match channel 0 interrrupt */ -#define PWM_IR_MR1 (1 << 1) /* Bit 1: PWM match channel 1 interrrupt */ -#define PWM_IR_MR2 (1 << 2) /* Bit 2: PWM match channel 2 interrrupt */ -#define PWM_IR_MR3 (1 << 3) /* Bit 3: PWM match channel 3 interrrupt */ -#define PWM_IR_CAP0 (1 << 4) /* Bit 4: Capture input 0 interrrupt */ -#define PWM_IR_CAP1 (1 << 5) /* Bit 5: Capture input 1 interrrupt */ - /* Bits 6-7: Reserved */ -#define PWM_IR_MR4 (1 << 8) /* Bit 8: PWM match channel 4 interrrupt */ -#define PWM_IR_MR5 (1 << 9) /* Bit 9: PWM match channel 5 interrrupt */ -#define PWM_IR_MR6 (1 << 10) /* Bit 10: PWM match channel 6 interrrupt */ - /* Bits 11-31: Reserved */ -/* Timer Control Register */ - -#define PWM_TCR_CNTREN (1 << 0) /* Bit 0: Counter Enable */ -#define PWM_TCR_CNTRRST (1 << 1) /* Bit 1: Counter Reset */ - /* Bit 2: Reserved */ -#define PWM_TCR_PWMEN (1 << 3) /* Bit 3: PWM Enable */ - /* Bits 4-31: Reserved */ -/* Match Control Register */ - -#define PWM_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */ -#define PWM_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */ -#define PWM_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */ -#define PWM_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */ -#define PWM_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */ -#define PWM_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */ -#define PWM_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */ -#define PWM_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */ -#define PWM_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */ -#define PWM_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */ -#define PWM_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */ -#define PWM_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */ -#define PWM_MCR_MR4I (1 << 12) /* Bit 12: Interrupt on MR4 */ -#define PWM_MCR_MR4R (1 << 13) /* Bit 13: Reset on MR4 */ -#define PWM_MCR_MR4S (1 << 14) /* Bit 14: Stop on MR4 */ -#define PWM_MCR_MR5I (1 << 15) /* Bit 15: Interrupt on MR5 */ -#define PWM_MCR_MR5R (1 << 16) /* Bit 16: Reset on MR5*/ -#define PWM_MCR_MR5S (1 << 17) /* Bit 17: Stop on MR5 */ -#define PWM_MCR_MR6I (1 << 18) /* Bit 18: Interrupt on MR6 */ -#define PWM_MCR_MR6R (1 << 19) /* Bit 19: Reset on MR6 */ -#define PWM_MCR_MR6S (1 << 20) /* Bit 20: Stop on MR6 */ - /* Bits 21-31: Reserved */ -/* Capture Control Register (Where are CAP2 and 3?) */ - -#define PWM_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */ -#define PWM_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edg */ -#define PWM_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */ -#define PWM_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */ -#define PWM_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edg */ -#define PWM_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */ - /* Bits 6-31: Reserved */ -/* PWM Control Register */ - /* Bits 0-1: Reserved */ -#define PWM_PCR_SEL2 (1 << 2) /* Bit 2: PWM2 single edge controlled mode */ -#define PWM_PCR_SEL3 (1 << 3) /* Bit 3: PWM3 single edge controlled mode */ -#define PWM_PCR_SEL4 (1 << 4) /* Bit 4: PWM4 single edge controlled mode */ -#define PWM_PCR_SEL5 (1 << 5) /* Bit 5: PWM5 single edge controlled mode */ -#define PWM_PCR_SEL6 (1 << 6) /* Bit 6: PWM6 single edge controlled mode */ - /* Bits 7-8: Reserved */ -#define PWM_PCR_ENA1 (1 << 9) /* Bit 9: Enable PWM1 output */ -#define PWM_PCR_ENA2 (1 << 10) /* Bit 10: Enable PWM2 output */ -#define PWM_PCR_ENA3 (1 << 11) /* Bit 11: Enable PWM3 output */ -#define PWM_PCR_ENA4 (1 << 12) /* Bit 12: Enable PWM4 output */ -#define PWM_PCR_ENA5 (1 << 13) /* Bit 13: Enable PWM5 output */ -#define PWM_PCR_ENA6 (1 << 14) /* Bit 14: Enable PWM6 output */ - /* Bits 15-31: Reserved */ -/* Load Enable Register */ - -#define PWM_LER_M0EN (1 << 0) /* Bit 0: Enable PWM Match 0 Latch */ -#define PWM_LER_M1EN (1 << 1) /* Bit 1: Enable PWM Match 1 Latch */ -#define PWM_LER_M2EN (1 << 2) /* Bit 2: Enable PWM Match 2 Latch */ -#define PWM_LER_M3EN (1 << 3) /* Bit 3: Enable PWM Match 3 Latch */ -#define PWM_LER_M4EN (1 << 4) /* Bit 4: Enable PWM Match 4 Latch */ -#define PWM_LER_M5EN (1 << 5) /* Bit 5: Enable PWM Match 5 Latch */ -#define PWM_LER_M6EN (1 << 6) /* Bit 6: Enable PWM Match 6 Latch */ - /* Bits 7-31: Reserved */ -/* Counter/Timer Control Register */ - -#define PWM_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */ -#define PWM_CTCR_MODE_MASK (3 << PWM_CTCR_MODE_SHIFT) -# define PWM_CTCR_MODE_TIMER (0 << PWM_CTCR_MODE_SHIFT) /* Timer Mode, prescal match */ -# define PWM_CTCR_MODE_CNTRRE (1 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */ -# define PWM_CTCR_MODE_CNTRFE (2 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */ -# define PWM_CTCR_MODE_CNTRBE (3 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */ -#define PWM_CTCR_INPSEL_SHIFT (2) /* Bits 2-3: Count Input Select */ -#define PWM_CTCR_INPSEL_MASK (3 << PWM_CTCR_INPSEL_SHIFT) -# define PWM_CTCR_INPSEL_CAPNp0 (0 << PWM_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */ -# define PWM_CTCR_INPSEL_CAPNp1 (1 << PWM_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */ - /* Bits 4-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_PWM_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_pwm.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_PWM_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_PWM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_PWM_IR_OFFSET 0x0000 /* Interrupt Register */ +#define LPC17_PWM_TCR_OFFSET 0x0004 /* Timer Control Register */ +#define LPC17_PWM_TC_OFFSET 0x0008 /* Timer Counter */ +#define LPC17_PWM_PR_OFFSET 0x000c /* Prescale Register */ +#define LPC17_PWM_PC_OFFSET 0x0010 /* Prescale Counter */ +#define LPC17_PWM_MCR_OFFSET 0x0014 /* Match Control Register */ +#define LPC17_PWM_MR0_OFFSET 0x0018 /* Match Register 0 */ +#define LPC17_PWM_MR1_OFFSET 0x001c /* Match Register 1 */ +#define LPC17_PWM_MR2_OFFSET 0x0020 /* Match Register 2 */ +#define LPC17_PWM_MR3_OFFSET 0x0024 /* Match Register 3 */ +#define LPC17_PWM_CCR_OFFSET 0x0028 /* Capture Control Register */ +#define LPC17_PWM_CR0_OFFSET 0x002c /* Capture Register 0 */ +#define LPC17_PWM_CR1_OFFSET 0x0030 /* Capture Register 1 */ +#define LPC17_PWM_CR2_OFFSET 0x0034 /* Capture Register 2 */ +#define LPC17_PWM_CR3_OFFSET 0x0038 /* Capture Register 3 */ +#define LPC17_PWM_MR4_OFFSET 0x0040 /* Match Register 4 */ +#define LPC17_PWM_MR5_OFFSET 0x0044 /* Match Register 5 */ +#define LPC17_PWM_MR6_OFFSET 0x0048 /* Match Register 6 */ +#define LPC17_PWM_PCR_OFFSET 0x004c /* PWM Control Register */ +#define LPC17_PWM_LER_OFFSET 0x0050 /* Load Enable Register */ +#define LPC17_PWM_CTCR_OFFSET 0x0070 /* Counter/Timer Control Register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_PWM1_IR (LPC17_PWM1_BASE+LPC17_PWM_IR_OFFSET) +#define LPC17_PWM1_TCR (LPC17_PWM1_BASE+LPC17_PWM_TCR_OFFSET) +#define LPC17_PWM1_TC (LPC17_PWM1_BASE+LPC17_PWM_TC_OFFSET) +#define LPC17_PWM1_PR (LPC17_PWM1_BASE+LPC17_PWM_PR_OFFSET) +#define LPC17_PWM1_PC (LPC17_PWM1_BASE+LPC17_PWM_PC_OFFSET) +#define LPC17_PWM1_MCR (LPC17_PWM1_BASE+LPC17_PWM_MCR_OFFSET) +#define LPC17_PWM1_MR0 (LPC17_PWM1_BASE+LPC17_PWM_MR0_OFFSET) +#define LPC17_PWM1_MR1 (LPC17_PWM1_BASE+LPC17_PWM_MR1_OFFSET) +#define LPC17_PWM1_MR2 (LPC17_PWM1_BASE+LPC17_PWM_MR2_OFFSET) +#define LPC17_PWM1_MR3 (LPC17_PWM1_BASE+LPC17_PWM_MR3_OFFSET) +#define LPC17_PWM1_MR4 (LPC17_PWM1_BASE+LPC17_PWM_MR4_OFFSET) +#define LPC17_PWM1_MR5 (LPC17_PWM1_BASE+LPC17_PWM_MR5_OFFSET) +#define LPC17_PWM1_MR6 (LPC17_PWM1_BASE+LPC17_PWM_MR6_OFFSET) +#define LPC17_PWM1_CCR (LPC17_PWM1_BASE+LPC17_PWM_CCR_OFFSET) +#define LPC17_PWM1_CR0 (LPC17_PWM1_BASE+LPC17_PWM_CR0_OFFSET) +#define LPC17_PWM1_CR1 (LPC17_PWM1_BASE+LPC17_PWM_CR1_OFFSET) +#define LPC17_PWM1_CR2 (LPC17_PWM1_BASE+LPC17_PWM_CR2_OFFSET) +#define LPC17_PWM1_CR3 (LPC17_PWM1_BASE+LPC17_PWM_CR3_OFFSET) +#define LPC17_PWM1_PCR (LPC17_PWM1_BASE+LPC17_PWM_PCR_OFFSET) +#define LPC17_PWM1_LER (LPC17_PWM1_BASE+LPC17_PWM_LER_OFFSET) +#define LPC17_PWM1_CTCR (LPC17_PWM1_BASE+LPC17_PWM_CTCR_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Registers holding 32-bit numeric values (no bit field definitions): + * + * Timer Counter (TC) + * Prescale Register (PR) + * Prescale Counter (PC) + * Match Register 0 (MR0) + * Match Register 1 (MR1) + * Match Register 2 (MR2) + * Match Register 3 (MR3) + * Match Register 4 (MR3) + * Match Register 5 (MR3) + * Match Register 6 (MR3) + * Capture Register 0 (CR0) + * Capture Register 1 (CR1) + * Capture Register 1 (CR2) + * Capture Register 1 (CR3) + */ + +/* Interrupt Register */ + +#define PWM_IR_MR0 (1 << 0) /* Bit 0: PWM match channel 0 interrrupt */ +#define PWM_IR_MR1 (1 << 1) /* Bit 1: PWM match channel 1 interrrupt */ +#define PWM_IR_MR2 (1 << 2) /* Bit 2: PWM match channel 2 interrrupt */ +#define PWM_IR_MR3 (1 << 3) /* Bit 3: PWM match channel 3 interrrupt */ +#define PWM_IR_CAP0 (1 << 4) /* Bit 4: Capture input 0 interrrupt */ +#define PWM_IR_CAP1 (1 << 5) /* Bit 5: Capture input 1 interrrupt */ + /* Bits 6-7: Reserved */ +#define PWM_IR_MR4 (1 << 8) /* Bit 8: PWM match channel 4 interrrupt */ +#define PWM_IR_MR5 (1 << 9) /* Bit 9: PWM match channel 5 interrrupt */ +#define PWM_IR_MR6 (1 << 10) /* Bit 10: PWM match channel 6 interrrupt */ + /* Bits 11-31: Reserved */ +/* Timer Control Register */ + +#define PWM_TCR_CNTREN (1 << 0) /* Bit 0: Counter Enable */ +#define PWM_TCR_CNTRRST (1 << 1) /* Bit 1: Counter Reset */ + /* Bit 2: Reserved */ +#define PWM_TCR_PWMEN (1 << 3) /* Bit 3: PWM Enable */ + /* Bits 4-31: Reserved */ +/* Match Control Register */ + +#define PWM_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */ +#define PWM_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */ +#define PWM_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */ +#define PWM_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */ +#define PWM_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */ +#define PWM_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */ +#define PWM_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */ +#define PWM_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */ +#define PWM_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */ +#define PWM_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */ +#define PWM_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */ +#define PWM_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */ +#define PWM_MCR_MR4I (1 << 12) /* Bit 12: Interrupt on MR4 */ +#define PWM_MCR_MR4R (1 << 13) /* Bit 13: Reset on MR4 */ +#define PWM_MCR_MR4S (1 << 14) /* Bit 14: Stop on MR4 */ +#define PWM_MCR_MR5I (1 << 15) /* Bit 15: Interrupt on MR5 */ +#define PWM_MCR_MR5R (1 << 16) /* Bit 16: Reset on MR5*/ +#define PWM_MCR_MR5S (1 << 17) /* Bit 17: Stop on MR5 */ +#define PWM_MCR_MR6I (1 << 18) /* Bit 18: Interrupt on MR6 */ +#define PWM_MCR_MR6R (1 << 19) /* Bit 19: Reset on MR6 */ +#define PWM_MCR_MR6S (1 << 20) /* Bit 20: Stop on MR6 */ + /* Bits 21-31: Reserved */ +/* Capture Control Register (Where are CAP2 and 3?) */ + +#define PWM_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */ +#define PWM_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edg */ +#define PWM_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */ +#define PWM_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */ +#define PWM_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edg */ +#define PWM_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */ + /* Bits 6-31: Reserved */ +/* PWM Control Register */ + /* Bits 0-1: Reserved */ +#define PWM_PCR_SEL2 (1 << 2) /* Bit 2: PWM2 single edge controlled mode */ +#define PWM_PCR_SEL3 (1 << 3) /* Bit 3: PWM3 single edge controlled mode */ +#define PWM_PCR_SEL4 (1 << 4) /* Bit 4: PWM4 single edge controlled mode */ +#define PWM_PCR_SEL5 (1 << 5) /* Bit 5: PWM5 single edge controlled mode */ +#define PWM_PCR_SEL6 (1 << 6) /* Bit 6: PWM6 single edge controlled mode */ + /* Bits 7-8: Reserved */ +#define PWM_PCR_ENA1 (1 << 9) /* Bit 9: Enable PWM1 output */ +#define PWM_PCR_ENA2 (1 << 10) /* Bit 10: Enable PWM2 output */ +#define PWM_PCR_ENA3 (1 << 11) /* Bit 11: Enable PWM3 output */ +#define PWM_PCR_ENA4 (1 << 12) /* Bit 12: Enable PWM4 output */ +#define PWM_PCR_ENA5 (1 << 13) /* Bit 13: Enable PWM5 output */ +#define PWM_PCR_ENA6 (1 << 14) /* Bit 14: Enable PWM6 output */ + /* Bits 15-31: Reserved */ +/* Load Enable Register */ + +#define PWM_LER_M0EN (1 << 0) /* Bit 0: Enable PWM Match 0 Latch */ +#define PWM_LER_M1EN (1 << 1) /* Bit 1: Enable PWM Match 1 Latch */ +#define PWM_LER_M2EN (1 << 2) /* Bit 2: Enable PWM Match 2 Latch */ +#define PWM_LER_M3EN (1 << 3) /* Bit 3: Enable PWM Match 3 Latch */ +#define PWM_LER_M4EN (1 << 4) /* Bit 4: Enable PWM Match 4 Latch */ +#define PWM_LER_M5EN (1 << 5) /* Bit 5: Enable PWM Match 5 Latch */ +#define PWM_LER_M6EN (1 << 6) /* Bit 6: Enable PWM Match 6 Latch */ + /* Bits 7-31: Reserved */ +/* Counter/Timer Control Register */ + +#define PWM_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */ +#define PWM_CTCR_MODE_MASK (3 << PWM_CTCR_MODE_SHIFT) +# define PWM_CTCR_MODE_TIMER (0 << PWM_CTCR_MODE_SHIFT) /* Timer Mode, prescal match */ +# define PWM_CTCR_MODE_CNTRRE (1 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */ +# define PWM_CTCR_MODE_CNTRFE (2 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */ +# define PWM_CTCR_MODE_CNTRBE (3 << PWM_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */ +#define PWM_CTCR_INPSEL_SHIFT (2) /* Bits 2-3: Count Input Select */ +#define PWM_CTCR_INPSEL_MASK (3 << PWM_CTCR_INPSEL_SHIFT) +# define PWM_CTCR_INPSEL_CAPNp0 (0 << PWM_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */ +# define PWM_CTCR_INPSEL_CAPNp1 (1 << PWM_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */ + /* Bits 4-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_PWM_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_qei.h b/arch/arm/src/lpc17xx/lpc17_qei.h index 2c37051b133a0a08ff589c9b88b90928b6c2cc20..d1637f943220983fbfcf54590665ebbb610b7261 100644 --- a/arch/arm/src/lpc17xx/lpc17_qei.h +++ b/arch/arm/src/lpc17xx/lpc17_qei.h @@ -1,190 +1,190 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_qei.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ -/* Control registers */ - -#define LPC17_QEI_CON_OFFSET 0x0000 /* Control register */ -#define LPC17_QEI_STAT_OFFSET 0x0004 /* Encoder status register */ -#define LPC17_QEI_CONF_OFFSET 0x0008 /* Configuration register */ - -/* Position, index, and timer registers */ - -#define LPC17_QEI_POS_OFFSET 0x000c /* Position register */ -#define LPC17_QEI_MAXPOS_OFFSET 0x0010 /* Maximum position register */ -#define LPC17_QEI_CMPOS0_OFFSET 0x0014 /* Position compare register */ -#define LPC17_QEI_CMPOS1_OFFSET 0x0018 /* Position compare register */ -#define LPC17_QEI_CMPOS2_OFFSET 0x001c /* Position compare register */ -#define LPC17_QEI_INXCNT_OFFSET 0x0020 /* Index count register */ -#define LPC17_QEI_INXCMP_OFFSET 0x0024 /* Index compare register */ -#define LPC17_QEI_LOAD_OFFSET 0x0028 /* Velocity timer reload register */ -#define LPC17_QEI_TIME_OFFSET 0x002c /* Velocity timer register */ -#define LPC17_QEI_VEL_OFFSET 0x0030 /* Velocity counter register */ -#define LPC17_QEI_CAP_OFFSET 0x0034 /* Velocity capture register */ -#define LPC17_QEI_VELCOMP_OFFSET 0x0038 /* Velocity compare register */ -#define LPC17_QEI_FILTER_OFFSET 0x003c /* Digital filter register */ - -/* Interrupt registers */ - -#define LPC17_QEI_IEC_OFFSET 0x0fd8 /* Interrupt enable clear register */ -#define LPC17_QEI_IES_OFFSET 0x0fdc /* Interrupt enable set register */ -#define LPC17_QEI_INTSTAT_OFFSET 0x0fe0 /* Interrupt status register */ -#define LPC17_QEI_IE_OFFSET 0x0fe4 /* Interrupt enable register */ -#define LPC17_QEI_CLR_OFFSET 0x0fe8 /* Interrupt status clear register */ -#define LPC17_QEI_SET_OFFSET 0x0fec /* Interrupt status set register */ - -/* Register addresses ***************************************************************/ -/* Control registers */ - -#define LPC17_QEI_CON (LPC17_QEI_BASE+LPC17_QEI_CON_OFFSET) -#define LPC17_QEI_STAT (LPC17_QEI_BASE+LPC17_QEI_STAT_OFFSET) -#define LPC17_QEI_CONF (LPC17_QEI_BASE+LPC17_QEI_CONF_OFFSET) - -/* Position, index, and timer registers */ - -#define LPC17_QEI_POS (LPC17_QEI_BASE+LPC17_QEI_POS_OFFSET) -#define LPC17_QEI_MAXPOS (LPC17_QEI_BASE+LPC17_QEI_MAXPOS_OFFSET) -#define LPC17_QEI_CMPOS0 (LPC17_QEI_BASE+LPC17_QEI_CMPOS0_OFFSET) -#define LPC17_QEI_CMPOS1 (LPC17_QEI_BASE+LPC17_QEI_CMPOS1_OFFSET) -#define LPC17_QEI_CMPOS2 (LPC17_QEI_BASE+LPC17_QEI_CMPOS2_OFFSET) -#define LPC17_QEI_INXCNT (LPC17_QEI_BASE+LPC17_QEI_INXCNT_OFFSET) -#define LPC17_QEI_INXCMP (LPC17_QEI_BASE+LPC17_QEI_INXCMP_OFFSET) -#define LPC17_QEI_LOAD (LPC17_QEI_BASE+LPC17_QEI_LOAD_OFFSET) -#define LPC17_QEI_TIME (LPC17_QEI_BASE+LPC17_QEI_TIME_OFFSET) -#define LPC17_QEI_VEL (LPC17_QEI_BASE+LPC17_QEI_VEL_OFFSET) -#define LPC17_QEI_CAP (LPC17_QEI_BASE+LPC17_QEI_CAP_OFFSET) -#define LPC17_QEI_VELCOMP (LPC17_QEI_BASE+LPC17_QEI_VELCOMP_OFFSET) -#define LPC17_QEI_FILTER (LPC17_QEI_BASE+LPC17_QEI_FILTER_OFFSET) - -/* Interrupt registers */ - -#define LPC17_QEI_IEC (LPC17_QEI_BASE+LPC17_QEI_IEC_OFFSET) -#define LPC17_QEI_IES (LPC17_QEI_BASE+LPC17_QEI_IES_OFFSET) -#define LPC17_QEI_INTSTAT (LPC17_QEI_BASE+LPC17_QEI_INTSTAT_OFFSET) -#define LPC17_QEI_IE (LPC17_QEI_BASE+LPC17_QEI_IE_OFFSET) -#define LPC17_QEI_CLR (LPC17_QEI_BASE+LPC17_QEI_CLR_OFFSET) -#define LPC17_QEI_SET (LPC17_QEI_BASE+LPC17_QEI_SET_OFFSET) - -/* Register bit definitions *********************************************************/ -/* The following registers hold 32-bit integer values and have no bit fields defined - * in this section: - * - * Position register (POS) - * Maximum position register (MAXPOS) - * Position compare register 0 (CMPOS0) - * Position compare register 1 (CMPOS) - * Position compare register 2 (CMPOS2) - * Index count register (INXCNT) - * Index compare register (INXCMP) - * Velocity timer reload register (LOAD) - * Velocity timer register (TIME) - * Velocity counter register (VEL) - * Velocity capture register (CAP) - * Velocity compare register (VELCOMP) - * Digital filter register (FILTER) - */ - -/* Control registers */ -/* Control register */ - -#define QEI_CON_RESP (1 << 0) /* Bit 0: Reset position counter */ -#define QEI_CON_RESPI (1 << 1) /* Bit 1: Reset position counter on index */ -#define QEI_CON_RESV (1 << 2) /* Bit 2: Reset velocity */ -#define QEI_CON_RESI (1 << 3) /* Bit 3: Reset index counter */ - /* Bits 4-31: reserved */ -/* Encoder status register */ - -#define QEI_STAT_DIR (1 << 0) /* Bit 0: Direction bit */ - /* Bits 1-31: reserved */ -/* Configuration register */ - -#define QEI_CONF_DIRINV (1 << 0) /* Bit 0: Direction invert */ -#define QEI_CONF_SIGMODE (1 << 1) /* Bit 1: Signal Mode */ -#define QEI_CONF_CAPMODE (1 << 2) /* Bit 2: Capture Mode */ -#define QEI_CONF_INVINX (1 << 3) /* Bit 3: Invert Index */ - /* Bits 4-31: reserved */ -/* Position, index, and timer registers (all 32-bit integer values with not bit fields */ - -/* Interrupt registers */ -/* Interrupt enable clear register (IEC), Interrupt enable set register (IES), - * Interrupt status register (INTSTAT), Interrupt enable register (IE), Interrupt - * status clear register (CLR), and Interrupt status set register (SET) common - * bit definitions. - */ - -#define QEI_INT_INX (1 << 0) /* Bit 0: Index pulse detected */ -#define QEI_INT_TIM (1 << 1) /* Bit 1: Velocity timer overflow occurred */ -#define QEI_INT_VELC (1 << 2) /* Bit 2: Captured velocity less than compare velocity */ -#define QEI_INT_DIR (1 << 3) /* Bit 3: Change of direction detected */ -#define QEI_INT_ERR (1 << 4) /* Bit 4: Encoder phase error detected */ -#define QEI_INT_ENCLK (1 << 5) /* Bit 5: Eencoder clock pulse detected */ -#define QEI_INT_POS0 (1 << 6) /* Bit 6: Position 0 compare equal to current position */ -#define QEI_INT_POS1 (1 << 7) /* Bit 7: Position 1 compare equal to current position */ -#define QEI_INT_POS2 (1 << 8) /* Bit 8: Position 2 compare equal to current position */ -#define QEI_INT_REV (1 << 9) /* Bit 9: Index compare value equal to current index count */ -#define QEI_INT_POS0REV (1 << 10) /* Bit 10: Combined position 0 and revolution count interrupt */ -#define QEI_INT_POS1REV (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */ -#define QEI_INT_POS2REV (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */ - /* Bits 13-31: reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_qei.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* Control registers */ + +#define LPC17_QEI_CON_OFFSET 0x0000 /* Control register */ +#define LPC17_QEI_STAT_OFFSET 0x0004 /* Encoder status register */ +#define LPC17_QEI_CONF_OFFSET 0x0008 /* Configuration register */ + +/* Position, index, and timer registers */ + +#define LPC17_QEI_POS_OFFSET 0x000c /* Position register */ +#define LPC17_QEI_MAXPOS_OFFSET 0x0010 /* Maximum position register */ +#define LPC17_QEI_CMPOS0_OFFSET 0x0014 /* Position compare register */ +#define LPC17_QEI_CMPOS1_OFFSET 0x0018 /* Position compare register */ +#define LPC17_QEI_CMPOS2_OFFSET 0x001c /* Position compare register */ +#define LPC17_QEI_INXCNT_OFFSET 0x0020 /* Index count register */ +#define LPC17_QEI_INXCMP_OFFSET 0x0024 /* Index compare register */ +#define LPC17_QEI_LOAD_OFFSET 0x0028 /* Velocity timer reload register */ +#define LPC17_QEI_TIME_OFFSET 0x002c /* Velocity timer register */ +#define LPC17_QEI_VEL_OFFSET 0x0030 /* Velocity counter register */ +#define LPC17_QEI_CAP_OFFSET 0x0034 /* Velocity capture register */ +#define LPC17_QEI_VELCOMP_OFFSET 0x0038 /* Velocity compare register */ +#define LPC17_QEI_FILTER_OFFSET 0x003c /* Digital filter register */ + +/* Interrupt registers */ + +#define LPC17_QEI_IEC_OFFSET 0x0fd8 /* Interrupt enable clear register */ +#define LPC17_QEI_IES_OFFSET 0x0fdc /* Interrupt enable set register */ +#define LPC17_QEI_INTSTAT_OFFSET 0x0fe0 /* Interrupt status register */ +#define LPC17_QEI_IE_OFFSET 0x0fe4 /* Interrupt enable register */ +#define LPC17_QEI_CLR_OFFSET 0x0fe8 /* Interrupt status clear register */ +#define LPC17_QEI_SET_OFFSET 0x0fec /* Interrupt status set register */ + +/* Register addresses ***************************************************************/ +/* Control registers */ + +#define LPC17_QEI_CON (LPC17_QEI_BASE+LPC17_QEI_CON_OFFSET) +#define LPC17_QEI_STAT (LPC17_QEI_BASE+LPC17_QEI_STAT_OFFSET) +#define LPC17_QEI_CONF (LPC17_QEI_BASE+LPC17_QEI_CONF_OFFSET) + +/* Position, index, and timer registers */ + +#define LPC17_QEI_POS (LPC17_QEI_BASE+LPC17_QEI_POS_OFFSET) +#define LPC17_QEI_MAXPOS (LPC17_QEI_BASE+LPC17_QEI_MAXPOS_OFFSET) +#define LPC17_QEI_CMPOS0 (LPC17_QEI_BASE+LPC17_QEI_CMPOS0_OFFSET) +#define LPC17_QEI_CMPOS1 (LPC17_QEI_BASE+LPC17_QEI_CMPOS1_OFFSET) +#define LPC17_QEI_CMPOS2 (LPC17_QEI_BASE+LPC17_QEI_CMPOS2_OFFSET) +#define LPC17_QEI_INXCNT (LPC17_QEI_BASE+LPC17_QEI_INXCNT_OFFSET) +#define LPC17_QEI_INXCMP (LPC17_QEI_BASE+LPC17_QEI_INXCMP_OFFSET) +#define LPC17_QEI_LOAD (LPC17_QEI_BASE+LPC17_QEI_LOAD_OFFSET) +#define LPC17_QEI_TIME (LPC17_QEI_BASE+LPC17_QEI_TIME_OFFSET) +#define LPC17_QEI_VEL (LPC17_QEI_BASE+LPC17_QEI_VEL_OFFSET) +#define LPC17_QEI_CAP (LPC17_QEI_BASE+LPC17_QEI_CAP_OFFSET) +#define LPC17_QEI_VELCOMP (LPC17_QEI_BASE+LPC17_QEI_VELCOMP_OFFSET) +#define LPC17_QEI_FILTER (LPC17_QEI_BASE+LPC17_QEI_FILTER_OFFSET) + +/* Interrupt registers */ + +#define LPC17_QEI_IEC (LPC17_QEI_BASE+LPC17_QEI_IEC_OFFSET) +#define LPC17_QEI_IES (LPC17_QEI_BASE+LPC17_QEI_IES_OFFSET) +#define LPC17_QEI_INTSTAT (LPC17_QEI_BASE+LPC17_QEI_INTSTAT_OFFSET) +#define LPC17_QEI_IE (LPC17_QEI_BASE+LPC17_QEI_IE_OFFSET) +#define LPC17_QEI_CLR (LPC17_QEI_BASE+LPC17_QEI_CLR_OFFSET) +#define LPC17_QEI_SET (LPC17_QEI_BASE+LPC17_QEI_SET_OFFSET) + +/* Register bit definitions *********************************************************/ +/* The following registers hold 32-bit integer values and have no bit fields defined + * in this section: + * + * Position register (POS) + * Maximum position register (MAXPOS) + * Position compare register 0 (CMPOS0) + * Position compare register 1 (CMPOS) + * Position compare register 2 (CMPOS2) + * Index count register (INXCNT) + * Index compare register (INXCMP) + * Velocity timer reload register (LOAD) + * Velocity timer register (TIME) + * Velocity counter register (VEL) + * Velocity capture register (CAP) + * Velocity compare register (VELCOMP) + * Digital filter register (FILTER) + */ + +/* Control registers */ +/* Control register */ + +#define QEI_CON_RESP (1 << 0) /* Bit 0: Reset position counter */ +#define QEI_CON_RESPI (1 << 1) /* Bit 1: Reset position counter on index */ +#define QEI_CON_RESV (1 << 2) /* Bit 2: Reset velocity */ +#define QEI_CON_RESI (1 << 3) /* Bit 3: Reset index counter */ + /* Bits 4-31: reserved */ +/* Encoder status register */ + +#define QEI_STAT_DIR (1 << 0) /* Bit 0: Direction bit */ + /* Bits 1-31: reserved */ +/* Configuration register */ + +#define QEI_CONF_DIRINV (1 << 0) /* Bit 0: Direction invert */ +#define QEI_CONF_SIGMODE (1 << 1) /* Bit 1: Signal Mode */ +#define QEI_CONF_CAPMODE (1 << 2) /* Bit 2: Capture Mode */ +#define QEI_CONF_INVINX (1 << 3) /* Bit 3: Invert Index */ + /* Bits 4-31: reserved */ +/* Position, index, and timer registers (all 32-bit integer values with not bit fields */ + +/* Interrupt registers */ +/* Interrupt enable clear register (IEC), Interrupt enable set register (IES), + * Interrupt status register (INTSTAT), Interrupt enable register (IE), Interrupt + * status clear register (CLR), and Interrupt status set register (SET) common + * bit definitions. + */ + +#define QEI_INT_INX (1 << 0) /* Bit 0: Index pulse detected */ +#define QEI_INT_TIM (1 << 1) /* Bit 1: Velocity timer overflow occurred */ +#define QEI_INT_VELC (1 << 2) /* Bit 2: Captured velocity less than compare velocity */ +#define QEI_INT_DIR (1 << 3) /* Bit 3: Change of direction detected */ +#define QEI_INT_ERR (1 << 4) /* Bit 4: Encoder phase error detected */ +#define QEI_INT_ENCLK (1 << 5) /* Bit 5: Eencoder clock pulse detected */ +#define QEI_INT_POS0 (1 << 6) /* Bit 6: Position 0 compare equal to current position */ +#define QEI_INT_POS1 (1 << 7) /* Bit 7: Position 1 compare equal to current position */ +#define QEI_INT_POS2 (1 << 8) /* Bit 8: Position 2 compare equal to current position */ +#define QEI_INT_REV (1 << 9) /* Bit 9: Index compare value equal to current index count */ +#define QEI_INT_POS0REV (1 << 10) /* Bit 10: Combined position 0 and revolution count interrupt */ +#define QEI_INT_POS1REV (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */ +#define QEI_INT_POS2REV (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */ + /* Bits 13-31: reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_rit.h b/arch/arm/src/lpc17xx/lpc17_rit.h index 57d89de95e440f7173083fa81c6410fe835d31ad..2da0164bdef33dd9cbfd584fe745867e62081b7a 100644 --- a/arch/arm/src/lpc17xx/lpc17_rit.h +++ b/arch/arm/src/lpc17xx/lpc17_rit.h @@ -1,92 +1,92 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_rit.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_RIT_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_RIT_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_RIT_COMPVAL_OFFSET 0x0000 /* Compare register */ -#define LPC17_RIT_MASK_OFFSET 0x0004 /* Mask register */ -#define LPC17_RIT_CTRL_OFFSET 0x0008 /* Control register */ -#define LPC17_RIT_COUNTER_OFFSET 0x000c /* 32-bit counter */ - -/* Register addresses ***************************************************************/ - -#define LPC17_RIT_COMPVAL (LPC17_RIT_BASE+LPC17_RIT_COMPVAL_OFFSET) -#define LPC17_RIT_MASK (LPC17_RIT_BASE+LPC17_RIT_MASK_OFFSET) -#define LPC17_RIT_CTRL (LPC17_RIT_BASE+LPC17_RIT_CTRL_OFFSET) -#define LPC17_RIT_COUNTER (LPC17_RIT_BASE+LPC17_RIT_COUNTER_OFFSET) - -/* Register bit definitions *********************************************************/ -/* Compare register (Bits 0-31: value compared to the counter) */ - -/* Mask register (Bits 0-31: 32-bit mask value) */ - -/* Control register */ - -#define RIT_CTRL_INT (1 << 0) /* Bit 0: Interrupt flag */ -#define RIT_CTRL_ENCLR (1 << 1) /* Bit 1: Timer enable clear */ -#define RIT_CTRL_ENBR (1 << 2) /* Bit 2: Timer enable for debug */ -#define RIT_CTRL_EN (1 << 3) /* Bit 3: Timer enable */ - /* Bits 4-31: Reserved */ -/* 32-bit counter (Bits 0-31: 32-bit up counter) */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_RIT_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_rit.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_RIT_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_RIT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_RIT_COMPVAL_OFFSET 0x0000 /* Compare register */ +#define LPC17_RIT_MASK_OFFSET 0x0004 /* Mask register */ +#define LPC17_RIT_CTRL_OFFSET 0x0008 /* Control register */ +#define LPC17_RIT_COUNTER_OFFSET 0x000c /* 32-bit counter */ + +/* Register addresses ***************************************************************/ + +#define LPC17_RIT_COMPVAL (LPC17_RIT_BASE+LPC17_RIT_COMPVAL_OFFSET) +#define LPC17_RIT_MASK (LPC17_RIT_BASE+LPC17_RIT_MASK_OFFSET) +#define LPC17_RIT_CTRL (LPC17_RIT_BASE+LPC17_RIT_CTRL_OFFSET) +#define LPC17_RIT_COUNTER (LPC17_RIT_BASE+LPC17_RIT_COUNTER_OFFSET) + +/* Register bit definitions *********************************************************/ +/* Compare register (Bits 0-31: value compared to the counter) */ + +/* Mask register (Bits 0-31: 32-bit mask value) */ + +/* Control register */ + +#define RIT_CTRL_INT (1 << 0) /* Bit 0: Interrupt flag */ +#define RIT_CTRL_ENCLR (1 << 1) /* Bit 1: Timer enable clear */ +#define RIT_CTRL_ENBR (1 << 2) /* Bit 2: Timer enable for debug */ +#define RIT_CTRL_EN (1 << 3) /* Bit 3: Timer enable */ + /* Bits 4-31: Reserved */ +/* 32-bit counter (Bits 0-31: 32-bit up counter) */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_RIT_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_serial.h b/arch/arm/src/lpc17xx/lpc17_serial.h index 9fca96219d743dcab580179a0c697f97d04e88b1..27d7da9d135dbcbb375f998c91b5f56788579b67 100644 --- a/arch/arm/src/lpc17xx/lpc17_serial.h +++ b/arch/arm/src/lpc17xx/lpc17_serial.h @@ -1,127 +1,127 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_serial.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#include "lpc17_uart.h" -#include "lpc17_syscon.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Configuration *********************************************************************/ - -/* Are any UARTs enabled? */ - -#undef HAVE_UART -#if defined(CONFIG_LPC17_UART0) || defined(CONFIG_LPC17_UART1) || \ - defined(CONFIG_LPC17_UART2) || defined(CONFIG_LPC17_UART3) -# define HAVE_UART 1 -#endif - -/* Is there a serial console? There should be at most one defined. It could be on - * any UARTn, n=0,1,2,3 - */ - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART0) -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART1) -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART2) -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART3) -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# define HAVE_CONSOLE 1 -#else -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# undef HAVE_CONSOLE -#endif - -/* Check UART flow control (Only supported by UART1) */ - -# undef CONFIG_UART0_FLOWCONTROL -# undef CONFIG_UART2_FLOWCONTROL -# undef CONFIG_UART3_FLOWCONTROL -#ifndef CONFIG_LPC17_UART1 -# undef CONFIG_UART1_FLOWCONTROL -#endif - -/* We cannot allow the DLM/DLL divisor to become to small or will will lose too - * much accuracy. This following is a "fudge factor" that represents the minimum - * value of the divisor that we will permit. - */ - -#define UART_MINDL 32 - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_serial.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "lpc17_uart.h" +#include "lpc17_syscon.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration *********************************************************************/ + +/* Are any UARTs enabled? */ + +#undef HAVE_UART +#if defined(CONFIG_LPC17_UART0) || defined(CONFIG_LPC17_UART1) || \ + defined(CONFIG_LPC17_UART2) || defined(CONFIG_LPC17_UART3) +# define HAVE_UART 1 +#endif + +/* Is there a serial console? There should be at most one defined. It could be on + * any UARTn, n=0,1,2,3 + */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART3) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#else +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef HAVE_CONSOLE +#endif + +/* Check UART flow control (Only supported by UART1) */ + +# undef CONFIG_UART0_FLOWCONTROL +# undef CONFIG_UART2_FLOWCONTROL +# undef CONFIG_UART3_FLOWCONTROL +#ifndef CONFIG_LPC17_UART1 +# undef CONFIG_UART1_FLOWCONTROL +#endif + +/* We cannot allow the DLM/DLL divisor to become to small or will will lose too + * much accuracy. This following is a "fudge factor" that represents the minimum + * value of the divisor that we will permit. + */ + +#define UART_MINDL 32 + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_spi.c b/arch/arm/src/lpc17xx/lpc17_spi.c index f0a2b1264b8c3930acd8f7e25e687752a4f98d2a..a7bb1593170966a3ce2cea05cfec24dbff438f90 100644 --- a/arch/arm/src/lpc17xx/lpc17_spi.c +++ b/arch/arm/src/lpc17xx/lpc17_spi.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc17xx/lpc17_spi.c * * Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc17xx/lpc17_spi.h b/arch/arm/src/lpc17xx/lpc17_spi.h index ca7699c15efa87a4b7cc7f8cdf4b2029ed9b7c9b..880966eb1cdbe2ce375077120edac357bf6aaff9 100644 --- a/arch/arm/src/lpc17xx/lpc17_spi.h +++ b/arch/arm/src/lpc17xx/lpc17_spi.h @@ -1,141 +1,141 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_spi.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_SPI_CR_OFFSET 0x0000 /* Control Register */ -#define LPC17_SPI_SR_OFFSET 0x0004 /* SPI Status Register */ -#define LPC17_SPI_DR_OFFSET 0x0008 /* SPI Data Register */ -#define LPC17_SPI_CCR_OFFSET 0x000c /* SPI Clock Counter Register */ -#define LPC17_SPI_TCR_OFFSET 0x0010 /* SPI Test Control Register */ -#define LPC17_SPI_TSR_OFFSET 0x0014 /* SPI Test Status Register */ -#define LPC17_SPI_INT_OFFSET 0x001c /* SPI Interrupt Register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_SPI_CR (LPC17_SPI_BASE+LPC17_SPI_CR_OFFSET) -#define LPC17_SPI_SR (LPC17_SPI_BASE+LPC17_SPI_SR_OFFSET) -#define LPC17_SPI_DR (LPC17_SPI_BASE+LPC17_SPI_DR_OFFSET) -#define LPC17_SPI_CCR (LPC17_SPI_BASE+LPC17_SPI_CCR_OFFSET) -#define LPC17_TCR_CCR (LPC17_SPI_BASE+LPC17_SPI_TCR_OFFSET) -#define LPC17_TSR_CCR (LPC17_SPI_BASE+LPC17_SPI_TSR_OFFSET) -#define LPC17_SPI_INT (LPC17_SPI_BASE+LPC17_SPI_INT_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* Control Register */ - /* Bits 0-1: Reserved */ -#define SPI_CR_BITENABLE (1 << 2) /* Bit 2: Enable word size selected by BITS */ -#define SPI_CR_CPHA (1 << 3) /* Bit 3: Clock phase control */ -#define SPI_CR_CPOL (1 << 4) /* Bit 4: Clock polarity control */ -#define SPI_CR_MSTR (1 << 5) /* Bit 5: Master mode select */ -#define SPI_CR_LSBF (1 << 6) /* Bit 6: SPI data is transferred LSB first */ -#define SPI_CR_SPIE (1 << 7) /* Bit 7: Serial peripheral interrupt enable */ -#define SPI_CR_BITS_SHIFT (8) /* Bits 8-11: Number of bits per word (BITENABLE==1) */ -#define SPI_CR_BITS_MASK (15 << SPI_CR_BITS_SHIFT) -# define SPI_CR_BITS_8BITS (8 << SPI_CR_BITS_SHIFT) /* 8 bits per transfer */ -# define SPI_CR_BITS_9BITS (9 << SPI_CR_BITS_SHIFT) /* 9 bits per transfer */ -# define SPI_CR_BITS_10BITS (10 << SPI_CR_BITS_SHIFT) /* 10 bits per transfer */ -# define SPI_CR_BITS_11BITS (11 << SPI_CR_BITS_SHIFT) /* 11 bits per transfer */ -# define SPI_CR_BITS_12BITS (12 << SPI_CR_BITS_SHIFT) /* 12 bits per transfer */ -# define SPI_CR_BITS_13BITS (13 << SPI_CR_BITS_SHIFT) /* 13 bits per transfer */ -# define SPI_CR_BITS_14BITS (14 << SPI_CR_BITS_SHIFT) /* 14 bits per transfer */ -# define SPI_CR_BITS_15BITS (15 << SPI_CR_BITS_SHIFT) /* 15 bits per transfer */ -# define SPI_CR_BITS_16BITS (0 << SPI_CR_BITS_SHIFT) /* 16 bits per transfer */ - /* Bits 12-31: Reserved */ -/* SPI Status Register */ - /* Bits 0-2: Reserved */ -#define SPI_SR_ABRT (1 << 3) /* Bit 3: Slave abort */ -#define SPI_SR_MODF (1 << 4) /* Bit 4: Mode fault */ -#define SPI_SR_ROVR (1 << 5) /* Bit 5: Read overrun */ -#define SPI_SR_WCOL (1 << 6) /* Bit 6: Write collision */ -#define SPI_SR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */ - /* Bits 8-31: Reserved */ -/* SPI Data Register */ - -#define SPI_DR_MASK (0xff) /* Bits 0-15: SPI Bi-directional data port */ -#define SPI_DR_MASKWIDE (0xffff) /* Bits 0-15: If SPI_CR_BITENABLE != 0 */ - /* Bits 8-31: Reserved */ -/* SPI Clock Counter Register */ - -#define SPI_CCR_MASK (0xff) /* Bits 0-7: SPI Clock counter setting */ - /* Bits 8-31: Reserved */ -/* SPI Test Control Register */ - /* Bit 0: Reserved */ -#define SPI_TCR_TEST_SHIFT (1) /* Bits 1-7: SPI test mode */ -#define SPI_TCR_TEST_MASK (0x7f << SPI_TCR_TEST_SHIFT) - /* Bits 8-31: Reserved */ -/* SPI Test Status Register */ - /* Bits 0-2: Reserved */ -#define SPI_TSR_ABRT (1 << 3) /* Bit 3: Slave abort */ -#define SPI_TSR_MODF (1 << 4) /* Bit 4: Mode fault */ -#define SPI_TSR_ROVR (1 << 5) /* Bit 5: Read overrun */ -#define SPI_TSR_WCOL (1 << 6) /* Bit 6: Write collision */ -#define SPI_TSR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */ - /* Bits 8-31: Reserved */ -/* SPI Interrupt Register */ - -#define SPI_INT_SPIF (1 << 0) /* SPI interrupt */ - /* Bits 1-31: Reserved */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_spi.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_SPI_CR_OFFSET 0x0000 /* Control Register */ +#define LPC17_SPI_SR_OFFSET 0x0004 /* SPI Status Register */ +#define LPC17_SPI_DR_OFFSET 0x0008 /* SPI Data Register */ +#define LPC17_SPI_CCR_OFFSET 0x000c /* SPI Clock Counter Register */ +#define LPC17_SPI_TCR_OFFSET 0x0010 /* SPI Test Control Register */ +#define LPC17_SPI_TSR_OFFSET 0x0014 /* SPI Test Status Register */ +#define LPC17_SPI_INT_OFFSET 0x001c /* SPI Interrupt Register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_SPI_CR (LPC17_SPI_BASE+LPC17_SPI_CR_OFFSET) +#define LPC17_SPI_SR (LPC17_SPI_BASE+LPC17_SPI_SR_OFFSET) +#define LPC17_SPI_DR (LPC17_SPI_BASE+LPC17_SPI_DR_OFFSET) +#define LPC17_SPI_CCR (LPC17_SPI_BASE+LPC17_SPI_CCR_OFFSET) +#define LPC17_TCR_CCR (LPC17_SPI_BASE+LPC17_SPI_TCR_OFFSET) +#define LPC17_TSR_CCR (LPC17_SPI_BASE+LPC17_SPI_TSR_OFFSET) +#define LPC17_SPI_INT (LPC17_SPI_BASE+LPC17_SPI_INT_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* Control Register */ + /* Bits 0-1: Reserved */ +#define SPI_CR_BITENABLE (1 << 2) /* Bit 2: Enable word size selected by BITS */ +#define SPI_CR_CPHA (1 << 3) /* Bit 3: Clock phase control */ +#define SPI_CR_CPOL (1 << 4) /* Bit 4: Clock polarity control */ +#define SPI_CR_MSTR (1 << 5) /* Bit 5: Master mode select */ +#define SPI_CR_LSBF (1 << 6) /* Bit 6: SPI data is transferred LSB first */ +#define SPI_CR_SPIE (1 << 7) /* Bit 7: Serial peripheral interrupt enable */ +#define SPI_CR_BITS_SHIFT (8) /* Bits 8-11: Number of bits per word (BITENABLE==1) */ +#define SPI_CR_BITS_MASK (15 << SPI_CR_BITS_SHIFT) +# define SPI_CR_BITS_8BITS (8 << SPI_CR_BITS_SHIFT) /* 8 bits per transfer */ +# define SPI_CR_BITS_9BITS (9 << SPI_CR_BITS_SHIFT) /* 9 bits per transfer */ +# define SPI_CR_BITS_10BITS (10 << SPI_CR_BITS_SHIFT) /* 10 bits per transfer */ +# define SPI_CR_BITS_11BITS (11 << SPI_CR_BITS_SHIFT) /* 11 bits per transfer */ +# define SPI_CR_BITS_12BITS (12 << SPI_CR_BITS_SHIFT) /* 12 bits per transfer */ +# define SPI_CR_BITS_13BITS (13 << SPI_CR_BITS_SHIFT) /* 13 bits per transfer */ +# define SPI_CR_BITS_14BITS (14 << SPI_CR_BITS_SHIFT) /* 14 bits per transfer */ +# define SPI_CR_BITS_15BITS (15 << SPI_CR_BITS_SHIFT) /* 15 bits per transfer */ +# define SPI_CR_BITS_16BITS (0 << SPI_CR_BITS_SHIFT) /* 16 bits per transfer */ + /* Bits 12-31: Reserved */ +/* SPI Status Register */ + /* Bits 0-2: Reserved */ +#define SPI_SR_ABRT (1 << 3) /* Bit 3: Slave abort */ +#define SPI_SR_MODF (1 << 4) /* Bit 4: Mode fault */ +#define SPI_SR_ROVR (1 << 5) /* Bit 5: Read overrun */ +#define SPI_SR_WCOL (1 << 6) /* Bit 6: Write collision */ +#define SPI_SR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */ + /* Bits 8-31: Reserved */ +/* SPI Data Register */ + +#define SPI_DR_MASK (0xff) /* Bits 0-15: SPI Bi-directional data port */ +#define SPI_DR_MASKWIDE (0xffff) /* Bits 0-15: If SPI_CR_BITENABLE != 0 */ + /* Bits 8-31: Reserved */ +/* SPI Clock Counter Register */ + +#define SPI_CCR_MASK (0xff) /* Bits 0-7: SPI Clock counter setting */ + /* Bits 8-31: Reserved */ +/* SPI Test Control Register */ + /* Bit 0: Reserved */ +#define SPI_TCR_TEST_SHIFT (1) /* Bits 1-7: SPI test mode */ +#define SPI_TCR_TEST_MASK (0x7f << SPI_TCR_TEST_SHIFT) + /* Bits 8-31: Reserved */ +/* SPI Test Status Register */ + /* Bits 0-2: Reserved */ +#define SPI_TSR_ABRT (1 << 3) /* Bit 3: Slave abort */ +#define SPI_TSR_MODF (1 << 4) /* Bit 4: Mode fault */ +#define SPI_TSR_ROVR (1 << 5) /* Bit 5: Read overrun */ +#define SPI_TSR_WCOL (1 << 6) /* Bit 6: Write collision */ +#define SPI_TSR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */ + /* Bits 8-31: Reserved */ +/* SPI Interrupt Register */ + +#define SPI_INT_SPIF (1 << 0) /* SPI interrupt */ + /* Bits 1-31: Reserved */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SPI_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_syscon.h b/arch/arm/src/lpc17xx/lpc17_syscon.h index c9a2dbb54691948bc808b692b5a0c09502eeb490..ce8654645d20a627657b29bd72ab37eca270adcf 100644 --- a/arch/arm/src/lpc17xx/lpc17_syscon.h +++ b/arch/arm/src/lpc17xx/lpc17_syscon.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc17xx/lpc17_syscon.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc17xx/lpc17_timerisr.c b/arch/arm/src/lpc17xx/lpc17_timerisr.c index aa113463a9bc611bd08227bdda78ec78f6aa2771..918c153a4bae10b3d4de4f3ad35372cacf6cc192 100644 --- a/arch/arm/src/lpc17xx/lpc17_timerisr.c +++ b/arch/arm/src/lpc17xx/lpc17_timerisr.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc17xx/lpc17_timerisr.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc17xx/lpc17_usb.h b/arch/arm/src/lpc17xx/lpc17_usb.h index 40c491811efd4643862809455746d254ec64a2f4..8fd599584659ee8fa6acb64a69954929784a09c9 100644 --- a/arch/arm/src/lpc17xx/lpc17_usb.h +++ b/arch/arm/src/lpc17xx/lpc17_usb.h @@ -1,778 +1,778 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_usb.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ -/* USB Host Controller (OHCI) *******************************************************/ -/* See include/nuttx/usb/ohci.h */ - -#define LPC17_USBHOST_MODID_OFFSET 0x00fc /* Module ID/Revision ID */ - -/* USB OTG Controller ***************************************************************/ -/* OTG registers */ - -#define LPC17_USBOTG_INTST_OFFSET 0x0100 /* OTG Interrupt Status */ -#define LPC17_USBOTG_INTEN_OFFSET 0x0104 /* OTG Interrupt Enable */ -#define LPC17_USBOTG_INTSET_OFFSET 0x0108 /* OTG Interrupt Set */ -#define LPC17_USBOTG_INTCLR_OFFSET 0x010c /* OTG Interrupt Clear */ -#define LPC17_USBOTG_STCTRL_OFFSET 0x0110 /* OTG Status and Control */ -#define LPC17_USBOTG_TMR_OFFSET 0x0114 /* OTG Timer */ - -/* USB Device Controller ************************************************************/ -/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ - -#define LPC17_USBDEV_INTST_OFFSET 0x0200 /* USB Device Interrupt Status */ -#define LPC17_USBDEV_INTEN_OFFSET 0x0204 /* USB Device Interrupt Enable */ -#define LPC17_USBDEV_INTCLR_OFFSET 0x0208 /* USB Device Interrupt Clear */ -#define LPC17_USBDEV_INTSET_OFFSET 0x020c /* USB Device Interrupt Set */ - -/* SIE Command registers */ - -#define LPC17_USBDEV_CMDCODE_OFFSET 0x0210 /* USB Command Code */ -#define LPC17_USBDEV_CMDDATA_OFFSET 0x0214 /* USB Command Data */ - -/* USB transfer registers */ - -#define LPC17_USBDEV_RXDATA_OFFSET 0x0218 /* USB Receive Data */ -#define LPC17_USBDEV_RXPLEN_OFFSET 0x0220 /* USB Receive Packet Length */ -#define LPC17_USBDEV_TXDATA_OFFSET 0x021c /* USB Transmit Data */ -#define LPC17_USBDEV_TXPLEN_OFFSET 0x0224 /* USB Transmit Packet Length */ -#define LPC17_USBDEV_CTRL_OFFSET 0x0228 /* USB Control */ - -/* More Device interrupt registers */ - -#define LPC17_USBDEV_INTPRI_OFFSET 0x022c /* USB Device Interrupt Priority */ - -/* Endpoint interrupt registers */ - -#define LPC17_USBDEV_EPINTST_OFFSET 0x0230 /* USB Endpoint Interrupt Status */ -#define LPC17_USBDEV_EPINTEN_OFFSET 0x0234 /* USB Endpoint Interrupt Enable */ -#define LPC17_USBDEV_EPINTCLR_OFFSET 0x0238 /* USB Endpoint Interrupt Clear */ -#define LPC17_USBDEV_EPINTSET_OFFSET 0x023c /* USB Endpoint Interrupt Set */ -#define LPC17_USBDEV_EPINTPRI_OFFSET 0x0240 /* USB Endpoint Priority */ - -/* Endpoint realization registers */ - -#define LPC17_USBDEV_REEP_OFFSET 0x0244 /* USB Realize Endpoint */ -#define LPC17_USBDEV_EPIND_OFFSET 0x0248 /* USB Endpoint Index */ -#define LPC17_USBDEV_MAXPSIZE_OFFSET 0x024c /* USB MaxPacketSize */ - -/* DMA registers */ - -#define LPC17_USBDEV_DMARST_OFFSET 0x0250 /* USB DMA Request Status */ -#define LPC17_USBDEV_DMARCLR_OFFSET 0x0254 /* USB DMA Request Clear */ -#define LPC17_USBDEV_DMARSET_OFFSET 0x0258 /* USB DMA Request Set */ -#define LPC17_USBDEV_UDCAH_OFFSET 0x0280 /* USB UDCA Head */ -#define LPC17_USBDEV_EPDMAST_OFFSET 0x0284 /* USB Endpoint DMA Status */ -#define LPC17_USBDEV_EPDMAEN_OFFSET 0x0288 /* USB Endpoint DMA Enable */ -#define LPC17_USBDEV_EPDMADIS_OFFSET 0x028c /* USB Endpoint DMA Disable */ -#define LPC17_USBDEV_DMAINTST_OFFSET 0x0290 /* USB DMA Interrupt Status */ -#define LPC17_USBDEV_DMAINTEN_OFFSET 0x0294 /* USB DMA Interrupt Enable */ -#define LPC17_USBDEV_EOTINTST_OFFSET 0x02a0 /* USB End of Transfer Interrupt Status */ -#define LPC17_USBDEV_EOTINTCLR_OFFSET 0x02a4 /* USB End of Transfer Interrupt Clear */ -#define LPC17_USBDEV_EOTINTSET_OFFSET 0x02a8 /* USB End of Transfer Interrupt Set */ -#define LPC17_USBDEV_NDDRINTST_OFFSET 0x02ac /* USB New DD Request Interrupt Status */ -#define LPC17_USBDEV_NDDRINTCLR_OFFSET 0x02b0 /* USB New DD Request Interrupt Clear */ -#define LPC17_USBDEV_NDDRINTSET_OFFSET 0x02b4 /* USB New DD Request Interrupt Set */ -#define LPC17_USBDEV_SYSERRINTST_OFFSET 0x02b8 /* USB System Error Interrupt Status */ -#define LPC17_USBDEV_SYSERRINTCLR_OFFSET 0x02bc /* USB System Error Interrupt Clear */ -#define LPC17_USBDEV_SYSERRINTSET_OFFSET 0x02c0 /* USB System Error Interrupt Set */ - -/* OTG I2C registers ****************************************************************/ - -#define LPC17_OTGI2C_RX_OFFSET 0x0300 /* I2C Receive */ -#define LPC17_OTGI2C_TX_OFFSET 0x0300 /* I2C Transmit */ -#define LPC17_OTGI2C_STS_OFFSET 0x0304 /* I2C Status */ -#define LPC17_OTGI2C_CTL_OFFSET 0x0308 /* I2C Control */ -#define LPC17_OTGI2C_CLKHI_OFFSET 0x030c /* I2C Clock High */ -#define LPC17_OTGI2C_CLKLO_OFFSET 0x0310 /* I2C Clock Low */ - -/* Clock control registers ***********************************************************/ - -#define LPC17_USBOTG_CLKCTRL_OFFSET 0x0ff4 /* OTG clock controller */ -#define LPC17_USBOTG_CLKST_OFFSET 0x0ff8 /* OTG clock status */ - -#define LPC17_USBDEV_CLKCTRL_OFFSET 0x0ff4 /* USB Clock Control */ -#define LPC17_USBDEV_CLKST_OFFSET 0x0ff8 /* USB Clock Status */ - -/* Register addresses ***************************************************************/ -/* USB Host Controller (OHCI) *******************************************************/ -/* Control and status registers (section 7.1) */ - -#define LPC17_USBHOST_HCIREV (LPC17_USB_BASE+OHCI_HCIREV_OFFSET) -#define LPC17_USBHOST_CTRL (LPC17_USB_BASE+OHCI_CTRL_OFFSET) -#define LPC17_USBHOST_CMDST (LPC17_USB_BASE+OHCI_CMDST_OFFSET) -#define LPC17_USBHOST_INTST (LPC17_USB_BASE+OHCI_INTST_OFFSET) -#define LPC17_USBHOST_INTEN (LPC17_USB_BASE+OHCI_INTEN_OFFSET) -#define LPC17_USBHOST_INTDIS (LPC17_USB_BASE+OHCI_INTDIS_OFFSET) - -/* Memory pointers (section 7.2) */ - -#define LPC17_USBHOST_HCCA (LPC17_USB_BASE+OHCI_HCCA_OFFSET) -#define LPC17_USBHOST_PERED (LPC17_USB_BASE+OHCI_PERED_OFFSET) -#define LPC17_USBHOST_CTRLHEADED (LPC17_USB_BASE+OHCI_CTRLHEADED_OFFSET) -#define LPC17_USBHOST_CTRLED (LPC17_USB_BASE+OHCI_CTRLED_OFFSET) -#define LPC17_USBHOST_BULKHEADED (LPC17_USB_BASE+OHCI_BULKHEADED_OFFSET) -#define LPC17_USBHOST_BULKED (LPC17_USB_BASE+OHCI_BULKED_OFFSET) -#define LPC17_USBHOST_DONEHEAD (LPC17_USB_BASE+OHCI_DONEHEAD_OFFSET) - -/* Frame counters (section 7.3) */ - -#define LPC17_USBHOST_FMINT (LPC17_USB_BASE+OHCI_FMINT_OFFSET) -#define LPC17_USBHOST_FMREM (LPC17_USB_BASE+OHCI_FMREM_OFFSET) -#define LPC17_USBHOST_FMNO (LPC17_USB_BASE+OHCI_FMNO_OFFSET) -#define LPC17_USBHOST_PERSTART (LPC17_USB_BASE+OHCI_PERSTART_OFFSET) - -/* Root hub ports (section 7.4) */ - -#define LPC17_USBHOST_LSTHRES (LPC17_USB_BASE+OHCI_LSTHRES_OFFSET) -#define LPC17_USBHOST_RHDESCA (LPC17_USB_BASE+OHCI_RHDESCA_OFFSET) -#define LPC17_USBHOST_RHDESCB (LPC17_USB_BASE+OHCI_RHDESCB_OFFSET) -#define LPC17_USBHOST_RHSTATUS (LPC17_USB_BASE+OHCI_RHSTATUS_OFFSET) -#define LPC17_USBHOST_RHPORTST1 (LPC17_USB_BASE+OHCI_RHPORTST1_OFFSET) -#define LPC17_USBHOST_RHPORTST2 (LPC17_USB_BASE+OHCI_RHPORTST2_OFFSET) -#define LPC17_USBHOST_MODID (LPC17_USB_BASE+LPC17_USBHOST_MODID_OFFSET) - -/* USB OTG Controller ***************************************************************/ -/* OTG registers */ - -#define LPC17_USBOTG_INTST (LPC17_USB_BASE+LPC17_USBOTG_INTST_OFFSET) -#define LPC17_USBOTG_INTEN (LPC17_USB_BASE+LPC17_USBOTG_INTEN_OFFSET) -#define LPC17_USBOTG_INTSET (LPC17_USB_BASE+LPC17_USBOTG_INTSET_OFFSET) -#define LPC17_USBOTG_INTCLR (LPC17_USB_BASE+LPC17_USBOTG_INTCLR_OFFSET) -#define LPC17_USBOTG_STCTRL (LPC17_USB_BASE+LPC17_USBOTG_STCTRL_OFFSET) -#define LPC17_USBOTG_TMR (LPC17_USB_BASE+LPC17_USBOTG_TMR_OFFSET) - -/* USB Device Controller ************************************************************/ -/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ - -#define LPC17_USBDEV_INTST (LPC17_USB_BASE+LPC17_USBDEV_INTST_OFFSET) -#define LPC17_USBDEV_INTEN (LPC17_USB_BASE+LPC17_USBDEV_INTEN_OFFSET) -#define LPC17_USBDEV_INTCLR (LPC17_USB_BASE+LPC17_USBDEV_INTCLR_OFFSET) -#define LPC17_USBDEV_INTSET (LPC17_USB_BASE+LPC17_USBDEV_INTSET_OFFSET) - -/* SIE Command registers */ - -#define LPC17_USBDEV_CMDCODE (LPC17_USB_BASE+LPC17_USBDEV_CMDCODE_OFFSET) -#define LPC17_USBDEV_CMDDATA (LPC17_USB_BASE+LPC17_USBDEV_CMDDATA_OFFSET) - -/* USB transfer registers */ - -#define LPC17_USBDEV_RXDATA (LPC17_USB_BASE+LPC17_USBDEV_RXDATA_OFFSET) -#define LPC17_USBDEV_RXPLEN (LPC17_USB_BASE+LPC17_USBDEV_RXPLEN_OFFSET) -#define LPC17_USBDEV_TXDATA (LPC17_USB_BASE+LPC17_USBDEV_TXDATA_OFFSET) -#define LPC17_USBDEV_TXPLEN (LPC17_USB_BASE+LPC17_USBDEV_TXPLEN_OFFSET) -#define LPC17_USBDEV_CTRL (LPC17_USB_BASE+LPC17_USBDEV_CTRL_OFFSET) - -/* More Device interrupt registers */ - -#define LPC17_USBDEV_INTPRI (LPC17_USB_BASE+LPC17_USBDEV_INTPRI_OFFSET) - -/* Endpoint interrupt registers */ - -#define LPC17_USBDEV_EPINTST (LPC17_USB_BASE+LPC17_USBDEV_EPINTST_OFFSET) -#define LPC17_USBDEV_EPINTEN (LPC17_USB_BASE+LPC17_USBDEV_EPINTEN_OFFSET) -#define LPC17_USBDEV_EPINTCLR (LPC17_USB_BASE+LPC17_USBDEV_EPINTCLR_OFFSET) -#define LPC17_USBDEV_EPINTSET (LPC17_USB_BASE+LPC17_USBDEV_EPINTSET_OFFSET) -#define LPC17_USBDEV_EPINTPRI (LPC17_USB_BASE+LPC17_USBDEV_EPINTPRI_OFFSET) - -/* Endpoint realization registers */ - -#define LPC17_USBDEV_REEP (LPC17_USB_BASE+LPC17_USBDEV_REEP_OFFSET) -#define LPC17_USBDEV_EPIND (LPC17_USB_BASE+LPC17_USBDEV_EPIND_OFFSET) -#define LPC17_USBDEV_MAXPSIZE (LPC17_USB_BASE+LPC17_USBDEV_MAXPSIZE_OFFSET) - -/* DMA registers */ - -#define LPC17_USBDEV_DMARST (LPC17_USB_BASE+LPC17_USBDEV_DMARST_OFFSET) -#define LPC17_USBDEV_DMARCLR (LPC17_USB_BASE+LPC17_USBDEV_DMARCLR_OFFSET) -#define LPC17_USBDEV_DMARSET (LPC17_USB_BASE+LPC17_USBDEV_DMARSET_OFFSET) -#define LPC17_USBDEV_UDCAH (LPC17_USB_BASE+LPC17_USBDEV_UDCAH_OFFSET) -#define LPC17_USBDEV_EPDMAST (LPC17_USB_BASE+LPC17_USBDEV_EPDMAST_OFFSET) -#define LPC17_USBDEV_EPDMAEN (LPC17_USB_BASE+LPC17_USBDEV_EPDMAEN_OFFSET) -#define LPC17_USBDEV_EPDMADIS (LPC17_USB_BASE+LPC17_USBDEV_EPDMADIS_OFFSET) -#define LPC17_USBDEV_DMAINTST (LPC17_USB_BASE+LPC17_USBDEV_DMAINTST_OFFSET) -#define LPC17_USBDEV_DMAINTEN (LPC17_USB_BASE+LPC17_USBDEV_DMAINTEN_OFFSET) -#define LPC17_USBDEV_EOTINTST (LPC17_USB_BASE+LPC17_USBDEV_EOTINTST_OFFSET) -#define LPC17_USBDEV_EOTINTCLR (LPC17_USB_BASE+LPC17_USBDEV_EOTINTCLR_OFFSET) -#define LPC17_USBDEV_EOTINTSET (LPC17_USB_BASE+LPC17_USBDEV_EOTINTSET_OFFSET) -#define LPC17_USBDEV_NDDRINTST (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTST_OFFSET) -#define LPC17_USBDEV_NDDRINTCLR (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTCLR_OFFSET) -#define LPC17_USBDEV_NDDRINTSET (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTSET_OFFSET) -#define LPC17_USBDEV_SYSERRINTST (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTST_OFFSET) -#define LPC17_USBDEV_SYSERRINTCLR (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTCLR_OFFSET) -#define LPC17_USBDEV_SYSERRINTSET (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTSET_OFFSET) - -/* OTG I2C registers ****************************************************************/ - -#define LPC17_OTGI2C_RX (LPC17_USB_BASE+LPC17_OTGI2C_RX_OFFSET) -#define LPC17_OTGI2C_TX (LPC17_USB_BASE+LPC17_OTGI2C_TX_OFFSET) -#define LPC17_OTGI2C_STS (LPC17_USB_BASE+LPC17_OTGI2C_STS_OFFSET) -#define LPC17_OTGI2C_CTL (LPC17_USB_BASE+LPC17_OTGI2C_CTL_OFFSET) -#define LPC17_OTGI2C_CLKHI (LPC17_USB_BASE+LPC17_OTGI2C_CLKHI_OFFSET) -#define LPC17_OTGI2C_CLKLO (LPC17_USB_BASE+LPC17_OTGI2C_CLKLO_OFFSET) - -/* Clock control registers ***********************************************************/ - -#define LPC17_USBOTG_CLKCTRL (LPC17_USB_BASE+LPC17_USBOTG_CLKCTRL_OFFSET) -#define LPC17_USBOTG_CLKST (LPC17_USB_BASE+LPC17_USBOTG_CLKST_OFFSET) - -#define LPC17_USBDEV_CLKCTRL (LPC17_USB_BASE+LPC17_USBDEV_CLKCTRL_OFFSET) -#define LPC17_USBDEV_CLKST (LPC17_USB_BASE+LPC17_USBDEV_CLKST_OFFSET) - -/* Register bit definitions *********************************************************/ -/* USB Host Controller (OHCI) *******************************************************/ -/* See include/nuttx/usb/ohci.h */ - -/* Module ID/Revision ID */ - -#define USBHOST_MODID_VER_SHIFT (0) /* Bits 0-7: Unique version number */ -#define USBHOST_MODID_VER_MASK (0xff << USBHOST_MODID_VER_SHIFT) -#define USBHOST_MODID_REV_SHIFT (8) /* Bits 9-15: Unique revision number */ -#define USBHOST_MODID_REV_MASK (0xff << USBHOST_MODID_REV_SHIFT) -#define USBHOST_MODID_3505_SHIFT (16) /* Bits 16-31: 0x3505 */ -#define USBHOST_MODID_3505_MASK (0xffff << USBHOST_MODID_3505_SHIFT) -# define USBHOST_MODID_3505 (0x3505 << USBHOST_MODID_3505_SHIFT) - -/* USB OTG Controller ***************************************************************/ -/* OTG registers: - * - * OTG Interrupt Status, OTG Interrupt Enable, OTG Interrupt Set, AND OTG Interrupt - * Clear - */ - -#define USBOTG_INT_TMR (1 << 0) /* Bit 0: Timer time-out */ -#define USBOTG_INT_REMOVE_PU (1 << 1) /* Bit 1: Remove pull-up */ -#define USBOTG_INT_HNP_FAILURE (1 << 2) /* Bit 2: HNP failed */ -#define USBOTG_INT_HNP_SUCCESS (1 << 3) /* Bit 3: HNP succeeded */ - /* Bits 4-31: Reserved */ -/* OTG Status and Control */ - -#define USBOTG_STCTRL_PORTFUNC_SHIFT (0) /* Bits 0-1: Controls port function */ -#define USBOTG_STCTRL_PORTFUNC_MASK (3 << USBOTG_STCTRL_PORTFUNC_SHIFT) -# define USBOTG_STCTRL_PORTFUNC_HNPOK (1 << USBOTG_STCTRL_PORTFUNC_SHIFT) /* HNP suceeded */ -#define USBOTG_STCTRL_TMRSCALE_SHIFT (2) /* Bits 2-3: Timer scale selection */ -#define USBOTG_STCTRL_TMRSCALE_MASK (3 << USBOTG_STCTRL_TMR_SCALE_SHIFT) -# define USBOTG_STCTRL_TMRSCALE_10US (0 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 10uS (100 KHz) */ -# define USBOTG_STCTRL_TMRSCALE_100US (1 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 100uS (10 KHz) */ -# define USBOTG_STCTRL_TMRSCALE_1000US (2 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 1000uS (1 KHz) */ -#define USBOTG_STCTRL_TMRMODE (1 << 4) /* Bit 4: Timer mode selection */ -#define USBOTG_STCTRL_TMREN (1 << 5) /* Bit 5: Timer enable */ -#define USBOTG_STCTRL_TMRRST (1 << 6) /* Bit 6: TTimer reset */ - /* Bit 7: Reserved */ -#define USBOTG_STCTRL_BHNPTRACK (1 << 8) /* Bit 8: Enable HNP tracking for B-device (peripheral) */ -#define USBOTG_STCTRL_AHNPTRACK (1 << 9) /* Bit 9: Enable HNP tracking for A-device (host) */ -#define USBOTG_STCTRL_PUREMOVED (1 << 10) /* Bit 10: Set when D+ pull-up removed */ - /* Bits 11-15: Reserved */ -#define USBOTG_STCTRL_TMRCNT_SHIFT (0) /* Bits 16-313: Timer scale selection */ -#define USBOTG_STCTRL_TMRCNT_MASK (0ffff << USBOTG_STCTRL_TMR_CNT_SHIFT) - -/* OTG Timer */ - -#define USBOTG_TMR_TIMEOUTCNT_SHIFT (0) /* Bits 0-15: Interrupt when CNT matches this */ -#define USBOTG_TMR_TIMEOUTCNT_MASK (0xffff << USBOTG_TMR_TIMEOUTCNT_SHIFT) - /* Bits 16-31: Reserved */ - -/* USB Device Controller ************************************************************/ -/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ -/* USB Device Interrupt Status, USB Device Interrupt Enable, USB Device Interrupt - * Clear, USB Device Interrupt Set, and USB Device Interrupt Priority - */ - -#define USBDEV_INT_FRAME (1 << 0) /* Bit 0: frame interrupt (every 1 ms) */ -#define USBDEV_INT_EPFAST (1 << 1) /* Bit 1: Fast endpoint interrupt */ -#define USBDEV_INT_EPSLOW (1 << 2) /* Bit 2: Slow endpoints interrupt */ -#define USBDEV_INT_DEVSTAT (1 << 3) /* Bit 3: Bus reset, suspend change or connect change */ -#define USBDEV_INT_CCEMPTY (1 << 4) /* Bit 4: Command code register empty */ -#define USBDEV_INT_CDFULL (1 << 5) /* Bit 5: Command data register full */ -#define USBDEV_INT_RXENDPKT (1 << 6) /* Bit 6: RX endpoint data transferred */ -#define USBDEV_INT_TXENDPKT (1 << 7) /* Bit 7: TX endpoint data tansferred */ -#define USBDEV_INT_EPRLZED (1 << 8) /* Bit 8: Endpoints realized */ -#define USBDEV_INT_ERRINT (1 << 9) /* Bit 9: Error Interrupt */ - /* Bits 10-31: Reserved */ -/* SIE Command registers: - * - * USB Command Code - */ - /* Bits 0-7: Reserved */ -#define USBDEV_CMDCODE_PHASE_SHIFT (8) /* Bits 8-15: Command phase */ -#define USBDEV_CMDCODE_PHASE_MASK (0xff << USBDEV_CMDCODE_PHASE_SHIFT) -# define USBDEV_CMDCODE_PHASE_READ (1 << USBDEV_CMDCODE_PHASE_SHIFT) -# define USBDEV_CMDCODE_PHASE_WRITE (2 << USBDEV_CMDCODE_PHASE_SHIFT) -# define USBDEV_CMDCODE_PHASE_COMMAND (5 << USBDEV_CMDCODE_PHASE_SHIFT) -#define USBDEV_CMDCODE_CMD_SHIFT (16) /* Bits 15-23: Command (READ/COMMAND phases) */ -#define USBDEV_CMDCODE_CMD_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT) -#define USBDEV_CMDCODE_WDATA_SHIFT (16) /* Bits 15-23: Write dagta (WRITE phase) */ -#define USBDEV_CMDCODE_WDATA_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT) - /* Bits 24-31: Reserved */ -/* USB Command Data */ - -#define USBDEV_CMDDATA_SHIFT (0) /* Bits 0-7: Command read data */ -#define USBDEV_CMDDATA_MASK (0xff << USBDEV_CMDDATA_SHIFT) - /* Bits 8-31: Reserved */ -/* USB transfer registers: - * - * USB Receive Data (Bits 0-31: Received data) - */ - -/* USB Receive Packet Length */ - -#define USBDEV_RXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be read */ -#define USBDEV_RXPLEN_MASK (0x3ff << USBDEV_RXPLEN_SHIFT) -#define USBDEV_RXPLEN_DV (1 << 10) /* Bit 10: DV Data valid */ -#define USBDEV_RXPLEN_PKTRDY (1 << 11) /* Bit 11: Packet ready for reading */ - /* Bits 12-31: Reserved */ -/* USB Transmit Data (Bits 0-31: Transmit data) */ - -/* USB Transmit Packet Length */ - -#define USBDEV_TXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be written */ -#define USBDEV_TXPLEN_MASK (0x3ff << USBDEV_TXPLEN_SHIFT) - /* Bits 10-31: Reserved */ -/* USB Control */ - -#define USBDEV_CTRL_RDEN (1 << 0) /* Bit 0: Read mode control */ -#define USBDEV_CTRL_WREN (1 << 1) /* Bit 1: Write mode control */ -#define USBDEV_CTRL_LOGEP_SHIFT (2) /* Bits 2-5: Logical Endpoint number */ -#define USBDEV_CTRL_LOGEP_MASK (15 << USBDEV_CTRL_LOGEP_SHIFT) - /* Bits 6-31: Reserved */ -/* Endpoint interrupt registers: - * - * USB Endpoint Interrupt Status, USB Endpoint Interrupt Enable, USB Endpoint Interrupt - * Clear, USB Endpoint Interrupt Set, and USB Endpoint Priority. Bits correspond - * to on RX or TX value for any of 15 logical endpoints). - */ - -#define USBDEV_LOGEPRX(n) (1 << ((n) << 1)) -#define USBDEV_LOGEPTX(n) ((1 << ((n) << 1)) + 1) -#define USBDEV_LOGEPRX0 (1 << 0) -#define USBDEV_LOGEPTX0 (1 << 1) -#define USBDEV_LOGEPRX1 (1 << 2) -#define USBDEV_LOGEPTX1 (1 << 3) -#define USBDEV_LOGEPRX2 (1 << 4) -#define USBDEV_LOGEPTX2 (1 << 5) -#define USBDEV_LOGEPRX3 (1 << 6) -#define USBDEV_LOGEPTX3 (1 << 7) -#define USBDEV_LOGEPRX4 (1 << 8) -#define USBDEV_LOGEPTX4 (1 << 9) -#define USBDEV_LOGEPRX5 (1 << 10) -#define USBDEV_LOGEPTX5 (1 << 11) -#define USBDEV_LOGEPRX6 (1 << 12) -#define USBDEV_LOGEPTX6 (1 << 13) -#define USBDEV_LOGEPRX7 (1 << 14) -#define USBDEV_LOGEPTX7 (1 << 15) -#define USBDEV_LOGEPRX8 (1 << 16) -#define USBDEV_LOGEPTX8 (1 << 17) -#define USBDEV_LOGEPRX9 (1 << 18) -#define USBDEV_LOGEPTX9 (1 << 19) -#define USBDEV_LOGEPRX10 (1 << 20) -#define USBDEV_LOGEPTX10 (1 << 21) -#define USBDEV_LOGEPRX11 (1 << 22) -#define USBDEV_LOGEPTX11 (1 << 23) -#define USBDEV_LOGEPRX12 (1 << 24) -#define USBDEV_LOGEPTX12 (1 << 25) -#define USBDEV_LOGEPRX13 (1 << 26) -#define USBDEV_LOGEPTX13 (1 << 27) -#define USBDEV_LOGEPRX14 (1 << 28) -#define USBDEV_LOGEPTX14 (1 << 29) -#define USBDEV_LOGEPRX15 (1 << 30) -#define USBDEV_LOGEPTX15 (1 << 31) - -/* Endpoint realization registers: - * - * USB Realize Endpoint (Bits correspond to 1 of 32 physical endpoints) - */ - -#define USBDEV_PHYEP(n) (1 << (n)) -#define USBDEV_PHYEP0 (1 << 0) -#define USBDEV_PHYEP1 (1 << 1) -#define USBDEV_PHYEP2 (1 << 2) -#define USBDEV_PHYEP3 (1 << 3) -#define USBDEV_PHYEP4 (1 << 4) -#define USBDEV_PHYEP5 (1 << 5) -#define USBDEV_PHYEP6 (1 << 6) -#define USBDEV_PHYEP7 (1 << 7) -#define USBDEV_PHYEP8 (1 << 8) -#define USBDEV_PHYEP9 (1 << 9) -#define USBDEV_PHYEP10 (1 << 10) -#define USBDEV_PHYEP11 (1 << 11) -#define USBDEV_PHYEP12 (1 << 12) -#define USBDEV_PHYEP13 (1 << 13) -#define USBDEV_PHYEP14 (1 << 14) -#define USBDEV_PHYEP15 (1 << 15) -#define USBDEV_PHYEP16 (1 << 16) -#define USBDEV_PHYEP17 (1 << 17) -#define USBDEV_PHYEP18 (1 << 18) -#define USBDEV_PHYEP19 (1 << 19) -#define USBDEV_PHYEP20 (1 << 20) -#define USBDEV_PHYEP21 (1 << 21) -#define USBDEV_PHYEP22 (1 << 22) -#define USBDEV_PHYEP23 (1 << 23) -#define USBDEV_PHYEP24 (1 << 24) -#define USBDEV_PHYEP25 (1 << 25) -#define USBDEV_PHYEP26 (1 << 26) -#define USBDEV_PHYEP27 (1 << 27) -#define USBDEV_PHYEP28 (1 << 28) -#define USBDEV_PHYEP29 (1 << 29) -#define USBDEV_PHYEP30 (1 << 30) -#define USBDEV_PHYEP31 (1 << 31) - -/* USB Endpoint Index */ - -#define USBDEV_EPIND_SHIFT (0) /* Bits 0-4: Physical endpoint number (0-31) */ -#define USBDEV_EPIND_MASK (31 << USBDEV_EPIND_SHIFT) - /* Bits 5-31: Reserved */ -/* USB MaxPacketSize */ - -#define USBDEV_MAXPSIZE_SHIFT (0) /* Bits 0-9: Maximum packet size value */ -#define USBDEV_MAXPSIZE_MASK (0x3ff << USBDEV_MAXPSIZE_SHIFT) - /* Bits 10-31: Reserved */ -/* DMA registers: - * - * USB DMA Request Status, USB DMA Request Clear, and USB DMA Request Set. Registers - * contain bits for each of 32 physical endpoints. Use the USBDEV_PHYEP* definitions - * above. PHYEP0-1 (bits 0-1) must be zero. - */ - -/* USB UDCA Head */ - /* Bits 0-6: Reserved */ -#define USBDEV_UDCAH_SHIFT (7) /* Bits 7-31: UDCA start address */ -#define USBDEV_UDCAH_MASK (0x01ffffff << USBDEV_UDCAH_SHIFT) - -/* USB Endpoint DMA Status, USB Endpoint DMA Enable, and USB Endpoint DMA Disable. - * Registers contain bits for physical endpoints 2-31. Use the USBDEV_PHYEP* - * definitions above. PHYEP0-1 (bits 0-1) must be zero. - */ - -/* USB DMA Interrupt Status and USB DMA Interrupt Enable */ - -#define USBDEV_DMAINT_EOT (1 << 0) /* Bit 0: End of Transfer Interrupt */ -#define USBDEV_DMAINT_NDDR (1 << 1) /* Bit 1: New DD Request Interrupt */ -#define USBDEV_DMAINT_ERR (1 << 2) /* Bit 2: System Error Interrupt */ - /* Bits 3-31: Reserved */ -/* USB End of Transfer Interrupt Status, USB End of Transfer Interrupt Clear, and USB - * End of Transfer Interrupt Set. Registers contain bits for physical endpoints 2-31. - * Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. - */ - -/* USB New DD Request Interrupt Status, USB New DD Request Interrupt Clear, and USB - * New DD Request Interrupt Set. Registers contain bits for physical endpoints 2-31. - * Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. - */ - -/* USB System Error Interrupt Status, USB System Error Interrupt Clear, USB System - * Error Interrupt Set. Registers contain bits for physical endpoints 2-31. Use - * the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. - */ - -/* OTG I2C registers ****************************************************************/ - -/* I2C Receive */ - -#define OTGI2C_RX_DATA_SHIFT (0) /* Bits 0-7: RX data */ -#define OTGI2C_RX_DATA_MASK (0xff << OTGI2C_RX_SHIFT) - /* Bits 8-31: Reserved */ -/* I2C Transmit */ - -#define OTGI2C_TX_DATA_SHIFT (0) /* Bits 0-7: TX data */ -#define OTGI2C_TX_DATA_MASK (0xff << OTGI2C_TX_DATA_SHIFT) -#define OTGI2C_TX_DATA_START (1 << 8) /* Bit 8: Issue START before transmit */ -#define OTGI2C_TX_DATA_STOP (1 << 9) /* Bit 9: Issue STOP before transmit */ - /* Bits 3-31: Reserved */ -/* I2C Status */ - -#define OTGI2C_STS_TDI (1 << 0) /* Bit 0: Transaction Done Interrupt */ -#define OTGI2C_STS_AFI (1 << 1) /* Bit 1: Arbitration Failure Interrupt */ -#define OTGI2C_STS_NAI (1 << 2) /* Bit 2: No Acknowledge Interrupt */ -#define OTGI2C_STS_DRMI (1 << 3) /* Bit 3: Master Data Request Interrupt */ -#define OTGI2C_STS_DRSI (1 << 4) /* Bit 4: Slave Data Request Interrupt */ -#define OTGI2C_STS_ACTIVE (1 << 5) /* Bit 5: Indicates whether the bus is busy */ -#define OTGI2C_STS_SCL (1 << 6) /* Bit 6: The current value of the SCL signal */ -#define OTGI2C_STS_SDA (1 << 7) /* Bit 7: The current value of the SDA signal */ -#define OTGI2C_STS_RFF (1 << 8) /* Bit 8: Receive FIFO Full (RFF) */ -#define OTGI2C_STS_RFE (1 << 9) /* Bit 9: Receive FIFO Empty */ -#define OTGI2C_STS_TFF (1 << 10) /* Bit 10: Transmit FIFO Full */ -#define OTGI2C_STS_TFE (1 << 11) /* Bit 11: Transmit FIFO Empty */ - /* Bits 12-31: Reserved */ -/* I2C Control */ - -#define OTGI2C_CTL_TDIE (1 << 0) /* Bit 0: Transmit Done Interrupt Enable */ -#define OTGI2C_CTL_AFIE (1 << 1) /* Bit 1: Transmitter Arbitration Failure Interrupt Enable */ -#define OTGI2C_CTL_NAIE (1 << 2) /* Bit 2: Transmitter No Acknowledge Interrupt Enable */ -#define OTGI2C_CTL_DRMIE (1 << 3) /* Bit 3: Master Transmitter Data Request Interrupt Enable */ -#define OTGI2C_CTL_DRSIE (1 << 4) /* Bit 4: Slave Transmitter Data Request Interrupt Enable */ -#define OTGI2C_CTL_REFIE (1 << 5) /* Bit 5: Receive FIFO Full Interrupt Enable */ -#define OTGI2C_CTL_RFDAIE (1 << 6) /* Bit 6: Receive Data Available Interrupt Enable */ -#define OTGI2C_CTL_TFFIE (1 << 7) /* Bit 7: Transmit FIFO Not Full Interrupt Enable */ -#define OTGI2C_CTL_SRST (1 << 8) /* Bit 8: Soft reset */ - /* Bits 9-31: Reserved */ -/* I2C Clock High */ - -#define OTGI2C_CLKHI_SHIFT (0) /* Bits 0-7: Clock divisor high */ -#define OTGI2C_CLKHI_MASK (0xff << OTGI2C_CLKHI_SHIFT) - /* Bits 8-31: Reserved */ -/* I2C Clock Low */ - -#define OTGI2C_CLKLO_SHIFT (0) /* Bits 0-7: Clock divisor high */ -#define OTGI2C_CLLO_MASK (0xff << OTGI2C_CLKLO_SHIFT) - /* Bits 8-31: Reserved */ -/* Clock control registers ***********************************************************/ - -/* USB Clock Control (OTG clock controller) and USB Clock Status (OTG clock status) */ - -#define USBDEV_CLK_HOSTCLK (1 << 0) /* Bit 1: Host clock (OTG only) */ -#define USBDEV_CLK_DEVCLK (1 << 1) /* Bit 1: Device clock */ -#define USBDEV_CLK_I2CCLK (1 << 2) /* Bit 2: I2C clock (OTG only) */ -#define USBDEV_CLK_PORTSELCLK (1 << 3) /* Bit 3: Port select register clock (device only) */ -#define USBDEV_CLK_OTGCLK (1 << 3) /* Bit 3: OTG clock (OTG only) */ -#define USBDEV_CLK_AHBCLK (1 << 4) /* Bit 4: AHB clock */ - /* Bits 5-31: Reserved */ -/* Alternate naming */ - -#define USBOTG_CLK_HOSTCLK USBDEV_CLK_HOSTCLK -#define USBOTG_CLK_DEVCLK USBDEV_CLK_DEVCLK -#define USBOTG_CLK_I2CCLK USBDEV_CLK_I2CCLK -#define USBOTG_CLK_PORTSELCLK USBDEV_CLK_PORTSELCLK -#define USBOTG_CLK_OTGCLK USBDEV_CLK_OTGCLK -#define USBOTG_CLK_AHBCLK USBDEV_CLK_AHBCLK - -/* Endpoints *************************************************************************/ - -#define LPC17_EP0_OUT 0 -#define LPC17_EP0_IN 1 -#define LPC17_CTRLEP_OUT LPC17_EP0_OUT -#define LPC17_CTRLEP_IN LPC17_EP0_IN -#define LPC17_EP1_OUT 2 -#define LPC17_EP1_IN 3 -#define LPC17_EP2_OUT 4 -#define LPC17_EP2_IN 5 -#define LPC17_EP3_OUT 6 -#define LPC17_EP3_IN 7 -#define LPC17_EP4_OUT 8 -#define LPC17_EP4_IN 9 -#define LPC17_EP5_OUT 10 -#define LPC17_EP5_IN 11 -#define LPC17_EP6_OUT 12 -#define LPC17_EP6_IN 13 -#define LPC17_EP7_OUT 14 -#define LPC17_EP7_IN 15 -#define LPC17_EP8_OUT 16 -#define LPC17_EP8_IN 17 -#define LPC17_EP9_OUT 18 -#define LPC17_EP9_IN 19 -#define LPC17_EP10_OUT 20 -#define LPC17_EP10_IN 21 -#define LPC17_EP11_OUT 22 -#define LPC17_EP11_IN 23 -#define LPC17_EP12_OUT 24 -#define LPC17_EP12_IN 25 -#define LPC17_EP13_OUT 26 -#define LPC17_EP13_IN 27 -#define LPC17_EP14_OUT 28 -#define LPC17_EP14_IN 29 -#define LPC17_EP15_OUT 30 -#define LPC17_EP15_IN 31 -#define LPC17_NUMEPS 32 - -/* Commands *************************************************************************/ - -/* USB Command Code Register */ - -#define CMD_USBDEV_PHASESHIFT (8) /* Bits 8-15: Command phase value */ -#define CMD_USBDEV_PHASEMASK (0xff << CMD_USBDEV_PHASESHIFT) -# define CMD_USBDEV_DATAWR (1 << CMD_USBDEV_PHASESHIFT) -# define CMD_USBDEV_DATARD (2 << CMD_USBDEV_PHASESHIFT) -# define CMD_USBDEV_CMDWR (5 << CMD_USBDEV_PHASESHIFT) -#define CMD_USBDEV_CMDSHIFT (16) /* Bits 16-23: Device command/WDATA */ -#define CMD_USBDEV_CMDMASK (0xff << CMD_USBDEV_CMDSHIFT) -#define CMD_USBDEV_WDATASHIFT CMD_USBDEV_CMDSHIFT -#define CMD_USBDEV_WDATAMASK CMD_USBDEV_CMDMASK - -/* Device Commands */ - -#define CMD_USBDEV_SETADDRESS (0x00d0) -#define CMD_USBDEV_CONFIG (0x00d8) -#define CMD_USBDEV_SETMODE (0x00f3) -#define CMD_USBDEV_READFRAMENO (0x00f5) -#define CMD_USBDEV_READTESTREG (0x00fd) -#define CMD_USBDEV_SETSTATUS (0x01fe) /* Bit 8 set to distingish get from set */ -#define CMD_USBDEV_GETSTATUS (0x00fe) -#define CMD_USBDEV_GETERRORCODE (0x00ff) -#define CMD_USBDEV_READERRORSTATUS (0x00fb) - -/* Endpoint Commands */ - -#define CMD_USBDEV_EPSELECT (0x0000) -#define CMD_USBDEV_EPSELECTCLEAR (0x0040) -#define CMD_USBDEV_EPSETSTATUS (0x0140) /* Bit 8 set to distingish get from selectclear */ -#define CMD_USBDEV_EPCLRBUFFER (0x00f2) -#define CMD_USBDEV_EPVALIDATEBUFFER (0x00fa) - -/* Command/response bit definitions ********************************************/ -/* SETADDRESS (0xd0) command definitions */ - -#define CMD_USBDEV_SETADDRESS_MASK (0x7f) /* Bits 0-6: Device address */ -#define CMD_USBDEV_SETADDRESS_DEVEN (1 << 7) /* Bit 7: Device enable */ - -/* SETSTATUS (0xfe) and GETSTATUS (0xfe) response: */ - -#define CMD_STATUS_CONNECT (1 << 0) /* Bit 0: Connected */ -#define CMD_STATUS_CONNCHG (1 << 1) /* Bit 1: Connect change */ -#define CMD_STATUS_SUSPEND (1 << 2) /* Bit 2: Suspend */ -#define CMD_STATUS_SUSPCHG (1 << 3) /* Bit 3: Suspend change */ -#define CMD_STATUS_RESET (1 << 4) /* Bit 4: Bus reset bit */ - -/* EPSELECT (0x00) endpoint status response */ - -#define CMD_EPSELECT_FE (1 << 0) /* Bit 0: IN empty or OUT full */ -#define CMD_EPSELECT_ST (1 << 1) /* Bit 1: Endpoint is stalled */ -#define CMD_EPSELECT_STP (1 << 2) /* Bit 2: Last packet was setup */ -#define CMD_EPSELECT_PO (1 << 3) /* Bit 3: Previous packet was overwritten */ -#define CMD_EPSELECT_EPN (1 << 4) /* Bit 4: NAK sent */ -#define CMD_EPSELECT_B1FULL (1 << 5) /* Bit 5: Buffer 1 full */ -#define CMD_EPSELECT_B2FULL (1 << 6) /* Bit 6: Buffer 2 full */ - /* Bit 7: Reserved */ -/* EPSETSTATUS (0x40) command */ - -#define CMD_SETSTAUS_ST (1 << 0) /* Bit 0: Stalled endpoint bit */ - /* Bits 1-4: Reserved */ -#define CMD_SETSTAUS_DA (1 << 5) /* Bit 5: Disabled endpoint bit */ -#define CMD_SETSTAUS_RFMO (1 << 6) /* Bit 6: Rate feedback mode */ -#define CMD_SETSTAUS_CNDST (1 << 7) /* Bit 7: Conditional stall bit */ - -/* EPCLRBUFFER (0xf2) response */ - -#define CMD_USBDEV_CLRBUFFER_PO (0x00000001) - -/* SETMODE(0xf3) command */ - -#define CMD_SETMODE_APCLK (1 << 0) /* Bit 0: Always PLL Clock */ -#define CMD_SETMODE_INAKCI (1 << 1) /* Bit 1: Interrupt on NAK for Control IN endpoint */ -#define CMD_SETMODE_INAKCO (1 << 2) /* Bit 2: Interrupt on NAK for Control OUT endpoint */ -#define CMD_SETMODE_INAKII (1 << 3) /* Bit 3: Interrupt on NAK for Interrupt IN endpoint */ -#define CMD_SETMODE_INAKIO (1 << 4) /* Bit 4: Interrupt on NAK for Interrupt OUT endpoints */ -#define CMD_SETMODE_INAKBI (1 << 5) /* Bit 5: Interrupt on NAK for Bulk IN endpoints */ -#define CMD_SETMODE_INAKBO (1 << 6) /* Bit 6: Interrupt on NAK for Bulk OUT endpoints */ - -/* READERRORSTATUS (0xFb) command */ - -#define CMD_READERRORSTATUS_PIDERR (1 << 0) /* Bit 0: PID encoding/unknown or Token CRC */ -#define CMD_READERRORSTATUS_UEPKT (1 << 1) /* Bit 1: Unexpected Packet */ -#define CMD_READERRORSTATUS_DCRC (1 << 2) /* Bit 2: Data CRC error */ -#define CMD_READERRORSTATUS_TIMEOUT (1 << 3) /* Bit 3: Time out error */ -#define CMD_READERRORSTATUS_EOP (1 << 4) /* Bit 4: End of packet error */ -#define CMD_READERRORSTATUS_BOVRN (1 << 5) /* Bit 5: Buffer Overrun */ -#define CMD_READERRORSTATUS_BTSTF (1 << 6) /* Bit 6: Bit stuff error */ -#define CMD_READERRORSTATUS_TGLERR (1 << 7) /* Bit 7: Wrong toggle in data PID */ -#define CMD_READERRORSTATUS_ALLERRS (0xff) - -/* DMA ******************************************************************************/ -/* The DMA descriptor */ - -#define USB_DMADESC_NEXTDDPTR 0 /* Offset 0: Next USB descriptor in RAM */ -#define USB_DMADESC_CONFIG 1 /* Offset 1: DMA configuration info. */ -#define USB_DMADESC_STARTADDR 2 /* Offset 2: DMA start address */ -#define USB_DMADESC_STATUS 3 /* Offset 3: DMA status info (read only) */ -#define USB_DMADESC_ISOCSIZEADDR 4 /* Offset 4: Isoc. packet size address */ - -/* Bit settings for CONFIG (offset 1 )*/ - -#define USB_DMADESC_MODE_SHIFT (0) /* Bits 0-1: DMA mode */ -#define USB_DMADESC_MODE_MASK (3 << USB_DMADESC_MODE_SHIFT) -# define USB_DMADESC_MODENORMAL (0 << USB_DMADESC_MODE_SHIFT) /* Mode normal */ -# define USB_DMADESC_MODEATLE (1 << USB_DMADESC_MODE_SHIFT) /* ATLE normal */ -#define USB_DMADESC_NEXTDDVALID (1 << 2) /* Bit 2: Next descriptor valid */ - /* Bit 3: Reserved */ -#define USB_DMADESC_ISCOEP (1 << 4) /* Bit 4: ISOC endpoint */ -#define USB_DMADESC_PKTSIZE_SHIFT (5) /* Bits 5-15: Max packet size */ -#define USB_DMADESC_PKTSIZE_MASK (0x7ff << USB_DMADESC_PKTSIZE_SHIFT) -#define USB_DMADESC_BUFLEN_SHIFT (16) /* Bits 16-31: DMA buffer length */ -#define USB_DMADESC_BUFLEN_MASK (0xffff << USB_DMADESC_BUFLEN_SHIFT - -/* Bit settings for STATUS (offset 3). All must be initialized to zero. */ - -#define USB_DMADESC_STATUS_SHIFT (1) /* Bits 1-4: DMA status */ -#define USB_DMADESC_STATUS_MASK (15 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_NOTSERVICED (0 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_BEINGSERVICED (1 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_NORMALCOMPLETION (2 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_DATAUNDERRUN (3 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_DATAOVERRUN (8 << USB_DMADESC_STATUS_SHIFT) -# define USB_DMADESC_SYSTEMERROR (9 << USB_DMADESC_STATUS_SHIFT) -#define USB_DMADESC_PKTVALID (1 << 5) /* Bit 5: Packet valid */ -#define USB_DMADESC_LSBEXTRACTED (1 << 6) /* Bit 6: LS byte extracted */ -#define USB_DMADESC_MSBEXTRACTED (1 << 7) /* Bit 7: MS byte extracted */ -#define USB_DMADESC_MSGLENPOS_SHIFT (8) /* Bits 8-13: Message length position */ -#define USB_DMADESC_MSGLENPOS_MASK (0x3f << USB_DMADESC_MSGLENPOS_SHIFT) -#define USB_DMADESC_DMACOUNT_SHIFT (16) /* Bits 16-31: DMA count */ -#define USB_DMADESC_DMACOUNT_MASK (0xffff << USB_DMADESC_DMACOUNT_SHIFT) - -/* DMA packet size format */ - -#define USB_DMAPKTSIZE_PKTLEN_SHIFT (0) /* Bits 0-15: Packet length */ -#define USB_DMAPKTSIZE_PKTLEN_MASK (0xffff << USB_DMAPKTSIZE_PKTLEN_SHIFT) -#define USB_DMAPKTSIZE_PKTVALID (1 << 16) /* Bit 16: Packet valid */ -#define USB_DMAPKTSIZE_FRAMENO_SHIFT (17) /* Bit 17-31: Frame number */ -#define USB_DMAPKTSIZE_FRAMENO_MASK (0x7fff << USB_DMAPKTSIZE_FRAMENO_SHIFT) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_usb.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ +/* USB Host Controller (OHCI) *******************************************************/ +/* See include/nuttx/usb/ohci.h */ + +#define LPC17_USBHOST_MODID_OFFSET 0x00fc /* Module ID/Revision ID */ + +/* USB OTG Controller ***************************************************************/ +/* OTG registers */ + +#define LPC17_USBOTG_INTST_OFFSET 0x0100 /* OTG Interrupt Status */ +#define LPC17_USBOTG_INTEN_OFFSET 0x0104 /* OTG Interrupt Enable */ +#define LPC17_USBOTG_INTSET_OFFSET 0x0108 /* OTG Interrupt Set */ +#define LPC17_USBOTG_INTCLR_OFFSET 0x010c /* OTG Interrupt Clear */ +#define LPC17_USBOTG_STCTRL_OFFSET 0x0110 /* OTG Status and Control */ +#define LPC17_USBOTG_TMR_OFFSET 0x0114 /* OTG Timer */ + +/* USB Device Controller ************************************************************/ +/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ + +#define LPC17_USBDEV_INTST_OFFSET 0x0200 /* USB Device Interrupt Status */ +#define LPC17_USBDEV_INTEN_OFFSET 0x0204 /* USB Device Interrupt Enable */ +#define LPC17_USBDEV_INTCLR_OFFSET 0x0208 /* USB Device Interrupt Clear */ +#define LPC17_USBDEV_INTSET_OFFSET 0x020c /* USB Device Interrupt Set */ + +/* SIE Command registers */ + +#define LPC17_USBDEV_CMDCODE_OFFSET 0x0210 /* USB Command Code */ +#define LPC17_USBDEV_CMDDATA_OFFSET 0x0214 /* USB Command Data */ + +/* USB transfer registers */ + +#define LPC17_USBDEV_RXDATA_OFFSET 0x0218 /* USB Receive Data */ +#define LPC17_USBDEV_RXPLEN_OFFSET 0x0220 /* USB Receive Packet Length */ +#define LPC17_USBDEV_TXDATA_OFFSET 0x021c /* USB Transmit Data */ +#define LPC17_USBDEV_TXPLEN_OFFSET 0x0224 /* USB Transmit Packet Length */ +#define LPC17_USBDEV_CTRL_OFFSET 0x0228 /* USB Control */ + +/* More Device interrupt registers */ + +#define LPC17_USBDEV_INTPRI_OFFSET 0x022c /* USB Device Interrupt Priority */ + +/* Endpoint interrupt registers */ + +#define LPC17_USBDEV_EPINTST_OFFSET 0x0230 /* USB Endpoint Interrupt Status */ +#define LPC17_USBDEV_EPINTEN_OFFSET 0x0234 /* USB Endpoint Interrupt Enable */ +#define LPC17_USBDEV_EPINTCLR_OFFSET 0x0238 /* USB Endpoint Interrupt Clear */ +#define LPC17_USBDEV_EPINTSET_OFFSET 0x023c /* USB Endpoint Interrupt Set */ +#define LPC17_USBDEV_EPINTPRI_OFFSET 0x0240 /* USB Endpoint Priority */ + +/* Endpoint realization registers */ + +#define LPC17_USBDEV_REEP_OFFSET 0x0244 /* USB Realize Endpoint */ +#define LPC17_USBDEV_EPIND_OFFSET 0x0248 /* USB Endpoint Index */ +#define LPC17_USBDEV_MAXPSIZE_OFFSET 0x024c /* USB MaxPacketSize */ + +/* DMA registers */ + +#define LPC17_USBDEV_DMARST_OFFSET 0x0250 /* USB DMA Request Status */ +#define LPC17_USBDEV_DMARCLR_OFFSET 0x0254 /* USB DMA Request Clear */ +#define LPC17_USBDEV_DMARSET_OFFSET 0x0258 /* USB DMA Request Set */ +#define LPC17_USBDEV_UDCAH_OFFSET 0x0280 /* USB UDCA Head */ +#define LPC17_USBDEV_EPDMAST_OFFSET 0x0284 /* USB Endpoint DMA Status */ +#define LPC17_USBDEV_EPDMAEN_OFFSET 0x0288 /* USB Endpoint DMA Enable */ +#define LPC17_USBDEV_EPDMADIS_OFFSET 0x028c /* USB Endpoint DMA Disable */ +#define LPC17_USBDEV_DMAINTST_OFFSET 0x0290 /* USB DMA Interrupt Status */ +#define LPC17_USBDEV_DMAINTEN_OFFSET 0x0294 /* USB DMA Interrupt Enable */ +#define LPC17_USBDEV_EOTINTST_OFFSET 0x02a0 /* USB End of Transfer Interrupt Status */ +#define LPC17_USBDEV_EOTINTCLR_OFFSET 0x02a4 /* USB End of Transfer Interrupt Clear */ +#define LPC17_USBDEV_EOTINTSET_OFFSET 0x02a8 /* USB End of Transfer Interrupt Set */ +#define LPC17_USBDEV_NDDRINTST_OFFSET 0x02ac /* USB New DD Request Interrupt Status */ +#define LPC17_USBDEV_NDDRINTCLR_OFFSET 0x02b0 /* USB New DD Request Interrupt Clear */ +#define LPC17_USBDEV_NDDRINTSET_OFFSET 0x02b4 /* USB New DD Request Interrupt Set */ +#define LPC17_USBDEV_SYSERRINTST_OFFSET 0x02b8 /* USB System Error Interrupt Status */ +#define LPC17_USBDEV_SYSERRINTCLR_OFFSET 0x02bc /* USB System Error Interrupt Clear */ +#define LPC17_USBDEV_SYSERRINTSET_OFFSET 0x02c0 /* USB System Error Interrupt Set */ + +/* OTG I2C registers ****************************************************************/ + +#define LPC17_OTGI2C_RX_OFFSET 0x0300 /* I2C Receive */ +#define LPC17_OTGI2C_TX_OFFSET 0x0300 /* I2C Transmit */ +#define LPC17_OTGI2C_STS_OFFSET 0x0304 /* I2C Status */ +#define LPC17_OTGI2C_CTL_OFFSET 0x0308 /* I2C Control */ +#define LPC17_OTGI2C_CLKHI_OFFSET 0x030c /* I2C Clock High */ +#define LPC17_OTGI2C_CLKLO_OFFSET 0x0310 /* I2C Clock Low */ + +/* Clock control registers ***********************************************************/ + +#define LPC17_USBOTG_CLKCTRL_OFFSET 0x0ff4 /* OTG clock controller */ +#define LPC17_USBOTG_CLKST_OFFSET 0x0ff8 /* OTG clock status */ + +#define LPC17_USBDEV_CLKCTRL_OFFSET 0x0ff4 /* USB Clock Control */ +#define LPC17_USBDEV_CLKST_OFFSET 0x0ff8 /* USB Clock Status */ + +/* Register addresses ***************************************************************/ +/* USB Host Controller (OHCI) *******************************************************/ +/* Control and status registers (section 7.1) */ + +#define LPC17_USBHOST_HCIREV (LPC17_USB_BASE+OHCI_HCIREV_OFFSET) +#define LPC17_USBHOST_CTRL (LPC17_USB_BASE+OHCI_CTRL_OFFSET) +#define LPC17_USBHOST_CMDST (LPC17_USB_BASE+OHCI_CMDST_OFFSET) +#define LPC17_USBHOST_INTST (LPC17_USB_BASE+OHCI_INTST_OFFSET) +#define LPC17_USBHOST_INTEN (LPC17_USB_BASE+OHCI_INTEN_OFFSET) +#define LPC17_USBHOST_INTDIS (LPC17_USB_BASE+OHCI_INTDIS_OFFSET) + +/* Memory pointers (section 7.2) */ + +#define LPC17_USBHOST_HCCA (LPC17_USB_BASE+OHCI_HCCA_OFFSET) +#define LPC17_USBHOST_PERED (LPC17_USB_BASE+OHCI_PERED_OFFSET) +#define LPC17_USBHOST_CTRLHEADED (LPC17_USB_BASE+OHCI_CTRLHEADED_OFFSET) +#define LPC17_USBHOST_CTRLED (LPC17_USB_BASE+OHCI_CTRLED_OFFSET) +#define LPC17_USBHOST_BULKHEADED (LPC17_USB_BASE+OHCI_BULKHEADED_OFFSET) +#define LPC17_USBHOST_BULKED (LPC17_USB_BASE+OHCI_BULKED_OFFSET) +#define LPC17_USBHOST_DONEHEAD (LPC17_USB_BASE+OHCI_DONEHEAD_OFFSET) + +/* Frame counters (section 7.3) */ + +#define LPC17_USBHOST_FMINT (LPC17_USB_BASE+OHCI_FMINT_OFFSET) +#define LPC17_USBHOST_FMREM (LPC17_USB_BASE+OHCI_FMREM_OFFSET) +#define LPC17_USBHOST_FMNO (LPC17_USB_BASE+OHCI_FMNO_OFFSET) +#define LPC17_USBHOST_PERSTART (LPC17_USB_BASE+OHCI_PERSTART_OFFSET) + +/* Root hub ports (section 7.4) */ + +#define LPC17_USBHOST_LSTHRES (LPC17_USB_BASE+OHCI_LSTHRES_OFFSET) +#define LPC17_USBHOST_RHDESCA (LPC17_USB_BASE+OHCI_RHDESCA_OFFSET) +#define LPC17_USBHOST_RHDESCB (LPC17_USB_BASE+OHCI_RHDESCB_OFFSET) +#define LPC17_USBHOST_RHSTATUS (LPC17_USB_BASE+OHCI_RHSTATUS_OFFSET) +#define LPC17_USBHOST_RHPORTST1 (LPC17_USB_BASE+OHCI_RHPORTST1_OFFSET) +#define LPC17_USBHOST_RHPORTST2 (LPC17_USB_BASE+OHCI_RHPORTST2_OFFSET) +#define LPC17_USBHOST_MODID (LPC17_USB_BASE+LPC17_USBHOST_MODID_OFFSET) + +/* USB OTG Controller ***************************************************************/ +/* OTG registers */ + +#define LPC17_USBOTG_INTST (LPC17_USB_BASE+LPC17_USBOTG_INTST_OFFSET) +#define LPC17_USBOTG_INTEN (LPC17_USB_BASE+LPC17_USBOTG_INTEN_OFFSET) +#define LPC17_USBOTG_INTSET (LPC17_USB_BASE+LPC17_USBOTG_INTSET_OFFSET) +#define LPC17_USBOTG_INTCLR (LPC17_USB_BASE+LPC17_USBOTG_INTCLR_OFFSET) +#define LPC17_USBOTG_STCTRL (LPC17_USB_BASE+LPC17_USBOTG_STCTRL_OFFSET) +#define LPC17_USBOTG_TMR (LPC17_USB_BASE+LPC17_USBOTG_TMR_OFFSET) + +/* USB Device Controller ************************************************************/ +/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ + +#define LPC17_USBDEV_INTST (LPC17_USB_BASE+LPC17_USBDEV_INTST_OFFSET) +#define LPC17_USBDEV_INTEN (LPC17_USB_BASE+LPC17_USBDEV_INTEN_OFFSET) +#define LPC17_USBDEV_INTCLR (LPC17_USB_BASE+LPC17_USBDEV_INTCLR_OFFSET) +#define LPC17_USBDEV_INTSET (LPC17_USB_BASE+LPC17_USBDEV_INTSET_OFFSET) + +/* SIE Command registers */ + +#define LPC17_USBDEV_CMDCODE (LPC17_USB_BASE+LPC17_USBDEV_CMDCODE_OFFSET) +#define LPC17_USBDEV_CMDDATA (LPC17_USB_BASE+LPC17_USBDEV_CMDDATA_OFFSET) + +/* USB transfer registers */ + +#define LPC17_USBDEV_RXDATA (LPC17_USB_BASE+LPC17_USBDEV_RXDATA_OFFSET) +#define LPC17_USBDEV_RXPLEN (LPC17_USB_BASE+LPC17_USBDEV_RXPLEN_OFFSET) +#define LPC17_USBDEV_TXDATA (LPC17_USB_BASE+LPC17_USBDEV_TXDATA_OFFSET) +#define LPC17_USBDEV_TXPLEN (LPC17_USB_BASE+LPC17_USBDEV_TXPLEN_OFFSET) +#define LPC17_USBDEV_CTRL (LPC17_USB_BASE+LPC17_USBDEV_CTRL_OFFSET) + +/* More Device interrupt registers */ + +#define LPC17_USBDEV_INTPRI (LPC17_USB_BASE+LPC17_USBDEV_INTPRI_OFFSET) + +/* Endpoint interrupt registers */ + +#define LPC17_USBDEV_EPINTST (LPC17_USB_BASE+LPC17_USBDEV_EPINTST_OFFSET) +#define LPC17_USBDEV_EPINTEN (LPC17_USB_BASE+LPC17_USBDEV_EPINTEN_OFFSET) +#define LPC17_USBDEV_EPINTCLR (LPC17_USB_BASE+LPC17_USBDEV_EPINTCLR_OFFSET) +#define LPC17_USBDEV_EPINTSET (LPC17_USB_BASE+LPC17_USBDEV_EPINTSET_OFFSET) +#define LPC17_USBDEV_EPINTPRI (LPC17_USB_BASE+LPC17_USBDEV_EPINTPRI_OFFSET) + +/* Endpoint realization registers */ + +#define LPC17_USBDEV_REEP (LPC17_USB_BASE+LPC17_USBDEV_REEP_OFFSET) +#define LPC17_USBDEV_EPIND (LPC17_USB_BASE+LPC17_USBDEV_EPIND_OFFSET) +#define LPC17_USBDEV_MAXPSIZE (LPC17_USB_BASE+LPC17_USBDEV_MAXPSIZE_OFFSET) + +/* DMA registers */ + +#define LPC17_USBDEV_DMARST (LPC17_USB_BASE+LPC17_USBDEV_DMARST_OFFSET) +#define LPC17_USBDEV_DMARCLR (LPC17_USB_BASE+LPC17_USBDEV_DMARCLR_OFFSET) +#define LPC17_USBDEV_DMARSET (LPC17_USB_BASE+LPC17_USBDEV_DMARSET_OFFSET) +#define LPC17_USBDEV_UDCAH (LPC17_USB_BASE+LPC17_USBDEV_UDCAH_OFFSET) +#define LPC17_USBDEV_EPDMAST (LPC17_USB_BASE+LPC17_USBDEV_EPDMAST_OFFSET) +#define LPC17_USBDEV_EPDMAEN (LPC17_USB_BASE+LPC17_USBDEV_EPDMAEN_OFFSET) +#define LPC17_USBDEV_EPDMADIS (LPC17_USB_BASE+LPC17_USBDEV_EPDMADIS_OFFSET) +#define LPC17_USBDEV_DMAINTST (LPC17_USB_BASE+LPC17_USBDEV_DMAINTST_OFFSET) +#define LPC17_USBDEV_DMAINTEN (LPC17_USB_BASE+LPC17_USBDEV_DMAINTEN_OFFSET) +#define LPC17_USBDEV_EOTINTST (LPC17_USB_BASE+LPC17_USBDEV_EOTINTST_OFFSET) +#define LPC17_USBDEV_EOTINTCLR (LPC17_USB_BASE+LPC17_USBDEV_EOTINTCLR_OFFSET) +#define LPC17_USBDEV_EOTINTSET (LPC17_USB_BASE+LPC17_USBDEV_EOTINTSET_OFFSET) +#define LPC17_USBDEV_NDDRINTST (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTST_OFFSET) +#define LPC17_USBDEV_NDDRINTCLR (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTCLR_OFFSET) +#define LPC17_USBDEV_NDDRINTSET (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTSET_OFFSET) +#define LPC17_USBDEV_SYSERRINTST (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTST_OFFSET) +#define LPC17_USBDEV_SYSERRINTCLR (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTCLR_OFFSET) +#define LPC17_USBDEV_SYSERRINTSET (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTSET_OFFSET) + +/* OTG I2C registers ****************************************************************/ + +#define LPC17_OTGI2C_RX (LPC17_USB_BASE+LPC17_OTGI2C_RX_OFFSET) +#define LPC17_OTGI2C_TX (LPC17_USB_BASE+LPC17_OTGI2C_TX_OFFSET) +#define LPC17_OTGI2C_STS (LPC17_USB_BASE+LPC17_OTGI2C_STS_OFFSET) +#define LPC17_OTGI2C_CTL (LPC17_USB_BASE+LPC17_OTGI2C_CTL_OFFSET) +#define LPC17_OTGI2C_CLKHI (LPC17_USB_BASE+LPC17_OTGI2C_CLKHI_OFFSET) +#define LPC17_OTGI2C_CLKLO (LPC17_USB_BASE+LPC17_OTGI2C_CLKLO_OFFSET) + +/* Clock control registers ***********************************************************/ + +#define LPC17_USBOTG_CLKCTRL (LPC17_USB_BASE+LPC17_USBOTG_CLKCTRL_OFFSET) +#define LPC17_USBOTG_CLKST (LPC17_USB_BASE+LPC17_USBOTG_CLKST_OFFSET) + +#define LPC17_USBDEV_CLKCTRL (LPC17_USB_BASE+LPC17_USBDEV_CLKCTRL_OFFSET) +#define LPC17_USBDEV_CLKST (LPC17_USB_BASE+LPC17_USBDEV_CLKST_OFFSET) + +/* Register bit definitions *********************************************************/ +/* USB Host Controller (OHCI) *******************************************************/ +/* See include/nuttx/usb/ohci.h */ + +/* Module ID/Revision ID */ + +#define USBHOST_MODID_VER_SHIFT (0) /* Bits 0-7: Unique version number */ +#define USBHOST_MODID_VER_MASK (0xff << USBHOST_MODID_VER_SHIFT) +#define USBHOST_MODID_REV_SHIFT (8) /* Bits 9-15: Unique revision number */ +#define USBHOST_MODID_REV_MASK (0xff << USBHOST_MODID_REV_SHIFT) +#define USBHOST_MODID_3505_SHIFT (16) /* Bits 16-31: 0x3505 */ +#define USBHOST_MODID_3505_MASK (0xffff << USBHOST_MODID_3505_SHIFT) +# define USBHOST_MODID_3505 (0x3505 << USBHOST_MODID_3505_SHIFT) + +/* USB OTG Controller ***************************************************************/ +/* OTG registers: + * + * OTG Interrupt Status, OTG Interrupt Enable, OTG Interrupt Set, AND OTG Interrupt + * Clear + */ + +#define USBOTG_INT_TMR (1 << 0) /* Bit 0: Timer time-out */ +#define USBOTG_INT_REMOVE_PU (1 << 1) /* Bit 1: Remove pull-up */ +#define USBOTG_INT_HNP_FAILURE (1 << 2) /* Bit 2: HNP failed */ +#define USBOTG_INT_HNP_SUCCESS (1 << 3) /* Bit 3: HNP succeeded */ + /* Bits 4-31: Reserved */ +/* OTG Status and Control */ + +#define USBOTG_STCTRL_PORTFUNC_SHIFT (0) /* Bits 0-1: Controls port function */ +#define USBOTG_STCTRL_PORTFUNC_MASK (3 << USBOTG_STCTRL_PORTFUNC_SHIFT) +# define USBOTG_STCTRL_PORTFUNC_HNPOK (1 << USBOTG_STCTRL_PORTFUNC_SHIFT) /* HNP suceeded */ +#define USBOTG_STCTRL_TMRSCALE_SHIFT (2) /* Bits 2-3: Timer scale selection */ +#define USBOTG_STCTRL_TMRSCALE_MASK (3 << USBOTG_STCTRL_TMR_SCALE_SHIFT) +# define USBOTG_STCTRL_TMRSCALE_10US (0 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 10uS (100 KHz) */ +# define USBOTG_STCTRL_TMRSCALE_100US (1 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 100uS (10 KHz) */ +# define USBOTG_STCTRL_TMRSCALE_1000US (2 << USBOTG_STCTRL_TMR_SCALE_SHIFT) /* 1000uS (1 KHz) */ +#define USBOTG_STCTRL_TMRMODE (1 << 4) /* Bit 4: Timer mode selection */ +#define USBOTG_STCTRL_TMREN (1 << 5) /* Bit 5: Timer enable */ +#define USBOTG_STCTRL_TMRRST (1 << 6) /* Bit 6: TTimer reset */ + /* Bit 7: Reserved */ +#define USBOTG_STCTRL_BHNPTRACK (1 << 8) /* Bit 8: Enable HNP tracking for B-device (peripheral) */ +#define USBOTG_STCTRL_AHNPTRACK (1 << 9) /* Bit 9: Enable HNP tracking for A-device (host) */ +#define USBOTG_STCTRL_PUREMOVED (1 << 10) /* Bit 10: Set when D+ pull-up removed */ + /* Bits 11-15: Reserved */ +#define USBOTG_STCTRL_TMRCNT_SHIFT (0) /* Bits 16-313: Timer scale selection */ +#define USBOTG_STCTRL_TMRCNT_MASK (0ffff << USBOTG_STCTRL_TMR_CNT_SHIFT) + +/* OTG Timer */ + +#define USBOTG_TMR_TIMEOUTCNT_SHIFT (0) /* Bits 0-15: Interrupt when CNT matches this */ +#define USBOTG_TMR_TIMEOUTCNT_MASK (0xffff << USBOTG_TMR_TIMEOUTCNT_SHIFT) + /* Bits 16-31: Reserved */ + +/* USB Device Controller ************************************************************/ +/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */ +/* USB Device Interrupt Status, USB Device Interrupt Enable, USB Device Interrupt + * Clear, USB Device Interrupt Set, and USB Device Interrupt Priority + */ + +#define USBDEV_INT_FRAME (1 << 0) /* Bit 0: frame interrupt (every 1 ms) */ +#define USBDEV_INT_EPFAST (1 << 1) /* Bit 1: Fast endpoint interrupt */ +#define USBDEV_INT_EPSLOW (1 << 2) /* Bit 2: Slow endpoints interrupt */ +#define USBDEV_INT_DEVSTAT (1 << 3) /* Bit 3: Bus reset, suspend change or connect change */ +#define USBDEV_INT_CCEMPTY (1 << 4) /* Bit 4: Command code register empty */ +#define USBDEV_INT_CDFULL (1 << 5) /* Bit 5: Command data register full */ +#define USBDEV_INT_RXENDPKT (1 << 6) /* Bit 6: RX endpoint data transferred */ +#define USBDEV_INT_TXENDPKT (1 << 7) /* Bit 7: TX endpoint data tansferred */ +#define USBDEV_INT_EPRLZED (1 << 8) /* Bit 8: Endpoints realized */ +#define USBDEV_INT_ERRINT (1 << 9) /* Bit 9: Error Interrupt */ + /* Bits 10-31: Reserved */ +/* SIE Command registers: + * + * USB Command Code + */ + /* Bits 0-7: Reserved */ +#define USBDEV_CMDCODE_PHASE_SHIFT (8) /* Bits 8-15: Command phase */ +#define USBDEV_CMDCODE_PHASE_MASK (0xff << USBDEV_CMDCODE_PHASE_SHIFT) +# define USBDEV_CMDCODE_PHASE_READ (1 << USBDEV_CMDCODE_PHASE_SHIFT) +# define USBDEV_CMDCODE_PHASE_WRITE (2 << USBDEV_CMDCODE_PHASE_SHIFT) +# define USBDEV_CMDCODE_PHASE_COMMAND (5 << USBDEV_CMDCODE_PHASE_SHIFT) +#define USBDEV_CMDCODE_CMD_SHIFT (16) /* Bits 15-23: Command (READ/COMMAND phases) */ +#define USBDEV_CMDCODE_CMD_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT) +#define USBDEV_CMDCODE_WDATA_SHIFT (16) /* Bits 15-23: Write dagta (WRITE phase) */ +#define USBDEV_CMDCODE_WDATA_MASK (0xff << USBDEV_CMDCODE_CMD_SHIFT) + /* Bits 24-31: Reserved */ +/* USB Command Data */ + +#define USBDEV_CMDDATA_SHIFT (0) /* Bits 0-7: Command read data */ +#define USBDEV_CMDDATA_MASK (0xff << USBDEV_CMDDATA_SHIFT) + /* Bits 8-31: Reserved */ +/* USB transfer registers: + * + * USB Receive Data (Bits 0-31: Received data) + */ + +/* USB Receive Packet Length */ + +#define USBDEV_RXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be read */ +#define USBDEV_RXPLEN_MASK (0x3ff << USBDEV_RXPLEN_SHIFT) +#define USBDEV_RXPLEN_DV (1 << 10) /* Bit 10: DV Data valid */ +#define USBDEV_RXPLEN_PKTRDY (1 << 11) /* Bit 11: Packet ready for reading */ + /* Bits 12-31: Reserved */ +/* USB Transmit Data (Bits 0-31: Transmit data) */ + +/* USB Transmit Packet Length */ + +#define USBDEV_TXPLEN_SHIFT (0) /* Bits 0-9: Bytes remaining to be written */ +#define USBDEV_TXPLEN_MASK (0x3ff << USBDEV_TXPLEN_SHIFT) + /* Bits 10-31: Reserved */ +/* USB Control */ + +#define USBDEV_CTRL_RDEN (1 << 0) /* Bit 0: Read mode control */ +#define USBDEV_CTRL_WREN (1 << 1) /* Bit 1: Write mode control */ +#define USBDEV_CTRL_LOGEP_SHIFT (2) /* Bits 2-5: Logical Endpoint number */ +#define USBDEV_CTRL_LOGEP_MASK (15 << USBDEV_CTRL_LOGEP_SHIFT) + /* Bits 6-31: Reserved */ +/* Endpoint interrupt registers: + * + * USB Endpoint Interrupt Status, USB Endpoint Interrupt Enable, USB Endpoint Interrupt + * Clear, USB Endpoint Interrupt Set, and USB Endpoint Priority. Bits correspond + * to on RX or TX value for any of 15 logical endpoints). + */ + +#define USBDEV_LOGEPRX(n) (1 << ((n) << 1)) +#define USBDEV_LOGEPTX(n) ((1 << ((n) << 1)) + 1) +#define USBDEV_LOGEPRX0 (1 << 0) +#define USBDEV_LOGEPTX0 (1 << 1) +#define USBDEV_LOGEPRX1 (1 << 2) +#define USBDEV_LOGEPTX1 (1 << 3) +#define USBDEV_LOGEPRX2 (1 << 4) +#define USBDEV_LOGEPTX2 (1 << 5) +#define USBDEV_LOGEPRX3 (1 << 6) +#define USBDEV_LOGEPTX3 (1 << 7) +#define USBDEV_LOGEPRX4 (1 << 8) +#define USBDEV_LOGEPTX4 (1 << 9) +#define USBDEV_LOGEPRX5 (1 << 10) +#define USBDEV_LOGEPTX5 (1 << 11) +#define USBDEV_LOGEPRX6 (1 << 12) +#define USBDEV_LOGEPTX6 (1 << 13) +#define USBDEV_LOGEPRX7 (1 << 14) +#define USBDEV_LOGEPTX7 (1 << 15) +#define USBDEV_LOGEPRX8 (1 << 16) +#define USBDEV_LOGEPTX8 (1 << 17) +#define USBDEV_LOGEPRX9 (1 << 18) +#define USBDEV_LOGEPTX9 (1 << 19) +#define USBDEV_LOGEPRX10 (1 << 20) +#define USBDEV_LOGEPTX10 (1 << 21) +#define USBDEV_LOGEPRX11 (1 << 22) +#define USBDEV_LOGEPTX11 (1 << 23) +#define USBDEV_LOGEPRX12 (1 << 24) +#define USBDEV_LOGEPTX12 (1 << 25) +#define USBDEV_LOGEPRX13 (1 << 26) +#define USBDEV_LOGEPTX13 (1 << 27) +#define USBDEV_LOGEPRX14 (1 << 28) +#define USBDEV_LOGEPTX14 (1 << 29) +#define USBDEV_LOGEPRX15 (1 << 30) +#define USBDEV_LOGEPTX15 (1 << 31) + +/* Endpoint realization registers: + * + * USB Realize Endpoint (Bits correspond to 1 of 32 physical endpoints) + */ + +#define USBDEV_PHYEP(n) (1 << (n)) +#define USBDEV_PHYEP0 (1 << 0) +#define USBDEV_PHYEP1 (1 << 1) +#define USBDEV_PHYEP2 (1 << 2) +#define USBDEV_PHYEP3 (1 << 3) +#define USBDEV_PHYEP4 (1 << 4) +#define USBDEV_PHYEP5 (1 << 5) +#define USBDEV_PHYEP6 (1 << 6) +#define USBDEV_PHYEP7 (1 << 7) +#define USBDEV_PHYEP8 (1 << 8) +#define USBDEV_PHYEP9 (1 << 9) +#define USBDEV_PHYEP10 (1 << 10) +#define USBDEV_PHYEP11 (1 << 11) +#define USBDEV_PHYEP12 (1 << 12) +#define USBDEV_PHYEP13 (1 << 13) +#define USBDEV_PHYEP14 (1 << 14) +#define USBDEV_PHYEP15 (1 << 15) +#define USBDEV_PHYEP16 (1 << 16) +#define USBDEV_PHYEP17 (1 << 17) +#define USBDEV_PHYEP18 (1 << 18) +#define USBDEV_PHYEP19 (1 << 19) +#define USBDEV_PHYEP20 (1 << 20) +#define USBDEV_PHYEP21 (1 << 21) +#define USBDEV_PHYEP22 (1 << 22) +#define USBDEV_PHYEP23 (1 << 23) +#define USBDEV_PHYEP24 (1 << 24) +#define USBDEV_PHYEP25 (1 << 25) +#define USBDEV_PHYEP26 (1 << 26) +#define USBDEV_PHYEP27 (1 << 27) +#define USBDEV_PHYEP28 (1 << 28) +#define USBDEV_PHYEP29 (1 << 29) +#define USBDEV_PHYEP30 (1 << 30) +#define USBDEV_PHYEP31 (1 << 31) + +/* USB Endpoint Index */ + +#define USBDEV_EPIND_SHIFT (0) /* Bits 0-4: Physical endpoint number (0-31) */ +#define USBDEV_EPIND_MASK (31 << USBDEV_EPIND_SHIFT) + /* Bits 5-31: Reserved */ +/* USB MaxPacketSize */ + +#define USBDEV_MAXPSIZE_SHIFT (0) /* Bits 0-9: Maximum packet size value */ +#define USBDEV_MAXPSIZE_MASK (0x3ff << USBDEV_MAXPSIZE_SHIFT) + /* Bits 10-31: Reserved */ +/* DMA registers: + * + * USB DMA Request Status, USB DMA Request Clear, and USB DMA Request Set. Registers + * contain bits for each of 32 physical endpoints. Use the USBDEV_PHYEP* definitions + * above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* USB UDCA Head */ + /* Bits 0-6: Reserved */ +#define USBDEV_UDCAH_SHIFT (7) /* Bits 7-31: UDCA start address */ +#define USBDEV_UDCAH_MASK (0x01ffffff << USBDEV_UDCAH_SHIFT) + +/* USB Endpoint DMA Status, USB Endpoint DMA Enable, and USB Endpoint DMA Disable. + * Registers contain bits for physical endpoints 2-31. Use the USBDEV_PHYEP* + * definitions above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* USB DMA Interrupt Status and USB DMA Interrupt Enable */ + +#define USBDEV_DMAINT_EOT (1 << 0) /* Bit 0: End of Transfer Interrupt */ +#define USBDEV_DMAINT_NDDR (1 << 1) /* Bit 1: New DD Request Interrupt */ +#define USBDEV_DMAINT_ERR (1 << 2) /* Bit 2: System Error Interrupt */ + /* Bits 3-31: Reserved */ +/* USB End of Transfer Interrupt Status, USB End of Transfer Interrupt Clear, and USB + * End of Transfer Interrupt Set. Registers contain bits for physical endpoints 2-31. + * Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* USB New DD Request Interrupt Status, USB New DD Request Interrupt Clear, and USB + * New DD Request Interrupt Set. Registers contain bits for physical endpoints 2-31. + * Use the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* USB System Error Interrupt Status, USB System Error Interrupt Clear, USB System + * Error Interrupt Set. Registers contain bits for physical endpoints 2-31. Use + * the USBDEV_PHYEP* definitions above. PHYEP0-1 (bits 0-1) must be zero. + */ + +/* OTG I2C registers ****************************************************************/ + +/* I2C Receive */ + +#define OTGI2C_RX_DATA_SHIFT (0) /* Bits 0-7: RX data */ +#define OTGI2C_RX_DATA_MASK (0xff << OTGI2C_RX_SHIFT) + /* Bits 8-31: Reserved */ +/* I2C Transmit */ + +#define OTGI2C_TX_DATA_SHIFT (0) /* Bits 0-7: TX data */ +#define OTGI2C_TX_DATA_MASK (0xff << OTGI2C_TX_DATA_SHIFT) +#define OTGI2C_TX_DATA_START (1 << 8) /* Bit 8: Issue START before transmit */ +#define OTGI2C_TX_DATA_STOP (1 << 9) /* Bit 9: Issue STOP before transmit */ + /* Bits 3-31: Reserved */ +/* I2C Status */ + +#define OTGI2C_STS_TDI (1 << 0) /* Bit 0: Transaction Done Interrupt */ +#define OTGI2C_STS_AFI (1 << 1) /* Bit 1: Arbitration Failure Interrupt */ +#define OTGI2C_STS_NAI (1 << 2) /* Bit 2: No Acknowledge Interrupt */ +#define OTGI2C_STS_DRMI (1 << 3) /* Bit 3: Master Data Request Interrupt */ +#define OTGI2C_STS_DRSI (1 << 4) /* Bit 4: Slave Data Request Interrupt */ +#define OTGI2C_STS_ACTIVE (1 << 5) /* Bit 5: Indicates whether the bus is busy */ +#define OTGI2C_STS_SCL (1 << 6) /* Bit 6: The current value of the SCL signal */ +#define OTGI2C_STS_SDA (1 << 7) /* Bit 7: The current value of the SDA signal */ +#define OTGI2C_STS_RFF (1 << 8) /* Bit 8: Receive FIFO Full (RFF) */ +#define OTGI2C_STS_RFE (1 << 9) /* Bit 9: Receive FIFO Empty */ +#define OTGI2C_STS_TFF (1 << 10) /* Bit 10: Transmit FIFO Full */ +#define OTGI2C_STS_TFE (1 << 11) /* Bit 11: Transmit FIFO Empty */ + /* Bits 12-31: Reserved */ +/* I2C Control */ + +#define OTGI2C_CTL_TDIE (1 << 0) /* Bit 0: Transmit Done Interrupt Enable */ +#define OTGI2C_CTL_AFIE (1 << 1) /* Bit 1: Transmitter Arbitration Failure Interrupt Enable */ +#define OTGI2C_CTL_NAIE (1 << 2) /* Bit 2: Transmitter No Acknowledge Interrupt Enable */ +#define OTGI2C_CTL_DRMIE (1 << 3) /* Bit 3: Master Transmitter Data Request Interrupt Enable */ +#define OTGI2C_CTL_DRSIE (1 << 4) /* Bit 4: Slave Transmitter Data Request Interrupt Enable */ +#define OTGI2C_CTL_REFIE (1 << 5) /* Bit 5: Receive FIFO Full Interrupt Enable */ +#define OTGI2C_CTL_RFDAIE (1 << 6) /* Bit 6: Receive Data Available Interrupt Enable */ +#define OTGI2C_CTL_TFFIE (1 << 7) /* Bit 7: Transmit FIFO Not Full Interrupt Enable */ +#define OTGI2C_CTL_SRST (1 << 8) /* Bit 8: Soft reset */ + /* Bits 9-31: Reserved */ +/* I2C Clock High */ + +#define OTGI2C_CLKHI_SHIFT (0) /* Bits 0-7: Clock divisor high */ +#define OTGI2C_CLKHI_MASK (0xff << OTGI2C_CLKHI_SHIFT) + /* Bits 8-31: Reserved */ +/* I2C Clock Low */ + +#define OTGI2C_CLKLO_SHIFT (0) /* Bits 0-7: Clock divisor high */ +#define OTGI2C_CLLO_MASK (0xff << OTGI2C_CLKLO_SHIFT) + /* Bits 8-31: Reserved */ +/* Clock control registers ***********************************************************/ + +/* USB Clock Control (OTG clock controller) and USB Clock Status (OTG clock status) */ + +#define USBDEV_CLK_HOSTCLK (1 << 0) /* Bit 1: Host clock (OTG only) */ +#define USBDEV_CLK_DEVCLK (1 << 1) /* Bit 1: Device clock */ +#define USBDEV_CLK_I2CCLK (1 << 2) /* Bit 2: I2C clock (OTG only) */ +#define USBDEV_CLK_PORTSELCLK (1 << 3) /* Bit 3: Port select register clock (device only) */ +#define USBDEV_CLK_OTGCLK (1 << 3) /* Bit 3: OTG clock (OTG only) */ +#define USBDEV_CLK_AHBCLK (1 << 4) /* Bit 4: AHB clock */ + /* Bits 5-31: Reserved */ +/* Alternate naming */ + +#define USBOTG_CLK_HOSTCLK USBDEV_CLK_HOSTCLK +#define USBOTG_CLK_DEVCLK USBDEV_CLK_DEVCLK +#define USBOTG_CLK_I2CCLK USBDEV_CLK_I2CCLK +#define USBOTG_CLK_PORTSELCLK USBDEV_CLK_PORTSELCLK +#define USBOTG_CLK_OTGCLK USBDEV_CLK_OTGCLK +#define USBOTG_CLK_AHBCLK USBDEV_CLK_AHBCLK + +/* Endpoints *************************************************************************/ + +#define LPC17_EP0_OUT 0 +#define LPC17_EP0_IN 1 +#define LPC17_CTRLEP_OUT LPC17_EP0_OUT +#define LPC17_CTRLEP_IN LPC17_EP0_IN +#define LPC17_EP1_OUT 2 +#define LPC17_EP1_IN 3 +#define LPC17_EP2_OUT 4 +#define LPC17_EP2_IN 5 +#define LPC17_EP3_OUT 6 +#define LPC17_EP3_IN 7 +#define LPC17_EP4_OUT 8 +#define LPC17_EP4_IN 9 +#define LPC17_EP5_OUT 10 +#define LPC17_EP5_IN 11 +#define LPC17_EP6_OUT 12 +#define LPC17_EP6_IN 13 +#define LPC17_EP7_OUT 14 +#define LPC17_EP7_IN 15 +#define LPC17_EP8_OUT 16 +#define LPC17_EP8_IN 17 +#define LPC17_EP9_OUT 18 +#define LPC17_EP9_IN 19 +#define LPC17_EP10_OUT 20 +#define LPC17_EP10_IN 21 +#define LPC17_EP11_OUT 22 +#define LPC17_EP11_IN 23 +#define LPC17_EP12_OUT 24 +#define LPC17_EP12_IN 25 +#define LPC17_EP13_OUT 26 +#define LPC17_EP13_IN 27 +#define LPC17_EP14_OUT 28 +#define LPC17_EP14_IN 29 +#define LPC17_EP15_OUT 30 +#define LPC17_EP15_IN 31 +#define LPC17_NUMEPS 32 + +/* Commands *************************************************************************/ + +/* USB Command Code Register */ + +#define CMD_USBDEV_PHASESHIFT (8) /* Bits 8-15: Command phase value */ +#define CMD_USBDEV_PHASEMASK (0xff << CMD_USBDEV_PHASESHIFT) +# define CMD_USBDEV_DATAWR (1 << CMD_USBDEV_PHASESHIFT) +# define CMD_USBDEV_DATARD (2 << CMD_USBDEV_PHASESHIFT) +# define CMD_USBDEV_CMDWR (5 << CMD_USBDEV_PHASESHIFT) +#define CMD_USBDEV_CMDSHIFT (16) /* Bits 16-23: Device command/WDATA */ +#define CMD_USBDEV_CMDMASK (0xff << CMD_USBDEV_CMDSHIFT) +#define CMD_USBDEV_WDATASHIFT CMD_USBDEV_CMDSHIFT +#define CMD_USBDEV_WDATAMASK CMD_USBDEV_CMDMASK + +/* Device Commands */ + +#define CMD_USBDEV_SETADDRESS (0x00d0) +#define CMD_USBDEV_CONFIG (0x00d8) +#define CMD_USBDEV_SETMODE (0x00f3) +#define CMD_USBDEV_READFRAMENO (0x00f5) +#define CMD_USBDEV_READTESTREG (0x00fd) +#define CMD_USBDEV_SETSTATUS (0x01fe) /* Bit 8 set to distingish get from set */ +#define CMD_USBDEV_GETSTATUS (0x00fe) +#define CMD_USBDEV_GETERRORCODE (0x00ff) +#define CMD_USBDEV_READERRORSTATUS (0x00fb) + +/* Endpoint Commands */ + +#define CMD_USBDEV_EPSELECT (0x0000) +#define CMD_USBDEV_EPSELECTCLEAR (0x0040) +#define CMD_USBDEV_EPSETSTATUS (0x0140) /* Bit 8 set to distingish get from selectclear */ +#define CMD_USBDEV_EPCLRBUFFER (0x00f2) +#define CMD_USBDEV_EPVALIDATEBUFFER (0x00fa) + +/* Command/response bit definitions ********************************************/ +/* SETADDRESS (0xd0) command definitions */ + +#define CMD_USBDEV_SETADDRESS_MASK (0x7f) /* Bits 0-6: Device address */ +#define CMD_USBDEV_SETADDRESS_DEVEN (1 << 7) /* Bit 7: Device enable */ + +/* SETSTATUS (0xfe) and GETSTATUS (0xfe) response: */ + +#define CMD_STATUS_CONNECT (1 << 0) /* Bit 0: Connected */ +#define CMD_STATUS_CONNCHG (1 << 1) /* Bit 1: Connect change */ +#define CMD_STATUS_SUSPEND (1 << 2) /* Bit 2: Suspend */ +#define CMD_STATUS_SUSPCHG (1 << 3) /* Bit 3: Suspend change */ +#define CMD_STATUS_RESET (1 << 4) /* Bit 4: Bus reset bit */ + +/* EPSELECT (0x00) endpoint status response */ + +#define CMD_EPSELECT_FE (1 << 0) /* Bit 0: IN empty or OUT full */ +#define CMD_EPSELECT_ST (1 << 1) /* Bit 1: Endpoint is stalled */ +#define CMD_EPSELECT_STP (1 << 2) /* Bit 2: Last packet was setup */ +#define CMD_EPSELECT_PO (1 << 3) /* Bit 3: Previous packet was overwritten */ +#define CMD_EPSELECT_EPN (1 << 4) /* Bit 4: NAK sent */ +#define CMD_EPSELECT_B1FULL (1 << 5) /* Bit 5: Buffer 1 full */ +#define CMD_EPSELECT_B2FULL (1 << 6) /* Bit 6: Buffer 2 full */ + /* Bit 7: Reserved */ +/* EPSETSTATUS (0x40) command */ + +#define CMD_SETSTAUS_ST (1 << 0) /* Bit 0: Stalled endpoint bit */ + /* Bits 1-4: Reserved */ +#define CMD_SETSTAUS_DA (1 << 5) /* Bit 5: Disabled endpoint bit */ +#define CMD_SETSTAUS_RFMO (1 << 6) /* Bit 6: Rate feedback mode */ +#define CMD_SETSTAUS_CNDST (1 << 7) /* Bit 7: Conditional stall bit */ + +/* EPCLRBUFFER (0xf2) response */ + +#define CMD_USBDEV_CLRBUFFER_PO (0x00000001) + +/* SETMODE(0xf3) command */ + +#define CMD_SETMODE_APCLK (1 << 0) /* Bit 0: Always PLL Clock */ +#define CMD_SETMODE_INAKCI (1 << 1) /* Bit 1: Interrupt on NAK for Control IN endpoint */ +#define CMD_SETMODE_INAKCO (1 << 2) /* Bit 2: Interrupt on NAK for Control OUT endpoint */ +#define CMD_SETMODE_INAKII (1 << 3) /* Bit 3: Interrupt on NAK for Interrupt IN endpoint */ +#define CMD_SETMODE_INAKIO (1 << 4) /* Bit 4: Interrupt on NAK for Interrupt OUT endpoints */ +#define CMD_SETMODE_INAKBI (1 << 5) /* Bit 5: Interrupt on NAK for Bulk IN endpoints */ +#define CMD_SETMODE_INAKBO (1 << 6) /* Bit 6: Interrupt on NAK for Bulk OUT endpoints */ + +/* READERRORSTATUS (0xFb) command */ + +#define CMD_READERRORSTATUS_PIDERR (1 << 0) /* Bit 0: PID encoding/unknown or Token CRC */ +#define CMD_READERRORSTATUS_UEPKT (1 << 1) /* Bit 1: Unexpected Packet */ +#define CMD_READERRORSTATUS_DCRC (1 << 2) /* Bit 2: Data CRC error */ +#define CMD_READERRORSTATUS_TIMEOUT (1 << 3) /* Bit 3: Time out error */ +#define CMD_READERRORSTATUS_EOP (1 << 4) /* Bit 4: End of packet error */ +#define CMD_READERRORSTATUS_BOVRN (1 << 5) /* Bit 5: Buffer Overrun */ +#define CMD_READERRORSTATUS_BTSTF (1 << 6) /* Bit 6: Bit stuff error */ +#define CMD_READERRORSTATUS_TGLERR (1 << 7) /* Bit 7: Wrong toggle in data PID */ +#define CMD_READERRORSTATUS_ALLERRS (0xff) + +/* DMA ******************************************************************************/ +/* The DMA descriptor */ + +#define USB_DMADESC_NEXTDDPTR 0 /* Offset 0: Next USB descriptor in RAM */ +#define USB_DMADESC_CONFIG 1 /* Offset 1: DMA configuration info. */ +#define USB_DMADESC_STARTADDR 2 /* Offset 2: DMA start address */ +#define USB_DMADESC_STATUS 3 /* Offset 3: DMA status info (read only) */ +#define USB_DMADESC_ISOCSIZEADDR 4 /* Offset 4: Isoc. packet size address */ + +/* Bit settings for CONFIG (offset 1 )*/ + +#define USB_DMADESC_MODE_SHIFT (0) /* Bits 0-1: DMA mode */ +#define USB_DMADESC_MODE_MASK (3 << USB_DMADESC_MODE_SHIFT) +# define USB_DMADESC_MODENORMAL (0 << USB_DMADESC_MODE_SHIFT) /* Mode normal */ +# define USB_DMADESC_MODEATLE (1 << USB_DMADESC_MODE_SHIFT) /* ATLE normal */ +#define USB_DMADESC_NEXTDDVALID (1 << 2) /* Bit 2: Next descriptor valid */ + /* Bit 3: Reserved */ +#define USB_DMADESC_ISCOEP (1 << 4) /* Bit 4: ISOC endpoint */ +#define USB_DMADESC_PKTSIZE_SHIFT (5) /* Bits 5-15: Max packet size */ +#define USB_DMADESC_PKTSIZE_MASK (0x7ff << USB_DMADESC_PKTSIZE_SHIFT) +#define USB_DMADESC_BUFLEN_SHIFT (16) /* Bits 16-31: DMA buffer length */ +#define USB_DMADESC_BUFLEN_MASK (0xffff << USB_DMADESC_BUFLEN_SHIFT + +/* Bit settings for STATUS (offset 3). All must be initialized to zero. */ + +#define USB_DMADESC_STATUS_SHIFT (1) /* Bits 1-4: DMA status */ +#define USB_DMADESC_STATUS_MASK (15 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_NOTSERVICED (0 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_BEINGSERVICED (1 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_NORMALCOMPLETION (2 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_DATAUNDERRUN (3 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_DATAOVERRUN (8 << USB_DMADESC_STATUS_SHIFT) +# define USB_DMADESC_SYSTEMERROR (9 << USB_DMADESC_STATUS_SHIFT) +#define USB_DMADESC_PKTVALID (1 << 5) /* Bit 5: Packet valid */ +#define USB_DMADESC_LSBEXTRACTED (1 << 6) /* Bit 6: LS byte extracted */ +#define USB_DMADESC_MSBEXTRACTED (1 << 7) /* Bit 7: MS byte extracted */ +#define USB_DMADESC_MSGLENPOS_SHIFT (8) /* Bits 8-13: Message length position */ +#define USB_DMADESC_MSGLENPOS_MASK (0x3f << USB_DMADESC_MSGLENPOS_SHIFT) +#define USB_DMADESC_DMACOUNT_SHIFT (16) /* Bits 16-31: DMA count */ +#define USB_DMADESC_DMACOUNT_MASK (0xffff << USB_DMADESC_DMACOUNT_SHIFT) + +/* DMA packet size format */ + +#define USB_DMAPKTSIZE_PKTLEN_SHIFT (0) /* Bits 0-15: Packet length */ +#define USB_DMAPKTSIZE_PKTLEN_MASK (0xffff << USB_DMAPKTSIZE_PKTLEN_SHIFT) +#define USB_DMAPKTSIZE_PKTVALID (1 << 16) /* Bit 16: Packet valid */ +#define USB_DMAPKTSIZE_FRAMENO_SHIFT (17) /* Bit 17-31: Frame number */ +#define USB_DMAPKTSIZE_FRAMENO_MASK (0x7fff << USB_DMAPKTSIZE_FRAMENO_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H */ diff --git a/arch/arm/src/lpc17xx/lpc17_vectors.S b/arch/arm/src/lpc17xx/lpc17_vectors.S index 75eb71f17fde10b31c2ba9353eb26533a9588d7d..cdb4bef66c155360fd1e558758261ab7db747c39 100644 --- a/arch/arm/src/lpc17xx/lpc17_vectors.S +++ b/arch/arm/src/lpc17xx/lpc17_vectors.S @@ -3,7 +3,7 @@ * arch/arm/src/chip/lpc17_vectors.S * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc17xx/lpc17_wdt.h b/arch/arm/src/lpc17xx/lpc17_wdt.h index dc02b2e1dc3ef635bdf43cdf98b24ac6765b9191..bd7790a6eac775c18d13cba83af17542dee4bfb2 100644 --- a/arch/arm/src/lpc17xx/lpc17_wdt.h +++ b/arch/arm/src/lpc17xx/lpc17_wdt.h @@ -1,108 +1,108 @@ -/************************************************************************************ - * arch/arm/src/lpc17xx/lpc17_wdt.h - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H -#define __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "lpc17_memorymap.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define LPC17_WDT_WDMOD_OFFSET 0x0000 /* Watchdog mode register */ -#define LPC17_WDT_WDTC_OFFSET 0x0004 /* Watchdog timer constant register */ -#define LPC17_WDT_WDFEED_OFFSET 0x0008 /* Watchdog feed sequence register */ -#define LPC17_WDT_WDTV_OFFSET 0x000c /* Watchdog timer value register */ -#define LPC17_WDT_WDCLKSEL_OFFSET 0x0010 /* Watchdog clock source selection register */ - -/* Register addresses ***************************************************************/ - -#define LPC17_WDT_WDMOD (LPC17_WDT_BASE+LPC17_WDT_WDMOD_OFFSET) -#define LPC17_WDT_WDTC (LPC17_WDT_BASE+LPC17_WDT_WDTC_OFFSET) -#define LPC17_WDT_WDFEED (LPC17_WDT_BASE+LPC17_WDT_WDFEED_OFFSET) -#define LPC17_WDT_WDTV (LPC17_WDT_BASE+LPC17_WDT_WDTV_OFFSET) -#define LPC17_WDT_WDCLKSEL (LPC17_WDT_BASE+LPC17_WDT_WDCLKSEL_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* Watchdog mode register */ - -#define WDT_WDMOD_WDEN (1 << 0) /* Bit 0: Watchdog enable */ -#define WDT_WDMOD_WDRESET (1 << 1) /* Bit 1: Watchdog reset enable */ -#define WDT_WDMOD_WDTOF (1 << 2) /* Bit 2: Watchdog time-out */ -#define WDT_WDMOD_WDINT (1 << 3) /* Bit 3: Watchdog interrupt */ - /* Bits 14-31: Reserved */ - -/* Watchdog timer constant register (Bits 0-31: Watchdog time-out interval) */ - -/* Watchdog feed sequence register */ - -#define WDT_WDFEED_MASK (0xff) /* Bits 0-7: Feed value should be 0xaa followed by 0x55 */ - /* Bits 14-31: Reserved */ -/* Watchdog timer value register (Bits 0-31: Counter timer value) */ - -/* Watchdog clock source selection register */ - -#define WDT_WDCLKSEL_WDSEL_SHIFT (0) /* Bits 0-1: Clock source for the Watchdog timer */ -#define WDT_WDCLKSEL_WDSEL_MASK (3 << WDT_WDCLKSEL_WDSEL_SHIFT) -# define WDT_WDCLKSEL_WDSEL_INTRC (0 << WDT_WDCLKSEL_WDSEL_SHIFT) /* Internal RC osc */ -# define WDT_WDCLKSEL_WDSEL_APB (1 << WDT_WDCLKSEL_WDSEL_SHIFT) /* APB peripheral clock (watchdog pclk) */ -# define WDT_WDCLKSEL_WDSEL_RTC (2 << WDT_WDCLKSEL_WDSEL_SHIFT) /* RTC oscillator (rtc_clk) */ - /* Bits 2-30: Reserved */ -#define WDT_WDCLKSEL_WDLOCK (1 << 31) /* Bit 31: Lock WDT register bits if set */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H */ +/************************************************************************************ + * arch/arm/src/lpc17xx/lpc17_wdt.h + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H +#define __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "lpc17_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define LPC17_WDT_WDMOD_OFFSET 0x0000 /* Watchdog mode register */ +#define LPC17_WDT_WDTC_OFFSET 0x0004 /* Watchdog timer constant register */ +#define LPC17_WDT_WDFEED_OFFSET 0x0008 /* Watchdog feed sequence register */ +#define LPC17_WDT_WDTV_OFFSET 0x000c /* Watchdog timer value register */ +#define LPC17_WDT_WDCLKSEL_OFFSET 0x0010 /* Watchdog clock source selection register */ + +/* Register addresses ***************************************************************/ + +#define LPC17_WDT_WDMOD (LPC17_WDT_BASE+LPC17_WDT_WDMOD_OFFSET) +#define LPC17_WDT_WDTC (LPC17_WDT_BASE+LPC17_WDT_WDTC_OFFSET) +#define LPC17_WDT_WDFEED (LPC17_WDT_BASE+LPC17_WDT_WDFEED_OFFSET) +#define LPC17_WDT_WDTV (LPC17_WDT_BASE+LPC17_WDT_WDTV_OFFSET) +#define LPC17_WDT_WDCLKSEL (LPC17_WDT_BASE+LPC17_WDT_WDCLKSEL_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* Watchdog mode register */ + +#define WDT_WDMOD_WDEN (1 << 0) /* Bit 0: Watchdog enable */ +#define WDT_WDMOD_WDRESET (1 << 1) /* Bit 1: Watchdog reset enable */ +#define WDT_WDMOD_WDTOF (1 << 2) /* Bit 2: Watchdog time-out */ +#define WDT_WDMOD_WDINT (1 << 3) /* Bit 3: Watchdog interrupt */ + /* Bits 14-31: Reserved */ + +/* Watchdog timer constant register (Bits 0-31: Watchdog time-out interval) */ + +/* Watchdog feed sequence register */ + +#define WDT_WDFEED_MASK (0xff) /* Bits 0-7: Feed value should be 0xaa followed by 0x55 */ + /* Bits 14-31: Reserved */ +/* Watchdog timer value register (Bits 0-31: Counter timer value) */ + +/* Watchdog clock source selection register */ + +#define WDT_WDCLKSEL_WDSEL_SHIFT (0) /* Bits 0-1: Clock source for the Watchdog timer */ +#define WDT_WDCLKSEL_WDSEL_MASK (3 << WDT_WDCLKSEL_WDSEL_SHIFT) +# define WDT_WDCLKSEL_WDSEL_INTRC (0 << WDT_WDCLKSEL_WDSEL_SHIFT) /* Internal RC osc */ +# define WDT_WDCLKSEL_WDSEL_APB (1 << WDT_WDCLKSEL_WDSEL_SHIFT) /* APB peripheral clock (watchdog pclk) */ +# define WDT_WDCLKSEL_WDSEL_RTC (2 << WDT_WDCLKSEL_WDSEL_SHIFT) /* RTC oscillator (rtc_clk) */ + /* Bits 2-30: Reserved */ +#define WDT_WDCLKSEL_WDLOCK (1 << 31) /* Bit 31: Lock WDT register bits if set */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H */ diff --git a/arch/arm/src/lpc214x/Make.defs b/arch/arm/src/lpc214x/Make.defs index 1f199a6ba7339a9eaa3162dd7c7be26f18a7c3ac..41dc0911c62468ba985a20d003c40f6ad4c09060 100644 --- a/arch/arm/src/lpc214x/Make.defs +++ b/arch/arm/src/lpc214x/Make.defs @@ -2,7 +2,7 @@ # lpc214x/Make.defs # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc214x/chip.h b/arch/arm/src/lpc214x/chip.h index 9d7d963b18cc4da55efbf868e16aee1764a7a15a..d469aae8bb115c16d8417e5a9cab1436d3cd01a7 100644 --- a/arch/arm/src/lpc214x/chip.h +++ b/arch/arm/src/lpc214x/chip.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/chip.h * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc214x/lpc214x_apb.h b/arch/arm/src/lpc214x/lpc214x_apb.h index 996983778ebd8393bdae7334eb016a637fdcdcfc..2d41ab106272dd061b1ab61d565ecba19b95a79a 100644 --- a/arch/arm/src/lpc214x/lpc214x_apb.h +++ b/arch/arm/src/lpc214x/lpc214x_apb.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_apb.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc214x/lpc214x_decodeirq.c b/arch/arm/src/lpc214x/lpc214x_decodeirq.c index 6317066c3fb3d0f00f5711fffca8d0aa38e76fa0..652fe4d6187dab9a137794f01a59dcf4977c7c48 100644 --- a/arch/arm/src/lpc214x/lpc214x_decodeirq.c +++ b/arch/arm/src/lpc214x/lpc214x_decodeirq.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_decodeirq.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc214x/lpc214x_i2c.h b/arch/arm/src/lpc214x/lpc214x_i2c.h index 804dc0a11ba476c8eff427fce38866c740f6aafd..a663999683d83ac791d32f8efc2ae566d5edc697 100644 --- a/arch/arm/src/lpc214x/lpc214x_i2c.h +++ b/arch/arm/src/lpc214x/lpc214x_i2c.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_i2c.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc214x/lpc214x_irq.c b/arch/arm/src/lpc214x/lpc214x_irq.c index a8b91037c836b70065a962bb6d772f0ecce82ff5..cb0f6e12fccb5b403a4b9b6ca145f3f8dc7e33df 100644 --- a/arch/arm/src/lpc214x/lpc214x_irq.c +++ b/arch/arm/src/lpc214x/lpc214x_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_irq.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc214x/lpc214x_lowputc.S b/arch/arm/src/lpc214x/lpc214x_lowputc.S index e36b1d83f849cf3d366cb51c14c31c201d618857..b53e7aa78e3d508c570da3901a3d292d5204264e 100644 --- a/arch/arm/src/lpc214x/lpc214x_lowputc.S +++ b/arch/arm/src/lpc214x/lpc214x_lowputc.S @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214X_lowputc.S * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc214x/lpc214x_pinsel.h b/arch/arm/src/lpc214x/lpc214x_pinsel.h index e3f793f0932927368212fa9c615b8c5653cf3f2c..b34eb86b68bb78f62d05fb2dd932049c1a7b32ec 100644 --- a/arch/arm/src/lpc214x/lpc214x_pinsel.h +++ b/arch/arm/src/lpc214x/lpc214x_pinsel.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_pinsl.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc214x/lpc214x_pll.h b/arch/arm/src/lpc214x/lpc214x_pll.h index 386f3a765cda2c42041d7e2db8d93c3360b20f3f..bea923e43115304a3914de176cef79cf2061a0ab 100644 --- a/arch/arm/src/lpc214x/lpc214x_pll.h +++ b/arch/arm/src/lpc214x/lpc214x_pll.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_pll.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc214x/lpc214x_power.h b/arch/arm/src/lpc214x/lpc214x_power.h index cd493dac65d97cfa40f374278ba77421ebe96d78..7eb253160de890048a8d1b7d09d35e15ed1babd2 100644 --- a/arch/arm/src/lpc214x/lpc214x_power.h +++ b/arch/arm/src/lpc214x/lpc214x_power.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_power.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc214x/lpc214x_spi.h b/arch/arm/src/lpc214x/lpc214x_spi.h index 202b9e2507caf6cfbd941c9bfc1c782872effddc..ce6a03db9b03054ce0c119f99179fd06f4b88d26 100644 --- a/arch/arm/src/lpc214x/lpc214x_spi.h +++ b/arch/arm/src/lpc214x/lpc214x_spi.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_spi.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc214x/lpc214x_timer.h b/arch/arm/src/lpc214x/lpc214x_timer.h index 47adf979671e7a4fd84843ca8301910ed73d671c..6c239f10cad0acf990d39e6a3f325cca89a01fe0 100644 --- a/arch/arm/src/lpc214x/lpc214x_timer.h +++ b/arch/arm/src/lpc214x/lpc214x_timer.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_timer.h * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc214x/lpc214x_timerisr.c b/arch/arm/src/lpc214x/lpc214x_timerisr.c index 65e9adb57d4b5b8a0e47688da7b538977eb982af..99d1d118ff0285623764e564672e404cecbd84a5 100644 --- a/arch/arm/src/lpc214x/lpc214x_timerisr.c +++ b/arch/arm/src/lpc214x/lpc214x_timerisr.c @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_timerisr.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc214x/lpc214x_uart.h b/arch/arm/src/lpc214x/lpc214x_uart.h index 2752d17ae9ddc197d15dec292f5dbddf6c80eb24..fd634a8165d0adaf335cc81b9b93d30f0d41336f 100755 --- a/arch/arm/src/lpc214x/lpc214x_uart.h +++ b/arch/arm/src/lpc214x/lpc214x_uart.h @@ -1,142 +1,142 @@ -/************************************************************************************ - * arch/arm/src/lpc214x/uart.h - * - * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __LPC214X_UART_H -#define __LPC214X_UART_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include /* For clock settings */ - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* PINSEL0 bit definitions for UART0/1 */ - -#define LPC214X_UART0_PINSEL 0x00000005 /* PINSEL0 value for UART0 */ -#define LPC214X_UART0_PINMASK 0x0000000f /* PINSEL0 mask for UART0 */ - -#define LPC214X_UART1_PINSEL 0x00050000 /* PINSEL0 value for UART1 */ -#define LPC214X_UART1_PINMASK 0x000f0000 /* PINSEL0 mask for UART1 */ - -/* Derive baud divisor setting from clock settings (see board.h) */ - -#define UART_BAUD(baud) ((LPC214X_FOSC * LPC214X_PLL_M) / (baud * 16)) - -/* Interrupt Enable Register (IER) bit definitions */ - -#define LPC214X_IER_ERBFI (1 << 0) /* Enable receive data available int */ -#define LPC214X_IER_ETBEI (1 << 1) /* Enable THR empty Interrupt */ -#define LPC214X_IER_ELSI (1 << 2) /* Enable receive line status int */ -#define LPC214X_IER_EDSSI (1 << 3) /* Enable MODEM atatus interrupt (2146/6/8 UART1 Only) */ -#define LPC214X_IER_ALLIE 0x0f /* All interrupts */ - -/* Interrupt ID Register(IIR) bit definitions */ - -#define LPC214X_IIR_NO_INT (1 << 0) /* No interrupts pending */ -#define LPC214X_IIR_MS_INT (0 << 1) /* MODEM Status (UART1 only) */ -#define LPC214X_IIR_THRE_INT (1 << 1) /* Transmit Holding Register Empty */ -#define LPC214X_IIR_RDA_INT (2 << 1) /* Receive Data Available */ -#define LPC214X_IIR_RLS_INT (3 << 1) /* Receive Line Status */ -#define LPC214X_IIR_CTI_INT (6 << 1) /* Character Timeout Indicator */ -#define LPC214X_IIR_MASK 0x0e - -/* FIFO Control Register (FCR) bit definitions */ - -#define LPC214X_FCR_FIFO_ENABLE (1 << 0) /* FIFO enable */ -#define LPC214X_FCR_RX_FIFO_RESET (1 << 1) /* Reset receive FIFO */ -#define LPC214X_FCR_TX_FIFO_RESET (1 << 2) /* Reset transmit FIFO */ -#define LPC214X_FCR_FIFO_TRIG1 (0 << 6) /* Trigger @1 character in FIFO */ -#define LPC214X_FCR_FIFO_TRIG4 (1 << 6) /* Trigger @4 characters in FIFO */ -#define LPC214X_FCR_FIFO_TRIG8 (2 << 6) /* Trigger @8 characters in FIFO */ -#define LPC214X_FCR_FIFO_TRIG14 (3 << 6) /* Trigger @14 characters in FIFO */ - -/* Line Control Register (LCR) bit definitions */ - -#define LPC214X_LCR_CHAR_5 (0 << 0) /* 5-bit character length */ -#define LPC214X_LCR_CHAR_6 (1 << 0) /* 6-bit character length */ -#define LPC214X_LCR_CHAR_7 (2 << 0) /* 7-bit character length */ -#define LPC214X_LCR_CHAR_8 (3 << 0) /* 8-bit character length */ -#define LPC214X_LCR_STOP_1 (0 << 2) /* 1 stop bit */ -#define LPC214X_LCR_STOP_2 (1 << 2) /* 2 stop bits */ -#define LPC214X_LCR_PAR_NONE (0 << 3) /* No parity */ -#define LPC214X_LCR_PAR_ODD (1 << 3) /* Odd parity */ -#define LPC214X_LCR_PAR_EVEN (3 << 3) /* Even parity */ -#define LPC214X_LCR_PAR_MARK (5 << 3) /* Mark "1" parity */ -#define LPC214X_LCR_PAR_SPACE (7 << 3) /* Space "0" parity */ -#define LPC214X_LCR_BREAK_ENABLE (1 << 6) /* Output BREAK */ -#define LPC214X_LCR_DLAB_ENABLE (1 << 7) /* Enable divisor latch access */ - -/* Modem Control Register (MCR) bit definitions */ - -#define LPC214X_MCR_DTR (1 << 0) /* Data terminal ready */ -#define LPC214X_MCR_RTS (1 << 1) /* Request to send */ -#define LPC214X_MCR_LB (1 << 4) /* Loopback */ - -/* Line Status Register (LSR) bit definitions */ - -#define LPC214X_LSR_RDR (1 << 0) /* Receive data ready */ -#define LPC214X_LSR_OE (1 << 1) /* Overrun error */ -#define LPC214X_LSR_PE (1 << 2) /* Parity error */ -#define LPC214X_LSR_FE (1 << 3) /* Framing error */ -#define LPC214X_LSR_BI (1 << 4) /* Break interrupt */ -#define LPC214X_LSR_THRE (1 << 5) /* THR empty */ -#define LPC214X_LSR_TEMT (1 << 6) /* Transmitter empty */ -#define LPC214X_LSR_RXFE (1 << 7) /* Error in receive FIFO */ -#define LPC214X_LSR_ERR_MASK 0x1e - -/* Modem Status Register (MSR) bit definitions */ - -#define LPC214X_MSR_DCTS (1 << 0) /* Delta clear to send */ -#define LPC214X_MSR_DDSR (1 << 1) /* Delta data set ready */ -#define LPC214X_MSR_TERI (1 << 2) /* Trailing edge ring indicator */ -#define LPC214X_MSR_DDCD (1 << 3) /* Delta data carrier detect */ -#define LPC214X_MSR_CTS (1 << 4) /* Clear to send */ -#define LPC214X_MSR_DSR (1 << 5) /* Data set ready */ -#define LPC214X_MSR_RI (1 << 6) /* Ring indicator */ -#define LPC214X_MSR_DCD (1 << 7) /* Data carrier detect */ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -/************************************************************************************ - * Global Function Prototypes - ************************************************************************************/ - -#endif /* __LPC214X_UART_H */ +/************************************************************************************ + * arch/arm/src/lpc214x/uart.h + * + * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __LPC214X_UART_H +#define __LPC214X_UART_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include /* For clock settings */ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* PINSEL0 bit definitions for UART0/1 */ + +#define LPC214X_UART0_PINSEL 0x00000005 /* PINSEL0 value for UART0 */ +#define LPC214X_UART0_PINMASK 0x0000000f /* PINSEL0 mask for UART0 */ + +#define LPC214X_UART1_PINSEL 0x00050000 /* PINSEL0 value for UART1 */ +#define LPC214X_UART1_PINMASK 0x000f0000 /* PINSEL0 mask for UART1 */ + +/* Derive baud divisor setting from clock settings (see board.h) */ + +#define UART_BAUD(baud) ((LPC214X_FOSC * LPC214X_PLL_M) / (baud * 16)) + +/* Interrupt Enable Register (IER) bit definitions */ + +#define LPC214X_IER_ERBFI (1 << 0) /* Enable receive data available int */ +#define LPC214X_IER_ETBEI (1 << 1) /* Enable THR empty Interrupt */ +#define LPC214X_IER_ELSI (1 << 2) /* Enable receive line status int */ +#define LPC214X_IER_EDSSI (1 << 3) /* Enable MODEM atatus interrupt (2146/6/8 UART1 Only) */ +#define LPC214X_IER_ALLIE 0x0f /* All interrupts */ + +/* Interrupt ID Register(IIR) bit definitions */ + +#define LPC214X_IIR_NO_INT (1 << 0) /* No interrupts pending */ +#define LPC214X_IIR_MS_INT (0 << 1) /* MODEM Status (UART1 only) */ +#define LPC214X_IIR_THRE_INT (1 << 1) /* Transmit Holding Register Empty */ +#define LPC214X_IIR_RDA_INT (2 << 1) /* Receive Data Available */ +#define LPC214X_IIR_RLS_INT (3 << 1) /* Receive Line Status */ +#define LPC214X_IIR_CTI_INT (6 << 1) /* Character Timeout Indicator */ +#define LPC214X_IIR_MASK 0x0e + +/* FIFO Control Register (FCR) bit definitions */ + +#define LPC214X_FCR_FIFO_ENABLE (1 << 0) /* FIFO enable */ +#define LPC214X_FCR_RX_FIFO_RESET (1 << 1) /* Reset receive FIFO */ +#define LPC214X_FCR_TX_FIFO_RESET (1 << 2) /* Reset transmit FIFO */ +#define LPC214X_FCR_FIFO_TRIG1 (0 << 6) /* Trigger @1 character in FIFO */ +#define LPC214X_FCR_FIFO_TRIG4 (1 << 6) /* Trigger @4 characters in FIFO */ +#define LPC214X_FCR_FIFO_TRIG8 (2 << 6) /* Trigger @8 characters in FIFO */ +#define LPC214X_FCR_FIFO_TRIG14 (3 << 6) /* Trigger @14 characters in FIFO */ + +/* Line Control Register (LCR) bit definitions */ + +#define LPC214X_LCR_CHAR_5 (0 << 0) /* 5-bit character length */ +#define LPC214X_LCR_CHAR_6 (1 << 0) /* 6-bit character length */ +#define LPC214X_LCR_CHAR_7 (2 << 0) /* 7-bit character length */ +#define LPC214X_LCR_CHAR_8 (3 << 0) /* 8-bit character length */ +#define LPC214X_LCR_STOP_1 (0 << 2) /* 1 stop bit */ +#define LPC214X_LCR_STOP_2 (1 << 2) /* 2 stop bits */ +#define LPC214X_LCR_PAR_NONE (0 << 3) /* No parity */ +#define LPC214X_LCR_PAR_ODD (1 << 3) /* Odd parity */ +#define LPC214X_LCR_PAR_EVEN (3 << 3) /* Even parity */ +#define LPC214X_LCR_PAR_MARK (5 << 3) /* Mark "1" parity */ +#define LPC214X_LCR_PAR_SPACE (7 << 3) /* Space "0" parity */ +#define LPC214X_LCR_BREAK_ENABLE (1 << 6) /* Output BREAK */ +#define LPC214X_LCR_DLAB_ENABLE (1 << 7) /* Enable divisor latch access */ + +/* Modem Control Register (MCR) bit definitions */ + +#define LPC214X_MCR_DTR (1 << 0) /* Data terminal ready */ +#define LPC214X_MCR_RTS (1 << 1) /* Request to send */ +#define LPC214X_MCR_LB (1 << 4) /* Loopback */ + +/* Line Status Register (LSR) bit definitions */ + +#define LPC214X_LSR_RDR (1 << 0) /* Receive data ready */ +#define LPC214X_LSR_OE (1 << 1) /* Overrun error */ +#define LPC214X_LSR_PE (1 << 2) /* Parity error */ +#define LPC214X_LSR_FE (1 << 3) /* Framing error */ +#define LPC214X_LSR_BI (1 << 4) /* Break interrupt */ +#define LPC214X_LSR_THRE (1 << 5) /* THR empty */ +#define LPC214X_LSR_TEMT (1 << 6) /* Transmitter empty */ +#define LPC214X_LSR_RXFE (1 << 7) /* Error in receive FIFO */ +#define LPC214X_LSR_ERR_MASK 0x1e + +/* Modem Status Register (MSR) bit definitions */ + +#define LPC214X_MSR_DCTS (1 << 0) /* Delta clear to send */ +#define LPC214X_MSR_DDSR (1 << 1) /* Delta data set ready */ +#define LPC214X_MSR_TERI (1 << 2) /* Trailing edge ring indicator */ +#define LPC214X_MSR_DDCD (1 << 3) /* Delta data carrier detect */ +#define LPC214X_MSR_CTS (1 << 4) /* Clear to send */ +#define LPC214X_MSR_DSR (1 << 5) /* Data set ready */ +#define LPC214X_MSR_RI (1 << 6) /* Ring indicator */ +#define LPC214X_MSR_DCD (1 << 7) /* Data carrier detect */ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Global Function Prototypes + ************************************************************************************/ + +#endif /* __LPC214X_UART_H */ diff --git a/arch/arm/src/lpc214x/lpc214x_usbdev.h b/arch/arm/src/lpc214x/lpc214x_usbdev.h index 67774f1fb0adf3c60b607ca3bbc7e40d7bf52ed6..814622ef51c6e33d65ad06104ec528d545923076 100644 --- a/arch/arm/src/lpc214x/lpc214x_usbdev.h +++ b/arch/arm/src/lpc214x/lpc214x_usbdev.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_usbdev.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc214x/lpc214x_vic.h b/arch/arm/src/lpc214x/lpc214x_vic.h index 912019e280b0d5641cbf520c96cc44a84c529f98..520c6037aea1933f38d5138d3e7d187b715aa4aa 100755 --- a/arch/arm/src/lpc214x/lpc214x_vic.h +++ b/arch/arm/src/lpc214x/lpc214x_vic.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc214x/lpc214x_vic.h * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc2378/Make.defs b/arch/arm/src/lpc2378/Make.defs index 2b444d317d87a7e7c5589401fff799632c6c1dc3..9126fa2a1a842dd3591c97b8b7c703879b4f1ddf 100755 --- a/arch/arm/src/lpc2378/Make.defs +++ b/arch/arm/src/lpc2378/Make.defs @@ -7,7 +7,7 @@ # This file is part of the NuttX RTOS and based on the lpc2148 port: # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc2378/chip.h b/arch/arm/src/lpc2378/chip.h index d371c12f056e820234b93395b4fd9cce7e5badd9..6113f21e8109182588494d996a128e6341c247f0 100755 --- a/arch/arm/src/lpc2378/chip.h +++ b/arch/arm/src/lpc2378/chip.h @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc2378/internal.h b/arch/arm/src/lpc2378/internal.h index 7abd98700956b7ad9ffbf538262a891bd7d351f1..5a0e63b6210cbed88ee76800d95af4ee5e1106df 100755 --- a/arch/arm/src/lpc2378/internal.h +++ b/arch/arm/src/lpc2378/internal.h @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc2378/lpc23xx_decodeirq.c b/arch/arm/src/lpc2378/lpc23xx_decodeirq.c index 100502a2218ca08aabccaaab1aa7c067199f223c..a55ed339d052148f5d6a7da58a603c79470d0719 100755 --- a/arch/arm/src/lpc2378/lpc23xx_decodeirq.c +++ b/arch/arm/src/lpc2378/lpc23xx_decodeirq.c @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc2378/lpc23xx_gpio.h b/arch/arm/src/lpc2378/lpc23xx_gpio.h index ecf629d842f80689ccdcb88645ef6d0108d58e9e..f18bd685a8b7e8a4b9dfee46e1d742e179cc9328 100755 --- a/arch/arm/src/lpc2378/lpc23xx_gpio.h +++ b/arch/arm/src/lpc2378/lpc23xx_gpio.h @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc2378/lpc23xx_irq.c b/arch/arm/src/lpc2378/lpc23xx_irq.c index 10f188cbaf5f571c5fe8a95def1df189a4664a87..96e94c45462504b06c3b5f4eb14e406e13c7641b 100755 --- a/arch/arm/src/lpc2378/lpc23xx_irq.c +++ b/arch/arm/src/lpc2378/lpc23xx_irq.c @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc2378/lpc23xx_lowputc.S b/arch/arm/src/lpc2378/lpc23xx_lowputc.S index 1d88b77fb4e8904cb055bc3cc4f1824cbc42fb5d..cc332a96158fd7b84e445906d16b6ed2edd5412d 100755 --- a/arch/arm/src/lpc2378/lpc23xx_lowputc.S +++ b/arch/arm/src/lpc2378/lpc23xx_lowputc.S @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc2378/lpc23xx_pinsel.h b/arch/arm/src/lpc2378/lpc23xx_pinsel.h index 04c6507b1b094dff6802d89044586e3c1ba19435..10a97c7f1a008f5938de805ccff88324b6357546 100755 --- a/arch/arm/src/lpc2378/lpc23xx_pinsel.h +++ b/arch/arm/src/lpc2378/lpc23xx_pinsel.h @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc2378/lpc23xx_scb.h b/arch/arm/src/lpc2378/lpc23xx_scb.h index e80f8e23ed871b2892105b980e2689a0a64501e2..d876ef6ecb7530fc2099ba8e46333715c8de52e9 100755 --- a/arch/arm/src/lpc2378/lpc23xx_scb.h +++ b/arch/arm/src/lpc2378/lpc23xx_scb.h @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc2378/lpc23xx_timer.h b/arch/arm/src/lpc2378/lpc23xx_timer.h index 28439e2201d723af3b4a06322fe8cf5302c71a28..4de1b3fff2c9462766f50f7c5338f5e1064dae52 100755 --- a/arch/arm/src/lpc2378/lpc23xx_timer.h +++ b/arch/arm/src/lpc2378/lpc23xx_timer.h @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc2378/lpc23xx_timerisr.c b/arch/arm/src/lpc2378/lpc23xx_timerisr.c index 5e8d5696d0a61a47592208bb3bb32b08190916a2..d9e63d6d6e143f324d617e5a0a2873e8102bf159 100755 --- a/arch/arm/src/lpc2378/lpc23xx_timerisr.c +++ b/arch/arm/src/lpc2378/lpc23xx_timerisr.c @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc2378/lpc23xx_uart.h b/arch/arm/src/lpc2378/lpc23xx_uart.h index e493a0abd85e21b39fcacaca1d367619295326be..2c8999bfa360fe2c4d2e9ef8de28b0917e8705f8 100755 --- a/arch/arm/src/lpc2378/lpc23xx_uart.h +++ b/arch/arm/src/lpc2378/lpc23xx_uart.h @@ -1,231 +1,231 @@ -/************************************************************************************ - * arch/arm/src/lpc2378/lpc2378/uart.h - * - * Copyright (C) 2010 Rommel Marcelo. All rights reserved. - * Author: Rommel Marcelo - * - * This file is part of the NuttX RTOS and based on the lpc2148 port: - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_UART_H -#define __ARCH_ARM_SRC_LPC2378_LPC23XX_UART_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include /* For clock settings */ - -/************************************************************************************ - * Definitions - ************************************************************************************/ -/* Derive baud divisor setting from clock settings (see board.h) */ -//--F_in = 57 600 000 Hz U0DLM=0, U0DLL=25, DIVADDVAL=3, MULVAL=12, baudrate=115200, err = 0.000000 % -//--F_in = 57 600 000 Hz U0DLM=1, U0DLL=119, DIVADDVAL=0, MULVAL=1, baudrate=9600, err = 0.000000 % -/* Used only if CONFIG_UART_MULVAL is not defined */ -#define DIVADDVAL 0 -#define MULVAL 1 -#define DLMVAL 1 -#define DLLVAL 119 - -/* UARTx PCLK divider valid values are 1,2,4 */ -#define U0_PCLKDIV 1 -//~ #define U1_PCLKDIV 1 -#define U2_PCLKDIV 1 -//~ #define U3_PCLKDIV 1 - - -#define U0_PCLK (CCLK / U0_PCLKDIV) -//~ #define U1_PCLK (CCLK / U1_PCLKDIV) -#define U2_PCLK (CCLK / U2_PCLKDIV) -//~ #define U3_PCLK (CCLK / U3_PCLKDIV) - -#define U0_PCLKSEL_MASK (0x000000C0) -#define U2_PCLKSEL_MASK (0x00030000) - -/* PCKLSEL0 bits 7:6, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */ -#ifdef U0_PCLKDIV -# if U0_PCLKDIV == 1 -# define U0_PCLKSEL (0x00000040) -# elif U0_PCLKDIV == 2 -# define U0_PCLKSEL (0x00000080) -# elif U0_PCLKDIV == 4 -# define U0_PCLKSEL (0x00000000) -# endif -#else -# error "UART0 PCLK divider not set" -#endif - -/* PCKLSEL1 bits 17:16, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */ -#ifdef U2_PCLKDIV -# if U2_PCLKDIV == 1 -# define U2_PCLKSEL (0x00010000) -# elif U2_PCLKDIV == 2 -# define U2_PCLKSEL (0x00020000) -# elif U2_PCLKDIV == 4 -# define U2_PCLKSEL (0x00000000) -# endif -#else -# error "UART2 PCLK divider not set" -#endif - - - - -/* Universal Asynchronous Receiver Transmitter Base Addresses */ -#define UART0_BASE_ADDR 0xE000C000 -#define UART1_BASE_ADDR 0xE0010000 -#define UART2_BASE_ADDR 0xE0078000 -#define UART3_BASE_ADDR 0xE007C000 - -/* UART 0/1/2/3 Register Offsets */ -#define UART_RBR_OFFSET 0x00 /* R: Receive Buffer Register (DLAB=0) */ -#define UART_THR_OFFSET 0x00 /* W: Transmit Holding Register (DLAB=0) */ -#define UART_DLL_OFFSET 0x00 /* W: Divisor Latch Register (LSB, DLAB=1) */ -#define UART_IER_OFFSET 0x04 /* W: Interrupt Enable Register (DLAB=0) */ -#define UART_DLM_OFFSET 0x04 /* RW: Divisor Latch Register (MSB, DLAB=1) */ -#define UART_IIR_OFFSET 0x08 /* R: Interrupt ID Register */ -#define UART_FCR_OFFSET 0x08 /* W: FIFO Control Register */ -#define UART_LCR_OFFSET 0x0c /* RW: Line Control Register */ -#define UART_MCR_OFFSET 0x10 /* RW: Modem Control REgister (2146/6/8 UART1 Only) */ -#define UART_LSR_OFFSET 0x14 /* R: Scratch Pad Register */ -#define UART_MSR_OFFSET 0x18 /* RW: MODEM Status Register (2146/6/8 UART1 Only) */ -#define UART_SCR_OFFSET 0x1c /* RW: Line Status Register */ -#define UART_ACR_OFFSET 0x20 /* RW: Autobaud Control Register */ -#define UART_FDR_OFFSET 0x28 /* RW: Fractional Divider Register */ -#define UART_TER_OFFSET 0x30 /* RW: Transmit Enable Register */ - -/* PINSEL0 bit definitions for UART0/2 */ - -#define UART0_PINSEL 0x00000050 /* PINSEL0 value for UART0 */ -#define UART0_PINMASK 0x000000F0 /* PINSEL0 mask for UART0 */ - -#define UART1_TX_PINSEL 0x40000000 /* PINSEL0 value for UART1 Tx */ -#define UART1_TXPINMASK 0xC0000000 /* PINSEL0 mask for UART1 Tx */ -#define UART1_RX_PINSEL 0x00000001 /* PINSEL1 value for UART1 Rx */ -#define UART1_RX_PINMASK 0x00000003 /* PINSEL1 mask for UART1 Rx */ -#define UART1_MODEM_PINSEL 0x00001555 /* PINSEL1 mask for UART1 Modem Interface */ -#define UART1_CTS_PINMASK 0x00003FFF /* PINSEL1 mask for UART1 Modem Interface */ -//~ #define UART1_CTS_PINSEL 0x00000004 /* PINSEL1 mask for UART1 CTS */ -//~ #define UART1_CTS_PINMASK 0x0000000C /* PINSEL1 mask for UART1 CTS */ -//~ #define UART1_CTS_PINSEL 0x00000010 /* PINSEL1 mask for UART1 Rx */ -//~ #define UART1_CTS_PINMASK 0x00000030 /* PINSEL1 mask for UART1 Rx */ -#define UART2_PINSEL 0x00500000 /* PINSEL0 value for UART2 */ -#define UART2_PINMASK 0x00F00000 /* PINSEL0 mask for UART2 */ - -#define UART3_PINSEL 0x0F000000 /* PINSEL9 value for UART3 */ -#define UART3_PINMASK 0x0F000000 /* PINSEL9 mask for UART3 */ - -/* Interrupt Enable Register (IER) bit definitions */ - -#define IER_ERBFI (1 << 0) /* Enable receive data available int */ -#define IER_ETBEI (1 << 1) /* Enable THR empty Interrupt */ -#define IER_ELSI (1 << 2) /* Enable receive line status int */ -#define IER_EDSSI (1 << 3) /* Enable MODEM atatus interrupt (2146/6/8 UART1 Only) */ -#define IER_ALLIE 0x0f /* All interrupts */ - -/* Interrupt ID Register(IIR) bit definitions */ - -#define IIR_NO_INT (1 << 0) /* No interrupts pending */ -#define IIR_MS_INT (0 << 1) /* MODEM Status (UART1 only) */ -#define IIR_THRE_INT (1 << 1) /* Transmit Holding Register Empty */ -#define IIR_RDA_INT (2 << 1) /* Receive Data Available */ -#define IIR_RLS_INT (3 << 1) /* Receive Line Status */ -#define IIR_CTI_INT (6 << 1) /* Character Timeout Indicator */ -#define IIR_MASK 0x0e - -/* FIFO Control Register (FCR) bit definitions */ - -#define FCR_FIFO_ENABLE (1 << 0) /* FIFO enable */ -#define FCR_RX_FIFO_RESET (1 << 1) /* Reset receive FIFO */ -#define FCR_TX_FIFO_RESET (1 << 2) /* Reset transmit FIFO */ -#define FCR_FIFO_TRIG1 (0 << 6) /* Trigger @1 character in FIFO */ -#define FCR_FIFO_TRIG4 (1 << 6) /* Trigger @4 characters in FIFO */ -#define FCR_FIFO_TRIG8 (2 << 6) /* Trigger @8 characters in FIFO */ -#define FCR_FIFO_TRIG14 (3 << 6) /* Trigger @14 characters in FIFO */ - -/* Line Control Register (LCR) bit definitions */ - -#define LCR_CHAR_5 (0 << 0) /* 5-bit character length */ -#define LCR_CHAR_6 (1 << 0) /* 6-bit character length */ -#define LCR_CHAR_7 (2 << 0) /* 7-bit character length */ -#define LCR_CHAR_8 (3 << 0) /* 8-bit character length */ -#define LCR_STOP_1 (0 << 2) /* 1 stop bit */ -#define LCR_STOP_2 (1 << 2) /* 2 stop bits */ -#define LCR_PAR_NONE (0 << 3) /* No parity */ -#define LCR_PAR_ODD (1 << 3) /* Odd parity */ -#define LCR_PAR_EVEN (3 << 3) /* Even parity */ -#define LCR_PAR_MARK (5 << 3) /* Mark "1" parity */ -#define LCR_PAR_SPACE (7 << 3) /* Space "0" parity */ -#define LCR_BREAK_ENABLE (1 << 6) /* Output BREAK */ -#define LCR_DLAB_ENABLE (1 << 7) /* Enable divisor latch access */ - -/* Modem Control Register (MCR) bit definitions */ - -#define MCR_DTR (1 << 0) /* Data terminal ready */ -#define MCR_RTS (1 << 1) /* Request to send */ -#define MCR_LB (1 << 4) /* Loopback */ - -/* Line Status Register (LSR) bit definitions */ - -#define LSR_RDR (1 << 0) /* Receive data ready */ -#define LSR_OE (1 << 1) /* Overrun error */ -#define LSR_PE (1 << 2) /* Parity error */ -#define LSR_FE (1 << 3) /* Framing error */ -#define LSR_BI (1 << 4) /* Break interrupt */ -#define LSR_THRE (1 << 5) /* THR empty */ -#define LSR_TEMT (1 << 6) /* Transmitter empty */ -#define LSR_RXFE (1 << 7) /* Error in receive FIFO */ -#define LSR_ERR_MASK 0x1e - -/* Modem Status Register (MSR) bit definitions */ - -#define MSR_DCTS (1 << 0) /* Delta clear to send */ -#define MSR_DDSR (1 << 1) /* Delta data set ready */ -#define MSR_TERI (1 << 2) /* Trailing edge ring indicator */ -#define MSR_DDCD (1 << 3) /* Delta data carrier detect */ -#define MSR_CTS (1 << 4) /* Clear to send */ -#define MSR_DSR (1 << 5) /* Data set ready */ -#define MSR_RI (1 << 6) /* Ring indicator */ -#define MSR_DCD (1 << 7) /* Data carrier detect */ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -/************************************************************************************ - * Global Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_UART_H */ +/************************************************************************************ + * arch/arm/src/lpc2378/lpc2378/uart.h + * + * Copyright (C) 2010 Rommel Marcelo. All rights reserved. + * Author: Rommel Marcelo + * + * This file is part of the NuttX RTOS and based on the lpc2148 port: + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_UART_H +#define __ARCH_ARM_SRC_LPC2378_LPC23XX_UART_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include /* For clock settings */ + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* Derive baud divisor setting from clock settings (see board.h) */ +//--F_in = 57 600 000 Hz U0DLM=0, U0DLL=25, DIVADDVAL=3, MULVAL=12, baudrate=115200, err = 0.000000 % +//--F_in = 57 600 000 Hz U0DLM=1, U0DLL=119, DIVADDVAL=0, MULVAL=1, baudrate=9600, err = 0.000000 % +/* Used only if CONFIG_UART_MULVAL is not defined */ +#define DIVADDVAL 0 +#define MULVAL 1 +#define DLMVAL 1 +#define DLLVAL 119 + +/* UARTx PCLK divider valid values are 1,2,4 */ +#define U0_PCLKDIV 1 +//~ #define U1_PCLKDIV 1 +#define U2_PCLKDIV 1 +//~ #define U3_PCLKDIV 1 + + +#define U0_PCLK (CCLK / U0_PCLKDIV) +//~ #define U1_PCLK (CCLK / U1_PCLKDIV) +#define U2_PCLK (CCLK / U2_PCLKDIV) +//~ #define U3_PCLK (CCLK / U3_PCLKDIV) + +#define U0_PCLKSEL_MASK (0x000000C0) +#define U2_PCLKSEL_MASK (0x00030000) + +/* PCKLSEL0 bits 7:6, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */ +#ifdef U0_PCLKDIV +# if U0_PCLKDIV == 1 +# define U0_PCLKSEL (0x00000040) +# elif U0_PCLKDIV == 2 +# define U0_PCLKSEL (0x00000080) +# elif U0_PCLKDIV == 4 +# define U0_PCLKSEL (0x00000000) +# endif +#else +# error "UART0 PCLK divider not set" +#endif + +/* PCKLSEL1 bits 17:16, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */ +#ifdef U2_PCLKDIV +# if U2_PCLKDIV == 1 +# define U2_PCLKSEL (0x00010000) +# elif U2_PCLKDIV == 2 +# define U2_PCLKSEL (0x00020000) +# elif U2_PCLKDIV == 4 +# define U2_PCLKSEL (0x00000000) +# endif +#else +# error "UART2 PCLK divider not set" +#endif + + + + +/* Universal Asynchronous Receiver Transmitter Base Addresses */ +#define UART0_BASE_ADDR 0xE000C000 +#define UART1_BASE_ADDR 0xE0010000 +#define UART2_BASE_ADDR 0xE0078000 +#define UART3_BASE_ADDR 0xE007C000 + +/* UART 0/1/2/3 Register Offsets */ +#define UART_RBR_OFFSET 0x00 /* R: Receive Buffer Register (DLAB=0) */ +#define UART_THR_OFFSET 0x00 /* W: Transmit Holding Register (DLAB=0) */ +#define UART_DLL_OFFSET 0x00 /* W: Divisor Latch Register (LSB, DLAB=1) */ +#define UART_IER_OFFSET 0x04 /* W: Interrupt Enable Register (DLAB=0) */ +#define UART_DLM_OFFSET 0x04 /* RW: Divisor Latch Register (MSB, DLAB=1) */ +#define UART_IIR_OFFSET 0x08 /* R: Interrupt ID Register */ +#define UART_FCR_OFFSET 0x08 /* W: FIFO Control Register */ +#define UART_LCR_OFFSET 0x0c /* RW: Line Control Register */ +#define UART_MCR_OFFSET 0x10 /* RW: Modem Control REgister (2146/6/8 UART1 Only) */ +#define UART_LSR_OFFSET 0x14 /* R: Scratch Pad Register */ +#define UART_MSR_OFFSET 0x18 /* RW: MODEM Status Register (2146/6/8 UART1 Only) */ +#define UART_SCR_OFFSET 0x1c /* RW: Line Status Register */ +#define UART_ACR_OFFSET 0x20 /* RW: Autobaud Control Register */ +#define UART_FDR_OFFSET 0x28 /* RW: Fractional Divider Register */ +#define UART_TER_OFFSET 0x30 /* RW: Transmit Enable Register */ + +/* PINSEL0 bit definitions for UART0/2 */ + +#define UART0_PINSEL 0x00000050 /* PINSEL0 value for UART0 */ +#define UART0_PINMASK 0x000000F0 /* PINSEL0 mask for UART0 */ + +#define UART1_TX_PINSEL 0x40000000 /* PINSEL0 value for UART1 Tx */ +#define UART1_TXPINMASK 0xC0000000 /* PINSEL0 mask for UART1 Tx */ +#define UART1_RX_PINSEL 0x00000001 /* PINSEL1 value for UART1 Rx */ +#define UART1_RX_PINMASK 0x00000003 /* PINSEL1 mask for UART1 Rx */ +#define UART1_MODEM_PINSEL 0x00001555 /* PINSEL1 mask for UART1 Modem Interface */ +#define UART1_CTS_PINMASK 0x00003FFF /* PINSEL1 mask for UART1 Modem Interface */ +//~ #define UART1_CTS_PINSEL 0x00000004 /* PINSEL1 mask for UART1 CTS */ +//~ #define UART1_CTS_PINMASK 0x0000000C /* PINSEL1 mask for UART1 CTS */ +//~ #define UART1_CTS_PINSEL 0x00000010 /* PINSEL1 mask for UART1 Rx */ +//~ #define UART1_CTS_PINMASK 0x00000030 /* PINSEL1 mask for UART1 Rx */ +#define UART2_PINSEL 0x00500000 /* PINSEL0 value for UART2 */ +#define UART2_PINMASK 0x00F00000 /* PINSEL0 mask for UART2 */ + +#define UART3_PINSEL 0x0F000000 /* PINSEL9 value for UART3 */ +#define UART3_PINMASK 0x0F000000 /* PINSEL9 mask for UART3 */ + +/* Interrupt Enable Register (IER) bit definitions */ + +#define IER_ERBFI (1 << 0) /* Enable receive data available int */ +#define IER_ETBEI (1 << 1) /* Enable THR empty Interrupt */ +#define IER_ELSI (1 << 2) /* Enable receive line status int */ +#define IER_EDSSI (1 << 3) /* Enable MODEM atatus interrupt (2146/6/8 UART1 Only) */ +#define IER_ALLIE 0x0f /* All interrupts */ + +/* Interrupt ID Register(IIR) bit definitions */ + +#define IIR_NO_INT (1 << 0) /* No interrupts pending */ +#define IIR_MS_INT (0 << 1) /* MODEM Status (UART1 only) */ +#define IIR_THRE_INT (1 << 1) /* Transmit Holding Register Empty */ +#define IIR_RDA_INT (2 << 1) /* Receive Data Available */ +#define IIR_RLS_INT (3 << 1) /* Receive Line Status */ +#define IIR_CTI_INT (6 << 1) /* Character Timeout Indicator */ +#define IIR_MASK 0x0e + +/* FIFO Control Register (FCR) bit definitions */ + +#define FCR_FIFO_ENABLE (1 << 0) /* FIFO enable */ +#define FCR_RX_FIFO_RESET (1 << 1) /* Reset receive FIFO */ +#define FCR_TX_FIFO_RESET (1 << 2) /* Reset transmit FIFO */ +#define FCR_FIFO_TRIG1 (0 << 6) /* Trigger @1 character in FIFO */ +#define FCR_FIFO_TRIG4 (1 << 6) /* Trigger @4 characters in FIFO */ +#define FCR_FIFO_TRIG8 (2 << 6) /* Trigger @8 characters in FIFO */ +#define FCR_FIFO_TRIG14 (3 << 6) /* Trigger @14 characters in FIFO */ + +/* Line Control Register (LCR) bit definitions */ + +#define LCR_CHAR_5 (0 << 0) /* 5-bit character length */ +#define LCR_CHAR_6 (1 << 0) /* 6-bit character length */ +#define LCR_CHAR_7 (2 << 0) /* 7-bit character length */ +#define LCR_CHAR_8 (3 << 0) /* 8-bit character length */ +#define LCR_STOP_1 (0 << 2) /* 1 stop bit */ +#define LCR_STOP_2 (1 << 2) /* 2 stop bits */ +#define LCR_PAR_NONE (0 << 3) /* No parity */ +#define LCR_PAR_ODD (1 << 3) /* Odd parity */ +#define LCR_PAR_EVEN (3 << 3) /* Even parity */ +#define LCR_PAR_MARK (5 << 3) /* Mark "1" parity */ +#define LCR_PAR_SPACE (7 << 3) /* Space "0" parity */ +#define LCR_BREAK_ENABLE (1 << 6) /* Output BREAK */ +#define LCR_DLAB_ENABLE (1 << 7) /* Enable divisor latch access */ + +/* Modem Control Register (MCR) bit definitions */ + +#define MCR_DTR (1 << 0) /* Data terminal ready */ +#define MCR_RTS (1 << 1) /* Request to send */ +#define MCR_LB (1 << 4) /* Loopback */ + +/* Line Status Register (LSR) bit definitions */ + +#define LSR_RDR (1 << 0) /* Receive data ready */ +#define LSR_OE (1 << 1) /* Overrun error */ +#define LSR_PE (1 << 2) /* Parity error */ +#define LSR_FE (1 << 3) /* Framing error */ +#define LSR_BI (1 << 4) /* Break interrupt */ +#define LSR_THRE (1 << 5) /* THR empty */ +#define LSR_TEMT (1 << 6) /* Transmitter empty */ +#define LSR_RXFE (1 << 7) /* Error in receive FIFO */ +#define LSR_ERR_MASK 0x1e + +/* Modem Status Register (MSR) bit definitions */ + +#define MSR_DCTS (1 << 0) /* Delta clear to send */ +#define MSR_DDSR (1 << 1) /* Delta data set ready */ +#define MSR_TERI (1 << 2) /* Trailing edge ring indicator */ +#define MSR_DDCD (1 << 3) /* Delta data carrier detect */ +#define MSR_CTS (1 << 4) /* Clear to send */ +#define MSR_DSR (1 << 5) /* Data set ready */ +#define MSR_RI (1 << 6) /* Ring indicator */ +#define MSR_DCD (1 << 7) /* Data carrier detect */ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Global Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_UART_H */ diff --git a/arch/arm/src/lpc2378/lpc23xx_vic.h b/arch/arm/src/lpc2378/lpc23xx_vic.h index 964c93ed9fa66cb0215837bda7222179fa5bf5ad..c8b9871a1a0e67a1b5a045927a727d7f4df35b11 100755 --- a/arch/arm/src/lpc2378/lpc23xx_vic.h +++ b/arch/arm/src/lpc2378/lpc23xx_vic.h @@ -7,7 +7,7 @@ * This file is part of the NuttX RTOS and based on the lpc2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc43xx/chip/lpc43_qei.h b/arch/arm/src/lpc43xx/chip/lpc43_qei.h index 5e110ce1545d8f85a5ba11512172adf09f4b185e..9994c4e9e7fc5e27445bacc9a3c5cc600dd14831 100644 --- a/arch/arm/src/lpc43xx/chip/lpc43_qei.h +++ b/arch/arm/src/lpc43xx/chip/lpc43_qei.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc43xx/lpc43_qei.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/lpc43xx/lpc43_usb0dev.c b/arch/arm/src/lpc43xx/lpc43_usb0dev.c index b4ca5542047aaeb2dbb4864dfea91bf0b85b2097..a40d6492de8b6f22fcaaa8d9279577bc1f65b1b6 100644 --- a/arch/arm/src/lpc43xx/lpc43_usb0dev.c +++ b/arch/arm/src/lpc43xx/lpc43_usb0dev.c @@ -7,7 +7,7 @@ * Part of the NuttX OS and based, in part, on the LPC31xx USB driver: * * Authors: David Hewson - * Gregory Nutt + * Gregory Nutt * * Which, in turn, was based on the LPC2148 USB driver: * diff --git a/arch/arm/src/lpc43xx/lpc43_usb0dev.h b/arch/arm/src/lpc43xx/lpc43_usb0dev.h index 94a2a64eacaea7f4b0927ef4470e5484e6ed86fb..fae22d3230bc7acb1bd8037870a43e648a5cdf2b 100644 --- a/arch/arm/src/lpc43xx/lpc43_usb0dev.h +++ b/arch/arm/src/lpc43xx/lpc43_usb0dev.h @@ -2,7 +2,7 @@ * arch/arm/src/lpc43xx/lpc43_usbdev.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/sam3u/chip.h b/arch/arm/src/sam3u/chip.h index 7e18e45c9115cd91fe584a21dd96d89c4614c79b..865cad5eac91a9b33a33d64919670c32be429619 100644 --- a/arch/arm/src/sam3u/chip.h +++ b/arch/arm/src/sam3u/chip.h @@ -2,7 +2,7 @@ * arch/arm/src/sam3u/chip.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/sam3u/sam3u_adc.h b/arch/arm/src/sam3u/sam3u_adc.h index 6b1f9552e85c14e1da818bc36b407c26d8c8b265..4701c0c48132aa68ac30e2ad42f26a336a1421c8 100644 --- a/arch/arm/src/sam3u/sam3u_adc.h +++ b/arch/arm/src/sam3u/sam3u_adc.h @@ -1,236 +1,236 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_adc.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_ADC_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_ADC_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* ADC register offsets ****************************************************************/ - -#define SAM3U_ADC_CR_OFFSET 0x00 /* Control Register (Both) */ -#define SAM3U_ADC_MR_OFFSET 0x04 /* Mode Register (Both) */ - /* 0x08: Reserved */ - /* 0x0c: Reserved */ -#define SAM3U_ADC_CHER_OFFSET 0x10 /* Channel Enable Register (Both) */ -#define SAM3U_ADC_CHDR_OFFSET 0x14 /* Channel Disable Register (Both) */ -#define SAM3U_ADC_CHSR_OFFSET 0x18 /* Channel Status Register (Both) */ -#define SAM3U_ADC_SR_OFFSET 0x1c /* Status Register (Both) */ -#define SAM3U_ADC_LCDR_OFFSET 0x20 /* Last Converted Data Register (Both) */ -#define SAM3U_ADC_IER_OFFSET 0x24 /* Interrupt Enable Register (Both) */ -#define SAM3U_ADC_IDR_OFFSET 0x28 /* Interrupt Disable Register (Both) */ -#define SAM3U_ADC_IMR_OFFSET 0x2c /* Interrupt Mask Register (Both) */ -#define SAM3U_ADC_CDR_OFFSET(n) (0x30+((n)<<2)) -#define SAM3U_ADC_CDR0_OFFSET 0x30 /* Channel Data Register 0 (Both) */ -#define SAM3U_ADC_CDR1_OFFSET 0x34 /* Channel Data Register 1 (Both) */ -#define SAM3U_ADC_CDR2_OFFSET 0x38 /* Channel Data Register 2 (Both) */ -#define SAM3U_ADC_CDR3_OFFSET 0x3c /* Channel Data Register 3 (Both) */ -#define SAM3U_ADC_CDR4_OFFSET 0x40 /* Channel Data Register 4 (Both) */ -#define SAM3U_ADC_CDR5_OFFSET 0x44 /* Channel Data Register 5 (Both) */ -#define SAM3U_ADC_CDR6_OFFSET 0x48 /* Channel Data Register 6 (Both) */ -#define SAM3U_ADC_CDR7_OFFSET 0x4c /* Channel Data Register 7 (Both) */ -#define SAM3U_ADC12B_ACR_OFFSET 0x64 /* Analog Control Register (ADC12B only) */ -#define SAM3U_ADC12B_EMR_OFFSET 0x68 /* Extended Mode Register (ADC12B only) */ - -/* ADC register adresses ***************************************************************/ - -#define SAM3U_ADC12B_CR (SAM3U_ADC12B_BASE+SAM3U_ADC_CR_OFFSET) -#define SAM3U_ADC12B_MR (SAM3U_ADC12B_BASE+SAM3U_ADC_MR_OFFSET) -#define SAM3U_ADC12B_CHER (SAM3U_ADC12B_BASE+SAM3U_ADC_CHER_OFFSET) -#define SAM3U_ADC12B_CHDR (SAM3U_ADC12B_BASE+SAM3U_ADC_CHDR_OFFSET) -#define SAM3U_ADC12B_CHSR (SAM3U_ADC12B_BASE+SAM3U_ADC_CHSR_OFFSET) -#define SAM3U_ADC12B_SR (SAM3U_ADC12B_BASE+SAM3U_ADC_SR_OFFSET) -#define SAM3U_ADC12B_LCDR_ (SAM3U_ADC12B_BASE+SAM3U_ADC_LCDR_OFFSET) -#define SAM3U_ADC12B_IER (SAM3U_ADC12B_BASE+SAM3U_ADC_IER_OFFSET) -#define SAM3U_ADC12B_IDR (SAM3U_ADC12B_BASE+SAM3U_ADC_IDR_OFFSET) -#define SAM3U_ADC12B_IMR (SAM3U_ADC12B_BASE+SAM3U_ADC_IMR_OFFSET) -#define SAM3U_ADC12B_CDR(n)) (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR_OFFSET(n)) -#define SAM3U_ADC12B_CDR0 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR0_OFFSET) -#define SAM3U_ADC12B_CDR1 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR1_OFFSET) -#define SAM3U_ADC12B_CDR2 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR2_OFFSET) -#define SAM3U_ADC12B_CDR3 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR3_OFFSET) -#define SAM3U_ADC12B_CDR4 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR4_OFFSET) -#define SAM3U_ADC12B_CDR5 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR5_OFFSET) -#define SAM3U_ADC12B_CDR6 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR6_OFFSET) -#define SAM3U_ADC12B_CDR7 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR7_OFFSET) -#define SAM3U_ADC12B_ACR (SAM3U_ADC12B_BASE+SAM3U_ADC12B_ACR_OFFSET) -#define SAM3U_ADC12B_EMR (SAM3U_ADC12B_BASE+SAM3U_ADC12B_EMR_OFFSET) - -#define SAM3U_ADC_CR (SAM3U_ADC_BASE+SAM3U_ADC_CR_OFFSET) -#define SAM3U_ADC_MR (SAM3U_ADC_BASE+SAM3U_ADC_MR_OFFSET) -#define SAM3U_ADC_CHER (SAM3U_ADC_BASE+SAM3U_ADC_CHER_OFFSET) -#define SAM3U_ADC_CHDR (SAM3U_ADC_BASE+SAM3U_ADC_CHDR_OFFSET) -#define SAM3U_ADC_CHSR (SAM3U_ADC_BASE+SAM3U_ADC_CHSR_OFFSET) -#define SAM3U_ADC_SR (SAM3U_ADC_BASE+SAM3U_ADC_SR_OFFSET) -#define SAM3U_ADC_LCDR (SAM3U_ADC_BASE+SAM3U_ADC_LCDR_OFFSET) -#define SAM3U_ADC_IER (SAM3U_ADC_BASE+SAM3U_ADC_IER_OFFSET) -#define SAM3U_ADC_IDR (SAM3U_ADC_BASE+SAM3U_ADC_IDR_OFFSET) -#define SAM3U_ADC_IMR (SAM3U_ADC_BASE+SAM3U_ADC_IMR_OFFSET) -#define SAM3U_ADC_CDR(n)) (SAM3U_ADC_BASE+SAM3U_ADC_CDR_OFFSET(n)) -#define SAM3U_ADC_CDR0 (SAM3U_ADC_BASE+SAM3U_ADC_CDR0_OFFSET) -#define SAM3U_ADC_CDR1 (SAM3U_ADC_BASE+SAM3U_ADC_CDR1_OFFSET) -#define SAM3U_ADC_CDR2 (SAM3U_ADC_BASE+SAM3U_ADC_CDR2_OFFSET) -#define SAM3U_ADC_CDR3 (SAM3U_ADC_BASE+SAM3U_ADC_CDR3_OFFSET) -#define SAM3U_ADC_CDR4 (SAM3U_ADC_BASE+SAM3U_ADC_CDR4_OFFSET) -#define SAM3U_ADC_CDR5 (SAM3U_ADC_BASE+SAM3U_ADC_CDR5_OFFSET) -#define SAM3U_ADC_CDR6 (SAM3U_ADC_BASE+SAM3U_ADC_CDR6_OFFSET) -#define SAM3U_ADC_CDR7 (SAM3U_ADC_BASE+SAM3U_ADC_CDR7_OFFSET) - -/* ADC register bit definitions ********************************************************/ - -/* ADC12B Control Register and ADC(10B) Control Register common bit-field definitions */ - -#define ADC_CR_SWRST (1 << 0) /* Bit 0: Software Reset */ -#define ADC_CR_START (1 << 1) /* Bit 1: Start Conversion */ - -/* ADC12B Mode Register and ADC(10B) Mode Register common bit-field definitions */ - -#define ADC_MR_TRGEN (1 << 0) /* Bit 0: Trigger Enable */ -#define ADC_MR_TRGSEL_SHIFT (1) /* Bits 1-3: Trigger Selection */ -#define ADC_MR_TRGSEL_MASK (7 << ADC_MR_TRGSEL_SHIFT) -#define ADC_MR_LOWRES (1 << 4) /* Bit 4: Resolution */ -#define ADC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */ -#define ADC_MR_PRESCAL_SHIFT (8) /* Bits 8-15: Prescaler Rate Selection */ -#define ADC_MR_PRESCAL_MASK (0xff << ADC_MR_PRESCAL_SHIFT) -#define ADB12B_MRSTARTUP_SHIFT (16) /* Bits 16-23: Start Up Time (ADC12B) */ -#define ADB12B_MRSTARTUP_MASK (0xff << ADB12B_MRSTARTUP_SHIFT -#define ADB10B_MRSTARTUP_SHIFT (16) /* Bits 16-22: Start Up Time (ADC10B) */ -#define ADB10B_MRSTARTUP_MASK (0x7f << ADB10B_MRSTARTUP_SHIFT) -#define ADC_MR_SHTIM_SHIFT (24) /* Bits 24-27: Sample & Hold Time */ -#define ADC_MR_SHTIM_MASK (15 << ADC_MR_SHTIM_SHIFT) - -/* ADC12B Channel Enable Register, ADC12B Channel Disable Register, ADC12B Channel - * Status Register, ADC(10B) Channel Enable Register, ADC(10B) Channel Disable Register, - * and ADC(10B) Channel Status Register common bit-field definitions - */ - -#define ADC_CH(n) (1 << (n)) -#define ADC_CH0 (1 << 0) /* Bit 0: Channel x Enable */ -#define ADC_CH1 (1 << 1) /* Bit 1: Channel x Enable */ -#define ADC_CH2 (1 << 2) /* Bit 2: Channel x Enable */ -#define ADC_CH3 (1 << 3) /* Bit 3: Channel x Enable */ -#define ADC_CH4 (1 << 4) /* Bit 4: Channel x Enable */ -#define ADC_CH5 (1 << 5) /* Bit 5: Channel x Enable */ -#define ADC_CH6 (1 << 6) /* Bit 6: Channel x Enable */ -#define ADC_CH7 (1 << 7) /* Bit 7: Channel x Enable */ - -/* ADC12B Analog Control Register (ADC12B only) */ - -#define ADC12B_ACR_GAIN_SHIFT (0) /* Bits 0-1: Input Gain */ -#define ADC12B_ACR_GAIN_MASK (3 << ADC12B_ACR_GAIN_SHIFT) -#define ADC12B_ACR_IBCTL_SHIFT (8) /* Bits 8-9: Bias Current Control */ -#define ADC12B_ACR_IBCTL_MASK (3 << ADC12B_ACR_IBCTL_SHIFT) -#define ADC12B_ACR_DIFF (1 << 16) /* Bit 16: Differential Mode */ -#define ADC12B_ACR_OFFSET (1 << 17) /* Bit 17: Input OFFSET */ - -/* ADC12B Extended Mode Register (ADC12B only) */ - -#define ADC12B_EMR_OFFMODES (1 << 0) /* Bit 0: Off Mode if Sleep Bit (ADC12B_MR) = 1 */ -#define ADC12B_EMR_OFFMSTIME_SHIFT (16) /* Bits 16-23: Startup Time */ -#define ADC12B_EMR_OFFMSTIME_MASK (0xff << ADC12B_EMR_OFFMSTIME_SHIFT) - -/* ADC12B Status Register , ADC12B Interrupt Enable Register, ADC12B Interrupt - * Disable Register, ADC12B Interrupt Mask Register, ADC(10B) Status Register, - * ADC(10B) Interrupt Enable Register, ADC(10B) Interrupt Disable Register, and - * ADC(10B) Interrupt Mask Register common bit-field definitions - */ - -#define ADC_INT_EOC(n) (1<<(n)) -#define ADC_INT_EOC0 (1 << 0) /* Bit 0: End of Conversion 0 */ -#define ADC_INT_EOC1 (1 << 1) /* Bit 1: End of Conversion 1 */ -#define ADC_INT_EOC2 (1 << 2) /* Bit 2: End of Conversion 2 */ -#define ADC_INT_EOC3 (1 << 3) /* Bit 3: End of Conversion 3 */ -#define ADC_INT_EOC4 (1 << 4) /* Bit 4: End of Conversion 4 */ -#define ADC_INT_EOC5 (1 << 5) /* Bit 5: End of Conversion 5 */ -#define ADC_INT_EOC6 (1 << 6) /* Bit 6: End of Conversion 6 */ -#define ADC_INT_EOC7 (1 << 7) /* Bit 0: End of Conversion 7 */ -#define ADC_INT_OVRE(n) (1<<((n)+8)) -#define ADC_INT_OVRE0 (1 << 8) /* Bit 8: Overrun Error 0 */ -#define ADC_INT_OVRE1 (1 << 9) /* Bit 9: Overrun Error 1 */ -#define ADC_INT_OVRE2 (1 << 10) /* Bit 10: Overrun Error 2 */ -#define ADC_INT_OVRE3 (1 << 11) /* Bit 11: Overrun Error 3 */ -#define ADC_INT_OVRE4 (1 << 12) /* Bit 12: Overrun Error 4 */ -#define ADC_INT_OVRE5 (1 << 13) /* Bit 13: Overrun Error 5 */ -#define ADC_INT_OVRE6 (1 << 14) /* Bit 14: Overrun Error 6 */ -#define ADC_INT_OVRE7 (1 << 15) /* Bit 15: Overrun Error 7 */ -#define ADC_INT_DRDY (1 << 16) /* Bit 16: Data Ready */ -#define ADC_INT_GOVRE (1 << 17) /* Bit 17: General Overrun Error */ -#define ADC_INT_ENDRX (1 << 18) /* Bit 18: End of RX Buffer */ -#define ADC_INT_RXBUFF (1 << 19) /* Bit 19: RX Buffer Full */ - -/* ADC12B Last Converted Data Register */ - -#define ADC12B_LCDR_DATA_SHIFT (0) /* Bits 0-11: Last Data Converted */ -#define ADC12B_LCDR_DATA_MASK (0xfff << ADC12B_LCDR_DATA_SHIFT) - -/* ADC(10B) Last Converted Data Register */ - -#define ADC10B_LCDR_DATA_SHIFT (0) /* Bits 0-9: Last Data Converted */ -#define ADC10B_LCDR_DATA_MASK (0x1ff << ADC10B_LCDR_DATA_SHIFT) - -/* ADC12B Channel Data Register */ - -#define ADC12B_CDR_DATA_SHIFT (0) /* Bits 0-11: Converted Data */ -#define ADC12B_CDR_DATA_MASK (0xfff << ADC12B_CDR_DATA_SHIFT) - -/* ADC(10B) Channel Data Register */ - -#define ADC10B_CDR_DATA_SHIFT (0) /* Bits 0-9: Converted Data */ -#define ADC10B_CDR_DATA_MASK (0x1ff << ADC10B_CDR_DATA_SHIFT) - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_ADC_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_adc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_ADC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_ADC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* ADC register offsets ****************************************************************/ + +#define SAM3U_ADC_CR_OFFSET 0x00 /* Control Register (Both) */ +#define SAM3U_ADC_MR_OFFSET 0x04 /* Mode Register (Both) */ + /* 0x08: Reserved */ + /* 0x0c: Reserved */ +#define SAM3U_ADC_CHER_OFFSET 0x10 /* Channel Enable Register (Both) */ +#define SAM3U_ADC_CHDR_OFFSET 0x14 /* Channel Disable Register (Both) */ +#define SAM3U_ADC_CHSR_OFFSET 0x18 /* Channel Status Register (Both) */ +#define SAM3U_ADC_SR_OFFSET 0x1c /* Status Register (Both) */ +#define SAM3U_ADC_LCDR_OFFSET 0x20 /* Last Converted Data Register (Both) */ +#define SAM3U_ADC_IER_OFFSET 0x24 /* Interrupt Enable Register (Both) */ +#define SAM3U_ADC_IDR_OFFSET 0x28 /* Interrupt Disable Register (Both) */ +#define SAM3U_ADC_IMR_OFFSET 0x2c /* Interrupt Mask Register (Both) */ +#define SAM3U_ADC_CDR_OFFSET(n) (0x30+((n)<<2)) +#define SAM3U_ADC_CDR0_OFFSET 0x30 /* Channel Data Register 0 (Both) */ +#define SAM3U_ADC_CDR1_OFFSET 0x34 /* Channel Data Register 1 (Both) */ +#define SAM3U_ADC_CDR2_OFFSET 0x38 /* Channel Data Register 2 (Both) */ +#define SAM3U_ADC_CDR3_OFFSET 0x3c /* Channel Data Register 3 (Both) */ +#define SAM3U_ADC_CDR4_OFFSET 0x40 /* Channel Data Register 4 (Both) */ +#define SAM3U_ADC_CDR5_OFFSET 0x44 /* Channel Data Register 5 (Both) */ +#define SAM3U_ADC_CDR6_OFFSET 0x48 /* Channel Data Register 6 (Both) */ +#define SAM3U_ADC_CDR7_OFFSET 0x4c /* Channel Data Register 7 (Both) */ +#define SAM3U_ADC12B_ACR_OFFSET 0x64 /* Analog Control Register (ADC12B only) */ +#define SAM3U_ADC12B_EMR_OFFSET 0x68 /* Extended Mode Register (ADC12B only) */ + +/* ADC register adresses ***************************************************************/ + +#define SAM3U_ADC12B_CR (SAM3U_ADC12B_BASE+SAM3U_ADC_CR_OFFSET) +#define SAM3U_ADC12B_MR (SAM3U_ADC12B_BASE+SAM3U_ADC_MR_OFFSET) +#define SAM3U_ADC12B_CHER (SAM3U_ADC12B_BASE+SAM3U_ADC_CHER_OFFSET) +#define SAM3U_ADC12B_CHDR (SAM3U_ADC12B_BASE+SAM3U_ADC_CHDR_OFFSET) +#define SAM3U_ADC12B_CHSR (SAM3U_ADC12B_BASE+SAM3U_ADC_CHSR_OFFSET) +#define SAM3U_ADC12B_SR (SAM3U_ADC12B_BASE+SAM3U_ADC_SR_OFFSET) +#define SAM3U_ADC12B_LCDR_ (SAM3U_ADC12B_BASE+SAM3U_ADC_LCDR_OFFSET) +#define SAM3U_ADC12B_IER (SAM3U_ADC12B_BASE+SAM3U_ADC_IER_OFFSET) +#define SAM3U_ADC12B_IDR (SAM3U_ADC12B_BASE+SAM3U_ADC_IDR_OFFSET) +#define SAM3U_ADC12B_IMR (SAM3U_ADC12B_BASE+SAM3U_ADC_IMR_OFFSET) +#define SAM3U_ADC12B_CDR(n)) (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR_OFFSET(n)) +#define SAM3U_ADC12B_CDR0 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR0_OFFSET) +#define SAM3U_ADC12B_CDR1 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR1_OFFSET) +#define SAM3U_ADC12B_CDR2 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR2_OFFSET) +#define SAM3U_ADC12B_CDR3 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR3_OFFSET) +#define SAM3U_ADC12B_CDR4 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR4_OFFSET) +#define SAM3U_ADC12B_CDR5 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR5_OFFSET) +#define SAM3U_ADC12B_CDR6 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR6_OFFSET) +#define SAM3U_ADC12B_CDR7 (SAM3U_ADC12B_BASE+SAM3U_ADC_CDR7_OFFSET) +#define SAM3U_ADC12B_ACR (SAM3U_ADC12B_BASE+SAM3U_ADC12B_ACR_OFFSET) +#define SAM3U_ADC12B_EMR (SAM3U_ADC12B_BASE+SAM3U_ADC12B_EMR_OFFSET) + +#define SAM3U_ADC_CR (SAM3U_ADC_BASE+SAM3U_ADC_CR_OFFSET) +#define SAM3U_ADC_MR (SAM3U_ADC_BASE+SAM3U_ADC_MR_OFFSET) +#define SAM3U_ADC_CHER (SAM3U_ADC_BASE+SAM3U_ADC_CHER_OFFSET) +#define SAM3U_ADC_CHDR (SAM3U_ADC_BASE+SAM3U_ADC_CHDR_OFFSET) +#define SAM3U_ADC_CHSR (SAM3U_ADC_BASE+SAM3U_ADC_CHSR_OFFSET) +#define SAM3U_ADC_SR (SAM3U_ADC_BASE+SAM3U_ADC_SR_OFFSET) +#define SAM3U_ADC_LCDR (SAM3U_ADC_BASE+SAM3U_ADC_LCDR_OFFSET) +#define SAM3U_ADC_IER (SAM3U_ADC_BASE+SAM3U_ADC_IER_OFFSET) +#define SAM3U_ADC_IDR (SAM3U_ADC_BASE+SAM3U_ADC_IDR_OFFSET) +#define SAM3U_ADC_IMR (SAM3U_ADC_BASE+SAM3U_ADC_IMR_OFFSET) +#define SAM3U_ADC_CDR(n)) (SAM3U_ADC_BASE+SAM3U_ADC_CDR_OFFSET(n)) +#define SAM3U_ADC_CDR0 (SAM3U_ADC_BASE+SAM3U_ADC_CDR0_OFFSET) +#define SAM3U_ADC_CDR1 (SAM3U_ADC_BASE+SAM3U_ADC_CDR1_OFFSET) +#define SAM3U_ADC_CDR2 (SAM3U_ADC_BASE+SAM3U_ADC_CDR2_OFFSET) +#define SAM3U_ADC_CDR3 (SAM3U_ADC_BASE+SAM3U_ADC_CDR3_OFFSET) +#define SAM3U_ADC_CDR4 (SAM3U_ADC_BASE+SAM3U_ADC_CDR4_OFFSET) +#define SAM3U_ADC_CDR5 (SAM3U_ADC_BASE+SAM3U_ADC_CDR5_OFFSET) +#define SAM3U_ADC_CDR6 (SAM3U_ADC_BASE+SAM3U_ADC_CDR6_OFFSET) +#define SAM3U_ADC_CDR7 (SAM3U_ADC_BASE+SAM3U_ADC_CDR7_OFFSET) + +/* ADC register bit definitions ********************************************************/ + +/* ADC12B Control Register and ADC(10B) Control Register common bit-field definitions */ + +#define ADC_CR_SWRST (1 << 0) /* Bit 0: Software Reset */ +#define ADC_CR_START (1 << 1) /* Bit 1: Start Conversion */ + +/* ADC12B Mode Register and ADC(10B) Mode Register common bit-field definitions */ + +#define ADC_MR_TRGEN (1 << 0) /* Bit 0: Trigger Enable */ +#define ADC_MR_TRGSEL_SHIFT (1) /* Bits 1-3: Trigger Selection */ +#define ADC_MR_TRGSEL_MASK (7 << ADC_MR_TRGSEL_SHIFT) +#define ADC_MR_LOWRES (1 << 4) /* Bit 4: Resolution */ +#define ADC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */ +#define ADC_MR_PRESCAL_SHIFT (8) /* Bits 8-15: Prescaler Rate Selection */ +#define ADC_MR_PRESCAL_MASK (0xff << ADC_MR_PRESCAL_SHIFT) +#define ADB12B_MRSTARTUP_SHIFT (16) /* Bits 16-23: Start Up Time (ADC12B) */ +#define ADB12B_MRSTARTUP_MASK (0xff << ADB12B_MRSTARTUP_SHIFT +#define ADB10B_MRSTARTUP_SHIFT (16) /* Bits 16-22: Start Up Time (ADC10B) */ +#define ADB10B_MRSTARTUP_MASK (0x7f << ADB10B_MRSTARTUP_SHIFT) +#define ADC_MR_SHTIM_SHIFT (24) /* Bits 24-27: Sample & Hold Time */ +#define ADC_MR_SHTIM_MASK (15 << ADC_MR_SHTIM_SHIFT) + +/* ADC12B Channel Enable Register, ADC12B Channel Disable Register, ADC12B Channel + * Status Register, ADC(10B) Channel Enable Register, ADC(10B) Channel Disable Register, + * and ADC(10B) Channel Status Register common bit-field definitions + */ + +#define ADC_CH(n) (1 << (n)) +#define ADC_CH0 (1 << 0) /* Bit 0: Channel x Enable */ +#define ADC_CH1 (1 << 1) /* Bit 1: Channel x Enable */ +#define ADC_CH2 (1 << 2) /* Bit 2: Channel x Enable */ +#define ADC_CH3 (1 << 3) /* Bit 3: Channel x Enable */ +#define ADC_CH4 (1 << 4) /* Bit 4: Channel x Enable */ +#define ADC_CH5 (1 << 5) /* Bit 5: Channel x Enable */ +#define ADC_CH6 (1 << 6) /* Bit 6: Channel x Enable */ +#define ADC_CH7 (1 << 7) /* Bit 7: Channel x Enable */ + +/* ADC12B Analog Control Register (ADC12B only) */ + +#define ADC12B_ACR_GAIN_SHIFT (0) /* Bits 0-1: Input Gain */ +#define ADC12B_ACR_GAIN_MASK (3 << ADC12B_ACR_GAIN_SHIFT) +#define ADC12B_ACR_IBCTL_SHIFT (8) /* Bits 8-9: Bias Current Control */ +#define ADC12B_ACR_IBCTL_MASK (3 << ADC12B_ACR_IBCTL_SHIFT) +#define ADC12B_ACR_DIFF (1 << 16) /* Bit 16: Differential Mode */ +#define ADC12B_ACR_OFFSET (1 << 17) /* Bit 17: Input OFFSET */ + +/* ADC12B Extended Mode Register (ADC12B only) */ + +#define ADC12B_EMR_OFFMODES (1 << 0) /* Bit 0: Off Mode if Sleep Bit (ADC12B_MR) = 1 */ +#define ADC12B_EMR_OFFMSTIME_SHIFT (16) /* Bits 16-23: Startup Time */ +#define ADC12B_EMR_OFFMSTIME_MASK (0xff << ADC12B_EMR_OFFMSTIME_SHIFT) + +/* ADC12B Status Register , ADC12B Interrupt Enable Register, ADC12B Interrupt + * Disable Register, ADC12B Interrupt Mask Register, ADC(10B) Status Register, + * ADC(10B) Interrupt Enable Register, ADC(10B) Interrupt Disable Register, and + * ADC(10B) Interrupt Mask Register common bit-field definitions + */ + +#define ADC_INT_EOC(n) (1<<(n)) +#define ADC_INT_EOC0 (1 << 0) /* Bit 0: End of Conversion 0 */ +#define ADC_INT_EOC1 (1 << 1) /* Bit 1: End of Conversion 1 */ +#define ADC_INT_EOC2 (1 << 2) /* Bit 2: End of Conversion 2 */ +#define ADC_INT_EOC3 (1 << 3) /* Bit 3: End of Conversion 3 */ +#define ADC_INT_EOC4 (1 << 4) /* Bit 4: End of Conversion 4 */ +#define ADC_INT_EOC5 (1 << 5) /* Bit 5: End of Conversion 5 */ +#define ADC_INT_EOC6 (1 << 6) /* Bit 6: End of Conversion 6 */ +#define ADC_INT_EOC7 (1 << 7) /* Bit 0: End of Conversion 7 */ +#define ADC_INT_OVRE(n) (1<<((n)+8)) +#define ADC_INT_OVRE0 (1 << 8) /* Bit 8: Overrun Error 0 */ +#define ADC_INT_OVRE1 (1 << 9) /* Bit 9: Overrun Error 1 */ +#define ADC_INT_OVRE2 (1 << 10) /* Bit 10: Overrun Error 2 */ +#define ADC_INT_OVRE3 (1 << 11) /* Bit 11: Overrun Error 3 */ +#define ADC_INT_OVRE4 (1 << 12) /* Bit 12: Overrun Error 4 */ +#define ADC_INT_OVRE5 (1 << 13) /* Bit 13: Overrun Error 5 */ +#define ADC_INT_OVRE6 (1 << 14) /* Bit 14: Overrun Error 6 */ +#define ADC_INT_OVRE7 (1 << 15) /* Bit 15: Overrun Error 7 */ +#define ADC_INT_DRDY (1 << 16) /* Bit 16: Data Ready */ +#define ADC_INT_GOVRE (1 << 17) /* Bit 17: General Overrun Error */ +#define ADC_INT_ENDRX (1 << 18) /* Bit 18: End of RX Buffer */ +#define ADC_INT_RXBUFF (1 << 19) /* Bit 19: RX Buffer Full */ + +/* ADC12B Last Converted Data Register */ + +#define ADC12B_LCDR_DATA_SHIFT (0) /* Bits 0-11: Last Data Converted */ +#define ADC12B_LCDR_DATA_MASK (0xfff << ADC12B_LCDR_DATA_SHIFT) + +/* ADC(10B) Last Converted Data Register */ + +#define ADC10B_LCDR_DATA_SHIFT (0) /* Bits 0-9: Last Data Converted */ +#define ADC10B_LCDR_DATA_MASK (0x1ff << ADC10B_LCDR_DATA_SHIFT) + +/* ADC12B Channel Data Register */ + +#define ADC12B_CDR_DATA_SHIFT (0) /* Bits 0-11: Converted Data */ +#define ADC12B_CDR_DATA_MASK (0xfff << ADC12B_CDR_DATA_SHIFT) + +/* ADC(10B) Channel Data Register */ + +#define ADC10B_CDR_DATA_SHIFT (0) /* Bits 0-9: Converted Data */ +#define ADC10B_CDR_DATA_MASK (0x1ff << ADC10B_CDR_DATA_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_ADC_H */ diff --git a/arch/arm/src/sam3u/sam3u_allocateheap.c b/arch/arm/src/sam3u/sam3u_allocateheap.c index f266fd7549f4bd85523232d26cf17bff2bdd7dd1..1f4b5fdd2b5a6471bc2f57fc79570f649695430e 100644 --- a/arch/arm/src/sam3u/sam3u_allocateheap.c +++ b/arch/arm/src/sam3u/sam3u_allocateheap.c @@ -2,7 +2,7 @@ * arch/arm/src/common/sam3u_allocateheap.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/sam3u/sam3u_chipid.h b/arch/arm/src/sam3u/sam3u_chipid.h index 9ef007d2783070da8d531c634e1543a47c0a6608..03071d77aec6b89ada2aa678156fe2b14180be34 100644 --- a/arch/arm/src/sam3u/sam3u_chipid.h +++ b/arch/arm/src/sam3u/sam3u_chipid.h @@ -1,167 +1,167 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_chipid.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_CHIPID_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_CHIPID_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* CHIPID register offsets **************************************************************/ - -#define SAM3U_CHIPID_CIDR 0x00 /* Chip ID Register */ -#define SAM3U_CHIPID_EXID 0x04 /* Chip ID Extension Register */ - -/* CHIPID register adresses *************************************************************/ - -#define SAM3U_CHIPID_CIDR (SAM3U_CHIPID_BASE+SAM3U_CHIPID_CIDR) -#define SAM3U_CHIPID_EXID (SAM3U_CHIPID_BASE+SAM3U_CHIPID_EXID) - -/* CHIPID register bit definitions ******************************************************/ - -#define CHIPID_CIDR_VERSION_SHIFT (0) /* Bits 0-4: Version of the Device */ -#define CHIPID_CIDR_VERSION_MASK (0x1f << CHIPID_CIDR_VERSION_SHIFT) -#define CHIPID_CIDR_EPROC_SHIFT (5) /* Bits 5-7: Embedded Processor */ -#define CHIPID_CIDR_EPROC_MASK (7 << CHIPID_CIDR_EPROC_SHIFT) -# define CHIPID_CIDR_EPROC_ARM946ES (1 << CHIPID_CIDR_EPROC_SHIFT) /* ARM946E-S */ -# define CHIPID_CIDR_EPROC_ARM7TDMI (2 << CHIPID_CIDR_EPROC_SHIFT) /* ARM7TDMI */ -# define CHIPID_CIDR_EPROC_CORTEXM3 (3 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-M3 */ -# define CHIPID_CIDR_EPROC_ARM920T (4 << CHIPID_CIDR_EPROC_SHIFT) /* ARM920T */ -# define CHIPID_CIDR_EPROC_ARM926EJS (5 << CHIPID_CIDR_EPROC_SHIFT) /* ARM926EJ-S */ -#define CHIPID_CIDR_NVPSIZ_SHIFT (8) /* Bits 8-11: Nonvolatile Program Memory Size */ -#define CHIPID_CIDR_NVPSIZ_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT) -# define CHIPID_CIDR_NVPSIZ_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */ -# define CHIPID_CIDR_NVPSIZ_8KB (1 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 8K bytes */ -# define CHIPID_CIDR_NVPSIZ_16KB (2 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 16K bytes */ -# define CHIPID_CIDR_NVPSIZ_32KB (3 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 32K bytes */ -# define CHIPID_CIDR_NVPSIZ_64KB (5 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 64K bytes */ -# define CHIPID_CIDR_NVPSIZ_128KB (7 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 128K bytes */ -# define CHIPID_CIDR_NVPSIZ_256KB (9 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 256K bytes */ -# define CHIPID_CIDR_NVPSIZ_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */ -# define CHIPID_CIDR_NVPSIZ_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */ -# define CHIPID_CIDR_NVPSIZ_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */ -#define CHIPID_CIDR_NVPSIZ2_SHIFT (12) /* Bits 12-15: Nonvolatile Program Memory Size */ -#define CHIPID_CIDR_NVPSIZ2_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT) -# define CHIPID_CIDR_NVPSIZ2_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */ -# define CHIPID_CIDR_NVPSIZ2_8KB (1 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 8K bytes */ -# define CHIPID_CIDR_NVPSIZ2_16KB (2 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 16K bytes */ -# define CHIPID_CIDR_NVPSIZ2_32KB (3 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 32K bytes */ -# define CHIPID_CIDR_NVPSIZ2_64KB (5 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 64K bytes */ -# define CHIPID_CIDR_NVPSIZ2_128KB (7 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 128K bytes */ -# define CHIPID_CIDR_NVPSIZ2_256KB (9 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 256K bytes */ -# define CHIPID_CIDR_NVPSIZ2_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */ -# define CHIPID_CIDR_NVPSIZ2_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */ -# define CHIPID_CIDR_NVPSIZ2_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */ -#define CHIPID_CIDR_SRAMSIZ_SHIFT (16) /* Bits 16-19: Internal SRAM Size */ -#define CHIPID_CIDR_SRAMSIZ_MASK (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) -# define CHIPID_CIDR_SRAMSIZ_48KB (0 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 48K bytes */ -# define CHIPID_CIDR_SRAMSIZ_1KB (1 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 1K bytes */ -# define CHIPID_CIDR_SRAMSIZ_2KB (2 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 2K bytes */ -# define CHIPID_CIDR_SRAMSIZ_6KB (3 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 6K bytes */ -# define CHIPID_CIDR_SRAMSIZ_112KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 112K bytes */ -# define CHIPID_CIDR_SRAMSIZ_4KB (5 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 4K bytes */ -# define CHIPID_CIDR_SRAMSIZ_80KB (6 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 80K bytes */ -# define CHIPID_CIDR_SRAMSIZ_160KB (7 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 160K bytes */ -# define CHIPID_CIDR_SRAMSIZ_8KB (8 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 8K bytes */ -# define CHIPID_CIDR_SRAMSIZ_16KB (9 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 16K bytes */ -# define CHIPID_CIDR_SRAMSIZ_32KB (10 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 32K bytes */ -# define CHIPID_CIDR_SRAMSIZ_64KB (11 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 64K bytes */ -# define CHIPID_CIDR_SRAMSIZ_128KB (12 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 128K bytes */ -# define CHIPID_CIDR_SRAMSIZ_256KB (13 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 256K bytes */ -# define CHIPID_CIDR_SRAMSIZ_96KB (14 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 96K bytes */ -# define CHIPID_CIDR_SRAMSIZ_512KB (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 512K bytes */ -#define CHIPID_CIDR_ARCH_SHIFT (20) /* Bits 20-27: Architecture Identifier */ -#define CHIPID_CIDR_ARCH_MASK (0xff << CHIPID_CIDR_ARCH_SHIFT) -# define CHIPID_CIDR_ARCH_AT91SAM9XX (0x19 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM9xx Series */ -# define CHIPID_CIDR_ARCH_AT91SAM9XEXX (0x29 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM9XExx Series */ -# define CHIPID_CIDR_ARCH_AT91X34 (0x34 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x34 Series */ -# define CHIPID_CIDR_ARCH_CAP7 (0x37 << CHIPID_CIDR_ARCH_SHIFT) /* CAP7 Series */ -# define CHIPID_CIDR_ARCH_CAP9 (0x39 << CHIPID_CIDR_ARCH_SHIFT) /* CAP9 Series */ -# define CHIPID_CIDR_ARCH_CAP11 (0x3b << CHIPID_CIDR_ARCH_SHIFT) /* CAP11 Series */ -# define CHIPID_CIDR_ARCH_AT91X40 (0x40 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x40 Series */ -# define CHIPID_CIDR_ARCH_AT91X42 (0x42 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x42 Series */ -# define CHIPID_CIDR_ARCH_AT91X55 (0x55 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x55 Series */ -# define CHIPID_CIDR_ARCH_AT91SAM7AXX (0x60 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Axx Series */ -# define CHIPID_CIDR_ARCH_AT91SAM7AQXX (0x61 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7AQxx Series */ -# define CHIPID_CIDR_ARCH_AT91X63 (0x63 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x63 Series */ -# define CHIPID_CIDR_ARCH_AT91SAM7SXX (0x70 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Sxx Series */ -# define CHIPID_CIDR_ARCH_AT91SAM7XCXX (0x71 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7XCxx Series */ -# define CHIPID_CIDR_ARCH_AT91SAM7SEXX (0x72 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7SExx Series */ -# define CHIPID_CIDR_ARCH_AT91SAM7LXX (0x73 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Lxx Series */ -# define CHIPID_CIDR_ARCH_AT91SAM7XXX (0x75 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Xxx Series */ -# define CHIPID_CIDR_ARCH_AT91SAM7SLXX (0x76 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7SLxx Series */ -# define CHIPID_CIDR_ARCH_SAM3UXC (0x80 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3UxC Series (100-pin version) */ -# define CHIPID_CIDR_ARCH_SAM3UXE (0x81 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3UxE Series (144-pin version) */ -# define CHIPID_CIDR_ARCH_SAM3AXC (0x83 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3AxC Series (100-pin version) */ -# define CHIPID_CIDR_ARCH_SAM3XXC (0x84 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxC Series (100-pin version) */ -# define CHIPID_CIDR_ARCH_SAM3XXE (0x85 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxE Series (144-pin version) */ -# define CHIPID_CIDR_ARCH_SAM3XXG (0x86 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxG Series (208/217-pin version) */ -# define CHIPID_CIDR_ARCH_SAM3SXA (0x88 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxA Series (48-pin version) */ -# define CHIPID_CIDR_ARCH_SAM3SXB (0x89 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxB Series (64-pin version) */ -# define CHIPID_CIDR_ARCH_SAM3SXC (0x8a << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxC Series (100-pin version) */ -# define CHIPID_CIDR_ARCH_AT91X92 (0x92 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x92 Series */ -# define CHIPID_CIDR_ARCH_AT75CXX (0xf0 << CHIPID_CIDR_ARCH_SHIFT) /* AT75Cxx Series */ -#define CHIPID_CIDR_NVPTYP_SHIFT (28) /* Bits 28-30: Nonvolatile Program Memory Type */ -#define CHIPID_CIDR_NVPTYP_MASK (7 << CHIPID_CIDR_NVPTYP_SHIFT) -# define CHIPID_CIDR_NVPTYP ROM (0 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM */ -# define CHIPID_CIDR_NVPTYP FLASH (1 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROMless or on-chip Flash */ -# define CHIPID_CIDR_NVPTYP SRAM (4 << CHIPID_CIDR_NVPTYP_SHIFT) /* SRAM emulating ROM */ -# define CHIPID_CIDR_NVPTYP EFLASH (2 << CHIPID_CIDR_NVPTYP_SHIFT) /* Embedded Flash Memory */ -# define CHIPID_CIDR_NVPTYP REFLASH (3 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */ -#define CHIPID_CIDR_EXT (1 << 31) /* Bit 31: Extension Flag */ - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_CHIPID_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_chipid.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_CHIPID_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_CHIPID_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* CHIPID register offsets **************************************************************/ + +#define SAM3U_CHIPID_CIDR 0x00 /* Chip ID Register */ +#define SAM3U_CHIPID_EXID 0x04 /* Chip ID Extension Register */ + +/* CHIPID register adresses *************************************************************/ + +#define SAM3U_CHIPID_CIDR (SAM3U_CHIPID_BASE+SAM3U_CHIPID_CIDR) +#define SAM3U_CHIPID_EXID (SAM3U_CHIPID_BASE+SAM3U_CHIPID_EXID) + +/* CHIPID register bit definitions ******************************************************/ + +#define CHIPID_CIDR_VERSION_SHIFT (0) /* Bits 0-4: Version of the Device */ +#define CHIPID_CIDR_VERSION_MASK (0x1f << CHIPID_CIDR_VERSION_SHIFT) +#define CHIPID_CIDR_EPROC_SHIFT (5) /* Bits 5-7: Embedded Processor */ +#define CHIPID_CIDR_EPROC_MASK (7 << CHIPID_CIDR_EPROC_SHIFT) +# define CHIPID_CIDR_EPROC_ARM946ES (1 << CHIPID_CIDR_EPROC_SHIFT) /* ARM946E-S */ +# define CHIPID_CIDR_EPROC_ARM7TDMI (2 << CHIPID_CIDR_EPROC_SHIFT) /* ARM7TDMI */ +# define CHIPID_CIDR_EPROC_CORTEXM3 (3 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-M3 */ +# define CHIPID_CIDR_EPROC_ARM920T (4 << CHIPID_CIDR_EPROC_SHIFT) /* ARM920T */ +# define CHIPID_CIDR_EPROC_ARM926EJS (5 << CHIPID_CIDR_EPROC_SHIFT) /* ARM926EJ-S */ +#define CHIPID_CIDR_NVPSIZ_SHIFT (8) /* Bits 8-11: Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT) +# define CHIPID_CIDR_NVPSIZ_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */ +# define CHIPID_CIDR_NVPSIZ_8KB (1 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 8K bytes */ +# define CHIPID_CIDR_NVPSIZ_16KB (2 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 16K bytes */ +# define CHIPID_CIDR_NVPSIZ_32KB (3 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 32K bytes */ +# define CHIPID_CIDR_NVPSIZ_64KB (5 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 64K bytes */ +# define CHIPID_CIDR_NVPSIZ_128KB (7 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 128K bytes */ +# define CHIPID_CIDR_NVPSIZ_256KB (9 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 256K bytes */ +# define CHIPID_CIDR_NVPSIZ_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */ +# define CHIPID_CIDR_NVPSIZ_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */ +# define CHIPID_CIDR_NVPSIZ_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */ +#define CHIPID_CIDR_NVPSIZ2_SHIFT (12) /* Bits 12-15: Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT) +# define CHIPID_CIDR_NVPSIZ2_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */ +# define CHIPID_CIDR_NVPSIZ2_8KB (1 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 8K bytes */ +# define CHIPID_CIDR_NVPSIZ2_16KB (2 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 16K bytes */ +# define CHIPID_CIDR_NVPSIZ2_32KB (3 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 32K bytes */ +# define CHIPID_CIDR_NVPSIZ2_64KB (5 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 64K bytes */ +# define CHIPID_CIDR_NVPSIZ2_128KB (7 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 128K bytes */ +# define CHIPID_CIDR_NVPSIZ2_256KB (9 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 256K bytes */ +# define CHIPID_CIDR_NVPSIZ2_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */ +# define CHIPID_CIDR_NVPSIZ2_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */ +# define CHIPID_CIDR_NVPSIZ2_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */ +#define CHIPID_CIDR_SRAMSIZ_SHIFT (16) /* Bits 16-19: Internal SRAM Size */ +#define CHIPID_CIDR_SRAMSIZ_MASK (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) +# define CHIPID_CIDR_SRAMSIZ_48KB (0 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 48K bytes */ +# define CHIPID_CIDR_SRAMSIZ_1KB (1 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 1K bytes */ +# define CHIPID_CIDR_SRAMSIZ_2KB (2 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 2K bytes */ +# define CHIPID_CIDR_SRAMSIZ_6KB (3 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 6K bytes */ +# define CHIPID_CIDR_SRAMSIZ_112KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 112K bytes */ +# define CHIPID_CIDR_SRAMSIZ_4KB (5 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 4K bytes */ +# define CHIPID_CIDR_SRAMSIZ_80KB (6 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 80K bytes */ +# define CHIPID_CIDR_SRAMSIZ_160KB (7 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 160K bytes */ +# define CHIPID_CIDR_SRAMSIZ_8KB (8 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 8K bytes */ +# define CHIPID_CIDR_SRAMSIZ_16KB (9 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 16K bytes */ +# define CHIPID_CIDR_SRAMSIZ_32KB (10 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 32K bytes */ +# define CHIPID_CIDR_SRAMSIZ_64KB (11 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 64K bytes */ +# define CHIPID_CIDR_SRAMSIZ_128KB (12 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 128K bytes */ +# define CHIPID_CIDR_SRAMSIZ_256KB (13 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 256K bytes */ +# define CHIPID_CIDR_SRAMSIZ_96KB (14 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 96K bytes */ +# define CHIPID_CIDR_SRAMSIZ_512KB (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 512K bytes */ +#define CHIPID_CIDR_ARCH_SHIFT (20) /* Bits 20-27: Architecture Identifier */ +#define CHIPID_CIDR_ARCH_MASK (0xff << CHIPID_CIDR_ARCH_SHIFT) +# define CHIPID_CIDR_ARCH_AT91SAM9XX (0x19 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM9xx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM9XEXX (0x29 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM9XExx Series */ +# define CHIPID_CIDR_ARCH_AT91X34 (0x34 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x34 Series */ +# define CHIPID_CIDR_ARCH_CAP7 (0x37 << CHIPID_CIDR_ARCH_SHIFT) /* CAP7 Series */ +# define CHIPID_CIDR_ARCH_CAP9 (0x39 << CHIPID_CIDR_ARCH_SHIFT) /* CAP9 Series */ +# define CHIPID_CIDR_ARCH_CAP11 (0x3b << CHIPID_CIDR_ARCH_SHIFT) /* CAP11 Series */ +# define CHIPID_CIDR_ARCH_AT91X40 (0x40 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x40 Series */ +# define CHIPID_CIDR_ARCH_AT91X42 (0x42 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x42 Series */ +# define CHIPID_CIDR_ARCH_AT91X55 (0x55 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x55 Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7AXX (0x60 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Axx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7AQXX (0x61 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7AQxx Series */ +# define CHIPID_CIDR_ARCH_AT91X63 (0x63 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x63 Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7SXX (0x70 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Sxx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7XCXX (0x71 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7XCxx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7SEXX (0x72 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7SExx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7LXX (0x73 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Lxx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7XXX (0x75 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7Xxx Series */ +# define CHIPID_CIDR_ARCH_AT91SAM7SLXX (0x76 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM7SLxx Series */ +# define CHIPID_CIDR_ARCH_SAM3UXC (0x80 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3UxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3UXE (0x81 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3UxE Series (144-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3AXC (0x83 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3AxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3XXC (0x84 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3XXE (0x85 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxE Series (144-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3XXG (0x86 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3XxG Series (208/217-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3SXA (0x88 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxA Series (48-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3SXB (0x89 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxB Series (64-pin version) */ +# define CHIPID_CIDR_ARCH_SAM3SXC (0x8a << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxC Series (100-pin version) */ +# define CHIPID_CIDR_ARCH_AT91X92 (0x92 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x92 Series */ +# define CHIPID_CIDR_ARCH_AT75CXX (0xf0 << CHIPID_CIDR_ARCH_SHIFT) /* AT75Cxx Series */ +#define CHIPID_CIDR_NVPTYP_SHIFT (28) /* Bits 28-30: Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_NVPTYP_MASK (7 << CHIPID_CIDR_NVPTYP_SHIFT) +# define CHIPID_CIDR_NVPTYP ROM (0 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM */ +# define CHIPID_CIDR_NVPTYP FLASH (1 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROMless or on-chip Flash */ +# define CHIPID_CIDR_NVPTYP SRAM (4 << CHIPID_CIDR_NVPTYP_SHIFT) /* SRAM emulating ROM */ +# define CHIPID_CIDR_NVPTYP EFLASH (2 << CHIPID_CIDR_NVPTYP_SHIFT) /* Embedded Flash Memory */ +# define CHIPID_CIDR_NVPTYP REFLASH (3 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */ +#define CHIPID_CIDR_EXT (1 << 31) /* Bit 31: Extension Flag */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_CHIPID_H */ diff --git a/arch/arm/src/sam3u/sam3u_clockconfig.c b/arch/arm/src/sam3u/sam3u_clockconfig.c index 0093368e9fc6780d0b2539ce42afee17694e30fb..c9ddba9649fe369ac2b290e7b1cbdcb109ab7d30 100644 --- a/arch/arm/src/sam3u/sam3u_clockconfig.c +++ b/arch/arm/src/sam3u/sam3u_clockconfig.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/sam3u_clockconfig.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/sam3u/sam3u_dmac.c b/arch/arm/src/sam3u/sam3u_dmac.c index 8bb186e91bbc6d2ad2937ce78192de4d70ddb57f..e3958af745413ccc10a5b35fd12fe8780714ff3b 100644 --- a/arch/arm/src/sam3u/sam3u_dmac.c +++ b/arch/arm/src/sam3u/sam3u_dmac.c @@ -2,7 +2,7 @@ * arch/arm/src/sam3u-ek/sam3u_dmac.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/sam3u/sam3u_dmac.h b/arch/arm/src/sam3u/sam3u_dmac.h index 523eaf68639f21da90064db2a9efbb4f9dee4422..9edf61df74fc42dc82e5424323c69c1ce71abb9b 100644 --- a/arch/arm/src/sam3u/sam3u_dmac.h +++ b/arch/arm/src/sam3u/sam3u_dmac.h @@ -1,441 +1,441 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_dmac.h - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_DMAC_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_DMAC_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* DMAC register offsets ****************************************************************/ - -/* Global Registers */ - -#define SAM3U_DMAC_GCFG_OFFSET 0x00 /* DMAC Global Configuration Register */ -#define SAM3U_DMAC_EN_OFFSET 0x04 /* DMAC Enable Register */ -#define SAM3U_DMAC_SREQ_OFFSET 0x08 /* DMAC Software Single Request Register */ -#define SAM3U_DMAC_CREQ_OFFSET 0x0c /* DMAC Software Chunk Transfer Request Register */ -#define SAM3U_DMAC_LAST_OFFSET 0x10 /* DMAC Software Last Transfer Flag Register */ - /* 0x014-0x18: Reserved */ -#define SAM3U_DMAC_EBCIER_OFFSET 0x18 /* DMAC Error Enable */ -#define SAM3U_DMAC_EBCIDR_OFFSET 0x1C /* DMAC Error Disable */ -#define SAM3U_DMAC_EBCIMR_OFFSET 0x20 /* DMAC Error Mask */ -#define SAM3U_DMAC_EBCISR_OFFSET 0x24 /* DMAC Error Status */ -#define SAM3U_DMAC_CHER_OFFSET 0x28 /* DMAC Channel Handler Enable Register */ -#define SAM3U_DMAC_CHDR_OFFSET 0x2c /* DMAC Channel Handler Disable Register */ -#define SAM3U_DMAC_CHSR_OFFSET 0x30 /* DMAC Channel Handler Status Register */ - /* 0x034-0x38: Reserved */ -/* DMA channel registers */ - -#define SAM3U_DMACHAN_OFFSET(n) (0x3c+((n)*0x28)) -#define SAM3U_DMACHAN0_OFFSET 0x3c /* 0x3c-0x60: Channel 0 */ -#define SAM3U_DMACHAN1_OFFSET 0x64 /* 0x64-0x88: Channel 1 */ -#define SAM3U_DMACHAN2_OFFSET 0x8c /* 0x8c-0xb0: Channel 2 */ -#define SAM3U_DMACHAN3_OFFSET 0xb4 /* 0xb4-0xd8: Channel 3 */ - -#define SAM3U_DMACHAN_SADDR_OFFSET 0x00 /* DMAC Channel Source Address Register */ -#define SAM3U_DMACHAN_DADDR_OFFSET 0x04 /* DMAC Channel Destination Address Register */ -#define SAM3U_DMACHAN_DSCR_OFFSET 0x08 /* DMAC Channel Descriptor Address Register */ -#define SAM3U_DMACHAN_CTRLA_OFFSET 0x0c /* DMAC Channel Control A Register */ -#define SAM3U_DMACHAN_CTRLB_OFFSET 0x10 /* DMAC Channel Control B Register */ -#define SAM3U_DMACHAN_CFG_OFFSET 0x14 /* DMAC Channel Configuration Register */ - /* 0x18-0x24: Reserved */ - - /* 0x017c-0x1fc: Reserved */ - -/* DMAC register adresses ***************************************************************/ - -/* Global Registers */ - -#define SAM3U_DMAC_GCFG (SAM3U_DMAC_BASE+SAM3U_DMAC_GCFG_OFFSET) -#define SAM3U_DMAC_EN (SAM3U_DMAC_BASE+SAM3U_DMAC_EN_OFFSET) -#define SAM3U_DMAC_SREQ (SAM3U_DMAC_BASE+SAM3U_DMAC_SREQ_OFFSET) -#define SAM3U_DMAC_CREQ (SAM3U_DMAC_BASE+SAM3U_DMAC_CREQ_OFFSET) -#define SAM3U_DMAC_LAST (SAM3U_DMAC_BASE+SAM3U_DMAC_LAST_OFFSET) -#define SAM3U_DMAC_EBCIER (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCIER_OFFSET) -#define SAM3U_DMAC_EBCIDR (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCIDR_OFFSET) -#define SAM3U_DMAC_EBCIMR (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCIMR_OFFSET) -#define SAM3U_DMAC_EBCISR (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCISR_OFFSET) -#define SAM3U_DMAC_CHER (SAM3U_DMAC_BASE+SAM3U_DMAC_CHER_OFFSET) -#define SAM3U_DMAC_CHDR (SAM3U_DMAC_BASE+SAM3U_DMAC_CHDR_OFFSET) -#define SAM3U_DMAC_CHSR (SAM3U_DMAC_BASE+SAM3U_DMAC_CHSR_OFFSET) - -/* DMA channel registers */ - -#define SAM3U_DMACHAN_BASE(n) (SAM3U_DMAC_BASE+SAM3U_DMACHAN_OFFSET(n)) -#define SAM3U_DMACHAN0_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN0_OFFSET) -#define SAM3U_DMACHAN1_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN1_OFFSET) -#define SAM3U_DMACHAN2_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN2_OFFSET) -#define SAM3U_DMACHAN3_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN3_OFFSET) - -#define SAM3U_DMACHAN_SADDR(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_SADDR_OFFSET) -#define SAM3U_DMACHAN_DADDR(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_DADDR_OFFSET) -#define SAM3U_DMACHAN_DSCR(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_DSCR_OFFSET) -#define SAM3U_DMACHAN_CTRLA(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_CTRLA_OFFSET) -#define SAM3U_DMACHAN_CTRLB(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_CTRLB_OFFSET) -#define SAM3U_DMACHAN_CFG(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_CFG_OFFSET) - -#define SAM3U_DMACHAN0_SADDR (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_SADDR_OFFSET) -#define SAM3U_DMACHAN0_DADDR (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_DADDR_OFFSET) -#define SAM3U_DMACHAN0_DSCR (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_DSCR_OFFSET) -#define SAM3U_DMACHAN0_CTRLA (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_CTRLA_OFFSET) -#define SAM3U_DMACHAN0_CTRLB (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_CTRLB_OFFSET) -#define SAM3U_DMACHAN0_CFG (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_CFG_OFFSET) - -#define SAM3U_DMACHAN1_SADDR (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_SADDR_OFFSET) -#define SAM3U_DMACHAN1_DADDR (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_DADDR_OFFSET) -#define SAM3U_DMACHAN1_DSCR (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_DSCR_OFFSET) -#define SAM3U_DMACHAN1_CTRLA (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_CTRLA_OFFSET) -#define SAM3U_DMACHAN1_CTRLB (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_CTRLB_OFFSET) -#define SAM3U_DMACHAN1_CFG (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_CFG_OFFSET) - -#define SAM3U_DMACHAN2_SADDR (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_SADDR_OFFSET) -#define SAM3U_DMACHAN2_DADDR (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_DADDR_OFFSET) -#define SAM3U_DMACHAN2_DSCR (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_DSCR_OFFSET) -#define SAM3U_DMACHAN2_CTRLA (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_CTRLA_OFFSET) -#define SAM3U_DMACHAN2_CTRLB (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_CTRLB_OFFSET) -#define SAM3U_DMACHAN2_CFG (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_CFG_OFFSET) - -#define SAM3U_DMACHAN3_SADDR (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_SADDR_OFFSET) -#define SAM3U_DMACHAN3_DADDR (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_DADDR_OFFSET) -#define SAM3U_DMACHAN3_DSCR (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_DSCR_OFFSET) -#define SAM3U_DMACHAN3_CTRLA (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_CTRLA_OFFSET) -#define SAM3U_DMACHAN3_CTRLB (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_CTRLB_OFFSET) -#define SAM3U_DMACHAN3_CFG (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_CFG_OFFSET) - -/* DMAC register bit definitions ********************************************************/ - -/* Global Registers */ - -/* DMAC Global Configuration Register */ - -#define DMAC_GCFG_ARB_CFG (1 << 4) /* Bit 4: Round robin (vs fixed) arbiter */ - -/* DMAC Enable Register */ - -#define DMAC_EN_ENABLE (1 << 0) /* Bit 0: DMA controller enable */ - -/* DMAC Software Single Request Register */ - -#define DMAC_SREQ_SHIFT(n) ((n)<<1) -#define DMAC_SREQ_MASK(n) (3 << DMAC_SREQ_SHIFT(n)) -#define DMAC_SREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */ -#define DMAC_SREQ0_MASK (3 << DMAC_SREQ0_SHIFT) -#define DMAC_SREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */ -#define DMAC_SREQ1_MASK (3 << DMAC_SREQ1_SHIFT) -#define DMAC_SREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */ -#define DMAC_SREQ2_MASK (3 << DMAC_SREQ2_SHIFT) -#define DMAC_SREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */ -#define DMAC_SREQ3_MASK (3 << DMAC_SREQ3_SHIFT) - -#define DMAC_SREQ_SSREQ_SHIFT (0) /* Bits 0, 2, 4, 6: Request a source single transfer */ -# define DMAC_SREQ_SSREQ(n) (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ_SHIFT(n))) -# define DMAC_SREQ_SSREQ0 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ0_SHIFT) -# define DMAC_SREQ_SSREQ1 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ1_SHIFT) -# define DMAC_SREQ_SSREQ2 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ2_SHIFT) -# define DMAC_SREQ_SSREQ3 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ3_SHIFT) -#define DMAC_SREQ_DSREQ_SHIFT (1) /* Bits 1, 3, 5, 7: Request a destination single transfer */ -# define DMAC_SREQ_DSREQ(n) (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ_SHIFT(n)))) -# define DMAC_SREQ_DSREQ0 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ0_SHIFT) -# define DMAC_SREQ_DSREQ1 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ1_SHIFT) -# define DMAC_SREQ_DSREQ2 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ2_SHIFT) -# define DMAC_SREQ_DSREQ3 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ3_SHIFT) - -/* DMAC Software Chunk Transfer Request Register */ - -#define DMAC_CREQ_SHIFT(n) ((n)<<1) -#define DMAC_CREQ_MASK(n) (3 << DMAC_CREQ_SHIFT(n)) -#define DMAC_CREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */ -#define DMAC_CREQ0_MASK (3 << DMAC_CREQ0_SHIFT) -#define DMAC_CREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */ -#define DMAC_CREQ1_MASK (3 << DMAC_CREQ1_SHIFT) -#define DMAC_CREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */ -#define DMAC_CREQ2_MASK (3 << DMAC_CREQ2_SHIFT) -#define DMAC_CREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */ -#define DMAC_CREQ3_MASK (3 << DMAC_CREQ3_SHIFT) - -#define DMAC_CREQ_SCREQ_SHIFT (0) /* Bits 0, 2, 4, 6: Request a source chunk transfer */ -# define DMAC_CREQ_SCREQ(n) (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ_SHIFT(n))) -# define DMAC_CREQ_SCREQ0 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ0_SHIFT) -# define DMAC_CREQ_SCREQ1 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ1_SHIFT) -# define DMAC_CREQ_SCREQ2 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ2_SHIFT) -# define DMAC_CREQ_SCREQ3 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ3_SHIFT) -#define DMAC_CREQ_DCREQ_SHIFT (1) /* Bits 1, 3, 5, 7: Request a destination chunk transfer */ -# define DMAC_CREQ_DCREQ(n) (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ_SHIFT(n)))) -# define DMAC_CREQ_DCREQ0 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ0_SHIFT) -# define DMAC_CREQ_DCREQ1 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ1_SHIFT) -# define DMAC_CREQ_DCREQ2 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ2_SHIFT) -# define DMAC_CREQ_DCREQ3 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ3_SHIFT) - -/* DMAC Software Last Transfer Flag Register */ - -#define DMAC_LAST_SHIFT(n) ((n)<<1) -#define DMAC_LAST_MASK(n) (3 << DMAC_LAST_SHIFT(n)) -#define DMAC_LAST0_SHIFT (0) /* Bits 0-1: Channel 0 */ -#define DMAC_LAST0_MASK (3 << DMAC_LAST0_SHIFT) -#define DMAC_LAST1_SHIFT (2) /* Bits 2-3: Channel 1 */ -#define DMAC_LAST1_MASK (3 << DMAC_LAST1_SHIFT) -#define DMAC_LAST2_SHIFT (4) /* Bits 4-5: Channel 2 */ -#define DMAC_LAST2_MASK (3 << DMAC_LAST2_SHIFT) -#define DMAC_LAST3_SHIFT (6) /* Bits 6-7: Channel 3 */ -#define DMAC_LAST3_MASK (3 << DMAC_LAST3_SHIFT) - -#define DMAC_LAST_SLAST_SHIFT (0) /* Bits 0, 2, 4, 6: Indicates the last transfer */ -# define DMAC_LAST_SLAST(n) (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST_SHIFT(n))) -# define DMAC_LAST_SLAST0 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST0_SHIFT) -# define DMAC_LAST_SLAST1 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST1_SHIFT) -# define DMAC_LAST_SLAST2 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST2_SHIFT) -# define DMAC_LAST_SLAST3 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST3_SHIFT) -#define DMAC_LAST_DLAST_SHIFT (1) /* Bits 1, 3, 5, 7: Indicates the last transfer */ -# define DMAC_LAST_DLAST(n) (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST_SHIFT(n)))) -# define DMAC_LAST_DLAST0 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST0_SHIFT) -# define DMAC_LAST_DLAST1 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST1_SHIFT) -# define DMAC_LAST_DLAST2 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST2_SHIFT) -# define DMAC_LAST_DLAST3 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST3_SHIFT) - -/* DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register, - * DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register, - * DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register, and - * DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register common - * bit field definitions - */ - -#define DMAC_EBC_BTC_SHIFT (0) /* Bits 0-3: Buffer Transfer Completed Interrupt Enable */ -#define DMAC_EBC_BTC_MASK (15 << DMAC_EBC_BTC_SHIFT) -# define DMAC_EBC_BTC(n) (1 << (DMAC_EBC_BTC_SHIFT+(n))) -# define DMAC_EBC_BTC0 (1 << (DMAC_EBC_BTC_SHIFT+0)) -# define DMAC_EBC_BTC1 (1 << (DMAC_EBC_BTC_SHIFT+1)) -# define DMAC_EBC_BTC2 (1 << (DMAC_EBC_BTC_SHIFT+2)) -# define DMAC_EBC_BTC3 (1 << (DMAC_EBC_BTC_SHIFT+3)) -#define DMAC_EBC_CBTC_SHIFT (8) /* Bits 8-11: Chained Buffer Transfer Completed Interrupt Enable */ -#define DMAC_EBC_CBTC_MASK (15 << DMAC_EBC_CBTC_SHIFT) -# define DMAC_EBC_CBTC(n) (1 << (DMAC_EBC_CBTC_SHIFT+(n))) -# define DMAC_EBC_CBTC0 (1 << (DMAC_EBC_CBTC_SHIFT+0)) -# define DMAC_EBC_CBTC1 (1 << (DMAC_EBC_CBTC_SHIFT+1)) -# define DMAC_EBC_CBTC2 (1 << (DMAC_EBC_CBTC_SHIFT+2)) -# define DMAC_EBC_CBTC3 (1 << (DMAC_EBC_CBTC_SHIFT+3)) -#define DMAC_EBC_ERR_SHIFT (16) /* Bits 16-19: Access Error Interrupt Enable */ -#define DMAC_EBC_ERR_MASK (15 << DMAC_EBC_ERR_SHIFT) -# define DMAC_EBC_ERR(n) (1 << (DMAC_EBC_ERR_SHIFT+(n))) -# define DMAC_EBC_ERR0 (1 << (DMAC_EBC_ERR_SHIFT+0)) -# define DMAC_EBC_ERR1 (1 << (DMAC_EBC_ERR_SHIFT+1)) -# define DMAC_EBC_ERR2 (1 << (DMAC_EBC_ERR_SHIFT+2)) -# define DMAC_EBC_ERR3 (1 << (DMAC_EBC_ERR_SHIFT+3)) - -#define DMAC_EBC_BTCINTS(n) (0x00010001 << (n)) /* BTC + ERR interrupts */ -#define DMAC_EBC_CBTCINTS(n) (0x00010100 << (n)) /* CBT + ERR interrupts */ -#define DMAC_EBC_CHANINTS(n) (0x00010101 << (n)) /* All channel interrupts */ -#define DMAC_EBC_ALLINTS (0x000f0f0f) /* All interrupts */ - -/* DMAC Channel Handler Enable Register */ - -#define DMAC_CHER_ENA_SHIFT (0) /* Bits 0-3: Enable channel */ -#define DMAC_CHER_ENA_MASK (15 << DMAC_CHER_ENA_SHIFT) -# define DMAC_CHER_ENA(n) (1 << (DMAC_CHER_ENA_SHIFT+(n))) -# define DMAC_CHER_ENA0 (1 << (DMAC_CHER_ENA_SHIFT+0)) -# define DMAC_CHER_ENA1 (1 << (DMAC_CHER_ENA_SHIFT+1)) -# define DMAC_CHER_ENA2 (1 << (DMAC_CHER_ENA_SHIFT+2)) -# define DMAC_CHER_ENA3 (1 << (DMAC_CHER_ENA_SHIFT+3)) -#define DMAC_CHER_SUSP_SHIFT (8) /* Bits 8-11: Freeze channel and its context */ -#define DMAC_CHER_SUSP_MASK (15 << DMAC_CHER_SUSP_SHIFT) -# define DMAC_CHER_SUSP(n) (1 << (DMAC_CHER_SUSP_SHIFT+(n))) -# define DMAC_CHER_SUSP0 (1 << (DMAC_CHER_SUSP_SHIFT+0)) -# define DMAC_CHER_SUSP1 (1 << (DMAC_CHER_SUSP_SHIFT+1)) -# define DMAC_CHER_SUSP2 (1 << (DMAC_CHER_SUSP_SHIFT+2)) -# define DMAC_CHER_SUSP3 (1 << (DMAC_CHER_SUSP_SHIFT+3)) -#define DMAC_CHER_KEEP_SHIFT (24) /* Bits 24-27: Resume channel from automatic stall */ -#define DMAC_CHER_KEEP_MASK (15 << DMAC_CHER_KEEP_SHIFT) -# define DMAC_CHER_KEEP(n) (1 << (DMAC_CHER_KEEP_SHIFT+(n))) -# define DMAC_CHER_KEEP0 (1 << (DMAC_CHER_KEEP_SHIFT+0)) -# define DMAC_CHER_KEEP1 (1 << (DMAC_CHER_KEEP_SHIFT+1)) -# define DMAC_CHER_KEEP2 (1 << (DMAC_CHER_KEEP_SHIFT+2)) -# define DMAC_CHER_KEEP3 (1 << (DMAC_CHER_KEEP_SHIFT+3)) - -/* DMAC Channel Handler Disable Register */ - -#define DMAC_CHDR_DIS_SHIFT (0) /* Bits 0-3: Disable DMAC channel */ -#define DMAC_CHDR_DIS_MASK (15 << DMAC_CHDR_DIS_SHIFT) -# define DMAC_CHDR_DIS(n) (1 << (DMAC_CHDR_DIS_SHIFT+(n))) -# define DMAC_CHDR_DIS0 (1 << (DMAC_CHDR_DIS_SHIFT+0)) -# define DMAC_CHDR_DIS1 (1 << (DMAC_CHDR_DIS_SHIFT+1)) -# define DMAC_CHDR_DIS2 (1 << (DMAC_CHDR_DIS_SHIFT+2)) -# define DMAC_CHDR_DIS3 (1 << (DMAC_CHDR_DIS_SHIFT+3)) -# define DMAC_CHDR_DIS_ALL DMAC_CHDR_DIS_MASK -#define DMAC_CHDR_RES_SHIFT (8) /* Bits 8-11: Resume trasnfer, restoring context */ -#define DMAC_CHDR_RES_MASK (15 << DMAC_CHDR_RES_SHIFT) -# define DMAC_CHDR_RES(n) (1 << (DMAC_CHDR_RES_SHIFT+(n))) -# define DMAC_CHDR_RES0 (1 << (DMAC_CHDR_RES_SHIFT+0)) -# define DMAC_CHDR_RES1 (1 << (DMAC_CHDR_RES_SHIFT+1)) -# define DMAC_CHDR_RES2 (1 << (DMAC_CHDR_RES_SHIFT+2)) -# define DMAC_CHDR_RES3 (1 << (DMAC_CHDR_RES_SHIFT+3)) - -/* DMAC Channel Handler Status Register */ - -#define DMAC_CHSR_ENA_SHIFT (0) /* Bits 0-3: Indicates that the channel is stalling */ -#define DMAC_CHSR_ENA_MASK (15 << DMAC_CHSR_ENA_SHIFT) -# define DMAC_CHSR_ENA(n) (1 << (DMAC_CHSR_ENA_SHIFT+(n))) -# define DMAC_CHSR_ENA0 (1 << (DMAC_CHSR_ENA_SHIFT+0)) -# define DMAC_CHSR_ENA1 (1 << (DMAC_CHSR_ENA_SHIFT+1)) -# define DMAC_CHSR_ENA2 (1 << (DMAC_CHSR_ENA_SHIFT+2)) -# define DMAC_CHSR_ENA3 (1 << (DMAC_CHSR_ENA_SHIFT+3)) -#define DMAC_CHSR_SUSP_SHIFT (8) /* Bits 8-11: Indicates that the channel is empty */ -#define DMAC_CHSR_SUSP_MASK (15 << DMAC_CHSR_SUSP_SHIFT) -# define DMAC_CHSR_SUSP(n) (1 << (DMAC_CHSR_SUSP_SHIFT+(n))) -# define DMAC_CHSR_SUSP0 (1 << (DMAC_CHSR_SUSP_SHIFT+0)) -# define DMAC_CHSR_SUSP1 (1 << (DMAC_CHSR_SUSP_SHIFT+1)) -# define DMAC_CHSR_SUSP2 (1 << (DMAC_CHSR_SUSP_SHIFT+2)) -# define DMAC_CHSR_SUSP3 (1 << (DMAC_CHSR_SUSP_SHIFT+3)) -#define DMAC_CHSR_EMPT_SHIFT (16) /* Bits 16-19: Access Error Interrupt Enable */ -#define DMAC_CHSR_EMPT_MASK (15 << DMAC_CHSR_EMPT_SHIFT) -# define DMAC_CHSR_EMPT(n) (1 << (DMAC_CHSR_EMPT_SHIFT+(n))) -# define DMAC_CHSR_EMPT0 (1 << (DMAC_CHSR_EMPT_SHIFT+0)) -# define DMAC_CHSR_EMPT1 (1 << (DMAC_CHSR_EMPT_SHIFT+1)) -# define DMAC_CHSR_EMPT2 (1 << (DMAC_CHSR_EMPT_SHIFT+2)) -# define DMAC_CHSR_EMPT3 (1 << (DMAC_CHSR_EMPT_SHIFT+3)) -#define DMAC_CHSR_STAL_SHIFT (24) /* Bits 24-27: Access Error Interrupt Enable */ -#define DMAC_CHSR_STAL_MASK (15 << DMAC_CHSR_STAL_SHIFT) -# define DMAC_CHSR_STAL(n) (1 << (DMAC_CHSR_STAL_SHIFT+(n))) -# define DMAC_CHSR_STAL0 (1 << (DMAC_CHSR_STAL_SHIFT+0)) -# define DMAC_CHSR_STAL1 (1 << (DMAC_CHSR_STAL_SHIFT+1)) -# define DMAC_CHSR_STAL2 (1 << (DMAC_CHSR_STAL_SHIFT+2)) -# define DMAC_CHSR_STAL3 (1 << (DMAC_CHSR_STAL_SHIFT+3)) - -/* DMA channel registers */ -/* DMAC Channel n [n = 0..3] Control A Register */ - -#define DMACHAN_CTRLA_BTSIZE_MAX (0xfff) -#define DMACHAN_CTRLA_BTSIZE_SHIFT (0) /* Bits 0-11: Buffer Transfer Size */ -#define DMACHAN_CTRLA_BTSIZE_MASK (DMACHAN_CTRLA_BTSIZE_MAX << DMACHAN_CTRLA_BTSIZE_SHIFT) -#define DMACHAN_CTRLA_SCSIZE (1 << 16) /* Bit 16: Source Chunk Transfer Size */ -# define DMACHAN_CTRLA_SCSIZE_1 (0) -# define DMACHAN_CTRLA_SCSIZE_4 DMACHAN_CTRLA_SCSIZE -#define DMACHAN_CTRLA_DCSIZE (1 << 20) /* Bit 20: Destination Chunk Transfer size */ -# define DMACHAN_CTRLA_DCSIZE_1 (0) -# define DMACHAN_CTRLA_DCSIZE_4 DMACHAN_CTRLA_DCSIZE -#define DMACHAN_CTRLA_SRCWIDTH_SHIFT (24) /* Bits 24-25 */ -#define DMACHAN_CTRLA_SRCWIDTH_MASK (3 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) -# define DMACHAN_CTRLA_SRCWIDTH_BYTE (0 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) -# define DMACHAN_CTRLA_SRCWIDTH_HWORD (1 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) -# define DMACHAN_CTRLA_SRCWIDTH_WORD (2 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) -#define DMACHAN_CTRLA_DSTWIDTH_SHIFT (28) /* Bits 28-29 */ -#define DMACHAN_CTRLA_DSTWIDTH_MASK (3 << DMACHAN_CTRLA_DSTWIDTH_SHIFT) -# define DMACHAN_CTRLA_DSTWIDTH_BYTE (0 << DMACHAN_CTRLA_DSTWIDTH_SHIFT) -# define DMACHAN_CTRLA_DSTWIDTH_HWORD (1 << DMACHAN_CTRLA_DSTWIDTH_SHIFT) -# define DMACHAN_CTRLA_DSTWIDTH_WORD (2 << DMACHAN_CTRLA_DSTWIDTH_SHIFT) -#define DMACHAN_CTRLA_DONE (1 << 31) /* Bit 31: Auto disable DMAC */ - -/* DMAC Channel n [n = 0..3] Control B Register */ - -#define DMACHAN_CTRLB_SRCDSCR (1 << 16) /* Bit 16: Source buffer descriptor fetch operation disabled */ -#define DMACHAN_CTRLB_DSTDSCR (1 << 20) /* Bit 20: Dest buffer descriptor fetch operation disabled */ -#define DMACHAN_CTRLB_FC_SHIFT (21) /* Bits 21-22: Flow controller */ -#define DMACHAN_CTRLB_FC_MASK (3 << DMACHAN_CTRLB_FC_SHIFT) -# define DMACHAN_CTRLB_FC_M2M (0 << DMACHAN_CTRLB_FC_SHIFT) /* Memory-to-Memory */ -# define DMACHAN_CTRLB_FC_M2P (1 << DMACHAN_CTRLB_FC_SHIFT) /* Memory-to-Peripheral */ -# define DMACHAN_CTRLB_FC_P2M (2 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Memory */ -# define DMACHAN_CTRLB_FC_P2P (3 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Peripheral */ -#define DMACHAN_CTRLB_SRCINCR_SHIFT (24) /* Bits 24-25 */ -#define DMACHAN_CTRLB_SRCINCR_MASK (3 << DMACHAN_CTRLB_SRCINCR_SHIFT) -# define DMACHAN_CTRLB_SRCINCR_INCR (0 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Incrementing address */ -# define DMACHAN_CTRLB_SRCINCR_FIXED (2 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Fixed address */ -#define DMACHAN_CTRLB_DSTINCR_SHIFT (28) /* Bits 28-29 */ -#define DMACHAN_CTRLB_DSTINCR_MASK (3 << DMACHAN_CTRLB_DSTINCR_SHIFT) -# define DMACHAN_CTRLB_DSTINCR_INCR (0 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Incrementing address */ -# define DMACHAN_CTRLB_DSTINCR_FIXED (2 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Fixed address */ -#define DMACHAN_CTRLB_IEN (1 << 30) /* Bit 30: Clear sets BTC[n] flag in EBCISR */ - -/* DMAC Channel n [n = 0..3] Configuration Register */ - -#define DMACHAN_CFG_SRCPER_SHIFT (0) /* Bits 0-3: Channel source associated with peripheral ID */ -#define DMACHAN_CFG_SRCPER_MASK (15 << DMACHAN_CFG_SRCPER_SHIFT) -#define DMACHAN_CFG_DSTPER_SHIFT (4) /* Bits 4-7: Channel dest associated with peripheral ID */ -#define DMACHAN_CFG_DSTPER_MASK (15 << DMACHAN_CFG_DSTPER_SHIFT) -#define DMACHAN_CFG_SRCH2SEL (1 << 9) /* Bit 9: HW handshake triggers transfer */ -#define DMACHAN_CFG_DSTH2SEL (1 << 13) /* Bit 13: HW handshake trigger transfer */ -#define DMACHAN_CFG_SOD (1 << 16) /* Bit 16: Stop on done */ -#define DMACHAN_CFG_LOCKIF (1 << 20) /* Bit 20: Enable lock interface capability */ -#define DMACHAN_CFG_LOCKB (1 << 21) /* Bit 21: Enable AHB Bus Locking capability */ -#define DMACHAN_CFG_LOCKIFL (1 << 22) /* Bit 22: Lock Master Interface Arbiter */ -#define DMACHAN_CFG_AHBPRO_SHIFT (24) /* Bits 24-26: Bus access privilege */ -#define DMACHAN_CFG_AHBPRO_MASK (7 << DMACHAN_CFG_AHBPRO_SHIFT) -# define DMACHAN_CFG_AHBPRO_PRIV (1 << DMACHAN_CFG_AHBPRO_SHIFT) -# define DMACHAN_CFG_AHBPRO_BUFF (2 << DMACHAN_CFG_AHBPRO_SHIFT) -# define DMACHAN_CFG_AHBPRO_CACHE (4 << DMACHAN_CFG_AHBPRO_SHIFT) -#define DMACHAN_CFG_FIFOCFG_SHIFT (28) /* Bits 28-29 */ -#define DMACHAN_CFG_FIFOCFG_MASK (3 << DMACHAN_CFG_FIFOCFG_SHIFT) -# define DMACHAN_CFG_FIFOCFG_LARGEST (0 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Largest length AHB burst */ -# define DMACHAN_CFG_FIFOCFG_HALF (1 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Half FIFO size */ -# define DMACHAN_CFG_FIFOCFG_SINGLE (2 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Single AHB access */ - -/* DMA Peripheral IDs *******************************************************************/ - -#define DMACHAN_PID_MCI0 0 -#define DMACHAN_PID_SSC 3 -#define DMACHAN_PID_MCI1 13 - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/* DMA multi buffer transfer link list entry structure */ - -struct dma_linklist_s -{ - uint32_t src; /* Source address */ - uint32_t dest; /* Destination address */ - uint32_t ctrla; /* Control A value */ - uint32_t ctrlb; /* Control B value */ - uint32_t next; /* Next descriptor address */ -}; - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_DMAC_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_dmac.h + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_DMAC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_DMAC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* DMAC register offsets ****************************************************************/ + +/* Global Registers */ + +#define SAM3U_DMAC_GCFG_OFFSET 0x00 /* DMAC Global Configuration Register */ +#define SAM3U_DMAC_EN_OFFSET 0x04 /* DMAC Enable Register */ +#define SAM3U_DMAC_SREQ_OFFSET 0x08 /* DMAC Software Single Request Register */ +#define SAM3U_DMAC_CREQ_OFFSET 0x0c /* DMAC Software Chunk Transfer Request Register */ +#define SAM3U_DMAC_LAST_OFFSET 0x10 /* DMAC Software Last Transfer Flag Register */ + /* 0x014-0x18: Reserved */ +#define SAM3U_DMAC_EBCIER_OFFSET 0x18 /* DMAC Error Enable */ +#define SAM3U_DMAC_EBCIDR_OFFSET 0x1C /* DMAC Error Disable */ +#define SAM3U_DMAC_EBCIMR_OFFSET 0x20 /* DMAC Error Mask */ +#define SAM3U_DMAC_EBCISR_OFFSET 0x24 /* DMAC Error Status */ +#define SAM3U_DMAC_CHER_OFFSET 0x28 /* DMAC Channel Handler Enable Register */ +#define SAM3U_DMAC_CHDR_OFFSET 0x2c /* DMAC Channel Handler Disable Register */ +#define SAM3U_DMAC_CHSR_OFFSET 0x30 /* DMAC Channel Handler Status Register */ + /* 0x034-0x38: Reserved */ +/* DMA channel registers */ + +#define SAM3U_DMACHAN_OFFSET(n) (0x3c+((n)*0x28)) +#define SAM3U_DMACHAN0_OFFSET 0x3c /* 0x3c-0x60: Channel 0 */ +#define SAM3U_DMACHAN1_OFFSET 0x64 /* 0x64-0x88: Channel 1 */ +#define SAM3U_DMACHAN2_OFFSET 0x8c /* 0x8c-0xb0: Channel 2 */ +#define SAM3U_DMACHAN3_OFFSET 0xb4 /* 0xb4-0xd8: Channel 3 */ + +#define SAM3U_DMACHAN_SADDR_OFFSET 0x00 /* DMAC Channel Source Address Register */ +#define SAM3U_DMACHAN_DADDR_OFFSET 0x04 /* DMAC Channel Destination Address Register */ +#define SAM3U_DMACHAN_DSCR_OFFSET 0x08 /* DMAC Channel Descriptor Address Register */ +#define SAM3U_DMACHAN_CTRLA_OFFSET 0x0c /* DMAC Channel Control A Register */ +#define SAM3U_DMACHAN_CTRLB_OFFSET 0x10 /* DMAC Channel Control B Register */ +#define SAM3U_DMACHAN_CFG_OFFSET 0x14 /* DMAC Channel Configuration Register */ + /* 0x18-0x24: Reserved */ + + /* 0x017c-0x1fc: Reserved */ + +/* DMAC register adresses ***************************************************************/ + +/* Global Registers */ + +#define SAM3U_DMAC_GCFG (SAM3U_DMAC_BASE+SAM3U_DMAC_GCFG_OFFSET) +#define SAM3U_DMAC_EN (SAM3U_DMAC_BASE+SAM3U_DMAC_EN_OFFSET) +#define SAM3U_DMAC_SREQ (SAM3U_DMAC_BASE+SAM3U_DMAC_SREQ_OFFSET) +#define SAM3U_DMAC_CREQ (SAM3U_DMAC_BASE+SAM3U_DMAC_CREQ_OFFSET) +#define SAM3U_DMAC_LAST (SAM3U_DMAC_BASE+SAM3U_DMAC_LAST_OFFSET) +#define SAM3U_DMAC_EBCIER (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCIER_OFFSET) +#define SAM3U_DMAC_EBCIDR (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCIDR_OFFSET) +#define SAM3U_DMAC_EBCIMR (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCIMR_OFFSET) +#define SAM3U_DMAC_EBCISR (SAM3U_DMAC_BASE+SAM3U_DMAC_EBCISR_OFFSET) +#define SAM3U_DMAC_CHER (SAM3U_DMAC_BASE+SAM3U_DMAC_CHER_OFFSET) +#define SAM3U_DMAC_CHDR (SAM3U_DMAC_BASE+SAM3U_DMAC_CHDR_OFFSET) +#define SAM3U_DMAC_CHSR (SAM3U_DMAC_BASE+SAM3U_DMAC_CHSR_OFFSET) + +/* DMA channel registers */ + +#define SAM3U_DMACHAN_BASE(n) (SAM3U_DMAC_BASE+SAM3U_DMACHAN_OFFSET(n)) +#define SAM3U_DMACHAN0_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN0_OFFSET) +#define SAM3U_DMACHAN1_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN1_OFFSET) +#define SAM3U_DMACHAN2_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN2_OFFSET) +#define SAM3U_DMACHAN3_BASE (SAM3U_DMAC_BASE+SAM3U_DMACHAN3_OFFSET) + +#define SAM3U_DMACHAN_SADDR(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_SADDR_OFFSET) +#define SAM3U_DMACHAN_DADDR(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_DADDR_OFFSET) +#define SAM3U_DMACHAN_DSCR(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_DSCR_OFFSET) +#define SAM3U_DMACHAN_CTRLA(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_CTRLA_OFFSET) +#define SAM3U_DMACHAN_CTRLB(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_CTRLB_OFFSET) +#define SAM3U_DMACHAN_CFG(n) (SAM3U_DMACHAN_BASE(n)+SAM3U_DMACHAN_CFG_OFFSET) + +#define SAM3U_DMACHAN0_SADDR (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_SADDR_OFFSET) +#define SAM3U_DMACHAN0_DADDR (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_DADDR_OFFSET) +#define SAM3U_DMACHAN0_DSCR (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_DSCR_OFFSET) +#define SAM3U_DMACHAN0_CTRLA (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_CTRLA_OFFSET) +#define SAM3U_DMACHAN0_CTRLB (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_CTRLB_OFFSET) +#define SAM3U_DMACHAN0_CFG (SAM3U_DMACHAN0_BASE+SAM3U_DMACHAN_CFG_OFFSET) + +#define SAM3U_DMACHAN1_SADDR (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_SADDR_OFFSET) +#define SAM3U_DMACHAN1_DADDR (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_DADDR_OFFSET) +#define SAM3U_DMACHAN1_DSCR (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_DSCR_OFFSET) +#define SAM3U_DMACHAN1_CTRLA (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_CTRLA_OFFSET) +#define SAM3U_DMACHAN1_CTRLB (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_CTRLB_OFFSET) +#define SAM3U_DMACHAN1_CFG (SAM3U_DMACHAN1_BASE+SAM3U_DMACHAN_CFG_OFFSET) + +#define SAM3U_DMACHAN2_SADDR (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_SADDR_OFFSET) +#define SAM3U_DMACHAN2_DADDR (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_DADDR_OFFSET) +#define SAM3U_DMACHAN2_DSCR (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_DSCR_OFFSET) +#define SAM3U_DMACHAN2_CTRLA (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_CTRLA_OFFSET) +#define SAM3U_DMACHAN2_CTRLB (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_CTRLB_OFFSET) +#define SAM3U_DMACHAN2_CFG (SAM3U_DMACHAN2_BASE+SAM3U_DMACHAN_CFG_OFFSET) + +#define SAM3U_DMACHAN3_SADDR (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_SADDR_OFFSET) +#define SAM3U_DMACHAN3_DADDR (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_DADDR_OFFSET) +#define SAM3U_DMACHAN3_DSCR (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_DSCR_OFFSET) +#define SAM3U_DMACHAN3_CTRLA (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_CTRLA_OFFSET) +#define SAM3U_DMACHAN3_CTRLB (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_CTRLB_OFFSET) +#define SAM3U_DMACHAN3_CFG (SAM3U_DMACHAN3_BASE+SAM3U_DMACHAN_CFG_OFFSET) + +/* DMAC register bit definitions ********************************************************/ + +/* Global Registers */ + +/* DMAC Global Configuration Register */ + +#define DMAC_GCFG_ARB_CFG (1 << 4) /* Bit 4: Round robin (vs fixed) arbiter */ + +/* DMAC Enable Register */ + +#define DMAC_EN_ENABLE (1 << 0) /* Bit 0: DMA controller enable */ + +/* DMAC Software Single Request Register */ + +#define DMAC_SREQ_SHIFT(n) ((n)<<1) +#define DMAC_SREQ_MASK(n) (3 << DMAC_SREQ_SHIFT(n)) +#define DMAC_SREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */ +#define DMAC_SREQ0_MASK (3 << DMAC_SREQ0_SHIFT) +#define DMAC_SREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */ +#define DMAC_SREQ1_MASK (3 << DMAC_SREQ1_SHIFT) +#define DMAC_SREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */ +#define DMAC_SREQ2_MASK (3 << DMAC_SREQ2_SHIFT) +#define DMAC_SREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */ +#define DMAC_SREQ3_MASK (3 << DMAC_SREQ3_SHIFT) + +#define DMAC_SREQ_SSREQ_SHIFT (0) /* Bits 0, 2, 4, 6: Request a source single transfer */ +# define DMAC_SREQ_SSREQ(n) (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ_SHIFT(n))) +# define DMAC_SREQ_SSREQ0 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ0_SHIFT) +# define DMAC_SREQ_SSREQ1 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ1_SHIFT) +# define DMAC_SREQ_SSREQ2 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ2_SHIFT) +# define DMAC_SREQ_SSREQ3 (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ3_SHIFT) +#define DMAC_SREQ_DSREQ_SHIFT (1) /* Bits 1, 3, 5, 7: Request a destination single transfer */ +# define DMAC_SREQ_DSREQ(n) (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ_SHIFT(n)))) +# define DMAC_SREQ_DSREQ0 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ0_SHIFT) +# define DMAC_SREQ_DSREQ1 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ1_SHIFT) +# define DMAC_SREQ_DSREQ2 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ2_SHIFT) +# define DMAC_SREQ_DSREQ3 (1 << (DMAC_SREQ_DSREQ_SHIFT+DMAC_SREQ3_SHIFT) + +/* DMAC Software Chunk Transfer Request Register */ + +#define DMAC_CREQ_SHIFT(n) ((n)<<1) +#define DMAC_CREQ_MASK(n) (3 << DMAC_CREQ_SHIFT(n)) +#define DMAC_CREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */ +#define DMAC_CREQ0_MASK (3 << DMAC_CREQ0_SHIFT) +#define DMAC_CREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */ +#define DMAC_CREQ1_MASK (3 << DMAC_CREQ1_SHIFT) +#define DMAC_CREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */ +#define DMAC_CREQ2_MASK (3 << DMAC_CREQ2_SHIFT) +#define DMAC_CREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */ +#define DMAC_CREQ3_MASK (3 << DMAC_CREQ3_SHIFT) + +#define DMAC_CREQ_SCREQ_SHIFT (0) /* Bits 0, 2, 4, 6: Request a source chunk transfer */ +# define DMAC_CREQ_SCREQ(n) (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ_SHIFT(n))) +# define DMAC_CREQ_SCREQ0 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ0_SHIFT) +# define DMAC_CREQ_SCREQ1 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ1_SHIFT) +# define DMAC_CREQ_SCREQ2 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ2_SHIFT) +# define DMAC_CREQ_SCREQ3 (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ3_SHIFT) +#define DMAC_CREQ_DCREQ_SHIFT (1) /* Bits 1, 3, 5, 7: Request a destination chunk transfer */ +# define DMAC_CREQ_DCREQ(n) (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ_SHIFT(n)))) +# define DMAC_CREQ_DCREQ0 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ0_SHIFT) +# define DMAC_CREQ_DCREQ1 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ1_SHIFT) +# define DMAC_CREQ_DCREQ2 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ2_SHIFT) +# define DMAC_CREQ_DCREQ3 (1 << (DMAC_CREQ_DCREQ_SHIFT+DMAC_CREQ3_SHIFT) + +/* DMAC Software Last Transfer Flag Register */ + +#define DMAC_LAST_SHIFT(n) ((n)<<1) +#define DMAC_LAST_MASK(n) (3 << DMAC_LAST_SHIFT(n)) +#define DMAC_LAST0_SHIFT (0) /* Bits 0-1: Channel 0 */ +#define DMAC_LAST0_MASK (3 << DMAC_LAST0_SHIFT) +#define DMAC_LAST1_SHIFT (2) /* Bits 2-3: Channel 1 */ +#define DMAC_LAST1_MASK (3 << DMAC_LAST1_SHIFT) +#define DMAC_LAST2_SHIFT (4) /* Bits 4-5: Channel 2 */ +#define DMAC_LAST2_MASK (3 << DMAC_LAST2_SHIFT) +#define DMAC_LAST3_SHIFT (6) /* Bits 6-7: Channel 3 */ +#define DMAC_LAST3_MASK (3 << DMAC_LAST3_SHIFT) + +#define DMAC_LAST_SLAST_SHIFT (0) /* Bits 0, 2, 4, 6: Indicates the last transfer */ +# define DMAC_LAST_SLAST(n) (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST_SHIFT(n))) +# define DMAC_LAST_SLAST0 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST0_SHIFT) +# define DMAC_LAST_SLAST1 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST1_SHIFT) +# define DMAC_LAST_SLAST2 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST2_SHIFT) +# define DMAC_LAST_SLAST3 (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST3_SHIFT) +#define DMAC_LAST_DLAST_SHIFT (1) /* Bits 1, 3, 5, 7: Indicates the last transfer */ +# define DMAC_LAST_DLAST(n) (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST_SHIFT(n)))) +# define DMAC_LAST_DLAST0 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST0_SHIFT) +# define DMAC_LAST_DLAST1 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST1_SHIFT) +# define DMAC_LAST_DLAST2 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST2_SHIFT) +# define DMAC_LAST_DLAST3 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST3_SHIFT) + +/* DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register, + * DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register, + * DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register, and + * DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register common + * bit field definitions + */ + +#define DMAC_EBC_BTC_SHIFT (0) /* Bits 0-3: Buffer Transfer Completed Interrupt Enable */ +#define DMAC_EBC_BTC_MASK (15 << DMAC_EBC_BTC_SHIFT) +# define DMAC_EBC_BTC(n) (1 << (DMAC_EBC_BTC_SHIFT+(n))) +# define DMAC_EBC_BTC0 (1 << (DMAC_EBC_BTC_SHIFT+0)) +# define DMAC_EBC_BTC1 (1 << (DMAC_EBC_BTC_SHIFT+1)) +# define DMAC_EBC_BTC2 (1 << (DMAC_EBC_BTC_SHIFT+2)) +# define DMAC_EBC_BTC3 (1 << (DMAC_EBC_BTC_SHIFT+3)) +#define DMAC_EBC_CBTC_SHIFT (8) /* Bits 8-11: Chained Buffer Transfer Completed Interrupt Enable */ +#define DMAC_EBC_CBTC_MASK (15 << DMAC_EBC_CBTC_SHIFT) +# define DMAC_EBC_CBTC(n) (1 << (DMAC_EBC_CBTC_SHIFT+(n))) +# define DMAC_EBC_CBTC0 (1 << (DMAC_EBC_CBTC_SHIFT+0)) +# define DMAC_EBC_CBTC1 (1 << (DMAC_EBC_CBTC_SHIFT+1)) +# define DMAC_EBC_CBTC2 (1 << (DMAC_EBC_CBTC_SHIFT+2)) +# define DMAC_EBC_CBTC3 (1 << (DMAC_EBC_CBTC_SHIFT+3)) +#define DMAC_EBC_ERR_SHIFT (16) /* Bits 16-19: Access Error Interrupt Enable */ +#define DMAC_EBC_ERR_MASK (15 << DMAC_EBC_ERR_SHIFT) +# define DMAC_EBC_ERR(n) (1 << (DMAC_EBC_ERR_SHIFT+(n))) +# define DMAC_EBC_ERR0 (1 << (DMAC_EBC_ERR_SHIFT+0)) +# define DMAC_EBC_ERR1 (1 << (DMAC_EBC_ERR_SHIFT+1)) +# define DMAC_EBC_ERR2 (1 << (DMAC_EBC_ERR_SHIFT+2)) +# define DMAC_EBC_ERR3 (1 << (DMAC_EBC_ERR_SHIFT+3)) + +#define DMAC_EBC_BTCINTS(n) (0x00010001 << (n)) /* BTC + ERR interrupts */ +#define DMAC_EBC_CBTCINTS(n) (0x00010100 << (n)) /* CBT + ERR interrupts */ +#define DMAC_EBC_CHANINTS(n) (0x00010101 << (n)) /* All channel interrupts */ +#define DMAC_EBC_ALLINTS (0x000f0f0f) /* All interrupts */ + +/* DMAC Channel Handler Enable Register */ + +#define DMAC_CHER_ENA_SHIFT (0) /* Bits 0-3: Enable channel */ +#define DMAC_CHER_ENA_MASK (15 << DMAC_CHER_ENA_SHIFT) +# define DMAC_CHER_ENA(n) (1 << (DMAC_CHER_ENA_SHIFT+(n))) +# define DMAC_CHER_ENA0 (1 << (DMAC_CHER_ENA_SHIFT+0)) +# define DMAC_CHER_ENA1 (1 << (DMAC_CHER_ENA_SHIFT+1)) +# define DMAC_CHER_ENA2 (1 << (DMAC_CHER_ENA_SHIFT+2)) +# define DMAC_CHER_ENA3 (1 << (DMAC_CHER_ENA_SHIFT+3)) +#define DMAC_CHER_SUSP_SHIFT (8) /* Bits 8-11: Freeze channel and its context */ +#define DMAC_CHER_SUSP_MASK (15 << DMAC_CHER_SUSP_SHIFT) +# define DMAC_CHER_SUSP(n) (1 << (DMAC_CHER_SUSP_SHIFT+(n))) +# define DMAC_CHER_SUSP0 (1 << (DMAC_CHER_SUSP_SHIFT+0)) +# define DMAC_CHER_SUSP1 (1 << (DMAC_CHER_SUSP_SHIFT+1)) +# define DMAC_CHER_SUSP2 (1 << (DMAC_CHER_SUSP_SHIFT+2)) +# define DMAC_CHER_SUSP3 (1 << (DMAC_CHER_SUSP_SHIFT+3)) +#define DMAC_CHER_KEEP_SHIFT (24) /* Bits 24-27: Resume channel from automatic stall */ +#define DMAC_CHER_KEEP_MASK (15 << DMAC_CHER_KEEP_SHIFT) +# define DMAC_CHER_KEEP(n) (1 << (DMAC_CHER_KEEP_SHIFT+(n))) +# define DMAC_CHER_KEEP0 (1 << (DMAC_CHER_KEEP_SHIFT+0)) +# define DMAC_CHER_KEEP1 (1 << (DMAC_CHER_KEEP_SHIFT+1)) +# define DMAC_CHER_KEEP2 (1 << (DMAC_CHER_KEEP_SHIFT+2)) +# define DMAC_CHER_KEEP3 (1 << (DMAC_CHER_KEEP_SHIFT+3)) + +/* DMAC Channel Handler Disable Register */ + +#define DMAC_CHDR_DIS_SHIFT (0) /* Bits 0-3: Disable DMAC channel */ +#define DMAC_CHDR_DIS_MASK (15 << DMAC_CHDR_DIS_SHIFT) +# define DMAC_CHDR_DIS(n) (1 << (DMAC_CHDR_DIS_SHIFT+(n))) +# define DMAC_CHDR_DIS0 (1 << (DMAC_CHDR_DIS_SHIFT+0)) +# define DMAC_CHDR_DIS1 (1 << (DMAC_CHDR_DIS_SHIFT+1)) +# define DMAC_CHDR_DIS2 (1 << (DMAC_CHDR_DIS_SHIFT+2)) +# define DMAC_CHDR_DIS3 (1 << (DMAC_CHDR_DIS_SHIFT+3)) +# define DMAC_CHDR_DIS_ALL DMAC_CHDR_DIS_MASK +#define DMAC_CHDR_RES_SHIFT (8) /* Bits 8-11: Resume trasnfer, restoring context */ +#define DMAC_CHDR_RES_MASK (15 << DMAC_CHDR_RES_SHIFT) +# define DMAC_CHDR_RES(n) (1 << (DMAC_CHDR_RES_SHIFT+(n))) +# define DMAC_CHDR_RES0 (1 << (DMAC_CHDR_RES_SHIFT+0)) +# define DMAC_CHDR_RES1 (1 << (DMAC_CHDR_RES_SHIFT+1)) +# define DMAC_CHDR_RES2 (1 << (DMAC_CHDR_RES_SHIFT+2)) +# define DMAC_CHDR_RES3 (1 << (DMAC_CHDR_RES_SHIFT+3)) + +/* DMAC Channel Handler Status Register */ + +#define DMAC_CHSR_ENA_SHIFT (0) /* Bits 0-3: Indicates that the channel is stalling */ +#define DMAC_CHSR_ENA_MASK (15 << DMAC_CHSR_ENA_SHIFT) +# define DMAC_CHSR_ENA(n) (1 << (DMAC_CHSR_ENA_SHIFT+(n))) +# define DMAC_CHSR_ENA0 (1 << (DMAC_CHSR_ENA_SHIFT+0)) +# define DMAC_CHSR_ENA1 (1 << (DMAC_CHSR_ENA_SHIFT+1)) +# define DMAC_CHSR_ENA2 (1 << (DMAC_CHSR_ENA_SHIFT+2)) +# define DMAC_CHSR_ENA3 (1 << (DMAC_CHSR_ENA_SHIFT+3)) +#define DMAC_CHSR_SUSP_SHIFT (8) /* Bits 8-11: Indicates that the channel is empty */ +#define DMAC_CHSR_SUSP_MASK (15 << DMAC_CHSR_SUSP_SHIFT) +# define DMAC_CHSR_SUSP(n) (1 << (DMAC_CHSR_SUSP_SHIFT+(n))) +# define DMAC_CHSR_SUSP0 (1 << (DMAC_CHSR_SUSP_SHIFT+0)) +# define DMAC_CHSR_SUSP1 (1 << (DMAC_CHSR_SUSP_SHIFT+1)) +# define DMAC_CHSR_SUSP2 (1 << (DMAC_CHSR_SUSP_SHIFT+2)) +# define DMAC_CHSR_SUSP3 (1 << (DMAC_CHSR_SUSP_SHIFT+3)) +#define DMAC_CHSR_EMPT_SHIFT (16) /* Bits 16-19: Access Error Interrupt Enable */ +#define DMAC_CHSR_EMPT_MASK (15 << DMAC_CHSR_EMPT_SHIFT) +# define DMAC_CHSR_EMPT(n) (1 << (DMAC_CHSR_EMPT_SHIFT+(n))) +# define DMAC_CHSR_EMPT0 (1 << (DMAC_CHSR_EMPT_SHIFT+0)) +# define DMAC_CHSR_EMPT1 (1 << (DMAC_CHSR_EMPT_SHIFT+1)) +# define DMAC_CHSR_EMPT2 (1 << (DMAC_CHSR_EMPT_SHIFT+2)) +# define DMAC_CHSR_EMPT3 (1 << (DMAC_CHSR_EMPT_SHIFT+3)) +#define DMAC_CHSR_STAL_SHIFT (24) /* Bits 24-27: Access Error Interrupt Enable */ +#define DMAC_CHSR_STAL_MASK (15 << DMAC_CHSR_STAL_SHIFT) +# define DMAC_CHSR_STAL(n) (1 << (DMAC_CHSR_STAL_SHIFT+(n))) +# define DMAC_CHSR_STAL0 (1 << (DMAC_CHSR_STAL_SHIFT+0)) +# define DMAC_CHSR_STAL1 (1 << (DMAC_CHSR_STAL_SHIFT+1)) +# define DMAC_CHSR_STAL2 (1 << (DMAC_CHSR_STAL_SHIFT+2)) +# define DMAC_CHSR_STAL3 (1 << (DMAC_CHSR_STAL_SHIFT+3)) + +/* DMA channel registers */ +/* DMAC Channel n [n = 0..3] Control A Register */ + +#define DMACHAN_CTRLA_BTSIZE_MAX (0xfff) +#define DMACHAN_CTRLA_BTSIZE_SHIFT (0) /* Bits 0-11: Buffer Transfer Size */ +#define DMACHAN_CTRLA_BTSIZE_MASK (DMACHAN_CTRLA_BTSIZE_MAX << DMACHAN_CTRLA_BTSIZE_SHIFT) +#define DMACHAN_CTRLA_SCSIZE (1 << 16) /* Bit 16: Source Chunk Transfer Size */ +# define DMACHAN_CTRLA_SCSIZE_1 (0) +# define DMACHAN_CTRLA_SCSIZE_4 DMACHAN_CTRLA_SCSIZE +#define DMACHAN_CTRLA_DCSIZE (1 << 20) /* Bit 20: Destination Chunk Transfer size */ +# define DMACHAN_CTRLA_DCSIZE_1 (0) +# define DMACHAN_CTRLA_DCSIZE_4 DMACHAN_CTRLA_DCSIZE +#define DMACHAN_CTRLA_SRCWIDTH_SHIFT (24) /* Bits 24-25 */ +#define DMACHAN_CTRLA_SRCWIDTH_MASK (3 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) +# define DMACHAN_CTRLA_SRCWIDTH_BYTE (0 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) +# define DMACHAN_CTRLA_SRCWIDTH_HWORD (1 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) +# define DMACHAN_CTRLA_SRCWIDTH_WORD (2 << DMACHAN_CTRLA_SRCWIDTH_SHIFT) +#define DMACHAN_CTRLA_DSTWIDTH_SHIFT (28) /* Bits 28-29 */ +#define DMACHAN_CTRLA_DSTWIDTH_MASK (3 << DMACHAN_CTRLA_DSTWIDTH_SHIFT) +# define DMACHAN_CTRLA_DSTWIDTH_BYTE (0 << DMACHAN_CTRLA_DSTWIDTH_SHIFT) +# define DMACHAN_CTRLA_DSTWIDTH_HWORD (1 << DMACHAN_CTRLA_DSTWIDTH_SHIFT) +# define DMACHAN_CTRLA_DSTWIDTH_WORD (2 << DMACHAN_CTRLA_DSTWIDTH_SHIFT) +#define DMACHAN_CTRLA_DONE (1 << 31) /* Bit 31: Auto disable DMAC */ + +/* DMAC Channel n [n = 0..3] Control B Register */ + +#define DMACHAN_CTRLB_SRCDSCR (1 << 16) /* Bit 16: Source buffer descriptor fetch operation disabled */ +#define DMACHAN_CTRLB_DSTDSCR (1 << 20) /* Bit 20: Dest buffer descriptor fetch operation disabled */ +#define DMACHAN_CTRLB_FC_SHIFT (21) /* Bits 21-22: Flow controller */ +#define DMACHAN_CTRLB_FC_MASK (3 << DMACHAN_CTRLB_FC_SHIFT) +# define DMACHAN_CTRLB_FC_M2M (0 << DMACHAN_CTRLB_FC_SHIFT) /* Memory-to-Memory */ +# define DMACHAN_CTRLB_FC_M2P (1 << DMACHAN_CTRLB_FC_SHIFT) /* Memory-to-Peripheral */ +# define DMACHAN_CTRLB_FC_P2M (2 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Memory */ +# define DMACHAN_CTRLB_FC_P2P (3 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Peripheral */ +#define DMACHAN_CTRLB_SRCINCR_SHIFT (24) /* Bits 24-25 */ +#define DMACHAN_CTRLB_SRCINCR_MASK (3 << DMACHAN_CTRLB_SRCINCR_SHIFT) +# define DMACHAN_CTRLB_SRCINCR_INCR (0 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Incrementing address */ +# define DMACHAN_CTRLB_SRCINCR_FIXED (2 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Fixed address */ +#define DMACHAN_CTRLB_DSTINCR_SHIFT (28) /* Bits 28-29 */ +#define DMACHAN_CTRLB_DSTINCR_MASK (3 << DMACHAN_CTRLB_DSTINCR_SHIFT) +# define DMACHAN_CTRLB_DSTINCR_INCR (0 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Incrementing address */ +# define DMACHAN_CTRLB_DSTINCR_FIXED (2 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Fixed address */ +#define DMACHAN_CTRLB_IEN (1 << 30) /* Bit 30: Clear sets BTC[n] flag in EBCISR */ + +/* DMAC Channel n [n = 0..3] Configuration Register */ + +#define DMACHAN_CFG_SRCPER_SHIFT (0) /* Bits 0-3: Channel source associated with peripheral ID */ +#define DMACHAN_CFG_SRCPER_MASK (15 << DMACHAN_CFG_SRCPER_SHIFT) +#define DMACHAN_CFG_DSTPER_SHIFT (4) /* Bits 4-7: Channel dest associated with peripheral ID */ +#define DMACHAN_CFG_DSTPER_MASK (15 << DMACHAN_CFG_DSTPER_SHIFT) +#define DMACHAN_CFG_SRCH2SEL (1 << 9) /* Bit 9: HW handshake triggers transfer */ +#define DMACHAN_CFG_DSTH2SEL (1 << 13) /* Bit 13: HW handshake trigger transfer */ +#define DMACHAN_CFG_SOD (1 << 16) /* Bit 16: Stop on done */ +#define DMACHAN_CFG_LOCKIF (1 << 20) /* Bit 20: Enable lock interface capability */ +#define DMACHAN_CFG_LOCKB (1 << 21) /* Bit 21: Enable AHB Bus Locking capability */ +#define DMACHAN_CFG_LOCKIFL (1 << 22) /* Bit 22: Lock Master Interface Arbiter */ +#define DMACHAN_CFG_AHBPRO_SHIFT (24) /* Bits 24-26: Bus access privilege */ +#define DMACHAN_CFG_AHBPRO_MASK (7 << DMACHAN_CFG_AHBPRO_SHIFT) +# define DMACHAN_CFG_AHBPRO_PRIV (1 << DMACHAN_CFG_AHBPRO_SHIFT) +# define DMACHAN_CFG_AHBPRO_BUFF (2 << DMACHAN_CFG_AHBPRO_SHIFT) +# define DMACHAN_CFG_AHBPRO_CACHE (4 << DMACHAN_CFG_AHBPRO_SHIFT) +#define DMACHAN_CFG_FIFOCFG_SHIFT (28) /* Bits 28-29 */ +#define DMACHAN_CFG_FIFOCFG_MASK (3 << DMACHAN_CFG_FIFOCFG_SHIFT) +# define DMACHAN_CFG_FIFOCFG_LARGEST (0 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Largest length AHB burst */ +# define DMACHAN_CFG_FIFOCFG_HALF (1 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Half FIFO size */ +# define DMACHAN_CFG_FIFOCFG_SINGLE (2 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Single AHB access */ + +/* DMA Peripheral IDs *******************************************************************/ + +#define DMACHAN_PID_MCI0 0 +#define DMACHAN_PID_SSC 3 +#define DMACHAN_PID_MCI1 13 + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/* DMA multi buffer transfer link list entry structure */ + +struct dma_linklist_s +{ + uint32_t src; /* Source address */ + uint32_t dest; /* Destination address */ + uint32_t ctrla; /* Control A value */ + uint32_t ctrlb; /* Control B value */ + uint32_t next; /* Next descriptor address */ +}; + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_DMAC_H */ diff --git a/arch/arm/src/sam3u/sam3u_eefc.h b/arch/arm/src/sam3u/sam3u_eefc.h index ed88a0134fafb99454e944f6ce3119a0fc0f83cc..d32c6670b7968d54c64337f7a9572a23f9c4fb96 100644 --- a/arch/arm/src/sam3u/sam3u_eefc.h +++ b/arch/arm/src/sam3u/sam3u_eefc.h @@ -1,120 +1,120 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_eefc.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* EEFC register offsets ****************************************************************/ - -#define SAM3U_EEFC_FMR_OFFSET 0x00 /* EEFC Flash Mode Register */ -#define SAM3U_EEFC_FCR_OFFSET 0x04 /* EEFC Flash Command Register */ -#define SAM3U_EEFC_FSR_OFFSET 0x08 /* EEFC Flash Status Register */ -#define SAM3U_EEFC_FRR_OFFSET 0x0c /* EEFC Flash Result Register */ - -/* EEFC register adresses ***************************************************************/ - -#define SAM3U_EEFC_FMR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FMR_OFFSET) -#define SAM3U_EEFC_FCR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FCR_OFFSET) -#define SAM3U_EEFC_FSR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FSR_OFFSET) -#define SAM3U_EEFC_FRR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FRR_OFFSET) - -#define SAM3U_EEFC0_FMR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FMR_OFFSET) -#define SAM3U_EEFC0_FCR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FCR_OFFSET) -#define SAM3U_EEFC0_FSR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FSR_OFFSET) -#define SAM3U_EEFC0_FRR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FRR_OFFSET) - -#define SAM3U_EEFC1_FMR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FMR_OFFSET) -#define SAM3U_EEFC1_FCR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FCR_OFFSET) -#define SAM3U_EEFC1_FSR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FSR_OFFSET) -#define SAM3U_EEFC1_FRR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FRR_OFFSET) - -/* EEFC register bit definitions ********************************************************/ - -#define EEFC_FMR_FRDY (1 << 0) /* Bit 0: Ready Interrupt Enable */ -#define EEFC_FMR_FWS_SHIFT (8) /* Bits 8-11: Flash Wait State */ -#define EEFC_FMR_FWS_MASK (15 << EEFC_FMR_FWS_SHIFT) -#define EEFC_FMR_FAM (1 << 24) /* Bit 24: Flash Access Mode */ - -#define EEFC_FCR_FCMD_SHIFT (0) /* Bits 0-7: Flash Command */ -#define EEFC_FCR_FCMD_MASK (0xff << EEFC_FCR_FCMD_SHIFT) -# define EEFC_FCR_FCMD_GETD (0 << EEFC_FCR_FCMD_SHIFT) /* Get Flash Descriptor */ -# define EEFC_FCR_FCMD_WP (1 << EEFC_FCR_FCMD_SHIFT) /* Write page */ -# define EEFC_FCR_FCMD_WPL (2 << EEFC_FCR_FCMD_SHIFT) /* Write page and lock */ -# define EEFC_FCR_FCMD_EWP (3 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page */ -# define EEFC_FCR_FCMD_EWPL (4 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page then lock */ -# define EEFC_FCR_FCMD_EA (5 << EEFC_FCR_FCMD_SHIFT) /* Erase all */ -# define EEFC_FCR_FCMD_SLB (8 << EEFC_FCR_FCMD_SHIFT) /* Set Lock Bit */ -# define EEFC_FCR_FCMD_CLB (9 << EEFC_FCR_FCMD_SHIFT) /* Clear Lock Bit */ -# define EEFC_FCR_FCMD_GLB (10 << EEFC_FCR_FCMD_SHIFT) /* Get Lock Bit */ -# define EEFC_FCR_FCMD_SGPB (11 << EEFC_FCR_FCMD_SHIFT) /* Set GPNVM Bit */ -# define EEFC_FCR_FCMD_CGPB (12 << EEFC_FCR_FCMD_SHIFT) /* Clear GPNVM Bit */ -# define EEFC_FCR_FCMD_GGPB (13 << EEFC_FCR_FCMD_SHIFT) /* Get GPNVM Bit */ -# define EEFC_FCR_FCMD_STUI (14 << EEFC_FCR_FCMD_SHIFT) /* Start Read Unique Identifier */ -# define EEFC_FCR_FCMD_SPUI (15 << EEFC_FCR_FCMD_SHIFT) /* Stop Read Unique Identifier */ -#define EEFC_FCR_FARG_SHIFT (8) /* Bits 8-23: Flash Command Argument */ -#define EEFC_FCR_FARG_MASK (0xffff << EEFC_FCR_FARG_SHIFT) -#define EEFC_FCR_FKEY_SHIFT (24) /* Bits 24-31: Flash Writing Protection Key */ -#define EEFC_FCR_FKEY__MASK (0xff << EEFC_FCR_FKEY_SHIFT) - -#define EEFC_FSR_FRDY (1 << 0) /* Bit 0: Flash Ready Status */ -#define EEFC_FSR_FCMDE (1 << 1) /* Bit 1: Flash Command Error Status */ -#define EEFC_FSR_FLOCKE (1 << 2) /* Bit 2: Flash Lock Error Status */ - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_eefc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* EEFC register offsets ****************************************************************/ + +#define SAM3U_EEFC_FMR_OFFSET 0x00 /* EEFC Flash Mode Register */ +#define SAM3U_EEFC_FCR_OFFSET 0x04 /* EEFC Flash Command Register */ +#define SAM3U_EEFC_FSR_OFFSET 0x08 /* EEFC Flash Status Register */ +#define SAM3U_EEFC_FRR_OFFSET 0x0c /* EEFC Flash Result Register */ + +/* EEFC register adresses ***************************************************************/ + +#define SAM3U_EEFC_FMR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FMR_OFFSET) +#define SAM3U_EEFC_FCR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FCR_OFFSET) +#define SAM3U_EEFC_FSR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FSR_OFFSET) +#define SAM3U_EEFC_FRR(n) (SAM3U_EEFCN_BASE(n)+SAM3U_EEFC_FRR_OFFSET) + +#define SAM3U_EEFC0_FMR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FMR_OFFSET) +#define SAM3U_EEFC0_FCR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FCR_OFFSET) +#define SAM3U_EEFC0_FSR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FSR_OFFSET) +#define SAM3U_EEFC0_FRR (SAM3U_EEFC0_BASE+SAM3U_EEFC_FRR_OFFSET) + +#define SAM3U_EEFC1_FMR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FMR_OFFSET) +#define SAM3U_EEFC1_FCR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FCR_OFFSET) +#define SAM3U_EEFC1_FSR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FSR_OFFSET) +#define SAM3U_EEFC1_FRR (SAM3U_EEFC1_BASE+SAM3U_EEFC_FRR_OFFSET) + +/* EEFC register bit definitions ********************************************************/ + +#define EEFC_FMR_FRDY (1 << 0) /* Bit 0: Ready Interrupt Enable */ +#define EEFC_FMR_FWS_SHIFT (8) /* Bits 8-11: Flash Wait State */ +#define EEFC_FMR_FWS_MASK (15 << EEFC_FMR_FWS_SHIFT) +#define EEFC_FMR_FAM (1 << 24) /* Bit 24: Flash Access Mode */ + +#define EEFC_FCR_FCMD_SHIFT (0) /* Bits 0-7: Flash Command */ +#define EEFC_FCR_FCMD_MASK (0xff << EEFC_FCR_FCMD_SHIFT) +# define EEFC_FCR_FCMD_GETD (0 << EEFC_FCR_FCMD_SHIFT) /* Get Flash Descriptor */ +# define EEFC_FCR_FCMD_WP (1 << EEFC_FCR_FCMD_SHIFT) /* Write page */ +# define EEFC_FCR_FCMD_WPL (2 << EEFC_FCR_FCMD_SHIFT) /* Write page and lock */ +# define EEFC_FCR_FCMD_EWP (3 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page */ +# define EEFC_FCR_FCMD_EWPL (4 << EEFC_FCR_FCMD_SHIFT) /* Erase page and write page then lock */ +# define EEFC_FCR_FCMD_EA (5 << EEFC_FCR_FCMD_SHIFT) /* Erase all */ +# define EEFC_FCR_FCMD_SLB (8 << EEFC_FCR_FCMD_SHIFT) /* Set Lock Bit */ +# define EEFC_FCR_FCMD_CLB (9 << EEFC_FCR_FCMD_SHIFT) /* Clear Lock Bit */ +# define EEFC_FCR_FCMD_GLB (10 << EEFC_FCR_FCMD_SHIFT) /* Get Lock Bit */ +# define EEFC_FCR_FCMD_SGPB (11 << EEFC_FCR_FCMD_SHIFT) /* Set GPNVM Bit */ +# define EEFC_FCR_FCMD_CGPB (12 << EEFC_FCR_FCMD_SHIFT) /* Clear GPNVM Bit */ +# define EEFC_FCR_FCMD_GGPB (13 << EEFC_FCR_FCMD_SHIFT) /* Get GPNVM Bit */ +# define EEFC_FCR_FCMD_STUI (14 << EEFC_FCR_FCMD_SHIFT) /* Start Read Unique Identifier */ +# define EEFC_FCR_FCMD_SPUI (15 << EEFC_FCR_FCMD_SHIFT) /* Stop Read Unique Identifier */ +#define EEFC_FCR_FARG_SHIFT (8) /* Bits 8-23: Flash Command Argument */ +#define EEFC_FCR_FARG_MASK (0xffff << EEFC_FCR_FARG_SHIFT) +#define EEFC_FCR_FKEY_SHIFT (24) /* Bits 24-31: Flash Writing Protection Key */ +#define EEFC_FCR_FKEY__MASK (0xff << EEFC_FCR_FKEY_SHIFT) + +#define EEFC_FSR_FRDY (1 << 0) /* Bit 0: Flash Ready Status */ +#define EEFC_FSR_FCMDE (1 << 1) /* Bit 1: Flash Command Error Status */ +#define EEFC_FSR_FLOCKE (1 << 2) /* Bit 2: Flash Lock Error Status */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_EEFC_H */ diff --git a/arch/arm/src/sam3u/sam3u_gpbr.h b/arch/arm/src/sam3u/sam3u_gpbr.h index e3ac0c12812516d5ef07d8bcae93037fb4e9119f..7e9853180bcf44e272261c677ef717299be7b36a 100644 --- a/arch/arm/src/sam3u/sam3u_gpbr.h +++ b/arch/arm/src/sam3u/sam3u_gpbr.h @@ -1,90 +1,90 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_gpbr.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* GPBR register offsets ****************************************************************/ - -#define SAM3U_GPBR_OFFSET(n) ((n)<<2) /* General purpose back-up registers */ -#define SAM3U_GPBR0_OFFSET 0x00 -#define SAM3U_GPBR1_OFFSET 0x04 -#define SAM3U_GPBR2_OFFSET 0x08 -#define SAM3U_GPBR3_OFFSET 0x0c -#define SAM3U_GPBR4_OFFSET 0x10 -#define SAM3U_GPBR5_OFFSET 0x14 -#define SAM3U_GPBR6_OFFSET 0x18 -#define SAM3U_GPBR7_OFFSET 0x1c - -/* GPBR register adresses ***************************************************************/ - -#define SAM3U_GPBR(n)) (SAM3U_GPBR_BASE+SAM3U_GPBR_OFFSET(n)) -#define SAM3U_GPBR0 (SAM3U_GPBR_BASE+SAM3U_GPBR0_OFFSET) -#define SAM3U_GPBR1 (SAM3U_GPBR_BASE+SAM3U_GPBR1_OFFSET) -#define SAM3U_GPBR2 (SAM3U_GPBR_BASE+SAM3U_GPBR2_OFFSET) -#define SAM3U_GPBR3 (SAM3U_GPBR_BASE+SAM3U_GPBR3_OFFSET) -#define SAM3U_GPBR4 (SAM3U_GPBR_BASE+SAM3U_GPBR4_OFFSET) -#define SAM3U_GPBR5 (SAM3U_GPBR_BASE+SAM3U_GPBR5_OFFSET) -#define SAM3U_GPBR6 (SAM3U_GPBR_BASE+SAM3U_GPBR6_OFFSET) -#define SAM3U_GPBR7 (SAM3U_GPBR_BASE+SAM3U_GPBR7_OFFSET) - -/* GPBR register bit definitions ********************************************************/ - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_gpbr.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* GPBR register offsets ****************************************************************/ + +#define SAM3U_GPBR_OFFSET(n) ((n)<<2) /* General purpose back-up registers */ +#define SAM3U_GPBR0_OFFSET 0x00 +#define SAM3U_GPBR1_OFFSET 0x04 +#define SAM3U_GPBR2_OFFSET 0x08 +#define SAM3U_GPBR3_OFFSET 0x0c +#define SAM3U_GPBR4_OFFSET 0x10 +#define SAM3U_GPBR5_OFFSET 0x14 +#define SAM3U_GPBR6_OFFSET 0x18 +#define SAM3U_GPBR7_OFFSET 0x1c + +/* GPBR register adresses ***************************************************************/ + +#define SAM3U_GPBR(n)) (SAM3U_GPBR_BASE+SAM3U_GPBR_OFFSET(n)) +#define SAM3U_GPBR0 (SAM3U_GPBR_BASE+SAM3U_GPBR0_OFFSET) +#define SAM3U_GPBR1 (SAM3U_GPBR_BASE+SAM3U_GPBR1_OFFSET) +#define SAM3U_GPBR2 (SAM3U_GPBR_BASE+SAM3U_GPBR2_OFFSET) +#define SAM3U_GPBR3 (SAM3U_GPBR_BASE+SAM3U_GPBR3_OFFSET) +#define SAM3U_GPBR4 (SAM3U_GPBR_BASE+SAM3U_GPBR4_OFFSET) +#define SAM3U_GPBR5 (SAM3U_GPBR_BASE+SAM3U_GPBR5_OFFSET) +#define SAM3U_GPBR6 (SAM3U_GPBR_BASE+SAM3U_GPBR6_OFFSET) +#define SAM3U_GPBR7 (SAM3U_GPBR_BASE+SAM3U_GPBR7_OFFSET) + +/* GPBR register bit definitions ********************************************************/ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_GPBR_H */ diff --git a/arch/arm/src/sam3u/sam3u_gpioirq.c b/arch/arm/src/sam3u/sam3u_gpioirq.c index bcc597b8602f7fa271828d267ded9edea560072e..dc01374a9f316c7cb7da0cd2369fe991b6a1bc07 100644 --- a/arch/arm/src/sam3u/sam3u_gpioirq.c +++ b/arch/arm/src/sam3u/sam3u_gpioirq.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/sam3u_gpioirq.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/sam3u/sam3u_hsmci.h b/arch/arm/src/sam3u/sam3u_hsmci.h index 3923adf5a0297c46b0fce05b032f453fb07297a1..1667789a6b6798f349bfb717d166b82f014d6494 100644 --- a/arch/arm/src/sam3u/sam3u_hsmci.h +++ b/arch/arm/src/sam3u/sam3u_hsmci.h @@ -1,297 +1,297 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_hsmci.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_HSMCI_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_HSMCI_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* HSMCI register offsets ***************************************************************/ - -#define SAM3U_HSMCI_CR_OFFSET 0x0000 /* Control Register */ -#define SAM3U_HSMCI_MR_OFFSET 0x0004 /* Mode Register */ -#define SAM3U_HSMCI_DTOR_OFFSET 0x0008 /* Data Timeout Register */ -#define SAM3U_HSMCI_SDCR_OFFSET 0x000c /* SD/SDIO Card Register */ -#define SAM3U_HSMCI_ARGR_OFFSET 0x0010 /* Argument Register */ -#define SAM3U_HSMCI_CMDR_OFFSET 0x0014 /* Command Register */ -#define SAM3U_HSMCI_BLKR_OFFSET 0x0018 /* Block Register */ -#define SAM3U_HSMCI_CSTOR_OFFSET 0x001c /* Completion Signal Timeout Register */ -#define SAM3U_HSMCI_RSPR0_OFFSET 0x0020 /* Response Register 0 */ -#define SAM3U_HSMCI_RSPR1_OFFSET 0x0024 /* Response Register 1 */ -#define SAM3U_HSMCI_RSPR2_OFFSET 0x0028 /* Response Register 2 */ -#define SAM3U_HSMCI_RSPR3_OFFSET 0x002c /* Response Register 3 */ -#define SAM3U_HSMCI_RDR_OFFSET 0x0030 /* Receive Data Register */ -#define SAM3U_HSMCI_TDR_OFFSET 0x0034 /* Transmit Data Register */ - /* 0x0038-0x003c: Reserved */ -#define SAM3U_HSMCI_SR_OFFSET 0x0040 /* Status Register */ -#define SAM3U_HSMCI_IER_OFFSET 0x0044 /* Interrupt Enable Register */ -#define SAM3U_HSMCI_IDR_OFFSET 0x0048 /* Interrupt Disable Register */ -#define SAM3U_HSMCI_IMR_OFFSET 0x004c /* Interrupt Mask Register */ -#define SAM3U_HSMCI_DMA_OFFSET 0x0050 /* DMA Configuration Register */ -#define SAM3U_HSMCI_CFG_OFFSET 0x0054 /* Configuration Register */ - /* 0x0058-0x00e0: Reserved */ -#define SAM3U_HSMCI_WPMR_OFFSET 0x00e4 /* Write Protection Mode Register */ -#define SAM3U_HSMCI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */ - /* 0x00ec-0x00fc: Reserved */ - /* 0x0100-0x0124: Reserved */ -#define SAM3U_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x3ffc FIFO Memory Aperture */ - -/* HSMCI register adresses **************************************************************/ - -#define SAM3U_HSMCI_CR (SAM3U_MCI_BASE+SAM3U_HSMCI_CR_OFFSET) -#define SAM3U_HSMCI_MR (SAM3U_MCI_BASE+SAM3U_HSMCI_MR_OFFSET) -#define SAM3U_HSMCI_DTOR (SAM3U_MCI_BASE+SAM3U_HSMCI_DTOR_OFFSET) -#define SAM3U_HSMCI_SDCR (SAM3U_MCI_BASE+SAM3U_HSMCI_SDCR_OFFSET) -#define SAM3U_HSMCI_ARGR (SAM3U_MCI_BASE+SAM3U_HSMCI_ARGR_OFFSET) -#define SAM3U_HSMCI_CMDR (SAM3U_MCI_BASE+SAM3U_HSMCI_CMDR_OFFSET) -#define SAM3U_HSMCI_BLKR (SAM3U_MCI_BASE+SAM3U_HSMCI_BLKR_OFFSET) -#define SAM3U_HSMCI_CSTOR (SAM3U_MCI_BASE+SAM3U_HSMCI_CSTOR_OFFSET) -#define SAM3U_HSMCI_RSPR0 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR0_OFFSET) -#define SAM3U_HSMCI_RSPR1 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR1_OFFSET) -#define SAM3U_HSMCI_RSPR2 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR2_OFFSET) -#define SAM3U_HSMCI_RSPR3 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR3_OFFSET) -#define SAM3U_HSMCI_RDR (SAM3U_MCI_BASE+SAM3U_HSMCI_RDR_OFFSET) -#define SAM3U_HSMCI_TDR (SAM3U_MCI_BASE+SAM3U_HSMCI_TDR_OFFSET) -#define SAM3U_HSMCI_SR (SAM3U_MCI_BASE+SAM3U_HSMCI_SR_OFFSET) -#define SAM3U_HSMCI_IER (SAM3U_MCI_BASE+SAM3U_HSMCI_IER_OFFSET) -#define SAM3U_HSMCI_IDR (SAM3U_MCI_BASE+SAM3U_HSMCI_IDR_OFFSET) -#define SAM3U_HSMCI_IMR (SAM3U_MCI_BASE+SAM3U_HSMCI_IMR_OFFSET) -#define SAM3U_HSMCI_DMA (SAM3U_MCI_BASE+SAM3U_HSMCI_DMA_OFFSET) -#define SAM3U_HSMCI_CFG (SAM3U_MCI_BASE+SAM3U_HSMCI_CFG_OFFSET) -#define SAM3U_HSMCI_WPMR (SAM3U_MCI_BASE+SAM3U_HSMCI_WPMR_OFFSET) -#define SAM3U_HSMCI_WPSR (SAM3U_MCI_BASE+SAM3U_HSMCI_WPSR_OFFSET) -#define SAM3U_HSMCI_FIFO (SAM3U_MCI_BASE+SAM3U_HSMCI_FIFO_OFFSET) - -/* HSMCI register bit definitions *******************************************************/ - -/* HSMCI Control Register */ - -#define HSMCI_CR_MCIEN (1 << 0) /* Bit 0: Multi-Media Interface Enable */ -#define HSMCI_CR_MCIDIS (1 << 1) /* Bit 1: Multi-Media Interface Disable */ -#define HSMCI_CR_PWSEN (1 << 2) /* Bit 2: Power Save Mode Enable */ -#define HSMCI_CR_PWSDIS (1 << 3) /* Bit 3: Power Save Mode Disable */ -#define HSMCI_CR_SWRST (1 << 7) /* Bit 7: Software Reset */ - -/* HSMCI Mode Register */ - -#define HSMCI_MR_CLKDIV_SHIFT (0) /* Bits 0-7: Clock Divider */ -#define HSMCI_MR_CLKDIV_MASK (0xff << HSMCI_MR_CLKDIV_SHIFT) -#define HSMCI_MR_PWSDIV_SHIFT (8) /* Bits 8-10: Power Saving Divider */ -#define HSMCI_MR_PWSDIV_MASK (7 << HSMCI_MR_PWSDIV_SHIFT) -# define HSMCI_MR_PWSDIV_MAX (7 << HSMCI_MR_PWSDIV_SHIFT) -#define HSMCI_MR_RDPROOF (1 << 11) /* Bit 11: Read Proof Enable */ -#define HSMCI_MR_WRPROOF (1 << 12) /* Bit 12: Write Proof Enable */ -#define HSMCI_MR_FBYTE (1 << 13) /* Bit 13: Force Byte Transfer */ -#define HSMCI_MR_PADV (1 << 14) /* Bit 14: Padding Value */ -#define HSMCI_MR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */ -#define HSMCI_MR_BLKLEN_MASK (0xffff << HSMCI_MR_BLKLEN_SHIFT) - -/* HSMCI Data Timeout Register */ - -#define HSMCI_DTOR_DTOCYC_SHIFT (0) /* Bits 0-3: Data Timeout Cycle Number */ -#define HSMCI_DTOR_DTOCYC_MASK (15 << HSMCI_DTOR_DTOCYC_SHIFT) -# define HSMCI_DTOR_DTOCYC_MAX (15 << HSMCI_DTOR_DTOCYC_SHIFT) -#define HSMCI_DTOR_DTOMUL_SHIFT (4) /* Bits 4-6: Data Timeout Multiplier */ -#define HSMCI_DTOR_DTOMUL_MASK (7 << HSMCI_DTOR_DTOMUL_SHIFT) -# define HSMCI_DTOR_DTOMUL_1 (0 << HSMCI_DTOR_DTOMUL_SHIFT) -# define HSMCI_DTOR_DTOMUL_16 (1 << HSMCI_DTOR_DTOMUL_SHIFT) -# define HSMCI_DTOR_DTOMUL_128 (2 << HSMCI_DTOR_DTOMUL_SHIFT) -# define HSMCI_DTOR_DTOMUL_256 (3 << HSMCI_DTOR_DTOMUL_SHIFT) -# define HSMCI_DTOR_DTOMUL_1024 (4 << HSMCI_DTOR_DTOMUL_SHIFT) -# define HSMCI_DTOR_DTOMUL_4096 (5 << HSMCI_DTOR_DTOMUL_SHIFT) -# define HSMCI_DTOR_DTOMUL_65536 (6 << HSMCI_DTOR_DTOMUL_SHIFT) -# define HSMCI_DTOR_DTOMUL_1048576 (7 << HSMCI_DTOR_DTOMUL_SHIFT) -# define HSMCI_DTOR_DTOMUL_MAX (7 << HSMCI_DTOR_DTOMUL_SHIFT) - -/* HSMCI SDCard/SDIO Register */ - -#define HSMCI_SDCR_SDCSEL_SHIFT (0) /* Bits 0-1: SDCard/SDIO Slot */ -#define HSMCI_SDCR_SDCSEL_MASK (3 << HSMCI_SDCR_SDCSEL_SHIFT) -# define HSMCI_SDCR_SDCSEL_SLOTA (0 << HSMCI_SDCR_SDCSEL_SHIFT) -#define HSMCI_SDCR_SDCBUS_SHIFT (6) /* Bits 6-7: SDCard/SDIO Bus Width */ -#define HSMCI_SDCR_SDCBUS_MASK (3 << HSMCI_SDCR_SDCBUS_SHIFT) -# define HSMCI_SDCR_SDCBUS_1BIT (0 << HSMCI_SDCR_SDCBUS_SHIFT) -# define HSMCI_SDCR_SDCBUS_4BIT (2 << HSMCI_SDCR_SDCBUS_SHIFT) -# define HSMCI_SDCR_SDCBUS_8BIT (3 << HSMCI_SDCR_SDCBUS_SHIFT) - -/* HSMCI Command Register */ - -#define HSMCI_CMDR_CMDNB_SHIFT (0) /* Bits 0-5: Command Number */ -#define HSMCI_CMDR_CMDNB_MASK (63 << HSMCI_CMDR_CMDNB_SHIFT) -#define HSMCI_CMDR_RSPTYP_SHIFT (6) /* Bits 6-7: Response Type */ -#define HSMCI_CMDR_RSPTYP_MASK (3 << HSMCI_CMDR_RSPTYP_SHIFT) -# define HSMCI_CMDR_RSPTYP_NONE (0 << HSMCI_CMDR_RSPTYP_SHIFT) /* No response */ -# define HSMCI_CMDR_RSPTYP_48BIT (1 << HSMCI_CMDR_RSPTYP_SHIFT) /* 48-bit response */ -# define HSMCI_CMDR_RSPTYP_136BIT (2 << HSMCI_CMDR_RSPTYP_SHIFT) /* 136-bit response */ -# define HSMCI_CMDR_RSPTYP_R1B (3 << HSMCI_CMDR_RSPTYP_SHIFT) /* R1b response type */ -#define HSMCI_CMDR_SPCMD_SHIFT (8) /* Bits 8-10: Special Command */ -#define HSMCI_CMDR_SPCMD_MASK (7 << HSMCI_CMDR_SPCMD_SHIFT) -# define HSMCI_CMDR_SPCMD_NORMAL (0 << HSMCI_CMDR_SPCMD_SHIFT) /* Not a special CMD */ -# define HSMCI_CMDR_SPCMD_INIT (1 << HSMCI_CMDR_SPCMD_SHIFT) /* Initialization CMD */ -# define HSMCI_CMDR_SPCMD_SYNC (2 << HSMCI_CMDR_SPCMD_SHIFT) /* Synchronized CMD */ -# define HSMCI_CMDR_SPCMD_CEATAC (3 << HSMCI_CMDR_SPCMD_SHIFT) /* CE-ATA Completion Signal disable CMD */ -# define HSMCI_CMDR_SPCMD_INTCMD (4 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt command */ -# define HSMCI_CMDR_SPCMD_INTRESP (5 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt response */ -# define HSMCI_CMDR_SPCMD_BOOTOP (6 << HSMCI_CMDR_SPCMD_SHIFT) /* Boot Operation Request */ -# define HSMCI_CMDR_SPCMD_BOOTEND (7 << HSMCI_CMDR_SPCMD_SHIFT) /* End Boot Operation */ -#define HSMCI_CMDR_OPDCMD (1 << 11) /* Bit 11: Open Drain Command */ -#define HSMCI_CMDR_MAXLAT (1 << 12) /* Bit 12: Max Latency for Command to Response */ -#define HSMCI_CMDR_TRCMD_SHIFT (16) /* Bits 16-17: Transfer Command */ -#define HSMCI_CMDR_TRCMD_MASK (3 << HSMCI_CMDR_TRCMD_SHIFT) -# define HSMCI_CMDR_TRCMD_NONE (0 << HSMCI_CMDR_TRCMD_SHIFT) /* No data transfer */ -# define HSMCI_CMDR_TRCMD_START (1 << HSMCI_CMDR_TRCMD_SHIFT) /* Start data transfer */ -# define HSMCI_CMDR_TRCMD_STOP (2 << HSMCI_CMDR_TRCMD_SHIFT) /* Stop data transfer */ -#define HSMCI_CMDR_TRDIR (1 << 18) /* Bit 18: Transfer Direction */ -# define HSMCI_CMDR_TRDIR_WRITE (0 << 18) -# define HSMCI_CMDR_TRDIR_READ (1 << 18) -#define HSMCI_CMDR_TRTYP_SHIFT (19) /* Bits 19-21: Transfer Type */ -#define HSMCI_CMDR_TRTYP_MASK (7 << HSMCI_CMDR_TRTYP_SHIFT) -# define HSMCI_CMDR_TRTYP_SINGLE (0 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Single Block */ -# define HSMCI_CMDR_TRTYP_MULTI (1 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Multiple Block */ -# define HSMCI_CMDR_TRTYP_STREAM (2 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC Stream */ -# define HSMCI_CMDR_TRTYP_SDIOBYTE (4 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Byte */ -# define HSMCI_CMDR_TRTYP_SDIOBLK (5 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Block */ -#define HSMCI_CMDR_IOSPCMD_SHIFT (24) /* Bits 24-25: SDIO Special Command */ -#define HSMCI_CMDR_IOSPCMD_MASK (3 << HSMCI_CMDR_IOSPCMD_SHIFT) -# define HSMCI_CMDR_IOSPCMD_NORMAL (0 << HSMCI_CMDR_IOSPCMD_SHIFT) /* Not an SDIO Special Command */ -# define HSMCI_CMDR_IOSPCMD_SUSP (1 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Suspend Command */ -# define HSMCI_CMDR_IOSPCMD_RESUME (2 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Resume Command */ -#define HSMCI_CMDR_ATACS (1 << 26) /* Bit 26: ATA with Command Completion Signal */ -#define HSMCI_CMDR_BOOTACK (1 << 17) /* Bit 27: Boot Operation Acknowledge */ - -/* HSMCI Block Register */ - -#define HSMCI_BLKR_BCNT_SHIFT (0) /* Bits 0-15: MMC/SDIO Block Count - SDIO Byte Count */ -#define HSMCI_BLKR_BCNT_MASK (0xffff << HSMCI_BLKR_BCNT_SHIFT) -#define HSMCI_BLKR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */ -#define HSMCI_BLKR_BLKLEN_MASK (0xffff << HSMCI_BLKR_BLKLEN_SHIFT) - -/* HSMCI Completion Signal Timeout Register */ - -#define HSMCI_CSTOR_CSTOCYC_SHIFT (0) /* Bits 0-3: Completion Signal Timeout Cycle Number */ -#define HSMCI_CSTOR_CSTOCYC_MASK (15 << HSMCI_CSTOR_CSTOCYC_SHIFT) -#define HSMCI_CSTOR_CSTOMUL_SHIFT (4) /* Bits 4-6: Completion Signal Timeout Multiplier */ -#define HSMCI_CSTOR_CSTOMUL_MASK (7 << HSMCI_CSTOR_CSTOMUL_SHIFT) -# define HSMCI_CSTOR_CSTOMUL_1 (0 << HSMCI_CSTOR_CSTOMUL_SHIFT) -# define HSMCI_CSTOR_CSTOMUL_16 (1 << HSMCI_CSTOR_CSTOMUL_SHIFT) -# define HSMCI_CSTOR_CSTOMUL_128 (2 << HSMCI_CSTOR_CSTOMUL_SHIFT) -# define HSMCI_CSTOR_CSTOMUL_256 (3 << HSMCI_CSTOR_CSTOMUL_SHIFT) -# define HSMCI_CSTOR_CSTOMUL_1024 (4 << HSMCI_CSTOR_CSTOMUL_SHIFT) -# define HSMCI_CSTOR_CSTOMUL_4096 (5 << HSMCI_CSTOR_CSTOMUL_SHIFT) -# define HSMCI_CSTOR_CSTOMUL_65536 (6 << HSMCI_CSTOR_CSTOMUL_SHIFT) -# define HSMCI_CSTOR_CSTOMUL_1048576 (7 << HSMCI_CSTOR_CSTOMUL_SHIFT) - -/* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt Disable - * Register, and HSMCI Interrupt Mask Register common bit-field definitions - */ - -#define HSMCI_INT_CMDRDY (1 << 0) /* Bit 0: Command Ready */ -#define HSMCI_INT_RXRDY (1 << 1) /* Bit 1: Receiver Ready */ -#define HSMCI_INT_TXRDY (1 << 2) /* Bit 2: Transmit Ready */ -#define HSMCI_INT_BLKE (1 << 3) /* Bit 3: Data Block Ended */ -#define HSMCI_INT_DTIP (1 << 4) /* Bit 4: Data Transfer in Progress */ -#define HSMCI_INT_NOTBUSY (1 << 5) /* Bit 6: HSMCI Not Busy */ -#define HSMCI_INT_SDIOIRQA (1 << 8) /* Bit 8: SDIO Interrupt for Slot A */ -#define HSMCI_INT_SDIOWAIT (1 << 12) /* Bit 12: SDIO Read Wait Operation Status */ -#define HSMCI_INT_CSRCV (1 << 13) /* Bit 13: CE-ATA Completion Signal Received */ -#define HSMCI_INT_RINDE (1 << 16) /* Bit 16: Response Index Error */ -#define HSMCI_INT_RDIRE (1 << 17) /* Bit 17: Response Direction Error */ -#define HSMCI_INT_RCRCE (1 << 18) /* Bit 18: Response CRC Error */ -#define HSMCI_INT_RENDE (1 << 19) /* Bit 19: Response End Bit Error */ -#define HSMCI_INT_RTOE (1 << 20) /* Bit 20: Response Time-out */ -#define HSMCI_INT_DCRCE (1 << 21) /* Bit 21: Data CRC Error */ -#define HSMCI_INT_DTOE (1 << 22) /* Bit 22: Data Time-out Error */ -#define HSMCI_INT_CSTOE (1 << 23) /* Bit 23: Completion Signal Time-out Error */ -#define HSMCI_INT_BLKOVRE (1 << 24) /* Bit 24: DMA Block Overrun Error */ -#define HSMCI_INT_DMADONE (1 << 25) /* Bit 25: DMA Transfer done */ -#define HSMCI_INT_FIFOEMPTY (1 << 26) /* Bit 26: FIFO empty flag */ -#define HSMCI_INT_XFRDONE (1 << 27) /* Bit 27: Transfer Done flag */ -#define HSMCI_INT_ACKRCV (1 << 28) /* Bit 28: Boot Operation Acknowledge Received */ -#define HSMCI_INT_ACKRCVE (1 << 29) /* Bit 29: Boot Operation Acknowledge Error */ -#define HSMCI_INT_OVRE (1 << 30) /* Bit 30: Overrun */ -#define HSMCI_INT_UNRE (1 << 31) /* Bit 31: Underrun */ - -/* HSMCI DMA Configuration Register */ - -#define HSMCI_DMA_OFFSET_SHIFT (0) /* Bits 0-1: DMA Write Buffer Offset */ -#define HSMCI_DMA_OFFSET_MASK (3 << HSMCI_DMA_OFFSET_SHIFT) -#define HSMCI_DMA_CHKSIZE (1 << 4) /* Bit 4: DMA Channel Read and Write Chunk Size */ -#define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */ -#define HSMCI_DMA_ROPT (1 << 12) /* Bit 12: Read Optimization with padding */ - -/* HSMCI Configuration Register */ - -#define HSMCI_CFG_FIFOMODE (1 << 0) /* Bit 0: HSMCI Internal FIFO control mode */ -#define HSMCI_CFG_FERRCTRL (1 << 4) /* Bit 4: Flow Error flag reset control mode */ -#define HSMCI_CFG_HSMODE (1 << 8) /* Bit 8: High Speed Mode */ -#define HSMCI_CFG_LSYNC (1 << 12) /* Bit 12: Synchronize on the last block */ - -/* HSMCI Write Protect Mode Register */ - -#define HSMCI_WPMR_WP_EN (1 << 0) /* Bit 0: Write Protection Enable */ -#define HSMCI_WPMR_WP_KEY_SHIFT (8) /* Bits 8-31: Write Protection Key password */ -#define HSMCI_WPMR_WP_KEY_MASK (0x00ffffff << HSMCI_WPMR_WP_KEY_SHIFT) - -/* HSMCI Write Protect Status Register */ - -#define HSMCI_WPSR_WP_VS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ -#define HSMCI_WPSR_WP_VS_MASK (15 << HSMCI_WPSR_WP_VS_SHIFT) -#define HSMCI_WPSR_WP_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ -#define HSMCI_WPSR_WP_VSRC_MASK (0xffff << HSMCI_WPSR_WP_VSRC_SHIFT) - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_HSMCI_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_hsmci.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_HSMCI_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_HSMCI_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* HSMCI register offsets ***************************************************************/ + +#define SAM3U_HSMCI_CR_OFFSET 0x0000 /* Control Register */ +#define SAM3U_HSMCI_MR_OFFSET 0x0004 /* Mode Register */ +#define SAM3U_HSMCI_DTOR_OFFSET 0x0008 /* Data Timeout Register */ +#define SAM3U_HSMCI_SDCR_OFFSET 0x000c /* SD/SDIO Card Register */ +#define SAM3U_HSMCI_ARGR_OFFSET 0x0010 /* Argument Register */ +#define SAM3U_HSMCI_CMDR_OFFSET 0x0014 /* Command Register */ +#define SAM3U_HSMCI_BLKR_OFFSET 0x0018 /* Block Register */ +#define SAM3U_HSMCI_CSTOR_OFFSET 0x001c /* Completion Signal Timeout Register */ +#define SAM3U_HSMCI_RSPR0_OFFSET 0x0020 /* Response Register 0 */ +#define SAM3U_HSMCI_RSPR1_OFFSET 0x0024 /* Response Register 1 */ +#define SAM3U_HSMCI_RSPR2_OFFSET 0x0028 /* Response Register 2 */ +#define SAM3U_HSMCI_RSPR3_OFFSET 0x002c /* Response Register 3 */ +#define SAM3U_HSMCI_RDR_OFFSET 0x0030 /* Receive Data Register */ +#define SAM3U_HSMCI_TDR_OFFSET 0x0034 /* Transmit Data Register */ + /* 0x0038-0x003c: Reserved */ +#define SAM3U_HSMCI_SR_OFFSET 0x0040 /* Status Register */ +#define SAM3U_HSMCI_IER_OFFSET 0x0044 /* Interrupt Enable Register */ +#define SAM3U_HSMCI_IDR_OFFSET 0x0048 /* Interrupt Disable Register */ +#define SAM3U_HSMCI_IMR_OFFSET 0x004c /* Interrupt Mask Register */ +#define SAM3U_HSMCI_DMA_OFFSET 0x0050 /* DMA Configuration Register */ +#define SAM3U_HSMCI_CFG_OFFSET 0x0054 /* Configuration Register */ + /* 0x0058-0x00e0: Reserved */ +#define SAM3U_HSMCI_WPMR_OFFSET 0x00e4 /* Write Protection Mode Register */ +#define SAM3U_HSMCI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */ + /* 0x00ec-0x00fc: Reserved */ + /* 0x0100-0x0124: Reserved */ +#define SAM3U_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x3ffc FIFO Memory Aperture */ + +/* HSMCI register adresses **************************************************************/ + +#define SAM3U_HSMCI_CR (SAM3U_MCI_BASE+SAM3U_HSMCI_CR_OFFSET) +#define SAM3U_HSMCI_MR (SAM3U_MCI_BASE+SAM3U_HSMCI_MR_OFFSET) +#define SAM3U_HSMCI_DTOR (SAM3U_MCI_BASE+SAM3U_HSMCI_DTOR_OFFSET) +#define SAM3U_HSMCI_SDCR (SAM3U_MCI_BASE+SAM3U_HSMCI_SDCR_OFFSET) +#define SAM3U_HSMCI_ARGR (SAM3U_MCI_BASE+SAM3U_HSMCI_ARGR_OFFSET) +#define SAM3U_HSMCI_CMDR (SAM3U_MCI_BASE+SAM3U_HSMCI_CMDR_OFFSET) +#define SAM3U_HSMCI_BLKR (SAM3U_MCI_BASE+SAM3U_HSMCI_BLKR_OFFSET) +#define SAM3U_HSMCI_CSTOR (SAM3U_MCI_BASE+SAM3U_HSMCI_CSTOR_OFFSET) +#define SAM3U_HSMCI_RSPR0 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR0_OFFSET) +#define SAM3U_HSMCI_RSPR1 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR1_OFFSET) +#define SAM3U_HSMCI_RSPR2 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR2_OFFSET) +#define SAM3U_HSMCI_RSPR3 (SAM3U_MCI_BASE+SAM3U_HSMCI_RSPR3_OFFSET) +#define SAM3U_HSMCI_RDR (SAM3U_MCI_BASE+SAM3U_HSMCI_RDR_OFFSET) +#define SAM3U_HSMCI_TDR (SAM3U_MCI_BASE+SAM3U_HSMCI_TDR_OFFSET) +#define SAM3U_HSMCI_SR (SAM3U_MCI_BASE+SAM3U_HSMCI_SR_OFFSET) +#define SAM3U_HSMCI_IER (SAM3U_MCI_BASE+SAM3U_HSMCI_IER_OFFSET) +#define SAM3U_HSMCI_IDR (SAM3U_MCI_BASE+SAM3U_HSMCI_IDR_OFFSET) +#define SAM3U_HSMCI_IMR (SAM3U_MCI_BASE+SAM3U_HSMCI_IMR_OFFSET) +#define SAM3U_HSMCI_DMA (SAM3U_MCI_BASE+SAM3U_HSMCI_DMA_OFFSET) +#define SAM3U_HSMCI_CFG (SAM3U_MCI_BASE+SAM3U_HSMCI_CFG_OFFSET) +#define SAM3U_HSMCI_WPMR (SAM3U_MCI_BASE+SAM3U_HSMCI_WPMR_OFFSET) +#define SAM3U_HSMCI_WPSR (SAM3U_MCI_BASE+SAM3U_HSMCI_WPSR_OFFSET) +#define SAM3U_HSMCI_FIFO (SAM3U_MCI_BASE+SAM3U_HSMCI_FIFO_OFFSET) + +/* HSMCI register bit definitions *******************************************************/ + +/* HSMCI Control Register */ + +#define HSMCI_CR_MCIEN (1 << 0) /* Bit 0: Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (1 << 1) /* Bit 1: Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (1 << 2) /* Bit 2: Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (1 << 3) /* Bit 3: Power Save Mode Disable */ +#define HSMCI_CR_SWRST (1 << 7) /* Bit 7: Software Reset */ + +/* HSMCI Mode Register */ + +#define HSMCI_MR_CLKDIV_SHIFT (0) /* Bits 0-7: Clock Divider */ +#define HSMCI_MR_CLKDIV_MASK (0xff << HSMCI_MR_CLKDIV_SHIFT) +#define HSMCI_MR_PWSDIV_SHIFT (8) /* Bits 8-10: Power Saving Divider */ +#define HSMCI_MR_PWSDIV_MASK (7 << HSMCI_MR_PWSDIV_SHIFT) +# define HSMCI_MR_PWSDIV_MAX (7 << HSMCI_MR_PWSDIV_SHIFT) +#define HSMCI_MR_RDPROOF (1 << 11) /* Bit 11: Read Proof Enable */ +#define HSMCI_MR_WRPROOF (1 << 12) /* Bit 12: Write Proof Enable */ +#define HSMCI_MR_FBYTE (1 << 13) /* Bit 13: Force Byte Transfer */ +#define HSMCI_MR_PADV (1 << 14) /* Bit 14: Padding Value */ +#define HSMCI_MR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */ +#define HSMCI_MR_BLKLEN_MASK (0xffff << HSMCI_MR_BLKLEN_SHIFT) + +/* HSMCI Data Timeout Register */ + +#define HSMCI_DTOR_DTOCYC_SHIFT (0) /* Bits 0-3: Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC_MASK (15 << HSMCI_DTOR_DTOCYC_SHIFT) +# define HSMCI_DTOR_DTOCYC_MAX (15 << HSMCI_DTOR_DTOCYC_SHIFT) +#define HSMCI_DTOR_DTOMUL_SHIFT (4) /* Bits 4-6: Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL_MASK (7 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_1 (0 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_16 (1 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_128 (2 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_256 (3 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_1024 (4 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_4096 (5 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_65536 (6 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_1048576 (7 << HSMCI_DTOR_DTOMUL_SHIFT) +# define HSMCI_DTOR_DTOMUL_MAX (7 << HSMCI_DTOR_DTOMUL_SHIFT) + +/* HSMCI SDCard/SDIO Register */ + +#define HSMCI_SDCR_SDCSEL_SHIFT (0) /* Bits 0-1: SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL_MASK (3 << HSMCI_SDCR_SDCSEL_SHIFT) +# define HSMCI_SDCR_SDCSEL_SLOTA (0 << HSMCI_SDCR_SDCSEL_SHIFT) +#define HSMCI_SDCR_SDCBUS_SHIFT (6) /* Bits 6-7: SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS_MASK (3 << HSMCI_SDCR_SDCBUS_SHIFT) +# define HSMCI_SDCR_SDCBUS_1BIT (0 << HSMCI_SDCR_SDCBUS_SHIFT) +# define HSMCI_SDCR_SDCBUS_4BIT (2 << HSMCI_SDCR_SDCBUS_SHIFT) +# define HSMCI_SDCR_SDCBUS_8BIT (3 << HSMCI_SDCR_SDCBUS_SHIFT) + +/* HSMCI Command Register */ + +#define HSMCI_CMDR_CMDNB_SHIFT (0) /* Bits 0-5: Command Number */ +#define HSMCI_CMDR_CMDNB_MASK (63 << HSMCI_CMDR_CMDNB_SHIFT) +#define HSMCI_CMDR_RSPTYP_SHIFT (6) /* Bits 6-7: Response Type */ +#define HSMCI_CMDR_RSPTYP_MASK (3 << HSMCI_CMDR_RSPTYP_SHIFT) +# define HSMCI_CMDR_RSPTYP_NONE (0 << HSMCI_CMDR_RSPTYP_SHIFT) /* No response */ +# define HSMCI_CMDR_RSPTYP_48BIT (1 << HSMCI_CMDR_RSPTYP_SHIFT) /* 48-bit response */ +# define HSMCI_CMDR_RSPTYP_136BIT (2 << HSMCI_CMDR_RSPTYP_SHIFT) /* 136-bit response */ +# define HSMCI_CMDR_RSPTYP_R1B (3 << HSMCI_CMDR_RSPTYP_SHIFT) /* R1b response type */ +#define HSMCI_CMDR_SPCMD_SHIFT (8) /* Bits 8-10: Special Command */ +#define HSMCI_CMDR_SPCMD_MASK (7 << HSMCI_CMDR_SPCMD_SHIFT) +# define HSMCI_CMDR_SPCMD_NORMAL (0 << HSMCI_CMDR_SPCMD_SHIFT) /* Not a special CMD */ +# define HSMCI_CMDR_SPCMD_INIT (1 << HSMCI_CMDR_SPCMD_SHIFT) /* Initialization CMD */ +# define HSMCI_CMDR_SPCMD_SYNC (2 << HSMCI_CMDR_SPCMD_SHIFT) /* Synchronized CMD */ +# define HSMCI_CMDR_SPCMD_CEATAC (3 << HSMCI_CMDR_SPCMD_SHIFT) /* CE-ATA Completion Signal disable CMD */ +# define HSMCI_CMDR_SPCMD_INTCMD (4 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt command */ +# define HSMCI_CMDR_SPCMD_INTRESP (5 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt response */ +# define HSMCI_CMDR_SPCMD_BOOTOP (6 << HSMCI_CMDR_SPCMD_SHIFT) /* Boot Operation Request */ +# define HSMCI_CMDR_SPCMD_BOOTEND (7 << HSMCI_CMDR_SPCMD_SHIFT) /* End Boot Operation */ +#define HSMCI_CMDR_OPDCMD (1 << 11) /* Bit 11: Open Drain Command */ +#define HSMCI_CMDR_MAXLAT (1 << 12) /* Bit 12: Max Latency for Command to Response */ +#define HSMCI_CMDR_TRCMD_SHIFT (16) /* Bits 16-17: Transfer Command */ +#define HSMCI_CMDR_TRCMD_MASK (3 << HSMCI_CMDR_TRCMD_SHIFT) +# define HSMCI_CMDR_TRCMD_NONE (0 << HSMCI_CMDR_TRCMD_SHIFT) /* No data transfer */ +# define HSMCI_CMDR_TRCMD_START (1 << HSMCI_CMDR_TRCMD_SHIFT) /* Start data transfer */ +# define HSMCI_CMDR_TRCMD_STOP (2 << HSMCI_CMDR_TRCMD_SHIFT) /* Stop data transfer */ +#define HSMCI_CMDR_TRDIR (1 << 18) /* Bit 18: Transfer Direction */ +# define HSMCI_CMDR_TRDIR_WRITE (0 << 18) +# define HSMCI_CMDR_TRDIR_READ (1 << 18) +#define HSMCI_CMDR_TRTYP_SHIFT (19) /* Bits 19-21: Transfer Type */ +#define HSMCI_CMDR_TRTYP_MASK (7 << HSMCI_CMDR_TRTYP_SHIFT) +# define HSMCI_CMDR_TRTYP_SINGLE (0 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Single Block */ +# define HSMCI_CMDR_TRTYP_MULTI (1 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Multiple Block */ +# define HSMCI_CMDR_TRTYP_STREAM (2 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC Stream */ +# define HSMCI_CMDR_TRTYP_SDIOBYTE (4 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Byte */ +# define HSMCI_CMDR_TRTYP_SDIOBLK (5 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_SHIFT (24) /* Bits 24-25: SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_MASK (3 << HSMCI_CMDR_IOSPCMD_SHIFT) +# define HSMCI_CMDR_IOSPCMD_NORMAL (0 << HSMCI_CMDR_IOSPCMD_SHIFT) /* Not an SDIO Special Command */ +# define HSMCI_CMDR_IOSPCMD_SUSP (1 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Suspend Command */ +# define HSMCI_CMDR_IOSPCMD_RESUME (2 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (1 << 26) /* Bit 26: ATA with Command Completion Signal */ +#define HSMCI_CMDR_BOOTACK (1 << 17) /* Bit 27: Boot Operation Acknowledge */ + +/* HSMCI Block Register */ + +#define HSMCI_BLKR_BCNT_SHIFT (0) /* Bits 0-15: MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT_MASK (0xffff << HSMCI_BLKR_BCNT_SHIFT) +#define HSMCI_BLKR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */ +#define HSMCI_BLKR_BLKLEN_MASK (0xffff << HSMCI_BLKR_BLKLEN_SHIFT) + +/* HSMCI Completion Signal Timeout Register */ + +#define HSMCI_CSTOR_CSTOCYC_SHIFT (0) /* Bits 0-3: Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC_MASK (15 << HSMCI_CSTOR_CSTOCYC_SHIFT) +#define HSMCI_CSTOR_CSTOMUL_SHIFT (4) /* Bits 4-6: Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL_MASK (7 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_1 (0 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_16 (1 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_128 (2 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_256 (3 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_1024 (4 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_4096 (5 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_65536 (6 << HSMCI_CSTOR_CSTOMUL_SHIFT) +# define HSMCI_CSTOR_CSTOMUL_1048576 (7 << HSMCI_CSTOR_CSTOMUL_SHIFT) + +/* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt Disable + * Register, and HSMCI Interrupt Mask Register common bit-field definitions + */ + +#define HSMCI_INT_CMDRDY (1 << 0) /* Bit 0: Command Ready */ +#define HSMCI_INT_RXRDY (1 << 1) /* Bit 1: Receiver Ready */ +#define HSMCI_INT_TXRDY (1 << 2) /* Bit 2: Transmit Ready */ +#define HSMCI_INT_BLKE (1 << 3) /* Bit 3: Data Block Ended */ +#define HSMCI_INT_DTIP (1 << 4) /* Bit 4: Data Transfer in Progress */ +#define HSMCI_INT_NOTBUSY (1 << 5) /* Bit 6: HSMCI Not Busy */ +#define HSMCI_INT_SDIOIRQA (1 << 8) /* Bit 8: SDIO Interrupt for Slot A */ +#define HSMCI_INT_SDIOWAIT (1 << 12) /* Bit 12: SDIO Read Wait Operation Status */ +#define HSMCI_INT_CSRCV (1 << 13) /* Bit 13: CE-ATA Completion Signal Received */ +#define HSMCI_INT_RINDE (1 << 16) /* Bit 16: Response Index Error */ +#define HSMCI_INT_RDIRE (1 << 17) /* Bit 17: Response Direction Error */ +#define HSMCI_INT_RCRCE (1 << 18) /* Bit 18: Response CRC Error */ +#define HSMCI_INT_RENDE (1 << 19) /* Bit 19: Response End Bit Error */ +#define HSMCI_INT_RTOE (1 << 20) /* Bit 20: Response Time-out */ +#define HSMCI_INT_DCRCE (1 << 21) /* Bit 21: Data CRC Error */ +#define HSMCI_INT_DTOE (1 << 22) /* Bit 22: Data Time-out Error */ +#define HSMCI_INT_CSTOE (1 << 23) /* Bit 23: Completion Signal Time-out Error */ +#define HSMCI_INT_BLKOVRE (1 << 24) /* Bit 24: DMA Block Overrun Error */ +#define HSMCI_INT_DMADONE (1 << 25) /* Bit 25: DMA Transfer done */ +#define HSMCI_INT_FIFOEMPTY (1 << 26) /* Bit 26: FIFO empty flag */ +#define HSMCI_INT_XFRDONE (1 << 27) /* Bit 27: Transfer Done flag */ +#define HSMCI_INT_ACKRCV (1 << 28) /* Bit 28: Boot Operation Acknowledge Received */ +#define HSMCI_INT_ACKRCVE (1 << 29) /* Bit 29: Boot Operation Acknowledge Error */ +#define HSMCI_INT_OVRE (1 << 30) /* Bit 30: Overrun */ +#define HSMCI_INT_UNRE (1 << 31) /* Bit 31: Underrun */ + +/* HSMCI DMA Configuration Register */ + +#define HSMCI_DMA_OFFSET_SHIFT (0) /* Bits 0-1: DMA Write Buffer Offset */ +#define HSMCI_DMA_OFFSET_MASK (3 << HSMCI_DMA_OFFSET_SHIFT) +#define HSMCI_DMA_CHKSIZE (1 << 4) /* Bit 4: DMA Channel Read and Write Chunk Size */ +#define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */ +#define HSMCI_DMA_ROPT (1 << 12) /* Bit 12: Read Optimization with padding */ + +/* HSMCI Configuration Register */ + +#define HSMCI_CFG_FIFOMODE (1 << 0) /* Bit 0: HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (1 << 4) /* Bit 4: Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (1 << 8) /* Bit 8: High Speed Mode */ +#define HSMCI_CFG_LSYNC (1 << 12) /* Bit 12: Synchronize on the last block */ + +/* HSMCI Write Protect Mode Register */ + +#define HSMCI_WPMR_WP_EN (1 << 0) /* Bit 0: Write Protection Enable */ +#define HSMCI_WPMR_WP_KEY_SHIFT (8) /* Bits 8-31: Write Protection Key password */ +#define HSMCI_WPMR_WP_KEY_MASK (0x00ffffff << HSMCI_WPMR_WP_KEY_SHIFT) + +/* HSMCI Write Protect Status Register */ + +#define HSMCI_WPSR_WP_VS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ +#define HSMCI_WPSR_WP_VS_MASK (15 << HSMCI_WPSR_WP_VS_SHIFT) +#define HSMCI_WPSR_WP_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ +#define HSMCI_WPSR_WP_VSRC_MASK (0xffff << HSMCI_WPSR_WP_VSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_HSMCI_H */ diff --git a/arch/arm/src/sam3u/sam3u_irq.c b/arch/arm/src/sam3u/sam3u_irq.c index 156cba3199d30d9b943d80ab5fc5764c0564c086..db79314c00fc15ff0e3f1e359f0568e4fff25d97 100644 --- a/arch/arm/src/sam3u/sam3u_irq.c +++ b/arch/arm/src/sam3u/sam3u_irq.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/sam3u_irq.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/sam3u/sam3u_lowputc.c b/arch/arm/src/sam3u/sam3u_lowputc.c index a0e0f992658b5eaa1bacc355a005c8e77b38b668..7a1e74248a3a1198c21a17df3b5839740119890d 100644 --- a/arch/arm/src/sam3u/sam3u_lowputc.c +++ b/arch/arm/src/sam3u/sam3u_lowputc.c @@ -2,7 +2,7 @@ * arch/arm/src/sam3u/sam3u_lowputc.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/sam3u/sam3u_matrix.h b/arch/arm/src/sam3u/sam3u_matrix.h index e9d41a658adc2e7d2c4e6d6276e9a9ca80bb90fe..52232bfa5103fca9b17896521aa79d1f7a8afd44 100644 --- a/arch/arm/src/sam3u/sam3u_matrix.h +++ b/arch/arm/src/sam3u/sam3u_matrix.h @@ -1,214 +1,214 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_matric.h - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* MATRIX register offsets **************************************************************/ - -#define SAM3U_MATRIX_MCFG_OFFSET(n) ((n)<<2) -#define SAM3U_MATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */ -#define SAM3U_MATRIX_MCFG1_OFFSET 0x0004 /* Master Configuration Register 1 */ -#define SAM3U_MATRIX_MCFG2_OFFSET 0x0008 /* Master Configuration Register 2 */ -#define SAM3U_MATRIX_MCFG3_OFFSET 0x000c /* Master Configuration Register 3 */ -#define SAM3U_MATRIX_MCFG4_OFFSET 0x0010 /* Master Configuration Register 4 */ - /* 0x0014-0x003c: Reserved */ -#define SAM3U_MATRIX_SCFG_OFFSET(n) (0x0040+((n)<<2)) -#define SAM3U_MATRIX_SCFG0_OFFSET 0x0040 /* Slave Configuration Register 0 */ -#define SAM3U_MATRIX_SCFG1_OFFSET 0x0044 /* Slave Configuration Register 1 */ -#define SAM3U_MATRIX_SCFG2_OFFSET 0x0048 /* Slave Configuration Register 2 */ -#define SAM3U_MATRIX_SCFG3_OFFSET 0x004c /* Slave Configuration Register 3 */ -#define SAM3U_MATRIX_SCFG4_OFFSET 0x0050 /* Slave Configuration Register 4 */ -#define SAM3U_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */ -#define SAM3U_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */ -#define SAM3U_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */ -#define SAM3U_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */ -#define SAM3U_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */ - /* 0x0068-0x007c: Reserved */ -#define SAM3U_MATRIX_PRAS_OFFSET(n) (0x0080+((n)<<3)) -#define SAM3U_MATRIX_PRAS0_OFFSET 0x0080 /* Priority Register A for Slave 0 */ - /* 0x0084: Reserved */ -#define SAM3U_MATRIX_PRAS1_OFFSET 0x0088 /* Priority Register A for Slave 1 */ - /* 0x008c: Reserved */ -#define SAM3U_MATRIX_PRAS2_OFFSET 0x0090 /* Priority Register A for Slave 2 */ - /* 0x0094: Reserved */ -#define SAM3U_MATRIX_PRAS3_OFFSET 0x0098 /* Priority Register A for Slave 3 */ - /* 0x009c: Reserved */ -#define SAM3U_MATRIX_PRAS4_OFFSET 0x00a0 /* Priority Register A for Slave 4 */ - /* 0x00a4: Reserved */ -#define SAM3U_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */ - /* 0x00ac: Reserved */ -#define SAM3U_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */ - /* 0x00b4: Reserved */ -#define SAM3U_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */ - /* 0x00bc: Reserved */ -#define SAM3U_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */ - /* 0x00c4: Reserved */ -#define SAM3U_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */ - /* 0x00cc-0x00fc: Reserved */ -#define SAM3U_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */ - /* 0x0104-0x010c: Reserved */ -#define SAM3U_MATRIX_WPMR_OFFSET 0x01e4 /* Write Protect Mode Register */ -#define SAM3U_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */ - /* 0x0110 - 0x01fc: Reserved */ - -/* MATRIX register adresses *************************************************************/ - -#define SAM3U_MATRIX_MCFG(n)) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG_OFFSET(n)) -#define SAM3U_MATRIX_MCFG0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG0_OFFSET) -#define SAM3U_MATRIX_MCFG1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG1_OFFSET) -#define SAM3U_MATRIX_MCFG2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG2_OFFSET) -#define SAM3U_MATRIX_MCFG3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG3_OFFSET) -#define SAM3U_MATRIX_MCFG4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG4_OFFSET) - -#define SAM3U_MATRIX_SCFG(n) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG_OFFSET(n)) -#define SAM3U_MATRIX_SCFG0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG0_OFFSET) -#define SAM3U_MATRIX_SCFG1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG1_OFFSET) -#define SAM3U_MATRIX_SCFG2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG2_OFFSET) -#define SAM3U_MATRIX_SCFG3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG3_OFFSET) -#define SAM3U_MATRIX_SCFG4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG4_OFFSET) -#define SAM3U_MATRIX_SCFG5 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG5_OFFSET) -#define SAM3U_MATRIX_SCFG6 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG6_OFFSET) -#define SAM3U_MATRIX_SCFG7 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG7_OFFSET) -#define SAM3U_MATRIX_SCFG8 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG8_OFFSET) -#define SAM3U_MATRIX_SCFG9 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG9_OFFSET) - -#define SAM3U_MATRIX_PRAS(n) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS_OFFSET(n)) -#define SAM3U_MATRIX_PRAS0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS0_OFFSET) -#define SAM3U_MATRIX_PRAS1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS1_OFFSET) -#define SAM3U_MATRIX_PRAS2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS2_OFFSET) -#define SAM3U_MATRIX_PRAS3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS3_OFFSET) -#define SAM3U_MATRIX_PRAS4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS4_OFFSET) -#define SAM3U_MATRIX_PRAS5 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS5_OFFSET) -#define SAM3U_MATRIX_PRAS6 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS6_OFFSET) -#define SAM3U_MATRIX_PRAS7 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS7_OFFSET) -#define SAM3U_MATRIX_PRAS8 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS8_OFFSET) -#define SAM3U_MATRIX_PRAS9 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS9_OFFSET) - -#define SAM3U_MATRIX_MRCR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MRCR_OFFSET) -#define SAM3U_MATRIX_WPMR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_WPMR_OFFSET) -#define SAM3U_MATRIX_WPSR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_WPSR_OFFSET) - -/* MATRIX register bit definitions ******************************************************/ - -#define MATRIX_MCFG_ULBT_SHIFT (0) /* Bits 0-2: Undefined Length Burst Type */ -#define MATRIX_MCFG_ULBT_MASK (7 << MATRIX_MCFG_ULBT_SHIFT) -# define MATRIX_MCFG_ULBT_INF (0 << MATRIX_MCFG_ULBT_SHIFT) /* Infinite Length Burst */ -# define MATRIX_MCFG_ULBT_SINGLE (1 << MATRIX_MCFG_ULBT_SHIFT) /* Single Access */ -# define MATRIX_MCFG_ULBT_4BEAT (2 << MATRIX_MCFG_ULBT_SHIFT) /* Four Beat Burst */ -# define MATRIX_MCFG_ULBT_8BEAT (3 << MATRIX_MCFG_ULBT_SHIFT) /* Eight Beat Burst */ -# define MATRIX_MCFG_ULBT_16BEAT (4 << MATRIX_MCFG_ULBT_SHIFT) /* Sixteen Beat Burst */ - -#define MATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-7: Maximum Number of Allowed Cycles for a Burst */ -#define MATRIX_SCFG_SLOTCYCLE_MASK (0xff << MATRIX_SCFG_SLOTCYCLE_SHIFT) -#define MATRIX_SCFG_DEFMSTRTYPE_SHIFT (16) /* Bits 16-17: Default Master Type */ -#define MATRIX_SCFG_DEFMSTRTYPE_MASK (3 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) -# define MATRIX_SCFG_DEFMSTRTYPE_NONE (0 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) -# define MATRIX_SCFG_DEFMSTRTYPE_LAST (1 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) -# define MATRIX_SCFG_DEFMSTRTYPE_FIXED (2 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) -#define MATRIX_SCFG_FIXEDDEFMSTR_SHIFT (18) /* Bits 18-20: Fixed Default Master */ -#define MATRIX_SCFG_FIXEDDEFMSTR_MASK (7 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) -# define MATRIX_SCFG0_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) -# define MATRIX_SCFG1_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) -# define MATRIX_SCFG2_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) -# define MATRIX_SCFG3_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) -# define MATRIX_SCFG4_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) -# define MATRIX_SCFG5_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) -# define MATRIX_SCFG6_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) -# define MATRIX_SCFG7_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) -# define MATRIX_SCFG8_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) -# define MATRIX_SCFG8_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) -# define MATRIX_SCFG9_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) -# define MATRIX_SCFG9_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) - -#define MATRIX_SCFG_ARBT_SHIFT (24) /* Bits 24-25: Arbitration Type */ -#define MATRIX_SCFG_ARBT_MASK (3 << MATRIX_SCFG_ARBT_SHIFT) -# define MATRIX_SCFG_ARBT_RR (0 << MATRIX_SCFG_ARBT_SHIFT) /* Round-Robin Arbitration */ -# define MATRIX_SCFG_ARBT_FIXED (1 << MATRIX_SCFG_ARBT_SHIFT) /* Fixed Priority Arbitration */ - -#define MATRIX_PRAS_MPR_SHIFT(x) ((n)<<2) -#define MATRIX_PRAS_MPR_MASK(x) (3 << MATRIX_PRAS_MPR_SHIFT(x)) -#define MATRIX_PRAS_M0PR_SHIFT (0) /* Bits 0-1: Master 0 Priority */ -#define MATRIX_PRAS_M0PR_MASK (3 << MATRIX_PRAS_M0PR_SHIFT) -#define MATRIX_PRAS_M1PR_SHIFT (4) /* Bits 4-5: Master 1 Priority */ -#define MATRIX_PRAS_M1PR_MASK (3 << MATRIX_PRAS_M1PR_SHIFT) -#define MATRIX_PRAS_M2PR_SHIFT (8) /* Bits 8-9: Master 2 Priority */ -#define MATRIX_PRAS_M2PR_MASK (3 << MATRIX_PRAS_M2PR_SHIFT) -#define MATRIX_PRAS_M3PR_SHIFT (12) /* Bits 12-13: Master 3 Priority */ -#define MATRIX_PRAS_M3PR_MASK (3 << MATRIX_PRAS_M3PR_SHIFT) -#define MATRIX_PRAS_M4PR_SHIFT (16) /* Bits 16-17 Master 4 Priority */ -#define MATRIX_PRAS_M4PR_MASK (3 << MATRIX_PRAS_M4PR_SHIFT) - -#define MATRIX_MRCR_RCB(x) (1 << (x)) -#define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for AHB Master 0 */ -#define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for AHB Master 1 */ -#define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for AHB Master 2 */ -#define MATRIX_MRCR_RCB3 (1 << 3) /* Bit 3: Remap Command Bit for AHB Master 3 */ -#define MATRIX_MRCR_RCB4 (1 << 4) /* Bit 4: Remap Command Bit for AHB Master 4 */ - -#define MATRIX_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ -#define MATRIX_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (Write-only) */ -#define MATRIX_WPMR_WPKEY_MASK (0x00ffffff << MATRIX_WPMR_WPKEY_SHIFT) - -#define MATRIX_WPSR_WPVS (1 << 0) /* Bit 0: Enable Write Protect */ -#define MATRIX_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ -#define MATRIX_WPSR_WPVSRC_MASK (0xffff << MATRIX_WPSR_WPVSRC_SHIFT) - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_matric.h + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* MATRIX register offsets **************************************************************/ + +#define SAM3U_MATRIX_MCFG_OFFSET(n) ((n)<<2) +#define SAM3U_MATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */ +#define SAM3U_MATRIX_MCFG1_OFFSET 0x0004 /* Master Configuration Register 1 */ +#define SAM3U_MATRIX_MCFG2_OFFSET 0x0008 /* Master Configuration Register 2 */ +#define SAM3U_MATRIX_MCFG3_OFFSET 0x000c /* Master Configuration Register 3 */ +#define SAM3U_MATRIX_MCFG4_OFFSET 0x0010 /* Master Configuration Register 4 */ + /* 0x0014-0x003c: Reserved */ +#define SAM3U_MATRIX_SCFG_OFFSET(n) (0x0040+((n)<<2)) +#define SAM3U_MATRIX_SCFG0_OFFSET 0x0040 /* Slave Configuration Register 0 */ +#define SAM3U_MATRIX_SCFG1_OFFSET 0x0044 /* Slave Configuration Register 1 */ +#define SAM3U_MATRIX_SCFG2_OFFSET 0x0048 /* Slave Configuration Register 2 */ +#define SAM3U_MATRIX_SCFG3_OFFSET 0x004c /* Slave Configuration Register 3 */ +#define SAM3U_MATRIX_SCFG4_OFFSET 0x0050 /* Slave Configuration Register 4 */ +#define SAM3U_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */ +#define SAM3U_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */ +#define SAM3U_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */ +#define SAM3U_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */ +#define SAM3U_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */ + /* 0x0068-0x007c: Reserved */ +#define SAM3U_MATRIX_PRAS_OFFSET(n) (0x0080+((n)<<3)) +#define SAM3U_MATRIX_PRAS0_OFFSET 0x0080 /* Priority Register A for Slave 0 */ + /* 0x0084: Reserved */ +#define SAM3U_MATRIX_PRAS1_OFFSET 0x0088 /* Priority Register A for Slave 1 */ + /* 0x008c: Reserved */ +#define SAM3U_MATRIX_PRAS2_OFFSET 0x0090 /* Priority Register A for Slave 2 */ + /* 0x0094: Reserved */ +#define SAM3U_MATRIX_PRAS3_OFFSET 0x0098 /* Priority Register A for Slave 3 */ + /* 0x009c: Reserved */ +#define SAM3U_MATRIX_PRAS4_OFFSET 0x00a0 /* Priority Register A for Slave 4 */ + /* 0x00a4: Reserved */ +#define SAM3U_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */ + /* 0x00ac: Reserved */ +#define SAM3U_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */ + /* 0x00b4: Reserved */ +#define SAM3U_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */ + /* 0x00bc: Reserved */ +#define SAM3U_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */ + /* 0x00c4: Reserved */ +#define SAM3U_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */ + /* 0x00cc-0x00fc: Reserved */ +#define SAM3U_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */ + /* 0x0104-0x010c: Reserved */ +#define SAM3U_MATRIX_WPMR_OFFSET 0x01e4 /* Write Protect Mode Register */ +#define SAM3U_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */ + /* 0x0110 - 0x01fc: Reserved */ + +/* MATRIX register adresses *************************************************************/ + +#define SAM3U_MATRIX_MCFG(n)) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG_OFFSET(n)) +#define SAM3U_MATRIX_MCFG0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG0_OFFSET) +#define SAM3U_MATRIX_MCFG1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG1_OFFSET) +#define SAM3U_MATRIX_MCFG2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG2_OFFSET) +#define SAM3U_MATRIX_MCFG3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG3_OFFSET) +#define SAM3U_MATRIX_MCFG4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG4_OFFSET) + +#define SAM3U_MATRIX_SCFG(n) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG_OFFSET(n)) +#define SAM3U_MATRIX_SCFG0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG0_OFFSET) +#define SAM3U_MATRIX_SCFG1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG1_OFFSET) +#define SAM3U_MATRIX_SCFG2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG2_OFFSET) +#define SAM3U_MATRIX_SCFG3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG3_OFFSET) +#define SAM3U_MATRIX_SCFG4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG4_OFFSET) +#define SAM3U_MATRIX_SCFG5 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG5_OFFSET) +#define SAM3U_MATRIX_SCFG6 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG6_OFFSET) +#define SAM3U_MATRIX_SCFG7 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG7_OFFSET) +#define SAM3U_MATRIX_SCFG8 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG8_OFFSET) +#define SAM3U_MATRIX_SCFG9 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG9_OFFSET) + +#define SAM3U_MATRIX_PRAS(n) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS_OFFSET(n)) +#define SAM3U_MATRIX_PRAS0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS0_OFFSET) +#define SAM3U_MATRIX_PRAS1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS1_OFFSET) +#define SAM3U_MATRIX_PRAS2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS2_OFFSET) +#define SAM3U_MATRIX_PRAS3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS3_OFFSET) +#define SAM3U_MATRIX_PRAS4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS4_OFFSET) +#define SAM3U_MATRIX_PRAS5 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS5_OFFSET) +#define SAM3U_MATRIX_PRAS6 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS6_OFFSET) +#define SAM3U_MATRIX_PRAS7 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS7_OFFSET) +#define SAM3U_MATRIX_PRAS8 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS8_OFFSET) +#define SAM3U_MATRIX_PRAS9 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS9_OFFSET) + +#define SAM3U_MATRIX_MRCR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MRCR_OFFSET) +#define SAM3U_MATRIX_WPMR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_WPMR_OFFSET) +#define SAM3U_MATRIX_WPSR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_WPSR_OFFSET) + +/* MATRIX register bit definitions ******************************************************/ + +#define MATRIX_MCFG_ULBT_SHIFT (0) /* Bits 0-2: Undefined Length Burst Type */ +#define MATRIX_MCFG_ULBT_MASK (7 << MATRIX_MCFG_ULBT_SHIFT) +# define MATRIX_MCFG_ULBT_INF (0 << MATRIX_MCFG_ULBT_SHIFT) /* Infinite Length Burst */ +# define MATRIX_MCFG_ULBT_SINGLE (1 << MATRIX_MCFG_ULBT_SHIFT) /* Single Access */ +# define MATRIX_MCFG_ULBT_4BEAT (2 << MATRIX_MCFG_ULBT_SHIFT) /* Four Beat Burst */ +# define MATRIX_MCFG_ULBT_8BEAT (3 << MATRIX_MCFG_ULBT_SHIFT) /* Eight Beat Burst */ +# define MATRIX_MCFG_ULBT_16BEAT (4 << MATRIX_MCFG_ULBT_SHIFT) /* Sixteen Beat Burst */ + +#define MATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-7: Maximum Number of Allowed Cycles for a Burst */ +#define MATRIX_SCFG_SLOTCYCLE_MASK (0xff << MATRIX_SCFG_SLOTCYCLE_SHIFT) +#define MATRIX_SCFG_DEFMSTRTYPE_SHIFT (16) /* Bits 16-17: Default Master Type */ +#define MATRIX_SCFG_DEFMSTRTYPE_MASK (3 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) +# define MATRIX_SCFG_DEFMSTRTYPE_NONE (0 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) +# define MATRIX_SCFG_DEFMSTRTYPE_LAST (1 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) +# define MATRIX_SCFG_DEFMSTRTYPE_FIXED (2 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) +#define MATRIX_SCFG_FIXEDDEFMSTR_SHIFT (18) /* Bits 18-20: Fixed Default Master */ +#define MATRIX_SCFG_FIXEDDEFMSTR_MASK (7 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG0_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG1_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG2_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG3_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG4_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG5_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG6_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG7_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG8_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG8_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG9_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) +# define MATRIX_SCFG9_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) + +#define MATRIX_SCFG_ARBT_SHIFT (24) /* Bits 24-25: Arbitration Type */ +#define MATRIX_SCFG_ARBT_MASK (3 << MATRIX_SCFG_ARBT_SHIFT) +# define MATRIX_SCFG_ARBT_RR (0 << MATRIX_SCFG_ARBT_SHIFT) /* Round-Robin Arbitration */ +# define MATRIX_SCFG_ARBT_FIXED (1 << MATRIX_SCFG_ARBT_SHIFT) /* Fixed Priority Arbitration */ + +#define MATRIX_PRAS_MPR_SHIFT(x) ((n)<<2) +#define MATRIX_PRAS_MPR_MASK(x) (3 << MATRIX_PRAS_MPR_SHIFT(x)) +#define MATRIX_PRAS_M0PR_SHIFT (0) /* Bits 0-1: Master 0 Priority */ +#define MATRIX_PRAS_M0PR_MASK (3 << MATRIX_PRAS_M0PR_SHIFT) +#define MATRIX_PRAS_M1PR_SHIFT (4) /* Bits 4-5: Master 1 Priority */ +#define MATRIX_PRAS_M1PR_MASK (3 << MATRIX_PRAS_M1PR_SHIFT) +#define MATRIX_PRAS_M2PR_SHIFT (8) /* Bits 8-9: Master 2 Priority */ +#define MATRIX_PRAS_M2PR_MASK (3 << MATRIX_PRAS_M2PR_SHIFT) +#define MATRIX_PRAS_M3PR_SHIFT (12) /* Bits 12-13: Master 3 Priority */ +#define MATRIX_PRAS_M3PR_MASK (3 << MATRIX_PRAS_M3PR_SHIFT) +#define MATRIX_PRAS_M4PR_SHIFT (16) /* Bits 16-17 Master 4 Priority */ +#define MATRIX_PRAS_M4PR_MASK (3 << MATRIX_PRAS_M4PR_SHIFT) + +#define MATRIX_MRCR_RCB(x) (1 << (x)) +#define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for AHB Master 0 */ +#define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for AHB Master 1 */ +#define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for AHB Master 2 */ +#define MATRIX_MRCR_RCB3 (1 << 3) /* Bit 3: Remap Command Bit for AHB Master 3 */ +#define MATRIX_MRCR_RCB4 (1 << 4) /* Bit 4: Remap Command Bit for AHB Master 4 */ + +#define MATRIX_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define MATRIX_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (Write-only) */ +#define MATRIX_WPMR_WPKEY_MASK (0x00ffffff << MATRIX_WPMR_WPKEY_SHIFT) + +#define MATRIX_WPSR_WPVS (1 << 0) /* Bit 0: Enable Write Protect */ +#define MATRIX_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define MATRIX_WPSR_WPVSRC_MASK (0xffff << MATRIX_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_MATRIX_H */ diff --git a/arch/arm/src/sam3u/sam3u_memorymap.h b/arch/arm/src/sam3u/sam3u_memorymap.h index b38864ae5b853781b2284b89d9c84d248881c0cc..81027f7b43a345cdeaa0a8df5a88e48f11db43b8 100644 --- a/arch/arm/src/sam3u/sam3u_memorymap.h +++ b/arch/arm/src/sam3u/sam3u_memorymap.h @@ -1,145 +1,145 @@ -/************************************************************************************************ - * arch/arm/src/sam3u/sam3u_memorymap.h - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H - -/************************************************************************************************ - * Included Files - ************************************************************************************************/ - -#include -#include "chip.h" - -/************************************************************************************************ - * Pre-processor Definitions - ************************************************************************************************/ - -#define SAM3U_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */ -# define SAM3U_BOOTMEMORY_BASE 0x00000000 /* 0x00000000-0x0007ffff: Boot Memory */ -# define SAM3U_INTFLASH0_BASE 0x00080000 /* 0x00080000-0x000fffff: Internal FLASH 0 */ -# define SAM3U_INTFLASH1_BASE 0x00100000 /* 0x00100000-0x0017ffff: Internal FLASH 1 */ -# define SAM3U_INTROM_BASE 0x00180000 /* 0x00180000-0x001fffff: Internal ROM */ - /* 0x00200000-0x1fffffff: Reserved */ -#define SAM3U_INTSRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */ -# define SAM3U_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: SRAM0 (see chip.h) */ -# define SAM3U_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: SRAM1 (see chip.h) */ -# define SAM3U_NFCSRAM_BASE 0x20100000 /* 0x20100000-0x207fffff: NAND FLASH controller (SRAM) */ -# define SAM3U_UDPHPSDMS_BASE 0x20180000 /* 0x20180000-0x201fffff: USB Device High Speed (DMA) */ - /* 0x20200000-0x2fffffff: Undefined */ -# define SAM3U_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32Mb bit-band alias */ - /* 0x24000000-0x3fffffff: Undefined */ -#define SAM3U_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */ -# define SAM3U_MCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */ -# define SAM3U_SSC_BASE 0x40004000 /* 0x40004000-0x40007fff: Synchronous Serial Controller */ -# define SAM3U_SPI_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */ - /* 0x4000c000-0x4007ffff: Reserved */ -# define SAM3U_TC_BASE 0x40080000 /* 0x40080000-0x40083fff: Timer Counters */ -# define SAM3U_TCN_BASE(n) (0x40080000+((n)<<6)) -# define SAM3U_TC0_BASE 0x40080000 /* 0x40080000-0x4008003f: Timer Counter 0 */ -# define SAM3U_TC1_BASE 0x40080040 /* 0x40080040-0x4008007f: Timer Counter 1 */ -# define SAM3U_TC2_BASE 0x40080080 /* 0x40080080-0x400800bf: Timer Counter 2 */ -# define SAM3U_TWI_BASE 0x40084000 /* 0x40084000-0x4008ffff: Two-Wire Interface */ -# define SAM3U_TWIN_BASE(n) (0x40084000+((n)<<14)) -# define SAM3U_TWI0_BASE 0x40084000 /* 0x40084000-0x40087fff: Two-Wire Interface 0 */ -# define SAM3U_TWI1_BASE 0x40088000 /* 0x40088000-0x4008bfff: Two-Wire Interface 1 */ -# define SAM3U_PWM_BASE 0x4008c000 /* 0x4008c000-0x4008ffff: Pulse Width Modulation Controller */ -# define SAM3U_USART_BASE 0x40090000 /* 0x40090000-0x4009ffff: USART */ -# define SAM3U_USARTN_BASE(n) (0x40090000+((n)<<14)) -# define SAM3U_USART0_BASE 0x40090000 /* 0x40090000-0x40093fff: USART0 */ -# define SAM3U_USART1_BASE 0x40094000 /* 0x40094000-0x40097fff: USART1 */ -# define SAM3U_USART2_BASE 0x40098000 /* 0x40098000-0x4009bfff: USART2 */ -# define SAM3U_USART3_BASE 0x4009c000 /* 0x4009c000-0x4009ffff: USART3 */ - /* 0x400a0000-0x400a3fff: Reserved */ -# define SAM3U_UDPHS_BASE 0x400a4000 /* 0x400a4000-0x400a7fff: USB Device High Speed */ -# define SAM3U_ADC12B_BASE 0x400a8000 /* 0x400a8000-0x400abfff: 12-bit ADC Controller */ -# define SAM3U_ADC_BASE 0x400ac000 /* 0x400ac000-0x400affff: 10-bit ADC Controller */ -# define SAM3U_DMAC_BASE 0x400b0000 /* 0x400b0000-0x400b3fff: DMA controller */ - /* 0x400b4000-0x400dffff: Reserved */ -# define SAM3U_SYSCTRLR_BASE 0x400e0000 /* 0x400e0000-0x400e25ff: System controller */ - /* 0x400e2600-0x400fffff: Reserved */ - /* 0x40100000-0x41ffffff: Reserved */ -# define SAM3U_BBPERIPH__BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */ - /* 0x44000000-0x5fffffff: Reserved */ -#define SAM3U_EXTSRAM_BASE 0x60000000 /* 0x60000000-0x9fffffff: External SRAM */ -# define SAM3U_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */ -# define SAM3U_EXTCSN_BASE(n) (0x60000000*((n)<<24)) -# define SAM3U_EXTCS0_BASE 0x60000000 /* 0x60000000-0x60ffffff: Chip select 0 */ -# define SAM3U_EXTCS1_BASE 0x61000000 /* 0x61000000-0x601fffff: Chip select 1 */ -# define SAM3U_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */ -# define SAM3U_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */ - /* 0x64000000-0x67ffffff: Reserved */ -# define SAM3U_NFC_BASE 0x68000000 /* 0x68000000-0x68ffffff: NAND FLASH controller */ - /* 0x69000000-0x9fffffff: Reserved */ - /* 0xa0000000-0xdfffffff: Reserved */ -#define SAM3U_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */ - -/* System Controller Register Blocks: 0x400e0000-0x4007ffff */ - -#define SAM3U_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */ -#define SAM3U_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */ -#define SAM3U_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */ -#define SAM3U_UART_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART */ -#define SAM3U_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */ -#define SAM3U_EEFC_BASE 0x400e0800 /* 0x400e0800-0x400e0bff: Enhanced Embedded Flash Controllers*/ -# define SAM3U_EEFCN_BASE(n) (0x400e0800+((n)<<9)) -# define SAM3U_EEFC0_BASE 0x400e0800 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */ -# define SAM3U_EEFC1_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */ -#define SAM3U_PIO_BASE 0x400e0c00 /* 0x400e0c00-0x400e11ff: Parallel I/O Controllers */ -# define SAM3U_PION_BASE(n) (0x400e0c00+((n)<<9)) -# define SAM3U_PIOA_BASE 0x400e0c00 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */ -# define SAM3U_PIOB_BASE 0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */ -# define SAM3U_PIOC_BASE 0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */ -#define SAM3U_RSTC_BASE 0x400e1200 /* 0x400e1200-0x400e120f: Reset Controller */ -#define SAM3U_SUPC_BASE 0x400e1210 /* 0x400e1210-0x400e122f: Supply Controller */ -#define SAM3U_RTT_BASE 0x400e1230 /* 0x400e1230-0x400e124f: Real Time Timer */ -#define SAM3U_WDT_BASE 0x400e1250 /* 0x400e1250-0x400e125f: Watchdog Timer */ -#define SAM3U_RTC_BASE 0x400e1260 /* 0x400e1260-0x400e128f: Real Time Clock */ -#define SAM3U_GPBR_BASE 0x400e1290 /* 0x400e1290-0x400e13ff: GPBR */ - /* 0x490e1400-0x4007ffff: Reserved */ - -/************************************************************************************************ - * Public Types - ************************************************************************************************/ - -/************************************************************************************************ - * Public Data - ************************************************************************************************/ - -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H */ +/************************************************************************************************ + * arch/arm/src/sam3u/sam3u_memorymap.h + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include +#include "chip.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +#define SAM3U_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */ +# define SAM3U_BOOTMEMORY_BASE 0x00000000 /* 0x00000000-0x0007ffff: Boot Memory */ +# define SAM3U_INTFLASH0_BASE 0x00080000 /* 0x00080000-0x000fffff: Internal FLASH 0 */ +# define SAM3U_INTFLASH1_BASE 0x00100000 /* 0x00100000-0x0017ffff: Internal FLASH 1 */ +# define SAM3U_INTROM_BASE 0x00180000 /* 0x00180000-0x001fffff: Internal ROM */ + /* 0x00200000-0x1fffffff: Reserved */ +#define SAM3U_INTSRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */ +# define SAM3U_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: SRAM0 (see chip.h) */ +# define SAM3U_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: SRAM1 (see chip.h) */ +# define SAM3U_NFCSRAM_BASE 0x20100000 /* 0x20100000-0x207fffff: NAND FLASH controller (SRAM) */ +# define SAM3U_UDPHPSDMS_BASE 0x20180000 /* 0x20180000-0x201fffff: USB Device High Speed (DMA) */ + /* 0x20200000-0x2fffffff: Undefined */ +# define SAM3U_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32Mb bit-band alias */ + /* 0x24000000-0x3fffffff: Undefined */ +#define SAM3U_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */ +# define SAM3U_MCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */ +# define SAM3U_SSC_BASE 0x40004000 /* 0x40004000-0x40007fff: Synchronous Serial Controller */ +# define SAM3U_SPI_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */ + /* 0x4000c000-0x4007ffff: Reserved */ +# define SAM3U_TC_BASE 0x40080000 /* 0x40080000-0x40083fff: Timer Counters */ +# define SAM3U_TCN_BASE(n) (0x40080000+((n)<<6)) +# define SAM3U_TC0_BASE 0x40080000 /* 0x40080000-0x4008003f: Timer Counter 0 */ +# define SAM3U_TC1_BASE 0x40080040 /* 0x40080040-0x4008007f: Timer Counter 1 */ +# define SAM3U_TC2_BASE 0x40080080 /* 0x40080080-0x400800bf: Timer Counter 2 */ +# define SAM3U_TWI_BASE 0x40084000 /* 0x40084000-0x4008ffff: Two-Wire Interface */ +# define SAM3U_TWIN_BASE(n) (0x40084000+((n)<<14)) +# define SAM3U_TWI0_BASE 0x40084000 /* 0x40084000-0x40087fff: Two-Wire Interface 0 */ +# define SAM3U_TWI1_BASE 0x40088000 /* 0x40088000-0x4008bfff: Two-Wire Interface 1 */ +# define SAM3U_PWM_BASE 0x4008c000 /* 0x4008c000-0x4008ffff: Pulse Width Modulation Controller */ +# define SAM3U_USART_BASE 0x40090000 /* 0x40090000-0x4009ffff: USART */ +# define SAM3U_USARTN_BASE(n) (0x40090000+((n)<<14)) +# define SAM3U_USART0_BASE 0x40090000 /* 0x40090000-0x40093fff: USART0 */ +# define SAM3U_USART1_BASE 0x40094000 /* 0x40094000-0x40097fff: USART1 */ +# define SAM3U_USART2_BASE 0x40098000 /* 0x40098000-0x4009bfff: USART2 */ +# define SAM3U_USART3_BASE 0x4009c000 /* 0x4009c000-0x4009ffff: USART3 */ + /* 0x400a0000-0x400a3fff: Reserved */ +# define SAM3U_UDPHS_BASE 0x400a4000 /* 0x400a4000-0x400a7fff: USB Device High Speed */ +# define SAM3U_ADC12B_BASE 0x400a8000 /* 0x400a8000-0x400abfff: 12-bit ADC Controller */ +# define SAM3U_ADC_BASE 0x400ac000 /* 0x400ac000-0x400affff: 10-bit ADC Controller */ +# define SAM3U_DMAC_BASE 0x400b0000 /* 0x400b0000-0x400b3fff: DMA controller */ + /* 0x400b4000-0x400dffff: Reserved */ +# define SAM3U_SYSCTRLR_BASE 0x400e0000 /* 0x400e0000-0x400e25ff: System controller */ + /* 0x400e2600-0x400fffff: Reserved */ + /* 0x40100000-0x41ffffff: Reserved */ +# define SAM3U_BBPERIPH__BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */ + /* 0x44000000-0x5fffffff: Reserved */ +#define SAM3U_EXTSRAM_BASE 0x60000000 /* 0x60000000-0x9fffffff: External SRAM */ +# define SAM3U_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */ +# define SAM3U_EXTCSN_BASE(n) (0x60000000*((n)<<24)) +# define SAM3U_EXTCS0_BASE 0x60000000 /* 0x60000000-0x60ffffff: Chip select 0 */ +# define SAM3U_EXTCS1_BASE 0x61000000 /* 0x61000000-0x601fffff: Chip select 1 */ +# define SAM3U_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */ +# define SAM3U_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */ + /* 0x64000000-0x67ffffff: Reserved */ +# define SAM3U_NFC_BASE 0x68000000 /* 0x68000000-0x68ffffff: NAND FLASH controller */ + /* 0x69000000-0x9fffffff: Reserved */ + /* 0xa0000000-0xdfffffff: Reserved */ +#define SAM3U_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */ + +/* System Controller Register Blocks: 0x400e0000-0x4007ffff */ + +#define SAM3U_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */ +#define SAM3U_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */ +#define SAM3U_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */ +#define SAM3U_UART_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART */ +#define SAM3U_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIP ID */ +#define SAM3U_EEFC_BASE 0x400e0800 /* 0x400e0800-0x400e0bff: Enhanced Embedded Flash Controllers*/ +# define SAM3U_EEFCN_BASE(n) (0x400e0800+((n)<<9)) +# define SAM3U_EEFC0_BASE 0x400e0800 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */ +# define SAM3U_EEFC1_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */ +#define SAM3U_PIO_BASE 0x400e0c00 /* 0x400e0c00-0x400e11ff: Parallel I/O Controllers */ +# define SAM3U_PION_BASE(n) (0x400e0c00+((n)<<9)) +# define SAM3U_PIOA_BASE 0x400e0c00 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */ +# define SAM3U_PIOB_BASE 0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */ +# define SAM3U_PIOC_BASE 0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */ +#define SAM3U_RSTC_BASE 0x400e1200 /* 0x400e1200-0x400e120f: Reset Controller */ +#define SAM3U_SUPC_BASE 0x400e1210 /* 0x400e1210-0x400e122f: Supply Controller */ +#define SAM3U_RTT_BASE 0x400e1230 /* 0x400e1230-0x400e124f: Real Time Timer */ +#define SAM3U_WDT_BASE 0x400e1250 /* 0x400e1250-0x400e125f: Watchdog Timer */ +#define SAM3U_RTC_BASE 0x400e1260 /* 0x400e1260-0x400e128f: Real Time Clock */ +#define SAM3U_GPBR_BASE 0x400e1290 /* 0x400e1290-0x400e13ff: GPBR */ + /* 0x490e1400-0x4007ffff: Reserved */ + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_MEMORYMAP_H */ diff --git a/arch/arm/src/sam3u/sam3u_mpuinit.c b/arch/arm/src/sam3u/sam3u_mpuinit.c index beff4d43bd17b93600a0f4f385fdd015d34b7569..c6788d3b5406a39619ea7a75be8351f085c271e7 100644 --- a/arch/arm/src/sam3u/sam3u_mpuinit.c +++ b/arch/arm/src/sam3u/sam3u_mpuinit.c @@ -2,7 +2,7 @@ * arch/arm/src/common/sam3u_mpuinit.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/sam3u/sam3u_pdc.h b/arch/arm/src/sam3u/sam3u_pdc.h index 3520d74c3be5226631fb094cb69408a9e283cf3b..106b2cd917902157f2bb5a4d431dd54cb4187972 100644 --- a/arch/arm/src/sam3u/sam3u_pdc.h +++ b/arch/arm/src/sam3u/sam3u_pdc.h @@ -1,103 +1,103 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_pdc.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PDC_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_PDC_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* PDC register offsets *****************************************************************/ - -#define SAM3U_PDC_RPR_OFFSET 0x100 /* Receive Pointer Register */ -#define SAM3U_PDC_RCR_OFFSET 0x104 /* Receive Counter Register */ -#define SAM3U_PDC_TPR_OFFSET 0x108 /* Transmit Pointer Register */ -#define SAM3U_PDC_TCR_OFFSET 0x10c /* Transmit Counter Register */ -#define SAM3U_PDC_RNPR_OFFSET 0x110 /* Receive Next Pointer Register */ -#define SAM3U_PDC_RNCR_OFFSET 0x114 /* Receive Next Counter Register */ -#define SAM3U_PDC_TNPR_OFFSET 0x118 /* Transmit Next Pointer Register */ -#define SAM3U_PDC_TNCR_OFFSET 0x11c /* Transmit Next Counter Register */ -#define SAM3U_PDC_PTCR_OFFSET 0x120 /* Transfer Control Register */ -#define SAM3U_PDC_PTSR_OFFSET 0x124 /* Transfer Status Register */ - -/* PDC register adresses ****************************************************************/ - -/* These 10 registers are mapped in the peripheral memory space at the same offset. */ - -/* PDC register bit definitions *********************************************************/ - -#define PDC_RCR_RXCTR_SHIFT (0) /* Bits 0-15: Receive Counter Register */ -#define PDC_RCR_RXCTR_MASK (0xffff << PDC_RCR_RXCTR_SHIFT) - -#define PDC_TCR_TXCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Register */ -#define PDC_TCR_TXCTR_MASK (0xffff << PDC_TCR_TXCTR_SHIFT) - -#define PDC_RNCR_RXNCTR_SHIFT (0) /* Bits 0-15: Receive Next Counter */ -#define PDC_RNCR_RXNCTR_MASK (0xffff << PDC_RNCR_RXNCTR_SHIFT) - -#define PDC_TNCR_TXNCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Next */ -#define PDC_TNCR_TXNCTR_MASK (0xffff << PDC_TNCR_TXNCTR_SHIFT) - -#define PDC_PTCR_RXTEN (1 << 0) /* Bit 0: Receiver Transfer Enable */ -#define PDC_PTCR_RXTDIS (1 << 1) /* Bit 1: Receiver Transfer Disable */ -#define PDC_PTCR_TXTEN (1 << 8) /* Bit 8: Transmitter Transfer Enable */ -#define PDC_PTCR_TXTDIS (1 << 9) /* Bit 9: Transmitter Transfer Disable */ - -#define PDC_PTSR_RXTEN (1 << 0) /* Bit 0: Receiver Transfer Enable */ -#define PDC_PTSR_TXTEN (1 << 8) /* Bit 8: Transmitter Transfer Enable */ - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PDC_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_pdc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PDC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_PDC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* PDC register offsets *****************************************************************/ + +#define SAM3U_PDC_RPR_OFFSET 0x100 /* Receive Pointer Register */ +#define SAM3U_PDC_RCR_OFFSET 0x104 /* Receive Counter Register */ +#define SAM3U_PDC_TPR_OFFSET 0x108 /* Transmit Pointer Register */ +#define SAM3U_PDC_TCR_OFFSET 0x10c /* Transmit Counter Register */ +#define SAM3U_PDC_RNPR_OFFSET 0x110 /* Receive Next Pointer Register */ +#define SAM3U_PDC_RNCR_OFFSET 0x114 /* Receive Next Counter Register */ +#define SAM3U_PDC_TNPR_OFFSET 0x118 /* Transmit Next Pointer Register */ +#define SAM3U_PDC_TNCR_OFFSET 0x11c /* Transmit Next Counter Register */ +#define SAM3U_PDC_PTCR_OFFSET 0x120 /* Transfer Control Register */ +#define SAM3U_PDC_PTSR_OFFSET 0x124 /* Transfer Status Register */ + +/* PDC register adresses ****************************************************************/ + +/* These 10 registers are mapped in the peripheral memory space at the same offset. */ + +/* PDC register bit definitions *********************************************************/ + +#define PDC_RCR_RXCTR_SHIFT (0) /* Bits 0-15: Receive Counter Register */ +#define PDC_RCR_RXCTR_MASK (0xffff << PDC_RCR_RXCTR_SHIFT) + +#define PDC_TCR_TXCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Register */ +#define PDC_TCR_TXCTR_MASK (0xffff << PDC_TCR_TXCTR_SHIFT) + +#define PDC_RNCR_RXNCTR_SHIFT (0) /* Bits 0-15: Receive Next Counter */ +#define PDC_RNCR_RXNCTR_MASK (0xffff << PDC_RNCR_RXNCTR_SHIFT) + +#define PDC_TNCR_TXNCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Next */ +#define PDC_TNCR_TXNCTR_MASK (0xffff << PDC_TNCR_TXNCTR_SHIFT) + +#define PDC_PTCR_RXTEN (1 << 0) /* Bit 0: Receiver Transfer Enable */ +#define PDC_PTCR_RXTDIS (1 << 1) /* Bit 1: Receiver Transfer Disable */ +#define PDC_PTCR_TXTEN (1 << 8) /* Bit 8: Transmitter Transfer Enable */ +#define PDC_PTCR_TXTDIS (1 << 9) /* Bit 9: Transmitter Transfer Disable */ + +#define PDC_PTSR_RXTEN (1 << 0) /* Bit 0: Receiver Transfer Enable */ +#define PDC_PTSR_TXTEN (1 << 8) /* Bit 8: Transmitter Transfer Enable */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PDC_H */ diff --git a/arch/arm/src/sam3u/sam3u_pio.h b/arch/arm/src/sam3u/sam3u_pio.h index ab20ace9b93e5c833eee313f60588f7836513339..b55197ae1fb297f1ef7752ede71a4d402857526c 100644 --- a/arch/arm/src/sam3u/sam3u_pio.h +++ b/arch/arm/src/sam3u/sam3u_pio.h @@ -1,324 +1,324 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_pio.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PIO_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_PIO_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* PIO register offsets *****************************************************************/ - -#define SAM3U_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */ -#define SAM3U_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */ -#define SAM3U_PIO_PSR_OFFSET 0x0008 /* PIO Status Register */ - /* 0x000c: Reserved */ -#define SAM3U_PIO_OER_OFFSET 0x0010 /* Output Enable Register */ -#define SAM3U_PIO_ODR_OFFSET 0x0014 /* Output Disable Register */ -#define SAM3U_PIO_OSR_OFFSET 0x0018 /* utput Status Register */ - /* 0x001c: Reserved */ -#define SAM3U_PIO_IFER_OFFSET 0x0020 /* Glitch Input Filter Enable Register */ -#define SAM3U_PIO_IFDR_OFFSET 0x0024 /* Glitch Input Filter Disable Register */ -#define SAM3U_PIO_IFSR_OFFSET 0x0028 /* Glitch Input Filter Status Register */ - /* 0x002c: Reserved */ -#define SAM3U_PIO_SODR_OFFSET 0x0030 /* Set Output Data Register */ -#define SAM3U_PIO_CODR_OFFSET 0x0034 /* Clear Output Data Register */ -#define SAM3U_PIO_ODSR_OFFSET 0x0038 /* Output Data Status Register */ -#define SAM3U_PIO_PDSR_OFFSET 0x003c /* Pin Data Status Register */ -#define SAM3U_PIO_IER_OFFSET 0x0040 /* Interrupt Enable Register */ -#define SAM3U_PIO_IDR_OFFSET 0x0044 /* Interrupt Disable Register */ -#define SAM3U_PIO_IMR_OFFSET 0x0048 /* Interrupt Mask Register */ -#define SAM3U_PIO_ISR_OFFSET 0x004c /* Interrupt Status Register */ -#define SAM3U_PIO_MDER_OFFSET 0x0050 /* Multi-driver Enable Register */ -#define SAM3U_PIO_MDDR_OFFSET 0x0054 /* Multi-driver Disable Register */ -#define SAM3U_PIO_MDSR_OFFSET 0x0058 /* Multi-driver Status Register */ - /* 0x005c: Reserved */ -#define SAM3U_PIO_PUDR_OFFSET 0x0060 /* Pull-up Disable Register */ -#define SAM3U_PIO_PUER_OFFSET 0x0064 /* Pull-up Enable Register */ -#define SAM3U_PIO_PUSR_OFFSET 0x0068 /* Pad Pull-up Status Register */ - /* 0x006c: Reserved */ -#define SAM3U_PIO_ABSR_OFFSET 0x0070 /* Peripheral AB Select Register */ - /* 0x0074-0x007c: Reserved */ -#define SAM3U_PIO_SCIFSR_OFFSET 0x0080 /* System Clock Glitch Input Filter Select Register */ -#define SAM3U_PIO_DIFSR_OFFSET 0x0084 /* Debouncing Input Filter Select Register */ -#define SAM3U_PIO_IFDGSR_OFFSET 0x0088 /* Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define SAM3U_PIO_SCDR_OFFSET 0x008c /* Slow Clock Divider Debouncing Register */ - /* 0x0090-0x009c: Reserved */ -#define SAM3U_PIO_OWER_OFFSET 0x00a0 /* Output Write Enable */ -#define SAM3U_PIO_OWDR_OFFSET 0x00a4 /* Output Write Disable */ -#define SAM3U_PIO_OWSR_OFFSET 0x00a8 /* Output Write Status Register */ - /* 0x00ac: Reserved */ -#define SAM3U_PIO_AIMER_OFFSET 0x00b0 /* Additional Interrupt Modes Enable Register */ -#define SAM3U_PIO_AIMDR_OFFSET 0x00b4 /* Additional Interrupt Modes Disables Register */ -#define SAM3U_PIO_AIMMR_OFFSET 0x00b8 /* Additional Interrupt Modes Mask Register */ - /* 0x00bc: Reserved */ -#define SAM3U_PIO_ESR_OFFSET 0x00c0 /* Edge Select Register */ -#define SAM3U_PIO_LSR_OFFSET 0x00c4 /* Level Select Register */ -#define SAM3U_PIO_ELSR_OFFSET 0x00c8 /* Edge/Level Status Register */ - /* 0x00cc: Reserved */ -#define SAM3U_PIO_FELLSR_OFFSET 0x00d0 /* Falling Edge/Low Level Select Register */ -#define SAM3U_PIO_REHLSR_OFFSET 0x00d4 /* Rising Edge/ High Level Select Register */ -#define SAM3U_PIO_FRLHSR_OFFSET 0x00d8 /* Fall/Rise - Low/High Status Register */ - /* 0x00dc: Reserved */ -#define SAM3U_PIO_LOCKSR_OFFSET 0x00e0 /* Lock Status */ -#define SAM3U_PIO_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ -#define SAM3U_PIO_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ - /* 0x00ec-0x00f8: Reserved */ - /* 0x0100-0x0144: Reserved */ - -/* PIO register adresses ****************************************************************/ - -#define PIOA (0) -#define PIOB (1) -#define PIOC (2) -#define NPIO (3) - -#define SAM3U_PIO_PER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PER_OFFSET) -#define SAM3U_PIO_PDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PDR_OFFSET) -#define SAM3U_PIO_PSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PSR_OFFSET) -#define SAM3U_PIO_OER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OER_OFFSET) -#define SAM3U_PIO_ODR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ODR_OFFSET) -#define SAM3U_PIO_OSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OSR_OFFSET) -#define SAM3U_PIO_IFER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFER_OFFSET) -#define SAM3U_PIO_IFDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFDR_OFFSET) -#define SAM3U_PIO_IFSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFSR_OFFSET) -#define SAM3U_PIO_SODR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_SODR_OFFSET) -#define SAM3U_PIO_CODR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_CODR_OFFSET) -#define SAM3U_PIO_ODSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ODSR_OFFSET) -#define SAM3U_PIO_PDSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PDSR_OFFSET) -#define SAM3U_PIO_IER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IER_OFFSET) -#define SAM3U_PIO_IDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IDR_OFFSET) -#define SAM3U_PIO_IMR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IMR_OFFSET) -#define SAM3U_PIO_ISR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ISR_OFFSET) -#define SAM3U_PIO_MDER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_MDER_OFFSET) -#define SAM3U_PIO_MDDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_MDDR_OFFSET) -#define SAM3U_PIO_MDSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_MDSR_OFFSET) -#define SAM3U_PIO_PUDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PUDR_OFFSET) -#define SAM3U_PIO_PUER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PUER_OFFSET) -#define SAM3U_PIO_PUSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PUSR_OFFSET) -#define SAM3U_PIO_ABSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ABSR_OFFSET) -#define SAM3U_PIO_SCIFSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_SCIFSR_OFFSET) -#define SAM3U_PIO_DIFSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_DIFSR_OFFSET) -#define SAM3U_PIO_IFDGSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFDGSR_OFFSET) -#define SAM3U_PIO_SCDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_SCDR_OFFSET) -#define SAM3U_PIO_OWER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OWER_OFFSET) -#define SAM3U_PIO_OWDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OWDR_OFFSET) -#define SAM3U_PIO_OWSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OWSR_OFFSET) -#define SAM3U_PIO_AIMER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_AIMER_OFFSET) -#define SAM3U_PIO_AIMDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_AIMDR_OFFSET) -#define SAM3U_PIO_AIMMR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_AIMMR_OFFSET) -#define SAM3U_PIO_ESR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ESR_OFFSET) -#define SAM3U_PIO_LSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_LSR_OFFSET) -#define SAM3U_PIO_ELSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ELSR_OFFSET) -#define SAM3U_PIO_FELLSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_FELLSR_OFFSET) -#define SAM3U_PIO_REHLSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_REHLSR_OFFSET) -#define SAM3U_PIO_FRLHSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_FRLHSR_OFFSET) -#define SAM3U_PIO_LOCKSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_LOCKSR_OFFSET) -#define SAM3U_PIO_WPMR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_WPMR_OFFSET) -#define SAM3U_PIO_WPSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_WPSR_OFFSET) - -#define SAM3U_PIOA_PER (SAM3U_PIOA_BASE+SAM3U_PIO_PER_OFFSET) -#define SAM3U_PIOA_PDR_ (SAM3U_PIOA_BASE+SAM3U_PIO_PDR_OFFSET) -#define SAM3U_PIOA_PSR (SAM3U_PIOA_BASE+SAM3U_PIO_PSR_OFFSET) -#define SAM3U_PIOA_OER (SAM3U_PIOA_BASE+SAM3U_PIO_OER_OFFSET) -#define SAM3U_PIOA_ODR (SAM3U_PIOA_BASE+SAM3U_PIO_ODR_OFFSET) -#define SAM3U_PIOA_OSR (SAM3U_PIOA_BASE+SAM3U_PIO_OSR_OFFSET) -#define SAM3U_PIOA_IFER (SAM3U_PIOA_BASE+SAM3U_PIO_IFER_OFFSET) -#define SAM3U_PIOA_IFDR (SAM3U_PIOA_BASE+SAM3U_PIO_IFDR_OFFSET) -#define SAM3U_PIOA_IFSR (SAM3U_PIOA_BASE+SAM3U_PIO_IFSR_OFFSET) -#define SAM3U_PIOA_SODR (SAM3U_PIOA_BASE+SAM3U_PIO_SODR_OFFSET) -#define SAM3U_PIOA_CODR (SAM3U_PIOA_BASE+SAM3U_PIO_CODR_OFFSET) -#define SAM3U_PIOA_ODSR (SAM3U_PIOA_BASE+SAM3U_PIO_ODSR_OFFSET) -#define SAM3U_PIOA_PDSR (SAM3U_PIOA_BASE+SAM3U_PIO_PDSR_OFFSET) -#define SAM3U_PIOA_IER (SAM3U_PIOA_BASE+SAM3U_PIO_IER_OFFSET) -#define SAM3U_PIOA_IDR (SAM3U_PIOA_BASE+SAM3U_PIO_IDR_OFFSET) -#define SAM3U_PIOA_IMR (SAM3U_PIOA_BASE+SAM3U_PIO_IMR_OFFSET) -#define SAM3U_PIOA_ISR (SAM3U_PIOA_BASE+SAM3U_PIO_ISR_OFFSET) -#define SAM3U_PIOA_MDER (SAM3U_PIOA_BASE+SAM3U_PIO_MDER_OFFSET) -#define SAM3U_PIOA_MDDR (SAM3U_PIOA_BASE+SAM3U_PIO_MDDR_OFFSET) -#define SAM3U_PIOA_MDSR (SAM3U_PIOA_BASE+SAM3U_PIO_MDSR_OFFSET) -#define SAM3U_PIOA_PUDR (SAM3U_PIOA_BASE+SAM3U_PIO_PUDR_OFFSET) -#define SAM3U_PIOA_PUER (SAM3U_PIOA_BASE+SAM3U_PIO_PUER_OFFSET) -#define SAM3U_PIOA_PUSR (SAM3U_PIOA_BASE+SAM3U_PIO_PUSR_OFFSET) -#define SAM3U_PIOA_ABSR (SAM3U_PIOA_BASE+SAM3U_PIO_ABSR_OFFSET) -#define SAM3U_PIOA_SCIFSR (SAM3U_PIOA_BASE+SAM3U_PIO_SCIFSR_OFFSET) -#define SAM3U_PIOA_DIFSR (SAM3U_PIOA_BASE+SAM3U_PIO_DIFSR_OFFSET) -#define SAM3U_PIOA_IFDGSR (SAM3U_PIOA_BASE+SAM3U_PIO_IFDGSR_OFFSET) -#define SAM3U_PIOA_SCDR (SAM3U_PIOA_BASE+SAM3U_PIO_SCDR_OFFSET) -#define SAM3U_PIOA_OWER (SAM3U_PIOA_BASE+SAM3U_PIO_OWER_OFFSET) -#define SAM3U_PIOA_OWDR (SAM3U_PIOA_BASE+SAM3U_PIO_OWDR_OFFSET) -#define SAM3U_PIOA_OWSR (SAM3U_PIOA_BASE+SAM3U_PIO_OWSR_OFFSET) -#define SAM3U_PIOA_AIMER (SAM3U_PIOA_BASE+SAM3U_PIO_AIMER_OFFSET) -#define SAM3U_PIOA_AIMDR (SAM3U_PIOA_BASE+SAM3U_PIO_AIMDR_OFFSET) -#define SAM3U_PIOA_AIMMR (SAM3U_PIOA_BASE+SAM3U_PIO_AIMMR_OFFSET) -#define SAM3U_PIOA_ESR (SAM3U_PIOA_BASE+SAM3U_PIO_ESR_OFFSET) -#define SAM3U_PIOA_LSR (SAM3U_PIOA_BASE+SAM3U_PIO_LSR_OFFSET) -#define SAM3U_PIOA_ELSR (SAM3U_PIOA_BASE+SAM3U_PIO_ELSR_OFFSET) -#define SAM3U_PIOA_FELLSR (SAM3U_PIOA_BASE+SAM3U_PIO_FELLSR_OFFSET) -#define SAM3U_PIOA_REHLSR (SAM3U_PIOA_BASE+SAM3U_PIO_REHLSR_OFFSET) -#define SAM3U_PIOA_FRLHSR (SAM3U_PIOA_BASE+SAM3U_PIO_FRLHSR_OFFSET) -#define SAM3U_PIOA_LOCKSR (SAM3U_PIOA_BASE+SAM3U_PIO_LOCKSR_OFFSET) -#define SAM3U_PIOA_WPMR (SAM3U_PIOA_BASE+SAM3U_PIO_WPMR_OFFSET) -#define SAM3U_PIOA_WPSR (SAM3U_PIOA_BASE+SAM3U_PIO_WPSR_OFFSET) - -#define SAM3U_PIOB_PER (SAM3U_PIOB_BASE+SAM3U_PIO_PER_OFFSET) -#define SAM3U_PIOB_PDR_ (SAM3U_PIOB_BASE+SAM3U_PIO_PDR_OFFSET) -#define SAM3U_PIOB_PSR (SAM3U_PIOB_BASE+SAM3U_PIO_PSR_OFFSET) -#define SAM3U_PIOB_OER (SAM3U_PIOB_BASE+SAM3U_PIO_OER_OFFSET) -#define SAM3U_PIOB_ODR (SAM3U_PIOB_BASE+SAM3U_PIO_ODR_OFFSET) -#define SAM3U_PIOB_OSR (SAM3U_PIOB_BASE+SAM3U_PIO_OSR_OFFSET) -#define SAM3U_PIOB_IFER (SAM3U_PIOB_BASE+SAM3U_PIO_IFER_OFFSET) -#define SAM3U_PIOB_IFDR (SAM3U_PIOB_BASE+SAM3U_PIO_IFDR_OFFSET) -#define SAM3U_PIOB_IFSR (SAM3U_PIOB_BASE+SAM3U_PIO_IFSR_OFFSET) -#define SAM3U_PIOB_SODR (SAM3U_PIOB_BASE+SAM3U_PIO_SODR_OFFSET) -#define SAM3U_PIOB_CODR (SAM3U_PIOB_BASE+SAM3U_PIO_CODR_OFFSET) -#define SAM3U_PIOB_ODSR (SAM3U_PIOB_BASE+SAM3U_PIO_ODSR_OFFSET) -#define SAM3U_PIOB_PDSR (SAM3U_PIOB_BASE+SAM3U_PIO_PDSR_OFFSET) -#define SAM3U_PIOB_IER (SAM3U_PIOB_BASE+SAM3U_PIO_IER_OFFSET) -#define SAM3U_PIOB_IDR (SAM3U_PIOB_BASE+SAM3U_PIO_IDR_OFFSET) -#define SAM3U_PIOB_IMR (SAM3U_PIOB_BASE+SAM3U_PIO_IMR_OFFSET) -#define SAM3U_PIOB_ISR (SAM3U_PIOB_BASE+SAM3U_PIO_ISR_OFFSET) -#define SAM3U_PIOB_MDER (SAM3U_PIOB_BASE+SAM3U_PIO_MDER_OFFSET) -#define SAM3U_PIOB_MDDR (SAM3U_PIOB_BASE+SAM3U_PIO_MDDR_OFFSET) -#define SAM3U_PIOB_MDSR (SAM3U_PIOB_BASE+SAM3U_PIO_MDSR_OFFSET) -#define SAM3U_PIOB_PUDR (SAM3U_PIOB_BASE+SAM3U_PIO_PUDR_OFFSET) -#define SAM3U_PIOB_PUER (SAM3U_PIOB_BASE+SAM3U_PIO_PUER_OFFSET) -#define SAM3U_PIOB_PUSR (SAM3U_PIOB_BASE+SAM3U_PIO_PUSR_OFFSET) -#define SAM3U_PIOB_ABSR (SAM3U_PIOB_BASE+SAM3U_PIO_ABSR_OFFSET) -#define SAM3U_PIOB_SCIFSR (SAM3U_PIOB_BASE+SAM3U_PIO_SCIFSR_OFFSET) -#define SAM3U_PIOB_DIFSR (SAM3U_PIOB_BASE+SAM3U_PIO_DIFSR_OFFSET) -#define SAM3U_PIOB_IFDGSR (SAM3U_PIOB_BASE+SAM3U_PIO_IFDGSR_OFFSET) -#define SAM3U_PIOB_SCDR (SAM3U_PIOB_BASE+SAM3U_PIO_SCDR_OFFSET) -#define SAM3U_PIOB_OWER (SAM3U_PIOB_BASE+SAM3U_PIO_OWER_OFFSET) -#define SAM3U_PIOB_OWDR (SAM3U_PIOB_BASE+SAM3U_PIO_OWDR_OFFSET) -#define SAM3U_PIOB_OWSR (SAM3U_PIOB_BASE+SAM3U_PIO_OWSR_OFFSET) -#define SAM3U_PIOB_AIMER (SAM3U_PIOB_BASE+SAM3U_PIO_AIMER_OFFSET) -#define SAM3U_PIOB_AIMDR (SAM3U_PIOB_BASE+SAM3U_PIO_AIMDR_OFFSET) -#define SAM3U_PIOB_AIMMR (SAM3U_PIOB_BASE+SAM3U_PIO_AIMMR_OFFSET) -#define SAM3U_PIOB_ESR (SAM3U_PIOB_BASE+SAM3U_PIO_ESR_OFFSET) -#define SAM3U_PIOB_LSR (SAM3U_PIOB_BASE+SAM3U_PIO_LSR_OFFSET) -#define SAM3U_PIOB_ELSR (SAM3U_PIOB_BASE+SAM3U_PIO_ELSR_OFFSET) -#define SAM3U_PIOB_FELLSR (SAM3U_PIOB_BASE+SAM3U_PIO_FELLSR_OFFSET) -#define SAM3U_PIOB_REHLSR (SAM3U_PIOB_BASE+SAM3U_PIO_REHLSR_OFFSET) -#define SAM3U_PIOB_FRLHSR (SAM3U_PIOB_BASE+SAM3U_PIO_FRLHSR_OFFSET) -#define SAM3U_PIOB_LOCKSR (SAM3U_PIOB_BASE+SAM3U_PIO_LOCKSR_OFFSET) -#define SAM3U_PIOB_WPMR (SAM3U_PIOB_BASE+SAM3U_PIO_WPMR_OFFSET) -#define SAM3U_PIOB_WPSR (SAM3U_PIOB_BASE+SAM3U_PIO_WPSR_OFFSET) - -#define SAM3U_PIOC_PER (SAM3U_PIOC_BASE+SAM3U_PIO_PER_OFFSET) -#define SAM3U_PIOC_PDR_ (SAM3U_PIOC_BASE+SAM3U_PIO_PDR_OFFSET) -#define SAM3U_PIOC_PSR (SAM3U_PIOC_BASE+SAM3U_PIO_PSR_OFFSET) -#define SAM3U_PIOC_OER (SAM3U_PIOC_BASE+SAM3U_PIO_OER_OFFSET) -#define SAM3U_PIOC_ODR (SAM3U_PIOC_BASE+SAM3U_PIO_ODR_OFFSET) -#define SAM3U_PIOC_OSR (SAM3U_PIOC_BASE+SAM3U_PIO_OSR_OFFSET) -#define SAM3U_PIOC_IFER (SAM3U_PIOC_BASE+SAM3U_PIO_IFER_OFFSET) -#define SAM3U_PIOC_IFDR (SAM3U_PIOC_BASE+SAM3U_PIO_IFDR_OFFSET) -#define SAM3U_PIOC_IFSR (SAM3U_PIOC_BASE+SAM3U_PIO_IFSR_OFFSET) -#define SAM3U_PIOC_SODR (SAM3U_PIOC_BASE+SAM3U_PIO_SODR_OFFSET) -#define SAM3U_PIOC_CODR (SAM3U_PIOC_BASE+SAM3U_PIO_CODR_OFFSET) -#define SAM3U_PIOC_ODSR (SAM3U_PIOC_BASE+SAM3U_PIO_ODSR_OFFSET) -#define SAM3U_PIOC_PDSR (SAM3U_PIOC_BASE+SAM3U_PIO_PDSR_OFFSET) -#define SAM3U_PIOC_IER (SAM3U_PIOC_BASE+SAM3U_PIO_IER_OFFSET) -#define SAM3U_PIOC_IDR (SAM3U_PIOC_BASE+SAM3U_PIO_IDR_OFFSET) -#define SAM3U_PIOC_IMR (SAM3U_PIOC_BASE+SAM3U_PIO_IMR_OFFSET) -#define SAM3U_PIOC_ISR (SAM3U_PIOC_BASE+SAM3U_PIO_ISR_OFFSET) -#define SAM3U_PIOC_MDER (SAM3U_PIOC_BASE+SAM3U_PIO_MDER_OFFSET) -#define SAM3U_PIOC_MDDR (SAM3U_PIOC_BASE+SAM3U_PIO_MDDR_OFFSET) -#define SAM3U_PIOC_MDSR (SAM3U_PIOC_BASE+SAM3U_PIO_MDSR_OFFSET) -#define SAM3U_PIOC_PUDR (SAM3U_PIOC_BASE+SAM3U_PIO_PUDR_OFFSET) -#define SAM3U_PIOC_PUER (SAM3U_PIOC_BASE+SAM3U_PIO_PUER_OFFSET) -#define SAM3U_PIOC_PUSR (SAM3U_PIOC_BASE+SAM3U_PIO_PUSR_OFFSET) -#define SAM3U_PIOC_ABSR (SAM3U_PIOC_BASE+SAM3U_PIO_ABSR_OFFSET) -#define SAM3U_PIOC_SCIFSR (SAM3U_PIOC_BASE+SAM3U_PIO_SCIFSR_OFFSET) -#define SAM3U_PIOC_DIFSR (SAM3U_PIOC_BASE+SAM3U_PIO_DIFSR_OFFSET) -#define SAM3U_PIOC_IFDGSR (SAM3U_PIOC_BASE+SAM3U_PIO_IFDGSR_OFFSET) -#define SAM3U_PIOC_SCDR (SAM3U_PIOC_BASE+SAM3U_PIO_SCDR_OFFSET) -#define SAM3U_PIOC_OWER (SAM3U_PIOC_BASE+SAM3U_PIO_OWER_OFFSET) -#define SAM3U_PIOC_OWDR (SAM3U_PIOC_BASE+SAM3U_PIO_OWDR_OFFSET) -#define SAM3U_PIOC_OWSR (SAM3U_PIOC_BASE+SAM3U_PIO_OWSR_OFFSET) -#define SAM3U_PIOC_AIMER (SAM3U_PIOC_BASE+SAM3U_PIO_AIMER_OFFSET) -#define SAM3U_PIOC_AIMDR (SAM3U_PIOC_BASE+SAM3U_PIO_AIMDR_OFFSET) -#define SAM3U_PIOC_AIMMR (SAM3U_PIOC_BASE+SAM3U_PIO_AIMMR_OFFSET) -#define SAM3U_PIOC_ESR (SAM3U_PIOC_BASE+SAM3U_PIO_ESR_OFFSET) -#define SAM3U_PIOC_LSR (SAM3U_PIOC_BASE+SAM3U_PIO_LSR_OFFSET) -#define SAM3U_PIOC_ELSR (SAM3U_PIOC_BASE+SAM3U_PIO_ELSR_OFFSET) -#define SAM3U_PIOC_FELLSR (SAM3U_PIOC_BASE+SAM3U_PIO_FELLSR_OFFSET) -#define SAM3U_PIOC_REHLSR (SAM3U_PIOC_BASE+SAM3U_PIO_REHLSR_OFFSET) -#define SAM3U_PIOC_FRLHSR (SAM3U_PIOC_BASE+SAM3U_PIO_FRLHSR_OFFSET) -#define SAM3U_PIOC_LOCKSR (SAM3U_PIOC_BASE+SAM3U_PIO_LOCKSR_OFFSET) -#define SAM3U_PIOC_WPMR (SAM3U_PIOC_BASE+SAM3U_PIO_WPMR_OFFSET) -#define SAM3U_PIOC_WPSR (SAM3U_PIOC_BASE+SAM3U_PIO_WPSR_OFFSET) - -/* PIO register bit definitions *********************************************************/ - -/* Common bit definitions for ALMOST all IO registers (exceptions follow) */ - -#define PIO(n) (1<<(n)) /* Bit n: PIO n */ - -/* PIO Write Protect Mode Register */ - -#define PIO_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ -#define PIO_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ -#define PIO_WPMR_WPKEY_MASK (0xffffff << PIO_WPMR_WPKEY_SHIFT) - -/* PIO Write Protect Status Register */ - -#define PIO_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ -#define PIO_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ -#define PIO_WPSR_WPVSRC_MASK (0xffff << PIO_WPSR_WPVSRC_SHIFT) - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PIO_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_pio.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PIO_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_PIO_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* PIO register offsets *****************************************************************/ + +#define SAM3U_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */ +#define SAM3U_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */ +#define SAM3U_PIO_PSR_OFFSET 0x0008 /* PIO Status Register */ + /* 0x000c: Reserved */ +#define SAM3U_PIO_OER_OFFSET 0x0010 /* Output Enable Register */ +#define SAM3U_PIO_ODR_OFFSET 0x0014 /* Output Disable Register */ +#define SAM3U_PIO_OSR_OFFSET 0x0018 /* utput Status Register */ + /* 0x001c: Reserved */ +#define SAM3U_PIO_IFER_OFFSET 0x0020 /* Glitch Input Filter Enable Register */ +#define SAM3U_PIO_IFDR_OFFSET 0x0024 /* Glitch Input Filter Disable Register */ +#define SAM3U_PIO_IFSR_OFFSET 0x0028 /* Glitch Input Filter Status Register */ + /* 0x002c: Reserved */ +#define SAM3U_PIO_SODR_OFFSET 0x0030 /* Set Output Data Register */ +#define SAM3U_PIO_CODR_OFFSET 0x0034 /* Clear Output Data Register */ +#define SAM3U_PIO_ODSR_OFFSET 0x0038 /* Output Data Status Register */ +#define SAM3U_PIO_PDSR_OFFSET 0x003c /* Pin Data Status Register */ +#define SAM3U_PIO_IER_OFFSET 0x0040 /* Interrupt Enable Register */ +#define SAM3U_PIO_IDR_OFFSET 0x0044 /* Interrupt Disable Register */ +#define SAM3U_PIO_IMR_OFFSET 0x0048 /* Interrupt Mask Register */ +#define SAM3U_PIO_ISR_OFFSET 0x004c /* Interrupt Status Register */ +#define SAM3U_PIO_MDER_OFFSET 0x0050 /* Multi-driver Enable Register */ +#define SAM3U_PIO_MDDR_OFFSET 0x0054 /* Multi-driver Disable Register */ +#define SAM3U_PIO_MDSR_OFFSET 0x0058 /* Multi-driver Status Register */ + /* 0x005c: Reserved */ +#define SAM3U_PIO_PUDR_OFFSET 0x0060 /* Pull-up Disable Register */ +#define SAM3U_PIO_PUER_OFFSET 0x0064 /* Pull-up Enable Register */ +#define SAM3U_PIO_PUSR_OFFSET 0x0068 /* Pad Pull-up Status Register */ + /* 0x006c: Reserved */ +#define SAM3U_PIO_ABSR_OFFSET 0x0070 /* Peripheral AB Select Register */ + /* 0x0074-0x007c: Reserved */ +#define SAM3U_PIO_SCIFSR_OFFSET 0x0080 /* System Clock Glitch Input Filter Select Register */ +#define SAM3U_PIO_DIFSR_OFFSET 0x0084 /* Debouncing Input Filter Select Register */ +#define SAM3U_PIO_IFDGSR_OFFSET 0x0088 /* Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define SAM3U_PIO_SCDR_OFFSET 0x008c /* Slow Clock Divider Debouncing Register */ + /* 0x0090-0x009c: Reserved */ +#define SAM3U_PIO_OWER_OFFSET 0x00a0 /* Output Write Enable */ +#define SAM3U_PIO_OWDR_OFFSET 0x00a4 /* Output Write Disable */ +#define SAM3U_PIO_OWSR_OFFSET 0x00a8 /* Output Write Status Register */ + /* 0x00ac: Reserved */ +#define SAM3U_PIO_AIMER_OFFSET 0x00b0 /* Additional Interrupt Modes Enable Register */ +#define SAM3U_PIO_AIMDR_OFFSET 0x00b4 /* Additional Interrupt Modes Disables Register */ +#define SAM3U_PIO_AIMMR_OFFSET 0x00b8 /* Additional Interrupt Modes Mask Register */ + /* 0x00bc: Reserved */ +#define SAM3U_PIO_ESR_OFFSET 0x00c0 /* Edge Select Register */ +#define SAM3U_PIO_LSR_OFFSET 0x00c4 /* Level Select Register */ +#define SAM3U_PIO_ELSR_OFFSET 0x00c8 /* Edge/Level Status Register */ + /* 0x00cc: Reserved */ +#define SAM3U_PIO_FELLSR_OFFSET 0x00d0 /* Falling Edge/Low Level Select Register */ +#define SAM3U_PIO_REHLSR_OFFSET 0x00d4 /* Rising Edge/ High Level Select Register */ +#define SAM3U_PIO_FRLHSR_OFFSET 0x00d8 /* Fall/Rise - Low/High Status Register */ + /* 0x00dc: Reserved */ +#define SAM3U_PIO_LOCKSR_OFFSET 0x00e0 /* Lock Status */ +#define SAM3U_PIO_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ +#define SAM3U_PIO_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ + /* 0x00ec-0x00f8: Reserved */ + /* 0x0100-0x0144: Reserved */ + +/* PIO register adresses ****************************************************************/ + +#define PIOA (0) +#define PIOB (1) +#define PIOC (2) +#define NPIO (3) + +#define SAM3U_PIO_PER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PER_OFFSET) +#define SAM3U_PIO_PDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PDR_OFFSET) +#define SAM3U_PIO_PSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PSR_OFFSET) +#define SAM3U_PIO_OER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OER_OFFSET) +#define SAM3U_PIO_ODR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ODR_OFFSET) +#define SAM3U_PIO_OSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OSR_OFFSET) +#define SAM3U_PIO_IFER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFER_OFFSET) +#define SAM3U_PIO_IFDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFDR_OFFSET) +#define SAM3U_PIO_IFSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFSR_OFFSET) +#define SAM3U_PIO_SODR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_SODR_OFFSET) +#define SAM3U_PIO_CODR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_CODR_OFFSET) +#define SAM3U_PIO_ODSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ODSR_OFFSET) +#define SAM3U_PIO_PDSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PDSR_OFFSET) +#define SAM3U_PIO_IER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IER_OFFSET) +#define SAM3U_PIO_IDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IDR_OFFSET) +#define SAM3U_PIO_IMR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IMR_OFFSET) +#define SAM3U_PIO_ISR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ISR_OFFSET) +#define SAM3U_PIO_MDER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_MDER_OFFSET) +#define SAM3U_PIO_MDDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_MDDR_OFFSET) +#define SAM3U_PIO_MDSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_MDSR_OFFSET) +#define SAM3U_PIO_PUDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PUDR_OFFSET) +#define SAM3U_PIO_PUER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PUER_OFFSET) +#define SAM3U_PIO_PUSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_PUSR_OFFSET) +#define SAM3U_PIO_ABSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ABSR_OFFSET) +#define SAM3U_PIO_SCIFSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_SCIFSR_OFFSET) +#define SAM3U_PIO_DIFSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_DIFSR_OFFSET) +#define SAM3U_PIO_IFDGSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_IFDGSR_OFFSET) +#define SAM3U_PIO_SCDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_SCDR_OFFSET) +#define SAM3U_PIO_OWER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OWER_OFFSET) +#define SAM3U_PIO_OWDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OWDR_OFFSET) +#define SAM3U_PIO_OWSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_OWSR_OFFSET) +#define SAM3U_PIO_AIMER(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_AIMER_OFFSET) +#define SAM3U_PIO_AIMDR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_AIMDR_OFFSET) +#define SAM3U_PIO_AIMMR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_AIMMR_OFFSET) +#define SAM3U_PIO_ESR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ESR_OFFSET) +#define SAM3U_PIO_LSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_LSR_OFFSET) +#define SAM3U_PIO_ELSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_ELSR_OFFSET) +#define SAM3U_PIO_FELLSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_FELLSR_OFFSET) +#define SAM3U_PIO_REHLSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_REHLSR_OFFSET) +#define SAM3U_PIO_FRLHSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_FRLHSR_OFFSET) +#define SAM3U_PIO_LOCKSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_LOCKSR_OFFSET) +#define SAM3U_PIO_WPMR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_WPMR_OFFSET) +#define SAM3U_PIO_WPSR(n) (SAM3U_PIO_BASE(n)+SAM3U_PIO_WPSR_OFFSET) + +#define SAM3U_PIOA_PER (SAM3U_PIOA_BASE+SAM3U_PIO_PER_OFFSET) +#define SAM3U_PIOA_PDR_ (SAM3U_PIOA_BASE+SAM3U_PIO_PDR_OFFSET) +#define SAM3U_PIOA_PSR (SAM3U_PIOA_BASE+SAM3U_PIO_PSR_OFFSET) +#define SAM3U_PIOA_OER (SAM3U_PIOA_BASE+SAM3U_PIO_OER_OFFSET) +#define SAM3U_PIOA_ODR (SAM3U_PIOA_BASE+SAM3U_PIO_ODR_OFFSET) +#define SAM3U_PIOA_OSR (SAM3U_PIOA_BASE+SAM3U_PIO_OSR_OFFSET) +#define SAM3U_PIOA_IFER (SAM3U_PIOA_BASE+SAM3U_PIO_IFER_OFFSET) +#define SAM3U_PIOA_IFDR (SAM3U_PIOA_BASE+SAM3U_PIO_IFDR_OFFSET) +#define SAM3U_PIOA_IFSR (SAM3U_PIOA_BASE+SAM3U_PIO_IFSR_OFFSET) +#define SAM3U_PIOA_SODR (SAM3U_PIOA_BASE+SAM3U_PIO_SODR_OFFSET) +#define SAM3U_PIOA_CODR (SAM3U_PIOA_BASE+SAM3U_PIO_CODR_OFFSET) +#define SAM3U_PIOA_ODSR (SAM3U_PIOA_BASE+SAM3U_PIO_ODSR_OFFSET) +#define SAM3U_PIOA_PDSR (SAM3U_PIOA_BASE+SAM3U_PIO_PDSR_OFFSET) +#define SAM3U_PIOA_IER (SAM3U_PIOA_BASE+SAM3U_PIO_IER_OFFSET) +#define SAM3U_PIOA_IDR (SAM3U_PIOA_BASE+SAM3U_PIO_IDR_OFFSET) +#define SAM3U_PIOA_IMR (SAM3U_PIOA_BASE+SAM3U_PIO_IMR_OFFSET) +#define SAM3U_PIOA_ISR (SAM3U_PIOA_BASE+SAM3U_PIO_ISR_OFFSET) +#define SAM3U_PIOA_MDER (SAM3U_PIOA_BASE+SAM3U_PIO_MDER_OFFSET) +#define SAM3U_PIOA_MDDR (SAM3U_PIOA_BASE+SAM3U_PIO_MDDR_OFFSET) +#define SAM3U_PIOA_MDSR (SAM3U_PIOA_BASE+SAM3U_PIO_MDSR_OFFSET) +#define SAM3U_PIOA_PUDR (SAM3U_PIOA_BASE+SAM3U_PIO_PUDR_OFFSET) +#define SAM3U_PIOA_PUER (SAM3U_PIOA_BASE+SAM3U_PIO_PUER_OFFSET) +#define SAM3U_PIOA_PUSR (SAM3U_PIOA_BASE+SAM3U_PIO_PUSR_OFFSET) +#define SAM3U_PIOA_ABSR (SAM3U_PIOA_BASE+SAM3U_PIO_ABSR_OFFSET) +#define SAM3U_PIOA_SCIFSR (SAM3U_PIOA_BASE+SAM3U_PIO_SCIFSR_OFFSET) +#define SAM3U_PIOA_DIFSR (SAM3U_PIOA_BASE+SAM3U_PIO_DIFSR_OFFSET) +#define SAM3U_PIOA_IFDGSR (SAM3U_PIOA_BASE+SAM3U_PIO_IFDGSR_OFFSET) +#define SAM3U_PIOA_SCDR (SAM3U_PIOA_BASE+SAM3U_PIO_SCDR_OFFSET) +#define SAM3U_PIOA_OWER (SAM3U_PIOA_BASE+SAM3U_PIO_OWER_OFFSET) +#define SAM3U_PIOA_OWDR (SAM3U_PIOA_BASE+SAM3U_PIO_OWDR_OFFSET) +#define SAM3U_PIOA_OWSR (SAM3U_PIOA_BASE+SAM3U_PIO_OWSR_OFFSET) +#define SAM3U_PIOA_AIMER (SAM3U_PIOA_BASE+SAM3U_PIO_AIMER_OFFSET) +#define SAM3U_PIOA_AIMDR (SAM3U_PIOA_BASE+SAM3U_PIO_AIMDR_OFFSET) +#define SAM3U_PIOA_AIMMR (SAM3U_PIOA_BASE+SAM3U_PIO_AIMMR_OFFSET) +#define SAM3U_PIOA_ESR (SAM3U_PIOA_BASE+SAM3U_PIO_ESR_OFFSET) +#define SAM3U_PIOA_LSR (SAM3U_PIOA_BASE+SAM3U_PIO_LSR_OFFSET) +#define SAM3U_PIOA_ELSR (SAM3U_PIOA_BASE+SAM3U_PIO_ELSR_OFFSET) +#define SAM3U_PIOA_FELLSR (SAM3U_PIOA_BASE+SAM3U_PIO_FELLSR_OFFSET) +#define SAM3U_PIOA_REHLSR (SAM3U_PIOA_BASE+SAM3U_PIO_REHLSR_OFFSET) +#define SAM3U_PIOA_FRLHSR (SAM3U_PIOA_BASE+SAM3U_PIO_FRLHSR_OFFSET) +#define SAM3U_PIOA_LOCKSR (SAM3U_PIOA_BASE+SAM3U_PIO_LOCKSR_OFFSET) +#define SAM3U_PIOA_WPMR (SAM3U_PIOA_BASE+SAM3U_PIO_WPMR_OFFSET) +#define SAM3U_PIOA_WPSR (SAM3U_PIOA_BASE+SAM3U_PIO_WPSR_OFFSET) + +#define SAM3U_PIOB_PER (SAM3U_PIOB_BASE+SAM3U_PIO_PER_OFFSET) +#define SAM3U_PIOB_PDR_ (SAM3U_PIOB_BASE+SAM3U_PIO_PDR_OFFSET) +#define SAM3U_PIOB_PSR (SAM3U_PIOB_BASE+SAM3U_PIO_PSR_OFFSET) +#define SAM3U_PIOB_OER (SAM3U_PIOB_BASE+SAM3U_PIO_OER_OFFSET) +#define SAM3U_PIOB_ODR (SAM3U_PIOB_BASE+SAM3U_PIO_ODR_OFFSET) +#define SAM3U_PIOB_OSR (SAM3U_PIOB_BASE+SAM3U_PIO_OSR_OFFSET) +#define SAM3U_PIOB_IFER (SAM3U_PIOB_BASE+SAM3U_PIO_IFER_OFFSET) +#define SAM3U_PIOB_IFDR (SAM3U_PIOB_BASE+SAM3U_PIO_IFDR_OFFSET) +#define SAM3U_PIOB_IFSR (SAM3U_PIOB_BASE+SAM3U_PIO_IFSR_OFFSET) +#define SAM3U_PIOB_SODR (SAM3U_PIOB_BASE+SAM3U_PIO_SODR_OFFSET) +#define SAM3U_PIOB_CODR (SAM3U_PIOB_BASE+SAM3U_PIO_CODR_OFFSET) +#define SAM3U_PIOB_ODSR (SAM3U_PIOB_BASE+SAM3U_PIO_ODSR_OFFSET) +#define SAM3U_PIOB_PDSR (SAM3U_PIOB_BASE+SAM3U_PIO_PDSR_OFFSET) +#define SAM3U_PIOB_IER (SAM3U_PIOB_BASE+SAM3U_PIO_IER_OFFSET) +#define SAM3U_PIOB_IDR (SAM3U_PIOB_BASE+SAM3U_PIO_IDR_OFFSET) +#define SAM3U_PIOB_IMR (SAM3U_PIOB_BASE+SAM3U_PIO_IMR_OFFSET) +#define SAM3U_PIOB_ISR (SAM3U_PIOB_BASE+SAM3U_PIO_ISR_OFFSET) +#define SAM3U_PIOB_MDER (SAM3U_PIOB_BASE+SAM3U_PIO_MDER_OFFSET) +#define SAM3U_PIOB_MDDR (SAM3U_PIOB_BASE+SAM3U_PIO_MDDR_OFFSET) +#define SAM3U_PIOB_MDSR (SAM3U_PIOB_BASE+SAM3U_PIO_MDSR_OFFSET) +#define SAM3U_PIOB_PUDR (SAM3U_PIOB_BASE+SAM3U_PIO_PUDR_OFFSET) +#define SAM3U_PIOB_PUER (SAM3U_PIOB_BASE+SAM3U_PIO_PUER_OFFSET) +#define SAM3U_PIOB_PUSR (SAM3U_PIOB_BASE+SAM3U_PIO_PUSR_OFFSET) +#define SAM3U_PIOB_ABSR (SAM3U_PIOB_BASE+SAM3U_PIO_ABSR_OFFSET) +#define SAM3U_PIOB_SCIFSR (SAM3U_PIOB_BASE+SAM3U_PIO_SCIFSR_OFFSET) +#define SAM3U_PIOB_DIFSR (SAM3U_PIOB_BASE+SAM3U_PIO_DIFSR_OFFSET) +#define SAM3U_PIOB_IFDGSR (SAM3U_PIOB_BASE+SAM3U_PIO_IFDGSR_OFFSET) +#define SAM3U_PIOB_SCDR (SAM3U_PIOB_BASE+SAM3U_PIO_SCDR_OFFSET) +#define SAM3U_PIOB_OWER (SAM3U_PIOB_BASE+SAM3U_PIO_OWER_OFFSET) +#define SAM3U_PIOB_OWDR (SAM3U_PIOB_BASE+SAM3U_PIO_OWDR_OFFSET) +#define SAM3U_PIOB_OWSR (SAM3U_PIOB_BASE+SAM3U_PIO_OWSR_OFFSET) +#define SAM3U_PIOB_AIMER (SAM3U_PIOB_BASE+SAM3U_PIO_AIMER_OFFSET) +#define SAM3U_PIOB_AIMDR (SAM3U_PIOB_BASE+SAM3U_PIO_AIMDR_OFFSET) +#define SAM3U_PIOB_AIMMR (SAM3U_PIOB_BASE+SAM3U_PIO_AIMMR_OFFSET) +#define SAM3U_PIOB_ESR (SAM3U_PIOB_BASE+SAM3U_PIO_ESR_OFFSET) +#define SAM3U_PIOB_LSR (SAM3U_PIOB_BASE+SAM3U_PIO_LSR_OFFSET) +#define SAM3U_PIOB_ELSR (SAM3U_PIOB_BASE+SAM3U_PIO_ELSR_OFFSET) +#define SAM3U_PIOB_FELLSR (SAM3U_PIOB_BASE+SAM3U_PIO_FELLSR_OFFSET) +#define SAM3U_PIOB_REHLSR (SAM3U_PIOB_BASE+SAM3U_PIO_REHLSR_OFFSET) +#define SAM3U_PIOB_FRLHSR (SAM3U_PIOB_BASE+SAM3U_PIO_FRLHSR_OFFSET) +#define SAM3U_PIOB_LOCKSR (SAM3U_PIOB_BASE+SAM3U_PIO_LOCKSR_OFFSET) +#define SAM3U_PIOB_WPMR (SAM3U_PIOB_BASE+SAM3U_PIO_WPMR_OFFSET) +#define SAM3U_PIOB_WPSR (SAM3U_PIOB_BASE+SAM3U_PIO_WPSR_OFFSET) + +#define SAM3U_PIOC_PER (SAM3U_PIOC_BASE+SAM3U_PIO_PER_OFFSET) +#define SAM3U_PIOC_PDR_ (SAM3U_PIOC_BASE+SAM3U_PIO_PDR_OFFSET) +#define SAM3U_PIOC_PSR (SAM3U_PIOC_BASE+SAM3U_PIO_PSR_OFFSET) +#define SAM3U_PIOC_OER (SAM3U_PIOC_BASE+SAM3U_PIO_OER_OFFSET) +#define SAM3U_PIOC_ODR (SAM3U_PIOC_BASE+SAM3U_PIO_ODR_OFFSET) +#define SAM3U_PIOC_OSR (SAM3U_PIOC_BASE+SAM3U_PIO_OSR_OFFSET) +#define SAM3U_PIOC_IFER (SAM3U_PIOC_BASE+SAM3U_PIO_IFER_OFFSET) +#define SAM3U_PIOC_IFDR (SAM3U_PIOC_BASE+SAM3U_PIO_IFDR_OFFSET) +#define SAM3U_PIOC_IFSR (SAM3U_PIOC_BASE+SAM3U_PIO_IFSR_OFFSET) +#define SAM3U_PIOC_SODR (SAM3U_PIOC_BASE+SAM3U_PIO_SODR_OFFSET) +#define SAM3U_PIOC_CODR (SAM3U_PIOC_BASE+SAM3U_PIO_CODR_OFFSET) +#define SAM3U_PIOC_ODSR (SAM3U_PIOC_BASE+SAM3U_PIO_ODSR_OFFSET) +#define SAM3U_PIOC_PDSR (SAM3U_PIOC_BASE+SAM3U_PIO_PDSR_OFFSET) +#define SAM3U_PIOC_IER (SAM3U_PIOC_BASE+SAM3U_PIO_IER_OFFSET) +#define SAM3U_PIOC_IDR (SAM3U_PIOC_BASE+SAM3U_PIO_IDR_OFFSET) +#define SAM3U_PIOC_IMR (SAM3U_PIOC_BASE+SAM3U_PIO_IMR_OFFSET) +#define SAM3U_PIOC_ISR (SAM3U_PIOC_BASE+SAM3U_PIO_ISR_OFFSET) +#define SAM3U_PIOC_MDER (SAM3U_PIOC_BASE+SAM3U_PIO_MDER_OFFSET) +#define SAM3U_PIOC_MDDR (SAM3U_PIOC_BASE+SAM3U_PIO_MDDR_OFFSET) +#define SAM3U_PIOC_MDSR (SAM3U_PIOC_BASE+SAM3U_PIO_MDSR_OFFSET) +#define SAM3U_PIOC_PUDR (SAM3U_PIOC_BASE+SAM3U_PIO_PUDR_OFFSET) +#define SAM3U_PIOC_PUER (SAM3U_PIOC_BASE+SAM3U_PIO_PUER_OFFSET) +#define SAM3U_PIOC_PUSR (SAM3U_PIOC_BASE+SAM3U_PIO_PUSR_OFFSET) +#define SAM3U_PIOC_ABSR (SAM3U_PIOC_BASE+SAM3U_PIO_ABSR_OFFSET) +#define SAM3U_PIOC_SCIFSR (SAM3U_PIOC_BASE+SAM3U_PIO_SCIFSR_OFFSET) +#define SAM3U_PIOC_DIFSR (SAM3U_PIOC_BASE+SAM3U_PIO_DIFSR_OFFSET) +#define SAM3U_PIOC_IFDGSR (SAM3U_PIOC_BASE+SAM3U_PIO_IFDGSR_OFFSET) +#define SAM3U_PIOC_SCDR (SAM3U_PIOC_BASE+SAM3U_PIO_SCDR_OFFSET) +#define SAM3U_PIOC_OWER (SAM3U_PIOC_BASE+SAM3U_PIO_OWER_OFFSET) +#define SAM3U_PIOC_OWDR (SAM3U_PIOC_BASE+SAM3U_PIO_OWDR_OFFSET) +#define SAM3U_PIOC_OWSR (SAM3U_PIOC_BASE+SAM3U_PIO_OWSR_OFFSET) +#define SAM3U_PIOC_AIMER (SAM3U_PIOC_BASE+SAM3U_PIO_AIMER_OFFSET) +#define SAM3U_PIOC_AIMDR (SAM3U_PIOC_BASE+SAM3U_PIO_AIMDR_OFFSET) +#define SAM3U_PIOC_AIMMR (SAM3U_PIOC_BASE+SAM3U_PIO_AIMMR_OFFSET) +#define SAM3U_PIOC_ESR (SAM3U_PIOC_BASE+SAM3U_PIO_ESR_OFFSET) +#define SAM3U_PIOC_LSR (SAM3U_PIOC_BASE+SAM3U_PIO_LSR_OFFSET) +#define SAM3U_PIOC_ELSR (SAM3U_PIOC_BASE+SAM3U_PIO_ELSR_OFFSET) +#define SAM3U_PIOC_FELLSR (SAM3U_PIOC_BASE+SAM3U_PIO_FELLSR_OFFSET) +#define SAM3U_PIOC_REHLSR (SAM3U_PIOC_BASE+SAM3U_PIO_REHLSR_OFFSET) +#define SAM3U_PIOC_FRLHSR (SAM3U_PIOC_BASE+SAM3U_PIO_FRLHSR_OFFSET) +#define SAM3U_PIOC_LOCKSR (SAM3U_PIOC_BASE+SAM3U_PIO_LOCKSR_OFFSET) +#define SAM3U_PIOC_WPMR (SAM3U_PIOC_BASE+SAM3U_PIO_WPMR_OFFSET) +#define SAM3U_PIOC_WPSR (SAM3U_PIOC_BASE+SAM3U_PIO_WPSR_OFFSET) + +/* PIO register bit definitions *********************************************************/ + +/* Common bit definitions for ALMOST all IO registers (exceptions follow) */ + +#define PIO(n) (1<<(n)) /* Bit n: PIO n */ + +/* PIO Write Protect Mode Register */ + +#define PIO_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define PIO_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define PIO_WPMR_WPKEY_MASK (0xffffff << PIO_WPMR_WPKEY_SHIFT) + +/* PIO Write Protect Status Register */ + +#define PIO_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +#define PIO_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define PIO_WPSR_WPVSRC_MASK (0xffff << PIO_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PIO_H */ diff --git a/arch/arm/src/sam3u/sam3u_pmc.h b/arch/arm/src/sam3u/sam3u_pmc.h index 3fde5b642ba6ccdcc6f94ed0c28de2553d72161e..75545f239469f2a4b9ead36bbbc5c499803d0a31 100644 --- a/arch/arm/src/sam3u/sam3u_pmc.h +++ b/arch/arm/src/sam3u/sam3u_pmc.h @@ -1,316 +1,316 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_pmc.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PMC_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_PMC_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* PMC register offsets *****************************************************************/ - -#define SAM3U_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */ -#define SAM3U_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */ -#define SAM3U_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */ - /* 0x000c: Reserved */ -#define SAM3U_PMC_PCER_OFFSET 0x0010 /* Peripheral Clock Enable Register */ -#define SAM3U_PMC_PCDR_OFFSET 0x0014 /* Peripheral Clock Disable Register */ -#define SAM3U_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */ -#define SAM3U_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */ -#define SAM3U_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */ -#define SAM3U_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */ -#define SAM3U_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */ - /* 0x002c: Reserved */ -#define SAM3U_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */ - /* 0x0034-0x003C Reserved */ -#define SAM3U_PMC_PCK_OFFSET(n) (0x0040+((n)<<2)) -#define SAM3U_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */ -#define SAM3U_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */ -#define SAM3U_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */ - /* 0x004c-0x005c: Reserved */ -#define SAM3U_PMC_IER_OFFSET 0x0060 /* Interrupt Enable Register */ -#define SAM3U_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */ -#define SAM3U_PMC_SR_OFFSET 0x0068 /* Status Register */ -#define SAM3U_PMC_IMR_OFFSET 0x006c /* Interrupt Mask Register */ -#define SAM3U_PMC_FSMR_OFFSET 0x0070 /* Fast Startup Mode Register */ -#define SAM3U_PMC_FSPR_OFFSET 0x0074 /* Fast Startup Polarity Register */ -#define SAM3U_PMC_FOCR_OFFSET 0x0078 /* Fault Output Clear Register */ - /* 0x007c-0x00fc: Reserved */ -#define SAM3U_PMC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ -#define SAM3U_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ - -/* PMC register adresses ****************************************************************/ - -#define SAM3U_PMC_SCER (SAM3U_PMC_BASE+SAM3U_PMC_SCER_OFFSET) -#define SAM3U_PMC_SCDR (SAM3U_PMC_BASE+SAM3U_PMC_SCDR_OFFSET) -#define SAM3U_PMC_SCSR (SAM3U_PMC_BASE+SAM3U_PMC_SCSR_OFFSET) -#define SAM3U_PMC_PCER (SAM3U_PMC_BASE+SAM3U_PMC_PCER_OFFSET) -#define SAM3U_PMC_PCDR (SAM3U_PMC_BASE+SAM3U_PMC_PCDR_OFFSET) -#define SAM3U_PMC_PCSR (SAM3U_PMC_BASE+SAM3U_PMC_PCSR_OFFSET) -#define SAM3U_CKGR_UCKR (SAM3U_PMC_BASE+SAM3U_CKGR_UCKR_OFFSET) -#define SAM3U_CKGR_MOR (SAM3U_PMC_BASE+SAM3U_CKGR_MOR_OFFSET) -#define SAM3U_CKGR_MCFR (SAM3U_PMC_BASE+SAM3U_CKGR_MCFR_OFFSET) -#define SAM3U_CKGR_PLLAR (SAM3U_PMC_BASE+SAM3U_CKGR_PLLAR_OFFSET) -#define SAM3U_PMC_MCKR (SAM3U_PMC_BASE+SAM3U_PMC_MCKR_OFFSET) -#define SAM3U_PMC_PCK(n) (SAM3U_PMC_BASE+SAM3U_PMC_PCK_OFFSET(n)) -#define SAM3U_PMC_PCK0 (SAM3U_PMC_BASE+SAM3U_PMC_PCK0_OFFSET) -#define SAM3U_PMC_PCK1 (SAM3U_PMC_BASE+SAM3U_PMC_PCK1_OFFSET) -#define SAM3U_PMC_PCK2 (SAM3U_PMC_BASE+SAM3U_PMC_PCK2_OFFSET) -#define SAM3U_PMC_IER (SAM3U_PMC_BASE+SAM3U_PMC_IER_OFFSET) -#define SAM3U_PMC_IDR (SAM3U_PMC_BASE+SAM3U_PMC_IDR_OFFSET) -#define SAM3U_PMC_SR (SAM3U_PMC_BASE+SAM3U_PMC_SR_OFFSET) -#define SAM3U_PMC_IMR (SAM3U_PMC_BASE+SAM3U_PMC_IMR_OFFSET) -#define SAM3U_PMC_FSMR (SAM3U_PMC_BASE+SAM3U_PMC_FSMR_OFFSET) -#define SAM3U_PMC_FSPR (SAM3U_PMC_BASE+SAM3U_PMC_FSPR_OFFSET) -#define SAM3U_PMC_FOCR (SAM3U_PMC_BASE+SAM3U_PMC_FOCR_OFFSET) -#define SAM3U_PMC_WPMR (SAM3U_PMC_BASE+SAM3U_PMC_WPMR_OFFSET) -#define SAM3U_PMC_WPSR (SAM3U_PMC_BASE+SAM3U_PMC_WPSR_OFFSET) - -/* PMC register bit definitions *********************************************************/ - -/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System - * Clock Status Register common bit-field definitions - */ - -#define PMC_PCK(n) (1 <<((n)+8) -#define PMC_PCK0 (1 << 8) /* Bit 8: Programmable Clock 0 Output Enable */ -#define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output Enable */ -#define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output Enable */ - -/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC - * Peripheral Clock Status Register common bit-field definitions. - */ - -#define PMC_PID(n) (1<<(n)) -#define PMC_PID2 (1 << 2) /* Bit 2: Peripheral Clock 2 Enable */ -#define PMC_PID3 (1 << 3) /* Bit 3: Peripheral Clock 3 Enable */ -#define PMC_PID4 (1 << 4) /* Bit 4: Peripheral Clock 4 Enable */ -#define PMC_PID5 (1 << 5) /* Bit 5: Peripheral Clock 5 Enable */ -#define PMC_PID6 (1 << 6) /* Bit 6: Peripheral Clock 6 Enable */ -#define PMC_PID7 (1 << 7) /* Bit 7: Peripheral Clock 7 Enable */ -#define PMC_PID8 (1 << 8) /* Bit 8: Peripheral Clock 8 Enable */ -#define PMC_PID9 (1 << 9) /* Bit 9: Peripheral Clock 9 Enable */ -#define PMC_PID10 (1 << 10) /* Bit 10: Peripheral Clock 10 Enable */ -#define PMC_PID11 (1 << 11) /* Bit 11: Peripheral Clock 11 Enable */ -#define PMC_PID12 (1 << 12) /* Bit 12: Peripheral Clock 12 Enable */ -#define PMC_PID13 (1 << 13) /* Bit 13: Peripheral Clock 13 Enable */ -#define PMC_PID14 (1 << 14) /* Bit 14: Peripheral Clock 14 Enable */ -#define PMC_PID15 (1 << 15) /* Bit 15: Peripheral Clock 15 Enable */ -#define PMC_PID16 (1 << 16) /* Bit 16: Peripheral Clock 16 Enable */ -#define PMC_PID17 (1 << 17) /* Bit 17: Peripheral Clock 17 Enable */ -#define PMC_PID18 (1 << 18) /* Bit 18: Peripheral Clock 18 Enable */ -#define PMC_PID19 (1 << 19) /* Bit 19: Peripheral Clock 19 Enable */ -#define PMC_PID20 (1 << 20) /* Bit 20: Peripheral Clock 20 Enable */ -#define PMC_PID21 (1 << 21) /* Bit 21: Peripheral Clock 21 Enable */ -#define PMC_PID22 (1 << 22) /* Bit 22: Peripheral Clock 22 Enable */ -#define PMC_PID23 (1 << 23) /* Bit 23: Peripheral Clock 23 Enable */ -#define PMC_PID24 (1 << 24) /* Bit 24: Peripheral Clock 24 Enable */ -#define PMC_PID25 (1 << 25) /* Bit 25: Peripheral Clock 25 Enable */ -#define PMC_PID26 (1 << 26) /* Bit 26: Peripheral Clock 26 Enable */ -#define PMC_PID27 (1 << 27) /* Bit 27: Peripheral Clock 27 Enable */ -#define PMC_PID28 (1 << 28) /* Bit 28: Peripheral Clock 28 Enable */ -#define PMC_PID29 (1 << 29) /* Bit 29: Peripheral Clock 29 Enable */ -#define PMC_PID30 (1 << 30) /* Bit 30: Peripheral Clock 30 Enable */ -#define PMC_PID31 (1 << 31) /* Bit 31: Peripheral Clock 31 Enable */ - -/* PMC UTMI Clock Configuration Register */ - -#define CKGR_UCKR_UPLLEN (1 << 16) /* Bit 16: UTMI PLL Enable */ -#define CKGR_UCKR_UPLLCOUNT_SHIFT (20) /* Bits 20-23: UTMI PLL Start-up Time */ -#define CKGR_UCKR_UPLLCOUNT_MASK (15 << CKGR_UCKR_UPLLCOUNT_SHIFT) - -/* PMC Clock Generator Main Oscillator Register */ - -#define CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */ -#define CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */ -#define CKGR_MOR_WAITMODE (1 << 2) /* Bit 2: Wait Mode Command */ -#define CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */ -#define CKGR_MOR_MOSCRCF_SHIFT (4) /* Bits 4-6: Main On-Chip RC Oscillator Frequency Selection */ -#define CKGR_MOR_MOSCRCF_MASK (7 << CKGR_MOR_MOSCRCF_SHIFT) -#define CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-16: Main Crystal Oscillator Start-up Time */ -#define CKGR_MOR_MOSCXTST_MASK (0x1ff << CKGR_MOR_MOSCXTST_SHIFT) -#define CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */ -#define CKGR_MOR_KEY_MASK (0xff << CKGR_MOR_KEY_SHIFT) -#define CKGR_MOR_MOSCSEL (1 << 24) /* Bit 24: Main Oscillator Selection */ -#define CKGR_MOR_CFDEN (1 << 25) /* Bit 25: Clock Failure Detector Enable */ - - -/* PMC Clock Generator Main Clock Frequency Register */ - -#define CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */ -#define CKGR_MCFR_MAINF_MASK (0xffff << CKGR_MCFR_MAINF_SHIFT) -#define CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */ - -/* PMC Clock Generator PLLA Register */ - -#define CKGR_PLLAR_DIVA_SHIFT (0) /* Bits 0-7: Divider */ -#define CKGR_PLLAR_DIVA_MASK (0xff << CKGR_PLLAR_DIVA_SHIFT) -# define CKGR_PLLAR_DIVA_ZERO (0 << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is 0 */ -# define CKGR_PLLAR_DIVA_BYPASS (1 << CKGR_PLLAR_DIVA_SHIFT) /* Divider is bypassed (DIVA=1) */ -# define CKGR_PLLAR_DIVA(n) ((n) << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is DIVA=n, n=2..255 */ -#define CKGR_PLLAR_PLLACOUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */ -#define CKGR_PLLAR_PLLACOUNT_MASK (63 << CKGR_PLLAR_PLLACOUNT_SHIFT) -#define CKGR_PLLAR_STMODE_SHIFT (14) /* Bits 14-15: Start Mode */ -#define CKGR_PLLAR_STMODE_MASK (3 << CKGR_PLLAR_STMODE_SHIFT) -# define CKGR_PLLAR_STMODE_FAST (0 << CKGR_PLLAR_STMODE_SHIFT) /* Fast Startup */ -# define CKGR_PLLAR_STMODE_NORMAL (2 << CKGR_PLLAR_STMODE_SHIFT) /* Normal Startup */ -#define CKGR_PLLAR_MULA_SHIFT (16) /* Bits 16-26: PLLA Multiplier */ -#define CKGR_PLLAR_MULA_MASK (0x7ff << CKGR_PLLAR_MULA_SHIFT) -#define CKGR_PLLAR_ONE (1 << 29) /* Bit 29: Always one */ - -/* PMC Master Clock Register */ - -#define PMC_MCKR_CSS_SHIFT (0) /* Bits 0-1: Master Clock Source Selection */ -#define PMC_MCKR_CSS_MASK (3 << PMC_MCKR_CSS_SHIFT) -# define PMC_MCKR_CSS_SLOW (0 << PMC_MCKR_CSS_SHIFT) /* Slow Clock */ -# define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */ -# define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */ -# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */ -#define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */ -#define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT) -# define PMC_MCKR_PRES_DIV1 (0 << PMC_MCKR_PRES_SHIFT) /* Selected clock */ -# define PMC_MCKR_PRES_DIV2 (1 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 2 */ -# define PMC_MCKR_PRES_DIV4 (2 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 4 */ -# define PMC_MCKR_PRES_DIV8 (3 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 8 */ -# define PMC_MCKR_PRES_DIV16 (4 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 16 */ -# define PMC_MCKR_PRES_DIV32K (5 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 32 */ -# define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */ -# define PMC_MCKR_PRES_DIV3 (7 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 3 */ -#define PMC_MCKR_UPLLDIV (1 << 13) /* Bit 13: UPLL Divider */ - -/* PMC Programmable Clock Register (0,1,2) */ - -#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */ -#define PMC_PCK_CSS_MASK (7 << PMC_PCK_CSS_MASK) -# define PMC_PCK_CSS_SLOW (0 << PMC_PCK_CSS_MASK) /* Slow Clock */ -# define PMC_PCK_CSS_MAIN (1 << PMC_PCK_CSS_MASK) /* Main Clock */ -# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_MASK) /* PLLA Clock */ -# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_MASK) /* UPLL Clock */ -# define PMC_PCK_CSS_MASTER (4 << PMC_PCK_CSS_MASK) /* Master Clock */ -#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */ -#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT) -# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */ -# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */ -# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */ -# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */ -# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */ -# define PMC_PCK_PRES_DIV32K (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */ -# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */ - -/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register, - * and PMC Interrupt Mask Register common bit-field definitions - */ - -#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */ -#define PMC_INT_LOCKA (1 << 1) /* Bit 1: PLL A Lock Interrupt */ -#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */ -#define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */ -#define PMC_SR_OSCSELS (1 << 7) /* Bit 7: Slow Clock Oscillator Selection (SR only) */ -#define PMC_INT_PCKRDY(n) (1<<((n)+8) -#define PMC_INT_PCKRDY0 (1 << 8) /* Bit 8: Programmable Clock Ready 0 Interrupt */ -#define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */ -#define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */ -#define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */ -#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */ -#define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */ -#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */ -#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */ - -/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register common bit-field - * definitions - */ - -#define PMC_FSTI(n) (1<<(n)) -#define PMC_FSTI0 (1 << 0) /* Bit 0: Fast Startup Input 0 */ -#define PMC_FSTI1 (1 << 1) /* Bit 1: Fast Startup Input 1 */ -#define PMC_FSTI2 (1 << 2) /* Bit 2: Fast Startup Input 2 */ -#define PMC_FSTI3 (1 << 3) /* Bit 3: Fast Startup Input 3 */ -#define PMC_FSTI4 (1 << 4) /* Bit 4: Fast Startup Input 4 */ -#define PMC_FSTI5 (1 << 5) /* Bit 5: Fast Startup Input 5 */ -#define PMC_FSTI6 (1 << 6) /* Bit 6: Fast Startup Input 6 */ -#define PMC_FSTI7 (1 << 7) /* Bit 7: Fast Startup Input 7 */ -#define PMC_FSTI8 (1 << 8) /* Bit 8: Fast Startup Input 8 */ -#define PMC_FSTI9 (1 << 9) /* Bit 9: Fast Startup Input 9 */ -#define PMC_FSTI10 (1 << 10) /* Bit 10: Fast Startup Input 10 */ -#define PMC_FSTI11 (1 << 11) /* Bit 11: Fast Startup Input 11 */ -#define PMC_FSTI12 (1 << 12) /* Bit 12: Fast Startup Input 12 */ -#define PMC_FSTI13 (1 << 13) /* Bit 13: Fast Startup Input 13 */ -#define PMC_FSTI14 (1 << 14) /* Bit 14: Fast Startup Input 14 */ -#define PMC_FSTI15 (1 << 15) /* Bit 15: Fast Startup Input 15 */ - -#define PMC_FSMR_RTTAL (1 << 16) /* Bit 16: RTT Alarm Enable (MR only) */ -#define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable (MR only) */ -#define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable (MR only) */ -#define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low Power Mode (MR only) */ - -/* PMC Fault Output Clear Register */ - -#define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */ - -/* PMC Write Protect Mode Register */ - -#define PMC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ -#define PMC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ -#define PMC_WPMR_WPKEY_MASK (0x00ffffff << PMC_WPMR_WPKEY_SHIFT) - -/* PMC Write Protect Status Register */ - -#define PMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ -#define PMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ -#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT) - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PMC_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_pmc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PMC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_PMC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* PMC register offsets *****************************************************************/ + +#define SAM3U_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */ +#define SAM3U_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */ +#define SAM3U_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */ + /* 0x000c: Reserved */ +#define SAM3U_PMC_PCER_OFFSET 0x0010 /* Peripheral Clock Enable Register */ +#define SAM3U_PMC_PCDR_OFFSET 0x0014 /* Peripheral Clock Disable Register */ +#define SAM3U_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */ +#define SAM3U_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */ +#define SAM3U_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */ +#define SAM3U_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */ +#define SAM3U_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */ + /* 0x002c: Reserved */ +#define SAM3U_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */ + /* 0x0034-0x003C Reserved */ +#define SAM3U_PMC_PCK_OFFSET(n) (0x0040+((n)<<2)) +#define SAM3U_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */ +#define SAM3U_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */ +#define SAM3U_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */ + /* 0x004c-0x005c: Reserved */ +#define SAM3U_PMC_IER_OFFSET 0x0060 /* Interrupt Enable Register */ +#define SAM3U_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */ +#define SAM3U_PMC_SR_OFFSET 0x0068 /* Status Register */ +#define SAM3U_PMC_IMR_OFFSET 0x006c /* Interrupt Mask Register */ +#define SAM3U_PMC_FSMR_OFFSET 0x0070 /* Fast Startup Mode Register */ +#define SAM3U_PMC_FSPR_OFFSET 0x0074 /* Fast Startup Polarity Register */ +#define SAM3U_PMC_FOCR_OFFSET 0x0078 /* Fault Output Clear Register */ + /* 0x007c-0x00fc: Reserved */ +#define SAM3U_PMC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ +#define SAM3U_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ + +/* PMC register adresses ****************************************************************/ + +#define SAM3U_PMC_SCER (SAM3U_PMC_BASE+SAM3U_PMC_SCER_OFFSET) +#define SAM3U_PMC_SCDR (SAM3U_PMC_BASE+SAM3U_PMC_SCDR_OFFSET) +#define SAM3U_PMC_SCSR (SAM3U_PMC_BASE+SAM3U_PMC_SCSR_OFFSET) +#define SAM3U_PMC_PCER (SAM3U_PMC_BASE+SAM3U_PMC_PCER_OFFSET) +#define SAM3U_PMC_PCDR (SAM3U_PMC_BASE+SAM3U_PMC_PCDR_OFFSET) +#define SAM3U_PMC_PCSR (SAM3U_PMC_BASE+SAM3U_PMC_PCSR_OFFSET) +#define SAM3U_CKGR_UCKR (SAM3U_PMC_BASE+SAM3U_CKGR_UCKR_OFFSET) +#define SAM3U_CKGR_MOR (SAM3U_PMC_BASE+SAM3U_CKGR_MOR_OFFSET) +#define SAM3U_CKGR_MCFR (SAM3U_PMC_BASE+SAM3U_CKGR_MCFR_OFFSET) +#define SAM3U_CKGR_PLLAR (SAM3U_PMC_BASE+SAM3U_CKGR_PLLAR_OFFSET) +#define SAM3U_PMC_MCKR (SAM3U_PMC_BASE+SAM3U_PMC_MCKR_OFFSET) +#define SAM3U_PMC_PCK(n) (SAM3U_PMC_BASE+SAM3U_PMC_PCK_OFFSET(n)) +#define SAM3U_PMC_PCK0 (SAM3U_PMC_BASE+SAM3U_PMC_PCK0_OFFSET) +#define SAM3U_PMC_PCK1 (SAM3U_PMC_BASE+SAM3U_PMC_PCK1_OFFSET) +#define SAM3U_PMC_PCK2 (SAM3U_PMC_BASE+SAM3U_PMC_PCK2_OFFSET) +#define SAM3U_PMC_IER (SAM3U_PMC_BASE+SAM3U_PMC_IER_OFFSET) +#define SAM3U_PMC_IDR (SAM3U_PMC_BASE+SAM3U_PMC_IDR_OFFSET) +#define SAM3U_PMC_SR (SAM3U_PMC_BASE+SAM3U_PMC_SR_OFFSET) +#define SAM3U_PMC_IMR (SAM3U_PMC_BASE+SAM3U_PMC_IMR_OFFSET) +#define SAM3U_PMC_FSMR (SAM3U_PMC_BASE+SAM3U_PMC_FSMR_OFFSET) +#define SAM3U_PMC_FSPR (SAM3U_PMC_BASE+SAM3U_PMC_FSPR_OFFSET) +#define SAM3U_PMC_FOCR (SAM3U_PMC_BASE+SAM3U_PMC_FOCR_OFFSET) +#define SAM3U_PMC_WPMR (SAM3U_PMC_BASE+SAM3U_PMC_WPMR_OFFSET) +#define SAM3U_PMC_WPSR (SAM3U_PMC_BASE+SAM3U_PMC_WPSR_OFFSET) + +/* PMC register bit definitions *********************************************************/ + +/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System + * Clock Status Register common bit-field definitions + */ + +#define PMC_PCK(n) (1 <<((n)+8) +#define PMC_PCK0 (1 << 8) /* Bit 8: Programmable Clock 0 Output Enable */ +#define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output Enable */ +#define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output Enable */ + +/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC + * Peripheral Clock Status Register common bit-field definitions. + */ + +#define PMC_PID(n) (1<<(n)) +#define PMC_PID2 (1 << 2) /* Bit 2: Peripheral Clock 2 Enable */ +#define PMC_PID3 (1 << 3) /* Bit 3: Peripheral Clock 3 Enable */ +#define PMC_PID4 (1 << 4) /* Bit 4: Peripheral Clock 4 Enable */ +#define PMC_PID5 (1 << 5) /* Bit 5: Peripheral Clock 5 Enable */ +#define PMC_PID6 (1 << 6) /* Bit 6: Peripheral Clock 6 Enable */ +#define PMC_PID7 (1 << 7) /* Bit 7: Peripheral Clock 7 Enable */ +#define PMC_PID8 (1 << 8) /* Bit 8: Peripheral Clock 8 Enable */ +#define PMC_PID9 (1 << 9) /* Bit 9: Peripheral Clock 9 Enable */ +#define PMC_PID10 (1 << 10) /* Bit 10: Peripheral Clock 10 Enable */ +#define PMC_PID11 (1 << 11) /* Bit 11: Peripheral Clock 11 Enable */ +#define PMC_PID12 (1 << 12) /* Bit 12: Peripheral Clock 12 Enable */ +#define PMC_PID13 (1 << 13) /* Bit 13: Peripheral Clock 13 Enable */ +#define PMC_PID14 (1 << 14) /* Bit 14: Peripheral Clock 14 Enable */ +#define PMC_PID15 (1 << 15) /* Bit 15: Peripheral Clock 15 Enable */ +#define PMC_PID16 (1 << 16) /* Bit 16: Peripheral Clock 16 Enable */ +#define PMC_PID17 (1 << 17) /* Bit 17: Peripheral Clock 17 Enable */ +#define PMC_PID18 (1 << 18) /* Bit 18: Peripheral Clock 18 Enable */ +#define PMC_PID19 (1 << 19) /* Bit 19: Peripheral Clock 19 Enable */ +#define PMC_PID20 (1 << 20) /* Bit 20: Peripheral Clock 20 Enable */ +#define PMC_PID21 (1 << 21) /* Bit 21: Peripheral Clock 21 Enable */ +#define PMC_PID22 (1 << 22) /* Bit 22: Peripheral Clock 22 Enable */ +#define PMC_PID23 (1 << 23) /* Bit 23: Peripheral Clock 23 Enable */ +#define PMC_PID24 (1 << 24) /* Bit 24: Peripheral Clock 24 Enable */ +#define PMC_PID25 (1 << 25) /* Bit 25: Peripheral Clock 25 Enable */ +#define PMC_PID26 (1 << 26) /* Bit 26: Peripheral Clock 26 Enable */ +#define PMC_PID27 (1 << 27) /* Bit 27: Peripheral Clock 27 Enable */ +#define PMC_PID28 (1 << 28) /* Bit 28: Peripheral Clock 28 Enable */ +#define PMC_PID29 (1 << 29) /* Bit 29: Peripheral Clock 29 Enable */ +#define PMC_PID30 (1 << 30) /* Bit 30: Peripheral Clock 30 Enable */ +#define PMC_PID31 (1 << 31) /* Bit 31: Peripheral Clock 31 Enable */ + +/* PMC UTMI Clock Configuration Register */ + +#define CKGR_UCKR_UPLLEN (1 << 16) /* Bit 16: UTMI PLL Enable */ +#define CKGR_UCKR_UPLLCOUNT_SHIFT (20) /* Bits 20-23: UTMI PLL Start-up Time */ +#define CKGR_UCKR_UPLLCOUNT_MASK (15 << CKGR_UCKR_UPLLCOUNT_SHIFT) + +/* PMC Clock Generator Main Oscillator Register */ + +#define CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */ +#define CKGR_MOR_WAITMODE (1 << 2) /* Bit 2: Wait Mode Command */ +#define CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF_SHIFT (4) /* Bits 4-6: Main On-Chip RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCRCF_MASK (7 << CKGR_MOR_MOSCRCF_SHIFT) +#define CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-16: Main Crystal Oscillator Start-up Time */ +#define CKGR_MOR_MOSCXTST_MASK (0x1ff << CKGR_MOR_MOSCXTST_SHIFT) +#define CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */ +#define CKGR_MOR_KEY_MASK (0xff << CKGR_MOR_KEY_SHIFT) +#define CKGR_MOR_MOSCSEL (1 << 24) /* Bit 24: Main Oscillator Selection */ +#define CKGR_MOR_CFDEN (1 << 25) /* Bit 25: Clock Failure Detector Enable */ + + +/* PMC Clock Generator Main Clock Frequency Register */ + +#define CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */ +#define CKGR_MCFR_MAINF_MASK (0xffff << CKGR_MCFR_MAINF_SHIFT) +#define CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */ + +/* PMC Clock Generator PLLA Register */ + +#define CKGR_PLLAR_DIVA_SHIFT (0) /* Bits 0-7: Divider */ +#define CKGR_PLLAR_DIVA_MASK (0xff << CKGR_PLLAR_DIVA_SHIFT) +# define CKGR_PLLAR_DIVA_ZERO (0 << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is 0 */ +# define CKGR_PLLAR_DIVA_BYPASS (1 << CKGR_PLLAR_DIVA_SHIFT) /* Divider is bypassed (DIVA=1) */ +# define CKGR_PLLAR_DIVA(n) ((n) << CKGR_PLLAR_DIVA_SHIFT) /* Divider output is DIVA=n, n=2..255 */ +#define CKGR_PLLAR_PLLACOUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */ +#define CKGR_PLLAR_PLLACOUNT_MASK (63 << CKGR_PLLAR_PLLACOUNT_SHIFT) +#define CKGR_PLLAR_STMODE_SHIFT (14) /* Bits 14-15: Start Mode */ +#define CKGR_PLLAR_STMODE_MASK (3 << CKGR_PLLAR_STMODE_SHIFT) +# define CKGR_PLLAR_STMODE_FAST (0 << CKGR_PLLAR_STMODE_SHIFT) /* Fast Startup */ +# define CKGR_PLLAR_STMODE_NORMAL (2 << CKGR_PLLAR_STMODE_SHIFT) /* Normal Startup */ +#define CKGR_PLLAR_MULA_SHIFT (16) /* Bits 16-26: PLLA Multiplier */ +#define CKGR_PLLAR_MULA_MASK (0x7ff << CKGR_PLLAR_MULA_SHIFT) +#define CKGR_PLLAR_ONE (1 << 29) /* Bit 29: Always one */ + +/* PMC Master Clock Register */ + +#define PMC_MCKR_CSS_SHIFT (0) /* Bits 0-1: Master Clock Source Selection */ +#define PMC_MCKR_CSS_MASK (3 << PMC_MCKR_CSS_SHIFT) +# define PMC_MCKR_CSS_SLOW (0 << PMC_MCKR_CSS_SHIFT) /* Slow Clock */ +# define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */ +# define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */ +# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */ +#define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */ +#define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT) +# define PMC_MCKR_PRES_DIV1 (0 << PMC_MCKR_PRES_SHIFT) /* Selected clock */ +# define PMC_MCKR_PRES_DIV2 (1 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 2 */ +# define PMC_MCKR_PRES_DIV4 (2 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 4 */ +# define PMC_MCKR_PRES_DIV8 (3 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 8 */ +# define PMC_MCKR_PRES_DIV16 (4 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 16 */ +# define PMC_MCKR_PRES_DIV32K (5 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 32 */ +# define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */ +# define PMC_MCKR_PRES_DIV3 (7 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 3 */ +#define PMC_MCKR_UPLLDIV (1 << 13) /* Bit 13: UPLL Divider */ + +/* PMC Programmable Clock Register (0,1,2) */ + +#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */ +#define PMC_PCK_CSS_MASK (7 << PMC_PCK_CSS_MASK) +# define PMC_PCK_CSS_SLOW (0 << PMC_PCK_CSS_MASK) /* Slow Clock */ +# define PMC_PCK_CSS_MAIN (1 << PMC_PCK_CSS_MASK) /* Main Clock */ +# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_MASK) /* PLLA Clock */ +# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_MASK) /* UPLL Clock */ +# define PMC_PCK_CSS_MASTER (4 << PMC_PCK_CSS_MASK) /* Master Clock */ +#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */ +#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT) +# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */ +# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */ +# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */ +# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */ +# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */ +# define PMC_PCK_PRES_DIV32K (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */ +# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */ + +/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register, + * and PMC Interrupt Mask Register common bit-field definitions + */ + +#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */ +#define PMC_INT_LOCKA (1 << 1) /* Bit 1: PLL A Lock Interrupt */ +#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */ +#define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */ +#define PMC_SR_OSCSELS (1 << 7) /* Bit 7: Slow Clock Oscillator Selection (SR only) */ +#define PMC_INT_PCKRDY(n) (1<<((n)+8) +#define PMC_INT_PCKRDY0 (1 << 8) /* Bit 8: Programmable Clock Ready 0 Interrupt */ +#define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */ +#define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */ +#define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */ +#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */ +#define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */ +#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */ +#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */ + +/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register common bit-field + * definitions + */ + +#define PMC_FSTI(n) (1<<(n)) +#define PMC_FSTI0 (1 << 0) /* Bit 0: Fast Startup Input 0 */ +#define PMC_FSTI1 (1 << 1) /* Bit 1: Fast Startup Input 1 */ +#define PMC_FSTI2 (1 << 2) /* Bit 2: Fast Startup Input 2 */ +#define PMC_FSTI3 (1 << 3) /* Bit 3: Fast Startup Input 3 */ +#define PMC_FSTI4 (1 << 4) /* Bit 4: Fast Startup Input 4 */ +#define PMC_FSTI5 (1 << 5) /* Bit 5: Fast Startup Input 5 */ +#define PMC_FSTI6 (1 << 6) /* Bit 6: Fast Startup Input 6 */ +#define PMC_FSTI7 (1 << 7) /* Bit 7: Fast Startup Input 7 */ +#define PMC_FSTI8 (1 << 8) /* Bit 8: Fast Startup Input 8 */ +#define PMC_FSTI9 (1 << 9) /* Bit 9: Fast Startup Input 9 */ +#define PMC_FSTI10 (1 << 10) /* Bit 10: Fast Startup Input 10 */ +#define PMC_FSTI11 (1 << 11) /* Bit 11: Fast Startup Input 11 */ +#define PMC_FSTI12 (1 << 12) /* Bit 12: Fast Startup Input 12 */ +#define PMC_FSTI13 (1 << 13) /* Bit 13: Fast Startup Input 13 */ +#define PMC_FSTI14 (1 << 14) /* Bit 14: Fast Startup Input 14 */ +#define PMC_FSTI15 (1 << 15) /* Bit 15: Fast Startup Input 15 */ + +#define PMC_FSMR_RTTAL (1 << 16) /* Bit 16: RTT Alarm Enable (MR only) */ +#define PMC_FSMR_RTCAL (1 << 17) /* Bit 17: RTC Alarm Enable (MR only) */ +#define PMC_FSMR_USBAL (1 << 18) /* Bit 18: USB Alarm Enable (MR only) */ +#define PMC_FSMR_LPM (1 << 20) /* Bit 20: Low Power Mode (MR only) */ + +/* PMC Fault Output Clear Register */ + +#define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */ + +/* PMC Write Protect Mode Register */ + +#define PMC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define PMC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define PMC_WPMR_WPKEY_MASK (0x00ffffff << PMC_WPMR_WPKEY_SHIFT) + +/* PMC Write Protect Status Register */ + +#define PMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +#define PMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PMC_H */ diff --git a/arch/arm/src/sam3u/sam3u_pwm.h b/arch/arm/src/sam3u/sam3u_pwm.h index 5890d0f676bdaeb07582c864a603df5b50adda6f..e8278d795578cd67187d73ad7cb11cf402902a62 100644 --- a/arch/arm/src/sam3u/sam3u_pwm.h +++ b/arch/arm/src/sam3u/sam3u_pwm.h @@ -1,633 +1,633 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_pwm.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PWM_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_PWM_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* PWM register offsets *****************************************************************/ - -#define SAM3U_PWM_CLK_OFFSET 0x000 /* PWM Clock Register */ -#define SAM3U_PWM_ENA_OFFSET 0x004 /* PWM Enable Register */ -#define SAM3U_PWM_DIS_OFFSET 0x008 /* PWM Disable Register */ -#define SAM3U_PWM_SR_OFFSET 0x00c /* PWM Status Register */ -#define SAM3U_PWM_IER1_OFFSET 0x010 /* PWM Interrupt Enable Register 1 */ -#define SAM3U_PWM_IDR1_OFFSET 0x014 /* PWM Interrupt Disable Register 1 */ -#define SAM3U_PWM_IMR1_OFFSET 0x018 /* PWM Interrupt Mask Register 1 */ -#define SAM3U_PWM_ISR1_OFFSET 0x01c /* PWM Interrupt Status Register 1 */ -#define SAM3U_PWM_SCM_OFFSET 0x020 /* PWM Sync Channels Mode Register */ - /* 0x024: Reserved */ -#define SAM3U_PWM_SCUC_OFFSET 0x028 /* PWM Sync Channels Update Control Register */ -#define SAM3U_PWM_SCUP_OFFSET 0x02c /* PWM Sync Channels Update Period Register */ -#define SAM3U_PWM_SCUPUPD_OFFSET 0x030 /* PWM Sync Channels Update Period Update Register */ -#define SAM3U_PWM_IER2_OFFSET 0x034 /* PWM Interrupt Enable Register 2 */ -#define SAM3U_PWM_IDR2_OFFSET 0x038 /* PWM Interrupt Disable Register 2 */ -#define SAM3U_PWM_IMR2_OFFSET 0x03c /* PWM Interrupt Mask Register 2 */ -#define SAM3U_PWM_ISR2_OFFSET 0x040 /* PWM Interrupt Status Register 2 */ -#define SAM3U_PWM_OOV_OFFSET 0x044 /* PWM Output Override Value Register */ -#define SAM3U_PWM_OS_OFFSET 0x048 /* PWM Output Selection Register */ -#define SAM3U_PWM_OSS_OFFSET 0x04c /* PWM Output Selection Set Register */ -#define SAM3U_PWM_OSC_OFFSET 0x050 /* PWM Output Selection Clear Register */ -#define SAM3U_PWM_OSSUPD_OFFSET 0x054 /* PWM Output Selection Set Update Register */ -#define SAM3U_PWM_OSCUPD_OFFSET 0x058 /* PWM Output Selection Clear Update Register */ -#define SAM3U_PWM_FMR_OFFSET 0x05c /* PWM Fault Mode Register */ -#define SAM3U_PWM_FSR_OFFSET 0x060 /* PWM Fault Status Register */ -#define SAM3U_PWM_FCR_OFFSET 0x064 /* PWM Fault Clear Register */ -#define SAM3U_PWM_FPV_OFFSET 0x068 /* PWM Fault Protection Value Register */ -#define SAM3U_PWM_FPE_OFFSET 0x06c /* PWM Fault Protection Enable Register */ - /* 0x070-0x078: Reserved */ -#define SAM3U_PWM_EL0MR_OFFSET 0x07c /* PWM Event Line 0 Mode Register */ -#define SAM3U_PWM_EL1MR_OFFSET 0x080 /* PWM Event Line 1 Mode Register */ - /* 0x084-0x0ac: Reserved */ - /* 0x0b4-0x0e0: Reserved */ -#define SAM3U_PWM_WPCR_OFFSET 0x0e4 /* PWM Write Protect Control Register */ -#define SAM3U_PWM_WPSR_OFFSET 0x0e8 /* PWM Write Protect Status Register */ - /* 0x100-0x128: Reserved for PDC registers */ - /* 0x12c: Reserved */ -/* PWM Comparison Registers */ - -#define SAM3U_PWMCMP_OFFSET(n) (0x130+((n)<<4)) -#define SAM3U_PWMCMP_V_OFFSET 0x00 /* PWM Comparison Value Register */ -#define SAM3U_PWMCMP_VUPD_OFFSET 0x04 /* PWM Comparison Value Update Register */ -#define SAM3U_PWMCMP_M_OFFSET 0x08 /* PWM Comparison Mode Register */ -#define SAM3U_PWMCMP_MUPD_OFFSET 0x0c /* PWM Comparison Mode Update Register */ - -#define SAM3U_PWMCMP0_V_OFFSET 0x130 /* PWM Comparison 0 Value Register */ -#define SAM3U_PWMCMP0_VUPD_OFFSET 0x134 /* PWM Comparison 0 Value Update Register */ -#define SAM3U_PWMCMP0_M_OFFSET 0x138 /* PWM Comparison 0 Mode Register */ -#define SAM3U_PWMCMP0_MUPD_OFFSET 0x13c /* PWM Comparison 0 Mode Update Register */ - -#define SAM3U_PWMCMP1_V_OFFSET 0x140 /* PWM Comparison 1 Value Register */ -#define SAM3U_PWMCMP1_VUPD_OFFSET 0x144 /* PWM Comparison 1 Value Update Register */ -#define SAM3U_PWMCMP1_M_OFFSET 0x148 /* PWM Comparison 1 Mode Register */ -#define SAM3U_PWMCMP1_MUPD_OFFSET 0x14c /* PWM Comparison 1 Mode Update Register */ - -#define SAM3U_PWMCMP2_V_OFFSET 0x150 /* PWM Comparison 2 Value Register */ -#define SAM3U_PWMCMP2_VUPD_OFFSET 0x154 /* PWM Comparison 2 Value Update Register */ -#define SAM3U_PWMCMP2_M_OFFSET 0x158 /* PWM Comparison 2 Mode Register */ -#define SAM3U_PWMCMP2_MUPD_OFFSET 0x15c /* PWM Comparison 2 Mode Update Register */ - -#define SAM3U_PWMCMP3_V_OFFSET 0x160 /* PWM Comparison 3 Value Register */ -#define SAM3U_PWMCMP3_VUPD_OFFSET 0x164 /* PWM Comparison 3 Value Update Register */ -#define SAM3U_PWMCMP3_M_OFFSET 0x168 /* PWM Comparison 3 Mode Register */ -#define SAM3U_PWMCMP3_MUPD_OFFSET 0x16c /* PWM Comparison 3 Mode Update Register */ - -#define SAM3U_PWMCMP4_V_OFFSET 0x170 /* PWM Comparison 4 Value Register */ -#define SAM3U_PWMCMP4_VUPD_OFFSET 0x174 /* PWM Comparison 4 Value Update Register */ -#define SAM3U_PWMCMP4_M_OFFSET 0x178 /* PWM Comparison 4 Mode Register */ -#define SAM3U_PWMCMP4_MUPD_OFFSET 0x17c /* PWM Comparison 4 Mode Update Register */ - -#define SAM3U_PWMCMP5_V_OFFSET 0x180 /* PWM Comparison 5 Value Register */ -#define SAM3U_PWMCMP5_VUPD_OFFSET 0x184 /* PWM Comparison 5 Value Update Register */ -#define SAM3U_PWMCMP5_M_OFFSET 0x188 /* PWM Comparison 5 Mode Register */ -#define SAM3U_PWMCMP5_MUPD_OFFSET 0x18c /* PWM Comparison 5 Mode Update Register */ - -#define SAM3U_PWMCMP6_V_OFFSET 0x190 /* PWM Comparison 6 Value Register */ -#define SAM3U_PWMCMP6_VUPD_OFFSET 0x194 /* PWM Comparison 6 Value Update Register */ -#define SAM3U_PWMCMP6_M_OFFSET 0x198 /* PWM Comparison 6 Mode Register */ -#define SAM3U_PWMCMP6_MUPD_OFFSET 0x19c /* PWM Comparison 6 Mode Update Register */ - -#define SAM3U_PWMCMP7_V_OFFSET 0x1a0 /* PWM Comparison 7 Value Register */ -#define SAM3U_PWMCMP7_VUPD_OFFSET 0x1a4 /* PWM Comparison 7 Value Update Register */ -#define SAM3U_PWMCMP7_M_OFFSET 0x1a8 /* PWM Comparison 7 Mode Register */ -#define SAM3U_PWMCMP7_MUPD_OFFSET 0x1ac /* PWM Comparison 7 Mode Update Register */ - /* 0x1b0-0x1fc: Reserved */ -/* PWM Channel Registers */ - -#define SAM3U_PWMCH_OFFSET(n) (0x200+((n)<< 5)) -#define SAM3U_PWMCH_MR_OFFSET 0x00 /* PWM Channel Mode Register */ -#define SAM3U_PWMCH_DTY_OFFSET 0x04 /* PWM Channel Duty Cycle Register */ -#define SAM3U_PWMCH_DTYUPD_OFFSET 0x08 /* PWM Channel Duty Cycle Update Register */ -#define SAM3U_PWMCH_PRD_OFFSET 0x0c /* PWM Channel Period Register */ -#define SAM3U_PWMCH_PRDUPD_OFFSET 0x10 /* PWM Channel Period Update Register */ -#define SAM3U_PWMCH_CCNT_OFFSET 0x14 /* PWM Channel Counter Register */ -#define SAM3U_PWMCH_DT_OFFSET 0x18 /* PWM Channel Dead Time Register */ -#define SAM3U_PWMCH_DTUPD_OFFSET 0x1c /* PWM Channel Dead Time Update Register */ - -#define SAM3U_PWMCH0_MR_OFFSET 0x200 /* PWM Channel 0 Mode Register */ -#define SAM3U_PWMCH0_DTY_OFFSET 0x204 /* PWM Channel 0 Duty Cycle Register */ -#define SAM3U_PWMCH0_DTYUPD_OFFSET 0x208 /* PWM Channel 0 Duty Cycle Update Register */ -#define SAM3U_PWMCH0_PRD_OFFSET 0x20c /* PWM Channel 0 Period Register */ -#define SAM3U_PWMCH0_PRDUPD_OFFSET 0x210 /* PWM Channel 0 Period Update Register */ -#define SAM3U_PWMCH0_CCNT_OFFSET 0x214 /* PWM Channel 0 Counter Register */ -#define SAM3U_PWMCH0_DT_OFFSET 0x218 /* PWM Channel 0 Dead Time Register */ -#define SAM3U_PWMCH0_DTUPD_OFFSET 0x21c /* PWM Channel 0 Dead Time Update Register */ - -#define SAM3U_PWMCH1_MR_OFFSET 0x220 /* PWM Channel 1 Mode Register */ -#define SAM3U_PWMCH1_DTY_OFFSET 0x224 /* PWM Channel 1 Duty Cycle Register */ -#define SAM3U_PWMCH1_DTYUPD_OFFSET 0x228 /* PWM Channel 1 Duty Cycle Update Register */ -#define SAM3U_PWMCH1_PRD_OFFSET 0x22c /* PWM Channel 1 Period Register */ -#define SAM3U_PWMCH1_PRDUPD_OFFSET 0x230 /* PWM Channel 1 Period Update Register */ -#define SAM3U_PWMCH1_CCNT_OFFSET 0x234 /* PWM Channel 1 Counter Register */ -#define SAM3U_PWMCH1_DT_OFFSET 0x238 /* PWM Channel 1 Dead Time Register */ -#define SAM3U_PWMCH1_DTUPD_OFFSET 0x23c /* PWM Channel 1 Dead Time Update Register */ - -#define SAM3U_PWMCH2_MR_OFFSET 0x240 /* PWM Channel 2 Mode Register */ -#define SAM3U_PWMCH2_DTY_OFFSET 0x244 /* PWM Channel 2 Duty Cycle Register */ -#define SAM3U_PWMCH2_DTYUPD_OFFSET 0x248 /* PWM Channel 2 Duty Cycle Update Register */ -#define SAM3U_PWMCH2_PRD_OFFSET 0x24c /* PWM Channel 2 Period Register */ -#define SAM3U_PWMCH2_PRDUPD_OFFSET 0x250 /* PWM Channel 2 Period Update Register */ -#define SAM3U_PWMCH2_CCNT_OFFSET 0x254 /* PWM Channel 2 Counter Register */ -#define SAM3U_PWMCH2_DT_OFFSET 0x258 /* PWM Channel 2 Dead Time Register */ -#define SAM3U_PWMCH2_DTUPD_OFFSET 0x25c /* PWM Channel 2 Dead Time Update Register */ - -#define SAM3U_PWMCH3_MR_OFFSET 0x260 /* PWM Channel 3 Mode Register */ -#define SAM3U_PWMCH3_DTY_OFFSET 0x264 /* PWM Channel 3 Duty Cycle Register */ -#define SAM3U_PWMCH3_DTYUPD_OFFSET 0x268 /* PWM Channel 3 Duty Cycle Update Register */ -#define SAM3U_PWMCH3_PRD_OFFSET 0x26c /* PWM Channel 3 Period Register */ -#define SAM3U_PWMCH3_PRDUPD_OFFSET 0x270 /* PWM Channel 3 Period Update Register */ -#define SAM3U_PWMCH3_CCNT_OFFSET 0x274 /* PWM Channel 3 Counter Register */ -#define SAM3U_PWMCH3_DT_OFFSET 0x278 /* PWM Channel 3 Dead Time Register */ -#define SAM3U_PWMCH3_DTUPD_OFFSET 0x27c /* PWM Channel 3 Dead Time Update Register */ - -/* PWM register adresses ****************************************************************/ - -#define SAM3U_PWM_CLK (SAM3U_PWM_BASE+SAM3U_PWM_CLK_OFFSET) -#define SAM3U_PWM_ENA (SAM3U_PWM_BASE+SAM3U_PWM_ENA_OFFSET) -#define SAM3U_PWM_DIS (SAM3U_PWM_BASE+SAM3U_PWM_DIS_OFFSET) -#define SAM3U_PWM_SR (SAM3U_PWM_BASE+SAM3U_PWM_SR_OFFSET) -#define SAM3U_PWM_IER1 (SAM3U_PWM_BASE+SAM3U_PWM_IER1_OFFSET) -#define SAM3U_PWM_IDR1 (SAM3U_PWM_BASE+SAM3U_PWM_IDR1_OFFSET) -#define SAM3U_PWM_IMR1 (SAM3U_PWM_BASE+SAM3U_PWM_IMR1_OFFSET) -#define SAM3U_PWM_ISR1 (SAM3U_PWM_BASE+SAM3U_PWM_ISR1_OFFSET) -#define SAM3U_PWM_SCM (SAM3U_PWM_BASE+SAM3U_PWM_SCM_OFFSET) -#define SAM3U_PWM_SCUC (SAM3U_PWM_BASE+SAM3U_PWM_SCUC_OFFSET) -#define SAM3U_PWM_SCUP (SAM3U_PWM_BASE+SAM3U_PWM_SCUP_OFFSET) -#define SAM3U_PWM_SCUPUPD (SAM3U_PWM_BASE+SAM3U_PWM_SCUPUPD_OFFSET) -#define SAM3U_PWM_IER2 (SAM3U_PWM_BASE+SAM3U_PWM_IER2_OFFSET) -#define SAM3U_PWM_IDR2 (SAM3U_PWM_BASE+SAM3U_PWM_IDR2_OFFSET) -#define SAM3U_PWM_IMR2 (SAM3U_PWM_BASE+SAM3U_PWM_IMR2_OFFSET) -#define SAM3U_PWM_ISR2 (SAM3U_PWM_BASE+SAM3U_PWM_ISR2_OFFSET) -#define SAM3U_PWM_OOV (SAM3U_PWM_BASE+SAM3U_PWM_OOV_OFFSET) -#define SAM3U_PWM_OS (SAM3U_PWM_BASE+SAM3U_PWM_OS_OFFSET) -#define SAM3U_PWM_OSS (SAM3U_PWM_BASE+SAM3U_PWM_OSS_OFFSET) -#define SAM3U_PWM_OSC (SAM3U_PWM_BASE+SAM3U_PWM_OSC_OFFSET) -#define SAM3U_PWM_OSSUPD (SAM3U_PWM_BASE+SAM3U_PWM_OSSUPD_OFFSET) -#define SAM3U_PWM_OSCUPD (SAM3U_PWM_BASE+SAM3U_PWM_OSCUPD_OFFSET) -#define SAM3U_PWM_FMR (SAM3U_PWM_BASE+SAM3U_PWM_FMR_OFFSET) -#define SAM3U_PWM_FSR (SAM3U_PWM_BASE+SAM3U_PWM_FSR_OFFSET) -#define SAM3U_PWM_FCR (SAM3U_PWM_BASE+SAM3U_PWM_FCR_OFFSET) -#define SAM3U_PWM_FPV (SAM3U_PWM_BASE+SAM3U_PWM_FPV_OFFSET) -#define SAM3U_PWM_FPE (SAM3U_PWM_BASE+SAM3U_PWM_FPE_OFFSET) -#define SAM3U_PWM_EL0MR (SAM3U_PWM_BASE+SAM3U_PWM_EL0MR_OFFSET) -#define SAM3U_PWM_EL1MR (SAM3U_PWM_BASE+SAM3U_PWM_EL1MR_OFFSET) -#define SAM3U_PWM_WPCR (SAM3U_PWM_BASE+SAM3U_PWM_WPCR_OFFSET) -#define SAM3U_PWM_WPSR (SAM3U_PWM_BASE+SAM3U_PWM_WPSR_OFFSET) - -/* PWM Comparison Registers */ - -#define SAM3U_PWCMP_BASE(n) (SAM3U_PWM_BASE+SAM3U_PWCMP_OFFSET(n)) -#define SAM3U_PWMCMP0_BASE (SAM3U_PWM_BASE+0x0130) -#define SAM3U_PWMCMP1_BASE (SAM3U_PWM_BASE+0x0140) -#define SAM3U_PWMCMP2_BASE (SAM3U_PWM_BASE+0x0150) -#define SAM3U_PWMCMP3_BASE (SAM3U_PWM_BASE+0x0160) -#define SAM3U_PWMCMP4_BASE (SAM3U_PWM_BASE+0x0170) -#define SAM3U_PWMCMP5_BASE (SAM3U_PWM_BASE+0x0180) -#define SAM3U_PWMCMP6_BASE (SAM3U_PWM_BASE+0x0190) -#define SAM3U_PWMCMP7_BASE (SAM3U_PWM_BASE+0x01a0) - -#define SAM3U_PWMCMP0_V (SAM3U_PWMCMP0_BASE+SAM3U_PWMCMP_V_OFFSET) -#define SAM3U_PWMCMP0_VUPD (SAM3U_PWMCMP0_BASE+SAM3U_PWMCMP_VUPD_OFFSET) -#define SAM3U_PWMCMP0_M (SAM3U_PWMCMP0_BASE+SAM3U_PWMCMP_M_OFFSET) -#define SAM3U_PWMCMP0_MUPD (SAM3U_PWMCMP0_BASE+SAM3U_PWMCMP_MUPD_OFFSET) - -#define SAM3U_PWMCMP1_V (SAM3U_PWMCMP1_BASE+SAM3U_PWMCMP_V_OFFSET) -#define SAM3U_PWMCMP1_VUPD (SAM3U_PWMCMP1_BASE+SAM3U_PWMCMP_VUPD_OFFSET) -#define SAM3U_PWMCMP1_M (SAM3U_PWMCMP1_BASE+SAM3U_PWMCMP_M_OFFSET) -#define SAM3U_PWMCMP1_MUPD (SAM3U_PWMCMP1_BASE+SAM3U_PWMCMP_MUPD_OFFSET) - -#define SAM3U_PWMCMP2_V (SAM3U_PWMCMP2_BASE+SAM3U_PWMCMP_V_OFFSET) -#define SAM3U_PWMCMP2_VUPD (SAM3U_PWMCMP2_BASE+SAM3U_PWMCMP_VUPD_OFFSET) -#define SAM3U_PWMCMP2_M (SAM3U_PWMCMP2_BASE+SAM3U_PWMCMP_M_OFFSET) -#define SAM3U_PWMCMP2_MUPD (SAM3U_PWMCMP2_BASE+SAM3U_PWMCMP_MUPD_OFFSET) - -#define SAM3U_PWMCMP3_V (SAM3U_PWMCMP3_BASE+SAM3U_PWMCMP_V_OFFSET) -#define SAM3U_PWMCMP3_VUPD (SAM3U_PWMCMP3_BASE+SAM3U_PWMCMP_VUPD_OFFSET) -#define SAM3U_PWMCMP3_M (SAM3U_PWMCMP3_BASE+SAM3U_PWMCMP_M_OFFSET) -#define SAM3U_PWMCMP3_MUPD (SAM3U_PWMCMP3_BASE+SAM3U_PWMCMP_MUPD_OFFSET) - -#define SAM3U_PWMCMP4_V (SAM3U_PWMCMP4_BASE+SAM3U_PWMCMP_V_OFFSET) -#define SAM3U_PWMCMP4_VUPD (SAM3U_PWMCMP4_BASE+SAM3U_PWMCMP_VUPD_OFFSET) -#define SAM3U_PWMCMP4_M (SAM3U_PWMCMP4_BASE+SAM3U_PWMCMP_M_OFFSET) -#define SAM3U_PWMCMP4_MUPD (SAM3U_PWMCMP4_BASE+SAM3U_PWMCMP_MUPD_OFFSET) - -#define SAM3U_PWMCMP5_V (SAM3U_PWMCMP5_BASE+SAM3U_PWMCMP_V_OFFSET) -#define SAM3U_PWMCMP5_VUPD (SAM3U_PWMCMP5_BASE+SAM3U_PWMCMP_VUPD_OFFSET) -#define SAM3U_PWMCMP5_M (SAM3U_PWMCMP5_BASE+SAM3U_PWMCMP_M_OFFSET) -#define SAM3U_PWMCMP5_MUPD (SAM3U_PWMCMP5_BASE+SAM3U_PWMCMP_MUPD_OFFSET) - -#define SAM3U_PWMCMP6_V (SAM3U_PWMCMP6_BASE+SAM3U_PWMCMP_V_OFFSET) -#define SAM3U_PWMCMP6_VUPD (SAM3U_PWMCMP6_BASE+SAM3U_PWMCMP_VUPD_OFFSET) -#define SAM3U_PWMCMP6_M (SAM3U_PWMCMP6_BASE+SAM3U_PWMCMP_M_OFFSET) -#define SAM3U_PWMCMP6_MUPD (SAM3U_PWMCMP6_BASE+SAM3U_PWMCMP_MUPD_OFFSET) - -#define SAM3U_PWMCMP7_V (SAM3U_PWMCMP7_BASE+SAM3U_PWMCMP_V_OFFSET) -#define SAM3U_PWMCMP7_VUPD (SAM3U_PWMCMP7_BASE+SAM3U_PWMCMP_VUPD_OFFSET) -#define SAM3U_PWMCMP7_M (SAM3U_PWMCMP7_BASE+SAM3U_PWMCMP_M_OFFSET) -#define SAM3U_PWMCMP7_MUPD (SAM3U_PWMCMP7_BASE+SAM3U_PWMCMP_MUPD_OFFSET) - -/* PWM Channel Registers */ - -#define SAM3U_PWCH_BASE(n) (SAM3U_PWM_BASE+SAM3U_PWCH_OFFSET(n)) -#define SAM3U_PWMCH0_BASE (SAM3U_PWM_BASE+0x0200) -#define SAM3U_PWMCH1_BASE (SAM3U_PWM_BASE+0x0220) -#define SAM3U_PWMCH2_BASE (SAM3U_PWM_BASE+0x0240) -#define SAM3U_PWMCH3_BASE (SAM3U_PWM_BASE+0x0260) - -#define SAM3U_PWMCH0_MR (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_MR_OFFSET) -#define SAM3U_PWMCH0_DTY (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_DTY_OFFSET) -#define SAM3U_PWMCH0_DTYUPD (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_DTYUPD_OFFSET) -#define SAM3U_PWMCH0_PRD (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_PRD_OFFSET) -#define SAM3U_PWMCH0_PRDUPD (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_PRDUPD_OFFSET) -#define SAM3U_PWMCH0_CCNT (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_CCNT_OFFSET) -#define SAM3U_PWMCH0_DT (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_DT_OFFSET) -#define SAM3U_PWMCH0_DTUPD (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_DTUPD_OFFSET) - -#define SAM3U_PWMCH1_MR (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_MR_OFFSET) -#define SAM3U_PWMCH1_DTY (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_DTY_OFFSET) -#define SAM3U_PWMCH1_DTYUPD (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_DTYUPD_OFFSET) -#define SAM3U_PWMCH1_PRD (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_PRD_OFFSET) -#define SAM3U_PWMCH1_PRDUPD (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_PRDUPD_OFFSET) -#define SAM3U_PWMCH1_CCNT (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_CCNT_OFFSET) -#define SAM3U_PWMCH1_DT (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_DT_OFFSET) -#define SAM3U_PWMCH1_DTUPD (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_DTUPD_OFFSET) - -#define SAM3U_PWMCH2_MR (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_MR_OFFSET) -#define SAM3U_PWMCH2_DTY (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_DTY_OFFSET) -#define SAM3U_PWMCH2_DTYUPD (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_DTYUPD_OFFSET) -#define SAM3U_PWMCH2_PRD (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_PRD_OFFSET) -#define SAM3U_PWMCH2_PRDUPD (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_PRDUPD_OFFSET) -#define SAM3U_PWMCH2_CCNT (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_CCNT_OFFSET) -#define SAM3U_PWMCH2_DT (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_DT_OFFSET) -#define SAM3U_PWMCH2_DTUPD (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_DTUPD_OFFSET) - -#define SAM3U_PWMCH3_MR (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_MR_OFFSET) -#define SAM3U_PWMCH3_DTY (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_DTY_OFFSET) -#define SAM3U_PWMCH3_DTYUPD (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_DTYUPD_OFFSET) -#define SAM3U_PWMCH3_PRD (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_PRD_OFFSET) -#define SAM3U_PWMCH3_PRDUPD (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_PRDUPD_OFFSET) -#define SAM3U_PWMCH3_CCNT (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_CCNT_OFFSET) -#define SAM3U_PWMCH3_DT (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_DT_OFFSET) -#define SAM3U_PWMCH3_DTUPD (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_DTUPD_OFFSET) - -/* PWM register bit definitions *********************************************************/ - -/* PWM Clock Register */ - -#define PWM_CLK_DIVA_SHIFT (0) /* Bits 0-7: CLKA Divide Factor */ -#define PWM_CLK_DIVA_MASK (0xff << PWM_CLK_DIVA_SHIFT) -#define PWM_CLK_PREA_SHIFT (8) /* Bits 8-11: CLKA Source Clock Selection */ -#define PWM_CLK_PREA_MASK (15 << PWM_CLK_PREA_SHIFT) -# define PWM_CLK_PREA_MCK (0 << PWM_CLK_PREA_SHIFT) /* MCK */ -# define PWM_CLK_PREA_MCKDIV2 (1 << PWM_CLK_PREA_SHIFT) /* MCK/2 */ -# define PWM_CLK_PREA_MCKDIV4 (2 << PWM_CLK_PREA_SHIFT) /* MCK/4 */ -# define PWM_CLK_PREA_MCKDIV8 (3 << PWM_CLK_PREA_SHIFT) /* MCK/8 */ -# define PWM_CLK_PREA_MCKDIV16 (4 << PWM_CLK_PREA_SHIFT) /* MCK/16 */ -# define PWM_CLK_PREA_MCKDIV32 (5 << PWM_CLK_PREA_SHIFT) /* MCK/32 */ -# define PWM_CLK_PREA_MCKDIV64 (6 << PWM_CLK_PREA_SHIFT) /* MCK/64 */ -# define PWM_CLK_PREA_MCKDIV128 (7 << PWM_CLK_PREA_SHIFT) /* MCK/128 */ -# define PWM_CLK_PREA_MCKDIV256 (8 << PWM_CLK_PREA_SHIFT) /* MCK/256 */ -# define PWM_CLK_PREA_MCKDIV512 (9 << PWM_CLK_PREA_SHIFT) /* MCK/512 */ -# define PWM_CLK_PREA_MCKDIV1024 (10 << PWM_CLK_PREA_SHIFT) /* MCK/1024 */ -#define PWM_CLK_DIVB_SHIFT (16) /* Bits 16-23: CLKB Divide Factor */ -#define PWM_CLK_DIVB_MASK (0xff << PWM_CLK_DIVB_SHIFT) -#define PWM_CLK_PREB_SHIFT (24) /* Bit 24-27: CLKB Source Clock Selection */ -#define PWM_CLK_PREB_MASK (15 << PWM_CLK_PREB_SHIFT) -# define PWM_CLK_PREB_MCK (0 << PWM_CLK_PREB_SHIFT) /* MCK */ -# define PWM_CLK_PREB_MCKDIV2 (1 << PWM_CLK_PREB_SHIFT) /* MCK/2 */ -# define PWM_CLK_PREB_MCKDIV4 (2 << PWM_CLK_PREB_SHIFT) /* MCK/4 */ -# define PWM_CLK_PREB_MCKDIV8 (3 << PWM_CLK_PREB_SHIFT) /* MCK/8 */ -# define PWM_CLK_PREB_MCKDIV16 (4 << PWM_CLK_PREB_SHIFT) /* MCK/16 */ -# define PWM_CLK_PREB_MCKDIV32 (5 << PWM_CLK_PREB_SHIFT) /* MCK/32 */ -# define PWM_CLK_PREB_MCKDIV64 (6 << PWM_CLK_PREB_SHIFT) /* MCK/64 */ -# define PWM_CLK_PREB_MCKDIV128 (7 << PWM_CLK_PREB_SHIFT) /* MCK/128 */ -# define PWM_CLK_PREB_MCKDIV256 (8 << PWM_CLK_PREB_SHIFT) /* MCK/256 */ -# define PWM_CLK_PREB_MCKDIV512 (9 << PWM_CLK_PREB_SHIFT) /* MCK/512 */ -# define PWM_CLK_PREB_MCKDIV1024 (10 << PWM_CLK_PREB_SHIFT) /* MCK/1024 */ - -/* PWM Enable Register, PWM Disable Register, and PWM Status Register common bit-field definitions */ - -#define SAM3U_ENAB_CHID(n) (1 << ((n)) -#define SAM3U_ENAB_CHID0 (1 << 0) /* Bit 0: Counter Event Channel 0 Interrupt */ -#define SAM3U_ENAB_CHID1 (1 << 1) /* Bit 1: Counter Event Channel 1 Interrupt */ -#define SAM3U_ENAB_CHID2 (1 << 2) /* Bit 2: Counter Event Channel 2 Interrupt */ -#define SAM3U_ENAB_CHID3 (1 << 3) /* Bit 3: Counter Event Channel 3 Interrupt */ - -/* PWM Interrupt Enable Register 1, PWM Interrupt Disable Register 1, PWM Interrupt - * Mask Register 1, and PWM Interrupt Status Register 1 common bit definitions - */ - -#define SAM3U_INT_CHID(n) (1 << (n)) -#define SAM3U_INT_CHID0 (1 << 0) /* Bit 0: Counter Event Channel 0 Interrupt */ -#define SAM3U_INT_CHID1 (1 << 1) /* Bit 1: Counter Event Channel 1 Interrupt */ -#define SAM3U_INT_CHID2 (1 << 2) /* Bit 2: Counter Event Channel 2 Interrupt */ -#define SAM3U_INT_CHID3 (1 << 3) /* Bit 3: Counter Event Channel 3 Interrupt */ -#define SAM3U_INT_FCHID(n) (1 << ((n)+16)) -#define SAM3U_INT_FCHID0 (1 << 16) /* Bit 16: Fault Protection Trigger Channel 0 Interrupt */ -#define SAM3U_INT_FCHID1 (1 << 17) /* Bit 17: Fault Protection Trigger Channel 1 Interrupt */ -#define SAM3U_INT_FCHID2 (1 << 18) /* Bit 18: Fault Protection Trigger Channel 2 Interrupt */ -#define SAM3U_INT_FCHID3 (1 << 19) /* Bit 19: Fault Protection Trigger Channel 3 Interrupt */ - -/* PWM Sync Channels Mode Register */ - -#define PWM_SCM_SYNC(n) (1 << (n)) -#define PWM_SCM_SYNC0 (1 << 0) /* Bit 0: Synchronous Channel 0 */ -#define PWM_SCM_SYNC1 (1 << 1) /* Bit 1: Synchronous Channel 1 */ -#define PWM_SCM_SYNC2 (1 << 2) /* Bit 2: Synchronous Channel 2 */ -#define PWM_SCM_SYNC3 (1 << 3) /* Bit 3: Synchronous Channel 3 */ -#define PWM_SCM_UPDM_SHIFT (16) /* Bits 16-17: Synchronous Channels Update Mode */ -#define PWM_SCM_UPDM_MASK (3 << PWM_SCM_UPDM_SHIFT) -# define PWM_SCM_UPDM_MANMAN (0 << PWM_SCM_UPDM_SHIFT) /* Manual write/manual update */ -# define PWM_SCM_UPDM_MANAUTO (1 << PWM_SCM_UPDM_SHIFT) /* Manual write/automatic update */ -# define PWM_SCM_UPDM_AUTOAUTO (2 << PWM_SCM_UPDM_SHIFT) /* Auto write/automatic update */ -#define PWM_SCM_PTRM (1 << 20) /* Bit 20: PDC Transfer Request Mode */ -#define PWM_SCM_PTRCS_SHIFT (21) /* Bits 21-23: PDC Transfer Request Comparison Selection */ -#define PWM_SCM_PTRCS_MASK (7 << PWM_SCM_PTRCS_SHIFT) - -/* PWM Sync Channels Update Control Register */ - -#define PWM_SCUC_UPDULOCK (1 << 0) /* Bit 0: Synchronous Channels Update Unlock */ - -/* PWM Sync Channels Update Period Register */ - -#define PWM_SCUP_UPR_SHIFT (0) /* Bits 0-3: Update Period */ -#define PWM_SCUP_UPR_MASK (15 << PWM_SCUP_UPR_MASK) -#define PWM_SCUP_UPRCNT_SHIFT (4) /* Bits 4-7: Update Period Counter */ -#define PWM_SCUP_UPRCNT_MASK (15 << PWM_SCUP_UPRCNT_SHIFT) - -/* PWM Sync Channels Update Period Update Register */ - -#define PWM_SCUPUPD_SHIFT (0) /* Bits 0-3: Update Period Update */ -#define PWM_SCUPUPD_MASK (15 << PWM_SCUPUPD_SHIFT) - -/* PWM Interrupt Enable Register 2, PWM Interrupt Disable Register 2, PWM Interrupt Mask Register 2, and PWM Interrupt Status Register 2 common bit-field definitions */ - -#define SAM3U_INT_WRDY (1 << 0) /* Bit 0: Write Ready Update Interrupt */ -#define SAM3U_INT_ENDTX (1 << 1) /* Bit 1: PDC End of TX Buffer Interrupt */ -#define SAM3U_INT_TXBUFE (1 << 2) /* Bit 2: PDC TX Buffer Empty Interrupt */ -#define SAM3U_INT_UNRE (1 << 3) /* Bit 3: Synch Update Underrun Error Interrupt */ -#define SAM3U_INT_CMPM(n) (1 << ((n)+8)) -#define SAM3U_INT_CMPM0 (1 << 8) /* Bit 8: Comparison 0 Match Interrupt */ -#define SAM3U_INT_CMPM1 (1 << 9) /* Bit 9: Comparison 1 Match Interrupt */ -#define SAM3U_INT_CMPM2 (1 << 10) /* Bit 10: Comparison 2 Match Interrupt */ -#define SAM3U_INT_CMPM3 (1 << 11) /* Bit 11: Comparison 3 Match Interrupt */ -#define SAM3U_INT_CMPM4 (1 << 12) /* Bit 12: Comparison 4 Match Interrupt */ -#define SAM3U_INT_CMPM5 (1 << 13) /* Bit 13: Comparison 5 Match Interrupt */ -#define SAM3U_INT_CMPM6 (1 << 14) /* Bit 14: Comparison 6 Match Interrupt */ -#define SAM3U_INT_CMPM7 (1 << 15) /* Bit 15: Comparison 7 Match Interrupt */ -#define SAM3U_INT_CMPU(n) (1 << ((n)+16)) -#define SAM3U_INT_CMPU0 (1 << 16) /* Bit 16: Comparison o Update Interrupt */ -#define SAM3U_INT_CMPU1 (1 << 17) /* Bit 17: Comparison 1 Update Interrupt */ -#define SAM3U_INT_CMPU2 (1 << 18) /* Bit 18: Comparison 2 Update Interrupt */ -#define SAM3U_INT_CMPU3 (1 << 19) /* Bit 19: Comparison 3 Update Interrupt */ -#define SAM3U_INT_CMPU4 (1 << 20) /* Bit 20: Comparison 4 Update Interrupt */ -#define SAM3U_INT_CMPU5 (1 << 21) /* Bit 21: Comparison 5 Update Interrupt */ -#define SAM3U_INT_CMPU6 (1 << 22) /* Bit 22: Comparison 6 Update Interrupt */ -#define SAM3U_INT_CMPU7 (1 << 23) /* Bit 23: Comparison 7 Update Interrupt */ - -/* PWM Output Override Value Register, PWM Output Selection Register, PWM Output - * Selection Set Register, PWM Output Selection Clear Register, PWM Output Selection - * Set Update Register, and PWM Output Selection Clear Update Register common bit-field - * definitions - */ - -#define PWM_OUT_OH(n) (1 << (n)) -#define PWM_OUT_OH0 (1 << 0) /* Bit 0: Value for PWMH output of the channel 0 */ -#define PWM_OUT_OH1 (1 << 1) /* Bit 1: Value for PWMH output of the channel 1 */ -#define PWM_OUT_OH2 (1 << 2) /* Bit 2: Value for PWMH output of the channel 2 */ -#define PWM_OUT_OH3 (1 << 3) /* Bit 3: Value for PWMH output of the channel 3 */ -#define PWM_OUT_OL(n) (1 << ((n)+16)) -#define PWM_OUT_OL0 (1 << 16) /* Bit 16: Value for PWML output of the channel 0 */ -#define PWM_OUT_OL1 (1 << 17) /* Bit 17: Value for PWML output of the channel 1 */ -#define PWM_OUT_OL2 (1 << 18) /* Bit 18: Value for PWML output of the channel 2 */ -#define PWM_OUT_OL3 (1 << 19) /* Bit 19: Value for PWML output of the channel 3 */ - -/* PWM Fault Mode Register */ - -#define PWM_FMR_FPOL(n) (1 << (n)) -#define PWM_FMR_FPOL0 (1 << 0) /* Bit 0: Fault 0 Polarity */ -#define PWM_FMR_FPOL1 (1 << 1) /* Bit 1: Fault 1 Polarity */ -#define PWM_FMR_FPOL2 (1 << 2) /* Bit 2: Fault 2 Polarity */ -#define PWM_FMR_FPOL3 (1 << 3) /* Bit 3: Fault 3 Polarity */ -#define PWM_FMR_FMOD(n) (1 << ((n)+8)) -#define PWM_FMR_FMOD0 (1 << 8) /* Bit 8: Fault 0 Activation Mode */ -#define PWM_FMR_FMOD1 (1 << 9) /* Bit 9: Fault 1 Activation Mode */ -#define PWM_FMR_FMOD2 (1 << 10) /* Bit 10: Fault 2 Activation Mode */ -#define PWM_FMR_FMOD3 (1 << 11) /* Bit 11: Fault 3 Activation Mode */ -#define PWM_FMR_FFIL(n) (1 << ((n)+16)) -#define PWM_FMR_FFIL0 (1 << 16) /* Bit 16: Fault 0 Filter */ -#define PWM_FMR_FFIL1 (1 << 17) /* Bit 17: Fault 1 Filter */ -#define PWM_FMR_FFIL2 (1 << 18) /* Bit 18: Fault 2 Filter */ -#define PWM_FMR_FFIL3 (1 << 19) /* Bit 19: Fault 3 Filter */ - -/* PWM Fault Status Register */ - -#define PWM_FSR_FIV(n) (1 << (n)) -#define PWM_FSR_FIV0 (1 << 0) /* Bit 0: Fault Input 0 Value */ -#define PWM_FSR_FIV1 (1 << 1) /* Bit 1: Fault Input 1 Value */ -#define PWM_FSR_FIV2 (1 << 2) /* Bit 2: Fault Input 2 Value */ -#define PWM_FSR_FIV3 (1 << 3) /* Bit 3: Fault Input 3 Value */ -#define PWM_FSR_FS(n) (1 << ((n)+8)) -#define PWM_FSR_FS0 (1 << 8) /* Bit 8: Fault 0 Status */ -#define PWM_FSR_FS1 (1 << 9) /* Bit 9: Fault 1 Status */ -#define PWM_FSR_FS2 (1 << 10) /* Bit 10: Fault 2 Status */ -#define PWM_FSR_FS3 (1 << 11) /* Bit 11: Fault 3 Status */ - -/* PWM Fault Clear Register */ - -#define PWM_FCR_FCLR(n) (1 << (n)) -#define PWM_FCR_FCLR0 (1 << 0) /* Bit 0: Fault 0 Clear */ -#define PWM_FCR_FCLR1 (1 << 1) /* Bit 1: Fault 1 Clear */ -#define PWM_FCR_FCLR2 (1 << 2) /* Bit 2: Fault 2 Clear */ -#define PWM_FCR_FCLR3 (1 << 3) /* Bit 3: Fault 3 Clear */ - -/* PWM Fault Protection Value Register */ - -#define PWM_FPV_FPVH(n) (1 << (n)) -#define PWM_FPV_FPVH0 (1 << 0) /* Bit 0: Fault Protection Value PWMH output channel 0 */ -#define PWM_FPV_FPVH1 (1 << 1) /* Bit 1: Fault Protection Value PWMH output channel 1 */ -#define PWM_FPV_FPVH2 (1 << 2) /* Bit 2: Fault Protection Value PWMH output channel 2 */ -#define PWM_FPV_FPVH3 (1 << 3) /* Bit 3: Fault Protection Value PWMH output channel 3 */ -#define PWM_FPV_FPVL(n) (1 << ((n)+16)) -#define PWM_FPV_FPVL0 (1 << 16) /* Bit 16: Fault Protection Value PWML output channel 0 */ -#define PWM_FPV_FPVL1 (1 << 17) /* Bit 17: Fault Protection Value PWML output channel 1 */ -#define PWM_FPV_FPVL2 (1 << 18) /* Bit 18: Fault Protection Value PWML output channel 2 */ -#define PWM_FPV_FPVL3 (1 << 19) /* Bit 19: Fault Protection Value PWML output channel 3 */ - -/* PWM Fault Protection Enable Register */ - -#define PWM_FPE_FPEN(n,y) (1 << (((n)<<8)+y)) -#define PWM_FPE_FPE0(y) (1 << (y)) /* Bits 0-7: Fault Protection Enable Fault=y chan=0 */ -#define PWM_FPE_FPE1(y) (1 << ((y)+8)) /* Bits 8-15: Fault Protection Enable Fault=y chan=1 */ -#define PWM_FPE_FPE2(y) (1 << ((y)+16)) /* Bits 16-23: Fault Protection Enable Fault=y chan=2 */ -#define PWM_FPE_FPE3(y) (1 << ((y)+24) /* Bits 24-31: Fault Protection Enable Fault=y chan=3 */ - -/* PWM Event Line 1/2 Register */ - -#define PWM_ELMR_CSEL(n) (1 << (n)) -#define PWM_ELMR_CSEL0 (1 << 0) /* Bit 0: Comparison 0 Selection */ -#define PWM_ELMR_CSEL1 (1 << 1) /* Bit 1: Comparison 1 Selection */ -#define PWM_ELMR_CSEL2 (1 << 2) /* Bit 2: Comparison 2 Selection */ -#define PWM_ELMR_CSEL3 (1 << 3) /* Bit 3: Comparison 3 Selection */ -#define PWM_ELMR_CSEL4 (1 << 4) /* Bit 4: Comparison 4 Selection */ -#define PWM_ELMR_CSEL5 (1 << 5) /* Bit 5: Comparison 5 Selection */ -#define PWM_ELMR_CSEL6 (1 << 6) /* Bit 6: Comparison 6 Selection */ -#define PWM_ELMR_CSEL7 (1 << 7) /* Bit 7: Comparison 7 Selection */ - -/* PWM Write Protect Control Register */ - -#define PWM_WPCR_WPCMD_SHIFT (0) /* Bits 0-1: Write Protect Command */ -#define PWM_WPCR_WPCMD_MASK (3 << PWM_WPCR_WPCMD_SHIFT) -#define PWM_WPCR_WPRG(n) (1 << ((n)+2)) -#define PWM_WPCR_WPRG0 (1 << 2) /* Bit 2: Write Protect Register Group 0 */ -#define PWM_WPCR_WPRG1 (1 << 3) /* Bit 3: Write Protect Register Group 1 */ -#define PWM_WPCR_WPRG2 (1 << 4) /* Bit 4: Write Protect Register Group 2 */ -#define PWM_WPCR_WPRG3 (1 << 5) /* Bit 5: Write Protect Register Group 3 */ -#define PWM_WPCR_WPRG4 (1 << 6) /* Bit 6: Write Protect Register Group 4 */ -#define PWM_WPCR_WPRG5 (1 << 7) /* Bit 7: Write Protect Register Group 5 */ -#define PWM_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect Key */ -#define PWM_WPCR_WPKEY_MASK (0x00ffffff << PWM_WPCR_WPKEY_SHIFT) - -/* PWM Write Protect Status Register */ - -#define PWM_WPSR_WPSWS(n) (1 << (n)) -#define PWM_WPSR_WPSWS0 (1 << 0) /* Bit 0: Write Protect SW Status */ -#define PWM_WPSR_WPSWS1 (1 << 1) /* Bit 1: Write Protect SW Status */ -#define PWM_WPSR_WPSWS2 (1 << 2) /* Bit 2: Write Protect SW Status */ -#define PWM_WPSR_WPSWS3 (1 << 3) /* Bit 3: Write Protect SW Status */ -#define PWM_WPSR_WPSWS4 (1 << 4) /* Bit 4: Write Protect SW Status */ -#define PWM_WPSR_WPSWS5 (1 << 5) /* Bit 5: Write Protect SW Status */ -#define PWM_WPSR_WPVS (1 << 7) /* Bit 7: Write Protect Violation Status */ -#define PWM_WPSR_WPHWS(n) (1 << ((n)+8)) -#define PWM_WPSR_WPHWS0 (1 << 8) /* Bit 8: Write Protect HW Status */ -#define PWM_WPSR_WPHWS1 (1 << 9) /* Bit 9: Write Protect HW Status */ -#define PWM_WPSR_WPHWS2 (1 << 10) /* Bit 10: Write Protect HW Status */ -#define PWM_WPSR_WPHWS3 (1 << 11) /* Bit 11: Write Protect HW Status */ -#define PWM_WPSR_WPHWS4 (1 << 12) /* Bit 12: Write Protect HW Status */ -#define PWM_WPSR_WPHWS5 (1 << 13) /* Bit 13: Write Protect HW Status */ -#define PWM_WPSR_WPVSRC_SHIFT (16) /* Bits 16-31: Write Protect Violation Source */ -#define PWM_WPSR_WPVSRC_MASK (0xffff << PWM_WPSR_WPVSRC_SHIFT) - -/* PWM Comparison x Value Register and PWM Comparison x Value Update Register */ - -#define PWMCMP_CV_SHIFT (0) /* Bits 0-23: Comparison x Value */ -#define PWMCMP_CV_MASK (0x00ffffff << PWMCMP_CV_SHIFT) -#define PWMCMP_CVM (1 << 24) /* Bit 24: Comparison x Value Mode */ - -/* PWM Comparison x Mode Register and PWM Comparison x Mode Update Register */ - -#define PWMCMP_CEN (1 << 0) /* Bit 0: Comparison x Enable */ -#define PWMCMP_CTR_SHIFT (4) /* Bits 4-7: Comparison x Trigger */ -#define PWMCMP_CTR_MASK (15 << PWMCMP_CTR_SHIFT) -#define PWMCMP_CPR_SHIFT (8) /* Bits 8-11: Comparison x Period */ -#define PWMCMP_CPR_MASK (15 << PWMCMP_CPR_SHIFT) -#define PWMCMP_M_CPRCNT_SHIFT (12) /* Bits 12-15: Comparison x Period Count (M only) */ -#define PWMCMP_M_CPRCNT_MASK (15 << PWMCMP_M_CPRCNT_SHIFT) -#define PWMCMP_CUPR_SHIFT (16) /* Bits 16-19: Comparison x Update Period */ -#define PWMCMP_CUPR_MASK (15 << PWMCMP_CUPR_SHIFT) -#define PWMCMP_M_CUPRCNT_SHIFT (20) /* Bits 20-23: Comparison x Update Period Counter (M only) */ -#define PWMCMP_M_CUPRCNT_MASK (15 << PWMCMP_M_CUPRCNT_SHIFT) - -/* PWM Channel Mode Register */ - -#define PWMCH_MR_CPRE_SHIFT (0) /* Bits 0-3: Channel Pre-scaler */ -#define PWMCH_MR_CPRE_MASK (15 << PWMCH_MR_CPRE_SHIFT) -# define PWMCH_MR_CPRE_MCK (0 << PWMCH_MR_CPRE_SHIFT) /* MCK */ -# define PWMCH_MR_CPRE_MCKDIV2 (1 << PWMCH_MR_CPRE_SHIFT) /* MCK/2 */ -# define PWMCH_MR_CPRE_MCKDIV4 (2 << PWMCH_MR_CPRE_SHIFT) /* MCK/4 */ -# define PWMCH_MR_CPRE_MCKDIV8 (3 << PWMCH_MR_CPRE_SHIFT) /* MCK/8 */ -# define PWMCH_MR_CPRE_MCKDIV16 (4 << PWMCH_MR_CPRE_SHIFT) /* MCK/16 */ -# define PWMCH_MR_CPRE_MCKDIV32 (5 << PWMCH_MR_CPRE_SHIFT) /* MCK/32 */ -# define PWMCH_MR_CPRE_MCKDIV64 (6 << PWMCH_MR_CPRE_SHIFT) /* MCK/64 */ -# define PWMCH_MR_CPRE_MCKDIV128 (7 << PWMCH_MR_CPRE_SHIFT) /* MCK/128 */ -# define PWMCH_MR_CPRE_MCKDIV256 (8 << PWMCH_MR_CPRE_SHIFT) /* MCK/256 */ -# define PWMCH_MR_CPRE_MCKDIV512 (9 << PWMCH_MR_CPRE_SHIFT) /* MCK/512 */ -# define PWMCH_MR_CPRE_MCKDIV1024 (10 << PWMCH_MR_CPRE_SHIFT) /* MCK/1024 */ -# define PWMCH_MR_CPRE_CLKA (11 << PWMCH_MR_CPRE_SHIFT) /*CLKA */ -# define PWMCH_MR_CPRE_CLKB (12 << PWMCH_MR_CPRE_SHIFT) /* CLKB */ -#define PWMCH_MR_CALG (1 << 8) /* Bit 8: Channel Alignment */ -#define PWMCH_MR_CPOL (1 << 9) /* Bit 9: Channel Polarity */ -#define PWMCH_MR_CES (1 << 10) /* Bit 10: Counter Event Selection */ -#define PWMCH_MR_DTE (1 << 16) /* Bit 16: Dead-Time Generator Enable */ -#define PWMCH_MR_DTHI (1 << 17) /* Bit 17: Dead-Time PWMHx Output Inverted */ -#define PWMCH_MR_DTLI (1 << 18) /* Bit 18: Dead-Time PWMLx Output Inverted */ - -/* PWM Channel Duty Cycle Register and PWM Channel Duty Cycle Update Register common bit-field definitions */ - -#define PWMCH_DTY_SHIFT (0) /* Bits 0-23: Channel Duty-Cycle */ -#define PWMCH_DTY_MASK (0x00ffffff << PWMCH_DTY_SHIFT) - -/* PWM Channel Period Register and PWM Channel Period Update Register common bit-field definitions */ - -#define PWMCH_PRD_SHIFT (0) /* Bits 0-23: Channel Period */ -#define PWMCH_PRD_MASK (0x00ffffff << PWMCH_PRD_SHIFT) - -/* PWM Channel Counter Register */ - -#define PWMCH_CCNT_SHIFT (0) /* Bits 0-23: Channel Counter Register */ -#define PWMCH_CCNT_MASK (0x00ffffff << PWMCH_CCNT_SHIFT) - -/* PWM Channel Dead Time Register and PWM Channel Dead Time Update Register common bit-field definitions */ - -#define PWMCH_DTH_SHIFT (0) /* Bits 0-15: Dead-Time Value for PWMHx Output */ -#define PWMCH_DTH_MASK (0xffff << PWMCH_DTH_SHIFT) -#define PWMCH_DTL_SHIFT (16) /* Bits 16-31: Dead-Time Value for PWMLx Output */ -#define PWMCH_DTL_MASK (0xffff << PWMCH_DTL_SHIFT) - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PWM_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_pwm.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_PWM_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_PWM_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* PWM register offsets *****************************************************************/ + +#define SAM3U_PWM_CLK_OFFSET 0x000 /* PWM Clock Register */ +#define SAM3U_PWM_ENA_OFFSET 0x004 /* PWM Enable Register */ +#define SAM3U_PWM_DIS_OFFSET 0x008 /* PWM Disable Register */ +#define SAM3U_PWM_SR_OFFSET 0x00c /* PWM Status Register */ +#define SAM3U_PWM_IER1_OFFSET 0x010 /* PWM Interrupt Enable Register 1 */ +#define SAM3U_PWM_IDR1_OFFSET 0x014 /* PWM Interrupt Disable Register 1 */ +#define SAM3U_PWM_IMR1_OFFSET 0x018 /* PWM Interrupt Mask Register 1 */ +#define SAM3U_PWM_ISR1_OFFSET 0x01c /* PWM Interrupt Status Register 1 */ +#define SAM3U_PWM_SCM_OFFSET 0x020 /* PWM Sync Channels Mode Register */ + /* 0x024: Reserved */ +#define SAM3U_PWM_SCUC_OFFSET 0x028 /* PWM Sync Channels Update Control Register */ +#define SAM3U_PWM_SCUP_OFFSET 0x02c /* PWM Sync Channels Update Period Register */ +#define SAM3U_PWM_SCUPUPD_OFFSET 0x030 /* PWM Sync Channels Update Period Update Register */ +#define SAM3U_PWM_IER2_OFFSET 0x034 /* PWM Interrupt Enable Register 2 */ +#define SAM3U_PWM_IDR2_OFFSET 0x038 /* PWM Interrupt Disable Register 2 */ +#define SAM3U_PWM_IMR2_OFFSET 0x03c /* PWM Interrupt Mask Register 2 */ +#define SAM3U_PWM_ISR2_OFFSET 0x040 /* PWM Interrupt Status Register 2 */ +#define SAM3U_PWM_OOV_OFFSET 0x044 /* PWM Output Override Value Register */ +#define SAM3U_PWM_OS_OFFSET 0x048 /* PWM Output Selection Register */ +#define SAM3U_PWM_OSS_OFFSET 0x04c /* PWM Output Selection Set Register */ +#define SAM3U_PWM_OSC_OFFSET 0x050 /* PWM Output Selection Clear Register */ +#define SAM3U_PWM_OSSUPD_OFFSET 0x054 /* PWM Output Selection Set Update Register */ +#define SAM3U_PWM_OSCUPD_OFFSET 0x058 /* PWM Output Selection Clear Update Register */ +#define SAM3U_PWM_FMR_OFFSET 0x05c /* PWM Fault Mode Register */ +#define SAM3U_PWM_FSR_OFFSET 0x060 /* PWM Fault Status Register */ +#define SAM3U_PWM_FCR_OFFSET 0x064 /* PWM Fault Clear Register */ +#define SAM3U_PWM_FPV_OFFSET 0x068 /* PWM Fault Protection Value Register */ +#define SAM3U_PWM_FPE_OFFSET 0x06c /* PWM Fault Protection Enable Register */ + /* 0x070-0x078: Reserved */ +#define SAM3U_PWM_EL0MR_OFFSET 0x07c /* PWM Event Line 0 Mode Register */ +#define SAM3U_PWM_EL1MR_OFFSET 0x080 /* PWM Event Line 1 Mode Register */ + /* 0x084-0x0ac: Reserved */ + /* 0x0b4-0x0e0: Reserved */ +#define SAM3U_PWM_WPCR_OFFSET 0x0e4 /* PWM Write Protect Control Register */ +#define SAM3U_PWM_WPSR_OFFSET 0x0e8 /* PWM Write Protect Status Register */ + /* 0x100-0x128: Reserved for PDC registers */ + /* 0x12c: Reserved */ +/* PWM Comparison Registers */ + +#define SAM3U_PWMCMP_OFFSET(n) (0x130+((n)<<4)) +#define SAM3U_PWMCMP_V_OFFSET 0x00 /* PWM Comparison Value Register */ +#define SAM3U_PWMCMP_VUPD_OFFSET 0x04 /* PWM Comparison Value Update Register */ +#define SAM3U_PWMCMP_M_OFFSET 0x08 /* PWM Comparison Mode Register */ +#define SAM3U_PWMCMP_MUPD_OFFSET 0x0c /* PWM Comparison Mode Update Register */ + +#define SAM3U_PWMCMP0_V_OFFSET 0x130 /* PWM Comparison 0 Value Register */ +#define SAM3U_PWMCMP0_VUPD_OFFSET 0x134 /* PWM Comparison 0 Value Update Register */ +#define SAM3U_PWMCMP0_M_OFFSET 0x138 /* PWM Comparison 0 Mode Register */ +#define SAM3U_PWMCMP0_MUPD_OFFSET 0x13c /* PWM Comparison 0 Mode Update Register */ + +#define SAM3U_PWMCMP1_V_OFFSET 0x140 /* PWM Comparison 1 Value Register */ +#define SAM3U_PWMCMP1_VUPD_OFFSET 0x144 /* PWM Comparison 1 Value Update Register */ +#define SAM3U_PWMCMP1_M_OFFSET 0x148 /* PWM Comparison 1 Mode Register */ +#define SAM3U_PWMCMP1_MUPD_OFFSET 0x14c /* PWM Comparison 1 Mode Update Register */ + +#define SAM3U_PWMCMP2_V_OFFSET 0x150 /* PWM Comparison 2 Value Register */ +#define SAM3U_PWMCMP2_VUPD_OFFSET 0x154 /* PWM Comparison 2 Value Update Register */ +#define SAM3U_PWMCMP2_M_OFFSET 0x158 /* PWM Comparison 2 Mode Register */ +#define SAM3U_PWMCMP2_MUPD_OFFSET 0x15c /* PWM Comparison 2 Mode Update Register */ + +#define SAM3U_PWMCMP3_V_OFFSET 0x160 /* PWM Comparison 3 Value Register */ +#define SAM3U_PWMCMP3_VUPD_OFFSET 0x164 /* PWM Comparison 3 Value Update Register */ +#define SAM3U_PWMCMP3_M_OFFSET 0x168 /* PWM Comparison 3 Mode Register */ +#define SAM3U_PWMCMP3_MUPD_OFFSET 0x16c /* PWM Comparison 3 Mode Update Register */ + +#define SAM3U_PWMCMP4_V_OFFSET 0x170 /* PWM Comparison 4 Value Register */ +#define SAM3U_PWMCMP4_VUPD_OFFSET 0x174 /* PWM Comparison 4 Value Update Register */ +#define SAM3U_PWMCMP4_M_OFFSET 0x178 /* PWM Comparison 4 Mode Register */ +#define SAM3U_PWMCMP4_MUPD_OFFSET 0x17c /* PWM Comparison 4 Mode Update Register */ + +#define SAM3U_PWMCMP5_V_OFFSET 0x180 /* PWM Comparison 5 Value Register */ +#define SAM3U_PWMCMP5_VUPD_OFFSET 0x184 /* PWM Comparison 5 Value Update Register */ +#define SAM3U_PWMCMP5_M_OFFSET 0x188 /* PWM Comparison 5 Mode Register */ +#define SAM3U_PWMCMP5_MUPD_OFFSET 0x18c /* PWM Comparison 5 Mode Update Register */ + +#define SAM3U_PWMCMP6_V_OFFSET 0x190 /* PWM Comparison 6 Value Register */ +#define SAM3U_PWMCMP6_VUPD_OFFSET 0x194 /* PWM Comparison 6 Value Update Register */ +#define SAM3U_PWMCMP6_M_OFFSET 0x198 /* PWM Comparison 6 Mode Register */ +#define SAM3U_PWMCMP6_MUPD_OFFSET 0x19c /* PWM Comparison 6 Mode Update Register */ + +#define SAM3U_PWMCMP7_V_OFFSET 0x1a0 /* PWM Comparison 7 Value Register */ +#define SAM3U_PWMCMP7_VUPD_OFFSET 0x1a4 /* PWM Comparison 7 Value Update Register */ +#define SAM3U_PWMCMP7_M_OFFSET 0x1a8 /* PWM Comparison 7 Mode Register */ +#define SAM3U_PWMCMP7_MUPD_OFFSET 0x1ac /* PWM Comparison 7 Mode Update Register */ + /* 0x1b0-0x1fc: Reserved */ +/* PWM Channel Registers */ + +#define SAM3U_PWMCH_OFFSET(n) (0x200+((n)<< 5)) +#define SAM3U_PWMCH_MR_OFFSET 0x00 /* PWM Channel Mode Register */ +#define SAM3U_PWMCH_DTY_OFFSET 0x04 /* PWM Channel Duty Cycle Register */ +#define SAM3U_PWMCH_DTYUPD_OFFSET 0x08 /* PWM Channel Duty Cycle Update Register */ +#define SAM3U_PWMCH_PRD_OFFSET 0x0c /* PWM Channel Period Register */ +#define SAM3U_PWMCH_PRDUPD_OFFSET 0x10 /* PWM Channel Period Update Register */ +#define SAM3U_PWMCH_CCNT_OFFSET 0x14 /* PWM Channel Counter Register */ +#define SAM3U_PWMCH_DT_OFFSET 0x18 /* PWM Channel Dead Time Register */ +#define SAM3U_PWMCH_DTUPD_OFFSET 0x1c /* PWM Channel Dead Time Update Register */ + +#define SAM3U_PWMCH0_MR_OFFSET 0x200 /* PWM Channel 0 Mode Register */ +#define SAM3U_PWMCH0_DTY_OFFSET 0x204 /* PWM Channel 0 Duty Cycle Register */ +#define SAM3U_PWMCH0_DTYUPD_OFFSET 0x208 /* PWM Channel 0 Duty Cycle Update Register */ +#define SAM3U_PWMCH0_PRD_OFFSET 0x20c /* PWM Channel 0 Period Register */ +#define SAM3U_PWMCH0_PRDUPD_OFFSET 0x210 /* PWM Channel 0 Period Update Register */ +#define SAM3U_PWMCH0_CCNT_OFFSET 0x214 /* PWM Channel 0 Counter Register */ +#define SAM3U_PWMCH0_DT_OFFSET 0x218 /* PWM Channel 0 Dead Time Register */ +#define SAM3U_PWMCH0_DTUPD_OFFSET 0x21c /* PWM Channel 0 Dead Time Update Register */ + +#define SAM3U_PWMCH1_MR_OFFSET 0x220 /* PWM Channel 1 Mode Register */ +#define SAM3U_PWMCH1_DTY_OFFSET 0x224 /* PWM Channel 1 Duty Cycle Register */ +#define SAM3U_PWMCH1_DTYUPD_OFFSET 0x228 /* PWM Channel 1 Duty Cycle Update Register */ +#define SAM3U_PWMCH1_PRD_OFFSET 0x22c /* PWM Channel 1 Period Register */ +#define SAM3U_PWMCH1_PRDUPD_OFFSET 0x230 /* PWM Channel 1 Period Update Register */ +#define SAM3U_PWMCH1_CCNT_OFFSET 0x234 /* PWM Channel 1 Counter Register */ +#define SAM3U_PWMCH1_DT_OFFSET 0x238 /* PWM Channel 1 Dead Time Register */ +#define SAM3U_PWMCH1_DTUPD_OFFSET 0x23c /* PWM Channel 1 Dead Time Update Register */ + +#define SAM3U_PWMCH2_MR_OFFSET 0x240 /* PWM Channel 2 Mode Register */ +#define SAM3U_PWMCH2_DTY_OFFSET 0x244 /* PWM Channel 2 Duty Cycle Register */ +#define SAM3U_PWMCH2_DTYUPD_OFFSET 0x248 /* PWM Channel 2 Duty Cycle Update Register */ +#define SAM3U_PWMCH2_PRD_OFFSET 0x24c /* PWM Channel 2 Period Register */ +#define SAM3U_PWMCH2_PRDUPD_OFFSET 0x250 /* PWM Channel 2 Period Update Register */ +#define SAM3U_PWMCH2_CCNT_OFFSET 0x254 /* PWM Channel 2 Counter Register */ +#define SAM3U_PWMCH2_DT_OFFSET 0x258 /* PWM Channel 2 Dead Time Register */ +#define SAM3U_PWMCH2_DTUPD_OFFSET 0x25c /* PWM Channel 2 Dead Time Update Register */ + +#define SAM3U_PWMCH3_MR_OFFSET 0x260 /* PWM Channel 3 Mode Register */ +#define SAM3U_PWMCH3_DTY_OFFSET 0x264 /* PWM Channel 3 Duty Cycle Register */ +#define SAM3U_PWMCH3_DTYUPD_OFFSET 0x268 /* PWM Channel 3 Duty Cycle Update Register */ +#define SAM3U_PWMCH3_PRD_OFFSET 0x26c /* PWM Channel 3 Period Register */ +#define SAM3U_PWMCH3_PRDUPD_OFFSET 0x270 /* PWM Channel 3 Period Update Register */ +#define SAM3U_PWMCH3_CCNT_OFFSET 0x274 /* PWM Channel 3 Counter Register */ +#define SAM3U_PWMCH3_DT_OFFSET 0x278 /* PWM Channel 3 Dead Time Register */ +#define SAM3U_PWMCH3_DTUPD_OFFSET 0x27c /* PWM Channel 3 Dead Time Update Register */ + +/* PWM register adresses ****************************************************************/ + +#define SAM3U_PWM_CLK (SAM3U_PWM_BASE+SAM3U_PWM_CLK_OFFSET) +#define SAM3U_PWM_ENA (SAM3U_PWM_BASE+SAM3U_PWM_ENA_OFFSET) +#define SAM3U_PWM_DIS (SAM3U_PWM_BASE+SAM3U_PWM_DIS_OFFSET) +#define SAM3U_PWM_SR (SAM3U_PWM_BASE+SAM3U_PWM_SR_OFFSET) +#define SAM3U_PWM_IER1 (SAM3U_PWM_BASE+SAM3U_PWM_IER1_OFFSET) +#define SAM3U_PWM_IDR1 (SAM3U_PWM_BASE+SAM3U_PWM_IDR1_OFFSET) +#define SAM3U_PWM_IMR1 (SAM3U_PWM_BASE+SAM3U_PWM_IMR1_OFFSET) +#define SAM3U_PWM_ISR1 (SAM3U_PWM_BASE+SAM3U_PWM_ISR1_OFFSET) +#define SAM3U_PWM_SCM (SAM3U_PWM_BASE+SAM3U_PWM_SCM_OFFSET) +#define SAM3U_PWM_SCUC (SAM3U_PWM_BASE+SAM3U_PWM_SCUC_OFFSET) +#define SAM3U_PWM_SCUP (SAM3U_PWM_BASE+SAM3U_PWM_SCUP_OFFSET) +#define SAM3U_PWM_SCUPUPD (SAM3U_PWM_BASE+SAM3U_PWM_SCUPUPD_OFFSET) +#define SAM3U_PWM_IER2 (SAM3U_PWM_BASE+SAM3U_PWM_IER2_OFFSET) +#define SAM3U_PWM_IDR2 (SAM3U_PWM_BASE+SAM3U_PWM_IDR2_OFFSET) +#define SAM3U_PWM_IMR2 (SAM3U_PWM_BASE+SAM3U_PWM_IMR2_OFFSET) +#define SAM3U_PWM_ISR2 (SAM3U_PWM_BASE+SAM3U_PWM_ISR2_OFFSET) +#define SAM3U_PWM_OOV (SAM3U_PWM_BASE+SAM3U_PWM_OOV_OFFSET) +#define SAM3U_PWM_OS (SAM3U_PWM_BASE+SAM3U_PWM_OS_OFFSET) +#define SAM3U_PWM_OSS (SAM3U_PWM_BASE+SAM3U_PWM_OSS_OFFSET) +#define SAM3U_PWM_OSC (SAM3U_PWM_BASE+SAM3U_PWM_OSC_OFFSET) +#define SAM3U_PWM_OSSUPD (SAM3U_PWM_BASE+SAM3U_PWM_OSSUPD_OFFSET) +#define SAM3U_PWM_OSCUPD (SAM3U_PWM_BASE+SAM3U_PWM_OSCUPD_OFFSET) +#define SAM3U_PWM_FMR (SAM3U_PWM_BASE+SAM3U_PWM_FMR_OFFSET) +#define SAM3U_PWM_FSR (SAM3U_PWM_BASE+SAM3U_PWM_FSR_OFFSET) +#define SAM3U_PWM_FCR (SAM3U_PWM_BASE+SAM3U_PWM_FCR_OFFSET) +#define SAM3U_PWM_FPV (SAM3U_PWM_BASE+SAM3U_PWM_FPV_OFFSET) +#define SAM3U_PWM_FPE (SAM3U_PWM_BASE+SAM3U_PWM_FPE_OFFSET) +#define SAM3U_PWM_EL0MR (SAM3U_PWM_BASE+SAM3U_PWM_EL0MR_OFFSET) +#define SAM3U_PWM_EL1MR (SAM3U_PWM_BASE+SAM3U_PWM_EL1MR_OFFSET) +#define SAM3U_PWM_WPCR (SAM3U_PWM_BASE+SAM3U_PWM_WPCR_OFFSET) +#define SAM3U_PWM_WPSR (SAM3U_PWM_BASE+SAM3U_PWM_WPSR_OFFSET) + +/* PWM Comparison Registers */ + +#define SAM3U_PWCMP_BASE(n) (SAM3U_PWM_BASE+SAM3U_PWCMP_OFFSET(n)) +#define SAM3U_PWMCMP0_BASE (SAM3U_PWM_BASE+0x0130) +#define SAM3U_PWMCMP1_BASE (SAM3U_PWM_BASE+0x0140) +#define SAM3U_PWMCMP2_BASE (SAM3U_PWM_BASE+0x0150) +#define SAM3U_PWMCMP3_BASE (SAM3U_PWM_BASE+0x0160) +#define SAM3U_PWMCMP4_BASE (SAM3U_PWM_BASE+0x0170) +#define SAM3U_PWMCMP5_BASE (SAM3U_PWM_BASE+0x0180) +#define SAM3U_PWMCMP6_BASE (SAM3U_PWM_BASE+0x0190) +#define SAM3U_PWMCMP7_BASE (SAM3U_PWM_BASE+0x01a0) + +#define SAM3U_PWMCMP0_V (SAM3U_PWMCMP0_BASE+SAM3U_PWMCMP_V_OFFSET) +#define SAM3U_PWMCMP0_VUPD (SAM3U_PWMCMP0_BASE+SAM3U_PWMCMP_VUPD_OFFSET) +#define SAM3U_PWMCMP0_M (SAM3U_PWMCMP0_BASE+SAM3U_PWMCMP_M_OFFSET) +#define SAM3U_PWMCMP0_MUPD (SAM3U_PWMCMP0_BASE+SAM3U_PWMCMP_MUPD_OFFSET) + +#define SAM3U_PWMCMP1_V (SAM3U_PWMCMP1_BASE+SAM3U_PWMCMP_V_OFFSET) +#define SAM3U_PWMCMP1_VUPD (SAM3U_PWMCMP1_BASE+SAM3U_PWMCMP_VUPD_OFFSET) +#define SAM3U_PWMCMP1_M (SAM3U_PWMCMP1_BASE+SAM3U_PWMCMP_M_OFFSET) +#define SAM3U_PWMCMP1_MUPD (SAM3U_PWMCMP1_BASE+SAM3U_PWMCMP_MUPD_OFFSET) + +#define SAM3U_PWMCMP2_V (SAM3U_PWMCMP2_BASE+SAM3U_PWMCMP_V_OFFSET) +#define SAM3U_PWMCMP2_VUPD (SAM3U_PWMCMP2_BASE+SAM3U_PWMCMP_VUPD_OFFSET) +#define SAM3U_PWMCMP2_M (SAM3U_PWMCMP2_BASE+SAM3U_PWMCMP_M_OFFSET) +#define SAM3U_PWMCMP2_MUPD (SAM3U_PWMCMP2_BASE+SAM3U_PWMCMP_MUPD_OFFSET) + +#define SAM3U_PWMCMP3_V (SAM3U_PWMCMP3_BASE+SAM3U_PWMCMP_V_OFFSET) +#define SAM3U_PWMCMP3_VUPD (SAM3U_PWMCMP3_BASE+SAM3U_PWMCMP_VUPD_OFFSET) +#define SAM3U_PWMCMP3_M (SAM3U_PWMCMP3_BASE+SAM3U_PWMCMP_M_OFFSET) +#define SAM3U_PWMCMP3_MUPD (SAM3U_PWMCMP3_BASE+SAM3U_PWMCMP_MUPD_OFFSET) + +#define SAM3U_PWMCMP4_V (SAM3U_PWMCMP4_BASE+SAM3U_PWMCMP_V_OFFSET) +#define SAM3U_PWMCMP4_VUPD (SAM3U_PWMCMP4_BASE+SAM3U_PWMCMP_VUPD_OFFSET) +#define SAM3U_PWMCMP4_M (SAM3U_PWMCMP4_BASE+SAM3U_PWMCMP_M_OFFSET) +#define SAM3U_PWMCMP4_MUPD (SAM3U_PWMCMP4_BASE+SAM3U_PWMCMP_MUPD_OFFSET) + +#define SAM3U_PWMCMP5_V (SAM3U_PWMCMP5_BASE+SAM3U_PWMCMP_V_OFFSET) +#define SAM3U_PWMCMP5_VUPD (SAM3U_PWMCMP5_BASE+SAM3U_PWMCMP_VUPD_OFFSET) +#define SAM3U_PWMCMP5_M (SAM3U_PWMCMP5_BASE+SAM3U_PWMCMP_M_OFFSET) +#define SAM3U_PWMCMP5_MUPD (SAM3U_PWMCMP5_BASE+SAM3U_PWMCMP_MUPD_OFFSET) + +#define SAM3U_PWMCMP6_V (SAM3U_PWMCMP6_BASE+SAM3U_PWMCMP_V_OFFSET) +#define SAM3U_PWMCMP6_VUPD (SAM3U_PWMCMP6_BASE+SAM3U_PWMCMP_VUPD_OFFSET) +#define SAM3U_PWMCMP6_M (SAM3U_PWMCMP6_BASE+SAM3U_PWMCMP_M_OFFSET) +#define SAM3U_PWMCMP6_MUPD (SAM3U_PWMCMP6_BASE+SAM3U_PWMCMP_MUPD_OFFSET) + +#define SAM3U_PWMCMP7_V (SAM3U_PWMCMP7_BASE+SAM3U_PWMCMP_V_OFFSET) +#define SAM3U_PWMCMP7_VUPD (SAM3U_PWMCMP7_BASE+SAM3U_PWMCMP_VUPD_OFFSET) +#define SAM3U_PWMCMP7_M (SAM3U_PWMCMP7_BASE+SAM3U_PWMCMP_M_OFFSET) +#define SAM3U_PWMCMP7_MUPD (SAM3U_PWMCMP7_BASE+SAM3U_PWMCMP_MUPD_OFFSET) + +/* PWM Channel Registers */ + +#define SAM3U_PWCH_BASE(n) (SAM3U_PWM_BASE+SAM3U_PWCH_OFFSET(n)) +#define SAM3U_PWMCH0_BASE (SAM3U_PWM_BASE+0x0200) +#define SAM3U_PWMCH1_BASE (SAM3U_PWM_BASE+0x0220) +#define SAM3U_PWMCH2_BASE (SAM3U_PWM_BASE+0x0240) +#define SAM3U_PWMCH3_BASE (SAM3U_PWM_BASE+0x0260) + +#define SAM3U_PWMCH0_MR (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_MR_OFFSET) +#define SAM3U_PWMCH0_DTY (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_DTY_OFFSET) +#define SAM3U_PWMCH0_DTYUPD (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_DTYUPD_OFFSET) +#define SAM3U_PWMCH0_PRD (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_PRD_OFFSET) +#define SAM3U_PWMCH0_PRDUPD (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_PRDUPD_OFFSET) +#define SAM3U_PWMCH0_CCNT (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_CCNT_OFFSET) +#define SAM3U_PWMCH0_DT (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_DT_OFFSET) +#define SAM3U_PWMCH0_DTUPD (SAM3U_PWMCH0_BASE+SAM3U_PWMCH_DTUPD_OFFSET) + +#define SAM3U_PWMCH1_MR (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_MR_OFFSET) +#define SAM3U_PWMCH1_DTY (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_DTY_OFFSET) +#define SAM3U_PWMCH1_DTYUPD (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_DTYUPD_OFFSET) +#define SAM3U_PWMCH1_PRD (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_PRD_OFFSET) +#define SAM3U_PWMCH1_PRDUPD (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_PRDUPD_OFFSET) +#define SAM3U_PWMCH1_CCNT (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_CCNT_OFFSET) +#define SAM3U_PWMCH1_DT (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_DT_OFFSET) +#define SAM3U_PWMCH1_DTUPD (SAM3U_PWMCH1_BASE+SAM3U_PWMCH_DTUPD_OFFSET) + +#define SAM3U_PWMCH2_MR (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_MR_OFFSET) +#define SAM3U_PWMCH2_DTY (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_DTY_OFFSET) +#define SAM3U_PWMCH2_DTYUPD (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_DTYUPD_OFFSET) +#define SAM3U_PWMCH2_PRD (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_PRD_OFFSET) +#define SAM3U_PWMCH2_PRDUPD (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_PRDUPD_OFFSET) +#define SAM3U_PWMCH2_CCNT (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_CCNT_OFFSET) +#define SAM3U_PWMCH2_DT (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_DT_OFFSET) +#define SAM3U_PWMCH2_DTUPD (SAM3U_PWMCH2_BASE+SAM3U_PWMCH_DTUPD_OFFSET) + +#define SAM3U_PWMCH3_MR (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_MR_OFFSET) +#define SAM3U_PWMCH3_DTY (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_DTY_OFFSET) +#define SAM3U_PWMCH3_DTYUPD (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_DTYUPD_OFFSET) +#define SAM3U_PWMCH3_PRD (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_PRD_OFFSET) +#define SAM3U_PWMCH3_PRDUPD (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_PRDUPD_OFFSET) +#define SAM3U_PWMCH3_CCNT (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_CCNT_OFFSET) +#define SAM3U_PWMCH3_DT (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_DT_OFFSET) +#define SAM3U_PWMCH3_DTUPD (SAM3U_PWMCH3_BASE+SAM3U_PWMCH_DTUPD_OFFSET) + +/* PWM register bit definitions *********************************************************/ + +/* PWM Clock Register */ + +#define PWM_CLK_DIVA_SHIFT (0) /* Bits 0-7: CLKA Divide Factor */ +#define PWM_CLK_DIVA_MASK (0xff << PWM_CLK_DIVA_SHIFT) +#define PWM_CLK_PREA_SHIFT (8) /* Bits 8-11: CLKA Source Clock Selection */ +#define PWM_CLK_PREA_MASK (15 << PWM_CLK_PREA_SHIFT) +# define PWM_CLK_PREA_MCK (0 << PWM_CLK_PREA_SHIFT) /* MCK */ +# define PWM_CLK_PREA_MCKDIV2 (1 << PWM_CLK_PREA_SHIFT) /* MCK/2 */ +# define PWM_CLK_PREA_MCKDIV4 (2 << PWM_CLK_PREA_SHIFT) /* MCK/4 */ +# define PWM_CLK_PREA_MCKDIV8 (3 << PWM_CLK_PREA_SHIFT) /* MCK/8 */ +# define PWM_CLK_PREA_MCKDIV16 (4 << PWM_CLK_PREA_SHIFT) /* MCK/16 */ +# define PWM_CLK_PREA_MCKDIV32 (5 << PWM_CLK_PREA_SHIFT) /* MCK/32 */ +# define PWM_CLK_PREA_MCKDIV64 (6 << PWM_CLK_PREA_SHIFT) /* MCK/64 */ +# define PWM_CLK_PREA_MCKDIV128 (7 << PWM_CLK_PREA_SHIFT) /* MCK/128 */ +# define PWM_CLK_PREA_MCKDIV256 (8 << PWM_CLK_PREA_SHIFT) /* MCK/256 */ +# define PWM_CLK_PREA_MCKDIV512 (9 << PWM_CLK_PREA_SHIFT) /* MCK/512 */ +# define PWM_CLK_PREA_MCKDIV1024 (10 << PWM_CLK_PREA_SHIFT) /* MCK/1024 */ +#define PWM_CLK_DIVB_SHIFT (16) /* Bits 16-23: CLKB Divide Factor */ +#define PWM_CLK_DIVB_MASK (0xff << PWM_CLK_DIVB_SHIFT) +#define PWM_CLK_PREB_SHIFT (24) /* Bit 24-27: CLKB Source Clock Selection */ +#define PWM_CLK_PREB_MASK (15 << PWM_CLK_PREB_SHIFT) +# define PWM_CLK_PREB_MCK (0 << PWM_CLK_PREB_SHIFT) /* MCK */ +# define PWM_CLK_PREB_MCKDIV2 (1 << PWM_CLK_PREB_SHIFT) /* MCK/2 */ +# define PWM_CLK_PREB_MCKDIV4 (2 << PWM_CLK_PREB_SHIFT) /* MCK/4 */ +# define PWM_CLK_PREB_MCKDIV8 (3 << PWM_CLK_PREB_SHIFT) /* MCK/8 */ +# define PWM_CLK_PREB_MCKDIV16 (4 << PWM_CLK_PREB_SHIFT) /* MCK/16 */ +# define PWM_CLK_PREB_MCKDIV32 (5 << PWM_CLK_PREB_SHIFT) /* MCK/32 */ +# define PWM_CLK_PREB_MCKDIV64 (6 << PWM_CLK_PREB_SHIFT) /* MCK/64 */ +# define PWM_CLK_PREB_MCKDIV128 (7 << PWM_CLK_PREB_SHIFT) /* MCK/128 */ +# define PWM_CLK_PREB_MCKDIV256 (8 << PWM_CLK_PREB_SHIFT) /* MCK/256 */ +# define PWM_CLK_PREB_MCKDIV512 (9 << PWM_CLK_PREB_SHIFT) /* MCK/512 */ +# define PWM_CLK_PREB_MCKDIV1024 (10 << PWM_CLK_PREB_SHIFT) /* MCK/1024 */ + +/* PWM Enable Register, PWM Disable Register, and PWM Status Register common bit-field definitions */ + +#define SAM3U_ENAB_CHID(n) (1 << ((n)) +#define SAM3U_ENAB_CHID0 (1 << 0) /* Bit 0: Counter Event Channel 0 Interrupt */ +#define SAM3U_ENAB_CHID1 (1 << 1) /* Bit 1: Counter Event Channel 1 Interrupt */ +#define SAM3U_ENAB_CHID2 (1 << 2) /* Bit 2: Counter Event Channel 2 Interrupt */ +#define SAM3U_ENAB_CHID3 (1 << 3) /* Bit 3: Counter Event Channel 3 Interrupt */ + +/* PWM Interrupt Enable Register 1, PWM Interrupt Disable Register 1, PWM Interrupt + * Mask Register 1, and PWM Interrupt Status Register 1 common bit definitions + */ + +#define SAM3U_INT_CHID(n) (1 << (n)) +#define SAM3U_INT_CHID0 (1 << 0) /* Bit 0: Counter Event Channel 0 Interrupt */ +#define SAM3U_INT_CHID1 (1 << 1) /* Bit 1: Counter Event Channel 1 Interrupt */ +#define SAM3U_INT_CHID2 (1 << 2) /* Bit 2: Counter Event Channel 2 Interrupt */ +#define SAM3U_INT_CHID3 (1 << 3) /* Bit 3: Counter Event Channel 3 Interrupt */ +#define SAM3U_INT_FCHID(n) (1 << ((n)+16)) +#define SAM3U_INT_FCHID0 (1 << 16) /* Bit 16: Fault Protection Trigger Channel 0 Interrupt */ +#define SAM3U_INT_FCHID1 (1 << 17) /* Bit 17: Fault Protection Trigger Channel 1 Interrupt */ +#define SAM3U_INT_FCHID2 (1 << 18) /* Bit 18: Fault Protection Trigger Channel 2 Interrupt */ +#define SAM3U_INT_FCHID3 (1 << 19) /* Bit 19: Fault Protection Trigger Channel 3 Interrupt */ + +/* PWM Sync Channels Mode Register */ + +#define PWM_SCM_SYNC(n) (1 << (n)) +#define PWM_SCM_SYNC0 (1 << 0) /* Bit 0: Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (1 << 1) /* Bit 1: Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (1 << 2) /* Bit 2: Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (1 << 3) /* Bit 3: Synchronous Channel 3 */ +#define PWM_SCM_UPDM_SHIFT (16) /* Bits 16-17: Synchronous Channels Update Mode */ +#define PWM_SCM_UPDM_MASK (3 << PWM_SCM_UPDM_SHIFT) +# define PWM_SCM_UPDM_MANMAN (0 << PWM_SCM_UPDM_SHIFT) /* Manual write/manual update */ +# define PWM_SCM_UPDM_MANAUTO (1 << PWM_SCM_UPDM_SHIFT) /* Manual write/automatic update */ +# define PWM_SCM_UPDM_AUTOAUTO (2 << PWM_SCM_UPDM_SHIFT) /* Auto write/automatic update */ +#define PWM_SCM_PTRM (1 << 20) /* Bit 20: PDC Transfer Request Mode */ +#define PWM_SCM_PTRCS_SHIFT (21) /* Bits 21-23: PDC Transfer Request Comparison Selection */ +#define PWM_SCM_PTRCS_MASK (7 << PWM_SCM_PTRCS_SHIFT) + +/* PWM Sync Channels Update Control Register */ + +#define PWM_SCUC_UPDULOCK (1 << 0) /* Bit 0: Synchronous Channels Update Unlock */ + +/* PWM Sync Channels Update Period Register */ + +#define PWM_SCUP_UPR_SHIFT (0) /* Bits 0-3: Update Period */ +#define PWM_SCUP_UPR_MASK (15 << PWM_SCUP_UPR_MASK) +#define PWM_SCUP_UPRCNT_SHIFT (4) /* Bits 4-7: Update Period Counter */ +#define PWM_SCUP_UPRCNT_MASK (15 << PWM_SCUP_UPRCNT_SHIFT) + +/* PWM Sync Channels Update Period Update Register */ + +#define PWM_SCUPUPD_SHIFT (0) /* Bits 0-3: Update Period Update */ +#define PWM_SCUPUPD_MASK (15 << PWM_SCUPUPD_SHIFT) + +/* PWM Interrupt Enable Register 2, PWM Interrupt Disable Register 2, PWM Interrupt Mask Register 2, and PWM Interrupt Status Register 2 common bit-field definitions */ + +#define SAM3U_INT_WRDY (1 << 0) /* Bit 0: Write Ready Update Interrupt */ +#define SAM3U_INT_ENDTX (1 << 1) /* Bit 1: PDC End of TX Buffer Interrupt */ +#define SAM3U_INT_TXBUFE (1 << 2) /* Bit 2: PDC TX Buffer Empty Interrupt */ +#define SAM3U_INT_UNRE (1 << 3) /* Bit 3: Synch Update Underrun Error Interrupt */ +#define SAM3U_INT_CMPM(n) (1 << ((n)+8)) +#define SAM3U_INT_CMPM0 (1 << 8) /* Bit 8: Comparison 0 Match Interrupt */ +#define SAM3U_INT_CMPM1 (1 << 9) /* Bit 9: Comparison 1 Match Interrupt */ +#define SAM3U_INT_CMPM2 (1 << 10) /* Bit 10: Comparison 2 Match Interrupt */ +#define SAM3U_INT_CMPM3 (1 << 11) /* Bit 11: Comparison 3 Match Interrupt */ +#define SAM3U_INT_CMPM4 (1 << 12) /* Bit 12: Comparison 4 Match Interrupt */ +#define SAM3U_INT_CMPM5 (1 << 13) /* Bit 13: Comparison 5 Match Interrupt */ +#define SAM3U_INT_CMPM6 (1 << 14) /* Bit 14: Comparison 6 Match Interrupt */ +#define SAM3U_INT_CMPM7 (1 << 15) /* Bit 15: Comparison 7 Match Interrupt */ +#define SAM3U_INT_CMPU(n) (1 << ((n)+16)) +#define SAM3U_INT_CMPU0 (1 << 16) /* Bit 16: Comparison o Update Interrupt */ +#define SAM3U_INT_CMPU1 (1 << 17) /* Bit 17: Comparison 1 Update Interrupt */ +#define SAM3U_INT_CMPU2 (1 << 18) /* Bit 18: Comparison 2 Update Interrupt */ +#define SAM3U_INT_CMPU3 (1 << 19) /* Bit 19: Comparison 3 Update Interrupt */ +#define SAM3U_INT_CMPU4 (1 << 20) /* Bit 20: Comparison 4 Update Interrupt */ +#define SAM3U_INT_CMPU5 (1 << 21) /* Bit 21: Comparison 5 Update Interrupt */ +#define SAM3U_INT_CMPU6 (1 << 22) /* Bit 22: Comparison 6 Update Interrupt */ +#define SAM3U_INT_CMPU7 (1 << 23) /* Bit 23: Comparison 7 Update Interrupt */ + +/* PWM Output Override Value Register, PWM Output Selection Register, PWM Output + * Selection Set Register, PWM Output Selection Clear Register, PWM Output Selection + * Set Update Register, and PWM Output Selection Clear Update Register common bit-field + * definitions + */ + +#define PWM_OUT_OH(n) (1 << (n)) +#define PWM_OUT_OH0 (1 << 0) /* Bit 0: Value for PWMH output of the channel 0 */ +#define PWM_OUT_OH1 (1 << 1) /* Bit 1: Value for PWMH output of the channel 1 */ +#define PWM_OUT_OH2 (1 << 2) /* Bit 2: Value for PWMH output of the channel 2 */ +#define PWM_OUT_OH3 (1 << 3) /* Bit 3: Value for PWMH output of the channel 3 */ +#define PWM_OUT_OL(n) (1 << ((n)+16)) +#define PWM_OUT_OL0 (1 << 16) /* Bit 16: Value for PWML output of the channel 0 */ +#define PWM_OUT_OL1 (1 << 17) /* Bit 17: Value for PWML output of the channel 1 */ +#define PWM_OUT_OL2 (1 << 18) /* Bit 18: Value for PWML output of the channel 2 */ +#define PWM_OUT_OL3 (1 << 19) /* Bit 19: Value for PWML output of the channel 3 */ + +/* PWM Fault Mode Register */ + +#define PWM_FMR_FPOL(n) (1 << (n)) +#define PWM_FMR_FPOL0 (1 << 0) /* Bit 0: Fault 0 Polarity */ +#define PWM_FMR_FPOL1 (1 << 1) /* Bit 1: Fault 1 Polarity */ +#define PWM_FMR_FPOL2 (1 << 2) /* Bit 2: Fault 2 Polarity */ +#define PWM_FMR_FPOL3 (1 << 3) /* Bit 3: Fault 3 Polarity */ +#define PWM_FMR_FMOD(n) (1 << ((n)+8)) +#define PWM_FMR_FMOD0 (1 << 8) /* Bit 8: Fault 0 Activation Mode */ +#define PWM_FMR_FMOD1 (1 << 9) /* Bit 9: Fault 1 Activation Mode */ +#define PWM_FMR_FMOD2 (1 << 10) /* Bit 10: Fault 2 Activation Mode */ +#define PWM_FMR_FMOD3 (1 << 11) /* Bit 11: Fault 3 Activation Mode */ +#define PWM_FMR_FFIL(n) (1 << ((n)+16)) +#define PWM_FMR_FFIL0 (1 << 16) /* Bit 16: Fault 0 Filter */ +#define PWM_FMR_FFIL1 (1 << 17) /* Bit 17: Fault 1 Filter */ +#define PWM_FMR_FFIL2 (1 << 18) /* Bit 18: Fault 2 Filter */ +#define PWM_FMR_FFIL3 (1 << 19) /* Bit 19: Fault 3 Filter */ + +/* PWM Fault Status Register */ + +#define PWM_FSR_FIV(n) (1 << (n)) +#define PWM_FSR_FIV0 (1 << 0) /* Bit 0: Fault Input 0 Value */ +#define PWM_FSR_FIV1 (1 << 1) /* Bit 1: Fault Input 1 Value */ +#define PWM_FSR_FIV2 (1 << 2) /* Bit 2: Fault Input 2 Value */ +#define PWM_FSR_FIV3 (1 << 3) /* Bit 3: Fault Input 3 Value */ +#define PWM_FSR_FS(n) (1 << ((n)+8)) +#define PWM_FSR_FS0 (1 << 8) /* Bit 8: Fault 0 Status */ +#define PWM_FSR_FS1 (1 << 9) /* Bit 9: Fault 1 Status */ +#define PWM_FSR_FS2 (1 << 10) /* Bit 10: Fault 2 Status */ +#define PWM_FSR_FS3 (1 << 11) /* Bit 11: Fault 3 Status */ + +/* PWM Fault Clear Register */ + +#define PWM_FCR_FCLR(n) (1 << (n)) +#define PWM_FCR_FCLR0 (1 << 0) /* Bit 0: Fault 0 Clear */ +#define PWM_FCR_FCLR1 (1 << 1) /* Bit 1: Fault 1 Clear */ +#define PWM_FCR_FCLR2 (1 << 2) /* Bit 2: Fault 2 Clear */ +#define PWM_FCR_FCLR3 (1 << 3) /* Bit 3: Fault 3 Clear */ + +/* PWM Fault Protection Value Register */ + +#define PWM_FPV_FPVH(n) (1 << (n)) +#define PWM_FPV_FPVH0 (1 << 0) /* Bit 0: Fault Protection Value PWMH output channel 0 */ +#define PWM_FPV_FPVH1 (1 << 1) /* Bit 1: Fault Protection Value PWMH output channel 1 */ +#define PWM_FPV_FPVH2 (1 << 2) /* Bit 2: Fault Protection Value PWMH output channel 2 */ +#define PWM_FPV_FPVH3 (1 << 3) /* Bit 3: Fault Protection Value PWMH output channel 3 */ +#define PWM_FPV_FPVL(n) (1 << ((n)+16)) +#define PWM_FPV_FPVL0 (1 << 16) /* Bit 16: Fault Protection Value PWML output channel 0 */ +#define PWM_FPV_FPVL1 (1 << 17) /* Bit 17: Fault Protection Value PWML output channel 1 */ +#define PWM_FPV_FPVL2 (1 << 18) /* Bit 18: Fault Protection Value PWML output channel 2 */ +#define PWM_FPV_FPVL3 (1 << 19) /* Bit 19: Fault Protection Value PWML output channel 3 */ + +/* PWM Fault Protection Enable Register */ + +#define PWM_FPE_FPEN(n,y) (1 << (((n)<<8)+y)) +#define PWM_FPE_FPE0(y) (1 << (y)) /* Bits 0-7: Fault Protection Enable Fault=y chan=0 */ +#define PWM_FPE_FPE1(y) (1 << ((y)+8)) /* Bits 8-15: Fault Protection Enable Fault=y chan=1 */ +#define PWM_FPE_FPE2(y) (1 << ((y)+16)) /* Bits 16-23: Fault Protection Enable Fault=y chan=2 */ +#define PWM_FPE_FPE3(y) (1 << ((y)+24) /* Bits 24-31: Fault Protection Enable Fault=y chan=3 */ + +/* PWM Event Line 1/2 Register */ + +#define PWM_ELMR_CSEL(n) (1 << (n)) +#define PWM_ELMR_CSEL0 (1 << 0) /* Bit 0: Comparison 0 Selection */ +#define PWM_ELMR_CSEL1 (1 << 1) /* Bit 1: Comparison 1 Selection */ +#define PWM_ELMR_CSEL2 (1 << 2) /* Bit 2: Comparison 2 Selection */ +#define PWM_ELMR_CSEL3 (1 << 3) /* Bit 3: Comparison 3 Selection */ +#define PWM_ELMR_CSEL4 (1 << 4) /* Bit 4: Comparison 4 Selection */ +#define PWM_ELMR_CSEL5 (1 << 5) /* Bit 5: Comparison 5 Selection */ +#define PWM_ELMR_CSEL6 (1 << 6) /* Bit 6: Comparison 6 Selection */ +#define PWM_ELMR_CSEL7 (1 << 7) /* Bit 7: Comparison 7 Selection */ + +/* PWM Write Protect Control Register */ + +#define PWM_WPCR_WPCMD_SHIFT (0) /* Bits 0-1: Write Protect Command */ +#define PWM_WPCR_WPCMD_MASK (3 << PWM_WPCR_WPCMD_SHIFT) +#define PWM_WPCR_WPRG(n) (1 << ((n)+2)) +#define PWM_WPCR_WPRG0 (1 << 2) /* Bit 2: Write Protect Register Group 0 */ +#define PWM_WPCR_WPRG1 (1 << 3) /* Bit 3: Write Protect Register Group 1 */ +#define PWM_WPCR_WPRG2 (1 << 4) /* Bit 4: Write Protect Register Group 2 */ +#define PWM_WPCR_WPRG3 (1 << 5) /* Bit 5: Write Protect Register Group 3 */ +#define PWM_WPCR_WPRG4 (1 << 6) /* Bit 6: Write Protect Register Group 4 */ +#define PWM_WPCR_WPRG5 (1 << 7) /* Bit 7: Write Protect Register Group 5 */ +#define PWM_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect Key */ +#define PWM_WPCR_WPKEY_MASK (0x00ffffff << PWM_WPCR_WPKEY_SHIFT) + +/* PWM Write Protect Status Register */ + +#define PWM_WPSR_WPSWS(n) (1 << (n)) +#define PWM_WPSR_WPSWS0 (1 << 0) /* Bit 0: Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (1 << 1) /* Bit 1: Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (1 << 2) /* Bit 2: Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (1 << 3) /* Bit 3: Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (1 << 4) /* Bit 4: Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (1 << 5) /* Bit 5: Write Protect SW Status */ +#define PWM_WPSR_WPVS (1 << 7) /* Bit 7: Write Protect Violation Status */ +#define PWM_WPSR_WPHWS(n) (1 << ((n)+8)) +#define PWM_WPSR_WPHWS0 (1 << 8) /* Bit 8: Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (1 << 9) /* Bit 9: Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (1 << 10) /* Bit 10: Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (1 << 11) /* Bit 11: Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (1 << 12) /* Bit 12: Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (1 << 13) /* Bit 13: Write Protect HW Status */ +#define PWM_WPSR_WPVSRC_SHIFT (16) /* Bits 16-31: Write Protect Violation Source */ +#define PWM_WPSR_WPVSRC_MASK (0xffff << PWM_WPSR_WPVSRC_SHIFT) + +/* PWM Comparison x Value Register and PWM Comparison x Value Update Register */ + +#define PWMCMP_CV_SHIFT (0) /* Bits 0-23: Comparison x Value */ +#define PWMCMP_CV_MASK (0x00ffffff << PWMCMP_CV_SHIFT) +#define PWMCMP_CVM (1 << 24) /* Bit 24: Comparison x Value Mode */ + +/* PWM Comparison x Mode Register and PWM Comparison x Mode Update Register */ + +#define PWMCMP_CEN (1 << 0) /* Bit 0: Comparison x Enable */ +#define PWMCMP_CTR_SHIFT (4) /* Bits 4-7: Comparison x Trigger */ +#define PWMCMP_CTR_MASK (15 << PWMCMP_CTR_SHIFT) +#define PWMCMP_CPR_SHIFT (8) /* Bits 8-11: Comparison x Period */ +#define PWMCMP_CPR_MASK (15 << PWMCMP_CPR_SHIFT) +#define PWMCMP_M_CPRCNT_SHIFT (12) /* Bits 12-15: Comparison x Period Count (M only) */ +#define PWMCMP_M_CPRCNT_MASK (15 << PWMCMP_M_CPRCNT_SHIFT) +#define PWMCMP_CUPR_SHIFT (16) /* Bits 16-19: Comparison x Update Period */ +#define PWMCMP_CUPR_MASK (15 << PWMCMP_CUPR_SHIFT) +#define PWMCMP_M_CUPRCNT_SHIFT (20) /* Bits 20-23: Comparison x Update Period Counter (M only) */ +#define PWMCMP_M_CUPRCNT_MASK (15 << PWMCMP_M_CUPRCNT_SHIFT) + +/* PWM Channel Mode Register */ + +#define PWMCH_MR_CPRE_SHIFT (0) /* Bits 0-3: Channel Pre-scaler */ +#define PWMCH_MR_CPRE_MASK (15 << PWMCH_MR_CPRE_SHIFT) +# define PWMCH_MR_CPRE_MCK (0 << PWMCH_MR_CPRE_SHIFT) /* MCK */ +# define PWMCH_MR_CPRE_MCKDIV2 (1 << PWMCH_MR_CPRE_SHIFT) /* MCK/2 */ +# define PWMCH_MR_CPRE_MCKDIV4 (2 << PWMCH_MR_CPRE_SHIFT) /* MCK/4 */ +# define PWMCH_MR_CPRE_MCKDIV8 (3 << PWMCH_MR_CPRE_SHIFT) /* MCK/8 */ +# define PWMCH_MR_CPRE_MCKDIV16 (4 << PWMCH_MR_CPRE_SHIFT) /* MCK/16 */ +# define PWMCH_MR_CPRE_MCKDIV32 (5 << PWMCH_MR_CPRE_SHIFT) /* MCK/32 */ +# define PWMCH_MR_CPRE_MCKDIV64 (6 << PWMCH_MR_CPRE_SHIFT) /* MCK/64 */ +# define PWMCH_MR_CPRE_MCKDIV128 (7 << PWMCH_MR_CPRE_SHIFT) /* MCK/128 */ +# define PWMCH_MR_CPRE_MCKDIV256 (8 << PWMCH_MR_CPRE_SHIFT) /* MCK/256 */ +# define PWMCH_MR_CPRE_MCKDIV512 (9 << PWMCH_MR_CPRE_SHIFT) /* MCK/512 */ +# define PWMCH_MR_CPRE_MCKDIV1024 (10 << PWMCH_MR_CPRE_SHIFT) /* MCK/1024 */ +# define PWMCH_MR_CPRE_CLKA (11 << PWMCH_MR_CPRE_SHIFT) /*CLKA */ +# define PWMCH_MR_CPRE_CLKB (12 << PWMCH_MR_CPRE_SHIFT) /* CLKB */ +#define PWMCH_MR_CALG (1 << 8) /* Bit 8: Channel Alignment */ +#define PWMCH_MR_CPOL (1 << 9) /* Bit 9: Channel Polarity */ +#define PWMCH_MR_CES (1 << 10) /* Bit 10: Counter Event Selection */ +#define PWMCH_MR_DTE (1 << 16) /* Bit 16: Dead-Time Generator Enable */ +#define PWMCH_MR_DTHI (1 << 17) /* Bit 17: Dead-Time PWMHx Output Inverted */ +#define PWMCH_MR_DTLI (1 << 18) /* Bit 18: Dead-Time PWMLx Output Inverted */ + +/* PWM Channel Duty Cycle Register and PWM Channel Duty Cycle Update Register common bit-field definitions */ + +#define PWMCH_DTY_SHIFT (0) /* Bits 0-23: Channel Duty-Cycle */ +#define PWMCH_DTY_MASK (0x00ffffff << PWMCH_DTY_SHIFT) + +/* PWM Channel Period Register and PWM Channel Period Update Register common bit-field definitions */ + +#define PWMCH_PRD_SHIFT (0) /* Bits 0-23: Channel Period */ +#define PWMCH_PRD_MASK (0x00ffffff << PWMCH_PRD_SHIFT) + +/* PWM Channel Counter Register */ + +#define PWMCH_CCNT_SHIFT (0) /* Bits 0-23: Channel Counter Register */ +#define PWMCH_CCNT_MASK (0x00ffffff << PWMCH_CCNT_SHIFT) + +/* PWM Channel Dead Time Register and PWM Channel Dead Time Update Register common bit-field definitions */ + +#define PWMCH_DTH_SHIFT (0) /* Bits 0-15: Dead-Time Value for PWMHx Output */ +#define PWMCH_DTH_MASK (0xffff << PWMCH_DTH_SHIFT) +#define PWMCH_DTL_SHIFT (16) /* Bits 16-31: Dead-Time Value for PWMLx Output */ +#define PWMCH_DTL_MASK (0xffff << PWMCH_DTL_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_PWM_H */ diff --git a/arch/arm/src/sam3u/sam3u_rstc.h b/arch/arm/src/sam3u/sam3u_rstc.h index 4241eeba46ebab099e7278d7573d1642cd374520..688631fb615f62a9f21d9b16836216d3ab4d1603 100644 --- a/arch/arm/src/sam3u/sam3u_rstc.h +++ b/arch/arm/src/sam3u/sam3u_rstc.h @@ -1,102 +1,102 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_rstc.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* RSTC register offsets ****************************************************************/ - -#define SAM3U_RSTC_CR_OFFSET 0x00 /* Control Register */ -#define SAM3U_RSTC_SR_OFFSET 0x04 /* Status Register */ -#define SAM3U_RSTC_MR_OFFSET 0x08 /* Mode Register */ - -/* RSTC register adresses ***************************************************************/ - -#define SAM3U_RSTC_CR (SAM3U_RSTC_BASE+SAM3U_RSTC_CR_OFFSET) -#define SAM3U_RSTC_SR (SAM3U_RSTC_BASE+SAM3U_RSTC_SR_OFFSET) -#define SAM3U_RSTC_MR (SAM3U_RSTC_BASE+SAM3U_RSTC_MR_OFFSET) - -/* RSTC register bit definitions ********************************************************/ - -#define RSTC_CR_PROCRST (1 << 0) /* Bit 0: Processor Reset */ -#define RSTC_CR_PERRST (1 << 2) /* Bit 2: Peripheral Reset */ -#define RSTC_CR_EXTRST (1 << 3) /* Bit 3: External Reset */ -#define RSTC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ -#define RSTC_CR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT) - -#define RSTC_SR_URSTS (1 << 0) /* Bit 0: User Reset Status */ -#define RSTC_SR_RSTTYP_SHIFT (8) /* Bits 8-10: Reset Type */ -#define RSTC_SR_RSTTYP_MASK (7 << RSTC_SR_RSTTYP_SHIFT) -# define RSTC_SR_RSTTYP_PWRUP (0 << RSTC_SR_RSTTYP_SHIFT) /* General Reset */ -# define RSTC_SR_RSTTYP_BACKUP (1 << RSTC_SR_RSTTYP_SHIFT) /* Backup Reset */ -# define RSTC_SR_RSTTYP_WDOG (2 << RSTC_SR_RSTTYP_SHIFT) /* Watchdog Reset */ -# define RSTC_SR_RSTTYP_SWRST (3 << RSTC_SR_RSTTYP_SHIFT) /* Software Reset */ -# define RSTC_SR_RSTTYP_NRST (4 << RSTC_SR_RSTTYP_SHIFT) /* User Reset NRST pin */ -#define RSTC_SR_NRSTL (1 << 16) /* Bit 16: NRST Pin Level */ -#define RSTC_SR_SRCMP (1 << 17) /* Bit 17: Software Reset Command in Progress */ - -#define RSTC_MR_URSTEN (1 << 0) /* Bit 0: User Reset Enable */ -#define RSTC_MR_URSTIEN (1 << 4) /* Bit 4: User Reset Interrupt Enable */ -#define RSTC_MR_ERSTL_SHIFT (8) /* Bits 8-11: External Reset Length */ -#define RSTC_MR_ERSTL_MASK (15 << RSTC_MR_ERSTL_SHIFT) -#define RSTC_MR_KEY_SHIFT (24) /* Bits 24-31: Password */ -#define RSTC_MR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT) - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_rstc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* RSTC register offsets ****************************************************************/ + +#define SAM3U_RSTC_CR_OFFSET 0x00 /* Control Register */ +#define SAM3U_RSTC_SR_OFFSET 0x04 /* Status Register */ +#define SAM3U_RSTC_MR_OFFSET 0x08 /* Mode Register */ + +/* RSTC register adresses ***************************************************************/ + +#define SAM3U_RSTC_CR (SAM3U_RSTC_BASE+SAM3U_RSTC_CR_OFFSET) +#define SAM3U_RSTC_SR (SAM3U_RSTC_BASE+SAM3U_RSTC_SR_OFFSET) +#define SAM3U_RSTC_MR (SAM3U_RSTC_BASE+SAM3U_RSTC_MR_OFFSET) + +/* RSTC register bit definitions ********************************************************/ + +#define RSTC_CR_PROCRST (1 << 0) /* Bit 0: Processor Reset */ +#define RSTC_CR_PERRST (1 << 2) /* Bit 2: Peripheral Reset */ +#define RSTC_CR_EXTRST (1 << 3) /* Bit 3: External Reset */ +#define RSTC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ +#define RSTC_CR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT) + +#define RSTC_SR_URSTS (1 << 0) /* Bit 0: User Reset Status */ +#define RSTC_SR_RSTTYP_SHIFT (8) /* Bits 8-10: Reset Type */ +#define RSTC_SR_RSTTYP_MASK (7 << RSTC_SR_RSTTYP_SHIFT) +# define RSTC_SR_RSTTYP_PWRUP (0 << RSTC_SR_RSTTYP_SHIFT) /* General Reset */ +# define RSTC_SR_RSTTYP_BACKUP (1 << RSTC_SR_RSTTYP_SHIFT) /* Backup Reset */ +# define RSTC_SR_RSTTYP_WDOG (2 << RSTC_SR_RSTTYP_SHIFT) /* Watchdog Reset */ +# define RSTC_SR_RSTTYP_SWRST (3 << RSTC_SR_RSTTYP_SHIFT) /* Software Reset */ +# define RSTC_SR_RSTTYP_NRST (4 << RSTC_SR_RSTTYP_SHIFT) /* User Reset NRST pin */ +#define RSTC_SR_NRSTL (1 << 16) /* Bit 16: NRST Pin Level */ +#define RSTC_SR_SRCMP (1 << 17) /* Bit 17: Software Reset Command in Progress */ + +#define RSTC_MR_URSTEN (1 << 0) /* Bit 0: User Reset Enable */ +#define RSTC_MR_URSTIEN (1 << 4) /* Bit 4: User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL_SHIFT (8) /* Bits 8-11: External Reset Length */ +#define RSTC_MR_ERSTL_MASK (15 << RSTC_MR_ERSTL_SHIFT) +#define RSTC_MR_KEY_SHIFT (24) /* Bits 24-31: Password */ +#define RSTC_MR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_RSTC_H */ diff --git a/arch/arm/src/sam3u/sam3u_rtc.h b/arch/arm/src/sam3u/sam3u_rtc.h index 479afb04548c72855aa87c26b6d079247d02a7f6..61e6bb68ed2a7d3306cb14f2675d8080eaa665a2 100644 --- a/arch/arm/src/sam3u/sam3u_rtc.h +++ b/arch/arm/src/sam3u/sam3u_rtc.h @@ -1,184 +1,184 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_rtc.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_RTC_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_RTC_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* RTC register offsets *****************************************************************/ - -#define SAM3U_RTC_CR_OFFSET 0x00 /* Control Register */ -#define SAM3U_RTC_MR_OFFSET 0x04 /* Mode Register */ -#define SAM3U_RTC_TIMR_OFFSET 0x08 /* Time Register */ -#define SAM3U_RTC_CALR_OFFSET 0x0c /* Calendar Register */ -#define SAM3U_RTC_TIMALR_OFFSET 0x10 /* Time Alarm Register */ -#define SAM3U_RTC_CALALR_OFFSET 0x14 /* Calendar Alarm Register */ -#define SAM3U_RTC_SR_OFFSET 0x18 /* Status Register */ -#define SAM3U_RTC_SCCR_OFFSET 0x1c /* Status Clear Command Register */ -#define SAM3U_RTC_IER_OFFSET 0x20 /* Interrupt Enable Register */ -#define SAM3U_RTC_IDR_OFFSET 0x24 /* Interrupt Disable Register */ -#define SAM3U_RTC_IMR_OFFSET 0x28 /* Interrupt Mask Register */ -#define SAM3U_RTC_VER_OFFSET 0x2c /* Valid Entry Register */ - -/* RTC register adresses ****************************************************************/ - -#define SAM3U_RTC_CR (SAM3U_RTC_BASE+SAM3U_RTC_CR_OFFSET) -#define SAM3U_RTC_MR (SAM3U_RTC_BASE+SAM3U_RTC_MR_OFFSET) -#define SAM3U_RTC_TIMR (SAM3U_RTC_BASE+SAM3U_RTC_TIMR_OFFSET) -#define SAM3U_RTC_CALR (SAM3U_RTC_BASE+SAM3U_RTC_CALR_OFFSET) -#define SAM3U_RTC_TIMALR (SAM3U_RTC_BASE+SAM3U_RTC_TIMALR_OFFSET) -#define SAM3U_RTC_CALALR (SAM3U_RTC_BASE+SAM3U_RTC_CALALR_OFFSET) -#define SAM3U_RTC_SR (SAM3U_RTC_BASE+SAM3U_RTC_SR_OFFSET) -#define SAM3U_RTC_SCCR (SAM3U_RTC_BASE+SAM3U_RTC_SCCR_OFFSET) -#define SAM3U_RTC_IER (SAM3U_RTC_BASE+SAM3U_RTC_IER_OFFSET) -#define SAM3U_RTC_IDR (SAM3U_RTC_BASE+SAM3U_RTC_IDR_OFFSET) -#define SAM3U_RTC_IMR (SAM3U_RTC_BASE+SAM3U_RTC_IMR_OFFSET) -#define SAM3U_RTC_VER (SAM3U_RTC_BASE+SAM3U_RTC_VER_OFFSET) - -/* RTC register bit definitions *********************************************************/ - -#define RTC_CR_UPDTIM (1 << 0) /* Bit 0: Update Request Time Register */ -#define RTC_CR_UPDCAL (1 << 1) /* Bit 1: Update Request Calendar Register */ -#define RTC_CR_TIMEVSEL_SHIFT (8) /* Bits 8-9: Time Event Selection */ -#define RTC_CR_TIMEVSEL_MASK (3 << RTC_CR_TIMEVSEL_SHIFT) -# define RTC_CR_TIMEVSEL_MIN (0 << RTC_CR_TIMEVSEL_SHIFT) -# define RTC_CR_TIMEVSEL_HOUR (1 << RTC_CR_TIMEVSEL_SHIFT) -# define RTC_CR_TIMEVSEL_MIDNIGHT (2 << RTC_CR_TIMEVSEL_SHIFT) -# define RTC_CR_TIMEVSEL_NOON (3 << RTC_CR_TIMEVSEL_SHIFT) -#define RTC_CR_CALEVSEL_SHIFT (16) /* Bits 16-17: Calendar Event Selection */ -#define RTC_CR_CALEVSEL_MASK (3 << RTC_CR_CALEVSEL_SHIFT) -# define RTC_CR_CALEVSEL_WEEK (0 << RTC_CR_CALEVSEL_SHIFT) -# define RTC_CR_CALEVSEL_MONTH (1 << RTC_CR_CALEVSEL_SHIFT) -# define RTC_CR_CALEVSEL_YEAR (2 << RTC_CR_CALEVSEL_SHIFT) - -#define RTC_MR_HRMOD (1 << 0) /* Bit 0: 12-/24-hour Mode */ - -#define RTC_TIMR_SEC_SHIFT (0) /* Bits 0-6: Current Second */ -#define RTC_TIMR_SEC_MASK (0x7f << RTC_TIMR_SEC_SHIFT) -#define RTC_TIMR_MIN_SHIFT (8) /* Bits 8-14: Current Minute */ -#define RTC_TIMR_MIN_MASK (0x7f << RTC_TIMR_MIN_SHIFT) -#define RTC_TIMR_HOUR_SHIFT (16) /* Bits 16-21: Current Hour */ -#define RTC_TIMR_HOUR_MASK (0x3f << RTC_TIMR_HOUR_SHIFT) -#define RTC_TIMR_AMPM (1 << 22) /* Bit 22: Ante Meridiem Post Meridiem Indicator */ - -#define RTC_CALR_CENT_SHIFT (0) /* Bits 0-6: Current Century */ -#define RTC_CALR_CENT_MASK (0x7f << RTC_TIMR_HOUR_SHIFT) -#define RTC_CALR_YEAR_SHIFT (8) /* Bits 8-15: Current Year */ -#define RTC_CALR_YEAR_MASK (0xff << RTC_CALR_YEAR_SHIFT) -#define RTC_CALR_MONTH_SHIFT (16) /* Bits 16-20: Current Month */ -#define RTC_CALR_MONTH_MASK (0x1f << RTC_CALR_MONTH_SHIFT) -#define RTC_CALR_DAY_SHIFT (21) /* Bits 21-23: Current Day in Current Week */ -#define RTC_CALR_DAY_MASK (7 << RTC_CALR_DAY_SHIFT) -#define RTC_CALR_DATE_SHIFT (24) /* Bits 24-29: Current Day in Current Month */ -#define RTC_CALR_DATE_MASK (0x3f << RTC_CALR_DATE_SHIFT) - -#define RTC_TIMALR_SEC_SHIFT (0) /* Bits 0-6: Second Alarm */ -#define RTC_TIMALR_SEC_MASK (0x7f << RTC_TIMALR_SEC_SHIFT) -#define RTC_TIMALR_SECEN (1 << 7) /* Bit 7: Second Alarm Enable */ -#define RTC_TIMALR_MIN_SHIFT (8) /* Bits 8-14: Minute Alarm */ -#define RTC_TIMALR_MIN_MASK (0x7f << RTC_TIMALR_MIN_SHIFT) -#define RTC_TIMALR_MINEN (1 << 15) /* Bit 15: Minute Alarm Enable */ -#define RTC_TIMALR_HOUR_SHIFT (16) /* Bits 16-21: Hour Alarm */ -#define RTC_TIMALR_HOUR_MASK (0x3f << RTC_TIMALR_HOUR_SHIFT) -#define RTC_TIMALR_AMPM (1 << 22) /* Bit 22: AM/PM Indicator */ -#define RTC_TIMALR_HOUREN (1 << 23) /* Bit 23: Hour Alarm Enable */ - -#define RTC_CALALR_MONTH_SHIFT (16) /* Bits 16-20: Month Alarm */ -#define RTC_CALALR_MONTH_MASK (0x1f << RTC_CALALR_MONTH_SHIFT) -#define RTC_CALALR_MTHEN (1 << 23) /* Bit 23: Month Alarm Enable */ -#define RTC_CALALR_DATE_SHIFT (24) /* Bits 24-29: Date Alarm */ -#define RTC_CALALR_DATE_MASK (0x3c << RTC_CALALR_DATE_SHIFT) -#define RTC_CALALR_DATEEN (1 << 31) /* Bit 31: Date Alarm Enable */ - -#define RTC_SR_ACKUPD (1 << 0) /* Bit 0: Acknowledge for Update */ -#define RTC_SR_ALARM (1 << 1) /* Bit 1: Alarm Flag */ -#define RTC_SR_SEC (1 << 2) /* Bit 2: Second Event */ -#define RTC_SR_TIMEV (1 << 3) /* Bit 3: Time Event */ -#define RTC_SR_CALEV (1 << 4) /* Bit 4: Calendar Event */ - -#define RTC_SCCR_ACKCLR (1 << 0) /* Bit 0: Acknowledge Clear */ -#define RTC_SCCR_ALRCLR (1 << 1) /* Bit 1: Alarm Clear */ -#define RTC_SCCR_SECCLR (1 << 2) /* Bit 2: Second Clear */ -#define RTC_SCCR_TIMCLR (1 << 3) /* Bit 3: Time Clear */ -#define RTC_SCCR_CALCLR (1 << 4) /* Bit 4: Calendar Clear */ - -#define RTC_IER_ACKEN (1 << 0) /* Bit 0: Acknowledge Update Interrupt Enable */ -#define RTC_IER_ALREN (1 << 1) /* Bit 1: Alarm Interrupt Enable */ -#define RTC_IER_SECEN (1 << 2) /* Bit 2: Second Event Interrupt Enable */ -#define RTC_IER_TIMEN (1 << 3) /* Bit 3: Time Event Interrupt Enable */ -#define RTC_IER_CALEN (1 << 4) /* Bit 4: Calendar Event Interrupt Enable */ - -#define RTC_IDR_ACKDIS (1 << 0) /* Bit 0: Acknowledge Update Interrupt Disable */ -#define RTC_IDR_ALRDIS (1 << 1) /* Bit 1: Alarm Interrupt Disable */ -#define RTC_IDR_SECDIS (1 << 2) /* Bit 2: Second Event Interrupt Disable */ -#define RTC_IDR_TIMDIS (1 << 3) /* Bit 3: Time Event Interrupt Disable */ -#define RTC_IDR_CALDIS (1 << 4) /* Bit 4: Calendar Event Interrupt Disable */ - -#define RTC_IMR_ACK (1 << 0) /* Bit 0: Acknowledge Update Interrupt Mask */ -#define RTC_IMR_ALR (1 << 1) /* Bit 1: Alarm Interrupt Mask */ -#define RTC_IMR_SEC (1 << 2) /* Bit 2: Second Event Interrupt Mask */ -#define RTC_IMR_TIM (1 << 3) /* Bit 3: Time Event Interrupt Mask */ -#define RTC_IMR_CAL (1 << 4) /* Bit 4: Calendar Event Interrupt Mask */ - -#define RTC_VER_NVTIM (1 << 0) /* Bit 0: Non-valid Time */ -#define RTC_VER_NVCAL (1 << 1) /* Bit 1: Non-valid Calendar */ -#define RTC_VER_NVTIMALR (1 << 2) /* Bit 2: Non-valid Time Alarm */ -#define RTC_VER_NVCALALR (1 << 3) /* Bit 3: Non-valid Calendar Alarm */ - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_RTC_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_rtc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_RTC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_RTC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* RTC register offsets *****************************************************************/ + +#define SAM3U_RTC_CR_OFFSET 0x00 /* Control Register */ +#define SAM3U_RTC_MR_OFFSET 0x04 /* Mode Register */ +#define SAM3U_RTC_TIMR_OFFSET 0x08 /* Time Register */ +#define SAM3U_RTC_CALR_OFFSET 0x0c /* Calendar Register */ +#define SAM3U_RTC_TIMALR_OFFSET 0x10 /* Time Alarm Register */ +#define SAM3U_RTC_CALALR_OFFSET 0x14 /* Calendar Alarm Register */ +#define SAM3U_RTC_SR_OFFSET 0x18 /* Status Register */ +#define SAM3U_RTC_SCCR_OFFSET 0x1c /* Status Clear Command Register */ +#define SAM3U_RTC_IER_OFFSET 0x20 /* Interrupt Enable Register */ +#define SAM3U_RTC_IDR_OFFSET 0x24 /* Interrupt Disable Register */ +#define SAM3U_RTC_IMR_OFFSET 0x28 /* Interrupt Mask Register */ +#define SAM3U_RTC_VER_OFFSET 0x2c /* Valid Entry Register */ + +/* RTC register adresses ****************************************************************/ + +#define SAM3U_RTC_CR (SAM3U_RTC_BASE+SAM3U_RTC_CR_OFFSET) +#define SAM3U_RTC_MR (SAM3U_RTC_BASE+SAM3U_RTC_MR_OFFSET) +#define SAM3U_RTC_TIMR (SAM3U_RTC_BASE+SAM3U_RTC_TIMR_OFFSET) +#define SAM3U_RTC_CALR (SAM3U_RTC_BASE+SAM3U_RTC_CALR_OFFSET) +#define SAM3U_RTC_TIMALR (SAM3U_RTC_BASE+SAM3U_RTC_TIMALR_OFFSET) +#define SAM3U_RTC_CALALR (SAM3U_RTC_BASE+SAM3U_RTC_CALALR_OFFSET) +#define SAM3U_RTC_SR (SAM3U_RTC_BASE+SAM3U_RTC_SR_OFFSET) +#define SAM3U_RTC_SCCR (SAM3U_RTC_BASE+SAM3U_RTC_SCCR_OFFSET) +#define SAM3U_RTC_IER (SAM3U_RTC_BASE+SAM3U_RTC_IER_OFFSET) +#define SAM3U_RTC_IDR (SAM3U_RTC_BASE+SAM3U_RTC_IDR_OFFSET) +#define SAM3U_RTC_IMR (SAM3U_RTC_BASE+SAM3U_RTC_IMR_OFFSET) +#define SAM3U_RTC_VER (SAM3U_RTC_BASE+SAM3U_RTC_VER_OFFSET) + +/* RTC register bit definitions *********************************************************/ + +#define RTC_CR_UPDTIM (1 << 0) /* Bit 0: Update Request Time Register */ +#define RTC_CR_UPDCAL (1 << 1) /* Bit 1: Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL_SHIFT (8) /* Bits 8-9: Time Event Selection */ +#define RTC_CR_TIMEVSEL_MASK (3 << RTC_CR_TIMEVSEL_SHIFT) +# define RTC_CR_TIMEVSEL_MIN (0 << RTC_CR_TIMEVSEL_SHIFT) +# define RTC_CR_TIMEVSEL_HOUR (1 << RTC_CR_TIMEVSEL_SHIFT) +# define RTC_CR_TIMEVSEL_MIDNIGHT (2 << RTC_CR_TIMEVSEL_SHIFT) +# define RTC_CR_TIMEVSEL_NOON (3 << RTC_CR_TIMEVSEL_SHIFT) +#define RTC_CR_CALEVSEL_SHIFT (16) /* Bits 16-17: Calendar Event Selection */ +#define RTC_CR_CALEVSEL_MASK (3 << RTC_CR_CALEVSEL_SHIFT) +# define RTC_CR_CALEVSEL_WEEK (0 << RTC_CR_CALEVSEL_SHIFT) +# define RTC_CR_CALEVSEL_MONTH (1 << RTC_CR_CALEVSEL_SHIFT) +# define RTC_CR_CALEVSEL_YEAR (2 << RTC_CR_CALEVSEL_SHIFT) + +#define RTC_MR_HRMOD (1 << 0) /* Bit 0: 12-/24-hour Mode */ + +#define RTC_TIMR_SEC_SHIFT (0) /* Bits 0-6: Current Second */ +#define RTC_TIMR_SEC_MASK (0x7f << RTC_TIMR_SEC_SHIFT) +#define RTC_TIMR_MIN_SHIFT (8) /* Bits 8-14: Current Minute */ +#define RTC_TIMR_MIN_MASK (0x7f << RTC_TIMR_MIN_SHIFT) +#define RTC_TIMR_HOUR_SHIFT (16) /* Bits 16-21: Current Hour */ +#define RTC_TIMR_HOUR_MASK (0x3f << RTC_TIMR_HOUR_SHIFT) +#define RTC_TIMR_AMPM (1 << 22) /* Bit 22: Ante Meridiem Post Meridiem Indicator */ + +#define RTC_CALR_CENT_SHIFT (0) /* Bits 0-6: Current Century */ +#define RTC_CALR_CENT_MASK (0x7f << RTC_TIMR_HOUR_SHIFT) +#define RTC_CALR_YEAR_SHIFT (8) /* Bits 8-15: Current Year */ +#define RTC_CALR_YEAR_MASK (0xff << RTC_CALR_YEAR_SHIFT) +#define RTC_CALR_MONTH_SHIFT (16) /* Bits 16-20: Current Month */ +#define RTC_CALR_MONTH_MASK (0x1f << RTC_CALR_MONTH_SHIFT) +#define RTC_CALR_DAY_SHIFT (21) /* Bits 21-23: Current Day in Current Week */ +#define RTC_CALR_DAY_MASK (7 << RTC_CALR_DAY_SHIFT) +#define RTC_CALR_DATE_SHIFT (24) /* Bits 24-29: Current Day in Current Month */ +#define RTC_CALR_DATE_MASK (0x3f << RTC_CALR_DATE_SHIFT) + +#define RTC_TIMALR_SEC_SHIFT (0) /* Bits 0-6: Second Alarm */ +#define RTC_TIMALR_SEC_MASK (0x7f << RTC_TIMALR_SEC_SHIFT) +#define RTC_TIMALR_SECEN (1 << 7) /* Bit 7: Second Alarm Enable */ +#define RTC_TIMALR_MIN_SHIFT (8) /* Bits 8-14: Minute Alarm */ +#define RTC_TIMALR_MIN_MASK (0x7f << RTC_TIMALR_MIN_SHIFT) +#define RTC_TIMALR_MINEN (1 << 15) /* Bit 15: Minute Alarm Enable */ +#define RTC_TIMALR_HOUR_SHIFT (16) /* Bits 16-21: Hour Alarm */ +#define RTC_TIMALR_HOUR_MASK (0x3f << RTC_TIMALR_HOUR_SHIFT) +#define RTC_TIMALR_AMPM (1 << 22) /* Bit 22: AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (1 << 23) /* Bit 23: Hour Alarm Enable */ + +#define RTC_CALALR_MONTH_SHIFT (16) /* Bits 16-20: Month Alarm */ +#define RTC_CALALR_MONTH_MASK (0x1f << RTC_CALALR_MONTH_SHIFT) +#define RTC_CALALR_MTHEN (1 << 23) /* Bit 23: Month Alarm Enable */ +#define RTC_CALALR_DATE_SHIFT (24) /* Bits 24-29: Date Alarm */ +#define RTC_CALALR_DATE_MASK (0x3c << RTC_CALALR_DATE_SHIFT) +#define RTC_CALALR_DATEEN (1 << 31) /* Bit 31: Date Alarm Enable */ + +#define RTC_SR_ACKUPD (1 << 0) /* Bit 0: Acknowledge for Update */ +#define RTC_SR_ALARM (1 << 1) /* Bit 1: Alarm Flag */ +#define RTC_SR_SEC (1 << 2) /* Bit 2: Second Event */ +#define RTC_SR_TIMEV (1 << 3) /* Bit 3: Time Event */ +#define RTC_SR_CALEV (1 << 4) /* Bit 4: Calendar Event */ + +#define RTC_SCCR_ACKCLR (1 << 0) /* Bit 0: Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (1 << 1) /* Bit 1: Alarm Clear */ +#define RTC_SCCR_SECCLR (1 << 2) /* Bit 2: Second Clear */ +#define RTC_SCCR_TIMCLR (1 << 3) /* Bit 3: Time Clear */ +#define RTC_SCCR_CALCLR (1 << 4) /* Bit 4: Calendar Clear */ + +#define RTC_IER_ACKEN (1 << 0) /* Bit 0: Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (1 << 1) /* Bit 1: Alarm Interrupt Enable */ +#define RTC_IER_SECEN (1 << 2) /* Bit 2: Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (1 << 3) /* Bit 3: Time Event Interrupt Enable */ +#define RTC_IER_CALEN (1 << 4) /* Bit 4: Calendar Event Interrupt Enable */ + +#define RTC_IDR_ACKDIS (1 << 0) /* Bit 0: Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (1 << 1) /* Bit 1: Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (1 << 2) /* Bit 2: Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (1 << 3) /* Bit 3: Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (1 << 4) /* Bit 4: Calendar Event Interrupt Disable */ + +#define RTC_IMR_ACK (1 << 0) /* Bit 0: Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (1 << 1) /* Bit 1: Alarm Interrupt Mask */ +#define RTC_IMR_SEC (1 << 2) /* Bit 2: Second Event Interrupt Mask */ +#define RTC_IMR_TIM (1 << 3) /* Bit 3: Time Event Interrupt Mask */ +#define RTC_IMR_CAL (1 << 4) /* Bit 4: Calendar Event Interrupt Mask */ + +#define RTC_VER_NVTIM (1 << 0) /* Bit 0: Non-valid Time */ +#define RTC_VER_NVCAL (1 << 1) /* Bit 1: Non-valid Calendar */ +#define RTC_VER_NVTIMALR (1 << 2) /* Bit 2: Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (1 << 3) /* Bit 3: Non-valid Calendar Alarm */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_RTC_H */ diff --git a/arch/arm/src/sam3u/sam3u_rtt.h b/arch/arm/src/sam3u/sam3u_rtt.h index ea25fbc4abd8aa6bb4e2ed5692420d83bf54ec1b..9cbb69b0a386c0e8ee1923ebb3b682605e5bfbbd 100644 --- a/arch/arm/src/sam3u/sam3u_rtt.h +++ b/arch/arm/src/sam3u/sam3u_rtt.h @@ -1,89 +1,89 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_rtt.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_RTT_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_RTT_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* RTT register offsets *****************************************************************/ - -#define SAM3U_RTT_MR_OFFSET 0x00 /* Mode Register */ -#define SAM3U_RTT_AR_OFFSET 0x04 /* Alarm Register */ -#define SAM3U_RTT_VR_OFFSET 0x08 /* Value Register */ -#define SAM3U_RTT_SR_OFFSET 0x0c /* Status Register */ - -/* RTT register adresses ***************************************************************/ - -#define SAM3U_RTT_MR (SAM3U_RTT_BASE+SAM3U_RTT_MR_OFFSET) -#define SAM3U_RTT_AR (SAM3U_RTT_BASE+SAM3U_RTT_AR_OFFSET) -#define SAM3U_RTT_VR (SAM3U_RTT_BASE+SAM3U_RTT_VR_OFFSET) -#define SAM3U_RTT_SR (SAM3U_RTT_BASE+SAM3U_RTT_SR_OFFSET) - -/* RTT register bit definitions ********************************************************/ - -#define RTT_MR_RTPRES_SHIFT (0) /* Bits 0-15: Real-time Timer Prescaler Value */ -#define RTT_MR_RTPRES__MASK (0xffff << RTT_MR_RTPRES_SHIFT) -#define RTT_MR_ALMIEN (1 << 16) /* Bit 16: Alarm Interrupt Enable */ -#define RTT_MR_RTTINCIEN (1 << 17) /* Bit 17: Real-time Timer Increment Int Enable */ -#define RTT_MR_RTTRST (1 << 18) /* Bit 18: Real-time Timer Restart */ - -#define RTT_SR_ALMS (1 << 0) /* Bit 0: Real-time Alarm Status */ -#define RTT_SR_RTTINC (1 << 1) /* Bit 1: Real-time Timer Increment */ - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_RTT_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_rtt.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_RTT_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_RTT_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* RTT register offsets *****************************************************************/ + +#define SAM3U_RTT_MR_OFFSET 0x00 /* Mode Register */ +#define SAM3U_RTT_AR_OFFSET 0x04 /* Alarm Register */ +#define SAM3U_RTT_VR_OFFSET 0x08 /* Value Register */ +#define SAM3U_RTT_SR_OFFSET 0x0c /* Status Register */ + +/* RTT register adresses ***************************************************************/ + +#define SAM3U_RTT_MR (SAM3U_RTT_BASE+SAM3U_RTT_MR_OFFSET) +#define SAM3U_RTT_AR (SAM3U_RTT_BASE+SAM3U_RTT_AR_OFFSET) +#define SAM3U_RTT_VR (SAM3U_RTT_BASE+SAM3U_RTT_VR_OFFSET) +#define SAM3U_RTT_SR (SAM3U_RTT_BASE+SAM3U_RTT_SR_OFFSET) + +/* RTT register bit definitions ********************************************************/ + +#define RTT_MR_RTPRES_SHIFT (0) /* Bits 0-15: Real-time Timer Prescaler Value */ +#define RTT_MR_RTPRES__MASK (0xffff << RTT_MR_RTPRES_SHIFT) +#define RTT_MR_ALMIEN (1 << 16) /* Bit 16: Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (1 << 17) /* Bit 17: Real-time Timer Increment Int Enable */ +#define RTT_MR_RTTRST (1 << 18) /* Bit 18: Real-time Timer Restart */ + +#define RTT_SR_ALMS (1 << 0) /* Bit 0: Real-time Alarm Status */ +#define RTT_SR_RTTINC (1 << 1) /* Bit 1: Real-time Timer Increment */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_RTT_H */ diff --git a/arch/arm/src/sam3u/sam3u_smc.h b/arch/arm/src/sam3u/sam3u_smc.h index f8b6e837e192e8d109beea6190f8e39efb6665c6..c831a91cde1517ca3eddda794e87ea0b6c091ea0 100644 --- a/arch/arm/src/sam3u/sam3u_smc.h +++ b/arch/arm/src/sam3u/sam3u_smc.h @@ -1,432 +1,432 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_smc.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_SMC_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_SMC_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* SMC register offsets *****************************************************************/ - -#define SAM3U_SMC_CFG_OFFSET 0x000 /* SMC NFC Configuration Register */ -#define SAM3U_SMC_CTRL_OFFSET 0x004 /* SMC NFC Control Register */ -#define SAM3U_SMC_SR_OFFSET 0x008 /* SMC NFC Status Register */ -#define SAM3U_SMC_IER_OFFSET 0x00c /* SMC NFC Interrupt Enable Register */ -#define SAM3U_SMC_IDR_OFFSET 0x010 /* SMC NFC Interrupt Disable Register */ -#define SAM3U_SMC_IMR_OFFSET 0x014 /* SMC NFC Interrupt Mask Register */ -#define SAM3U_SMC_ADDR_OFFSET 0x018 /* SMC NFC Address Cycle Zero Register */ -#define SAM3U_SMC_BANK_OFFSET 0x01c /* SMC Bank Address Register */ -#define SAM3U_SMC_ECCCTRL_OFFSET 0x020 /* SMC ECC Control Register */ -#define SAM3U_SMC_ECCMD_OFFSET 0x024 /* SMC ECC Mode Register */ -#define SAM3U_SMC_ECCSR1_OFFSET 0x028 /* SMC ECC Status 1 Register */ -#define SAM3U_SMC_ECCPR0_OFFSET 0x02c /* SMC ECC parity 0 Register */ -#define SAM3U_SMC_ECCPR1_OFFSET 0x030 /* SMC ECC parity 1 Register */ -#define SAM3U_SMC_ECCSR2_OFFSET 0x034 /* SMC ECC status 2 Register */ -#define SAM3U_SMC_ECCPR2_OFFSET 0x038 /* SMC ECC parity 2 Register */ -#define SAM3U_SMC_ECCPR3_OFFSET 0x03c /* SMC ECC parity 3 Register */ -#define SAM3U_SMC_ECCPR4_OFFSET 0x040 /* SMC ECC parity 4 Register */ -#define SAM3U_SMC_ECCPR5_OFFSET 0x044 /* SMC ECC parity 5 Register */ -#define SAM3U_SMC_ECCPR6_OFFSET 0x048 /* SMC ECC parity 6 Register */ -#define SAM3U_SMC_ECCPR7_OFFSET 0x04c /* SMC ECC parity 7 Register */ -#define SAM3U_SMC_ECCPR8_OFFSET 0x050 /* SMC ECC parity 8 Register */ -#define SAM3U_SMC_ECCPR9_OFFSET 0x054 /* SMC ECC parity 9 Register */ -#define SAM3U_SMC_ECCPR10_OFFSET 0x058 /* SMC ECC parity 10 Register */ -#define SAM3U_SMC_ECCPR11_OFFSET 0x05c /* SMC ECC parity 11 Register */ -#define SAM3U_SMC_ECCPR12_OFFSET 0x060 /* SMC ECC parity 12 Register */ -#define SAM3U_SMC_ECCPR13_OFFSET 0x064 /* SMC ECC parity 13 Register */ -#define SAM3U_SMC_ECCPR14_OFFSET 0x068 /* SMC ECC parity 14 Register */ -#define SAM3U_SMC_ECCPR15_OFFSET 0x06c /* SMC ECC parity 15 Register */ - -#define SAM3U_SMCCS_OFFSET(n) (0x070+((n)*0x014)) -#define SAM3U_SMCCS_SETUP_OFFSET 0x000 /* SMC SETUP Register */ -#define SAM3U_SMCCS_PULSE_OFFSET 0x004 /* SMC PULSE Register */ -#define SAM3U_SMCCS_CYCLE_OFFSET 0x008 /* SMC CYCLE Register */ -#define SAM3U_SMCCS_TIMINGS_OFFSET 0x00c /* SMC TIMINGS Register */ -#define SAM3U_SMCCS_MODE_OFFSET 0x010 /* SMC MODE Register */ - -#define SAM3U_SMC_OCMS_OFFSET 0x110 /* SMC OCMS MODE Register */ -#define SAM3U_SMC_KEY1_OFFSET 0x114 /* SMC KEY1 Register */ -#define SAM3U_SMC_KEY2_OFFSET 0x118 /* SMC KEY2 Register */ -#define SAM3U_SMC_WPCR_OFFSET 0x1e4 /* Write Protection Control Register */ -#define SAM3U_SMC_WPSR_OFFSET 0x1e8 /* Write Protection Status Register */ - -/* SMC register adresses ****************************************************************/ - -#define SAM3U_SMC_CFG (SAM3U_SMC_BASE+SAM3U_SMC_CFG_OFFSET) -#define SAM3U_SMC_CTRL (SAM3U_SMC_BASE+SAM3U_SMC_CTRL_OFFSET) -#define SAM3U_SMC_SR (SAM3U_SMC_BASE+SAM3U_SMC_SR_OFFSET) -#define SAM3U_SMC_IER (SAM3U_SMC_BASE+SAM3U_SMC_IER_OFFSET) -#define SAM3U_SMC_IDR (SAM3U_SMC_BASE+SAM3U_SMC_IDR_OFFSET) -#define SAM3U_SMC_IMR (SAM3U_SMC_BASE+SAM3U_SMC_IMR_OFFSET) -#define SAM3U_SMC_ADDR (SAM3U_SMC_BASE+SAM3U_SMC_ADDR_OFFSET) -#define SAM3U_SMC_BANK (SAM3U_SMC_BASE+SAM3U_SMC_BANK_OFFSET) -#define SAM3U_SMC_ECCCTRL (SAM3U_SMC_BASE+SAM3U_SMC_ECCCTRL_OFFSET) -#define SAM3U_SMC_ECCMD (SAM3U_SMC_BASE+SAM3U_SMC_ECCMD_OFFSET) -#define SAM3U_SMC_ECCSR1 (SAM3U_SMC_BASE+SAM3U_SMC_ECCSR1_OFFSET) -#define SAM3U_SMC_ECCPR0 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR0_OFFSET) -#define SAM3U_SMC_ECCPR1 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR1_OFFSET) -#define SAM3U_SMC_ECCSR2 (SAM3U_SMC_BASE+SAM3U_SMC_ECCSR2_OFFSET) -#define SAM3U_SMC_ECCPR2 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR2_OFFSET) -#define SAM3U_SMC_ECCPR3 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR3_OFFSET) -#define SAM3U_SMC_ECCPR4 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR4_OFFSET) -#define SAM3U_SMC_ECCPR5 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR5_OFFSET) -#define SAM3U_SMC_ECCPR6 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR6_OFFSET) -#define SAM3U_SMC_ECCPR7 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR7_OFFSET) -#define SAM3U_SMC_ECCPR8 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR8_OFFSET) -#define SAM3U_SMC_ECCPR9 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR9_OFFSET) -#define SAM3U_SMC_ECCPR10 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR10_OFFSET) -#define SAM3U_SMC_ECCPR11 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR11_OFFSET) -#define SAM3U_SMC_ECCPR12 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR12_OFFSET) -#define SAM3U_SMC_ECCPR13 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR13_OFFSET) -#define SAM3U_SMC_ECCPR14 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR14_OFFSET) -#define SAM3U_SMC_ECCPR15 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR15_OFFSET) - -#define SAM3U_SMCCS_BASE(n) (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(n)) -# define SAM3U_SMC_CS0_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(0)) -# define SAM3U_SMC_CS1_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(1)) -# define SAM3U_SMC_CS2_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(2)) -# define SAM3U_SMC_CS3_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(3)) -#define SAM3U_SMCCS_SETUP(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_SETUP_OFFSET) -#define SAM3U_SMCCS_PULSE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_PULSE_OFFSET) -#define SAM3U_SMCCS_CYCLE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_CYCLE_OFFSET) -#define SAM3U_SMCCS_TIMINGS(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_TIMINGS_OFFSET) -#define SAM3U_SMCCS_MODE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_MODE_OFFSET) - -#define SAM3U_SMC_OCMS (SAM3U_SMC_BASE+SAM3U_SMC_OCMS_OFFSET) -#define SAM3U_SMC_KEY1 (SAM3U_SMC_BASE+SAM3U_SMC_KEY1_OFFSET) -#define SAM3U_SMC_KEY2 (SAM3U_SMC_BASE+SAM3U_SMC_KEY2_OFFSET) -#define SAM3U_SMC_WPCR (SAM3U_SMC_BASE+SAM3U_SMC_WPCR_OFFSET) -#define SAM3U_SMC_WPSR (SAM3U_SMC_BASE+SAM3U_SMC_WPSR_OFFSET) - -/* SMC register bit definitions *********************************************************/ - -/* SMC NFC Configuration Register */ - -#define SMC_CFG_PAGESIZE_SHIFT (0) /* Bits 0-1: Page size of NAND Flash device */ -#define SMC_CFG_PAGESIZE_MASK (3 << SMC_CFG_PAGESIZE_SHIFT) -# define SMC_CFG_PAGESIZE_16 BYTES (0 << SMC_CFG_PAGESIZE_SHIFT) /* 528 Bytes 16 byte */ -# define SMC_CFG_PAGESIZE_ 2 BYTES (1 << SMC_CFG_PAGESIZE_SHIFT) /* 1056 Bytes 32 bytes */ -# define SMC_CFG_PAGESIZE_64 BYTES (2 << SMC_CFG_PAGESIZE_SHIFT) /* 2112 Bytes 64 bytes */ -# define SMC_CFG_PAGESIZE_128 BYTES (3 << SMC_CFG_PAGESIZE_SHIFT) /* 4224 Bytes 128 bytes */ -#define SMC_CFG_WSPARE (1 << 8) /* Bit 8: Write Spare Area */ -#define SMC_CFG_RSPARE (1 << 9) /* Bit 9: Read Spare Area */ -#define SMC_CFG_EDGECTRL (1 << 12) /* Bit 12: Rising/Falling Edge Detection Control */ -#define SMC_CFG_RBEDGE (1 << 13) /* Bit 13: Ready/Busy Signal Edge Detection */ -#define SMC_CFG_DTOCYC_SHIFT (16) /* Bits 16-19: Data Timeout Cycle Number */ -#define SMC_CFG_DTOCYC_MASK (15 << SMC_CFG_DTOCYC_SHIFT) -#define SMC_CFG_DTOMUL_SHIFT (20) /* Bits 20-22: Data Timeout Multiplier */ -#define SMC_CFG_DTOMUL_MASK (7 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_1 (0 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_16 (1 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_128 (2 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_256 (3 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_1024 (4 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_4096 (5 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_65536 (6 << SMC_CFG_DTOMUL_SHIFT) -# define SMC_CFG_DTOMUL_1048576 (7 << SMC_CFG_DTOMUL_SHIFT) - -/* SMC NFC Control Register */ - -#define SMC_CTRL_NFCEN (1 << 0) /* Bit 0: NAND Flash Controller Enable */ -#define SMC_CTRL_NFCDIS (1 << 1) /* Bit 1: NAND Flash Controller Disable */ - -/* SMC NFC Status Register, SMC NFC Interrupt Enable Register, SMC NFC Interrupt - * Disable Register, and SMC NFC Interrupt Mask Register common bit-field definitions - */ - -#define SMC_SR_SMCSTS (1 << 0) /* Bit 0: NAND Flash Controller status (SR only) */ -#define SMC_INT_RBRISE (1 << 4) /* Bit 4: Ready Busy Rising Edge Detection Interrupt */ -#define SMC_INT_RBFALL (1 << 5) /* Bit 5: Ready Busy Falling Edge Detection Interrupt */ -#define SMC_SR_NFCBUSY (1 << 8) /* Bit 8: NFC Busy (SR only) */ -#define SMC_SR_NFCWR (1 << 11) /* Bit 11: NFC Write/Read Operation (SR only) */ -#define SMC_SR_NFCSID (1 << 12) /* Bit 13: NFC Chip Select ID (SR only) */ -#define SMC_INT_XFRDONE (1 << 16) /* Bit 16: Transfer Done Interrupt */ -#define SMC_INT_CMDDONE (1 << 17) /* Bit 17: Command Done Interrupt */ -#define SMC_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error Interrupt */ -#define SMC_INT_UNDEF (1 << 21) /* Bit 21: Undefined Area Access Interrupt */ -#define SMC_INT_AWB (1 << 22) /* Bit 22: Accessing While Busy Interrupt */ -#define SMC_INT_NFCASE (1 << 23) /* Bit 23: NFC Access Size Error Interrupt */ -#define SMC_INT_RBEDGE(n) (1<<((n)+24)) -#define SMC_INT_RB_EDGE0 (1 << 24) /* Bit 24: Ready/Busy Line 0 Interrupt */ -#define SMC_INT_RB_EDGE1 (1 << 25) /* Bit 25: Ready/Busy Line 1 Interrupt */ -#define SMC_INT_RB_EDGE2 (1 << 26) /* Bit 26: Ready/Busy Line 2 Interrupt */ -#define SMC_INT_RB_EDGE3 (1 << 27) /* Bit 27: Ready/Busy Line 3 Interrupt */ -#define SMC_INT_RB_EDGE4 (1 << 28) /* Bit 28: Ready/Busy Line 4 Interrupt */ -#define SMC_INT_RB_EDGE5 (1 << 29) /* Bit 29: Ready/Busy Line 5 Interrupt */ -#define SMC_INT_RB_EDGE6 (1 << 30) /* Bit 30: Ready/Busy Line 6 Interrupt */ -#define SMC_INT_RB_EDGE7 (1 << 31) /* Bit 31: Ready/Busy Line 7 Interrupt */ - -/* SMC NFC Address Cycle Zero Register */ - -#define SMC_ADDR_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */ -#define SMC_ADDR_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */ - -/* SMC NFC Bank Register */ - -#define SMC_BANK_SHIFT (0) /* Bits 0-2: Bank identifier */ -#define SMC_BANK_MASK (7 << SMC_BANK_SHIFT) - -/* SMC ECC Control Register */ - -#define SMC_ECCCTRL_RST (1 << 0) /* Bit 0: Reset ECC */ -#define SMC_ECCCTRL_SWRST (1 << 1) /* Bit 1: Software Reset */ - -/* SMC ECC MODE Register */ - -#define SMC_ECCMD_ECC_PAGESIZE_SHIFT (0) /* Bits 0-1 */ -#define SMC_ECCMD_ECC_PAGESIZE_MASK (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) -# define SMC_ECCMD_ECC_PAGESIZE_528 (0 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) -# define SMC_ECCMD_ECC_PAGESIZE_1056 (1 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) -# define SMC_ECCMD_ECC_PAGESIZE_2112 (2 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) -# define SMC_ECCMD_ECC_PAGESIZE_4224 (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) -#define SMC_ECCMD_TYPCORREC_SHIFT (4) /* Bits 4-5: type of correction */ -#define SMC_ECCMD_TYPCORREC_MASK (3 << SMC_ECCMD_TYPCORREC_SHIFT) -# define SMC_ECCMD_TYPCORREC_PAGE (0 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for a page */ -# define SMC_ECCMD_TYPCORREC_256 (1 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 256 bytes */ -# define SMC_ECCMD_TYPCORREC_512 (2 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 512 bytes */ - -/* SMC ECC Status Register 1 */ - -#define _RECERR (0) /* Recoverable Error */ -#define _ECCERR (1) /* ECC Error */ -#define _MULERR (2) /* Multiple Error */ - -#define SMC_ECCSR1_RECERR(n) (1 << (((n)<<4)+_RECERR)) -#define SMC_ECCSR1_ECCERR(n) (1 << (((n)<<4)+_ECCERR)) -#define SMC_ECCSR1_MULERR(n) (1 << (((n)<<4)+_MULERR)) - -#define SMC_ECCSR1_RECERR0 SMC_ECCSR1_RECERR(0) -#define SMC_ECCSR1_ECCERR0 SMC_ECCSR1_ECCERR(0) -#define SMC_ECCSR1_MULERR0 SMC_ECCSR1_MULERR(0) -#define SMC_ECCSR1_RECERR1 SMC_ECCSR1_RECERR(1) -#define SMC_ECCSR1_ECCERR1 SMC_ECCSR1_ECCERR(1) -#define SMC_ECCSR1_MULERR1 SMC_ECCSR1_MULERR(1) -#define SMC_ECCSR1_RECERR2 SMC_ECCSR1_RECERR(2) -#define SMC_ECCSR1_ECCERR2 SMC_ECCSR1_ECCERR(2) -#define SMC_ECCSR1_MULERR2 SMC_ECCSR1_MULERR(2) -#define SMC_ECCSR1_RECERR3 SMC_ECCSR1_RECERR(3) -#define SMC_ECCSR1_ECCERR3 SMC_ECCSR1_ECCERR(3) -#define SMC_ECCSR1_MULERR3 SMC_ECCSR1_MULERR(3) -#define SMC_ECCSR1_RECERR4 SMC_ECCSR1_RECERR(4) -#define SMC_ECCSR1_ECCERR4 SMC_ECCSR1_ECCERR(4) -#define SMC_ECCSR1_MULERR4 SMC_ECCSR1_MULERR(4) -#define SMC_ECCSR1_RECERR5 SMC_ECCSR1_RECERR(5) -#define SMC_ECCSR1_ECCERR5 SMC_ECCSR1_ECCERR(5) -#define SMC_ECCSR1_MULERR5 SMC_ECCSR1_MULERR(5) -#define SMC_ECCSR1_RECERR6 SMC_ECCSR1_RECERR(6) -#define SMC_ECCSR1_ECCERR6 SMC_ECCSR1_ECCERR(6) -#define SMC_ECCSR1_MULERR6 SMC_ECCSR1_MULERR(6) -#define SMC_ECCSR1_RECERR7 SMC_ECCSR1_RECERR(7) -#define SMC_ECCSR1_ECCERR7 SMC_ECCSR1_ECCERR(7) -#define SMC_ECCSR1_MULERR7 SMC_ECCSR1_MULERR(7) - -/* SMC ECC Status Register 2 */ - -#define SMC_ECCSR2_RECERR(n) (1 << ((((n)-8)<<4)+_RECERR)) -#define SMC_ECCSR2_ECCERR(n) (1 << ((((n)-8)<<4)+_ECCERR)) -#define SMC_ECCSR2_MULERR(n) (1 << ((((n)-8)<<4)+_MULERR)) - -#define SMC_ECCSR2_RECERR8 SMC_ECCSR2_RECERR(8) -#define SMC_ECCSR2_ECCERR8 SMC_ECCSR2_ECCERR(8) -#define SMC_ECCSR2_MULERR8 SMC_ECCSR2_MULERR(8) -#define SMC_ECCSR2_RECERR9 SMC_ECCSR2_RECERR(9) -#define SMC_ECCSR2_ECCERR9 SMC_ECCSR2_ECCERR(9) -#define SMC_ECCSR2_MULERR9 SMC_ECCSR2_MULERR(9) -#define SMC_ECCSR2_RECERR10 SMC_ECCSR2_RECERR(10) -#define SMC_ECCSR2_ECCERR10 SMC_ECCSR2_ECCERR(10) -#define SMC_ECCSR2_MULERR10 SMC_ECCSR2_MULERR(10) -#define SMC_ECCSR2_RECERR11 SMC_ECCSR2_RECERR(11) -#define SMC_ECCSR2_ECCERR11 SMC_ECCSR2_ECCERR(11) -#define SMC_ECCSR2_MULERR11 SMC_ECCSR2_MULERR(11) -#define SMC_ECCSR2_RECERR12 SMC_ECCSR2_RECERR(12) -#define SMC_ECCSR2_ECCERR12 SMC_ECCSR2_ECCERR(12) -#define SMC_ECCSR2_MULERR12 SMC_ECCSR2_MULERR(12) -#define SMC_ECCSR2_RECERR13 SMC_ECCSR2_RECERR(13) -#define SMC_ECCSR2_ECCERR13 SMC_ECCSR2_ECCERR(13) -#define SMC_ECCSR2_MULERR13 SMC_ECCSR2_MULERR(13) -#define SMC_ECCSR1_RECERR14 SMC_ECCSR2_RECERR(14) -#define SMC_ECCSR1_ECCERR14 SMC_ECCSR2_ECCERR(14) -#define SMC_ECCSR1_MULERR14 SMC_ECCSR2_MULERR(14) -#define SMC_ECCSR1_RECERR15 SMC_ECCSR2_RECERR(15) -#define SMC_ECCSR1_ECCERR15 SMC_ECCSR2_ECCERR(15) -#define SMC_ECCSR1_MULERR15 SMC_ECCSR2_MULERR(15) - -/* Registers for 1 ECC for a page of 512/1024/2048/4096 bytes */ -/* SMC_ECC_PR0 */ - -#define SMC_ECCPR0_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */ -#define SMC_ECCPR0_BITADDR_MASK (15 << SMC_ECCPR0_BITADDR_SHIFT) -#define SMC_ECCPR0_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */ -#define SMC_ECCPR0_WORDADDR_MASK (0xfff << SMC_ECCPR0_WORDADDR_SHIFT) - -#define SMC_ECCPR1_NPARITY_SHIFT (0) /* Bits 0-15 */ -#define SMC_ECCPR1_NPARITY_MASK (0xffff << SMC_ECCPR1_NPARITY_SHIFT) - -/* Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word */ - -#define SMC_ECCPR512_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */ -#define SMC_ECCPR512_BITADDR_MASK (15 << SMC_ECCPR512_BITADDR_SHIFT) -#define SMC_ECCPR512_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */ -#define SMC_ECCPR512_WORDADDR_MASK (0xfff << SMC_ECCPR512_WORDADDR_SHIFT) -#define SMC_ECCPR512_NPARITY_SHIFT (12) /* Bits 12-23 (or is it 31?) */ -#define SMC_ECCPR512_NPARITY_MASK (0xfff << SMC_ECCPR512_NPARITY_SHIFT) - -/* Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word */ - -#define SMC_ECCPR256_BITADDR_SHIFT (0) /* Bits 0-2: Bit Address */ -#define SMC_ECCPR256_BITADDR_MASK (7 << SMC_ECCPR256_BITADDR_SHIFT) -#define SMC_ECCPR256_WORDADDR_SHIFT (4) /* Bits 4-10: Word Address */ -#define SMC_ECCPR256_WORDADDR_MASK (0x7f << SMC_ECCPR256_WORDADDR_SHIFT) -#define SMC_ECCPR256_NPARITY_SHIFT (12) /* Bits 12-22 */ -#define SMC_ECCPR256_NPARITY_MASK (0x7ff << SMC_ECCPR256_NPARITY_SHIFT) - -/* SMC Setup Register */ - -#define SMCCS_SETUP_NWESETUP_SHIFT (0) /* Bits 0-5: NWE Setup length */ -#define SMCCS_SETUP_NWESETUP_MASK (63 << SMCCS_SETUP_NWESETUP_SHIFT) -#define SMCCS_SETUP_NCSWRSETUP_SHIFT (8) /* Bits 8-13: NCS Setup length in Write access */ -#define SMCCS_SETUP_NCSWRSETUP_MASK (63 << SMCCS_SETUP_NCSWRSETUP_SHIFT) -#define SMCCS_SETUP_NRDSETUP_SHIFT (16) /* Bits 16-21: NRD Setup length */ -#define SMCCS_SETUP_NRDSETUP_MASK (63 << SMCCS_SETUP_NRDSETUP_SHIFT) -#define SMCCS_SETUP_NCSRDSETUP_SHIFT (24) /* Bits 24-29: NCS Setup length in Read access */ -#define SMCCS_SETUP_NCSRDSETUP_MASK (63 << SMCCS_SETUP_NCSRDSETUP_SHIFT) - -/* SMC Pulse Register */ - -#define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-5: NWE Pulse Length */ -#define SMCCS_PULSE_NWEPULSE_MASK (63 << SMCCS_PULSE_NWEPULSE_SHIFT) -#define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-13: NCS Pulse Length in WRITE Access */ -#define SMCCS_PULSE_NCSWRPULSE_MASK (63 << SMCCS_PULSE_NCSWRPULSE_SHIFT) -#define SMCCS_PULSE_RDPULSE_SHIFT (16) /* Bits 16-21: NRD Pulse Length */ -#define SMCCS_PULSE_RDPULSE_MASK (63 << SMCCS_PULSE_RDPULSE_SHIFT) -#define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-29: NCS Pulse Length in READ Access */ -#define SMCCS_PULSE_NCSRDPULSE_MASK (63 << SMCCS_PULSE_NCSRDPULSE_SHIFT) - -/* SMC Cycle Register */ - -#define SMCCS_CYCLE_NWECYCLE_SHIFT (0) /* Bits 0-8: Total Write Cycle Length */ -#define SMCCS_CYCLE_NWECYCLE_MASK (0x1ff << SMCCS_CYCLE_NWECYCLE_SHIFT) -#define SMCCS_CYCLE_NRDCYCLE_SHIFT (16) /* Bits 16-24: Total Read Cycle Length */ -#define SMCCS_CYCLE_NRDCYCLE_MASK (0x1ff << SMCCS_CYCLE_NRDCYCLE_SHIFT) - -/* SMC Timings Register */ - -#define SMCCS_TIMINGS_TCLR_SHIFT (0) /* Bits 0-3: CLE to REN Low Delay */ -#define SMCCS_TIMINGS_TCLR_MASK (15 << SMCCS_TIMINGS_TCLR_SHIFT) -#define SMCCS_TIMINGS_TADL_SHIFT (4) /* Bits 4-7: ALE to Data Start */ -#define SMCCS_TIMINGS_TADL_MASK (15 << SMCCS_TIMINGS_TADL_SHIFT) -#define SMCCS_TIMINGS_TAR_SHIFT (8) /* Bits 8-11: ALE to REN Low Delay */ -#define SMCCS_TIMINGS_TAR_MASK (15 << SMCCS_TIMINGS_TAR_SHIFT) -#define SMCCS_TIMINGS_OCMS (1 << 12) /* Bit 12: Off Chip Memory Scrambling Enable */ -#define SMCCS_TIMINGS_TRR_SHIFT (16) /* Bits 16-19: Ready to REN Low Delay */ -#define SMCCS_TIMINGS_TRR_MASK (15 << SMCCS_TIMINGS_TRR_SHIFT) -#define SMCCS_TIMINGS_TWB_SHIFT (24) /* Bits 24-27: WEN High to REN to Busy */ -#define SMCCS_TIMINGS_TWB_MASK (15 << SMCCS_TIMINGS_TWB_SHIFT) -#define SMCCS_TIMINGS_RBNSEL_SHIFT (28) /* Bits 28-30: Ready/Busy Line Selection */ -#define SMCCS_TIMINGS_RBNSEL_MASK (7 << SMCCS_TIMINGS_RBNSEL_SHIFT) -#define SMCCS_TIMINGS_NFSEL (1 << 31) /* Bit 31: NAND Flash Selection */ - -/* SMC Mode Register */ - -#define SMCCS_MODE_READMODE (1 << 0) /* Bit 0: Read mode */ -#define SMCCS_MODE_WRITEMODE (1 << 1) /* Bit 1: Write mode */ -#define SMCCS_MODE_EXNWMODE_SHIFT (4) /* Bits 4-5: NWAIT Mode */ -#define SMCCS_MODE_EXNWMODE_MASK (3 << SMCCS_MODE_EXNWMODE_SHIFT) -# define SMCCS_EXNWMODE_DISABLED (0 << SMCCS_MODE_EXNWMODE_SHIFT) -# define SMCCS_EXNWMODE_FROZEN (2 << SMCCS_MODE_EXNWMODE_SHIFT) -# define SMCCS_EXNWMODE_READY (3 << SMCCS_MODE_EXNWMODE_SHIFT) -#define SMCCS_MODE_BAT (1 << 8) /* Bit 8: Byte Access Type */ -#define SMCCS_MODE_DBW_SHIFT (12) /* Bits 12-13: Data Bus Width */ -#define SMCCS_MODE_DBW_MASK (3 << SMCCS_MODE_DBW_SHIFT) -# define SMCCS_MODE_DBW_8BITS (0 << 12) /* 8 bits */ -# define SMCCS_MODE_DBW_16BITS (1 << 12) /* 16 bits */ -# define SMCCS_MODE_DBW_32BITS (2 << 12) /* 32 bits */ -#define SMCCS_MODE_TDFCYCLES_SHIFT (16) /* Bits 16-19: Data Float Time */ -#define SMCCS_MODE_TDFCYCLES_MASK (15 << SMCCS_MODE_TDFCYCLES_SHIFT) -#define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization */ -#define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */ -#define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */ -#define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT) -# define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */ -# define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */ -# define SMCCS_MODE_PS_SIZE_16BYTES (2 << SMCCS_MODE_PS_SHIFT) /* 16 bytes */ -# define SMCCS_MODE_PS_SIZE_32BYTES (3 << SMCCS_MODE_PS_SHIFT) /* 32 bytes */ - -/* SMC OCMS Register */ - -#define SMC_OCMS_SMSE (1 << 0) /* Bit 0: Static Memory Controller Scrambling Enable */ -#define SMC_OCMS_SRSE (1 << 1) /* Bit 1: SRAM Scrambling Enable */ - -/* SMC Write Protection Control */ - -#define SMC_WPCR_WPPEN (1 << 9) /* Bit 9: Write Protection Enable */ -#define SMC_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection KEY password */ -#define SMC_WPCR_WPKEY_MASK (0x00ffffff << SMC_WPCR_WPKEY_SHIFT) - -/* SMC Write Protection Status */ - -#define SMC_WPSR_PVS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ -#define SMC_WPSR_PVS_MASK (15 << SMC_WPSR_PVS_SHIFT) -# define SMC_WPSR_PVS_NONE (0 << SMC_WPSR_PVS_SHIFT) /* No Write Protection Violation */ -# define SMC_WPSR_PVS_ RCREG (1 << SMC_WPSR_PVS_SHIFT) /* Attempt to write a control reg */ -# define SMC_WPSR_PVS_RESET (2 << SMC_WPSR_PVS_SHIFT) /* Software reset */ -# define SMC_WPSR_PVS_BOTH (3 << SMC_WPSR_PVS_SHIFT) /* Write + reset */ -#define SMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ -#define SMC_WPSR_WPVSRC_MASK (0xffff << SMC_WPSR_WPVSRC_SHIFT) - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_SMC_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_smc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_SMC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_SMC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* SMC register offsets *****************************************************************/ + +#define SAM3U_SMC_CFG_OFFSET 0x000 /* SMC NFC Configuration Register */ +#define SAM3U_SMC_CTRL_OFFSET 0x004 /* SMC NFC Control Register */ +#define SAM3U_SMC_SR_OFFSET 0x008 /* SMC NFC Status Register */ +#define SAM3U_SMC_IER_OFFSET 0x00c /* SMC NFC Interrupt Enable Register */ +#define SAM3U_SMC_IDR_OFFSET 0x010 /* SMC NFC Interrupt Disable Register */ +#define SAM3U_SMC_IMR_OFFSET 0x014 /* SMC NFC Interrupt Mask Register */ +#define SAM3U_SMC_ADDR_OFFSET 0x018 /* SMC NFC Address Cycle Zero Register */ +#define SAM3U_SMC_BANK_OFFSET 0x01c /* SMC Bank Address Register */ +#define SAM3U_SMC_ECCCTRL_OFFSET 0x020 /* SMC ECC Control Register */ +#define SAM3U_SMC_ECCMD_OFFSET 0x024 /* SMC ECC Mode Register */ +#define SAM3U_SMC_ECCSR1_OFFSET 0x028 /* SMC ECC Status 1 Register */ +#define SAM3U_SMC_ECCPR0_OFFSET 0x02c /* SMC ECC parity 0 Register */ +#define SAM3U_SMC_ECCPR1_OFFSET 0x030 /* SMC ECC parity 1 Register */ +#define SAM3U_SMC_ECCSR2_OFFSET 0x034 /* SMC ECC status 2 Register */ +#define SAM3U_SMC_ECCPR2_OFFSET 0x038 /* SMC ECC parity 2 Register */ +#define SAM3U_SMC_ECCPR3_OFFSET 0x03c /* SMC ECC parity 3 Register */ +#define SAM3U_SMC_ECCPR4_OFFSET 0x040 /* SMC ECC parity 4 Register */ +#define SAM3U_SMC_ECCPR5_OFFSET 0x044 /* SMC ECC parity 5 Register */ +#define SAM3U_SMC_ECCPR6_OFFSET 0x048 /* SMC ECC parity 6 Register */ +#define SAM3U_SMC_ECCPR7_OFFSET 0x04c /* SMC ECC parity 7 Register */ +#define SAM3U_SMC_ECCPR8_OFFSET 0x050 /* SMC ECC parity 8 Register */ +#define SAM3U_SMC_ECCPR9_OFFSET 0x054 /* SMC ECC parity 9 Register */ +#define SAM3U_SMC_ECCPR10_OFFSET 0x058 /* SMC ECC parity 10 Register */ +#define SAM3U_SMC_ECCPR11_OFFSET 0x05c /* SMC ECC parity 11 Register */ +#define SAM3U_SMC_ECCPR12_OFFSET 0x060 /* SMC ECC parity 12 Register */ +#define SAM3U_SMC_ECCPR13_OFFSET 0x064 /* SMC ECC parity 13 Register */ +#define SAM3U_SMC_ECCPR14_OFFSET 0x068 /* SMC ECC parity 14 Register */ +#define SAM3U_SMC_ECCPR15_OFFSET 0x06c /* SMC ECC parity 15 Register */ + +#define SAM3U_SMCCS_OFFSET(n) (0x070+((n)*0x014)) +#define SAM3U_SMCCS_SETUP_OFFSET 0x000 /* SMC SETUP Register */ +#define SAM3U_SMCCS_PULSE_OFFSET 0x004 /* SMC PULSE Register */ +#define SAM3U_SMCCS_CYCLE_OFFSET 0x008 /* SMC CYCLE Register */ +#define SAM3U_SMCCS_TIMINGS_OFFSET 0x00c /* SMC TIMINGS Register */ +#define SAM3U_SMCCS_MODE_OFFSET 0x010 /* SMC MODE Register */ + +#define SAM3U_SMC_OCMS_OFFSET 0x110 /* SMC OCMS MODE Register */ +#define SAM3U_SMC_KEY1_OFFSET 0x114 /* SMC KEY1 Register */ +#define SAM3U_SMC_KEY2_OFFSET 0x118 /* SMC KEY2 Register */ +#define SAM3U_SMC_WPCR_OFFSET 0x1e4 /* Write Protection Control Register */ +#define SAM3U_SMC_WPSR_OFFSET 0x1e8 /* Write Protection Status Register */ + +/* SMC register adresses ****************************************************************/ + +#define SAM3U_SMC_CFG (SAM3U_SMC_BASE+SAM3U_SMC_CFG_OFFSET) +#define SAM3U_SMC_CTRL (SAM3U_SMC_BASE+SAM3U_SMC_CTRL_OFFSET) +#define SAM3U_SMC_SR (SAM3U_SMC_BASE+SAM3U_SMC_SR_OFFSET) +#define SAM3U_SMC_IER (SAM3U_SMC_BASE+SAM3U_SMC_IER_OFFSET) +#define SAM3U_SMC_IDR (SAM3U_SMC_BASE+SAM3U_SMC_IDR_OFFSET) +#define SAM3U_SMC_IMR (SAM3U_SMC_BASE+SAM3U_SMC_IMR_OFFSET) +#define SAM3U_SMC_ADDR (SAM3U_SMC_BASE+SAM3U_SMC_ADDR_OFFSET) +#define SAM3U_SMC_BANK (SAM3U_SMC_BASE+SAM3U_SMC_BANK_OFFSET) +#define SAM3U_SMC_ECCCTRL (SAM3U_SMC_BASE+SAM3U_SMC_ECCCTRL_OFFSET) +#define SAM3U_SMC_ECCMD (SAM3U_SMC_BASE+SAM3U_SMC_ECCMD_OFFSET) +#define SAM3U_SMC_ECCSR1 (SAM3U_SMC_BASE+SAM3U_SMC_ECCSR1_OFFSET) +#define SAM3U_SMC_ECCPR0 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR0_OFFSET) +#define SAM3U_SMC_ECCPR1 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR1_OFFSET) +#define SAM3U_SMC_ECCSR2 (SAM3U_SMC_BASE+SAM3U_SMC_ECCSR2_OFFSET) +#define SAM3U_SMC_ECCPR2 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR2_OFFSET) +#define SAM3U_SMC_ECCPR3 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR3_OFFSET) +#define SAM3U_SMC_ECCPR4 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR4_OFFSET) +#define SAM3U_SMC_ECCPR5 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR5_OFFSET) +#define SAM3U_SMC_ECCPR6 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR6_OFFSET) +#define SAM3U_SMC_ECCPR7 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR7_OFFSET) +#define SAM3U_SMC_ECCPR8 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR8_OFFSET) +#define SAM3U_SMC_ECCPR9 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR9_OFFSET) +#define SAM3U_SMC_ECCPR10 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR10_OFFSET) +#define SAM3U_SMC_ECCPR11 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR11_OFFSET) +#define SAM3U_SMC_ECCPR12 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR12_OFFSET) +#define SAM3U_SMC_ECCPR13 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR13_OFFSET) +#define SAM3U_SMC_ECCPR14 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR14_OFFSET) +#define SAM3U_SMC_ECCPR15 (SAM3U_SMC_BASE+SAM3U_SMC_ECCPR15_OFFSET) + +#define SAM3U_SMCCS_BASE(n) (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(n)) +# define SAM3U_SMC_CS0_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(0)) +# define SAM3U_SMC_CS1_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(1)) +# define SAM3U_SMC_CS2_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(2)) +# define SAM3U_SMC_CS3_BASE (SAM3U_SMC_BASE+SAM3U_SMCCS_OFFSET(3)) +#define SAM3U_SMCCS_SETUP(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_SETUP_OFFSET) +#define SAM3U_SMCCS_PULSE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_PULSE_OFFSET) +#define SAM3U_SMCCS_CYCLE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_CYCLE_OFFSET) +#define SAM3U_SMCCS_TIMINGS(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_TIMINGS_OFFSET) +#define SAM3U_SMCCS_MODE(n) (SAM3U_SMCCS_BASE(n)+SAM3U_SMCCS_MODE_OFFSET) + +#define SAM3U_SMC_OCMS (SAM3U_SMC_BASE+SAM3U_SMC_OCMS_OFFSET) +#define SAM3U_SMC_KEY1 (SAM3U_SMC_BASE+SAM3U_SMC_KEY1_OFFSET) +#define SAM3U_SMC_KEY2 (SAM3U_SMC_BASE+SAM3U_SMC_KEY2_OFFSET) +#define SAM3U_SMC_WPCR (SAM3U_SMC_BASE+SAM3U_SMC_WPCR_OFFSET) +#define SAM3U_SMC_WPSR (SAM3U_SMC_BASE+SAM3U_SMC_WPSR_OFFSET) + +/* SMC register bit definitions *********************************************************/ + +/* SMC NFC Configuration Register */ + +#define SMC_CFG_PAGESIZE_SHIFT (0) /* Bits 0-1: Page size of NAND Flash device */ +#define SMC_CFG_PAGESIZE_MASK (3 << SMC_CFG_PAGESIZE_SHIFT) +# define SMC_CFG_PAGESIZE_16 BYTES (0 << SMC_CFG_PAGESIZE_SHIFT) /* 528 Bytes 16 byte */ +# define SMC_CFG_PAGESIZE_ 2 BYTES (1 << SMC_CFG_PAGESIZE_SHIFT) /* 1056 Bytes 32 bytes */ +# define SMC_CFG_PAGESIZE_64 BYTES (2 << SMC_CFG_PAGESIZE_SHIFT) /* 2112 Bytes 64 bytes */ +# define SMC_CFG_PAGESIZE_128 BYTES (3 << SMC_CFG_PAGESIZE_SHIFT) /* 4224 Bytes 128 bytes */ +#define SMC_CFG_WSPARE (1 << 8) /* Bit 8: Write Spare Area */ +#define SMC_CFG_RSPARE (1 << 9) /* Bit 9: Read Spare Area */ +#define SMC_CFG_EDGECTRL (1 << 12) /* Bit 12: Rising/Falling Edge Detection Control */ +#define SMC_CFG_RBEDGE (1 << 13) /* Bit 13: Ready/Busy Signal Edge Detection */ +#define SMC_CFG_DTOCYC_SHIFT (16) /* Bits 16-19: Data Timeout Cycle Number */ +#define SMC_CFG_DTOCYC_MASK (15 << SMC_CFG_DTOCYC_SHIFT) +#define SMC_CFG_DTOMUL_SHIFT (20) /* Bits 20-22: Data Timeout Multiplier */ +#define SMC_CFG_DTOMUL_MASK (7 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_1 (0 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_16 (1 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_128 (2 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_256 (3 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_1024 (4 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_4096 (5 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_65536 (6 << SMC_CFG_DTOMUL_SHIFT) +# define SMC_CFG_DTOMUL_1048576 (7 << SMC_CFG_DTOMUL_SHIFT) + +/* SMC NFC Control Register */ + +#define SMC_CTRL_NFCEN (1 << 0) /* Bit 0: NAND Flash Controller Enable */ +#define SMC_CTRL_NFCDIS (1 << 1) /* Bit 1: NAND Flash Controller Disable */ + +/* SMC NFC Status Register, SMC NFC Interrupt Enable Register, SMC NFC Interrupt + * Disable Register, and SMC NFC Interrupt Mask Register common bit-field definitions + */ + +#define SMC_SR_SMCSTS (1 << 0) /* Bit 0: NAND Flash Controller status (SR only) */ +#define SMC_INT_RBRISE (1 << 4) /* Bit 4: Ready Busy Rising Edge Detection Interrupt */ +#define SMC_INT_RBFALL (1 << 5) /* Bit 5: Ready Busy Falling Edge Detection Interrupt */ +#define SMC_SR_NFCBUSY (1 << 8) /* Bit 8: NFC Busy (SR only) */ +#define SMC_SR_NFCWR (1 << 11) /* Bit 11: NFC Write/Read Operation (SR only) */ +#define SMC_SR_NFCSID (1 << 12) /* Bit 13: NFC Chip Select ID (SR only) */ +#define SMC_INT_XFRDONE (1 << 16) /* Bit 16: Transfer Done Interrupt */ +#define SMC_INT_CMDDONE (1 << 17) /* Bit 17: Command Done Interrupt */ +#define SMC_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error Interrupt */ +#define SMC_INT_UNDEF (1 << 21) /* Bit 21: Undefined Area Access Interrupt */ +#define SMC_INT_AWB (1 << 22) /* Bit 22: Accessing While Busy Interrupt */ +#define SMC_INT_NFCASE (1 << 23) /* Bit 23: NFC Access Size Error Interrupt */ +#define SMC_INT_RBEDGE(n) (1<<((n)+24)) +#define SMC_INT_RB_EDGE0 (1 << 24) /* Bit 24: Ready/Busy Line 0 Interrupt */ +#define SMC_INT_RB_EDGE1 (1 << 25) /* Bit 25: Ready/Busy Line 1 Interrupt */ +#define SMC_INT_RB_EDGE2 (1 << 26) /* Bit 26: Ready/Busy Line 2 Interrupt */ +#define SMC_INT_RB_EDGE3 (1 << 27) /* Bit 27: Ready/Busy Line 3 Interrupt */ +#define SMC_INT_RB_EDGE4 (1 << 28) /* Bit 28: Ready/Busy Line 4 Interrupt */ +#define SMC_INT_RB_EDGE5 (1 << 29) /* Bit 29: Ready/Busy Line 5 Interrupt */ +#define SMC_INT_RB_EDGE6 (1 << 30) /* Bit 30: Ready/Busy Line 6 Interrupt */ +#define SMC_INT_RB_EDGE7 (1 << 31) /* Bit 31: Ready/Busy Line 7 Interrupt */ + +/* SMC NFC Address Cycle Zero Register */ + +#define SMC_ADDR_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */ +#define SMC_ADDR_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */ + +/* SMC NFC Bank Register */ + +#define SMC_BANK_SHIFT (0) /* Bits 0-2: Bank identifier */ +#define SMC_BANK_MASK (7 << SMC_BANK_SHIFT) + +/* SMC ECC Control Register */ + +#define SMC_ECCCTRL_RST (1 << 0) /* Bit 0: Reset ECC */ +#define SMC_ECCCTRL_SWRST (1 << 1) /* Bit 1: Software Reset */ + +/* SMC ECC MODE Register */ + +#define SMC_ECCMD_ECC_PAGESIZE_SHIFT (0) /* Bits 0-1 */ +#define SMC_ECCMD_ECC_PAGESIZE_MASK (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_528 (0 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_1056 (1 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_2112 (2 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +# define SMC_ECCMD_ECC_PAGESIZE_4224 (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) +#define SMC_ECCMD_TYPCORREC_SHIFT (4) /* Bits 4-5: type of correction */ +#define SMC_ECCMD_TYPCORREC_MASK (3 << SMC_ECCMD_TYPCORREC_SHIFT) +# define SMC_ECCMD_TYPCORREC_PAGE (0 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for a page */ +# define SMC_ECCMD_TYPCORREC_256 (1 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 256 bytes */ +# define SMC_ECCMD_TYPCORREC_512 (2 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 512 bytes */ + +/* SMC ECC Status Register 1 */ + +#define _RECERR (0) /* Recoverable Error */ +#define _ECCERR (1) /* ECC Error */ +#define _MULERR (2) /* Multiple Error */ + +#define SMC_ECCSR1_RECERR(n) (1 << (((n)<<4)+_RECERR)) +#define SMC_ECCSR1_ECCERR(n) (1 << (((n)<<4)+_ECCERR)) +#define SMC_ECCSR1_MULERR(n) (1 << (((n)<<4)+_MULERR)) + +#define SMC_ECCSR1_RECERR0 SMC_ECCSR1_RECERR(0) +#define SMC_ECCSR1_ECCERR0 SMC_ECCSR1_ECCERR(0) +#define SMC_ECCSR1_MULERR0 SMC_ECCSR1_MULERR(0) +#define SMC_ECCSR1_RECERR1 SMC_ECCSR1_RECERR(1) +#define SMC_ECCSR1_ECCERR1 SMC_ECCSR1_ECCERR(1) +#define SMC_ECCSR1_MULERR1 SMC_ECCSR1_MULERR(1) +#define SMC_ECCSR1_RECERR2 SMC_ECCSR1_RECERR(2) +#define SMC_ECCSR1_ECCERR2 SMC_ECCSR1_ECCERR(2) +#define SMC_ECCSR1_MULERR2 SMC_ECCSR1_MULERR(2) +#define SMC_ECCSR1_RECERR3 SMC_ECCSR1_RECERR(3) +#define SMC_ECCSR1_ECCERR3 SMC_ECCSR1_ECCERR(3) +#define SMC_ECCSR1_MULERR3 SMC_ECCSR1_MULERR(3) +#define SMC_ECCSR1_RECERR4 SMC_ECCSR1_RECERR(4) +#define SMC_ECCSR1_ECCERR4 SMC_ECCSR1_ECCERR(4) +#define SMC_ECCSR1_MULERR4 SMC_ECCSR1_MULERR(4) +#define SMC_ECCSR1_RECERR5 SMC_ECCSR1_RECERR(5) +#define SMC_ECCSR1_ECCERR5 SMC_ECCSR1_ECCERR(5) +#define SMC_ECCSR1_MULERR5 SMC_ECCSR1_MULERR(5) +#define SMC_ECCSR1_RECERR6 SMC_ECCSR1_RECERR(6) +#define SMC_ECCSR1_ECCERR6 SMC_ECCSR1_ECCERR(6) +#define SMC_ECCSR1_MULERR6 SMC_ECCSR1_MULERR(6) +#define SMC_ECCSR1_RECERR7 SMC_ECCSR1_RECERR(7) +#define SMC_ECCSR1_ECCERR7 SMC_ECCSR1_ECCERR(7) +#define SMC_ECCSR1_MULERR7 SMC_ECCSR1_MULERR(7) + +/* SMC ECC Status Register 2 */ + +#define SMC_ECCSR2_RECERR(n) (1 << ((((n)-8)<<4)+_RECERR)) +#define SMC_ECCSR2_ECCERR(n) (1 << ((((n)-8)<<4)+_ECCERR)) +#define SMC_ECCSR2_MULERR(n) (1 << ((((n)-8)<<4)+_MULERR)) + +#define SMC_ECCSR2_RECERR8 SMC_ECCSR2_RECERR(8) +#define SMC_ECCSR2_ECCERR8 SMC_ECCSR2_ECCERR(8) +#define SMC_ECCSR2_MULERR8 SMC_ECCSR2_MULERR(8) +#define SMC_ECCSR2_RECERR9 SMC_ECCSR2_RECERR(9) +#define SMC_ECCSR2_ECCERR9 SMC_ECCSR2_ECCERR(9) +#define SMC_ECCSR2_MULERR9 SMC_ECCSR2_MULERR(9) +#define SMC_ECCSR2_RECERR10 SMC_ECCSR2_RECERR(10) +#define SMC_ECCSR2_ECCERR10 SMC_ECCSR2_ECCERR(10) +#define SMC_ECCSR2_MULERR10 SMC_ECCSR2_MULERR(10) +#define SMC_ECCSR2_RECERR11 SMC_ECCSR2_RECERR(11) +#define SMC_ECCSR2_ECCERR11 SMC_ECCSR2_ECCERR(11) +#define SMC_ECCSR2_MULERR11 SMC_ECCSR2_MULERR(11) +#define SMC_ECCSR2_RECERR12 SMC_ECCSR2_RECERR(12) +#define SMC_ECCSR2_ECCERR12 SMC_ECCSR2_ECCERR(12) +#define SMC_ECCSR2_MULERR12 SMC_ECCSR2_MULERR(12) +#define SMC_ECCSR2_RECERR13 SMC_ECCSR2_RECERR(13) +#define SMC_ECCSR2_ECCERR13 SMC_ECCSR2_ECCERR(13) +#define SMC_ECCSR2_MULERR13 SMC_ECCSR2_MULERR(13) +#define SMC_ECCSR1_RECERR14 SMC_ECCSR2_RECERR(14) +#define SMC_ECCSR1_ECCERR14 SMC_ECCSR2_ECCERR(14) +#define SMC_ECCSR1_MULERR14 SMC_ECCSR2_MULERR(14) +#define SMC_ECCSR1_RECERR15 SMC_ECCSR2_RECERR(15) +#define SMC_ECCSR1_ECCERR15 SMC_ECCSR2_ECCERR(15) +#define SMC_ECCSR1_MULERR15 SMC_ECCSR2_MULERR(15) + +/* Registers for 1 ECC for a page of 512/1024/2048/4096 bytes */ +/* SMC_ECC_PR0 */ + +#define SMC_ECCPR0_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */ +#define SMC_ECCPR0_BITADDR_MASK (15 << SMC_ECCPR0_BITADDR_SHIFT) +#define SMC_ECCPR0_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */ +#define SMC_ECCPR0_WORDADDR_MASK (0xfff << SMC_ECCPR0_WORDADDR_SHIFT) + +#define SMC_ECCPR1_NPARITY_SHIFT (0) /* Bits 0-15 */ +#define SMC_ECCPR1_NPARITY_MASK (0xffff << SMC_ECCPR1_NPARITY_SHIFT) + +/* Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word */ + +#define SMC_ECCPR512_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */ +#define SMC_ECCPR512_BITADDR_MASK (15 << SMC_ECCPR512_BITADDR_SHIFT) +#define SMC_ECCPR512_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */ +#define SMC_ECCPR512_WORDADDR_MASK (0xfff << SMC_ECCPR512_WORDADDR_SHIFT) +#define SMC_ECCPR512_NPARITY_SHIFT (12) /* Bits 12-23 (or is it 31?) */ +#define SMC_ECCPR512_NPARITY_MASK (0xfff << SMC_ECCPR512_NPARITY_SHIFT) + +/* Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word */ + +#define SMC_ECCPR256_BITADDR_SHIFT (0) /* Bits 0-2: Bit Address */ +#define SMC_ECCPR256_BITADDR_MASK (7 << SMC_ECCPR256_BITADDR_SHIFT) +#define SMC_ECCPR256_WORDADDR_SHIFT (4) /* Bits 4-10: Word Address */ +#define SMC_ECCPR256_WORDADDR_MASK (0x7f << SMC_ECCPR256_WORDADDR_SHIFT) +#define SMC_ECCPR256_NPARITY_SHIFT (12) /* Bits 12-22 */ +#define SMC_ECCPR256_NPARITY_MASK (0x7ff << SMC_ECCPR256_NPARITY_SHIFT) + +/* SMC Setup Register */ + +#define SMCCS_SETUP_NWESETUP_SHIFT (0) /* Bits 0-5: NWE Setup length */ +#define SMCCS_SETUP_NWESETUP_MASK (63 << SMCCS_SETUP_NWESETUP_SHIFT) +#define SMCCS_SETUP_NCSWRSETUP_SHIFT (8) /* Bits 8-13: NCS Setup length in Write access */ +#define SMCCS_SETUP_NCSWRSETUP_MASK (63 << SMCCS_SETUP_NCSWRSETUP_SHIFT) +#define SMCCS_SETUP_NRDSETUP_SHIFT (16) /* Bits 16-21: NRD Setup length */ +#define SMCCS_SETUP_NRDSETUP_MASK (63 << SMCCS_SETUP_NRDSETUP_SHIFT) +#define SMCCS_SETUP_NCSRDSETUP_SHIFT (24) /* Bits 24-29: NCS Setup length in Read access */ +#define SMCCS_SETUP_NCSRDSETUP_MASK (63 << SMCCS_SETUP_NCSRDSETUP_SHIFT) + +/* SMC Pulse Register */ + +#define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-5: NWE Pulse Length */ +#define SMCCS_PULSE_NWEPULSE_MASK (63 << SMCCS_PULSE_NWEPULSE_SHIFT) +#define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-13: NCS Pulse Length in WRITE Access */ +#define SMCCS_PULSE_NCSWRPULSE_MASK (63 << SMCCS_PULSE_NCSWRPULSE_SHIFT) +#define SMCCS_PULSE_RDPULSE_SHIFT (16) /* Bits 16-21: NRD Pulse Length */ +#define SMCCS_PULSE_RDPULSE_MASK (63 << SMCCS_PULSE_RDPULSE_SHIFT) +#define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-29: NCS Pulse Length in READ Access */ +#define SMCCS_PULSE_NCSRDPULSE_MASK (63 << SMCCS_PULSE_NCSRDPULSE_SHIFT) + +/* SMC Cycle Register */ + +#define SMCCS_CYCLE_NWECYCLE_SHIFT (0) /* Bits 0-8: Total Write Cycle Length */ +#define SMCCS_CYCLE_NWECYCLE_MASK (0x1ff << SMCCS_CYCLE_NWECYCLE_SHIFT) +#define SMCCS_CYCLE_NRDCYCLE_SHIFT (16) /* Bits 16-24: Total Read Cycle Length */ +#define SMCCS_CYCLE_NRDCYCLE_MASK (0x1ff << SMCCS_CYCLE_NRDCYCLE_SHIFT) + +/* SMC Timings Register */ + +#define SMCCS_TIMINGS_TCLR_SHIFT (0) /* Bits 0-3: CLE to REN Low Delay */ +#define SMCCS_TIMINGS_TCLR_MASK (15 << SMCCS_TIMINGS_TCLR_SHIFT) +#define SMCCS_TIMINGS_TADL_SHIFT (4) /* Bits 4-7: ALE to Data Start */ +#define SMCCS_TIMINGS_TADL_MASK (15 << SMCCS_TIMINGS_TADL_SHIFT) +#define SMCCS_TIMINGS_TAR_SHIFT (8) /* Bits 8-11: ALE to REN Low Delay */ +#define SMCCS_TIMINGS_TAR_MASK (15 << SMCCS_TIMINGS_TAR_SHIFT) +#define SMCCS_TIMINGS_OCMS (1 << 12) /* Bit 12: Off Chip Memory Scrambling Enable */ +#define SMCCS_TIMINGS_TRR_SHIFT (16) /* Bits 16-19: Ready to REN Low Delay */ +#define SMCCS_TIMINGS_TRR_MASK (15 << SMCCS_TIMINGS_TRR_SHIFT) +#define SMCCS_TIMINGS_TWB_SHIFT (24) /* Bits 24-27: WEN High to REN to Busy */ +#define SMCCS_TIMINGS_TWB_MASK (15 << SMCCS_TIMINGS_TWB_SHIFT) +#define SMCCS_TIMINGS_RBNSEL_SHIFT (28) /* Bits 28-30: Ready/Busy Line Selection */ +#define SMCCS_TIMINGS_RBNSEL_MASK (7 << SMCCS_TIMINGS_RBNSEL_SHIFT) +#define SMCCS_TIMINGS_NFSEL (1 << 31) /* Bit 31: NAND Flash Selection */ + +/* SMC Mode Register */ + +#define SMCCS_MODE_READMODE (1 << 0) /* Bit 0: Read mode */ +#define SMCCS_MODE_WRITEMODE (1 << 1) /* Bit 1: Write mode */ +#define SMCCS_MODE_EXNWMODE_SHIFT (4) /* Bits 4-5: NWAIT Mode */ +#define SMCCS_MODE_EXNWMODE_MASK (3 << SMCCS_MODE_EXNWMODE_SHIFT) +# define SMCCS_EXNWMODE_DISABLED (0 << SMCCS_MODE_EXNWMODE_SHIFT) +# define SMCCS_EXNWMODE_FROZEN (2 << SMCCS_MODE_EXNWMODE_SHIFT) +# define SMCCS_EXNWMODE_READY (3 << SMCCS_MODE_EXNWMODE_SHIFT) +#define SMCCS_MODE_BAT (1 << 8) /* Bit 8: Byte Access Type */ +#define SMCCS_MODE_DBW_SHIFT (12) /* Bits 12-13: Data Bus Width */ +#define SMCCS_MODE_DBW_MASK (3 << SMCCS_MODE_DBW_SHIFT) +# define SMCCS_MODE_DBW_8BITS (0 << 12) /* 8 bits */ +# define SMCCS_MODE_DBW_16BITS (1 << 12) /* 16 bits */ +# define SMCCS_MODE_DBW_32BITS (2 << 12) /* 32 bits */ +#define SMCCS_MODE_TDFCYCLES_SHIFT (16) /* Bits 16-19: Data Float Time */ +#define SMCCS_MODE_TDFCYCLES_MASK (15 << SMCCS_MODE_TDFCYCLES_SHIFT) +#define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization */ +#define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */ +#define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */ +#define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT) +# define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */ +# define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */ +# define SMCCS_MODE_PS_SIZE_16BYTES (2 << SMCCS_MODE_PS_SHIFT) /* 16 bytes */ +# define SMCCS_MODE_PS_SIZE_32BYTES (3 << SMCCS_MODE_PS_SHIFT) /* 32 bytes */ + +/* SMC OCMS Register */ + +#define SMC_OCMS_SMSE (1 << 0) /* Bit 0: Static Memory Controller Scrambling Enable */ +#define SMC_OCMS_SRSE (1 << 1) /* Bit 1: SRAM Scrambling Enable */ + +/* SMC Write Protection Control */ + +#define SMC_WPCR_WPPEN (1 << 9) /* Bit 9: Write Protection Enable */ +#define SMC_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection KEY password */ +#define SMC_WPCR_WPKEY_MASK (0x00ffffff << SMC_WPCR_WPKEY_SHIFT) + +/* SMC Write Protection Status */ + +#define SMC_WPSR_PVS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */ +#define SMC_WPSR_PVS_MASK (15 << SMC_WPSR_PVS_SHIFT) +# define SMC_WPSR_PVS_NONE (0 << SMC_WPSR_PVS_SHIFT) /* No Write Protection Violation */ +# define SMC_WPSR_PVS_ RCREG (1 << SMC_WPSR_PVS_SHIFT) /* Attempt to write a control reg */ +# define SMC_WPSR_PVS_RESET (2 << SMC_WPSR_PVS_SHIFT) /* Software reset */ +# define SMC_WPSR_PVS_BOTH (3 << SMC_WPSR_PVS_SHIFT) /* Write + reset */ +#define SMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */ +#define SMC_WPSR_WPVSRC_MASK (0xffff << SMC_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_SMC_H */ diff --git a/arch/arm/src/sam3u/sam3u_ssc.h b/arch/arm/src/sam3u/sam3u_ssc.h index d4f848c1389156efb38535c0409e19161653a986..5a5df824b14e5f47e7936936e87b476248911e4c 100644 --- a/arch/arm/src/sam3u/sam3u_ssc.h +++ b/arch/arm/src/sam3u/sam3u_ssc.h @@ -1,292 +1,292 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_ssc.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_SSC_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_SSC_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* SSC register offsets *****************************************************************/ - -#define SAM3U_SSC_CR_OFFSET 0x000 /* Control Register */ -#define SAM3U_SSC_CMR_OFFSET 0x004 /* Clock Mode Register */ - /* 0x008: Reserved */ - /* 0x00c: Reserved */ -#define SAM3U_SSC_RCMR_OFFSET 0x010 /* Receive Clock Mode Register */ -#define SAM3U_SSC_RFMR_OFFSET 0x014 /* Receive Frame Mode Register */ -#define SAM3U_SSC_TCMR_OFFSET 0x018 /* Transmit Clock Mode Register */ -#define SAM3U_SSC_TFMR_OFFSET 0x01c /* Transmit Frame Mode Register */ -#define SAM3U_SSC_RHR_OFFSET 0x020 /* Receive Holding Register */ -#define SAM3U_SSC_THR_OFFSET 0x024 /* Transmit Holding Register */ - /* 0x028: Reserved */ - /* 0x02c: Reserved */ -#define SAM3U_SSC_RSHR_OFFSET 0x030 /* Receive Sync. Holding Register */ -#define SAM3U_SSC_TSHR_OFFSET 0x034 /* Transmit Sync. Holding Register */ -#define SAM3U_SSC_RC0R_OFFSET 0x038 /* Receive Compare 0 Register */ -#define SAM3U_SSC_RC1R_OFFSET 0x03c /* Receive Compare 1 Register */ -#define SAM3U_SSC_SR_OFFSET 0x040 /* Status Register */ -#define SAM3U_SSC_IER_OFFSET 0x044 /* Interrupt Enable Register */ -#define SAM3U_SSC_IDR_OFFSET 0x048 /* Interrupt Disable Register */ -#define SAM3U_SSC_IMR_OFFSET 0x04c /* Interrupt Mask Register */ -#define SAM3U_SSC_WPMR_OFFSET 0x0e4 /* Write Protect Mode Register */ -#define SAM3U_SSC_WPSR_OFFSET 0x0e8 /* Write Protect Status Register */ - /* 0x050-0x0fc: Reserved */ - /* 0x100-0x124: Reserved */ - -/* SSC register adresses ****************************************************************/ - -#define SAM3U_SSC_CR (SAM3U_SSC_BASE+SAM3U_SSC_CR_OFFSET) -#define SAM3U_SSC_CMR (SAM3U_SSC_BASE+SAM3U_SSC_CMR_OFFSET) -#define SAM3U_SSC_RCMR (SAM3U_SSC_BASE+SAM3U_SSC_RCMR_OFFSET) -#define SAM3U_SSC_RFMR (SAM3U_SSC_BASE+SAM3U_SSC_RFMR_OFFSET) -#define SAM3U_SSC_TCMR (SAM3U_SSC_BASE+SAM3U_SSC_TCMR_OFFSET) -#define SAM3U_SSC_TFMR (SAM3U_SSC_BASE+SAM3U_SSC_TFMR_OFFSET) -#define SAM3U_SSC_RHR (SAM3U_SSC_BASE+SAM3U_SSC_RHR_OFFSET) -#define SAM3U_SSC_THR (SAM3U_SSC_BASE+SAM3U_SSC_THR_OFFSET) -#define SAM3U_SSC_RSHR (SAM3U_SSC_BASE+SAM3U_SSC_RSHR_OFFSET) -#define SAM3U_SSC_TSHR (SAM3U_SSC_BASE+SAM3U_SSC_TSHR_OFFSET) -#define SAM3U_SSC_RC0R (SAM3U_SSC_BASE+SAM3U_SSC_RC0R_OFFSET) -#define SAM3U_SSC_RC1R (SAM3U_SSC_BASE+SAM3U_SSC_RC1R_OFFSET) -#define SAM3U_SSC_SR (SAM3U_SSC_BASE+SAM3U_SSC_SR_OFFSET) -#define SAM3U_SSC_IER (SAM3U_SSC_BASE+SAM3U_SSC_IER_OFFSET) -#define SAM3U_SSC_IDR (SAM3U_SSC_BASE+SAM3U_SSC_IDR_OFFSET) -#define SAM3U_SSC_IMR (SAM3U_SSC_BASE+SAM3U_SSC_IMR_OFFSET) -#define SAM3U_SSC_WPMR (SAM3U_SSC_BASE+SAM3U_SSC_WPMR_OFFSET) -#define SAM3U_SSC_WPSR (SAM3U_SSC_BASE+SAM3U_SSC_WPSR_OFFSET) - -/* SSC register bit definitions *********************************************************/ - -/* SSC Control Register */ - -#define SSC_CR_RXEN (1 << 0) /* Bit 0: Receive Enable */ -#define SSC_CR_RXDIS (1 << 1) /* Bit 1: Receive Disable */ -#define SSC_CR_TXEN (1 << 8) /* Bit 8: Transmit Enable */ -#define SSC_CR_TXDIS (1 << 9) /* Bit 9: Transmit Disable */ -#define SSC_CR_SWRST (1 << 15) /* Bit 15: Software Reset */ - -/* SSC Clock Mode Register */ - -#define SSC_CMR_DIV_SHIFT (0) /* Bits 0-11: Clock Divider */ -#define SSC_CMR_DIV_MASK (0xfff << SSC_CMR_DIV_SHIFT) - -/* SSC Receive Clock Mode Register */ - -#define SSC_RCMR_CKS_SHIFT (0) /* Bits 0-1: Receive Clock Selection */ -#define SSC_RCMR_CKS_MASK (3 << SSC_RCMR_CKS_SHIFT) -# define SSC_RCMR_CKS_DIVIDED (0 << SSC_RCMR_CKS_SHIFT) /* Divided Clock */ -# define SSC_RCMR_CKS_TK (1 << SSC_RCMR_CKS_SHIFT) /* TK Clock signal */ -# define SSC_RCMR_CKS_RK (2 << SSC_RCMR_CKS_SHIFT) /* RK pin */ -#define SSC_RCMR_CKO_SHIFT (2) /* Bits 2-4: Receive Clock Output Mode Selection */ -#define SSC_RCMR_CKO_MASK (7 << SSC_RCMR_CKO_SHIFT) -# define SSC_RCMR_CKO_ NONE (0 << SSC_RCMR_CKO_SHIFT) /* None */ -# define SSC_RCMR_CKO_CONTINUOUS (1 << SSC_RCMR_CKO_SHIFT) /* Continuous Receive Clock */ -# define SSC_RCMR_CKO_XFERS (2 << SSC_RCMR_CKO_SHIFT) /* Receive Clock only during data transfers */ -#define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */ -#define SSC_RCMR_CKG_SHIFT (6) /* Bits 6-7: Receive Clock Gating Selection */ -#define SSC_RCMR_CKG_MASK (3 << SSC_RCMR_CKG_SHIFT) -# define SSC_RCMR_CKG_NONE (0 << SSC_RCMR_CKG_SHIFT) /* None, continuous clock */ -# define SSC_RCMR_CKG_RFLOW (1 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF Low */ -# define SSC_RCMR_CKG_RFHIGH (2 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF High */ -#define SSC_RCMR_START_SHIFT (8) /* Bits 8-11: Receive Start Selection */ -#define SSC_RCMR_START_MASK (15 << SSC_RCMR_START_SHIFT) -# define SSC_RCMR_START_CONTINOUS (0 << SSC_RCMR_START_SHIFT) /* Continuous */ -# define SSC_RCMR_START_START (1 << SSC_RCMR_START_SHIFT) /* Transmit start */ -# define SSC_RCMR_START_RFLOW (2 << SSC_RCMR_START_SHIFT) /* Low level on RF signal */ -# define SSC_RCMR_START_RFHIGH (3 << SSC_RCMR_START_SHIFT) /* High level on RF signal */ -# define SSC_RCMR_START_RFFALL (4 << SSC_RCMR_START_SHIFT) /* Falling edge on RF signal */ -# define SSC_RCMR_START_RFRISE (5 << SSC_RCMR_START_SHIFT) /* Rising edge on RF signal */ -# define SSC_RCMR_START_ANYLEVEL (6 << SSC_RCMR_START_SHIFT) /* Any level change on RF signal */ -# define SSC_RCMR_START_ANYEDGE (7 << SSC_RCMR_START_SHIFT) /* Any edge on RF signal */ -# define SSC_RCMR_START_CMP0 (8 << SSC_RCMR_START_SHIFT) /* Compare 0 */ -#define SSC_RCMR_STOP (1 << 12) /* Bit 12: Receive Stop Select */ -#define SSC_RCMR_STTDLY_SHIFT (15) /* Bits 16-23: Receive Start Delay */ -#define SSC_RCMR_STTDLY_MASK (0xff << SSC_RCMR_STTDLY_SHIFT) -#define SSC_RCMR_PERIOD_SHIFT (24) /* Bits 24-31: Receive Period Divider Selection */ -#define SSC_RCMR_PERIOD_MASK (0xff << SSC_RCMR_PERIOD_SHIFT) - - -/* SSC Receive Frame Mode Register */ - -#define SSC_RFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */ -#define SSC_RFMR_DATLEN_MASK (31 << SSC_RFMR_DATLEN_SHIFT) -#define SSC_RFMR_LOOP (1 << 5) /* Bit 5: Loop Mode */ -#define SSC_RFMR_MSBF (1 << 7) /* Bit 7: Most Significant Bit First */ -#define SSC_RFMR_DATNB_SHIFT (8) /* Bits 8-11: Data Number per Frame */ -#define SSC_RFMR_DATNB_MASK (15 << SSC_RFMR_DATNB_SHIFT) -#define SSC_RFMR_FSLEN_SHIFT (16) /* Bits 16-19: Receive Frame Sync Length */ -#define SSC_RFMR_FSLEN_MASK (15 << SSC_RFMR_FSLEN_SHIFT) -#define SSC_RFMR_FSOS_SHIFT (20) /* Bits 20-22: Receive Frame Sync Output Selection */ -#define SSC_RFMR_FSOS_MASK (7 << SSC_RFMR_FSOS_SHIFT) -# define SSC_RFMR_FSOS_NONE (0 << SSC_RFMR_FSOS_SHIFT) /* None */ -# define SSC_RFMR_FSOS_NEG (1 << SSC_RFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */ -# define SSC_RFMR_FSOS_POW (2 << SSC_RFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */ -# define SSC_RFMR_FSOS_LOW (3 << SSC_RFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */ -# define SSC_RFMR_FSOS_HIGH (4 << SSC_RFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */ -# define SSC_RFMR_FSOS_TOGGLE (5 << SSC_RFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */ -#define SSC_RFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detect */ -#define SSC_RFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */ -#define SSC_RFMR_FSLENEXT_MASK (15 << SSC_RFMR_FSLENEXT_SHIFT) - -/* SSC Transmit Clock Mode Register */ - -#define SSC_TCMR_CKS_SHIFT (0) /* Bits 0-1: Transmit Clock Selection */ -#define SSC_TCMR_CKS_MASK (3 << SSC_TCMR_CKS_SHIFT) -# define SSC_TCMR_CKS_DIVIDED (0 << SSC_TCMR_CKS_SHIFT) /* Divided Clock */ -# define SSC_TCMR_CKS_TK (1 << SSC_TCMR_CKS_SHIFT) /* TK Clock signal */ -# define SSC_TCMR_CKS_RK (2 << SSC_TCMR_CKS_SHIFT) /* RK pin */ -#define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */ -#define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT) -# define SSC_TCMR_CKO_ NONE (0 << SSC_TCMR_CKO_SHIFT) /* None */ -# define SSC_TCMR_CKO_CONTINUOUS (1 << SSC_TCMR_CKO_SHIFT) /* Continuous Transmit Clock */ -# define SSC_TCMR_CKO_XFERS (2 << SSC_TCMR_CKO_SHIFT) /* Transmit Clock only during data transfers */ -#define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */ -#define SSC_TCMR_CKG_SHIFT (6) /* Bits 6-7: Transmit Clock Gating Selection */ -#define SSC_TCMR_CKG_MASK (3 << SSC_TCMR_CKG_SHIFT) -# define SSC_TCMR_CKG_NONE (0 << SSC_TCMR_CKG_SHIFT) /* None, continuous clock */ -# define SSC_tCMR_CKG_TFLOW (1 << SSC_TCMR_CKG_SHIFT) /* Receive Clock enabled only if TF Low */ -# define SSC_TCMR_CKG_TFHIGH (2 << SSC_TCMR_CKG_SHIFT) /* Receive Clock enabled only if TF High */ -#define SSC_TCMR_START_SHIFT (8) /* Bits 8-11: Transmit Start Selection */ -#define SSC_TCMR_START_MASK (15 << SSC_TCMR_START_SHIFT) -# define SSC_TCMR_START_CONTINOUS (0 << SSC_TCMR_START_SHIFT) /* Continuous */ -# define SSC_TCMR_START_START (1 << SSC_TCMR_START_SHIFT) /* Receive start */ -# define SSC_TCMR_START_TFLOW (2 << SSC_TCMR_START_SHIFT) /* Low level on TF signal */ -# define SSC_TCMR_START_TFHIGH (3 << SSC_TCMR_START_SHIFT) /* High level on TF signal */ -# define SSC_TCMR_START_TFFALL (4 << SSC_TCMR_START_SHIFT) /* Falling edge on TF signal */ -# define SSC_TCMR_START_TFRISE (5 << SSC_TCMR_START_SHIFT) /* Rising edge on TF signal */ -# define SSC_TCMR_START_ANYLEVEL (6 << SSC_TCMR_START_SHIFT) /* Any level change on TF signal */ -# define SSC_TCMR_START_ANYEDGE (7 << SSC_TCMR_START_SHIFT) /* Any edge on TF signal */ -#define SSC_TCMR_STTDLY_SHIFT (16) /* Bits 16-23: Transmit Start Delay */ -#define SSC_TCMR_STTDLY_MASK (0xff << SSC_TCMR_STTDLY_SHIFT) -#define SSC_TCMR_PERIOD_SHIFT (24) /* Bits 24-31: Transmit Period Divider Selection */ -#define SSC_TCMR_PERIOD_MASK (0xff << SSC_TCMR_PERIOD_SHIFT) - -/* SSC Transmit Frame Mode Register */ - -#define SSC_TFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */ -#define SSC_TFMR_DATLEN_MASK (31 << SSC_TFMR_DATLEN_SHIFT) -#define SSC_TFMR_DATDEF (1 << 5) /* Bit 5: Data Default Value */ -#define SSC_TFMR_MSBF (1 << 7) /* Bit 7: Most Significant Bit First */ -#define SSC_TFMR_DATNB_SHIFT (8) /* Bits 8-11: Data Number per frame */ -#define SSC_TFMR_DATNB_MASK (15 << SSC_TFMR_DATNB_SHIFT) -#define SSC_TFMR_FSLEN_SHIFT (16) /* Bits 16-19: Transmit Frame Syn Length */ -#define SSC_TFMR_FSLEN_MASK (15 << SSC_TFMR_FSLEN_SHIFT) -#define SSC_TFMR_FSOS_SHIFT (20) /* Bits 20-22: Transmit Frame Sync Output Selection */ -#define SSC_TFMR_FSOS_MASK (7 << SSC_TFMR_FSOS_SHIFT) -# define SSC_TFMR_FSOS_NONE (0 << SSC_TFMR_FSOS_SHIFT) /* None */ -# define SSC_TFMR_FSOS_NEG (1 << SSC_TFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */ -# define SSC_TFMR_FSOS_POW (2 << SSC_TFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */ -# define SSC_TFMR_FSOS_LOW (3 << SSC_TFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */ -# define SSC_TFMR_FSOS_HIGH (4 << SSC_TFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */ -# define SSC_TFMR_FSOS_TOGGLE (5 << SSC_TFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */ -#define SSC_TFMR_FSDEN (1 << 23) /* Bit 23: Frame Sync Data Enable */ -#define SSC_TFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detection */ -#define SSC_TFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */ -#define SSC_TFMR_FSLENEXT_MASK (15 << SSC_TFMR_FSLENEXT_SHIFT) - -/* SSC Receive Synchronization Holding Register */ - -#define SSC_RSHR_RSDAT_SHIFT (0) /* Bits 0-15: Receive Synchronization Data */ -#define SSC_RSHR_RSDAT_MASK (0xffff << SSC_RSHR_RSDAT_SHIFT) - -/* SSC Transmit Synchronization Holding Register */ - -#define SSC_TSHR_TSDAT_SHIFT (0) /* Bits 0-15: Transmit Synchronization Data */ -#define SSC_TSHR_TSDAT_MASK (0xffff << SSC_TSHR_TSDAT_SHIFT) - -/* SSC Receive Compare 0 Register */ - -#define SSC_RC0R_CP0_SHIFT (0) /* Bits 0-15: Receive Compare Data 0 */ -#define SSC_RC0R_CP0_MASK (0xffff << SSC_RC0R_CP0_SHIFT) - -/* SSC Receive Compare 1 Register */ - -#define SSC_RC1R_CP1_SHIFT (0) /* Bits 0-15: Receive Compare Data 1 */ -#define SSC_RC1R_CP1_MASK (0xffff << SSC_RC1R_CP1_SHIFT) - -/* SSC Status Register, SSC Interrupt Enable Register, SSC Interrupt Disable - * Register, and SSC Interrupt Mask Register commin bit-field definitions - */ - -#define SSC_INT_TXRDY (1 << 0) /* Bit 0: Transmit Ready */ -#define SSC_INT_TXEMPTY (1 << 1) /* Bit 1: Transmit Empty */ -#define SSC_INT_ENDTX (1 << 2) /* Bit 2: End of Transmission */ -#define SSC_INT_TXBUFE (1 << 3) /* Bit 3: Transmit Buffer Empty */ -#define SSC_INT_RXRDY (1 << 4) /* Bit 4: Receive Ready */ -#define SSC_INT_OVRUN (1 << 5) /* Bit 5: Receive Overrun */ -#define SSC_INT_ENDRX (1 << 6) /* Bit 6: End of Reception */ -#define SSC_INT_RXBUFF (1 << 7) /* Bit 7: Receive Buffer Full */ -#define SSC_INT_CP0 (1 << 8) /* Bit 8: Compare 0 */ -#define SSC_INT_CP1 (1 << 9) /* Bit 9: Compare 1 */ -#define SSC_INT_TXSYN (1 << 10) /* Bit 10: Transmit Sync */ -#define SSC_INT_RXSYN (1 << 11) /* Bit 11: Receive Sync */ -#define SSC_SR_TXEN (1 << 16) /* Bit 16: Transmit Enable (SR only) */ -#define SSC_SR_RXEN (1 << 17) /* Bit 17: Receive Enable (SR only) */ - -/* SSC Write Protect Mode Register */ - -#define SSC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ -#define SSC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ -#define SSC_WPMR_WPKEY_MASK (0x00ffffff << SSC_WPMR_WPKEY_SHIFT) - -/* SSC Write Protect Status Register */ - -#define SSC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ -#define SSC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ -#define SSC_WPSR_WPVSRC_MASK (0xffff << SSC_WPSR_WPVSRC_SHIFT) - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_SSC_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_ssc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_SSC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_SSC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* SSC register offsets *****************************************************************/ + +#define SAM3U_SSC_CR_OFFSET 0x000 /* Control Register */ +#define SAM3U_SSC_CMR_OFFSET 0x004 /* Clock Mode Register */ + /* 0x008: Reserved */ + /* 0x00c: Reserved */ +#define SAM3U_SSC_RCMR_OFFSET 0x010 /* Receive Clock Mode Register */ +#define SAM3U_SSC_RFMR_OFFSET 0x014 /* Receive Frame Mode Register */ +#define SAM3U_SSC_TCMR_OFFSET 0x018 /* Transmit Clock Mode Register */ +#define SAM3U_SSC_TFMR_OFFSET 0x01c /* Transmit Frame Mode Register */ +#define SAM3U_SSC_RHR_OFFSET 0x020 /* Receive Holding Register */ +#define SAM3U_SSC_THR_OFFSET 0x024 /* Transmit Holding Register */ + /* 0x028: Reserved */ + /* 0x02c: Reserved */ +#define SAM3U_SSC_RSHR_OFFSET 0x030 /* Receive Sync. Holding Register */ +#define SAM3U_SSC_TSHR_OFFSET 0x034 /* Transmit Sync. Holding Register */ +#define SAM3U_SSC_RC0R_OFFSET 0x038 /* Receive Compare 0 Register */ +#define SAM3U_SSC_RC1R_OFFSET 0x03c /* Receive Compare 1 Register */ +#define SAM3U_SSC_SR_OFFSET 0x040 /* Status Register */ +#define SAM3U_SSC_IER_OFFSET 0x044 /* Interrupt Enable Register */ +#define SAM3U_SSC_IDR_OFFSET 0x048 /* Interrupt Disable Register */ +#define SAM3U_SSC_IMR_OFFSET 0x04c /* Interrupt Mask Register */ +#define SAM3U_SSC_WPMR_OFFSET 0x0e4 /* Write Protect Mode Register */ +#define SAM3U_SSC_WPSR_OFFSET 0x0e8 /* Write Protect Status Register */ + /* 0x050-0x0fc: Reserved */ + /* 0x100-0x124: Reserved */ + +/* SSC register adresses ****************************************************************/ + +#define SAM3U_SSC_CR (SAM3U_SSC_BASE+SAM3U_SSC_CR_OFFSET) +#define SAM3U_SSC_CMR (SAM3U_SSC_BASE+SAM3U_SSC_CMR_OFFSET) +#define SAM3U_SSC_RCMR (SAM3U_SSC_BASE+SAM3U_SSC_RCMR_OFFSET) +#define SAM3U_SSC_RFMR (SAM3U_SSC_BASE+SAM3U_SSC_RFMR_OFFSET) +#define SAM3U_SSC_TCMR (SAM3U_SSC_BASE+SAM3U_SSC_TCMR_OFFSET) +#define SAM3U_SSC_TFMR (SAM3U_SSC_BASE+SAM3U_SSC_TFMR_OFFSET) +#define SAM3U_SSC_RHR (SAM3U_SSC_BASE+SAM3U_SSC_RHR_OFFSET) +#define SAM3U_SSC_THR (SAM3U_SSC_BASE+SAM3U_SSC_THR_OFFSET) +#define SAM3U_SSC_RSHR (SAM3U_SSC_BASE+SAM3U_SSC_RSHR_OFFSET) +#define SAM3U_SSC_TSHR (SAM3U_SSC_BASE+SAM3U_SSC_TSHR_OFFSET) +#define SAM3U_SSC_RC0R (SAM3U_SSC_BASE+SAM3U_SSC_RC0R_OFFSET) +#define SAM3U_SSC_RC1R (SAM3U_SSC_BASE+SAM3U_SSC_RC1R_OFFSET) +#define SAM3U_SSC_SR (SAM3U_SSC_BASE+SAM3U_SSC_SR_OFFSET) +#define SAM3U_SSC_IER (SAM3U_SSC_BASE+SAM3U_SSC_IER_OFFSET) +#define SAM3U_SSC_IDR (SAM3U_SSC_BASE+SAM3U_SSC_IDR_OFFSET) +#define SAM3U_SSC_IMR (SAM3U_SSC_BASE+SAM3U_SSC_IMR_OFFSET) +#define SAM3U_SSC_WPMR (SAM3U_SSC_BASE+SAM3U_SSC_WPMR_OFFSET) +#define SAM3U_SSC_WPSR (SAM3U_SSC_BASE+SAM3U_SSC_WPSR_OFFSET) + +/* SSC register bit definitions *********************************************************/ + +/* SSC Control Register */ + +#define SSC_CR_RXEN (1 << 0) /* Bit 0: Receive Enable */ +#define SSC_CR_RXDIS (1 << 1) /* Bit 1: Receive Disable */ +#define SSC_CR_TXEN (1 << 8) /* Bit 8: Transmit Enable */ +#define SSC_CR_TXDIS (1 << 9) /* Bit 9: Transmit Disable */ +#define SSC_CR_SWRST (1 << 15) /* Bit 15: Software Reset */ + +/* SSC Clock Mode Register */ + +#define SSC_CMR_DIV_SHIFT (0) /* Bits 0-11: Clock Divider */ +#define SSC_CMR_DIV_MASK (0xfff << SSC_CMR_DIV_SHIFT) + +/* SSC Receive Clock Mode Register */ + +#define SSC_RCMR_CKS_SHIFT (0) /* Bits 0-1: Receive Clock Selection */ +#define SSC_RCMR_CKS_MASK (3 << SSC_RCMR_CKS_SHIFT) +# define SSC_RCMR_CKS_DIVIDED (0 << SSC_RCMR_CKS_SHIFT) /* Divided Clock */ +# define SSC_RCMR_CKS_TK (1 << SSC_RCMR_CKS_SHIFT) /* TK Clock signal */ +# define SSC_RCMR_CKS_RK (2 << SSC_RCMR_CKS_SHIFT) /* RK pin */ +#define SSC_RCMR_CKO_SHIFT (2) /* Bits 2-4: Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKO_MASK (7 << SSC_RCMR_CKO_SHIFT) +# define SSC_RCMR_CKO_ NONE (0 << SSC_RCMR_CKO_SHIFT) /* None */ +# define SSC_RCMR_CKO_CONTINUOUS (1 << SSC_RCMR_CKO_SHIFT) /* Continuous Receive Clock */ +# define SSC_RCMR_CKO_XFERS (2 << SSC_RCMR_CKO_SHIFT) /* Receive Clock only during data transfers */ +#define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */ +#define SSC_RCMR_CKG_SHIFT (6) /* Bits 6-7: Receive Clock Gating Selection */ +#define SSC_RCMR_CKG_MASK (3 << SSC_RCMR_CKG_SHIFT) +# define SSC_RCMR_CKG_NONE (0 << SSC_RCMR_CKG_SHIFT) /* None, continuous clock */ +# define SSC_RCMR_CKG_RFLOW (1 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF Low */ +# define SSC_RCMR_CKG_RFHIGH (2 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF High */ +#define SSC_RCMR_START_SHIFT (8) /* Bits 8-11: Receive Start Selection */ +#define SSC_RCMR_START_MASK (15 << SSC_RCMR_START_SHIFT) +# define SSC_RCMR_START_CONTINOUS (0 << SSC_RCMR_START_SHIFT) /* Continuous */ +# define SSC_RCMR_START_START (1 << SSC_RCMR_START_SHIFT) /* Transmit start */ +# define SSC_RCMR_START_RFLOW (2 << SSC_RCMR_START_SHIFT) /* Low level on RF signal */ +# define SSC_RCMR_START_RFHIGH (3 << SSC_RCMR_START_SHIFT) /* High level on RF signal */ +# define SSC_RCMR_START_RFFALL (4 << SSC_RCMR_START_SHIFT) /* Falling edge on RF signal */ +# define SSC_RCMR_START_RFRISE (5 << SSC_RCMR_START_SHIFT) /* Rising edge on RF signal */ +# define SSC_RCMR_START_ANYLEVEL (6 << SSC_RCMR_START_SHIFT) /* Any level change on RF signal */ +# define SSC_RCMR_START_ANYEDGE (7 << SSC_RCMR_START_SHIFT) /* Any edge on RF signal */ +# define SSC_RCMR_START_CMP0 (8 << SSC_RCMR_START_SHIFT) /* Compare 0 */ +#define SSC_RCMR_STOP (1 << 12) /* Bit 12: Receive Stop Select */ +#define SSC_RCMR_STTDLY_SHIFT (15) /* Bits 16-23: Receive Start Delay */ +#define SSC_RCMR_STTDLY_MASK (0xff << SSC_RCMR_STTDLY_SHIFT) +#define SSC_RCMR_PERIOD_SHIFT (24) /* Bits 24-31: Receive Period Divider Selection */ +#define SSC_RCMR_PERIOD_MASK (0xff << SSC_RCMR_PERIOD_SHIFT) + + +/* SSC Receive Frame Mode Register */ + +#define SSC_RFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */ +#define SSC_RFMR_DATLEN_MASK (31 << SSC_RFMR_DATLEN_SHIFT) +#define SSC_RFMR_LOOP (1 << 5) /* Bit 5: Loop Mode */ +#define SSC_RFMR_MSBF (1 << 7) /* Bit 7: Most Significant Bit First */ +#define SSC_RFMR_DATNB_SHIFT (8) /* Bits 8-11: Data Number per Frame */ +#define SSC_RFMR_DATNB_MASK (15 << SSC_RFMR_DATNB_SHIFT) +#define SSC_RFMR_FSLEN_SHIFT (16) /* Bits 16-19: Receive Frame Sync Length */ +#define SSC_RFMR_FSLEN_MASK (15 << SSC_RFMR_FSLEN_SHIFT) +#define SSC_RFMR_FSOS_SHIFT (20) /* Bits 20-22: Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSOS_MASK (7 << SSC_RFMR_FSOS_SHIFT) +# define SSC_RFMR_FSOS_NONE (0 << SSC_RFMR_FSOS_SHIFT) /* None */ +# define SSC_RFMR_FSOS_NEG (1 << SSC_RFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */ +# define SSC_RFMR_FSOS_POW (2 << SSC_RFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */ +# define SSC_RFMR_FSOS_LOW (3 << SSC_RFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */ +# define SSC_RFMR_FSOS_HIGH (4 << SSC_RFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */ +# define SSC_RFMR_FSOS_TOGGLE (5 << SSC_RFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */ +#define SSC_RFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detect */ +#define SSC_RFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */ +#define SSC_RFMR_FSLENEXT_MASK (15 << SSC_RFMR_FSLENEXT_SHIFT) + +/* SSC Transmit Clock Mode Register */ + +#define SSC_TCMR_CKS_SHIFT (0) /* Bits 0-1: Transmit Clock Selection */ +#define SSC_TCMR_CKS_MASK (3 << SSC_TCMR_CKS_SHIFT) +# define SSC_TCMR_CKS_DIVIDED (0 << SSC_TCMR_CKS_SHIFT) /* Divided Clock */ +# define SSC_TCMR_CKS_TK (1 << SSC_TCMR_CKS_SHIFT) /* TK Clock signal */ +# define SSC_TCMR_CKS_RK (2 << SSC_TCMR_CKS_SHIFT) /* RK pin */ +#define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT) +# define SSC_TCMR_CKO_ NONE (0 << SSC_TCMR_CKO_SHIFT) /* None */ +# define SSC_TCMR_CKO_CONTINUOUS (1 << SSC_TCMR_CKO_SHIFT) /* Continuous Transmit Clock */ +# define SSC_TCMR_CKO_XFERS (2 << SSC_TCMR_CKO_SHIFT) /* Transmit Clock only during data transfers */ +#define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */ +#define SSC_TCMR_CKG_SHIFT (6) /* Bits 6-7: Transmit Clock Gating Selection */ +#define SSC_TCMR_CKG_MASK (3 << SSC_TCMR_CKG_SHIFT) +# define SSC_TCMR_CKG_NONE (0 << SSC_TCMR_CKG_SHIFT) /* None, continuous clock */ +# define SSC_tCMR_CKG_TFLOW (1 << SSC_TCMR_CKG_SHIFT) /* Receive Clock enabled only if TF Low */ +# define SSC_TCMR_CKG_TFHIGH (2 << SSC_TCMR_CKG_SHIFT) /* Receive Clock enabled only if TF High */ +#define SSC_TCMR_START_SHIFT (8) /* Bits 8-11: Transmit Start Selection */ +#define SSC_TCMR_START_MASK (15 << SSC_TCMR_START_SHIFT) +# define SSC_TCMR_START_CONTINOUS (0 << SSC_TCMR_START_SHIFT) /* Continuous */ +# define SSC_TCMR_START_START (1 << SSC_TCMR_START_SHIFT) /* Receive start */ +# define SSC_TCMR_START_TFLOW (2 << SSC_TCMR_START_SHIFT) /* Low level on TF signal */ +# define SSC_TCMR_START_TFHIGH (3 << SSC_TCMR_START_SHIFT) /* High level on TF signal */ +# define SSC_TCMR_START_TFFALL (4 << SSC_TCMR_START_SHIFT) /* Falling edge on TF signal */ +# define SSC_TCMR_START_TFRISE (5 << SSC_TCMR_START_SHIFT) /* Rising edge on TF signal */ +# define SSC_TCMR_START_ANYLEVEL (6 << SSC_TCMR_START_SHIFT) /* Any level change on TF signal */ +# define SSC_TCMR_START_ANYEDGE (7 << SSC_TCMR_START_SHIFT) /* Any edge on TF signal */ +#define SSC_TCMR_STTDLY_SHIFT (16) /* Bits 16-23: Transmit Start Delay */ +#define SSC_TCMR_STTDLY_MASK (0xff << SSC_TCMR_STTDLY_SHIFT) +#define SSC_TCMR_PERIOD_SHIFT (24) /* Bits 24-31: Transmit Period Divider Selection */ +#define SSC_TCMR_PERIOD_MASK (0xff << SSC_TCMR_PERIOD_SHIFT) + +/* SSC Transmit Frame Mode Register */ + +#define SSC_TFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */ +#define SSC_TFMR_DATLEN_MASK (31 << SSC_TFMR_DATLEN_SHIFT) +#define SSC_TFMR_DATDEF (1 << 5) /* Bit 5: Data Default Value */ +#define SSC_TFMR_MSBF (1 << 7) /* Bit 7: Most Significant Bit First */ +#define SSC_TFMR_DATNB_SHIFT (8) /* Bits 8-11: Data Number per frame */ +#define SSC_TFMR_DATNB_MASK (15 << SSC_TFMR_DATNB_SHIFT) +#define SSC_TFMR_FSLEN_SHIFT (16) /* Bits 16-19: Transmit Frame Syn Length */ +#define SSC_TFMR_FSLEN_MASK (15 << SSC_TFMR_FSLEN_SHIFT) +#define SSC_TFMR_FSOS_SHIFT (20) /* Bits 20-22: Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSOS_MASK (7 << SSC_TFMR_FSOS_SHIFT) +# define SSC_TFMR_FSOS_NONE (0 << SSC_TFMR_FSOS_SHIFT) /* None */ +# define SSC_TFMR_FSOS_NEG (1 << SSC_TFMR_FSOS_SHIFT) /* 0x1 Negative Pulse */ +# define SSC_TFMR_FSOS_POW (2 << SSC_TFMR_FSOS_SHIFT) /* 0x2 Positive Pulse */ +# define SSC_TFMR_FSOS_LOW (3 << SSC_TFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */ +# define SSC_TFMR_FSOS_HIGH (4 << SSC_TFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */ +# define SSC_TFMR_FSOS_TOGGLE (5 << SSC_TFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */ +#define SSC_TFMR_FSDEN (1 << 23) /* Bit 23: Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detection */ +#define SSC_TFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */ +#define SSC_TFMR_FSLENEXT_MASK (15 << SSC_TFMR_FSLENEXT_SHIFT) + +/* SSC Receive Synchronization Holding Register */ + +#define SSC_RSHR_RSDAT_SHIFT (0) /* Bits 0-15: Receive Synchronization Data */ +#define SSC_RSHR_RSDAT_MASK (0xffff << SSC_RSHR_RSDAT_SHIFT) + +/* SSC Transmit Synchronization Holding Register */ + +#define SSC_TSHR_TSDAT_SHIFT (0) /* Bits 0-15: Transmit Synchronization Data */ +#define SSC_TSHR_TSDAT_MASK (0xffff << SSC_TSHR_TSDAT_SHIFT) + +/* SSC Receive Compare 0 Register */ + +#define SSC_RC0R_CP0_SHIFT (0) /* Bits 0-15: Receive Compare Data 0 */ +#define SSC_RC0R_CP0_MASK (0xffff << SSC_RC0R_CP0_SHIFT) + +/* SSC Receive Compare 1 Register */ + +#define SSC_RC1R_CP1_SHIFT (0) /* Bits 0-15: Receive Compare Data 1 */ +#define SSC_RC1R_CP1_MASK (0xffff << SSC_RC1R_CP1_SHIFT) + +/* SSC Status Register, SSC Interrupt Enable Register, SSC Interrupt Disable + * Register, and SSC Interrupt Mask Register commin bit-field definitions + */ + +#define SSC_INT_TXRDY (1 << 0) /* Bit 0: Transmit Ready */ +#define SSC_INT_TXEMPTY (1 << 1) /* Bit 1: Transmit Empty */ +#define SSC_INT_ENDTX (1 << 2) /* Bit 2: End of Transmission */ +#define SSC_INT_TXBUFE (1 << 3) /* Bit 3: Transmit Buffer Empty */ +#define SSC_INT_RXRDY (1 << 4) /* Bit 4: Receive Ready */ +#define SSC_INT_OVRUN (1 << 5) /* Bit 5: Receive Overrun */ +#define SSC_INT_ENDRX (1 << 6) /* Bit 6: End of Reception */ +#define SSC_INT_RXBUFF (1 << 7) /* Bit 7: Receive Buffer Full */ +#define SSC_INT_CP0 (1 << 8) /* Bit 8: Compare 0 */ +#define SSC_INT_CP1 (1 << 9) /* Bit 9: Compare 1 */ +#define SSC_INT_TXSYN (1 << 10) /* Bit 10: Transmit Sync */ +#define SSC_INT_RXSYN (1 << 11) /* Bit 11: Receive Sync */ +#define SSC_SR_TXEN (1 << 16) /* Bit 16: Transmit Enable (SR only) */ +#define SSC_SR_RXEN (1 << 17) /* Bit 17: Receive Enable (SR only) */ + +/* SSC Write Protect Mode Register */ + +#define SSC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define SSC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define SSC_WPMR_WPKEY_MASK (0x00ffffff << SSC_WPMR_WPKEY_SHIFT) + +/* SSC Write Protect Status Register */ + +#define SSC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +#define SSC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define SSC_WPSR_WPVSRC_MASK (0xffff << SSC_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_SSC_H */ diff --git a/arch/arm/src/sam3u/sam3u_supc.h b/arch/arm/src/sam3u/sam3u_supc.h index 8cde5389e7cfd6d10f27c7c9800cb0942610743b..5bd28de5040e2a724e5e62908654e2408d6d4d2d 100644 --- a/arch/arm/src/sam3u/sam3u_supc.h +++ b/arch/arm/src/sam3u/sam3u_supc.h @@ -1,164 +1,164 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_supc.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_SUPC_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_SUPC_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* SUPC register offsets ****************************************************************/ - -#define SAM3U_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */ -#define SAM3U_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */ -#define SAM3U_SUPC_MR_OFFSET 0x08 /* Supply Controller Mode Register */ -#define SAM3U_SUPC_WUMR_OFFSET 0x0c /* Supply Controller Wake Up Mode Register */ -#define SAM3U_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */ -#define SAM3U_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */ - -/* SUPC register adresses ***************************************************************/ - -#define SAM3U_SUPC_CR (SAM3U_SUPC_BASE+SAM3U_SUPC_CR_OFFSET) -#define SAM3U_SUPC_SMMR (SAM3U_SUPC_BASE+SAM3U_SUPC_SMMR_OFFSET) -#define SAM3U_SUPC_MR (SAM3U_SUPC_BASE+SAM3U_SUPC_MR_OFFSET) -#define SAM3U_SUPC_WUMR (SAM3U_SUPC_BASE+SAM3U_SUPC_WUMR_OFFSET) -#define SAM3U_SUPC_WUIR (SAM3U_SUPC_BASE+SAM3U_SUPC_WUIR_OFFSET) -#define SAM3U_SUPC_SR (SAM3U_SUPC_BASE+SAM3U_SUPC_SR_OFFSET) - -/* SUPC register bit definitions ********************************************************/ - -#define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */ -#define SUPC_CR_XTALSEL (1 << 3) /* Bit 3: Crystal Oscillator Select */ -#define SUPC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ -#define SUPC_CR_KEY_MASK (0xff << SUPC_CR_KEY_SHIFT) - -#define SUPC_SMMR_SMTH_SHIFT (0) /* Bits 0-3: Supply Monitor Threshold */ -#define SUPC_SMMR_SMTH_MASK (15 << SUPC_SMMR_SMTH_SHIFT) -# define SUPC_SMMR_SMTH_1p9V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.9V */ -# define SUPC_SMMR_SMTH_2p0V (1 << SUPC_SMMR_SMTH_SHIFT) /* 2.0V */ -# define SUPC_SMMR_SMTH_2p1V (2 << SUPC_SMMR_SMTH_SHIFT) /* 2.1V */ -# define SUPC_SMMR_SMTH_2p2V (3 << SUPC_SMMR_SMTH_SHIFT) /* 2.2V */ -# define SUPC_SMMR_SMTH_2p3V (4 << SUPC_SMMR_SMTH_SHIFT) /* 2.3V */ -# define SUPC_SMMR_SMTH_2p4V (5 << SUPC_SMMR_SMTH_SHIFT) /* 2.4V */ -# define SUPC_SMMR_SMTH_2p5V (6 << SUPC_SMMR_SMTH_SHIFT) /* 2.5V */ -# define SUPC_SMMR_SMTH_2p6V (7 << SUPC_SMMR_SMTH_SHIFT) /* 2.6V */ -# define SUPC_SMMR_SMTH_2p7V (8 << SUPC_SMMR_SMTH_SHIFT) /* 2.7V */ -# define SUPC_SMMR_SMTH_2p8V (9 << SUPC_SMMR_SMTH_SHIFT) /* 2.8V */ -# define SUPC_SMMR_SMTH_2p9V (10 << SUPC_SMMR_SMTH_SHIFT) /* 2.9V */ -# define SUPC_SMMR_SMTH_3p0V (11 << SUPC_SMMR_SMTH_SHIFT) /* 3.0V */ -# define SUPC_SMMR_SMTH_3p1V (12 << SUPC_SMMR_SMTH_SHIFT) /* 3.1V */ -# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.2V */ -# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.3V */ -# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.4V */ -#define SUPC_SMMR_SMSMPL_SHIFT (8) /* Bits 8-10: Supply Monitor Sampling Period */ -#define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT) -# define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */ -# define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor */ -# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */ -# define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */ -# define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */ -#define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */ -#define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */ - -#define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */ -#define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */ -#define SUPC_MR_VDDIORDY (1 << 14) /* Bit 14: VDDIO Ready */ -#define SUPC_MR_OSCBYPASS (1 << 20) /* Bit 20: Oscillator Bypass */ -#define SUPC_MR_KEY_SHIFT (24) /* Bits 24-31: Password Key */ -#define SUPC_MR_KEY_MASK (0xff << SUPC_MR_KEY_SHIFT) - -#define SUPC_WUMR_FWUPEN (1 << 0) /* Bit 0: Force Wake Up Enable */ -#define SUPC_WUMR_SMEN (1 << 1) /* Bit 1: Supply Monitor Wake Up Enable */ -#define SUPC_WUMR_RTTEN (1 << 2) /* Bit 2: Real Time Timer Wake Up Enable */ -#define SUPC_WUMR_RTCEN (1 << 3) /* Bit 3: Real Time Clock Wake Up Enable */ -#define SUPC_WUMR_FWUPDBC_SHIFT (8) /* Bits 8-10: Force Wake Up Debouncer */ -#define SUPC_WUMR_FWUPDBC_MASK (7 << SUPC_WUMR_FWUPDBC_SHIFT) - #define SUPC_WUMR_FWUPDBC_1SCLK (0 << SUPC_WUMR_FWUPDBC_SHIFT) /* Immediate, no debouncing */ - #define SUPC_WUMR_FWUPDBC_3SCLK (1 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 3 SLCK periods */ - #define SUPC_WUMR_FWUPDBC_32SCLK (2 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32 SLCK periods */ - #define SUPC_WUMR_FWUPDBC_512SCLK (3 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 512 SLCK periods */ - #define SUPC_WUMR_FWUPDBC_4096SCLK (4 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 4096 SLCK periods */ - #define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */ -#define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT) -# define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */ -# define SUPC_WUMR_WKUPDBC_3SCLK (1 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 3 SLCK periods */ -# define SUPC_WUMR_WKUPDBC_32SCLK (2 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32 SLCK periods */ -# define SUPC_WUMR_WKUPDBC_512SCLK (3 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 512 SLCK periods */ -# define SUPC_WUMR_WKUPDBC_4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */ -# define SUPC_WUMR_WKUPDBC_32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */ - -#define SUPC_WUIR_WKUPEN_SHIFT (0) /* Bits 0-15: Wake Up Input Enable 0 to 15 */ -#define SUPC_WUIR_WKUPEN_MASK (0xffff << SUPC_WUIR_WKUPEN_SHIFT) -#define SUPC_WUIR_WKUPEN(n) ((1 << (n)) << SUPC_WUIR_WKUPEN_SHIFT) -#define SUPC_WUIR_WKUPT_SHIFT (16) /* Bits 16-31 Wake Up Input Transition 0 to 15 */ -#define SUPC_WUIR_WKUPT_MASK (0xffff << SUPC_WUIR_WKUPT_SHIFT) -#define SUPC_WUIR_WKUPT(n) ((1 << (n)) << SUPC_WUIR_WKUPT_SHIFT) - -#define SUPC_SR_FWUPS (1 << 0) /* Bit 0: FWUP Wake Up Status */ -#define SUPC_SR_WKUPS (1 << 1) /* Bit 1: WKUP Wake Up Status */ -#define SUPC_SR_SMWS (1 << 2) /* Bit 2: Supply Monitor Detection Wake Up Status */ -#define SUPC_SR_BODRSTS (1 << 3) /* Bit 3: Brownout Detector Reset Status */ -#define SUPC_SR_SMRSTS (1 << 4) /* Bit 4: Supply Monitor Reset Status */ -#define SUPC_SR_SMS (1 << 5) /* Bit 5: Supply Monitor Status */ -#define SUPC_SR_SMOS (1 << 6) /* Bit 6: Supply Monitor Output Status */ -#define SUPC_SR_OSCSEL (1 << 7) /* Bit 7: 32-kHz Oscillator Selection Status */ -#define SUPC_SR_FWUPIS (1 << 12) /* Bit 12: FWUP Input Status */ -#define SUPC_SR_WKUPIS_SHIFT (16) /* Bits 16-31: WKUP Input Status 0 to 15 */ -#define SUPC_SR_WKUPIS_MASK (0xffff << SUPC_SR_WKUPIS_SHIFT) - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_SUPC_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_supc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_SUPC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_SUPC_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* SUPC register offsets ****************************************************************/ + +#define SAM3U_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */ +#define SAM3U_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */ +#define SAM3U_SUPC_MR_OFFSET 0x08 /* Supply Controller Mode Register */ +#define SAM3U_SUPC_WUMR_OFFSET 0x0c /* Supply Controller Wake Up Mode Register */ +#define SAM3U_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */ +#define SAM3U_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */ + +/* SUPC register adresses ***************************************************************/ + +#define SAM3U_SUPC_CR (SAM3U_SUPC_BASE+SAM3U_SUPC_CR_OFFSET) +#define SAM3U_SUPC_SMMR (SAM3U_SUPC_BASE+SAM3U_SUPC_SMMR_OFFSET) +#define SAM3U_SUPC_MR (SAM3U_SUPC_BASE+SAM3U_SUPC_MR_OFFSET) +#define SAM3U_SUPC_WUMR (SAM3U_SUPC_BASE+SAM3U_SUPC_WUMR_OFFSET) +#define SAM3U_SUPC_WUIR (SAM3U_SUPC_BASE+SAM3U_SUPC_WUIR_OFFSET) +#define SAM3U_SUPC_SR (SAM3U_SUPC_BASE+SAM3U_SUPC_SR_OFFSET) + +/* SUPC register bit definitions ********************************************************/ + +#define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */ +#define SUPC_CR_XTALSEL (1 << 3) /* Bit 3: Crystal Oscillator Select */ +#define SUPC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ +#define SUPC_CR_KEY_MASK (0xff << SUPC_CR_KEY_SHIFT) + +#define SUPC_SMMR_SMTH_SHIFT (0) /* Bits 0-3: Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH_MASK (15 << SUPC_SMMR_SMTH_SHIFT) +# define SUPC_SMMR_SMTH_1p9V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.9V */ +# define SUPC_SMMR_SMTH_2p0V (1 << SUPC_SMMR_SMTH_SHIFT) /* 2.0V */ +# define SUPC_SMMR_SMTH_2p1V (2 << SUPC_SMMR_SMTH_SHIFT) /* 2.1V */ +# define SUPC_SMMR_SMTH_2p2V (3 << SUPC_SMMR_SMTH_SHIFT) /* 2.2V */ +# define SUPC_SMMR_SMTH_2p3V (4 << SUPC_SMMR_SMTH_SHIFT) /* 2.3V */ +# define SUPC_SMMR_SMTH_2p4V (5 << SUPC_SMMR_SMTH_SHIFT) /* 2.4V */ +# define SUPC_SMMR_SMTH_2p5V (6 << SUPC_SMMR_SMTH_SHIFT) /* 2.5V */ +# define SUPC_SMMR_SMTH_2p6V (7 << SUPC_SMMR_SMTH_SHIFT) /* 2.6V */ +# define SUPC_SMMR_SMTH_2p7V (8 << SUPC_SMMR_SMTH_SHIFT) /* 2.7V */ +# define SUPC_SMMR_SMTH_2p8V (9 << SUPC_SMMR_SMTH_SHIFT) /* 2.8V */ +# define SUPC_SMMR_SMTH_2p9V (10 << SUPC_SMMR_SMTH_SHIFT) /* 2.9V */ +# define SUPC_SMMR_SMTH_3p0V (11 << SUPC_SMMR_SMTH_SHIFT) /* 3.0V */ +# define SUPC_SMMR_SMTH_3p1V (12 << SUPC_SMMR_SMTH_SHIFT) /* 3.1V */ +# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.2V */ +# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.3V */ +# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.4V */ +#define SUPC_SMMR_SMSMPL_SHIFT (8) /* Bits 8-10: Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT) +# define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */ +# define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor */ +# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */ +# define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */ +# define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */ + +#define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */ +#define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */ +#define SUPC_MR_VDDIORDY (1 << 14) /* Bit 14: VDDIO Ready */ +#define SUPC_MR_OSCBYPASS (1 << 20) /* Bit 20: Oscillator Bypass */ +#define SUPC_MR_KEY_SHIFT (24) /* Bits 24-31: Password Key */ +#define SUPC_MR_KEY_MASK (0xff << SUPC_MR_KEY_SHIFT) + +#define SUPC_WUMR_FWUPEN (1 << 0) /* Bit 0: Force Wake Up Enable */ +#define SUPC_WUMR_SMEN (1 << 1) /* Bit 1: Supply Monitor Wake Up Enable */ +#define SUPC_WUMR_RTTEN (1 << 2) /* Bit 2: Real Time Timer Wake Up Enable */ +#define SUPC_WUMR_RTCEN (1 << 3) /* Bit 3: Real Time Clock Wake Up Enable */ +#define SUPC_WUMR_FWUPDBC_SHIFT (8) /* Bits 8-10: Force Wake Up Debouncer */ +#define SUPC_WUMR_FWUPDBC_MASK (7 << SUPC_WUMR_FWUPDBC_SHIFT) + #define SUPC_WUMR_FWUPDBC_1SCLK (0 << SUPC_WUMR_FWUPDBC_SHIFT) /* Immediate, no debouncing */ + #define SUPC_WUMR_FWUPDBC_3SCLK (1 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 3 SLCK periods */ + #define SUPC_WUMR_FWUPDBC_32SCLK (2 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32 SLCK periods */ + #define SUPC_WUMR_FWUPDBC_512SCLK (3 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 512 SLCK periods */ + #define SUPC_WUMR_FWUPDBC_4096SCLK (4 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 4096 SLCK periods */ + #define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */ +#define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT) +# define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */ +# define SUPC_WUMR_WKUPDBC_3SCLK (1 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 3 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_32SCLK (2 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_512SCLK (3 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 512 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */ +# define SUPC_WUMR_WKUPDBC_32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */ + +#define SUPC_WUIR_WKUPEN_SHIFT (0) /* Bits 0-15: Wake Up Input Enable 0 to 15 */ +#define SUPC_WUIR_WKUPEN_MASK (0xffff << SUPC_WUIR_WKUPEN_SHIFT) +#define SUPC_WUIR_WKUPEN(n) ((1 << (n)) << SUPC_WUIR_WKUPEN_SHIFT) +#define SUPC_WUIR_WKUPT_SHIFT (16) /* Bits 16-31 Wake Up Input Transition 0 to 15 */ +#define SUPC_WUIR_WKUPT_MASK (0xffff << SUPC_WUIR_WKUPT_SHIFT) +#define SUPC_WUIR_WKUPT(n) ((1 << (n)) << SUPC_WUIR_WKUPT_SHIFT) + +#define SUPC_SR_FWUPS (1 << 0) /* Bit 0: FWUP Wake Up Status */ +#define SUPC_SR_WKUPS (1 << 1) /* Bit 1: WKUP Wake Up Status */ +#define SUPC_SR_SMWS (1 << 2) /* Bit 2: Supply Monitor Detection Wake Up Status */ +#define SUPC_SR_BODRSTS (1 << 3) /* Bit 3: Brownout Detector Reset Status */ +#define SUPC_SR_SMRSTS (1 << 4) /* Bit 4: Supply Monitor Reset Status */ +#define SUPC_SR_SMS (1 << 5) /* Bit 5: Supply Monitor Status */ +#define SUPC_SR_SMOS (1 << 6) /* Bit 6: Supply Monitor Output Status */ +#define SUPC_SR_OSCSEL (1 << 7) /* Bit 7: 32-kHz Oscillator Selection Status */ +#define SUPC_SR_FWUPIS (1 << 12) /* Bit 12: FWUP Input Status */ +#define SUPC_SR_WKUPIS_SHIFT (16) /* Bits 16-31: WKUP Input Status 0 to 15 */ +#define SUPC_SR_WKUPIS_MASK (0xffff << SUPC_SR_WKUPIS_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_SUPC_H */ diff --git a/arch/arm/src/sam3u/sam3u_tc.h b/arch/arm/src/sam3u/sam3u_tc.h index 1c330d38b6793fbb77e19f0b7fc88afad7e75303..0fb36da97ed115f9bf6156f3cc887a079b81ed55 100644 --- a/arch/arm/src/sam3u/sam3u_tc.h +++ b/arch/arm/src/sam3u/sam3u_tc.h @@ -1,347 +1,347 @@ -/************************************************************************************************ - * arch/arm/src/sam3u/sam3u_tc.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_TC_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_TC_H - -/************************************************************************************************ - * Included Files - ************************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/************************************************************************************************ - * Pre-processor Definitions - ************************************************************************************************/ - -/* TC register offsets **************************************************************************/ - -/* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */ - -#define SAM3U_TCN_OFFSET(n) (0x00 + ((n)<<6)) /* 0x00, 0x40, 0x80 */ -#define SAM3U_TCN_CCR_OFFSET 0x00 /* Channel Control Register */ -#define SAM3U_TCN_CMR_OFFSET 0x04 /* Channel Mode Register */ - /* 0x08 Reserved */ - /* 0x0c Reserved */ -#define SAM3U_TCN_CV_OFFSET 0x10 /* Counter Value */ -#define SAM3U_TCN_RA_OFFSET 0x14 /* Register A */ -#define SAM3U_TCN_RB_OFFSET 0x18 /* Register B */ -#define SAM3U_TCN_RC_OFFSET 0x1c /* Register C */ -#define SAM3U_TCN_SR_OFFSET 0x20 /* Status Register */ -#define SAM3U_TCN_IER_OFFSET 0x24 /* Interrupt Enable Register */ -#define SAM3U_TCN_IDR_OFFSET 0x28 /* Interrupt Disable Register */ -#define SAM3U_TCN_IMR_OFFSET 0x2c /* Interrupt Mask Register */ - -/* Timer common registers */ - -#define SAM3U_TC_BCR_OFFSET 0xc0 /* Block Control Register */ -#define SAM3U_TC_BMR_OFFSET 0xc4 /* Block Mode Register */ -#define SAM3U_TC_QIER_OFFSET 0xc8 /* QDEC Interrupt Enable Register */ -#define SAM3U_TC_QIDR_OFFSET 0xcc /* QDEC Interrupt Disable Register */ -#define SAM3U_TC_QIMR_OFFSET 0xd0 /* QDEC Interrupt Mask Register */ -#define SAM3U_TC_QISR_OFFSET 0xd4 /* QDEC Interrupt Status Register */ - /* 0xd8 Reserved */ - /* 0xe4 Reserved */ - -/* TC register adresses *************************************************************************/ - -/* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */ - -#define SAM3U_TC_CCR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_CCR_OFFSET) -#define SAM3U_TC_CMR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_CMR_OFFSET) -#define SAM3U_TC_CV(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_CV_OFFSET) -#define SAM3U_TC_RA(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_RA_OFFSET) -#define SAM3U_TC_RB(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_RB_OFFSET) -#define SAM3U_TC_RC(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_RC_OFFSET) -#define SAM3U_TC_SR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_SR_OFFSET) -#define SAM3U_TC_IER(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_IER_OFFSET) -#define SAM3U_TC_IDR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_IDR_OFFSET) -#define SAM3U_TC_IMR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_IMR_OFFSET) - -#define SAM3U_TC0_CCR (SAM3U_TC0_BASE+SAM3U_TCN_CCR_OFFSET) -#define SAM3U_TC0_CMR (SAM3U_TC0_BASE+SAM3U_TCN_CMR_OFFSET) -#define SAM3U_TC0_CV (SAM3U_TC0_BASE+SAM3U_TCN_CV_OFFSET) -#define SAM3U_TC0_RA (SAM3U_TC0_BASE+SAM3U_TCN_RA_OFFSET) -#define SAM3U_TC0_RB (SAM3U_TC0_BASE+SAM3U_TCN_RB_OFFSET) -#define SAM3U_TC0_RC (SAM3U_TC0_BASE+SAM3U_TCN_RC_OFFSET) -#define SAM3U_TC0_SR (SAM3U_TC0_BASE+SAM3U_TCN_SR_OFFSET) -#define SAM3U_TC0_IER (SAM3U_TC0_BASE+SAM3U_TCN_IER_OFFSET) -#define SAM3U_TC0_IDR (SAM3U_TC0_BASE+SAM3U_TCN_IDR_OFFSET) -#define SAM3U_TC0_IMR (SAM3U_TC0_BASE+SAM3U_TCN_IMR_OFFSET) - -#define SAM3U_TC1_CCR (SAM3U_TC1_BASE+SAM3U_TCN_CCR_OFFSET) -#define SAM3U_TC1_CMR (SAM3U_TC1_BASE+SAM3U_TCN_CMR_OFFSET) -#define SAM3U_TC1_CV (SAM3U_TC1_BASE+SAM3U_TCN_CV_OFFSET) -#define SAM3U_TC1_RA (SAM3U_TC1_BASE+SAM3U_TCN_RA_OFFSET) -#define SAM3U_TC1_RB (SAM3U_TC1_BASE+SAM3U_TCN_RB_OFFSET) -#define SAM3U_TC1_RC (SAM3U_TC1_BASE+SAM3U_TCN_RC_OFFSET) -#define SAM3U_TC1_SR (SAM3U_TC1_BASE+SAM3U_TCN_SR_OFFSET) -#define SAM3U_TC1_IER (SAM3U_TC1_BASE+SAM3U_TCN_IER_OFFSET) -#define SAM3U_TC1_IDR (SAM3U_TC1_BASE+SAM3U_TCN_IDR_OFFSET) -#define SAM3U_TC1_IMR (SAM3U_TC1_BASE+SAM3U_TCN_IMR_OFFSET) - -#define SAM3U_TC2_CCR (SAM3U_TC2_BASE+SAM3U_TCN_CCR_OFFSET) -#define SAM3U_TC2_CMR (SAM3U_TC2_BASE+SAM3U_TCN_CMR_OFFSET) -#define SAM3U_TC2_CV (SAM3U_TC2_BASE+SAM3U_TCN_CV_OFFSET) -#define SAM3U_TC2_RA (SAM3U_TC2_BASE+SAM3U_TCN_RA_OFFSET) -#define SAM3U_TC2_RB (SAM3U_TC2_BASE+SAM3U_TCN_RB_OFFSET) -#define SAM3U_TC2_RC (SAM3U_TC2_BASE+SAM3U_TCN_RC_OFFSET) -#define SAM3U_TC2_SR (SAM3U_TC2_BASE+SAM3U_TCN_SR_OFFSET) -#define SAM3U_TC2_IER (SAM3U_TC2_BASE+SAM3U_TCN_IER_OFFSET) -#define SAM3U_TC2_IDR (SAM3U_TC2_BASE+SAM3U_TCN_IDR_OFFSET) -#define SAM3U_TC2_IMR (SAM3U_TC2_BASE+SAM3U_TCN_IMR_OFFSET) - -/* Timer common registers */ - -#define SAM3U_TC_BCR (SAM3U_TC_BASE+SAM3U_TC_BCR_OFFSET) -#define SAM3U_TC_BMR (SAM3U_TC_BASE+SAM3U_TC_BMR_OFFSET) -#define SAM3U_TC_QIER (SAM3U_TC_BASE+SAM3U_TC_QIER_OFFSET) -#define SAM3U_TC_QIDR (SAM3U_TC_BASE+SAM3U_TC_QIDR_OFFSET) -#define SAM3U_TC_QIMR (SAM3U_TC_BASE+SAM3U_TC_QIMR_OFFSET) -#define SAM3U_TC_QISR (SAM3U_TC_BASE+SAM3U_TC_QISR_OFFSET) - -/* TC register bit definitions ******************************************************************/ - -/* Timer common registers */ -/* TC Block Control Register */ - -#define TC_BCR_SYNC (1 << 0) /* Bit 0: Synchro Command - -/* TC Block Mode Register */ - -#define TC_BMR_TC0XC0S_SHIFT (0) /* Bits 0-1: External Clock Signal 0 Selection */ -#define TC_BMR_TC0XC0S_MASK (3 << TC_BMR_TC0XC0S_SHIFT) -# define TC_BMR_TC0XC0S_TCLK0 (0 << TC_BMR_TC0XC0S_SHIFT) -# define TC_BMR_TC0XC0S_NONE (1 << TC_BMR_TC0XC0S_SHIFT) -# define TC_BMR_TC0XC0S_TIOA1 (2 << TC_BMR_TC0XC0S_SHIFT) -# define TC_BMR_TC0XC0S_TIOA2 (3 << TC_BMR_TC0XC0S_SHIFT) -#define TC_BMR_TC1XC1S_SHIFT (2) /* Bits 2-3: External Clock Signal 1 Selection */ -#define TC_BMR_TC1XC1S_MASK (3 << TC_BMR_TC1XC1S_MASK) -# define TC_BMR_TC1XC1S_TCLK1 (0 << TC_BMR_TC1XC1S_SHIFT) -# define TC_BMR_TC1XC1S_NONE (1 << TC_BMR_TC1XC1S_SHIFT) -# define TC_BMR_TC1XC1S_TIOA0 (2 << TC_BMR_TC1XC1S_SHIFT) -# define TC_BMR_TC1XC1S_TIOA2 (3 << TC_BMR_TC1XC1S_SHIFT) -#define TC_BMR_TC2XC2S_SHIFT (4) /* Bits 4-5: External Clock Signal 2 Selection */ -#define TC_BMR_TC2XC2S_MASK (3 << TC_BMR_TC2XC2S_SHIFT) -# define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT) -# define TC_BMR_TC2XC2S_NONE (1 << TC_BMR_TC2XC2S_SHIFT) -# define TC_BMR_TC2XC2S_TIOA0 (2 << TC_BMR_TC2XC2S_SHIFT) -# define TC_BMR_TC2XC2S_TIOA1 (3 << TC_BMR_TC2XC2S_SHIFT) -#define TC_BMR_QDEN (1 << 8) /* Bit 8: Quadrature Decoder Enabled */ -#define TC_BMR_POSEN (1 << 9) /* Bit 9: Position Enabled */ -#define TC_BMR_SPEEDEN (1 << 10) /* Bit 10: Speed Enabled */ -#define TC_BMR_QDTRANS (1 << 11) /* Bit 11: Quadrature Decoding Transparent */ -#define TC_BMR_EDGPHA (1 << 12) /* Bit 12: Edge on PHA count mode */ -#define TC_BMR_INVA (1 << 13) /* Bit 13: Inverted PHA */ -#define TC_BMR_INVB (1 << 14) /* Bit 14: Inverted PHB */ -#define TC_BMR_SWAP (1 << 15) /* Bit 15: Swap PHA and PHB */ -#define TC_BMR_INVIDX (1 << 16) /* Bit 16: Inverted Index */ -#define TC_BMR_IDXPHB (1 << 17) /* Bit 17: Index pin is PHB pin */ -#define TC_BMR_FILTER (1 << 19) /* Bit 19 */ -#define TC_BMR_MAXFILT_SHIFT (20) /* Bits 20-25: Maximum Filter */ -#define TC_BMR_MAXFILT_MASK (63 << TC_BMR_MAXFILT_SHIFT) - -/* TC QDEC Interrupt Enable Register, TC QDEC Interrupt Disable Register, - * TC QDEC Interrupt Mask Register, TC QDEC Interrupt Status Register common - * bit field definitions - */ - -#define TC_QINT_IDX (1 << 0) /* Bit 0: Index (Common) */ -#define TC_QINT_DIRCHG (1 << 1) /* Bit 1: Direction Change (Common) */ -#define TC_QINT_QERR (1 << 2) /* Bit 2: Quadrature Error (Common) */ -#define TC_QISR_DIR (1 << 8) /* Bit 8: Direction (QISR only) */ - -/* Timer Channel Registers */ -/* TC Channel Control Register */ - -#define TCN_CCR_CLKEN (1 << 0) /* Bit 0: Counter Clock Enable Command */ -#define TCN_CCR_CLKDIS (1 << 1) /* Bit 1: Counter Clock Disable Command */ -#define TCN_CCR_SWTRG (1 << 2) /* Bit 2: Software Trigger Command */ - -/* TC Channel Mode Register */ - -#define TCN_CMR_TCCLKS_SHIFT (0) /* Bits 0-2: Clock Selection (Common) */ -#define TCN_CMR_TCCLKS_MASK (7 << TCN_CMR_TCCLKS_SHIFT) -# define TCN_CMR_TCCLKS_TIMERCLOCK1 (0 << TCN_CMR_TCCLKS_SHIFT) -# define TCN_CMR_TCCLKS_TIMERCLOCK2 (1 << TCN_CMR_TCCLKS_SHIFT) -# define TCN_CMR_TCCLKS_TIMERCLOCK3 (2 << TCN_CMR_TCCLKS_SHIFT) -# define TCN_CMR_TCCLKS_TIMERCLOCK4 (3 << TCN_CMR_TCCLKS_SHIFT) -# define TCN_CMR_TCCLKS_TIMERCLOCK5 (4 << TCN_CMR_TCCLKS_SHIFT) -# define TCN_CMR_TCCLKS_XC0 (5 << TCN_CMR_TCCLKS_SHIFT) -# define TCN_CMR_TCCLKS_XC1 (6 << TCN_CMR_TCCLKS_SHIFT) -# define TCN_CMR_TCCLKS_XC2 (7 << TCN_CMR_TCCLKS_SHIFT) -#define TCN_CMR_CLKI (1 << 3) /* Bit 3: Clock Invert (Common) */ -#define TCN_CMR_BURST_SHIFT (4) /* Bits 4-5: Burst Signal Selection (Common) */ -#define TCN_CMR_BURST_MASK (3 << TCN_CMR_BURST_MASK) -#define TCN_CMR_BURST_MASK (3 << TCN_CMR_BURST_MASK) -# define TCN_CMR_BURST_NOTGATED (0 << TCN_CMR_BURST_MASK) /* Nott gated by external signal */ -# define TCN_CMR_BURST_XC0 (1 << TCN_CMR_BURST_MASK) /* XC0 ANDed with selected clock */ -# define TCN_CMR_BURST_XC1 (2 << TCN_CMR_BURST_MASK) /* XC1 ANDed with selected clock */ -# define TCN_CMR_BURST_XC2 (3 << TCN_CMR_BURST_MASK) /* XC2 ANDed with selected clock */ -#define TCN_CMR_WAVE (1 << 15) /* Bit 15: (Common) */ - -#define TCN_CMR_LDBSTOP (1 << 6) /* Bit 6: Counter stopped with RB Loading (Capture mode) */ -#define TCN_CMR_LDBDIS (1 << 7) /* Bit 7: Counter disable with RB Loading (Capture mode) */ -#define TCN_CMR_ETRGEDG_SHIFT (8) /* Bits 8-9: External Trigger Edge Selection (Capture mode) */ -#define TCN_CMR_ETRGEDG_MASK (3 << TCN_CMR_ETRGEDG_SHIFT) -# define TCN_CMR_ETRGEDG_NONE (0 << TCN_CMR_ETRGEDG_SHIFT) /* None */ -# define TCN_CMR_ETRGEDG_REDGE (1 << TCN_CMR_ETRGEDG_SHIFT) /* Rising edge */ -# define TCN_CMR_ETRGEDG_FEDGE (2 << TCN_CMR_ETRGEDG_SHIFT) /* Falling edge */ -# define TCN_CMR_ETRGEDG_EACH (3 << TCN_CMR_ETRGEDG_SHIFT) /* Each */ -#define TCN_CMR_ABETRG (1 << 10) /* Bit 10: TIOA or TIOB External Trigger Selection (Capture mode) */ -#define TCN_CMR_CPCTRG (1 << 14) /* Bit 14: RC Compare Trigger Enable (Capture mode) */ -#define TCN_CMR_LDRA_SHIFT (16) /* Bits 16-17: RA Loading Selection (Capture mode) */ -#define TCN_CMR_LDRA_MASK (3 << TCN_CMR_LDRA_SHIFT) -# define TCN_CMR_LDRA_NONE (0 << TCN_CMR_LDRA_SHIFT) /* None */ -# define TCN_CMR_LDRA_REDGE (1 << TCN_CMR_LDRA_SHIFT) /* Rising edge of TIOA */ -# define TCN_CMR_LDRA_FEDGE (2 << TCN_CMR_LDRA_SHIFT) /* Falling edge of TIOA */ -# define TCN_CMR_LDRA_EACH (3 << TCN_CMR_LDRA_SHIFT) /* Each edge of TIOA */ -#define TCN_CMR_LDRB_SHIFT (18) /* Bits 18-19: RB Loading Selection (Capture mode) */ -#define TCN_CMR_LDRB_MASK (3 << TCN_CMR_LDRB_SHIFT) -# define TCN_CMR_LDRB_NONE (0 << TCN_CMR_LDRB_SHIFT) /* None */ -# define TCN_CMR_LDRB_REDGE (1 << TCN_CMR_LDRB_SHIFT) /* Rising edge of TIOB */ -# define TCN_CMR_LDRB_FEDGE (2 << TCN_CMR_LDRB_SHIFT) /* Falling edge of TIOB */ -# define TCN_CMR_LDRB_EACH (3 << TCN_CMR_LDRB_SHIFT) /* Each edge of TIOB */ - -#define TCN_CMR_CPCSTOP (1 << 6) /* Bit 6: Counter Clock Stopped with RC Compare (Waveform mode) */ -#define TCN_CMR_CPCDIS (1 << 7) /* Bit 7: Counter Clock Disable with RC Compare (Waveform mode) */ -#define TCN_CMR_EEVTEDG_SHIFT (8) /* Bits 8-9: External Event Edge Selection (Waveform mode) */ -#define TCN_CMR_EEVTEDG_MASK (3 << TCN_CMR_EEVTEDG_SHIFT) -# define TCN_CMR_EEVTEDG_NONE (0 << TCN_CMR_EEVTEDG_SHIFT) /* None */ -# define TCN_CMR_EEVTEDG_REDGE (1 << TCN_CMR_EEVTEDG_SHIFT) /* Rising edge */ -# define TCN_CMR_EEVTEDG_FEDGE (2 << TCN_CMR_EEVTEDG_SHIFT) /* Falling edge */ -# define TCN_CMR_EEVTEDG_EACH (3 << TCN_CMR_EEVTEDG_SHIFT) /* Each edge */ -#define TCN_CMR_EEVT_SHIFT (10) /* Bits 10-11: External Event Selection (Waveform mode) */ -#define TCN_CMR_EEVT_MASK (3 << TCN_CMR_EEVT_SHIFT) -# define TCN_CMR_EEVT_TIOB (0 << TCN_CMR_EEVT_SHIFT) /* TIOB input */ -# define TCN_CMR_EEVT_XC0 (1 << TCN_CMR_EEVT_SHIFT) /* XC0 output */ -# define TCN_CMR_EEVT_XC1 (2 << TCN_CMR_EEVT_SHIFT) /* XC1 output */ -# define TCN_CMR_EEVT_XC2 (3 << TCN_CMR_EEVT_SHIFT) /* XC2 output */ -#define TCN_CMR_ENETRG (1 << 12) /* Bit 12: External Event Trigger Enable (Waveform mode) */ -#define TCN_CMR_WAVSEL_SHIFT (13) /* Bits 13-14: Waveform Selection (Waveform mode) */ -#define TCN_CMR_WAVSEL_MASK (3 << TCN_CMR_WAVSEL_SHIFT) -# define TCN_CMR_WAVSEL_UP (0 << TCN_CMR_WAVSEL_SHIFT) /* UP mode w/o auto trigger (Waveform mode) */ -# define TCN_CMR_WAVSEL_UPAUTO (1 << TCN_CMR_WAVSEL_SHIFT) /* UP mode with auto trigger (Waveform mode) */ -# define TCN_CMR_WAVSEL_UPDWN (2 << TCN_CMR_WAVSEL_SHIFT) /* UPDOWN mode w/o auto trigger (Waveform mode) */ -# define TCN_CMR_WAVSEL_UPDWNAUTO (3 << TCN_CMR_WAVSEL_SHIFT) /* UPDOWN mode with auto trigger (Waveform mode) */ -#define TCN_CMR_ACPA_SHIFT (16) /* Bits 16-17: RA Compare Effect on TIOA (Waveform mode) */ -#define TCN_CMR_ACPA_MASK (3 << TCN_CMR_ACPA_SHIFT) -# define TCN_CMR_ACPA_NONE (0 << TCN_CMR_ACPA_SHIFT) -# define TCN_CMR_ACPA_SET (1 << TCN_CMR_ACPA_SHIFT) -# define TCN_CMR_ACPA_CLEAR (2 << TCN_CMR_ACPA_SHIFT) -# define TCN_CMR_ACPA_TOGGLE (3 << TCN_CMR_ACPA_SHIFT) -#define TCN_CMR_ACPC_SHIFT (18) /* Bits 18-19: RC Compare Effect on TIOA (Waveform mode) */ -#define TCN_CMR_ACPC_MASK (3 << TCN_CMR_ACPC_SHIFT) -# define TCN_CMR_ACPC_NONE (0 << TCN_CMR_ACPC_SHIFT) -# define TCN_CMR_ACPC_SET (1 << TCN_CMR_ACPC_SHIFT) -# define TCN_CMR_ACPC_CLEAR (2 << TCN_CMR_ACPC_SHIFT) -# define TCN_CMR_ACPC_TOGGLE (3 << TCN_CMR_ACPC_SHIFT) -#define TCN_CMR_AEEVT_SHIFT (20) /* Bits 20-21: External Event Effect on TIOA (Waveform mode) */ -#define TCN_CMR_AEEVT_MASK (3 << TCN_CMR_AEEVT_SHIFT) -# define TCN_CMR_AEEVT_NONE (0 << TCN_CMR_AEEVT_SHIFT) -# define TCN_CMR_AEEVT_SET (1 << TCN_CMR_AEEVT_SHIFT) -# define TCN_CMR_AEEVT_CLEAR (2 << TCN_CMR_AEEVT_SHIFT) -# define TCN_CMR_AEEVT_TOGGLE (3 << TCN_CMR_AEEVT_SHIFT) -#define TCN_CMR_ASWTRG_SHIFT (22) /* Bits 22-23: Software Trigger Effect on TIOA (Waveform mode) */ -#define TCN_CMR_ASWTRG_MASK (3 << TCN_CMR_ASWTRG_SHIFT) -# define TCN_CMR_ASWTRG_NONE (0 << TCN_CMR_ASWTRG_SHIFT) -# define TCN_CMR_ASWTRG_SET (1 << TCN_CMR_ASWTRG_SHIFT) -# define TCN_CMR_ASWTRG_CLEAR (2 << TCN_CMR_ASWTRG_SHIFT) -# define TCN_CMR_ASWTRG_TOGGLE (3 << TCN_CMR_ASWTRG_SHIFT) -#define TCN_CMR_BCPB_SHIFT (24) /* Bits 24-25: RB Compare Effect on TIOB (Waveform mode) */ -#define TCN_CMR_BCPB_MASK (3 << TCN_CMR_BCPB_SHIFT) -# define TCN_CMR_BCPB_NONE (0 << TCN_CMR_BCPB_SHIFT) -# define TCN_CMR_BCPB_SET (1 << TCN_CMR_BCPB_SHIFT) -# define TCN_CMR_BCPB_CLEAR (2 << TCN_CMR_BCPB_SHIFT) -# define TCN_CMR_BCPB_TOGGLE (3 << TCN_CMR_BCPB_SHIFT) -#define TCN_CMR_BCPC_SHIFT (26) /* Bits 26-27: RC Compare Effect on TIOB (Waveform mode) */ -#define TCN_CMR_BCPC_MASK (3 << TCN_CMR_BCPC_SHIFT) -# define TCN_CMR_BCPC_NONE (0 << TCN_CMR_BCPC_SHIFT) -# define TCN_CMR_BCPC_SET (1 << TCN_CMR_BCPC_SHIFT) -# define TCN_CMR_BCPC_CLEAR (2 << TCN_CMR_BCPC_SHIFT) -# define TCN_CMR_BCPC_TOGGLE (3 << TCN_CMR_BCPC_SHIFT) -#define TCN_CMR_BEEVT_SHIFT (28) /* Bits 28-29: External Event Effect on TIOB (Waveform mode) */ -#define TCN_CMR_BEEVT_MASK (3 << TCN_CMR_BEEVT_SHIFT) -# define TCN_CMR_BEEVT_NONE (0 << TCN_CMR_BEEVT_SHIFT) -# define TCN_CMR_BEEVT_SET (1 << TCN_CMR_BEEVT_SHIFT) -# define TCN_CMR_BEEVT_CLEAR (2 << TCN_CMR_BEEVT_SHIFT) -# define TCN_CMR_BEEVT_TOGGLE (3 << TCN_CMR_BEEVT_SHIFT) -#define TCN_CMR_BSWTRG_SHIFT (30) /* Bits 30-31: Software Trigger Effect on TIOB (Waveform mode) */ -#define TCN_CMR_BSWTRG_MASK (3 << TCN_CMR_BSWTRG_SHIFT) -# define TCN_CMR_BSWTRG_NONE (0 << TCN_CMR_BSWTRG_SHIFT) -# define TCN_CMR_BSWTRG_SET (1 << TCN_CMR_BSWTRG_SHIFT) -# define TCN_CMR_BSWTRG_CLEAR (2 << TCN_CMR_BSWTRG_SHIFT) -# define TCN_CMR_BSWTRG_TOGGLE (3 << TCN_CMR_BSWTRG_SHIFT) - -/* TC Counter Value Register */ - -#define TCN_CV_SHIFT (0) /* Bits 0-15: Counter Value */ -#define TCN_CV_MASK (0xffff << TCN_CV_SHIFT) - -/* TC Register A, B, C */ - -#define TCN_RVALUE_SHIFT (0) /* Bits 0-15: Register A, B, or C value */ -#define TCN_RVALUE_MASK (0xffff << TCN_RVALUE_SHIFT) - -/* TC Status Register, TC Interrupt Enable Register, TC Interrupt Disable Register, and TC Interrupt Mask Register common bit-field definitions */ - -#define TCN_INT_COVFS (1 << 0) /* Bit 0: Counter Overflow */ -#define TCN_INT_LOVRS (1 << 1) /* Bit 1: Load Overrun */ -#define TCN_INT_CPAS (1 << 2) /* Bit 2: RA Compare */ -#define TCN_INT_CPBS (1 << 3) /* Bit 3: RB Compare */ -#define TCN_INT_CPCS (1 << 4) /* Bit 4: RC Compare */ -#define TCN_INT_LDRAS (1 << 5) /* Bit 5: RA Loading */ -#define TCN_INT_LDRBS (1 << 6) /* Bit 6: RB Loading */ -#define TCN_INT_ETRGS (1 << 7) /* Bit 7: External Trigger */ -#define TCN_INT_CLKSTA (1 << 16) /* Bit 16: Clock Enabling (SR only) */ -#define TCN_SR_MTIOA (1 << 17) /* Bit 17: TIOA Mirror (SR only) */ -#define TCN_SR_MTIOB (1 << 18) /* Bit 18: TIOB Mirror (SR only)*/ - -/************************************************************************************************ - * Public Types - ************************************************************************************************/ - -/************************************************************************************************ - * Public Data - ************************************************************************************************/ - -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_TC_H */ +/************************************************************************************************ + * arch/arm/src/sam3u/sam3u_tc.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_TC_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_TC_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* TC register offsets **************************************************************************/ + +/* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */ + +#define SAM3U_TCN_OFFSET(n) (0x00 + ((n)<<6)) /* 0x00, 0x40, 0x80 */ +#define SAM3U_TCN_CCR_OFFSET 0x00 /* Channel Control Register */ +#define SAM3U_TCN_CMR_OFFSET 0x04 /* Channel Mode Register */ + /* 0x08 Reserved */ + /* 0x0c Reserved */ +#define SAM3U_TCN_CV_OFFSET 0x10 /* Counter Value */ +#define SAM3U_TCN_RA_OFFSET 0x14 /* Register A */ +#define SAM3U_TCN_RB_OFFSET 0x18 /* Register B */ +#define SAM3U_TCN_RC_OFFSET 0x1c /* Register C */ +#define SAM3U_TCN_SR_OFFSET 0x20 /* Status Register */ +#define SAM3U_TCN_IER_OFFSET 0x24 /* Interrupt Enable Register */ +#define SAM3U_TCN_IDR_OFFSET 0x28 /* Interrupt Disable Register */ +#define SAM3U_TCN_IMR_OFFSET 0x2c /* Interrupt Mask Register */ + +/* Timer common registers */ + +#define SAM3U_TC_BCR_OFFSET 0xc0 /* Block Control Register */ +#define SAM3U_TC_BMR_OFFSET 0xc4 /* Block Mode Register */ +#define SAM3U_TC_QIER_OFFSET 0xc8 /* QDEC Interrupt Enable Register */ +#define SAM3U_TC_QIDR_OFFSET 0xcc /* QDEC Interrupt Disable Register */ +#define SAM3U_TC_QIMR_OFFSET 0xd0 /* QDEC Interrupt Mask Register */ +#define SAM3U_TC_QISR_OFFSET 0xd4 /* QDEC Interrupt Status Register */ + /* 0xd8 Reserved */ + /* 0xe4 Reserved */ + +/* TC register adresses *************************************************************************/ + +/* Timer channel offsets (with respect to timer base offset 0f 0x00, 0x40, or 0x80 */ + +#define SAM3U_TC_CCR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_CCR_OFFSET) +#define SAM3U_TC_CMR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_CMR_OFFSET) +#define SAM3U_TC_CV(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_CV_OFFSET) +#define SAM3U_TC_RA(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_RA_OFFSET) +#define SAM3U_TC_RB(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_RB_OFFSET) +#define SAM3U_TC_RC(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_RC_OFFSET) +#define SAM3U_TC_SR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_SR_OFFSET) +#define SAM3U_TC_IER(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_IER_OFFSET) +#define SAM3U_TC_IDR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_IDR_OFFSET) +#define SAM3U_TC_IMR(n) (SAM3U_TCN_BASE(n)+SAM3U_TCN_IMR_OFFSET) + +#define SAM3U_TC0_CCR (SAM3U_TC0_BASE+SAM3U_TCN_CCR_OFFSET) +#define SAM3U_TC0_CMR (SAM3U_TC0_BASE+SAM3U_TCN_CMR_OFFSET) +#define SAM3U_TC0_CV (SAM3U_TC0_BASE+SAM3U_TCN_CV_OFFSET) +#define SAM3U_TC0_RA (SAM3U_TC0_BASE+SAM3U_TCN_RA_OFFSET) +#define SAM3U_TC0_RB (SAM3U_TC0_BASE+SAM3U_TCN_RB_OFFSET) +#define SAM3U_TC0_RC (SAM3U_TC0_BASE+SAM3U_TCN_RC_OFFSET) +#define SAM3U_TC0_SR (SAM3U_TC0_BASE+SAM3U_TCN_SR_OFFSET) +#define SAM3U_TC0_IER (SAM3U_TC0_BASE+SAM3U_TCN_IER_OFFSET) +#define SAM3U_TC0_IDR (SAM3U_TC0_BASE+SAM3U_TCN_IDR_OFFSET) +#define SAM3U_TC0_IMR (SAM3U_TC0_BASE+SAM3U_TCN_IMR_OFFSET) + +#define SAM3U_TC1_CCR (SAM3U_TC1_BASE+SAM3U_TCN_CCR_OFFSET) +#define SAM3U_TC1_CMR (SAM3U_TC1_BASE+SAM3U_TCN_CMR_OFFSET) +#define SAM3U_TC1_CV (SAM3U_TC1_BASE+SAM3U_TCN_CV_OFFSET) +#define SAM3U_TC1_RA (SAM3U_TC1_BASE+SAM3U_TCN_RA_OFFSET) +#define SAM3U_TC1_RB (SAM3U_TC1_BASE+SAM3U_TCN_RB_OFFSET) +#define SAM3U_TC1_RC (SAM3U_TC1_BASE+SAM3U_TCN_RC_OFFSET) +#define SAM3U_TC1_SR (SAM3U_TC1_BASE+SAM3U_TCN_SR_OFFSET) +#define SAM3U_TC1_IER (SAM3U_TC1_BASE+SAM3U_TCN_IER_OFFSET) +#define SAM3U_TC1_IDR (SAM3U_TC1_BASE+SAM3U_TCN_IDR_OFFSET) +#define SAM3U_TC1_IMR (SAM3U_TC1_BASE+SAM3U_TCN_IMR_OFFSET) + +#define SAM3U_TC2_CCR (SAM3U_TC2_BASE+SAM3U_TCN_CCR_OFFSET) +#define SAM3U_TC2_CMR (SAM3U_TC2_BASE+SAM3U_TCN_CMR_OFFSET) +#define SAM3U_TC2_CV (SAM3U_TC2_BASE+SAM3U_TCN_CV_OFFSET) +#define SAM3U_TC2_RA (SAM3U_TC2_BASE+SAM3U_TCN_RA_OFFSET) +#define SAM3U_TC2_RB (SAM3U_TC2_BASE+SAM3U_TCN_RB_OFFSET) +#define SAM3U_TC2_RC (SAM3U_TC2_BASE+SAM3U_TCN_RC_OFFSET) +#define SAM3U_TC2_SR (SAM3U_TC2_BASE+SAM3U_TCN_SR_OFFSET) +#define SAM3U_TC2_IER (SAM3U_TC2_BASE+SAM3U_TCN_IER_OFFSET) +#define SAM3U_TC2_IDR (SAM3U_TC2_BASE+SAM3U_TCN_IDR_OFFSET) +#define SAM3U_TC2_IMR (SAM3U_TC2_BASE+SAM3U_TCN_IMR_OFFSET) + +/* Timer common registers */ + +#define SAM3U_TC_BCR (SAM3U_TC_BASE+SAM3U_TC_BCR_OFFSET) +#define SAM3U_TC_BMR (SAM3U_TC_BASE+SAM3U_TC_BMR_OFFSET) +#define SAM3U_TC_QIER (SAM3U_TC_BASE+SAM3U_TC_QIER_OFFSET) +#define SAM3U_TC_QIDR (SAM3U_TC_BASE+SAM3U_TC_QIDR_OFFSET) +#define SAM3U_TC_QIMR (SAM3U_TC_BASE+SAM3U_TC_QIMR_OFFSET) +#define SAM3U_TC_QISR (SAM3U_TC_BASE+SAM3U_TC_QISR_OFFSET) + +/* TC register bit definitions ******************************************************************/ + +/* Timer common registers */ +/* TC Block Control Register */ + +#define TC_BCR_SYNC (1 << 0) /* Bit 0: Synchro Command + +/* TC Block Mode Register */ + +#define TC_BMR_TC0XC0S_SHIFT (0) /* Bits 0-1: External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S_MASK (3 << TC_BMR_TC0XC0S_SHIFT) +# define TC_BMR_TC0XC0S_TCLK0 (0 << TC_BMR_TC0XC0S_SHIFT) +# define TC_BMR_TC0XC0S_NONE (1 << TC_BMR_TC0XC0S_SHIFT) +# define TC_BMR_TC0XC0S_TIOA1 (2 << TC_BMR_TC0XC0S_SHIFT) +# define TC_BMR_TC0XC0S_TIOA2 (3 << TC_BMR_TC0XC0S_SHIFT) +#define TC_BMR_TC1XC1S_SHIFT (2) /* Bits 2-3: External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S_MASK (3 << TC_BMR_TC1XC1S_MASK) +# define TC_BMR_TC1XC1S_TCLK1 (0 << TC_BMR_TC1XC1S_SHIFT) +# define TC_BMR_TC1XC1S_NONE (1 << TC_BMR_TC1XC1S_SHIFT) +# define TC_BMR_TC1XC1S_TIOA0 (2 << TC_BMR_TC1XC1S_SHIFT) +# define TC_BMR_TC1XC1S_TIOA2 (3 << TC_BMR_TC1XC1S_SHIFT) +#define TC_BMR_TC2XC2S_SHIFT (4) /* Bits 4-5: External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S_MASK (3 << TC_BMR_TC2XC2S_SHIFT) +# define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT) +# define TC_BMR_TC2XC2S_NONE (1 << TC_BMR_TC2XC2S_SHIFT) +# define TC_BMR_TC2XC2S_TIOA0 (2 << TC_BMR_TC2XC2S_SHIFT) +# define TC_BMR_TC2XC2S_TIOA1 (3 << TC_BMR_TC2XC2S_SHIFT) +#define TC_BMR_QDEN (1 << 8) /* Bit 8: Quadrature Decoder Enabled */ +#define TC_BMR_POSEN (1 << 9) /* Bit 9: Position Enabled */ +#define TC_BMR_SPEEDEN (1 << 10) /* Bit 10: Speed Enabled */ +#define TC_BMR_QDTRANS (1 << 11) /* Bit 11: Quadrature Decoding Transparent */ +#define TC_BMR_EDGPHA (1 << 12) /* Bit 12: Edge on PHA count mode */ +#define TC_BMR_INVA (1 << 13) /* Bit 13: Inverted PHA */ +#define TC_BMR_INVB (1 << 14) /* Bit 14: Inverted PHB */ +#define TC_BMR_SWAP (1 << 15) /* Bit 15: Swap PHA and PHB */ +#define TC_BMR_INVIDX (1 << 16) /* Bit 16: Inverted Index */ +#define TC_BMR_IDXPHB (1 << 17) /* Bit 17: Index pin is PHB pin */ +#define TC_BMR_FILTER (1 << 19) /* Bit 19 */ +#define TC_BMR_MAXFILT_SHIFT (20) /* Bits 20-25: Maximum Filter */ +#define TC_BMR_MAXFILT_MASK (63 << TC_BMR_MAXFILT_SHIFT) + +/* TC QDEC Interrupt Enable Register, TC QDEC Interrupt Disable Register, + * TC QDEC Interrupt Mask Register, TC QDEC Interrupt Status Register common + * bit field definitions + */ + +#define TC_QINT_IDX (1 << 0) /* Bit 0: Index (Common) */ +#define TC_QINT_DIRCHG (1 << 1) /* Bit 1: Direction Change (Common) */ +#define TC_QINT_QERR (1 << 2) /* Bit 2: Quadrature Error (Common) */ +#define TC_QISR_DIR (1 << 8) /* Bit 8: Direction (QISR only) */ + +/* Timer Channel Registers */ +/* TC Channel Control Register */ + +#define TCN_CCR_CLKEN (1 << 0) /* Bit 0: Counter Clock Enable Command */ +#define TCN_CCR_CLKDIS (1 << 1) /* Bit 1: Counter Clock Disable Command */ +#define TCN_CCR_SWTRG (1 << 2) /* Bit 2: Software Trigger Command */ + +/* TC Channel Mode Register */ + +#define TCN_CMR_TCCLKS_SHIFT (0) /* Bits 0-2: Clock Selection (Common) */ +#define TCN_CMR_TCCLKS_MASK (7 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_TIMERCLOCK1 (0 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_TIMERCLOCK2 (1 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_TIMERCLOCK3 (2 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_TIMERCLOCK4 (3 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_TIMERCLOCK5 (4 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_XC0 (5 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_XC1 (6 << TCN_CMR_TCCLKS_SHIFT) +# define TCN_CMR_TCCLKS_XC2 (7 << TCN_CMR_TCCLKS_SHIFT) +#define TCN_CMR_CLKI (1 << 3) /* Bit 3: Clock Invert (Common) */ +#define TCN_CMR_BURST_SHIFT (4) /* Bits 4-5: Burst Signal Selection (Common) */ +#define TCN_CMR_BURST_MASK (3 << TCN_CMR_BURST_MASK) +#define TCN_CMR_BURST_MASK (3 << TCN_CMR_BURST_MASK) +# define TCN_CMR_BURST_NOTGATED (0 << TCN_CMR_BURST_MASK) /* Nott gated by external signal */ +# define TCN_CMR_BURST_XC0 (1 << TCN_CMR_BURST_MASK) /* XC0 ANDed with selected clock */ +# define TCN_CMR_BURST_XC1 (2 << TCN_CMR_BURST_MASK) /* XC1 ANDed with selected clock */ +# define TCN_CMR_BURST_XC2 (3 << TCN_CMR_BURST_MASK) /* XC2 ANDed with selected clock */ +#define TCN_CMR_WAVE (1 << 15) /* Bit 15: (Common) */ + +#define TCN_CMR_LDBSTOP (1 << 6) /* Bit 6: Counter stopped with RB Loading (Capture mode) */ +#define TCN_CMR_LDBDIS (1 << 7) /* Bit 7: Counter disable with RB Loading (Capture mode) */ +#define TCN_CMR_ETRGEDG_SHIFT (8) /* Bits 8-9: External Trigger Edge Selection (Capture mode) */ +#define TCN_CMR_ETRGEDG_MASK (3 << TCN_CMR_ETRGEDG_SHIFT) +# define TCN_CMR_ETRGEDG_NONE (0 << TCN_CMR_ETRGEDG_SHIFT) /* None */ +# define TCN_CMR_ETRGEDG_REDGE (1 << TCN_CMR_ETRGEDG_SHIFT) /* Rising edge */ +# define TCN_CMR_ETRGEDG_FEDGE (2 << TCN_CMR_ETRGEDG_SHIFT) /* Falling edge */ +# define TCN_CMR_ETRGEDG_EACH (3 << TCN_CMR_ETRGEDG_SHIFT) /* Each */ +#define TCN_CMR_ABETRG (1 << 10) /* Bit 10: TIOA or TIOB External Trigger Selection (Capture mode) */ +#define TCN_CMR_CPCTRG (1 << 14) /* Bit 14: RC Compare Trigger Enable (Capture mode) */ +#define TCN_CMR_LDRA_SHIFT (16) /* Bits 16-17: RA Loading Selection (Capture mode) */ +#define TCN_CMR_LDRA_MASK (3 << TCN_CMR_LDRA_SHIFT) +# define TCN_CMR_LDRA_NONE (0 << TCN_CMR_LDRA_SHIFT) /* None */ +# define TCN_CMR_LDRA_REDGE (1 << TCN_CMR_LDRA_SHIFT) /* Rising edge of TIOA */ +# define TCN_CMR_LDRA_FEDGE (2 << TCN_CMR_LDRA_SHIFT) /* Falling edge of TIOA */ +# define TCN_CMR_LDRA_EACH (3 << TCN_CMR_LDRA_SHIFT) /* Each edge of TIOA */ +#define TCN_CMR_LDRB_SHIFT (18) /* Bits 18-19: RB Loading Selection (Capture mode) */ +#define TCN_CMR_LDRB_MASK (3 << TCN_CMR_LDRB_SHIFT) +# define TCN_CMR_LDRB_NONE (0 << TCN_CMR_LDRB_SHIFT) /* None */ +# define TCN_CMR_LDRB_REDGE (1 << TCN_CMR_LDRB_SHIFT) /* Rising edge of TIOB */ +# define TCN_CMR_LDRB_FEDGE (2 << TCN_CMR_LDRB_SHIFT) /* Falling edge of TIOB */ +# define TCN_CMR_LDRB_EACH (3 << TCN_CMR_LDRB_SHIFT) /* Each edge of TIOB */ + +#define TCN_CMR_CPCSTOP (1 << 6) /* Bit 6: Counter Clock Stopped with RC Compare (Waveform mode) */ +#define TCN_CMR_CPCDIS (1 << 7) /* Bit 7: Counter Clock Disable with RC Compare (Waveform mode) */ +#define TCN_CMR_EEVTEDG_SHIFT (8) /* Bits 8-9: External Event Edge Selection (Waveform mode) */ +#define TCN_CMR_EEVTEDG_MASK (3 << TCN_CMR_EEVTEDG_SHIFT) +# define TCN_CMR_EEVTEDG_NONE (0 << TCN_CMR_EEVTEDG_SHIFT) /* None */ +# define TCN_CMR_EEVTEDG_REDGE (1 << TCN_CMR_EEVTEDG_SHIFT) /* Rising edge */ +# define TCN_CMR_EEVTEDG_FEDGE (2 << TCN_CMR_EEVTEDG_SHIFT) /* Falling edge */ +# define TCN_CMR_EEVTEDG_EACH (3 << TCN_CMR_EEVTEDG_SHIFT) /* Each edge */ +#define TCN_CMR_EEVT_SHIFT (10) /* Bits 10-11: External Event Selection (Waveform mode) */ +#define TCN_CMR_EEVT_MASK (3 << TCN_CMR_EEVT_SHIFT) +# define TCN_CMR_EEVT_TIOB (0 << TCN_CMR_EEVT_SHIFT) /* TIOB input */ +# define TCN_CMR_EEVT_XC0 (1 << TCN_CMR_EEVT_SHIFT) /* XC0 output */ +# define TCN_CMR_EEVT_XC1 (2 << TCN_CMR_EEVT_SHIFT) /* XC1 output */ +# define TCN_CMR_EEVT_XC2 (3 << TCN_CMR_EEVT_SHIFT) /* XC2 output */ +#define TCN_CMR_ENETRG (1 << 12) /* Bit 12: External Event Trigger Enable (Waveform mode) */ +#define TCN_CMR_WAVSEL_SHIFT (13) /* Bits 13-14: Waveform Selection (Waveform mode) */ +#define TCN_CMR_WAVSEL_MASK (3 << TCN_CMR_WAVSEL_SHIFT) +# define TCN_CMR_WAVSEL_UP (0 << TCN_CMR_WAVSEL_SHIFT) /* UP mode w/o auto trigger (Waveform mode) */ +# define TCN_CMR_WAVSEL_UPAUTO (1 << TCN_CMR_WAVSEL_SHIFT) /* UP mode with auto trigger (Waveform mode) */ +# define TCN_CMR_WAVSEL_UPDWN (2 << TCN_CMR_WAVSEL_SHIFT) /* UPDOWN mode w/o auto trigger (Waveform mode) */ +# define TCN_CMR_WAVSEL_UPDWNAUTO (3 << TCN_CMR_WAVSEL_SHIFT) /* UPDOWN mode with auto trigger (Waveform mode) */ +#define TCN_CMR_ACPA_SHIFT (16) /* Bits 16-17: RA Compare Effect on TIOA (Waveform mode) */ +#define TCN_CMR_ACPA_MASK (3 << TCN_CMR_ACPA_SHIFT) +# define TCN_CMR_ACPA_NONE (0 << TCN_CMR_ACPA_SHIFT) +# define TCN_CMR_ACPA_SET (1 << TCN_CMR_ACPA_SHIFT) +# define TCN_CMR_ACPA_CLEAR (2 << TCN_CMR_ACPA_SHIFT) +# define TCN_CMR_ACPA_TOGGLE (3 << TCN_CMR_ACPA_SHIFT) +#define TCN_CMR_ACPC_SHIFT (18) /* Bits 18-19: RC Compare Effect on TIOA (Waveform mode) */ +#define TCN_CMR_ACPC_MASK (3 << TCN_CMR_ACPC_SHIFT) +# define TCN_CMR_ACPC_NONE (0 << TCN_CMR_ACPC_SHIFT) +# define TCN_CMR_ACPC_SET (1 << TCN_CMR_ACPC_SHIFT) +# define TCN_CMR_ACPC_CLEAR (2 << TCN_CMR_ACPC_SHIFT) +# define TCN_CMR_ACPC_TOGGLE (3 << TCN_CMR_ACPC_SHIFT) +#define TCN_CMR_AEEVT_SHIFT (20) /* Bits 20-21: External Event Effect on TIOA (Waveform mode) */ +#define TCN_CMR_AEEVT_MASK (3 << TCN_CMR_AEEVT_SHIFT) +# define TCN_CMR_AEEVT_NONE (0 << TCN_CMR_AEEVT_SHIFT) +# define TCN_CMR_AEEVT_SET (1 << TCN_CMR_AEEVT_SHIFT) +# define TCN_CMR_AEEVT_CLEAR (2 << TCN_CMR_AEEVT_SHIFT) +# define TCN_CMR_AEEVT_TOGGLE (3 << TCN_CMR_AEEVT_SHIFT) +#define TCN_CMR_ASWTRG_SHIFT (22) /* Bits 22-23: Software Trigger Effect on TIOA (Waveform mode) */ +#define TCN_CMR_ASWTRG_MASK (3 << TCN_CMR_ASWTRG_SHIFT) +# define TCN_CMR_ASWTRG_NONE (0 << TCN_CMR_ASWTRG_SHIFT) +# define TCN_CMR_ASWTRG_SET (1 << TCN_CMR_ASWTRG_SHIFT) +# define TCN_CMR_ASWTRG_CLEAR (2 << TCN_CMR_ASWTRG_SHIFT) +# define TCN_CMR_ASWTRG_TOGGLE (3 << TCN_CMR_ASWTRG_SHIFT) +#define TCN_CMR_BCPB_SHIFT (24) /* Bits 24-25: RB Compare Effect on TIOB (Waveform mode) */ +#define TCN_CMR_BCPB_MASK (3 << TCN_CMR_BCPB_SHIFT) +# define TCN_CMR_BCPB_NONE (0 << TCN_CMR_BCPB_SHIFT) +# define TCN_CMR_BCPB_SET (1 << TCN_CMR_BCPB_SHIFT) +# define TCN_CMR_BCPB_CLEAR (2 << TCN_CMR_BCPB_SHIFT) +# define TCN_CMR_BCPB_TOGGLE (3 << TCN_CMR_BCPB_SHIFT) +#define TCN_CMR_BCPC_SHIFT (26) /* Bits 26-27: RC Compare Effect on TIOB (Waveform mode) */ +#define TCN_CMR_BCPC_MASK (3 << TCN_CMR_BCPC_SHIFT) +# define TCN_CMR_BCPC_NONE (0 << TCN_CMR_BCPC_SHIFT) +# define TCN_CMR_BCPC_SET (1 << TCN_CMR_BCPC_SHIFT) +# define TCN_CMR_BCPC_CLEAR (2 << TCN_CMR_BCPC_SHIFT) +# define TCN_CMR_BCPC_TOGGLE (3 << TCN_CMR_BCPC_SHIFT) +#define TCN_CMR_BEEVT_SHIFT (28) /* Bits 28-29: External Event Effect on TIOB (Waveform mode) */ +#define TCN_CMR_BEEVT_MASK (3 << TCN_CMR_BEEVT_SHIFT) +# define TCN_CMR_BEEVT_NONE (0 << TCN_CMR_BEEVT_SHIFT) +# define TCN_CMR_BEEVT_SET (1 << TCN_CMR_BEEVT_SHIFT) +# define TCN_CMR_BEEVT_CLEAR (2 << TCN_CMR_BEEVT_SHIFT) +# define TCN_CMR_BEEVT_TOGGLE (3 << TCN_CMR_BEEVT_SHIFT) +#define TCN_CMR_BSWTRG_SHIFT (30) /* Bits 30-31: Software Trigger Effect on TIOB (Waveform mode) */ +#define TCN_CMR_BSWTRG_MASK (3 << TCN_CMR_BSWTRG_SHIFT) +# define TCN_CMR_BSWTRG_NONE (0 << TCN_CMR_BSWTRG_SHIFT) +# define TCN_CMR_BSWTRG_SET (1 << TCN_CMR_BSWTRG_SHIFT) +# define TCN_CMR_BSWTRG_CLEAR (2 << TCN_CMR_BSWTRG_SHIFT) +# define TCN_CMR_BSWTRG_TOGGLE (3 << TCN_CMR_BSWTRG_SHIFT) + +/* TC Counter Value Register */ + +#define TCN_CV_SHIFT (0) /* Bits 0-15: Counter Value */ +#define TCN_CV_MASK (0xffff << TCN_CV_SHIFT) + +/* TC Register A, B, C */ + +#define TCN_RVALUE_SHIFT (0) /* Bits 0-15: Register A, B, or C value */ +#define TCN_RVALUE_MASK (0xffff << TCN_RVALUE_SHIFT) + +/* TC Status Register, TC Interrupt Enable Register, TC Interrupt Disable Register, and TC Interrupt Mask Register common bit-field definitions */ + +#define TCN_INT_COVFS (1 << 0) /* Bit 0: Counter Overflow */ +#define TCN_INT_LOVRS (1 << 1) /* Bit 1: Load Overrun */ +#define TCN_INT_CPAS (1 << 2) /* Bit 2: RA Compare */ +#define TCN_INT_CPBS (1 << 3) /* Bit 3: RB Compare */ +#define TCN_INT_CPCS (1 << 4) /* Bit 4: RC Compare */ +#define TCN_INT_LDRAS (1 << 5) /* Bit 5: RA Loading */ +#define TCN_INT_LDRBS (1 << 6) /* Bit 6: RB Loading */ +#define TCN_INT_ETRGS (1 << 7) /* Bit 7: External Trigger */ +#define TCN_INT_CLKSTA (1 << 16) /* Bit 16: Clock Enabling (SR only) */ +#define TCN_SR_MTIOA (1 << 17) /* Bit 17: TIOA Mirror (SR only) */ +#define TCN_SR_MTIOB (1 << 18) /* Bit 18: TIOB Mirror (SR only)*/ + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_TC_H */ diff --git a/arch/arm/src/sam3u/sam3u_timerisr.c b/arch/arm/src/sam3u/sam3u_timerisr.c index 225af25f6a381976cfeac5674d1c6c8351796fc0..5ff6dea699e7a73fb51e953ec5fe1f9838b7e168 100644 --- a/arch/arm/src/sam3u/sam3u_timerisr.c +++ b/arch/arm/src/sam3u/sam3u_timerisr.c @@ -2,7 +2,7 @@ * arch/arm/src/sam3u/sam3u_timerisr.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/sam3u/sam3u_twi.h b/arch/arm/src/sam3u/sam3u_twi.h index 4a26ecdc4e9b4908a25ebbc06fb98a79b13c9168..66d1f23b3674771c2ff8156070b76d4832594d28 100644 --- a/arch/arm/src/sam3u/sam3u_twi.h +++ b/arch/arm/src/sam3u/sam3u_twi.h @@ -1,192 +1,192 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_twi.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_TWI_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_TWI_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* TWI register offsets *****************************************************************/ - -#define SAM3U_TWI_CR_OFFSET 0x00 /* Control Register */ -#define SAM3U_TWI_MMR_OFFSET 0x04 /* Master Mode Register */ -#define SAM3U_TWI_SMR_OFFSET 0x08 /* Slave Mode Register */ -#define SAM3U_TWI_IADR_OFFSET 0x0c /* Internal Address Register */ -#define SAM3U_TWI_CWGR_OFFSET 0x10 /* Clock Waveform Generator Register */ -#define SAM3U_TWI_SR_OFFSET 0x20 /* Status Register */ -#define SAM3U_TWI_IER_OFFSET 0x24 /* Interrupt Enable Register */ -#define SAM3U_TWI_IDR_OFFSET 0x28 /* Interrupt Disable Register */ -#define SAM3U_TWI_IMR_OFFSET 0x2c /* Interrupt Mask Register */ -#define SAM3U_TWI_RHR_OFFSET 0x30 /* Receive Holding Register */ -#define SAM3U_TWI_THR_OFFSET 0x34 /* Transmit Holding Register */ - /* 0x38-0xfc: Reserved */ - /* 0x100-0x124: Reserved for the PDC */ - -/* TWI register adresses ****************************************************************/ - -#define SAM3U_TWI_CR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_CR_OFFSET) -#define SAM3U_TWI_MMR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_MMR_OFFSET) -#define SAM3U_TWI_SMR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_SMR_OFFSET) -#define SAM3U_TWI_IADR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IADR_OFFSET) -#define SAM3U_TWI_CWGR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_CWGR_OFFSET) -#define SAM3U_TWI_SR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_SR_OFFSET) -#define SAM3U_TWI_IER(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IER_OFFSET) -#define SAM3U_TWI_IDR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IDR_OFFSET) -#define SAM3U_TWI_IMR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IMR_OFFSET) -#define SAM3U_TWI_RHR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_RHR_OFFSET) -#define SAM3U_TWI_THR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_THR_OFFSET) - -#define SAM3U_TWI0_CR (SAM3U_TWI0_BASE+SAM3U_TWI_CR_OFFSET) -#define SAM3U_TWI0_MMR (SAM3U_TWI0_BASE+SAM3U_TWI_MMR_OFFSET) -#define SAM3U_TWI0_SMR (SAM3U_TWI0_BASE+SAM3U_TWI_SMR_OFFSET) -#define SAM3U_TWI0_IADR (SAM3U_TWI0_BASE+SAM3U_TWI_IADR_OFFSET) -#define SAM3U_TWI0_CWGR (SAM3U_TWI0_BASE+SAM3U_TWI_CWGR_OFFSET) -#define SAM3U_TWI0_SR (SAM3U_TWI0_BASE+SAM3U_TWI_SR_OFFSET) -#define SAM3U_TWI0_IER (SAM3U_TWI0_BASE+SAM3U_TWI_IER_OFFSET) -#define SAM3U_TWI0_IDR (SAM3U_TWI0_BASE+SAM3U_TWI_IDR_OFFSET) -#define SAM3U_TWI0_IMR (SAM3U_TWI0_BASE+SAM3U_TWI_IMR_OFFSET) -#define SAM3U_TWI0_RHR (SAM3U_TWI0_BASE+SAM3U_TWI_RHR_OFFSET) -#define SAM3U_TWI0_THR (SAM3U_TWI0_BASE+SAM3U_TWI_THR_OFFSET) - -#define SAM3U_TWI1_CR (SAM3U_TWI1_BASE+SAM3U_TWI_CR_OFFSET) -#define SAM3U_TWI1_MMR (SAM3U_TWI1_BASE+SAM3U_TWI_MMR_OFFSET) -#define SAM3U_TWI1_SMR (SAM3U_TWI1_BASE+SAM3U_TWI_SMR_OFFSET) -#define SAM3U_TWI1_IADR (SAM3U_TWI1_BASE+SAM3U_TWI_IADR_OFFSET) -#define SAM3U_TWI1_CWGR (SAM3U_TWI1_BASE+SAM3U_TWI_CWGR_OFFSET) -#define SAM3U_TWI1_SR (SAM3U_TWI1_BASE+SAM3U_TWI_SR_OFFSET) -#define SAM3U_TWI1_IER (SAM3U_TWI1_BASE+SAM3U_TWI_IER_OFFSET) -#define SAM3U_TWI1_IDR (SAM3U_TWI1_BASE+SAM3U_TWI_IDR_OFFSET) -#define SAM3U_TWI1_IMR (SAM3U_TWI1_BASE+SAM3U_TWI_IMR_OFFSET) -#define SAM3U_TWI1_RHR (SAM3U_TWI1_BASE+SAM3U_TWI_RHR_OFFSET) -#define SAM3U_TWI1_THR (SAM3U_TWI1_BASE+SAM3U_TWI_THR_OFFSET) - -/* TWI register bit definitions *********************************************************/ - -/* TWI Control Register */ - -#define TWI_CR_START (1 << 0) /* Bit 0: Send a START Condition */ -#define TWI_CR_STOP (1 << 1) /* Bit 1: Send a STOP Condition */ -#define TWI_CR_MSEN (1 << 2) /* Bit 2: TWI Master Mode Enabled */ -#define TWI_CR_MSDIS (1 << 3) /* Bit 3: TWI Master Mode Disabled */ -#define TWI_CR_SVEN (1 << 4) /* Bit 4: TWI Slave Mode Enabled */ -#define TWI_CR_SVDIS (1 << 5) /* Bit 5: TWI Slave Mode Disabled */ -#define TWI_CR_QUICK (1 << 6) /* Bit 6: SMBUS Quick Command */ -#define TWI_CR_SWRST (1 << 7) /* Bit 7: Software Reset */ - -/* TWI Master Mode Register */' - -#define TWI_MMR_IADRSZ_SHIFT (8) /* Bits 8-9: Internal Device Address Size */ -#define TWI_MMR_IADRSZ_MASK (3 << TWI_MMR_IADRSZ_SHIFT) -# define TWI_MMR_IADRSZ_NONE (0 << TWI_MMR_IADRSZ_SHIFT) /* No internal device address */ -# define TWI_MMR_IADRSZ_1BYTE (1 << TWI_MMR_IADRSZ_SHIFT) /* One-byte internal device address */ -# define TWI_MMR_IADRSZ_3BYTE (2 << TWI_MMR_IADRSZ_SHIFT) /* Two-byte internal device address */ -# define TWI_MMR_IADRSZ_3BYTE (3 << TWI_MMR_IADRSZ_SHIFT) /* Three-byte internal device address */ -#define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */ -#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-23: Device Address */ -#define TWI_MMR_DADR_MASK (0xff << TWI_MMR_DADR_SHIFT) - -/* TWI Slave Mode Register */ - -#define TWI_SMR_SADR_SHIFT (16) /* Bits 16-23: Slave Address */ -#define TWI_SMR_SADR_MASK (0xff << TWI_SMR_SADR_SHIFT) - -/* TWI Internal Address Register */ - -#define TWI_IADR_SHIFT (0) /* Bits 0-23: Internal Address */ -#define TWI_IADR_MASK (0x00ffffff << TWI_IADR_SHIFT) - -/* TWI Clock Waveform Generator Register */ - -#define TWI_CWGR_CLDIV_SHIFT (0) /* Bits 0-7: Clock Low Divider */ -#define TWI_CWGR_CLDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT) -#define TWI_CWGR_CHDIV_SHIFT (8) /* Bits 8-15: Clock High Divider */ -#define TWI_CWGR_CHDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT) -#define TWI_CWGR_CKDIV_SHIFT (16) /* Bits 16-18: Clock Divider */ -#define TWI_CWGR_CKDIV_MASK (7 << TWI_CWGR_CLDIV_SHIFT) - -/* TWI Status Register, TWI Interrupt Enable Register, TWI Interrupt Disable - * Register, and TWI Interrupt Mask Register common bit fields. - */ - -#define TWI_INT_TXCOMP (1 << 0) /* Bit 0: Transmission Completed */ -#define TWI_INT_RXRDY (1 << 1) /* Bit 1: Receive Holding Register */ -#define TWI_INT_TXRDY (1 << 2) /* Bit 2: Transmit Holding Register Ready */ -#define TWI_SR_SVREAD (1 << 3) /* Bit 3: Slave Read (SR only) */ -#define TWI_INT_SVACC (1 << 4) /* Bit 4: Slave Access */ -#define TWI_INT_GACC (1 << 5) /* Bit 5: General Call Access */ -#define TWI_INT_OVRE (1 << 6) /* Bit 6: Overrun Error */ -#define TWI_INT_NACK (1 << 8) /* Bit 8: Not Acknowledged */ -#define TWI_INT_ARBLST (1 << 9) /* Bit 9: Arbitration Lost */ -#define TWI_INT_SCLWS (1 << 10) /* Bit 10: Clock Wait State */ -#define TWI_INT_EOSACC (1 << 11) /* Bit 11: End Of Slave Access */ -#define TWI_INT_ENDRX (1 << 12) /* Bit 12: End of RX buffer */ -#define TWI_INT_ENDTX (1 << 13) /* Bit 13: End of TX buffer */ -#define TWI_INT_RXBUFF (1 << 14) /* Bit 14: RX Buffer */ -#define TWI_INT_TXBUFE (1 << 15) /* Bit 15: TX Buffer Empty */ - -/* TWI Receive Holding Register */ - -#define TWI_RHR_RXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Receive Holding Data */ -#define TWI_RHR_RXDATA_MASK (0xff << TWI_RHR_RXDATA_SHIFT) - -/* TWI Transmit Holding Register */ - -#define TWI_THR_TXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Transmit Holding Data */ -#define TWI_THR_TXDATA_MASK (0xff << TWI_THR_TXDATA_SHIFT) - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_TWI_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_twi.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_TWI_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_TWI_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* TWI register offsets *****************************************************************/ + +#define SAM3U_TWI_CR_OFFSET 0x00 /* Control Register */ +#define SAM3U_TWI_MMR_OFFSET 0x04 /* Master Mode Register */ +#define SAM3U_TWI_SMR_OFFSET 0x08 /* Slave Mode Register */ +#define SAM3U_TWI_IADR_OFFSET 0x0c /* Internal Address Register */ +#define SAM3U_TWI_CWGR_OFFSET 0x10 /* Clock Waveform Generator Register */ +#define SAM3U_TWI_SR_OFFSET 0x20 /* Status Register */ +#define SAM3U_TWI_IER_OFFSET 0x24 /* Interrupt Enable Register */ +#define SAM3U_TWI_IDR_OFFSET 0x28 /* Interrupt Disable Register */ +#define SAM3U_TWI_IMR_OFFSET 0x2c /* Interrupt Mask Register */ +#define SAM3U_TWI_RHR_OFFSET 0x30 /* Receive Holding Register */ +#define SAM3U_TWI_THR_OFFSET 0x34 /* Transmit Holding Register */ + /* 0x38-0xfc: Reserved */ + /* 0x100-0x124: Reserved for the PDC */ + +/* TWI register adresses ****************************************************************/ + +#define SAM3U_TWI_CR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_CR_OFFSET) +#define SAM3U_TWI_MMR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_MMR_OFFSET) +#define SAM3U_TWI_SMR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_SMR_OFFSET) +#define SAM3U_TWI_IADR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IADR_OFFSET) +#define SAM3U_TWI_CWGR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_CWGR_OFFSET) +#define SAM3U_TWI_SR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_SR_OFFSET) +#define SAM3U_TWI_IER(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IER_OFFSET) +#define SAM3U_TWI_IDR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IDR_OFFSET) +#define SAM3U_TWI_IMR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_IMR_OFFSET) +#define SAM3U_TWI_RHR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_RHR_OFFSET) +#define SAM3U_TWI_THR(n) (SAM3U_TWIN_BASE(n)+SAM3U_TWI_THR_OFFSET) + +#define SAM3U_TWI0_CR (SAM3U_TWI0_BASE+SAM3U_TWI_CR_OFFSET) +#define SAM3U_TWI0_MMR (SAM3U_TWI0_BASE+SAM3U_TWI_MMR_OFFSET) +#define SAM3U_TWI0_SMR (SAM3U_TWI0_BASE+SAM3U_TWI_SMR_OFFSET) +#define SAM3U_TWI0_IADR (SAM3U_TWI0_BASE+SAM3U_TWI_IADR_OFFSET) +#define SAM3U_TWI0_CWGR (SAM3U_TWI0_BASE+SAM3U_TWI_CWGR_OFFSET) +#define SAM3U_TWI0_SR (SAM3U_TWI0_BASE+SAM3U_TWI_SR_OFFSET) +#define SAM3U_TWI0_IER (SAM3U_TWI0_BASE+SAM3U_TWI_IER_OFFSET) +#define SAM3U_TWI0_IDR (SAM3U_TWI0_BASE+SAM3U_TWI_IDR_OFFSET) +#define SAM3U_TWI0_IMR (SAM3U_TWI0_BASE+SAM3U_TWI_IMR_OFFSET) +#define SAM3U_TWI0_RHR (SAM3U_TWI0_BASE+SAM3U_TWI_RHR_OFFSET) +#define SAM3U_TWI0_THR (SAM3U_TWI0_BASE+SAM3U_TWI_THR_OFFSET) + +#define SAM3U_TWI1_CR (SAM3U_TWI1_BASE+SAM3U_TWI_CR_OFFSET) +#define SAM3U_TWI1_MMR (SAM3U_TWI1_BASE+SAM3U_TWI_MMR_OFFSET) +#define SAM3U_TWI1_SMR (SAM3U_TWI1_BASE+SAM3U_TWI_SMR_OFFSET) +#define SAM3U_TWI1_IADR (SAM3U_TWI1_BASE+SAM3U_TWI_IADR_OFFSET) +#define SAM3U_TWI1_CWGR (SAM3U_TWI1_BASE+SAM3U_TWI_CWGR_OFFSET) +#define SAM3U_TWI1_SR (SAM3U_TWI1_BASE+SAM3U_TWI_SR_OFFSET) +#define SAM3U_TWI1_IER (SAM3U_TWI1_BASE+SAM3U_TWI_IER_OFFSET) +#define SAM3U_TWI1_IDR (SAM3U_TWI1_BASE+SAM3U_TWI_IDR_OFFSET) +#define SAM3U_TWI1_IMR (SAM3U_TWI1_BASE+SAM3U_TWI_IMR_OFFSET) +#define SAM3U_TWI1_RHR (SAM3U_TWI1_BASE+SAM3U_TWI_RHR_OFFSET) +#define SAM3U_TWI1_THR (SAM3U_TWI1_BASE+SAM3U_TWI_THR_OFFSET) + +/* TWI register bit definitions *********************************************************/ + +/* TWI Control Register */ + +#define TWI_CR_START (1 << 0) /* Bit 0: Send a START Condition */ +#define TWI_CR_STOP (1 << 1) /* Bit 1: Send a STOP Condition */ +#define TWI_CR_MSEN (1 << 2) /* Bit 2: TWI Master Mode Enabled */ +#define TWI_CR_MSDIS (1 << 3) /* Bit 3: TWI Master Mode Disabled */ +#define TWI_CR_SVEN (1 << 4) /* Bit 4: TWI Slave Mode Enabled */ +#define TWI_CR_SVDIS (1 << 5) /* Bit 5: TWI Slave Mode Disabled */ +#define TWI_CR_QUICK (1 << 6) /* Bit 6: SMBUS Quick Command */ +#define TWI_CR_SWRST (1 << 7) /* Bit 7: Software Reset */ + +/* TWI Master Mode Register */' + +#define TWI_MMR_IADRSZ_SHIFT (8) /* Bits 8-9: Internal Device Address Size */ +#define TWI_MMR_IADRSZ_MASK (3 << TWI_MMR_IADRSZ_SHIFT) +# define TWI_MMR_IADRSZ_NONE (0 << TWI_MMR_IADRSZ_SHIFT) /* No internal device address */ +# define TWI_MMR_IADRSZ_1BYTE (1 << TWI_MMR_IADRSZ_SHIFT) /* One-byte internal device address */ +# define TWI_MMR_IADRSZ_3BYTE (2 << TWI_MMR_IADRSZ_SHIFT) /* Two-byte internal device address */ +# define TWI_MMR_IADRSZ_3BYTE (3 << TWI_MMR_IADRSZ_SHIFT) /* Three-byte internal device address */ +#define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */ +#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-23: Device Address */ +#define TWI_MMR_DADR_MASK (0xff << TWI_MMR_DADR_SHIFT) + +/* TWI Slave Mode Register */ + +#define TWI_SMR_SADR_SHIFT (16) /* Bits 16-23: Slave Address */ +#define TWI_SMR_SADR_MASK (0xff << TWI_SMR_SADR_SHIFT) + +/* TWI Internal Address Register */ + +#define TWI_IADR_SHIFT (0) /* Bits 0-23: Internal Address */ +#define TWI_IADR_MASK (0x00ffffff << TWI_IADR_SHIFT) + +/* TWI Clock Waveform Generator Register */ + +#define TWI_CWGR_CLDIV_SHIFT (0) /* Bits 0-7: Clock Low Divider */ +#define TWI_CWGR_CLDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT) +#define TWI_CWGR_CHDIV_SHIFT (8) /* Bits 8-15: Clock High Divider */ +#define TWI_CWGR_CHDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT) +#define TWI_CWGR_CKDIV_SHIFT (16) /* Bits 16-18: Clock Divider */ +#define TWI_CWGR_CKDIV_MASK (7 << TWI_CWGR_CLDIV_SHIFT) + +/* TWI Status Register, TWI Interrupt Enable Register, TWI Interrupt Disable + * Register, and TWI Interrupt Mask Register common bit fields. + */ + +#define TWI_INT_TXCOMP (1 << 0) /* Bit 0: Transmission Completed */ +#define TWI_INT_RXRDY (1 << 1) /* Bit 1: Receive Holding Register */ +#define TWI_INT_TXRDY (1 << 2) /* Bit 2: Transmit Holding Register Ready */ +#define TWI_SR_SVREAD (1 << 3) /* Bit 3: Slave Read (SR only) */ +#define TWI_INT_SVACC (1 << 4) /* Bit 4: Slave Access */ +#define TWI_INT_GACC (1 << 5) /* Bit 5: General Call Access */ +#define TWI_INT_OVRE (1 << 6) /* Bit 6: Overrun Error */ +#define TWI_INT_NACK (1 << 8) /* Bit 8: Not Acknowledged */ +#define TWI_INT_ARBLST (1 << 9) /* Bit 9: Arbitration Lost */ +#define TWI_INT_SCLWS (1 << 10) /* Bit 10: Clock Wait State */ +#define TWI_INT_EOSACC (1 << 11) /* Bit 11: End Of Slave Access */ +#define TWI_INT_ENDRX (1 << 12) /* Bit 12: End of RX buffer */ +#define TWI_INT_ENDTX (1 << 13) /* Bit 13: End of TX buffer */ +#define TWI_INT_RXBUFF (1 << 14) /* Bit 14: RX Buffer */ +#define TWI_INT_TXBUFE (1 << 15) /* Bit 15: TX Buffer Empty */ + +/* TWI Receive Holding Register */ + +#define TWI_RHR_RXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Receive Holding Data */ +#define TWI_RHR_RXDATA_MASK (0xff << TWI_RHR_RXDATA_SHIFT) + +/* TWI Transmit Holding Register */ + +#define TWI_THR_TXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Transmit Holding Data */ +#define TWI_THR_TXDATA_MASK (0xff << TWI_THR_TXDATA_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_TWI_H */ diff --git a/arch/arm/src/sam3u/sam3u_uart.h b/arch/arm/src/sam3u/sam3u_uart.h index b784677946f659acf3fc559bdfb5e84dc3687ca5..1103cbfad5208db01029aa0d725177c4bf908f73 100644 --- a/arch/arm/src/sam3u/sam3u_uart.h +++ b/arch/arm/src/sam3u/sam3u_uart.h @@ -1,391 +1,391 @@ -/************************************************************************************************ - * arch/arm/src/sam3u/sam3u_uart.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_UART_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_UART_H - -/************************************************************************************************ - * Included Files - ************************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/************************************************************************************************ - * Pre-processor Definitions - ************************************************************************************************/ - -/* UART register offsets ************************************************************************/ - -#define SAM3U_UART_CR_OFFSET 0x0000 /* Control Register (Common) */ -#define SAM3U_UART_MR_OFFSET 0x0004 /* Mode Register (Common) */ -#define SAM3U_UART_IER_OFFSET 0x0008 /* Interrupt Enable Register (Common) */ -#define SAM3U_UART_IDR_OFFSET 0x000c /* Interrupt Disable Register (Common) */ -#define SAM3U_UART_IMR_OFFSET 0x0010 /* Interrupt Mask Register (Common) */ -#define SAM3U_UART_SR_OFFSET 0x0014 /* Status Register (Common) */ -#define SAM3U_UART_RHR_OFFSET 0x0018 /* Receive Holding Register (Common) */ -#define SAM3U_UART_THR_OFFSET 0x001c /* Transmit Holding Register (Common) */ -#define SAM3U_UART_BRGR_OFFSET 0x0020 /* Baud Rate Generator Register (Common) */ - /* 0x0024-0x003c: Reserved (UART) */ -#define SAM3U_USART_RTOR_OFFSET 0x0024 /* Receiver Time-out Register (USART only) */ -#define SAM3U_USART_TTGR_OFFSET 0x0028 /* Transmitter Timeguard Register (USART only) */ - /* 0x002c-0x003c: Reserved (UART) */ -#define SAM3U_USART_FIDI_OFFSET 0x0040 /* FI DI Ratio Register (USART only) */ -#define SAM3U_USART_NER_OFFSET 0x0044 /* Number of Errors Register ((USART only) */ - /* 0x0048: Reserved (USART) */ -#define SAM3U_USART_IF_OFFSET 0x004c /* IrDA Filter Register (USART only) */ -#define SAM3U_USART_MAN_OFFSET 0x0050 /* Manchester Encoder Decoder Register (USART only) */ -#define SAM3U_USART_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register (USART only) */ -#define SAM3U_USART_WPSR_OFFSET 0x00e8 /* Write Protect Status Register (USART only) */ - /* 0x005c-0xf008: Reserved (USART) */ -#define SAM3U_USART_VERSION_OFFSET 0x00fc /* Version Register (USART only) */ - /* 0x0100-0x0124: PDC Area (Common) */ - -/* UART register adresses ***********************************************************************/ - -#define SAM3U_UART_CR (SAM3U_UART_BASE+SAM3U_UART_CR_OFFSET) -#define SAM3U_UART_MR (SAM3U_UART_BASE+SAM3U_UART_MR_OFFSET) -#define SAM3U_UART_IER (SAM3U_UART_BASE+SAM3U_UART_IER_OFFSET) -#define SAM3U_UART_IDR (SAM3U_UART_BASE+SAM3U_UART_IDR_OFFSET) -#define SAM3U_UART_IMR (SAM3U_UART_BASE+SAM3U_UART_IMR_OFFSET) -#define SAM3U_UART_SR (SAM3U_UART_BASE+SAM3U_UART_SR_OFFSET) -#define SAM3U_UART_RHR (SAM3U_UART_BASE+SAM3U_UART_RHR_OFFSET) -#define SAM3U_UART_THR (SAM3U_UART_BASE+SAM3U_UART_THR_OFFSET) -#define SAM3U_UART_BRGR (SAM3U_UART_BASE+SAM3U_UART_BRGR_OFFSET) - -#define SAM3U_USART_CR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_CR_OFFSET) -#define SAM3U_USART_MR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_MR_OFFSET) -#define SAM3U_USART_IER(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_IER_OFFSET) -#define SAM3U_USART_IDR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_IDR_OFFSET) -#define SAM3U_USART_IMR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_IMR_OFFSET) -#define SAM3U_USART_SR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_SR_OFFSET) -#define SAM3U_USART_RHR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_RHR_OFFSET) -#define SAM3U_USART_THR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_THR_OFFSET) -#define SAM3U_USART_BRGR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_BRGR_OFFSET) -#define SAM3U_USART_RTOR(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_RTOR_OFFSET) -#define SAM3U_USART_TTGR(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_TTGR_OFFSET) -#define SAM3U_USART_FIDI(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_FIDI_OFFSET) -#define SAM3U_USART_NER(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_NER_OFFSET) -#define SAM3U_USART_IF(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_IF_OFFSET) -#define SAM3U_USART_MAN(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_MAN_OFFSET) -#define SAM3U_USART_WPMR(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_WPMR_OFFSET) -#define SAM3U_USART_WPSR(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_WPSR_OFFSET) -#define SAM3U_USART_VERSION(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_VERSION_OFFSET) - -#define SAM3U_USART0_CR (SAM3U_USART0_BASE+SAM3U_UART_CR_OFFSET) -#define SAM3U_USART0_MR_ (SAM3U_USART0_BASE+SAM3U_UART_MR_OFFSET) -#define SAM3U_USART0_IER (SAM3U_USART0_BASE+SAM3U_UART_IER_OFFSET) -#define SAM3U_USART0_IDR (SAM3U_USART0_BASE+SAM3U_UART_IDR_OFFSET) -#define SAM3U_USART0_IMR (SAM3U_USART0_BASE+SAM3U_UART_IMR_OFFSET) -#define SAM3U_USART0_SR (SAM3U_USART0_BASE+SAM3U_UART_SR_OFFSET) -#define SAM3U_USART0_RHR (SAM3U_USART0_BASE+SAM3U_UART_RHR_OFFSET) -#define SAM3U_USART0_THR (SAM3U_USART0_BASE+SAM3U_UART_THR_OFFSET) -#define SAM3U_USART0_BRGR (SAM3U_USART0_BASE+SAM3U_UART_BRGR_OFFSET) -#define SAM3U_USART0_RTOR (SAM3U_USART0_BASE+SAM3U_USART_RTOR_OFFSET) -#define SAM3U_USART0_TTGR (SAM3U_USART0_BASE+SAM3U_USART_TTGR_OFFSET) -#define SAM3U_USART0_FIDI (SAM3U_USART0_BASE+SAM3U_USART_FIDI_OFFSET) -#define SAM3U_USART0_NER (SAM3U_USART0_BASE+SAM3U_USART_NER_OFFSET) -#define SAM3U_USART0_IF (SAM3U_USART0_BASE+SAM3U_USART_IF_OFFSET) -#define SAM3U_USART0_MAN (SAM3U_USART0_BASE+SAM3U_USART_MAN_OFFSET) -#define SAM3U_USART0_WPMR (SAM3U_USART0_BASE+SAM3U_USART_WPMR_OFFSET) -#define SAM3U_USART0_WPSR (SAM3U_USART0_BASE+SAM3U_USART_WPSR_OFFSET) -#define SAM3U_USART0_VERSION (SAM3U_USART0_BASE+SAM3U_USART_VERSION_OFFSET) - -#define SAM3U_USART1_CR (SAM3U_USART1_BASE+SAM3U_UART_CR_OFFSET) -#define SAM3U_USART1_MR_ (SAM3U_USART1_BASE+SAM3U_UART_MR_OFFSET) -#define SAM3U_USART1_IER (SAM3U_USART1_BASE+SAM3U_UART_IER_OFFSET) -#define SAM3U_USART1_IDR (SAM3U_USART1_BASE+SAM3U_UART_IDR_OFFSET) -#define SAM3U_USART1_IMR (SAM3U_USART1_BASE+SAM3U_UART_IMR_OFFSET) -#define SAM3U_USART1_SR (SAM3U_USART1_BASE+SAM3U_UART_SR_OFFSET) -#define SAM3U_USART1_RHR (SAM3U_USART1_BASE+SAM3U_UART_RHR_OFFSET) -#define SAM3U_USART1_THR (SAM3U_USART1_BASE+SAM3U_UART_THR_OFFSET) -#define SAM3U_USART1_BRGR (SAM3U_USART1_BASE+SAM3U_UART_BRGR_OFFSET) -#define SAM3U_USART1_RTOR (SAM3U_USART1_BASE+SAM3U_USART_RTOR_OFFSET) -#define SAM3U_USART1_TTGR (SAM3U_USART1_BASE+SAM3U_USART_TTGR_OFFSET) -#define SAM3U_USART1_FIDI (SAM3U_USART1_BASE+SAM3U_USART_FIDI_OFFSET) -#define SAM3U_USART1_NER (SAM3U_USART1_BASE+SAM3U_USART_NER_OFFSET) -#define SAM3U_USART1_IF (SAM3U_USART1_BASE+SAM3U_USART_IF_OFFSET) -#define SAM3U_USART1_MAN (SAM3U_USART1_BASE+SAM3U_USART_MAN_OFFSET) -#define SAM3U_USART1_WPMR (SAM3U_USART1_BASE+SAM3U_USART_WPMR_OFFSET) -#define SAM3U_USART1_WPSR (SAM3U_USART1_BASE+SAM3U_USART_WPSR_OFFSET) -#define SAM3U_USART1_VERSION (SAM3U_USART1_BASE+SAM3U_USART_VERSION_OFFSET) - -#define SAM3U_USART2_CR (SAM3U_USART2_BASE+SAM3U_UART_CR_OFFSET) -#define SAM3U_USART2_MR_ (SAM3U_USART2_BASE+SAM3U_UART_MR_OFFSET) -#define SAM3U_USART2_IER (SAM3U_USART2_BASE+SAM3U_UART_IER_OFFSET) -#define SAM3U_USART2_IDR (SAM3U_USART2_BASE+SAM3U_UART_IDR_OFFSET) -#define SAM3U_USART2_IMR (SAM3U_USART2_BASE+SAM3U_UART_IMR_OFFSET) -#define SAM3U_USART2_SR (SAM3U_USART2_BASE+SAM3U_UART_SR_OFFSET) -#define SAM3U_USART2_RHR (SAM3U_USART2_BASE+SAM3U_UART_RHR_OFFSET) -#define SAM3U_USART2_THR (SAM3U_USART2_BASE+SAM3U_UART_THR_OFFSET) -#define SAM3U_USART2_BRGR (SAM3U_USART2_BASE+SAM3U_UART_BRGR_OFFSET) -#define SAM3U_USART2_RTOR (SAM3U_USART2_BASE+SAM3U_USART_RTOR_OFFSET) -#define SAM3U_USART2_TTGR (SAM3U_USART2_BASE+SAM3U_USART_TTGR_OFFSET) -#define SAM3U_USART2_FIDI (SAM3U_USART2_BASE+SAM3U_USART_FIDI_OFFSET) -#define SAM3U_USART2_NER (SAM3U_USART2_BASE+SAM3U_USART_NER_OFFSET) -#define SAM3U_USART2_IF (SAM3U_USART2_BASE+SAM3U_USART_IF_OFFSET) -#define SAM3U_USART2_MAN (SAM3U_USART2_BASE+SAM3U_USART_MAN_OFFSET) -#define SAM3U_USART2_WPMR (SAM3U_USART2_BASE+SAM3U_USART_WPMR_OFFSET) -#define SAM3U_USART2_WPSR (SAM3U_USART2_BASE+SAM3U_USART_WPSR_OFFSET) -#define SAM3U_USART2_VERSION (SAM3U_USART2_BASE+SAM3U_USART_VERSION_OFFSET) - -#define SAM3U_USART3_CR (SAM3U_USART3_BASE+SAM3U_UART_CR_OFFSET) -#define SAM3U_USART3_MR_ (SAM3U_USART3_BASE+SAM3U_UART_MR_OFFSET) -#define SAM3U_USART3_IER (SAM3U_USART3_BASE+SAM3U_UART_IER_OFFSET) -#define SAM3U_USART3_IDR (SAM3U_USART3_BASE+SAM3U_UART_IDR_OFFSET) -#define SAM3U_USART3_IMR (SAM3U_USART3_BASE+SAM3U_UART_IMR_OFFSET) -#define SAM3U_USART3_SR (SAM3U_USART3_BASE+SAM3U_UART_SR_OFFSET) -#define SAM3U_USART3_RHR (SAM3U_USART3_BASE+SAM3U_UART_RHR_OFFSET) -#define SAM3U_USART3_THR (SAM3U_USART3_BASE+SAM3U_UART_THR_OFFSET) -#define SAM3U_USART3_BRGR (SAM3U_USART3_BASE+SAM3U_UART_BRGR_OFFSET) -#define SAM3U_USART3_RTOR (SAM3U_USART3_BASE+SAM3U_USART_RTOR_OFFSET) -#define SAM3U_USART3_TTGR (SAM3U_USART3_BASE+SAM3U_USART_TTGR_OFFSET) -#define SAM3U_USART3_FIDI (SAM3U_USART3_BASE+SAM3U_USART_FIDI_OFFSET) -#define SAM3U_USART3_NER (SAM3U_USART3_BASE+SAM3U_USART_NER_OFFSET) -#define SAM3U_USART3_IF (SAM3U_USART3_BASE+SAM3U_USART_IF_OFFSET) -#define SAM3U_USART3_MAN (SAM3U_USART3_BASE+SAM3U_USART_MAN_OFFSET) -#define SAM3U_USART3_WPMR (SAM3U_USART3_BASE+SAM3U_USART_WPMR_OFFSET) -#define SAM3U_USART3_WPSR (SAM3U_USART3_BASE+SAM3U_USART_WPSR_OFFSET) -#define SAM3U_USART3_VERSION (SAM3U_USART3_BASE+SAM3U_USART_VERSION_OFFSET) - -/* UART register bit definitions ****************************************************************/ - -/* UART Control Register */ - -#define UART_CR_RSTRX (1 << 2) /* Bit 2: Reset Receiver (Common) */ -#define UART_CR_RSTTX (1 << 3) /* Bit 3: Reset Transmitter (Common) */ -#define UART_CR_RXEN (1 << 4) /* Bit 4: Receiver Enable (Common) */ -#define UART_CR_RXDIS (1 << 5) /* Bit 5: Receiver Disable (Common) */ -#define UART_CR_TXEN (1 << 6) /* Bit 6: Transmitter Enable (Common) */ -#define UART_CR_TXDIS (1 << 7) /* Bit 7: Transmitter Disable (Common) */ -#define UART_CR_RSTSTA (1 << 8) /* Bit 8: Reset Status Bits (Common) */ -#define USART_CR_STTBRK (1 << 9) /* Bit 9: Start Break (USART only) */ -#define USART_CR_STPBRK (1 << 10) /* Bit 10: Stop Break (USART only) */ -#define USART_CR_STTTO (1 << 11) /* Bit 11: Start Time-out (USART only) */ -#define USART_CR_SENDA (1 << 12) /* Bit 12: Send Address (USART only) */ -#define USART_CR_RSTIT (1 << 13) /* Bit 13: Reset Iterations (USART only) */ -#define USART_CR_RSTNACK (1 << 14) /* Bit 14: Reset Non Acknowledge (USART only) */ -#define USART_CR_RETTO (1 << 15) /* Bit 15: Rearm Time-out (USART only) */ -#define USART_CR_RTSEN (1 << 18) /* Bit 18: Request to Send Enable (USART only) */ -#define USART_CR_FCS (1 << 18) /* Bit 18: Force SPI Chip Select (USART only) */ -#define USART_CR_RTSDIS (1 << 19) /* Bit 19: Request to Send Disable (USART only) */ -#define USART_CR_RCS (1 << 19) /* Bit 19: Release SPI Chip Select (USART only) */ - -/* UART Mode Register */ - -#define USART_MR_MODE_SHIFT (0) /* Bits 0-3: (USART only) */ -#define USART_MR_MODE_MASK (15 << USART_MR_MODE_SHIFT) -# define USART_MR_MODE_NORMAL (0 << USART_MR_MODE_SHIFT) /* Normal */ -# define USART_MR_MODE_RS485 (1 << USART_MR_MODE_SHIFT) /* RS485 */ -# define USART_MR_MODE_HWHS (2 << USART_MR_MODE_SHIFT) /* Hardware Handshaking */ -# define USART_MR_MODE_ISO7816_0 (4 << USART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 0 */ -# define USART_MR_MODE_ISO7816_1 (6 << USART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 1 */ -# define USART_MR_MODE_IRDA (8 << USART_MR_MODE_SHIFT) /* IrDA */ -# define USART_MR_MODE_SPIMSTR (14 << USART_MR_MODE_SHIFT) /* SPI Master */ -# define USART_MR_MODE_SPISLV (15 << USART_MR_MODE_SHIFT) /* SPI Slave */ -#define USART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection (USART only) */ -#define USART_MR_USCLKS_MASK (3 << USART_MR_USCLKS_SHIFT) -# define USART_MR_USCLKS_MCK (0 << USART_MR_USCLKS_SHIFT) /* MCK */ -# define USART_MR_USCLKS_MCKDIV (1 << USART_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */ -# define USART_MR_USCLKS_SCK (3 << USART_MR_USCLKS_SHIFT) /* SCK */ -#define USART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length (USART only) */ -#define USART_MR_CHRL_MASK (3 << USART_MR_CHRL_SHIFT) -# define USART_MR_CHRL_5BITS (0 << USART_MR_CHRL_SHIFT) /* 5 bits */ -# define USART_MR_CHRL_6BITS (1 << USART_MR_CHRL_SHIFT) /* 6 bits */ -# define USART_MR_CHRL_7BITS (2 << USART_MR_CHRL_SHIFT) /* 7 bits */ -# define USART_MR_CHRL_8BITS (3 << USART_MR_CHRL_SHIFT) /* 8 bits */ -#define USART_MR_YNC (1 << 8) /* Bit 8: Synchronous Mode Select (USART only) */ -#define USART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase (USART only) */ -#define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type (Common) */ -#define UART_MR_PAR_MASK (7 << UART_MR_PAR_SHIFT) -# define UART_MR_PAR_EVEN (0 << UART_MR_PAR_SHIFT) /* Even parity (Common) */ -# define UART_MR_PAR_ODD (1 << UART_MR_PAR_SHIFT) /* Odd parity (Common) */ -# define UART_MR_PAR_SPACE (2 << UART_MR_PAR_SHIFT) /* Space: parity forced to 0 (Common) */ -# define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 (Common) */ -# define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity (Common) */ -# define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode (USART only) */ -#define USART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits (USART only) */ -#define USART_MR_NBSTOP_MASK (3 << USART_MR_NBSTOP_SHIFT) -# define USART_MR_NBSTOP_1 (0 << USART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */ -# define USART_MR_NBSTOP_1p5 (1 << USART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */ -# define USART_MR_NBSTOP_2 (2 << USART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */ -#define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode (Common) */ -#define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT) -# define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */ -# define UART_MR_CHMODE_ECHO (1 << UART_MR_CHMODE_SHIFT) /* Automatic Echo */ -# define UART_MR_CHMODE_LLPBK (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */ -# define UART_MR_CHMODE_RLPBK (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */ -#define USART_MR_MSBF (1 << 16) /* Bit 16: Bit Order or SPI Clock Polarity (USART only) */ -#define USART_MR_CPOL (1 << 16) -#define USART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length (USART only) */ -#define USART_MR_CLKO (1 << 18) /* Bit 18: Clock Output Select (USART only) */ -#define USART_MR_OVER (1 << 19) /* Bit 19: Oversampling Mode (USART only) */ -#define USART_MR_INACK (1 << 20) /* Bit 20: Inhibit Non Acknowledge (USART only) */ -#define USART_MR_DSNACK (1 << 21) /* Bit 21: Disable Successive NACK (USART only) */ -#define USART_MR_VARSYNC (1 << 22) /* Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter (USART only) */ -#define USART_MR_INVDATA (1 << 23) /* Bit 23: INverted Data (USART only) */ -#define USART_MR_MAXITER_SHIFT (24) /* Bits 24-26: Max iterations (ISO7816 T=0 (USART only) */ -#define USART_MR_MAXITER_MASK (7 << USART_MR_MAXITER_SHIFT) -#define USART_MR_FILTER (1 << 28) /* Bit 28: Infrared Receive Line Filter (USART only) */ -#define USART_MR_MAN (1 << 29) /* Bit 29: Manchester Encoder/Decoder Enable (USART only) */ -#define USART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode (USART only) */ -#define USART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector (USART only) */ - -/* UART Interrupt Enable Register, UART Interrupt Disable Register, UART Interrupt Mask - * Register, and UART Status Register common bit field definitions - */ - -#define UART_INT_RXRDY (1 << 0) /* Bit 0: RXRDY Interrupt (Common) */ -#define UART_INT_TXRDY (1 << 1) /* Bit 1: TXRDY Interrupt (Common) */ -#define UART_INT_RXBRK (1 << 2) /* Bit 2: Break Received/End of Break */ -#define UART_INT_ENDRX (1 << 3) /* Bit 3: End of Receive Transfer Interrupt (Common) */ -#define UART_INT_ENDTX (1 << 4) /* Bit 4: End of Transmit Interrupt (Common) */ -#define UART_INT_OVRE (1 << 5) /* Bit 5: Overrun Error Interrupt (Common) */ -#define UART_INT_FRAME (1 << 6) /* Bit 6: Framing Error Interrupt (Common) */ -#define UART_INT_PARE (1 << 7) /* Bit 7: Parity Error Interrupt (Common) */ -#define USART_INT_TIMEOUT (1 << 8) /* Bit 8: Time-out Interrupt (USART only) */ -#define UART_INT_TXEMPTY (1 << 9) /* Bit 9: TXEMPTY Interrupt (Common) */ -#define USART_INT_ITER (1 << 10) /* Bit 10: Iteration Interrupt (USART only) */ -#define USART_INT_UNRE (1 << 10) /* Bit 10: SPI Underrun Error Interrupt (USART only) */ -#define UART_INT_TXBUFE (1 << 11) /* Bit 11: Buffer Empty Interrupt (Common) */ -#define UART_INT_RXBUFF (1 << 12) /* Bit 12: Buffer Full Interrupt (Common) */ -#define USART_INT_NACK (1 << 13) /* Bit 13: Non Acknowledge Interrupt (USART only) */ -#define USART_INT_CTSIC (1 << 19) /* Bit 19: Clear to Send Input Change Interrupt (USART only) */ -#define USART_INT_MANE (1 << 24) /* Bit 24: Manchester Error Interrupt (USART only) */ - -/* UART Receiver Holding Register */ - -#define UART_RHR_RXCHR_SHIFT (0) /* Bits 0-7: Received Character (UART only) */ -#define UART_RHR_RXCHR_MASK (0xff << UART_RHR_RXCHR_SHIFT) -#define USART_RHR_RXCHR_SHIFT (0) /* Bits 0-8: Received Character (USART only) */ -#define USART_RHR_RXCHR_MASK (0x1ff << UART_RHR_RXCHR_SHIFT) -#define USART_RHR_RXSYNH (1 << 15) /* Bit 15: Received Sync (USART only) */ - -/* UART Transmit Holding Register */ - -#define UART_THR_TXCHR_SHIFT (0) /* Bits 0-7: Character to be Transmitted (UART only) */ -#define UART_THR_TXCHR_MASK (0xff << UART_THR_TXCHR_SHIFT) -#define USART_THR_TXCHR_SHIFT (0) /* Bits 0-8: Character to be Transmitted (USART only) */ -#define USART_THR_TXCHR_MASK (0x1ff << USART_THR_TXCHR_SHIFT) -#define USART_THR_TXSYNH (1 << 15) /* Bit 15: Sync Field to be tran (USART only) */ - -/* UART Baud Rate Generator Register */ - -#define UART_BRGR_CD_SHIFT (0) /* Bits 0-15: Clock Divisor (Common) */ -#define UART_BRGR_CD_MASK (0xffff << UART_BRGR_CD_SHIFT) -#define UART_BRGR_FP_SHIFT (16) /* Bits 16-18: Fractional Part (USART only) */ -#define UART_BRGR_FP_MASK (7 << UART_BRGR_FP_SHIFT) - -/* USART Receiver Time-out Register (USART only) */ - -#define USART_RTOR_TO_SHIFT (0) /* Bits 0-15: Time-out Value (USART only) */ -#define USART_RTOR_TO_MASK (0xffff << USART_RTOR_TO_SHIFT) - -/* USART Transmitter Timeguard Register (USART only) */ - -#define USART_TTGR_TG_SHIFT (0) /* Bits 0-7: Timeguard Value (USART only) */ -#define USART_TTGR_TG_MASK (0xff << USART_TTGR_TG_SHIFT) - -/* USART FI DI RATIO Register (USART only) */ - -#define USART_FIDI_RATIO_SHIFT (0) /* Bits 0-10: FI Over DI Ratio Value (USART only) */ -#define USART_FIDI_RATIO_MASK (0x7ff << USART_FIDI_RATIO_SHIFT) - -/* USART Number of Errors Register (USART only) */ - -#define USART_NER_NBERRORS_SHIFT (0) /* Bits 0-7: Number of Errrors (USART only) */ -#define USART_NER_NBERRORS_MASK (0xff << USART_NER_NBERRORS_SHIFT) - -/* USART IrDA FILTER Register (USART only) */ - -#define USART_IF_IRDAFILTER_SHIFT (0) /* Bits 0-7: IrDA Filter (USART only) */ -#define USART_IF_IRDAFILTER_MASK (0xff << USART_IF_IRDAFILTER_SHIFT) - -/* USART Manchester Configuration Register (USART only) */ - -#define USART_MAN_TXPL_SHIFT (0) /* Bits 0-3: Transmitter Preamble Length (USART only) */ -#define USART_MAN_TXPL_MASK (15 << USART_MAN_TXPL_SHIFT) -#define USART_MAN_TXPP_SHIFT (8) /* Bits 8-9: Transmitter Preamble Pattern (USART only) */ -#define USART_MAN_TXPP_MASK (3 << USART_MAN_TXPP_SHIFT) -# define USART_MAN_TXPP_ALLONE (0 << USART_MAN_TXPP_SHIFT) /* ALL_ONE */ -# define USART_MAN_TXPP_ALLZERO (1 << USART_MAN_TXPP_SHIFT) /* ALL_ZERO */ -# define USART_MAN_TXPP_ZEROONE (2 << USART_MAN_TXPP_SHIFT) /* ZERO_ONE */ -# define USART_MAN_TXPP_ONEZERO (3 << USART_MAN_TXPP_SHIFT) /* ONE_ZERO */ -#define USART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity (USART only) */ -#define USART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length (USART only) */ -#define USART_MAN_RXPL_MASK (15 << USART_MAN_RXPL_SHIFT) -#define USART_MAN_RXPP_SHIFT (24) /* Bits 24-25: Receiver Preamble Pattern detected (USART only) */ -#define USART_MAN_RXPP_MASK (3 << USART_MAN_RXPP_SHIFT) -# define USART_MAN_RXPP_ALLONE (0 << USART_MAN_RXPP_SHIFT) /* ALL_ONE */ -# define USART_MAN_RXPP_ALLZERO (1 << USART_MAN_RXPP_SHIFT) /* ALL_ZERO */ -# define USART_MAN_RXPP_ZEROONE (2 << USART_MAN_RXPP_SHIFT) /* ZERO_ONE */ -# define USART_MAN_RXPP_ONEZERO (3 << USART_MAN_RXPP_SHIFT) /* ONE_ZERO */ -#define USART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity (USART only) */ -#define USART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation (USART only) */ - -/* USART Write Protect Mode Register (USART only) */ - -#define USART_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable (USART only) */ -#define USART_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (USART only) */ -#define USART_WPMR_WPKEY_MASK (0x00ffffff << USART_WPMR_WPKEY_SHIFT) - -/* USART Write Protect Status Register (USART only) */ - -#define USART_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status (USART only) */ -#define USART_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source (USART only) */ -#define USART_WPSR_WPVSRC_MASK (0xffff << USART_WPSR_WPVSRC_SHIFT) - -/* USART Version Register */ - -#define USART_VERSION_VERSION_SHIFT (0) /* Bits 0-11: Macrocell version number (USART only) */ -#define USART_VERSION_VERSION_MASK (0xfff << USART_VERSION_VERSION_SHIFT) -#define USART_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved (USART only) */ -#define USART_VERSION_MFN_MASK (7 << USART_VERSION_MFN_SHIFT) - -/************************************************************************************************ - * Public Types - ************************************************************************************************/ - -/************************************************************************************************ - * Public Data - ************************************************************************************************/ - -/************************************************************************************************ - * Public Functions - ************************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_UART_H */ +/************************************************************************************************ + * arch/arm/src/sam3u/sam3u_uart.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_UART_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_UART_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* UART register offsets ************************************************************************/ + +#define SAM3U_UART_CR_OFFSET 0x0000 /* Control Register (Common) */ +#define SAM3U_UART_MR_OFFSET 0x0004 /* Mode Register (Common) */ +#define SAM3U_UART_IER_OFFSET 0x0008 /* Interrupt Enable Register (Common) */ +#define SAM3U_UART_IDR_OFFSET 0x000c /* Interrupt Disable Register (Common) */ +#define SAM3U_UART_IMR_OFFSET 0x0010 /* Interrupt Mask Register (Common) */ +#define SAM3U_UART_SR_OFFSET 0x0014 /* Status Register (Common) */ +#define SAM3U_UART_RHR_OFFSET 0x0018 /* Receive Holding Register (Common) */ +#define SAM3U_UART_THR_OFFSET 0x001c /* Transmit Holding Register (Common) */ +#define SAM3U_UART_BRGR_OFFSET 0x0020 /* Baud Rate Generator Register (Common) */ + /* 0x0024-0x003c: Reserved (UART) */ +#define SAM3U_USART_RTOR_OFFSET 0x0024 /* Receiver Time-out Register (USART only) */ +#define SAM3U_USART_TTGR_OFFSET 0x0028 /* Transmitter Timeguard Register (USART only) */ + /* 0x002c-0x003c: Reserved (UART) */ +#define SAM3U_USART_FIDI_OFFSET 0x0040 /* FI DI Ratio Register (USART only) */ +#define SAM3U_USART_NER_OFFSET 0x0044 /* Number of Errors Register ((USART only) */ + /* 0x0048: Reserved (USART) */ +#define SAM3U_USART_IF_OFFSET 0x004c /* IrDA Filter Register (USART only) */ +#define SAM3U_USART_MAN_OFFSET 0x0050 /* Manchester Encoder Decoder Register (USART only) */ +#define SAM3U_USART_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register (USART only) */ +#define SAM3U_USART_WPSR_OFFSET 0x00e8 /* Write Protect Status Register (USART only) */ + /* 0x005c-0xf008: Reserved (USART) */ +#define SAM3U_USART_VERSION_OFFSET 0x00fc /* Version Register (USART only) */ + /* 0x0100-0x0124: PDC Area (Common) */ + +/* UART register adresses ***********************************************************************/ + +#define SAM3U_UART_CR (SAM3U_UART_BASE+SAM3U_UART_CR_OFFSET) +#define SAM3U_UART_MR (SAM3U_UART_BASE+SAM3U_UART_MR_OFFSET) +#define SAM3U_UART_IER (SAM3U_UART_BASE+SAM3U_UART_IER_OFFSET) +#define SAM3U_UART_IDR (SAM3U_UART_BASE+SAM3U_UART_IDR_OFFSET) +#define SAM3U_UART_IMR (SAM3U_UART_BASE+SAM3U_UART_IMR_OFFSET) +#define SAM3U_UART_SR (SAM3U_UART_BASE+SAM3U_UART_SR_OFFSET) +#define SAM3U_UART_RHR (SAM3U_UART_BASE+SAM3U_UART_RHR_OFFSET) +#define SAM3U_UART_THR (SAM3U_UART_BASE+SAM3U_UART_THR_OFFSET) +#define SAM3U_UART_BRGR (SAM3U_UART_BASE+SAM3U_UART_BRGR_OFFSET) + +#define SAM3U_USART_CR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_CR_OFFSET) +#define SAM3U_USART_MR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_MR_OFFSET) +#define SAM3U_USART_IER(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_IER_OFFSET) +#define SAM3U_USART_IDR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_IDR_OFFSET) +#define SAM3U_USART_IMR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_IMR_OFFSET) +#define SAM3U_USART_SR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_SR_OFFSET) +#define SAM3U_USART_RHR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_RHR_OFFSET) +#define SAM3U_USART_THR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_THR_OFFSET) +#define SAM3U_USART_BRGR(n) (SAM3U_USARTN_BASE(n)+SAM3U_UART_BRGR_OFFSET) +#define SAM3U_USART_RTOR(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_RTOR_OFFSET) +#define SAM3U_USART_TTGR(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_TTGR_OFFSET) +#define SAM3U_USART_FIDI(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_FIDI_OFFSET) +#define SAM3U_USART_NER(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_NER_OFFSET) +#define SAM3U_USART_IF(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_IF_OFFSET) +#define SAM3U_USART_MAN(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_MAN_OFFSET) +#define SAM3U_USART_WPMR(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_WPMR_OFFSET) +#define SAM3U_USART_WPSR(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_WPSR_OFFSET) +#define SAM3U_USART_VERSION(n) (SAM3U_USARTN_BASE(n)+SAM3U_USART_VERSION_OFFSET) + +#define SAM3U_USART0_CR (SAM3U_USART0_BASE+SAM3U_UART_CR_OFFSET) +#define SAM3U_USART0_MR_ (SAM3U_USART0_BASE+SAM3U_UART_MR_OFFSET) +#define SAM3U_USART0_IER (SAM3U_USART0_BASE+SAM3U_UART_IER_OFFSET) +#define SAM3U_USART0_IDR (SAM3U_USART0_BASE+SAM3U_UART_IDR_OFFSET) +#define SAM3U_USART0_IMR (SAM3U_USART0_BASE+SAM3U_UART_IMR_OFFSET) +#define SAM3U_USART0_SR (SAM3U_USART0_BASE+SAM3U_UART_SR_OFFSET) +#define SAM3U_USART0_RHR (SAM3U_USART0_BASE+SAM3U_UART_RHR_OFFSET) +#define SAM3U_USART0_THR (SAM3U_USART0_BASE+SAM3U_UART_THR_OFFSET) +#define SAM3U_USART0_BRGR (SAM3U_USART0_BASE+SAM3U_UART_BRGR_OFFSET) +#define SAM3U_USART0_RTOR (SAM3U_USART0_BASE+SAM3U_USART_RTOR_OFFSET) +#define SAM3U_USART0_TTGR (SAM3U_USART0_BASE+SAM3U_USART_TTGR_OFFSET) +#define SAM3U_USART0_FIDI (SAM3U_USART0_BASE+SAM3U_USART_FIDI_OFFSET) +#define SAM3U_USART0_NER (SAM3U_USART0_BASE+SAM3U_USART_NER_OFFSET) +#define SAM3U_USART0_IF (SAM3U_USART0_BASE+SAM3U_USART_IF_OFFSET) +#define SAM3U_USART0_MAN (SAM3U_USART0_BASE+SAM3U_USART_MAN_OFFSET) +#define SAM3U_USART0_WPMR (SAM3U_USART0_BASE+SAM3U_USART_WPMR_OFFSET) +#define SAM3U_USART0_WPSR (SAM3U_USART0_BASE+SAM3U_USART_WPSR_OFFSET) +#define SAM3U_USART0_VERSION (SAM3U_USART0_BASE+SAM3U_USART_VERSION_OFFSET) + +#define SAM3U_USART1_CR (SAM3U_USART1_BASE+SAM3U_UART_CR_OFFSET) +#define SAM3U_USART1_MR_ (SAM3U_USART1_BASE+SAM3U_UART_MR_OFFSET) +#define SAM3U_USART1_IER (SAM3U_USART1_BASE+SAM3U_UART_IER_OFFSET) +#define SAM3U_USART1_IDR (SAM3U_USART1_BASE+SAM3U_UART_IDR_OFFSET) +#define SAM3U_USART1_IMR (SAM3U_USART1_BASE+SAM3U_UART_IMR_OFFSET) +#define SAM3U_USART1_SR (SAM3U_USART1_BASE+SAM3U_UART_SR_OFFSET) +#define SAM3U_USART1_RHR (SAM3U_USART1_BASE+SAM3U_UART_RHR_OFFSET) +#define SAM3U_USART1_THR (SAM3U_USART1_BASE+SAM3U_UART_THR_OFFSET) +#define SAM3U_USART1_BRGR (SAM3U_USART1_BASE+SAM3U_UART_BRGR_OFFSET) +#define SAM3U_USART1_RTOR (SAM3U_USART1_BASE+SAM3U_USART_RTOR_OFFSET) +#define SAM3U_USART1_TTGR (SAM3U_USART1_BASE+SAM3U_USART_TTGR_OFFSET) +#define SAM3U_USART1_FIDI (SAM3U_USART1_BASE+SAM3U_USART_FIDI_OFFSET) +#define SAM3U_USART1_NER (SAM3U_USART1_BASE+SAM3U_USART_NER_OFFSET) +#define SAM3U_USART1_IF (SAM3U_USART1_BASE+SAM3U_USART_IF_OFFSET) +#define SAM3U_USART1_MAN (SAM3U_USART1_BASE+SAM3U_USART_MAN_OFFSET) +#define SAM3U_USART1_WPMR (SAM3U_USART1_BASE+SAM3U_USART_WPMR_OFFSET) +#define SAM3U_USART1_WPSR (SAM3U_USART1_BASE+SAM3U_USART_WPSR_OFFSET) +#define SAM3U_USART1_VERSION (SAM3U_USART1_BASE+SAM3U_USART_VERSION_OFFSET) + +#define SAM3U_USART2_CR (SAM3U_USART2_BASE+SAM3U_UART_CR_OFFSET) +#define SAM3U_USART2_MR_ (SAM3U_USART2_BASE+SAM3U_UART_MR_OFFSET) +#define SAM3U_USART2_IER (SAM3U_USART2_BASE+SAM3U_UART_IER_OFFSET) +#define SAM3U_USART2_IDR (SAM3U_USART2_BASE+SAM3U_UART_IDR_OFFSET) +#define SAM3U_USART2_IMR (SAM3U_USART2_BASE+SAM3U_UART_IMR_OFFSET) +#define SAM3U_USART2_SR (SAM3U_USART2_BASE+SAM3U_UART_SR_OFFSET) +#define SAM3U_USART2_RHR (SAM3U_USART2_BASE+SAM3U_UART_RHR_OFFSET) +#define SAM3U_USART2_THR (SAM3U_USART2_BASE+SAM3U_UART_THR_OFFSET) +#define SAM3U_USART2_BRGR (SAM3U_USART2_BASE+SAM3U_UART_BRGR_OFFSET) +#define SAM3U_USART2_RTOR (SAM3U_USART2_BASE+SAM3U_USART_RTOR_OFFSET) +#define SAM3U_USART2_TTGR (SAM3U_USART2_BASE+SAM3U_USART_TTGR_OFFSET) +#define SAM3U_USART2_FIDI (SAM3U_USART2_BASE+SAM3U_USART_FIDI_OFFSET) +#define SAM3U_USART2_NER (SAM3U_USART2_BASE+SAM3U_USART_NER_OFFSET) +#define SAM3U_USART2_IF (SAM3U_USART2_BASE+SAM3U_USART_IF_OFFSET) +#define SAM3U_USART2_MAN (SAM3U_USART2_BASE+SAM3U_USART_MAN_OFFSET) +#define SAM3U_USART2_WPMR (SAM3U_USART2_BASE+SAM3U_USART_WPMR_OFFSET) +#define SAM3U_USART2_WPSR (SAM3U_USART2_BASE+SAM3U_USART_WPSR_OFFSET) +#define SAM3U_USART2_VERSION (SAM3U_USART2_BASE+SAM3U_USART_VERSION_OFFSET) + +#define SAM3U_USART3_CR (SAM3U_USART3_BASE+SAM3U_UART_CR_OFFSET) +#define SAM3U_USART3_MR_ (SAM3U_USART3_BASE+SAM3U_UART_MR_OFFSET) +#define SAM3U_USART3_IER (SAM3U_USART3_BASE+SAM3U_UART_IER_OFFSET) +#define SAM3U_USART3_IDR (SAM3U_USART3_BASE+SAM3U_UART_IDR_OFFSET) +#define SAM3U_USART3_IMR (SAM3U_USART3_BASE+SAM3U_UART_IMR_OFFSET) +#define SAM3U_USART3_SR (SAM3U_USART3_BASE+SAM3U_UART_SR_OFFSET) +#define SAM3U_USART3_RHR (SAM3U_USART3_BASE+SAM3U_UART_RHR_OFFSET) +#define SAM3U_USART3_THR (SAM3U_USART3_BASE+SAM3U_UART_THR_OFFSET) +#define SAM3U_USART3_BRGR (SAM3U_USART3_BASE+SAM3U_UART_BRGR_OFFSET) +#define SAM3U_USART3_RTOR (SAM3U_USART3_BASE+SAM3U_USART_RTOR_OFFSET) +#define SAM3U_USART3_TTGR (SAM3U_USART3_BASE+SAM3U_USART_TTGR_OFFSET) +#define SAM3U_USART3_FIDI (SAM3U_USART3_BASE+SAM3U_USART_FIDI_OFFSET) +#define SAM3U_USART3_NER (SAM3U_USART3_BASE+SAM3U_USART_NER_OFFSET) +#define SAM3U_USART3_IF (SAM3U_USART3_BASE+SAM3U_USART_IF_OFFSET) +#define SAM3U_USART3_MAN (SAM3U_USART3_BASE+SAM3U_USART_MAN_OFFSET) +#define SAM3U_USART3_WPMR (SAM3U_USART3_BASE+SAM3U_USART_WPMR_OFFSET) +#define SAM3U_USART3_WPSR (SAM3U_USART3_BASE+SAM3U_USART_WPSR_OFFSET) +#define SAM3U_USART3_VERSION (SAM3U_USART3_BASE+SAM3U_USART_VERSION_OFFSET) + +/* UART register bit definitions ****************************************************************/ + +/* UART Control Register */ + +#define UART_CR_RSTRX (1 << 2) /* Bit 2: Reset Receiver (Common) */ +#define UART_CR_RSTTX (1 << 3) /* Bit 3: Reset Transmitter (Common) */ +#define UART_CR_RXEN (1 << 4) /* Bit 4: Receiver Enable (Common) */ +#define UART_CR_RXDIS (1 << 5) /* Bit 5: Receiver Disable (Common) */ +#define UART_CR_TXEN (1 << 6) /* Bit 6: Transmitter Enable (Common) */ +#define UART_CR_TXDIS (1 << 7) /* Bit 7: Transmitter Disable (Common) */ +#define UART_CR_RSTSTA (1 << 8) /* Bit 8: Reset Status Bits (Common) */ +#define USART_CR_STTBRK (1 << 9) /* Bit 9: Start Break (USART only) */ +#define USART_CR_STPBRK (1 << 10) /* Bit 10: Stop Break (USART only) */ +#define USART_CR_STTTO (1 << 11) /* Bit 11: Start Time-out (USART only) */ +#define USART_CR_SENDA (1 << 12) /* Bit 12: Send Address (USART only) */ +#define USART_CR_RSTIT (1 << 13) /* Bit 13: Reset Iterations (USART only) */ +#define USART_CR_RSTNACK (1 << 14) /* Bit 14: Reset Non Acknowledge (USART only) */ +#define USART_CR_RETTO (1 << 15) /* Bit 15: Rearm Time-out (USART only) */ +#define USART_CR_RTSEN (1 << 18) /* Bit 18: Request to Send Enable (USART only) */ +#define USART_CR_FCS (1 << 18) /* Bit 18: Force SPI Chip Select (USART only) */ +#define USART_CR_RTSDIS (1 << 19) /* Bit 19: Request to Send Disable (USART only) */ +#define USART_CR_RCS (1 << 19) /* Bit 19: Release SPI Chip Select (USART only) */ + +/* UART Mode Register */ + +#define USART_MR_MODE_SHIFT (0) /* Bits 0-3: (USART only) */ +#define USART_MR_MODE_MASK (15 << USART_MR_MODE_SHIFT) +# define USART_MR_MODE_NORMAL (0 << USART_MR_MODE_SHIFT) /* Normal */ +# define USART_MR_MODE_RS485 (1 << USART_MR_MODE_SHIFT) /* RS485 */ +# define USART_MR_MODE_HWHS (2 << USART_MR_MODE_SHIFT) /* Hardware Handshaking */ +# define USART_MR_MODE_ISO7816_0 (4 << USART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 0 */ +# define USART_MR_MODE_ISO7816_1 (6 << USART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 1 */ +# define USART_MR_MODE_IRDA (8 << USART_MR_MODE_SHIFT) /* IrDA */ +# define USART_MR_MODE_SPIMSTR (14 << USART_MR_MODE_SHIFT) /* SPI Master */ +# define USART_MR_MODE_SPISLV (15 << USART_MR_MODE_SHIFT) /* SPI Slave */ +#define USART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection (USART only) */ +#define USART_MR_USCLKS_MASK (3 << USART_MR_USCLKS_SHIFT) +# define USART_MR_USCLKS_MCK (0 << USART_MR_USCLKS_SHIFT) /* MCK */ +# define USART_MR_USCLKS_MCKDIV (1 << USART_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */ +# define USART_MR_USCLKS_SCK (3 << USART_MR_USCLKS_SHIFT) /* SCK */ +#define USART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length (USART only) */ +#define USART_MR_CHRL_MASK (3 << USART_MR_CHRL_SHIFT) +# define USART_MR_CHRL_5BITS (0 << USART_MR_CHRL_SHIFT) /* 5 bits */ +# define USART_MR_CHRL_6BITS (1 << USART_MR_CHRL_SHIFT) /* 6 bits */ +# define USART_MR_CHRL_7BITS (2 << USART_MR_CHRL_SHIFT) /* 7 bits */ +# define USART_MR_CHRL_8BITS (3 << USART_MR_CHRL_SHIFT) /* 8 bits */ +#define USART_MR_YNC (1 << 8) /* Bit 8: Synchronous Mode Select (USART only) */ +#define USART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase (USART only) */ +#define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type (Common) */ +#define UART_MR_PAR_MASK (7 << UART_MR_PAR_SHIFT) +# define UART_MR_PAR_EVEN (0 << UART_MR_PAR_SHIFT) /* Even parity (Common) */ +# define UART_MR_PAR_ODD (1 << UART_MR_PAR_SHIFT) /* Odd parity (Common) */ +# define UART_MR_PAR_SPACE (2 << UART_MR_PAR_SHIFT) /* Space: parity forced to 0 (Common) */ +# define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 (Common) */ +# define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity (Common) */ +# define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode (USART only) */ +#define USART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits (USART only) */ +#define USART_MR_NBSTOP_MASK (3 << USART_MR_NBSTOP_SHIFT) +# define USART_MR_NBSTOP_1 (0 << USART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */ +# define USART_MR_NBSTOP_1p5 (1 << USART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */ +# define USART_MR_NBSTOP_2 (2 << USART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */ +#define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode (Common) */ +#define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT) +# define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */ +# define UART_MR_CHMODE_ECHO (1 << UART_MR_CHMODE_SHIFT) /* Automatic Echo */ +# define UART_MR_CHMODE_LLPBK (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */ +# define UART_MR_CHMODE_RLPBK (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */ +#define USART_MR_MSBF (1 << 16) /* Bit 16: Bit Order or SPI Clock Polarity (USART only) */ +#define USART_MR_CPOL (1 << 16) +#define USART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length (USART only) */ +#define USART_MR_CLKO (1 << 18) /* Bit 18: Clock Output Select (USART only) */ +#define USART_MR_OVER (1 << 19) /* Bit 19: Oversampling Mode (USART only) */ +#define USART_MR_INACK (1 << 20) /* Bit 20: Inhibit Non Acknowledge (USART only) */ +#define USART_MR_DSNACK (1 << 21) /* Bit 21: Disable Successive NACK (USART only) */ +#define USART_MR_VARSYNC (1 << 22) /* Bit 22: Variable Synchronization of Command/Data Sync Start Frame Delimiter (USART only) */ +#define USART_MR_INVDATA (1 << 23) /* Bit 23: INverted Data (USART only) */ +#define USART_MR_MAXITER_SHIFT (24) /* Bits 24-26: Max iterations (ISO7816 T=0 (USART only) */ +#define USART_MR_MAXITER_MASK (7 << USART_MR_MAXITER_SHIFT) +#define USART_MR_FILTER (1 << 28) /* Bit 28: Infrared Receive Line Filter (USART only) */ +#define USART_MR_MAN (1 << 29) /* Bit 29: Manchester Encoder/Decoder Enable (USART only) */ +#define USART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode (USART only) */ +#define USART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector (USART only) */ + +/* UART Interrupt Enable Register, UART Interrupt Disable Register, UART Interrupt Mask + * Register, and UART Status Register common bit field definitions + */ + +#define UART_INT_RXRDY (1 << 0) /* Bit 0: RXRDY Interrupt (Common) */ +#define UART_INT_TXRDY (1 << 1) /* Bit 1: TXRDY Interrupt (Common) */ +#define UART_INT_RXBRK (1 << 2) /* Bit 2: Break Received/End of Break */ +#define UART_INT_ENDRX (1 << 3) /* Bit 3: End of Receive Transfer Interrupt (Common) */ +#define UART_INT_ENDTX (1 << 4) /* Bit 4: End of Transmit Interrupt (Common) */ +#define UART_INT_OVRE (1 << 5) /* Bit 5: Overrun Error Interrupt (Common) */ +#define UART_INT_FRAME (1 << 6) /* Bit 6: Framing Error Interrupt (Common) */ +#define UART_INT_PARE (1 << 7) /* Bit 7: Parity Error Interrupt (Common) */ +#define USART_INT_TIMEOUT (1 << 8) /* Bit 8: Time-out Interrupt (USART only) */ +#define UART_INT_TXEMPTY (1 << 9) /* Bit 9: TXEMPTY Interrupt (Common) */ +#define USART_INT_ITER (1 << 10) /* Bit 10: Iteration Interrupt (USART only) */ +#define USART_INT_UNRE (1 << 10) /* Bit 10: SPI Underrun Error Interrupt (USART only) */ +#define UART_INT_TXBUFE (1 << 11) /* Bit 11: Buffer Empty Interrupt (Common) */ +#define UART_INT_RXBUFF (1 << 12) /* Bit 12: Buffer Full Interrupt (Common) */ +#define USART_INT_NACK (1 << 13) /* Bit 13: Non Acknowledge Interrupt (USART only) */ +#define USART_INT_CTSIC (1 << 19) /* Bit 19: Clear to Send Input Change Interrupt (USART only) */ +#define USART_INT_MANE (1 << 24) /* Bit 24: Manchester Error Interrupt (USART only) */ + +/* UART Receiver Holding Register */ + +#define UART_RHR_RXCHR_SHIFT (0) /* Bits 0-7: Received Character (UART only) */ +#define UART_RHR_RXCHR_MASK (0xff << UART_RHR_RXCHR_SHIFT) +#define USART_RHR_RXCHR_SHIFT (0) /* Bits 0-8: Received Character (USART only) */ +#define USART_RHR_RXCHR_MASK (0x1ff << UART_RHR_RXCHR_SHIFT) +#define USART_RHR_RXSYNH (1 << 15) /* Bit 15: Received Sync (USART only) */ + +/* UART Transmit Holding Register */ + +#define UART_THR_TXCHR_SHIFT (0) /* Bits 0-7: Character to be Transmitted (UART only) */ +#define UART_THR_TXCHR_MASK (0xff << UART_THR_TXCHR_SHIFT) +#define USART_THR_TXCHR_SHIFT (0) /* Bits 0-8: Character to be Transmitted (USART only) */ +#define USART_THR_TXCHR_MASK (0x1ff << USART_THR_TXCHR_SHIFT) +#define USART_THR_TXSYNH (1 << 15) /* Bit 15: Sync Field to be tran (USART only) */ + +/* UART Baud Rate Generator Register */ + +#define UART_BRGR_CD_SHIFT (0) /* Bits 0-15: Clock Divisor (Common) */ +#define UART_BRGR_CD_MASK (0xffff << UART_BRGR_CD_SHIFT) +#define UART_BRGR_FP_SHIFT (16) /* Bits 16-18: Fractional Part (USART only) */ +#define UART_BRGR_FP_MASK (7 << UART_BRGR_FP_SHIFT) + +/* USART Receiver Time-out Register (USART only) */ + +#define USART_RTOR_TO_SHIFT (0) /* Bits 0-15: Time-out Value (USART only) */ +#define USART_RTOR_TO_MASK (0xffff << USART_RTOR_TO_SHIFT) + +/* USART Transmitter Timeguard Register (USART only) */ + +#define USART_TTGR_TG_SHIFT (0) /* Bits 0-7: Timeguard Value (USART only) */ +#define USART_TTGR_TG_MASK (0xff << USART_TTGR_TG_SHIFT) + +/* USART FI DI RATIO Register (USART only) */ + +#define USART_FIDI_RATIO_SHIFT (0) /* Bits 0-10: FI Over DI Ratio Value (USART only) */ +#define USART_FIDI_RATIO_MASK (0x7ff << USART_FIDI_RATIO_SHIFT) + +/* USART Number of Errors Register (USART only) */ + +#define USART_NER_NBERRORS_SHIFT (0) /* Bits 0-7: Number of Errrors (USART only) */ +#define USART_NER_NBERRORS_MASK (0xff << USART_NER_NBERRORS_SHIFT) + +/* USART IrDA FILTER Register (USART only) */ + +#define USART_IF_IRDAFILTER_SHIFT (0) /* Bits 0-7: IrDA Filter (USART only) */ +#define USART_IF_IRDAFILTER_MASK (0xff << USART_IF_IRDAFILTER_SHIFT) + +/* USART Manchester Configuration Register (USART only) */ + +#define USART_MAN_TXPL_SHIFT (0) /* Bits 0-3: Transmitter Preamble Length (USART only) */ +#define USART_MAN_TXPL_MASK (15 << USART_MAN_TXPL_SHIFT) +#define USART_MAN_TXPP_SHIFT (8) /* Bits 8-9: Transmitter Preamble Pattern (USART only) */ +#define USART_MAN_TXPP_MASK (3 << USART_MAN_TXPP_SHIFT) +# define USART_MAN_TXPP_ALLONE (0 << USART_MAN_TXPP_SHIFT) /* ALL_ONE */ +# define USART_MAN_TXPP_ALLZERO (1 << USART_MAN_TXPP_SHIFT) /* ALL_ZERO */ +# define USART_MAN_TXPP_ZEROONE (2 << USART_MAN_TXPP_SHIFT) /* ZERO_ONE */ +# define USART_MAN_TXPP_ONEZERO (3 << USART_MAN_TXPP_SHIFT) /* ONE_ZERO */ +#define USART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity (USART only) */ +#define USART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length (USART only) */ +#define USART_MAN_RXPL_MASK (15 << USART_MAN_RXPL_SHIFT) +#define USART_MAN_RXPP_SHIFT (24) /* Bits 24-25: Receiver Preamble Pattern detected (USART only) */ +#define USART_MAN_RXPP_MASK (3 << USART_MAN_RXPP_SHIFT) +# define USART_MAN_RXPP_ALLONE (0 << USART_MAN_RXPP_SHIFT) /* ALL_ONE */ +# define USART_MAN_RXPP_ALLZERO (1 << USART_MAN_RXPP_SHIFT) /* ALL_ZERO */ +# define USART_MAN_RXPP_ZEROONE (2 << USART_MAN_RXPP_SHIFT) /* ZERO_ONE */ +# define USART_MAN_RXPP_ONEZERO (3 << USART_MAN_RXPP_SHIFT) /* ONE_ZERO */ +#define USART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity (USART only) */ +#define USART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation (USART only) */ + +/* USART Write Protect Mode Register (USART only) */ + +#define USART_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable (USART only) */ +#define USART_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (USART only) */ +#define USART_WPMR_WPKEY_MASK (0x00ffffff << USART_WPMR_WPKEY_SHIFT) + +/* USART Write Protect Status Register (USART only) */ + +#define USART_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status (USART only) */ +#define USART_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source (USART only) */ +#define USART_WPSR_WPVSRC_MASK (0xffff << USART_WPSR_WPVSRC_SHIFT) + +/* USART Version Register */ + +#define USART_VERSION_VERSION_SHIFT (0) /* Bits 0-11: Macrocell version number (USART only) */ +#define USART_VERSION_VERSION_MASK (0xfff << USART_VERSION_VERSION_SHIFT) +#define USART_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved (USART only) */ +#define USART_VERSION_MFN_MASK (7 << USART_VERSION_MFN_SHIFT) + +/************************************************************************************************ + * Public Types + ************************************************************************************************/ + +/************************************************************************************************ + * Public Data + ************************************************************************************************/ + +/************************************************************************************************ + * Public Functions + ************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_UART_H */ diff --git a/arch/arm/src/sam3u/sam3u_udphs.h b/arch/arm/src/sam3u/sam3u_udphs.h index 1ce901e1d9d5b0106c5501c420095d626350a5fc..e6eb88c7793cca8f5d72e3e5bb5c852e2bd3839b 100644 --- a/arch/arm/src/sam3u/sam3u_udphs.h +++ b/arch/arm/src/sam3u/sam3u_udphs.h @@ -1,370 +1,371 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_udphs.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* UDPHS register offsets ***************************************************************/ - -#define SAM3U_UDPHS_CTRL_OFFSET 0x00 /* UDPHS Control Register */ -#define SAM3U_UDPHS_FNUM_OFFSET 0x04 /* UDPHS Frame Number Register */ - /* 0x08-0x0C: Reserved */ -#define SAM3U_UDPHS_IEN_OFFSET 0x10 /* UDPHS Interrupt Enable Register */ -#define SAM3U_UDPHS_INTSTA_OFFSET 0x14 /* UDPHS Interrupt Status Register */ -#define SAM3U_UDPHS_CLRINT_OFFSET 0x18 /* UDPHS Clear Interrupt Register */ -#define SAM3U_UDPHS_EPTRST_OFFSET 0x1c /* UDPHS Endpoints Reset Register */ - /* 0x20-0xcc: Reserved */ -#define SAM3U_UDPHS_TST_OFFSET 0xe0 /* UDPHS Test Register */ - /* 0xE4-0xE8: Reserved */ -#define SAM3U_UDPHS_IPNAME1_OFFSET 0xf0 /* UDPHS Name1 Register */ -#define SAM3U_UDPHS_IPNAME2_OFFSET 0xf4 /* UDPHS Name2 Register */ -#define SAM3U_UDPHS_IPFEATURES_OFFSET 0xf8 /* UDPHS Features Register */ - -/* Endpoint registers: Offsets for Endpoints 0-6: 0x100, 0x120, 0x140, 0x160, 0x180, - * 0x1a0, and 0x1c0 - */ - -#define SAM3U_UDPHSEP_OFFSET(n) (0x100+((n)<<5)) -#define SAM3U_UDPHSEP_CFG_OFFSET 0x00 /* UDPHS Endpoint Configuration Register */ -#define SAM3U_UDPHSEP_CTLENB_OFFSET 0x04 /* UDPHS Endpoint Control Enable Register */ -#define SAM3U_UDPHSEP_CTLDIS_OFFSET 0x08 /* UDPHS Endpoint Control Disable Register */ -#define SAM3U_UDPHSEP_CTL_OFFSET 0x0c /* UDPHS Endpoint Control Register */ - /* 0x10: Reserved */ -#define SAM3U_UDPHSEP_SETSTA_OFFSET 0x14 /* UDPHS Endpoint Set Status Register */ -#define SAM3U_UDPHSEP_CLRSTA_OFFSET 0x18 /* UDPHS Endpoint Clear Status Register */ -#define SAM3U_UDPHSEP_STA_OFFSET 0x1c /* UDPHS Endpoint Status Register */ - /* 0x1e0-0x300: Reserved */ - /* 0x300-0x30c: Reserved */ -/* DMA Channel Registers: Offsets for DMA channels 1-6 0x320, 0x330, 0x340, 0x350, and - * 0x360. NOTE that there is no DMA channel 0. - */ - -#define SAM3U_UDPHSDMA_OFFSET(n) (0x310+((n)<<4)) -#define SAM3U_UDPHSDMA_NXTDSC_OFFSET 0x00 /* UDPHS DMA Next Descriptor Address Register */ -#define SAM3U_UDPHSDMA_ADDRESS_OFFSET 0x04 /* UDPHS DMA Channel Address Register */ -#define SAM3U_UDPHSDMA_CONTROL_OFFSET 0x08 /* UDPHS DMA Channel Control Register */ -#define SAM3U_UDPHSDMA_STATUS_OFFSET) 0x0c /* UDPHS DMA Channel Status Register */ - -/* UDPHS register adresses **************************************************************/ - -#define SAM3U_UDPHS_CTRL (SAM3U_UDPHS_BASE+SAM3U_UDPHS_CTRL_OFFSET) -#define SAM3U_UDPHS_FNUM (SAM3U_UDPHS_BASE+SAM3U_UDPHS_FNUM_OFFSET) -#define SAM3U_UDPHS_IEN (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IEN_OFFSET) -#define SAM3U_UDPHS_INTSTA (SAM3U_UDPHS_BASE+SAM3U_UDPHS_INTSTA_OFFSET) -#define SAM3U_UDPHS_CLRINT (SAM3U_UDPHS_BASE+ SAM3U_UDPHS_CLRINT_OFFSET) -#define SAM3U_UDPHS_EPTRST (SAM3U_UDPHS_BASE+SAM3U_UDPHS_EPTRST_OFFSET) -#define SAM3U_UDPHS_TST (SAM3U_UDPHS_BASE+SAM3U_UDPHS_TST_OFFSET) -#define SAM3U_UDPHS_IPNAME1 (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPNAME1_OFFSET) -#define SAM3U_UDPHS_IPNAME2 (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPNAME2_OFFSET) -#define SAM3U_UDPHS_IPFEATURES (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPFEATURES_OFFSET) - -/* Endpoint registers */ - -#define SAM3U_UDPHSEP_BASE(n)) (SAM3U_UDPHS_BASE+SAM3U_UDPHSEP_OFFSET(n)) -#define SAM3U_UDPHSEP_CFG(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CFG_OFFSET) -#define SAM3U_UDPHSEP_CTLENB(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTLENB_OFFSET) -#define SAM3U_UDPHSEP_CTLDIS(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTLDIS_OFFSET) -#define SAM3U_UDPHSEP_CTL(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTL_OFFSET) -#define SAM3U_UDPHSEP_SETSTA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_SETSTA_OFFSET) -#define SAM3U_UDPHSEP_CLRSTA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CLRSTA_OFFSET) -#define SAM3U_UDPHSEP_STA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_STA_OFFSET) - -/* DMA Channel Registers*/ - -#define SAM3U_UDPHSDMA_BASE(n) (SAM3U_UDPHS_BASE+SAM3U_UDPHSDMA_OFFSET(n)) -#define SAM3U_UDPHSDMA_NXTDSC(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_NXTDSC_OFFSET) -#define SAM3U_UDPHSDMA_ADDRESS(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_ADDRESS_OFFSET) -#define SAM3U_UDPHSDMA_CONTROL(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_CONTROL_OFFSET) -#define SAM3U_UDPHSDMA_STATUS(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_STATUS_OFFSET) - -/* UDPHS register bit definitions *******************************************************/ -/* UDPHS Control Register */ - -#define UDPHS_CTRL_DEVADDR_SHIFT (0) /* Bits 0-6: UDPHS Address */ -#define UDPHS_CTRL_DEVADDR_MASK (0x7f << UDPHS_CTRL_DEVADDR_SHIFT) -#define UDPHS_CTRL_FADDREN (1 << 7) /* Bit 7: Function Address Enable */ -#define UDPHS_CTRL_ENUDPHS (1 << 8) /* Bit 8: UDPHS Enable */ -#define UDPHS_CTRL_DETACH (1 << 9) /* Bit 9: Detach Command */ -#define UDPHS_CTRL_REWAKEUP (1 << 10) /* Bit 10: Send Remote Wake Up */ -#define UDPHS_CTRL_PULLDDIS (1 << 11) /* Bit 11: Pull-Down Disable */ - -/* UDPHS Frame Number Register */ - -#define UDPHS_FNUM_MICROFRAMENUM_SHIFT (0) /* Bits 0-2: Microframe Num */ -#define UDPHS_FNUM_MICROFRAMENUM_MASK (7 << UDPHS_FNUM_MICROFRAMENUM_SHIFT) -#define UDPHS_FNUM_FRAMENUMBER_SHIFT (3) /* Bits 3-7: Frame Number in Packet Field Formats */ -#define UDPHS_FNUM_FRAMENUMBER_MASK (31 << UDPHS_FNUM_FRAMENUMBER_SHIFT) -#define UDPHS_FNUM_FNUMERR_SHIFT (8) /* Bits 8-13: Frame Number CRC Error */ -#define UDPHS_FNUM_FNUMERR_MASK (63 << UDPHS_FNUM_FNUMERR_SHIFT) - -/* UDPHS Interrupt Enable Register, UDPHS Interrupt Status Register, and UDPHS Clear - * Interrupt Register common bit-field definitions - */ - -#define USBPHS_INT_DETSUSPD (1 << 1) /* Bit 1: Suspend Interrupt (Common) */ -#define USBPHS_INT_MICROSOF (1 << 2) /* Bit 2: Micro-SOF Interrupt (Common) */ -#define USBPHS_INT_INTSOF (1 << 3) /* Bit 3: SOF Interrupt (Common) */ -#define USBPHS_INT_ENDRESET (1 << 4) /* Bit 4: End Of Reset Interrupt (Common) */ -#define USBPHS_INT_WAKEUP (1 << 5) /* Bit 5: Wake Up CPU Interrupt (Common) */ -#define USBPHS_INT_ENDOFRSM (1 << 6) /* Bit 6: End Of Resume Interrupt (Common) */ -#define USBPHS_INT_UPSTRRES (1 << 7) /* Bit 7: Upstream Resume Interrupt (Common) */ -#define USBPHS_INT_EPT(n) (1 << ((n)+8)) -#define USBPHS_INT_EPT0 (1 << 8) /* Bit 8: Endpoint 0 Interrupt (not Clear) */ -#define USBPHS_INT_EPT1 (1 << 9) /* Bit 9: Endpoint 1 Interrupt (not Clear) */ -#define USBPHS_INT_EPT2 (1 << 10) /* Bit 10: Endpoint 2 Interrupt (not Clear) */ -#define USBPHS_INT_EPT3 (1 << 11) /* Bit 11: Endpoint 3 Interrupt (not Clear) */ -#define USBPHS_INT_EPT4 (1 << 12) /* Bit 12: Endpoint 4 Interrupt (not Clear) */ -#define USBPHS_INT_EPT5 (1 << 13) /* Bit 13: Endpoint 5 Interrupt (not Clear) */ -#define USBPHS_INT_EPT6 (1 << 13) /* Bit 14: Endpoint 6 Interrupt (not Clear) */ -#define USBPHS_INT_DMA(n) (1<<((n)+24)) -#define USBPHS_INT_DMA1 (1 << 25) /* Bit 25: DMA Channel 1 Interrupt (not Clear) */ -#define USBPHS_INT_DMA2 (1 << 26) /* Bit 26: DMA Channel 2 Interrupt (not Clear) */ -#define USBPHS_INT_DMA3 (1 << 27) /* Bit 27: DMA Channel 3 Interrupt (not Clear) */ -#define USBPHS_INT_DMA4 (1 << 28) /* Bit 28: DMA Channel 4 Interrupt (not Clear) */ -#define USBPHS_INT_DMA5 (1 << 29) /* Bit 29: DMA Channel 5 Interrupt (not Clear) */ -#define USBPHS_INT_DMA6 (1 << 30) /* Bit 30: DMA Channel 6 Interrupt (not Clear) */ - -/* UDPHS Endpoints Reset Register */ - -#define UDPHS_EPTRST_EPT(n) (1<<(n)) /* Bit 0-6: Endpoint n Reset */ - -/* UDPHS Test Register */ - -#define UDPHS_TST_SPEEDCFG_SHIFT (0) /* Bits 0-1: Speed Configuration */ -#define UDPHS_TST_SPEEDCFG_MASK (3 << UDPHS_TST_SPEEDCFG_SHIFT) -00 Normal Mode -10 Force High Speed -11 Force Full Speed -#define UDPHS_TST_TSTJ (1 << 2) /* Bit 2: Test J Mode */ -#define UDPHS_TST_TSTK (1 << 3) /* Bit 3: Test K Mode */ -#define UDPHS_TST_TSTPKT (1 << 4) /* Bit 4: Test Packet Mo */ -#define UDPHS_TST_OPMODE2 (1 << 5) /* Bit 5: OpMode2 */ - -/* UDPHS Features Register */ - -#define UDPHS_IPFEATURES_EPTNBRMAX_SHIFT (0) /* Bits 0-3: Max Number of Endpoints */ -#define UDPHS_IPFEATURES_EPTNBRMAX_MASK (15 << UDPHS_IPFEATURES_EPTNBRMAX_SHIFT) -#define UDPHS_IPFEATURES_DMACHANNELNBR_SHIFT (4) /* Bits 4-6: Number of DMA Channels */ -#define UDPHS_IPFEATURES_DMACHANNELNBR_MASK (7 << UDPHS_IPFEATURES_DMACHANNELNBR_SHIFT) -#define UDPHS_IPFEATURES_DMABSIZ (1 << 7) /* Bit 7: DMA Buffer Size */ -#define UDPHS_IPFEATURES_DMAFIFOWDDEPTH_SHIFT (8) /* Bits 8-11: DMA FIFO Depth in Words */ -#define UDPHS_IPFEATURES_DMAFIFOWDDEPTH_MASK (15 << UDPHS_IPFEATURES_DMAFIFOWDDEPTH_SHIFT) -# define UDPHS_IPFEATURES_DMAFIFOWDDEPTH(n) ((n)&15) -#define UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT (12) /* Bits 12-14: DPRAM Size */ -#define UDPHS_IPFEATURES_FIFOMAXSIZE_MASK (7 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) -# define UDPHS_IPFEATURES_FIFOMAXSIZE_128b (0 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 128 bytes */ -# define UDPHS_IPFEATURES_FIFOMAXSIZE_256b (1 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 256 bytes */ -# define UDPHS_IPFEATURES_FIFOMAXSIZE_512b (2 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 512 bytes */ -# define UDPHS_IPFEATURES_FIFOMAXSIZE_1Kb (3 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 1024 bytes */ -# define UDPHS_IPFEATURES_FIFOMAXSIZE_2Kb (4 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 2048 bytes */ -# define UDPHS_IPFEATURES_FIFOMAXSIZE_4Kb (5 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 4096 bytes */ -# define UDPHS_IPFEATURES_FIFOMAXSIZE_8Kb (6 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 8192 bytes */ -# define UDPHS_IPFEATURES_FIFOMAXSIZE_16Kb (7 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 16384 bytes */ -#define UDPHS_IPFEATURES_BWDPRAM (1 << 15) /* Bit 15: DPRAM Byte Write Capability */ -#define UDPHS_IPFEATURES_DATAB168 (1 << 15) /* Bit 15: UTMI DataBus16_8 */ -#define UDPHS_IPFEATURES_ISOEPT(n) (1<<((n)+16) -#define UDPHS_IPFEATURES_ISOEPT1 (1 << 17) /* Bit 17: EP1 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT2 (1 << 18) /* Bit 18: EP2 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT3 (1 << 19) /* Bit 19: EP3 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT4 (1 << 20) /* Bit 20: EP4 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT5 (1 << 21) /* Bit 21: EP5 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT6 (1 << 22) /* Bit 22: EP6 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT7 (1 << 23) /* Bit 23: EP7 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT8 (1 << 24) /* Bit 24: EP8 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT9 (1 << 25) /* Bit 25: EP9 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT0 (1 << 26) /* Bit 26: EP10 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT1 (1 << 27) /* Bit 27: EP11 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT2 (1 << 28) /* Bit 28: EP12 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT3 (1 << 29) /* Bit 29: EP13 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT4 (1 << 30) /* Bit 30: EP14 High B/W Isoc Capability */ -#define UDPHS_IPFEATURES_ISOEPT5 (1 << 31) /* Bit 31: EP15 High B/W Isoc Capability */ - -/* UDPHS Endpoint Configuration Register (0-6) */ - -#define UDPHSEP_CFG_SIZE_SHIFT (0) /* Bits 0-2: Endpoint Size */ -#define UDPHSEP_CFG_SIZE_MASK (7 << UDPHSEP_CFG_SIZE_SHIFT) -# define UDPHSEP_CFG_SIZE_8b (0 << UDPHSEP_CFG_SIZE_SHIFT) /* 8 bytes */ -# define UDPHSEP_CFG_SIZE_16b (1 << UDPHSEP_CFG_SIZE_SHIFT) /* 16 bytes */ -# define UDPHSEP_CFG_SIZE_32b (2 << UDPHSEP_CFG_SIZE_SHIFT) /* 32 bytes */ -# define UDPHSEP_CFG_SIZE_16b (3 << UDPHSEP_CFG_SIZE_SHIFT) /* 64 bytes */ -# define UDPHSEP_CFG_SIZE_128b (4 << UDPHSEP_CFG_SIZE_SHIFT) /* 128 bytes */ -# define UDPHSEP_CFG_SIZE_256b (5 << UDPHSEP_CFG_SIZE_SHIFT) /* 256 bytes */ -# define UDPHSEP_CFG_SIZE_512b (6 << UDPHSEP_CFG_SIZE_SHIFT) /* 512 bytes */ -# define UDPHSEP_CFG_SIZE_1Kb (7 << UDPHSEP_CFG_SIZE_SHIFT) /* 1024 bytes */ -#define UDPHSEP_CFG_DIR (1 << 3) /* Bit 3: Endpoint Direction */ -#define UDPHSEP_CFG_TYPE_SHIFT (4) /* Bits 4-5: Endpoint Type */ -#define UDPHSEP_CFG_TYPE_MASK (3 << UDPHSEP_CFG_TYPE_SHIFT) -# define UDPHSEP_CFG_TYPE_CNTRL (0 << UDPHSEP_CFG_TYPE_SHIFT) /* Control endpoint */ -# define UDPHSEP_CFG_TYPE_ISOC (1 << UDPHSEP_CFG_TYPE_SHIFT) /* Isochronous endpoint */ -# define UDPHSEP_CFG_TYPE_BULK (2 << UDPHSEP_CFG_TYPE_SHIFT) /* Bulk endpoint */ -# define UDPHSEP_CFG_TYPE_INTR (3 << UDPHSEP_CFG_TYPE_SHIFT) /* Interrupt endpoint */ -#define UDPHSEP_CFG_BKNUMBER_SHIFT (6) /* Bits 6-7: Number of Banks */ -#define UDPHSEP_CFG_BKNUMBER_MASK (3 << UDPHSEP_CFG_BKNUMBER_SHIFT) -# define UDPHSEP_CFG_BKNUMBER_0BANK (0 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Zero bank (unmapped) */ -# define UDPHSEP_CFG_BKNUMBER_1BANK (1 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* One bank (bank 0) */ -# define UDPHSEP_CFG_BKNUMBER_2BANK (2 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Double bank (bank 0-1) */ -# define UDPHSEP_CFG_BKNUMBER_3BANK (3 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Triple bank (bank 0-2) */ -#define UDPHSEP_CFG_NBTRANS_SHIFT (8) /* Bits 8-9: Number Of Transaction per Microframe */ -#define UDPHSEP_CFG_NBTRANS_MASK (3 << UDPHSEP_CFG_NBTRANS_SHIFT) -#define UDPHSEP_CFG_MAPD (1 << 31) /*Bit 31: Endpoint Mapped */ - -/* UDPHS Endpoint Control Enable Register, UDPHS Endpoint Control Disable Register, - * and UDPHS Endpoint Control Register common bit-field definitions - */ - -#define UDPHSEP_INT_EPT (1 << 0) /* Bit 0: Endpoint Enable/Disable */ -#define UDPHSEP_INT_AUTOVALID (1 << 1) /* Bit 1: Packet Auto-Valid */ -#define UDPHSEP_INT_INTDISDMA (1 << 3) /* Bit 3: Interrupts Disable DMA */ -#define UDPHSEP_INT_NYETDIS (1 << 4) /* Bit 4: NYET Disable (HS Bulk OUT EPs) */ -#define UDPHSEP_INT_DATAXRX (1 << 6) /* Bit 6: DATAx Interrupt Enable (High B/W Isoc OUT EPs) */ -#define UDPHSEP_INT_MDATARX (1 << 7) /* Bit 7: MDATA Interrupt Enable (High B/W Isoc OUT EPs) */ -#define UDPHSEP_INT_ERROVFLW (1 << 8) /* Bit 8: Overflow Error Interrupt */ -#define UDPHSEP_INT_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data Interrupt */ -#define UDPHSEP_INT_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete Interrupt */ -#define UDPHSEP_INT_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready Interrupt */ -#define UDPHSEP_INT_ERRTRANS (1 << 11) /* Bit 11: Transaction Error Interrupt */ -#define UDPHSEP_INT_RXSETUP (1 << 12) /* Bit 12: Received SETUP Interrupt */ -#define UDPHSEP_INT_ERRFLISO (1 << 12) /* Bit 12: Error Flow Interrupt */ -#define UDPHSEP_INT_STALLSNT (1 << 13) /* Bit 13: Stall Sent Interrupt */ -#define UDPHSEP_INT_ERRCRISO (1 << 13) /* Bit 13: ISO CRC Error Error Interrupt */ -#define UDPHSEP_INT_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error Interrupt */ -#define UDPHSEP_INT_NAKIN (1 << 14) /* Bit 14: NAKIN Interrupt */ -#define UDPHSEP_INT_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error Interrupt */ -#define UDPHSEP_INT_NAKOUT (1 << 15) /* Bit 15: NAKOUT Interrupt */ -#define UDPHSEP_INT_BUSYBANK (1 << 18) /* Bit 18: Busy Bank Interrupt */ -#define UDPHSEP_INT_SHRTPCKT (1 << 31) /* Bit 31: Short Packet Send/Short Packet Interrupt */ - -/* UDPHS Endpoint Set Status Register */ - -#define UDPHSEP_SETSTA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request Set */ -#define UDPHSEP_SETSTA_KILLBANK (1 << 9) /* Bit 9: KILL Bank Set (for IN Endpoint) */ -#define UDPHSEP_SETSTA_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready Set */ - -/* UDPHS Endpoint Clear Status Register */ - -#define UDPHSEP_CLRSTA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request Clear */ -#define UDPHSEP_CLRSTA_TOGGLESQ (1 << 6) /* Bit 6: Data Toggle Clear */ -#define UDPHSEP_CLRSTA_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data Clear */ -#define UDPHSEP_CLRSTA_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete Clear */ -#define UDPHSEP_CLRSTA_RXSETUP (1 << 12) /* Bit 12: Received SETUP Clear */ -#define UDPHSEP_CLRSTA_ERRFLISO (1 << 12) /* Bit 12: Error Flow Clear */ -#define UDPHSEP_CLRSTA_STALL_NT (1 << 13) /* Bit 13: Stall Sent Clear */ -#define UDPHSEP_CLRSTA_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error Clear */ -#define UDPHSEP_CLRSTA_NAKIN (1 << 14) /* Bit 14: NAKIN Clear */ -#define UDPHSEP_CLRSTA_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error Clear */ -#define UDPHSEP_CLRSTA_NAKOUT (1 << 15) /* Bit 15: NAKOUT Clear */ - -/* UDPHS Endpoint Status Register */ - -#define UDPHSEP_STA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request */ -#define UDPHSEP_STA_TOGGLESQSTA_SHIFT (6) /* Bits 6-7: Toggle Sequencing */ -#define UDPHSEP_STA_TOGGLESQSTA_MASK (3 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) -# define UDPHSEP_STA_TOGGLESQSTA_DATA0 (0 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data0 */ -# define UDPHSEP_STA_TOGGLESQSTA_DATA1 (1 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data1 */ -# define UDPHSEP_STA_TOGGLESQSTA_DATA2 (2 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data2 (High B/W Isoc EP) */ -# define UDPHSEP_STA_TOGGLESQSTA_MDATA (3 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* MData (High B/W Isoc EP) */ -#define UDPHSEP_STA_ERROVFLW (1 << 8) /* Bit 8: Overflow Error */ -#define UDPHSEP_STA_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data */ -#define UDPHSEP_STA_KILLBANK (1 << 9) /* Bit 9: KILL Bank */ -#define UDPHSEP_STA_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete */ -#define UDPHSEP_STA_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready */ -#define UDPHSEP_STA_ERRTRANS (1 << 11) /* Bit 11: Transaction Error */ -#define UDPHSEP_STA_RXSETUP (1 << 12) /* Bit 12: Received SETUP */ -#define UDPHSEP_STA_ERRFLISO (1 << 12) /* Bit 12: Error Flow */ -#define UDPHSEP_STA_STALLSNT (1 << 13) /* Bit 13: Stall Sent */ -#define UDPHSEP_STA_ERRCRISO (1 << 13) /* Bit 13: CRC ISO Error */ -#define UDPHSEP_STA_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error */ -#define UDPHSEP_STA_NAKIN (1 << 14) /* Bit 14: NAK IN */ -#define UDPHSEP_STA_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error */ -#define UDPHSEP_STA_NAKOUT (1 << 15) /* Bit 15: NAK OUT */ -#define UDPHSEP_STA_CURRENTBANK_SHIFT (16) /* Bits 16-17: Current Bank */ -#define UDPHSEP_STA_CURRENTBANK_MASK (3 << UDPHSEP_STA_CURRENTBANK_MASK) -#define UDPHSEP_STA_CONTROLDIR_SHIFT (16) /* Bits 16-17: Control Direction */ -#define UDPHSEP_STA_CONTROLDIR_MASK (3 << UDPHSEP_STA_CONTROLDIR_SHIFT) -#define UDPHSEP_STA_BUSYBANKSTA_SHIFT (18) /* Bits 18-19: Busy Bank Number */ -#define UDPHSEP_STA_BUSYBANKSTA_MASK (3 << UDPHSEP_STA_BUSYBANKSTA_SHIFT) -#define UDPHSEP_STA_BYTECOUNT_SHIFT (20) /* Bits 20-23: UDPHS Byte Count */ -#define UDPHSEP_STA_BYTECOUNT_MASK (15 << UDPHSEP_STA_BYTECOUNT_SHIFT) -#define UDPHSEP_STA_SHRTPCKT (1 << 31) /* Bit 31: Short Packet - -/* UDPHS DMA Channel Control Register */ - -#define UDPHSDMA_CONTROL_CHANNENB (1 << 0) /* Bit 0: Channel Enable Command */ -#define UDPHSDMA_CONTROL_LDNXTDSC (1 << 1) /* Bit 1: Load Next Channel Xfr Desc Enable (Command) */ -#define UDPHSDMA_CONTROL_ENDTREN (1 << 2) /* Bit 2: End of Transfer Enable (Control) */ -#define UDPHSDMA_CONTROL_ENDBEN (1 << 3) /* Bit 3: End of Buffer Enable (Control) */ -#define UDPHSDMA_CONTROL_ENDTRIT (1 << 4) /* Bit 4: End of Transfer Interrupt Enable */ -#define UDPHSDMA_CONTROL_ENDBUFFIT (1 << 5) /* Bit 5: End of Buffer Interrupt Enable */ -#define UDPHSDMA_CONTROL_DESCLDIT (1 << 6) /* Bit 6: Descriptor Loaded Interrupt Enab */ -#define UDPHSDMA_CONTROL_BURSTLCK (1 << 7) /* Bit 7: Burst Lock Ena */ -#define UDPHSDMA_CONTROL_BUFFLENGTH_SHIFT (16) /* Bits 16-31: Buffer Byte Length (Write-only) */ -#define UDPHSDMA_CONTROL_BUFFLENGTH_MASK (0xffff << UDPHSDMA_CONTROL_BUFFLENGTH_SHIFT) - -/* UDPHS DMA Channel Status Register */ - -#define UDPHSDMA_STATUS_CHANNENB (1 << 0) /* Bit 0: Channel Enable Status */ -#define UDPHSDMA_STATUS_CHANNACT (1 << 1) /* Bit 1: Channel Active Status */ -#define UDPHSDMA_STATUS_ENDTRST (1 << 4) /* Bit 4: End of Channel Transfer Status */ -#define UDPHSDMA_STATUS_ENDBFST (1 << 5) /* Bit 5: End of Channel Buffer Status */ -#define UDPHSDMA_STATUS_DESCLDST (1 << 6) /* Bit 6: Descriptor Loaded Status */ -#define UDPHSDMA_STATUS_BUFFCOUNT_SHIFT (16) /* Bits 16-31: Buffer Byte Count */ -#define UDPHSDMA_STATUS_BUFFCOUNT_MASK (0xffff << UDPHSDMA_STATUS_BUFFCOUNT_SHIFT) - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_udphs.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* UDPHS register offsets ***************************************************************/ + +#define SAM3U_UDPHS_CTRL_OFFSET 0x00 /* UDPHS Control Register */ +#define SAM3U_UDPHS_FNUM_OFFSET 0x04 /* UDPHS Frame Number Register */ + /* 0x08-0x0C: Reserved */ +#define SAM3U_UDPHS_IEN_OFFSET 0x10 /* UDPHS Interrupt Enable Register */ +#define SAM3U_UDPHS_INTSTA_OFFSET 0x14 /* UDPHS Interrupt Status Register */ +#define SAM3U_UDPHS_CLRINT_OFFSET 0x18 /* UDPHS Clear Interrupt Register */ +#define SAM3U_UDPHS_EPTRST_OFFSET 0x1c /* UDPHS Endpoints Reset Register */ + /* 0x20-0xcc: Reserved */ +#define SAM3U_UDPHS_TST_OFFSET 0xe0 /* UDPHS Test Register */ + /* 0xE4-0xE8: Reserved */ +#define SAM3U_UDPHS_IPNAME1_OFFSET 0xf0 /* UDPHS Name1 Register */ +#define SAM3U_UDPHS_IPNAME2_OFFSET 0xf4 /* UDPHS Name2 Register */ +#define SAM3U_UDPHS_IPFEATURES_OFFSET 0xf8 /* UDPHS Features Register */ + +/* Endpoint registers: Offsets for Endpoints 0-6: 0x100, 0x120, 0x140, 0x160, 0x180, + * 0x1a0, and 0x1c0 + */ + +#define SAM3U_UDPHSEP_OFFSET(n) (0x100+((n)<<5)) +#define SAM3U_UDPHSEP_CFG_OFFSET 0x00 /* UDPHS Endpoint Configuration Register */ +#define SAM3U_UDPHSEP_CTLENB_OFFSET 0x04 /* UDPHS Endpoint Control Enable Register */ +#define SAM3U_UDPHSEP_CTLDIS_OFFSET 0x08 /* UDPHS Endpoint Control Disable Register */ +#define SAM3U_UDPHSEP_CTL_OFFSET 0x0c /* UDPHS Endpoint Control Register */ + /* 0x10: Reserved */ +#define SAM3U_UDPHSEP_SETSTA_OFFSET 0x14 /* UDPHS Endpoint Set Status Register */ +#define SAM3U_UDPHSEP_CLRSTA_OFFSET 0x18 /* UDPHS Endpoint Clear Status Register */ +#define SAM3U_UDPHSEP_STA_OFFSET 0x1c /* UDPHS Endpoint Status Register */ + /* 0x1e0-0x300: Reserved */ + /* 0x300-0x30c: Reserved */ +/* DMA Channel Registers: Offsets for DMA channels 1-6 0x320, 0x330, 0x340, 0x350, and + * 0x360. NOTE that there is no DMA channel 0. + */ + +#define SAM3U_UDPHSDMA_OFFSET(n) (0x310+((n)<<4)) +#define SAM3U_UDPHSDMA_NXTDSC_OFFSET 0x00 /* UDPHS DMA Next Descriptor Address Register */ +#define SAM3U_UDPHSDMA_ADDRESS_OFFSET 0x04 /* UDPHS DMA Channel Address Register */ +#define SAM3U_UDPHSDMA_CONTROL_OFFSET 0x08 /* UDPHS DMA Channel Control Register */ +#define SAM3U_UDPHSDMA_STATUS_OFFSET) 0x0c /* UDPHS DMA Channel Status Register */ + +/* UDPHS register adresses **************************************************************/ + +#define SAM3U_UDPHS_CTRL (SAM3U_UDPHS_BASE+SAM3U_UDPHS_CTRL_OFFSET) +#define SAM3U_UDPHS_FNUM (SAM3U_UDPHS_BASE+SAM3U_UDPHS_FNUM_OFFSET) +#define SAM3U_UDPHS_IEN (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IEN_OFFSET) +#define SAM3U_UDPHS_INTSTA (SAM3U_UDPHS_BASE+SAM3U_UDPHS_INTSTA_OFFSET) +#define SAM3U_UDPHS_CLRINT (SAM3U_UDPHS_BASE+ SAM3U_UDPHS_CLRINT_OFFSET) +#define SAM3U_UDPHS_EPTRST (SAM3U_UDPHS_BASE+SAM3U_UDPHS_EPTRST_OFFSET) +#define SAM3U_UDPHS_TST (SAM3U_UDPHS_BASE+SAM3U_UDPHS_TST_OFFSET) +#define SAM3U_UDPHS_IPNAME1 (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPNAME1_OFFSET) +#define SAM3U_UDPHS_IPNAME2 (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPNAME2_OFFSET) +#define SAM3U_UDPHS_IPFEATURES (SAM3U_UDPHS_BASE+SAM3U_UDPHS_IPFEATURES_OFFSET) + +/* Endpoint registers */ + +#define SAM3U_UDPHSEP_BASE(n)) (SAM3U_UDPHS_BASE+SAM3U_UDPHSEP_OFFSET(n)) +#define SAM3U_UDPHSEP_CFG(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CFG_OFFSET) +#define SAM3U_UDPHSEP_CTLENB(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTLENB_OFFSET) +#define SAM3U_UDPHSEP_CTLDIS(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTLDIS_OFFSET) +#define SAM3U_UDPHSEP_CTL(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CTL_OFFSET) +#define SAM3U_UDPHSEP_SETSTA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_SETSTA_OFFSET) +#define SAM3U_UDPHSEP_CLRSTA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_CLRSTA_OFFSET) +#define SAM3U_UDPHSEP_STA(n) (SAM3U_UDPHSEP_BASE(n)+SAM3U_UDPHSEP_STA_OFFSET) + +/* DMA Channel Registers*/ + +#define SAM3U_UDPHSDMA_BASE(n) (SAM3U_UDPHS_BASE+SAM3U_UDPHSDMA_OFFSET(n)) +#define SAM3U_UDPHSDMA_NXTDSC(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_NXTDSC_OFFSET) +#define SAM3U_UDPHSDMA_ADDRESS(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_ADDRESS_OFFSET) +#define SAM3U_UDPHSDMA_CONTROL(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_CONTROL_OFFSET) +#define SAM3U_UDPHSDMA_STATUS(n) (SAM3U_UDPHSDMA_BASE(n)+SAM3U_UDPHSDMA_STATUS_OFFSET) + +/* UDPHS register bit definitions *******************************************************/ +/* UDPHS Control Register */ + +#define UDPHS_CTRL_DEVADDR_SHIFT (0) /* Bits 0-6: UDPHS Address */ +#define UDPHS_CTRL_DEVADDR_MASK (0x7f << UDPHS_CTRL_DEVADDR_SHIFT) +#define UDPHS_CTRL_FADDREN (1 << 7) /* Bit 7: Function Address Enable */ +#define UDPHS_CTRL_ENUDPHS (1 << 8) /* Bit 8: UDPHS Enable */ +#define UDPHS_CTRL_DETACH (1 << 9) /* Bit 9: Detach Command */ +#define UDPHS_CTRL_REWAKEUP (1 << 10) /* Bit 10: Send Remote Wake Up */ +#define UDPHS_CTRL_PULLDDIS (1 << 11) /* Bit 11: Pull-Down Disable */ + +/* UDPHS Frame Number Register */ + +#define UDPHS_FNUM_MICROFRAMENUM_SHIFT (0) /* Bits 0-2: Microframe Num */ +#define UDPHS_FNUM_MICROFRAMENUM_MASK (7 << UDPHS_FNUM_MICROFRAMENUM_SHIFT) +#define UDPHS_FNUM_FRAMENUMBER_SHIFT (3) /* Bits 3-7: Frame Number in Packet Field Formats */ +#define UDPHS_FNUM_FRAMENUMBER_MASK (31 << UDPHS_FNUM_FRAMENUMBER_SHIFT) +#define UDPHS_FNUM_FNUMERR_SHIFT (8) /* Bits 8-13: Frame Number CRC Error */ +#define UDPHS_FNUM_FNUMERR_MASK (63 << UDPHS_FNUM_FNUMERR_SHIFT) + +/* UDPHS Interrupt Enable Register, UDPHS Interrupt Status Register, and UDPHS Clear + * Interrupt Register common bit-field definitions + */ + +#define USBPHS_INT_DETSUSPD (1 << 1) /* Bit 1: Suspend Interrupt (Common) */ +#define USBPHS_INT_MICROSOF (1 << 2) /* Bit 2: Micro-SOF Interrupt (Common) */ +#define USBPHS_INT_INTSOF (1 << 3) /* Bit 3: SOF Interrupt (Common) */ +#define USBPHS_INT_ENDRESET (1 << 4) /* Bit 4: End Of Reset Interrupt (Common) */ +#define USBPHS_INT_WAKEUP (1 << 5) /* Bit 5: Wake Up CPU Interrupt (Common) */ +#define USBPHS_INT_ENDOFRSM (1 << 6) /* Bit 6: End Of Resume Interrupt (Common) */ +#define USBPHS_INT_UPSTRRES (1 << 7) /* Bit 7: Upstream Resume Interrupt (Common) */ +#define USBPHS_INT_EPT(n) (1 << ((n)+8)) +#define USBPHS_INT_EPT0 (1 << 8) /* Bit 8: Endpoint 0 Interrupt (not Clear) */ +#define USBPHS_INT_EPT1 (1 << 9) /* Bit 9: Endpoint 1 Interrupt (not Clear) */ +#define USBPHS_INT_EPT2 (1 << 10) /* Bit 10: Endpoint 2 Interrupt (not Clear) */ +#define USBPHS_INT_EPT3 (1 << 11) /* Bit 11: Endpoint 3 Interrupt (not Clear) */ +#define USBPHS_INT_EPT4 (1 << 12) /* Bit 12: Endpoint 4 Interrupt (not Clear) */ +#define USBPHS_INT_EPT5 (1 << 13) /* Bit 13: Endpoint 5 Interrupt (not Clear) */ +#define USBPHS_INT_EPT6 (1 << 13) /* Bit 14: Endpoint 6 Interrupt (not Clear) */ +#define USBPHS_INT_DMA(n) (1<<((n)+24)) +#define USBPHS_INT_DMA1 (1 << 25) /* Bit 25: DMA Channel 1 Interrupt (not Clear) */ +#define USBPHS_INT_DMA2 (1 << 26) /* Bit 26: DMA Channel 2 Interrupt (not Clear) */ +#define USBPHS_INT_DMA3 (1 << 27) /* Bit 27: DMA Channel 3 Interrupt (not Clear) */ +#define USBPHS_INT_DMA4 (1 << 28) /* Bit 28: DMA Channel 4 Interrupt (not Clear) */ +#define USBPHS_INT_DMA5 (1 << 29) /* Bit 29: DMA Channel 5 Interrupt (not Clear) */ +#define USBPHS_INT_DMA6 (1 << 30) /* Bit 30: DMA Channel 6 Interrupt (not Clear) */ + +/* UDPHS Endpoints Reset Register */ + +#define UDPHS_EPTRST_EPT(n) (1<<(n)) /* Bit 0-6: Endpoint n Reset */ + +/* UDPHS Test Register */ + +#define UDPHS_TST_SPEEDCFG_SHIFT (0) /* Bits 0-1: Speed Configuration */ +#define UDPHS_TST_SPEEDCFG_MASK (3 << UDPHS_TST_SPEEDCFG_SHIFT) +# define UDPHS_TST_SPEEDCFG_NORMAL (0 << UDPHS_TST_SPEEDCFG_SHIFT) /* Normal Mode */ +# define UDPHS_TST_SPEEDCFG_HIGH (2 << UDPHS_TST_SPEEDCFG_SHIFT) /* Force High Speed */ +# define UDPHS_TST_SPEEDCFG_FULL (3 << UDPHS_TST_SPEEDCFG_SHIFT) /* Force Full Speed */ +#define UDPHS_TST_TSTJ (1 << 2) /* Bit 2: Test J Mode */ +#define UDPHS_TST_TSTK (1 << 3) /* Bit 3: Test K Mode */ +#define UDPHS_TST_TSTPKT (1 << 4) /* Bit 4: Test Packet Mo */ +#define UDPHS_TST_OPMODE2 (1 << 5) /* Bit 5: OpMode2 */ + +/* UDPHS Features Register */ + +#define UDPHS_IPFEATURES_EPTNBRMAX_SHIFT (0) /* Bits 0-3: Max Number of Endpoints */ +#define UDPHS_IPFEATURES_EPTNBRMAX_MASK (15 << UDPHS_IPFEATURES_EPTNBRMAX_SHIFT) +#define UDPHS_IPFEATURES_DMACHANNELNBR_SHIFT (4) /* Bits 4-6: Number of DMA Channels */ +#define UDPHS_IPFEATURES_DMACHANNELNBR_MASK (7 << UDPHS_IPFEATURES_DMACHANNELNBR_SHIFT) +#define UDPHS_IPFEATURES_DMABSIZ (1 << 7) /* Bit 7: DMA Buffer Size */ +#define UDPHS_IPFEATURES_DMAFIFOWDDEPTH_SHIFT (8) /* Bits 8-11: DMA FIFO Depth in Words */ +#define UDPHS_IPFEATURES_DMAFIFOWDDEPTH_MASK (15 << UDPHS_IPFEATURES_DMAFIFOWDDEPTH_SHIFT) +# define UDPHS_IPFEATURES_DMAFIFOWDDEPTH(n) ((n)&15) +#define UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT (12) /* Bits 12-14: DPRAM Size */ +#define UDPHS_IPFEATURES_FIFOMAXSIZE_MASK (7 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) +# define UDPHS_IPFEATURES_FIFOMAXSIZE_128b (0 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 128 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_256b (1 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 256 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_512b (2 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 512 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_1Kb (3 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 1024 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_2Kb (4 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 2048 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_4Kb (5 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 4096 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_8Kb (6 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 8192 bytes */ +# define UDPHS_IPFEATURES_FIFOMAXSIZE_16Kb (7 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 16384 bytes */ +#define UDPHS_IPFEATURES_BWDPRAM (1 << 15) /* Bit 15: DPRAM Byte Write Capability */ +#define UDPHS_IPFEATURES_DATAB168 (1 << 15) /* Bit 15: UTMI DataBus16_8 */ +#define UDPHS_IPFEATURES_ISOEPT(n) (1<<((n)+16) +#define UDPHS_IPFEATURES_ISOEPT1 (1 << 17) /* Bit 17: EP1 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT2 (1 << 18) /* Bit 18: EP2 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT3 (1 << 19) /* Bit 19: EP3 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT4 (1 << 20) /* Bit 20: EP4 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT5 (1 << 21) /* Bit 21: EP5 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT6 (1 << 22) /* Bit 22: EP6 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT7 (1 << 23) /* Bit 23: EP7 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT8 (1 << 24) /* Bit 24: EP8 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT9 (1 << 25) /* Bit 25: EP9 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT0 (1 << 26) /* Bit 26: EP10 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT1 (1 << 27) /* Bit 27: EP11 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT2 (1 << 28) /* Bit 28: EP12 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT3 (1 << 29) /* Bit 29: EP13 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT4 (1 << 30) /* Bit 30: EP14 High B/W Isoc Capability */ +#define UDPHS_IPFEATURES_ISOEPT5 (1 << 31) /* Bit 31: EP15 High B/W Isoc Capability */ + +/* UDPHS Endpoint Configuration Register (0-6) */ + +#define UDPHSEP_CFG_SIZE_SHIFT (0) /* Bits 0-2: Endpoint Size */ +#define UDPHSEP_CFG_SIZE_MASK (7 << UDPHSEP_CFG_SIZE_SHIFT) +# define UDPHSEP_CFG_SIZE_8b (0 << UDPHSEP_CFG_SIZE_SHIFT) /* 8 bytes */ +# define UDPHSEP_CFG_SIZE_16b (1 << UDPHSEP_CFG_SIZE_SHIFT) /* 16 bytes */ +# define UDPHSEP_CFG_SIZE_32b (2 << UDPHSEP_CFG_SIZE_SHIFT) /* 32 bytes */ +# define UDPHSEP_CFG_SIZE_16b (3 << UDPHSEP_CFG_SIZE_SHIFT) /* 64 bytes */ +# define UDPHSEP_CFG_SIZE_128b (4 << UDPHSEP_CFG_SIZE_SHIFT) /* 128 bytes */ +# define UDPHSEP_CFG_SIZE_256b (5 << UDPHSEP_CFG_SIZE_SHIFT) /* 256 bytes */ +# define UDPHSEP_CFG_SIZE_512b (6 << UDPHSEP_CFG_SIZE_SHIFT) /* 512 bytes */ +# define UDPHSEP_CFG_SIZE_1Kb (7 << UDPHSEP_CFG_SIZE_SHIFT) /* 1024 bytes */ +#define UDPHSEP_CFG_DIR (1 << 3) /* Bit 3: Endpoint Direction */ +#define UDPHSEP_CFG_TYPE_SHIFT (4) /* Bits 4-5: Endpoint Type */ +#define UDPHSEP_CFG_TYPE_MASK (3 << UDPHSEP_CFG_TYPE_SHIFT) +# define UDPHSEP_CFG_TYPE_CNTRL (0 << UDPHSEP_CFG_TYPE_SHIFT) /* Control endpoint */ +# define UDPHSEP_CFG_TYPE_ISOC (1 << UDPHSEP_CFG_TYPE_SHIFT) /* Isochronous endpoint */ +# define UDPHSEP_CFG_TYPE_BULK (2 << UDPHSEP_CFG_TYPE_SHIFT) /* Bulk endpoint */ +# define UDPHSEP_CFG_TYPE_INTR (3 << UDPHSEP_CFG_TYPE_SHIFT) /* Interrupt endpoint */ +#define UDPHSEP_CFG_BKNUMBER_SHIFT (6) /* Bits 6-7: Number of Banks */ +#define UDPHSEP_CFG_BKNUMBER_MASK (3 << UDPHSEP_CFG_BKNUMBER_SHIFT) +# define UDPHSEP_CFG_BKNUMBER_0BANK (0 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Zero bank (unmapped) */ +# define UDPHSEP_CFG_BKNUMBER_1BANK (1 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* One bank (bank 0) */ +# define UDPHSEP_CFG_BKNUMBER_2BANK (2 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Double bank (bank 0-1) */ +# define UDPHSEP_CFG_BKNUMBER_3BANK (3 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Triple bank (bank 0-2) */ +#define UDPHSEP_CFG_NBTRANS_SHIFT (8) /* Bits 8-9: Number Of Transaction per Microframe */ +#define UDPHSEP_CFG_NBTRANS_MASK (3 << UDPHSEP_CFG_NBTRANS_SHIFT) +#define UDPHSEP_CFG_MAPD (1 << 31) /*Bit 31: Endpoint Mapped */ + +/* UDPHS Endpoint Control Enable Register, UDPHS Endpoint Control Disable Register, + * and UDPHS Endpoint Control Register common bit-field definitions + */ + +#define UDPHSEP_INT_EPT (1 << 0) /* Bit 0: Endpoint Enable/Disable */ +#define UDPHSEP_INT_AUTOVALID (1 << 1) /* Bit 1: Packet Auto-Valid */ +#define UDPHSEP_INT_INTDISDMA (1 << 3) /* Bit 3: Interrupts Disable DMA */ +#define UDPHSEP_INT_NYETDIS (1 << 4) /* Bit 4: NYET Disable (HS Bulk OUT EPs) */ +#define UDPHSEP_INT_DATAXRX (1 << 6) /* Bit 6: DATAx Interrupt Enable (High B/W Isoc OUT EPs) */ +#define UDPHSEP_INT_MDATARX (1 << 7) /* Bit 7: MDATA Interrupt Enable (High B/W Isoc OUT EPs) */ +#define UDPHSEP_INT_ERROVFLW (1 << 8) /* Bit 8: Overflow Error Interrupt */ +#define UDPHSEP_INT_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data Interrupt */ +#define UDPHSEP_INT_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete Interrupt */ +#define UDPHSEP_INT_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready Interrupt */ +#define UDPHSEP_INT_ERRTRANS (1 << 11) /* Bit 11: Transaction Error Interrupt */ +#define UDPHSEP_INT_RXSETUP (1 << 12) /* Bit 12: Received SETUP Interrupt */ +#define UDPHSEP_INT_ERRFLISO (1 << 12) /* Bit 12: Error Flow Interrupt */ +#define UDPHSEP_INT_STALLSNT (1 << 13) /* Bit 13: Stall Sent Interrupt */ +#define UDPHSEP_INT_ERRCRISO (1 << 13) /* Bit 13: ISO CRC Error Error Interrupt */ +#define UDPHSEP_INT_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error Interrupt */ +#define UDPHSEP_INT_NAKIN (1 << 14) /* Bit 14: NAKIN Interrupt */ +#define UDPHSEP_INT_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error Interrupt */ +#define UDPHSEP_INT_NAKOUT (1 << 15) /* Bit 15: NAKOUT Interrupt */ +#define UDPHSEP_INT_BUSYBANK (1 << 18) /* Bit 18: Busy Bank Interrupt */ +#define UDPHSEP_INT_SHRTPCKT (1 << 31) /* Bit 31: Short Packet Send/Short Packet Interrupt */ + +/* UDPHS Endpoint Set Status Register */ + +#define UDPHSEP_SETSTA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request Set */ +#define UDPHSEP_SETSTA_KILLBANK (1 << 9) /* Bit 9: KILL Bank Set (for IN Endpoint) */ +#define UDPHSEP_SETSTA_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready Set */ + +/* UDPHS Endpoint Clear Status Register */ + +#define UDPHSEP_CLRSTA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request Clear */ +#define UDPHSEP_CLRSTA_TOGGLESQ (1 << 6) /* Bit 6: Data Toggle Clear */ +#define UDPHSEP_CLRSTA_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data Clear */ +#define UDPHSEP_CLRSTA_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete Clear */ +#define UDPHSEP_CLRSTA_RXSETUP (1 << 12) /* Bit 12: Received SETUP Clear */ +#define UDPHSEP_CLRSTA_ERRFLISO (1 << 12) /* Bit 12: Error Flow Clear */ +#define UDPHSEP_CLRSTA_STALL_NT (1 << 13) /* Bit 13: Stall Sent Clear */ +#define UDPHSEP_CLRSTA_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error Clear */ +#define UDPHSEP_CLRSTA_NAKIN (1 << 14) /* Bit 14: NAKIN Clear */ +#define UDPHSEP_CLRSTA_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error Clear */ +#define UDPHSEP_CLRSTA_NAKOUT (1 << 15) /* Bit 15: NAKOUT Clear */ + +/* UDPHS Endpoint Status Register */ + +#define UDPHSEP_STA_FRCESTALL (1 << 5) /* Bit 5: Stall Handshake Request */ +#define UDPHSEP_STA_TOGGLESQSTA_SHIFT (6) /* Bits 6-7: Toggle Sequencing */ +#define UDPHSEP_STA_TOGGLESQSTA_MASK (3 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) +# define UDPHSEP_STA_TOGGLESQSTA_DATA0 (0 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data0 */ +# define UDPHSEP_STA_TOGGLESQSTA_DATA1 (1 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data1 */ +# define UDPHSEP_STA_TOGGLESQSTA_DATA2 (2 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data2 (High B/W Isoc EP) */ +# define UDPHSEP_STA_TOGGLESQSTA_MDATA (3 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* MData (High B/W Isoc EP) */ +#define UDPHSEP_STA_ERROVFLW (1 << 8) /* Bit 8: Overflow Error */ +#define UDPHSEP_STA_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data */ +#define UDPHSEP_STA_KILLBANK (1 << 9) /* Bit 9: KILL Bank */ +#define UDPHSEP_STA_TXCOMPLT (1 << 10) /* Bit 10: Transmitted IN Data Complete */ +#define UDPHSEP_STA_TXPKRDY (1 << 11) /* Bit 11: TX Packet Ready */ +#define UDPHSEP_STA_ERRTRANS (1 << 11) /* Bit 11: Transaction Error */ +#define UDPHSEP_STA_RXSETUP (1 << 12) /* Bit 12: Received SETUP */ +#define UDPHSEP_STA_ERRFLISO (1 << 12) /* Bit 12: Error Flow */ +#define UDPHSEP_STA_STALLSNT (1 << 13) /* Bit 13: Stall Sent */ +#define UDPHSEP_STA_ERRCRISO (1 << 13) /* Bit 13: CRC ISO Error */ +#define UDPHSEP_STA_ERRNBTRA (1 << 13) /* Bit 13: Number of Transaction Error */ +#define UDPHSEP_STA_NAKIN (1 << 14) /* Bit 14: NAK IN */ +#define UDPHSEP_STA_ERRFLUSH (1 << 14) /* Bit 14: Bank Flush Error */ +#define UDPHSEP_STA_NAKOUT (1 << 15) /* Bit 15: NAK OUT */ +#define UDPHSEP_STA_CURRENTBANK_SHIFT (16) /* Bits 16-17: Current Bank */ +#define UDPHSEP_STA_CURRENTBANK_MASK (3 << UDPHSEP_STA_CURRENTBANK_MASK) +#define UDPHSEP_STA_CONTROLDIR_SHIFT (16) /* Bits 16-17: Control Direction */ +#define UDPHSEP_STA_CONTROLDIR_MASK (3 << UDPHSEP_STA_CONTROLDIR_SHIFT) +#define UDPHSEP_STA_BUSYBANKSTA_SHIFT (18) /* Bits 18-19: Busy Bank Number */ +#define UDPHSEP_STA_BUSYBANKSTA_MASK (3 << UDPHSEP_STA_BUSYBANKSTA_SHIFT) +#define UDPHSEP_STA_BYTECOUNT_SHIFT (20) /* Bits 20-23: UDPHS Byte Count */ +#define UDPHSEP_STA_BYTECOUNT_MASK (15 << UDPHSEP_STA_BYTECOUNT_SHIFT) +#define UDPHSEP_STA_SHRTPCKT (1 << 31) /* Bit 31: Short Packet + +/* UDPHS DMA Channel Control Register */ + +#define UDPHSDMA_CONTROL_CHANNENB (1 << 0) /* Bit 0: Channel Enable Command */ +#define UDPHSDMA_CONTROL_LDNXTDSC (1 << 1) /* Bit 1: Load Next Channel Xfr Desc Enable (Command) */ +#define UDPHSDMA_CONTROL_ENDTREN (1 << 2) /* Bit 2: End of Transfer Enable (Control) */ +#define UDPHSDMA_CONTROL_ENDBEN (1 << 3) /* Bit 3: End of Buffer Enable (Control) */ +#define UDPHSDMA_CONTROL_ENDTRIT (1 << 4) /* Bit 4: End of Transfer Interrupt Enable */ +#define UDPHSDMA_CONTROL_ENDBUFFIT (1 << 5) /* Bit 5: End of Buffer Interrupt Enable */ +#define UDPHSDMA_CONTROL_DESCLDIT (1 << 6) /* Bit 6: Descriptor Loaded Interrupt Enab */ +#define UDPHSDMA_CONTROL_BURSTLCK (1 << 7) /* Bit 7: Burst Lock Ena */ +#define UDPHSDMA_CONTROL_BUFFLENGTH_SHIFT (16) /* Bits 16-31: Buffer Byte Length (Write-only) */ +#define UDPHSDMA_CONTROL_BUFFLENGTH_MASK (0xffff << UDPHSDMA_CONTROL_BUFFLENGTH_SHIFT) + +/* UDPHS DMA Channel Status Register */ + +#define UDPHSDMA_STATUS_CHANNENB (1 << 0) /* Bit 0: Channel Enable Status */ +#define UDPHSDMA_STATUS_CHANNACT (1 << 1) /* Bit 1: Channel Active Status */ +#define UDPHSDMA_STATUS_ENDTRST (1 << 4) /* Bit 4: End of Channel Transfer Status */ +#define UDPHSDMA_STATUS_ENDBFST (1 << 5) /* Bit 5: End of Channel Buffer Status */ +#define UDPHSDMA_STATUS_DESCLDST (1 << 6) /* Bit 6: Descriptor Loaded Status */ +#define UDPHSDMA_STATUS_BUFFCOUNT_SHIFT (16) /* Bits 16-31: Buffer Byte Count */ +#define UDPHSDMA_STATUS_BUFFCOUNT_MASK (0xffff << UDPHSDMA_STATUS_BUFFCOUNT_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_UDPHS_H */ + diff --git a/arch/arm/src/sam3u/sam3u_userspace.c b/arch/arm/src/sam3u/sam3u_userspace.c index a62eee792295c75d6d5041794e152d643ad71ff3..e59cc561900d1d490c2b4c6e5926e42a93cffd9b 100644 --- a/arch/arm/src/sam3u/sam3u_userspace.c +++ b/arch/arm/src/sam3u/sam3u_userspace.c @@ -2,7 +2,7 @@ * arch/arm/src/common/sam3u_userspace.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/sam3u/sam3u_vectors.S b/arch/arm/src/sam3u/sam3u_vectors.S index 7e7ad188eebf7f000cabdc3e72537e4d5801ffa5..3ed17f7672dd1f071fa9db818ae7011113bc7fb2 100644 --- a/arch/arm/src/sam3u/sam3u_vectors.S +++ b/arch/arm/src/sam3u/sam3u_vectors.S @@ -3,7 +3,7 @@ * arch/arm/src/chip/sam3u_vectors.S * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/sam3u/sam3u_wdt.h b/arch/arm/src/sam3u/sam3u_wdt.h index b885608d7bd5cd3a3bde3b1b8df0e1a65e9ad875..50b16d2a851f9d1c2c2439a9aa21ebdbd2ded123 100644 --- a/arch/arm/src/sam3u/sam3u_wdt.h +++ b/arch/arm/src/sam3u/sam3u_wdt.h @@ -1,96 +1,96 @@ -/**************************************************************************************** - * arch/arm/src/sam3u/sam3u_wdt.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_WDT_H -#define __ARCH_ARM_SRC_SAM3U_SAM3U_WDT_H - -/**************************************************************************************** - * Included Files - ****************************************************************************************/ - -#include - -#include "chip.h" -#include "sam3u_memorymap.h" - -/**************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************/ - -/* WDT register offsets ****************************************************************/ - -#define SAM3U_WDT_CR_OFFSET 0x00 /* Control Register */ -#define SAM3U_WDT_MR_OFFSET 0x04 /* Mode Register */ -#define SAM3U_WDT_SR_OFFSET 0x08 /* Status Register */ - -/* WDT register adresses ***************************************************************/ - -#define SAM3U_WDT_CR (SAM3U_WDT_BASE+SAM3U_WDT_CR_OFFSET) -#define SAM3U_WDT_MR (SAM3U_WDT_BASE+SAM3U_WDT_MR_OFFSET) -#define SAM3U_WDT_SR (SAM3U_WDT_BASE+SAM3U_WDT_SR_OFFSET) - -/* WDT register bit definitions ********************************************************/ - -#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */ -#define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ -#define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT) - -#define WDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */ -#define WDT_MR_WDV_MASK (0xfff << WDT_MR_WDV_SHIFT) -#define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */ -#define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */ -#define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */ -#define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */ -#define WDT_MR_WDD_SHIFT (16) /* Bits 16-17: Watchdog Delta Value */ -#define WDT_MR_WDD_MASK (0xfff << WDT_MR_WDD_SHIFT) -#define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */ -#define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */ - -#define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */ -#define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */ - -/**************************************************************************************** - * Public Types - ****************************************************************************************/ - -/**************************************************************************************** - * Public Data - ****************************************************************************************/ - -/**************************************************************************************** - * Public Functions - ****************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_WDT_H */ +/**************************************************************************************** + * arch/arm/src/sam3u/sam3u_wdt.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM3U_SAM3U_WDT_H +#define __ARCH_ARM_SRC_SAM3U_SAM3U_WDT_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include + +#include "chip.h" +#include "sam3u_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* WDT register offsets ****************************************************************/ + +#define SAM3U_WDT_CR_OFFSET 0x00 /* Control Register */ +#define SAM3U_WDT_MR_OFFSET 0x04 /* Mode Register */ +#define SAM3U_WDT_SR_OFFSET 0x08 /* Status Register */ + +/* WDT register adresses ***************************************************************/ + +#define SAM3U_WDT_CR (SAM3U_WDT_BASE+SAM3U_WDT_CR_OFFSET) +#define SAM3U_WDT_MR (SAM3U_WDT_BASE+SAM3U_WDT_MR_OFFSET) +#define SAM3U_WDT_SR (SAM3U_WDT_BASE+SAM3U_WDT_SR_OFFSET) + +/* WDT register bit definitions ********************************************************/ + +#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */ +#define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ +#define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT) + +#define WDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */ +#define WDT_MR_WDV_MASK (0xfff << WDT_MR_WDV_SHIFT) +#define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */ +#define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */ +#define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */ +#define WDT_MR_WDD_SHIFT (16) /* Bits 16-17: Watchdog Delta Value */ +#define WDT_MR_WDD_MASK (0xfff << WDT_MR_WDD_SHIFT) +#define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */ + +#define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */ +#define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAM3U_SAM3U_WDT_H */ diff --git a/arch/arm/src/stm32/chip/stm32_bkp.h b/arch/arm/src/stm32/chip/stm32_bkp.h index 1788bdee08ec7d730c4dd2505b735938a0f20f61..5bda839a88d56f2d360fe302806d03b6b98af12a 100644 --- a/arch/arm/src/stm32/chip/stm32_bkp.h +++ b/arch/arm/src/stm32/chip/stm32_bkp.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32_bkp.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/chip/stm32_exti.h b/arch/arm/src/stm32/chip/stm32_exti.h index 82477db5490083aab33b7c29e514511e301df250..5386a260fb519cbc4498fc331423c0ba37574e03 100644 --- a/arch/arm/src/stm32/chip/stm32_exti.h +++ b/arch/arm/src/stm32/chip/stm32_exti.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32_exti.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/chip/stm32_memorymap.h b/arch/arm/src/stm32/chip/stm32_memorymap.h index a53c7441cf3cfbe405704c1a6df43220da936d42..36813b5651c0e7ad6b21b874e1dd90486d8dfc6e 100644 --- a/arch/arm/src/stm32/chip/stm32_memorymap.h +++ b/arch/arm/src/stm32/chip/stm32_memorymap.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32_memorymap.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/chip/stm32f100_pinmap.h b/arch/arm/src/stm32/chip/stm32f100_pinmap.h index 18e8435f7704fbbc1e140d8b4304dc7921baa02f..01d6e1ce06e8d7ebb2b12c597f7bd8ee93f5a60e 100644 --- a/arch/arm/src/stm32/chip/stm32f100_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f100_pinmap.h @@ -4,7 +4,7 @@ * Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (C) 2011 Uros Platise. All rights reserved. * Copyright (C) 2012 Michael Smith. All Rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * Uros Platise * * Redistribution and use in source and binary forms, with or without diff --git a/arch/arm/src/stm32/chip/stm32f103re_pinmap.h b/arch/arm/src/stm32/chip/stm32f103re_pinmap.h index d0b5a6386b42a09797dba0f8304ce7f5402f2087..042f57f74a4497da403ac13d5142490793bc6323 100644 --- a/arch/arm/src/stm32/chip/stm32f103re_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f103re_pinmap.h @@ -3,7 +3,7 @@ * * Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (C) 2011 Uros Platise. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * Uros Platise * * Redistribution and use in source and binary forms, with or without diff --git a/arch/arm/src/stm32/chip/stm32f105vb_pinmap.h b/arch/arm/src/stm32/chip/stm32f105vb_pinmap.h index fde8dd93587d3fbccefbfc1a332b6b166032d891..7a5ec3381efb169c4a0200b75b03bb0fac2d0e61 100644 --- a/arch/arm/src/stm32/chip/stm32f105vb_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f105vb_pinmap.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32f105vb_pinmap.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h b/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h index a7438a70ee833757703771615c91b234aa0d20c7..9bbc214798f18e10153cde3e03d8b04a86b88aaf 100644 --- a/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32f107vc_pinmap.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h index 88eb1ad6729e9bfcc33f05580e106f914e6fe746..ed1bc262592e93bad2ae4aaa05b5861a387b71b1 100644 --- a/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h +++ b/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h b/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h index c59cd565a20bed85b9d56bab801dc8a4909697ee..817e747f718227b43deafc32727870eca4c8f67c 100644 --- a/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h * * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h b/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h index aa7353ed9de54f7f8479ef7773dca2f7356d91f3..3a5f8bc6a13e9aa0f9225e77396164778d7dadc3 100644 --- a/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h +++ b/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32f40xxx_gpio.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h b/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h index fdfa9b323079f9233f2b39317af4758d412cabb0..a656cfda04c776cd7796360ac07ddb2f5f63f9d6 100644 --- a/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h +++ b/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/chip/stm32f40xxx_rtc.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/stm32_dbgmcu.h b/arch/arm/src/stm32/stm32_dbgmcu.h index 080f4bec5d3fcb9128d3b3a55bc3ab8156ab2919..5fb19218665bb1ebcfed347be7c335e902cf2d0c 100644 --- a/arch/arm/src/stm32/stm32_dbgmcu.h +++ b/arch/arm/src/stm32/stm32_dbgmcu.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_dbgmcu.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/stm32_eth.h b/arch/arm/src/stm32/stm32_eth.h index 188dc10d362527290bc1e0e5c32583b7bb30f188..f0c14b5b1f4055f7991f4713b2dc5967f38d8bc8 100644 --- a/arch/arm/src/stm32/stm32_eth.h +++ b/arch/arm/src/stm32/stm32_eth.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_eth.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/stm32_gpio.h b/arch/arm/src/stm32/stm32_gpio.h index 34623c5253022009c7b8b7d69ac156fa3c5cfc22..fde564cbbf7bb38f3c5972f73ad3ad7d70c6c8d6 100644 --- a/arch/arm/src/stm32/stm32_gpio.h +++ b/arch/arm/src/stm32/stm32_gpio.h @@ -3,7 +3,7 @@ * * Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved. * Copyright (C) 2011 Uros Platise. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * Uros Platise * * Redistribution and use in source and binary forms, with or without diff --git a/arch/arm/src/stm32/stm32_i2c.h b/arch/arm/src/stm32/stm32_i2c.h index 23a06bc05170d010b4df1a1dfeec5a0f59c74632..b914c4247bbff225539cb46fb84bd5b8ba500c88 100644 --- a/arch/arm/src/stm32/stm32_i2c.h +++ b/arch/arm/src/stm32/stm32_i2c.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_i2c.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/stm32_lowputc.h b/arch/arm/src/stm32/stm32_lowputc.h index edcc78d8f18947cc5b361dede18f4ed122053ca0..659de7b1c61cd7132cfe87ce19e327b1302e03b5 100644 --- a/arch/arm/src/stm32/stm32_lowputc.h +++ b/arch/arm/src/stm32/stm32_lowputc.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_lowputc.h * * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/stm32_pwr.h b/arch/arm/src/stm32/stm32_pwr.h index 56aee49b67c042bf74c2a705a627c526da0d9bcb..7a2751677ed08d66703b7182cb360b45f3311224 100644 --- a/arch/arm/src/stm32/stm32_pwr.h +++ b/arch/arm/src/stm32/stm32_pwr.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_pwr.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/stm32_spi.h b/arch/arm/src/stm32/stm32_spi.h index 268589bf35f794682726cc64d30edf3118590bca..6030ddfdd25733bd71ce144adc8de4fb537c2670 100644 --- a/arch/arm/src/stm32/stm32_spi.h +++ b/arch/arm/src/stm32/stm32_spi.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_spi.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/stm32_timerisr.c b/arch/arm/src/stm32/stm32_timerisr.c index 93cca02acab28e769029f93beb8bbbbe9974a1b6..ff649941566a18abe0b91feca0914513374d419e 100644 --- a/arch/arm/src/stm32/stm32_timerisr.c +++ b/arch/arm/src/stm32/stm32_timerisr.c @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_timerisr.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/stm32_usbdev.h b/arch/arm/src/stm32/stm32_usbdev.h index a1af471b25f3e125829134ab470fed02fd648ebc..587107dc8a487bcbdd1737b1e5329f044ed4f308 100644 --- a/arch/arm/src/stm32/stm32_usbdev.h +++ b/arch/arm/src/stm32/stm32_usbdev.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_usbdev.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/stm32_wdg.h b/arch/arm/src/stm32/stm32_wdg.h index 38af388f924e71953dc3b58ec25000a60c6213b6..fbb8128b55dbce7d726bb7d8d0f840bc92d69a5d 100644 --- a/arch/arm/src/stm32/stm32_wdg.h +++ b/arch/arm/src/stm32/stm32_wdg.h @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_wdg.h * * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/str71x/Make.defs b/arch/arm/src/str71x/Make.defs index 4ca4edff412a096482c1bdd6c5d71d49aa7e1175..545ce17352526caacba07ab95e84ca77f2c802d4 100644 --- a/arch/arm/src/str71x/Make.defs +++ b/arch/arm/src/str71x/Make.defs @@ -2,7 +2,7 @@ # arch/arm/src/str71x/Make.defs # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/arm/src/str71x/chip.h b/arch/arm/src/str71x/chip.h index 94514199304e03475f19b0b3cb2e5139ecf8ef25..af1da9ea861790d2a509a23fec879b1fdabf9b49 100644 --- a/arch/arm/src/str71x/chip.h +++ b/arch/arm/src/str71x/chip.h @@ -2,7 +2,7 @@ * arch/arm/src/str71x/chip.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/str71x/str71x_adc12.h b/arch/arm/src/str71x/str71x_adc12.h index 1f15adfb71843248ebb6128a93d6a6f0f6213640..1b982e0b18e2e02d192cd32a78b467251dc2cebd 100644 --- a/arch/arm/src/str71x/str71x_adc12.h +++ b/arch/arm/src/str71x/str71x_adc12.h @@ -1,109 +1,109 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_adc12.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_ADC12_H -#define __ARCH_ARM_SRC_STR71X_STR71X_ADC12_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "str71x_map.h" - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* ADC12 registers ******************************************************************/ - -#define STR71X_ADC12_DATA0 (STR71X_ADC12_BASE + 0x0000) /* 16-bits wide */ -#define STR71X_ADC12_DATA1 (STR71X_ADC12_BASE + 0x0008) /* 16-bits wide */ -#define STR71X_ADC12_DATA2 (STR71X_ADC12_BASE + 0x0010) /* 16-bits wide */ -#define STR71X_ADC12_DATA3 (STR71X_ADC12_BASE + 0x0018) /* 16-bits wide */ -#define STR71X_ADC12_CSR (STR71X_ADC12_BASE + 0x0020) /* 16-bits wide */ -#define STR71X_ADC12_CPR (STR71X_ADC12_BASE + 0x0030) /* 16-bits wide */ - -/* Register bit settings ************************************************************/ -/* ADC12 Conversion modes */ - -#define STR71X_ADC12_SINGLE (0) -#define STR71X_ADC12_ROUND (1) - -/* ADC12 Channels */ - -#define STR71X_ADC12_CHANNEL0 (0x00) -#define STR71X_ADC12_CHANNEL1 (0x10) -#define STR71X_ADC12_CHANNEL2 (0x20) -#define STR71X_ADC12_CHANNEL3 (0x30) - -/* ADC12 control status register */ - -#define STR71X_ADC12_DA0 (0x0001) -#define STR71X_ADC12_DA1 (0x0002) -#define STR71X_ADC12_DA2 (0x0004) -#define STR71X_ADC12_DA3 (0x0008) -#define STR71X_ADC12_OR (0x2000) - -/* Interrupt bits for channel n */ - -#define STR71X_ADC12_IT0 (0x0100) -#define STR71X_ADC12_IT1 (0x0200) -#define STR71X_ADC12_IT2 (0x0400) -#define STR71X_ADC12_IT3 (0x0800) -#define STR71X_ADC12_ITALL (0x0f00) - -/* Mode selection */ - -#define STR71X_ADC12_MODE (0x0040) - -/* Converter configuration */ - -#define STR71X_ADC12_START (0x0020) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STR71X_STR71X_ADC12_H */ +/************************************************************************************ + * arch/arm/src/str71x/str71x_adc12.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_ADC12_H +#define __ARCH_ARM_SRC_STR71X_STR71X_ADC12_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* ADC12 registers ******************************************************************/ + +#define STR71X_ADC12_DATA0 (STR71X_ADC12_BASE + 0x0000) /* 16-bits wide */ +#define STR71X_ADC12_DATA1 (STR71X_ADC12_BASE + 0x0008) /* 16-bits wide */ +#define STR71X_ADC12_DATA2 (STR71X_ADC12_BASE + 0x0010) /* 16-bits wide */ +#define STR71X_ADC12_DATA3 (STR71X_ADC12_BASE + 0x0018) /* 16-bits wide */ +#define STR71X_ADC12_CSR (STR71X_ADC12_BASE + 0x0020) /* 16-bits wide */ +#define STR71X_ADC12_CPR (STR71X_ADC12_BASE + 0x0030) /* 16-bits wide */ + +/* Register bit settings ************************************************************/ +/* ADC12 Conversion modes */ + +#define STR71X_ADC12_SINGLE (0) +#define STR71X_ADC12_ROUND (1) + +/* ADC12 Channels */ + +#define STR71X_ADC12_CHANNEL0 (0x00) +#define STR71X_ADC12_CHANNEL1 (0x10) +#define STR71X_ADC12_CHANNEL2 (0x20) +#define STR71X_ADC12_CHANNEL3 (0x30) + +/* ADC12 control status register */ + +#define STR71X_ADC12_DA0 (0x0001) +#define STR71X_ADC12_DA1 (0x0002) +#define STR71X_ADC12_DA2 (0x0004) +#define STR71X_ADC12_DA3 (0x0008) +#define STR71X_ADC12_OR (0x2000) + +/* Interrupt bits for channel n */ + +#define STR71X_ADC12_IT0 (0x0100) +#define STR71X_ADC12_IT1 (0x0200) +#define STR71X_ADC12_IT2 (0x0400) +#define STR71X_ADC12_IT3 (0x0800) +#define STR71X_ADC12_ITALL (0x0f00) + +/* Mode selection */ + +#define STR71X_ADC12_MODE (0x0040) + +/* Converter configuration */ + +#define STR71X_ADC12_START (0x0020) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_ADC12_H */ diff --git a/arch/arm/src/str71x/str71x_apb.h b/arch/arm/src/str71x/str71x_apb.h index 4b8efe2a92816c56df13c2fe40d55ba50b6b40ce..5ceee8ec963fe6ca8150ac4e07feca09d0a0b6d3 100644 --- a/arch/arm/src/str71x/str71x_apb.h +++ b/arch/arm/src/str71x/str71x_apb.h @@ -1,109 +1,109 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_apb.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_APB_H -#define __ARCH_ARM_SRC_STR71X_STR71X_APB_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "str71x_map.h" - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* APB register offsets *************************************************************/ - -#define STR71X_APB_CKDIS_OFFSET (0x0010) /* 32-bits wide */ -#define STR71X_APB_SWRES_OFFSET (0x0014) /* 32-bits wide */ - -/* APB register addresses ***********************************************************/ - -#define STR71X_APB1_CKDIS (STR71X_APB1_BASE + STR71X_APB_CKDIS_OFFSET) -#define STR71X_APB1_SWRES (STR71X_APB1_BASE + STR71X_APB_SWRES_OFFSET) - -#define STR71X_APB2_CKDIS (STR71X_APB2_BASE + STR71X_APB_CKDIS_OFFSET) -#define STR71X_APB2_SWRES (STR71X_APB2_BASE + STR71X_APB_SWRES_OFFSET) - -/* Register bit settings ***********************************************************/ - -/* APB1 periperals */ - -#define STR71X_APB1_I2C0 (0x0001) /* Bit 0: I2C0 */ -#define STR71X_APB1_I2C1 (0x0002) /* Bit 1: I2C1 */ -#define STR71X_APB1_UART0 (0x0008) /* Bit 3: UART0 */ -#define STR71X_APB1_UART1 (0x0010) /* Bit 4: UART1 */ -#define STR71X_APB1_UART2 (0x0020) /* Bit 5: UART2 */ -#define STR71X_APB1_UART3 (0x0040) /* Bit 6: UART3 */ -#define STR71X_APB1_USB (0x0080) /* Bit 7: USB */ -#define STR71X_APB1_CAN (0x0100) /* Bit 8: CAN */ -#define STR71X_APB1_BSPI0 (0x0200) /* Bit 9: BSPI0 */ -#define STR71X_APB1_BSPI1 (0x0400) /* Bit 10: BSPI1 */ -#define STR71X_APB1_HDLC (0x2000) /* Bit 13: HDLC */ -#define STR71X_APB1_APB1ALL (0x27fb) - -/* APB2 Peripherals */ - -#define STR71X_APB2_XTI (0x0001) /* Bit 0: XTI */ -#define STR71X_APB2_GPIO0 (0x0004) /* Bit 2: IOPORT0 */ -#define STR71X_APB2_GPIO1 (0x0008) /* Bit 3: IOPORT1 */ -#define STR71X_APB2_GPIO2 (0x0010) /* Bit 4: IOPORT2 */ -#define STR71X_APB2_ADC12 (0x0040) /* Bit 6: ADC */ -#define STR71X_APB2_CKOUT (0x0080) /* Bit 7: CKOUT */ -#define STR71X_APB2_TIM0 (0x0100) /* Bit 8: TIMER0 */ -#define STR71X_APB2_TIM1 (0x0200) /* Bit 9: TIMER1 */ -#define STR71X_APB2_TIM2 (0x0400) /* Bit 10: TIMER2 */ -#define STR71X_APB2_TIM3 (0x0800) /* Bit 11: TIMER3 */ -#define STR71X_APB2_RTC (0x1000) /* Bit 12: RTC */ -#define STR71X_APB2_EIC (0x4000) /* Bit 14: EIC */ -#define STR71X_APB2_APB2ALL (0x5fdd) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STR71X_STR71X_APB_H */ +/************************************************************************************ + * arch/arm/src/str71x/str71x_apb.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_APB_H +#define __ARCH_ARM_SRC_STR71X_STR71X_APB_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* APB register offsets *************************************************************/ + +#define STR71X_APB_CKDIS_OFFSET (0x0010) /* 32-bits wide */ +#define STR71X_APB_SWRES_OFFSET (0x0014) /* 32-bits wide */ + +/* APB register addresses ***********************************************************/ + +#define STR71X_APB1_CKDIS (STR71X_APB1_BASE + STR71X_APB_CKDIS_OFFSET) +#define STR71X_APB1_SWRES (STR71X_APB1_BASE + STR71X_APB_SWRES_OFFSET) + +#define STR71X_APB2_CKDIS (STR71X_APB2_BASE + STR71X_APB_CKDIS_OFFSET) +#define STR71X_APB2_SWRES (STR71X_APB2_BASE + STR71X_APB_SWRES_OFFSET) + +/* Register bit settings ***********************************************************/ + +/* APB1 periperals */ + +#define STR71X_APB1_I2C0 (0x0001) /* Bit 0: I2C0 */ +#define STR71X_APB1_I2C1 (0x0002) /* Bit 1: I2C1 */ +#define STR71X_APB1_UART0 (0x0008) /* Bit 3: UART0 */ +#define STR71X_APB1_UART1 (0x0010) /* Bit 4: UART1 */ +#define STR71X_APB1_UART2 (0x0020) /* Bit 5: UART2 */ +#define STR71X_APB1_UART3 (0x0040) /* Bit 6: UART3 */ +#define STR71X_APB1_USB (0x0080) /* Bit 7: USB */ +#define STR71X_APB1_CAN (0x0100) /* Bit 8: CAN */ +#define STR71X_APB1_BSPI0 (0x0200) /* Bit 9: BSPI0 */ +#define STR71X_APB1_BSPI1 (0x0400) /* Bit 10: BSPI1 */ +#define STR71X_APB1_HDLC (0x2000) /* Bit 13: HDLC */ +#define STR71X_APB1_APB1ALL (0x27fb) + +/* APB2 Peripherals */ + +#define STR71X_APB2_XTI (0x0001) /* Bit 0: XTI */ +#define STR71X_APB2_GPIO0 (0x0004) /* Bit 2: IOPORT0 */ +#define STR71X_APB2_GPIO1 (0x0008) /* Bit 3: IOPORT1 */ +#define STR71X_APB2_GPIO2 (0x0010) /* Bit 4: IOPORT2 */ +#define STR71X_APB2_ADC12 (0x0040) /* Bit 6: ADC */ +#define STR71X_APB2_CKOUT (0x0080) /* Bit 7: CKOUT */ +#define STR71X_APB2_TIM0 (0x0100) /* Bit 8: TIMER0 */ +#define STR71X_APB2_TIM1 (0x0200) /* Bit 9: TIMER1 */ +#define STR71X_APB2_TIM2 (0x0400) /* Bit 10: TIMER2 */ +#define STR71X_APB2_TIM3 (0x0800) /* Bit 11: TIMER3 */ +#define STR71X_APB2_RTC (0x1000) /* Bit 12: RTC */ +#define STR71X_APB2_EIC (0x4000) /* Bit 14: EIC */ +#define STR71X_APB2_APB2ALL (0x5fdd) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_APB_H */ diff --git a/arch/arm/src/str71x/str71x_bspi.h b/arch/arm/src/str71x/str71x_bspi.h index 537563c3d63695e9c5d207cf401392aedbf8c18f..f876ebb2b8ff79e1adfba6dbc58e98ac85ed9fb5 100644 --- a/arch/arm/src/str71x/str71x_bspi.h +++ b/arch/arm/src/str71x/str71x_bspi.h @@ -1,153 +1,153 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_bspi.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_BSPI_H -#define __ARCH_ARM_SRC_STR71X_STR71X_BSPI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "str71x_map.h" - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* Register Offsets *****************************************************************/ - -#define STR71X_BSPI_RXR_OFFSET (0x0000) /* 16-bits wide */ -#define STR71X_BSPI_TXR_OFFSET (0x0004) /* 16-bits wide */ -#define STR71X_BSPI_CSR1_OFFSET (0x0008) /* 16-bits wide */ -#define STR71X_BSPI_CSR2_OFFSET (0x000c) /* 16-bits wide */ -#define STR71X_BSPI_CLK_OFFSET (0x0010) /* 16-bits wide */ - -/* Registers ************************************************************************/ - -#define STR71X_BSPI_RXR(b) ((b) + STR71X_BSPI_RXR_OFFSET) -#define STR71X_BSPI_TXR(b) ((b) + STR71X_BSPI_TXR_OFFSET) -#define STR71X_BSPI_CSR1(b) ((b) + STR71X_BSPI_CSR1_OFFSET) -#define STR71X_BSPI_CSR2(b) ((b) + STR71X_BSPI_CSR2_OFFSET) -#define STR71X_BSPI_CLK(b) ((b) + STR71X_BSPI_CLK_OFFSET) - -#define STR71X_BSPI0_RXR (STR71X_BSPI0_BASE + STR71X_BSPI_RXR_OFFSET) -#define STR71X_BSPI0_TXR (STR71X_BSPI0_BASE + STR71X_BSPI_TXR_OFFSET) -#define STR71X_BSPI0_CSR1 (STR71X_BSPI0_BASE + STR71X_BSPI_CSR1_OFFSET) -#define STR71X_BSPI0_CSR2 (STR71X_BSPI0_BASE + STR71X_BSPI_CSR2_OFFSET) -#define STR71X_BSPI0_CLK (STR71X_BSPI0_BASE + STR71X_BSPI_CLK_OFFSET) - -#define STR71X_BSPI1_RXR (STR71X_BSPI1_BASE + STR71X_BSPI_RXR_OFFSET) -#define STR71X_BSPI1_TXR (STR71X_BSPI1_BASE + STR71X_BSPI_TXR_OFFSET) -#define STR71X_BSPI1_CSR1 (STR71X_BSPI1_BASE + STR71X_BSPI_CSR1_OFFSET) -#define STR71X_BSPI1_CSR2 (STR71X_BSPI1_BASE + STR71X_BSPI_CSR2_OFFSET) -#define STR71X_BSPI1_CLK (STR71X_BSPI1_BASE + STR71X_BSPI_CLK_OFFSET) - -/* Register bit settings ***********************************************************/ - -/* BSPI control/status register 1 */ - -#define STR71X_BSPICSR1_BSPE (1 << 0) /* Bit 0: BSPI enable */ -#define STR71X_BSPICSR1_MSTR (1 << 1) /* Bit 1: Master/Slave select */ -#define STR71X_BSPICSR1_RIESHIFT 2 /* Bit 2-3: BSPI receive interrupt enable */ -#define STR71X_BSPICSR1_RIEMASK (3 << STR71X_BSPICSR1_RIESHIFT) -#define STR71X_BSPICSR1_RIEDISABLED (0 << STR71X_BSPICSR1_RIESHIFT) /* Disabled */ -#define STR71X_BSPICSR1_RIERFNE (1 << STR71X_BSPICSR1_RIESHIFT) /* Receive FIFO not empty */ -#define STR71X_BSPICSR1_RIERFF (3 << STR71X_BSPICSR1_RIESHIFT) /* Receive FIFO full */ -#define STR71X_BSPICSR1_REIE (1 << 4) /* Bit 4: Receive error interrupt enable */ -#define STR71X_BSPICSR1_BEIE (1 << 7) /* Bit 7: Bus error interrupt enable */ -#define STR71X_BSPICSR1_CPOL (1 << 8) /* Bit 8: Clock polarity select */ -#define STR71X_BSPICSR1_CPHA (1 << 9) /* Bit 9: Clock phase select */ -#define STR71X_BSPICSR1_WLSHIFT 10 /* Bits 10-11: Word length */ -#define STR71X_BSPICSR1_WLMASK (3 << STR71X_BSPICSR1_WLSHIFT) -#define STR71X_BSPICSR1_WL8BIT (0 << STR71X_BSPICSR1_WLSHIFT) /* 8-bits */ -#define STR71X_BSPICSR1_WL16BIT (1 << STR71X_BSPICSR1_WLSHIFT) /* 16-bits */ -#define STR71X_BSPICSR1_RFESHIFT 12 /* Bits 12-15: Receive FIFO enable */ -#define STR71X_BSPICSR1_RFEMASK (15 << STR71X_BSPICSR1_RFESHIFT) -#define STR71X_BSPICSR1_RFE1 (0 << STR71X_BSPICSR1_RFESHIFT) /* Word 1 enabled */ -#define STR71X_BSPICSR1_RFE12 (1 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-2 enabled */ -#define STR71X_BSPICSR1_RFE13 (2 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-3 enabled */ -#define STR71X_BSPICSR1_RFE14 (3 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-4 enabled */ -#define STR71X_BSPICSR1_RFE15 (4 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-5 enabled */ -#define STR71X_BSPICSR1_RFE16 (5 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-6 enabled */ -#define STR71X_BSPICSR1_RFE17 (6 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-7 enabled */ -#define STR71X_BSPICSR1_RFE18 (7 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-8 enabled */ -#define STR71X_BSPICSR1_RFE19 (8 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-9 enabled */ -#define STR71X_BSPICSR1_RFE110 (9 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-10 enabled */ - -/* BSPI control/status register 2 */ - -#define STR71X_BSPICSR2_DFIFO (1 << 0) /* Bit 0: FIFO disable */ -#define STR71X_BSPICSR2_BERR (1 << 2) /* Bit 2: Bus error */ -#define STR71X_BSPICSR2_RFNE (1 << 3) /* Bit 3: Receiver FIFO not empty */ -#define STR71X_BSPICSR2_RFF (1 << 4) /* Bit 4: Receiver FIFO full */ -#define STR71X_BSPICSR2_ROFL (1 << 5) /* Bit 5: Receiver overflow */ -#define STR71X_BSPICSR2_TFE (1 << 6) /* Bit 6: Transmit FIFO empty */ -#define STR71X_BSPICSR2_TUFL (1 << 7) /* Bit 7: Transmit FIFO underflow */ -#define STR71X_BSPICSR2_TFF (1 << 8) /* Bit 8: Transmit FIFO full */ -#define STR71X_BSPICSR2_TFNE (1 << 9) /* Bit 9: Transmit FIFO not empty */ -#define STR71X_BSPICSR2_TFESHIFT 10 /* Bits 10-13: Transmit FIFO enable*/ -#define STR71X_BSPICSR2_TFEMASK (15 << STR71X_BSPICSR2_TFESHIFT) -#define STR71X_BSPICSR2_TFE1 (0 << STR71X_BSPICSR2_TFESHIFT) /* Word 1 enabled */ -#define STR71X_BSPICSR2_TFE12 (1 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-2 enabled */ -#define STR71X_BSPICSR2_TFE13 (2 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-3 enabled */ -#define STR71X_BSPICSR2_TFE14 (3 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-4 enabled */ -#define STR71X_BSPICSR2_TFE15 (4 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-5 enabled */ -#define STR71X_BSPICSR2_TFE16 (5 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-6 enabled */ -#define STR71X_BSPICSR2_TFE17 (6 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-7 enabled */ -#define STR71X_BSPICSR2_TFE18 (7 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-8 enabled */ -#define STR71X_BSPICSR2_TFE19 (8 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-9 enabled */ -#define STR71X_BSPICSR2_TFE110 (9 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-10 enabled */ -#define STR71X_BSPICSR2_TIESHIFT 14 /* Bit 14-15: BSPI transmit interrupt enable */ -#define STR71X_BSPICSR2_TIEMASK (3 << STR71X_BSPICSR2_TIESHIFT) -#define STR71X_BSPICSR2_TIEDISABLED (0 << STR71X_BSPICSR2_TIESHIFT) /* Disabled */ -#define STR71X_BSPICSR2_TIETFE (1 << STR71X_BSPICSR2_TIESHIFT) /* Interrupt on transmit FIFO empty */ -#define STR71X_BSPICSR2_TIETUFL (2 << STR71X_BSPICSR2_TIESHIFT) /* Interrupt on transmit underlow */ -#define STR71X_BSPICSR2_TIETFF (3 << STR71X_BSPICSR2_TIESHIFT) /* Interrupt on transmit FIFO full */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STR71X_STR71X_BSPI_H */ +/************************************************************************************ + * arch/arm/src/str71x/str71x_bspi.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_BSPI_H +#define __ARCH_ARM_SRC_STR71X_STR71X_BSPI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STR71X_BSPI_RXR_OFFSET (0x0000) /* 16-bits wide */ +#define STR71X_BSPI_TXR_OFFSET (0x0004) /* 16-bits wide */ +#define STR71X_BSPI_CSR1_OFFSET (0x0008) /* 16-bits wide */ +#define STR71X_BSPI_CSR2_OFFSET (0x000c) /* 16-bits wide */ +#define STR71X_BSPI_CLK_OFFSET (0x0010) /* 16-bits wide */ + +/* Registers ************************************************************************/ + +#define STR71X_BSPI_RXR(b) ((b) + STR71X_BSPI_RXR_OFFSET) +#define STR71X_BSPI_TXR(b) ((b) + STR71X_BSPI_TXR_OFFSET) +#define STR71X_BSPI_CSR1(b) ((b) + STR71X_BSPI_CSR1_OFFSET) +#define STR71X_BSPI_CSR2(b) ((b) + STR71X_BSPI_CSR2_OFFSET) +#define STR71X_BSPI_CLK(b) ((b) + STR71X_BSPI_CLK_OFFSET) + +#define STR71X_BSPI0_RXR (STR71X_BSPI0_BASE + STR71X_BSPI_RXR_OFFSET) +#define STR71X_BSPI0_TXR (STR71X_BSPI0_BASE + STR71X_BSPI_TXR_OFFSET) +#define STR71X_BSPI0_CSR1 (STR71X_BSPI0_BASE + STR71X_BSPI_CSR1_OFFSET) +#define STR71X_BSPI0_CSR2 (STR71X_BSPI0_BASE + STR71X_BSPI_CSR2_OFFSET) +#define STR71X_BSPI0_CLK (STR71X_BSPI0_BASE + STR71X_BSPI_CLK_OFFSET) + +#define STR71X_BSPI1_RXR (STR71X_BSPI1_BASE + STR71X_BSPI_RXR_OFFSET) +#define STR71X_BSPI1_TXR (STR71X_BSPI1_BASE + STR71X_BSPI_TXR_OFFSET) +#define STR71X_BSPI1_CSR1 (STR71X_BSPI1_BASE + STR71X_BSPI_CSR1_OFFSET) +#define STR71X_BSPI1_CSR2 (STR71X_BSPI1_BASE + STR71X_BSPI_CSR2_OFFSET) +#define STR71X_BSPI1_CLK (STR71X_BSPI1_BASE + STR71X_BSPI_CLK_OFFSET) + +/* Register bit settings ***********************************************************/ + +/* BSPI control/status register 1 */ + +#define STR71X_BSPICSR1_BSPE (1 << 0) /* Bit 0: BSPI enable */ +#define STR71X_BSPICSR1_MSTR (1 << 1) /* Bit 1: Master/Slave select */ +#define STR71X_BSPICSR1_RIESHIFT 2 /* Bit 2-3: BSPI receive interrupt enable */ +#define STR71X_BSPICSR1_RIEMASK (3 << STR71X_BSPICSR1_RIESHIFT) +#define STR71X_BSPICSR1_RIEDISABLED (0 << STR71X_BSPICSR1_RIESHIFT) /* Disabled */ +#define STR71X_BSPICSR1_RIERFNE (1 << STR71X_BSPICSR1_RIESHIFT) /* Receive FIFO not empty */ +#define STR71X_BSPICSR1_RIERFF (3 << STR71X_BSPICSR1_RIESHIFT) /* Receive FIFO full */ +#define STR71X_BSPICSR1_REIE (1 << 4) /* Bit 4: Receive error interrupt enable */ +#define STR71X_BSPICSR1_BEIE (1 << 7) /* Bit 7: Bus error interrupt enable */ +#define STR71X_BSPICSR1_CPOL (1 << 8) /* Bit 8: Clock polarity select */ +#define STR71X_BSPICSR1_CPHA (1 << 9) /* Bit 9: Clock phase select */ +#define STR71X_BSPICSR1_WLSHIFT 10 /* Bits 10-11: Word length */ +#define STR71X_BSPICSR1_WLMASK (3 << STR71X_BSPICSR1_WLSHIFT) +#define STR71X_BSPICSR1_WL8BIT (0 << STR71X_BSPICSR1_WLSHIFT) /* 8-bits */ +#define STR71X_BSPICSR1_WL16BIT (1 << STR71X_BSPICSR1_WLSHIFT) /* 16-bits */ +#define STR71X_BSPICSR1_RFESHIFT 12 /* Bits 12-15: Receive FIFO enable */ +#define STR71X_BSPICSR1_RFEMASK (15 << STR71X_BSPICSR1_RFESHIFT) +#define STR71X_BSPICSR1_RFE1 (0 << STR71X_BSPICSR1_RFESHIFT) /* Word 1 enabled */ +#define STR71X_BSPICSR1_RFE12 (1 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-2 enabled */ +#define STR71X_BSPICSR1_RFE13 (2 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-3 enabled */ +#define STR71X_BSPICSR1_RFE14 (3 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-4 enabled */ +#define STR71X_BSPICSR1_RFE15 (4 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-5 enabled */ +#define STR71X_BSPICSR1_RFE16 (5 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-6 enabled */ +#define STR71X_BSPICSR1_RFE17 (6 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-7 enabled */ +#define STR71X_BSPICSR1_RFE18 (7 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-8 enabled */ +#define STR71X_BSPICSR1_RFE19 (8 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-9 enabled */ +#define STR71X_BSPICSR1_RFE110 (9 << STR71X_BSPICSR1_RFESHIFT) /* Word 1-10 enabled */ + +/* BSPI control/status register 2 */ + +#define STR71X_BSPICSR2_DFIFO (1 << 0) /* Bit 0: FIFO disable */ +#define STR71X_BSPICSR2_BERR (1 << 2) /* Bit 2: Bus error */ +#define STR71X_BSPICSR2_RFNE (1 << 3) /* Bit 3: Receiver FIFO not empty */ +#define STR71X_BSPICSR2_RFF (1 << 4) /* Bit 4: Receiver FIFO full */ +#define STR71X_BSPICSR2_ROFL (1 << 5) /* Bit 5: Receiver overflow */ +#define STR71X_BSPICSR2_TFE (1 << 6) /* Bit 6: Transmit FIFO empty */ +#define STR71X_BSPICSR2_TUFL (1 << 7) /* Bit 7: Transmit FIFO underflow */ +#define STR71X_BSPICSR2_TFF (1 << 8) /* Bit 8: Transmit FIFO full */ +#define STR71X_BSPICSR2_TFNE (1 << 9) /* Bit 9: Transmit FIFO not empty */ +#define STR71X_BSPICSR2_TFESHIFT 10 /* Bits 10-13: Transmit FIFO enable*/ +#define STR71X_BSPICSR2_TFEMASK (15 << STR71X_BSPICSR2_TFESHIFT) +#define STR71X_BSPICSR2_TFE1 (0 << STR71X_BSPICSR2_TFESHIFT) /* Word 1 enabled */ +#define STR71X_BSPICSR2_TFE12 (1 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-2 enabled */ +#define STR71X_BSPICSR2_TFE13 (2 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-3 enabled */ +#define STR71X_BSPICSR2_TFE14 (3 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-4 enabled */ +#define STR71X_BSPICSR2_TFE15 (4 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-5 enabled */ +#define STR71X_BSPICSR2_TFE16 (5 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-6 enabled */ +#define STR71X_BSPICSR2_TFE17 (6 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-7 enabled */ +#define STR71X_BSPICSR2_TFE18 (7 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-8 enabled */ +#define STR71X_BSPICSR2_TFE19 (8 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-9 enabled */ +#define STR71X_BSPICSR2_TFE110 (9 << STR71X_BSPICSR2_TFESHIFT) /* Word 1-10 enabled */ +#define STR71X_BSPICSR2_TIESHIFT 14 /* Bit 14-15: BSPI transmit interrupt enable */ +#define STR71X_BSPICSR2_TIEMASK (3 << STR71X_BSPICSR2_TIESHIFT) +#define STR71X_BSPICSR2_TIEDISABLED (0 << STR71X_BSPICSR2_TIESHIFT) /* Disabled */ +#define STR71X_BSPICSR2_TIETFE (1 << STR71X_BSPICSR2_TIESHIFT) /* Interrupt on transmit FIFO empty */ +#define STR71X_BSPICSR2_TIETUFL (2 << STR71X_BSPICSR2_TIESHIFT) /* Interrupt on transmit underlow */ +#define STR71X_BSPICSR2_TIETFF (3 << STR71X_BSPICSR2_TIESHIFT) /* Interrupt on transmit FIFO full */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_BSPI_H */ diff --git a/arch/arm/src/str71x/str71x_can.h b/arch/arm/src/str71x/str71x_can.h index a38630d660d55f568da19f63347d14ceedeedce8..a891b60dc64285f36f6d6242bcc5e3960a0304e1 100644 --- a/arch/arm/src/str71x/str71x_can.h +++ b/arch/arm/src/str71x/str71x_can.h @@ -1,207 +1,207 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_can.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_CAN_H -#define __ARCH_ARM_SRC_STR71X_STR71X_CAN_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "str71x_map.h" - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* Registers ************************************************************************/ - -#define STR71X_CAN_CR (STR71X_CAN_BASE + 0x0000) /* 16-bits wide */ -#define STR71X_CAN_SR (STR71X_CAN_BASE + 0x0004) /* 16-bits wide */ -#define STR71X_CAN_ERR (STR71X_CAN_BASE + 0x0008) /* 16-bits wide */ -#define STR71X_CAN_BTR (STR71X_CAN_BASE + 0x000c) /* 16-bits wide */ -#define STR71X_CAN_IDR (STR71X_CAN_BASE + 0x0010) /* 16-bits wide */ -#define STR71X_CAN_TESTR (STR71X_CAN_BASE + 0x0014) /* 16-bits wide */ -#define STR71X_CAN_BRPR (STR71X_CAN_BASE + 0x0018) /* 16-bits wide */ - -#define STR71X_CAN_IF1BASE (STR71X_CAN_BASE + 0x0020) -#define STR71X_CAN_IF2BASE (STR71X_CAN_BASE + 0x0080) - -#define STR71X_CAN_CRR_OFFSET (0x0000) /* 16-bits wide */ -#define STR71X_CAN_CMR_OFFSET (0x0004) /* 16-bits wide */ -#define STR71X_CAN_M1R_OFFSET (0x0008) /* 16-bits wide */ -#define STR71X_CAN_M2R_OFFSET (0x000c) /* 16-bits wide */ -#define STR71X_CAN_A1R_OFFSET (0x0010) /* 16-bits wide */ -#define STR71X_CAN_A2R_OFFSET (0x0014) /* 16-bits wide */ -#define STR71X_CAN_MCR_OFFSET (0x0018) /* 16-bits wide */ -#define STR71X_CAN_DA1R_OFFSET (0x001c) /* 16-bits wide */ -#define STR71X_CAN_DA2R_OFFSET (0x0020) /* 16-bits wide */ -#define STR71X_CAN_DB1R_OFFSET (0x0024) /* 16-bits wide */ -#define STR71X_CAN_DB2R_OFFSET (0x0028) /* 16-bits wide */ - -#define STR71X_CAN_CRR(b) ((b) + STR71X_CAN_CRR_OFFSET) -#define STR71X_CAN_CMR(b) ((b) + STR71X_CAN_CMR_OFFSET) -#define STR71X_CAN_M1R(b) ((b) + STR71X_CAN_M1R_OFFSET) -#define STR71X_CAN_M2R(b) ((b) + STR71X_CAN_M2R_OFFSET) -#define STR71X_CAN_A1R(b) ((b) + STR71X_CAN_A1R_OFFSET) -#define STR71X_CAN_A2R(b) ((b) + STR71X_CAN_A2R_OFFSET) -#define STR71X_CAN_MCR(b) ((b) + STR71X_CAN_MCR_OFFSET) -#define STR71X_CAN_DA1R(b) ((b) + STR71X_CAN_DA1R_OFFSET) -#define STR71X_CAN_DA2R(b) ((b) + STR71X_CAN_DA2R_OFFSET) -#define STR71X_CAN_DB1R(b) ((b) + STR71X_CAN_DB1R_OFFSET) -#define STR71X_CAN_DB2R(b) ((b) + STR71X_CAN_DB2R_OFFSET) - -#define STR71X_CAN_IF1CRR (STR71X_CAN_IF1BASE + STR71X_CAN_CRR_OFFSET) -#define STR71X_CAN_IF1CMR (STR71X_CAN_IF1BASE + STR71X_CAN_CMR_OFFSET) -#define STR71X_CAN_IF1M1R (STR71X_CAN_IF1BASE + STR71X_CAN_M1R_OFFSET) -#define STR71X_CAN_IF1M2R (STR71X_CAN_IF1BASE + STR71X_CAN_M2R_OFFSET) -#define STR71X_CAN_IF1A1R (STR71X_CAN_IF1BASE + STR71X_CAN_A1R_OFFSET) -#define STR71X_CAN_IF1A2R (STR71X_CAN_IF1BASE + STR71X_CAN_A2R_OFFSET) -#define STR71X_CAN_IF1MCR (STR71X_CAN_IF1BASE + STR71X_CAN_MCR_OFFSET) -#define STR71X_CAN_IF1DA1R (STR71X_CAN_IF1BASE + STR71X_CAN_DA1R_OFFSET) -#define STR71X_CAN_IF1DA2R (STR71X_CAN_IF1BASE + STR71X_CAN_DA2R_OFFSET) -#define STR71X_CAN_IF1DB1R (STR71X_CAN_IF1BASE + STR71X_CAN_DB1R_OFFSET) -#define STR71X_CAN_IF1DB2R (STR71X_CAN_IF1BASE + STR71X_CAN_DB2R_OFFSET) - -#define STR71X_CAN_IF2CRR (STR71X_CAN_IF2BASE + STR71X_CAN_CRR_OFFSET) -#define STR71X_CAN_IF2CMR (STR71X_CAN_IF2BASE + STR71X_CAN_CMR_OFFSET) -#define STR71X_CAN_IF2M1R (STR71X_CAN_IF2BASE + STR71X_CAN_M1R_OFFSET) -#define STR71X_CAN_IF2M2R (STR71X_CAN_IF2BASE + STR71X_CAN_M2R_OFFSET) -#define STR71X_CAN_IF2A1R (STR71X_CAN_IF2BASE + STR71X_CAN_A1R_OFFSET) -#define STR71X_CAN_IF2A2R (STR71X_CAN_IF2BASE + STR71X_CAN_A2R_OFFSET) -#define STR71X_CAN_IF2MCR (STR71X_CAN_IF2BASE + STR71X_CAN_MCR_OFFSET) -#define STR71X_CAN_IF2DA1R (STR71X_CAN_IF2BASE + STR71X_CAN_DA1R_OFFSET) -#define STR71X_CAN_IF2DA2R (STR71X_CAN_IF2BASE + STR71X_CAN_DA2R_OFFSET) -#define STR71X_CAN_IF2DB1R (STR71X_CAN_IF2BASE + STR71X_CAN_DB1R_OFFSET) -#define STR71X_CAN_IF2DB2R (STR71X_CAN_IF2BASE + STR71X_CAN_DB2R_OFFSET) - -#define STR71X_CAN_TR1R (STR71X_CAN_BASE + 0x0100) /* 16-bits wide */ -#define STR71X_CAN_TR2R (STR71X_CAN_BASE + 0x0104) /* 16-bits wide */ -#define STR71X_CAN_ND1R (STR71X_CAN_BASE + 0x0120) /* 16-bits wide */ -#define STR71X_CAN_ND2R (STR71X_CAN_BASE + 0x0124) /* 16-bits wide */ -#define STR71X_CAN_IP1R (STR71X_CAN_BASE + 0x0140) /* 16-bits wide */ -#define STR71X_CAN_IP2R (STR71X_CAN_BASE + 0x0144) /* 16-bits wide */ -#define STR71X_CAN_MV1R (STR71X_CAN_BASE + 0x0160) /* 16-bits wide */ -#define STR71X_CAN_MV2R (STR71X_CAN_BASE + 0x0164) /* 16-bits wide */ - -/* Register bit settings ***********************************************************/ - -/* Control register */ - -#define STR41X_CANCR_INIT (0x0001) -#define STR41X_CANCR_IE (0x0002) -#define STR41X_CANCR_SIE (0x0004) -#define STR41X_CANCR_EIE (0x0008) -#define STR41X_CANCR_DAR (0x0020) -#define STR41X_CANCR_CCE (0x0040) -#define STR41X_CANCR_TEST (0x0080) - -/* Status register */ - -#define STR41X_CANSR_LEC (0x0007) -#define STR41X_CANSR_TXOK (0x0008) -#define STR41X_CANSR_RXOK (0x0010) -#define STR41X_CANSR_EPASS (0x0020) -#define STR41X_CANSR_EWARN (0x0040) -#define STR41X_CANSR_BOFF (0x0080) - -/* Test register */ - -#define STR41X_CANTESTR_BASIC (0x0004) -#define STR41X_CANTESTR_SILENT (0x0008) -#define STR41X_CANTESTR_LBACK (0x0010) -#define STR41X_CANTESTR_TX0 (0x0020) -#define STR41X_CANTESTR_TX1 (0x0040) -#define STR41X_CANTESTR_RX (0x0080) - -/* IFn / Command Request register */ - -#define STR41X_CANCRR_BUSY (0x8000) - -/* IFn / Command Mask register */ - -#define STR41X_CANCMR_DATAB (0x0001) -#define STR41X_CANCMR_DATAA (0x0002) -#define STR41X_CANCMR_TXRQST (0x0004) -#define STR41X_CANCMR_CLRINTPND (0x0008) -#define STR41X_CANCMR_CONTROL (0x0010) -#define STR41X_CANCMR_ARB (0x0020) -#define STR41X_CANCMR_MASK (0x0040) -#define STR41X_CANCMR_WRRD (0x0080) - -/* IFn / Mask 2 register */ - -#define STR41X_CANM2R_MXTD (0x8000) -#define STR41X_CANM2R_MDIR (0x4000) - -/* IFn / Arbitration 2 register */ - -#define STR41X_CANA2R_DIR (0x2000) -#define STR41X_CANA2R_XTD (0x4000) -#define STR41X_CANA2R_MSGVAL (0x8000) - -/* IFn / Message Control register */ - -#define STR41X_CANMCR_EOB (0x0080) -#define STR41X_CANMCR_TXRQST (0x0100) -#define STR41X_CANMCR_RMTEN (0x0200) -#define STR41X_CANMCR_RXIE (0x0400) -#define STR41X_CANMCR_TXIE (0x0800) -#define STR41X_CANMCR_UMASK (0x1000) -#define STR41X_CANMCR_INTPND (0x2000) -#define STR41X_CANMCR_MSGLST (0x4000) -#define STR41X_CANMCR_NEWDAT (0x8000) - -/* Message ID limits */ - -#define STR41X_CAN_LASTSTDID ((1 << 11) - 1) -#define STR41X_CAN_LASTEXTID ((1 << 29) - 1) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STR71X_STR71X_CAN_H */ - +/************************************************************************************ + * arch/arm/src/str71x/str71x_can.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_CAN_H +#define __ARCH_ARM_SRC_STR71X_STR71X_CAN_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Registers ************************************************************************/ + +#define STR71X_CAN_CR (STR71X_CAN_BASE + 0x0000) /* 16-bits wide */ +#define STR71X_CAN_SR (STR71X_CAN_BASE + 0x0004) /* 16-bits wide */ +#define STR71X_CAN_ERR (STR71X_CAN_BASE + 0x0008) /* 16-bits wide */ +#define STR71X_CAN_BTR (STR71X_CAN_BASE + 0x000c) /* 16-bits wide */ +#define STR71X_CAN_IDR (STR71X_CAN_BASE + 0x0010) /* 16-bits wide */ +#define STR71X_CAN_TESTR (STR71X_CAN_BASE + 0x0014) /* 16-bits wide */ +#define STR71X_CAN_BRPR (STR71X_CAN_BASE + 0x0018) /* 16-bits wide */ + +#define STR71X_CAN_IF1BASE (STR71X_CAN_BASE + 0x0020) +#define STR71X_CAN_IF2BASE (STR71X_CAN_BASE + 0x0080) + +#define STR71X_CAN_CRR_OFFSET (0x0000) /* 16-bits wide */ +#define STR71X_CAN_CMR_OFFSET (0x0004) /* 16-bits wide */ +#define STR71X_CAN_M1R_OFFSET (0x0008) /* 16-bits wide */ +#define STR71X_CAN_M2R_OFFSET (0x000c) /* 16-bits wide */ +#define STR71X_CAN_A1R_OFFSET (0x0010) /* 16-bits wide */ +#define STR71X_CAN_A2R_OFFSET (0x0014) /* 16-bits wide */ +#define STR71X_CAN_MCR_OFFSET (0x0018) /* 16-bits wide */ +#define STR71X_CAN_DA1R_OFFSET (0x001c) /* 16-bits wide */ +#define STR71X_CAN_DA2R_OFFSET (0x0020) /* 16-bits wide */ +#define STR71X_CAN_DB1R_OFFSET (0x0024) /* 16-bits wide */ +#define STR71X_CAN_DB2R_OFFSET (0x0028) /* 16-bits wide */ + +#define STR71X_CAN_CRR(b) ((b) + STR71X_CAN_CRR_OFFSET) +#define STR71X_CAN_CMR(b) ((b) + STR71X_CAN_CMR_OFFSET) +#define STR71X_CAN_M1R(b) ((b) + STR71X_CAN_M1R_OFFSET) +#define STR71X_CAN_M2R(b) ((b) + STR71X_CAN_M2R_OFFSET) +#define STR71X_CAN_A1R(b) ((b) + STR71X_CAN_A1R_OFFSET) +#define STR71X_CAN_A2R(b) ((b) + STR71X_CAN_A2R_OFFSET) +#define STR71X_CAN_MCR(b) ((b) + STR71X_CAN_MCR_OFFSET) +#define STR71X_CAN_DA1R(b) ((b) + STR71X_CAN_DA1R_OFFSET) +#define STR71X_CAN_DA2R(b) ((b) + STR71X_CAN_DA2R_OFFSET) +#define STR71X_CAN_DB1R(b) ((b) + STR71X_CAN_DB1R_OFFSET) +#define STR71X_CAN_DB2R(b) ((b) + STR71X_CAN_DB2R_OFFSET) + +#define STR71X_CAN_IF1CRR (STR71X_CAN_IF1BASE + STR71X_CAN_CRR_OFFSET) +#define STR71X_CAN_IF1CMR (STR71X_CAN_IF1BASE + STR71X_CAN_CMR_OFFSET) +#define STR71X_CAN_IF1M1R (STR71X_CAN_IF1BASE + STR71X_CAN_M1R_OFFSET) +#define STR71X_CAN_IF1M2R (STR71X_CAN_IF1BASE + STR71X_CAN_M2R_OFFSET) +#define STR71X_CAN_IF1A1R (STR71X_CAN_IF1BASE + STR71X_CAN_A1R_OFFSET) +#define STR71X_CAN_IF1A2R (STR71X_CAN_IF1BASE + STR71X_CAN_A2R_OFFSET) +#define STR71X_CAN_IF1MCR (STR71X_CAN_IF1BASE + STR71X_CAN_MCR_OFFSET) +#define STR71X_CAN_IF1DA1R (STR71X_CAN_IF1BASE + STR71X_CAN_DA1R_OFFSET) +#define STR71X_CAN_IF1DA2R (STR71X_CAN_IF1BASE + STR71X_CAN_DA2R_OFFSET) +#define STR71X_CAN_IF1DB1R (STR71X_CAN_IF1BASE + STR71X_CAN_DB1R_OFFSET) +#define STR71X_CAN_IF1DB2R (STR71X_CAN_IF1BASE + STR71X_CAN_DB2R_OFFSET) + +#define STR71X_CAN_IF2CRR (STR71X_CAN_IF2BASE + STR71X_CAN_CRR_OFFSET) +#define STR71X_CAN_IF2CMR (STR71X_CAN_IF2BASE + STR71X_CAN_CMR_OFFSET) +#define STR71X_CAN_IF2M1R (STR71X_CAN_IF2BASE + STR71X_CAN_M1R_OFFSET) +#define STR71X_CAN_IF2M2R (STR71X_CAN_IF2BASE + STR71X_CAN_M2R_OFFSET) +#define STR71X_CAN_IF2A1R (STR71X_CAN_IF2BASE + STR71X_CAN_A1R_OFFSET) +#define STR71X_CAN_IF2A2R (STR71X_CAN_IF2BASE + STR71X_CAN_A2R_OFFSET) +#define STR71X_CAN_IF2MCR (STR71X_CAN_IF2BASE + STR71X_CAN_MCR_OFFSET) +#define STR71X_CAN_IF2DA1R (STR71X_CAN_IF2BASE + STR71X_CAN_DA1R_OFFSET) +#define STR71X_CAN_IF2DA2R (STR71X_CAN_IF2BASE + STR71X_CAN_DA2R_OFFSET) +#define STR71X_CAN_IF2DB1R (STR71X_CAN_IF2BASE + STR71X_CAN_DB1R_OFFSET) +#define STR71X_CAN_IF2DB2R (STR71X_CAN_IF2BASE + STR71X_CAN_DB2R_OFFSET) + +#define STR71X_CAN_TR1R (STR71X_CAN_BASE + 0x0100) /* 16-bits wide */ +#define STR71X_CAN_TR2R (STR71X_CAN_BASE + 0x0104) /* 16-bits wide */ +#define STR71X_CAN_ND1R (STR71X_CAN_BASE + 0x0120) /* 16-bits wide */ +#define STR71X_CAN_ND2R (STR71X_CAN_BASE + 0x0124) /* 16-bits wide */ +#define STR71X_CAN_IP1R (STR71X_CAN_BASE + 0x0140) /* 16-bits wide */ +#define STR71X_CAN_IP2R (STR71X_CAN_BASE + 0x0144) /* 16-bits wide */ +#define STR71X_CAN_MV1R (STR71X_CAN_BASE + 0x0160) /* 16-bits wide */ +#define STR71X_CAN_MV2R (STR71X_CAN_BASE + 0x0164) /* 16-bits wide */ + +/* Register bit settings ***********************************************************/ + +/* Control register */ + +#define STR41X_CANCR_INIT (0x0001) +#define STR41X_CANCR_IE (0x0002) +#define STR41X_CANCR_SIE (0x0004) +#define STR41X_CANCR_EIE (0x0008) +#define STR41X_CANCR_DAR (0x0020) +#define STR41X_CANCR_CCE (0x0040) +#define STR41X_CANCR_TEST (0x0080) + +/* Status register */ + +#define STR41X_CANSR_LEC (0x0007) +#define STR41X_CANSR_TXOK (0x0008) +#define STR41X_CANSR_RXOK (0x0010) +#define STR41X_CANSR_EPASS (0x0020) +#define STR41X_CANSR_EWARN (0x0040) +#define STR41X_CANSR_BOFF (0x0080) + +/* Test register */ + +#define STR41X_CANTESTR_BASIC (0x0004) +#define STR41X_CANTESTR_SILENT (0x0008) +#define STR41X_CANTESTR_LBACK (0x0010) +#define STR41X_CANTESTR_TX0 (0x0020) +#define STR41X_CANTESTR_TX1 (0x0040) +#define STR41X_CANTESTR_RX (0x0080) + +/* IFn / Command Request register */ + +#define STR41X_CANCRR_BUSY (0x8000) + +/* IFn / Command Mask register */ + +#define STR41X_CANCMR_DATAB (0x0001) +#define STR41X_CANCMR_DATAA (0x0002) +#define STR41X_CANCMR_TXRQST (0x0004) +#define STR41X_CANCMR_CLRINTPND (0x0008) +#define STR41X_CANCMR_CONTROL (0x0010) +#define STR41X_CANCMR_ARB (0x0020) +#define STR41X_CANCMR_MASK (0x0040) +#define STR41X_CANCMR_WRRD (0x0080) + +/* IFn / Mask 2 register */ + +#define STR41X_CANM2R_MXTD (0x8000) +#define STR41X_CANM2R_MDIR (0x4000) + +/* IFn / Arbitration 2 register */ + +#define STR41X_CANA2R_DIR (0x2000) +#define STR41X_CANA2R_XTD (0x4000) +#define STR41X_CANA2R_MSGVAL (0x8000) + +/* IFn / Message Control register */ + +#define STR41X_CANMCR_EOB (0x0080) +#define STR41X_CANMCR_TXRQST (0x0100) +#define STR41X_CANMCR_RMTEN (0x0200) +#define STR41X_CANMCR_RXIE (0x0400) +#define STR41X_CANMCR_TXIE (0x0800) +#define STR41X_CANMCR_UMASK (0x1000) +#define STR41X_CANMCR_INTPND (0x2000) +#define STR41X_CANMCR_MSGLST (0x4000) +#define STR41X_CANMCR_NEWDAT (0x8000) + +/* Message ID limits */ + +#define STR41X_CAN_LASTSTDID ((1 << 11) - 1) +#define STR41X_CAN_LASTEXTID ((1 << 29) - 1) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_CAN_H */ + diff --git a/arch/arm/src/str71x/str71x_decodeirq.c b/arch/arm/src/str71x/str71x_decodeirq.c index 8a24ea44d7d1ac18308fe54bec98fad17f7ff447..326abd763aeb688282abdf9f80f9c5621eff1af5 100644 --- a/arch/arm/src/str71x/str71x_decodeirq.c +++ b/arch/arm/src/str71x/str71x_decodeirq.c @@ -2,7 +2,7 @@ * arch/arm/src/str71x/str71x_decodeirq.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/str71x/str71x_eic.h b/arch/arm/src/str71x/str71x_eic.h index 7b0301695a4818b6d1dbf3c3a887f1a1193de7cb..c45cfaa6bc0bc72e7e06a9ba069bf6aac36da698 100644 --- a/arch/arm/src/str71x/str71x_eic.h +++ b/arch/arm/src/str71x/str71x_eic.h @@ -1,176 +1,176 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_eic.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_EIC_H -#define __ARCH_ARM_SRC_STR71X_STR71X_EIC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* Enhanced Interupt Controller (EIC) register offsets ******************************/ - -#define STR71X_EIC_ICR_OFFSET (0x0000) /* 32-bits wide */ -#define STR71X_EIC_CICR_OFFSET (0x0004) /* 32-bits wide */ -#define STR71X_EIC_CIPR_OFFSET (0x0008) /* 32-bits wide */ -#define STR71X_EIC_IVR_OFFSET (0x0018) /* 32-bits wide */ -#define STR71X_EIC_FIR_OFFSET (0x001c) /* 32-bits wide */ -#define STR71X_EIC_IER_OFFSET (0x0020) /* 32-bits wide */ -#define STR71X_EIC_IPR_OFFSET (0x0040) /* 32-bits wide */ - -#define STR71X_EIC_SIR_OFFSET (0x0060) /* 32 x 32-bits */ -#define STR71X_EIC_SIR0_OFFSET (0x0060) /* 32-bits wide */ -#define STR71X_EIC_SIR1_OFFSET (0x0064) /* 32-bits wide */ -#define STR71X_EIC_SIR2_OFFSET (0x0068) /* 32-bits wide */ -#define STR71X_EIC_SIR3_OFFSET (0x006c) /* 32-bits wide */ -#define STR71X_EIC_SIR4_OFFSET (0x0070) /* 32-bits wide */ -#define STR71X_EIC_SIR5_OFFSET (0x0074) /* 32-bits wide */ -#define STR71X_EIC_SIR6_OFFSET (0x0078) /* 32-bits wide */ -#define STR71X_EIC_SIR7_OFFSET (0x007c) /* 32-bits wide */ -#define STR71X_EIC_SIR8_OFFSET (0x0080) /* 32-bits wide */ -#define STR71X_EIC_SIR9_OFFSET (0x0084) /* 32-bits wide */ -#define STR71X_EIC_SIR10_OFFSET (0x0088) /* 32-bits wide */ -#define STR71X_EIC_SIR11_OFFSET (0x008c) /* 32-bits wide */ -#define STR71X_EIC_SIR12_OFFSET (0x0090) /* 32-bits wide */ -#define STR71X_EIC_SIR13_OFFSET (0x0094) /* 32-bits wide */ -#define STR71X_EIC_SIR14_OFFSET (0x0098) /* 32-bits wide */ -#define STR71X_EIC_SIR15_OFFSET (0x009c) /* 32-bits wide */ -#define STR71X_EIC_SIR16_OFFSET (0x00a0) /* 32-bits wide */ -#define STR71X_EIC_SIR17_OFFSET (0x00a4) /* 32-bits wide */ -#define STR71X_EIC_SIR18_OFFSET (0x00a8) /* 32-bits wide */ -#define STR71X_EIC_SIR19_OFFSET (0x00ac) /* 32-bits wide */ -#define STR71X_EIC_SIR20_OFFSET (0x00b0) /* 32-bits wide */ -#define STR71X_EIC_SIR21_OFFSET (0x00b4) /* 32-bits wide */ -#define STR71X_EIC_SIR22_OFFSET (0x00b8) /* 32-bits wide */ -#define STR71X_EIC_SIR23_OFFSET (0x00bc) /* 32-bits wide */ -#define STR71X_EIC_SIR24_OFFSET (0x00c0) /* 32-bits wide */ -#define STR71X_EIC_SIR25_OFFSET (0x00c4) /* 32-bits wide */ -#define STR71X_EIC_SIR26_OFFSET (0x00c8) /* 32-bits wide */ -#define STR71X_EIC_SIR27_OFFSET (0x00cc) /* 32-bits wide */ -#define STR71X_EIC_SIR28_OFFSET (0x00d0) /* 32-bits wide */ -#define STR71X_EIC_SIR29_OFFSET (0x00d4) /* 32-bits wide */ -#define STR71X_EIC_SIR30_OFFSET (0x00d8) /* 32-bits wide */ -#define STR71X_EIC_SIR31_OFFSET (0x00dc) /* 32-bits wide */ - -#define STR71X_EIC_NCHANNELS (32) -#define STR71X_EIC_SIR_BASE (STR71X_EIC_BASE + STR71X_EIC_SIR_OFFSET) - -/* Enhanced Interupt Controller (EIC) registers *************************************/ - -#define STR71X_EIC_ICR (STR71X_EIC_BASE + STR71X_EIC_ICR_OFFSET) -#define STR71X_EIC_CICR (STR71X_EIC_BASE + STR71X_EIC_CICR_OFFSET) -#define STR71X_EIC_CIPR (STR71X_EIC_BASE + STR71X_EIC_CIPR_OFFSET) -#define STR71X_EIC_IVR (STR71X_EIC_BASE + STR71X_EIC_IVR_OFFSET) -#define STR71X_EIC_FIR (STR71X_EIC_BASE + STR71X_EIC_FIR_OFFSET) -#define STR71X_EIC_IER (STR71X_EIC_BASE + STR71X_EIC_IER_OFFSET) -#define STR71X_EIC_IPR (STR71X_EIC_BASE + STR71X_EIC_IPR_OFFSET) - -#define STR71X_EIC_SIR(n) (STR71X_EIC_SIR_BASE + ((n) << 2)) - -#define STR71X_EIC_SIR0 (STR71X_EIC_BASE + STR71X_EIC_SIR0_OFFSET) -#define STR71X_EIC_SIR1 (STR71X_EIC_BASE + STR71X_EIC_SIR1_OFFSET) -#define STR71X_EIC_SIR2 (STR71X_EIC_BASE + STR71X_EIC_SIR2_OFFSET) -#define STR71X_EIC_SIR3 (STR71X_EIC_BASE + STR71X_EIC_SIR3_OFFSET) -#define STR71X_EIC_SIR4 (STR71X_EIC_BASE + STR71X_EIC_SIR4_OFFSET) -#define STR71X_EIC_SIR5 (STR71X_EIC_BASE + STR71X_EIC_SIR5_OFFSET) -#define STR71X_EIC_SIR6 (STR71X_EIC_BASE + STR71X_EIC_SIR6_OFFSET) -#define STR71X_EIC_SIR7 (STR71X_EIC_BASE + STR71X_EIC_SIR7_OFFSET) -#define STR71X_EIC_SIR8 (STR71X_EIC_BASE + STR71X_EIC_SIR8_OFFSET) -#define STR71X_EIC_SIR9 (STR71X_EIC_BASE + STR71X_EIC_SIR9_OFFSET) -#define STR71X_EIC_SIR10 (STR71X_EIC_BASE + STR71X_EIC_SIR10_OFFSET) -#define STR71X_EIC_SIR11 (STR71X_EIC_BASE + STR71X_EIC_SIR11_OFFSET) -#define STR71X_EIC_SIR12 (STR71X_EIC_BASE + STR71X_EIC_SIR12_OFFSET) -#define STR71X_EIC_SIR13 (STR71X_EIC_BASE + STR71X_EIC_SIR13_OFFSET) -#define STR71X_EIC_SIR14 (STR71X_EIC_BASE + STR71X_EIC_SIR14_OFFSET) -#define STR71X_EIC_SIR15 (STR71X_EIC_BASE + STR71X_EIC_SIR15_OFFSET) -#define STR71X_EIC_SIR16 (STR71X_EIC_BASE + STR71X_EIC_SIR16_OFFSET) -#define STR71X_EIC_SIR17 (STR71X_EIC_BASE + STR71X_EIC_SIR17_OFFSET) -#define STR71X_EIC_SIR18 (STR71X_EIC_BASE + STR71X_EIC_SIR18_OFFSET) -#define STR71X_EIC_SIR19 (STR71X_EIC_BASE + STR71X_EIC_SIR19_OFFSET) -#define STR71X_EIC_SIR20 (STR71X_EIC_BASE + STR71X_EIC_SIR20_OFFSET) -#define STR71X_EIC_SIR21 (STR71X_EIC_BASE + STR71X_EIC_SIR21_OFFSET) -#define STR71X_EIC_SIR22 (STR71X_EIC_BASE + STR71X_EIC_SIR22_OFFSET) -#define STR71X_EIC_SIR23 (STR71X_EIC_BASE + STR71X_EIC_SIR23_OFFSET) -#define STR71X_EIC_SIR24 (STR71X_EIC_BASE + STR71X_EIC_SIR24_OFFSET) -#define STR71X_EIC_SIR25 (STR71X_EIC_BASE + STR71X_EIC_SIR25_OFFSET) -#define STR71X_EIC_SIR26 (STR71X_EIC_BASE + STR71X_EIC_SIR26_OFFSET) -#define STR71X_EIC_SIR27 (STR71X_EIC_BASE + STR71X_EIC_SIR27_OFFSET) -#define STR71X_EIC_SIR28 (STR71X_EIC_BASE + STR71X_EIC_SIR28_OFFSET) -#define STR71X_EIC_SIR29 (STR71X_EIC_BASE + STR71X_EIC_SIR29_OFFSET) -#define STR71X_EIC_SIR30 (STR71X_EIC_BASE + STR71X_EIC_SIR30_OFFSET) -#define STR71X_EIC_SIR31 (STR71X_EIC_BASE + STR71X_EIC_SIR31_OFFSET) - -/* Register bit settings ************************************************************/ - -/* Interrupt control register (ICR) bit definitions */ - -#define STR71X_EICICR_IRQEN (0x00000001) /* Bit 0: IRQ output enable */ -#define STR71X_EICICR_FIQEN (0x00000002) /* Bit 1: FIQ output enable */ - -/* Current interrupt channel register (CICR) bit definitions */ - -#define STR71X_EICCICR_MASK 0x1f /* Bits: 0-4: CIC */ - -/* Fast interrupt register (FIR) bit definitions */ - -#define STR71X_EICFIR_FIE (0x00000001) /* Bit 0: FIQ channel 1/0 enable */ -#define STR71X_EICFIR_FIP (0x00000002) /* Bit 1: channel 1/0 FIQ pending */ - -/* Source interrrupt register definitions */ - -#define STR71X_EICSIR_SIPLMASK (0x0000000f) /* Bits 0-3: Source interrupt priority level */ -#define STR71X_EICSIR_SIVMASK (0xffff0000) /* Bits 16-31: Source interrupt vector */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STR71X_STR71X_EIC_H */ +/************************************************************************************ + * arch/arm/src/str71x/str71x_eic.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_EIC_H +#define __ARCH_ARM_SRC_STR71X_STR71X_EIC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Enhanced Interupt Controller (EIC) register offsets ******************************/ + +#define STR71X_EIC_ICR_OFFSET (0x0000) /* 32-bits wide */ +#define STR71X_EIC_CICR_OFFSET (0x0004) /* 32-bits wide */ +#define STR71X_EIC_CIPR_OFFSET (0x0008) /* 32-bits wide */ +#define STR71X_EIC_IVR_OFFSET (0x0018) /* 32-bits wide */ +#define STR71X_EIC_FIR_OFFSET (0x001c) /* 32-bits wide */ +#define STR71X_EIC_IER_OFFSET (0x0020) /* 32-bits wide */ +#define STR71X_EIC_IPR_OFFSET (0x0040) /* 32-bits wide */ + +#define STR71X_EIC_SIR_OFFSET (0x0060) /* 32 x 32-bits */ +#define STR71X_EIC_SIR0_OFFSET (0x0060) /* 32-bits wide */ +#define STR71X_EIC_SIR1_OFFSET (0x0064) /* 32-bits wide */ +#define STR71X_EIC_SIR2_OFFSET (0x0068) /* 32-bits wide */ +#define STR71X_EIC_SIR3_OFFSET (0x006c) /* 32-bits wide */ +#define STR71X_EIC_SIR4_OFFSET (0x0070) /* 32-bits wide */ +#define STR71X_EIC_SIR5_OFFSET (0x0074) /* 32-bits wide */ +#define STR71X_EIC_SIR6_OFFSET (0x0078) /* 32-bits wide */ +#define STR71X_EIC_SIR7_OFFSET (0x007c) /* 32-bits wide */ +#define STR71X_EIC_SIR8_OFFSET (0x0080) /* 32-bits wide */ +#define STR71X_EIC_SIR9_OFFSET (0x0084) /* 32-bits wide */ +#define STR71X_EIC_SIR10_OFFSET (0x0088) /* 32-bits wide */ +#define STR71X_EIC_SIR11_OFFSET (0x008c) /* 32-bits wide */ +#define STR71X_EIC_SIR12_OFFSET (0x0090) /* 32-bits wide */ +#define STR71X_EIC_SIR13_OFFSET (0x0094) /* 32-bits wide */ +#define STR71X_EIC_SIR14_OFFSET (0x0098) /* 32-bits wide */ +#define STR71X_EIC_SIR15_OFFSET (0x009c) /* 32-bits wide */ +#define STR71X_EIC_SIR16_OFFSET (0x00a0) /* 32-bits wide */ +#define STR71X_EIC_SIR17_OFFSET (0x00a4) /* 32-bits wide */ +#define STR71X_EIC_SIR18_OFFSET (0x00a8) /* 32-bits wide */ +#define STR71X_EIC_SIR19_OFFSET (0x00ac) /* 32-bits wide */ +#define STR71X_EIC_SIR20_OFFSET (0x00b0) /* 32-bits wide */ +#define STR71X_EIC_SIR21_OFFSET (0x00b4) /* 32-bits wide */ +#define STR71X_EIC_SIR22_OFFSET (0x00b8) /* 32-bits wide */ +#define STR71X_EIC_SIR23_OFFSET (0x00bc) /* 32-bits wide */ +#define STR71X_EIC_SIR24_OFFSET (0x00c0) /* 32-bits wide */ +#define STR71X_EIC_SIR25_OFFSET (0x00c4) /* 32-bits wide */ +#define STR71X_EIC_SIR26_OFFSET (0x00c8) /* 32-bits wide */ +#define STR71X_EIC_SIR27_OFFSET (0x00cc) /* 32-bits wide */ +#define STR71X_EIC_SIR28_OFFSET (0x00d0) /* 32-bits wide */ +#define STR71X_EIC_SIR29_OFFSET (0x00d4) /* 32-bits wide */ +#define STR71X_EIC_SIR30_OFFSET (0x00d8) /* 32-bits wide */ +#define STR71X_EIC_SIR31_OFFSET (0x00dc) /* 32-bits wide */ + +#define STR71X_EIC_NCHANNELS (32) +#define STR71X_EIC_SIR_BASE (STR71X_EIC_BASE + STR71X_EIC_SIR_OFFSET) + +/* Enhanced Interupt Controller (EIC) registers *************************************/ + +#define STR71X_EIC_ICR (STR71X_EIC_BASE + STR71X_EIC_ICR_OFFSET) +#define STR71X_EIC_CICR (STR71X_EIC_BASE + STR71X_EIC_CICR_OFFSET) +#define STR71X_EIC_CIPR (STR71X_EIC_BASE + STR71X_EIC_CIPR_OFFSET) +#define STR71X_EIC_IVR (STR71X_EIC_BASE + STR71X_EIC_IVR_OFFSET) +#define STR71X_EIC_FIR (STR71X_EIC_BASE + STR71X_EIC_FIR_OFFSET) +#define STR71X_EIC_IER (STR71X_EIC_BASE + STR71X_EIC_IER_OFFSET) +#define STR71X_EIC_IPR (STR71X_EIC_BASE + STR71X_EIC_IPR_OFFSET) + +#define STR71X_EIC_SIR(n) (STR71X_EIC_SIR_BASE + ((n) << 2)) + +#define STR71X_EIC_SIR0 (STR71X_EIC_BASE + STR71X_EIC_SIR0_OFFSET) +#define STR71X_EIC_SIR1 (STR71X_EIC_BASE + STR71X_EIC_SIR1_OFFSET) +#define STR71X_EIC_SIR2 (STR71X_EIC_BASE + STR71X_EIC_SIR2_OFFSET) +#define STR71X_EIC_SIR3 (STR71X_EIC_BASE + STR71X_EIC_SIR3_OFFSET) +#define STR71X_EIC_SIR4 (STR71X_EIC_BASE + STR71X_EIC_SIR4_OFFSET) +#define STR71X_EIC_SIR5 (STR71X_EIC_BASE + STR71X_EIC_SIR5_OFFSET) +#define STR71X_EIC_SIR6 (STR71X_EIC_BASE + STR71X_EIC_SIR6_OFFSET) +#define STR71X_EIC_SIR7 (STR71X_EIC_BASE + STR71X_EIC_SIR7_OFFSET) +#define STR71X_EIC_SIR8 (STR71X_EIC_BASE + STR71X_EIC_SIR8_OFFSET) +#define STR71X_EIC_SIR9 (STR71X_EIC_BASE + STR71X_EIC_SIR9_OFFSET) +#define STR71X_EIC_SIR10 (STR71X_EIC_BASE + STR71X_EIC_SIR10_OFFSET) +#define STR71X_EIC_SIR11 (STR71X_EIC_BASE + STR71X_EIC_SIR11_OFFSET) +#define STR71X_EIC_SIR12 (STR71X_EIC_BASE + STR71X_EIC_SIR12_OFFSET) +#define STR71X_EIC_SIR13 (STR71X_EIC_BASE + STR71X_EIC_SIR13_OFFSET) +#define STR71X_EIC_SIR14 (STR71X_EIC_BASE + STR71X_EIC_SIR14_OFFSET) +#define STR71X_EIC_SIR15 (STR71X_EIC_BASE + STR71X_EIC_SIR15_OFFSET) +#define STR71X_EIC_SIR16 (STR71X_EIC_BASE + STR71X_EIC_SIR16_OFFSET) +#define STR71X_EIC_SIR17 (STR71X_EIC_BASE + STR71X_EIC_SIR17_OFFSET) +#define STR71X_EIC_SIR18 (STR71X_EIC_BASE + STR71X_EIC_SIR18_OFFSET) +#define STR71X_EIC_SIR19 (STR71X_EIC_BASE + STR71X_EIC_SIR19_OFFSET) +#define STR71X_EIC_SIR20 (STR71X_EIC_BASE + STR71X_EIC_SIR20_OFFSET) +#define STR71X_EIC_SIR21 (STR71X_EIC_BASE + STR71X_EIC_SIR21_OFFSET) +#define STR71X_EIC_SIR22 (STR71X_EIC_BASE + STR71X_EIC_SIR22_OFFSET) +#define STR71X_EIC_SIR23 (STR71X_EIC_BASE + STR71X_EIC_SIR23_OFFSET) +#define STR71X_EIC_SIR24 (STR71X_EIC_BASE + STR71X_EIC_SIR24_OFFSET) +#define STR71X_EIC_SIR25 (STR71X_EIC_BASE + STR71X_EIC_SIR25_OFFSET) +#define STR71X_EIC_SIR26 (STR71X_EIC_BASE + STR71X_EIC_SIR26_OFFSET) +#define STR71X_EIC_SIR27 (STR71X_EIC_BASE + STR71X_EIC_SIR27_OFFSET) +#define STR71X_EIC_SIR28 (STR71X_EIC_BASE + STR71X_EIC_SIR28_OFFSET) +#define STR71X_EIC_SIR29 (STR71X_EIC_BASE + STR71X_EIC_SIR29_OFFSET) +#define STR71X_EIC_SIR30 (STR71X_EIC_BASE + STR71X_EIC_SIR30_OFFSET) +#define STR71X_EIC_SIR31 (STR71X_EIC_BASE + STR71X_EIC_SIR31_OFFSET) + +/* Register bit settings ************************************************************/ + +/* Interrupt control register (ICR) bit definitions */ + +#define STR71X_EICICR_IRQEN (0x00000001) /* Bit 0: IRQ output enable */ +#define STR71X_EICICR_FIQEN (0x00000002) /* Bit 1: FIQ output enable */ + +/* Current interrupt channel register (CICR) bit definitions */ + +#define STR71X_EICCICR_MASK 0x1f /* Bits: 0-4: CIC */ + +/* Fast interrupt register (FIR) bit definitions */ + +#define STR71X_EICFIR_FIE (0x00000001) /* Bit 0: FIQ channel 1/0 enable */ +#define STR71X_EICFIR_FIP (0x00000002) /* Bit 1: channel 1/0 FIQ pending */ + +/* Source interrrupt register definitions */ + +#define STR71X_EICSIR_SIPLMASK (0x0000000f) /* Bits 0-3: Source interrupt priority level */ +#define STR71X_EICSIR_SIVMASK (0xffff0000) /* Bits 16-31: Source interrupt vector */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_EIC_H */ diff --git a/arch/arm/src/str71x/str71x_emi.h b/arch/arm/src/str71x/str71x_emi.h index 68c35cd07ec74322b841c4e2afd0e37bb538bf49..ade4d1145ba3db6b375e81eac972cfd4a49daa35 100644 --- a/arch/arm/src/str71x/str71x_emi.h +++ b/arch/arm/src/str71x/str71x_emi.h @@ -1,103 +1,103 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_emi.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_EMI_H -#define __ARCH_ARM_SRC_STR71X_STR71X_EMI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "str71x_map.h" - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* External Memory Interfac (EMI) register offset ***********************************/ - -#define STR71X_EMI_BCON0_OFFSET (0x0000) /* 16-bits wide */ -#define STR71X_EMI_BCON1_OFFSET (0x0004) /* 16-bits wide */ -#define STR71X_EMI_BCON2_OFFSET (0x0008) /* 16-bits wide */ -#define STR71X_EMI_BCON3_OFFSET (0x000c) /* 16-bits wide */ - -/* External Memory Interfac (EMI) register addresses ********************************/ - -#define STR71X_EMI_BCON0 (STR71X_EMI_BASE + STR71X_EMI_BCON0_OFFSET) -#define STR71X_EMI_BCON1 (STR71X_EMI_BASE + STR71X_EMI_BCON1_OFFSET) -#define STR71X_EMI_BCON2 (STR71X_EMI_BASE + STR71X_EMI_BCON2_OFFSET) -#define STR71X_EMI_BCON3 (STR71X_EMI_BASE + STR71X_EMI_BCON3_OFFSET) - -/* Register bit settings ***********************************************************/ - -/* Bank-N configuration register (BCONn) bit definitions */ - -#define STR71X_EMIBCON_BSIZEMASK (0x0003) /* Bits 0-1: Bank size */ -#define STR71X_EMIBCON_BSIZE8 (0x0000) /* 8-bit */ -#define STR71X_EMIBCON_BSIZE16 (0x0001) /* 16-bit */ -#define STR71X_EMIBCON_WSMASK (0x003c) /* Bits 2-5: Wait states */ -#define STR71X_EMIBCON_WS0 (0x0000) /* 0 waitstates */ -#define STR71X_EMIBCON_WS1 (0x0004) /* 1 waitstates */ -#define STR71X_EMIBCON_WS2 (0x0008) /* 2 waitstates */ -#define STR71X_EMIBCON_WS3 (0x000c) /* 3 waitstates */ -#define STR71X_EMIBCON_WS4 (0x0010) /* 4 waitstates */ -#define STR71X_EMIBCON_WS5 (0x0014) /* 5 waitstates */ -#define STR71X_EMIBCON_WS6 (0x0018) /* 6 waitstates */ -#define STR71X_EMIBCON_WS7 (0x001c) /* 7 waitstates */ -#define STR71X_EMIBCON_WS8 (0x0020) /* 8 waitstates */ -#define STR71X_EMIBCON_WS9 (0x0024) /* 9 waitstates */ -#define STR71X_EMIBCON_WS10 (0x0028) /* 10 waitstates */ -#define STR71X_EMIBCON_WS11 (0x002c) /* 11 waitstates */ -#define STR71X_EMIBCON_WS12 (0x0030) /* 12 waitstates */ -#define STR71X_EMIBCON_WS13 (0x0034) /* 13 waitstates */ -#define STR71X_EMIBCON_WS14 (0x0038) /* 14 waitstates */ -#define STR71X_EMIBCON_WS15 (0x003c) /* 15 waitstates */ -#define STR71X_EMIBCON_ENABLE (0x8000) /* Bit 15: Bank enable */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STR71X_STR71X_EMI_H */ +/************************************************************************************ + * arch/arm/src/str71x/str71x_emi.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_EMI_H +#define __ARCH_ARM_SRC_STR71X_STR71X_EMI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* External Memory Interfac (EMI) register offset ***********************************/ + +#define STR71X_EMI_BCON0_OFFSET (0x0000) /* 16-bits wide */ +#define STR71X_EMI_BCON1_OFFSET (0x0004) /* 16-bits wide */ +#define STR71X_EMI_BCON2_OFFSET (0x0008) /* 16-bits wide */ +#define STR71X_EMI_BCON3_OFFSET (0x000c) /* 16-bits wide */ + +/* External Memory Interfac (EMI) register addresses ********************************/ + +#define STR71X_EMI_BCON0 (STR71X_EMI_BASE + STR71X_EMI_BCON0_OFFSET) +#define STR71X_EMI_BCON1 (STR71X_EMI_BASE + STR71X_EMI_BCON1_OFFSET) +#define STR71X_EMI_BCON2 (STR71X_EMI_BASE + STR71X_EMI_BCON2_OFFSET) +#define STR71X_EMI_BCON3 (STR71X_EMI_BASE + STR71X_EMI_BCON3_OFFSET) + +/* Register bit settings ***********************************************************/ + +/* Bank-N configuration register (BCONn) bit definitions */ + +#define STR71X_EMIBCON_BSIZEMASK (0x0003) /* Bits 0-1: Bank size */ +#define STR71X_EMIBCON_BSIZE8 (0x0000) /* 8-bit */ +#define STR71X_EMIBCON_BSIZE16 (0x0001) /* 16-bit */ +#define STR71X_EMIBCON_WSMASK (0x003c) /* Bits 2-5: Wait states */ +#define STR71X_EMIBCON_WS0 (0x0000) /* 0 waitstates */ +#define STR71X_EMIBCON_WS1 (0x0004) /* 1 waitstates */ +#define STR71X_EMIBCON_WS2 (0x0008) /* 2 waitstates */ +#define STR71X_EMIBCON_WS3 (0x000c) /* 3 waitstates */ +#define STR71X_EMIBCON_WS4 (0x0010) /* 4 waitstates */ +#define STR71X_EMIBCON_WS5 (0x0014) /* 5 waitstates */ +#define STR71X_EMIBCON_WS6 (0x0018) /* 6 waitstates */ +#define STR71X_EMIBCON_WS7 (0x001c) /* 7 waitstates */ +#define STR71X_EMIBCON_WS8 (0x0020) /* 8 waitstates */ +#define STR71X_EMIBCON_WS9 (0x0024) /* 9 waitstates */ +#define STR71X_EMIBCON_WS10 (0x0028) /* 10 waitstates */ +#define STR71X_EMIBCON_WS11 (0x002c) /* 11 waitstates */ +#define STR71X_EMIBCON_WS12 (0x0030) /* 12 waitstates */ +#define STR71X_EMIBCON_WS13 (0x0034) /* 13 waitstates */ +#define STR71X_EMIBCON_WS14 (0x0038) /* 14 waitstates */ +#define STR71X_EMIBCON_WS15 (0x003c) /* 15 waitstates */ +#define STR71X_EMIBCON_ENABLE (0x8000) /* Bit 15: Bank enable */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_EMI_H */ diff --git a/arch/arm/src/str71x/str71x_flash.h b/arch/arm/src/str71x/str71x_flash.h index 352972d4821ab7d1c90c7ba6d64ce009f8fbdc56..9b45fa3e9269ace1384e3fbc7e0622d721c47ebd 100644 --- a/arch/arm/src/str71x/str71x_flash.h +++ b/arch/arm/src/str71x/str71x_flash.h @@ -1,123 +1,123 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_flash.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_FLASH_H -#define __ARCH_ARM_SRC_STR71X_STR71X_FLASH_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "str71x_map.h" - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* Flash registers ******************************************************************/ - -#define STR71X_FLASH_CR0 (STR71X_FLASHREG_BASE + 0x0000) /* 32-bits wide */ -#define STR71X_FLASH_CR1 (STR71X_FLASHREG_BASE + 0x0004) /* 32-bits wide */ -#define STR71X_FLASH_DR0 (STR71X_FLASHREG_BASE + 0x0008) /* 32-bits wide */ -#define STR71X_FLASH_DR1 (STR71X_FLASHREG_BASE + 0x000c) /* 32-bits wide */ -#define STR71X_FLASH_AR (STR71X_FLASHREG_BASE + 0x0010) /* 32-bits wide */ -#define STR71X_FLASH_ER (STR71X_FLASHREG_BASE + 0x0014) /* 32-bits wide */ - -/* Register bit settings ************************************************************/ - -#define STR71X_FLASH_B0F0 (0x00000001) -#define STR71X_FLASH_B0F1 (0x00000002) -#define STR71X_FLASH_B0F2 (0x00000004) -#define STR71X_FLASH_B0F3 (0x00000008) -#define STR71X_FLASH_B0F4 (0x00000010) -#define STR71X_FLASH_B0F5 (0x00000020) -#define STR71X_FLASH_B0F6 (0x00000040) -#define STR71X_FLASH_B0F7 (0x00000080) - -#define STR71X_FLASH_B1F0 (0x00010000) -#define STR71X_FLASH_B1F1 (0x00020000) - -#define STR71X_FLASH_B0 (STR71X_FLASH_B0F0|STR71X_FLASH_B0F1|\ - STR71X_FLASH_B0F2|STR71X_FLASH_B0F3|\ - STR71X_FLASH_B0F4|STR71X_FLASH_B0F5|\ - STR71X_FLASH_B0F6| STR71X_FLASH_B0F7) -#define STR71X_FLASH_B1 (STR71X_FLASH_B1F0|STR71X_FLASH_B1F1) - -#define STR71X_FLASH_BANK0 (0x1000000) -#define STR71X_FLASH_BANK1 (0x2000000) - -#define STR71X_FLASH_BSYA0 (0x01) /* 000-00001 (0000 0001 (0x01 */ /* STR71X_FLASH_CR0.1 */ -#define STR71X_FLASH_BSYA1 (0x02) /* 000-00010 (0000 0010 (0x02 */ /* STR71X_FLASH_CR0.2 */ -#define STR71X_FLASH_LOCK (0x04) /* 000-00100 (0000 0100 (0x04 */ /* STR71X_FLASH_CR0.4 */ -#define STR71X_FLASH_INTP (0x14) /* 000-10100 (0001 0100 (0x14 */ /* STR71X_FLASH_CR0.20 */ -#define STR71X_FLASH_B0S (0x38) /* 001-11000 (0011 1000 (0x38 */ /* STR71X_FLASH_CR1.24 */ -#define STR71X_FLASH_B1S (0x39) /* 001-11001 (0011 1001 (0x39 */ /* STR71X_FLASH_CR1.25 */ -#define STR71X_FLASH_ERR (0xa0) /* 101-00000 (1010 0000 (0xA0 */ /* STR71X_FLASH_ER.0 */ -#define STR71X_FLASH_ERER (0xa1) /* 101-00001 (1010 0001 (0xA1 */ /* STR71X_FLASH_ER.1 */ -#define STR71X_FLASH_PGER (0xa2) /* 101-00010 (1010 0010 (0xA2 */ /* STR71X_FLASH_ER.2 */ -#define STR71X_FLASH_10ER (0xa3) /* 101-00011 (1010 0011 (0xA3 */ /* STR71X_FLASH_ER.3 */ -#define STR71X_FLASH_SEQER (0xa6) /* 101-00110 (1010 0110 (0xA6 */ /* STR71X_FLASH_ER.6 */ -#define STR71X_FLASH_RESER (0xa7) /* 101-00111 (1010 0111 (0xA7 */ /* STR71X_FLASH_ER.7 */ -#define STR71X_FLASH_WPF (0xa8) /* 101-01000 (1010 1000 (0xA8 */ /* STR71X_FLASH_ER.8 */ - -#define STR71X_FLASH_WMS_MASK (0x80000000) -#define STR71X_FLASH_SUSP_MASK (0x40000000) -#define STR71X_FLASH_WPG_MASK (0x20000000) -#define STR71X_FLASH_DWPG_MASK (0x10000000) -#define STR71X_FLASH_SER_MASK (0x08000000) -#define STR71X_FLASH_SPR_MASK (0x01000000) -#define STR71X_FLASH_DBGP_MASK (0x00000002) -#define STR71X_FLASH_ACCP_MASK (0x00000001) - -#define STR71X_FLASH_Reg_Mask (0xe0) -#define STR71X_FLASH_Flag_Mask (0x1f) - -#define STR71X_FLASH_INTM_Mask (0x00200000) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STR71X_STR71X_FLASH_H */ +/************************************************************************************ + * arch/arm/src/str71x/str71x_flash.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_FLASH_H +#define __ARCH_ARM_SRC_STR71X_STR71X_FLASH_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Flash registers ******************************************************************/ + +#define STR71X_FLASH_CR0 (STR71X_FLASHREG_BASE + 0x0000) /* 32-bits wide */ +#define STR71X_FLASH_CR1 (STR71X_FLASHREG_BASE + 0x0004) /* 32-bits wide */ +#define STR71X_FLASH_DR0 (STR71X_FLASHREG_BASE + 0x0008) /* 32-bits wide */ +#define STR71X_FLASH_DR1 (STR71X_FLASHREG_BASE + 0x000c) /* 32-bits wide */ +#define STR71X_FLASH_AR (STR71X_FLASHREG_BASE + 0x0010) /* 32-bits wide */ +#define STR71X_FLASH_ER (STR71X_FLASHREG_BASE + 0x0014) /* 32-bits wide */ + +/* Register bit settings ************************************************************/ + +#define STR71X_FLASH_B0F0 (0x00000001) +#define STR71X_FLASH_B0F1 (0x00000002) +#define STR71X_FLASH_B0F2 (0x00000004) +#define STR71X_FLASH_B0F3 (0x00000008) +#define STR71X_FLASH_B0F4 (0x00000010) +#define STR71X_FLASH_B0F5 (0x00000020) +#define STR71X_FLASH_B0F6 (0x00000040) +#define STR71X_FLASH_B0F7 (0x00000080) + +#define STR71X_FLASH_B1F0 (0x00010000) +#define STR71X_FLASH_B1F1 (0x00020000) + +#define STR71X_FLASH_B0 (STR71X_FLASH_B0F0|STR71X_FLASH_B0F1|\ + STR71X_FLASH_B0F2|STR71X_FLASH_B0F3|\ + STR71X_FLASH_B0F4|STR71X_FLASH_B0F5|\ + STR71X_FLASH_B0F6| STR71X_FLASH_B0F7) +#define STR71X_FLASH_B1 (STR71X_FLASH_B1F0|STR71X_FLASH_B1F1) + +#define STR71X_FLASH_BANK0 (0x1000000) +#define STR71X_FLASH_BANK1 (0x2000000) + +#define STR71X_FLASH_BSYA0 (0x01) /* 000-00001 (0000 0001 (0x01 */ /* STR71X_FLASH_CR0.1 */ +#define STR71X_FLASH_BSYA1 (0x02) /* 000-00010 (0000 0010 (0x02 */ /* STR71X_FLASH_CR0.2 */ +#define STR71X_FLASH_LOCK (0x04) /* 000-00100 (0000 0100 (0x04 */ /* STR71X_FLASH_CR0.4 */ +#define STR71X_FLASH_INTP (0x14) /* 000-10100 (0001 0100 (0x14 */ /* STR71X_FLASH_CR0.20 */ +#define STR71X_FLASH_B0S (0x38) /* 001-11000 (0011 1000 (0x38 */ /* STR71X_FLASH_CR1.24 */ +#define STR71X_FLASH_B1S (0x39) /* 001-11001 (0011 1001 (0x39 */ /* STR71X_FLASH_CR1.25 */ +#define STR71X_FLASH_ERR (0xa0) /* 101-00000 (1010 0000 (0xA0 */ /* STR71X_FLASH_ER.0 */ +#define STR71X_FLASH_ERER (0xa1) /* 101-00001 (1010 0001 (0xA1 */ /* STR71X_FLASH_ER.1 */ +#define STR71X_FLASH_PGER (0xa2) /* 101-00010 (1010 0010 (0xA2 */ /* STR71X_FLASH_ER.2 */ +#define STR71X_FLASH_10ER (0xa3) /* 101-00011 (1010 0011 (0xA3 */ /* STR71X_FLASH_ER.3 */ +#define STR71X_FLASH_SEQER (0xa6) /* 101-00110 (1010 0110 (0xA6 */ /* STR71X_FLASH_ER.6 */ +#define STR71X_FLASH_RESER (0xa7) /* 101-00111 (1010 0111 (0xA7 */ /* STR71X_FLASH_ER.7 */ +#define STR71X_FLASH_WPF (0xa8) /* 101-01000 (1010 1000 (0xA8 */ /* STR71X_FLASH_ER.8 */ + +#define STR71X_FLASH_WMS_MASK (0x80000000) +#define STR71X_FLASH_SUSP_MASK (0x40000000) +#define STR71X_FLASH_WPG_MASK (0x20000000) +#define STR71X_FLASH_DWPG_MASK (0x10000000) +#define STR71X_FLASH_SER_MASK (0x08000000) +#define STR71X_FLASH_SPR_MASK (0x01000000) +#define STR71X_FLASH_DBGP_MASK (0x00000002) +#define STR71X_FLASH_ACCP_MASK (0x00000001) + +#define STR71X_FLASH_Reg_Mask (0xe0) +#define STR71X_FLASH_Flag_Mask (0x1f) + +#define STR71X_FLASH_INTM_Mask (0x00200000) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_FLASH_H */ diff --git a/arch/arm/src/str71x/str71x_gpio.h b/arch/arm/src/str71x/str71x_gpio.h index dbcd3cdeb038247919da494dba0c21d8fd16bc17..16b3256130195d80224a328088788d620a80f378 100644 --- a/arch/arm/src/str71x/str71x_gpio.h +++ b/arch/arm/src/str71x/str71x_gpio.h @@ -1,94 +1,94 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_gpio.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_GPIO_H -#define __ARCH_ARM_SRC_STR71X_STR71X_GPIO_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "str71x_map.h" - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* GPIO register offsets ************************************************************/ - -#define STR71X_GPIO_PC0_OFFSET (0x0000) /* 16-bits wide */ -#define STR71X_GPIO_PC1_OFFSET (0x0004) /* 16-bits wide */ -#define STR71X_GPIO_PC2_OFFSET (0x0008) /* 16-bits wide */ -#define STR71X_GPIO_PD_OFFSET (0x000c) /* 16-bits wide */ - -/* GPIO register addresses **********************************************************/ - -#define STR71X_GPIO_PC0(b) ((b) + STR71X_GPIO_PC0_OFFSET) -#define STR71X_GPIO_PC1(b) ((b) + STR71X_GPIO_PC1_OFFSET) -#define STR71X_GPIO_PC2(b) ((b) + STR71X_GPIO_PC2_OFFSET) -#define STR71X_GPIO_PD(b) ((b) + STR71X_GPIO_PD_OFFSET) - -#define STR71X_GPIO0_PC0 (STR71X_GPIO0_BASE + STR71X_GPIO_PC0_OFFSET) -#define STR71X_GPIO0_PC1 (STR71X_GPIO0_BASE + STR71X_GPIO_PC1_OFFSET) -#define STR71X_GPIO0_PC2 (STR71X_GPIO0_BASE + STR71X_GPIO_PC2_OFFSET) -#define STR71X_GPIO0_PD (STR71X_GPIO0_BASE + STR71X_GPIO_PD_OFFSET) - -#define STR71X_GPIO1_PC0 (STR71X_GPIO1_BASE + STR71X_GPIO_PC0_OFFSET) -#define STR71X_GPIO1_PC1 (STR71X_GPIO1_BASE + STR71X_GPIO_PC1_OFFSET) -#define STR71X_GPIO1_PC2 (STR71X_GPIO1_BASE + STR71X_GPIO_PC2_OFFSET) -#define STR71X_GPIO1_PD (STR71X_GPIO1_BASE + STR71X_GPIO_PD_OFFSET) - -#define STR71X_GPIO2_PC0 (STR71X_GPIO2_BASE + STR71X_GPIO_PC0_OFFSET) -#define STR71X_GPIO2_PC1 (STR71X_GPIO2_BASE + STR71X_GPIO_PC1_OFFSET) -#define STR71X_GPIO2_PC2 (STR71X_GPIO2_BASE + STR71X_GPIO_PC2_OFFSET) -#define STR71X_GPIO2_PD (STR71X_GPIO2_BASE + STR71X_GPIO_PD_OFFSET) - -/* Register bit settings ************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STR71X_STR71X_GPIO_H */ +/************************************************************************************ + * arch/arm/src/str71x/str71x_gpio.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_GPIO_H +#define __ARCH_ARM_SRC_STR71X_STR71X_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* GPIO register offsets ************************************************************/ + +#define STR71X_GPIO_PC0_OFFSET (0x0000) /* 16-bits wide */ +#define STR71X_GPIO_PC1_OFFSET (0x0004) /* 16-bits wide */ +#define STR71X_GPIO_PC2_OFFSET (0x0008) /* 16-bits wide */ +#define STR71X_GPIO_PD_OFFSET (0x000c) /* 16-bits wide */ + +/* GPIO register addresses **********************************************************/ + +#define STR71X_GPIO_PC0(b) ((b) + STR71X_GPIO_PC0_OFFSET) +#define STR71X_GPIO_PC1(b) ((b) + STR71X_GPIO_PC1_OFFSET) +#define STR71X_GPIO_PC2(b) ((b) + STR71X_GPIO_PC2_OFFSET) +#define STR71X_GPIO_PD(b) ((b) + STR71X_GPIO_PD_OFFSET) + +#define STR71X_GPIO0_PC0 (STR71X_GPIO0_BASE + STR71X_GPIO_PC0_OFFSET) +#define STR71X_GPIO0_PC1 (STR71X_GPIO0_BASE + STR71X_GPIO_PC1_OFFSET) +#define STR71X_GPIO0_PC2 (STR71X_GPIO0_BASE + STR71X_GPIO_PC2_OFFSET) +#define STR71X_GPIO0_PD (STR71X_GPIO0_BASE + STR71X_GPIO_PD_OFFSET) + +#define STR71X_GPIO1_PC0 (STR71X_GPIO1_BASE + STR71X_GPIO_PC0_OFFSET) +#define STR71X_GPIO1_PC1 (STR71X_GPIO1_BASE + STR71X_GPIO_PC1_OFFSET) +#define STR71X_GPIO1_PC2 (STR71X_GPIO1_BASE + STR71X_GPIO_PC2_OFFSET) +#define STR71X_GPIO1_PD (STR71X_GPIO1_BASE + STR71X_GPIO_PD_OFFSET) + +#define STR71X_GPIO2_PC0 (STR71X_GPIO2_BASE + STR71X_GPIO_PC0_OFFSET) +#define STR71X_GPIO2_PC1 (STR71X_GPIO2_BASE + STR71X_GPIO_PC1_OFFSET) +#define STR71X_GPIO2_PC2 (STR71X_GPIO2_BASE + STR71X_GPIO_PC2_OFFSET) +#define STR71X_GPIO2_PD (STR71X_GPIO2_BASE + STR71X_GPIO_PD_OFFSET) + +/* Register bit settings ************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_GPIO_H */ diff --git a/arch/arm/src/str71x/str71x_i2c.h b/arch/arm/src/str71x/str71x_i2c.h index 8a0cd498f07096ce78c95f1e0190b2682725c207..759c75e7eb83ffedc7894caa9a4a9367612db17a 100644 --- a/arch/arm/src/str71x/str71x_i2c.h +++ b/arch/arm/src/str71x/str71x_i2c.h @@ -1,153 +1,153 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_i2c.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_I2C_H -#define __ARCH_ARM_SRC_STR71X_STR71X_I2C_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "str71x_map.h" - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* Register offets ******************************************************************/ - -#define STR71X_I2C_CR_OFFSET (0x0000) /* 8-bits wide */ -#define STR71X_I2C_SR1_OFFSET (0x0004) /* 8-bits wide */ -#define STR71X_I2C_SR2_OFFSET (0x0008) /* 8-bits wide */ -#define STR71X_I2C_CCR_OFFSET (0x000c) /* 8-bits wide */ -#define STR71X_I2C_OAR1_OFFSET (0x0010) /* 8-bits wide */ -#define STR71X_I2C_OAR2_OFFSET (0x0014) /* 8-bits wide */ -#define STR71X_I2C_DR_OFFSET (0x0018) /* 8-bits wide */ -#define STR71X_I2C_ECCR_OFFSET (0x001c) /* 8-bits wide */ - -/* Registers ************************************************************************/ - -#define STR71X_I2C_CR(b) ((b) + STR71X_I2C_SR_OFFSET) -#define STR71X_I2C_SR1(b) ((b) + STR71X_I2C_SR1_OFFSET) -#define STR71X_I2C_SR2(b) ((b) + STR71X_I2C_SR2_OFFSET) -#define STR71X_I2C_CCR(b) ((b) + STR71X_I2C_CCR_OFFSET) -#define STR71X_I2C_OAR1(b) ((b) + STR71X_I2C_OAR1_OFFSET) -#define STR71X_I2C_OAR2(b) ((b) + STR71X_I2C_OAR2_OFFSET) -#define STR71X_I2C_DR(b) ((b) + STR71X_I2C_DR_OFFSET) -#define STR71X_I2C_ECCR(b) ((b) + STR71X_I2C_ECCR_OFFSET) - -#define STR71X_I2C0_CR (STR71X_I2C0_BASE + STR71X_I2C_SR_OFFSET) -#define STR71X_I2C0_SR1 (STR71X_I2C0_BASE + STR71X_I2C_SR1_OFFSET) -#define STR71X_I2C0_SR2 (STR71X_I2C0_BASE + STR71X_I2C_SR2_OFFSET) -#define STR71X_I2C0_CCR (STR71X_I2C0_BASE + STR71X_I2C_CCR_OFFSET) -#define STR71X_I2C0_OAR1 (STR71X_I2C0_BASE + STR71X_I2C_OAR1_OFFSET) -#define STR71X_I2C0_OAR2 (STR71X_I2C0_BASE + STR71X_I2C_OAR2_OFFSET) -#define STR71X_I2C0_DR (STR71X_I2C0_BASE + STR71X_I2C_DR_OFFSET) -#define STR71X_I2C0_ECCR (STR71X_I2C0_BASE + STR71X_I2C_ECCR_OFFSET) - -#define STR71X_I2C1_CR (STR71X_I2C1_BASE + STR71X_I2C_SR_OFFSET) -#define STR71X_I2C1_SR1 (STR71X_I2C1_BASE + STR71X_I2C_SR1_OFFSET) -#define STR71X_I2C1_SR2 (STR71X_I2C1_BASE + STR71X_I2C_SR2_OFFSET) -#define STR71X_I2C1_CCR (STR71X_I2C1_BASE + STR71X_I2C_CCR_OFFSET) -#define STR71X_I2C1_OAR1 (STR71X_I2C1_BASE + STR71X_I2C_OAR1_OFFSET) -#define STR71X_I2C1_OAR2 (STR71X_I2C1_BASE + STR71X_I2C_OAR2_OFFSET) -#define STR71X_I2C1_DR (STR71X_I2C1_BASE + STR71X_I2C_DR_OFFSET) -#define STR71X_I2C1_ECCR (STR71X_I2C1_BASE + STR71X_I2C_ECCR_OFFSET) - -/* Register bit settings ***********************************************************/ - -/* I2C Control Register (CR) */ - -#define STR71X_I2CCR_ITE (0x01) /* Bit 0: Interrupt enable */ -#define STR71X_I2CCR_STOP (0x02) /* Bit 1: Generation of a stop condition */ -#define STR71X_I2CCR_ACK (0x04) /* Bit 2: Acknowledge enable */ -#define STR71X_I2CCR_START (0x08) /* Bit 3: Generation of a start condition */ -#define STR71X_I2CCR_ENGC (0x10) /* Bit 4: Enable general call */ -#define STR71X_I2CCR_PE (0x20) /* Bit 5: Peripheral enable */ - -/* I2C Status Register 1 (SR1) */ - -#define STR71X_I2CSR1_SB (0x01) /* Bit 0: Start bit (master mode) */ -#define STR71X_I2CSR1_MSL (0x02) /* Bit 1: Master/slave */ -#define STR71X_I2CSR1_ADSL (0x04) /* Bit 2: Address matched */ -#define STR71X_I2CSR1_BTF (0x08) /* Bit 3: Byte transfer finished */ -#define STR71X_I2CSR1_BUSY (0x10) /* Bit 4: Bus busy */ -#define STR71X_I2CSR1_TRA (0x20) /* Bit 5: Transmitter/receiver */ -#define STR71X_I2CSR1_ADD10 (0x40) /* Bit 6: 10-bit addressing in master mode */ -#define STR71X_I2CSR1_EVF (0x80) /* Bit 7: Event flag */ - -/* I2C Status Register 2 (SR2) */ - -#define STR71X_I2CSR2_GCAL (0x01) /* Bit 0: General call (slave mode) */ -#define STR71X_I2CSR2_BERR (0x02) /* Bit 1: Bus error */ -#define STR71X_I2CSR2_ARLO (0x04) /* Bit 2: Arbitration lost */ -#define STR71X_I2CSR2_STOPF (0x08) /* Bit 3: Stop detection (slave mode) */ -#define STR71X_I2CSR2_AF (0x10) /* Bit 4: Acknowledge failure */ -#define STR71X_I2CSR2_ENDAD (0x20) /* Bit 5: End of address transmission */ - -/* I2C Clock Control Register (CCR) */ - -#define STR71X_I2CCCR_DIVMASK (0x7f) /* Bits 0-6: 7 bits of the 12-bit clock divider */ -#define STR71X_I2CCCR_FMSM (0x80) /* Bit 7: Fast/standard I2C mode */ - -/* I2C Extended Clock Control Register (ECCR) */ - -#define STR71X_I2CECCR_DIVMASK (0x1f) /* Bits 0-5: 5 bits of the 12-bit clock divider */ - -/* I2C Own Address Register 2 (OAR2) */ - -#define STR71X_I2COAR2_ADDRMASK (0x06) /* Bits 1-2: 2 bits of the 10-bit interface address */ -#define STR71X_I2COAR2_FREQMASK (0xe0) /* Bits 5-7: Frequency */ -#define STR71X_I2COAR2_5_10 (0x00) /* FPCLK1 = 5 to 10 */ -#define STR71X_I2COAR2_10_16 (0x20) /* FPCLK1 = 10 to 16.67 */ -#define STR71X_I2COAR2_16_26 (0x40) /* FPCLK1 = 16.67 to 26.67 */ -#define STR71X_I2COAR2_26_40 (0x60) /* FPCLK1 = 26.67 to 40 */ -#define STR71X_I2COAR2_40_53 (0x80) /* FPCLK1 = 40 to 53.33 */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STR71X_STR71X_I2C_H */ +/************************************************************************************ + * arch/arm/src/str71x/str71x_i2c.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_I2C_H +#define __ARCH_ARM_SRC_STR71X_STR71X_I2C_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Register offets ******************************************************************/ + +#define STR71X_I2C_CR_OFFSET (0x0000) /* 8-bits wide */ +#define STR71X_I2C_SR1_OFFSET (0x0004) /* 8-bits wide */ +#define STR71X_I2C_SR2_OFFSET (0x0008) /* 8-bits wide */ +#define STR71X_I2C_CCR_OFFSET (0x000c) /* 8-bits wide */ +#define STR71X_I2C_OAR1_OFFSET (0x0010) /* 8-bits wide */ +#define STR71X_I2C_OAR2_OFFSET (0x0014) /* 8-bits wide */ +#define STR71X_I2C_DR_OFFSET (0x0018) /* 8-bits wide */ +#define STR71X_I2C_ECCR_OFFSET (0x001c) /* 8-bits wide */ + +/* Registers ************************************************************************/ + +#define STR71X_I2C_CR(b) ((b) + STR71X_I2C_SR_OFFSET) +#define STR71X_I2C_SR1(b) ((b) + STR71X_I2C_SR1_OFFSET) +#define STR71X_I2C_SR2(b) ((b) + STR71X_I2C_SR2_OFFSET) +#define STR71X_I2C_CCR(b) ((b) + STR71X_I2C_CCR_OFFSET) +#define STR71X_I2C_OAR1(b) ((b) + STR71X_I2C_OAR1_OFFSET) +#define STR71X_I2C_OAR2(b) ((b) + STR71X_I2C_OAR2_OFFSET) +#define STR71X_I2C_DR(b) ((b) + STR71X_I2C_DR_OFFSET) +#define STR71X_I2C_ECCR(b) ((b) + STR71X_I2C_ECCR_OFFSET) + +#define STR71X_I2C0_CR (STR71X_I2C0_BASE + STR71X_I2C_SR_OFFSET) +#define STR71X_I2C0_SR1 (STR71X_I2C0_BASE + STR71X_I2C_SR1_OFFSET) +#define STR71X_I2C0_SR2 (STR71X_I2C0_BASE + STR71X_I2C_SR2_OFFSET) +#define STR71X_I2C0_CCR (STR71X_I2C0_BASE + STR71X_I2C_CCR_OFFSET) +#define STR71X_I2C0_OAR1 (STR71X_I2C0_BASE + STR71X_I2C_OAR1_OFFSET) +#define STR71X_I2C0_OAR2 (STR71X_I2C0_BASE + STR71X_I2C_OAR2_OFFSET) +#define STR71X_I2C0_DR (STR71X_I2C0_BASE + STR71X_I2C_DR_OFFSET) +#define STR71X_I2C0_ECCR (STR71X_I2C0_BASE + STR71X_I2C_ECCR_OFFSET) + +#define STR71X_I2C1_CR (STR71X_I2C1_BASE + STR71X_I2C_SR_OFFSET) +#define STR71X_I2C1_SR1 (STR71X_I2C1_BASE + STR71X_I2C_SR1_OFFSET) +#define STR71X_I2C1_SR2 (STR71X_I2C1_BASE + STR71X_I2C_SR2_OFFSET) +#define STR71X_I2C1_CCR (STR71X_I2C1_BASE + STR71X_I2C_CCR_OFFSET) +#define STR71X_I2C1_OAR1 (STR71X_I2C1_BASE + STR71X_I2C_OAR1_OFFSET) +#define STR71X_I2C1_OAR2 (STR71X_I2C1_BASE + STR71X_I2C_OAR2_OFFSET) +#define STR71X_I2C1_DR (STR71X_I2C1_BASE + STR71X_I2C_DR_OFFSET) +#define STR71X_I2C1_ECCR (STR71X_I2C1_BASE + STR71X_I2C_ECCR_OFFSET) + +/* Register bit settings ***********************************************************/ + +/* I2C Control Register (CR) */ + +#define STR71X_I2CCR_ITE (0x01) /* Bit 0: Interrupt enable */ +#define STR71X_I2CCR_STOP (0x02) /* Bit 1: Generation of a stop condition */ +#define STR71X_I2CCR_ACK (0x04) /* Bit 2: Acknowledge enable */ +#define STR71X_I2CCR_START (0x08) /* Bit 3: Generation of a start condition */ +#define STR71X_I2CCR_ENGC (0x10) /* Bit 4: Enable general call */ +#define STR71X_I2CCR_PE (0x20) /* Bit 5: Peripheral enable */ + +/* I2C Status Register 1 (SR1) */ + +#define STR71X_I2CSR1_SB (0x01) /* Bit 0: Start bit (master mode) */ +#define STR71X_I2CSR1_MSL (0x02) /* Bit 1: Master/slave */ +#define STR71X_I2CSR1_ADSL (0x04) /* Bit 2: Address matched */ +#define STR71X_I2CSR1_BTF (0x08) /* Bit 3: Byte transfer finished */ +#define STR71X_I2CSR1_BUSY (0x10) /* Bit 4: Bus busy */ +#define STR71X_I2CSR1_TRA (0x20) /* Bit 5: Transmitter/receiver */ +#define STR71X_I2CSR1_ADD10 (0x40) /* Bit 6: 10-bit addressing in master mode */ +#define STR71X_I2CSR1_EVF (0x80) /* Bit 7: Event flag */ + +/* I2C Status Register 2 (SR2) */ + +#define STR71X_I2CSR2_GCAL (0x01) /* Bit 0: General call (slave mode) */ +#define STR71X_I2CSR2_BERR (0x02) /* Bit 1: Bus error */ +#define STR71X_I2CSR2_ARLO (0x04) /* Bit 2: Arbitration lost */ +#define STR71X_I2CSR2_STOPF (0x08) /* Bit 3: Stop detection (slave mode) */ +#define STR71X_I2CSR2_AF (0x10) /* Bit 4: Acknowledge failure */ +#define STR71X_I2CSR2_ENDAD (0x20) /* Bit 5: End of address transmission */ + +/* I2C Clock Control Register (CCR) */ + +#define STR71X_I2CCCR_DIVMASK (0x7f) /* Bits 0-6: 7 bits of the 12-bit clock divider */ +#define STR71X_I2CCCR_FMSM (0x80) /* Bit 7: Fast/standard I2C mode */ + +/* I2C Extended Clock Control Register (ECCR) */ + +#define STR71X_I2CECCR_DIVMASK (0x1f) /* Bits 0-5: 5 bits of the 12-bit clock divider */ + +/* I2C Own Address Register 2 (OAR2) */ + +#define STR71X_I2COAR2_ADDRMASK (0x06) /* Bits 1-2: 2 bits of the 10-bit interface address */ +#define STR71X_I2COAR2_FREQMASK (0xe0) /* Bits 5-7: Frequency */ +#define STR71X_I2COAR2_5_10 (0x00) /* FPCLK1 = 5 to 10 */ +#define STR71X_I2COAR2_10_16 (0x20) /* FPCLK1 = 10 to 16.67 */ +#define STR71X_I2COAR2_16_26 (0x40) /* FPCLK1 = 16.67 to 26.67 */ +#define STR71X_I2COAR2_26_40 (0x60) /* FPCLK1 = 26.67 to 40 */ +#define STR71X_I2COAR2_40_53 (0x80) /* FPCLK1 = 40 to 53.33 */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_I2C_H */ diff --git a/arch/arm/src/str71x/str71x_internal.h b/arch/arm/src/str71x/str71x_internal.h index 99012ca9c9502f19a5d1fadb7970c86d2eecee03..6e60a671cde7c78c8eb9ea23a0990155ba04f160 100644 --- a/arch/arm/src/str71x/str71x_internal.h +++ b/arch/arm/src/str71x/str71x_internal.h @@ -1,156 +1,156 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_internal.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H -#define __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include - -#include - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* Calculate the values of PCLK1 and PCLK2 from settings in board.h. - * - * Example: - * STR71X_RCCU_MAIN_OSC = 4MHz (not divided by 2) - * STR71X_CLK2 = 4MHz - * STR71X_PLL1OUT = 16 * STR71X_CLK2 / 2 = 32MHz - * CLK3 = 32MHz - * RCLK = 32MHz - * PCLK1 = 32MHz / 1 = 32MHz - */ - -/* PLL1OUT derives from Main OSC->CLK2 */ - -#ifdef STR71X_PLL1IN_DIV2 /* CLK2 is input to PLL1 */ -# define STR71X_CLK2 (STR71X_RCCU_MAIN_OSC/2) /* CLK2 is OSC/2 */ -#else -# define STR71X_CLK2 STR71X_RCCU_MAIN_OSC /* CLK2 is OSC */ -#endif - -#define STR71X_PLL1OUT ((STR71X_PLL1OUT_MUL * STR71X_CLK2) / STR71X_PLL1OUT_DIV) - -/* PLL2 OUT derives from HCLK */ - -#define STR71X_PLL2OUT ((STR71X_PLL2OUT_MUL * STR71X_HCLK) / STR71X_PLL2OUT_DIV) - -/* Peripheral clocks derive from PLL1OUT->CLK3->RCLK->PCLK1/2 */ - -#define STR71X_CLK3 STR71X_PLL1OUT /* CLK3 hard coded to be PLL1OUT */ -#define STR71X_RCLK STR71X_CLK3 /* RCLK hard coded to be CLK3 */ -#define STR71X_PCLK1 (STR71X_RCLK / STR71X_APB1_DIV) /* PCLK1 derives from RCLK */ -#define STR71X_PCLK2 (STR71X_RCLK / STR71X_APB2_DIV) /* PCLK2 derives from RCLK */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/******************************************************************************** - * Name: str7x_xtiinitialize - * - * Description: - * Configure XTI for operation. Note that the lines are not used as wake-up - * sources in this implementation. Some extensions would be required for that - * capability. - * - ********************************************************************************/ - -#ifdef CONFIG_STR71X_XTI -extern int str71x_xtiinitialize(void); -#else -# define str71x_xtiinitialize() -#endif /* CONFIG_STR71X_XTI */ - -/******************************************************************************** - * Name: str7x_xticonfig - * - * Description: - * Configure an external line to provide interrupts. Interrupt is configured, - * but disabled on return. - * - ********************************************************************************/ - -#ifdef CONFIG_STR71X_XTI -extern int str71x_xticonfig(int irq, bool rising); -#else -# define str71x_xticonfig(irq,rising) -#endif /* CONFIG_STR71X_XTI */ - -/**************************************************************************** - * Name: str71x_enable_xtiirq - * - * Description: - * Enable an external interrupt. - * - ****************************************************************************/ - -#ifdef CONFIG_STR71X_XTI -extern void str71x_enable_xtiirq(int irq); -#else -# define str71x_enable_xtiirq(irq) -#endif /* CONFIG_STR71X_XTI */ - -/**************************************************************************** - * Name: str71x_disable_xtiirq - * - * Description: - * Disable an external interrupt. - * - ****************************************************************************/ - -#ifdef CONFIG_STR71X_XTI -extern void str71x_disable_xtiirq(int irq); -#else -# define str71x_disable_xtiirq(irq) -#endif /* CONFIG_STR71X_XTI */ - -#endif /* __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H */ +/************************************************************************************ + * arch/arm/src/str71x/str71x_internal.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H +#define __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Calculate the values of PCLK1 and PCLK2 from settings in board.h. + * + * Example: + * STR71X_RCCU_MAIN_OSC = 4MHz (not divided by 2) + * STR71X_CLK2 = 4MHz + * STR71X_PLL1OUT = 16 * STR71X_CLK2 / 2 = 32MHz + * CLK3 = 32MHz + * RCLK = 32MHz + * PCLK1 = 32MHz / 1 = 32MHz + */ + +/* PLL1OUT derives from Main OSC->CLK2 */ + +#ifdef STR71X_PLL1IN_DIV2 /* CLK2 is input to PLL1 */ +# define STR71X_CLK2 (STR71X_RCCU_MAIN_OSC/2) /* CLK2 is OSC/2 */ +#else +# define STR71X_CLK2 STR71X_RCCU_MAIN_OSC /* CLK2 is OSC */ +#endif + +#define STR71X_PLL1OUT ((STR71X_PLL1OUT_MUL * STR71X_CLK2) / STR71X_PLL1OUT_DIV) + +/* PLL2 OUT derives from HCLK */ + +#define STR71X_PLL2OUT ((STR71X_PLL2OUT_MUL * STR71X_HCLK) / STR71X_PLL2OUT_DIV) + +/* Peripheral clocks derive from PLL1OUT->CLK3->RCLK->PCLK1/2 */ + +#define STR71X_CLK3 STR71X_PLL1OUT /* CLK3 hard coded to be PLL1OUT */ +#define STR71X_RCLK STR71X_CLK3 /* RCLK hard coded to be CLK3 */ +#define STR71X_PCLK1 (STR71X_RCLK / STR71X_APB1_DIV) /* PCLK1 derives from RCLK */ +#define STR71X_PCLK2 (STR71X_RCLK / STR71X_APB2_DIV) /* PCLK2 derives from RCLK */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/******************************************************************************** + * Name: str7x_xtiinitialize + * + * Description: + * Configure XTI for operation. Note that the lines are not used as wake-up + * sources in this implementation. Some extensions would be required for that + * capability. + * + ********************************************************************************/ + +#ifdef CONFIG_STR71X_XTI +extern int str71x_xtiinitialize(void); +#else +# define str71x_xtiinitialize() +#endif /* CONFIG_STR71X_XTI */ + +/******************************************************************************** + * Name: str7x_xticonfig + * + * Description: + * Configure an external line to provide interrupts. Interrupt is configured, + * but disabled on return. + * + ********************************************************************************/ + +#ifdef CONFIG_STR71X_XTI +extern int str71x_xticonfig(int irq, bool rising); +#else +# define str71x_xticonfig(irq,rising) +#endif /* CONFIG_STR71X_XTI */ + +/**************************************************************************** + * Name: str71x_enable_xtiirq + * + * Description: + * Enable an external interrupt. + * + ****************************************************************************/ + +#ifdef CONFIG_STR71X_XTI +extern void str71x_enable_xtiirq(int irq); +#else +# define str71x_enable_xtiirq(irq) +#endif /* CONFIG_STR71X_XTI */ + +/**************************************************************************** + * Name: str71x_disable_xtiirq + * + * Description: + * Disable an external interrupt. + * + ****************************************************************************/ + +#ifdef CONFIG_STR71X_XTI +extern void str71x_disable_xtiirq(int irq); +#else +# define str71x_disable_xtiirq(irq) +#endif /* CONFIG_STR71X_XTI */ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H */ diff --git a/arch/arm/src/str71x/str71x_irq.c b/arch/arm/src/str71x/str71x_irq.c index c5c359cdf3b1b0f33e2f17c16064fa58e67d694c..3bf8706683c0b5fb111386867d355998e6655356 100644 --- a/arch/arm/src/str71x/str71x_irq.c +++ b/arch/arm/src/str71x/str71x_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/st71x/st71x_irq.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/str71x/str71x_lowputc.c b/arch/arm/src/str71x/str71x_lowputc.c index a34b185c8ff56a232ff85166d81e7c2cedece967..fde33adb4c3c900d92ea5d9efacb4e5ceed02d73 100644 --- a/arch/arm/src/str71x/str71x_lowputc.c +++ b/arch/arm/src/str71x/str71x_lowputc.c @@ -2,7 +2,7 @@ * arch/arm/src/str71x/str71x_lowputc.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/str71x/str71x_map.h b/arch/arm/src/str71x/str71x_map.h index ad29e4d8d260a6dcfa673a6ebf6164609ecb286e..e61be9e3e489a29a0996b026513a05ccda5cec5c 100644 --- a/arch/arm/src/str71x/str71x_map.h +++ b/arch/arm/src/str71x/str71x_map.h @@ -1,99 +1,99 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_map.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_MAP_H -#define __ARCH_ARM_SRC_STR71X_STR71X_MAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* Memory Map ***********************************************************************/ - -#define STR71X_FLASHRAMEMI_BASE (0x00000000) /* Flash alias for booting */ -#define STR71X_RAM_BASE (0x20000000) -#define STR71X_FLASH_BASE (0x40000000) -#define STR71X_FLASHREG_BASE (0x40100000) -#define STR71X_EXTMEM_BASE (0x60000000) -#define STR71X_EMI_BASE (STR71X_EXTMEM_BASE + 0x0c000000) -#define STR71X_RCCU_BASE (0xa0000000) -#define STR71X_PCU_BASE (0xa0000040) -#define STR71X_APB1_BASE (0xc0000000) -#define STR71X_I2C0_BASE (STR71X_APB1_BASE + 0x1000) -#define STR71X_I2C1_BASE (STR71X_APB1_BASE + 0x2000) -#define STR71X_UART0_BASE (STR71X_APB1_BASE + 0x4000) -#define STR71X_UART1_BASE (STR71X_APB1_BASE + 0x5000) -#define STR71X_UART2_BASE (STR71X_APB1_BASE + 0x6000) -#define STR71X_UART3_BASE (STR71X_APB1_BASE + 0x7000) -#define STR71X_USBRAM_BASE (STR71X_APB1_BASE + 0x8000) -#define STR71X_USB_BASE (STR71X_APB1_BASE + 0x8800) -#define STR71X_CAN_BASE (STR71X_APB1_BASE + 0x9000) -#define STR71X_BSPI0_BASE (STR71X_APB1_BASE + 0xa000) -#define STR71X_BSPI1_BASE (STR71X_APB1_BASE + 0xb000) -#define STR71X_HDLCRAM_BASE (STR71X_APB1_BASE + 0xe000) -#define STR71X_APB2_BASE (0xe0000000) -#define STR71X_XTI_BASE (STR71X_APB2_BASE + 0x1000) -#define STR71X_GPIO0_BASE (STR71X_APB2_BASE + 0x3000) -#define STR71X_GPIO1_BASE (STR71X_APB2_BASE + 0x4000) -#define STR71X_GPIO2_BASE (STR71X_APB2_BASE + 0x5000) -#define STR71X_ADC12_BASE (STR71X_APB2_BASE + 0x7000) -#define STR71X_CLKOUT_BASE (STR71X_APB2_BASE + 0x8000) -#define STR71X_TIMER0_BASE (STR71X_APB2_BASE + 0x9000) -#define STR71X_TIMER1_BASE (STR71X_APB2_BASE + 0xa000) -#define STR71X_TIMER2_BASE (STR71X_APB2_BASE + 0xb000) -#define STR71X_TIMER3_BASE (STR71X_APB2_BASE + 0xc000) -#define STR71X_RTC_BASE (STR71X_APB2_BASE + 0xd000) -#define STR71X_WDOG_BASE (STR71X_APB2_BASE + 0xe000) -#define STR71X_EIC_BASE (0xfffff800) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif // __ARCH_ARM_SRC_STR71X_STR71X_MAP_H +/************************************************************************************ + * arch/arm/src/str71x/str71x_map.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_MAP_H +#define __ARCH_ARM_SRC_STR71X_STR71X_MAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Memory Map ***********************************************************************/ + +#define STR71X_FLASHRAMEMI_BASE (0x00000000) /* Flash alias for booting */ +#define STR71X_RAM_BASE (0x20000000) +#define STR71X_FLASH_BASE (0x40000000) +#define STR71X_FLASHREG_BASE (0x40100000) +#define STR71X_EXTMEM_BASE (0x60000000) +#define STR71X_EMI_BASE (STR71X_EXTMEM_BASE + 0x0c000000) +#define STR71X_RCCU_BASE (0xa0000000) +#define STR71X_PCU_BASE (0xa0000040) +#define STR71X_APB1_BASE (0xc0000000) +#define STR71X_I2C0_BASE (STR71X_APB1_BASE + 0x1000) +#define STR71X_I2C1_BASE (STR71X_APB1_BASE + 0x2000) +#define STR71X_UART0_BASE (STR71X_APB1_BASE + 0x4000) +#define STR71X_UART1_BASE (STR71X_APB1_BASE + 0x5000) +#define STR71X_UART2_BASE (STR71X_APB1_BASE + 0x6000) +#define STR71X_UART3_BASE (STR71X_APB1_BASE + 0x7000) +#define STR71X_USBRAM_BASE (STR71X_APB1_BASE + 0x8000) +#define STR71X_USB_BASE (STR71X_APB1_BASE + 0x8800) +#define STR71X_CAN_BASE (STR71X_APB1_BASE + 0x9000) +#define STR71X_BSPI0_BASE (STR71X_APB1_BASE + 0xa000) +#define STR71X_BSPI1_BASE (STR71X_APB1_BASE + 0xb000) +#define STR71X_HDLCRAM_BASE (STR71X_APB1_BASE + 0xe000) +#define STR71X_APB2_BASE (0xe0000000) +#define STR71X_XTI_BASE (STR71X_APB2_BASE + 0x1000) +#define STR71X_GPIO0_BASE (STR71X_APB2_BASE + 0x3000) +#define STR71X_GPIO1_BASE (STR71X_APB2_BASE + 0x4000) +#define STR71X_GPIO2_BASE (STR71X_APB2_BASE + 0x5000) +#define STR71X_ADC12_BASE (STR71X_APB2_BASE + 0x7000) +#define STR71X_CLKOUT_BASE (STR71X_APB2_BASE + 0x8000) +#define STR71X_TIMER0_BASE (STR71X_APB2_BASE + 0x9000) +#define STR71X_TIMER1_BASE (STR71X_APB2_BASE + 0xa000) +#define STR71X_TIMER2_BASE (STR71X_APB2_BASE + 0xb000) +#define STR71X_TIMER3_BASE (STR71X_APB2_BASE + 0xc000) +#define STR71X_RTC_BASE (STR71X_APB2_BASE + 0xd000) +#define STR71X_WDOG_BASE (STR71X_APB2_BASE + 0xe000) +#define STR71X_EIC_BASE (0xfffff800) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif // __ARCH_ARM_SRC_STR71X_STR71X_MAP_H diff --git a/arch/arm/src/str71x/str71x_pcu.h b/arch/arm/src/str71x/str71x_pcu.h index 19050253e07b04efc8180558b3d8220df0feb2ab..5e23204f040e843df834e8b3f542f1617583bee3 100644 --- a/arch/arm/src/str71x/str71x_pcu.h +++ b/arch/arm/src/str71x/str71x_pcu.h @@ -1,159 +1,159 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_pcu.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_PCU_H -#define __ARCH_ARM_SRC_STR71X_STR71X_PCU_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "str71x_map.h" - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* Power Control Unit (PCU) register offsets ****************************************/ - -#define STR71X_PCU_MDIVR_OFFSET (0x0000) /* 16-bits wide */ -#define STR71X_PCU_PDIVR_OFFSET (0x0004) /* 16-bits wide */ -#define STR71X_PCU_RSTR_OFFSET (0x0008) /* 16-bits wide */ -#define STR71X_PCU_PLL2CR_OFFSET (0x000c) /* 16-bits wide */ -#define STR71X_PCU_BOOTCR_OFFSET (0x0010) /* 16-bits wide */ -#define STR71X_PCU_PWRCR_OFFSET (0x0014) /* 16-bits wide */ - -/* Power Control Unit (PCU) register addresses **************************************/ - -#define STR71X_PCU_MDIVR (STR71X_PCU_BASE + STR71X_PCU_MDIVR_OFFSET) -#define STR71X_PCU_PDIVR (STR71X_PCU_BASE + STR71X_PCU_PDIVR_OFFSET) -#define STR71X_PCU_RSTR (STR71X_PCU_BASE + STR71X_PCU_RSTR_OFFSET) -#define STR71X_PCU_PLL2CR (STR71X_PCU_BASE + STR71X_PCU_PLL2CR_OFFSET) -#define STR71X_PCU_BOOTCR (STR71X_PCU_BASE + STR71X_PCU_BOOTCR_OFFSET) -#define STR71X_PCU_PWRCR (STR71X_PCU_BASE + STR71X_PCU_PWRCR_OFFSET) - -/* Register bit settings ************************************************************/ - -/* PCU MDIVR register bit definitions */ - -#define STR71X_PCUMDIVR_FACTMASK (0x0003) /* Bits 0-1: Division factor for main system clock */ -#define STR71X_PCUMDIVR_DIV1 (0x0000) /* MCLK = RCLK */ -#define STR71X_PCUMDIVR_DIV2 (0x0001) /* MCLK = RCLK / 2 */ -#define STR71X_PCUMDIVR_DIV4 (0x0002) /* MCLK = RCLK / 4 */ -#define STR71X_PCUMDIVR_DIV8 (0x0003) /* MCLK = RCLK / 8 */ - -/* PCU PDIVR register bit definitions */ - -#define STR71X_PCUPDIVR_FACT1MASK (0x0003) /* Bits 0-1: Division factor for APB1 peripherals */ -#define STR71X_PCUPDIVR_APB1DIV1 (0x0000) /* PCLK1 = RCLK */ -#define STR71X_PCUPDIVR_APB1DIV2 (0x0001) /* PCLK1 = RCLK / 2 */ -#define STR71X_PCUPDIVR_APB1DIV4 (0x0002) /* PCLK1 = RCLK / 4 */ -#define STR71X_PCUPDIVR_APB1DIV8 (0x0003) /* PCLK1 = RCLK / 8 */ -#define STR71X_PCUPDIVR_FACT2MASK (0x0300) /* Bits 8-9: Division factor for APB2 peripherals */ -#define STR71X_PCUPDIVR_APB2DIV1 (0x0000) /* PCLK2 = RCLK */ -#define STR71X_PCUPDIVR_APB2DIV2 (0x0100) /* PCLK2 = RCLK / 2 */ -#define STR71X_PCUPDIVR_APB2DIV4 (0x0200) /* PCLK2 = RCLK / 4 */ -#define STR71X_PCUPDIVR_APB2DIV8 (0x0300) /* PCLK2 = RCLK / 8 */ - -/* PCU RSTR register bit definitions */ - -#define STR71X_PCURSTR_EMIRESET (0x0004) /* Bit 2: EMI reset */ - -/* PCU PLL2CR register bit definitions */ - -#define STR71X_PCUPPL2CR_DXMASK (0x0007) /* Bits 0-2: PLL2 output clock divider */ -#define STR71X_PCUPPL2CR_DIV1 (0x0000) /* PLL2 / 1 */ -#define STR71X_PCUPPL2CR_DIV2 (0x0001) /* PLL2 / 2 */ -#define STR71X_PCUPPL2CR_DIV3 (0x0002) /* PLL2 / 3 */ -#define STR71X_PCUPPL2CR_DIV4 (0x0003) /* PLL2 / 4 */ -#define STR71X_PCUPPL2CR_DIV5 (0x0004) /* PLL2 / 5 */ -#define STR71X_PCUPPL2CR_DIV6 (0x0005) /* PLL2 / 6 */ -#define STR71X_PCUPPL2CR_DIV7 (0x0006) /* PLL2 / 7 */ -#define STR71X_PCUPPL2CR_OFF (0x0007) /* PLL2 OFF */ -#define STR71X_PCUPPL2CR_MXMASK (0x0030) /* Bits 4-5: PLL2 multiplier */ -#define STR71X_PCUPPL2CR_MUL20 (0x0000) /* CLK2 * 20 */ -#define STR71X_PCUPPL2CR_MUL12 (0x0010) /* CLK2 * 12 */ -#define STR71X_PCUPPL2CR_MUL28 (0x0020) /* CLK2 * 28 */ -#define STR71X_PCUPPL2CR_MUL16 (0x0030) /* CLK2 * 16 */ -#define STR71X_PCUPPL2CR_FRQRNG (0x0040) /* Bit 6: PLL2 frequency range selection */ -#define STR71X_PCUPPL2CR_PLLEN (0x0080) /* Bit 7: PLL2 enable */ -#define STR71X_PCUPPL2CR_USBEN (0x0100) /* Bit 8: Enable PLL clock to USB */ -#define STR71X_PCUPPL2CR_IRQMASK (0x0200) /* Bit 9: Enable interrupt request CPU on lock transition */ -#define STR71X_PCUPPL2CR_IRQPEND (0x0400) /* Bit 10: Interrtup request to CPU on lock transition pending */ -#define STR71X_PCUPPL2CR_LOCK (0x8000) /* Bit 15: PLL2 locked */ - -/* PCU BOOTCR register bit definitions */ - -#define STR71X_PCUBOOTCR_BOOTMASK (0x0003) /* Bits 0-1: Boot mode */ -#define STR71X_PCUBOOTCR_BMFLASH (0x0000) /* FLASH */ -#define STR71X_PCUBOOTCR_BMRAM (0x0002) /* RAM */ -#define STR71X_PCUBOOTCR_BMEXTMEM (0x0003) /* FLASH */ -#define STR71X_PCUBOOTCR_BSPIOEN (0x0004) /* Bit 2: Enable BSPI0 */ -#define STR71X_PCUBOOTCR_USBFILTEN (0x0008) /* Bit 3: Enable USB standby filtering */ -#define STR71X_PCUBOOTCR_LPOWDBGEN (0x0010) /* Bit 4: Enable reserved features for STOP mode */ -#define STR71X_PCUBOOTCR_ACDEN (0x0020) /* Bit 5: Enable ADC */ -#define STR71X_PCUBOOTCR_CANACTIVE (0x0040) /* Bit 6: CAN active */ -#define STR71X_PCUBOOTCR_HDLCACTIVE (0x0080) /* Bit 7: HDLC active */ -#define STR71X_PCUBOOTCR_PKG64 (0x0200) /* Bit 9: Die is hosted in 64-pin package */ - -/* PCU PWRCR register bit definitions */ - -#define STR71X_PCUPWRCR_VRBYP (0x0008) /* Bit 3: Main regulator bypass */ -#define STR71X_PCUPWRCR_LPRWFI (0x0010) /* Bit 4: Low power regulator in wait-for-interrupt mode */ -#define STR71X_PCUPWRCR_LPRBYP (0x0020) /* Bit 5: Low power regulator bypass */ -#define STR71X_PCUPWRCR_PWRDWN (0x0040) /* Bit 6: Activate standby mode */ -#define STR71X_PCUPWRCR_OSCBYP (0x0080) /* Bit 7: 32KHz oscillator bypass */ -#define STR71X_PCUPWRCR_LVDDIS (0x0100) /* Bit 8: Low voltage detector disable */ -#define STR71X_PCUPWRCR_FLASHLP (0x0200) /* Bit 9: FLASH low speed (low power) select */ -#define STR71X_PCUPWRCR_VROK (0x1000) /* Bit 12: Voltage regulator OK */ -#define STR71X_PCUPWRCR_WKUPALRM (0x2000) /* Bit 13: Wakeup or alarm active */ -#define STR71X_PCUPWRCR_BUSY (0x4000) /* Bit 14: PCU register backup logic busy */ -#define STR71X_PCUPWRCR_WREN (0x8000) /* Bit 15: PCU register write enable */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STR71X_STR71X_PCU_H */ +/************************************************************************************ + * arch/arm/src/str71x/str71x_pcu.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_PCU_H +#define __ARCH_ARM_SRC_STR71X_STR71X_PCU_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Power Control Unit (PCU) register offsets ****************************************/ + +#define STR71X_PCU_MDIVR_OFFSET (0x0000) /* 16-bits wide */ +#define STR71X_PCU_PDIVR_OFFSET (0x0004) /* 16-bits wide */ +#define STR71X_PCU_RSTR_OFFSET (0x0008) /* 16-bits wide */ +#define STR71X_PCU_PLL2CR_OFFSET (0x000c) /* 16-bits wide */ +#define STR71X_PCU_BOOTCR_OFFSET (0x0010) /* 16-bits wide */ +#define STR71X_PCU_PWRCR_OFFSET (0x0014) /* 16-bits wide */ + +/* Power Control Unit (PCU) register addresses **************************************/ + +#define STR71X_PCU_MDIVR (STR71X_PCU_BASE + STR71X_PCU_MDIVR_OFFSET) +#define STR71X_PCU_PDIVR (STR71X_PCU_BASE + STR71X_PCU_PDIVR_OFFSET) +#define STR71X_PCU_RSTR (STR71X_PCU_BASE + STR71X_PCU_RSTR_OFFSET) +#define STR71X_PCU_PLL2CR (STR71X_PCU_BASE + STR71X_PCU_PLL2CR_OFFSET) +#define STR71X_PCU_BOOTCR (STR71X_PCU_BASE + STR71X_PCU_BOOTCR_OFFSET) +#define STR71X_PCU_PWRCR (STR71X_PCU_BASE + STR71X_PCU_PWRCR_OFFSET) + +/* Register bit settings ************************************************************/ + +/* PCU MDIVR register bit definitions */ + +#define STR71X_PCUMDIVR_FACTMASK (0x0003) /* Bits 0-1: Division factor for main system clock */ +#define STR71X_PCUMDIVR_DIV1 (0x0000) /* MCLK = RCLK */ +#define STR71X_PCUMDIVR_DIV2 (0x0001) /* MCLK = RCLK / 2 */ +#define STR71X_PCUMDIVR_DIV4 (0x0002) /* MCLK = RCLK / 4 */ +#define STR71X_PCUMDIVR_DIV8 (0x0003) /* MCLK = RCLK / 8 */ + +/* PCU PDIVR register bit definitions */ + +#define STR71X_PCUPDIVR_FACT1MASK (0x0003) /* Bits 0-1: Division factor for APB1 peripherals */ +#define STR71X_PCUPDIVR_APB1DIV1 (0x0000) /* PCLK1 = RCLK */ +#define STR71X_PCUPDIVR_APB1DIV2 (0x0001) /* PCLK1 = RCLK / 2 */ +#define STR71X_PCUPDIVR_APB1DIV4 (0x0002) /* PCLK1 = RCLK / 4 */ +#define STR71X_PCUPDIVR_APB1DIV8 (0x0003) /* PCLK1 = RCLK / 8 */ +#define STR71X_PCUPDIVR_FACT2MASK (0x0300) /* Bits 8-9: Division factor for APB2 peripherals */ +#define STR71X_PCUPDIVR_APB2DIV1 (0x0000) /* PCLK2 = RCLK */ +#define STR71X_PCUPDIVR_APB2DIV2 (0x0100) /* PCLK2 = RCLK / 2 */ +#define STR71X_PCUPDIVR_APB2DIV4 (0x0200) /* PCLK2 = RCLK / 4 */ +#define STR71X_PCUPDIVR_APB2DIV8 (0x0300) /* PCLK2 = RCLK / 8 */ + +/* PCU RSTR register bit definitions */ + +#define STR71X_PCURSTR_EMIRESET (0x0004) /* Bit 2: EMI reset */ + +/* PCU PLL2CR register bit definitions */ + +#define STR71X_PCUPPL2CR_DXMASK (0x0007) /* Bits 0-2: PLL2 output clock divider */ +#define STR71X_PCUPPL2CR_DIV1 (0x0000) /* PLL2 / 1 */ +#define STR71X_PCUPPL2CR_DIV2 (0x0001) /* PLL2 / 2 */ +#define STR71X_PCUPPL2CR_DIV3 (0x0002) /* PLL2 / 3 */ +#define STR71X_PCUPPL2CR_DIV4 (0x0003) /* PLL2 / 4 */ +#define STR71X_PCUPPL2CR_DIV5 (0x0004) /* PLL2 / 5 */ +#define STR71X_PCUPPL2CR_DIV6 (0x0005) /* PLL2 / 6 */ +#define STR71X_PCUPPL2CR_DIV7 (0x0006) /* PLL2 / 7 */ +#define STR71X_PCUPPL2CR_OFF (0x0007) /* PLL2 OFF */ +#define STR71X_PCUPPL2CR_MXMASK (0x0030) /* Bits 4-5: PLL2 multiplier */ +#define STR71X_PCUPPL2CR_MUL20 (0x0000) /* CLK2 * 20 */ +#define STR71X_PCUPPL2CR_MUL12 (0x0010) /* CLK2 * 12 */ +#define STR71X_PCUPPL2CR_MUL28 (0x0020) /* CLK2 * 28 */ +#define STR71X_PCUPPL2CR_MUL16 (0x0030) /* CLK2 * 16 */ +#define STR71X_PCUPPL2CR_FRQRNG (0x0040) /* Bit 6: PLL2 frequency range selection */ +#define STR71X_PCUPPL2CR_PLLEN (0x0080) /* Bit 7: PLL2 enable */ +#define STR71X_PCUPPL2CR_USBEN (0x0100) /* Bit 8: Enable PLL clock to USB */ +#define STR71X_PCUPPL2CR_IRQMASK (0x0200) /* Bit 9: Enable interrupt request CPU on lock transition */ +#define STR71X_PCUPPL2CR_IRQPEND (0x0400) /* Bit 10: Interrtup request to CPU on lock transition pending */ +#define STR71X_PCUPPL2CR_LOCK (0x8000) /* Bit 15: PLL2 locked */ + +/* PCU BOOTCR register bit definitions */ + +#define STR71X_PCUBOOTCR_BOOTMASK (0x0003) /* Bits 0-1: Boot mode */ +#define STR71X_PCUBOOTCR_BMFLASH (0x0000) /* FLASH */ +#define STR71X_PCUBOOTCR_BMRAM (0x0002) /* RAM */ +#define STR71X_PCUBOOTCR_BMEXTMEM (0x0003) /* FLASH */ +#define STR71X_PCUBOOTCR_BSPIOEN (0x0004) /* Bit 2: Enable BSPI0 */ +#define STR71X_PCUBOOTCR_USBFILTEN (0x0008) /* Bit 3: Enable USB standby filtering */ +#define STR71X_PCUBOOTCR_LPOWDBGEN (0x0010) /* Bit 4: Enable reserved features for STOP mode */ +#define STR71X_PCUBOOTCR_ACDEN (0x0020) /* Bit 5: Enable ADC */ +#define STR71X_PCUBOOTCR_CANACTIVE (0x0040) /* Bit 6: CAN active */ +#define STR71X_PCUBOOTCR_HDLCACTIVE (0x0080) /* Bit 7: HDLC active */ +#define STR71X_PCUBOOTCR_PKG64 (0x0200) /* Bit 9: Die is hosted in 64-pin package */ + +/* PCU PWRCR register bit definitions */ + +#define STR71X_PCUPWRCR_VRBYP (0x0008) /* Bit 3: Main regulator bypass */ +#define STR71X_PCUPWRCR_LPRWFI (0x0010) /* Bit 4: Low power regulator in wait-for-interrupt mode */ +#define STR71X_PCUPWRCR_LPRBYP (0x0020) /* Bit 5: Low power regulator bypass */ +#define STR71X_PCUPWRCR_PWRDWN (0x0040) /* Bit 6: Activate standby mode */ +#define STR71X_PCUPWRCR_OSCBYP (0x0080) /* Bit 7: 32KHz oscillator bypass */ +#define STR71X_PCUPWRCR_LVDDIS (0x0100) /* Bit 8: Low voltage detector disable */ +#define STR71X_PCUPWRCR_FLASHLP (0x0200) /* Bit 9: FLASH low speed (low power) select */ +#define STR71X_PCUPWRCR_VROK (0x1000) /* Bit 12: Voltage regulator OK */ +#define STR71X_PCUPWRCR_WKUPALRM (0x2000) /* Bit 13: Wakeup or alarm active */ +#define STR71X_PCUPWRCR_BUSY (0x4000) /* Bit 14: PCU register backup logic busy */ +#define STR71X_PCUPWRCR_WREN (0x8000) /* Bit 15: PCU register write enable */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_PCU_H */ diff --git a/arch/arm/src/str71x/str71x_prccu.c b/arch/arm/src/str71x/str71x_prccu.c index 61cee03dde2459373f735b6f36d5dc5e95a6103f..5379b11642cd94380ec3cfb4c13ab7af3ce746c6 100644 --- a/arch/arm/src/str71x/str71x_prccu.c +++ b/arch/arm/src/str71x/str71x_prccu.c @@ -2,7 +2,7 @@ * arch/arm/src/str71x/str71x_prccu.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/str71x/str71x_rccu.h b/arch/arm/src/str71x/str71x_rccu.h index 858bd80892b7b84da004b205969ddea6f78cdaa7..ed3114c2c9b27ef13df24100af2b9b5a8309ffdc 100644 --- a/arch/arm/src/str71x/str71x_rccu.h +++ b/arch/arm/src/str71x/str71x_rccu.h @@ -1,143 +1,143 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_rccu.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_RCCU_H -#define __ARCH_ARM_SRC_STR71X_STR71X_RCCU_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "str71x_map.h" - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* Reset and Clock Control Unit (RCCU) register offsets *****************************/ - -/* All registers are 32-bits wide, but with the top 16 bits "reserved" */ - -#define STR71X_RCCU_CCR_OFFSET (0x0000) /* 32-bits wide */ -#define STR71X_RCCU_CFR_OFFSET (0x0008) /* 32-bits wide */ -#define STR71X_RCCU_PLL1CR_OFFSET (0x0018) /* 32-bits wide */ -#define STR71X_RCCU_PER_OFFSET (0x001c) /* 32-bits wide */ -#define STR71X_RCCU_SMR_OFFSET (0x0020) /* 32-bits wide */ - -/* Reset and Clock Control Unit (RCCU) register addresses ***************************/ - -#define STR71X_RCCU_CCR (STR71X_RCCU_BASE + STR71X_RCCU_CCR_OFFSET) -#define STR71X_RCCU_CFR (STR71X_RCCU_BASE + STR71X_RCCU_CFR_OFFSET) -#define STR71X_RCCU_PLL1CR (STR71X_RCCU_BASE + STR71X_RCCU_PLL1CR_OFFSET) -#define STR71X_RCCU_PER (STR71X_RCCU_BASE + STR71X_RCCU_PER_OFFSET) -#define STR71X_RCCU_SMR (STR71X_RCCU_BASE + STR71X_RCCU_SMR_OFFSET) - -/* Register bit settings ************************************************************/ - -/* RCCU CCR register bit definitions */ - -#define STR71X_RCCUCCR_LPOWFI (0x00000001) /* Bit 0: Low power mode in wait-for-interrupt mode */ -#define STR71X_RCCUCCR_WFICLKSEL (0x00000002) /* Bit 1: WFI clock select */ -#define STR71X_RCCUCCR_CKAFSEL (0x00000004) /* Bit 2: Alternate function clock select */ -#define STR71X_RCCUCCR_SRESEN (0x00000008) /* Bit 3: Software reset enable */ -#define STR71X_RCCUCCR_ENCLOCK (0x00000080) /* Bit 7: Lock interrupt enable */ -#define STR71X_RCCUCCR_ENCKAF (0x00000100) /* Bit 8: CKAF interrupt enable */ -#define STR71X_RCCUCCR_ENCK216 (0x00000200) /* Bit 9: CK2_16 interrupt enable */ -#define STR71X_RCCUCCR_ENSTOP (0x00000400) /* Bit 10: Stop interrupt enable */ -#define STR71X_RCCUCCR_ENHALT (0x00000800) /* Bit 11: Enable halt */ - -/* RCCU CFR register bit definitions */ - -#define STR71X_RCCUCFR_CSUCKSEL (0x00000001) /* Bit 0: CSU clock select */ -#define STR71X_RCCUCFR_LOCK (0x00000002) /* Bit 1: PLL locked-in */ -#define STR71X_RCCUCFR_CKAFST (0x00000004) /* Bit 2: CK_AF status */ -#define STR71X_RCCUCFR_CK216 (0x00000008) /* Bit 3: CLK2/16 selection */ -#define STR71X_RCCUCFR_CKSTOPEN (0x00000010) /* Bit 4: Clock stop enable */ -#define STR71X_RCCUCFR_SOFTRES (0x00000020) /* Bit 5: Software reset */ -#define STR71X_RCCUCFR_WDGRES (0x00000040) /* Bit 6: Watchdog reset */ -#define STR71X_RCCUCFR_RTCALARM (0x00000080) /* Bit 7: RTC alarm reset */ -#define STR71X_RCCUCFR_LVDRES (0x00000200) /* Bit 9: Voltage regulator low voltage detector reset */ -#define STR71X_RCCUCFR_WKPRES (0x00000400) /* Bit 10: External wakeup */ -#define STR71X_RCCUCFR_LOCKI (0x00000800) /* Bit 11: Lock interrupt pending */ -#define STR71X_RCCUCFR_CKAFI (0x00001000) /* Bit 12: CK_AF switching interrupt pending */ -#define STR71X_RCCUCFR_CK216I (0x00002000) /* Bit 13: CK2_16 switching interrupt pending */ -#define STR71X_RCCUCFR_STOPI (0x00004000) /* Bit 14: Stop interrupt pending */ -#define STR71X_RCCUCFR_DIV2 (0x00008000) /* Bit 15: OSCIN divided by 2 */ - -/* RCCU PPL1CR register bit definitions */ - -#define STR71X_RCCUPLL1CR_DXMASK (0x00000003) /* Bit 0-2: PLL1 clock divisor */ -#define STR71X_RCCUPLL1CR_DIV1 (0x00000000) /* PLLCK / 1 */ -#define STR71X_RCCUPLL1CR_DIV2 (0x00000001) /* PLLCK / 2 */ -#define STR71X_RCCUPLL1CR_DIV3 (0x00000002) /* PLLCK / 3 */ -#define STR71X_RCCUPLL1CR_DIV4 (0x00000003) /* PLLCK / 4 */ -#define STR71X_RCCUPLL1CR_DIV5 (0x00000004) /* PLLCK / 5 */ -#define STR71X_RCCUPLL1CR_DIV6 (0x00000005) /* PLLCK / 6 */ -#define STR71X_RCCUPLL1CR_DIV7 (0x00000006) /* PLLCK / 7 */ -#define STR71X_RCCUPLL1CR_CLK2 (0x00000007) /* FREEN==0: CLK2 */ -#define STR71X_RCCUPLL1CR_FREERM (0x00000007) /* FREEN==1: PLL1 in free running mode */ -#define STR71X_RCCUPLL1CR_MXMASK (0x00000030) /* Bit 4-5: PLL1 clock multiplier */ -#define STR71X_RCCUPLL1CR_MUL20 (0x00000000) /* CLK2 * 20 */ -#define STR71X_RCCUPLL1CR_MUL12 (0x00000010) /* CLK2 * 12 */ -#define STR71X_RCCUPLL1CR_MUL24 (0x00000020) /* CLK2 * 24 */ -#define STR71X_RCCUPLL1CR_MUL16 (0x00000030) /* CLK2 * 16 */ -#define STR71X_RCCUPLL1CR_FREFRANGE (0x00000040) /* Bit 6: Reference frequency range select */ -#define STR71X_RCCUPLL1CR_FREEN (0x00000080) /* Bit 7: PKL free running mode */ - -/* RCCU PER register bit definitions */ - -#define STR71X_RCCUPER_EMI (0x00000004) /* Bit 2: EMI */ -#define STR71X_RCCUPER_USBKERNEL (0x00000010) /* Bit 4: USB Kernel */ - -/* RCCU SMR register bit definitions */ - -#define STR71X_RCCUSMR_WFI (0x00000001) /* Bit 0: Wait for interrupt */ -#define STR71X_RCCUSMR_HALT (0x00000000) /* Bit 1: Halt */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STR71X_STR71X_RCCU_H */ +/************************************************************************************ + * arch/arm/src/str71x/str71x_rccu.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_RCCU_H +#define __ARCH_ARM_SRC_STR71X_STR71X_RCCU_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Reset and Clock Control Unit (RCCU) register offsets *****************************/ + +/* All registers are 32-bits wide, but with the top 16 bits "reserved" */ + +#define STR71X_RCCU_CCR_OFFSET (0x0000) /* 32-bits wide */ +#define STR71X_RCCU_CFR_OFFSET (0x0008) /* 32-bits wide */ +#define STR71X_RCCU_PLL1CR_OFFSET (0x0018) /* 32-bits wide */ +#define STR71X_RCCU_PER_OFFSET (0x001c) /* 32-bits wide */ +#define STR71X_RCCU_SMR_OFFSET (0x0020) /* 32-bits wide */ + +/* Reset and Clock Control Unit (RCCU) register addresses ***************************/ + +#define STR71X_RCCU_CCR (STR71X_RCCU_BASE + STR71X_RCCU_CCR_OFFSET) +#define STR71X_RCCU_CFR (STR71X_RCCU_BASE + STR71X_RCCU_CFR_OFFSET) +#define STR71X_RCCU_PLL1CR (STR71X_RCCU_BASE + STR71X_RCCU_PLL1CR_OFFSET) +#define STR71X_RCCU_PER (STR71X_RCCU_BASE + STR71X_RCCU_PER_OFFSET) +#define STR71X_RCCU_SMR (STR71X_RCCU_BASE + STR71X_RCCU_SMR_OFFSET) + +/* Register bit settings ************************************************************/ + +/* RCCU CCR register bit definitions */ + +#define STR71X_RCCUCCR_LPOWFI (0x00000001) /* Bit 0: Low power mode in wait-for-interrupt mode */ +#define STR71X_RCCUCCR_WFICLKSEL (0x00000002) /* Bit 1: WFI clock select */ +#define STR71X_RCCUCCR_CKAFSEL (0x00000004) /* Bit 2: Alternate function clock select */ +#define STR71X_RCCUCCR_SRESEN (0x00000008) /* Bit 3: Software reset enable */ +#define STR71X_RCCUCCR_ENCLOCK (0x00000080) /* Bit 7: Lock interrupt enable */ +#define STR71X_RCCUCCR_ENCKAF (0x00000100) /* Bit 8: CKAF interrupt enable */ +#define STR71X_RCCUCCR_ENCK216 (0x00000200) /* Bit 9: CK2_16 interrupt enable */ +#define STR71X_RCCUCCR_ENSTOP (0x00000400) /* Bit 10: Stop interrupt enable */ +#define STR71X_RCCUCCR_ENHALT (0x00000800) /* Bit 11: Enable halt */ + +/* RCCU CFR register bit definitions */ + +#define STR71X_RCCUCFR_CSUCKSEL (0x00000001) /* Bit 0: CSU clock select */ +#define STR71X_RCCUCFR_LOCK (0x00000002) /* Bit 1: PLL locked-in */ +#define STR71X_RCCUCFR_CKAFST (0x00000004) /* Bit 2: CK_AF status */ +#define STR71X_RCCUCFR_CK216 (0x00000008) /* Bit 3: CLK2/16 selection */ +#define STR71X_RCCUCFR_CKSTOPEN (0x00000010) /* Bit 4: Clock stop enable */ +#define STR71X_RCCUCFR_SOFTRES (0x00000020) /* Bit 5: Software reset */ +#define STR71X_RCCUCFR_WDGRES (0x00000040) /* Bit 6: Watchdog reset */ +#define STR71X_RCCUCFR_RTCALARM (0x00000080) /* Bit 7: RTC alarm reset */ +#define STR71X_RCCUCFR_LVDRES (0x00000200) /* Bit 9: Voltage regulator low voltage detector reset */ +#define STR71X_RCCUCFR_WKPRES (0x00000400) /* Bit 10: External wakeup */ +#define STR71X_RCCUCFR_LOCKI (0x00000800) /* Bit 11: Lock interrupt pending */ +#define STR71X_RCCUCFR_CKAFI (0x00001000) /* Bit 12: CK_AF switching interrupt pending */ +#define STR71X_RCCUCFR_CK216I (0x00002000) /* Bit 13: CK2_16 switching interrupt pending */ +#define STR71X_RCCUCFR_STOPI (0x00004000) /* Bit 14: Stop interrupt pending */ +#define STR71X_RCCUCFR_DIV2 (0x00008000) /* Bit 15: OSCIN divided by 2 */ + +/* RCCU PPL1CR register bit definitions */ + +#define STR71X_RCCUPLL1CR_DXMASK (0x00000003) /* Bit 0-2: PLL1 clock divisor */ +#define STR71X_RCCUPLL1CR_DIV1 (0x00000000) /* PLLCK / 1 */ +#define STR71X_RCCUPLL1CR_DIV2 (0x00000001) /* PLLCK / 2 */ +#define STR71X_RCCUPLL1CR_DIV3 (0x00000002) /* PLLCK / 3 */ +#define STR71X_RCCUPLL1CR_DIV4 (0x00000003) /* PLLCK / 4 */ +#define STR71X_RCCUPLL1CR_DIV5 (0x00000004) /* PLLCK / 5 */ +#define STR71X_RCCUPLL1CR_DIV6 (0x00000005) /* PLLCK / 6 */ +#define STR71X_RCCUPLL1CR_DIV7 (0x00000006) /* PLLCK / 7 */ +#define STR71X_RCCUPLL1CR_CLK2 (0x00000007) /* FREEN==0: CLK2 */ +#define STR71X_RCCUPLL1CR_FREERM (0x00000007) /* FREEN==1: PLL1 in free running mode */ +#define STR71X_RCCUPLL1CR_MXMASK (0x00000030) /* Bit 4-5: PLL1 clock multiplier */ +#define STR71X_RCCUPLL1CR_MUL20 (0x00000000) /* CLK2 * 20 */ +#define STR71X_RCCUPLL1CR_MUL12 (0x00000010) /* CLK2 * 12 */ +#define STR71X_RCCUPLL1CR_MUL24 (0x00000020) /* CLK2 * 24 */ +#define STR71X_RCCUPLL1CR_MUL16 (0x00000030) /* CLK2 * 16 */ +#define STR71X_RCCUPLL1CR_FREFRANGE (0x00000040) /* Bit 6: Reference frequency range select */ +#define STR71X_RCCUPLL1CR_FREEN (0x00000080) /* Bit 7: PKL free running mode */ + +/* RCCU PER register bit definitions */ + +#define STR71X_RCCUPER_EMI (0x00000004) /* Bit 2: EMI */ +#define STR71X_RCCUPER_USBKERNEL (0x00000010) /* Bit 4: USB Kernel */ + +/* RCCU SMR register bit definitions */ + +#define STR71X_RCCUSMR_WFI (0x00000001) /* Bit 0: Wait for interrupt */ +#define STR71X_RCCUSMR_HALT (0x00000000) /* Bit 1: Halt */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_RCCU_H */ diff --git a/arch/arm/src/str71x/str71x_rtc.h b/arch/arm/src/str71x/str71x_rtc.h index 634638f7e3e6547a755f8b162d1e19a222751eb5..554123ff6438b50070507e14ca684ea33f62e45c 100644 --- a/arch/arm/src/str71x/str71x_rtc.h +++ b/arch/arm/src/str71x/str71x_rtc.h @@ -1,92 +1,92 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_rtc.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_RTC_H -#define __ARCH_ARM_SRC_STR71X_STR71X_RTC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "str71x_map.h" - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* RTC Registers ********************************************************************/ - -#define STR71X_RTC_CRH (STR71X_RTC_BASE + 0x0000) /* 16-bits wide */ -#define STR71X_RTC_CRL (STR71X_RTC_BASE + 0x0004) /* 16-bits wide */ -#define STR71X_RTC_PRLH (STR71X_RTC_BASE + 0x0008) /* 16-bits wide */ -#define STR71X_RTC_PRLL (STR71X_RTC_BASE + 0x000c) /* 16-bits wide */ -#define STR71X_RTC_DIVH (STR71X_RTC_BASE + 0x0010) /* 16-bits wide */ -#define STR71X_RTC_DIVL (STR71X_RTC_BASE + 0x0014) /* 16-bits wide */ -#define STR71X_RTC_CNTH (STR71X_RTC_BASE + 0x0018) /* 16-bits wide */ -#define STR71X_RTC_CNTL (STR71X_RTC_BASE + 0x001c) /* 16-bits wide */ -#define STR71X_RTC_ALRH (STR71X_RTC_BASE + 0x0020) /* 16-bits wide */ -#define STR71X_RTC_ALRL (STR71X_RTC_BASE + 0x0024) /* 16-bits wide */ - -/* Register bit settings ***********************************************************/ - -/* RTC control register */ - -#define STR71X_RTCCRH_SEN (0x0001) /* Bit 0: Second interrupt enable */ -#define STR71X_RTCCRH_AEN (0x0002) /* Bit 1: Alarm interrupt enable */ -#define STR71X_RTCCRH_OWEN (0x0004) /* Bit 2: Overflow interrupt enable */ -#define STR71X_RTCCRH_GEN (0x0008) /* Bit 3: Global interrupt enable */ - -#define STR71X_RTCCRL_SIR (0x0001) /* Bit 0: Second interrupt request */ -#define STR71X_RTCCRL_AIR (0x0002) /* Bit 1: Alarm interrupt request */ -#define STR71X_RTCCRL_OWIR (0x0004) /* Bit 2: Overflow interrupt request */ -#define STR71X_RTCCRL_GIR (0x0008) /* Bit 3: Global interrupt request */ -#define STR71X_RTCCRL_CNF (0x0010) /* Bit 4: Enter configuration mode */ -#define STR71X_RTCCRL_RTOFF (0x0020) /* Bit 5: RTC Operation Off */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STR71X_STR71X_RTC_H */ +/************************************************************************************ + * arch/arm/src/str71x/str71x_rtc.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_RTC_H +#define __ARCH_ARM_SRC_STR71X_STR71X_RTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* RTC Registers ********************************************************************/ + +#define STR71X_RTC_CRH (STR71X_RTC_BASE + 0x0000) /* 16-bits wide */ +#define STR71X_RTC_CRL (STR71X_RTC_BASE + 0x0004) /* 16-bits wide */ +#define STR71X_RTC_PRLH (STR71X_RTC_BASE + 0x0008) /* 16-bits wide */ +#define STR71X_RTC_PRLL (STR71X_RTC_BASE + 0x000c) /* 16-bits wide */ +#define STR71X_RTC_DIVH (STR71X_RTC_BASE + 0x0010) /* 16-bits wide */ +#define STR71X_RTC_DIVL (STR71X_RTC_BASE + 0x0014) /* 16-bits wide */ +#define STR71X_RTC_CNTH (STR71X_RTC_BASE + 0x0018) /* 16-bits wide */ +#define STR71X_RTC_CNTL (STR71X_RTC_BASE + 0x001c) /* 16-bits wide */ +#define STR71X_RTC_ALRH (STR71X_RTC_BASE + 0x0020) /* 16-bits wide */ +#define STR71X_RTC_ALRL (STR71X_RTC_BASE + 0x0024) /* 16-bits wide */ + +/* Register bit settings ***********************************************************/ + +/* RTC control register */ + +#define STR71X_RTCCRH_SEN (0x0001) /* Bit 0: Second interrupt enable */ +#define STR71X_RTCCRH_AEN (0x0002) /* Bit 1: Alarm interrupt enable */ +#define STR71X_RTCCRH_OWEN (0x0004) /* Bit 2: Overflow interrupt enable */ +#define STR71X_RTCCRH_GEN (0x0008) /* Bit 3: Global interrupt enable */ + +#define STR71X_RTCCRL_SIR (0x0001) /* Bit 0: Second interrupt request */ +#define STR71X_RTCCRL_AIR (0x0002) /* Bit 1: Alarm interrupt request */ +#define STR71X_RTCCRL_OWIR (0x0004) /* Bit 2: Overflow interrupt request */ +#define STR71X_RTCCRL_GIR (0x0008) /* Bit 3: Global interrupt request */ +#define STR71X_RTCCRL_CNF (0x0010) /* Bit 4: Enter configuration mode */ +#define STR71X_RTCCRL_RTOFF (0x0020) /* Bit 5: RTC Operation Off */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_RTC_H */ diff --git a/arch/arm/src/str71x/str71x_timer.h b/arch/arm/src/str71x/str71x_timer.h index 2076a1d1d65e8641a735eb551508c3851f0109ef..7712009c2a284a7b3e02db6eece35343e2a0d961 100644 --- a/arch/arm/src/str71x/str71x_timer.h +++ b/arch/arm/src/str71x/str71x_timer.h @@ -1,155 +1,155 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_timer.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_TIMER_H -#define __ARCH_ARM_SRC_STR71X_STR71X_TIMER_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "str71x_map.h" - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* Register offsets *****************************************************************/ - -#define STR71X_TIMER_ICAR_OFFSET (0x0000) /* 16-bits wide */ -#define STR71X_TIMER_ICBR_OFFSET (0x0004) /* 16-bits wide */ -#define STR71X_TIMER_OCAR_OFFSET (0x0008) /* 16-bits wide */ -#define STR71X_TIMER_OCBR_OFFSET (0x000c) /* 16-bits wide */ -#define STR71X_TIMER_CNTR_OFFSET (0x0010) /* 16-bits wide */ -#define STR71X_TIMER_CR1_OFFSET (0x0014) /* 16-bits wide */ -#define STR71X_TIMER_CR2_OFFSET (0x0018) /* 16-bits wide */ -#define STR71X_TIMER_SR_OFFSET (0x001c) /* 16-bits wide */ - -/* Register Addresses ***************************************************************/ - -#define STR71X_TIMER_ICAR(b) ((b) + STR71X_TIMER_ICAR_OFFSET) -#define STR71X_TIMER_ICBR(b) ((b) + STR71X_TIMER_ICBR_OFFSET) -#define STR71X_TIMER_OCAR(b) ((b) + STR71X_TIMER_OCAR_OFFSET) -#define STR71X_TIMER_OCBR(b) ((b) + STR71X_TIMER_OCBR_OFFSET) -#define STR71X_TIMER_CNTR(b) ((b) + STR71X_TIMER_CNTR_OFFSET) -#define STR71X_TIMER_CR1(b) ((b) + STR71X_TIMER_CR1_OFFSET) -#define STR71X_TIMER_CR2(b) ((b) + STR71X_TIMER_CR2_OFFSET) -#define STR71X_TIMER_SR(b) ((b) + STR71X_TIMER_SR_OFFSET) - -#define STR71X_TIMER0_ICAR (STR71X_TIMER0_BASE + STR71X_TIMER_ICAR_OFFSET) -#define STR71X_TIMER0_ICBR (STR71X_TIMER0_BASE + STR71X_TIMER_ICBR_OFFSET) -#define STR71X_TIMER0_OCAR (STR71X_TIMER0_BASE + STR71X_TIMER_OCAR_OFFSET) -#define STR71X_TIMER0_OCBR (STR71X_TIMER0_BASE + STR71X_TIMER_OCBR_OFFSET) -#define STR71X_TIMER0_CNTR (STR71X_TIMER0_BASE + STR71X_TIMER_CNTR_OFFSET) -#define STR71X_TIMER0_CR1 (STR71X_TIMER0_BASE + STR71X_TIMER_CR1_OFFSET) -#define STR71X_TIMER0_CR2 (STR71X_TIMER0_BASE + STR71X_TIMER_CR2_OFFSET) -#define STR71X_TIMER0_SR (STR71X_TIMER0_BASE + STR71X_TIMER_SR_OFFSET) - -#define STR71X_TIMER1_ICAR (STR71X_TIMER1_BASE + STR71X_TIMER_ICAR_OFFSET) -#define STR71X_TIMER1_ICBR (STR71X_TIMER1_BASE + STR71X_TIMER_ICBR_OFFSET) -#define STR71X_TIMER1_OCAR (STR71X_TIMER1_BASE + STR71X_TIMER_OCAR_OFFSET) -#define STR71X_TIMER1_OCBR (STR71X_TIMER1_BASE + STR71X_TIMER_OCBR_OFFSET) -#define STR71X_TIMER1_CNTR (STR71X_TIMER1_BASE + STR71X_TIMER_CNTR_OFFSET) -#define STR71X_TIMER1_CR1 (STR71X_TIMER1_BASE + STR71X_TIMER_CR1_OFFSET) -#define STR71X_TIMER1_CR2 (STR71X_TIMER1_BASE + STR71X_TIMER_CR2_OFFSET) -#define STR71X_TIMER1_SR (STR71X_TIMER1_BASE + STR71X_TIMER_SR_OFFSET) - -#define STR71X_TIMER2_ICAR (STR71X_TIMER2_BASE + STR71X_TIMER_ICAR_OFFSET) -#define STR71X_TIMER2_ICBR (STR71X_TIMER2_BASE + STR71X_TIMER_ICBR_OFFSET) -#define STR71X_TIMER2_OCAR (STR71X_TIMER2_BASE + STR71X_TIMER_OCAR_OFFSET) -#define STR71X_TIMER2_OCBR (STR71X_TIMER2_BASE + STR71X_TIMER_OCBR_OFFSET) -#define STR71X_TIMER2_CNTR (STR71X_TIMER2_BASE + STR71X_TIMER_CNTR_OFFSET) -#define STR71X_TIMER2_CR1 (STR71X_TIMER2_BASE + STR71X_TIMER_CR1_OFFSET) -#define STR71X_TIMER2_CR2 (STR71X_TIMER2_BASE + STR71X_TIMER_CR2_OFFSET) -#define STR71X_TIMER2_SR (STR71X_TIMER2_BASE + STR71X_TIMER_SR_OFFSET) - -#define STR71X_TIMER3_ICAR (STR71X_TIMER3_BASE + STR71X_TIMER_ICAR_OFFSET) -#define STR71X_TIMER3_ICBR (STR71X_TIMER3_BASE + STR71X_TIMER_ICBR_OFFSET) -#define STR71X_TIMER3_OCAR (STR71X_TIMER3_BASE + STR71X_TIMER_OCAR_OFFSET) -#define STR71X_TIMER3_OCBR (STR71X_TIMER3_BASE + STR71X_TIMER_OCBR_OFFSET) -#define STR71X_TIMER3_CNTR (STR71X_TIMER3_BASE + STR71X_TIMER_CNTR_OFFSET) -#define STR71X_TIMER3_CR1 (STR71X_TIMER3_BASE + STR71X_TIMER_CR1_OFFSET) -#define STR71X_TIMER3_CR2 (STR71X_TIMER3_BASE + STR71X_TIMER_CR2_OFFSET) -#define STR71X_TIMER3_SR (STR71X_TIMER3_BASE + STR71X_TIMER_SR_OFFSET) - -/* Register bit settings ***********************************************************/ - -/* Timer control register (CR1 and CR2) */ - -#define STR71X_TIMERCR1_ECKEN (0x0001) /* Bit 0: External clock enable */ -#define STR71X_TIMERCR1_EXEDG (0x0002) /* Bit 1: External clock edge */ -#define STR71X_TIMERCR1_IEDGA (0x0004) /* Bit 2: Input edge A */ -#define STR71X_TIMERCR1_IEDGB (0x0008) /* Bit 3: Input edge B */ -#define STR71X_TIMERCR1_PWM (0x0010) /* Bit 4: Pulse width modulation */ -#define STR71X_TIMERCR1_OPM (0x0020) /* Bit 5: One pulse mode */ -#define STR71X_TIMERCR1_OCAE (0x0040) /* Bit 6: Output compare A enable */ -#define STR71X_TIMERCR1_OCBE (0x0080) /* Bit 7: Output compare B enable */ -#define STR71X_TIMERCR1_OLVLA (0x0100) /* Bit 8: Output level A */ -#define STR71X_TIMERCR1_OLVLB (0x0200) /* Bit 9: Output level B */ -#define STR71X_TIMERCR1_FOLVA (0x0400) /* Bit 10: Forced output compare A */ -#define STR71X_TIMERCR1_FOLVB (0x0800) /* Bit 11: Forced output compare B */ -#define STR71X_TIMERCR1_PWMI (0x4000) /* Bit 14: Pulse width modulation input */ -#define STR71X_TIMERCR1_EN (0x8000) /* Bit 15: Timer count enable */ - -#define STR71X_TIMERCR2_DIVMASK (0x00ff) /* Bits 0-7: Timer prescaler value */ -#define STR71X_TIMERCR2_OCBIE (0x0800) /* Bit 11: Output capture B enable */ -#define STR71X_TIMERCR2_ICBIE (0x1000) /* Bit 12: Input capture B enable */ -#define STR71X_TIMERCR2_TOIE (0x2000) /* Bit 13: Timer overflow enable */ -#define STR71X_TIMERCR2_OCAIE (0x4000) /* Bit 14: Output capture A enable */ -#define STR71X_TIMERCR2_ICAIE (0x8000) /* Bit 15: Input capture B enable */ - -/* Timer status register (SR) */ - -#define STR71X_TIMERSR_OCFB (0x0800) /* Bit 11: Output capture flag B */ -#define STR71X_TIMERSR_ICFB (0x1000) /* Bit 12: Input capture flag B */ -#define STR71X_TIMERSR_TOF (0x2000) /* Bit 13: Timer overflow */ -#define STR71X_TIMERSR_OCFA (0x4000) /* Bit 14: Output capture flag A */ -#define STR71X_TIMERSR_ICFA (0x8000) /* Bit 15: Input capture flag A */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STR71X_STR71X_TIMER_H */ +/************************************************************************************ + * arch/arm/src/str71x/str71x_timer.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_TIMER_H +#define __ARCH_ARM_SRC_STR71X_STR71X_TIMER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define STR71X_TIMER_ICAR_OFFSET (0x0000) /* 16-bits wide */ +#define STR71X_TIMER_ICBR_OFFSET (0x0004) /* 16-bits wide */ +#define STR71X_TIMER_OCAR_OFFSET (0x0008) /* 16-bits wide */ +#define STR71X_TIMER_OCBR_OFFSET (0x000c) /* 16-bits wide */ +#define STR71X_TIMER_CNTR_OFFSET (0x0010) /* 16-bits wide */ +#define STR71X_TIMER_CR1_OFFSET (0x0014) /* 16-bits wide */ +#define STR71X_TIMER_CR2_OFFSET (0x0018) /* 16-bits wide */ +#define STR71X_TIMER_SR_OFFSET (0x001c) /* 16-bits wide */ + +/* Register Addresses ***************************************************************/ + +#define STR71X_TIMER_ICAR(b) ((b) + STR71X_TIMER_ICAR_OFFSET) +#define STR71X_TIMER_ICBR(b) ((b) + STR71X_TIMER_ICBR_OFFSET) +#define STR71X_TIMER_OCAR(b) ((b) + STR71X_TIMER_OCAR_OFFSET) +#define STR71X_TIMER_OCBR(b) ((b) + STR71X_TIMER_OCBR_OFFSET) +#define STR71X_TIMER_CNTR(b) ((b) + STR71X_TIMER_CNTR_OFFSET) +#define STR71X_TIMER_CR1(b) ((b) + STR71X_TIMER_CR1_OFFSET) +#define STR71X_TIMER_CR2(b) ((b) + STR71X_TIMER_CR2_OFFSET) +#define STR71X_TIMER_SR(b) ((b) + STR71X_TIMER_SR_OFFSET) + +#define STR71X_TIMER0_ICAR (STR71X_TIMER0_BASE + STR71X_TIMER_ICAR_OFFSET) +#define STR71X_TIMER0_ICBR (STR71X_TIMER0_BASE + STR71X_TIMER_ICBR_OFFSET) +#define STR71X_TIMER0_OCAR (STR71X_TIMER0_BASE + STR71X_TIMER_OCAR_OFFSET) +#define STR71X_TIMER0_OCBR (STR71X_TIMER0_BASE + STR71X_TIMER_OCBR_OFFSET) +#define STR71X_TIMER0_CNTR (STR71X_TIMER0_BASE + STR71X_TIMER_CNTR_OFFSET) +#define STR71X_TIMER0_CR1 (STR71X_TIMER0_BASE + STR71X_TIMER_CR1_OFFSET) +#define STR71X_TIMER0_CR2 (STR71X_TIMER0_BASE + STR71X_TIMER_CR2_OFFSET) +#define STR71X_TIMER0_SR (STR71X_TIMER0_BASE + STR71X_TIMER_SR_OFFSET) + +#define STR71X_TIMER1_ICAR (STR71X_TIMER1_BASE + STR71X_TIMER_ICAR_OFFSET) +#define STR71X_TIMER1_ICBR (STR71X_TIMER1_BASE + STR71X_TIMER_ICBR_OFFSET) +#define STR71X_TIMER1_OCAR (STR71X_TIMER1_BASE + STR71X_TIMER_OCAR_OFFSET) +#define STR71X_TIMER1_OCBR (STR71X_TIMER1_BASE + STR71X_TIMER_OCBR_OFFSET) +#define STR71X_TIMER1_CNTR (STR71X_TIMER1_BASE + STR71X_TIMER_CNTR_OFFSET) +#define STR71X_TIMER1_CR1 (STR71X_TIMER1_BASE + STR71X_TIMER_CR1_OFFSET) +#define STR71X_TIMER1_CR2 (STR71X_TIMER1_BASE + STR71X_TIMER_CR2_OFFSET) +#define STR71X_TIMER1_SR (STR71X_TIMER1_BASE + STR71X_TIMER_SR_OFFSET) + +#define STR71X_TIMER2_ICAR (STR71X_TIMER2_BASE + STR71X_TIMER_ICAR_OFFSET) +#define STR71X_TIMER2_ICBR (STR71X_TIMER2_BASE + STR71X_TIMER_ICBR_OFFSET) +#define STR71X_TIMER2_OCAR (STR71X_TIMER2_BASE + STR71X_TIMER_OCAR_OFFSET) +#define STR71X_TIMER2_OCBR (STR71X_TIMER2_BASE + STR71X_TIMER_OCBR_OFFSET) +#define STR71X_TIMER2_CNTR (STR71X_TIMER2_BASE + STR71X_TIMER_CNTR_OFFSET) +#define STR71X_TIMER2_CR1 (STR71X_TIMER2_BASE + STR71X_TIMER_CR1_OFFSET) +#define STR71X_TIMER2_CR2 (STR71X_TIMER2_BASE + STR71X_TIMER_CR2_OFFSET) +#define STR71X_TIMER2_SR (STR71X_TIMER2_BASE + STR71X_TIMER_SR_OFFSET) + +#define STR71X_TIMER3_ICAR (STR71X_TIMER3_BASE + STR71X_TIMER_ICAR_OFFSET) +#define STR71X_TIMER3_ICBR (STR71X_TIMER3_BASE + STR71X_TIMER_ICBR_OFFSET) +#define STR71X_TIMER3_OCAR (STR71X_TIMER3_BASE + STR71X_TIMER_OCAR_OFFSET) +#define STR71X_TIMER3_OCBR (STR71X_TIMER3_BASE + STR71X_TIMER_OCBR_OFFSET) +#define STR71X_TIMER3_CNTR (STR71X_TIMER3_BASE + STR71X_TIMER_CNTR_OFFSET) +#define STR71X_TIMER3_CR1 (STR71X_TIMER3_BASE + STR71X_TIMER_CR1_OFFSET) +#define STR71X_TIMER3_CR2 (STR71X_TIMER3_BASE + STR71X_TIMER_CR2_OFFSET) +#define STR71X_TIMER3_SR (STR71X_TIMER3_BASE + STR71X_TIMER_SR_OFFSET) + +/* Register bit settings ***********************************************************/ + +/* Timer control register (CR1 and CR2) */ + +#define STR71X_TIMERCR1_ECKEN (0x0001) /* Bit 0: External clock enable */ +#define STR71X_TIMERCR1_EXEDG (0x0002) /* Bit 1: External clock edge */ +#define STR71X_TIMERCR1_IEDGA (0x0004) /* Bit 2: Input edge A */ +#define STR71X_TIMERCR1_IEDGB (0x0008) /* Bit 3: Input edge B */ +#define STR71X_TIMERCR1_PWM (0x0010) /* Bit 4: Pulse width modulation */ +#define STR71X_TIMERCR1_OPM (0x0020) /* Bit 5: One pulse mode */ +#define STR71X_TIMERCR1_OCAE (0x0040) /* Bit 6: Output compare A enable */ +#define STR71X_TIMERCR1_OCBE (0x0080) /* Bit 7: Output compare B enable */ +#define STR71X_TIMERCR1_OLVLA (0x0100) /* Bit 8: Output level A */ +#define STR71X_TIMERCR1_OLVLB (0x0200) /* Bit 9: Output level B */ +#define STR71X_TIMERCR1_FOLVA (0x0400) /* Bit 10: Forced output compare A */ +#define STR71X_TIMERCR1_FOLVB (0x0800) /* Bit 11: Forced output compare B */ +#define STR71X_TIMERCR1_PWMI (0x4000) /* Bit 14: Pulse width modulation input */ +#define STR71X_TIMERCR1_EN (0x8000) /* Bit 15: Timer count enable */ + +#define STR71X_TIMERCR2_DIVMASK (0x00ff) /* Bits 0-7: Timer prescaler value */ +#define STR71X_TIMERCR2_OCBIE (0x0800) /* Bit 11: Output capture B enable */ +#define STR71X_TIMERCR2_ICBIE (0x1000) /* Bit 12: Input capture B enable */ +#define STR71X_TIMERCR2_TOIE (0x2000) /* Bit 13: Timer overflow enable */ +#define STR71X_TIMERCR2_OCAIE (0x4000) /* Bit 14: Output capture A enable */ +#define STR71X_TIMERCR2_ICAIE (0x8000) /* Bit 15: Input capture B enable */ + +/* Timer status register (SR) */ + +#define STR71X_TIMERSR_OCFB (0x0800) /* Bit 11: Output capture flag B */ +#define STR71X_TIMERSR_ICFB (0x1000) /* Bit 12: Input capture flag B */ +#define STR71X_TIMERSR_TOF (0x2000) /* Bit 13: Timer overflow */ +#define STR71X_TIMERSR_OCFA (0x4000) /* Bit 14: Output capture flag A */ +#define STR71X_TIMERSR_ICFA (0x8000) /* Bit 15: Input capture flag A */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_TIMER_H */ diff --git a/arch/arm/src/str71x/str71x_timerisr.c b/arch/arm/src/str71x/str71x_timerisr.c index 8f41b929127efc9af3c903432acb2dd342f7e4e0..e55e1f21a74d8a0e440c65311ca09e531e033e3b 100644 --- a/arch/arm/src/str71x/str71x_timerisr.c +++ b/arch/arm/src/str71x/str71x_timerisr.c @@ -2,7 +2,7 @@ * arch/arm/src/str71x/str71x_timerisr.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/str71x/str71x_uart.h b/arch/arm/src/str71x/str71x_uart.h index 9178062c436e26aab1337df30db4a323f79a9989..3073e00539d48f9b93a6da3017bb279953557e18 100644 --- a/arch/arm/src/str71x/str71x_uart.h +++ b/arch/arm/src/str71x/str71x_uart.h @@ -1,181 +1,181 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_uart.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_UART_H -#define __ARCH_ARM_SRC_STR71X_STR71X_UART_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "str71x_map.h" - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* Registers offsets ****************************************************************/ - -#define STR71X_UART_BR_OFFSET (0x0000) /* 16-bits wide */ -#define STR71X_UART_TXBUFR_OFFSET (0x0004) /* 16-bits wide */ -#define STR71X_UART_RXBUFR_OFFSET (0x0008) /* 16-bits wide */ -#define STR71X_UART_CR_OFFSET (0x000c) /* 16-bits wide */ -#define STR71X_UART_IER_OFFSET (0x0010) /* 16-bits wide */ -#define STR71X_UART_SR_OFFSET (0x0014) /* 16-bits wide */ -#define STR71X_UART_GTR_OFFSET (0x0018) /* 16-bits wide */ -#define STR71X_UART_TOR_OFFSET (0x001c) /* 16-bits wide */ -#define STR71X_UART_TXRSTR_OFFSET (0x0020) /* 16-bits wide */ -#define STR71X_UART_RXRSTR_OFFSET (0x0024) /* 16-bits wide */ - -/* Registers addresses **************************************************************/ - -#define STR71X_UART_BR(b) ((b) + STR71X_UART_BR_OFFSET) -#define STR71X_UART_TXBUFR(b) ((b) + STR71X_UART_TXBUFR_OFFSET) -#define STR71X_UART_RXBUFR(b) ((b) + STR71X_UART_RXBUFR_OFFSET) -#define STR71X_UART_CR(b) ((b) + STR71X_UART_CR_OFFSET) -#define STR71X_UART_IER(b) ((b) + STR71X_UART_IER_OFFSET) -#define STR71X_UART_SR(b) ((b) + STR71X_UART_SR_OFFSET) -#define STR71X_UART_GTR(b) ((b) + STR71X_UART_GTR_OFFSET) -#define STR71X_UART_TOR(b) ((b) + STR71X_UART_TOR_OFFSET) -#define STR71X_UART_TXRSTR(b) ((b) + STR71X_UART_TXRSTR_OFFSET) -#define STR71X_UART_RXRSTR(b) ((b) + STR71X_UART_RXRSTR_OFFSET) - -#define STR71X_UART0_BR (STR71X_UART0_BASE + STR71X_UART_BR_OFFSET) -#define STR71X_UART0_TXBUFR (STR71X_UART0_BASE + STR71X_UART_TXBUFR_OFFSET) -#define STR71X_UART0_RXBUFR (STR71X_UART0_BASE + STR71X_UART_RXBUFR_OFFSET) -#define STR71X_UART0_CR (STR71X_UART0_BASE + STR71X_UART_CR_OFFSET) -#define STR71X_UART0_IER (STR71X_UART0_BASE + STR71X_UART_IER_OFFSET) -#define STR71X_UART0_SR (STR71X_UART0_BASE + STR71X_UART_SR_OFFSET) -#define STR71X_UART0_GTR (STR71X_UART0_BASE + STR71X_UART_GTR_OFFSET) -#define STR71X_UART0_TOR (STR71X_UART0_BASE + STR71X_UART_TOR_OFFSET) -#define STR71X_UART0_TXRSTR (STR71X_UART0_BASE + STR71X_UART_TXRSTR_OFFSET) -#define STR71X_UART0_RXRSTR (STR71X_UART0_BASE + STR71X_UART_RXRSTR_OFFSET) - -#define STR71X_UART1_BR (STR71X_UART1_BASE + STR71X_UART_BR_OFFSET) -#define STR71X_UART1_TXBUFR (STR71X_UART1_BASE + STR71X_UART_TXBUFR_OFFSET) -#define STR71X_UART1_RXBUFR (STR71X_UART1_BASE + STR71X_UART_RXBUFR_OFFSET) -#define STR71X_UART1_CR (STR71X_UART1_BASE + STR71X_UART_CR_OFFSET) -#define STR71X_UART1_IER (STR71X_UART1_BASE + STR71X_UART_IER_OFFSET) -#define STR71X_UART1_SR (STR71X_UART1_BASE + STR71X_UART_SR_OFFSET) -#define STR71X_UART1_GTR (STR71X_UART1_BASE + STR71X_UART_GTR_OFFSET) -#define STR71X_UART1_TOR (STR71X_UART1_BASE + STR71X_UART_TOR_OFFSET) -#define STR71X_UART1_TXRSTR (STR71X_UART1_BASE + STR71X_UART_TXRSTR_OFFSET) -#define STR71X_UART1_RXRSTR (STR71X_UART1_BASE + STR71X_UART_RXRSTR_OFFSET) - -#define STR71X_UART2_BR (STR71X_UART2_BASE + STR71X_UART_BR_OFFSET) -#define STR71X_UART2_TXBUFR (STR71X_UART2_BASE + STR71X_UART_TXBUFR_OFFSET) -#define STR71X_UART2_RXBUFR (STR71X_UART2_BASE + STR71X_UART_RXBUFR_OFFSET) -#define STR71X_UART2_CR (STR71X_UART2_BASE + STR71X_UART_CR_OFFSET) -#define STR71X_UART2_IER (STR71X_UART2_BASE + STR71X_UART_IER_OFFSET) -#define STR71X_UART2_SR (STR71X_UART2_BASE + STR71X_UART_SR_OFFSET) -#define STR71X_UART2_GTR (STR71X_UART2_BASE + STR71X_UART_GTR_OFFSET) -#define STR71X_UART2_TOR (STR71X_UART2_BASE + STR71X_UART_TOR_OFFSET) -#define STR71X_UART2_TXRSTR (STR71X_UART2_BASE + STR71X_UART_TXRSTR_OFFSET) -#define STR71X_UART2_RXRSTR (STR71X_UART2_BASE + STR71X_UART_RXRSTR_OFFSET) - -#define STR71X_UART3_BR (STR71X_UART3_BASE + STR71X_UART_BR_OFFSET) -#define STR71X_UART3_TXBUFR (STR71X_UART3_BASE + STR71X_UART_TXBUFR_OFFSET) -#define STR71X_UART3_RXBUFR (STR71X_UART3_BASE + STR71X_UART_RXBUFR_OFFSET) -#define STR71X_UART3_CR (STR71X_UART3_BASE + STR71X_UART_CR_OFFSET) -#define STR71X_UART3_IER (STR71X_UART3_BASE + STR71X_UART_IER_OFFSET) -#define STR71X_UART3_SR (STR71X_UART3_BASE + STR71X_UART_SR_OFFSET) -#define STR71X_UART3_GTR (STR71X_UART3_BASE + STR71X_UART_GTR_OFFSET) -#define STR71X_UART3_TOR (STR71X_UART3_BASE + STR71X_UART_TOR_OFFSET) -#define STR71X_UART3_TXRSTR (STR71X_UART3_BASE + STR71X_UART_TXRSTR_OFFSET) -#define STR71X_UART3_RXRSTR (STR71X_UART3_BASE + STR71X_UART_RXRSTR_OFFSET) - -/* Register bit settings ***********************************************************/ - -/* UART control register (CR) */ - -#define STR71X_UARTCR_MODEMASK (0x0007) /* Bits 0-2: Mode */ -#define STR71X_UARTCR_MODE8BIT (0x0001) /* 8-bit */ -#define STR71X_UARTCR_MODE7BITP (0x0003) /* 7-bit with parity bit */ -#define STR71X_UARTCR_MODE9BIT (0x0004) /* 9-bit */ -#define STR71X_UARTCR_MODE8BITWU (0x0005) /* 8-bit with wakeup bit */ -#define STR71X_UARTCR_MODE8BITP (0x0007) /* 8-bit with parity bit */ -#define STR71X_UARTCR_STOPBITSMASK (0x0018) /* Bits 3-4: Stop bits */ -#define STR71X_UARTCR_STOPBIT05 (0x0000) /* 0.5 stop bits */ -#define STR71X_UARTCR_STOPBIT10 (0x0008) /* 1.0 stop bit */ -#define STR71X_UARTCR_STOPBIT15 (0x0010) /* 1.5 stop bits */ -#define STR71X_UARTCR_STOPBIT20 (0x0018) /* 2.0 stop bits */ -#define STR71X_UARTCR_PARITYODD (0x0020) /* Bit 5: Parity selection */ -#define STR71X_UARTCR_LOOPBACK (0x0040) /* Bit 6: Loopback mode enable */ -#define STR71X_UARTCR_RUN (0x0080) /* Bit 7: Baudrate generator run bit */ -#define STR71X_UARTCR_RXENABLE (0x0100) /* Bit 8: Receiver enable */ -#define STR71X_UARTCR_SCENABLE (0x0200) /* Bit 9: SmartCard mode enable */ -#define STR71X_UARTCR_FIFOENABLE (0x0400) /* Bit 10: FIFO enable */ - -/* UART interrupt enable (IER) register */ - -#define STR71X_UARTIER_RNE (0x0001) /* Bit 0: Rx buffer not empty */ -#define STR71X_UARTIER_TE (0x0002) /* Bit 1: Tx empty */ -#define STR71X_UARTIER_THE (0x0004) /* Bit 2: Tx half empty */ -#define STR71X_UARTIER_PERROR (0x0008) /* Bit 3: Parity error */ -#define STR71X_UARTIER_FRERROR (0x0010) /* Bit 4: Frame error */ -#define STR71X_UARTIER_OVERRUN (0x0020) /* Bit 5: Overrun error */ -#define STR71X_UARTIER_TIMEOUTNE (0x0040) /* Bit 6: Time out not empty*/ -#define STR71X_UARTIER_TIMEOUTIDLE (0x0080) /* Bit 7: Timeout out idle */ -#define STR71X_UARTIER_RHF (0x0100) /* Bit 8: Rx half full */ -#define STR71X_UARTIER_ALL (0x01ff) /* All interrupt bits */ - -/* UART status register (SR) */ - -#define STR71X_UARTSR_RNE (0x0001) /* Bit 0: Rx buffer not empty */ -#define STR71X_UARTSR_TE (0x0002) /* Bit 1: Tx empty */ -#define STR71X_UARTSR_THE (0x0004) /* Bit 2: Tx half empty */ -#define STR71X_UARTSR_PERR (0x0008) /* Bit 3: Parity error */ -#define STR71X_UARTSR_FRERROR (0x0010) /* Bit 4: Frame error */ -#define STR71X_UARTSR_OVERRUN (0x0020) /* Bit 5: Overrun error */ -#define STR71X_UARTSR_TIMEOUTNE (0x0040) /* Bit 6: Time out not empty */ -#define STR71X_UARTSR_TIMEOUTIDLE (0x0080) /* Bit 7: Timeout out idle */ -#define STR71X_UARTSR_RHF (0x0100) /* Bit 8: Rx half full */ -#define STR71X_UARTSR_TF (0x0200) /* Bit 9: Tx full */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STR71X_STR71X_UART_H */ +/************************************************************************************ + * arch/arm/src/str71x/str71x_uart.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_UART_H +#define __ARCH_ARM_SRC_STR71X_STR71X_UART_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Registers offsets ****************************************************************/ + +#define STR71X_UART_BR_OFFSET (0x0000) /* 16-bits wide */ +#define STR71X_UART_TXBUFR_OFFSET (0x0004) /* 16-bits wide */ +#define STR71X_UART_RXBUFR_OFFSET (0x0008) /* 16-bits wide */ +#define STR71X_UART_CR_OFFSET (0x000c) /* 16-bits wide */ +#define STR71X_UART_IER_OFFSET (0x0010) /* 16-bits wide */ +#define STR71X_UART_SR_OFFSET (0x0014) /* 16-bits wide */ +#define STR71X_UART_GTR_OFFSET (0x0018) /* 16-bits wide */ +#define STR71X_UART_TOR_OFFSET (0x001c) /* 16-bits wide */ +#define STR71X_UART_TXRSTR_OFFSET (0x0020) /* 16-bits wide */ +#define STR71X_UART_RXRSTR_OFFSET (0x0024) /* 16-bits wide */ + +/* Registers addresses **************************************************************/ + +#define STR71X_UART_BR(b) ((b) + STR71X_UART_BR_OFFSET) +#define STR71X_UART_TXBUFR(b) ((b) + STR71X_UART_TXBUFR_OFFSET) +#define STR71X_UART_RXBUFR(b) ((b) + STR71X_UART_RXBUFR_OFFSET) +#define STR71X_UART_CR(b) ((b) + STR71X_UART_CR_OFFSET) +#define STR71X_UART_IER(b) ((b) + STR71X_UART_IER_OFFSET) +#define STR71X_UART_SR(b) ((b) + STR71X_UART_SR_OFFSET) +#define STR71X_UART_GTR(b) ((b) + STR71X_UART_GTR_OFFSET) +#define STR71X_UART_TOR(b) ((b) + STR71X_UART_TOR_OFFSET) +#define STR71X_UART_TXRSTR(b) ((b) + STR71X_UART_TXRSTR_OFFSET) +#define STR71X_UART_RXRSTR(b) ((b) + STR71X_UART_RXRSTR_OFFSET) + +#define STR71X_UART0_BR (STR71X_UART0_BASE + STR71X_UART_BR_OFFSET) +#define STR71X_UART0_TXBUFR (STR71X_UART0_BASE + STR71X_UART_TXBUFR_OFFSET) +#define STR71X_UART0_RXBUFR (STR71X_UART0_BASE + STR71X_UART_RXBUFR_OFFSET) +#define STR71X_UART0_CR (STR71X_UART0_BASE + STR71X_UART_CR_OFFSET) +#define STR71X_UART0_IER (STR71X_UART0_BASE + STR71X_UART_IER_OFFSET) +#define STR71X_UART0_SR (STR71X_UART0_BASE + STR71X_UART_SR_OFFSET) +#define STR71X_UART0_GTR (STR71X_UART0_BASE + STR71X_UART_GTR_OFFSET) +#define STR71X_UART0_TOR (STR71X_UART0_BASE + STR71X_UART_TOR_OFFSET) +#define STR71X_UART0_TXRSTR (STR71X_UART0_BASE + STR71X_UART_TXRSTR_OFFSET) +#define STR71X_UART0_RXRSTR (STR71X_UART0_BASE + STR71X_UART_RXRSTR_OFFSET) + +#define STR71X_UART1_BR (STR71X_UART1_BASE + STR71X_UART_BR_OFFSET) +#define STR71X_UART1_TXBUFR (STR71X_UART1_BASE + STR71X_UART_TXBUFR_OFFSET) +#define STR71X_UART1_RXBUFR (STR71X_UART1_BASE + STR71X_UART_RXBUFR_OFFSET) +#define STR71X_UART1_CR (STR71X_UART1_BASE + STR71X_UART_CR_OFFSET) +#define STR71X_UART1_IER (STR71X_UART1_BASE + STR71X_UART_IER_OFFSET) +#define STR71X_UART1_SR (STR71X_UART1_BASE + STR71X_UART_SR_OFFSET) +#define STR71X_UART1_GTR (STR71X_UART1_BASE + STR71X_UART_GTR_OFFSET) +#define STR71X_UART1_TOR (STR71X_UART1_BASE + STR71X_UART_TOR_OFFSET) +#define STR71X_UART1_TXRSTR (STR71X_UART1_BASE + STR71X_UART_TXRSTR_OFFSET) +#define STR71X_UART1_RXRSTR (STR71X_UART1_BASE + STR71X_UART_RXRSTR_OFFSET) + +#define STR71X_UART2_BR (STR71X_UART2_BASE + STR71X_UART_BR_OFFSET) +#define STR71X_UART2_TXBUFR (STR71X_UART2_BASE + STR71X_UART_TXBUFR_OFFSET) +#define STR71X_UART2_RXBUFR (STR71X_UART2_BASE + STR71X_UART_RXBUFR_OFFSET) +#define STR71X_UART2_CR (STR71X_UART2_BASE + STR71X_UART_CR_OFFSET) +#define STR71X_UART2_IER (STR71X_UART2_BASE + STR71X_UART_IER_OFFSET) +#define STR71X_UART2_SR (STR71X_UART2_BASE + STR71X_UART_SR_OFFSET) +#define STR71X_UART2_GTR (STR71X_UART2_BASE + STR71X_UART_GTR_OFFSET) +#define STR71X_UART2_TOR (STR71X_UART2_BASE + STR71X_UART_TOR_OFFSET) +#define STR71X_UART2_TXRSTR (STR71X_UART2_BASE + STR71X_UART_TXRSTR_OFFSET) +#define STR71X_UART2_RXRSTR (STR71X_UART2_BASE + STR71X_UART_RXRSTR_OFFSET) + +#define STR71X_UART3_BR (STR71X_UART3_BASE + STR71X_UART_BR_OFFSET) +#define STR71X_UART3_TXBUFR (STR71X_UART3_BASE + STR71X_UART_TXBUFR_OFFSET) +#define STR71X_UART3_RXBUFR (STR71X_UART3_BASE + STR71X_UART_RXBUFR_OFFSET) +#define STR71X_UART3_CR (STR71X_UART3_BASE + STR71X_UART_CR_OFFSET) +#define STR71X_UART3_IER (STR71X_UART3_BASE + STR71X_UART_IER_OFFSET) +#define STR71X_UART3_SR (STR71X_UART3_BASE + STR71X_UART_SR_OFFSET) +#define STR71X_UART3_GTR (STR71X_UART3_BASE + STR71X_UART_GTR_OFFSET) +#define STR71X_UART3_TOR (STR71X_UART3_BASE + STR71X_UART_TOR_OFFSET) +#define STR71X_UART3_TXRSTR (STR71X_UART3_BASE + STR71X_UART_TXRSTR_OFFSET) +#define STR71X_UART3_RXRSTR (STR71X_UART3_BASE + STR71X_UART_RXRSTR_OFFSET) + +/* Register bit settings ***********************************************************/ + +/* UART control register (CR) */ + +#define STR71X_UARTCR_MODEMASK (0x0007) /* Bits 0-2: Mode */ +#define STR71X_UARTCR_MODE8BIT (0x0001) /* 8-bit */ +#define STR71X_UARTCR_MODE7BITP (0x0003) /* 7-bit with parity bit */ +#define STR71X_UARTCR_MODE9BIT (0x0004) /* 9-bit */ +#define STR71X_UARTCR_MODE8BITWU (0x0005) /* 8-bit with wakeup bit */ +#define STR71X_UARTCR_MODE8BITP (0x0007) /* 8-bit with parity bit */ +#define STR71X_UARTCR_STOPBITSMASK (0x0018) /* Bits 3-4: Stop bits */ +#define STR71X_UARTCR_STOPBIT05 (0x0000) /* 0.5 stop bits */ +#define STR71X_UARTCR_STOPBIT10 (0x0008) /* 1.0 stop bit */ +#define STR71X_UARTCR_STOPBIT15 (0x0010) /* 1.5 stop bits */ +#define STR71X_UARTCR_STOPBIT20 (0x0018) /* 2.0 stop bits */ +#define STR71X_UARTCR_PARITYODD (0x0020) /* Bit 5: Parity selection */ +#define STR71X_UARTCR_LOOPBACK (0x0040) /* Bit 6: Loopback mode enable */ +#define STR71X_UARTCR_RUN (0x0080) /* Bit 7: Baudrate generator run bit */ +#define STR71X_UARTCR_RXENABLE (0x0100) /* Bit 8: Receiver enable */ +#define STR71X_UARTCR_SCENABLE (0x0200) /* Bit 9: SmartCard mode enable */ +#define STR71X_UARTCR_FIFOENABLE (0x0400) /* Bit 10: FIFO enable */ + +/* UART interrupt enable (IER) register */ + +#define STR71X_UARTIER_RNE (0x0001) /* Bit 0: Rx buffer not empty */ +#define STR71X_UARTIER_TE (0x0002) /* Bit 1: Tx empty */ +#define STR71X_UARTIER_THE (0x0004) /* Bit 2: Tx half empty */ +#define STR71X_UARTIER_PERROR (0x0008) /* Bit 3: Parity error */ +#define STR71X_UARTIER_FRERROR (0x0010) /* Bit 4: Frame error */ +#define STR71X_UARTIER_OVERRUN (0x0020) /* Bit 5: Overrun error */ +#define STR71X_UARTIER_TIMEOUTNE (0x0040) /* Bit 6: Time out not empty*/ +#define STR71X_UARTIER_TIMEOUTIDLE (0x0080) /* Bit 7: Timeout out idle */ +#define STR71X_UARTIER_RHF (0x0100) /* Bit 8: Rx half full */ +#define STR71X_UARTIER_ALL (0x01ff) /* All interrupt bits */ + +/* UART status register (SR) */ + +#define STR71X_UARTSR_RNE (0x0001) /* Bit 0: Rx buffer not empty */ +#define STR71X_UARTSR_TE (0x0002) /* Bit 1: Tx empty */ +#define STR71X_UARTSR_THE (0x0004) /* Bit 2: Tx half empty */ +#define STR71X_UARTSR_PERR (0x0008) /* Bit 3: Parity error */ +#define STR71X_UARTSR_FRERROR (0x0010) /* Bit 4: Frame error */ +#define STR71X_UARTSR_OVERRUN (0x0020) /* Bit 5: Overrun error */ +#define STR71X_UARTSR_TIMEOUTNE (0x0040) /* Bit 6: Time out not empty */ +#define STR71X_UARTSR_TIMEOUTIDLE (0x0080) /* Bit 7: Timeout out idle */ +#define STR71X_UARTSR_RHF (0x0100) /* Bit 8: Rx half full */ +#define STR71X_UARTSR_TF (0x0200) /* Bit 9: Tx full */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_UART_H */ diff --git a/arch/arm/src/str71x/str71x_usb.h b/arch/arm/src/str71x/str71x_usb.h index 7fcbf57277a219b74d20ba7fb8bfc3631540f431..24ddd8a6b2c48f3cc1ae1a96ec99e778bfe69ff9 100644 --- a/arch/arm/src/str71x/str71x_usb.h +++ b/arch/arm/src/str71x/str71x_usb.h @@ -1,180 +1,180 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_usb.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_USB_H -#define __ARCH_ARM_SRC_STR71X_STR71X_USB_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "str71x_map.h" - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* USB registers ********************************************************************/ - -#define STR71X_USB_NENDPNTS (16) -#define STR71X_USB_EPR(ep) (STR71X_USB_BASE + ((ep) << 4)) -#define STR71X_USB_EP0R (STR71X_USB_BASE + 0x0000) /* Endpoint 0 */ -#define STR71X_USB_EP1R (STR71X_USB_BASE + 0x0004) /* Endpoint 1 */ -#define STR71X_USB_EP2R (STR71X_USB_BASE + 0x0008) /* Endpoint 2 */ -#define STR71X_USB_EP3R (STR71X_USB_BASE + 0x000c) /* Endpoint 3 */ -#define STR71X_USB_EP4R (STR71X_USB_BASE + 0x0010) /* Endpoint 4 */ -#define STR71X_USB_EP5R (STR71X_USB_BASE + 0x0014) /* Endpoint 5 */ -#define STR71X_USB_EP6R (STR71X_USB_BASE + 0x0018) /* Endpoint 6 */ -#define STR71X_USB_EP7R (STR71X_USB_BASE + 0x001c) /* Endpoint 7 */ -#define STR71X_USB_EP8R (STR71X_USB_BASE + 0x0020) /* Endpoint 8 */ -#define STR71X_USB_EP9R (STR71X_USB_BASE + 0x0024) /* Endpoint 9 */ -#define STR71X_USB_EP10R (STR71X_USB_BASE + 0x0028) /* Endpoint 10 */ -#define STR71X_USB_EP11R (STR71X_USB_BASE + 0x002c) /* Endpoint 11 */ -#define STR71X_USB_EP12R (STR71X_USB_BASE + 0x0030) /* Endpoint 12 */ -#define STR71X_USB_EP13R (STR71X_USB_BASE + 0x0034) /* Endpoint 13 */ -#define STR71X_USB_EP14R (STR71X_USB_BASE + 0x0038) /* Endpoint 14 */ -#define STR71X_USB_EP15R (STR71X_USB_BASE + 0x003c) /* Endpoint 15 */ -#define STR71X_USB_CNTR (STR71X_USB_BASE + 0x0040) /* Control register */ -#define STR71X_USB_ISTR (STR71X_USB_BASE + 0x0044) /* Interrupt status register */ -#define STR71X_USB_FNR (STR71X_USB_BASE + 0x0048) /* Frame number register */ -#define STR71X_USB_DADDR (STR71X_USB_BASE + 0x004C) /* Device address register */ -#define STR71X_USB_BTABLE (STR71X_USB_BASE + 0x0050) /* Buffer Table address register */ - -/* Register bit settings ***********************************************************/ - -/* Control Register (CNTR) */ - -#define USB_CNTR_FRES (1 << 0) /* Bit 0: Force usb reset */ -#define USB_CNTR_PDWN (1 << 1) /* Bit 1: Power down */ -#define USB_CNTR_LPMODE (1 << 2) /* Bit 2: Low-power mode */ -#define USB_CNTR_FSUSP (1 << 3) /* Bit 3: Force suspend */ -#define USB_CNTR_RESUME (1 << 4) /* Bit 4: Resume request */ -#define USB_CNTR_ESOFM (1 << 8) /* Bit 8: Expected start of frame */ -#define USB_CNTR_SOFM (1 << 9) /* Bit 9: Start of frame */ -#define USB_CNTR_RESETM (1 << 10) /* Bit 10: Reset */ -#define USB_CNTR_SUSPM (1 << 11) /* Bit 11: Suspend */ -#define USB_CNTR_WKUPM (1 << 12) /* Bit 12: Wake up */ -#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error */ -#define USB_CNTR_DOVRM (1 << 14) /* Bit 14: DMA over/underrun */ -#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct transfer */ - -/* Interrupt status register (ISTR) */ - -#define USB_ISTR_EPID_SHIFT 0 /* Bits 0-3: Endpoint Identifier */ -#define USB_ISTR_EPID_MASK (0x0f << USB_ISTR_EPID_SHIFT) -#define USB_ISTR_DIR (1 << 4) /* Bit 4: DIRection of transaction */ -#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected start of frame */ -#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start of frame */ -#define USB_ISTR_RESET (1 << 10) /* Bit 10: Reset */ -#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend */ -#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wakeup */ -#define USB_ISTR_ERR (1 << 13) /* Bit 13: Error */ -#define USB_ISTR_DOVR (1 << 14) /* Bit 14: DMA Over/underrun */ -#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */ - -/* Frame number register (FNR) */ - -#define USB_FNR_FN_SHIFT 0 /* Bit 0-10: Frame number */ -#define USB_FNR_LSOF_SHIFT 11 /* Bits 11-12 : Lost SOF */ -#define USB_FNR_LSOF_MASK (3 << USB_FNR_LSOF_SHIFT) -#define USB_FNR_FN_MASK (0x07ff << USB_FNR_FN_SHIFT) -#define USB_FNR_LCK (1 << 13) /* Bit 13: Locked */ -#define USB_FNR_RXDM (1 << 14) /* Bit 14: Status of D- data line */ -#define USB_FNR_RXDP (1 << 15) /* Bit 15: Status of D+ data line */ - -/* Device address register (DADDR) */ - -#define USB_DADDR_ADD_SHIFT 0 /* Bits 0-7: Device address */ -#define USB_DADDR_ADD_MASK (0x7f << USB_DADDR_ADD_SHIFT) -#define USB_DADDR_EF (1 << 7) /* Bit 8: Enable function */ - -/* Endpoint registers (EPR) */ - -#define USB_EPR_ADDRFIELD_SHIFT 0 /* Bits 0-3: Endpoint address */ -#define USB_EPR_ADDRFIELD_MASK (0x0f << USB_EPR_ADDRFIELD_SHIFT) -#define USB_EPR_TXSTAT_SHIFT 4 /* Bits 4-5: Endpoint TX status bit */ -#define USB_EPR_TXSTAT_MASK (3 << USB_EPR_TXSTAT_SHIFT) -# define USB_EPR_TXDIS (0 << USB_EPR_TXSTAT_SHIFT) /* Endpoint TX disabled */ -# define USB_EPR_TXSTALL (1 << USB_EPR_TXSTAT_SHIFT) /* Endpoint TX stalled */ -# define USB_EPR_TXNAK (2 << USB_EPR_TXSTAT_SHIFT) /* Endpoint TX NAKed */ -# define USB_EPR_TXVALID (3 << USB_EPR_TXSTAT_SHIFT) /* Endpoint TX valid */ -# define USB_EPR_TXDTOG1 (1 << USB_EPR_TXSTAT_SHIFT) /* Bit : Endpoint TX data toggle bit1 */ -# define USB_EPR_TXDTOG2 (2 << USB_EPR_TXSTAT_SHIFT) /* Bit : Endpoint TX data toggle bit2 */ -#define USB_EPR_DTOGTX (1 << 6) /* Bit 6: Endpoint data toggle TX */ -#define USB_EPR_CTRTX (1 << 7) /* Bit 7: Endpoint correct transfer TX */ -#define USB_EPR_KIND (1 << 8) /* Bit 8: Endpoint kind */ -#define USB_EPR_EPTYPE_SHIFT 9 /* Bits 9-10: Endpoint type */ -#define USB_EPR_EPTYPE_MASK (3 << USB_EPR_EPTYPE_SHIFT) -# define USB_EPR_BULK (0 << USB_EPR_EPTYPE_SHIFT) /* Endpoint BULK */ -# define USB_EPR_CONTROL (1 << USB_EPR_EPTYPE_SHIFT) /* Endpoint CONTROL */ -# define USB_EPR_ISOC (2 << USB_EPR_EPTYPE_SHIFT)) /* Endpoint ISOCHRONOUS */ -# define USB_EPR_INTERRUPT (3 << USB_EPR_EPTYPE_SHIFT) /* Endpoint INTERRUPT */ -#define USB_EPR_SETUP (1 << 11) /* Bit 11: Endpoint setup */ -#define USB_EPR_RXSTAT_SHIFT 12 /* Bits 12-13: Endpoint RX status bit */ -#define USB_EPR_RXSTAT_MASK (3 << USB_EPR_RXSTAT_SHIFT) -# define USB_EPR_RXDIS (0 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX disabled */ -# define USB_EPR_RXSTALL (1 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX stalled */ -# define USB_EPR_RXNAK (2 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX NAKed */ -# define USB_EPR_RXVALID (3 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX valid */ -# define USB_EPR_RXDTOG1 (1 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX data toggle bit1 */ -# define USB_EPR_RXDTOG2 (2 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX data toggle bit2 */ -#define USB_EPR_DTOGRX (1 << 14) /* Bit 14: Endpoint data toggle RX */ -#define USB_EPR_CTRRX (1 << 15) /* Bit 15: Endpoint correct transfer RX */ - -/* Endpoint register mask (no toggle fields) */ - -#define USB_EPR_NOTOGGLE_MASK (USB_EPR_CTRRX|USB_EPR_SETUP|USB_EPR_TFIELD|\ - USB_EPR_KIND|USB_EPR_CTRTX|USB_EPR_ADDRFIELD) - -/* Toggles only */ - -#define USB_EPR_TXDTOG_MASK (USB_EPR_TXSTAT_MASK|USB_EPR_NOTOGGLE_MASK) -#define USB_EPR_RXDTOG_MASK (USB_EPR_RXSTAT_MASK|USB_EPR_NOTOGGLE_MASK) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STR71X_STR71X_USB_H */ +/************************************************************************************ + * arch/arm/src/str71x/str71x_usb.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_USB_H +#define __ARCH_ARM_SRC_STR71X_STR71X_USB_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* USB registers ********************************************************************/ + +#define STR71X_USB_NENDPNTS (16) +#define STR71X_USB_EPR(ep) (STR71X_USB_BASE + ((ep) << 4)) +#define STR71X_USB_EP0R (STR71X_USB_BASE + 0x0000) /* Endpoint 0 */ +#define STR71X_USB_EP1R (STR71X_USB_BASE + 0x0004) /* Endpoint 1 */ +#define STR71X_USB_EP2R (STR71X_USB_BASE + 0x0008) /* Endpoint 2 */ +#define STR71X_USB_EP3R (STR71X_USB_BASE + 0x000c) /* Endpoint 3 */ +#define STR71X_USB_EP4R (STR71X_USB_BASE + 0x0010) /* Endpoint 4 */ +#define STR71X_USB_EP5R (STR71X_USB_BASE + 0x0014) /* Endpoint 5 */ +#define STR71X_USB_EP6R (STR71X_USB_BASE + 0x0018) /* Endpoint 6 */ +#define STR71X_USB_EP7R (STR71X_USB_BASE + 0x001c) /* Endpoint 7 */ +#define STR71X_USB_EP8R (STR71X_USB_BASE + 0x0020) /* Endpoint 8 */ +#define STR71X_USB_EP9R (STR71X_USB_BASE + 0x0024) /* Endpoint 9 */ +#define STR71X_USB_EP10R (STR71X_USB_BASE + 0x0028) /* Endpoint 10 */ +#define STR71X_USB_EP11R (STR71X_USB_BASE + 0x002c) /* Endpoint 11 */ +#define STR71X_USB_EP12R (STR71X_USB_BASE + 0x0030) /* Endpoint 12 */ +#define STR71X_USB_EP13R (STR71X_USB_BASE + 0x0034) /* Endpoint 13 */ +#define STR71X_USB_EP14R (STR71X_USB_BASE + 0x0038) /* Endpoint 14 */ +#define STR71X_USB_EP15R (STR71X_USB_BASE + 0x003c) /* Endpoint 15 */ +#define STR71X_USB_CNTR (STR71X_USB_BASE + 0x0040) /* Control register */ +#define STR71X_USB_ISTR (STR71X_USB_BASE + 0x0044) /* Interrupt status register */ +#define STR71X_USB_FNR (STR71X_USB_BASE + 0x0048) /* Frame number register */ +#define STR71X_USB_DADDR (STR71X_USB_BASE + 0x004C) /* Device address register */ +#define STR71X_USB_BTABLE (STR71X_USB_BASE + 0x0050) /* Buffer Table address register */ + +/* Register bit settings ***********************************************************/ + +/* Control Register (CNTR) */ + +#define USB_CNTR_FRES (1 << 0) /* Bit 0: Force usb reset */ +#define USB_CNTR_PDWN (1 << 1) /* Bit 1: Power down */ +#define USB_CNTR_LPMODE (1 << 2) /* Bit 2: Low-power mode */ +#define USB_CNTR_FSUSP (1 << 3) /* Bit 3: Force suspend */ +#define USB_CNTR_RESUME (1 << 4) /* Bit 4: Resume request */ +#define USB_CNTR_ESOFM (1 << 8) /* Bit 8: Expected start of frame */ +#define USB_CNTR_SOFM (1 << 9) /* Bit 9: Start of frame */ +#define USB_CNTR_RESETM (1 << 10) /* Bit 10: Reset */ +#define USB_CNTR_SUSPM (1 << 11) /* Bit 11: Suspend */ +#define USB_CNTR_WKUPM (1 << 12) /* Bit 12: Wake up */ +#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error */ +#define USB_CNTR_DOVRM (1 << 14) /* Bit 14: DMA over/underrun */ +#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct transfer */ + +/* Interrupt status register (ISTR) */ + +#define USB_ISTR_EPID_SHIFT 0 /* Bits 0-3: Endpoint Identifier */ +#define USB_ISTR_EPID_MASK (0x0f << USB_ISTR_EPID_SHIFT) +#define USB_ISTR_DIR (1 << 4) /* Bit 4: DIRection of transaction */ +#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected start of frame */ +#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start of frame */ +#define USB_ISTR_RESET (1 << 10) /* Bit 10: Reset */ +#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend */ +#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wakeup */ +#define USB_ISTR_ERR (1 << 13) /* Bit 13: Error */ +#define USB_ISTR_DOVR (1 << 14) /* Bit 14: DMA Over/underrun */ +#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */ + +/* Frame number register (FNR) */ + +#define USB_FNR_FN_SHIFT 0 /* Bit 0-10: Frame number */ +#define USB_FNR_LSOF_SHIFT 11 /* Bits 11-12 : Lost SOF */ +#define USB_FNR_LSOF_MASK (3 << USB_FNR_LSOF_SHIFT) +#define USB_FNR_FN_MASK (0x07ff << USB_FNR_FN_SHIFT) +#define USB_FNR_LCK (1 << 13) /* Bit 13: Locked */ +#define USB_FNR_RXDM (1 << 14) /* Bit 14: Status of D- data line */ +#define USB_FNR_RXDP (1 << 15) /* Bit 15: Status of D+ data line */ + +/* Device address register (DADDR) */ + +#define USB_DADDR_ADD_SHIFT 0 /* Bits 0-7: Device address */ +#define USB_DADDR_ADD_MASK (0x7f << USB_DADDR_ADD_SHIFT) +#define USB_DADDR_EF (1 << 7) /* Bit 8: Enable function */ + +/* Endpoint registers (EPR) */ + +#define USB_EPR_ADDRFIELD_SHIFT 0 /* Bits 0-3: Endpoint address */ +#define USB_EPR_ADDRFIELD_MASK (0x0f << USB_EPR_ADDRFIELD_SHIFT) +#define USB_EPR_TXSTAT_SHIFT 4 /* Bits 4-5: Endpoint TX status bit */ +#define USB_EPR_TXSTAT_MASK (3 << USB_EPR_TXSTAT_SHIFT) +# define USB_EPR_TXDIS (0 << USB_EPR_TXSTAT_SHIFT) /* Endpoint TX disabled */ +# define USB_EPR_TXSTALL (1 << USB_EPR_TXSTAT_SHIFT) /* Endpoint TX stalled */ +# define USB_EPR_TXNAK (2 << USB_EPR_TXSTAT_SHIFT) /* Endpoint TX NAKed */ +# define USB_EPR_TXVALID (3 << USB_EPR_TXSTAT_SHIFT) /* Endpoint TX valid */ +# define USB_EPR_TXDTOG1 (1 << USB_EPR_TXSTAT_SHIFT) /* Bit : Endpoint TX data toggle bit1 */ +# define USB_EPR_TXDTOG2 (2 << USB_EPR_TXSTAT_SHIFT) /* Bit : Endpoint TX data toggle bit2 */ +#define USB_EPR_DTOGTX (1 << 6) /* Bit 6: Endpoint data toggle TX */ +#define USB_EPR_CTRTX (1 << 7) /* Bit 7: Endpoint correct transfer TX */ +#define USB_EPR_KIND (1 << 8) /* Bit 8: Endpoint kind */ +#define USB_EPR_EPTYPE_SHIFT 9 /* Bits 9-10: Endpoint type */ +#define USB_EPR_EPTYPE_MASK (3 << USB_EPR_EPTYPE_SHIFT) +# define USB_EPR_BULK (0 << USB_EPR_EPTYPE_SHIFT) /* Endpoint BULK */ +# define USB_EPR_CONTROL (1 << USB_EPR_EPTYPE_SHIFT) /* Endpoint CONTROL */ +# define USB_EPR_ISOC (2 << USB_EPR_EPTYPE_SHIFT)) /* Endpoint ISOCHRONOUS */ +# define USB_EPR_INTERRUPT (3 << USB_EPR_EPTYPE_SHIFT) /* Endpoint INTERRUPT */ +#define USB_EPR_SETUP (1 << 11) /* Bit 11: Endpoint setup */ +#define USB_EPR_RXSTAT_SHIFT 12 /* Bits 12-13: Endpoint RX status bit */ +#define USB_EPR_RXSTAT_MASK (3 << USB_EPR_RXSTAT_SHIFT) +# define USB_EPR_RXDIS (0 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX disabled */ +# define USB_EPR_RXSTALL (1 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX stalled */ +# define USB_EPR_RXNAK (2 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX NAKed */ +# define USB_EPR_RXVALID (3 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX valid */ +# define USB_EPR_RXDTOG1 (1 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX data toggle bit1 */ +# define USB_EPR_RXDTOG2 (2 << USB_EPR_RXSTAT_SHIFT) /* Endpoint RX data toggle bit2 */ +#define USB_EPR_DTOGRX (1 << 14) /* Bit 14: Endpoint data toggle RX */ +#define USB_EPR_CTRRX (1 << 15) /* Bit 15: Endpoint correct transfer RX */ + +/* Endpoint register mask (no toggle fields) */ + +#define USB_EPR_NOTOGGLE_MASK (USB_EPR_CTRRX|USB_EPR_SETUP|USB_EPR_TFIELD|\ + USB_EPR_KIND|USB_EPR_CTRTX|USB_EPR_ADDRFIELD) + +/* Toggles only */ + +#define USB_EPR_TXDTOG_MASK (USB_EPR_TXSTAT_MASK|USB_EPR_NOTOGGLE_MASK) +#define USB_EPR_RXDTOG_MASK (USB_EPR_RXSTAT_MASK|USB_EPR_NOTOGGLE_MASK) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_USB_H */ diff --git a/arch/arm/src/str71x/str71x_wdog.h b/arch/arm/src/str71x/str71x_wdog.h index 75b89ab891dcf76442cdcc078854f2b01b98f997..81caf6a25f731d567f566b0becd4a1759a4a8ee5 100644 --- a/arch/arm/src/str71x/str71x_wdog.h +++ b/arch/arm/src/str71x/str71x_wdog.h @@ -1,75 +1,75 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_wdog.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H -#define __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "str71x_map.h" - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* Registers ************************************************************************/ - -#define STR71X_WDOG_CR (STR71X_WDOG_BASE + 0x0000) /* 16-bits wide */ -#define STR71X_WDOG_PR (STR71X_WDOG_BASE + 0x0004) /* 16-bits wide */ -#define STR71X_WDOG_VR (STR71X_WDOG_BASE + 0x0008) /* 16-bits wide */ -#define STR71X_WDOG_CNT (STR71X_WDOG_BASE + 0x000c) /* 16-bits wide */ -#define STR71X_WDOG_SR (STR71X_WDOG_BASE + 0x0010) /* 16-bits wide */ -#define STR71X_WDOG_MR (STR71X_WDOG_BASE + 0x0014) /* 16-bits wide */ -#define STR71X_WDOG_KR (STR71X_WDOG_BASE + 0x00018 /* 16-bits wide */ - -/* Register bit settings ***********************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H */ +/************************************************************************************ + * arch/arm/src/str71x/str71x_wdog.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H +#define __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* Registers ************************************************************************/ + +#define STR71X_WDOG_CR (STR71X_WDOG_BASE + 0x0000) /* 16-bits wide */ +#define STR71X_WDOG_PR (STR71X_WDOG_BASE + 0x0004) /* 16-bits wide */ +#define STR71X_WDOG_VR (STR71X_WDOG_BASE + 0x0008) /* 16-bits wide */ +#define STR71X_WDOG_CNT (STR71X_WDOG_BASE + 0x000c) /* 16-bits wide */ +#define STR71X_WDOG_SR (STR71X_WDOG_BASE + 0x0010) /* 16-bits wide */ +#define STR71X_WDOG_MR (STR71X_WDOG_BASE + 0x0014) /* 16-bits wide */ +#define STR71X_WDOG_KR (STR71X_WDOG_BASE + 0x00018 /* 16-bits wide */ + +/* Register bit settings ***********************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_WDOG_H */ diff --git a/arch/arm/src/str71x/str71x_xti.c b/arch/arm/src/str71x/str71x_xti.c index 3143ad76f3acda1de8b6c7b07b86b283bceb8f7f..3ef0a803dbc2a8768119717f120b7539060c46e7 100755 --- a/arch/arm/src/str71x/str71x_xti.c +++ b/arch/arm/src/str71x/str71x_xti.c @@ -2,7 +2,7 @@ * arch/arm/src/str71x/str71x_xti.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/str71x/str71x_xti.h b/arch/arm/src/str71x/str71x_xti.h index d9458c196ecc6152d1bf3a08e87a46a138ac36c8..638ab4f87763e755637be0e70992bd523cfacb54 100644 --- a/arch/arm/src/str71x/str71x_xti.h +++ b/arch/arm/src/str71x/str71x_xti.h @@ -1,105 +1,105 @@ -/************************************************************************************ - * arch/arm/src/str71x/str71x_xti.h - * - * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STR71X_STR71X_XTI_H -#define __ARCH_ARM_SRC_STR71X_STR71X_XTI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "str71x_map.h" - -/************************************************************************************ - * Pre-procesor Definitions - ************************************************************************************/ - -/* External Interupt Controller (XTI) registers *************************************/ - -#define STR71X_XTI_SR (STR71X_XTI_BASE + 0x001c) /* 8-bits wide */ -#define STR71X_XTI_CTRL (STR71X_XTI_BASE + 0x0024) /* 8-bits wide */ -#define STR71X_XTI_MRH (STR71X_XTI_BASE + 0x0028) /* 8-bits wide */ -#define STR71X_XTI_MRL (STR71X_XTI_BASE + 0x002c) /* 8-bits wide */ -#define STR71X_XTI_TRH (STR71X_XTI_BASE + 0x0030) /* 8-bits wide */ -#define STR71X_XTI_TRL (STR71X_XTI_BASE + 0x0034) /* 8-bits wide */ -#define STR71X_XTI_PRH (STR71X_XTI_BASE + 0x0038) /* 8-bits wide */ -#define STR71X_XTI_PRL (STR71X_XTI_BASE + 0x003c) /* 8-bits wide */ - -/* Register bit settings ************************************************************/ - -/* Control register (CTRL) */ - -#define STR71X_XTICTRL_WKUPINT (0x01) -#define STR71X_XTICTRL_ID1S (0x02) -#define STR71X_XTICTRL_STOP (0x04) - -/* Most registers are address by external interrupt line in two 8-bit high and low - * registers - */ - -#define STR71X_XTI_LINE(n) (1 << (n)) -#define STR71X_XTI_LINE0 STR71X_XTI_LINE(0) /* Low register */ -#define STR71X_XTI_LINE1 STR71X_XTI_LINE(1) -#define STR71X_XTI_LINE2 STR71X_XTI_LINE(2) -#define STR71X_XTI_LINE3 STR71X_XTI_LINE(3) -#define STR71X_XTI_LINE4 STR71X_XTI_LINE(4) -#define STR71X_XTI_LINE5 STR71X_XTI_LINE(5) -#define STR71X_XTI_LINE6 STR71X_XTI_LINE(6) -#define STR71X_XTI_LINE7 STR71X_XTI_LINE(7) - -#define STR71X_XTI_LINE8 STR71X_XTI_LINE(8) /* High register */ -#define STR71X_XTI_LINE9 STR71X_XTI_LINE(9) -#define STR71X_XTI_LINE10 STR71X_XTI_LINE(10) -#define STR71X_XTI_LINE11 STR71X_XTI_LINE(11) -#define STR71X_XTI_LINE12 STR71X_XTI_LINE(12) -#define STR71X_XTI_LINE13 STR71X_XTI_LINE(13) -#define STR71X_XTI_LINE14 STR71X_XTI_LINE(14) -#define STR71X_XTI_LINE15 STR71X_XTI_LINE(15) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* _ARCH_ARM_SRC_STR71X_STR71X_XTI_H */ +/************************************************************************************ + * arch/arm/src/str71x/str71x_xti.h + * + * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STR71X_STR71X_XTI_H +#define __ARCH_ARM_SRC_STR71X_STR71X_XTI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "str71x_map.h" + +/************************************************************************************ + * Pre-procesor Definitions + ************************************************************************************/ + +/* External Interupt Controller (XTI) registers *************************************/ + +#define STR71X_XTI_SR (STR71X_XTI_BASE + 0x001c) /* 8-bits wide */ +#define STR71X_XTI_CTRL (STR71X_XTI_BASE + 0x0024) /* 8-bits wide */ +#define STR71X_XTI_MRH (STR71X_XTI_BASE + 0x0028) /* 8-bits wide */ +#define STR71X_XTI_MRL (STR71X_XTI_BASE + 0x002c) /* 8-bits wide */ +#define STR71X_XTI_TRH (STR71X_XTI_BASE + 0x0030) /* 8-bits wide */ +#define STR71X_XTI_TRL (STR71X_XTI_BASE + 0x0034) /* 8-bits wide */ +#define STR71X_XTI_PRH (STR71X_XTI_BASE + 0x0038) /* 8-bits wide */ +#define STR71X_XTI_PRL (STR71X_XTI_BASE + 0x003c) /* 8-bits wide */ + +/* Register bit settings ************************************************************/ + +/* Control register (CTRL) */ + +#define STR71X_XTICTRL_WKUPINT (0x01) +#define STR71X_XTICTRL_ID1S (0x02) +#define STR71X_XTICTRL_STOP (0x04) + +/* Most registers are address by external interrupt line in two 8-bit high and low + * registers + */ + +#define STR71X_XTI_LINE(n) (1 << (n)) +#define STR71X_XTI_LINE0 STR71X_XTI_LINE(0) /* Low register */ +#define STR71X_XTI_LINE1 STR71X_XTI_LINE(1) +#define STR71X_XTI_LINE2 STR71X_XTI_LINE(2) +#define STR71X_XTI_LINE3 STR71X_XTI_LINE(3) +#define STR71X_XTI_LINE4 STR71X_XTI_LINE(4) +#define STR71X_XTI_LINE5 STR71X_XTI_LINE(5) +#define STR71X_XTI_LINE6 STR71X_XTI_LINE(6) +#define STR71X_XTI_LINE7 STR71X_XTI_LINE(7) + +#define STR71X_XTI_LINE8 STR71X_XTI_LINE(8) /* High register */ +#define STR71X_XTI_LINE9 STR71X_XTI_LINE(9) +#define STR71X_XTI_LINE10 STR71X_XTI_LINE(10) +#define STR71X_XTI_LINE11 STR71X_XTI_LINE(11) +#define STR71X_XTI_LINE12 STR71X_XTI_LINE(12) +#define STR71X_XTI_LINE13 STR71X_XTI_LINE(13) +#define STR71X_XTI_LINE14 STR71X_XTI_LINE(14) +#define STR71X_XTI_LINE15 STR71X_XTI_LINE(15) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* _ARCH_ARM_SRC_STR71X_STR71X_XTI_H */ diff --git a/arch/avr/include/arch.h b/arch/avr/include/arch.h index 389e5689a8a908b5b233888930f9d20360436a02..0f3ce5fcbad41ab2cc71bd6333e5611b49d47420 100644 --- a/arch/avr/include/arch.h +++ b/arch/avr/include/arch.h @@ -2,7 +2,7 @@ * arch/avr/include/arch.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/include/at32uc3/irq.h b/arch/avr/include/at32uc3/irq.h index 670a4504c78624e21fdcd0a73c7a3dbc1acba3e4..00802ebab19ab491eccae5b5fd23e9246f740e6b 100755 --- a/arch/avr/include/at32uc3/irq.h +++ b/arch/avr/include/at32uc3/irq.h @@ -2,7 +2,7 @@ * arch/avr/include/at32uc3/irq.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/include/at90usb/irq.h b/arch/avr/include/at90usb/irq.h index 8e6412125d04250bc5922ebb99a17b3ce4b7838b..4c11d368872a93799d4d470f6e32e5d59a37387a 100644 --- a/arch/avr/include/at90usb/irq.h +++ b/arch/avr/include/at90usb/irq.h @@ -2,7 +2,7 @@ * arch/avr/include/avr/at90usb/irq.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/include/atmega/irq.h b/arch/avr/include/atmega/irq.h index aabf227ee0eb85983d9965f1002e577c6de09095..194c7d008474924409c0a31832b020b51e4cbd35 100644 --- a/arch/avr/include/atmega/irq.h +++ b/arch/avr/include/atmega/irq.h @@ -2,7 +2,7 @@ * arch/avr/include/avr/atmega/irq.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/include/avr/avr.h b/arch/avr/include/avr/avr.h index d6b6f428dfb276c68b5a0951993bf7a920a19161..fc3e82bb4bb190ed017c7736b005fdb9202ef5f7 100755 --- a/arch/avr/include/avr/avr.h +++ b/arch/avr/include/avr/avr.h @@ -2,7 +2,7 @@ * arch/avr/include/avr/avr.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/include/avr/irq.h b/arch/avr/include/avr/irq.h index 242114e98e3696ed9cced5cddfee2b3553dc5b11..9a84d1aa7f7d7e1e752e4927671604c51c52b4a0 100644 --- a/arch/avr/include/avr/irq.h +++ b/arch/avr/include/avr/irq.h @@ -2,7 +2,7 @@ * arch/avr/include/avr/irq.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/include/avr/syscall.h b/arch/avr/include/avr/syscall.h index de5c4e31793dade3e5b7d1a40ef3209f8a7702f2..515c7adfb361fd079a18931a5bbcb120f9ef567f 100644 --- a/arch/avr/include/avr/syscall.h +++ b/arch/avr/include/avr/syscall.h @@ -2,7 +2,7 @@ * arch/avr/include/avr/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/include/avr/types.h b/arch/avr/include/avr/types.h index e0a70fb7f94d39ac2a848d804dae69daccbfc732..4ea22aeafae9fc3026c223ba81598263fbfbb8eb 100644 --- a/arch/avr/include/avr/types.h +++ b/arch/avr/include/avr/types.h @@ -2,7 +2,7 @@ * arch/avr/include/avr/types.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/include/avr32/avr32.h b/arch/avr/include/avr32/avr32.h index 2c0c66dbff8beeb3d7c419cafa20ef2d48d62dea..2488516ca2bf0dec443f7cb182c2fce2bb71a806 100755 --- a/arch/avr/include/avr32/avr32.h +++ b/arch/avr/include/avr32/avr32.h @@ -2,7 +2,7 @@ * arch/avr/include/avr32/avr32.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/include/avr32/irq.h b/arch/avr/include/avr32/irq.h index 5d4ddf6b1ca2b0beb9f398a3276a9ee4f213be73..09ee0296ab7d180f3ceeb71f38996f4eb6e8ad5e 100644 --- a/arch/avr/include/avr32/irq.h +++ b/arch/avr/include/avr32/irq.h @@ -2,7 +2,7 @@ * arch/avr/include/avr32/irq.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/include/avr32/syscall.h b/arch/avr/include/avr32/syscall.h index 2fb43dde41be183b3f3afea75e33789e316bcfff..920b196485da40f1de5e836b07e5abee1f08fb0b 100644 --- a/arch/avr/include/avr32/syscall.h +++ b/arch/avr/include/avr32/syscall.h @@ -2,7 +2,7 @@ * arch/avr/include/avr32/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/include/avr32/types.h b/arch/avr/include/avr32/types.h index 4b5f20cea601f476467c45a6b3c7d98f11dc7894..6a7c00b4780b5fa7c41216e3ccc406a6d977ea55 100644 --- a/arch/avr/include/avr32/types.h +++ b/arch/avr/include/avr32/types.h @@ -2,7 +2,7 @@ * arch/avr/include/avr32/types.h * * Copyright (C) 2010, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/include/irq.h b/arch/avr/include/irq.h index 8f5ef73bc0a6b43da1ffd7519d8ce337b5b0a618..de9981cd508b7ffc3f16e5012d62a636f5a773c9 100644 --- a/arch/avr/include/irq.h +++ b/arch/avr/include/irq.h @@ -2,7 +2,7 @@ * arch/avr/include/irq.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/include/limits.h b/arch/avr/include/limits.h index 2213834739ef62e6da386d70e750cc507423c157..2089bf9379a9d5182da1a5d4444fc22bf703c698 100644 --- a/arch/avr/include/limits.h +++ b/arch/avr/include/limits.h @@ -2,7 +2,7 @@ * arch/avr/include/limits.h * * Copyright (C) 2010, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/include/syscall.h b/arch/avr/include/syscall.h index 29e2d8871f8bb9e23b0a5aa9bc378b0720c03fd8..aa6c501d1fdeb769eb134f8cbecf6e33b09c2281 100644 --- a/arch/avr/include/syscall.h +++ b/arch/avr/include/syscall.h @@ -2,7 +2,7 @@ * arch/avr/include/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/include/types.h b/arch/avr/include/types.h index 48481039f8a51da25a2b4a4624b32235246bc2aa..8089c96c137d3999a4693ccde5caf16a4ce322be 100644 --- a/arch/avr/include/types.h +++ b/arch/avr/include/types.h @@ -2,7 +2,7 @@ * arch/avr/include/types.h * * Copyright (C) 2010, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/Make.defs b/arch/avr/src/at32uc3/Make.defs index 49d35ed4be98827ecc70c04f0d61b4ebc0eefce1..69d17456d075a7797bf0066505be25a02f8fa6a5 100644 --- a/arch/avr/src/at32uc3/Make.defs +++ b/arch/avr/src/at32uc3/Make.defs @@ -2,7 +2,7 @@ # arch/avr/src/at32uc3/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_abdac.h b/arch/avr/src/at32uc3/at32uc3_abdac.h index f71229f895d73753ea4ec2cdec48d3ac8b9490fa..b2f01e30c80f3d231b954011703e3dbdc9777d3e 100644 --- a/arch/avr/src/at32uc3/at32uc3_abdac.h +++ b/arch/avr/src/at32uc3/at32uc3_abdac.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_abdac.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_adc.h b/arch/avr/src/at32uc3/at32uc3_adc.h index 7695e6e653677cfd9ce9455be7a0d09726909f74..37b1456b49768421878f16827c50a03cfc8ddf8a 100644 --- a/arch/avr/src/at32uc3/at32uc3_adc.h +++ b/arch/avr/src/at32uc3/at32uc3_adc.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_adc.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_clkinit.c b/arch/avr/src/at32uc3/at32uc3_clkinit.c index cf75ad00193d1ccf64cbb52b5649c5732788f7ba..1a39aad78349c1fceea11da3119b7872307a00ff 100644 --- a/arch/avr/src/at32uc3/at32uc3_clkinit.c +++ b/arch/avr/src/at32uc3/at32uc3_clkinit.c @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_clkinit.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_config.h b/arch/avr/src/at32uc3/at32uc3_config.h index c1b337676581cd1f690f331b7cff8e5561b7ac25..1f942591a3a258a2fa697bf97901c9c481674567 100644 --- a/arch/avr/src/at32uc3/at32uc3_config.h +++ b/arch/avr/src/at32uc3/at32uc3_config.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_config.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_eic.h b/arch/avr/src/at32uc3/at32uc3_eic.h index 505d0b84bdbef267062ad584dee46bb6bf8340aa..44c050b2b47400a655ef3bc0caa5197a0ac552df 100644 --- a/arch/avr/src/at32uc3/at32uc3_eic.h +++ b/arch/avr/src/at32uc3/at32uc3_eic.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_eic.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_flashc.h b/arch/avr/src/at32uc3/at32uc3_flashc.h index 45df326baba0f2cb5faa5a76a14ed5f9f8243dab..e66663fee3612bd78de42609196afa40b48d2c58 100644 --- a/arch/avr/src/at32uc3/at32uc3_flashc.h +++ b/arch/avr/src/at32uc3/at32uc3_flashc.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_flashc.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_gpio.c b/arch/avr/src/at32uc3/at32uc3_gpio.c index 2a2948f8770578207a4055b6058d71aafee5cd5c..a0e39e19dd957fe949eeaee8277e4e31bb93e3a6 100644 --- a/arch/avr/src/at32uc3/at32uc3_gpio.c +++ b/arch/avr/src/at32uc3/at32uc3_gpio.c @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_gpio.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_gpio.h b/arch/avr/src/at32uc3/at32uc3_gpio.h index b5f377efbfac018910e63017e7c45569a903a9eb..6467ef7c14e5d79608d2eee93acb14aa39df3c44 100644 --- a/arch/avr/src/at32uc3/at32uc3_gpio.h +++ b/arch/avr/src/at32uc3/at32uc3_gpio.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_gpio.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_gpioirq.c b/arch/avr/src/at32uc3/at32uc3_gpioirq.c index 0e05bf02a1db4460c5a97a153c838e61c83c77a0..c55ba3d136885560a87bb0aa73042fef5dca3536 100644 --- a/arch/avr/src/at32uc3/at32uc3_gpioirq.c +++ b/arch/avr/src/at32uc3/at32uc3_gpioirq.c @@ -3,7 +3,7 @@ * arch/avr/src/chip/at32uc3_gpioirq.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_hmatrix.h b/arch/avr/src/at32uc3/at32uc3_hmatrix.h index 6190fe3de31faef806f362bd5304c31db22d1f7e..40708fc1f162269c755518c00943117132de4cf3 100644 --- a/arch/avr/src/at32uc3/at32uc3_hmatrix.h +++ b/arch/avr/src/at32uc3/at32uc3_hmatrix.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_hmatrix.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_intc.h b/arch/avr/src/at32uc3/at32uc3_intc.h index 700b274596b04a9964318e3cd86295b146783914..25aedd275b59bf3bfa0fa4a28d5c1b9b942a654c 100644 --- a/arch/avr/src/at32uc3/at32uc3_intc.h +++ b/arch/avr/src/at32uc3/at32uc3_intc.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_intc.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_internal.h b/arch/avr/src/at32uc3/at32uc3_internal.h index 6fa53ef056c5c335e6cc5bf07374b4d28f6774db..57d52a2885efad348597b6da9a1a898c3b674dc9 100644 --- a/arch/avr/src/at32uc3/at32uc3_internal.h +++ b/arch/avr/src/at32uc3/at32uc3_internal.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_internal.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_irq.c b/arch/avr/src/at32uc3/at32uc3_irq.c index ce42fd03d223b5b640d31751b561fb7fa48a1af6..771d1b9da92b91b3bace9cea65c584f1eb4684ca 100644 --- a/arch/avr/src/at32uc3/at32uc3_irq.c +++ b/arch/avr/src/at32uc3/at32uc3_irq.c @@ -3,7 +3,7 @@ * arch/avr/src/chip/at32uc3_irq.c * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_memorymap.h b/arch/avr/src/at32uc3/at32uc3_memorymap.h index dfe31ee272a277f751d8d476dfbbc4fad9e6ef0d..8df5183f79d6bcaad61bb14fb1788cfe61b49895 100644 --- a/arch/avr/src/at32uc3/at32uc3_memorymap.h +++ b/arch/avr/src/at32uc3/at32uc3_memorymap.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_memorymap.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_pdca.h b/arch/avr/src/at32uc3/at32uc3_pdca.h index 7a6c3bfe16ca77495c3a01028615ff55b8d63082..ee84f8f09080a242e819c349573dffeeb7d72d32 100644 --- a/arch/avr/src/at32uc3/at32uc3_pdca.h +++ b/arch/avr/src/at32uc3/at32uc3_pdca.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_pdca.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_pinmux.h b/arch/avr/src/at32uc3/at32uc3_pinmux.h index 0c55fb94ca1384622e68527b93942a76b581e318..e5c7e71436b3cc26d75417994b88cb076808725e 100644 --- a/arch/avr/src/at32uc3/at32uc3_pinmux.h +++ b/arch/avr/src/at32uc3/at32uc3_pinmux.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_pinmux.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_pm.h b/arch/avr/src/at32uc3/at32uc3_pm.h index 365876877387d563ba4953803f231ed1477d0f55..964d839ee0072fdf97014d26f8de3e3f39f27508 100644 --- a/arch/avr/src/at32uc3/at32uc3_pm.h +++ b/arch/avr/src/at32uc3/at32uc3_pm.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_pm.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_pwm.h b/arch/avr/src/at32uc3/at32uc3_pwm.h index e2dee47e589aefbba645370d638432795bd356f9..5aedf7d601acbdfaf954587ea47c0132bd326b73 100644 --- a/arch/avr/src/at32uc3/at32uc3_pwm.h +++ b/arch/avr/src/at32uc3/at32uc3_pwm.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_pwm.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_rtc.h b/arch/avr/src/at32uc3/at32uc3_rtc.h index 1a861d0bccf477daabba164589f126b7d3ea1a91..aa762065cb5ffcaacfb39de75def4354f47cf644 100644 --- a/arch/avr/src/at32uc3/at32uc3_rtc.h +++ b/arch/avr/src/at32uc3/at32uc3_rtc.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_rtc.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_spi.h b/arch/avr/src/at32uc3/at32uc3_spi.h index c2a4b99d3ed487af06ffba7e1fe339cc846b43cd..1c1a804504dd84af57d468bc3b4a266a2ac76ed0 100644 --- a/arch/avr/src/at32uc3/at32uc3_spi.h +++ b/arch/avr/src/at32uc3/at32uc3_spi.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_spi.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_ssc.h b/arch/avr/src/at32uc3/at32uc3_ssc.h index fa67d4714a5ffc217f7d19d2bb742e84806146c1..35b286b6aed945a296cc84d842a1f6a46eab4675 100644 --- a/arch/avr/src/at32uc3/at32uc3_ssc.h +++ b/arch/avr/src/at32uc3/at32uc3_ssc.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_ssc.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_tc.h b/arch/avr/src/at32uc3/at32uc3_tc.h index f615d1b9366b65e99623d52d12fd59cecf1ac212..821b35b333568c89dce1763a930ae5e864d718cc 100644 --- a/arch/avr/src/at32uc3/at32uc3_tc.h +++ b/arch/avr/src/at32uc3/at32uc3_tc.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_tc.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_timerisr.c b/arch/avr/src/at32uc3/at32uc3_timerisr.c index 3d171390962efcde9b6ee116f44532db637bb424..711cef3c911bff3e86b81424c8b324145ca52910 100644 --- a/arch/avr/src/at32uc3/at32uc3_timerisr.c +++ b/arch/avr/src/at32uc3/at32uc3_timerisr.c @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_timerisr.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_twi.h b/arch/avr/src/at32uc3/at32uc3_twi.h index afec99fb12424a2349b38c7a228ba802a65482aa..3a82b733a631defa0fbf7768c8bfec7b7eda478f 100644 --- a/arch/avr/src/at32uc3/at32uc3_twi.h +++ b/arch/avr/src/at32uc3/at32uc3_twi.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_twi.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_usart.h b/arch/avr/src/at32uc3/at32uc3_usart.h index 350946321c51d9f086eefeacdc60256d1cc52d5d..17b01e08440f231c38d966643367686245a071ad 100644 --- a/arch/avr/src/at32uc3/at32uc3_usart.h +++ b/arch/avr/src/at32uc3/at32uc3_usart.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_usart.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_usbb.h b/arch/avr/src/at32uc3/at32uc3_usbb.h index b6bc1765ae74701e8e0fc0a9d9c2b16f6da6664a..247f7d5f0f371d11bad808a33980014dc71e10f3 100644 --- a/arch/avr/src/at32uc3/at32uc3_usbb.h +++ b/arch/avr/src/at32uc3/at32uc3_usbb.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_usbb.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3_wdt.h b/arch/avr/src/at32uc3/at32uc3_wdt.h index 384e67265be13fdc051b5936f0981b3b3f53b277..b3bfde6a93daaf1922621fe58e23966b70566485 100644 --- a/arch/avr/src/at32uc3/at32uc3_wdt.h +++ b/arch/avr/src/at32uc3/at32uc3_wdt.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3_wdt.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3a_pinmux.h b/arch/avr/src/at32uc3/at32uc3a_pinmux.h index 124d056d6a0deed56b15ae6962f5e169253eb20d..695db47b58e30151f676873e24ae5097ea9046d4 100644 --- a/arch/avr/src/at32uc3/at32uc3a_pinmux.h +++ b/arch/avr/src/at32uc3/at32uc3a_pinmux.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3a_pinmux.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/at32uc3b_pinmux.h b/arch/avr/src/at32uc3/at32uc3b_pinmux.h index 352af2635c3b16de93f8f267bf60409530636a1e..d5758745da12f995c6a57685422ad3e267eaf2df 100644 --- a/arch/avr/src/at32uc3/at32uc3b_pinmux.h +++ b/arch/avr/src/at32uc3/at32uc3b_pinmux.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/at32uc3b_pinmux.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at32uc3/chip.h b/arch/avr/src/at32uc3/chip.h index ec2351b9cff6dfd9b40d1d04522b66acfdfb11b1..42b3ea681dc8ce80f43ac2faea9ecdc903e193c3 100644 --- a/arch/avr/src/at32uc3/chip.h +++ b/arch/avr/src/at32uc3/chip.h @@ -2,7 +2,7 @@ * arch/avr/src/at32uc3/chip.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at90usb/Make.defs b/arch/avr/src/at90usb/Make.defs index 0497acd9504109c8d05569ce108067949b5c6317..be372613438cc83e46c3bdda4c0c1b73fe6d7cdc 100644 --- a/arch/avr/src/at90usb/Make.defs +++ b/arch/avr/src/at90usb/Make.defs @@ -2,7 +2,7 @@ # arch/avr/src/at90usb/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at90usb/at90usb_exceptions.S b/arch/avr/src/at90usb/at90usb_exceptions.S index 79eda5f18d30d02b029b6b7b63ac04547a97a53b..cb51c1616c796c2ec08d8e89e1a12e44e7b174a3 100755 --- a/arch/avr/src/at90usb/at90usb_exceptions.S +++ b/arch/avr/src/at90usb/at90usb_exceptions.S @@ -2,7 +2,7 @@ * arch/avr/src/at90usb/at90usb_exceptions.S * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at90usb/at90usb_head.S b/arch/avr/src/at90usb/at90usb_head.S index 4efa973b6d6668d3781fc91ae650fbd3335ec8d3..be747632b7602bd933d7ae80fc4c972ff8844bb3 100755 --- a/arch/avr/src/at90usb/at90usb_head.S +++ b/arch/avr/src/at90usb/at90usb_head.S @@ -2,7 +2,7 @@ * arch/avr32/src/at90usb/at90usb_head.S * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at90usb/at90usb_internal.h b/arch/avr/src/at90usb/at90usb_internal.h index 609631dd50898515a56d469d2b4dc94bde24f941..329f3ce4a6069b7eb3dc2cd357cb20d25af563a2 100644 --- a/arch/avr/src/at90usb/at90usb_internal.h +++ b/arch/avr/src/at90usb/at90usb_internal.h @@ -2,7 +2,7 @@ * arch/avr/src/at90usb/at90usb_internal.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at90usb/at90usb_lowconsole.c b/arch/avr/src/at90usb/at90usb_lowconsole.c index bbba4478b92d4f2e79516ee35008e8c782d91be4..d29f9a832580cfa115e1fed92ebe66e665447bc6 100644 --- a/arch/avr/src/at90usb/at90usb_lowconsole.c +++ b/arch/avr/src/at90usb/at90usb_lowconsole.c @@ -2,7 +2,7 @@ * arch/avr/src/at90usb/at90usb_lowconsole.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at90usb/at90usb_memorymap.h b/arch/avr/src/at90usb/at90usb_memorymap.h index 71635d3832481df0ba6c8f0d9e11532856092eaf..a40bd3d36f9f22793c4432419603e84989804820 100644 --- a/arch/avr/src/at90usb/at90usb_memorymap.h +++ b/arch/avr/src/at90usb/at90usb_memorymap.h @@ -2,7 +2,7 @@ * arch/avr/src/at90usb/at90usb_memorymap.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at90usb/at90usb_timerisr.c b/arch/avr/src/at90usb/at90usb_timerisr.c index 5e92acb5a8916e7b5953055681586191f711e5f9..21e577ad2766696030015c819d8af14de8f36151 100644 --- a/arch/avr/src/at90usb/at90usb_timerisr.c +++ b/arch/avr/src/at90usb/at90usb_timerisr.c @@ -2,7 +2,7 @@ * arch/avr/src/at90usb/at90usb_timerisr.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/at90usb/chip.h b/arch/avr/src/at90usb/chip.h index c58c2040d1ad034a20177044bfd8b0f7c825dcfe..4e3ec8297b1de4cdffc4a9b94c52cb859ede8c56 100644 --- a/arch/avr/src/at90usb/chip.h +++ b/arch/avr/src/at90usb/chip.h @@ -2,7 +2,7 @@ * arch/avr/src/at90usb/chip.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/atmega/Make.defs b/arch/avr/src/atmega/Make.defs index b3451aaa1f4545628c5f6d5b2c77cd0be842d9a1..a7d3a881b50133e8b81493914db6c4361d68fd69 100644 --- a/arch/avr/src/atmega/Make.defs +++ b/arch/avr/src/atmega/Make.defs @@ -2,7 +2,7 @@ # arch/avr/src/atmega/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/avr/src/atmega/atmega_exceptions.S b/arch/avr/src/atmega/atmega_exceptions.S index 4050f1880edc97ca1bc1460372f563ada644448e..0b8b4416d5b215bf5ec913e2c5677ad9b36df8fa 100755 --- a/arch/avr/src/atmega/atmega_exceptions.S +++ b/arch/avr/src/atmega/atmega_exceptions.S @@ -2,7 +2,7 @@ * arch/avr/src/atmega/atmega_exceptions.S * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/atmega/atmega_head.S b/arch/avr/src/atmega/atmega_head.S index b930c309bde6fcf837ac7889693402333ccee005..95de2f100cf2960f547d7ecac84deaaaaa4faf72 100755 --- a/arch/avr/src/atmega/atmega_head.S +++ b/arch/avr/src/atmega/atmega_head.S @@ -2,7 +2,7 @@ * arch/avr32/src/atmega/atmega_head.S * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/atmega/atmega_internal.h b/arch/avr/src/atmega/atmega_internal.h index a062835bdcb564827e66948f98103ed5dde802cc..4a51661a7a5a76cf08b98768af38faec679c98c0 100644 --- a/arch/avr/src/atmega/atmega_internal.h +++ b/arch/avr/src/atmega/atmega_internal.h @@ -2,7 +2,7 @@ * arch/avr/src/atmega/atmega_internal.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/atmega/atmega_lowconsole.c b/arch/avr/src/atmega/atmega_lowconsole.c index 4e52f4aba18b0ba4a123683fa2d7e53787767c92..9a03c56a47e7a0a197f5e5c55ee6a21aa14b6a5c 100644 --- a/arch/avr/src/atmega/atmega_lowconsole.c +++ b/arch/avr/src/atmega/atmega_lowconsole.c @@ -2,7 +2,7 @@ * arch/avr/src/atmega/atmega_lowconsole.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/atmega/atmega_memorymap.h b/arch/avr/src/atmega/atmega_memorymap.h index 7b990754c91d863a1c38d6da8ec43e03d213edf2..d957247d5c36ac010cf3e2bfbbf6fd1ef073a677 100644 --- a/arch/avr/src/atmega/atmega_memorymap.h +++ b/arch/avr/src/atmega/atmega_memorymap.h @@ -2,7 +2,7 @@ * arch/avr/src/atmega/atmega_memorymap.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/atmega/atmega_timerisr.c b/arch/avr/src/atmega/atmega_timerisr.c index d724bf6f8a807d440fcf06c9d6c332dd40db04a5..bcac060a0262ecbc45ac8504f91980af85812536 100644 --- a/arch/avr/src/atmega/atmega_timerisr.c +++ b/arch/avr/src/atmega/atmega_timerisr.c @@ -2,7 +2,7 @@ * arch/avr/src/atmega/atmega_timerisr.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/atmega/chip.h b/arch/avr/src/atmega/chip.h index 0e3f779ab78845cc3e362d14fc829a31aff52679..43f54df3134203e3981b75e2823b130f2481f9b1 100644 --- a/arch/avr/src/atmega/chip.h +++ b/arch/avr/src/atmega/chip.h @@ -2,7 +2,7 @@ * arch/avr/src/atmega/chip.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/avr_internal.h b/arch/avr/src/avr/avr_internal.h index 13c5d37c5a47bad1a43e830f154f7c81dd9bd6b8..c87254b77084e7017c94ace349df1ea2b9c87cfb 100644 --- a/arch/avr/src/avr/avr_internal.h +++ b/arch/avr/src/avr/avr_internal.h @@ -2,7 +2,7 @@ * arch/avr/src/avr/avr_internal.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/excptmacros.h b/arch/avr/src/avr/excptmacros.h index 2d55a810955ed849e914ca1b0a73e5f487339360..51e1e61a1e6e7b819663438a6c6fb1ecaf3fbe22 100755 --- a/arch/avr/src/avr/excptmacros.h +++ b/arch/avr/src/avr/excptmacros.h @@ -2,7 +2,7 @@ * arch/avr/src/avr/excptmacros.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/up_blocktask.c b/arch/avr/src/avr/up_blocktask.c index 6444132e0267b729d1f4b472be9023529d951425..4bc587903de543e7f4cf83adf099d9b4c134f40c 100755 --- a/arch/avr/src/avr/up_blocktask.c +++ b/arch/avr/src/avr/up_blocktask.c @@ -2,7 +2,7 @@ * arch/avr/src/avr/up_blocktask.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/up_checkstack.c b/arch/avr/src/avr/up_checkstack.c index bf646f7ec9ba3517f1647884d355155b1a029f25..b8325ccbc8e60d8dd937c456e387e50476700069 100644 --- a/arch/avr/src/avr/up_checkstack.c +++ b/arch/avr/src/avr/up_checkstack.c @@ -2,7 +2,7 @@ * arch/avr/src/avr/up_checkstack.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/up_copystate.c b/arch/avr/src/avr/up_copystate.c index 5423202f2baac02849b3419d074955cb899ef03b..4c9c13bf8338586cf3044bddf6407344f185fe64 100644 --- a/arch/avr/src/avr/up_copystate.c +++ b/arch/avr/src/avr/up_copystate.c @@ -2,7 +2,7 @@ * arch/avr/src/avr/up_copystate.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/up_createstack.c b/arch/avr/src/avr/up_createstack.c index 2ef60e8159b0eb27db56302ab3febc560350d22b..67219ec9c143fc44634025a73f11257a8191fd16 100644 --- a/arch/avr/src/avr/up_createstack.c +++ b/arch/avr/src/avr/up_createstack.c @@ -2,7 +2,7 @@ * arch/avr/src/avr/up_createstack.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/up_doirq.c b/arch/avr/src/avr/up_doirq.c index e3d3f18217dc83d7e6f56970b481d03514d656a7..e38bf7fa845cdd21c21e849a958c9fa98e99585d 100644 --- a/arch/avr/src/avr/up_doirq.c +++ b/arch/avr/src/avr/up_doirq.c @@ -2,7 +2,7 @@ * arch/avr/src/avr/up_doirq.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/up_dumpstate.c b/arch/avr/src/avr/up_dumpstate.c index 73cb823c4cb4b87e2d29b4c3577e61395a23039b..902c2ce9fd9d3a57fc166537dc4adb16dbd660c0 100644 --- a/arch/avr/src/avr/up_dumpstate.c +++ b/arch/avr/src/avr/up_dumpstate.c @@ -2,7 +2,7 @@ * arch/avr/src/avr/up_dumpstate.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/up_initialstate.c b/arch/avr/src/avr/up_initialstate.c index af7e881013879cc0bc18e0f33ef815cb1d68d8f1..12fead20ae3e20483ffbc4dcfb107ee81dbe67e4 100644 --- a/arch/avr/src/avr/up_initialstate.c +++ b/arch/avr/src/avr/up_initialstate.c @@ -2,7 +2,7 @@ * arch/avr/src/avr/up_initialstate.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/up_irq.c b/arch/avr/src/avr/up_irq.c index 1e0072427bd0d258752d90f2dac685121fa99758..6362fe66a75d0dee101911debfd9820157163d59 100644 --- a/arch/avr/src/avr/up_irq.c +++ b/arch/avr/src/avr/up_irq.c @@ -2,7 +2,7 @@ * arch/avr/src/avr/up_irq.c * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/up_releasepending.c b/arch/avr/src/avr/up_releasepending.c index bd35379440af03057b7b5250b5f526e2eb9912d4..5684dcf5502e48ede0e2abd44453ef93a31cc134 100755 --- a/arch/avr/src/avr/up_releasepending.c +++ b/arch/avr/src/avr/up_releasepending.c @@ -2,7 +2,7 @@ * arch/avr/src/avr/up_releasepending.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/up_reprioritizertr.c b/arch/avr/src/avr/up_reprioritizertr.c index 3983b3953ad1bc43db5416d9dfffab6b2d4724a5..14033a3bde56f679af843b64ffad159f84b3cf64 100755 --- a/arch/avr/src/avr/up_reprioritizertr.c +++ b/arch/avr/src/avr/up_reprioritizertr.c @@ -2,7 +2,7 @@ * arch/avr/src/avr/up_reprioritizertr.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/up_romgetc.c b/arch/avr/src/avr/up_romgetc.c index 7d46b17929ce81aeb3b188331b9e19ac85cdce79..db2fa55c286fd87c55173244edb38c79cb6fd6a6 100644 --- a/arch/avr/src/avr/up_romgetc.c +++ b/arch/avr/src/avr/up_romgetc.c @@ -2,7 +2,7 @@ * arch/avr/src/avr/up_romgetc.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/up_schedulesigaction.c b/arch/avr/src/avr/up_schedulesigaction.c index ba56234d1cd4c0ab252e7d7d216e028fc38f371b..a70158a0deb04dca251a922f556a1cccf0d75e54 100644 --- a/arch/avr/src/avr/up_schedulesigaction.c +++ b/arch/avr/src/avr/up_schedulesigaction.c @@ -2,7 +2,7 @@ * arch/avr/src/avr/up_schedulesigaction.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/up_sigdeliver.c b/arch/avr/src/avr/up_sigdeliver.c index bef2834140811dceee42976bd0b5d455bee4fa04..4398dba6b2bef708d7126d0128a7414cee5bb506 100644 --- a/arch/avr/src/avr/up_sigdeliver.c +++ b/arch/avr/src/avr/up_sigdeliver.c @@ -2,7 +2,7 @@ * arch/avr/src/avr/up_sigdeliver.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/up_spi.c b/arch/avr/src/avr/up_spi.c index 7a38d5c9729e81ad78560541dc170479c8d0b561..c490eb02b09aa3833f628d7273a44382a9962600 100644 --- a/arch/avr/src/avr/up_spi.c +++ b/arch/avr/src/avr/up_spi.c @@ -2,7 +2,7 @@ * arch/arm/src/avr/up_spi.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/up_switchcontext.S b/arch/avr/src/avr/up_switchcontext.S index 3e451f4092eb281ff7a2d265775081a7d15ebd5c..62532081f1a93897805fde2f1791102c7a38fa92 100755 --- a/arch/avr/src/avr/up_switchcontext.S +++ b/arch/avr/src/avr/up_switchcontext.S @@ -2,7 +2,7 @@ * arch/avr/src/avr/up_switchcontext.S * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/up_unblocktask.c b/arch/avr/src/avr/up_unblocktask.c index a55b81e2c78407c1d4ea7cda99704c9261ae0a22..0eff2edcd88653478151ec73dd78531bbb7f9b71 100755 --- a/arch/avr/src/avr/up_unblocktask.c +++ b/arch/avr/src/avr/up_unblocktask.c @@ -2,7 +2,7 @@ * arch/avr/src/avr/up_unblocktask.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr/up_usestack.c b/arch/avr/src/avr/up_usestack.c index 0c86b64ee6a626f6999b948e8ff729bf02dc8279..cedc9afe3168efd5058a2d595c2658a8290bdc20 100644 --- a/arch/avr/src/avr/up_usestack.c +++ b/arch/avr/src/avr/up_usestack.c @@ -2,7 +2,7 @@ * arch/avr/src/avr/up_usestack.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr32/avr32_internal.h b/arch/avr/src/avr32/avr32_internal.h index 332b0918e635e662466ce866afb79e0079914061..680e2c804f7fc4c802fc4446f1dff088b91d658c 100644 --- a/arch/avr/src/avr32/avr32_internal.h +++ b/arch/avr/src/avr32/avr32_internal.h @@ -2,7 +2,7 @@ * arch/avr/src/avr32/up_internal.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr32/up_blocktask.c b/arch/avr/src/avr32/up_blocktask.c index 5897825caadfb693fc7bffdaa721ad0b368dfc1d..5d05350e6849c6395c65310016ff5fb50e50a658 100755 --- a/arch/avr/src/avr32/up_blocktask.c +++ b/arch/avr/src/avr32/up_blocktask.c @@ -2,7 +2,7 @@ * arch/avr/src/avr32/up_blocktask.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr32/up_copystate.c b/arch/avr/src/avr32/up_copystate.c index 67640f8ccec556007d12c3f5c86ede0677222cc2..fa69f8cdd50ffaa486697f5d16c00dffa238323b 100644 --- a/arch/avr/src/avr32/up_copystate.c +++ b/arch/avr/src/avr32/up_copystate.c @@ -2,7 +2,7 @@ * arch/avr/src/avr32/up_copystate.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr32/up_createstack.c b/arch/avr/src/avr32/up_createstack.c index cd72a66ac339e2d1db34643f5f8477c974c09b1e..2d34a9adfefb364d71819b2457aff4156b53e167 100644 --- a/arch/avr/src/avr32/up_createstack.c +++ b/arch/avr/src/avr32/up_createstack.c @@ -2,7 +2,7 @@ * arch/avr/src/avr32/up_createstack.c * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr32/up_doirq.c b/arch/avr/src/avr32/up_doirq.c index 061583393d164047241e63407a111053a7f275ed..7ade35fadcdbdf2ef52216fb75ead377c69e79af 100644 --- a/arch/avr/src/avr32/up_doirq.c +++ b/arch/avr/src/avr32/up_doirq.c @@ -2,7 +2,7 @@ * arch/avr/src/avr32/up_doirq.c * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr32/up_dumpstate.c b/arch/avr/src/avr32/up_dumpstate.c index 71e35eea69e3e4a4e8ba9f064e807ff63273cbd0..15a3e7ef871d47f98a0e5615f77fcc99af12706a 100644 --- a/arch/avr/src/avr32/up_dumpstate.c +++ b/arch/avr/src/avr32/up_dumpstate.c @@ -2,7 +2,7 @@ * arch/avr/src/avr32/up_dumpstate.c * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr32/up_exceptions.S b/arch/avr/src/avr32/up_exceptions.S index 448a93d7674ac2f08e5c80e96d1365559d401e2f..53a5b9c4fbd00fe300f64016f2d35f924df59e5f 100755 --- a/arch/avr/src/avr32/up_exceptions.S +++ b/arch/avr/src/avr32/up_exceptions.S @@ -2,7 +2,7 @@ * arch/avr/src/avr32/up_exceptions.S * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr32/up_fullcontextrestore.S b/arch/avr/src/avr32/up_fullcontextrestore.S index 466303abb2a1be2e2fe4a0e7fbed1a123c087346..8b0910998347d03e07e228a86879143577ddf3c5 100755 --- a/arch/avr/src/avr32/up_fullcontextrestore.S +++ b/arch/avr/src/avr32/up_fullcontextrestore.S @@ -2,7 +2,7 @@ * arch/avr32/src/avr32/up_fullcontextrestore.S * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr32/up_initialstate.c b/arch/avr/src/avr32/up_initialstate.c index 38fe40d677dced567b0bb27ed75ced5b1a67e945..fe3a79d90ba807bb6ae9d49d75ce311fcb9d3e36 100644 --- a/arch/avr/src/avr32/up_initialstate.c +++ b/arch/avr/src/avr32/up_initialstate.c @@ -2,7 +2,7 @@ * arch/avr/src/avr32/up_initialstate.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr32/up_nommuhead.S b/arch/avr/src/avr32/up_nommuhead.S index 3f4321df09c74316af6b46c1c73e46cf5b88718a..316e68aaff4fa83cf630d48c25cb5f312dfd5c5f 100644 --- a/arch/avr/src/avr32/up_nommuhead.S +++ b/arch/avr/src/avr32/up_nommuhead.S @@ -2,7 +2,7 @@ * arch/avr32/src/avr32/up_nommuhead.S * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr32/up_releasepending.c b/arch/avr/src/avr32/up_releasepending.c index cf8ac55907f03c13c5dc197f698c6f1992eeb67c..3cf29e623b042b27367880e44939c9b4762fc468 100755 --- a/arch/avr/src/avr32/up_releasepending.c +++ b/arch/avr/src/avr32/up_releasepending.c @@ -2,7 +2,7 @@ * arch/avr/src/avr32/up_releasepending.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr32/up_reprioritizertr.c b/arch/avr/src/avr32/up_reprioritizertr.c index 967ea025aa3e240e6c63d48086470abfdae00b6d..e1712fed09eb1ef94afca3a75a3dad01fd8b91d7 100755 --- a/arch/avr/src/avr32/up_reprioritizertr.c +++ b/arch/avr/src/avr32/up_reprioritizertr.c @@ -2,7 +2,7 @@ * arch/avr/src/avr32/up_reprioritizertr.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr32/up_schedulesigaction.c b/arch/avr/src/avr32/up_schedulesigaction.c index d56bb1e5126901e00196be71be9e5b590295a2b0..edf145a17c103ca1ea250ddc932ca61e6f272935 100644 --- a/arch/avr/src/avr32/up_schedulesigaction.c +++ b/arch/avr/src/avr32/up_schedulesigaction.c @@ -2,7 +2,7 @@ * arch/avr/src/avr32/up_schedulesigaction.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr32/up_sigdeliver.c b/arch/avr/src/avr32/up_sigdeliver.c index c8866948290154fe522723dbe8a9325012c9f6c0..8c1c0b705d94aef9834cf25cc44e572aa112932b 100644 --- a/arch/avr/src/avr32/up_sigdeliver.c +++ b/arch/avr/src/avr32/up_sigdeliver.c @@ -2,7 +2,7 @@ * arch/avr/src/avr32/up_sigdeliver.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr32/up_switchcontext.S b/arch/avr/src/avr32/up_switchcontext.S index 5cddc17a14952f0a38ce08d50ff3d0138b80fa0b..91b6a98bae53f895a61912943acef9bc8d5cce53 100755 --- a/arch/avr/src/avr32/up_switchcontext.S +++ b/arch/avr/src/avr32/up_switchcontext.S @@ -2,7 +2,7 @@ * arch/avr/src/avr32/up_switchcontext.S * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr32/up_syscall6.S b/arch/avr/src/avr32/up_syscall6.S index 143980e62ccae549776008010c70aaa821adb099..78e518dd75c6dbe019a7a1c634b34b24559d54ad 100755 --- a/arch/avr/src/avr32/up_syscall6.S +++ b/arch/avr/src/avr32/up_syscall6.S @@ -2,7 +2,7 @@ * arch/avr/src/avr32/up_syscall6.S * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Based on Bran's kernel development tutorials. Rewritten for JamesM's * kernel development tutorials. diff --git a/arch/avr/src/avr32/up_unblocktask.c b/arch/avr/src/avr32/up_unblocktask.c index 43b6e583089d9d4db1aad4ef2c889c397d27e349..da6b31f83351c7efb7e94bd1e517087182b47da3 100755 --- a/arch/avr/src/avr32/up_unblocktask.c +++ b/arch/avr/src/avr32/up_unblocktask.c @@ -2,7 +2,7 @@ * arch/avr/src/avr32/up_unblocktask.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/avr32/up_usestack.c b/arch/avr/src/avr32/up_usestack.c index 2161ec6dd098b0d32322b91fd066a8c8ddc4ce20..e73de3fb06b224334248b335309d7428d11976b0 100644 --- a/arch/avr/src/avr32/up_usestack.c +++ b/arch/avr/src/avr32/up_usestack.c @@ -2,7 +2,7 @@ * arch/avr/src/avr32/up_usestack.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/common/up_allocateheap.c b/arch/avr/src/common/up_allocateheap.c index 675352d5e75154306d5401c6779936bc3ce07658..b4a7cde0247921c16c034becb81c2d5c37c28546 100644 --- a/arch/avr/src/common/up_allocateheap.c +++ b/arch/avr/src/common/up_allocateheap.c @@ -2,7 +2,7 @@ * arch/avr/src/common/up_allocateheap.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/common/up_arch.h b/arch/avr/src/common/up_arch.h index 16a303c5a9c04576067709001d6ee4cbcf2c78e0..f02c14fb11152e3ddf385d8ef5a6ccf60638cb3b 100644 --- a/arch/avr/src/common/up_arch.h +++ b/arch/avr/src/common/up_arch.h @@ -2,7 +2,7 @@ * arch/avr/src/common/up_arch.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/common/up_assert.c b/arch/avr/src/common/up_assert.c index a0ba2355e2efb273a5ce49274d45a5b1cd4ec525..82c58d658731c4198d44086b1289f8b626410c5c 100644 --- a/arch/avr/src/common/up_assert.c +++ b/arch/avr/src/common/up_assert.c @@ -2,7 +2,7 @@ * arch/avr/src/common/up_assert.c * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/common/up_exit.c b/arch/avr/src/common/up_exit.c index 1c41b7496c6433109c4b7d76757c0f5e1ba1798c..0a8cc0d18269be0bb9bb6870c95ceb6f8df9c486 100644 --- a/arch/avr/src/common/up_exit.c +++ b/arch/avr/src/common/up_exit.c @@ -2,7 +2,7 @@ * arch/avr/src/common/up_exit.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/common/up_idle.c b/arch/avr/src/common/up_idle.c index 2854956cd1a2ccd390766264842c405180982551..7221a36e75f824d0e2824c2c551516970d09fb54 100644 --- a/arch/avr/src/common/up_idle.c +++ b/arch/avr/src/common/up_idle.c @@ -2,7 +2,7 @@ * arch/avr/src/common/up_idle.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/common/up_internal.h b/arch/avr/src/common/up_internal.h index e65b5627d9463b5d1111ccf0ea70ab435805efe8..fce3bc6faa65a95cfb8c8f44922e1b7be1a9436e 100644 --- a/arch/avr/src/common/up_internal.h +++ b/arch/avr/src/common/up_internal.h @@ -2,7 +2,7 @@ * arch/avr/src/common/up_internal.h * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/common/up_interruptcontext.c b/arch/avr/src/common/up_interruptcontext.c index c1bfb0e4dc5c3fded92e1011d14a889b2b43d65a..4930e56eacc7a93f069c93f70523389432ab68c7 100644 --- a/arch/avr/src/common/up_interruptcontext.c +++ b/arch/avr/src/common/up_interruptcontext.c @@ -2,7 +2,7 @@ * arch/avr/src/common/up_interruptcontext.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/common/up_lowputs.c b/arch/avr/src/common/up_lowputs.c index 5695b806a2396f462aa1af6a8dcb487095135251..5e57ac726285c2de7ce383cbf94284f3b1a739bf 100644 --- a/arch/avr/src/common/up_lowputs.c +++ b/arch/avr/src/common/up_lowputs.c @@ -2,7 +2,7 @@ * arch/avr/src/common/up_lowputs.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/common/up_mdelay.c b/arch/avr/src/common/up_mdelay.c index 171835f39bfb551ac9cc1e5925d3b35c771649f7..02fcf4c2773b9e36e9c44225ad118a9950237152 100644 --- a/arch/avr/src/common/up_mdelay.c +++ b/arch/avr/src/common/up_mdelay.c @@ -2,7 +2,7 @@ * arch/avr/src/common/up_mdelay.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/common/up_modifyreg16.c b/arch/avr/src/common/up_modifyreg16.c index e06f91f960821462b90889745bb22383080e2a9b..1bca1410e4d322822b1d7ae6fba5c8e5ac817e20 100644 --- a/arch/avr/src/common/up_modifyreg16.c +++ b/arch/avr/src/common/up_modifyreg16.c @@ -2,7 +2,7 @@ * arch/avr/src/common/up_modifyreg16.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/common/up_modifyreg32.c b/arch/avr/src/common/up_modifyreg32.c index 3369abb56643e26b3111b36595cb581a12a9be91..40aaaad09f7755faeb390b8ae3049ef7e99d7ce8 100644 --- a/arch/avr/src/common/up_modifyreg32.c +++ b/arch/avr/src/common/up_modifyreg32.c @@ -2,7 +2,7 @@ * arch/avr/src/common/up_modifyreg32.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/common/up_modifyreg8.c b/arch/avr/src/common/up_modifyreg8.c index 35537a4abbe3a3c4610b5ab98c4210e3074e927b..227bd7904a225eaba9ad36d7a1fbbb13666d598c 100644 --- a/arch/avr/src/common/up_modifyreg8.c +++ b/arch/avr/src/common/up_modifyreg8.c @@ -2,7 +2,7 @@ * arch/avr/src/common/up_modifyreg8.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/common/up_puts.c b/arch/avr/src/common/up_puts.c index aa651e2940d6e647bc9841f553cc11682f9fbdc0..c7cde66a26eece402203375d08bf2d84a39bc5a0 100644 --- a/arch/avr/src/common/up_puts.c +++ b/arch/avr/src/common/up_puts.c @@ -2,7 +2,7 @@ * arch/avr/src/common/up_puts.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/common/up_releasestack.c b/arch/avr/src/common/up_releasestack.c index 4c453c590e2c4876ab7f2e433f41e7e52e61b730..2cf3c30e86202dce27ba1ec65cb35b5bb7abac19 100644 --- a/arch/avr/src/common/up_releasestack.c +++ b/arch/avr/src/common/up_releasestack.c @@ -2,7 +2,7 @@ * arch/avr/src/common/up_releasestack.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/avr/src/common/up_udelay.c b/arch/avr/src/common/up_udelay.c index 5bbeed907520b593b258465bfd2fa87aff74f65b..6dd8809cc8124473aa029ca4670151cdffcc842b 100644 --- a/arch/avr/src/common/up_udelay.c +++ b/arch/avr/src/common/up_udelay.c @@ -2,7 +2,7 @@ * arch/avr/src/common/up_udelay.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/include/arch.h b/arch/hc/include/arch.h index 980d5517a86941f040a7162d3e21874536c0deed..840c8b292a99a1b00f77548786d652aefa0600d3 100755 --- a/arch/hc/include/arch.h +++ b/arch/hc/include/arch.h @@ -2,7 +2,7 @@ * arch/hc/include/arch.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/include/hc12/irq.h b/arch/hc/include/hc12/irq.h index 8754dc5d8ae6c7105395534b827134e144306670..ad9ffc4bcaf4c9ad42029ec6ee5aaaed312c76b9 100755 --- a/arch/hc/include/hc12/irq.h +++ b/arch/hc/include/hc12/irq.h @@ -2,7 +2,7 @@ * arch/hc/include/hc12/irq.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/include/hc12/types.h b/arch/hc/include/hc12/types.h index d676e3d27a9a9cad686e2fff2eea71ebe65cf62d..11bcf2ee52f625c3a82967d672c42a30e7d089b4 100755 --- a/arch/hc/include/hc12/types.h +++ b/arch/hc/include/hc12/types.h @@ -2,7 +2,7 @@ * arch/hc/include/hc12/types.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/include/hcs12/irq.h b/arch/hc/include/hcs12/irq.h index d6162b82e239e27e4c883e7293a2481a26b41d13..d8054bbff8432e8f2815e37dc045f1c1137c0684 100755 --- a/arch/hc/include/hcs12/irq.h +++ b/arch/hc/include/hcs12/irq.h @@ -2,7 +2,7 @@ * arch/hc/include/hcs12/irq.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/include/hcs12/types.h b/arch/hc/include/hcs12/types.h index 739ddef2157e775d2970fceab2f9decd79a73226..47c266b862d35d813b90ef4b06957a46d9f7bacb 100755 --- a/arch/hc/include/hcs12/types.h +++ b/arch/hc/include/hcs12/types.h @@ -2,7 +2,7 @@ * arch/hc/include/hcs12/types.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/include/irq.h b/arch/hc/include/irq.h index fbf7a624e60f9b14ef038bf7fa5c5d73f2d655cc..ef15ccbf93a04eb124b2a503cc329796c12da8eb 100755 --- a/arch/hc/include/irq.h +++ b/arch/hc/include/irq.h @@ -2,7 +2,7 @@ * arch/hc/include/irq.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/include/limits.h b/arch/hc/include/limits.h index 5a2c9791e80c1557e047e4c83815dd6653e0948f..47ffd2c7dade14ccb74192cf70f7438976515bd8 100755 --- a/arch/hc/include/limits.h +++ b/arch/hc/include/limits.h @@ -2,7 +2,7 @@ * arch/hc/include/limits.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/include/m9s12/irq.h b/arch/hc/include/m9s12/irq.h index 30bed2d4c8f1444663e13ea2d27239b27654f500..dd4345558d8efeabf90f692ad42230f9b5e7097a 100755 --- a/arch/hc/include/m9s12/irq.h +++ b/arch/hc/include/m9s12/irq.h @@ -2,7 +2,7 @@ * arch/hc/include/m9s12/irq.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/include/syscall.h b/arch/hc/include/syscall.h index ff71179466879b847e098177f7e94d80267c1d5e..37f6f8e990f73857473c87cc0ad45664840e98f3 100644 --- a/arch/hc/include/syscall.h +++ b/arch/hc/include/syscall.h @@ -2,7 +2,7 @@ * arch/hc/include/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/include/types.h b/arch/hc/include/types.h index 5cba37a9f07cd4b19265e8b94b283b0c63849409..a70d6df7b6d0a33e44771cd84a9491ef2d7b3f09 100755 --- a/arch/hc/include/types.h +++ b/arch/hc/include/types.h @@ -2,7 +2,7 @@ * arch/hc/include/types.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_allocateheap.c b/arch/hc/src/common/up_allocateheap.c index 174e61564ea9ed88d369a69d0edcbd9b779b3828..fc86faca5d9a0b2a76f7e8ebae4805723fefa1c3 100755 --- a/arch/hc/src/common/up_allocateheap.c +++ b/arch/hc/src/common/up_allocateheap.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_allocateheap.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_arch.h b/arch/hc/src/common/up_arch.h index 01fa74b283453d66801407f4c42dc5c4afa0b4d6..a9a768553ab238fed7f66d2eb6a521871d3ba562 100755 --- a/arch/hc/src/common/up_arch.h +++ b/arch/hc/src/common/up_arch.h @@ -2,7 +2,7 @@ * arch/hc/src/common/up_arch.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_blocktask.c b/arch/hc/src/common/up_blocktask.c index 3bb0d1d32584ec6063e8e1db861b915fcf616bd8..4e5bf1826ba08ab789d2d49f898d7f4660675082 100755 --- a/arch/hc/src/common/up_blocktask.c +++ b/arch/hc/src/common/up_blocktask.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_blocktask.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_copystate.c b/arch/hc/src/common/up_copystate.c index 0858872dff8a9e369c7ef48a0007fc510e0aae20..ed3fe331d5f0a01469e6456c82ed5df05e6bded4 100644 --- a/arch/hc/src/common/up_copystate.c +++ b/arch/hc/src/common/up_copystate.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_copystate.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_createstack.c b/arch/hc/src/common/up_createstack.c index 6e2240ef92f61bda5e20dc3a30bebe8ea3b56ea1..ef0a9df9c359de1d41e2109fca77c6da8bbd2fa9 100755 --- a/arch/hc/src/common/up_createstack.c +++ b/arch/hc/src/common/up_createstack.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_createstack.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_doirq.c b/arch/hc/src/common/up_doirq.c index 4fc52224ef52abd1b5bcdd88f2a70196bc7f72b2..d03b007df1cf79cc49def37a63b5140fa13c863c 100644 --- a/arch/hc/src/common/up_doirq.c +++ b/arch/hc/src/common/up_doirq.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_doirq.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_exit.c b/arch/hc/src/common/up_exit.c index 5b85ffe68ea646dc1b921a9c0404047d9984ea69..7cd16b4383fcb37bc32d8777b5a0ea84c5985b45 100644 --- a/arch/hc/src/common/up_exit.c +++ b/arch/hc/src/common/up_exit.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_exit.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_idle.c b/arch/hc/src/common/up_idle.c index ec00a8da62d7bcec2a3f815c17be8c1b8868df39..701523609bcf53728c9b53c3044c8fb917cb7cdb 100755 --- a/arch/hc/src/common/up_idle.c +++ b/arch/hc/src/common/up_idle.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_idle.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_interruptcontext.c b/arch/hc/src/common/up_interruptcontext.c index 82caae044453af00770c64b18aed95e9c61350b8..87c5053287114c29fdd64e15d58198a4ff702797 100755 --- a/arch/hc/src/common/up_interruptcontext.c +++ b/arch/hc/src/common/up_interruptcontext.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_interruptcontext.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_mdelay.c b/arch/hc/src/common/up_mdelay.c index aa6d8776caca20ca1e2d8ae2759a39a6794f916e..c5b9e095b0337063859528a459bcb26edfc64496 100755 --- a/arch/hc/src/common/up_mdelay.c +++ b/arch/hc/src/common/up_mdelay.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_mdelay.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_modifyreg16.c b/arch/hc/src/common/up_modifyreg16.c index c5ca0f86c039f5b97762e2ae5d60c74b46caca3f..15692ae6950cd2d9bb14a3b94b688d399c37ffe1 100755 --- a/arch/hc/src/common/up_modifyreg16.c +++ b/arch/hc/src/common/up_modifyreg16.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_modifyreg16.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_modifyreg32.c b/arch/hc/src/common/up_modifyreg32.c index ba68fc723c1c2fa64d1756618a4221affc67ffa2..724a020cd13de0e34868c8ddd1fb6b8d94c55114 100755 --- a/arch/hc/src/common/up_modifyreg32.c +++ b/arch/hc/src/common/up_modifyreg32.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_modifyreg32.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_modifyreg8.c b/arch/hc/src/common/up_modifyreg8.c index 063c0921b82b60011e375f42de3015e4aeed6744..32fc768b66ab96f9d85e47cacc17c362cde4ed40 100755 --- a/arch/hc/src/common/up_modifyreg8.c +++ b/arch/hc/src/common/up_modifyreg8.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_modifyreg8.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_puts.c b/arch/hc/src/common/up_puts.c index 7681b7483780e658ae0517b72b58f77cb8fdf068..68ad386708a54083835cebeaf8889519e4aebc12 100755 --- a/arch/hc/src/common/up_puts.c +++ b/arch/hc/src/common/up_puts.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_puts.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_releasepending.c b/arch/hc/src/common/up_releasepending.c index 222aa717efc540665c3495385a85f9fb88e2ac60..0c09cb0c6cda9b3c9584a07a84bace165be4c089 100755 --- a/arch/hc/src/common/up_releasepending.c +++ b/arch/hc/src/common/up_releasepending.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_releasepending.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_releasestack.c b/arch/hc/src/common/up_releasestack.c index bcb3761cc09947449234afb09639ace4180c373e..d3d917fc364cb36042aea0dc22e188041948ba8e 100755 --- a/arch/hc/src/common/up_releasestack.c +++ b/arch/hc/src/common/up_releasestack.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_releasestack.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_reprioritizertr.c b/arch/hc/src/common/up_reprioritizertr.c index e17a488673d18d782b1c8f981d6d67c5a3413ef2..ffd90bf1f28095a594f03162f6e261fb800c608d 100755 --- a/arch/hc/src/common/up_reprioritizertr.c +++ b/arch/hc/src/common/up_reprioritizertr.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_reprioritizertr.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_udelay.c b/arch/hc/src/common/up_udelay.c index 812390f874e7cf283221da230203d98056d71950..72a6b80a314d220c76fe37fac2503b1243fb4bf8 100755 --- a/arch/hc/src/common/up_udelay.c +++ b/arch/hc/src/common/up_udelay.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_udelay.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_unblocktask.c b/arch/hc/src/common/up_unblocktask.c index 0883a1661808687fa140787ef474c304abfca017..9518da774bc673aef2bc865fdddd6fd778ba1685 100755 --- a/arch/hc/src/common/up_unblocktask.c +++ b/arch/hc/src/common/up_unblocktask.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_unblocktask.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/common/up_usestack.c b/arch/hc/src/common/up_usestack.c index f5b5798f04f90f5c6bd30a775363d21da4a63432..b0349b21b30a40fca4e60c715e3e6a29dbf09204 100755 --- a/arch/hc/src/common/up_usestack.c +++ b/arch/hc/src/common/up_usestack.c @@ -2,7 +2,7 @@ * arch/hc/src/common/up_usestack.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/Make.defs b/arch/hc/src/m9s12/Make.defs index f3ef80795dbdebb7dd16a963ee8d5279873dac86..0f70c42ab58dec906e444603693cdf094c1897c6 100755 --- a/arch/hc/src/m9s12/Make.defs +++ b/arch/hc/src/m9s12/Make.defs @@ -2,7 +2,7 @@ # arch/arm/src/m9s12/Make.defs # # Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/chip.h b/arch/hc/src/m9s12/chip.h index 422d6978cbbb48e0c0b053f0389296e4fc743fc8..b9ba652710be3062be05b6d152ccf895c9b2ba19 100755 --- a/arch/hc/src/m9s12/chip.h +++ b/arch/hc/src/m9s12/chip.h @@ -2,7 +2,7 @@ * arch/hc/src/m9s12/chip.h * * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_assert.c b/arch/hc/src/m9s12/m9s12_assert.c index 97d18b64f6d9b9eede85d458f4550ff9c348c9de..386bcb2dfc284252cf656f0d8e34aaf246895ab7 100644 --- a/arch/hc/src/m9s12/m9s12_assert.c +++ b/arch/hc/src/m9s12/m9s12_assert.c @@ -2,7 +2,7 @@ * arch/hc/src/m9s12/m9s12_assert.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_atd.h b/arch/hc/src/m9s12/m9s12_atd.h index e79f028ae14f6041520ad0f208f731d97c540777..437574181025cfa0151b8133fb6224a8e5580736 100755 --- a/arch/hc/src/m9s12/m9s12_atd.h +++ b/arch/hc/src/m9s12/m9s12_atd.h @@ -3,7 +3,7 @@ * Defintions for ATD10b8c v3 * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_crg.h b/arch/hc/src/m9s12/m9s12_crg.h index 0c71cee5a957164ed575e2d45669e3703a6f17a0..0231d838bf7d1003b9ecdc06e0865f8bbdcc4e37 100755 --- a/arch/hc/src/m9s12/m9s12_crg.h +++ b/arch/hc/src/m9s12/m9s12_crg.h @@ -1,140 +1,140 @@ -/************************************************************************************ - * arch/hc/src/m9s12/m9s12_crg.h - * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_HC_SRC_M9S12_M9S12_CRG_H -#define __ARCH_ARM_HC_SRC_M9S12_M9S12_CRG_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include "chip.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* CRG Module Register Offsets */ - -#define HCS12_CRG_SYNR_OFFSET (HCS12_CRG_BASE+0x00) /* CRG Synthesizer Register */ -#define HCS12_CRG_REFDV_OFFSET (HCS12_CRG_BASE+0x01) /* CRG Reference Divider Register */ -#define HCS12_CRG_CTFLG_OFFSET (HCS12_CRG_BASE+0x02) /* CRG Test Flags Register */ -#define HCS12_CRG_CRGFLG_OFFSET (HCS12_CRG_BASE+0x03) /* CRG Flags Register */ -#define HCS12_CRG_CRGINT_OFFSET (HCS12_CRG_BASE+0x04) /* CRG Interrupt Enable Register */ -#define HCS12_CRG_CLKSEL_OFFSET (HCS12_CRG_BASE+0x05) /* CRG Clock Select Register */ -#define HCS12_CRG_PLLCTL_OFFSET (HCS12_CRG_BASE+0x06) /* CRG PLL Control Register */ -#define HCS12_CRG_RTICTL_OFFSET (HCS12_CRG_BASE+0x07) /* CRG RTI Control Register */ -#define HCS12_CRG_COPCTL_OFFSET (HCS12_CRG_BASE+0x08) /* CRG COP Control Register */ -#define HCS12_CRG_FORBYP_OFFSET (HCS12_CRG_BASE+0x09) /* CRG Force and Bypass Test Register */ -#define HCS12_CRG_CTCTL_OFFSET (HCS12_CRG_BASE+0x0a) /* CRG Test Control Register */ -#define HCS12_CRG_ARMCOP_OFFSET (HCS12_CRG_BASE+0x0b) /* CRG COP Arm/Timer Reset */ - -/* CRG Module Register Addresses */ - -#define HCS12_CRG_SYNR (HCS12_REG_BASE+HCS12_CRG_SYNR_OFFSET) -#define HCS12_CRG_REFDV (HCS12_REG_BASE+HCS12_CRG_REFDV_OFFSET) -#define HCS12_CRG_CTFLG (HCS12_REG_BASE+HCS12_CRG_CTFLG_OFFSET) -#define HCS12_CRG_CRGFLG (HCS12_REG_BASE+HCS12_CRG_CRGFLG_OFFSET) -#define HCS12_CRG_CRGINT (HCS12_REG_BASE+HCS12_CRG_CRGINT_OFFSET) -#define HCS12_CRG_CLKSEL (HCS12_REG_BASE+HCS12_CRG_CLKSEL_OFFSET) -#define HCS12_CRG_PLLCTL (HCS12_REG_BASE+HCS12_CRG_PLLCTL_OFFSET) -#define HCS12_CRG_RTICTL (HCS12_REG_BASE+HCS12_CRG_RTICTL_OFFSET) -#define HCS12_CRG_COPCTL (HCS12_REG_BASE+HCS12_CRG_COPCTL_OFFSET) -#define HCS12_CRG_FORBYP (HCS12_REG_BASE+HCS12_CRG_FORBYP_OFFSET) -#define HCS12_CRG_CTCTL (HCS12_REG_BASE+HCS12_CRG_CTCTL_OFFSET) -#define HCS12_CRG_ARMCOP (HCS12_REG_BASE+HCS12_CRG_ARMCOP_OFFSET) - -/* CRG Module Register Bit Definitions */ - -#define CRG_SYNR_SHIFT (0) /* Bits 0-5: CRG synthesizer value */ -#define CRG_SYNR_MASK (0x3f << CRG_SYNR_SHIFT) - -#define CRG_REFDV_SHIFT (0) /* Bit 0-3: Reference divider */ -#define CRG_REFDV_MASK (15 << CRG_REFDV_SHIFT) - -#define CRG_CRGFLG_SCM (1 << 0) /* Bit 0: Self-Clock Mode Status Bit */ -#define CRG_CRGFLG_SCMIF (1 << 1) /* Bit 1: Self-Clock Mode Interrupt Flag */ -#define CRG_CRGFLG_TRACK (1 << 2) /* Bit 2: Track Status Bit */ -#define CRG_CRGFLG_LOCK (1 << 3) /* Bit 3: Lock Status Bit */ -#define CRG_CRGFLG_LOCKIF (1 << 4) /* Bit 4: PLL Lock Interrupt Flag */ -#define CRG_CRGFLG_LVRF (1 << 5) /* Bit 5: Low Voltage Reset Flag */ -#define CRG_CRGFLG_PORF (1 << 6) /* Bit 6: Power-on Reset Flag */ -#define CRG_CRGFLG_RTIF (1 << 7) /* Bit 7: Real-Time Interrupt Flag */ - -#define CRG_CRGINT_SCMIE (1 << 1) /* Bit 1: Self-Clock Mode Status Bit */ -#define CRG_CRGINT_LOCKIE (1 << 4) /* Bit 4: Lock Interrupt Enable Bit */ -#define CRG_CRGINT_RTIE (1 << 7) /* Bit 7: Lock Interrupt Enable Bit */ - -#define CRG_CLKSEL_COPWAI (1 << 0) /* Bit 0: COP stops in Wait Mode Bit */ -#define CRG_CLKSEL_RTIWAI (1 << 1) /* Bit 1: RTI stops in Wait Mode Bit */ -#define CRG_CLKSEL_CWAI (1 << 2) /* Bit 2: Core stops in Wait Mode Bit */ -#define CRG_CLKSEL_PLLWAI (1 << 3) /* Bit 3: PLL stops in Wait Mode Bit */ -#define CRG_CLKSEL_ROAWAI (1 << 4) /* Bit 4: Reduced Oscillator Amplitude in Wait Mode Bit */ -#define CRG_CLKSEL_SYSWAI (1 << 5) /* Bit 5: System clocks stop in wait mode bit */ -#define CRG_CLKSEL_PSTP (1 << 6) /* Bit 6: Pseudo-Stop Bit */ -#define CRG_CLKSEL_PLLSEL (1 << 7) /* Bit 7: PLL Select Bit */ - -#define CRG_PLLCTL_SCME (1 << 0) /* Bit 0: Self-Clock Mode Enable Bit */ -#define CRG_PLLCTL_PCE (1 << 1) /* Bit 1: COP Enable during Pseudo-Stop Bit */ -#define CRG_PLLCTL_PRE (1 << 2) /* Bit 2: RTI Enable during Pseudo-Stop Bit */ -#define CRG_PLLCTL_ACQ (1 << 4) /* Bit 4: Acquisition Bit */ -#define CRG_PLLCTL_AUTO (1 << 5) /* Bit 5: Automatic Bandwidth Control Bit */ -#define CRG_PLLCTL_PLLON (1 << 6) /* Bit 6: Phase Lock Loop On Bit */ -#define CRG_PLLCTL_CME (1 << 7) /* Bit 7: Clock Monitor Enable Bit */ - -#define CRG_RTICTL_MODCNT_SHIFT (0) /* Bits 0-3: Real-Time Interrupt Modulus Counter Select Bits */ -#define CRG_RTICTL_MODCNT_MASK (15 << CRG_RTICTL_MODCNT_SHIFT) -#define CRG_RTICTL_PRER_SHIFT (4) /* Bits 4-6: Real-Time Interrupt Prescale Rate Select Bits */ -#define CRG_RTICTL_PRER_MASK (7 << CRG_RTICTL_PRE_SHIFT) - -#define CRG_COPCTL_CR_SHIFT (0) /* Bits 0-2: COP Watchdog Timer Rate select */ -#define CRG_COPCTL_CR_MASK (7 << CRG_COPCTL_CR_SHIFT) -#define CRG_COPCTL_RSBCK (1 << 6) /* Bit 6: COP and RTI stop in Active BDM mode B */ -#define CRG_COPCTL_WCOP (1 << 7) /* Bit 7: Window COP Mode Bit */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_HC_SRC_M9S12_M9S12_CRG_H */ +/************************************************************************************ + * arch/hc/src/m9s12/m9s12_crg.h + * + * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_HC_SRC_M9S12_M9S12_CRG_H +#define __ARCH_ARM_HC_SRC_M9S12_M9S12_CRG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* CRG Module Register Offsets */ + +#define HCS12_CRG_SYNR_OFFSET (HCS12_CRG_BASE+0x00) /* CRG Synthesizer Register */ +#define HCS12_CRG_REFDV_OFFSET (HCS12_CRG_BASE+0x01) /* CRG Reference Divider Register */ +#define HCS12_CRG_CTFLG_OFFSET (HCS12_CRG_BASE+0x02) /* CRG Test Flags Register */ +#define HCS12_CRG_CRGFLG_OFFSET (HCS12_CRG_BASE+0x03) /* CRG Flags Register */ +#define HCS12_CRG_CRGINT_OFFSET (HCS12_CRG_BASE+0x04) /* CRG Interrupt Enable Register */ +#define HCS12_CRG_CLKSEL_OFFSET (HCS12_CRG_BASE+0x05) /* CRG Clock Select Register */ +#define HCS12_CRG_PLLCTL_OFFSET (HCS12_CRG_BASE+0x06) /* CRG PLL Control Register */ +#define HCS12_CRG_RTICTL_OFFSET (HCS12_CRG_BASE+0x07) /* CRG RTI Control Register */ +#define HCS12_CRG_COPCTL_OFFSET (HCS12_CRG_BASE+0x08) /* CRG COP Control Register */ +#define HCS12_CRG_FORBYP_OFFSET (HCS12_CRG_BASE+0x09) /* CRG Force and Bypass Test Register */ +#define HCS12_CRG_CTCTL_OFFSET (HCS12_CRG_BASE+0x0a) /* CRG Test Control Register */ +#define HCS12_CRG_ARMCOP_OFFSET (HCS12_CRG_BASE+0x0b) /* CRG COP Arm/Timer Reset */ + +/* CRG Module Register Addresses */ + +#define HCS12_CRG_SYNR (HCS12_REG_BASE+HCS12_CRG_SYNR_OFFSET) +#define HCS12_CRG_REFDV (HCS12_REG_BASE+HCS12_CRG_REFDV_OFFSET) +#define HCS12_CRG_CTFLG (HCS12_REG_BASE+HCS12_CRG_CTFLG_OFFSET) +#define HCS12_CRG_CRGFLG (HCS12_REG_BASE+HCS12_CRG_CRGFLG_OFFSET) +#define HCS12_CRG_CRGINT (HCS12_REG_BASE+HCS12_CRG_CRGINT_OFFSET) +#define HCS12_CRG_CLKSEL (HCS12_REG_BASE+HCS12_CRG_CLKSEL_OFFSET) +#define HCS12_CRG_PLLCTL (HCS12_REG_BASE+HCS12_CRG_PLLCTL_OFFSET) +#define HCS12_CRG_RTICTL (HCS12_REG_BASE+HCS12_CRG_RTICTL_OFFSET) +#define HCS12_CRG_COPCTL (HCS12_REG_BASE+HCS12_CRG_COPCTL_OFFSET) +#define HCS12_CRG_FORBYP (HCS12_REG_BASE+HCS12_CRG_FORBYP_OFFSET) +#define HCS12_CRG_CTCTL (HCS12_REG_BASE+HCS12_CRG_CTCTL_OFFSET) +#define HCS12_CRG_ARMCOP (HCS12_REG_BASE+HCS12_CRG_ARMCOP_OFFSET) + +/* CRG Module Register Bit Definitions */ + +#define CRG_SYNR_SHIFT (0) /* Bits 0-5: CRG synthesizer value */ +#define CRG_SYNR_MASK (0x3f << CRG_SYNR_SHIFT) + +#define CRG_REFDV_SHIFT (0) /* Bit 0-3: Reference divider */ +#define CRG_REFDV_MASK (15 << CRG_REFDV_SHIFT) + +#define CRG_CRGFLG_SCM (1 << 0) /* Bit 0: Self-Clock Mode Status Bit */ +#define CRG_CRGFLG_SCMIF (1 << 1) /* Bit 1: Self-Clock Mode Interrupt Flag */ +#define CRG_CRGFLG_TRACK (1 << 2) /* Bit 2: Track Status Bit */ +#define CRG_CRGFLG_LOCK (1 << 3) /* Bit 3: Lock Status Bit */ +#define CRG_CRGFLG_LOCKIF (1 << 4) /* Bit 4: PLL Lock Interrupt Flag */ +#define CRG_CRGFLG_LVRF (1 << 5) /* Bit 5: Low Voltage Reset Flag */ +#define CRG_CRGFLG_PORF (1 << 6) /* Bit 6: Power-on Reset Flag */ +#define CRG_CRGFLG_RTIF (1 << 7) /* Bit 7: Real-Time Interrupt Flag */ + +#define CRG_CRGINT_SCMIE (1 << 1) /* Bit 1: Self-Clock Mode Status Bit */ +#define CRG_CRGINT_LOCKIE (1 << 4) /* Bit 4: Lock Interrupt Enable Bit */ +#define CRG_CRGINT_RTIE (1 << 7) /* Bit 7: Lock Interrupt Enable Bit */ + +#define CRG_CLKSEL_COPWAI (1 << 0) /* Bit 0: COP stops in Wait Mode Bit */ +#define CRG_CLKSEL_RTIWAI (1 << 1) /* Bit 1: RTI stops in Wait Mode Bit */ +#define CRG_CLKSEL_CWAI (1 << 2) /* Bit 2: Core stops in Wait Mode Bit */ +#define CRG_CLKSEL_PLLWAI (1 << 3) /* Bit 3: PLL stops in Wait Mode Bit */ +#define CRG_CLKSEL_ROAWAI (1 << 4) /* Bit 4: Reduced Oscillator Amplitude in Wait Mode Bit */ +#define CRG_CLKSEL_SYSWAI (1 << 5) /* Bit 5: System clocks stop in wait mode bit */ +#define CRG_CLKSEL_PSTP (1 << 6) /* Bit 6: Pseudo-Stop Bit */ +#define CRG_CLKSEL_PLLSEL (1 << 7) /* Bit 7: PLL Select Bit */ + +#define CRG_PLLCTL_SCME (1 << 0) /* Bit 0: Self-Clock Mode Enable Bit */ +#define CRG_PLLCTL_PCE (1 << 1) /* Bit 1: COP Enable during Pseudo-Stop Bit */ +#define CRG_PLLCTL_PRE (1 << 2) /* Bit 2: RTI Enable during Pseudo-Stop Bit */ +#define CRG_PLLCTL_ACQ (1 << 4) /* Bit 4: Acquisition Bit */ +#define CRG_PLLCTL_AUTO (1 << 5) /* Bit 5: Automatic Bandwidth Control Bit */ +#define CRG_PLLCTL_PLLON (1 << 6) /* Bit 6: Phase Lock Loop On Bit */ +#define CRG_PLLCTL_CME (1 << 7) /* Bit 7: Clock Monitor Enable Bit */ + +#define CRG_RTICTL_MODCNT_SHIFT (0) /* Bits 0-3: Real-Time Interrupt Modulus Counter Select Bits */ +#define CRG_RTICTL_MODCNT_MASK (15 << CRG_RTICTL_MODCNT_SHIFT) +#define CRG_RTICTL_PRER_SHIFT (4) /* Bits 4-6: Real-Time Interrupt Prescale Rate Select Bits */ +#define CRG_RTICTL_PRER_MASK (7 << CRG_RTICTL_PRE_SHIFT) + +#define CRG_COPCTL_CR_SHIFT (0) /* Bits 0-2: COP Watchdog Timer Rate select */ +#define CRG_COPCTL_CR_MASK (7 << CRG_COPCTL_CR_SHIFT) +#define CRG_COPCTL_RSBCK (1 << 6) /* Bit 6: COP and RTI stop in Active BDM mode B */ +#define CRG_COPCTL_WCOP (1 << 7) /* Bit 7: Window COP Mode Bit */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_HC_SRC_M9S12_M9S12_CRG_H */ diff --git a/arch/hc/src/m9s12/m9s12_dumpgpio.c b/arch/hc/src/m9s12/m9s12_dumpgpio.c index 13a84dacf046d18745d064f48455153437693a74..c43d4439ef5c7188676a5bf0bbaa799b5105e8cb 100755 --- a/arch/hc/src/m9s12/m9s12_dumpgpio.c +++ b/arch/hc/src/m9s12/m9s12_dumpgpio.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/m9s12_dumpgpio.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_emac.h b/arch/hc/src/m9s12/m9s12_emac.h index b12f238b5de5f3aa9e1b4c0cc9d3f2ccb42d5309..0fd13f67d5be5048617855932da237b37a5665c6 100755 --- a/arch/hc/src/m9s12/m9s12_emac.h +++ b/arch/hc/src/m9s12/m9s12_emac.h @@ -2,7 +2,7 @@ * arch/hc/src/m9s12/m9s12_emac.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_ethernet.c b/arch/hc/src/m9s12/m9s12_ethernet.c index a2b890d22b99e18a01e85c0d186f796e55fb1067..ed2977e88915bf3c34edfe2ec634187348dcaa00 100644 --- a/arch/hc/src/m9s12/m9s12_ethernet.c +++ b/arch/hc/src/m9s12/m9s12_ethernet.c @@ -2,7 +2,7 @@ * drivers/net/m9s12_ethernet.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_flash.h b/arch/hc/src/m9s12/m9s12_flash.h index 8761c328f3bd9ccbecb4ef08bc00ee8e6239b345..697eee57a3764c451b03bed8a009e75b65d9b456 100755 --- a/arch/hc/src/m9s12/m9s12_flash.h +++ b/arch/hc/src/m9s12/m9s12_flash.h @@ -2,7 +2,7 @@ * arch/hc/src/m9s12/m9s12_flash.h * * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_gpio.c b/arch/hc/src/m9s12/m9s12_gpio.c index 0f866dc87eed972e1c87b4eb99345ac95321fc20..280202da544c9e8dd1f883d4a0092c7ed4fa5d06 100755 --- a/arch/hc/src/m9s12/m9s12_gpio.c +++ b/arch/hc/src/m9s12/m9s12_gpio.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/m9s12_gpio.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_gpioirq.c b/arch/hc/src/m9s12/m9s12_gpioirq.c index 6d31513d277203e6f49f2950a46498e4440180a6..017292a26ecd9126096dcb5b11c2dee8ecce78fa 100755 --- a/arch/hc/src/m9s12/m9s12_gpioirq.c +++ b/arch/hc/src/m9s12/m9s12_gpioirq.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/m9s12_gpioirq.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_iic.h b/arch/hc/src/m9s12/m9s12_iic.h index 5d26391a07099bf6ec725e186bb1dbe343def62c..f8d17014c39977c9bfbfe270cf9d8b8ccc6dca66 100755 --- a/arch/hc/src/m9s12/m9s12_iic.h +++ b/arch/hc/src/m9s12/m9s12_iic.h @@ -2,7 +2,7 @@ * arch/hc/src/m9s12/m9s12_iic.h (v2) * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_initialstate.c b/arch/hc/src/m9s12/m9s12_initialstate.c index c537546b1e31b74ba0d599489ae81e92a7018ef8..80bb5fe0356d51b5199fc702f8c74be886f942e7 100644 --- a/arch/hc/src/m9s12/m9s12_initialstate.c +++ b/arch/hc/src/m9s12/m9s12_initialstate.c @@ -2,7 +2,7 @@ * arch/hc/src/m9s12/m9s12_initialstate.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_int.h b/arch/hc/src/m9s12/m9s12_int.h index 1794e0b73d14acdc9cffdaf0e0ada8edea0e7aba..10e229aae61a89fc72bbe1af88b63fc52d9dba5f 100755 --- a/arch/hc/src/m9s12/m9s12_int.h +++ b/arch/hc/src/m9s12/m9s12_int.h @@ -2,7 +2,7 @@ * arch/hc/src/m9s12/m9s12_int.h (v1) * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_internal.h b/arch/hc/src/m9s12/m9s12_internal.h index e4aa1e36dc5fa602025815c55fff1ee060033106..140aa0e5e8d66b3e2b4f94bd10adf9355cc8ec51 100755 --- a/arch/hc/src/m9s12/m9s12_internal.h +++ b/arch/hc/src/m9s12/m9s12_internal.h @@ -2,7 +2,7 @@ * arch/hc/src/m9s12/m9s12_internal.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_irq.c b/arch/hc/src/m9s12/m9s12_irq.c index ab47589253749f4a9e11a666825b9e7c98551b89..56e357a2e1af6aa51fee487c9b24e1a129d6e959 100755 --- a/arch/hc/src/m9s12/m9s12_irq.c +++ b/arch/hc/src/m9s12/m9s12_irq.c @@ -3,7 +3,7 @@ * arch/arm/src/chip/m9s12_irq.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_lowputc.S b/arch/hc/src/m9s12/m9s12_lowputc.S index 0a6e761b7f62e97c4f3d34c1364880a0d5d787d0..0905c096076d2904a64911f2aeea0c37e5ffdbbd 100755 --- a/arch/hc/src/m9s12/m9s12_lowputc.S +++ b/arch/hc/src/m9s12/m9s12_lowputc.S @@ -2,7 +2,7 @@ * arch/arm/src/m9s12/m9s12_lowputc.S * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_mebi.h b/arch/hc/src/m9s12/m9s12_mebi.h index 7db814b651c9c79edce63b943fc05a6fa27e0c10..f7426a3e5116348ef377f9f990467f4bc6078f95 100755 --- a/arch/hc/src/m9s12/m9s12_mebi.h +++ b/arch/hc/src/m9s12/m9s12_mebi.h @@ -2,7 +2,7 @@ * arch/hc/src/m9s12/m9s12_mebi.h (v3) * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_mmc.h b/arch/hc/src/m9s12/m9s12_mmc.h index 2dadd5be863d7d1b3bb9e4d3be602c7e0a5bf81b..5d68a425a0ac6942c46af338354ec6f6fbaea41d 100755 --- a/arch/hc/src/m9s12/m9s12_mmc.h +++ b/arch/hc/src/m9s12/m9s12_mmc.h @@ -2,7 +2,7 @@ * arch/hc/src/m9s12/m9s12_mmcv4.h (v4) * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_phy.h b/arch/hc/src/m9s12/m9s12_phy.h index 635036b46497a9115bb17a85cd21d2733adc569a..23a06957b7e33a740cc48f3bd7b01924f3c913d3 100755 --- a/arch/hc/src/m9s12/m9s12_phy.h +++ b/arch/hc/src/m9s12/m9s12_phy.h @@ -2,7 +2,7 @@ * arch/hc/src/m9s12/m9s12_phyv2.h (v2) * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_pim.h b/arch/hc/src/m9s12/m9s12_pim.h index 68b702382f995bdb7805922f51874b8c30fc6d55..a76d9f58193ad8eb1f9d14d99493d05c3efd3131 100755 --- a/arch/hc/src/m9s12/m9s12_pim.h +++ b/arch/hc/src/m9s12/m9s12_pim.h @@ -2,7 +2,7 @@ * arch/hc/src/m9s12/m9s12_pim.h * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_saveusercontext.S b/arch/hc/src/m9s12/m9s12_saveusercontext.S index 749dd6383b9c22a82e2566bc0a8c5b0f7d15eb96..91fb0d9ef8a8faf5a70d1fb4959ea2f84fe45f0d 100755 --- a/arch/hc/src/m9s12/m9s12_saveusercontext.S +++ b/arch/hc/src/m9s12/m9s12_saveusercontext.S @@ -2,7 +2,7 @@ * arch/arm/src/m9s12/m9s12_saveusercontext.S * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_sci.h b/arch/hc/src/m9s12/m9s12_sci.h index c80c1fcfa76af7203c11385b1545249e77958f26..28747e890da7a9a05c51e22b343f64fb9428e76b 100755 --- a/arch/hc/src/m9s12/m9s12_sci.h +++ b/arch/hc/src/m9s12/m9s12_sci.h @@ -2,7 +2,7 @@ * arch/hc/src/m9s12/m9s12_sci.h (v3) * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_serial.h b/arch/hc/src/m9s12/m9s12_serial.h index 580862dce40fda620113abf8e16b93cb4962efba..f38377982b139e62f3f8004e2ed2dec4c64b6d4f 100755 --- a/arch/hc/src/m9s12/m9s12_serial.h +++ b/arch/hc/src/m9s12/m9s12_serial.h @@ -2,7 +2,7 @@ * arch/hc/src/m9s12/serial.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_spi.h b/arch/hc/src/m9s12/m9s12_spi.h index fe3e3cddfbc4585a59a5b1afa3bbff8610cedfa1..931e0efcf5d44cad18d941d57efbfba52ad3b2d0 100755 --- a/arch/hc/src/m9s12/m9s12_spi.h +++ b/arch/hc/src/m9s12/m9s12_spi.h @@ -2,7 +2,7 @@ * arch/hc/src/m9s12/m9s12_spi.h (v3) * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_start.S b/arch/hc/src/m9s12/m9s12_start.S index dd5b9ce14e70e4e94256c314e660bf5eddd94afe..66c1b80f9a0e83e19e7b5486020f7435caf17962 100755 --- a/arch/hc/src/m9s12/m9s12_start.S +++ b/arch/hc/src/m9s12/m9s12_start.S @@ -3,7 +3,7 @@ * arch/hc/src/chip/m9s12_start.S * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_tim.h b/arch/hc/src/m9s12/m9s12_tim.h index 820e069f14b2202360d0b17e0b895d1462ea2a5e..e50c86dbf3222bc24a0c976ec539bf3a7981ae56 100755 --- a/arch/hc/src/m9s12/m9s12_tim.h +++ b/arch/hc/src/m9s12/m9s12_tim.h @@ -2,7 +2,7 @@ * arch/hc/src/m9s12/m9s12_tim.h (TIM16b4c v1) * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_timerisr.c b/arch/hc/src/m9s12/m9s12_timerisr.c index 22e76d7ee6a5ca5458c4f808a077982343b958f1..dcefa1dc6d8c5fc162a22133c266dd65a252ce43 100755 --- a/arch/hc/src/m9s12/m9s12_timerisr.c +++ b/arch/hc/src/m9s12/m9s12_timerisr.c @@ -2,7 +2,7 @@ * arch/hc/src/m9s12/m9s12_timerisr.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/hc/src/m9s12/m9s12_vectors.S b/arch/hc/src/m9s12/m9s12_vectors.S index 991d37dd81de74cf0d794a6e402e48848bdf923f..dc57bf8b3b9543c4b386295ea90b4435f26bdb66 100755 --- a/arch/hc/src/m9s12/m9s12_vectors.S +++ b/arch/hc/src/m9s12/m9s12_vectors.S @@ -3,7 +3,7 @@ * arch/hc/src/chip/m9s12_vectors.S * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/include/arch.h b/arch/mips/include/arch.h index 13945d2b5c71060beede860a87c0aa9b4207d16e..c19d55cb949b1d0947c9fa218fd9fd56f84dc2c1 100644 --- a/arch/mips/include/arch.h +++ b/arch/mips/include/arch.h @@ -2,7 +2,7 @@ * arch/mips/include/arch.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/include/irq.h b/arch/mips/include/irq.h index d1a7f8eaf01f515fcb7b392d4613def01e00b072..c82661da11ac666a7a1e00c920f4e4d014e0f2d2 100644 --- a/arch/mips/include/irq.h +++ b/arch/mips/include/irq.h @@ -2,7 +2,7 @@ * arch/mips/include/irq.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/include/mips32/registers.h b/arch/mips/include/mips32/registers.h index e541a8e53195ad9d5811ed7d431a68e4c8476aa9..70279cb6f34d1a5dc78036d6506808e5c26d02f7 100644 --- a/arch/mips/include/mips32/registers.h +++ b/arch/mips/include/mips32/registers.h @@ -2,7 +2,7 @@ * arch/mips/include/mips32/registers.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/include/mips32/syscall.h b/arch/mips/include/mips32/syscall.h index b2aac6904c43aa998e8873fcf72f2152d69159ef..9c497c8b6c0ed9ab850f143bbc9c5e66bf05e901 100644 --- a/arch/mips/include/mips32/syscall.h +++ b/arch/mips/include/mips32/syscall.h @@ -2,7 +2,7 @@ * arch/mips/include/mips32/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/include/syscall.h b/arch/mips/include/syscall.h index 9fe94e14921f1373925829fc5a49a6eeb5cde091..f87c51d4c3af0e23a91b14584a92d8ee722968d9 100644 --- a/arch/mips/include/syscall.h +++ b/arch/mips/include/syscall.h @@ -2,7 +2,7 @@ * arch/mips/include/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/include/types.h b/arch/mips/include/types.h index a83208c5a6b58518754f13777438096b9f3bc6d9..625f4de274be8a1231578bf3bd68c7506fb8ab9e 100644 --- a/arch/mips/include/types.h +++ b/arch/mips/include/types.h @@ -2,7 +2,7 @@ * arch/mips/include/types.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/common/up_allocateheap.c b/arch/mips/src/common/up_allocateheap.c index 73933775d6fe77bd6b155eec6fd53dc620b92e64..f29b2685f209c1f0eb5f0f1c8f8ad47aabe51537 100644 --- a/arch/mips/src/common/up_allocateheap.c +++ b/arch/mips/src/common/up_allocateheap.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_allocateheap.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/common/up_arch.h b/arch/mips/src/common/up_arch.h index 06e2eb7e4e6e91d850c111df186338fabdc18fd0..9496016bcc5693b59d6efd81f10a6fd3cbbce6b3 100644 --- a/arch/mips/src/common/up_arch.h +++ b/arch/mips/src/common/up_arch.h @@ -2,7 +2,7 @@ * arch/mips/src/common/up_arch.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/common/up_createstack.c b/arch/mips/src/common/up_createstack.c index 08c7231dd8ee4cc28494bc25b56ee6f24c109c56..d5c285e25e630ed5b794484ceb5d9597d4b201c4 100644 --- a/arch/mips/src/common/up_createstack.c +++ b/arch/mips/src/common/up_createstack.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_createstack.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/common/up_interruptcontext.c b/arch/mips/src/common/up_interruptcontext.c index 48f6abd93d2c38cca4cdb10c98f387ae138ed83d..526e86f87e45a8b6253a60a0bf759f683fb63275 100644 --- a/arch/mips/src/common/up_interruptcontext.c +++ b/arch/mips/src/common/up_interruptcontext.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_interruptcontext.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/common/up_lowputs.c b/arch/mips/src/common/up_lowputs.c index 9734b584e7b47e396931b1ad7bdde775e9562121..314e239b1d478baab49eabb055fe9bfc48b737a4 100644 --- a/arch/mips/src/common/up_lowputs.c +++ b/arch/mips/src/common/up_lowputs.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_lowputs.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/common/up_mdelay.c b/arch/mips/src/common/up_mdelay.c index ff9b790e80813f7ed463166a18ee9fb710b918ba..c55fb55bdc306d73c97d6f03e8e24779e0719469 100644 --- a/arch/mips/src/common/up_mdelay.c +++ b/arch/mips/src/common/up_mdelay.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_mdelay.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/common/up_modifyreg16.c b/arch/mips/src/common/up_modifyreg16.c index ca72dec3eddd74e95d2b82cfc605aff1724254e1..2d6579947036b100df0f46326cf831f37ff53330 100644 --- a/arch/mips/src/common/up_modifyreg16.c +++ b/arch/mips/src/common/up_modifyreg16.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_modifyreg16.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/common/up_modifyreg32.c b/arch/mips/src/common/up_modifyreg32.c index 59bb3a1d82953de35a747b015d9eeb5bea4e4ef9..e5de12e5e9d89b8ac935981fb7c00a0203806ae1 100644 --- a/arch/mips/src/common/up_modifyreg32.c +++ b/arch/mips/src/common/up_modifyreg32.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_modifyreg32.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/common/up_modifyreg8.c b/arch/mips/src/common/up_modifyreg8.c index b590458b3bc58f5b7009e15f7d32354651130136..53ed99f9c7ba7ac6599f57e3583ae2b552f7da44 100644 --- a/arch/mips/src/common/up_modifyreg8.c +++ b/arch/mips/src/common/up_modifyreg8.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_modifyreg8.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/common/up_puts.c b/arch/mips/src/common/up_puts.c index 9dd4bb5f4e9a1b2f874e0efb9a68bc2b6962e1c1..2394343f9545c3dc3f91af0f08cec1b707c2f461 100644 --- a/arch/mips/src/common/up_puts.c +++ b/arch/mips/src/common/up_puts.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_puts.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/common/up_releasestack.c b/arch/mips/src/common/up_releasestack.c index 0724f1a76d89a5a3da3fca2136db0df22a6a3d7f..a54ea70cdbd9cb8c81a2b3e35deb7cd6513f5812 100644 --- a/arch/mips/src/common/up_releasestack.c +++ b/arch/mips/src/common/up_releasestack.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_releasestack.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/common/up_udelay.c b/arch/mips/src/common/up_udelay.c index b26f9d956e053281d90ab7cb2969ac39320be534..261348726de22b8ceb0cac27a6046bea6cec8271 100644 --- a/arch/mips/src/common/up_udelay.c +++ b/arch/mips/src/common/up_udelay.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_udelay.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/common/up_usestack.c b/arch/mips/src/common/up_usestack.c index fc27c1e76f69b5a3cbb0f722c17370e8c5a1fe40..e41608f67d9b7657eb7aa4bbe84c82df87cf8f4e 100644 --- a/arch/mips/src/common/up_usestack.c +++ b/arch/mips/src/common/up_usestack.c @@ -2,7 +2,7 @@ * arch/mips/src/common/up_usestack.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/mips32/mips32-memorymap.h b/arch/mips/src/mips32/mips32-memorymap.h index f4a0fed7d5d8d5484bedc0889b4a325d58d42ba1..21093c3b7cdd36ef40e37435f9527c6903a6cfdf 100644 --- a/arch/mips/src/mips32/mips32-memorymap.h +++ b/arch/mips/src/mips32/mips32-memorymap.h @@ -1,96 +1,96 @@ -/******************************************************************************************** - * arch/mips/src/mips32/mips32-memorymap.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************/ - -#ifndef __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H -#define __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H - -/******************************************************************************************** - * Included Files - ********************************************************************************************/ - -#include - -/******************************************************************************************** - * Pre-Processor Definitions - ********************************************************************************************/ - -/******************************************************************************************** - * Public Types - ********************************************************************************************/ - -/* MIPS32 address space organization */ - -#define USEG_BASE 0x00000000 -#define USEG_SIZE 0x80000000 - -#define KSEG0_BASE 0x80000000 -#define KSEG0_SIZE 0x20000000 - -#define KSEG1_BASE 0xa0000000 -#define KSEG1_SIZE 0x20000000 - -#define KSEG2_BASE 0xc0000000 -#define KSEG2_SIZE 0x20000000 - -#define KSEG3_BASE 0xe0000000 -#define KSEG3_SIZE 0x20000000 - -#define DSEG_BASE 0xff200000 -#define DSEG_SIZE 0x00200000 - -#ifndef __ASSEMBLY__ - -/******************************************************************************************** - * Inline Functions - ********************************************************************************************/ - -/******************************************************************************************** - * Public Function Prototypes - ********************************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H */ +/******************************************************************************************** + * arch/mips/src/mips32/mips32-memorymap.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H +#define __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +/******************************************************************************************** + * Pre-Processor Definitions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/* MIPS32 address space organization */ + +#define USEG_BASE 0x00000000 +#define USEG_SIZE 0x80000000 + +#define KSEG0_BASE 0x80000000 +#define KSEG0_SIZE 0x20000000 + +#define KSEG1_BASE 0xa0000000 +#define KSEG1_SIZE 0x20000000 + +#define KSEG2_BASE 0xc0000000 +#define KSEG2_SIZE 0x20000000 + +#define KSEG3_BASE 0xe0000000 +#define KSEG3_SIZE 0x20000000 + +#define DSEG_BASE 0xff200000 +#define DSEG_SIZE 0x00200000 + +#ifndef __ASSEMBLY__ + +/******************************************************************************************** + * Inline Functions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Function Prototypes + ********************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H */ diff --git a/arch/mips/src/mips32/up_assert.c b/arch/mips/src/mips32/up_assert.c index 977fe828747800aa34c77d9ebf5eeb2aea23e5eb..881ec12cb72a71ab3d2ce65b0b1784aee2bcd9f4 100644 --- a/arch/mips/src/mips32/up_assert.c +++ b/arch/mips/src/mips32/up_assert.c @@ -2,7 +2,7 @@ * arch/mips/src/mips32/up_assert.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/mips32/up_copystate.c b/arch/mips/src/mips32/up_copystate.c index 1bafffd0e3d4987ba571c6942d6b952a301d8c2f..798e82b045f01dcea004c8b34bf9e64387436226 100644 --- a/arch/mips/src/mips32/up_copystate.c +++ b/arch/mips/src/mips32/up_copystate.c @@ -2,7 +2,7 @@ * arch/mips/src/mips32/up_copystate.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/mips32/up_doirq.c b/arch/mips/src/mips32/up_doirq.c index d4a3d93a07a909ead7fb30a3ab0329160fe802ff..29cdf9c60a07eff6e003f85a05857151bebc94af 100644 --- a/arch/mips/src/mips32/up_doirq.c +++ b/arch/mips/src/mips32/up_doirq.c @@ -2,7 +2,7 @@ * arch/mips/src/mips32/up_doirq.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/mips32/up_dumpstate.c b/arch/mips/src/mips32/up_dumpstate.c index 369d98d7f546b05f4dbef8ff0794c826c52ff2e7..866c17b4f231b87b3182136e9cc3bb6fb7962a42 100644 --- a/arch/mips/src/mips32/up_dumpstate.c +++ b/arch/mips/src/mips32/up_dumpstate.c @@ -2,7 +2,7 @@ * arch/mips/src/mips32/up_dumpstate.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/mips32/up_releasepending.c b/arch/mips/src/mips32/up_releasepending.c index 978df0c7dfc476ad33ad2732aa159b17a62be392..13918ca216609ca88ba0dd64529c5aa1aed18455 100644 --- a/arch/mips/src/mips32/up_releasepending.c +++ b/arch/mips/src/mips32/up_releasepending.c @@ -2,7 +2,7 @@ * arch/mips/src/mips32/up_releasepending.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/mips32/up_reprioritizertr.c b/arch/mips/src/mips32/up_reprioritizertr.c index 24e33693cccd7bbb1e8acbc8ea190ad7467b9c1d..66ce687e0176adae216d1bed633658fdefb172a4 100644 --- a/arch/mips/src/mips32/up_reprioritizertr.c +++ b/arch/mips/src/mips32/up_reprioritizertr.c @@ -2,7 +2,7 @@ * arch/mips/src/mips32/up_reprioritizertr.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/mips32/up_unblocktask.c b/arch/mips/src/mips32/up_unblocktask.c index ba29cb736d539e0032a508cc2c89bd728d1e25b4..5dafe90f0ed14d077504684a4573b83e2aad5841 100644 --- a/arch/mips/src/mips32/up_unblocktask.c +++ b/arch/mips/src/mips32/up_unblocktask.c @@ -2,7 +2,7 @@ * arch/mips/src/mips32/up_unblocktask.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/pic32mx/pic32mx-che.h b/arch/mips/src/pic32mx/pic32mx-che.h index c4b0913a2a091381c99d2e2e01e4c432e9d33005..f552486ba9092b8398089b9ab57f211a8a2f5725 100644 --- a/arch/mips/src/pic32mx/pic32mx-che.h +++ b/arch/mips/src/pic32mx/pic32mx-che.h @@ -1,185 +1,185 @@ -/******************************************************************************************** - * arch/mips/src/pic32mx/pic32mx-che.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************/ - -#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H -#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H - -/******************************************************************************************** - * Included Files - ********************************************************************************************/ - -#include - -#include "pic32mx-memorymap.h" - -/******************************************************************************************** - * Pre-Processor Definitions - ********************************************************************************************/ -/* Register Offsets *************************************************************************/ - -#define PIC32MX_CHE_CON_OFFSET 0x0000 /* Pre-fetch cache control register */ -#define PIC32MX_CHE_CONCLR_OFFSET 0x0004 /* Pre-fetch cache control clear register */ -#define PIC32MX_CHE_CONSET_OFFSET 0x0008 /* Pre-fetch cache control set register */ -#define PIC32MX_CHE_CONINV_OFFSET 0x000c /* Pre-fetch cache control invert register */ -#define PIC32MX_CHE_ACC_OFFSET 0x0010 /* Pre-fetch cache access register */ -#define PIC32MX_CHE_ACCCLR_OFFSET 0x0014 /* Pre-fetch cache access clear register */ -#define PIC32MX_CHE_ACCSET_OFFSET 0x0018 /* Pre-fetch cache access set register */ -#define PIC32MX_CHE_ACCINV_OFFSET 0x001c /* Pre-fetch cache access invert register */ -#define PIC32MX_CHE_TAG_OFFSET 0x0020 /* Pre-fetch cache tag register */ -#define PIC32MX_CHE_TAGCLR_OFFSET 0x0024 /* Pre-fetch cache tag clear register */ -#define PIC32MX_CHE_TAGSET_OFFSET 0x0028 /* Pre-fetch cache tag set register */ -#define PIC32MX_CHE_TAGINV_OFFSET 0x002c /* Pre-fetch cache tag invert register */ -#define PIC32MX_CHE_MSK_OFFSET 0x0030 /* Pre-fetch cache tag mask register */ -#define PIC32MX_CHE_MSKCLR_OFFSET 0x0034 /* Pre-fetch cache tag mask clear register */ -#define PIC32MX_CHE_MSKSET_OFFSET 0x0038 /* Pre-fetch cache tag mask set register */ -#define PIC32MX_CHE_MSKINV_OFFSET 0x003c /* Pre-fetch cache tag mask invert register */ -#define PIC32MX_CHE_W0_OFFSET 0x0040 /* Cache word 0 register */ -#define PIC32MX_CHE_W1_OFFSET 0x0050 /* Cache word 1 register */ -#define PIC32MX_CHE_W2_OFFSET 0x0060 /* Cache word 2 register */ -#define PIC32MX_CHE_W3_OFFSET 0x0070 /* Cache word 3 register */ -#define PIC32MX_CHE_LRU_OFFSET 0x0080 /* Cache LRU register */ -#define PIC32MX_CHE_HIT_OFFSET 0x0090 /* Cache hit statistics register */ -#define PIC32MX_CHE_MIS_OFFSET 0x00a0 /* Cache miss statistics register */ -#define PIC32MX_CHE_PFABT_OFFSET 0x00c0 /* Pre-fetch cache abort statistics register */ - -/* Register Addresses ***********************************************************************/ - -#define PIC32MX_CHE_CON (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CON_OFFSET) -#define PIC32MX_CHE_CONCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONCLR_OFFSET) -#define PIC32MX_CHE_CONSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONSET_OFFSET) -#define PIC32MX_CHE_CONINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONINV_OFFSET) -#define PIC32MX_CHE_ACC (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACC_OFFSET) -#define PIC32MX_CHE_ACCCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCCLR_OFFSET) -#define PIC32MX_CHE_ACCSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCSET_OFFSET) -#define PIC32MX_CHE_ACCINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCINV_OFFSET) -#define PIC32MX_CHE_TAG (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAG_OFFSET) -#define PIC32MX_CHE_TAGCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGCLR_OFFSET) -#define PIC32MX_CHE_TAGSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGSET_OFFSET) -#define PIC32MX_CHE_TAGINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGINV_OFFSET) -#define PIC32MX_CHE_MSK (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSK_OFFSET) -#define PIC32MX_CHE_MSKCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKCLR_OFFSET) -#define PIC32MX_CHE_MSKSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKSET_OFFSET) -#define PIC32MX_CHE_MSKINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKINV_OFFSET) -#define PIC32MX_CHE_W0 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W0_OFFSET) -#define PIC32MX_CHE_W1 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W1_OFFSET) -#define PIC32MX_CHE_W2 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W2_OFFSET) -#define PIC32MX_CHE_W3 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W3_OFFSET) -#define PIC32MX_CHE_LRU (PIC32MX_CHE_K1BASE+PIC32MX_CHE_LRU_OFFSET) -#define PIC32MX_CHE_HIT (PIC32MX_CHE_K1BASE+PIC32MX_CHE_HIT_OFFSET) -#define PIC32MX_CHE_MIS (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MIS_OFFSET) -#define PIC32MX_CHE_PFABT (PIC32MX_CHE_K1BASE+PIC32MX_CHE_PFABT_OFFSET) - -/* Register Bit-Field Definitions ***********************************************************/ - -/* Pre-fetch cache control register */ - - -#define CHE_CON_PFMWS_SHIFT (0) /* Bits 0-2: PFM access time (SYSCLK wait states) */ -#define CHE_CON_PFMWS_MASK (7 << CHE_CON_PFMWS_SHIFT) -# define CHE_CON_PFMWS(n) ((n) << CHE_CON_PFMWS_SHIFT) /* n wait states, n=0-7 */ -#define CHE_CON_PREFEN_SHIFT (4) /* Bits 4-5: Predictive pre-fetch cache enable */ -#define CHE_CON_PREFEN_MASK (3 << CHE_CON_PREFEN_SHIFT) -# define CHE_CON_PREFEN_DISABLE (0 << CHE_CON_PREFEN_SHIFT) /* Disable predictive pre-fetch cache */ -# define CHE_CON_PREFEN_CACHE (1 << CHE_CON_PREFEN_SHIFT) /* Enable for cacheable regions only */ -# define CHE_CON_PREFEN_NONCACHE (2 << CHE_CON_PREFEN_SHIFT) /* Enable for non-cacheable regions only */ -# define CHE_CON_PREFEN_ALL (3 << CHE_CON_PREFEN_SHIFT) /* Enable for both regions */ -#define CHE_CON_DCSZ_SHIFT (8) /* Bits 8-9: Data cache size (lines) */ -#define CHE_CON_DCSZ_MASK (3 << CHE_CON_DCSZ_SHIFT) -# define CHE_CON_DCSZ_DISABLE (0 << CHE_CON_DCSZ_SHIFT) /* Disable data caching */ -# define CHE_CON_DCSZ_1LINE (1 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 1 line */ -# define CHE_CON_DCSZ_2LINES (2 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 2 lines */ -# define CHE_CON_DCSZ_4LINES (3 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 4 lines */ -#define CHE_CON_CHECOH (1 << 16) /* Bit 16: Cache coherency setting */ - -/* Pre-fetch cache access register */ - -#define CHE_ACC_CHEIDX_SHIFT (0) /* Bits 0-3: Cache line index */ -#define CHE_ACC_CHEIDX_MASK (15 << CHE_ACC_CHEIDX_SHIFT) -#define CHE_ACC_CHEWEN (1 << 31) /* Bit 31: Cache access enable */ - -/* Pre-fetch cache tag register */ - -#define CHE_TAG_LTYPE (1 << 1) /* Bit 1: Line type */ -#define CHE_TAG_LLOCK (1 << 2) /* Bit 2: Line lock */ -#define CHE_TAG_LVALID (1 << 3) /* Bit 3: Line valid */ -#define CHE_TAG_LTAG_SHIFT (4) /* Bits 4-23: Line tag address */ -#define CHE_TAG_LTAG_MASK (0x000fffff << CHE_TAG_LTAG_SHIFT) -#define CHE_TAG_LTAGBOOT (1 << 31) /* Bit 31: Line tag address boot */ - -/* Pre-fetch cache tag mask register */ - -#define CHE_MSK_SHIFT (5) /* Bits 5-15: Line mask */ -#define CHE_MSK_MASK (0x7ff << CHE_MSK_SHIFT) - -/* Cache word 0-3 register -- 32-bit cache line data */ - -/* Cache LRU register */ - -#define CHE_LRU_MASK 0x01ffffff /* Bits 0-24 */ - -/* Cache hit statistics register -- 32 bit counter value */ - -/* Cache miss statistics register -- 32 bit counter value */ - -/* Pre-fetch cache abort statistics register -- 32 bit counter value */ - -/******************************************************************************************** - * Public Types - ********************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/******************************************************************************************** - * Inline Functions - ********************************************************************************************/ - -/******************************************************************************************** - * Public Function Prototypes - ********************************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H */ +/******************************************************************************************** + * arch/mips/src/pic32mx/pic32mx-che.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include "pic32mx-memorymap.h" + +/******************************************************************************************** + * Pre-Processor Definitions + ********************************************************************************************/ +/* Register Offsets *************************************************************************/ + +#define PIC32MX_CHE_CON_OFFSET 0x0000 /* Pre-fetch cache control register */ +#define PIC32MX_CHE_CONCLR_OFFSET 0x0004 /* Pre-fetch cache control clear register */ +#define PIC32MX_CHE_CONSET_OFFSET 0x0008 /* Pre-fetch cache control set register */ +#define PIC32MX_CHE_CONINV_OFFSET 0x000c /* Pre-fetch cache control invert register */ +#define PIC32MX_CHE_ACC_OFFSET 0x0010 /* Pre-fetch cache access register */ +#define PIC32MX_CHE_ACCCLR_OFFSET 0x0014 /* Pre-fetch cache access clear register */ +#define PIC32MX_CHE_ACCSET_OFFSET 0x0018 /* Pre-fetch cache access set register */ +#define PIC32MX_CHE_ACCINV_OFFSET 0x001c /* Pre-fetch cache access invert register */ +#define PIC32MX_CHE_TAG_OFFSET 0x0020 /* Pre-fetch cache tag register */ +#define PIC32MX_CHE_TAGCLR_OFFSET 0x0024 /* Pre-fetch cache tag clear register */ +#define PIC32MX_CHE_TAGSET_OFFSET 0x0028 /* Pre-fetch cache tag set register */ +#define PIC32MX_CHE_TAGINV_OFFSET 0x002c /* Pre-fetch cache tag invert register */ +#define PIC32MX_CHE_MSK_OFFSET 0x0030 /* Pre-fetch cache tag mask register */ +#define PIC32MX_CHE_MSKCLR_OFFSET 0x0034 /* Pre-fetch cache tag mask clear register */ +#define PIC32MX_CHE_MSKSET_OFFSET 0x0038 /* Pre-fetch cache tag mask set register */ +#define PIC32MX_CHE_MSKINV_OFFSET 0x003c /* Pre-fetch cache tag mask invert register */ +#define PIC32MX_CHE_W0_OFFSET 0x0040 /* Cache word 0 register */ +#define PIC32MX_CHE_W1_OFFSET 0x0050 /* Cache word 1 register */ +#define PIC32MX_CHE_W2_OFFSET 0x0060 /* Cache word 2 register */ +#define PIC32MX_CHE_W3_OFFSET 0x0070 /* Cache word 3 register */ +#define PIC32MX_CHE_LRU_OFFSET 0x0080 /* Cache LRU register */ +#define PIC32MX_CHE_HIT_OFFSET 0x0090 /* Cache hit statistics register */ +#define PIC32MX_CHE_MIS_OFFSET 0x00a0 /* Cache miss statistics register */ +#define PIC32MX_CHE_PFABT_OFFSET 0x00c0 /* Pre-fetch cache abort statistics register */ + +/* Register Addresses ***********************************************************************/ + +#define PIC32MX_CHE_CON (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CON_OFFSET) +#define PIC32MX_CHE_CONCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONCLR_OFFSET) +#define PIC32MX_CHE_CONSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONSET_OFFSET) +#define PIC32MX_CHE_CONINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONINV_OFFSET) +#define PIC32MX_CHE_ACC (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACC_OFFSET) +#define PIC32MX_CHE_ACCCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCCLR_OFFSET) +#define PIC32MX_CHE_ACCSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCSET_OFFSET) +#define PIC32MX_CHE_ACCINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_ACCINV_OFFSET) +#define PIC32MX_CHE_TAG (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAG_OFFSET) +#define PIC32MX_CHE_TAGCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGCLR_OFFSET) +#define PIC32MX_CHE_TAGSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGSET_OFFSET) +#define PIC32MX_CHE_TAGINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_TAGINV_OFFSET) +#define PIC32MX_CHE_MSK (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSK_OFFSET) +#define PIC32MX_CHE_MSKCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKCLR_OFFSET) +#define PIC32MX_CHE_MSKSET (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKSET_OFFSET) +#define PIC32MX_CHE_MSKINV (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MSKINV_OFFSET) +#define PIC32MX_CHE_W0 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W0_OFFSET) +#define PIC32MX_CHE_W1 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W1_OFFSET) +#define PIC32MX_CHE_W2 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W2_OFFSET) +#define PIC32MX_CHE_W3 (PIC32MX_CHE_K1BASE+PIC32MX_CHE_W3_OFFSET) +#define PIC32MX_CHE_LRU (PIC32MX_CHE_K1BASE+PIC32MX_CHE_LRU_OFFSET) +#define PIC32MX_CHE_HIT (PIC32MX_CHE_K1BASE+PIC32MX_CHE_HIT_OFFSET) +#define PIC32MX_CHE_MIS (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MIS_OFFSET) +#define PIC32MX_CHE_PFABT (PIC32MX_CHE_K1BASE+PIC32MX_CHE_PFABT_OFFSET) + +/* Register Bit-Field Definitions ***********************************************************/ + +/* Pre-fetch cache control register */ + + +#define CHE_CON_PFMWS_SHIFT (0) /* Bits 0-2: PFM access time (SYSCLK wait states) */ +#define CHE_CON_PFMWS_MASK (7 << CHE_CON_PFMWS_SHIFT) +# define CHE_CON_PFMWS(n) ((n) << CHE_CON_PFMWS_SHIFT) /* n wait states, n=0-7 */ +#define CHE_CON_PREFEN_SHIFT (4) /* Bits 4-5: Predictive pre-fetch cache enable */ +#define CHE_CON_PREFEN_MASK (3 << CHE_CON_PREFEN_SHIFT) +# define CHE_CON_PREFEN_DISABLE (0 << CHE_CON_PREFEN_SHIFT) /* Disable predictive pre-fetch cache */ +# define CHE_CON_PREFEN_CACHE (1 << CHE_CON_PREFEN_SHIFT) /* Enable for cacheable regions only */ +# define CHE_CON_PREFEN_NONCACHE (2 << CHE_CON_PREFEN_SHIFT) /* Enable for non-cacheable regions only */ +# define CHE_CON_PREFEN_ALL (3 << CHE_CON_PREFEN_SHIFT) /* Enable for both regions */ +#define CHE_CON_DCSZ_SHIFT (8) /* Bits 8-9: Data cache size (lines) */ +#define CHE_CON_DCSZ_MASK (3 << CHE_CON_DCSZ_SHIFT) +# define CHE_CON_DCSZ_DISABLE (0 << CHE_CON_DCSZ_SHIFT) /* Disable data caching */ +# define CHE_CON_DCSZ_1LINE (1 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 1 line */ +# define CHE_CON_DCSZ_2LINES (2 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 2 lines */ +# define CHE_CON_DCSZ_4LINES (3 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 4 lines */ +#define CHE_CON_CHECOH (1 << 16) /* Bit 16: Cache coherency setting */ + +/* Pre-fetch cache access register */ + +#define CHE_ACC_CHEIDX_SHIFT (0) /* Bits 0-3: Cache line index */ +#define CHE_ACC_CHEIDX_MASK (15 << CHE_ACC_CHEIDX_SHIFT) +#define CHE_ACC_CHEWEN (1 << 31) /* Bit 31: Cache access enable */ + +/* Pre-fetch cache tag register */ + +#define CHE_TAG_LTYPE (1 << 1) /* Bit 1: Line type */ +#define CHE_TAG_LLOCK (1 << 2) /* Bit 2: Line lock */ +#define CHE_TAG_LVALID (1 << 3) /* Bit 3: Line valid */ +#define CHE_TAG_LTAG_SHIFT (4) /* Bits 4-23: Line tag address */ +#define CHE_TAG_LTAG_MASK (0x000fffff << CHE_TAG_LTAG_SHIFT) +#define CHE_TAG_LTAGBOOT (1 << 31) /* Bit 31: Line tag address boot */ + +/* Pre-fetch cache tag mask register */ + +#define CHE_MSK_SHIFT (5) /* Bits 5-15: Line mask */ +#define CHE_MSK_MASK (0x7ff << CHE_MSK_SHIFT) + +/* Cache word 0-3 register -- 32-bit cache line data */ + +/* Cache LRU register */ + +#define CHE_LRU_MASK 0x01ffffff /* Bits 0-24 */ + +/* Cache hit statistics register -- 32 bit counter value */ + +/* Cache miss statistics register -- 32 bit counter value */ + +/* Pre-fetch cache abort statistics register -- 32 bit counter value */ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/******************************************************************************************** + * Inline Functions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Function Prototypes + ********************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H */ diff --git a/arch/mips/src/pic32mx/pic32mx-cm.h b/arch/mips/src/pic32mx/pic32mx-cm.h index 9268089c095e852d3fb62569c1614b415840a6a5..de2c0216c0d79047b6e7e2090312f343b316a553 100644 --- a/arch/mips/src/pic32mx/pic32mx-cm.h +++ b/arch/mips/src/pic32mx/pic32mx-cm.h @@ -1,140 +1,140 @@ -/************************************************************************************ - * arch/mips/src/pic32mx/pic32mx-cm.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CM_H -#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CM_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "pic32mx-memorymap.h" - -#if CHIP_NCM > 0 - -/************************************************************************************ - * Pre-Processor Definitions - ************************************************************************************/ -/* Register Offsets *****************************************************************/ - -#define PIC32MX_CM_CON_OFFSET 0x0000 /* Comparator control register */ -#define PIC32MX_CM_CONCLR_OFFSET 0x0004 /* Comparator control clear register */ -#define PIC32MX_CM_CONSET_OFFSET 0x0008 /* Comparator control set register */ -#define PIC32MX_CM_CONINV_OFFSET 0x000c /* Comparator control invert register */ -#define PIC32MX_CM_STAT_OFFSET 0x0060 /* Comparator status register */ -#define PIC32MX_CM_STATCLR_OFFSET 0x0064 /* Comparator status clear register */ -#define PIC32MX_CM_STATSET_OFFSET 0x0068 /* Comparator status set register */ -#define PIC32MX_CM_STATINV_OFFSET 0x006c /* Comparator status invert register */ - -/* Register Addresses ***************************************************************/ - -#define PIC32MX_CM1_CON (PIC32MX_CM1_K1BASE+PIC32MX_CM_CON_OFFSET) -#define PIC32MX_CM1_CONCLR (PIC32MX_CM1_K1BASE+PIC32MX_CM_CONCLR_OFFSET) -#define PIC32MX_CM1_CONSET (PIC32MX_CM1_K1BASE+PIC32MX_CM_CONSET_OFFSET) -#define PIC32MX_CM1_CONINV (PIC32MX_CM1_K1BASE+PIC32MX_CM_CONINV_OFFSET) - -#if CHIP_NCM > 0 -# define PIC32MX_CM2_CON (PIC32MX_CM2_K1BASE+PIC32MX_CM_CON_OFFSET) -# define PIC32MX_CM2_CONCLR (PIC32MX_CM2_K1BASE+PIC32MX_CM_CONCLR_OFFSET) -# define PIC32MX_CM2_CONSET (PIC32MX_CM2_K1BASE+PIC32MX_CM_CONSET_OFFSET) -# define PIC32MX_CM2_CONINV (PIC32MX_CM2_K1BASE+PIC32MX_CM_CONINV_OFFSET) -#endif - -#define PIC32MX_CM_STAT (PIC32MX_CM_K1BASE+PIC32MX_CM_STAT_OFFSET) -#define PIC32MX_CM_STATCLR (PIC32MX_CM1_K1BASE+PIC32MX_CM_STATCLR_OFFSET) -#define PIC32MX_CM_STATSET (PIC32MX_CM1_K1BASE+PIC32MX_CM_STATSET_OFFSET) -#define PIC32MX_CM_STATINV (PIC32MX_CM1_K1BASE+PIC32MX_CM_STATINV_OFFSET) - -/* Register Bit-Field Definitions ***************************************************/ - -/* Comparator control register */ - -#define CM_CON_CCH_SHIFT (0) /* Bits 0-1: Comparator negative input select */ -#define CM_CON_CCH_MASK (3 << CM_CON_CCH_SHIFT) -# define CM_CON_CCH_CXINM (0 << CM_CON_CCH_SHIFT) /* Inverting input connected to CxIN- */ -# define CM_CON_CCH_CXINP (1 << CM_CON_CCH_SHIFT) /* Inverting input connected to CxIN+ */ -# define CM_CON_CCH_CYINP (2 << CM_CON_CCH_SHIFT) /* Inverting input connected to CyIN+ */ -# define CM_CON_CCH_IVREF (3 << CM_CON_CCH_SHIFT) /* Inverting input connected to IVREF */ -#define CM_CON_CREF (1 << 4) /* Bit 4: Comparator positive input configure */ -#define CM_CON_EVPOL_SHIFT (6) /* Bits 6-7: Interrupt event polarity select */ -#define CM_CON_EVPOL_MASK (3 << CM_CON_EVPOL_SHIFT) -# define CM_CON_EVPOL_DISABLED (0 << CM_CON_EVPOL_SHIFT) /* Interrupt disabled */ -# define CM_CON_EVPOL_RISING (1 << CM_CON_EVPOL_SHIFT) /* Interrupt on low-to-high transition */ -# define CM_CON_EVPOL_FALLING (2 << CM_CON_EVPOL_SHIFT) /* Interrupt on high-to-low transition */ -# define CM_CON_EVPOL_BOTH (3 << CM_CON_EVPOL_SHIFT) /* Interrupt on a both transitions */ -#define CM_CON_COUT (1 << 8) /* Bit 8: Comparator output */ -#define CM_CON_CPOL (1 << 13) /* Bit 13: Comparator output inversion */ -#define CM_CON_COE (1 << 14) /* Bit 14: Comparator output enable */ -#define CM_CON_ON (1 << 15) /* Bit 15: Comparator ON */ - -/* Comparator status register */ - -#define CM_STAT_C1OUT (1 << 0) /* Bit 0: Comparator 1 output */ -#define CM_STAT_C2OUT (1 << 1) /* Bit 1: Comparator 2 output */ -#define CM_STAT_SIDL (1 << 13) /* Bit 13: Stop in idle control */ -#define CM_STAT_FRZ (1 << 14) /* Bit 14: Freeze control */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* CHIP_NCM > 0 */ -#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CM_H */ +/************************************************************************************ + * arch/mips/src/pic32mx/pic32mx-cm.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CM_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CM_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "pic32mx-memorymap.h" + +#if CHIP_NCM > 0 + +/************************************************************************************ + * Pre-Processor Definitions + ************************************************************************************/ +/* Register Offsets *****************************************************************/ + +#define PIC32MX_CM_CON_OFFSET 0x0000 /* Comparator control register */ +#define PIC32MX_CM_CONCLR_OFFSET 0x0004 /* Comparator control clear register */ +#define PIC32MX_CM_CONSET_OFFSET 0x0008 /* Comparator control set register */ +#define PIC32MX_CM_CONINV_OFFSET 0x000c /* Comparator control invert register */ +#define PIC32MX_CM_STAT_OFFSET 0x0060 /* Comparator status register */ +#define PIC32MX_CM_STATCLR_OFFSET 0x0064 /* Comparator status clear register */ +#define PIC32MX_CM_STATSET_OFFSET 0x0068 /* Comparator status set register */ +#define PIC32MX_CM_STATINV_OFFSET 0x006c /* Comparator status invert register */ + +/* Register Addresses ***************************************************************/ + +#define PIC32MX_CM1_CON (PIC32MX_CM1_K1BASE+PIC32MX_CM_CON_OFFSET) +#define PIC32MX_CM1_CONCLR (PIC32MX_CM1_K1BASE+PIC32MX_CM_CONCLR_OFFSET) +#define PIC32MX_CM1_CONSET (PIC32MX_CM1_K1BASE+PIC32MX_CM_CONSET_OFFSET) +#define PIC32MX_CM1_CONINV (PIC32MX_CM1_K1BASE+PIC32MX_CM_CONINV_OFFSET) + +#if CHIP_NCM > 0 +# define PIC32MX_CM2_CON (PIC32MX_CM2_K1BASE+PIC32MX_CM_CON_OFFSET) +# define PIC32MX_CM2_CONCLR (PIC32MX_CM2_K1BASE+PIC32MX_CM_CONCLR_OFFSET) +# define PIC32MX_CM2_CONSET (PIC32MX_CM2_K1BASE+PIC32MX_CM_CONSET_OFFSET) +# define PIC32MX_CM2_CONINV (PIC32MX_CM2_K1BASE+PIC32MX_CM_CONINV_OFFSET) +#endif + +#define PIC32MX_CM_STAT (PIC32MX_CM_K1BASE+PIC32MX_CM_STAT_OFFSET) +#define PIC32MX_CM_STATCLR (PIC32MX_CM1_K1BASE+PIC32MX_CM_STATCLR_OFFSET) +#define PIC32MX_CM_STATSET (PIC32MX_CM1_K1BASE+PIC32MX_CM_STATSET_OFFSET) +#define PIC32MX_CM_STATINV (PIC32MX_CM1_K1BASE+PIC32MX_CM_STATINV_OFFSET) + +/* Register Bit-Field Definitions ***************************************************/ + +/* Comparator control register */ + +#define CM_CON_CCH_SHIFT (0) /* Bits 0-1: Comparator negative input select */ +#define CM_CON_CCH_MASK (3 << CM_CON_CCH_SHIFT) +# define CM_CON_CCH_CXINM (0 << CM_CON_CCH_SHIFT) /* Inverting input connected to CxIN- */ +# define CM_CON_CCH_CXINP (1 << CM_CON_CCH_SHIFT) /* Inverting input connected to CxIN+ */ +# define CM_CON_CCH_CYINP (2 << CM_CON_CCH_SHIFT) /* Inverting input connected to CyIN+ */ +# define CM_CON_CCH_IVREF (3 << CM_CON_CCH_SHIFT) /* Inverting input connected to IVREF */ +#define CM_CON_CREF (1 << 4) /* Bit 4: Comparator positive input configure */ +#define CM_CON_EVPOL_SHIFT (6) /* Bits 6-7: Interrupt event polarity select */ +#define CM_CON_EVPOL_MASK (3 << CM_CON_EVPOL_SHIFT) +# define CM_CON_EVPOL_DISABLED (0 << CM_CON_EVPOL_SHIFT) /* Interrupt disabled */ +# define CM_CON_EVPOL_RISING (1 << CM_CON_EVPOL_SHIFT) /* Interrupt on low-to-high transition */ +# define CM_CON_EVPOL_FALLING (2 << CM_CON_EVPOL_SHIFT) /* Interrupt on high-to-low transition */ +# define CM_CON_EVPOL_BOTH (3 << CM_CON_EVPOL_SHIFT) /* Interrupt on a both transitions */ +#define CM_CON_COUT (1 << 8) /* Bit 8: Comparator output */ +#define CM_CON_CPOL (1 << 13) /* Bit 13: Comparator output inversion */ +#define CM_CON_COE (1 << 14) /* Bit 14: Comparator output enable */ +#define CM_CON_ON (1 << 15) /* Bit 15: Comparator ON */ + +/* Comparator status register */ + +#define CM_STAT_C1OUT (1 << 0) /* Bit 0: Comparator 1 output */ +#define CM_STAT_C2OUT (1 << 1) /* Bit 1: Comparator 2 output */ +#define CM_STAT_SIDL (1 << 13) /* Bit 13: Stop in idle control */ +#define CM_STAT_FRZ (1 << 14) /* Bit 14: Freeze control */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CHIP_NCM > 0 */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CM_H */ diff --git a/arch/mips/src/pic32mx/pic32mx-ddp.h b/arch/mips/src/pic32mx/pic32mx-ddp.h index 8c8b8d7876bf11ad003895d71e72a5be25f7955f..c23cbb9c30c7fcd47395723cdae4dfe97e6328f7 100644 --- a/arch/mips/src/pic32mx/pic32mx-ddp.h +++ b/arch/mips/src/pic32mx/pic32mx-ddp.h @@ -1,94 +1,94 @@ -/************************************************************************************ - * arch/mips/src/pic32mx/pic32mx-ddp.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DDP_H -#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DDP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "pic32mx-memorymap.h" - -/************************************************************************************ - * Pre-Processor Definitions - ************************************************************************************/ -/* Register Offsets *****************************************************************/ - -#define PIC32MX_DDP_CON_OFFSET 0x0000 /* Control Register for the Diagnostic Module */ - -/* Register Addresses ***************************************************************/ - -#define PIC32MX_DDP_CON (PIC32MX_DDP_K1BASE+PIC32MX_DDP_CON_OFFSET) - -/* See also the ICESEL, DEBUG, and DEBUG0 in the DEVCFG0 register */ - -/* Register Bit-Field Definitions ***************************************************/ - -/* Control Register for the Diagnostic Module */ - -#define DDP_CON_TROEN (1 << 2) /* Bit 2: Trace output enable */ -#define DDP_CON_JTAGEN (1 << 3) /* Bit 3: JTAG port enable */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DDP_H */ +/************************************************************************************ + * arch/mips/src/pic32mx/pic32mx-ddp.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DDP_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DDP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "pic32mx-memorymap.h" + +/************************************************************************************ + * Pre-Processor Definitions + ************************************************************************************/ +/* Register Offsets *****************************************************************/ + +#define PIC32MX_DDP_CON_OFFSET 0x0000 /* Control Register for the Diagnostic Module */ + +/* Register Addresses ***************************************************************/ + +#define PIC32MX_DDP_CON (PIC32MX_DDP_K1BASE+PIC32MX_DDP_CON_OFFSET) + +/* See also the ICESEL, DEBUG, and DEBUG0 in the DEVCFG0 register */ + +/* Register Bit-Field Definitions ***************************************************/ + +/* Control Register for the Diagnostic Module */ + +#define DDP_CON_TROEN (1 << 2) /* Bit 2: Trace output enable */ +#define DDP_CON_JTAGEN (1 << 3) /* Bit 3: JTAG port enable */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DDP_H */ diff --git a/arch/mips/src/pic32mx/pic32mx-flash.h b/arch/mips/src/pic32mx/pic32mx-flash.h index 8ef9f31867747c0eb17d1ec28fab0c202914ec11..604f66c462015d1fe9daa024cc143585cd63cb31 100644 --- a/arch/mips/src/pic32mx/pic32mx-flash.h +++ b/arch/mips/src/pic32mx/pic32mx-flash.h @@ -1,130 +1,130 @@ - /******************************************************************************************** - * arch/mips/src/pic32mx/pic32mx-flash.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************/ - -#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_FLASH_H -#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_FLASH_H - - /******************************************************************************************** - * Included Files - ********************************************************************************************/ - -#include - -#include "pic32mx-memorymap.h" - - /******************************************************************************************** - * Pre-Processor Definitions - ********************************************************************************************/ -/* Register Offsets *************************************************************************/ - -#define PIC32MX_FLASH_NVMCON_OFFSET 0x0000 /* Programming Control Register */ -#define PIC32MX_FLASH_NVMCONCLR_OFFSET 0x0004 /* Programming Control Clear Register */ -#define PIC32MX_FLASH_NVMCONSET_OFFSET 0x0008 /* Programming Control Set Register */ -#define PIC32MX_FLASH_NVMCONINV_OFFSET 0x000c /* Programming Control Invert Register */ -#define PIC32MX_FLASH_NVMKEY_OFFSET 0x0010 /* Programming Unlock Register */ -#define PIC32MX_FLASH_NVMADDR_OFFSET 0x0020 /* Flash Address Register */ -#define PIC32MX_FLASH_NVMADDRCLR_OFFSET 0x0024 /* Flash Address Clear Register */ -#define PIC32MX_FLASH_NVMADDRSET_OFFSET 0x0028 /* Flash Address Set Register */ -#define PIC32MX_FLASH_NVMADDRINV_OFFSET 0x002c /* Flash Address Invert Register */ -#define PIC32MX_FLASH_NVMDATA_OFFSET 0x0030 /* Flash Program Data Register */ -#define PIC32MX_FLASH_NVMSRCADDR_OFFSET 0x0040 /* Source Data Address Register */ - -/* Register Addresses ***********************************************************************/ - -#define PIC32MX_FLASH_NVMCON (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCON_OFFSET) -#define PIC32MX_FLASH_NVMCONCLR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCONCLR_OFFSET) -#define PIC32MX_FLASH_NVMCONSET (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCONSET_OFFSET) -#define PIC32MX_FLASH_NVMCONINV (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCONINV_OFFSET) -#define PIC32MX_FLASH_NVMKEY (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMKEY_OFFSET) -#define PIC32MX_FLASH_NVMADDRCLR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDRCLR_OFFSET) -#define PIC32MX_FLASH_NVMADDRSET (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDRSET_OFFSET) -#define PIC32MX_FLASH_NVMADDRINV (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDRINV_OFFSET) -#define PIC32MX_FLASH_NVMADDR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDR_OFFSET) -#define PIC32MX_FLASH_NVMDATA (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMDATA_OFFSET) -#define PIC32MX_FLASH_NVMSRCADDR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMSRCADDR_OFFSET) - -/* Register Bit-Field Definitions ***********************************************************/ - -/* Programming Control Register */ - -#define FLASH_NVMCON_NVMOP_SHIFT (0) /* Bits 0-3: NVM operation */ -#define FLASH_NVMCON_NVMOP_MASK (15 << FLASH_NVMCON_NVMOP_SHIFT) -# define FLASH_NVMCON_NVMOP_NOP (0 << FLASH_NVMCON_NVMOP_SHIFT) /* No operation */ -# define FLASH_NVMCON_NVMOP_WDPROG (1 << FLASH_NVMCON_NVMOP_SHIFT) /* Word program operation */ -# define FLASH_NVMCON_NVMOP_ROWPROG (3 << FLASH_NVMCON_NVMOP_SHIFT) /* Row program operation */ -# define FLASH_NVMCON_NVMOP_PFMERASE (4 << FLASH_NVMCON_NVMOP_SHIFT) /* Page erase operation */ -# define FLASH_NVMCON_NVMOP_PFMERASE (5 << FLASH_NVMCON_NVMOP_SHIFT) /* PFM erase operationxx */ -#define FLASH_NVMCON_LVDSTAT (1 << 11) /* Bit nn: Low-voltage detect status */ -#define FLASH_NVMCON_LVDERR (1 << 12) /* Bit nn: Low-voltage detect error */ -#define FLASH_NVMCON_WRERR (1 << 13) /* Bit nn: Write error */ -#define FLASH_NVMCON_WREN (1 << 14) /* Bit nn: Write enable */ -#define FLASH_NVMCON_WR (1 << 15) /* Bit nn: Write control */ - -/* Programming Unlock Register -- 32 Bits of data */ - -/* Flash Address Register -- 32 Bits of data */ - -/* Flash Program Data Register -- 32 Bits of data */ - -/* Source Data Address Register -- 32 Bits of data */ - - /******************************************************************************************** - * Public Types - ********************************************************************************************/ - -#ifndef __ASSEMBLY__ - - /******************************************************************************************** - * Inline Functions - ********************************************************************************************/ - - /******************************************************************************************** - * Public Function Prototypes - ********************************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_FLASH_H */ + /******************************************************************************************** + * arch/mips/src/pic32mx/pic32mx-flash.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_FLASH_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_FLASH_H + + /******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include "pic32mx-memorymap.h" + + /******************************************************************************************** + * Pre-Processor Definitions + ********************************************************************************************/ +/* Register Offsets *************************************************************************/ + +#define PIC32MX_FLASH_NVMCON_OFFSET 0x0000 /* Programming Control Register */ +#define PIC32MX_FLASH_NVMCONCLR_OFFSET 0x0004 /* Programming Control Clear Register */ +#define PIC32MX_FLASH_NVMCONSET_OFFSET 0x0008 /* Programming Control Set Register */ +#define PIC32MX_FLASH_NVMCONINV_OFFSET 0x000c /* Programming Control Invert Register */ +#define PIC32MX_FLASH_NVMKEY_OFFSET 0x0010 /* Programming Unlock Register */ +#define PIC32MX_FLASH_NVMADDR_OFFSET 0x0020 /* Flash Address Register */ +#define PIC32MX_FLASH_NVMADDRCLR_OFFSET 0x0024 /* Flash Address Clear Register */ +#define PIC32MX_FLASH_NVMADDRSET_OFFSET 0x0028 /* Flash Address Set Register */ +#define PIC32MX_FLASH_NVMADDRINV_OFFSET 0x002c /* Flash Address Invert Register */ +#define PIC32MX_FLASH_NVMDATA_OFFSET 0x0030 /* Flash Program Data Register */ +#define PIC32MX_FLASH_NVMSRCADDR_OFFSET 0x0040 /* Source Data Address Register */ + +/* Register Addresses ***********************************************************************/ + +#define PIC32MX_FLASH_NVMCON (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCON_OFFSET) +#define PIC32MX_FLASH_NVMCONCLR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCONCLR_OFFSET) +#define PIC32MX_FLASH_NVMCONSET (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCONSET_OFFSET) +#define PIC32MX_FLASH_NVMCONINV (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCONINV_OFFSET) +#define PIC32MX_FLASH_NVMKEY (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMKEY_OFFSET) +#define PIC32MX_FLASH_NVMADDRCLR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDRCLR_OFFSET) +#define PIC32MX_FLASH_NVMADDRSET (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDRSET_OFFSET) +#define PIC32MX_FLASH_NVMADDRINV (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDRINV_OFFSET) +#define PIC32MX_FLASH_NVMADDR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDR_OFFSET) +#define PIC32MX_FLASH_NVMDATA (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMDATA_OFFSET) +#define PIC32MX_FLASH_NVMSRCADDR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMSRCADDR_OFFSET) + +/* Register Bit-Field Definitions ***********************************************************/ + +/* Programming Control Register */ + +#define FLASH_NVMCON_NVMOP_SHIFT (0) /* Bits 0-3: NVM operation */ +#define FLASH_NVMCON_NVMOP_MASK (15 << FLASH_NVMCON_NVMOP_SHIFT) +# define FLASH_NVMCON_NVMOP_NOP (0 << FLASH_NVMCON_NVMOP_SHIFT) /* No operation */ +# define FLASH_NVMCON_NVMOP_WDPROG (1 << FLASH_NVMCON_NVMOP_SHIFT) /* Word program operation */ +# define FLASH_NVMCON_NVMOP_ROWPROG (3 << FLASH_NVMCON_NVMOP_SHIFT) /* Row program operation */ +# define FLASH_NVMCON_NVMOP_PFMERASE (4 << FLASH_NVMCON_NVMOP_SHIFT) /* Page erase operation */ +# define FLASH_NVMCON_NVMOP_PFMERASE (5 << FLASH_NVMCON_NVMOP_SHIFT) /* PFM erase operationxx */ +#define FLASH_NVMCON_LVDSTAT (1 << 11) /* Bit nn: Low-voltage detect status */ +#define FLASH_NVMCON_LVDERR (1 << 12) /* Bit nn: Low-voltage detect error */ +#define FLASH_NVMCON_WRERR (1 << 13) /* Bit nn: Write error */ +#define FLASH_NVMCON_WREN (1 << 14) /* Bit nn: Write enable */ +#define FLASH_NVMCON_WR (1 << 15) /* Bit nn: Write control */ + +/* Programming Unlock Register -- 32 Bits of data */ + +/* Flash Address Register -- 32 Bits of data */ + +/* Flash Program Data Register -- 32 Bits of data */ + +/* Source Data Address Register -- 32 Bits of data */ + + /******************************************************************************************** + * Public Types + ********************************************************************************************/ + +#ifndef __ASSEMBLY__ + + /******************************************************************************************** + * Inline Functions + ********************************************************************************************/ + + /******************************************************************************************** + * Public Function Prototypes + ********************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_FLASH_H */ diff --git a/arch/mips/src/pic32mx/pic32mx-osc.h b/arch/mips/src/pic32mx/pic32mx-osc.h index 9142b19a2d0769bd1cc9f013c8cac4f7d3f9c9cc..69c00329d6a81b5e22bde8f37956f2e1974e89fd 100644 --- a/arch/mips/src/pic32mx/pic32mx-osc.h +++ b/arch/mips/src/pic32mx/pic32mx-osc.h @@ -1,165 +1,165 @@ -/**************************************************************************** - * arch/mips/src/pic32mx/pic32mx-osc.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H -#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "pic32mx-memorymap.h" - -/**************************************************************************** - * Pre-Processor Definitions - ****************************************************************************/ -/* Register Offsets *********************************************************/ - -#define PIC32MX_OSCCON_OFFSET 0x0000 /* Oscillator control register offset */ -#define PIC32MX_OSCTUN_OFFSET 0x0010 /* FRC tuning register offset */ - -/* Register Addresses *******************************************************/ - -#define PIC32MX_OSCCON (PIC32MX_OSC_K1BASE+PIC32MX_OSCCON_OFFSET) -#define PIC32MX_OSCTUN (PIC32MX_OSC_K1BASE+PIC32MX_OSCTUN_OFFSET) - -/* Register Bit-Field Definitions *******************************************/ - -/* Oscillator control register offset */ - -#define OSCCON_OSWEN (1 << 0) /* Bit 0: Oscillator switch enable */ -#define OSCCON_SOSCEN (1 << 1) /* Bit 1: 32.768kHz secondary oscillator enable */ -#define OSCCON_UFRCEN (1 << 2) /* Bit 2: USB FRC clock enable */ -#define OSCCON_CF (1 << 3) /* Bit 3: Clock fail detect */ -#define OSCCON_SLPEN (1 << 4) /* Bit 4: Sleep mode enable */ -#define OSCCON_SLOCK (1 << 5) /* Bit 5: PLL lock status */ -#define OSCCON_ULOCK (1 << 6) /* Bit 6: USB PLL lock status */ -#define OSCCON_CLKLOCK (1 << 7) /* Bit 7: Clock selection lock enable */ -#define OSCCON_NOSC_SHIFT (8) /* Bits 8-10: New oscillator selection */ -#define OSCCON_NOSC_MASK (7 << OSCCON_NOSC_SHIFT) -# define OSCCON_NOSC_FRC (0 << OSCCON_NOSC_SHIFT) /* FRC oscillator */ -# define OSCCON_NOSC_FRCPLL (1 << OSCCON_NOSC_SHIFT) /* FRC w/PLL postscaler */ -# define OSCCON_NOSC_POSC (2 << OSCCON_NOSC_SHIFT) /* Primary oscillator */ -# define OSCCON_NOSC_POSCPLL (3 << OSCCON_NOSC_SHIFT) /* Primary oscillator with PLL */ -# define OSCCON_NOSC_SOSC (4 << OSCCON_NOSC_SHIFT) /* Secondary oscillator */ -# define OSCCON_NOSC_LPRC (5 << OSCCON_NOSC_SHIFT) /* Low power RC oscillator */ -# define OSCCON_NOSC_FRCDIV16 (6 << OSCCON_NOSC_SHIFT) /* FRC divided by 16 */ -# define OSCCON_NOSC_FRCDIV (7 << OSCCON_NOSC_SHIFT) /* FRC dived by FRCDIV */ -#define OSCCON_COSC_SHIFT (12) /* Bits 12-14: Current oscillator selection */ -#define OSCCON_COSC_MASK (7 << OSCCON_COSC_SHIFT) -# define OSCCON_COSC_FRC (0 << OSCCON_COSC_SHIFT) /* FRC oscillator */ -# define OSCCON_COSC_FRCPLL (1 << OSCCON_COSC_SHIFT) /* FRC w/PLL postscaler */ -# define OSCCON_COSC_POSC (2 << OSCCON_COSC_SHIFT) /* Primary oscillator */ -# define OSCCON_COSC_POSCPLL (3 << OSCCON_COSC_SHIFT) /* Primary oscillator with PLL */ -# define OSCCON_COSC_SOSC (4 << OSCCON_COSC_SHIFT) /* Secondary oscillator */ -# define OSCCON_COSC_LPRC (5 << OSCCON_COSC_SHIFT) /* Low power RC oscillator */ -# define OSCCON_COSC_FRCDIV16 (6 << OSCCON_COSC_SHIFT) /* FRC divided by 16 */ -# define OSCCON_COSC_FRCDIV (7 << OSCCON_COSC_SHIFT) /* FRC dived by FRCDIV */ -#define OSCCON_PLLMULT_SHIFT (16) /* Bits 16-18: PLL multiplier */ -#define OSCCON_PLLMULT_MASK (7 << OSCCON_PLLMULT_SHIFT) -# define OSCCON_PLLMULT_MUL15 (0 << OSCCON_PLLMULT_SHIFT) -# define OSCCON_PLLMULT_MUL16 (1 << OSCCON_PLLMULT_SHIFT) -# define OSCCON_PLLMULT_MUL17 (2 << OSCCON_PLLMULT_SHIFT) -# define OSCCON_PLLMULT_MUL18 (3 << OSCCON_PLLMULT_SHIFT) -# define OSCCON_PLLMULT_MUL19 (4 << OSCCON_PLLMULT_SHIFT) -# define OSCCON_PLLMULT_MUL20 (5 << OSCCON_PLLMULT_SHIFT) -# define OSCCON_PLLMULT_MUL21 (6 << OSCCON_PLLMULT_SHIFT) -# define OSCCON_PLLMULT_MUL24 (7 << OSCCON_PLLMULT_SHIFT) -#define OSCCON_PBDIV_SHIFT (19) /* Bits 19-20: PBVLK divisor */ -#define OSCCON_PBDIV_SMASK (3 << OSCCON_PBDIV_SHIFT) -# define OSCCON_PBDIV_DIV1 (0 << OSCCON_PBDIV_SHIFT) -# define OSCCON_PBDIV_DIV2 (1 << OSCCON_PBDIV_SHIFT) -# define OSCCON_PBDIV_DIV4 (2 << OSCCON_PBDIV_SHIFT) -# define OSCCON_PBDIV_DIV8 (3 << OSCCON_PBDIV_SHIFT) -#define OSCCON_SOSCRDY (1 << 22) /* Bit 22: Secondary oscillator ready */ -#define OSCCON_FRCDIV_SHIFT (24) /* Bits 24-26: FRC oscillator divider */ -#define OSCCON_FRCDIV_MASK (7 << OSCCON_FRCDIV_SHIFT) -# define OSCCON_FRCDIV_DIV1 (0 << OSCCON_FRCDIV_SHIFT) -# define OSCCON_FRCDIV_DIV2 (1 << OSCCON_FRCDIV_SHIFT) -# define OSCCON_FRCDIV_DIV4 (2 << OSCCON_FRCDIV_SHIFT) -# define OSCCON_FRCDIV_DIV8 (3 << OSCCON_FRCDIV_SHIFT) -# define OSCCON_FRCDIV_DIV16 (4 << OSCCON_FRCDIV_SHIFT) -# define OSCCON_FRCDIV_DIV32 (5 << OSCCON_FRCDIV_SHIFT) -# define OSCCON_FRCDIV_DIV64 (6 << OSCCON_FRCDIV_SHIFT) -# define OSCCON_FRCDIV_DIV256 (7 << OSCCON_FRCDIV_SHIFT) -#define OSCCON_PLL0DIV_SHIFT (27) /* Bits 27-29: Output divider for PLL */ -#define OSCCON_PLL0DIV_MASK (7 << OSCCON_PLL0DIV_SHIFT) -# define OSCCON_PLL0DIV_DIV1 (0 << OSCCON_PLL0DIV_SHIFT) -# define OSCCON_PLL0DIV_DIV2 (1 << OSCCON_PLL0DIV_SHIFT) -# define OSCCON_PLL0DIV_DIV4 (2 << OSCCON_PLL0DIV_SHIFT) -# define OSCCON_PLL0DIV_DIV8 (3 << OSCCON_PLL0DIV_SHIFT) -# define OSCCON_PLL0DIV_DIV16 (4 << OSCCON_PLL0DIV_SHIFT) -# define OSCCON_PLL0DIV_DIV32 (5 << OSCCON_PLL0DIV_SHIFT) -# define OSCCON_PLL0DIV_DIV64 (6 << OSCCON_PLL0DIV_SHIFT) -# define OSCCON_PLL0DIV_DIV256 (7 << OSCCON_PLL0DIV_SHIFT) - -/* FRC tuning register offset (6-bit, signed twos complement) */ - -#define OSCTUN_SHIFT (0) /* Bits 0-5: FRC tuning bits */ -#define OSCTUN_MASK (0x3f << OSCTUN_SHIFT) -# define OSCTUN_MIN (0x20 << OSCTUN_SHIFT) -# define OSCTUN_CENTER (0x00 << OSCTUN_SHIFT) -# define OSCTUN_MAX (0x1f << OSCTUN_SHIFT) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H */ +/**************************************************************************** + * arch/mips/src/pic32mx/pic32mx-osc.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "pic32mx-memorymap.h" + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ +/* Register Offsets *********************************************************/ + +#define PIC32MX_OSCCON_OFFSET 0x0000 /* Oscillator control register offset */ +#define PIC32MX_OSCTUN_OFFSET 0x0010 /* FRC tuning register offset */ + +/* Register Addresses *******************************************************/ + +#define PIC32MX_OSCCON (PIC32MX_OSC_K1BASE+PIC32MX_OSCCON_OFFSET) +#define PIC32MX_OSCTUN (PIC32MX_OSC_K1BASE+PIC32MX_OSCTUN_OFFSET) + +/* Register Bit-Field Definitions *******************************************/ + +/* Oscillator control register offset */ + +#define OSCCON_OSWEN (1 << 0) /* Bit 0: Oscillator switch enable */ +#define OSCCON_SOSCEN (1 << 1) /* Bit 1: 32.768kHz secondary oscillator enable */ +#define OSCCON_UFRCEN (1 << 2) /* Bit 2: USB FRC clock enable */ +#define OSCCON_CF (1 << 3) /* Bit 3: Clock fail detect */ +#define OSCCON_SLPEN (1 << 4) /* Bit 4: Sleep mode enable */ +#define OSCCON_SLOCK (1 << 5) /* Bit 5: PLL lock status */ +#define OSCCON_ULOCK (1 << 6) /* Bit 6: USB PLL lock status */ +#define OSCCON_CLKLOCK (1 << 7) /* Bit 7: Clock selection lock enable */ +#define OSCCON_NOSC_SHIFT (8) /* Bits 8-10: New oscillator selection */ +#define OSCCON_NOSC_MASK (7 << OSCCON_NOSC_SHIFT) +# define OSCCON_NOSC_FRC (0 << OSCCON_NOSC_SHIFT) /* FRC oscillator */ +# define OSCCON_NOSC_FRCPLL (1 << OSCCON_NOSC_SHIFT) /* FRC w/PLL postscaler */ +# define OSCCON_NOSC_POSC (2 << OSCCON_NOSC_SHIFT) /* Primary oscillator */ +# define OSCCON_NOSC_POSCPLL (3 << OSCCON_NOSC_SHIFT) /* Primary oscillator with PLL */ +# define OSCCON_NOSC_SOSC (4 << OSCCON_NOSC_SHIFT) /* Secondary oscillator */ +# define OSCCON_NOSC_LPRC (5 << OSCCON_NOSC_SHIFT) /* Low power RC oscillator */ +# define OSCCON_NOSC_FRCDIV16 (6 << OSCCON_NOSC_SHIFT) /* FRC divided by 16 */ +# define OSCCON_NOSC_FRCDIV (7 << OSCCON_NOSC_SHIFT) /* FRC dived by FRCDIV */ +#define OSCCON_COSC_SHIFT (12) /* Bits 12-14: Current oscillator selection */ +#define OSCCON_COSC_MASK (7 << OSCCON_COSC_SHIFT) +# define OSCCON_COSC_FRC (0 << OSCCON_COSC_SHIFT) /* FRC oscillator */ +# define OSCCON_COSC_FRCPLL (1 << OSCCON_COSC_SHIFT) /* FRC w/PLL postscaler */ +# define OSCCON_COSC_POSC (2 << OSCCON_COSC_SHIFT) /* Primary oscillator */ +# define OSCCON_COSC_POSCPLL (3 << OSCCON_COSC_SHIFT) /* Primary oscillator with PLL */ +# define OSCCON_COSC_SOSC (4 << OSCCON_COSC_SHIFT) /* Secondary oscillator */ +# define OSCCON_COSC_LPRC (5 << OSCCON_COSC_SHIFT) /* Low power RC oscillator */ +# define OSCCON_COSC_FRCDIV16 (6 << OSCCON_COSC_SHIFT) /* FRC divided by 16 */ +# define OSCCON_COSC_FRCDIV (7 << OSCCON_COSC_SHIFT) /* FRC dived by FRCDIV */ +#define OSCCON_PLLMULT_SHIFT (16) /* Bits 16-18: PLL multiplier */ +#define OSCCON_PLLMULT_MASK (7 << OSCCON_PLLMULT_SHIFT) +# define OSCCON_PLLMULT_MUL15 (0 << OSCCON_PLLMULT_SHIFT) +# define OSCCON_PLLMULT_MUL16 (1 << OSCCON_PLLMULT_SHIFT) +# define OSCCON_PLLMULT_MUL17 (2 << OSCCON_PLLMULT_SHIFT) +# define OSCCON_PLLMULT_MUL18 (3 << OSCCON_PLLMULT_SHIFT) +# define OSCCON_PLLMULT_MUL19 (4 << OSCCON_PLLMULT_SHIFT) +# define OSCCON_PLLMULT_MUL20 (5 << OSCCON_PLLMULT_SHIFT) +# define OSCCON_PLLMULT_MUL21 (6 << OSCCON_PLLMULT_SHIFT) +# define OSCCON_PLLMULT_MUL24 (7 << OSCCON_PLLMULT_SHIFT) +#define OSCCON_PBDIV_SHIFT (19) /* Bits 19-20: PBVLK divisor */ +#define OSCCON_PBDIV_SMASK (3 << OSCCON_PBDIV_SHIFT) +# define OSCCON_PBDIV_DIV1 (0 << OSCCON_PBDIV_SHIFT) +# define OSCCON_PBDIV_DIV2 (1 << OSCCON_PBDIV_SHIFT) +# define OSCCON_PBDIV_DIV4 (2 << OSCCON_PBDIV_SHIFT) +# define OSCCON_PBDIV_DIV8 (3 << OSCCON_PBDIV_SHIFT) +#define OSCCON_SOSCRDY (1 << 22) /* Bit 22: Secondary oscillator ready */ +#define OSCCON_FRCDIV_SHIFT (24) /* Bits 24-26: FRC oscillator divider */ +#define OSCCON_FRCDIV_MASK (7 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV1 (0 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV2 (1 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV4 (2 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV8 (3 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV16 (4 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV32 (5 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV64 (6 << OSCCON_FRCDIV_SHIFT) +# define OSCCON_FRCDIV_DIV256 (7 << OSCCON_FRCDIV_SHIFT) +#define OSCCON_PLL0DIV_SHIFT (27) /* Bits 27-29: Output divider for PLL */ +#define OSCCON_PLL0DIV_MASK (7 << OSCCON_PLL0DIV_SHIFT) +# define OSCCON_PLL0DIV_DIV1 (0 << OSCCON_PLL0DIV_SHIFT) +# define OSCCON_PLL0DIV_DIV2 (1 << OSCCON_PLL0DIV_SHIFT) +# define OSCCON_PLL0DIV_DIV4 (2 << OSCCON_PLL0DIV_SHIFT) +# define OSCCON_PLL0DIV_DIV8 (3 << OSCCON_PLL0DIV_SHIFT) +# define OSCCON_PLL0DIV_DIV16 (4 << OSCCON_PLL0DIV_SHIFT) +# define OSCCON_PLL0DIV_DIV32 (5 << OSCCON_PLL0DIV_SHIFT) +# define OSCCON_PLL0DIV_DIV64 (6 << OSCCON_PLL0DIV_SHIFT) +# define OSCCON_PLL0DIV_DIV256 (7 << OSCCON_PLL0DIV_SHIFT) + +/* FRC tuning register offset (6-bit, signed twos complement) */ + +#define OSCTUN_SHIFT (0) /* Bits 0-5: FRC tuning bits */ +#define OSCTUN_MASK (0x3f << OSCTUN_SHIFT) +# define OSCTUN_MIN (0x20 << OSCTUN_SHIFT) +# define OSCTUN_CENTER (0x00 << OSCTUN_SHIFT) +# define OSCTUN_MAX (0x1f << OSCTUN_SHIFT) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H */ diff --git a/arch/mips/src/pic32mx/pic32mx-pmp.h b/arch/mips/src/pic32mx/pic32mx-pmp.h index d3ed74627bd156a3b6772e88bdeca2c75b3c08fc..745c56a3d9baf6ef8185c3aa85739bb77e3b9940 100644 --- a/arch/mips/src/pic32mx/pic32mx-pmp.h +++ b/arch/mips/src/pic32mx/pic32mx-pmp.h @@ -2,7 +2,7 @@ * arch/mips/src/pic32mx/pic32mx-pmp.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/pic32mx/pic32mx-reset.h b/arch/mips/src/pic32mx/pic32mx-reset.h index 5e1721796a49f1780994cec4f0bbc3ff6701fb76..22fc62e4e17ef20abd2600c4cf4fb073a719c11a 100644 --- a/arch/mips/src/pic32mx/pic32mx-reset.h +++ b/arch/mips/src/pic32mx/pic32mx-reset.h @@ -1,117 +1,117 @@ -/************************************************************************************ - * arch/mips/src/pic32mx/pic32mx-reset.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RESET_H -#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RESET_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "pic32mx-memorymap.h" - -/************************************************************************************ - * Pre-Processor Definitions - ************************************************************************************/ -/* Register Offsets *****************************************************************/ - -#define PIC32MX_RESET_RCON_OFFSET 0x0000 /* Reset control register */ -#define PIC32MX_RESET_RCONCLR_OFFSET 0x0004 /* RCON clear register */ -#define PIC32MX_RESET_RCONSET_OFFSET 0x0008 /* RCON set register */ -#define PIC32MX_RESET_RCONINV_OFFSET 0x000c /* RCON invert register */ -#define PIC32MX_RESET_RSWRST_OFFSET 0x0010 /* Software reset register */ -#define PIC32MX_RESET_RSWRSTCLR_OFFSET 0x0014 /* RSWRST clear register */ -#define PIC32MX_RESET_RSWRSTSET_OFFSET 0x0018 /* RSWRST set register */ -#define PIC32MX_RESET_RSWRSTINV_OFFSET 0x001c /* RSWRST invert register */ - -/* Register Addresses ***************************************************************/ - -#define PIC32MX_RESET_RCON (PIC32MX_RESET_K1BASE+PIC32MX_RCON_OFFSET) -#define PIC32MX_RESET_RCONCLR (PIC32MX_RESET_K1BASE+PIC32MX_RCONCLR_OFFSET) -#define PIC32MX_RESET_RCONSET (PIC32MX_RESET_K1BASE+PIC32MX_RCONSET_OFFSET) -#define PIC32MX_RESET_RCONINV (PIC32MX_RESET_K1BASE+PIC32MX_RCONINV_OFFSET) -#define PIC32MX_RESET_RSWRST (PIC32MX_RESET_K1BASE+PIC32MX_RSWRST_OFFSET) -#define PIC32MX_RESET_RSWRSTCLR (PIC32MX_RESET_K1BASE+PIC32MX_RSWRSTCLR_OFFSET) -#define PIC32MX_RESET_RSWRSTSET (PIC32MX_RESET_K1BASE+PIC32MX_RSWRSTSET_OFFSET) -#define PIC32MX_RESET_RSWRSTINV (PIC32MX_RESET_K1BASE+PIC32MX_RSWRSTINV_OFFSET) - -/* Register Bit-Field Definitions ***************************************************/ - -/* Reset control register */ - -#define RESET_RCON_POR (1 << 0) /* Bit 0: Power on reset */ -#define RESET_RCON_BOR (1 << 1) /* Bit 1: Brown out reset */ -#define RESET_RCON_IDLE (1 << 2) /* Bit 2: Wake from idle */ -#define RESET_RCON_SLEEP (1 << 3) /* Bit 3: Wake from sleep */ -#define RESET_RCON_WDTO (1 << 4) /* Bit 4: Watchdog timer time-out */ -#define RESET_RCON_SWR (1 << 6) /* Bit 6: Software reset */ -#define RESET_RCON_EXTR (1 << 7) /* Bit 7: External reset pin */ -#define RESET_RCON_VREGS (1 << 8) /* Bit 8: Voltage regulator standby enable */ -#define RESET_RCON_CMR (1 << 9) /* Bit 9: Configuration mismatch reset */ - -/* Software reset register */ - -#define RESET_RSWRST_TRIGGER (1 << 0) /* Bit 0: Software reset trigger */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RESET_H */ +/************************************************************************************ + * arch/mips/src/pic32mx/pic32mx-reset.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RESET_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RESET_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "pic32mx-memorymap.h" + +/************************************************************************************ + * Pre-Processor Definitions + ************************************************************************************/ +/* Register Offsets *****************************************************************/ + +#define PIC32MX_RESET_RCON_OFFSET 0x0000 /* Reset control register */ +#define PIC32MX_RESET_RCONCLR_OFFSET 0x0004 /* RCON clear register */ +#define PIC32MX_RESET_RCONSET_OFFSET 0x0008 /* RCON set register */ +#define PIC32MX_RESET_RCONINV_OFFSET 0x000c /* RCON invert register */ +#define PIC32MX_RESET_RSWRST_OFFSET 0x0010 /* Software reset register */ +#define PIC32MX_RESET_RSWRSTCLR_OFFSET 0x0014 /* RSWRST clear register */ +#define PIC32MX_RESET_RSWRSTSET_OFFSET 0x0018 /* RSWRST set register */ +#define PIC32MX_RESET_RSWRSTINV_OFFSET 0x001c /* RSWRST invert register */ + +/* Register Addresses ***************************************************************/ + +#define PIC32MX_RESET_RCON (PIC32MX_RESET_K1BASE+PIC32MX_RCON_OFFSET) +#define PIC32MX_RESET_RCONCLR (PIC32MX_RESET_K1BASE+PIC32MX_RCONCLR_OFFSET) +#define PIC32MX_RESET_RCONSET (PIC32MX_RESET_K1BASE+PIC32MX_RCONSET_OFFSET) +#define PIC32MX_RESET_RCONINV (PIC32MX_RESET_K1BASE+PIC32MX_RCONINV_OFFSET) +#define PIC32MX_RESET_RSWRST (PIC32MX_RESET_K1BASE+PIC32MX_RSWRST_OFFSET) +#define PIC32MX_RESET_RSWRSTCLR (PIC32MX_RESET_K1BASE+PIC32MX_RSWRSTCLR_OFFSET) +#define PIC32MX_RESET_RSWRSTSET (PIC32MX_RESET_K1BASE+PIC32MX_RSWRSTSET_OFFSET) +#define PIC32MX_RESET_RSWRSTINV (PIC32MX_RESET_K1BASE+PIC32MX_RSWRSTINV_OFFSET) + +/* Register Bit-Field Definitions ***************************************************/ + +/* Reset control register */ + +#define RESET_RCON_POR (1 << 0) /* Bit 0: Power on reset */ +#define RESET_RCON_BOR (1 << 1) /* Bit 1: Brown out reset */ +#define RESET_RCON_IDLE (1 << 2) /* Bit 2: Wake from idle */ +#define RESET_RCON_SLEEP (1 << 3) /* Bit 3: Wake from sleep */ +#define RESET_RCON_WDTO (1 << 4) /* Bit 4: Watchdog timer time-out */ +#define RESET_RCON_SWR (1 << 6) /* Bit 6: Software reset */ +#define RESET_RCON_EXTR (1 << 7) /* Bit 7: External reset pin */ +#define RESET_RCON_VREGS (1 << 8) /* Bit 8: Voltage regulator standby enable */ +#define RESET_RCON_CMR (1 << 9) /* Bit 9: Configuration mismatch reset */ + +/* Software reset register */ + +#define RESET_RSWRST_TRIGGER (1 << 0) /* Bit 0: Software reset trigger */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RESET_H */ diff --git a/arch/mips/src/pic32mx/pic32mx-rtcc.h b/arch/mips/src/pic32mx/pic32mx-rtcc.h index 4a3c2a31d917da76b005b0cf88c714005754c815..5ecb9090ca8a2987e8eb5f3dd3b5f35ff1013111 100644 --- a/arch/mips/src/pic32mx/pic32mx-rtcc.h +++ b/arch/mips/src/pic32mx/pic32mx-rtcc.h @@ -1,219 +1,219 @@ -/******************************************************************************************** - * arch/mips/src/pic32mx/pic32mx-rtcc.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************/ - -#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RTCC_H -#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RTCC_H - -/******************************************************************************************** - * Included Files - ********************************************************************************************/ - -#include - -#include "pic32mx-memorymap.h" - -/******************************************************************************************** - * Pre-Processor Definitions - ********************************************************************************************/ -/* Register Offsets *************************************************************************/ - -#define PIC32MX_RTCC_CON_OFFSET 0x0000 /* RTC Control Register */ -#define PIC32MX_RTCC_CONCLR_OFFSET 0x0004 /* RTC Control Clear Register */ -#define PIC32MX_RTCC_CONSET_OFFSET 0x0008 /* RTC Control Set Register */ -#define PIC32MX_RTCC_CONINV_OFFSET 0x000c /* RTC Control Invert Register */ -#define PIC32MX_RTCC_ALRM_OFFSET 0x0010 /* RTC ALARM Control Register */ -#define PIC32MX_RTCC_ALRMCLR_OFFSET 0x0014 /* RTC ALARM Control Clear Register */ -#define PIC32MX_RTCC_ALRMSET_OFFSET 0x0018 /* RTC ALARM Control Set Register */ -#define PIC32MX_RTCC_ALRMINV_OFFSET 0x001c /* RTC ALARM Control Invert Register */ -#define PIC32MX_RTCC_TIME_OFFSET 0x0020 /* RTC Time Value Register */ -#define PIC32MX_RTCC_TIMECLR_OFFSET 0x0024 /* RTC Time Value Clear Register */ -#define PIC32MX_RTCC_TIMESET_OFFSET 0x0028 /* RTC Time Value Set Register */ -#define PIC32MX_RTCC_TIMEINV_OFFSET 0x002c /* RTC Time Value Invert Register */ -#define PIC32MX_RTCC_DATE_OFFSET 0x0030 /* RTC Date Value Register */ -#define PIC32MX_RTCC_DATECLR_OFFSET 0x0034 /* RTC Date Value Clear Register */ -#define PIC32MX_RTCC_DATESET_OFFSET 0x0038 /* RTC Date Value Set Register */ -#define PIC32MX_RTCC_DATEINV_OFFSET 0x003c /* RTC Date Value Invert Register */ -#define PIC32MX_RTCC_ALRMTIME_OFFSET 0x0040 /* Alarm Time Value Register */ -#define PIC32MX_RTCC_ALRMTIMECLR_OFFSET 0x0044 /* Alarm Time Value Clear Register */ -#define PIC32MX_RTCC_ALRMTIMESET_OFFSET 0x0048 /* Alarm Time Value Set Register */ -#define PIC32MX_RTCC_ALRMTIMEINV_OFFSET 0x004c /* Alarm Time Value Invert Register */ -#define PIC32MX_RTCC_ALRMDATE_OFFSET 0x0050 /* Alarm Date Value Register */ -#define PIC32MX_RTCC_ALRMDATECLR_OFFSET 0x0054 /* Alarm Date Value Clear Register */ -#define PIC32MX_RTCC_ALRMDATESET_OFFSET 0x0058 /* Alarm Date Value Set Register */ -#define PIC32MX_RTCC_ALRMDATEINV_OFFSET 0x005c /* Alarm Date Value Invert Register */ - -/* Register Addresses ***********************************************************************/ - -#define PIC32MX_RTCC_CON (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CON_OFFSET) -#define PIC32MX_RTCC_CONCLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CONCLR_OFFSET) -#define PIC32MX_RTCC_CONSET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CONSET_OFFSET) -#define PIC32MX_RTCC_CONINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CONINV_OFFSET) -#define PIC32MX_RTCC_ALRM (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRM_OFFSET) -#define PIC32MX_RTCC_ALRMCLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMCLR_OFFSET) -#define PIC32MX_RTCC_ALRMSET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMSET_OFFSET) -#define PIC32MX_RTCC_ALRMINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMINV_OFFSET) -#define PIC32MX_RTCC_TIME (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_TIME_OFFSET) -#define PIC32MX_RTCC_TIMECLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_TIMECLR_OFFSET) -#define PIC32MX_RTCC_TIMESET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_TIMESET_OFFSET) -#define PIC32MX_RTCC_TIMEINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_TIMEINV_OFFSET) -#define PIC32MX_RTCC_DATE (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_DATE_OFFSET) -#define PIC32MX_RTCC_DATECLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_DATECLR_OFFSET) -#define PIC32MX_RTCC_DATESET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_DATESET_OFFSET) -#define PIC32MX_RTCC_DATEINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_DATEINV_OFFSET) -#define PIC32MX_RTCC_ALRMTIME (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMTIME_OFFSET) -#define PIC32MX_RTCC_ALRMTIMECLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMTIMECLR_OFFSET) -#define PIC32MX_RTCC_ALRMTIMESET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMTIMESET_OFFSET) -#define PIC32MX_RTCC_ALRMTIMEINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMTIMEINV_OFFSET) -#define PIC32MX_RTCC_ALRMDATE (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATE_OFFSET) -#define PIC32MX_RTCC_ALRMDATECLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATECLR_OFFSET) -#define PIC32MX_RTCC_ALRMDATESET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATESET_OFFSET) -#define PIC32MX_RTCC_ALRMDATEINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATEINV_OFFSET) - -/* Register Bit-Field Definitions ***********************************************************/ - -/* RTC Control Register */ - -#define RTCC_CON_CAL_SHIFT (16) /* Bits 16-25: RTC drift calibration */ -#define RTCC_CON_CAL_MASK (0x3ff << RTCC_CON_CAL_SHIFT) /* 10-bit 2's complement */ -# define RTCC_CON_CAL_MAX (0x1ff << RTCC_CON_CAL_SHIFT) -# define RTCC_CON_CAL_CENTER (0x000 << RTCC_CON_CAL_SHIFT) -# define RTCC_CON_CAL_MIN (0x200 << RTCC_CON_CAL_SHIFT) -#define RTCC_CON_ON (1 << 15) /* Bit 15: RTCC on */ -#define RTCC_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug mode */ -#define RTCC_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */ -#define RTCC_CON_RTSECSEL (1 << 9) /* Bit 7: RTCC seconds clock output select */ -#define RTCC_CON_RTCCLKON (1 << 8) /* Bit 6: RTCC clock enable status */ -#define RTCC_CON_RTCWREN (1 << 3) /* Bit 3: RTC value registers write enable */ -#define RTCC_CON_RTCSYNC (1 << 2) /* Bit 2: RTCC value registers read synchronization */ -#define RTCC_CON_HALFSEC (1 << 1) /* Bit 1: Half-second status */ -#define RTCC_CON_RTCOE (1 << 0) /* Bit 0: RTCC output enable */ - -/* RTC ALARM Control Register */ - -#define RTCC_ALRM_ARPT_SHIFT (0) /* Bits 0-7: Alarm repeat counter value */ -#define RTCC_ALRM_ARPT_MASK (0xff << RTCC_ALRM_ARPT_SHIFT) -#define RTCC_ALRM_AMASK_SHIFT (8) /* Bits 8-11: Alarm mask configuration */ -#define RTCC_ALRM_AMASK_MASK (15 << RTCC_ALRM_AMASK_SHIFT) -#define RTCC_ALRM_ALRMSYNC (1 << 12) /* Bit 12: Alarm sync */ -#define RTCC_ALRM_PIV (1 << 13) /* Bit 13: Alarm pulse initial value */ -#define RTCC_ALRM_CHIME (1 << 14) /* Bit 14: Chime enable */ -#define RTCC_ALRM_ALRMEN (1 << 15) /* Bit 15: Alarm enable */ - -/* RTC Time Value Register */ - -#define RTCC_TIME_SEC01_SHIFT (8) /* Bits 8-11: BCD seconds, 1 digit */ -#define RTCC_TIME_SEC01_MASK (15 << RTCC_TIME_SEC01_SHIFT) -#define RTCC_TIME_SEC10_SHIFT (12) /* Bits 12-14: BCD seconds, 10 digits */ -#define RTCC_TIME_SEC10_MASK (7 << RTCC_TIME_SEC10_SHIFT) -#define RTCC_TIME_MIN01_SHIFT (16) /* Bits 16-19: BCD minutes, 1 digit */ -#define RTCC_TIME_MIN01_MASK (15 << RTCC_TIME_MIN01_SHIFT) -#define RTCC_TIME_MIN10_SHIFT (20) /* Bits 20-22: BCD minutes, 10 digits */ -#define RTCC_TIME_MIN10_MASK (7 << RTCC_TIME_MIN10_SHIFT) -#define RTCC_TIME_HR01_SHIFT (24) /* Bits 24-27: BCD hours, 1 digit */ -#define RTCC_TIME_HR01_MASK (15 << RTCC_TIME_HR01_SHIFT) -#define RTCC_TIME_HR10_SHIFT (28) /* Bits 28-29: BCD hours, 10 digits */ -#define RTCC_TIME_HR10_MASK (3 << RTCC_TIME_HR10_SHIFT) - -/* RTC Date Value Register */ - -#define RTCC_DATE_WDAY01_SHIFT (0) /* Bits 0-2: BCD weekday, 1 digit */ -#define RTCC_DATE_WDAY01_MASK (7 << RTCC_DATE_WDAY01_SHIFT) -#define RTCC_DATE_DAY01_SHIFT (8) /* Bits 8-11: BCD day, 1 digit */ -#define RTCC_DATE_DAY01_MASK (15 << RTCC_DATE_DAY01_SHIFT) -#define RTCC_DATE_DAY10_SHIFT (12) /* Bits 12-13: BCD day, 10 digits */ -#define RTCC_DATE_DAY10_MASK (3 << RTCC_DATE_DAY10_SHIFT) -#define RTCC_DATE_MONTH01_SHIFT (16) /* Bits 16-19: BCD month, 1 digit */ -#define RTCC_DATE_MONTH01_MASK (15 << RTCC_DATE_MONTH01_SHIFT) -#define RTCC_DATE_MONTH10 (1 << 20) /* Bit 20: BCD month, 10 digits */ -#define RTCC_DATE_YEAR01_SHIFT (24) /* Bits 24-27: BCD year, 1 digit */ -#define RTCC_DATE_YEAR01_MASK (15 << RTCC_DATE_YEAR01_SHIFT) -#define RTCC_DATE_YEAR10_SHIFT (28) /* Bits 28-31: BCD year, 10 digits */ -#define RTCC_DATE_YEAR10_MASK (15 << RTCC_DATE_YEAR10_SHIFT) - -/* Alarm Time Value Register */ - -#define RTCC_ALRMTIME_SEC01_SHIFT (8) /* Bits 8-11: BCD seconds, 1 digit */ -#define RTCC_ALRMTIME_SEC01_MASK (15 << RTCC_ALRMTIME_SEC01_SHIFT) -#define RTCC_ALRMTIME_SEC10_SHIFT (12) /* Bits 12-14: BCD seconds, 1 digit */ -#define RTCC_ALRMTIME_SEC10_MASK (7 << RTCC_ALRMTIME_SEC10_SHIFT) -#define RTCC_ALRMTIME_MIN01_SHIFT (16) /* Bits 16-19: BCD minutes, 1 digit */ -#define RTCC_ALRMTIME_MIN01_MASK (15 << RTCC_ALRMTIME_MIN01_SHIFT) -#define RTCC_ALRMTIME_MIN10_SHIFT (20) /* Bits 20-22: BCD minutes, 1 digit */ -#define RTCC_ALRMTIME_MIN10_MASK (7 << RTCC_ALRMTIME_MIN10_SHIFT) -#define RTCC_ALRMTIME_HR01_SHIFT (24) /* Bits 24-27: BCD hours, 1 digit */ -#define RTCC_ALRMTIME_HR01_MASK (15 << RTCC_ALRMTIME_HR01_SHIFT) -#define RTCC_ALRMTIME_HR10_SHIFT (28) /* Bits 28-29: BCD hours, 1 digit */ -#define RTCC_ALRMTIME_HR10_MASK (3 << RTCC_ALRMTIME_HR10_SHIFT) - -/* Alarm Date Value Register */ - -#define RTCC_ALRMDATE_WDAY01_SHIFT (0) /* Bits 0-2: BCD weekday, 1 digit */ -#define RTCC_ALRMDATE_WDAY01_MASK (7 << RTCC_ALRMDATE_WDAY01_SHIFT) -#define RTCC_ALRMDATE_DAY01_SHIFT (8) /* Bits 8-11: BCD days, 1 digit */ -#define RTCC_ALRMDATE_DAY01_MASK (15 << RTCC_ALRMDATE_DAY01_SHIFT) -#define RTCC_ALRMDATE_DAY10_SHIFT (12) /* Bits 12-13: BCD days, 1 digit */ -#define RTCC_ALRMDATE_DAY10_MASK (3 << RTCC_ALRMDATE_DAY10_SHIFT) -#define RTCC_ALRMDATE_MONTH01_SHIFT (16) /* Bits 16-19: BCD month, 1 digit */ -#define RTCC_ALRMDATE_MONTH01_MASK (15 << RTCC_ALRMDATE_MONTH01_SHIFT) -#define RTCC_DATE_MONTH10 (1 << 20) /* Bit 20: BCD month, 10 digits */ - -/******************************************************************************************** - * Public Types - ********************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/******************************************************************************************** - * Inline Functions - ********************************************************************************************/ - -/******************************************************************************************** - * Public Function Prototypes - ********************************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RTCC_H */ +/******************************************************************************************** + * arch/mips/src/pic32mx/pic32mx-rtcc.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RTCC_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RTCC_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include "pic32mx-memorymap.h" + +/******************************************************************************************** + * Pre-Processor Definitions + ********************************************************************************************/ +/* Register Offsets *************************************************************************/ + +#define PIC32MX_RTCC_CON_OFFSET 0x0000 /* RTC Control Register */ +#define PIC32MX_RTCC_CONCLR_OFFSET 0x0004 /* RTC Control Clear Register */ +#define PIC32MX_RTCC_CONSET_OFFSET 0x0008 /* RTC Control Set Register */ +#define PIC32MX_RTCC_CONINV_OFFSET 0x000c /* RTC Control Invert Register */ +#define PIC32MX_RTCC_ALRM_OFFSET 0x0010 /* RTC ALARM Control Register */ +#define PIC32MX_RTCC_ALRMCLR_OFFSET 0x0014 /* RTC ALARM Control Clear Register */ +#define PIC32MX_RTCC_ALRMSET_OFFSET 0x0018 /* RTC ALARM Control Set Register */ +#define PIC32MX_RTCC_ALRMINV_OFFSET 0x001c /* RTC ALARM Control Invert Register */ +#define PIC32MX_RTCC_TIME_OFFSET 0x0020 /* RTC Time Value Register */ +#define PIC32MX_RTCC_TIMECLR_OFFSET 0x0024 /* RTC Time Value Clear Register */ +#define PIC32MX_RTCC_TIMESET_OFFSET 0x0028 /* RTC Time Value Set Register */ +#define PIC32MX_RTCC_TIMEINV_OFFSET 0x002c /* RTC Time Value Invert Register */ +#define PIC32MX_RTCC_DATE_OFFSET 0x0030 /* RTC Date Value Register */ +#define PIC32MX_RTCC_DATECLR_OFFSET 0x0034 /* RTC Date Value Clear Register */ +#define PIC32MX_RTCC_DATESET_OFFSET 0x0038 /* RTC Date Value Set Register */ +#define PIC32MX_RTCC_DATEINV_OFFSET 0x003c /* RTC Date Value Invert Register */ +#define PIC32MX_RTCC_ALRMTIME_OFFSET 0x0040 /* Alarm Time Value Register */ +#define PIC32MX_RTCC_ALRMTIMECLR_OFFSET 0x0044 /* Alarm Time Value Clear Register */ +#define PIC32MX_RTCC_ALRMTIMESET_OFFSET 0x0048 /* Alarm Time Value Set Register */ +#define PIC32MX_RTCC_ALRMTIMEINV_OFFSET 0x004c /* Alarm Time Value Invert Register */ +#define PIC32MX_RTCC_ALRMDATE_OFFSET 0x0050 /* Alarm Date Value Register */ +#define PIC32MX_RTCC_ALRMDATECLR_OFFSET 0x0054 /* Alarm Date Value Clear Register */ +#define PIC32MX_RTCC_ALRMDATESET_OFFSET 0x0058 /* Alarm Date Value Set Register */ +#define PIC32MX_RTCC_ALRMDATEINV_OFFSET 0x005c /* Alarm Date Value Invert Register */ + +/* Register Addresses ***********************************************************************/ + +#define PIC32MX_RTCC_CON (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CON_OFFSET) +#define PIC32MX_RTCC_CONCLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CONCLR_OFFSET) +#define PIC32MX_RTCC_CONSET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CONSET_OFFSET) +#define PIC32MX_RTCC_CONINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CONINV_OFFSET) +#define PIC32MX_RTCC_ALRM (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRM_OFFSET) +#define PIC32MX_RTCC_ALRMCLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMCLR_OFFSET) +#define PIC32MX_RTCC_ALRMSET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMSET_OFFSET) +#define PIC32MX_RTCC_ALRMINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMINV_OFFSET) +#define PIC32MX_RTCC_TIME (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_TIME_OFFSET) +#define PIC32MX_RTCC_TIMECLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_TIMECLR_OFFSET) +#define PIC32MX_RTCC_TIMESET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_TIMESET_OFFSET) +#define PIC32MX_RTCC_TIMEINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_TIMEINV_OFFSET) +#define PIC32MX_RTCC_DATE (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_DATE_OFFSET) +#define PIC32MX_RTCC_DATECLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_DATECLR_OFFSET) +#define PIC32MX_RTCC_DATESET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_DATESET_OFFSET) +#define PIC32MX_RTCC_DATEINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_DATEINV_OFFSET) +#define PIC32MX_RTCC_ALRMTIME (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMTIME_OFFSET) +#define PIC32MX_RTCC_ALRMTIMECLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMTIMECLR_OFFSET) +#define PIC32MX_RTCC_ALRMTIMESET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMTIMESET_OFFSET) +#define PIC32MX_RTCC_ALRMTIMEINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMTIMEINV_OFFSET) +#define PIC32MX_RTCC_ALRMDATE (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATE_OFFSET) +#define PIC32MX_RTCC_ALRMDATECLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATECLR_OFFSET) +#define PIC32MX_RTCC_ALRMDATESET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATESET_OFFSET) +#define PIC32MX_RTCC_ALRMDATEINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATEINV_OFFSET) + +/* Register Bit-Field Definitions ***********************************************************/ + +/* RTC Control Register */ + +#define RTCC_CON_CAL_SHIFT (16) /* Bits 16-25: RTC drift calibration */ +#define RTCC_CON_CAL_MASK (0x3ff << RTCC_CON_CAL_SHIFT) /* 10-bit 2's complement */ +# define RTCC_CON_CAL_MAX (0x1ff << RTCC_CON_CAL_SHIFT) +# define RTCC_CON_CAL_CENTER (0x000 << RTCC_CON_CAL_SHIFT) +# define RTCC_CON_CAL_MIN (0x200 << RTCC_CON_CAL_SHIFT) +#define RTCC_CON_ON (1 << 15) /* Bit 15: RTCC on */ +#define RTCC_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug mode */ +#define RTCC_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */ +#define RTCC_CON_RTSECSEL (1 << 9) /* Bit 7: RTCC seconds clock output select */ +#define RTCC_CON_RTCCLKON (1 << 8) /* Bit 6: RTCC clock enable status */ +#define RTCC_CON_RTCWREN (1 << 3) /* Bit 3: RTC value registers write enable */ +#define RTCC_CON_RTCSYNC (1 << 2) /* Bit 2: RTCC value registers read synchronization */ +#define RTCC_CON_HALFSEC (1 << 1) /* Bit 1: Half-second status */ +#define RTCC_CON_RTCOE (1 << 0) /* Bit 0: RTCC output enable */ + +/* RTC ALARM Control Register */ + +#define RTCC_ALRM_ARPT_SHIFT (0) /* Bits 0-7: Alarm repeat counter value */ +#define RTCC_ALRM_ARPT_MASK (0xff << RTCC_ALRM_ARPT_SHIFT) +#define RTCC_ALRM_AMASK_SHIFT (8) /* Bits 8-11: Alarm mask configuration */ +#define RTCC_ALRM_AMASK_MASK (15 << RTCC_ALRM_AMASK_SHIFT) +#define RTCC_ALRM_ALRMSYNC (1 << 12) /* Bit 12: Alarm sync */ +#define RTCC_ALRM_PIV (1 << 13) /* Bit 13: Alarm pulse initial value */ +#define RTCC_ALRM_CHIME (1 << 14) /* Bit 14: Chime enable */ +#define RTCC_ALRM_ALRMEN (1 << 15) /* Bit 15: Alarm enable */ + +/* RTC Time Value Register */ + +#define RTCC_TIME_SEC01_SHIFT (8) /* Bits 8-11: BCD seconds, 1 digit */ +#define RTCC_TIME_SEC01_MASK (15 << RTCC_TIME_SEC01_SHIFT) +#define RTCC_TIME_SEC10_SHIFT (12) /* Bits 12-14: BCD seconds, 10 digits */ +#define RTCC_TIME_SEC10_MASK (7 << RTCC_TIME_SEC10_SHIFT) +#define RTCC_TIME_MIN01_SHIFT (16) /* Bits 16-19: BCD minutes, 1 digit */ +#define RTCC_TIME_MIN01_MASK (15 << RTCC_TIME_MIN01_SHIFT) +#define RTCC_TIME_MIN10_SHIFT (20) /* Bits 20-22: BCD minutes, 10 digits */ +#define RTCC_TIME_MIN10_MASK (7 << RTCC_TIME_MIN10_SHIFT) +#define RTCC_TIME_HR01_SHIFT (24) /* Bits 24-27: BCD hours, 1 digit */ +#define RTCC_TIME_HR01_MASK (15 << RTCC_TIME_HR01_SHIFT) +#define RTCC_TIME_HR10_SHIFT (28) /* Bits 28-29: BCD hours, 10 digits */ +#define RTCC_TIME_HR10_MASK (3 << RTCC_TIME_HR10_SHIFT) + +/* RTC Date Value Register */ + +#define RTCC_DATE_WDAY01_SHIFT (0) /* Bits 0-2: BCD weekday, 1 digit */ +#define RTCC_DATE_WDAY01_MASK (7 << RTCC_DATE_WDAY01_SHIFT) +#define RTCC_DATE_DAY01_SHIFT (8) /* Bits 8-11: BCD day, 1 digit */ +#define RTCC_DATE_DAY01_MASK (15 << RTCC_DATE_DAY01_SHIFT) +#define RTCC_DATE_DAY10_SHIFT (12) /* Bits 12-13: BCD day, 10 digits */ +#define RTCC_DATE_DAY10_MASK (3 << RTCC_DATE_DAY10_SHIFT) +#define RTCC_DATE_MONTH01_SHIFT (16) /* Bits 16-19: BCD month, 1 digit */ +#define RTCC_DATE_MONTH01_MASK (15 << RTCC_DATE_MONTH01_SHIFT) +#define RTCC_DATE_MONTH10 (1 << 20) /* Bit 20: BCD month, 10 digits */ +#define RTCC_DATE_YEAR01_SHIFT (24) /* Bits 24-27: BCD year, 1 digit */ +#define RTCC_DATE_YEAR01_MASK (15 << RTCC_DATE_YEAR01_SHIFT) +#define RTCC_DATE_YEAR10_SHIFT (28) /* Bits 28-31: BCD year, 10 digits */ +#define RTCC_DATE_YEAR10_MASK (15 << RTCC_DATE_YEAR10_SHIFT) + +/* Alarm Time Value Register */ + +#define RTCC_ALRMTIME_SEC01_SHIFT (8) /* Bits 8-11: BCD seconds, 1 digit */ +#define RTCC_ALRMTIME_SEC01_MASK (15 << RTCC_ALRMTIME_SEC01_SHIFT) +#define RTCC_ALRMTIME_SEC10_SHIFT (12) /* Bits 12-14: BCD seconds, 1 digit */ +#define RTCC_ALRMTIME_SEC10_MASK (7 << RTCC_ALRMTIME_SEC10_SHIFT) +#define RTCC_ALRMTIME_MIN01_SHIFT (16) /* Bits 16-19: BCD minutes, 1 digit */ +#define RTCC_ALRMTIME_MIN01_MASK (15 << RTCC_ALRMTIME_MIN01_SHIFT) +#define RTCC_ALRMTIME_MIN10_SHIFT (20) /* Bits 20-22: BCD minutes, 1 digit */ +#define RTCC_ALRMTIME_MIN10_MASK (7 << RTCC_ALRMTIME_MIN10_SHIFT) +#define RTCC_ALRMTIME_HR01_SHIFT (24) /* Bits 24-27: BCD hours, 1 digit */ +#define RTCC_ALRMTIME_HR01_MASK (15 << RTCC_ALRMTIME_HR01_SHIFT) +#define RTCC_ALRMTIME_HR10_SHIFT (28) /* Bits 28-29: BCD hours, 1 digit */ +#define RTCC_ALRMTIME_HR10_MASK (3 << RTCC_ALRMTIME_HR10_SHIFT) + +/* Alarm Date Value Register */ + +#define RTCC_ALRMDATE_WDAY01_SHIFT (0) /* Bits 0-2: BCD weekday, 1 digit */ +#define RTCC_ALRMDATE_WDAY01_MASK (7 << RTCC_ALRMDATE_WDAY01_SHIFT) +#define RTCC_ALRMDATE_DAY01_SHIFT (8) /* Bits 8-11: BCD days, 1 digit */ +#define RTCC_ALRMDATE_DAY01_MASK (15 << RTCC_ALRMDATE_DAY01_SHIFT) +#define RTCC_ALRMDATE_DAY10_SHIFT (12) /* Bits 12-13: BCD days, 1 digit */ +#define RTCC_ALRMDATE_DAY10_MASK (3 << RTCC_ALRMDATE_DAY10_SHIFT) +#define RTCC_ALRMDATE_MONTH01_SHIFT (16) /* Bits 16-19: BCD month, 1 digit */ +#define RTCC_ALRMDATE_MONTH01_MASK (15 << RTCC_ALRMDATE_MONTH01_SHIFT) +#define RTCC_DATE_MONTH10 (1 << 20) /* Bit 20: BCD month, 10 digits */ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/******************************************************************************************** + * Inline Functions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Function Prototypes + ********************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RTCC_H */ diff --git a/arch/mips/src/pic32mx/pic32mx-timerisr.c b/arch/mips/src/pic32mx/pic32mx-timerisr.c index a3273e868cdca727e1919a19c511206bf7aa1763..126c2a7bceb7927e347daf89b9106051c1357ae7 100644 --- a/arch/mips/src/pic32mx/pic32mx-timerisr.c +++ b/arch/mips/src/pic32mx/pic32mx-timerisr.c @@ -2,7 +2,7 @@ * arch/mips/src/pic32mx/pic32mx_timerisr.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/mips/src/pic32mx/pic32mx-wdt.h b/arch/mips/src/pic32mx/pic32mx-wdt.h index e6dfeea937def46ed073ba7cbed2402cecb63234..5da30fa05ae70b27b513dc547c7d0485034ed59b 100644 --- a/arch/mips/src/pic32mx/pic32mx-wdt.h +++ b/arch/mips/src/pic32mx/pic32mx-wdt.h @@ -2,7 +2,7 @@ * arch/mips/src/pic32mx/pic32mx-wdt.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/rgmp/include/math.h b/arch/rgmp/include/math.h index 55f24aaa40632ca6d50425cfe316213fb14b3caf..16992d63c66013b21fca1be5616a1815304064d5 100644 --- a/arch/rgmp/include/math.h +++ b/arch/rgmp/include/math.h @@ -2,7 +2,7 @@ * arch/rgmp/include/math.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/rgmp/include/stdbool.h b/arch/rgmp/include/stdbool.h index 4af9ec9e33678bbdeebce37bc9cc22347ebcc60e..993e0f7361a8d2c7fdc4f8610c4c2f9cdd723da0 100644 --- a/arch/rgmp/include/stdbool.h +++ b/arch/rgmp/include/stdbool.h @@ -2,7 +2,7 @@ * arch/rgmp/include/stdbool.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/rgmp/include/stdint.h b/arch/rgmp/include/stdint.h index 7b244dd9f4467abb9ba53157d0981119a9d40b2e..07b9ffdeeb2d5d45e94daca6f34dc84ee1a27b33 100644 --- a/arch/rgmp/include/stdint.h +++ b/arch/rgmp/include/stdint.h @@ -2,7 +2,7 @@ * arch/rgmp/include/stdint.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/rgmp/include/types.h b/arch/rgmp/include/types.h index 48e141db3aa6d38a15601409cef000a873b16bac..81bf0e817a991ed57de85f041c394ee453352e23 100644 --- a/arch/rgmp/include/types.h +++ b/arch/rgmp/include/types.h @@ -2,7 +2,7 @@ * arch/rgmp/include/types.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/rgmp/src/x86/com.c b/arch/rgmp/src/x86/com.c index e5e7f70f6ad3785d61bd17d920440ba727afda28..6a136ac7d7b4040e72d36f81ed2a64d31905ee19 100644 --- a/arch/rgmp/src/x86/com.c +++ b/arch/rgmp/src/x86/com.c @@ -4,7 +4,7 @@ * Copyright (C) 2011 Yu Qiang. All rights reserved. * Copyright (C) 2011 Gregory Nutt. All rights reserved. * Authors: Yu Qiang - * Gregory Nutt + * Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/include/arch.h b/arch/sh/include/arch.h index 81853b12ea8f1b1a02ec8be17f0c9ae63f59d513..e277d9f386bb9a06d2c80beb1974c8ce9d8c5a0c 100644 --- a/arch/sh/include/arch.h +++ b/arch/sh/include/arch.h @@ -2,7 +2,7 @@ * arch/sh/include/arch.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/include/irq.h b/arch/sh/include/irq.h index 87c80e3497d70ac8a45e6fb24b69c224283bb438..cb8a345ee527393849c6f7936914d378ef451df0 100644 --- a/arch/sh/include/irq.h +++ b/arch/sh/include/irq.h @@ -2,7 +2,7 @@ * arch/sh/include/irq.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/include/limits.h b/arch/sh/include/limits.h index 18860b96ee9c848ea25491ee7a2cf06772fdf6e1..eeae7c5aab1fc8832f0380f96d46d1cc5b42b436 100644 --- a/arch/sh/include/limits.h +++ b/arch/sh/include/limits.h @@ -2,7 +2,7 @@ * arch/sh/include/limits.h * * Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/include/m16c/irq.h b/arch/sh/include/m16c/irq.h index 8809d06e61067714ee9a2022808ef931fdb576d2..b134428a7e4cc8e80f982587708145182d40c0fc 100644 --- a/arch/sh/include/m16c/irq.h +++ b/arch/sh/include/m16c/irq.h @@ -2,7 +2,7 @@ * arch/sh/include/m16c/irq.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/include/m16c/types.h b/arch/sh/include/m16c/types.h index 4f84a31132780033c9a4432dcc379a551b0e8fe9..bd23a9a5fa07648f51b87a0639d4f54a5b38631a 100644 --- a/arch/sh/include/m16c/types.h +++ b/arch/sh/include/m16c/types.h @@ -2,7 +2,7 @@ * arch/sh/include/m16c/types.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/include/serial.h b/arch/sh/include/serial.h index 09073e1449593d40b25f3af48e6daf7cf9e3ebdd..b91494e5021e17f9ee43934c7424942d962a7e8c 100644 --- a/arch/sh/include/serial.h +++ b/arch/sh/include/serial.h @@ -2,7 +2,7 @@ * arch/sh/include/serial.h * * Copyright (C) 2008, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/include/sh1/irq.h b/arch/sh/include/sh1/irq.h index a6b0fcbaee8b304bbf5cc1db44294cade57977d5..e4c7ce9909909c30baebe9f07ea660048692487f 100644 --- a/arch/sh/include/sh1/irq.h +++ b/arch/sh/include/sh1/irq.h @@ -2,7 +2,7 @@ * arch/sh/include/sh1/irq.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/include/sh1/types.h b/arch/sh/include/sh1/types.h index ac0769ecd50634d01808cea91efab9695b30784b..f9e31242df7646f6a25be8aa44fc2cd9f3bda538 100644 --- a/arch/sh/include/sh1/types.h +++ b/arch/sh/include/sh1/types.h @@ -2,7 +2,7 @@ * arch/sh/include/sh1/types.h * * Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/include/syscall.h b/arch/sh/include/syscall.h index 4cbfefec4c08784af63099ed6b37bc3cc4dadca4..7295005f07851e7f15037ee0255d26d1a9b78364 100644 --- a/arch/sh/include/syscall.h +++ b/arch/sh/include/syscall.h @@ -2,7 +2,7 @@ * arch/sh/include/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/include/types.h b/arch/sh/include/types.h index e50a71c00cb83d99938a8c7fcdd2edd68b8763bb..daec7c68217fbcbfdedebb7c291bdf65d5b539c8 100644 --- a/arch/sh/include/types.h +++ b/arch/sh/include/types.h @@ -2,7 +2,7 @@ * arch/sh/include/types.h * * Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/include/watchdog.h b/arch/sh/include/watchdog.h index 2b70dfc88abe89eaaa73f1cf7b8f915767848b1e..c69612b791050085b0f6734d5a67fabdffc83339 100644 --- a/arch/sh/include/watchdog.h +++ b/arch/sh/include/watchdog.h @@ -2,7 +2,7 @@ * arch/sh/include/watchdog.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_allocateheap.c b/arch/sh/src/common/up_allocateheap.c index 676634ed6c382b686ef8e65b6523aee8e5bcf815..e19b2c18e9a00942df159790b88aeb48f5c1e57d 100644 --- a/arch/sh/src/common/up_allocateheap.c +++ b/arch/sh/src/common/up_allocateheap.c @@ -2,7 +2,7 @@ * arch/sh/src/common/up_allocateheap.c * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_arch.h b/arch/sh/src/common/up_arch.h index ddc66fb7601f85aa2d0be05c2275e8cd3e59bbcc..c23d9dff166e0e06fe79e34f7f9e88a59090d908 100644 --- a/arch/sh/src/common/up_arch.h +++ b/arch/sh/src/common/up_arch.h @@ -2,7 +2,7 @@ * arch/sh/src/common/up_arch.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_assert.c b/arch/sh/src/common/up_assert.c index 95b87af6fe3951f25f3e9c8ed5a58bccb11b75ef..cfd7854dffa9c417b051bf0a52b986d7600619fd 100644 --- a/arch/sh/src/common/up_assert.c +++ b/arch/sh/src/common/up_assert.c @@ -2,7 +2,7 @@ * arch/sh/src/common/up_assert.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_blocktask.c b/arch/sh/src/common/up_blocktask.c index dc8c1a1fa74cb06559132d031ed551b4fde4b86f..0a53b6633ea46f19099a01859cf22a9047268372 100644 --- a/arch/sh/src/common/up_blocktask.c +++ b/arch/sh/src/common/up_blocktask.c @@ -2,7 +2,7 @@ * arch/sh/src/common/up_blocktask.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_createstack.c b/arch/sh/src/common/up_createstack.c index 37346b84b3a747473acd8fbc3741725750cc52bc..f80e4f7c0065aab7e2fe05277e9f48cb1a66cdfa 100644 --- a/arch/sh/src/common/up_createstack.c +++ b/arch/sh/src/common/up_createstack.c @@ -2,7 +2,7 @@ * arch/sh/src/common/up_createstack.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_doirq.c b/arch/sh/src/common/up_doirq.c index 0ec82b7d9d7d7b44e65d359b17ebe24e5621c10f..717196682b752ef936d562726c3eae219270c938 100644 --- a/arch/sh/src/common/up_doirq.c +++ b/arch/sh/src/common/up_doirq.c @@ -2,7 +2,7 @@ * arch/sh/src/common/up_doirq.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_exit.c b/arch/sh/src/common/up_exit.c index fc1991db13ef13283bad53a6f9ea4e7e9fc21b94..84a44a7057926acf4aeac0d908944267d61c7e90 100644 --- a/arch/sh/src/common/up_exit.c +++ b/arch/sh/src/common/up_exit.c @@ -2,7 +2,7 @@ * common/up_exit.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_idle.c b/arch/sh/src/common/up_idle.c index f95f019aec35bc3bdeb8652e7e13bb404034317c..71c4ff1d15aaebf5f643b4ee12f5e7bf9436b3d1 100644 --- a/arch/sh/src/common/up_idle.c +++ b/arch/sh/src/common/up_idle.c @@ -2,7 +2,7 @@ * arch/sh/src/common/up_idle.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_interruptcontext.c b/arch/sh/src/common/up_interruptcontext.c index 16b443619e37fb1057ca14222ba33e15bedef97a..19a7997b10186cdb4e7188fcf9692a4d20fa9ff2 100644 --- a/arch/sh/src/common/up_interruptcontext.c +++ b/arch/sh/src/common/up_interruptcontext.c @@ -2,7 +2,7 @@ * arch/sh/src/common/up_interruptcontext.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_lowputs.c b/arch/sh/src/common/up_lowputs.c index 54438835d0ac719e8f42ff21a1b1a5d44e5b104b..88cc240689ed692d7c1e5e43441774a2bbba664e 100644 --- a/arch/sh/src/common/up_lowputs.c +++ b/arch/sh/src/common/up_lowputs.c @@ -2,7 +2,7 @@ * arch/sh/src/common/up_lowputs.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_mdelay.c b/arch/sh/src/common/up_mdelay.c index 5d3958700ce036368fd277b4999541eaaaeaf0bd..8ea915886d28af51891b704c03770c4bbbbd12cc 100644 --- a/arch/sh/src/common/up_mdelay.c +++ b/arch/sh/src/common/up_mdelay.c @@ -2,7 +2,7 @@ * arch/sh/src/common/up_mdelay.c * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_puts.c b/arch/sh/src/common/up_puts.c index d22b22e71474f9697740b7826fae7c4641d80be3..e17338039f650bb23fa5bacca11b7edfa0ae57fc 100644 --- a/arch/sh/src/common/up_puts.c +++ b/arch/sh/src/common/up_puts.c @@ -2,7 +2,7 @@ * arch/sh/src/common/up_puts.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_releasepending.c b/arch/sh/src/common/up_releasepending.c index 2f54e0249f44a533fbdc0257981942c2516f9b85..955febea1489ace0285070d71eeb7ca693e471c5 100644 --- a/arch/sh/src/common/up_releasepending.c +++ b/arch/sh/src/common/up_releasepending.c @@ -2,7 +2,7 @@ * arch/sh/src/common/up_releasepending.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_releasestack.c b/arch/sh/src/common/up_releasestack.c index b8c9fb8bbfd7f8ba6d864ccb72ddd7a9e5ba531c..bb6739433be2a248f33f0ff3a39b2c16201c65e1 100644 --- a/arch/sh/src/common/up_releasestack.c +++ b/arch/sh/src/common/up_releasestack.c @@ -2,7 +2,7 @@ * arch/sh/src/common/up_releasestack.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_reprioritizertr.c b/arch/sh/src/common/up_reprioritizertr.c index 58a142563e05a79efc413734bd7eaf73032a0b09..728cafdf305d5dfc5f96b24c0f3962f3d2395916 100644 --- a/arch/sh/src/common/up_reprioritizertr.c +++ b/arch/sh/src/common/up_reprioritizertr.c @@ -2,7 +2,7 @@ * arch/sh/src/common/up_reprioritizertr.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_udelay.c b/arch/sh/src/common/up_udelay.c index 097cbb9e65475e60a37fd4fc10574e16951ea4ac..4ec4b09488e3f88ce3822fcc04d830ce318a1655 100644 --- a/arch/sh/src/common/up_udelay.c +++ b/arch/sh/src/common/up_udelay.c @@ -2,7 +2,7 @@ * arch/sh/src/common/up_udelay.c * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_unblocktask.c b/arch/sh/src/common/up_unblocktask.c index 6421c5619454bebd817542a9e02d7f5b8ab4d1b2..5841f50adbdda3b52c72827f4ebf00549a4229c5 100644 --- a/arch/sh/src/common/up_unblocktask.c +++ b/arch/sh/src/common/up_unblocktask.c @@ -2,7 +2,7 @@ * arch/sh/src/common/up_unblocktask.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/common/up_usestack.c b/arch/sh/src/common/up_usestack.c index 6b472b8a2957ca1ef3651850da8ec73a08c3933b..41367ce0b28fe02ad284724f99b1d5a8974ab9c9 100644 --- a/arch/sh/src/common/up_usestack.c +++ b/arch/sh/src/common/up_usestack.c @@ -2,7 +2,7 @@ * arch/sh/src/common/up_usestack.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/m16c/Make.defs b/arch/sh/src/m16c/Make.defs index 5c4b2ea8a95a4cdae53cead59092c76b61f2ef73..6d5877b8b6d1c2af225a3c7a330fc920b5f00a5f 100644 --- a/arch/sh/src/m16c/Make.defs +++ b/arch/sh/src/m16c/Make.defs @@ -2,7 +2,7 @@ # arch/sh/src/m16c/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/sh/src/m16c/chip.h b/arch/sh/src/m16c/chip.h index 32d04b26e572c42c15f43ee0f06bd0fcb687e4c6..0a91d6041e5c1aae38eb1a5d6a948dfb9c237968 100644 --- a/arch/sh/src/m16c/chip.h +++ b/arch/sh/src/m16c/chip.h @@ -2,7 +2,7 @@ * arch/sh/src/m16c/chip.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/m16c/m16c_copystate.c b/arch/sh/src/m16c/m16c_copystate.c index 3c1748549b861edc4f335f9a7452fda89ae67f35..5ba40e294e293f13aa7671f8786448b6d95dd13b 100644 --- a/arch/sh/src/m16c/m16c_copystate.c +++ b/arch/sh/src/m16c/m16c_copystate.c @@ -2,7 +2,7 @@ * arch/sh/src/m16c/up_copystate.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/m16c/m16c_dumpstate.c b/arch/sh/src/m16c/m16c_dumpstate.c index eeae392d4f3ede3f69aa2ed8c878c57f3b7b451b..438ff21d2b1372e53b5f10715ef1d07bdb4fcb51 100755 --- a/arch/sh/src/m16c/m16c_dumpstate.c +++ b/arch/sh/src/m16c/m16c_dumpstate.c @@ -2,7 +2,7 @@ * arch/sh/src/m16c/m16c_assert.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/m16c/m16c_initialstate.c b/arch/sh/src/m16c/m16c_initialstate.c index deb6dd304fed14b28afc58b486c4073168d26b6b..f667cf557264963e9635d8f1e4d586c97bbdcbc4 100644 --- a/arch/sh/src/m16c/m16c_initialstate.c +++ b/arch/sh/src/m16c/m16c_initialstate.c @@ -2,7 +2,7 @@ * arch/sh/src/m16c/m16c_initialstate.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/m16c/m16c_irq.c b/arch/sh/src/m16c/m16c_irq.c index 5cfb43e8dc98814bb6c75d6452c28db95609d533..b62f55b547b9cacc0bca8c5199e6a5040eeb9c99 100644 --- a/arch/sh/src/m16c/m16c_irq.c +++ b/arch/sh/src/m16c/m16c_irq.c @@ -2,7 +2,7 @@ * arch/sh/src/m16c/m16c_irq.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/m16c/m16c_lowputc.c b/arch/sh/src/m16c/m16c_lowputc.c index 4651e617ed9ef1083fd7cb185ffb98ee72ecc780..a473351f3f9c21c733568cd9940b140f302dc7de 100644 --- a/arch/sh/src/m16c/m16c_lowputc.c +++ b/arch/sh/src/m16c/m16c_lowputc.c @@ -2,7 +2,7 @@ * arch/sh/src/m16c/m16c_lowputc.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/m16c/m16c_schedulesigaction.c b/arch/sh/src/m16c/m16c_schedulesigaction.c index d921fca01ebf161b2cc562b3f8dcc9f386a77baa..0dc33568d22af2f75df55d5a60066832a498023c 100644 --- a/arch/sh/src/m16c/m16c_schedulesigaction.c +++ b/arch/sh/src/m16c/m16c_schedulesigaction.c @@ -2,7 +2,7 @@ * arch/sh/src/m16c/m16c_schedulesigaction.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/m16c/m16c_sigdeliver.c b/arch/sh/src/m16c/m16c_sigdeliver.c index 848249721a33576ada968dd85c75ea8200d85a45..958ff56af62a48fada4b54dd9febd6c343755953 100644 --- a/arch/sh/src/m16c/m16c_sigdeliver.c +++ b/arch/sh/src/m16c/m16c_sigdeliver.c @@ -2,7 +2,7 @@ * arch/sh/src/m16c/m16c_sigdeliver.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/m16c/m16c_timer.h b/arch/sh/src/m16c/m16c_timer.h index 22cc31682808de8a5f7945980c5b28e54109a6c4..a3d0b0377feb07385f5dbc40a86198eb14f39b37 100644 --- a/arch/sh/src/m16c/m16c_timer.h +++ b/arch/sh/src/m16c/m16c_timer.h @@ -2,7 +2,7 @@ * arch/sh/src/m16c/m16c_timer.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/m16c/m16c_timerisr.c b/arch/sh/src/m16c/m16c_timerisr.c index 4a7493cd6d123bb81da50578d8133aea2c57e8e3..ee61d76019026e6cc64a7bd8cb7f80047e36bad8 100644 --- a/arch/sh/src/m16c/m16c_timerisr.c +++ b/arch/sh/src/m16c/m16c_timerisr.c @@ -2,7 +2,7 @@ * arch/sh/src/m16c/m16c_timerisr.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/m16c/m16c_uart.h b/arch/sh/src/m16c/m16c_uart.h index 38f41ac28a8130df32ce301602feb1a0118718a4..4996d97d3db585b96e2011cf130d3f3f08a320c9 100644 --- a/arch/sh/src/m16c/m16c_uart.h +++ b/arch/sh/src/m16c/m16c_uart.h @@ -2,7 +2,7 @@ * arch/sh/src/m16c/m16c_uart.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/m16c/m16c_vectors.S b/arch/sh/src/m16c/m16c_vectors.S index a07b2ab015a2ad9e013a342c590c5f0520dab6da..8a99148e49c301d1e5fabc2f9f0d37b63e5677a1 100644 --- a/arch/sh/src/m16c/m16c_vectors.S +++ b/arch/sh/src/m16c/m16c_vectors.S @@ -2,7 +2,7 @@ * arch/sh/src/m16c/m16c_vectors.S * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/sh1/Make.defs b/arch/sh/src/sh1/Make.defs index aaa6bebe082ed376e878087ebaf445d4fcea19cc..d75fdf70d7d024a0ff48ea1f4d8b56bedbce98a6 100644 --- a/arch/sh/src/sh1/Make.defs +++ b/arch/sh/src/sh1/Make.defs @@ -2,7 +2,7 @@ # arch/sh/src/sh1/Make.defs # # Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/sh/src/sh1/chip.h b/arch/sh/src/sh1/chip.h index e907bbd421fc40d36b8eca11075fae5ee024d0a7..b679fe86618f2c4238093b766777f7914baa2170 100644 --- a/arch/sh/src/sh1/chip.h +++ b/arch/sh/src/sh1/chip.h @@ -2,7 +2,7 @@ * arch/sh/src/sh1/chip.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/sh1/sh1_703x.h b/arch/sh/src/sh1/sh1_703x.h index b79bbb0395e3d7a52c713cf3d538bf8b479e81ad..92fcd92bf62bbf19507b3cc6f254b4021a35f056 100644 --- a/arch/sh/src/sh1/sh1_703x.h +++ b/arch/sh/src/sh1/sh1_703x.h @@ -1,475 +1,475 @@ -/************************************************************************************ - * arch/sh/src/sh1/sh1_703x.h - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_SH_SRC_SH1_703X_H -#define __ARCH_SH_SRC_SH1_703X_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* Memory-mapped register addresses *************************************************/ - -/* Serial Communications interface (SCI) */ - -#define SH1_SCI0_BASE (0x05fffec0) -#define SH1_SCI1_BASE (0x05fffec8) - -#define SH1_SCI_SMR_OFFSET (0) /* Serial Mode Register (8-bits wide) */ -#define SH1_SCI_BRR_OFFSET (1) /* Bit Rate Register (8-bits wide) */ -#define SH1_SCI_SCR_OFFSET (2) /* Serial Control Register (8-bits wide) */ -#define SH1_SCI_TDR_OFFSET (3) /* Transmit Data Register (8-bits wide) */ -#define SH1_SCI_SSR_OFFSET (4) /* Serial Status Register (8-bits wide) */ -#define SH1_SCI_RDR_OFFSET (5) /* Receive Data Register (8-bits wide) */ - -#define SH1_SCI0_SMR (SH1_SCI0_BASE+SH1_SCI_SMR_OFFSET) -#define SH1_SCI0_BRR (SH1_SCI0_BASE+SH1_SCI_BRR_OFFSET) -#define SH1_SCI0_SCR (SH1_SCI0_BASE+SH1_SCI_SCR_OFFSET) -#define SH1_SCI0_TDR (SH1_SCI0_BASE+SH1_SCI_TDR_OFFSET) -#define SH1_SCI0_SSR (SH1_SCI0_BASE+SH1_SCI_SSR_OFFSET) -#define SH1_SCI0_RDR (SH1_SCI0_BASE+SH1_SCI_RDR_OFFSET) - -#define SH1_SCI1_SMR (SH1_SCI1_BASE+SH1_SCI_SMR_OFFSET) -#define SH1_SCI1_BRR (SH1_SCI1_BASE+SH1_SCI_BRR_OFFSET) -#define SH1_SCI1_SCR (SH1_SCI1_BASE+SH1_SCI_SCR_OFFSET) -#define SH1_SCI1_TDR (SH1_SCI1_BASE+SH1_SCI_TDR_OFFSET) -#define SH1_SCI1_SSR (SH1_SCI1_BASE+SH1_SCI_SSR_OFFSET) -#define SH1_SCI1_RDR (SH1_SCI1_BASE+SH1_SCI_RDR_OFFSET) - -/* A/D */ - -#define SH1_AD_ADDRA (0x05fffee0) /* 16-bits wide */ -#define SH1_AD_DRAH (0x05fffee0) /* 8-bits wide */ -#define SH1_AD_DRAL (0x05fffee1) /* 8-bits wide */ -#define SH1_AD_DRB (0x05fffee2) /* 16-bits wide */ -#define SH1_AD_DRBH (0x05fffee2) /* 8-bits wide */ -#define SH1_AD_DRBL (0x05fffee3) /* 8-bits wide */ -#define SH1_AD_DRC (0x05fffee4) /* 16-bits wide */ -#define SH1_AD_DRCH (0x05fffee4) /* 8-bits wide */ -#define SH1_AD_DRCL (0x05fffee5) /* 8-bits wide */ -#define SH1_AD_DRD (0x05fffee6) /* 16-bits wide */ -#define SH1_AD_DRDH (0x05fffee6) /* 8-bits wide */ -#define SH1_AD_DRDL (0x05fffee7) /* 8-bits wide */ -#define SH1_AD_CSR (0x05fffee8) /* 8-bits wide */ -#define SH1_AD_CR (0x05fffee9) /* 8-bits wide */ - -/* Integrated Timer/Pulse Unit (ITU) */ - -/* ITU shared */ - -#define SH1_ITU_TSTR (0x05ffff00) /* 8-bits wide */ -#define SH1_ITU_TSNC (0x05ffff01) /* 16-bits wide */ -#define SH1_ITU_TMDR (0x05ffff02) /* 16-bits wide */ -#define SH1_ITU_TFCR (0x05ffff03) /* 16-bits wide */ - -/* ITU channel 0 */ - -#define SH1_ITU0_TCR (0x05ffff04) /* 8-bits wide */ -#define SH1_ITU0_TIOR (0x05ffff05) /* 8-bits wide */ -#define SH1_ITU0_TIER (0x05ffff06) /* 8-bits wide */ -#define SH1_ITU0_TSR (0x05ffff07) /* 8-bits wide */ -#define SH1_ITU0_TCNT (0x05ffff08) /* 16-bits wide */ -#define SH1_ITU0_GRA (0x05ffff0a) /* 16-bits wide */ -#define SH1_ITU0_GRB (0x05ffff0c) /* 16-bits wide */ - -/* ITU channel 1 */ - -#define SH1_ITU1_TCR (0x05ffff0e) /* 8-bits wide */ -#define SH1_ITU1_TIOR (0x05ffff0f) /* 8-bits wide */ -#define SH1_ITU1_TIER (0x05ffff10) /* 8-bits wide */ -#define SH1_ITU1_TSR (0x05ffff11) /* 8-bits wide */ -#define SH1_ITU1_TCNT (0x05ffff12) /* 16-bits wide */ -#define SH1_ITU1_GRA (0x05ffff14) /* 16-bits wide */ -#define SH1_ITU1_GRB (0x05ffff16) /* 16-bits wide */ - -/* ITU channel 2 */ - -#define SH1_ITU2_TCR (0x05ffff18) /* 8-bits wide */ -#define SH1_ITU2_TIOR (0x05ffff19) /* 8-bits wide */ -#define SH1_ITU2_TIER (0x05ffff1a) /* 8-bits wide */ -#define SH1_ITU2_TSR (0x05ffff1b) /* 8-bits wide */ -#define SH1_ITU2_TCNT (0x05ffff1c) /* 16-bits wide */ -#define SH1_ITU2_GRA (0x05ffff1e) /* 16-bits wide */ -#define SH1_ITU2_GRB (0x05ffff20) /* 16-bits wide */ - -/* ITU channel 3 */ - -#define SH1_ITU3_TCR (0x05ffff22) /* 8-bits wide */ -#define SH1_ITU3_TIOR (0x05ffff23) /* 8-bits wide */ -#define SH1_ITU3_TIER (0x05ffff24) /* 8-bits wide */ -#define SH1_ITU3_TSR (0x05ffff25) /* 8-bits wide */ -#define SH1_ITU3_TCNT (0x05ffff26) /* 16-bits wide */ -#define SH1_ITU3_GRA (0x05ffff28) /* 16-bits wide */ -#define SH1_ITU3_GRB (0x05ffff2a) /* 16-bits wide */ -#define SH1_ITU3_BRA (0x05ffff2c) /* 16-bits wide */ -#define SH1_ITU3_BRB3 (0x05ffff2e) /* 16-bits wide */ - -/* ITU channels 0-4 shared */ - -#define SH1_ITU_TOCR (0x05ffff31) /* 8-bits wide */ - -/* ITU channel 4 */ - -#define SH1_ITU4_TCR (0x05ffff32) /* 8-bits wide */ -#define SH1_ITU4_TIOR (0x05ffff33) /* 8-bits wide */ -#define SH1_ITU4_TIER (0x05ffff34) /* 8-bits wide */ -#define SH1_ITU4_TSR (0x05ffff35) /* 8-bits wide */ -#define SH1_ITU4_TCNT (0x05ffff36) /* 16-bits wide */ -#define SH1_ITU4_GRA (0x05ffff38) /* 16-bits wide */ -#define SH1_ITU4_GRB (0x05ffff3a) /* 16-bits wide */ -#define SH1_ITU4_BRA (0x05ffff3c) /* 16-bits wide */ -#define SH1_ITU4_BRB (0x05ffff3e) /* 16-bits wide */ - -/* DMA controller (DMAC) */ - -/* DMAC channels 0-3 shared */ - -#define SH1_DMAOR (0x05ffff48) /* 16-bits wide */ - -/* DMAC channel 0 */ - -#define SH1_DMA0_SAR0 (0x05ffff40) /* 32-bits wide */ -#define SH1_DMA0_DAR0 (0x05ffff44) /* 32-bits wide */ -#define SH1_DMA0_TCR0 (0x05ffff4a) /* 16-bits wide */ -#define SH1_DMA0_CHCR0 (0x05ffff4e) /* 16-bits wide */ - -/* DMAC channel 1 */ - -#define SH1_DMA1_SAR (0x05ffff50) /* 32-bits wide */ -#define SH1_DMA1_DAR (0x05ffff54) /* 32-bits wide */ -#define SH1_DMA1_TCR (0x05fffF5a) /* 16-bits wide */ -#define SH1_DMA1_CHCR (0x05ffff5e) /* 16-bits wide */ - -/* DMAC channel 2 */ - -#define SH1_DMA2_SAR (0x05ffff60) /* 32-bits wide */ -#define SH1_DMA2_DAR (0x05ffff64) /* 32-bits wide */ -#define SH1_DMA2_TCR (0x05fffF6a) /* 16-bits wide */ -#define SH1_DMA2_CHCR (0x05ffff6e) /* 16-bits wide */ - -/* DMAC channel 3 */ - -#define SH1_DMA3_SAR (0x05ffff70) /* 32-bits wide */ -#define SH1_DMA3_DAR (0x05ffff74) /* 32-bits wide */ -#define SH1_DMA3_TCR (0x05fffF7a) /* 16-bits wide */ -#define SH1_DMA3_CHCR (0x05ffff7e) /* 16-bits wide */ - -/* Interrupt Controller (INTC) */ - -#define SH1_INTC_IPRA (0x05ffff84) /* Interrupt priority register A (16-bits wide) */ -#define SH1_INTC_IPRB (0x05ffff86) /* Interrupt priority register B (16-bits wide) */ -#define SH1_INTC_IPRC (0x05ffff88) /* Interrupt priority register C (16-bits wide) */ -#define SH1_INTC_IPRD (0x05ffff8a) /* Interrupt priority register D (16-bits wide) */ -#define SH1_INTC_IPRE (0x05ffff8c) /* Interrupt priority register E (16-bits wide) */ -#define SH1_INTC_ICR (0x05ffff8e) /* Interrupt control register (16-bits wide) */ - -/* User Break Controller (UBC) */ - -#define SH1_UBC_BARH (0x05ffff90) /* 16-bits wide */ -#define SH1_UBC_BARL (0x05ffff92) /* 16-bits wide */ -#define SH1_UBC_BAMRH (0x05ffff94) /* 16-bits wide */ -#define SH1_UBC_BAMRL (0x05ffff96) /* 16-bits wide */ -#define SH1_UBC_BBR (0x05ffff98) /* 16-bits wide */ - -/* Bus State Controller (BSC) */ - -#define SH1_BSC_BCR (0x05ffffa0) /* 16-bits wide */ -#define SH1_BSC_WCR1 (0x05ffffa2) /* 16-bits wide */ -#define SH1_BSC_WCR2 (0x05ffffa4) /* 16-bits wide */ -#define SH1_BSC_WCR3 (0x05ffffa6) /* 16-bits wide */ -#define SH1_BSC_DCR (0x05ffffa8) /* 16-bits wide */ -#define SH1_BSC_PCR (0x05ffffaa) /* 16-bits wide */ -#define SH1_BSC_RCR (0x05ffffac) /* 16-bits wide */ -#define SH1_BSC_RTCSR (0x05ffffae) /* 16-bits wide */ -#define SH1_BSC_RTCNT (0x05ffffb0) /* 16-bits wide */ -#define SH1_BSC_RTCOR (0x05ffffb2) /* 16-bits wide */ - -/* Watchdog Timer (WDT) */ - -#define SH1_WDT_TCSR (0x05ffffb8) /* 8-bits wide */ -#define SH1_WDT_TCNT (0x05ffffb9) /* 8-bits wide */ -#define SH1_WDT_RSTCSR (0x05ffffbb) /* 8-bits wide */ - -/* Power down state */ - -#define SH1_PDT_SBYCR (0x05ffffbc) /* 8-bits wide */ - -/* Port A */ - -#define SH1_PORTA_DR (0x05ffffc0) /* 16-bits wide */ - -/* Port B */ - -#define SH1_PORTB_DR (0x05ffffc2) /* 16-bits wide */ - -/* Pin Function Controller (PFC) */ - -#define SH1_PFC_PAIOR (0x05ffffc4) /* Port B I/O register (16-bits wide) */ -#define SH1_PFC_PBIOR (0x05ffffc6) /* Port B I/O register (16-bits wide) */ -#define SH1_PFC_PACR1 (0x05ffffc8) /* Port A control register 1 (16-bits wide) */ -#define SH1_PFC_PACR2 (0x05ffffca) /* Port A control register 2 (16-bits wide) */ -#define SH1_PFC_PBCR1 (0x05ffffcc) /* Port B control register 1 (16-bits wide) */ -#define SH1_PFC_PBCR2 (0x05ffffce) /* Port B control register 2 )16-bits wide) */ - -/* Port C */ - -#define SH1_PORTC_DR (0x05ffffd0) /* 16-bits wide */ - -/* Pin Function Controller (PFC, cont'd) */ - -#define SH1_PFC_CASCR (0x05ffffee) /* 16-bits wide */ - -/* Timing Pattern Controller (TPC) */ - -#define SH1_TPC_TPMR (0x05fffff0) /* 16-bits wide */ -#define SH1_TPC_TPCR (0x05fffff1) /* 16-bits wide */ -#define SH1_TPC_NDERH (0x05fffff2) /* 16-bits wide */ -#define SH1_TPC_NDERL (0x05fffff3) /* 16-bits wide */ -#define SH1_TPC_NDRB0 (0x05fffff4) /* 8-bits wide */ -#define SH1_TPC_NDRA0 (0x05fffff5) /* 8-bits wide */ -#define SH1_TPC_NDRB1 (0x05fffff6) /* 8-bits wide */ -#define SH1_TPC_NDRA1 (0x05fffff7) /* 8-bits wide */ - -/* Register bit definitions *********************************************************/ - -/* Serial Communications interface (SCI) */ - -#define SH1_SCISMR_CKSMASK (0x03) /* Bit 0-1: Internal clock source */ -#define SH1_SCISMR_DIV1 (0x00) /* System clock (phi) */ -#define SH1_SCISMR_DIV4 (0x01) /* phi/4 */ -#define SH1_SCISMR_DIV16 (0x02) /* phi/16 */ -#define SH1_SCISMR_DIV64 (0x03) /* phi/64 */ -#define SH1_SCISMR_MP (0x04) /* Bit 2: Multiprocessor select */ -#define SH1_SCISMR_STOP (0x08) /* Bit 3: 0:One stop bit, 1:Two stop bits */ -#define SH1_SCISMR_OE (0x10) /* Bit 4: 0:Even parity, 1:Odd parity */ -#define SH1_SCISMR_PE (0x20) /* Bit 5: Parity enable */ -#define SH1_SCISMR_CHR (0x40) /* Bit 6: 0:8-bit data, 1:7-bit data */ -#define SH1_SCISMR_CA (0x80) /* Bit 7: 0:Asynchronous, 1:clocked synchronous */ - -#define SH1_SCISCR_CKEMASK (0x03) /* Bit 0-1: Internal clock source */ - /* Asynchronous mode: */ -#define SH1_SCISCR_AISIN (0x00) /* Internal clock, SCK pin used for input pin */ -#define SH1_SCISCR_AISOUT (0x01) /* Internal clock, SCK pin used for clock output */ -#define SH1_SCISCR_AXSIN1 (0x02) /* External clock, SCK pin used for clock input */ -#define SH1_SCISCR_AXSIN2 (0x03) /* External clock, SCK pin used for clock input */ - /* Synchronous mode: */ -#define SH1_SCISCR_SISOUT1 (0x00) /* Internal clock, SCK pin used for input pin */ -#define SH1_SCISCR_SISOUT2 (0x01) /* Internal clock, SCK pin used for clock output */ -#define SH1_SCISCR_SXSIN1 (0x02) /* External clock, SCK pin used for clock input */ -#define SH1_SCISCR_SXSIN2 (0x03) /* External clock, SCK pin used for clock input */ -#define SH1_SCISCR_TEIE (0x04) /* Bit 2: 1=Transmit end interrupt enable */ -#define SH1_SCISCR_MPIE (0x08) /* Bit 3: 1=Multiprocessor interrupt enable */ -#define SH1_SCISCR_RE (0x10) /* Bit 4: 1=Receiver enable */ -#define SH1_SCISCR_TE (0x20) /* Bit 5: 1=Transmitter enable */ -#define SH1_SCISCR_RIE (0x40) /* Bit 6: 1=Recieve-data-full interrupt enable */ -#define SH1_SCISCR_TIE (0x80) /* Bit 7: 1=Transmit-data-empty interrupt enable */ -#define SH1_SCISCR_ALLINTS (0xcc) - -#define SH1_SCISSR_MPBT (0x01) /* Bit 0: Multi-processor Bit in Transmit data */ -#define SH1_SCISSR_MPB (0x02) /* Bit 1: Multi-processor Bit in receive data */ -#define SH1_SCISSR_TEND (0x04) /* Bit 2: End of transmission */ -#define SH1_SCISSR_PER (0x08) /* Bit 3: Receive parity error */ -#define SH1_SCISSR_FER (0x10) /* Bit 4: Receive framing error */ -#define SH1_SCISSR_ORER (0x20) /* Bit 5: Receive overrun error */ -#define SH1_SCISSR_RDRF (0x40) /* Bit 6: RDR contains valid received data */ -#define SH1_SCISSR_TDRE (0x80) /* Bit 7: TDR does not contain valid transmit data */ - -/* Integrated Timer unit (ITU) */ - -#define SH1_ITUTSTR_STR0 (0x01) /* Bit 0: TCNT0 is counting */ -#define SH1_ITUTSTR_STR1 (0x02) /* Bit 1: TCNT1 is counting */ -#define SH1_ITUTSTR_STR2 (0x04) /* Bit 2: TCNT2 is counting */ -#define SH1_ITUTSTR_STR3 (0x08) /* Bit 3: TCNT3 is counting */ -#define SH1_ITUTSTR_STR4 (0x10) /* Bit 4: TCNT4 is counting */ - -#define SH1_ITUTSNC_SYNC0 (0x01) /* Bit 0: Channel 0 operates synchronously */ -#define SH1_ITUTSNC_SYNC1 (0x02) /* Bit 1: Channel 1 operates synchronously */ -#define SH1_ITUTSNC_SYNC2 (0x04) /* Bit 2: Channel 2 operates synchronously */ -#define SH1_ITUTSNC_SYNC3 (0x08) /* Bit 3: Channel 3 operates synchronously */ -#define SH1_ITUTSNC_SYNC4 (0x10) /* Bit 4: Channel 4 operates synchronously */ - -#define SH1_ITUTMDR_PWM0 (0x01) /* Bit 0: Channel 0 operated in PWM mode */ -#define SH1_ITUTMDR_PWM1 (0x02) /* Bit 1: Channel 1 operated in PWM mode */ -#define SH1_ITUTMDR_PWM2 (0x04) /* Bit 2: Channel 2 operated in PWM mode */ -#define SH1_ITUTMDR_PWM3 (0x08) /* Bit 3: Channel 3 operated in PWM mode */ -#define SH1_ITUTMDR_PWM4 (0x10) /* Bit 4: Channel 4 operated in PWM mode */ -#define SH1_ITUTMDR_FDIR (0x20) /* Bit 5: OVF set when TCNT2 overflows */ -#define SH1_ITUTMDR_MDF (0x40) /* Bit 6: Channel 2 operates in phase counting mode */ - -#define SH1_ITUTFCR_BFA3 (0x01) /* Bit 0: GRA3 & BRA3 operate in mode in channel 4 */ -#define SH1_ITUTFCR_BFB3 (0x02) /* Bit 1: GRB3 & BRB3 operate in mode in channel 4 */ -#define SH1_ITUTFCR_BFA4 (0x04) /* Bit 2: GRA4 & BRA4 operate in mode in channel 4 */ -#define SH1_ITUTFCR_BFB4 (0x08) /* Bit 3: GRB4 & BRB4 operate in mode in channel 4 */ -#define SH1_ITUTFCR_CMDMASK (0x30) /* Bit 4-5: Command */ -#define SH1_ITUTFCR_34NDEF (0x00) /* Channels 3/4 normal (default) */ -#define SH1_ITUTFCR_34NORM (0x10) /* Channels 3/4 normal */ -#define SH1_ITUTFCR_34CPWM (0x20) /* Channels 3/4 in complementary PWM mode*/ -#define SH1_ITUTFCR_34RSPWN (0x30) /* Channels 3/4 in reset-synchronized PWM mode */ - -#define SH1_ITUTOCR_OLS3 (0x01) /* Bit 0: 1=TIOCA3, A4 & B4 not inverted */ -#define SH1_ITUTOCR_OLS4 (0x02) /* Bit 1: 1=TIOCB3, XA4 & XB4 not inverted */ - -#define SH1_ITUTCR_TPSCMSK (0x07) /* Bits 0-2: Clock setup, internal/external, divider */ -#define SH1_ITUTCR_DIV1 (0x00) /* Internal clock (phi) */ -#define SH1_ITUTCR_DIV2 (0x01) /* phi / 2 */ -#define SH1_ITUTCR_DIV4 (0x02) /* phi / 4 */ -#define SH1_ITUTCR_DIV8 (0x03) /* phi / 8 */ -#define SH1_ITUTCR_TCLKA (0x04) /* External clock A (TCLKA) */ -#define SH1_ITUTCR_TCLKB (0x05) /* External clock B (TCLKB) */ -#define SH1_ITUTCR_TCLKC (0x06) /* External clock C (TCLKC) */ -#define SH1_ITUTCR_TCLKD (0x07) /* External clock D (TCLKD) */ -#define SH1_ITUTCR_CKEGMSK (0x18) /* Bits 3-4: External clock input edge selection */ -#define SH1_ITUTCR_RISING (0x00) /* Count rising edges */ -#define SH1_ITUTCR_FALLING (0x08) /* Count falling edges */ -#define SH1_ITUTCR_BOTH (0x10) /* Count both */ -#define SH1_ITUTCR_CCLRMSK (0x60) /* Bits 5-6: TCNT clear controls */ -#define SH1_ITUTCR_NCLR (0x00) /* TCNT not cleared */ -#define SH1_ITUTCR_CGRA (0x20) /* TCNT cleared by GRA */ -#define SH1_ITUTCR_CGRB (0x40) /* TCNT cleared by GRB */ -#define SH1_ITUTCR_CSYNC (0x60) /* Synchronized clear */ - -#define SH1_ITUTIOR_IOAMSK (0x07) /* Bits 0-3: GRA function */ -#define SH1_ITUTIOR_OCGRAD (0x00) /* GRA output comparator, disabled */ -#define SH1_ITUTIOR_OCGRA0 (0x01) /* GRA output comparator, 0 output at match */ -#define SH1_ITUTIOR_OCGRA1 (0x02) /* GRA output comparator, 1 output at match */ -#define SH1_ITUTIOR_OCATOG (0x03) /* GRA output comparator, output toggles at match */ -#define SH1_ITUTIOR_ICGRAR (0x04) /* GRA input capture, rising edge */ -#define SH1_ITUTIOR_ICGRAF (0x05) /* GRA input capture, falling edge */ -#define SH1_ITUTIOR_ICGRAB (0x06) /* GRA input capture, both edges */ -#define SH1_ITUTIOR_IOBMSK (0x70) /* Bits 4-6: GRB function */ -#define SH1_ITUTIOR_OCGRBD (0x00) /* GRB output comparator, disabled */ -#define SH1_ITUTIOR_OCGRB0 (0x10) /* GRB output comparator, 0 output at match */ -#define SH1_ITUTIOR_OCGRB1 (0x20) /* GRB output comparator, 1 output at match */ -#define SH1_ITUTIOR_OCBTOG (0x30) /* GRB output comparator, output toggles at match */ -#define SH1_ITUTIOR_ICGRBR (0x40) /* GRB input capture, rising edge */ -#define SH1_ITUTIOR_ICGRBF (0x50) /* GRB input capture, falling edge */ -#define SH1_ITUTIOR_ICGRBB (0x60) /* GRB input capture, both edges */ - -#define SH1_ITUTSR_IMFA (0x01) /* Bit 0: 0=Clearing condition, 1=setting confition */ -#define SH1_ITUTSR_IMFB (0x02) /* Bit 1: 0=Clearing condition, 1=setting confition */ -#define SH1_ITUTSR_OVF (0x04) /* Bit 2: 0=Clearing condition, 1=setting confition */ - -#define SH1_ITUTIER_IMIEA (0x01) /* Bit 0: Enables interrupt request from IMFA */ -#define SH1_ITUTIER_IMIEB (0x02) /* Bit 1: Enables interrupt request from IMFB */ -#define SH1_ITUTIER_OVIE (0x04) /* Bit 2: Enables interrupt request from OVR */ - -/* Interrupt Controller (INTC) */ - -#define SH1_IPRA_IRQ3MASK (0x000f) /* Bits 0-3: IRQ3 */ -#define SH1_IPRA_IRQ3SHIFT (0) -#define SH1_IPRA_IRQ2MASK (0x00f0) /* Bits 4-7: IRQ2 */ -#define SH1_IPRA_IRQ2SHIFT (4) -#define SH1_IPRA_IRQ1MASK (0x0f00) /* Bits 8-11: IRQ1 */ -#define SH1_IPRA_IRQ1SHIFT (8) -#define SH1_IPRA_IRQ0MASK (0xf000) /* Bits 12-15: IRQ0 */ -#define SH1_IPRA_IRQ0SHIFT (12) - -#define SH1_IPRB_IRQ7MASK (0x000f) /* Bits 0-3: IRQ7 */ -#define SH1_IPRB_IRQ7SHIFT (0) -#define SH1_IPRB_IRQ6MASK (0x00f0) /* Bits 4-7: IRQ6 */ -#define SH1_IPRB_IRQ6SHIFT (4) -#define SH1_IPRB_IRQ5MASK (0x0f00) /* Bits 8-11: IRQ5 */ -#define SH1_IPRB_IRQ5SHIFT (8) -#define SH1_IPRB_IRQ4MASK (0xf000) /* Bits 12-15: IRQ4 */ -#define SH1_IPRB_IRQ4SHIFT (12) - -#define SH1_IPRC_ITU1MASK (0x000f) /* Bits 0-3: ITU1 */ -#define SH1_IPRC_ITU1SHIFT (0) -#define SH1_IPRC_ITU0MASK (0x00f0) /* Bits 4-7: ITU0 */ -#define SH1_IPRC_ITU0SHIFT (4) -#define SH1_IPRC_DM23MASK (0x0f00) /* Bits 8-11: DMAC2,3 */ -#define SH1_IPRC_DM23SHIFT (8) -#define SH1_IPRC_DM01MASK (0xf000) /* Bits 12-15: DMAC0,1 */ -#define SH1_IPRC_DM01SHIFT (12) - -#define SH1_IPRD_SCI0MASK (0x000f) /* Bits 0-3: SCI0 */ -#define SH1_IPRD_SCI0SHIFT (0) -#define SH1_IPRD_ITU4MASK (0x00f0) /* Bits 4-7: ITU4 */ -#define SH1_IPRD_ITU4SHIFT (4) -#define SH1_IPRD_ITU3MASK (0x0f00) /* Bits 8-11: ITU3 */ -#define SH1_IPRD_ITU3SHIFT (8) -#define SH1_IPRD_ITU2MASK (0xf000) /* Bits 12-15: ITU2 */ -#define SH1_IPRD_ITU2SHIFT (12) - -#define SH1_IPRE_WDRFMASK (0x00f0) /* Bits 4-7: WDT, REF */ -#define SH1_IPRE_WDRFSHIFT (4) -#define SH1_IPRE_PRADMASK (0x0f00) /* Bits 8-11: PRT, A/D */ -#define SH1_IPRE_PRADSHIFT (8) -#define SH1_IPRE_SCI1MASK (0xf000) /* Bits 12-15: SCI1 */ -#define SH1_IPRE_SCI1SHIFT (12) - -#define SH1_ICR_IRQ7S (0x0001) /* Bits 0: Interrupt on falling edge of IRQ7 input */ -#define SH1_ICR_IRQ6S (0x0002) /* Bits 1: Interrupt on falling edge of IRQ6 input */ -#define SH1_ICR_IRQ5S (0x0004) /* Bits 2: Interrupt on falling edge of IRQ5 input */ -#define SH1_ICR_IRQ4S (0x0008) /* Bits 3: Interrupt on falling edge of IRQ4 input */ -#define SH1_ICR_IRQ3S (0x0010) /* Bits 4: Interrupt on falling edge of IRQ3 input */ -#define SH1_ICR_IRQ2S (0x0020) /* Bits 5: Interrupt on falling edge of IRQ2 input */ -#define SH1_ICR_IRQ1S (0x0040) /* Bits 6: Interrupt on falling edge of IRQ1 input */ -#define SH1_ICR_IRQ0S (0x0080) /* Bits 7: Interrupt on falling edge of IRQ0 input */ -#define SH1_ICR_NMIE (0x0100) /* Bits 8: Interupt on rising edge of NMI input */ -#define SH1_ICR_NMIL (0x8000) /* Bits 15: NMI input level high */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_SH_SRC_SH1_703X_H */ - - - - - - - - - - - - - +/************************************************************************************ + * arch/sh/src/sh1/sh1_703x.h + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_SH_SRC_SH1_703X_H +#define __ARCH_SH_SRC_SH1_703X_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Memory-mapped register addresses *************************************************/ + +/* Serial Communications interface (SCI) */ + +#define SH1_SCI0_BASE (0x05fffec0) +#define SH1_SCI1_BASE (0x05fffec8) + +#define SH1_SCI_SMR_OFFSET (0) /* Serial Mode Register (8-bits wide) */ +#define SH1_SCI_BRR_OFFSET (1) /* Bit Rate Register (8-bits wide) */ +#define SH1_SCI_SCR_OFFSET (2) /* Serial Control Register (8-bits wide) */ +#define SH1_SCI_TDR_OFFSET (3) /* Transmit Data Register (8-bits wide) */ +#define SH1_SCI_SSR_OFFSET (4) /* Serial Status Register (8-bits wide) */ +#define SH1_SCI_RDR_OFFSET (5) /* Receive Data Register (8-bits wide) */ + +#define SH1_SCI0_SMR (SH1_SCI0_BASE+SH1_SCI_SMR_OFFSET) +#define SH1_SCI0_BRR (SH1_SCI0_BASE+SH1_SCI_BRR_OFFSET) +#define SH1_SCI0_SCR (SH1_SCI0_BASE+SH1_SCI_SCR_OFFSET) +#define SH1_SCI0_TDR (SH1_SCI0_BASE+SH1_SCI_TDR_OFFSET) +#define SH1_SCI0_SSR (SH1_SCI0_BASE+SH1_SCI_SSR_OFFSET) +#define SH1_SCI0_RDR (SH1_SCI0_BASE+SH1_SCI_RDR_OFFSET) + +#define SH1_SCI1_SMR (SH1_SCI1_BASE+SH1_SCI_SMR_OFFSET) +#define SH1_SCI1_BRR (SH1_SCI1_BASE+SH1_SCI_BRR_OFFSET) +#define SH1_SCI1_SCR (SH1_SCI1_BASE+SH1_SCI_SCR_OFFSET) +#define SH1_SCI1_TDR (SH1_SCI1_BASE+SH1_SCI_TDR_OFFSET) +#define SH1_SCI1_SSR (SH1_SCI1_BASE+SH1_SCI_SSR_OFFSET) +#define SH1_SCI1_RDR (SH1_SCI1_BASE+SH1_SCI_RDR_OFFSET) + +/* A/D */ + +#define SH1_AD_ADDRA (0x05fffee0) /* 16-bits wide */ +#define SH1_AD_DRAH (0x05fffee0) /* 8-bits wide */ +#define SH1_AD_DRAL (0x05fffee1) /* 8-bits wide */ +#define SH1_AD_DRB (0x05fffee2) /* 16-bits wide */ +#define SH1_AD_DRBH (0x05fffee2) /* 8-bits wide */ +#define SH1_AD_DRBL (0x05fffee3) /* 8-bits wide */ +#define SH1_AD_DRC (0x05fffee4) /* 16-bits wide */ +#define SH1_AD_DRCH (0x05fffee4) /* 8-bits wide */ +#define SH1_AD_DRCL (0x05fffee5) /* 8-bits wide */ +#define SH1_AD_DRD (0x05fffee6) /* 16-bits wide */ +#define SH1_AD_DRDH (0x05fffee6) /* 8-bits wide */ +#define SH1_AD_DRDL (0x05fffee7) /* 8-bits wide */ +#define SH1_AD_CSR (0x05fffee8) /* 8-bits wide */ +#define SH1_AD_CR (0x05fffee9) /* 8-bits wide */ + +/* Integrated Timer/Pulse Unit (ITU) */ + +/* ITU shared */ + +#define SH1_ITU_TSTR (0x05ffff00) /* 8-bits wide */ +#define SH1_ITU_TSNC (0x05ffff01) /* 16-bits wide */ +#define SH1_ITU_TMDR (0x05ffff02) /* 16-bits wide */ +#define SH1_ITU_TFCR (0x05ffff03) /* 16-bits wide */ + +/* ITU channel 0 */ + +#define SH1_ITU0_TCR (0x05ffff04) /* 8-bits wide */ +#define SH1_ITU0_TIOR (0x05ffff05) /* 8-bits wide */ +#define SH1_ITU0_TIER (0x05ffff06) /* 8-bits wide */ +#define SH1_ITU0_TSR (0x05ffff07) /* 8-bits wide */ +#define SH1_ITU0_TCNT (0x05ffff08) /* 16-bits wide */ +#define SH1_ITU0_GRA (0x05ffff0a) /* 16-bits wide */ +#define SH1_ITU0_GRB (0x05ffff0c) /* 16-bits wide */ + +/* ITU channel 1 */ + +#define SH1_ITU1_TCR (0x05ffff0e) /* 8-bits wide */ +#define SH1_ITU1_TIOR (0x05ffff0f) /* 8-bits wide */ +#define SH1_ITU1_TIER (0x05ffff10) /* 8-bits wide */ +#define SH1_ITU1_TSR (0x05ffff11) /* 8-bits wide */ +#define SH1_ITU1_TCNT (0x05ffff12) /* 16-bits wide */ +#define SH1_ITU1_GRA (0x05ffff14) /* 16-bits wide */ +#define SH1_ITU1_GRB (0x05ffff16) /* 16-bits wide */ + +/* ITU channel 2 */ + +#define SH1_ITU2_TCR (0x05ffff18) /* 8-bits wide */ +#define SH1_ITU2_TIOR (0x05ffff19) /* 8-bits wide */ +#define SH1_ITU2_TIER (0x05ffff1a) /* 8-bits wide */ +#define SH1_ITU2_TSR (0x05ffff1b) /* 8-bits wide */ +#define SH1_ITU2_TCNT (0x05ffff1c) /* 16-bits wide */ +#define SH1_ITU2_GRA (0x05ffff1e) /* 16-bits wide */ +#define SH1_ITU2_GRB (0x05ffff20) /* 16-bits wide */ + +/* ITU channel 3 */ + +#define SH1_ITU3_TCR (0x05ffff22) /* 8-bits wide */ +#define SH1_ITU3_TIOR (0x05ffff23) /* 8-bits wide */ +#define SH1_ITU3_TIER (0x05ffff24) /* 8-bits wide */ +#define SH1_ITU3_TSR (0x05ffff25) /* 8-bits wide */ +#define SH1_ITU3_TCNT (0x05ffff26) /* 16-bits wide */ +#define SH1_ITU3_GRA (0x05ffff28) /* 16-bits wide */ +#define SH1_ITU3_GRB (0x05ffff2a) /* 16-bits wide */ +#define SH1_ITU3_BRA (0x05ffff2c) /* 16-bits wide */ +#define SH1_ITU3_BRB3 (0x05ffff2e) /* 16-bits wide */ + +/* ITU channels 0-4 shared */ + +#define SH1_ITU_TOCR (0x05ffff31) /* 8-bits wide */ + +/* ITU channel 4 */ + +#define SH1_ITU4_TCR (0x05ffff32) /* 8-bits wide */ +#define SH1_ITU4_TIOR (0x05ffff33) /* 8-bits wide */ +#define SH1_ITU4_TIER (0x05ffff34) /* 8-bits wide */ +#define SH1_ITU4_TSR (0x05ffff35) /* 8-bits wide */ +#define SH1_ITU4_TCNT (0x05ffff36) /* 16-bits wide */ +#define SH1_ITU4_GRA (0x05ffff38) /* 16-bits wide */ +#define SH1_ITU4_GRB (0x05ffff3a) /* 16-bits wide */ +#define SH1_ITU4_BRA (0x05ffff3c) /* 16-bits wide */ +#define SH1_ITU4_BRB (0x05ffff3e) /* 16-bits wide */ + +/* DMA controller (DMAC) */ + +/* DMAC channels 0-3 shared */ + +#define SH1_DMAOR (0x05ffff48) /* 16-bits wide */ + +/* DMAC channel 0 */ + +#define SH1_DMA0_SAR0 (0x05ffff40) /* 32-bits wide */ +#define SH1_DMA0_DAR0 (0x05ffff44) /* 32-bits wide */ +#define SH1_DMA0_TCR0 (0x05ffff4a) /* 16-bits wide */ +#define SH1_DMA0_CHCR0 (0x05ffff4e) /* 16-bits wide */ + +/* DMAC channel 1 */ + +#define SH1_DMA1_SAR (0x05ffff50) /* 32-bits wide */ +#define SH1_DMA1_DAR (0x05ffff54) /* 32-bits wide */ +#define SH1_DMA1_TCR (0x05fffF5a) /* 16-bits wide */ +#define SH1_DMA1_CHCR (0x05ffff5e) /* 16-bits wide */ + +/* DMAC channel 2 */ + +#define SH1_DMA2_SAR (0x05ffff60) /* 32-bits wide */ +#define SH1_DMA2_DAR (0x05ffff64) /* 32-bits wide */ +#define SH1_DMA2_TCR (0x05fffF6a) /* 16-bits wide */ +#define SH1_DMA2_CHCR (0x05ffff6e) /* 16-bits wide */ + +/* DMAC channel 3 */ + +#define SH1_DMA3_SAR (0x05ffff70) /* 32-bits wide */ +#define SH1_DMA3_DAR (0x05ffff74) /* 32-bits wide */ +#define SH1_DMA3_TCR (0x05fffF7a) /* 16-bits wide */ +#define SH1_DMA3_CHCR (0x05ffff7e) /* 16-bits wide */ + +/* Interrupt Controller (INTC) */ + +#define SH1_INTC_IPRA (0x05ffff84) /* Interrupt priority register A (16-bits wide) */ +#define SH1_INTC_IPRB (0x05ffff86) /* Interrupt priority register B (16-bits wide) */ +#define SH1_INTC_IPRC (0x05ffff88) /* Interrupt priority register C (16-bits wide) */ +#define SH1_INTC_IPRD (0x05ffff8a) /* Interrupt priority register D (16-bits wide) */ +#define SH1_INTC_IPRE (0x05ffff8c) /* Interrupt priority register E (16-bits wide) */ +#define SH1_INTC_ICR (0x05ffff8e) /* Interrupt control register (16-bits wide) */ + +/* User Break Controller (UBC) */ + +#define SH1_UBC_BARH (0x05ffff90) /* 16-bits wide */ +#define SH1_UBC_BARL (0x05ffff92) /* 16-bits wide */ +#define SH1_UBC_BAMRH (0x05ffff94) /* 16-bits wide */ +#define SH1_UBC_BAMRL (0x05ffff96) /* 16-bits wide */ +#define SH1_UBC_BBR (0x05ffff98) /* 16-bits wide */ + +/* Bus State Controller (BSC) */ + +#define SH1_BSC_BCR (0x05ffffa0) /* 16-bits wide */ +#define SH1_BSC_WCR1 (0x05ffffa2) /* 16-bits wide */ +#define SH1_BSC_WCR2 (0x05ffffa4) /* 16-bits wide */ +#define SH1_BSC_WCR3 (0x05ffffa6) /* 16-bits wide */ +#define SH1_BSC_DCR (0x05ffffa8) /* 16-bits wide */ +#define SH1_BSC_PCR (0x05ffffaa) /* 16-bits wide */ +#define SH1_BSC_RCR (0x05ffffac) /* 16-bits wide */ +#define SH1_BSC_RTCSR (0x05ffffae) /* 16-bits wide */ +#define SH1_BSC_RTCNT (0x05ffffb0) /* 16-bits wide */ +#define SH1_BSC_RTCOR (0x05ffffb2) /* 16-bits wide */ + +/* Watchdog Timer (WDT) */ + +#define SH1_WDT_TCSR (0x05ffffb8) /* 8-bits wide */ +#define SH1_WDT_TCNT (0x05ffffb9) /* 8-bits wide */ +#define SH1_WDT_RSTCSR (0x05ffffbb) /* 8-bits wide */ + +/* Power down state */ + +#define SH1_PDT_SBYCR (0x05ffffbc) /* 8-bits wide */ + +/* Port A */ + +#define SH1_PORTA_DR (0x05ffffc0) /* 16-bits wide */ + +/* Port B */ + +#define SH1_PORTB_DR (0x05ffffc2) /* 16-bits wide */ + +/* Pin Function Controller (PFC) */ + +#define SH1_PFC_PAIOR (0x05ffffc4) /* Port B I/O register (16-bits wide) */ +#define SH1_PFC_PBIOR (0x05ffffc6) /* Port B I/O register (16-bits wide) */ +#define SH1_PFC_PACR1 (0x05ffffc8) /* Port A control register 1 (16-bits wide) */ +#define SH1_PFC_PACR2 (0x05ffffca) /* Port A control register 2 (16-bits wide) */ +#define SH1_PFC_PBCR1 (0x05ffffcc) /* Port B control register 1 (16-bits wide) */ +#define SH1_PFC_PBCR2 (0x05ffffce) /* Port B control register 2 )16-bits wide) */ + +/* Port C */ + +#define SH1_PORTC_DR (0x05ffffd0) /* 16-bits wide */ + +/* Pin Function Controller (PFC, cont'd) */ + +#define SH1_PFC_CASCR (0x05ffffee) /* 16-bits wide */ + +/* Timing Pattern Controller (TPC) */ + +#define SH1_TPC_TPMR (0x05fffff0) /* 16-bits wide */ +#define SH1_TPC_TPCR (0x05fffff1) /* 16-bits wide */ +#define SH1_TPC_NDERH (0x05fffff2) /* 16-bits wide */ +#define SH1_TPC_NDERL (0x05fffff3) /* 16-bits wide */ +#define SH1_TPC_NDRB0 (0x05fffff4) /* 8-bits wide */ +#define SH1_TPC_NDRA0 (0x05fffff5) /* 8-bits wide */ +#define SH1_TPC_NDRB1 (0x05fffff6) /* 8-bits wide */ +#define SH1_TPC_NDRA1 (0x05fffff7) /* 8-bits wide */ + +/* Register bit definitions *********************************************************/ + +/* Serial Communications interface (SCI) */ + +#define SH1_SCISMR_CKSMASK (0x03) /* Bit 0-1: Internal clock source */ +#define SH1_SCISMR_DIV1 (0x00) /* System clock (phi) */ +#define SH1_SCISMR_DIV4 (0x01) /* phi/4 */ +#define SH1_SCISMR_DIV16 (0x02) /* phi/16 */ +#define SH1_SCISMR_DIV64 (0x03) /* phi/64 */ +#define SH1_SCISMR_MP (0x04) /* Bit 2: Multiprocessor select */ +#define SH1_SCISMR_STOP (0x08) /* Bit 3: 0:One stop bit, 1:Two stop bits */ +#define SH1_SCISMR_OE (0x10) /* Bit 4: 0:Even parity, 1:Odd parity */ +#define SH1_SCISMR_PE (0x20) /* Bit 5: Parity enable */ +#define SH1_SCISMR_CHR (0x40) /* Bit 6: 0:8-bit data, 1:7-bit data */ +#define SH1_SCISMR_CA (0x80) /* Bit 7: 0:Asynchronous, 1:clocked synchronous */ + +#define SH1_SCISCR_CKEMASK (0x03) /* Bit 0-1: Internal clock source */ + /* Asynchronous mode: */ +#define SH1_SCISCR_AISIN (0x00) /* Internal clock, SCK pin used for input pin */ +#define SH1_SCISCR_AISOUT (0x01) /* Internal clock, SCK pin used for clock output */ +#define SH1_SCISCR_AXSIN1 (0x02) /* External clock, SCK pin used for clock input */ +#define SH1_SCISCR_AXSIN2 (0x03) /* External clock, SCK pin used for clock input */ + /* Synchronous mode: */ +#define SH1_SCISCR_SISOUT1 (0x00) /* Internal clock, SCK pin used for input pin */ +#define SH1_SCISCR_SISOUT2 (0x01) /* Internal clock, SCK pin used for clock output */ +#define SH1_SCISCR_SXSIN1 (0x02) /* External clock, SCK pin used for clock input */ +#define SH1_SCISCR_SXSIN2 (0x03) /* External clock, SCK pin used for clock input */ +#define SH1_SCISCR_TEIE (0x04) /* Bit 2: 1=Transmit end interrupt enable */ +#define SH1_SCISCR_MPIE (0x08) /* Bit 3: 1=Multiprocessor interrupt enable */ +#define SH1_SCISCR_RE (0x10) /* Bit 4: 1=Receiver enable */ +#define SH1_SCISCR_TE (0x20) /* Bit 5: 1=Transmitter enable */ +#define SH1_SCISCR_RIE (0x40) /* Bit 6: 1=Recieve-data-full interrupt enable */ +#define SH1_SCISCR_TIE (0x80) /* Bit 7: 1=Transmit-data-empty interrupt enable */ +#define SH1_SCISCR_ALLINTS (0xcc) + +#define SH1_SCISSR_MPBT (0x01) /* Bit 0: Multi-processor Bit in Transmit data */ +#define SH1_SCISSR_MPB (0x02) /* Bit 1: Multi-processor Bit in receive data */ +#define SH1_SCISSR_TEND (0x04) /* Bit 2: End of transmission */ +#define SH1_SCISSR_PER (0x08) /* Bit 3: Receive parity error */ +#define SH1_SCISSR_FER (0x10) /* Bit 4: Receive framing error */ +#define SH1_SCISSR_ORER (0x20) /* Bit 5: Receive overrun error */ +#define SH1_SCISSR_RDRF (0x40) /* Bit 6: RDR contains valid received data */ +#define SH1_SCISSR_TDRE (0x80) /* Bit 7: TDR does not contain valid transmit data */ + +/* Integrated Timer unit (ITU) */ + +#define SH1_ITUTSTR_STR0 (0x01) /* Bit 0: TCNT0 is counting */ +#define SH1_ITUTSTR_STR1 (0x02) /* Bit 1: TCNT1 is counting */ +#define SH1_ITUTSTR_STR2 (0x04) /* Bit 2: TCNT2 is counting */ +#define SH1_ITUTSTR_STR3 (0x08) /* Bit 3: TCNT3 is counting */ +#define SH1_ITUTSTR_STR4 (0x10) /* Bit 4: TCNT4 is counting */ + +#define SH1_ITUTSNC_SYNC0 (0x01) /* Bit 0: Channel 0 operates synchronously */ +#define SH1_ITUTSNC_SYNC1 (0x02) /* Bit 1: Channel 1 operates synchronously */ +#define SH1_ITUTSNC_SYNC2 (0x04) /* Bit 2: Channel 2 operates synchronously */ +#define SH1_ITUTSNC_SYNC3 (0x08) /* Bit 3: Channel 3 operates synchronously */ +#define SH1_ITUTSNC_SYNC4 (0x10) /* Bit 4: Channel 4 operates synchronously */ + +#define SH1_ITUTMDR_PWM0 (0x01) /* Bit 0: Channel 0 operated in PWM mode */ +#define SH1_ITUTMDR_PWM1 (0x02) /* Bit 1: Channel 1 operated in PWM mode */ +#define SH1_ITUTMDR_PWM2 (0x04) /* Bit 2: Channel 2 operated in PWM mode */ +#define SH1_ITUTMDR_PWM3 (0x08) /* Bit 3: Channel 3 operated in PWM mode */ +#define SH1_ITUTMDR_PWM4 (0x10) /* Bit 4: Channel 4 operated in PWM mode */ +#define SH1_ITUTMDR_FDIR (0x20) /* Bit 5: OVF set when TCNT2 overflows */ +#define SH1_ITUTMDR_MDF (0x40) /* Bit 6: Channel 2 operates in phase counting mode */ + +#define SH1_ITUTFCR_BFA3 (0x01) /* Bit 0: GRA3 & BRA3 operate in mode in channel 4 */ +#define SH1_ITUTFCR_BFB3 (0x02) /* Bit 1: GRB3 & BRB3 operate in mode in channel 4 */ +#define SH1_ITUTFCR_BFA4 (0x04) /* Bit 2: GRA4 & BRA4 operate in mode in channel 4 */ +#define SH1_ITUTFCR_BFB4 (0x08) /* Bit 3: GRB4 & BRB4 operate in mode in channel 4 */ +#define SH1_ITUTFCR_CMDMASK (0x30) /* Bit 4-5: Command */ +#define SH1_ITUTFCR_34NDEF (0x00) /* Channels 3/4 normal (default) */ +#define SH1_ITUTFCR_34NORM (0x10) /* Channels 3/4 normal */ +#define SH1_ITUTFCR_34CPWM (0x20) /* Channels 3/4 in complementary PWM mode*/ +#define SH1_ITUTFCR_34RSPWN (0x30) /* Channels 3/4 in reset-synchronized PWM mode */ + +#define SH1_ITUTOCR_OLS3 (0x01) /* Bit 0: 1=TIOCA3, A4 & B4 not inverted */ +#define SH1_ITUTOCR_OLS4 (0x02) /* Bit 1: 1=TIOCB3, XA4 & XB4 not inverted */ + +#define SH1_ITUTCR_TPSCMSK (0x07) /* Bits 0-2: Clock setup, internal/external, divider */ +#define SH1_ITUTCR_DIV1 (0x00) /* Internal clock (phi) */ +#define SH1_ITUTCR_DIV2 (0x01) /* phi / 2 */ +#define SH1_ITUTCR_DIV4 (0x02) /* phi / 4 */ +#define SH1_ITUTCR_DIV8 (0x03) /* phi / 8 */ +#define SH1_ITUTCR_TCLKA (0x04) /* External clock A (TCLKA) */ +#define SH1_ITUTCR_TCLKB (0x05) /* External clock B (TCLKB) */ +#define SH1_ITUTCR_TCLKC (0x06) /* External clock C (TCLKC) */ +#define SH1_ITUTCR_TCLKD (0x07) /* External clock D (TCLKD) */ +#define SH1_ITUTCR_CKEGMSK (0x18) /* Bits 3-4: External clock input edge selection */ +#define SH1_ITUTCR_RISING (0x00) /* Count rising edges */ +#define SH1_ITUTCR_FALLING (0x08) /* Count falling edges */ +#define SH1_ITUTCR_BOTH (0x10) /* Count both */ +#define SH1_ITUTCR_CCLRMSK (0x60) /* Bits 5-6: TCNT clear controls */ +#define SH1_ITUTCR_NCLR (0x00) /* TCNT not cleared */ +#define SH1_ITUTCR_CGRA (0x20) /* TCNT cleared by GRA */ +#define SH1_ITUTCR_CGRB (0x40) /* TCNT cleared by GRB */ +#define SH1_ITUTCR_CSYNC (0x60) /* Synchronized clear */ + +#define SH1_ITUTIOR_IOAMSK (0x07) /* Bits 0-3: GRA function */ +#define SH1_ITUTIOR_OCGRAD (0x00) /* GRA output comparator, disabled */ +#define SH1_ITUTIOR_OCGRA0 (0x01) /* GRA output comparator, 0 output at match */ +#define SH1_ITUTIOR_OCGRA1 (0x02) /* GRA output comparator, 1 output at match */ +#define SH1_ITUTIOR_OCATOG (0x03) /* GRA output comparator, output toggles at match */ +#define SH1_ITUTIOR_ICGRAR (0x04) /* GRA input capture, rising edge */ +#define SH1_ITUTIOR_ICGRAF (0x05) /* GRA input capture, falling edge */ +#define SH1_ITUTIOR_ICGRAB (0x06) /* GRA input capture, both edges */ +#define SH1_ITUTIOR_IOBMSK (0x70) /* Bits 4-6: GRB function */ +#define SH1_ITUTIOR_OCGRBD (0x00) /* GRB output comparator, disabled */ +#define SH1_ITUTIOR_OCGRB0 (0x10) /* GRB output comparator, 0 output at match */ +#define SH1_ITUTIOR_OCGRB1 (0x20) /* GRB output comparator, 1 output at match */ +#define SH1_ITUTIOR_OCBTOG (0x30) /* GRB output comparator, output toggles at match */ +#define SH1_ITUTIOR_ICGRBR (0x40) /* GRB input capture, rising edge */ +#define SH1_ITUTIOR_ICGRBF (0x50) /* GRB input capture, falling edge */ +#define SH1_ITUTIOR_ICGRBB (0x60) /* GRB input capture, both edges */ + +#define SH1_ITUTSR_IMFA (0x01) /* Bit 0: 0=Clearing condition, 1=setting confition */ +#define SH1_ITUTSR_IMFB (0x02) /* Bit 1: 0=Clearing condition, 1=setting confition */ +#define SH1_ITUTSR_OVF (0x04) /* Bit 2: 0=Clearing condition, 1=setting confition */ + +#define SH1_ITUTIER_IMIEA (0x01) /* Bit 0: Enables interrupt request from IMFA */ +#define SH1_ITUTIER_IMIEB (0x02) /* Bit 1: Enables interrupt request from IMFB */ +#define SH1_ITUTIER_OVIE (0x04) /* Bit 2: Enables interrupt request from OVR */ + +/* Interrupt Controller (INTC) */ + +#define SH1_IPRA_IRQ3MASK (0x000f) /* Bits 0-3: IRQ3 */ +#define SH1_IPRA_IRQ3SHIFT (0) +#define SH1_IPRA_IRQ2MASK (0x00f0) /* Bits 4-7: IRQ2 */ +#define SH1_IPRA_IRQ2SHIFT (4) +#define SH1_IPRA_IRQ1MASK (0x0f00) /* Bits 8-11: IRQ1 */ +#define SH1_IPRA_IRQ1SHIFT (8) +#define SH1_IPRA_IRQ0MASK (0xf000) /* Bits 12-15: IRQ0 */ +#define SH1_IPRA_IRQ0SHIFT (12) + +#define SH1_IPRB_IRQ7MASK (0x000f) /* Bits 0-3: IRQ7 */ +#define SH1_IPRB_IRQ7SHIFT (0) +#define SH1_IPRB_IRQ6MASK (0x00f0) /* Bits 4-7: IRQ6 */ +#define SH1_IPRB_IRQ6SHIFT (4) +#define SH1_IPRB_IRQ5MASK (0x0f00) /* Bits 8-11: IRQ5 */ +#define SH1_IPRB_IRQ5SHIFT (8) +#define SH1_IPRB_IRQ4MASK (0xf000) /* Bits 12-15: IRQ4 */ +#define SH1_IPRB_IRQ4SHIFT (12) + +#define SH1_IPRC_ITU1MASK (0x000f) /* Bits 0-3: ITU1 */ +#define SH1_IPRC_ITU1SHIFT (0) +#define SH1_IPRC_ITU0MASK (0x00f0) /* Bits 4-7: ITU0 */ +#define SH1_IPRC_ITU0SHIFT (4) +#define SH1_IPRC_DM23MASK (0x0f00) /* Bits 8-11: DMAC2,3 */ +#define SH1_IPRC_DM23SHIFT (8) +#define SH1_IPRC_DM01MASK (0xf000) /* Bits 12-15: DMAC0,1 */ +#define SH1_IPRC_DM01SHIFT (12) + +#define SH1_IPRD_SCI0MASK (0x000f) /* Bits 0-3: SCI0 */ +#define SH1_IPRD_SCI0SHIFT (0) +#define SH1_IPRD_ITU4MASK (0x00f0) /* Bits 4-7: ITU4 */ +#define SH1_IPRD_ITU4SHIFT (4) +#define SH1_IPRD_ITU3MASK (0x0f00) /* Bits 8-11: ITU3 */ +#define SH1_IPRD_ITU3SHIFT (8) +#define SH1_IPRD_ITU2MASK (0xf000) /* Bits 12-15: ITU2 */ +#define SH1_IPRD_ITU2SHIFT (12) + +#define SH1_IPRE_WDRFMASK (0x00f0) /* Bits 4-7: WDT, REF */ +#define SH1_IPRE_WDRFSHIFT (4) +#define SH1_IPRE_PRADMASK (0x0f00) /* Bits 8-11: PRT, A/D */ +#define SH1_IPRE_PRADSHIFT (8) +#define SH1_IPRE_SCI1MASK (0xf000) /* Bits 12-15: SCI1 */ +#define SH1_IPRE_SCI1SHIFT (12) + +#define SH1_ICR_IRQ7S (0x0001) /* Bits 0: Interrupt on falling edge of IRQ7 input */ +#define SH1_ICR_IRQ6S (0x0002) /* Bits 1: Interrupt on falling edge of IRQ6 input */ +#define SH1_ICR_IRQ5S (0x0004) /* Bits 2: Interrupt on falling edge of IRQ5 input */ +#define SH1_ICR_IRQ4S (0x0008) /* Bits 3: Interrupt on falling edge of IRQ4 input */ +#define SH1_ICR_IRQ3S (0x0010) /* Bits 4: Interrupt on falling edge of IRQ3 input */ +#define SH1_ICR_IRQ2S (0x0020) /* Bits 5: Interrupt on falling edge of IRQ2 input */ +#define SH1_ICR_IRQ1S (0x0040) /* Bits 6: Interrupt on falling edge of IRQ1 input */ +#define SH1_ICR_IRQ0S (0x0080) /* Bits 7: Interrupt on falling edge of IRQ0 input */ +#define SH1_ICR_NMIE (0x0100) /* Bits 8: Interupt on rising edge of NMI input */ +#define SH1_ICR_NMIL (0x8000) /* Bits 15: NMI input level high */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_SH_SRC_SH1_703X_H */ + + + + + + + + + + + + + diff --git a/arch/sh/src/sh1/sh1_copystate.c b/arch/sh/src/sh1/sh1_copystate.c index 3b0863eb7e704912403d6099060b01e74297ad74..323f96c4a10af2dfa7b5b4361d0bd1ab9c12aa4d 100644 --- a/arch/sh/src/sh1/sh1_copystate.c +++ b/arch/sh/src/sh1/sh1_copystate.c @@ -2,7 +2,7 @@ * arch/sh/src/sh1/up_copystate.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/sh1/sh1_dumpstate.c b/arch/sh/src/sh1/sh1_dumpstate.c index ddfa5e455a2f1268c0f0e23d56297a20d5b75984..296e20a45c9f86766d247c73c34f4ca61c17da34 100755 --- a/arch/sh/src/sh1/sh1_dumpstate.c +++ b/arch/sh/src/sh1/sh1_dumpstate.c @@ -2,7 +2,7 @@ * arch/sh/src/sh1/sh1_assert.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/sh1/sh1_initialstate.c b/arch/sh/src/sh1/sh1_initialstate.c index 94b74c3abd587802d323ea6304b77cb87a59fa33..c4fb11a74579322c06d2e22f967afe8f2a783c13 100644 --- a/arch/sh/src/sh1/sh1_initialstate.c +++ b/arch/sh/src/sh1/sh1_initialstate.c @@ -2,7 +2,7 @@ * arch/sh/src/sh1/sh1_initialstate.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/sh1/sh1_irq.c b/arch/sh/src/sh1/sh1_irq.c index d76d1d94cdaead08486dd01c3d6ac5fd162e39d2..7757c9ba906a6a1ef76ac6aac4e033b22af7b5d1 100644 --- a/arch/sh/src/sh1/sh1_irq.c +++ b/arch/sh/src/sh1/sh1_irq.c @@ -2,7 +2,7 @@ * arch/sh/src/sh1/sh1_irq.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/sh1/sh1_lowputc.c b/arch/sh/src/sh1/sh1_lowputc.c index dd66c727b8f7ede4889057af6f7c33c9d92c3b07..ed9cbb8e225aaf685db70d342ac2d67e39819233 100644 --- a/arch/sh/src/sh1/sh1_lowputc.c +++ b/arch/sh/src/sh1/sh1_lowputc.c @@ -2,7 +2,7 @@ * arch/sh/src/sh1/sh1_lowputc.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/sh1/sh1_saveusercontext.S b/arch/sh/src/sh1/sh1_saveusercontext.S index 1514b9399258a2a701f712d209ee8148cbdab344..56a43a2fbb6d6d4d01042e312a0afcda686cd2a0 100644 --- a/arch/sh/src/sh1/sh1_saveusercontext.S +++ b/arch/sh/src/sh1/sh1_saveusercontext.S @@ -2,7 +2,7 @@ * arch/sh/src/sh1/sh1_saveusercontext.S * * Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/sh1/sh1_schedulesigaction.c b/arch/sh/src/sh1/sh1_schedulesigaction.c index 4454195d695c8259997da75adc7c17e42c1958c0..f0bc0af848374d4ba90fc1b93346ab992b0702a9 100644 --- a/arch/sh/src/sh1/sh1_schedulesigaction.c +++ b/arch/sh/src/sh1/sh1_schedulesigaction.c @@ -2,7 +2,7 @@ * arch/sh/src/sh1/sh1_schedulesigaction.c * * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/sh1/sh1_sigdeliver.c b/arch/sh/src/sh1/sh1_sigdeliver.c index 568b448e3e9b1d9dafcde191a852fbeee7aa28e5..2f596b6b0f1c376823187a51e78f39a088b0bce6 100644 --- a/arch/sh/src/sh1/sh1_sigdeliver.c +++ b/arch/sh/src/sh1/sh1_sigdeliver.c @@ -2,7 +2,7 @@ * common/up_sigdeliver.c * * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/sh1/sh1_timerisr.c b/arch/sh/src/sh1/sh1_timerisr.c index 7072c4c643f51b7929bddee4a77e46996d895c96..4f0f176a2b5304ba11c2d51edc6d0564a9fd2f6d 100644 --- a/arch/sh/src/sh1/sh1_timerisr.c +++ b/arch/sh/src/sh1/sh1_timerisr.c @@ -2,7 +2,7 @@ * arch/sh/src/sh1/sh1_timerisr.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sh/src/sh1/sh1_vector.S b/arch/sh/src/sh1/sh1_vector.S index 9e7ef5075243e37ccee8ebb232bb196db8fb42fe..1655a782dc642eceeaaa63d456b68c11ce6a053d 100644 --- a/arch/sh/src/sh1/sh1_vector.S +++ b/arch/sh/src/sh1/sh1_vector.S @@ -2,7 +2,7 @@ * arch/sh/src/sh1/sh1_vector.S * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/include/arch.h b/arch/sim/include/arch.h index 03e8ae36eb985f99f612c00ab36b2c4af6a594ef..5ec8022b27039d709e559ab07bd172fb0bc49a66 100644 --- a/arch/sim/include/arch.h +++ b/arch/sim/include/arch.h @@ -2,7 +2,7 @@ * arch.h * * Copyright (C) 2007 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/include/irq.h b/arch/sim/include/irq.h index e5405f0cafeec2695e160a8e7151bbb952bdbe25..ffc325790c0bc274e9afb69009297e74b966997f 100644 --- a/arch/sim/include/irq.h +++ b/arch/sim/include/irq.h @@ -2,7 +2,7 @@ * irq.h * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/include/syscall.h b/arch/sim/include/syscall.h index 73b78def4234bd4e0d972f8233c82795288cf9a2..7ffcbf5e69c6f824dea2ff8279631d85d2b27efb 100644 --- a/arch/sim/include/syscall.h +++ b/arch/sim/include/syscall.h @@ -2,7 +2,7 @@ * arch/sim/include/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/include/types.h b/arch/sim/include/types.h index 5b58264e6cdc7e5fbdda2413ffaffc8a3c0a3e97..719944f1f5587607dc4b586918d311a1c21a3f47 100644 --- a/arch/sim/include/types.h +++ b/arch/sim/include/types.h @@ -2,7 +2,7 @@ * arch/sim/include/types.h * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_allocateheap.c b/arch/sim/src/up_allocateheap.c index f02f8cbfa0afa2d0675e16ff436efeb5a21a8ad0..47400ec7c3a33819416346f13b7cf6b4e6b771c9 100644 --- a/arch/sim/src/up_allocateheap.c +++ b/arch/sim/src/up_allocateheap.c @@ -2,7 +2,7 @@ * up_allocateheap.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_blockdevice.c b/arch/sim/src/up_blockdevice.c index f697b36cbbbcd089d96def2546dcf43aaaf9f0f2..edcb6f3774a4ab986faefda5280ebd1946742255 100644 --- a/arch/sim/src/up_blockdevice.c +++ b/arch/sim/src/up_blockdevice.c @@ -2,7 +2,7 @@ * up_blockdevice.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_blocktask.c b/arch/sim/src/up_blocktask.c index cfa9adb59e7a4a7530c73a0c7a5b50bda3d17b7d..c69c979aeb4f165d7f4ca975bcc1d3f3add54d33 100644 --- a/arch/sim/src/up_blocktask.c +++ b/arch/sim/src/up_blocktask.c @@ -2,7 +2,7 @@ * up_blocktask.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_createstack.c b/arch/sim/src/up_createstack.c index 03426ade2e6a7af732742aea70f8ca494174b67d..be8fe278b41c634fef602dbbb7af45587cd87e38 100644 --- a/arch/sim/src/up_createstack.c +++ b/arch/sim/src/up_createstack.c @@ -2,7 +2,7 @@ * arch/sim/src/up_createstack.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_devconsole.c b/arch/sim/src/up_devconsole.c index a2406f232b554d3af608ffbe0fc88d584cd7d51d..bd2be0f10f118c6cd9f1a983b83d59a1e70a8914 100644 --- a/arch/sim/src/up_devconsole.c +++ b/arch/sim/src/up_devconsole.c @@ -2,7 +2,7 @@ * up_devconsole.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_deviceimage.c b/arch/sim/src/up_deviceimage.c index 19b7650ec76d620542dafd4a08b9948fd36fd2db..e32f649275162582472cc390b7570cc9b9352528 100644 --- a/arch/sim/src/up_deviceimage.c +++ b/arch/sim/src/up_deviceimage.c @@ -2,7 +2,7 @@ * up_deviceimage.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_exit.c b/arch/sim/src/up_exit.c index d42ab94dd46df887ab247d7b856c78c5a3f3a651..3f82246c97e0ac089942953b09fcde4d99f0b68c 100644 --- a/arch/sim/src/up_exit.c +++ b/arch/sim/src/up_exit.c @@ -2,7 +2,7 @@ * up_exit.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_framebuffer.c b/arch/sim/src/up_framebuffer.c index d8e9a452f320701dc9b2e0754e05eab766f5fbb2..35329b9d88cff31ec0ab41fa1fde71d8cc88cc4e 100644 --- a/arch/sim/src/up_framebuffer.c +++ b/arch/sim/src/up_framebuffer.c @@ -2,7 +2,7 @@ * arch/sim/src/up_framebuffer.c * * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_hostusleep.c b/arch/sim/src/up_hostusleep.c index 67eb3e221423c572806caf360da417fcc182a326..df65d7be5c7da759ed39cf76267bdd24f4de0e55 100644 --- a/arch/sim/src/up_hostusleep.c +++ b/arch/sim/src/up_hostusleep.c @@ -2,7 +2,7 @@ * arch/sim/src/up_hostusleep.c * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_initialstate.c b/arch/sim/src/up_initialstate.c index 6c959589fe5225e25c93ee6d1f9bdbeaccdeb14f..6f241fc47da733b65f4bba06fbb176ca5323e456 100644 --- a/arch/sim/src/up_initialstate.c +++ b/arch/sim/src/up_initialstate.c @@ -2,7 +2,7 @@ * up_initialstate.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_interruptcontext.c b/arch/sim/src/up_interruptcontext.c index 8c211fc4774f96249f816bae43bd6b213413016b..83a17d3b6dbb73234b09a914f6da2507e0fc96c2 100644 --- a/arch/sim/src/up_interruptcontext.c +++ b/arch/sim/src/up_interruptcontext.c @@ -2,7 +2,7 @@ * up_interruptcontext.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_lcd.c b/arch/sim/src/up_lcd.c index f5a1e0159978cc450dddb9518b691af2b97e881c..4c2031dd29ec28ebeb49180537aca1ff86f5c3d8 100644 --- a/arch/sim/src/up_lcd.c +++ b/arch/sim/src/up_lcd.c @@ -2,7 +2,7 @@ * arch/sim/src/up_lcd.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_netdev.c b/arch/sim/src/up_netdev.c index 8758facc43560a740694ad88d53b95f70d5e9df5..e02b30ef6d1594952da3866d46b4aa1ed69eec0a 100644 --- a/arch/sim/src/up_netdev.c +++ b/arch/sim/src/up_netdev.c @@ -2,7 +2,7 @@ * arch/sim/src/up_tapdev.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_releasepending.c b/arch/sim/src/up_releasepending.c index a5152ee86cd95a7e4cbadf410dfae1b9ba14afe0..52d76bcace85d4d6ff23be283e80ed4fe0c279d1 100644 --- a/arch/sim/src/up_releasepending.c +++ b/arch/sim/src/up_releasepending.c @@ -2,7 +2,7 @@ * up_releasepending.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_releasestack.c b/arch/sim/src/up_releasestack.c index 745345c1aaf2d7ba12f749baa3d00502da3a55f1..ef09fcb2a9a1b98a47c99cd27107be28fbf940bf 100644 --- a/arch/sim/src/up_releasestack.c +++ b/arch/sim/src/up_releasestack.c @@ -2,7 +2,7 @@ * up_releasestack.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_reprioritizertr.c b/arch/sim/src/up_reprioritizertr.c index a7ffb137dccc16c810ce197184d333aaa5bedba1..913d8d5f5bfc44296aaf99ccaddafa96a2eaf5a4 100644 --- a/arch/sim/src/up_reprioritizertr.c +++ b/arch/sim/src/up_reprioritizertr.c @@ -2,7 +2,7 @@ * up_reprioritizertr.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_romgetc.c b/arch/sim/src/up_romgetc.c index 7218445081ab85e26b36e6d620cdd2c6e09d3f2f..9b75ecd6536da5c9b25199703162618f9ea8e93a 100644 --- a/arch/sim/src/up_romgetc.c +++ b/arch/sim/src/up_romgetc.c @@ -2,7 +2,7 @@ * arch/sim/src/up_romgetc.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_schedulesigaction.c b/arch/sim/src/up_schedulesigaction.c index ca61e8ddf3e73f4312f902d46c1c0a26289c2e37..871040a9490ff32635c9a3ff2cec4bbe49b9d224 100644 --- a/arch/sim/src/up_schedulesigaction.c +++ b/arch/sim/src/up_schedulesigaction.c @@ -2,7 +2,7 @@ * up_schedulesigaction.c * * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_stdio.c b/arch/sim/src/up_stdio.c index 7a014d4d88ec866a5288dacb745012d74ba4a063..b6da9cb2fc3bf612b63c13cc4ba5869bc3adfd12 100644 --- a/arch/sim/src/up_stdio.c +++ b/arch/sim/src/up_stdio.c @@ -2,7 +2,7 @@ * up_stdio.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_tapdev.c b/arch/sim/src/up_tapdev.c index 4176258e2fd067d4e468dc615096c909e6940ffb..d0deea6d9bd2b63c30640d259739e18a7e17672c 100644 --- a/arch/sim/src/up_tapdev.c +++ b/arch/sim/src/up_tapdev.c @@ -2,7 +2,7 @@ * up_tapdev.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Based on code from uIP which also has a BSD-like license: * diff --git a/arch/sim/src/up_touchscreen.c b/arch/sim/src/up_touchscreen.c index a05b42c74d5ff39f426ae5130ec1e55055b47a89..cc40f50fecbb7765b1501e4a996aee3d4b5f31b3 100644 --- a/arch/sim/src/up_touchscreen.c +++ b/arch/sim/src/up_touchscreen.c @@ -2,7 +2,7 @@ * arch/sim/src/up_touchscreen.c * * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_unblocktask.c b/arch/sim/src/up_unblocktask.c index 684b7fb0bf0dd6f9d2769989d8484a550169d688..04b6455f31c3b0517372accb58b9964a6637b00b 100644 --- a/arch/sim/src/up_unblocktask.c +++ b/arch/sim/src/up_unblocktask.c @@ -2,7 +2,7 @@ * up_unblocktask.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_usestack.c b/arch/sim/src/up_usestack.c index 309dc2dc40ef56080abb7e2b317b4e1520393df0..aa832ff90258acfced9f82ae9b56d585f092ffa2 100644 --- a/arch/sim/src/up_usestack.c +++ b/arch/sim/src/up_usestack.c @@ -2,7 +2,7 @@ * arch/sim/src/up_usestack.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_wpcap.c b/arch/sim/src/up_wpcap.c index 18a6ad4aecb9c146cae2ec7d6a199a6a36c6b160..42e8764f80dd15af30452d70bcfb7e81ac59b76f 100644 --- a/arch/sim/src/up_wpcap.c +++ b/arch/sim/src/up_wpcap.c @@ -2,7 +2,7 @@ * up_wcap.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Based on code from uIP which also has a BSD-like license: * diff --git a/arch/sim/src/up_x11eventloop.c b/arch/sim/src/up_x11eventloop.c index 47838806573f1f0740b8fb826508615757028fcb..e2354dbecaadcf884bac604b301fff7d82bf740d 100644 --- a/arch/sim/src/up_x11eventloop.c +++ b/arch/sim/src/up_x11eventloop.c @@ -2,7 +2,7 @@ * arch/sim/src/up_x11eventloop.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/sim/src/up_x11framebuffer.c b/arch/sim/src/up_x11framebuffer.c index 248156100cfbdada95cd4aee044058db9033150a..a035e2f3a2e9d36999a36b944a4f0bdab138ca0a 100644 --- a/arch/sim/src/up_x11framebuffer.c +++ b/arch/sim/src/up_x11framebuffer.c @@ -2,7 +2,7 @@ * arch/sim/src/up_x11framebuffer.c * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/include/arch.h b/arch/x86/include/arch.h index 966bfbc56400f46628ac7a205aa2b8c4bca93c64..b55880e4ef9350e6881d7fe5d79c400a6edbcc9f 100755 --- a/arch/x86/include/arch.h +++ b/arch/x86/include/arch.h @@ -2,7 +2,7 @@ * arch/x86/include/arch.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/include/i486/arch.h b/arch/x86/include/i486/arch.h index 077c76626129a18ac5ad2bfa4b905089645106d0..64d9d85bf2fa0e26e00b31ff685b6818a1e2de69 100755 --- a/arch/x86/include/i486/arch.h +++ b/arch/x86/include/i486/arch.h @@ -2,7 +2,7 @@ * arch/x86/include/i486/arch.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/include/i486/io.h b/arch/x86/include/i486/io.h index ce3c37ecb7f43892243ce2ad26f28a1da25e713c..6f170ac9754dac99db91a6d548daa8ed9723db38 100644 --- a/arch/x86/include/i486/io.h +++ b/arch/x86/include/i486/io.h @@ -3,7 +3,7 @@ * arch/chip/io.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/include/i486/irq.h b/arch/x86/include/i486/irq.h index bca34b3ba98f46a2ecd92c240cd065a19bff92d6..95dc200e4a0c72823f7b92f3be90730f53171349 100755 --- a/arch/x86/include/i486/irq.h +++ b/arch/x86/include/i486/irq.h @@ -2,7 +2,7 @@ * arch/x86/include/i486/irq.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/include/i486/limits.h b/arch/x86/include/i486/limits.h index ae8a779d4dbf72574a7d722f1d43ac38b1b5e9fb..c2a9a620f03dd3a87b39424b1e631b5108bf6b51 100755 --- a/arch/x86/include/i486/limits.h +++ b/arch/x86/include/i486/limits.h @@ -2,7 +2,7 @@ * arch/x86/include/i486/limits.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/include/i486/syscall.h b/arch/x86/include/i486/syscall.h index 7ca5f81eafb3407b84cefee05899f8c1da2a18ee..96437b4b577eccdb866646bad95c968aaf127617 100644 --- a/arch/x86/include/i486/syscall.h +++ b/arch/x86/include/i486/syscall.h @@ -2,7 +2,7 @@ * arch/x86/include/i486/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/include/i486/types.h b/arch/x86/include/i486/types.h index d6f25f3e0e16dd401abf754893cabe7fce60f66a..e83f5f43592a2bef020d8a15413209fe4a520a32 100755 --- a/arch/x86/include/i486/types.h +++ b/arch/x86/include/i486/types.h @@ -2,7 +2,7 @@ * arch/x86/include/i486/types.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/include/io.h b/arch/x86/include/io.h index 4f88932c52605193d43e45e8e6adecb09e23451d..71225760d8e159693bf70c6b647a19cf9de2146c 100755 --- a/arch/x86/include/io.h +++ b/arch/x86/include/io.h @@ -2,7 +2,7 @@ * arch/x86/include/io.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/include/irq.h b/arch/x86/include/irq.h index 97c8c0f9c774877d0395b5f12ac6fa50b4325bde..3f4c21da66c9f024e504c8860875ee204254a279 100755 --- a/arch/x86/include/irq.h +++ b/arch/x86/include/irq.h @@ -2,7 +2,7 @@ * arch/x86/include/irq.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/include/limits.h b/arch/x86/include/limits.h index 729504edda65892ef7fa2efc9387853ab957456d..9f9c620712294377978fa5c3ef20d6231cbb4e76 100755 --- a/arch/x86/include/limits.h +++ b/arch/x86/include/limits.h @@ -2,7 +2,7 @@ * arch/x86/include/limits.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/include/qemu/arch.h b/arch/x86/include/qemu/arch.h index fc2a7278ba76965603975ebfc0521dda509f37df..097e37fc9128dcba55efaac6603b01d0a216cf4d 100755 --- a/arch/x86/include/qemu/arch.h +++ b/arch/x86/include/qemu/arch.h @@ -2,7 +2,7 @@ * arch/x86/include/qemu/arch.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/include/qemu/irq.h b/arch/x86/include/qemu/irq.h index 23611b83c4c55324d6d02beddd3938266ff438dc..8161e6b83a7cf0099b99e26a6a411a7aa343f7e2 100755 --- a/arch/x86/include/qemu/irq.h +++ b/arch/x86/include/qemu/irq.h @@ -2,7 +2,7 @@ * arch/x86/include/qemu/irq.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/include/syscall.h b/arch/x86/include/syscall.h index 2d3f9a8c08af7d00352c2be80524f4f25b620564..a9171a61977b733527bee98018ef8e8b3d20eef3 100644 --- a/arch/x86/include/syscall.h +++ b/arch/x86/include/syscall.h @@ -2,7 +2,7 @@ * arch/x86/include/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/include/types.h b/arch/x86/include/types.h index 112de8525f3d42ef22a47a7ba605fa5d34138a1c..0a6807b028db929c78be680f7a0764ab96e01d1c 100755 --- a/arch/x86/include/types.h +++ b/arch/x86/include/types.h @@ -2,7 +2,7 @@ * arch/x86/include/types.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/common/up_allocateheap.c b/arch/x86/src/common/up_allocateheap.c index 3273d681fd5d33b3550394fed3caf414bd6509d2..74b169df32b4ba29cb8699157c7c4e6bd16e63ea 100644 --- a/arch/x86/src/common/up_allocateheap.c +++ b/arch/x86/src/common/up_allocateheap.c @@ -2,7 +2,7 @@ * arch/x86/src/common/up_allocateheap.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/common/up_arch.h b/arch/x86/src/common/up_arch.h index 96d49d306e94f6086ff38ddd9e94959f98ce30f0..9d477cd9a8825b8177ead7f79323b1160ec2d403 100644 --- a/arch/x86/src/common/up_arch.h +++ b/arch/x86/src/common/up_arch.h @@ -2,7 +2,7 @@ * arch/x86/src/common/up_arch.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/common/up_assert.c b/arch/x86/src/common/up_assert.c index 776784656853a20298ca060adcd202c3698d94ee..be82a36169b57797924c4aa9c17f981a91dbb9b3 100644 --- a/arch/x86/src/common/up_assert.c +++ b/arch/x86/src/common/up_assert.c @@ -2,7 +2,7 @@ * arch/x86/src/common/up_assert.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/common/up_blocktask.c b/arch/x86/src/common/up_blocktask.c index f11931103807bb94ed987da239909ffcec5dbdbb..530147a9787eb3ef3cecd3412c9b118847aeb985 100755 --- a/arch/x86/src/common/up_blocktask.c +++ b/arch/x86/src/common/up_blocktask.c @@ -2,7 +2,7 @@ * arch/x86/src/common/up_blocktask.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/common/up_copystate.c b/arch/x86/src/common/up_copystate.c index 4ae842308d4c8db2231ef215db30cb9526019bff..5e53e38465c5ac3a37d89a866fb6ec458ff6caa9 100644 --- a/arch/x86/src/common/up_copystate.c +++ b/arch/x86/src/common/up_copystate.c @@ -2,7 +2,7 @@ * arch/x86/src/common/up_copystate.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/common/up_exit.c b/arch/x86/src/common/up_exit.c index 840464da162182c35bbefea7c77272c7a566647d..e3d27b0afef399411ddd54272a7043695644eea0 100644 --- a/arch/x86/src/common/up_exit.c +++ b/arch/x86/src/common/up_exit.c @@ -2,7 +2,7 @@ * common/up_exit.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/common/up_interruptcontext.c b/arch/x86/src/common/up_interruptcontext.c index 6fbe67989d4dc7528860645f7cc727cf390638f2..4cf65f4e1e1efc875501755fdf995bd5b7485af0 100644 --- a/arch/x86/src/common/up_interruptcontext.c +++ b/arch/x86/src/common/up_interruptcontext.c @@ -2,7 +2,7 @@ * arch/x86/src/common/up_interruptcontext.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/common/up_lowputs.c b/arch/x86/src/common/up_lowputs.c index 46c8940ccf4c06794e4c478780d231eecff32ad4..b6ea96cc2cc21664a0bd495f33dac7cad599a762 100644 --- a/arch/x86/src/common/up_lowputs.c +++ b/arch/x86/src/common/up_lowputs.c @@ -2,7 +2,7 @@ * arch/x86/src/common/up_lowputs.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/common/up_mdelay.c b/arch/x86/src/common/up_mdelay.c index 22fc78d0454d71fd77c66bdd81be6be9324fe822..e742470f2357dd730c3bfe84a5e6d598dce1775b 100644 --- a/arch/x86/src/common/up_mdelay.c +++ b/arch/x86/src/common/up_mdelay.c @@ -2,7 +2,7 @@ * arch/x86/src/common/up_mdelay.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/common/up_modifyreg16.c b/arch/x86/src/common/up_modifyreg16.c index 9a7ae45073ef813877476e9b0163507b8861614d..144cd4797cf9bc72d21fe77b902bb115069ab490 100644 --- a/arch/x86/src/common/up_modifyreg16.c +++ b/arch/x86/src/common/up_modifyreg16.c @@ -2,7 +2,7 @@ * arch/x86/src/common/up_modifyreg16.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/common/up_modifyreg32.c b/arch/x86/src/common/up_modifyreg32.c index c2a4003358080d8f8f16f0e09394ad9538814105..9953f52ad64e2f4c182255ce1570b43058587fd9 100644 --- a/arch/x86/src/common/up_modifyreg32.c +++ b/arch/x86/src/common/up_modifyreg32.c @@ -2,7 +2,7 @@ * arch/x86/src/common/up_modifyreg32.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/common/up_modifyreg8.c b/arch/x86/src/common/up_modifyreg8.c index fd4031dc5573e638f6e418c617752c28af411121..d75b7deba5809dd60328d1d4fe57582550ac7eb6 100644 --- a/arch/x86/src/common/up_modifyreg8.c +++ b/arch/x86/src/common/up_modifyreg8.c @@ -2,7 +2,7 @@ * arch/x86/src/common/up_modifyreg8.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/common/up_puts.c b/arch/x86/src/common/up_puts.c index 58420c598fa0441c55e10bdaea8a6012c7f51fb8..c4df9ad71a3d3e33ac142f67b6eb0222cd989835 100644 --- a/arch/x86/src/common/up_puts.c +++ b/arch/x86/src/common/up_puts.c @@ -2,7 +2,7 @@ * arch/x86/src/common/up_puts.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/common/up_releasepending.c b/arch/x86/src/common/up_releasepending.c index f476837da29cb3dd74443fca40429df94eb6aa7e..979e0b50f62676752a82281de00c76e0310b4c74 100755 --- a/arch/x86/src/common/up_releasepending.c +++ b/arch/x86/src/common/up_releasepending.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_releasepending.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/common/up_reprioritizertr.c b/arch/x86/src/common/up_reprioritizertr.c index 5df8c26b06d4bbb4a6ff91eada7ebb565c933866..ad8a748a89929b57508797fbda763148ec324f48 100755 --- a/arch/x86/src/common/up_reprioritizertr.c +++ b/arch/x86/src/common/up_reprioritizertr.c @@ -2,7 +2,7 @@ * arch/arm/src/arm/up_reprioritizertr.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/common/up_udelay.c b/arch/x86/src/common/up_udelay.c index 92d3b7c1678d13b343e3fba4937606da32e81e0e..208b5be4a7f1997e505f700466b1583b800e3aed 100644 --- a/arch/x86/src/common/up_udelay.c +++ b/arch/x86/src/common/up_udelay.c @@ -2,7 +2,7 @@ * arch/x86/src/common/up_udelay.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/common/up_unblocktask.c b/arch/x86/src/common/up_unblocktask.c index 7dd263f1a725c1d6487dbc3f304a595d7a714672..3397b75e5636a29f797b0575ea2b619bca6610e8 100755 --- a/arch/x86/src/common/up_unblocktask.c +++ b/arch/x86/src/common/up_unblocktask.c @@ -2,7 +2,7 @@ * arch/x86/src/common/up_unblocktask.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/i486/i486_utils.S b/arch/x86/src/i486/i486_utils.S index ee89c0c68d437c43855480f8e57c6eccc6c90aa0..f405289220f3c273e6fce86e6c7f9d508e28b8ab 100644 --- a/arch/x86/src/i486/i486_utils.S +++ b/arch/x86/src/i486/i486_utils.S @@ -2,7 +2,7 @@ * arch/x86/src/i486/i486_utils.S * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Based on Bran's kernel development tutorials. Rewritten for JamesM's * kernel development tutorials. diff --git a/arch/x86/src/i486/up_createstack.c b/arch/x86/src/i486/up_createstack.c index 842872d312ef01af7008ada1df234ecaec85960e..1a2f67f335bfffa26511248278e8261ab30d2c06 100644 --- a/arch/x86/src/i486/up_createstack.c +++ b/arch/x86/src/i486/up_createstack.c @@ -2,7 +2,7 @@ * arch/x86/src/i486/up_createstack.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/i486/up_initialstate.c b/arch/x86/src/i486/up_initialstate.c index c1bb422da14c62c3e85331eb992d0e1dd7faffb7..078099bd1245afa5ca47f91b08fbe5166133e10d 100644 --- a/arch/x86/src/i486/up_initialstate.c +++ b/arch/x86/src/i486/up_initialstate.c @@ -2,7 +2,7 @@ * arch/x86/src/i486/up_initialstate.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/i486/up_irq.c b/arch/x86/src/i486/up_irq.c index 01da4962e39ce2abd63111672150bbd61b30f32e..3eb6d6070cb26ff0720db0b94b832d7ae11c500b 100755 --- a/arch/x86/src/i486/up_irq.c +++ b/arch/x86/src/i486/up_irq.c @@ -3,7 +3,7 @@ * arch/x86/src/chip/up_irq.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/i486/up_regdump.c b/arch/x86/src/i486/up_regdump.c index 5a5da0e70bd12862043c8b95274ef257a6a121c6..b7547aec4c75bc9ee56099ba6c741451b2613f2d 100644 --- a/arch/x86/src/i486/up_regdump.c +++ b/arch/x86/src/i486/up_regdump.c @@ -2,7 +2,7 @@ * arch/x86/src/i486/up_regdump.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/i486/up_releasestack.c b/arch/x86/src/i486/up_releasestack.c index ac93688d6c4b97fc83a7679c0cd03f1870d1a52c..a10a001e1ab0d28e7319670103611e482a7ee633 100644 --- a/arch/x86/src/i486/up_releasestack.c +++ b/arch/x86/src/i486/up_releasestack.c @@ -2,7 +2,7 @@ * arch/x86/src/common/up_releasestack.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/i486/up_savestate.c b/arch/x86/src/i486/up_savestate.c index 1d35c62a99d3fa8d2ff59bede8e7c03c3b5f52e8..ce237efac4a60cd6323595c747a8ad5e3174490f 100644 --- a/arch/x86/src/i486/up_savestate.c +++ b/arch/x86/src/i486/up_savestate.c @@ -2,7 +2,7 @@ * arch/x86/src/i486/up_savestate.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/i486/up_schedulesigaction.c b/arch/x86/src/i486/up_schedulesigaction.c index 7d91bb3e319dcb8da4358f5ee692ab26d1c2f00b..bacc126223bf3e7ad394b7884efce90cd29d4c90 100644 --- a/arch/x86/src/i486/up_schedulesigaction.c +++ b/arch/x86/src/i486/up_schedulesigaction.c @@ -2,7 +2,7 @@ * arch/x86/src/i486/up_schedulesigaction.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/i486/up_sigdeliver.c b/arch/x86/src/i486/up_sigdeliver.c index 8dbf466982baad5858c3a9275bc0a3de94853c0a..468f5bc66621e1942903792abb71ad05bec8a21a 100644 --- a/arch/x86/src/i486/up_sigdeliver.c +++ b/arch/x86/src/i486/up_sigdeliver.c @@ -2,7 +2,7 @@ * arch/x86/src/i486/up_sigdeliver.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/i486/up_syscall6.S b/arch/x86/src/i486/up_syscall6.S index 9c6f879e39bab2da3104a796dbce2d9f349da393..3bcbad9ba63ab71b56ece9ff274e2cf148369342 100755 --- a/arch/x86/src/i486/up_syscall6.S +++ b/arch/x86/src/i486/up_syscall6.S @@ -1,97 +1,97 @@ -/**************************************************************************** - * arch/x86/src/i486/up_syscall6.S - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Based on Bran's kernel development tutorials. Rewritten for JamesM's - * kernel development tutorials. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - - .file "up_syscall6.S" - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Globals - ****************************************************************************/ - -/**************************************************************************** - * .text - ****************************************************************************/ - - .text - -/**************************************************************************** - * Name: sys_call6 - * - * C Prototype: - * uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1, - * uintptr_t parm2, uintptr_t parm3, - * uintptr_t parm4, uintptr_t parm5, - * uintptr_t parm6); - * - ****************************************************************************/ - - .global sys_call6 - .type sys_call6, %function - -sys_call6: - pushl %ebp /* Save ebx, esi, edi, and ebp */ - pushl %edi - pushl %esi - pushl %ebx - - movl 44(%esp),%ebp /* Save parm6 in ebp */ - movl 40(%esp),%edi /* Save parm5 in edi */ - movl 36(%esp),%esi /* Save parm4 in esi */ - movl 32(%esp),%edx /* Save parm3 in edx */ - movl 28(%esp),%ecx /* Save parm2 in ecx */ - movl 24(%esp),%ebx /* Save parm1 in ebx */ - movl 20(%esp),%eax /* Save syscall number in eax */ - int $0x80 /* Execute the trap */ - /* Return value is in %eax */ - popl %ebx /* Restore ebx, esi, edi, and ebp */ - popl %esi - popl %edi - popl %ebp - ret /* And return with result in %eax */ - - .size sys_call6,.-sys_call6 - .end +/**************************************************************************** + * arch/x86/src/i486/up_syscall6.S + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Based on Bran's kernel development tutorials. Rewritten for JamesM's + * kernel development tutorials. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + + .file "up_syscall6.S" + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Globals + ****************************************************************************/ + +/**************************************************************************** + * .text + ****************************************************************************/ + + .text + +/**************************************************************************** + * Name: sys_call6 + * + * C Prototype: + * uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1, + * uintptr_t parm2, uintptr_t parm3, + * uintptr_t parm4, uintptr_t parm5, + * uintptr_t parm6); + * + ****************************************************************************/ + + .global sys_call6 + .type sys_call6, %function + +sys_call6: + pushl %ebp /* Save ebx, esi, edi, and ebp */ + pushl %edi + pushl %esi + pushl %ebx + + movl 44(%esp),%ebp /* Save parm6 in ebp */ + movl 40(%esp),%edi /* Save parm5 in edi */ + movl 36(%esp),%esi /* Save parm4 in esi */ + movl 32(%esp),%edx /* Save parm3 in edx */ + movl 28(%esp),%ecx /* Save parm2 in ecx */ + movl 24(%esp),%ebx /* Save parm1 in ebx */ + movl 20(%esp),%eax /* Save syscall number in eax */ + int $0x80 /* Execute the trap */ + /* Return value is in %eax */ + popl %ebx /* Restore ebx, esi, edi, and ebp */ + popl %esi + popl %edi + popl %ebp + ret /* And return with result in %eax */ + + .size sys_call6,.-sys_call6 + .end diff --git a/arch/x86/src/i486/up_usestack.c b/arch/x86/src/i486/up_usestack.c index fb8ded0e14e029da7cac29e252d53188068334ea..4a44c84151d07b644bb3a91100e7f4fbb86a981b 100644 --- a/arch/x86/src/i486/up_usestack.c +++ b/arch/x86/src/i486/up_usestack.c @@ -2,7 +2,7 @@ * arch/x86/src/common/up_usestack.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/qemu/Make.defs b/arch/x86/src/qemu/Make.defs index f4a57128c0d02fa86aa6e41d4c9ab5a2bb1d029d..3c6e99fcca0fcd50860727a9fcc7b0e726625d26 100755 --- a/arch/x86/src/qemu/Make.defs +++ b/arch/x86/src/qemu/Make.defs @@ -2,7 +2,7 @@ # arch/x86/src/qemu/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/x86/src/qemu/chip.h b/arch/x86/src/qemu/chip.h index 0cbf26cb3608d6ad5c8dc8958f4c3c4720d07747..63c7529f2f6535e42292dc716bcdd8babdf754bc 100755 --- a/arch/x86/src/qemu/chip.h +++ b/arch/x86/src/qemu/chip.h @@ -2,7 +2,7 @@ * arch/x86/src/qemu/chip.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/qemu/qemu_fullcontextrestore.S b/arch/x86/src/qemu/qemu_fullcontextrestore.S index ded55a1470b3b10942570f5191ba11e591ae3d4c..50ebdc0411f2a1f4788c7620e2ef161ba78c6868 100644 --- a/arch/x86/src/qemu/qemu_fullcontextrestore.S +++ b/arch/x86/src/qemu/qemu_fullcontextrestore.S @@ -2,7 +2,7 @@ * arch/x86/src/qemu/qemu_fullcontextrestore.S * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/qemu/qemu_handlers.c b/arch/x86/src/qemu/qemu_handlers.c index a85370f767016f918d6385598b424a194067b126..aeb9b8b1fa81e577900e1389f3414eeacc92cbf2 100644 --- a/arch/x86/src/qemu/qemu_handlers.c +++ b/arch/x86/src/qemu/qemu_handlers.c @@ -2,7 +2,7 @@ * arch/x86/src/qemu/qemu_handlers.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/qemu/qemu_head.S b/arch/x86/src/qemu/qemu_head.S index 9933d91ffb911a45b67289468ff529e7942997ee..2b86c1835475e1092acd4393df0ad852863c3c09 100755 --- a/arch/x86/src/qemu/qemu_head.S +++ b/arch/x86/src/qemu/qemu_head.S @@ -1,161 +1,161 @@ -/**************************************************************************** - * arch/x86/src/qemu/qemu_head.S - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - - .file "qemu_head.S" - -/**************************************************************************** - * Pre-processor definitions - ****************************************************************************/ - -/* Memory Map: _sbss is the start of the BSS region (see ld.script) _ebss is - * the end of the BSS regsion (see ld.script). The idle task stack starts at - * the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread - * is the thread that the system boots on and, eventually, becomes the idle, - * do nothing task that runs only when there is nothing else to run. The - * heap continues from there until the end of memory. See g_heapbase below. - */ - -#define STACKBASE ((_ebss + 0x1f) & 0xffffffe0) -#define IDLE_STACK (STACKBASE+CONFIG_IDLETHREAD_STACKSIZE) -#define HEAP_BASE (STACKBASE+CONFIG_IDLETHREAD_STACKSIZE) - -/**************************************************************************** - * Macros - ****************************************************************************/ - -/* Trace macros, use like trace 'i' to print char to serial port. */ - - .macro trace, ch -#ifdef CONFIG_DEBUG - mov $0x3f8, %dx - mov $\ch, %al - out %al, %dx -#endif - .endm - -/**************************************************************************** - * Global Symbols - ****************************************************************************/ - - .global __start /* Making entry point visible to linker */ - .global os_start /* os_start is defined elsewhere */ - .global up_lowsetup /* up_lowsetup is defined elsewhere */ - .global g_heapbase /* The start of the heap */ - -/**************************************************************************** - * .text - ****************************************************************************/ -/**************************************************************************** - * Multiboot Header - ****************************************************************************/ - - /* Setting up the Multiboot header - see GRUB docs for details */ - - .set ALIGN, 1<<0 /* Align loaded modules on page boundaries */ - .set MEMINFO, 1<<1 /* Provide memory map */ - .set FLAGS, ALIGN | MEMINFO /* This is the Multiboot 'flag' field */ - .set MAGIC, 0x1badb002 /* 'magic number' lets bootloader find the header */ - .set CHECKSUM, -(MAGIC + FLAGS) /* Checksum required */ - - .text - .align 4 - .long MAGIC - .long FLAGS - .long CHECKSUM - -/**************************************************************************** - * Name: Start - ****************************************************************************/ - - .type __start, @function -__start: - /* Set up the stack */ - - mov $(idle_stack + CONFIG_IDLETHREAD_STACKSIZE), %esp - - /* Multiboot setup */ - - push %eax /* Multiboot magic number */ - push %ebx /* Multiboot data structure */ - - /* Initialize and start NuttX */ - - call up_lowsetup /* Low-level, pre-OS initialization */ - call os_start /* Start NuttX */ - - /* NuttX will not return */ - - cli -hang: - hlt /* Halt machine should NuttX return */ - jmp hang - .size __start, . - __start - -/**************************************************************************** - * .bss - ****************************************************************************/ - -/* The stack for the IDLE task thread is declared in .bss. NuttX boots and - * initializes on the IDLE thread, then at the completion of OS startup, this - * thread becomes the thread that executes when there is nothing else to - * do in the system (see up_idle()). - */ - - .type idle_stack, @object - .comm idle_stack, CONFIG_IDLETHREAD_STACKSIZE, 32 - .size idle_stack, . - idle_stack - -/**************************************************************************** - * .rodata - ****************************************************************************/ - - .section .rodata, "a" - -/* HEAP BASE: _sbss is the start of the BSS region (see ld.script) _ebss is - * the end of the BSS region (see ld.script). The heap continues from there - * until the end of memory. - */ - - .type g_heapbase, @object -g_heapbase: - .long _ebss - .size g_heapbase, . - g_heapbase - .end +/**************************************************************************** + * arch/x86/src/qemu/qemu_head.S + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + + .file "qemu_head.S" + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +/* Memory Map: _sbss is the start of the BSS region (see ld.script) _ebss is + * the end of the BSS regsion (see ld.script). The idle task stack starts at + * the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread + * is the thread that the system boots on and, eventually, becomes the idle, + * do nothing task that runs only when there is nothing else to run. The + * heap continues from there until the end of memory. See g_heapbase below. + */ + +#define STACKBASE ((_ebss + 0x1f) & 0xffffffe0) +#define IDLE_STACK (STACKBASE+CONFIG_IDLETHREAD_STACKSIZE) +#define HEAP_BASE (STACKBASE+CONFIG_IDLETHREAD_STACKSIZE) + +/**************************************************************************** + * Macros + ****************************************************************************/ + +/* Trace macros, use like trace 'i' to print char to serial port. */ + + .macro trace, ch +#ifdef CONFIG_DEBUG + mov $0x3f8, %dx + mov $\ch, %al + out %al, %dx +#endif + .endm + +/**************************************************************************** + * Global Symbols + ****************************************************************************/ + + .global __start /* Making entry point visible to linker */ + .global os_start /* os_start is defined elsewhere */ + .global up_lowsetup /* up_lowsetup is defined elsewhere */ + .global g_heapbase /* The start of the heap */ + +/**************************************************************************** + * .text + ****************************************************************************/ +/**************************************************************************** + * Multiboot Header + ****************************************************************************/ + + /* Setting up the Multiboot header - see GRUB docs for details */ + + .set ALIGN, 1<<0 /* Align loaded modules on page boundaries */ + .set MEMINFO, 1<<1 /* Provide memory map */ + .set FLAGS, ALIGN | MEMINFO /* This is the Multiboot 'flag' field */ + .set MAGIC, 0x1badb002 /* 'magic number' lets bootloader find the header */ + .set CHECKSUM, -(MAGIC + FLAGS) /* Checksum required */ + + .text + .align 4 + .long MAGIC + .long FLAGS + .long CHECKSUM + +/**************************************************************************** + * Name: Start + ****************************************************************************/ + + .type __start, @function +__start: + /* Set up the stack */ + + mov $(idle_stack + CONFIG_IDLETHREAD_STACKSIZE), %esp + + /* Multiboot setup */ + + push %eax /* Multiboot magic number */ + push %ebx /* Multiboot data structure */ + + /* Initialize and start NuttX */ + + call up_lowsetup /* Low-level, pre-OS initialization */ + call os_start /* Start NuttX */ + + /* NuttX will not return */ + + cli +hang: + hlt /* Halt machine should NuttX return */ + jmp hang + .size __start, . - __start + +/**************************************************************************** + * .bss + ****************************************************************************/ + +/* The stack for the IDLE task thread is declared in .bss. NuttX boots and + * initializes on the IDLE thread, then at the completion of OS startup, this + * thread becomes the thread that executes when there is nothing else to + * do in the system (see up_idle()). + */ + + .type idle_stack, @object + .comm idle_stack, CONFIG_IDLETHREAD_STACKSIZE, 32 + .size idle_stack, . - idle_stack + +/**************************************************************************** + * .rodata + ****************************************************************************/ + + .section .rodata, "a" + +/* HEAP BASE: _sbss is the start of the BSS region (see ld.script) _ebss is + * the end of the BSS region (see ld.script). The heap continues from there + * until the end of memory. + */ + + .type g_heapbase, @object +g_heapbase: + .long _ebss + .size g_heapbase, . - g_heapbase + .end diff --git a/arch/x86/src/qemu/qemu_idle.c b/arch/x86/src/qemu/qemu_idle.c index 42145105b90883e8782e9fb0f3a651166929a4ba..b3c97948ba110232c1af2b9e18fdecdf9299ba52 100644 --- a/arch/x86/src/qemu/qemu_idle.c +++ b/arch/x86/src/qemu/qemu_idle.c @@ -2,7 +2,7 @@ * arch/x86/src/qemu/qemu_idle.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/qemu/qemu_internal.h b/arch/x86/src/qemu/qemu_internal.h index c8bd5cd95de31440d368f48acdcb0ecea662a76d..b63a7b68cd64a1d5b27b667f62fa7dbd9cd0e119 100755 --- a/arch/x86/src/qemu/qemu_internal.h +++ b/arch/x86/src/qemu/qemu_internal.h @@ -2,7 +2,7 @@ * arch/x86/src/qemu/qemu_internal.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/qemu/qemu_lowputc.c b/arch/x86/src/qemu/qemu_lowputc.c index 1fa4aa6c59980cc033b080f8a5447ec5cb70fb61..9bfee18d05d9768047cbf99948f74ae6d098e4a8 100644 --- a/arch/x86/src/qemu/qemu_lowputc.c +++ b/arch/x86/src/qemu/qemu_lowputc.c @@ -2,7 +2,7 @@ * arch/x86/src/qemu/qemu_lowputc.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/qemu/qemu_memorymap.h b/arch/x86/src/qemu/qemu_memorymap.h index 571ddd03d7e008b728846eff451b235849ffbf23..1bb8afe68df9969312e9f5898a21eaee5347b8bd 100755 --- a/arch/x86/src/qemu/qemu_memorymap.h +++ b/arch/x86/src/qemu/qemu_memorymap.h @@ -1,67 +1,67 @@ -/************************************************************************************ - * arch/x86/src/qemu/qemu_memorymap.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_X86_SRC_QEMU_QEMU_MEMORYMAP_H -#define __ARCH_X86_SRC_QEMU_QEMU_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Memory Map ***********************************************************************/ - -/* Peripheral Base Addresses ********************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_X86_SRC_QEMU_QEMU_MEMORYMAP_H */ +/************************************************************************************ + * arch/x86/src/qemu/qemu_memorymap.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_X86_SRC_QEMU_QEMU_MEMORYMAP_H +#define __ARCH_X86_SRC_QEMU_QEMU_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory Map ***********************************************************************/ + +/* Peripheral Base Addresses ********************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_X86_SRC_QEMU_QEMU_MEMORYMAP_H */ diff --git a/arch/x86/src/qemu/qemu_saveusercontext.S b/arch/x86/src/qemu/qemu_saveusercontext.S index 427c3bd5d40da25cf95301badf81166986fbc356..ab12447986cb10b7f73b3bd3f6f6acb5221868cf 100644 --- a/arch/x86/src/qemu/qemu_saveusercontext.S +++ b/arch/x86/src/qemu/qemu_saveusercontext.S @@ -2,7 +2,7 @@ * arch/x86/src/qemu/up_saveusercontext.S * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/x86/src/qemu/qemu_timerisr.c b/arch/x86/src/qemu/qemu_timerisr.c index 531b7d09d9180254857ce316ab8417c25f2998c3..b363d226788c146b956ab4a51942b18197a5b050 100755 --- a/arch/x86/src/qemu/qemu_timerisr.c +++ b/arch/x86/src/qemu/qemu_timerisr.c @@ -2,7 +2,7 @@ * arch/x86/src/qemu/qemu_timerisr.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Based on Bran's kernel development tutorials. Rewritten for JamesM's * kernel development tutorials. diff --git a/arch/x86/src/qemu/qemu_vectors.S b/arch/x86/src/qemu/qemu_vectors.S index d6e17e57bcbfbf1383e2a3da2e925a0b054080c7..8a68e2e09542052b2cfb724ccc1b8815a5a36898 100755 --- a/arch/x86/src/qemu/qemu_vectors.S +++ b/arch/x86/src/qemu/qemu_vectors.S @@ -2,7 +2,7 @@ * arch/x86/src/qemu/qemu_head.S * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Based on Bran's kernel development tutorials. Rewritten for JamesM's * kernel development tutorials. diff --git a/arch/z16/include/arch.h b/arch/z16/include/arch.h index f32e2a998edf65581fe26a92a6ca3ad2bedf6536..31dfe61d036be8f93bb6fbcfc4be04282047ba4f 100644 --- a/arch/z16/include/arch.h +++ b/arch/z16/include/arch.h @@ -2,7 +2,7 @@ * arch/arch.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/include/irq.h b/arch/z16/include/irq.h index 116cba8fa8aab76d3491e4889a3b78e2d4f075b0..4926510288fce1bfdf665cb8d3ffe0f2538fc437 100644 --- a/arch/z16/include/irq.h +++ b/arch/z16/include/irq.h @@ -2,7 +2,7 @@ * arch/irq.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/include/serial.h b/arch/z16/include/serial.h index c46a8c35d0cd8165bafc151abeca50a273097d1d..15d49ee434c4c477b114c0d96afda925b5e1c12f 100644 --- a/arch/z16/include/serial.h +++ b/arch/z16/include/serial.h @@ -2,7 +2,7 @@ * arch/serial.h * * Copyright (C) 2007 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/include/syscall.h b/arch/z16/include/syscall.h index a009452c0184260fdec84391148db630148de843..c682189d8051151fe39986064deaaac1131e9b89 100644 --- a/arch/z16/include/syscall.h +++ b/arch/z16/include/syscall.h @@ -2,7 +2,7 @@ * arch/z16/include/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/include/types.h b/arch/z16/include/types.h index 536cb52a74c53c7a2d0d9055a9214042c1684a23..e58a93ba1ca4eda8c1cce06cec0f28c5d4c01a34 100644 --- a/arch/z16/include/types.h +++ b/arch/z16/include/types.h @@ -2,7 +2,7 @@ * arch/z16/include/types.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/include/z16f/arch.h b/arch/z16/include/z16f/arch.h index 3d0e02c209cf8b82d46423e2521fb32eb5e8d415..52f77228a2e013339ed1c4a08f43d55f17c5c274 100644 --- a/arch/z16/include/z16f/arch.h +++ b/arch/z16/include/z16f/arch.h @@ -3,7 +3,7 @@ * arch/chip/arch.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/include/z16f/irq.h b/arch/z16/include/z16f/irq.h index 46abe4d3f0ac4cc7130483ba5a3791df5b3cfc49..83b251e81b8efa76d2a4858c3a0acf5d3d4a0299 100644 --- a/arch/z16/include/z16f/irq.h +++ b/arch/z16/include/z16f/irq.h @@ -3,7 +3,7 @@ * arch/chip/irq.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_allocateheap.c b/arch/z16/src/common/up_allocateheap.c index 0b6c766d36882aa70918d6a4a42448643ec5a78a..72686b7516f8ed48c9f07ed881aa32e76d330511 100644 --- a/arch/z16/src/common/up_allocateheap.c +++ b/arch/z16/src/common/up_allocateheap.c @@ -2,7 +2,7 @@ * common/up_allocateheap.c * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_assert.c b/arch/z16/src/common/up_assert.c index d1bedb065eed463402e6b367c6c773095541671d..d7d614a91919ad8909ad92452a43794aaeecf14b 100644 --- a/arch/z16/src/common/up_assert.c +++ b/arch/z16/src/common/up_assert.c @@ -2,7 +2,7 @@ * common/up_assert.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_blocktask.c b/arch/z16/src/common/up_blocktask.c index 015ebed3a158f0f991e743e9a55b62a75d2ff6f5..88b422cf8889941752cbb69f9fa125da2fc7f5be 100644 --- a/arch/z16/src/common/up_blocktask.c +++ b/arch/z16/src/common/up_blocktask.c @@ -2,7 +2,7 @@ * common/up_blocktask.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_copystate.c b/arch/z16/src/common/up_copystate.c index 1a48536d736c6e43cdd5f53f17aae71664ebf72d..d3a4d47a056b06b4e631e215e3c09bf874225a9f 100644 --- a/arch/z16/src/common/up_copystate.c +++ b/arch/z16/src/common/up_copystate.c @@ -2,7 +2,7 @@ * common/up_copystate.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_createstack.c b/arch/z16/src/common/up_createstack.c index 1adcc78358d8fc5546f39df8e9057027db5ad549..ed9b1655cb5a56aa46bc6044cace8e8a5c62e200 100644 --- a/arch/z16/src/common/up_createstack.c +++ b/arch/z16/src/common/up_createstack.c @@ -2,7 +2,7 @@ * arch/z16/common/up_createstack.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_doirq.c b/arch/z16/src/common/up_doirq.c index 3adddf6db181254e35a4edbfa46c9e42e94ea77e..e8f40fb5637c916d607fdf4b41fd4a5a549954b6 100644 --- a/arch/z16/src/common/up_doirq.c +++ b/arch/z16/src/common/up_doirq.c @@ -2,7 +2,7 @@ * common/up_doirq.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_exit.c b/arch/z16/src/common/up_exit.c index be5411b1f95ff4ba953276b3a5359784c444b416..41f058347213f735e3a69637da01e9a9861132a7 100644 --- a/arch/z16/src/common/up_exit.c +++ b/arch/z16/src/common/up_exit.c @@ -2,7 +2,7 @@ * common/up_exit.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_idle.c b/arch/z16/src/common/up_idle.c index 154e041bcd310baed161e250fd79d035c10227e5..58cd1afc6630ebba43058be9bda7b771c897cdf7 100644 --- a/arch/z16/src/common/up_idle.c +++ b/arch/z16/src/common/up_idle.c @@ -2,7 +2,7 @@ * common/up_idle.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_initialstate.c b/arch/z16/src/common/up_initialstate.c index c01c18e89c2763a975141177abd2321b23785167..8938679aca5d3db0a67525b418d6fdd4053da265 100644 --- a/arch/z16/src/common/up_initialstate.c +++ b/arch/z16/src/common/up_initialstate.c @@ -2,7 +2,7 @@ * common/up_initialstate.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_interruptcontext.c b/arch/z16/src/common/up_interruptcontext.c index fe9c281f7168822cc2eb914e09ce6afad91b15eb..99cc4abe77254ab0232172701722758097a8cc39 100644 --- a/arch/z16/src/common/up_interruptcontext.c +++ b/arch/z16/src/common/up_interruptcontext.c @@ -2,7 +2,7 @@ * common/up_interruptcontext.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_mdelay.c b/arch/z16/src/common/up_mdelay.c index 94ae885411500273c4e6442a672f227000ee4ed5..d69253ab07fc8c52cbf55fba8fbdec032fadbad7 100644 --- a/arch/z16/src/common/up_mdelay.c +++ b/arch/z16/src/common/up_mdelay.c @@ -2,7 +2,7 @@ * common/up_mdelay.c * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_registerdump.c b/arch/z16/src/common/up_registerdump.c index 90c7d79c5298e1d259591578a62df88a26973645..dd1f210f7510eac501652972a2ecce1b1d26a40a 100644 --- a/arch/z16/src/common/up_registerdump.c +++ b/arch/z16/src/common/up_registerdump.c @@ -2,7 +2,7 @@ * common/up_registerdump.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_releasepending.c b/arch/z16/src/common/up_releasepending.c index a91d7850333172598071d282c0f60ec4bde3b099..ff9a9782ee91bc54645fe235fc2a0c4f57fbd267 100644 --- a/arch/z16/src/common/up_releasepending.c +++ b/arch/z16/src/common/up_releasepending.c @@ -2,7 +2,7 @@ * common/up_releasepending.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_releasestack.c b/arch/z16/src/common/up_releasestack.c index 6f96c0c30fdb33652c45b2a74c96acf094507147..f064cae7ffda6d80f8901dcd088063d2b0023815 100644 --- a/arch/z16/src/common/up_releasestack.c +++ b/arch/z16/src/common/up_releasestack.c @@ -2,7 +2,7 @@ * common/up_releasestack.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_reprioritizertr.c b/arch/z16/src/common/up_reprioritizertr.c index e0ddc364b577f432337b1562c8f78413324fbd96..0363184cd5df6a9f603ee5ecefd32fd24e13b9d6 100644 --- a/arch/z16/src/common/up_reprioritizertr.c +++ b/arch/z16/src/common/up_reprioritizertr.c @@ -2,7 +2,7 @@ * common/up_reprioritizertr.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_schedulesigaction.c b/arch/z16/src/common/up_schedulesigaction.c index 368b2ed541900c1a9a3eaf0c3381b653acc61a8c..1c5b9a78c594af7f0666b9f3273f569d3bf3aec1 100644 --- a/arch/z16/src/common/up_schedulesigaction.c +++ b/arch/z16/src/common/up_schedulesigaction.c @@ -2,7 +2,7 @@ * common/up_schedulesigaction.c * * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_sigdeliver.c b/arch/z16/src/common/up_sigdeliver.c index 4ca05d17ba639a036f60b3ef3c3f1a63ccb7fa0d..d8636bd6f5f4e0c58660dedd033c22f8bae3a4c6 100644 --- a/arch/z16/src/common/up_sigdeliver.c +++ b/arch/z16/src/common/up_sigdeliver.c @@ -2,7 +2,7 @@ * common/up_sigdeliver.c * * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_stackdump.c b/arch/z16/src/common/up_stackdump.c index 8f63e2c59dc2b85d9b462a00fabb97a5f2e4af42..b4930f620698d29ba50c6657fc59270822306ba2 100644 --- a/arch/z16/src/common/up_stackdump.c +++ b/arch/z16/src/common/up_stackdump.c @@ -2,7 +2,7 @@ * common/up_stackdump.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_udelay.c b/arch/z16/src/common/up_udelay.c index f909eb18c99d8583b31afd6ecae33d1951fe85fc..a68b6a1723f21ef5568b53528b01ab8122757508 100644 --- a/arch/z16/src/common/up_udelay.c +++ b/arch/z16/src/common/up_udelay.c @@ -2,7 +2,7 @@ * common/up_udelay.c * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_unblocktask.c b/arch/z16/src/common/up_unblocktask.c index 3e4958ab54b14a57aa33a221ea0ff2052f69bbf2..d72d554241d7ae6cc06692863f285f62e9e2d219 100644 --- a/arch/z16/src/common/up_unblocktask.c +++ b/arch/z16/src/common/up_unblocktask.c @@ -2,7 +2,7 @@ * common/up_unblocktask.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/common/up_usestack.c b/arch/z16/src/common/up_usestack.c index 14a18ccb3387d1f37ef0a48e9fa856c63df4568b..69e4763c53e1dea58d5f17cbc323df5e322b9ddf 100644 --- a/arch/z16/src/common/up_usestack.c +++ b/arch/z16/src/common/up_usestack.c @@ -2,7 +2,7 @@ * arch/z16/common/up_usestack.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/z16f/Make.defs b/arch/z16/src/z16f/Make.defs index 3fb62ae73e9bbf86740f9dae165171c45a8161da..4c47cf41bc258270bcf60222ca8bee63d3299d76 100644 --- a/arch/z16/src/z16f/Make.defs +++ b/arch/z16/src/z16f/Make.defs @@ -2,7 +2,7 @@ # arch/z16/src/z16f/Make.defs # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/z16/src/z16f/chip.h b/arch/z16/src/z16f/chip.h index f4b0cd0ed85dcbe12207e399df6afa1e811d8404..bf4b7fd0ca838c7e8742c776645563051b39888a 100644 --- a/arch/z16/src/z16f/chip.h +++ b/arch/z16/src/z16f/chip.h @@ -3,7 +3,7 @@ * include/arch/chip/chip.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/z16f/z16f_clkinit.c b/arch/z16/src/z16f/z16f_clkinit.c index 298fbb45ae5cf92200f52660379542947a7c0fc9..9aa80ec50593ef2bcc00f6f8c2e8e43e33b97572 100644 --- a/arch/z16/src/z16f/z16f_clkinit.c +++ b/arch/z16/src/z16f/z16f_clkinit.c @@ -2,7 +2,7 @@ * z16f/z16f_clkinit.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Based upon sample code included with the Zilog ZDS-II toolchain. * diff --git a/arch/z16/src/z16f/z16f_irq.c b/arch/z16/src/z16f/z16f_irq.c index ed29a810190a9a82142f9f360879a4a4c36b6083..5c089d654d379f1d4debe2214d648c3bc4d3c2ac 100644 --- a/arch/z16/src/z16f/z16f_irq.c +++ b/arch/z16/src/z16f/z16f_irq.c @@ -2,7 +2,7 @@ * z16f/z16f_irq.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/z16f/z16f_restoreusercontext.S b/arch/z16/src/z16f/z16f_restoreusercontext.S index 0d6f5fec1be1e2bf99b9df7d4d66a6443a342503..796874fbaa0e5757b89a332db190dcd1859b7780 100755 --- a/arch/z16/src/z16f/z16f_restoreusercontext.S +++ b/arch/z16/src/z16f/z16f_restoreusercontext.S @@ -2,7 +2,7 @@ * arch/z16/src/z16f/z16f_restoreusercontext.asm * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/z16f/z16f_saveusercontext.S b/arch/z16/src/z16f/z16f_saveusercontext.S index 892f9779e88a8f193bde20a13addf0d1057f58b7..6b56c2a498dfca5c9e02247791194743c5b4b480 100644 --- a/arch/z16/src/z16f/z16f_saveusercontext.S +++ b/arch/z16/src/z16f/z16f_saveusercontext.S @@ -2,7 +2,7 @@ * arch/z16/src/z16f/z16f_saveusercontext.asm * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/z16f/z16f_sysexec.c b/arch/z16/src/z16f/z16f_sysexec.c index 889e768823d8bfda8df914a93352f1dcc34e08e6..2fbc1e2c96ee50c52c4f1f6952cd6fbd3b702bd8 100644 --- a/arch/z16/src/z16f/z16f_sysexec.c +++ b/arch/z16/src/z16f/z16f_sysexec.c @@ -2,7 +2,7 @@ * z16f/z16f_sysexec.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z16/src/z16f/z16f_timerisr.c b/arch/z16/src/z16f/z16f_timerisr.c index 981cc54f018975a8184ffeda7e2a8d9632806c4f..2849fd0af9bb7d4398b7451d8a244225fcd9b836 100644 --- a/arch/z16/src/z16f/z16f_timerisr.c +++ b/arch/z16/src/z16f/z16f_timerisr.c @@ -2,7 +2,7 @@ * z16f/z16f_timerisr.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/arch.h b/arch/z80/include/arch.h index ff3a059e0d00b87e8b4997950d2d37d12dcc2ed2..112fcde3aa8a7a2dbb7b972924c187a92c1c86bc 100644 --- a/arch/z80/include/arch.h +++ b/arch/z80/include/arch.h @@ -2,7 +2,7 @@ * arch/arch.h * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/ez80/arch.h b/arch/z80/include/ez80/arch.h index 2440c12e4901637a0c698c3c3710f61233a58028..e86d1004b368ef1bd9e80f6c172fc33434e38047 100644 --- a/arch/z80/include/ez80/arch.h +++ b/arch/z80/include/ez80/arch.h @@ -3,7 +3,7 @@ * arch/chip/arch.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/ez80/io.h b/arch/z80/include/ez80/io.h index fc41ccb596e56fe66032be5cbf6926e9d52d618c..b5f23d38e68cd1fe3836f360e2272e56435ee852 100644 --- a/arch/z80/include/ez80/io.h +++ b/arch/z80/include/ez80/io.h @@ -3,7 +3,7 @@ * arch/chip/io.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/ez80/irq.h b/arch/z80/include/ez80/irq.h index 49039fbce285d9f69d2ca0e2d749192a28ffb420..5d57e244b54eeb6a66d63730719005f1b83fb375 100644 --- a/arch/z80/include/ez80/irq.h +++ b/arch/z80/include/ez80/irq.h @@ -3,7 +3,7 @@ * arch/chip/irq.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/ez80/types.h b/arch/z80/include/ez80/types.h index f3569d9baa36134b951126abc24e2014efc35a5e..f7ec1d38575cbdfab9c73a50e66ca2aa1710f1a5 100644 --- a/arch/z80/include/ez80/types.h +++ b/arch/z80/include/ez80/types.h @@ -3,7 +3,7 @@ * include/arch/chip/types.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/io.h b/arch/z80/include/io.h index ce6a90ab5b94f373b2b460c115dac2f320b2f7f6..dacc0bc5b4b4b3f6beaba833e2a770a67bbbd346 100644 --- a/arch/z80/include/io.h +++ b/arch/z80/include/io.h @@ -3,7 +3,7 @@ * arch/chip/io.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/irq.h b/arch/z80/include/irq.h index 62957914f2127bf090b63b8200623f51e8e4a60b..a617540a98e81babe60a6cd2e922801df437e4bb 100644 --- a/arch/z80/include/irq.h +++ b/arch/z80/include/irq.h @@ -2,7 +2,7 @@ * arch/z80/include/irq.h * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/limits.h b/arch/z80/include/limits.h index 27707012d735adf3f4ee4a9d309f88fc1a2d66a5..3cfd65dc6bcebbca8e7785acdcc2fa65450e8615 100644 --- a/arch/z80/include/limits.h +++ b/arch/z80/include/limits.h @@ -2,7 +2,7 @@ * arch/z80/include/limits.h * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/serial.h b/arch/z80/include/serial.h index 91a0184c4ff20c2aefb6be4d278298f56ee79671..2688c045f5c4b42f4821734ce8790b9e68fb2f99 100644 --- a/arch/z80/include/serial.h +++ b/arch/z80/include/serial.h @@ -2,7 +2,7 @@ * arch/z80/include/serial.h * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/syscall.h b/arch/z80/include/syscall.h index a20711c13c4c452d069e2610cc2da4720a4af78c..b1894ca347604da1fdc2a1d99c8e3512cfe7cd61 100644 --- a/arch/z80/include/syscall.h +++ b/arch/z80/include/syscall.h @@ -2,7 +2,7 @@ * arch/z80/include/syscall.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/types.h b/arch/z80/include/types.h index 67f44ddd48033df8ff189794b2ee3f078c44cca1..5b2b5ff16fc2bace6aa7db802f3e396f6b898010 100644 --- a/arch/z80/include/types.h +++ b/arch/z80/include/types.h @@ -2,7 +2,7 @@ * arch/z80/include/types.h * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/z8/arch.h b/arch/z80/include/z8/arch.h index d5f02a49acfd44636d12539af9b701ba10c5a40b..d834bd7919fafbdcd619bf0891e1e2aba82c1985 100644 --- a/arch/z80/include/z8/arch.h +++ b/arch/z80/include/z8/arch.h @@ -3,7 +3,7 @@ * arch/chip/arch.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/z8/irq.h b/arch/z80/include/z8/irq.h index fb0cc7281f406a5f89751899294d30f552021252..3a0c75900bf67e296038fc3b2a063ff84c1862a6 100644 --- a/arch/z80/include/z8/irq.h +++ b/arch/z80/include/z8/irq.h @@ -3,7 +3,7 @@ * arch/chip/irq.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/z8/types.h b/arch/z80/include/z8/types.h index 324ca236c4c96b58bcbdd532c20286266e9516d0..f9aee3ff9a95e2ccd560e93b507bd1be6987ef00 100644 --- a/arch/z80/include/z8/types.h +++ b/arch/z80/include/z8/types.h @@ -3,7 +3,7 @@ * include/arch/chip/types.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/z80/arch.h b/arch/z80/include/z80/arch.h index e9033596cd8cacacafc072bd4659235591c1c4a7..eb9a838603789b670ec09b1851e08d1d34de3483 100644 --- a/arch/z80/include/z80/arch.h +++ b/arch/z80/include/z80/arch.h @@ -3,7 +3,7 @@ * arch/chip/arch.h * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/z80/io.h b/arch/z80/include/z80/io.h index f3cc992eeb4bd2f864e11f0f2c2fd5a4588e797b..b45526a03f2ae463c4c9e6d8c232b18bb10b88ec 100644 --- a/arch/z80/include/z80/io.h +++ b/arch/z80/include/z80/io.h @@ -3,7 +3,7 @@ * arch/chip/io.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/z80/irq.h b/arch/z80/include/z80/irq.h index cc0cb25cc9a2e474fa73cee0c0da91a9c0f81dc6..6c172c63325b55efb2c94b5a40b8befecfa0e509 100644 --- a/arch/z80/include/z80/irq.h +++ b/arch/z80/include/z80/irq.h @@ -3,7 +3,7 @@ * arch/chip/irq.h * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/include/z80/types.h b/arch/z80/include/z80/types.h index 42bba5ac803d1979d00414c1c8e737b4a7499367..19dab710340108efe6b75aebbb521a99ec01a69e 100644 --- a/arch/z80/include/z80/types.h +++ b/arch/z80/include/z80/types.h @@ -3,7 +3,7 @@ * include/arch/chip/types.h * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_allocateheap.c b/arch/z80/src/common/up_allocateheap.c index 368785cf2c3bfb8230774a465d11678152ae86ee..94b06e3755d13624754c57c878ef20057c486c1d 100644 --- a/arch/z80/src/common/up_allocateheap.c +++ b/arch/z80/src/common/up_allocateheap.c @@ -2,7 +2,7 @@ * common/up_allocateheap.c * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_arch.h b/arch/z80/src/common/up_arch.h index 0cb523ea10fe3bde031d97ddd9168bb9b77b2e8b..99087bb088068c21302665e5757ce7c309b2b983 100644 --- a/arch/z80/src/common/up_arch.h +++ b/arch/z80/src/common/up_arch.h @@ -2,7 +2,7 @@ * common/up_arch.h * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_assert.c b/arch/z80/src/common/up_assert.c index 9fe66ecdafa4fd57a95e270e55e0e000530835bf..b35e8dd33a8fdefdaf9e07d713d64da0ec2031d5 100644 --- a/arch/z80/src/common/up_assert.c +++ b/arch/z80/src/common/up_assert.c @@ -2,7 +2,7 @@ * common/up_assert.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_blocktask.c b/arch/z80/src/common/up_blocktask.c index 7feb02169f9770486edb38670e1f270d56513b04..bbc2be5e658e6163fb18c568b3641abaccb00c54 100644 --- a/arch/z80/src/common/up_blocktask.c +++ b/arch/z80/src/common/up_blocktask.c @@ -2,7 +2,7 @@ * arch/z80/src/common/up_blocktask.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_createstack.c b/arch/z80/src/common/up_createstack.c index 6ffaa272bf1157dffd37c335d6bf4973a6ea6ed7..28246aec331faedf8cdad5c451130abcc4d83760 100644 --- a/arch/z80/src/common/up_createstack.c +++ b/arch/z80/src/common/up_createstack.c @@ -2,7 +2,7 @@ * arch/z80/src/common/up_createstack.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_doirq.c b/arch/z80/src/common/up_doirq.c index 828806a496547d748d9338c80f8c9db03b985170..fd871e2462583a0d36269d207f4b4f07598d1f03 100644 --- a/arch/z80/src/common/up_doirq.c +++ b/arch/z80/src/common/up_doirq.c @@ -2,7 +2,7 @@ * arch/z80/src/common/up_doirq.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_exit.c b/arch/z80/src/common/up_exit.c index f57fd442c7d595caa28d1fd1a0c7a2ce520959b7..85ddd841ef25fbe88281d1ab4df465c470c67f79 100644 --- a/arch/z80/src/common/up_exit.c +++ b/arch/z80/src/common/up_exit.c @@ -2,7 +2,7 @@ * common/up_exit.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_idle.c b/arch/z80/src/common/up_idle.c index 550bc124d8a24e1e8faf06a89b5ca6728b9d8e5c..938a150a0d09555e5d459c7752fffc3db8d4cc30 100644 --- a/arch/z80/src/common/up_idle.c +++ b/arch/z80/src/common/up_idle.c @@ -2,7 +2,7 @@ * common/up_idle.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_internal.h b/arch/z80/src/common/up_internal.h index 919a74353bafb230dbaaa85453a35f48f658ca1a..960061a8023a71afe4d53d272c6a0ce876d53197 100644 --- a/arch/z80/src/common/up_internal.h +++ b/arch/z80/src/common/up_internal.h @@ -2,7 +2,7 @@ * arch/z80/src/common/up_internal.h * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_interruptcontext.c b/arch/z80/src/common/up_interruptcontext.c index e8887abef09f453948454fd584928e86db1520cd..31a63641896e8e6aeae46b967b9e4f28968779b9 100644 --- a/arch/z80/src/common/up_interruptcontext.c +++ b/arch/z80/src/common/up_interruptcontext.c @@ -2,7 +2,7 @@ * arch/z80/src/common/up_interruptcontext.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_mdelay.c b/arch/z80/src/common/up_mdelay.c index 33a8130639085e5c9de9c59eeeb2965565fa6664..dd09043fc7a8ccac64cc7a125f2c78010450dd69 100644 --- a/arch/z80/src/common/up_mdelay.c +++ b/arch/z80/src/common/up_mdelay.c @@ -2,7 +2,7 @@ * common/up_mdelay.c * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_puts.c b/arch/z80/src/common/up_puts.c index 06c38573dd00f190d1f770a3616c8c90856cd299..a91d05c0c89cd50350028bea83b8084d49d6e1d0 100644 --- a/arch/z80/src/common/up_puts.c +++ b/arch/z80/src/common/up_puts.c @@ -2,7 +2,7 @@ * arch/z80/src/common/up_puts.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_releasepending.c b/arch/z80/src/common/up_releasepending.c index 8090cb763c9e49eda4bb5c22a0b2ac5bbbd5173a..bb51874653de0a3c0c64830c90d75848bb83d944 100644 --- a/arch/z80/src/common/up_releasepending.c +++ b/arch/z80/src/common/up_releasepending.c @@ -2,7 +2,7 @@ * arch/z80/src/common/up_releasepending.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_releasestack.c b/arch/z80/src/common/up_releasestack.c index 549879725bc1780c67572aa285f505226910977f..d41cc9918259148de945a31c8e1d412c8df6118a 100644 --- a/arch/z80/src/common/up_releasestack.c +++ b/arch/z80/src/common/up_releasestack.c @@ -2,7 +2,7 @@ * common/up_releasestack.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_reprioritizertr.c b/arch/z80/src/common/up_reprioritizertr.c index f520500330a15048c2fa6b69d21c2e7b9119fa80..84cd3e1e10d89cadf562aba8de3a3ce672ab2a05 100644 --- a/arch/z80/src/common/up_reprioritizertr.c +++ b/arch/z80/src/common/up_reprioritizertr.c @@ -2,7 +2,7 @@ * arch/z80/src/common/up_reprioritizertr.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_stackdump.c b/arch/z80/src/common/up_stackdump.c index be6c67dd439191ad31f7624545b99645bc70887e..817c2d3156fd885d17410339a8d2fad257906d56 100644 --- a/arch/z80/src/common/up_stackdump.c +++ b/arch/z80/src/common/up_stackdump.c @@ -2,7 +2,7 @@ * common/up_stackdump.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_udelay.c b/arch/z80/src/common/up_udelay.c index 06faa9a80eb8e9552e981c3a6c445cde0263cd6c..f03357418f0db37b807d7b265cdae3406f5c5d98 100644 --- a/arch/z80/src/common/up_udelay.c +++ b/arch/z80/src/common/up_udelay.c @@ -2,7 +2,7 @@ * common/up_udelay.c * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_unblocktask.c b/arch/z80/src/common/up_unblocktask.c index 33d98e864d483ea4c0ea0650a4a34973ff9a599f..d99d6d87dfc93a9e14bb6a3b07f291eb43b6e8f6 100644 --- a/arch/z80/src/common/up_unblocktask.c +++ b/arch/z80/src/common/up_unblocktask.c @@ -2,7 +2,7 @@ * arch/z80/src/common/up_unblocktask.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/common/up_usestack.c b/arch/z80/src/common/up_usestack.c index 7f22e9ce62e7daefd8ddc3b9eaeea37649c3564e..7d348a9c6578a148186217b3f0c0c6e83d44da45 100644 --- a/arch/z80/src/common/up_usestack.c +++ b/arch/z80/src/common/up_usestack.c @@ -2,7 +2,7 @@ * arch/z80/src/common/up_usestack.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/Make.defs b/arch/z80/src/ez80/Make.defs index 8999b6a66bc860ac4ec4e654cea9a56aa76b0a2c..fb2b3d48f8a6db044a8dc34e1ff80d62f194e654 100644 --- a/arch/z80/src/ez80/Make.defs +++ b/arch/z80/src/ez80/Make.defs @@ -2,7 +2,7 @@ # arch/z80/src/ez80/Make.defs # # Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/chip.h b/arch/z80/src/ez80/chip.h index 3402943aec30ed2b1fbaabdfb67aadd2393df072..8bc6d0eefc52f1dcb2f50f16a8f29efc6d46891a 100644 --- a/arch/z80/src/ez80/chip.h +++ b/arch/z80/src/ez80/chip.h @@ -3,7 +3,7 @@ * arch/z80/src/chip/chip.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/ez80_clock.c b/arch/z80/src/ez80/ez80_clock.c index 8446e8124f615dedcf5b1d40d41da997fcc84985..3cbe1f8f441b6de44afcb2a6aa50a26e1d07abf6 100644 --- a/arch/z80/src/ez80/ez80_clock.c +++ b/arch/z80/src/ez80/ez80_clock.c @@ -2,7 +2,7 @@ * arch/z80/src/ez80/ez80_clock.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/ez80_copystate.c b/arch/z80/src/ez80/ez80_copystate.c index 976817c6ebe26c923b1694f9008b90beafff52ed..c85d2b7169560e43d74e9c70b48e3841f21c4a06 100644 --- a/arch/z80/src/ez80/ez80_copystate.c +++ b/arch/z80/src/ez80/ez80_copystate.c @@ -2,7 +2,7 @@ * arch/z80/src/ez80/ez80_copystate.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/ez80_i2c.c b/arch/z80/src/ez80/ez80_i2c.c index 609ab22bd57e0c1dece5959c05ef3672207f9547..dbc817442c4dba57d10b8f5dd49e33ed5155dee0 100644 --- a/arch/z80/src/ez80/ez80_i2c.c +++ b/arch/z80/src/ez80/ez80_i2c.c @@ -2,7 +2,7 @@ * arch/z80/src/ez80/ez80_i2c.c * * Copyright(C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/ez80_initialstate.c b/arch/z80/src/ez80/ez80_initialstate.c index 5b6e5fb4b7bf7413edb2026923fad20f1d99d1ff..9ff56e7c1791c5e41ace96997164503dc22362d7 100644 --- a/arch/z80/src/ez80/ez80_initialstate.c +++ b/arch/z80/src/ez80/ez80_initialstate.c @@ -2,7 +2,7 @@ * arch/z80/src/ez80/ez80_initialstate.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/ez80_io.asm b/arch/z80/src/ez80/ez80_io.asm index 9c5d28e7e49fb0478ce141a1d86c53aabfde13be..32cd5296c042b32fbab0c4b4609dd6e7e510f40f 100644 --- a/arch/z80/src/ez80/ez80_io.asm +++ b/arch/z80/src/ez80/ez80_io.asm @@ -2,7 +2,7 @@ ; arch/z80/src/ze80/ez80_io.c ; ; Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. -; Author: Gregory Nutt +; Author: Gregory Nutt ; ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/ez80_irq.c b/arch/z80/src/ez80/ez80_irq.c index d89bff859802d96385ee1922fcdaafb0034a7083..604e5c5b3f9d5ae83ee2e7c7f37c481cf781aac5 100644 --- a/arch/z80/src/ez80/ez80_irq.c +++ b/arch/z80/src/ez80/ez80_irq.c @@ -2,7 +2,7 @@ * arch/z80/src/ez80/ez80_irq.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/ez80_irqsave.asm b/arch/z80/src/ez80/ez80_irqsave.asm index c19ef0bdd9b5376d9089eeb05105677ab73eb67e..0efae6a4786ad2d64835d2aa9ab06f859ee60c26 100644 --- a/arch/z80/src/ez80/ez80_irqsave.asm +++ b/arch/z80/src/ez80/ez80_irqsave.asm @@ -1,88 +1,88 @@ -;************************************************************************** -; arch/z80/src/ez80/ez80_irqsave.asm -; -; Copyright (C) 2008 Gregory Nutt. All rights reserved. -; Author: Gregory Nutt -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions -; are met: -; -; 1. Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in -; the documentation and/or other materials provided with the -; distribution. -; 3. Neither the name NuttX nor the names of its contributors may be -; used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; -;************************************************************************** - -;************************************************************************** -; Global Symbols Imported -;************************************************************************** - -;************************************************************************** -; Global Symbols Expported -;************************************************************************** - - xdef _irqsave - xdef _irqrestore - -;************************************************************************** -; Code -;************************************************************************** - - segment CODE - .assume ADL=1 - -;************************************************************************** -;* Name: irqstate_t irqsave(void) -;* -;* Description: -;* Disable all interrupts; return previous interrupt state -;* -;************************************************************************** - -_irqsave: - ld a, i ; AF = interrupt state - di ; Interrupts are disabled (does not affect F) - push af ; Transfer to HL via the stack - pop hl ; - ret ; And return - -;************************************************************************** -;* Name: void irqrestore(irqstate_t flags) -;* -;* Description: -;* Restore previous interrupt state -;* -;************************************************************************** - -_irqrestore: - di ; Assume disabled - pop hl ; HL = return address - pop af ; AF Parity bit holds interrupt state - jp po, _disabled ; Skip over re-enable if Parity odd - ei ; Re-enable interrupts -_disabled: - push af ; Restore stack - push hl ; - ret ; and return - - end +;************************************************************************** +; arch/z80/src/ez80/ez80_irqsave.asm +; +; Copyright (C) 2008 Gregory Nutt. All rights reserved. +; Author: Gregory Nutt +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in +; the documentation and/or other materials provided with the +; distribution. +; 3. Neither the name NuttX nor the names of its contributors may be +; used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; +;************************************************************************** + +;************************************************************************** +; Global Symbols Imported +;************************************************************************** + +;************************************************************************** +; Global Symbols Expported +;************************************************************************** + + xdef _irqsave + xdef _irqrestore + +;************************************************************************** +; Code +;************************************************************************** + + segment CODE + .assume ADL=1 + +;************************************************************************** +;* Name: irqstate_t irqsave(void) +;* +;* Description: +;* Disable all interrupts; return previous interrupt state +;* +;************************************************************************** + +_irqsave: + ld a, i ; AF = interrupt state + di ; Interrupts are disabled (does not affect F) + push af ; Transfer to HL via the stack + pop hl ; + ret ; And return + +;************************************************************************** +;* Name: void irqrestore(irqstate_t flags) +;* +;* Description: +;* Restore previous interrupt state +;* +;************************************************************************** + +_irqrestore: + di ; Assume disabled + pop hl ; HL = return address + pop af ; AF Parity bit holds interrupt state + jp po, _disabled ; Skip over re-enable if Parity odd + ei ; Re-enable interrupts +_disabled: + push af ; Restore stack + push hl ; + ret ; and return + + end diff --git a/arch/z80/src/ez80/ez80_registerdump.c b/arch/z80/src/ez80/ez80_registerdump.c index d1aa3726bb1974d6d191b3e068bf7de4645264e3..a43bd6459bd8267c6ac0d4a857371083d6629a7c 100644 --- a/arch/z80/src/ez80/ez80_registerdump.c +++ b/arch/z80/src/ez80/ez80_registerdump.c @@ -2,7 +2,7 @@ * arch/z80/src/ez80/ez80_registerdump.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/ez80_restorecontext.asm b/arch/z80/src/ez80/ez80_restorecontext.asm index da1d050f0c9546c877078a93718e86151403bd65..c90ce808fae243db973840507ff882683c7a8c68 100644 --- a/arch/z80/src/ez80/ez80_restorecontext.asm +++ b/arch/z80/src/ez80/ez80_restorecontext.asm @@ -1,110 +1,110 @@ -;************************************************************************** -; arch/z80/src/ez80/ez80_restorcontext.asm -; -; Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. -; Author: Gregory Nutt -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions -; are met: -; -; 1. Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in -; the documentation and/or other materials provided with the -; distribution. -; 3. Neither the name NuttX nor the names of its contributors may be -; used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; -;************************************************************************** - -;************************************************************************** -; Global Symbols Imported -;************************************************************************** - -;************************************************************************** -; Global Symbols Expported -;************************************************************************** - - xdef _ez80_restorecontext - -;************************************************************************** -; Code -;************************************************************************** - - segment CODE - .assume ADL=1 - -;************************************************************************** -; ez80_restorecontext -;************************************************************************** - -_ez80_restorecontext: - ; On entry, stack contains return address (not used), then address - ; of the register save structure - - ; Discard the return address, we won't be returning - - pop hl - - ; Get the address of the beginning of the state save area. Each - ; pop will increment to the next element of the structure - - pop hl ; BC = Address of save structure - ld sp, hl ; SP points to top of storage area - - ; Disable interrupts while we muck with the alternative registers. The - ; Correct interrupt state will be restore below - - di - - ; Restore registers. HL points to the beginning of the reg structure to restore - - ex af, af' ; Select alternate AF - pop af ; Offset 0: AF' = I with interrupt state in parity - ex af, af' ; Restore original AF - pop bc ; Offset 1: BC - pop de ; Offset 2: DE - pop ix ; Offset 3: IX - pop iy ; Offset 4: IY - exx ; Use alternate BC/DE/HL - pop hl ; Offset 5: HL' = Stack pointer after return - exx ; Restore original BC/DE/HL - pop hl ; Offset 6: HL - pop af ; Offset 7: AF - - ; Restore the stack pointer - - exx ; Use alternate BC/DE/HL - pop de ; DE' = return address - ld sp, hl ; Set SP = saved stack pointer value before return - push de ; Save return address for ret instruction - exx ; Restore original BC/DE/HL - - ; Restore interrupt state - - ex af, af' ; Recover interrupt state - jp po, noinrestore ; Odd parity, IFF2=0, means disabled - ex af, af' ; Restore AF (before enabling interrupts) - ei ; yes.. Enable interrupts - ret ; and return -noinrestore: - ex af, af' ; Restore AF - ret ; Return with interrupts disabled - end - +;************************************************************************** +; arch/z80/src/ez80/ez80_restorcontext.asm +; +; Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. +; Author: Gregory Nutt +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in +; the documentation and/or other materials provided with the +; distribution. +; 3. Neither the name NuttX nor the names of its contributors may be +; used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; +;************************************************************************** + +;************************************************************************** +; Global Symbols Imported +;************************************************************************** + +;************************************************************************** +; Global Symbols Expported +;************************************************************************** + + xdef _ez80_restorecontext + +;************************************************************************** +; Code +;************************************************************************** + + segment CODE + .assume ADL=1 + +;************************************************************************** +; ez80_restorecontext +;************************************************************************** + +_ez80_restorecontext: + ; On entry, stack contains return address (not used), then address + ; of the register save structure + + ; Discard the return address, we won't be returning + + pop hl + + ; Get the address of the beginning of the state save area. Each + ; pop will increment to the next element of the structure + + pop hl ; BC = Address of save structure + ld sp, hl ; SP points to top of storage area + + ; Disable interrupts while we muck with the alternative registers. The + ; Correct interrupt state will be restore below + + di + + ; Restore registers. HL points to the beginning of the reg structure to restore + + ex af, af' ; Select alternate AF + pop af ; Offset 0: AF' = I with interrupt state in parity + ex af, af' ; Restore original AF + pop bc ; Offset 1: BC + pop de ; Offset 2: DE + pop ix ; Offset 3: IX + pop iy ; Offset 4: IY + exx ; Use alternate BC/DE/HL + pop hl ; Offset 5: HL' = Stack pointer after return + exx ; Restore original BC/DE/HL + pop hl ; Offset 6: HL + pop af ; Offset 7: AF + + ; Restore the stack pointer + + exx ; Use alternate BC/DE/HL + pop de ; DE' = return address + ld sp, hl ; Set SP = saved stack pointer value before return + push de ; Save return address for ret instruction + exx ; Restore original BC/DE/HL + + ; Restore interrupt state + + ex af, af' ; Recover interrupt state + jp po, noinrestore ; Odd parity, IFF2=0, means disabled + ex af, af' ; Restore AF (before enabling interrupts) + ei ; yes.. Enable interrupts + ret ; and return +noinrestore: + ex af, af' ; Restore AF + ret ; Return with interrupts disabled + end + diff --git a/arch/z80/src/ez80/ez80_saveusercontext.asm b/arch/z80/src/ez80/ez80_saveusercontext.asm index ecd7db1143fa4f24f2ed697cfd1bca2bfac11033..429dc3dd57a686b328853dd5e4b92af85521ebd8 100644 --- a/arch/z80/src/ez80/ez80_saveusercontext.asm +++ b/arch/z80/src/ez80/ez80_saveusercontext.asm @@ -2,7 +2,7 @@ ; arch/z80/src/ez80/ez80_saveusercontext.asm ; ; Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. -; Author: Gregory Nutt +; Author: Gregory Nutt ; ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/ez80_schedulesigaction.c b/arch/z80/src/ez80/ez80_schedulesigaction.c index ce48fe98718141cecdb4cbab83a64f8640d67a45..04643304d8d7968ea92b16ad92dbeff581b75ec8 100644 --- a/arch/z80/src/ez80/ez80_schedulesigaction.c +++ b/arch/z80/src/ez80/ez80_schedulesigaction.c @@ -2,7 +2,7 @@ * arch/z80/src/ez80/ez80_schedulesigaction.c * * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/ez80_sigdeliver.c b/arch/z80/src/ez80/ez80_sigdeliver.c index 86aaad2d5016453aa35af540cc2d1674b9b50b98..2d946aa32257e43fe6d761fcbdc4f48e445b2bbf 100644 --- a/arch/z80/src/ez80/ez80_sigdeliver.c +++ b/arch/z80/src/ez80/ez80_sigdeliver.c @@ -2,7 +2,7 @@ * arch/z80/src/ez80/ez80_sigdeliver.c * * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/ez80_spi.c b/arch/z80/src/ez80/ez80_spi.c index 0c238f663e33eeb6ab06602fa8981297f247e4d8..14f8e05f3b50624750c5638f2e70e21851f07ad3 100755 --- a/arch/z80/src/ez80/ez80_spi.c +++ b/arch/z80/src/ez80/ez80_spi.c @@ -2,7 +2,7 @@ * arch/z80/src/ez80/ez80_spi.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/ez80_startup.asm b/arch/z80/src/ez80/ez80_startup.asm index 2173f80a42d238cae6f626e7eed3d6d5dbf047b6..d52795d6373fd758fad141cc247d711f88e3b7b3 100644 --- a/arch/z80/src/ez80/ez80_startup.asm +++ b/arch/z80/src/ez80/ez80_startup.asm @@ -1,155 +1,155 @@ -;************************************************************************** -; arch/z80/src/ez80/ez80_startup.asm -; -; Copyright (C) 2008 Gregory Nutt. All rights reserved. -; Author: Gregory Nutt -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions -; are met: -; -; 1. Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in -; the documentation and/or other materials provided with the -; distribution. -; 3. Neither the name NuttX nor the names of its contributors may be -; used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; -;************************************************************************** - -;************************************************************************** -; Included Files -;************************************************************************** - -;************************************************************************** -; Constants -;************************************************************************** - -;************************************************************************** -; Global symbols used -;************************************************************************** - - xref __stack - xref _ez80_init - xref _ez80_initvectors - xref _ez80_initsysclk - xref _ez80_lowinit - xref __low_bss ; Low address of bss segment - xref __len_bss ; Length of bss segment - - xref __low_data ; Address of initialized data section - xref __low_romdata ; Addr of initialized data section in ROM - xref __len_data ; Length of initialized data section - - xref __copy_code_to_ram - xref __len_code - xref __low_code - xref __low_romcode - xref _os_start - xdef _ez80_startup - xdef _ez80_halt - -;************************************************************************** -; Code -;************************************************************************** - - segment CODE - .assume ADL=1 - -;************************************************************************** -; System reset start logic -;************************************************************************** - -_ez80_startup: - ; Set up the stack pointer at the location determined the lincmd - ; file - - ld sp, __stack - - ; Peform chip-specific initialization - - call _ez80_init - - ; initialize the interrupt vector table - - call _ez80_initvectors - - ; Initialize the system clock - - call _ez80_initsysclk - - ; Perform C initializations - ; Clear the uninitialized data section - - ld bc, __len_bss ; Check for non-zero length - ld a, __len_bss >> 16 - or a, c - or a, b - jr z, _ez80_bssdone ; BSS is zero-length ... - xor a, a - ld (__low_bss), a - sbc hl, hl ; hl = 0 - dec bc ; 1st byte's taken care of - sbc hl, bc - jr z, _ez80_bssdone ; Just 1 byte ... - ld hl, __low_bss ; reset hl - ld de, __low_bss + 1 ; [de] = bss + 1 - ldir -_ez80_bssdone: - - ; Copy the initialized data section - ld bc, __len_data ; [bc] = data length - ld a, __len_data >> 16 ; Check for non-zero length - or a, c - or a, b - jr z, _ez80_datadone ; __len_data is zero-length ... - ld hl, __low_romdata ; [hl] = data_copy - ld de, __low_data ; [de] = data - ldir ; Copy the data section -_ez80_datadone: - - ; Copy CODE (which may be in FLASH) to RAM if the - ; copy_code_to_ram symbol is set in the link control file - ld a, __copy_code_to_ram - or a, a - jr z, _ez80_codedone - ld bc, __len_code ; [bc] = code length - ld a, __len_code >> 16 ; Check for non-zero length - or a, c - or a, b - jr z, _ez80_codedone ; __len_code is zero-length - ld hl, __low_romcode ; [hl] = code_copy - ld de, __low_code ; [de] = code - ldir ; Copy the code section -_ez80_codedone: - - ; Perform board-specific intialization - - call _ez80_lowinit - - ; Then start NuttX - - call _os_start ; jump to the OS entry point - - ; NuttX will never return, but just in case... - -_ez80_halt: - halt ; We should never get here - jp _ez80_halt - +;************************************************************************** +; arch/z80/src/ez80/ez80_startup.asm +; +; Copyright (C) 2008 Gregory Nutt. All rights reserved. +; Author: Gregory Nutt +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in +; the documentation and/or other materials provided with the +; distribution. +; 3. Neither the name NuttX nor the names of its contributors may be +; used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; +;************************************************************************** + +;************************************************************************** +; Included Files +;************************************************************************** + +;************************************************************************** +; Constants +;************************************************************************** + +;************************************************************************** +; Global symbols used +;************************************************************************** + + xref __stack + xref _ez80_init + xref _ez80_initvectors + xref _ez80_initsysclk + xref _ez80_lowinit + xref __low_bss ; Low address of bss segment + xref __len_bss ; Length of bss segment + + xref __low_data ; Address of initialized data section + xref __low_romdata ; Addr of initialized data section in ROM + xref __len_data ; Length of initialized data section + + xref __copy_code_to_ram + xref __len_code + xref __low_code + xref __low_romcode + xref _os_start + xdef _ez80_startup + xdef _ez80_halt + +;************************************************************************** +; Code +;************************************************************************** + + segment CODE + .assume ADL=1 + +;************************************************************************** +; System reset start logic +;************************************************************************** + +_ez80_startup: + ; Set up the stack pointer at the location determined the lincmd + ; file + + ld sp, __stack + + ; Peform chip-specific initialization + + call _ez80_init + + ; initialize the interrupt vector table + + call _ez80_initvectors + + ; Initialize the system clock + + call _ez80_initsysclk + + ; Perform C initializations + ; Clear the uninitialized data section + + ld bc, __len_bss ; Check for non-zero length + ld a, __len_bss >> 16 + or a, c + or a, b + jr z, _ez80_bssdone ; BSS is zero-length ... + xor a, a + ld (__low_bss), a + sbc hl, hl ; hl = 0 + dec bc ; 1st byte's taken care of + sbc hl, bc + jr z, _ez80_bssdone ; Just 1 byte ... + ld hl, __low_bss ; reset hl + ld de, __low_bss + 1 ; [de] = bss + 1 + ldir +_ez80_bssdone: + + ; Copy the initialized data section + ld bc, __len_data ; [bc] = data length + ld a, __len_data >> 16 ; Check for non-zero length + or a, c + or a, b + jr z, _ez80_datadone ; __len_data is zero-length ... + ld hl, __low_romdata ; [hl] = data_copy + ld de, __low_data ; [de] = data + ldir ; Copy the data section +_ez80_datadone: + + ; Copy CODE (which may be in FLASH) to RAM if the + ; copy_code_to_ram symbol is set in the link control file + ld a, __copy_code_to_ram + or a, a + jr z, _ez80_codedone + ld bc, __len_code ; [bc] = code length + ld a, __len_code >> 16 ; Check for non-zero length + or a, c + or a, b + jr z, _ez80_codedone ; __len_code is zero-length + ld hl, __low_romcode ; [hl] = code_copy + ld de, __low_code ; [de] = code + ldir ; Copy the code section +_ez80_codedone: + + ; Perform board-specific intialization + + call _ez80_lowinit + + ; Then start NuttX + + call _os_start ; jump to the OS entry point + + ; NuttX will never return, but just in case... + +_ez80_halt: + halt ; We should never get here + jp _ez80_halt + diff --git a/arch/z80/src/ez80/ez80_timerisr.c b/arch/z80/src/ez80/ez80_timerisr.c index a251b57e7d4cccb404aabc4c678a1598c52fda3f..d29237e54cee9f64396259c323198a1408b88ca3 100644 --- a/arch/z80/src/ez80/ez80_timerisr.c +++ b/arch/z80/src/ez80/ez80_timerisr.c @@ -2,7 +2,7 @@ * arch/z80/src/ez80/ez80_timerisr.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/ez80_vectors.asm b/arch/z80/src/ez80/ez80_vectors.asm index 3e3d44ced678a6618f6592ebc2fb6947e0aa9fa1..eaec4b36fd31666bbd4b16a029405706cfe693a7 100644 --- a/arch/z80/src/ez80/ez80_vectors.asm +++ b/arch/z80/src/ez80/ez80_vectors.asm @@ -1,340 +1,340 @@ -;************************************************************************** -; arch/z80/src/ez80/ez80_vectors.asm -; -; Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. -; Author: Gregory Nutt -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions -; are met: -; -; 1. Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in -; the documentation and/or other materials provided with the -; distribution. -; 3. Neither the name NuttX nor the names of its contributors may be -; used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; -;************************************************************************** - -;************************************************************************** -; Constants -;************************************************************************** - -NVECTORS EQU 64 ; max possible interrupt vectors - -;* Bits in the Z80 FLAGS register ***************************************** - -EZ80_C_FLAG EQU 01h ; Bit 0: Carry flag -EZ80_N_FLAG EQU 02h ; Bit 1: Add/Subtract flag -EZ80_PV_FLAG EQU 04h ; Bit 2: Parity/Overflow flag -EZ80_H_FLAG EQU 10h ; Bit 4: Half carry flag -EZ80_Z_FLAG EQU 40h ; Bit 5: Zero flag -EZ80_S_FLAG EQU 80h ; Bit 7: Sign flag - -;* The IRQ number to use for unused vectors - -EZ80_UNUSED EQU 40h - -;************************************************************************** -; Global Symbols Imported -;************************************************************************** - - xref _ez80_startup - xref _up_doirq - -;************************************************************************** -; Global Symbols Exported -;************************************************************************** - - xdef _ez80_reset - xdef _ez80_initvectors - xdef _ez80_handlers - xdef _ez80_rstcommon - xdef _ez80_initvectors - xdef _ez80_vectable - -;************************************************************************** -; Macros -;************************************************************************** - -; Define one reset handler -; 1. Disable interrupts -; 2. Dlear mixed memory mode (MADL) flag -; 3. jump to initialization procedure with jp.lil to set ADL -rstvector: macro - di - rsmix - jp.lil _ez80_startup - endmac rstvector - -; Define one interrupt handler -irqhandler: macro vectno - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #vectno ; A = vector number - jp _ez80_rstcommon ; Remaining RST handling is common - endmac irqhandler - -;************************************************************************** -; Reset entry points -;************************************************************************** - - define .RESET, space = ROM - segment .RESET - -_ez80_reset: -_rst0: - rstvector -_rst8: - rstvector -_rst10: - rstvector -_rst18: - rstvector -_rst20: - rstvector -_rst28: - rstvector -_rst30: - rstvector -_rst38: - rstvector - ds %26 -_nmi: - retn - -;************************************************************************** -; Startup logic -;************************************************************************** - - define .STARTUP, space = ROM - segment .STARTUP - .assume ADL=1 - -;************************************************************************** -; Interrupt Vector Handling -;************************************************************************** - - ; Symbol Val VecNo Addr - ;----------------- --- ----- ----- -_ez80_handlers: - irqhandler 0 ; EZ80_EMACRX_IRQ 0 0 0x040 - handlersize equ $-_ez80handlers - irqhandler 1 ; EZ80_EMACTX_IRQ 1 1 0x044 - irqhandler 2 ; EZ80_EMACSYS_IRQ 2 2 0x048 - irqhandler 3 ; EZ80_PLL_IRQ 3 3 0x04c - irqhandler 4 ; EZ80_FLASH_IRQ 4 4 0x050 - irqhandler 5 ; EZ80_TIMER0_IRQ 5 5 0x054 - irqhandler 6 ; EZ80_TIMER1_IRQ 6 6 0x058 - irqhandler 7 ; EZ80_TIMER2_IRQ 7 7 0x05c - irqhandler 8 ; EZ80_TIMER3_IRQ 8 8 0x060 - irqhandler EZ80_UNUSED ; 9 0x064 - irqhandler EZ80_UNUSED+1 ; 10 0x068 - irqhandler 9 ; EZ80_RTC_IRQ 9 11 0x06C - irqhandler 10 ; EZ80_UART0_IRQ 10 12 0x070 - irqhandler 11 ; EZ80_UART1_IRQ 11 13 0x074 - irqhandler 12 ; EZ80_I2C_IRQ 12 14 0x078 - irqhandler 13 ; EZ80_SPI_IRQ 13 15 0x07c - irqhandler 14 ; EZ80_PORTA0_IRQ 14 16 0x080 - irqhandler 15 ; EZ80_PORTA1_IRQ 15 17 0x084 - irqhandler 16 ; EZ80_PORTA2_IRQ 16 18 0x088 - irqhandler 17 ; EZ80_PORTA3_IRQ 17 19 0x08c - irqhandler 18 ; EZ80_PORTA4_IRQ 18 20 0x090 - irqhandler 19 ; EZ80_PORTA5_IRQ 19 21 0x094 - irqhandler 20 ; EZ80_PORTA6_IRQ 20 22 0x098 - irqhandler 21 ; EZ80_PORTA7_IRQ 21 23 0x09c - irqhandler 22 ; EZ80_PORTB0_IRQ 22 24 0x0a0 - irqhandler 23 ; EZ80_PORTB1_IRQ 23 25 0x0a4 - irqhandler 24 ; EZ80_PORTB2_IRQ 24 26 0x0a8 - irqhandler 25 ; EZ80_PORTB3_IRQ 25 27 0x0ac - irqhandler 26 ; EZ80_PORTB4_IRQ 26 28 0x0b0 - irqhandler 27 ; EZ80_PORTB5_IRQ 27 29 0x0b4 - irqhandler 28 ; EZ80_PORTB6_IRQ 28 20 0x0b8 - irqhandler 29 ; EZ80_PORTB7_IRQ 29 21 0x0bc - irqhandler 30 ; EZ80_PORTC0_IRQ 30 22 0x0c0 - irqhandler 31 ; EZ80_PORTC1_IRQ 31 23 0x0c4 - irqhandler 32 ; EZ80_PORTC2_IRQ 32 24 0x0c8 - irqhandler 33 ; EZ80_PORTC3_IRQ 33 25 0x0cc - irqhandler 34 ; EZ80_PORTC4_IRQ 34 26 0x0d0 - irqhandler 35 ; EZ80_PORTC5_IRQ 35 27 0x0d4 - irqhandler 36 ; EZ80_PORTC6_IRQ 36 28 0x0d8 - irqhandler 37 ; EZ80_PORTC7_IRQ 37 29 0x0dc - irqhandler 38 ; EZ80_PORTD0_IRQ 38 40 0x0e0 - irqhandler 39 ; EZ80_PORTD1_IRQ 39 41 0x0e4 - irqhandler 40 ; EZ80_PORTD2_IRQ 40 42 0x0e8 - irqhandler 41 ; EZ80_PORTD3_IRQ 41 43 0x0ec - irqhandler 42 ; EZ80_PORTD4_IRQ 42 44 0x0f0 - irqhandler 43 ; EZ80_PORTD5_IRQ 43 45 0x0f4 - irqhandler 44 ; EZ80_PORTD6_IRQ 44 46 0x0f8 - irqhandler 45 ; EZ80_PORTD7_IRQ 45 47 0x0fc - irqhandler EZ80_UNUSED+1 ; 48 0x100 - irqhandler EZ80_UNUSED+2 ; 49 0x104 - irqhandler EZ80_UNUSED+3 ; 50 0x108 - irqhandler EZ80_UNUSED+4 ; 51 0x10c - irqhandler EZ80_UNUSED+5 ; 52 0x110 - irqhandler EZ80_UNUSED+6 ; 53 0x114 - irqhandler EZ80_UNUSED+7 ; 54 0x118 - irqhandler EZ80_UNUSED+8 ; 55 0x11c - irqhandler EZ80_UNUSED+9 ; 56 0x120 - irqhandler EZ80_UNUSED+10 ; 57 0x124 - irqhandler EZ80_UNUSED+11 ; 58 0x128 - irqhandler EZ80_UNUSED+12 ; 59 0x12c - irqhandler EZ80_UNUSED+13 ; 60 0x130 - irqhandler EZ80_UNUSED+14 ; 61 0x134 - irqhandler EZ80_UNUSED+15 ; 62 0x138 - irqhandler EZ80_UNUSED+16 ; 63 0x13c - -;************************************************************************** -; Common Interrupt handler -;************************************************************************** - -_ez80_rstcommon: - ; Create a register frame. SP points to top of frame + 4, pushes - ; decrement the stack pointer. Already have - ; - ; Offset 8: Return PC is already on the stack - ; Offset 7: AF (retaining flags) - ; - ; IRQ number is in A - - push hl ; Offset 6: HL - ld hl, #(3*3) ; HL is the value of the stack pointer before - add hl, sp ; the interrupt occurred (3 for PC, AF, HL) - push hl ; Offset 5: Stack pointer - push iy ; Offset 4: IY - push ix ; Offset 3: IX - push de ; Offset 2: DE - push bc ; Offset 1: BC - - ; At this point, we know that interrupts were enabled (or we wouldn't be here - ; so we can save a fake indicationn that will cause interrupts to restored when - ; this context is restored - - ld bc, #EZ80_PV_FLAG ; Parity bit. 1=parity odd, IEF2=1 - push bc ; Offset 0: I with interrupt state in parity - di ; (not necessary) - - ; Call the interrupt decode logic. SP points to the beggining of the reg structure - - ld hl, #0 ; Argument #2 is the beginning of the reg structure - add hl, sp ; - push hl ; Place argument #2 at the top of stack - ld bc, #0 ; BC = reset number - ld c, a ; Save the reset number in C - push bc ; Argument #1 is the Reset number - call _up_doirq ; Decode the IRQ - - ; On return, HL points to the beginning of the reg structure to restore - ; Note that (1) the arguments pushed on the stack are not popped, and (2) the - ; original stack pointer is lost. In the normal case (no context switch), - ; HL will contain the value of the SP before the arguments were pushed. - - ld sp, hl ; Use the new stack pointer - - ; Restore registers. HL points to the beginning of the reg structure to restore - - ex af, af' ; Select alternate AF - pop af ; Offset 0: AF' = I with interrupt state in parity - ex af, af' ; Restore original AF - pop bc ; Offset 1: BC - pop de ; Offset 2: DE - pop ix ; Offset 3: IX - pop iy ; Offset 4: IY - exx ; Use alternate BC/DE/HL - pop hl ; Offset 5: HL' = Stack pointer after return - exx ; Restore original BC/DE/HL - pop hl ; Offset 6: HL - pop af ; Offset 7: AF - - ; Restore the stack pointer - - exx ; Use alternate BC/DE/HL - pop de ; Offset 8: Return address - ld sp, hl ; Set SP = saved stack pointer value before return - push de ; Set up for reti - exx ; Restore original BC/DE/HL - - ; Restore interrupt state - - ex af, af' ; Recover interrupt state - jp po, nointenable ; Odd parity, IFF2=0, means disabled - ex af, af' ; Restore AF (before enabling interrupts) - ei ; yes - reti -nointenable: - ex af, af' ; Restore AF - reti - -;************************************************************************** -; Vector Setup Logic -;************************************************************************** - -_ez80_initvectors: - ; Initialize the vector table - - ld iy, _ez80_vectable - ld ix, 4 - ld bc, 4 - ld b, NVECTORS - xor a, a ; Clear carry - ld hl, handlersize - ld de, _ez80_handlers - sbc hl, de ; Length of irq handler in hl - ld d, h - ld e, l - ld hl, _ez80_handlers ; Start of handlers in hl - - ld a, 0 -$1: - ld (iy), hl ; Store IRQ handler - ld (iy+3), a ; Pad to 4 bytes - add hl, de ; Point to next handler - push de - ld de, 4 - add iy, de ; Point to next entry in vector table - pop de - djnz $1 ; Loop until all vectors have been written - - ; Select interrupt mode 2 - - im 2 ; Interrupt mode 2 - - ; Write the address of the vector table into the interrupt vector base - - ld hl, _ez80_vectable >> 8 - ld i, hl - ret - -;************************************************************************** -; Vector Table -;************************************************************************** -; This segment must be aligned on a 512 byte boundary anywhere in RAM -; Each entry will be a 3-byte address in a 4-byte space - - define .IVECTS, space = RAM, align = 200h - segment .IVECTS - - ; The first 64 bytes are not used... the vectors actually start at +0x40 -_ez80_vecreserve: - ds 64 -_ez80_vectable: - ds NVECTORS * 4 +;************************************************************************** +; arch/z80/src/ez80/ez80_vectors.asm +; +; Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. +; Author: Gregory Nutt +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in +; the documentation and/or other materials provided with the +; distribution. +; 3. Neither the name NuttX nor the names of its contributors may be +; used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; +;************************************************************************** + +;************************************************************************** +; Constants +;************************************************************************** + +NVECTORS EQU 64 ; max possible interrupt vectors + +;* Bits in the Z80 FLAGS register ***************************************** + +EZ80_C_FLAG EQU 01h ; Bit 0: Carry flag +EZ80_N_FLAG EQU 02h ; Bit 1: Add/Subtract flag +EZ80_PV_FLAG EQU 04h ; Bit 2: Parity/Overflow flag +EZ80_H_FLAG EQU 10h ; Bit 4: Half carry flag +EZ80_Z_FLAG EQU 40h ; Bit 5: Zero flag +EZ80_S_FLAG EQU 80h ; Bit 7: Sign flag + +;* The IRQ number to use for unused vectors + +EZ80_UNUSED EQU 40h + +;************************************************************************** +; Global Symbols Imported +;************************************************************************** + + xref _ez80_startup + xref _up_doirq + +;************************************************************************** +; Global Symbols Exported +;************************************************************************** + + xdef _ez80_reset + xdef _ez80_initvectors + xdef _ez80_handlers + xdef _ez80_rstcommon + xdef _ez80_initvectors + xdef _ez80_vectable + +;************************************************************************** +; Macros +;************************************************************************** + +; Define one reset handler +; 1. Disable interrupts +; 2. Dlear mixed memory mode (MADL) flag +; 3. jump to initialization procedure with jp.lil to set ADL +rstvector: macro + di + rsmix + jp.lil _ez80_startup + endmac rstvector + +; Define one interrupt handler +irqhandler: macro vectno + ; Save AF on the stack, set the interrupt number and jump to the + ; common reset handling logic. + ; Offset 8: Return PC is already on the stack + push af ; Offset 7: AF (retaining flags) + ld a, #vectno ; A = vector number + jp _ez80_rstcommon ; Remaining RST handling is common + endmac irqhandler + +;************************************************************************** +; Reset entry points +;************************************************************************** + + define .RESET, space = ROM + segment .RESET + +_ez80_reset: +_rst0: + rstvector +_rst8: + rstvector +_rst10: + rstvector +_rst18: + rstvector +_rst20: + rstvector +_rst28: + rstvector +_rst30: + rstvector +_rst38: + rstvector + ds %26 +_nmi: + retn + +;************************************************************************** +; Startup logic +;************************************************************************** + + define .STARTUP, space = ROM + segment .STARTUP + .assume ADL=1 + +;************************************************************************** +; Interrupt Vector Handling +;************************************************************************** + + ; Symbol Val VecNo Addr + ;----------------- --- ----- ----- +_ez80_handlers: + irqhandler 0 ; EZ80_EMACRX_IRQ 0 0 0x040 + handlersize equ $-_ez80handlers + irqhandler 1 ; EZ80_EMACTX_IRQ 1 1 0x044 + irqhandler 2 ; EZ80_EMACSYS_IRQ 2 2 0x048 + irqhandler 3 ; EZ80_PLL_IRQ 3 3 0x04c + irqhandler 4 ; EZ80_FLASH_IRQ 4 4 0x050 + irqhandler 5 ; EZ80_TIMER0_IRQ 5 5 0x054 + irqhandler 6 ; EZ80_TIMER1_IRQ 6 6 0x058 + irqhandler 7 ; EZ80_TIMER2_IRQ 7 7 0x05c + irqhandler 8 ; EZ80_TIMER3_IRQ 8 8 0x060 + irqhandler EZ80_UNUSED ; 9 0x064 + irqhandler EZ80_UNUSED+1 ; 10 0x068 + irqhandler 9 ; EZ80_RTC_IRQ 9 11 0x06C + irqhandler 10 ; EZ80_UART0_IRQ 10 12 0x070 + irqhandler 11 ; EZ80_UART1_IRQ 11 13 0x074 + irqhandler 12 ; EZ80_I2C_IRQ 12 14 0x078 + irqhandler 13 ; EZ80_SPI_IRQ 13 15 0x07c + irqhandler 14 ; EZ80_PORTA0_IRQ 14 16 0x080 + irqhandler 15 ; EZ80_PORTA1_IRQ 15 17 0x084 + irqhandler 16 ; EZ80_PORTA2_IRQ 16 18 0x088 + irqhandler 17 ; EZ80_PORTA3_IRQ 17 19 0x08c + irqhandler 18 ; EZ80_PORTA4_IRQ 18 20 0x090 + irqhandler 19 ; EZ80_PORTA5_IRQ 19 21 0x094 + irqhandler 20 ; EZ80_PORTA6_IRQ 20 22 0x098 + irqhandler 21 ; EZ80_PORTA7_IRQ 21 23 0x09c + irqhandler 22 ; EZ80_PORTB0_IRQ 22 24 0x0a0 + irqhandler 23 ; EZ80_PORTB1_IRQ 23 25 0x0a4 + irqhandler 24 ; EZ80_PORTB2_IRQ 24 26 0x0a8 + irqhandler 25 ; EZ80_PORTB3_IRQ 25 27 0x0ac + irqhandler 26 ; EZ80_PORTB4_IRQ 26 28 0x0b0 + irqhandler 27 ; EZ80_PORTB5_IRQ 27 29 0x0b4 + irqhandler 28 ; EZ80_PORTB6_IRQ 28 20 0x0b8 + irqhandler 29 ; EZ80_PORTB7_IRQ 29 21 0x0bc + irqhandler 30 ; EZ80_PORTC0_IRQ 30 22 0x0c0 + irqhandler 31 ; EZ80_PORTC1_IRQ 31 23 0x0c4 + irqhandler 32 ; EZ80_PORTC2_IRQ 32 24 0x0c8 + irqhandler 33 ; EZ80_PORTC3_IRQ 33 25 0x0cc + irqhandler 34 ; EZ80_PORTC4_IRQ 34 26 0x0d0 + irqhandler 35 ; EZ80_PORTC5_IRQ 35 27 0x0d4 + irqhandler 36 ; EZ80_PORTC6_IRQ 36 28 0x0d8 + irqhandler 37 ; EZ80_PORTC7_IRQ 37 29 0x0dc + irqhandler 38 ; EZ80_PORTD0_IRQ 38 40 0x0e0 + irqhandler 39 ; EZ80_PORTD1_IRQ 39 41 0x0e4 + irqhandler 40 ; EZ80_PORTD2_IRQ 40 42 0x0e8 + irqhandler 41 ; EZ80_PORTD3_IRQ 41 43 0x0ec + irqhandler 42 ; EZ80_PORTD4_IRQ 42 44 0x0f0 + irqhandler 43 ; EZ80_PORTD5_IRQ 43 45 0x0f4 + irqhandler 44 ; EZ80_PORTD6_IRQ 44 46 0x0f8 + irqhandler 45 ; EZ80_PORTD7_IRQ 45 47 0x0fc + irqhandler EZ80_UNUSED+1 ; 48 0x100 + irqhandler EZ80_UNUSED+2 ; 49 0x104 + irqhandler EZ80_UNUSED+3 ; 50 0x108 + irqhandler EZ80_UNUSED+4 ; 51 0x10c + irqhandler EZ80_UNUSED+5 ; 52 0x110 + irqhandler EZ80_UNUSED+6 ; 53 0x114 + irqhandler EZ80_UNUSED+7 ; 54 0x118 + irqhandler EZ80_UNUSED+8 ; 55 0x11c + irqhandler EZ80_UNUSED+9 ; 56 0x120 + irqhandler EZ80_UNUSED+10 ; 57 0x124 + irqhandler EZ80_UNUSED+11 ; 58 0x128 + irqhandler EZ80_UNUSED+12 ; 59 0x12c + irqhandler EZ80_UNUSED+13 ; 60 0x130 + irqhandler EZ80_UNUSED+14 ; 61 0x134 + irqhandler EZ80_UNUSED+15 ; 62 0x138 + irqhandler EZ80_UNUSED+16 ; 63 0x13c + +;************************************************************************** +; Common Interrupt handler +;************************************************************************** + +_ez80_rstcommon: + ; Create a register frame. SP points to top of frame + 4, pushes + ; decrement the stack pointer. Already have + ; + ; Offset 8: Return PC is already on the stack + ; Offset 7: AF (retaining flags) + ; + ; IRQ number is in A + + push hl ; Offset 6: HL + ld hl, #(3*3) ; HL is the value of the stack pointer before + add hl, sp ; the interrupt occurred (3 for PC, AF, HL) + push hl ; Offset 5: Stack pointer + push iy ; Offset 4: IY + push ix ; Offset 3: IX + push de ; Offset 2: DE + push bc ; Offset 1: BC + + ; At this point, we know that interrupts were enabled (or we wouldn't be here + ; so we can save a fake indicationn that will cause interrupts to restored when + ; this context is restored + + ld bc, #EZ80_PV_FLAG ; Parity bit. 1=parity odd, IEF2=1 + push bc ; Offset 0: I with interrupt state in parity + di ; (not necessary) + + ; Call the interrupt decode logic. SP points to the beggining of the reg structure + + ld hl, #0 ; Argument #2 is the beginning of the reg structure + add hl, sp ; + push hl ; Place argument #2 at the top of stack + ld bc, #0 ; BC = reset number + ld c, a ; Save the reset number in C + push bc ; Argument #1 is the Reset number + call _up_doirq ; Decode the IRQ + + ; On return, HL points to the beginning of the reg structure to restore + ; Note that (1) the arguments pushed on the stack are not popped, and (2) the + ; original stack pointer is lost. In the normal case (no context switch), + ; HL will contain the value of the SP before the arguments were pushed. + + ld sp, hl ; Use the new stack pointer + + ; Restore registers. HL points to the beginning of the reg structure to restore + + ex af, af' ; Select alternate AF + pop af ; Offset 0: AF' = I with interrupt state in parity + ex af, af' ; Restore original AF + pop bc ; Offset 1: BC + pop de ; Offset 2: DE + pop ix ; Offset 3: IX + pop iy ; Offset 4: IY + exx ; Use alternate BC/DE/HL + pop hl ; Offset 5: HL' = Stack pointer after return + exx ; Restore original BC/DE/HL + pop hl ; Offset 6: HL + pop af ; Offset 7: AF + + ; Restore the stack pointer + + exx ; Use alternate BC/DE/HL + pop de ; Offset 8: Return address + ld sp, hl ; Set SP = saved stack pointer value before return + push de ; Set up for reti + exx ; Restore original BC/DE/HL + + ; Restore interrupt state + + ex af, af' ; Recover interrupt state + jp po, nointenable ; Odd parity, IFF2=0, means disabled + ex af, af' ; Restore AF (before enabling interrupts) + ei ; yes + reti +nointenable: + ex af, af' ; Restore AF + reti + +;************************************************************************** +; Vector Setup Logic +;************************************************************************** + +_ez80_initvectors: + ; Initialize the vector table + + ld iy, _ez80_vectable + ld ix, 4 + ld bc, 4 + ld b, NVECTORS + xor a, a ; Clear carry + ld hl, handlersize + ld de, _ez80_handlers + sbc hl, de ; Length of irq handler in hl + ld d, h + ld e, l + ld hl, _ez80_handlers ; Start of handlers in hl + + ld a, 0 +$1: + ld (iy), hl ; Store IRQ handler + ld (iy+3), a ; Pad to 4 bytes + add hl, de ; Point to next handler + push de + ld de, 4 + add iy, de ; Point to next entry in vector table + pop de + djnz $1 ; Loop until all vectors have been written + + ; Select interrupt mode 2 + + im 2 ; Interrupt mode 2 + + ; Write the address of the vector table into the interrupt vector base + + ld hl, _ez80_vectable >> 8 + ld i, hl + ret + +;************************************************************************** +; Vector Table +;************************************************************************** +; This segment must be aligned on a 512 byte boundary anywhere in RAM +; Each entry will be a 3-byte address in a 4-byte space + + define .IVECTS, space = RAM, align = 200h + segment .IVECTS + + ; The first 64 bytes are not used... the vectors actually start at +0x40 +_ez80_vecreserve: + ds 64 +_ez80_vectable: + ds NVECTORS * 4 diff --git a/arch/z80/src/ez80/ez80f91.h b/arch/z80/src/ez80/ez80f91.h index ec15d8f250ffb4a6dca052ae44f0ad82f855cee8..490c7f923126f53c7095ee01f7562005bae70001 100644 --- a/arch/z80/src/ez80/ez80f91.h +++ b/arch/z80/src/ez80/ez80f91.h @@ -3,7 +3,7 @@ * arch/z80/src/chip/ez80f91.h * * Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/ez80f91_emac.h b/arch/z80/src/ez80/ez80f91_emac.h index 61f2e7f5a43a91e348465f61b9e5fe6ad045e91c..ddd8299a0e3e2964069a6cad3aa0b97831f6bc98 100644 --- a/arch/z80/src/ez80/ez80f91_emac.h +++ b/arch/z80/src/ez80/ez80f91_emac.h @@ -3,7 +3,7 @@ * arch/z80/src/chip/ez80f91_emac.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/ez80f91_i2c.h b/arch/z80/src/ez80/ez80f91_i2c.h index 20ffb513a86367fd27d19ab5b17a6887cc80cd70..f0d6cda4d27789b4e9ab54147add12c9d7d9aa2d 100644 --- a/arch/z80/src/ez80/ez80f91_i2c.h +++ b/arch/z80/src/ez80/ez80f91_i2c.h @@ -3,7 +3,7 @@ * arch/z80/src/chip/ez80f91_i2c.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/ez80f91_init.asm b/arch/z80/src/ez80/ez80f91_init.asm index 422c14f2dc81a27aa3f45f21148ee2353fa34972..17ef5f2952f6c13e32fbad1398dc45e950e4288d 100644 --- a/arch/z80/src/ez80/ez80f91_init.asm +++ b/arch/z80/src/ez80/ez80f91_init.asm @@ -1,257 +1,257 @@ -;************************************************************************** -; arch/z80/src/ez80/ez80f91_init.asm -; -; Copyright (C) 2008 Gregory Nutt. All rights reserved. -; Author: Gregory Nutt -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions -; are met: -; -; 1. Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in -; the documentation and/or other materials provided with the -; distribution. -; 3. Neither the name NuttX nor the names of its contributors may be -; used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; -;************************************************************************** - -;************************************************************************** -; Included Files -;************************************************************************** - - include "ez80f91.inc" - -;************************************************************************** -; Constants -;************************************************************************** - -;PLL_DIV_L EQU %5C -;PLL_DIV_H EQU %5D -;PLL_CTL0 EQU %5E -;PLL_CTL1 EQU %5F - -OSC EQU 0 -PLL EQU 1 -RTC EQU 2 - -CLK_MUX_OSC EQU %00 -CLK_MUX_PLL EQU %01 -CLK_MUX_RTC EQU %02 - -CHRP_CTL_0 EQU %00 -CHRP_CTL_1 EQU %40 -CHRP_CTL_2 EQU %80 -CHRP_CTL_3 EQU %C0 - -LDS_CTL_0 EQU %00 -LDS_CTL_1 EQU %04 -LDS_CTL_2 EQU %08 -LDS_CTL_3 EQU %0C - -LCK_STATUS EQU %20 -INT_LOCK EQU %10 -INT_UNLOCK EQU %08 -INT_LOCK_EN EQU %04 -INT_UNLOCK_EN EQU %02 -PLL_ENABLE EQU %01 - -;************************************************************************** -; Global symbols used -;************************************************************************** - -; Exported symbols - xdef _ez80_init - xdef _ez80_initsysclk - -; Imported symbols - xref __CS0_LBR_INIT_PARAM - xref __CS0_UBR_INIT_PARAM - xref __CS0_CTL_INIT_PARAM - xref __CS1_LBR_INIT_PARAM - xref __CS1_UBR_INIT_PARAM - xref __CS1_CTL_INIT_PARAM - xref __CS2_LBR_INIT_PARAM - xref __CS2_UBR_INIT_PARAM - xref __CS2_CTL_INIT_PARAM - xref __CS3_LBR_INIT_PARAM - xref __CS3_UBR_INIT_PARAM - xref __CS3_CTL_INIT_PARAM - xref __CS0_BMC_INIT_PARAM - xref __CS1_BMC_INIT_PARAM - xref __CS2_BMC_INIT_PARAM - xref __CS3_BMC_INIT_PARAM - xref __FLASH_CTL_INIT_PARAM - xref __FLASH_ADDR_U_INIT_PARAM - xref __RAM_CTL_INIT_PARAM - xref __RAM_ADDR_U_INIT_PARAM - xref _SYS_CLK_SRC - xref _SYS_CLK_FREQ - xref _OSC_FREQ - xref _OSC_FREQ_MULT - xref __PLL_CTL0_INIT_PARAM - -;************************************************************************** -; Chip-specific initialization logic -;************************************************************************** -; Minimum default initialization for eZ80F91 - - define .STARTUP, space = ROM - segment .STARTUP - .assume ADL = 1 - -_ez80_init: - ; Disable internal peripheral interrupt sources - - ld a, %ff - out0 (PA_DDR), a ; GPIO - out0 (PB_DDR), a - out0 (PC_DDR), a - out0 (PD_DDR), a - ld a, %00 - out0 (PA_ALT1), a - out0 (PB_ALT1), a - out0 (PC_ALT1), a - out0 (PD_ALT1), a - out0 (PA_ALT2), a - out0 (PB_ALT2), a - out0 (PC_ALT2), a - out0 (PD_ALT2), a - out0 (PLL_CTL1), a ; PLL - out0 (TMR0_IER), a ; timers - out0 (TMR1_IER), a - out0 (TMR2_IER), a - out0 (TMR3_IER), a - out0 (UART0_IER), a ; UARTs - out0 (UART1_IER), a - out0 (I2C_CTL), a ; I2C - out0 (EMAC_IEN), a ; EMAC - out0 (FLASH_IRQ), a ; Flash - ld a, %04 - out0 (SPI_CTL), a ; SPI - in0 a, (RTC_CTRL) ; RTC, - and a, %be - out0 (RTC_CTRL), a - - ; Configure external memory/io - - ld a, __CS0_LBR_INIT_PARAM - out0 (CS0_LBR), a - ld a, __CS0_UBR_INIT_PARAM - out0 (CS0_UBR), a - ld a, __CS0_BMC_INIT_PARAM - out0 (CS0_BMC), a - ld a, __CS0_CTL_INIT_PARAM - out0 (CS0_CTL), a - - ld a, __CS1_LBR_INIT_PARAM - out0 (CS1_LBR), a - ld a, __CS1_UBR_INIT_PARAM - out0 (CS1_UBR), a - ld a, __CS1_BMC_INIT_PARAM - out0 (CS1_BMC), a - ld a, __CS1_CTL_INIT_PARAM - out0 (CS1_CTL), a - - ld a, __CS2_LBR_INIT_PARAM - out0 (CS2_LBR), a - ld a, __CS2_UBR_INIT_PARAM - out0 (CS2_UBR), a - ld a, __CS2_BMC_INIT_PARAM - out0 (CS2_BMC), a - ld a, __CS2_CTL_INIT_PARAM - out0 (CS2_CTL), a - - ld a, __CS3_LBR_INIT_PARAM - out0 (CS3_LBR), a - ld a, __CS3_UBR_INIT_PARAM - out0 (CS3_UBR), a - ld a, __CS3_BMC_INIT_PARAM - out0 (CS3_BMC), a - ld a, __CS3_CTL_INIT_PARAM - out0 (CS3_CTL), a - - ; Enable internal memory - - ld a, __FLASH_ADDR_U_INIT_PARAM - out0 (FLASH_ADDR_U), a - ld a, __FLASH_CTL_INIT_PARAM - out0 (FLASH_CTRL), a - - ld a, __RAM_ADDR_U_INIT_PARAM - out0 (RAM_ADDR_U), a - ld a, __RAM_CTL_INIT_PARAM - out0 (RAM_CTL), a - ret - -;***************************************************************************** -; eZ80F91 System Clock Initialization -;***************************************************************************** - -_ez80_initsysclk: - ; check if the PLL should be used - ld a, (_ez80_sysclksrc) - cp a, PLL - jr nz, _ez80_initsysclkdone - - ; Load PLL divider - - ld a, (_ez80_oscfreqmult) ;CR 6202 - out0 (PLL_DIV_L), a - ld a, (_ez80_oscfreqmult+1) - out0 (PLL_DIV_H), a - - ; Set charge pump and lock criteria - - ld a, __PLL_CTL0_INIT_PARAM - and a, %CC ; mask off reserved and clock source bits - out0 (PLL_CTL0), a - - ; Enable PLL - - in0 a, (PLL_CTL1) - set 0, a - out0 (PLL_CTL1), a - - ; Wait for PLL to lock -_ez80_initsysclkwait: - in0 a, (PLL_CTL1) - and a, LCK_STATUS - cp a, LCK_STATUS - jr nz, _ez80_initsysclkwait - - ; Select PLL as system clock source - - ld a, __PLL_CTL0_INIT_PARAM - set 0, a - out0 (PLL_CTL0), a - -_ez80_initsysclkdone: - ret - -;_ez80_oscfreq: -; dl _OSC_FREQ -_ez80_oscfreqmult: - dw _OSC_FREQ_MULT -;_ez80_sysclkfreq: -; dl _SYS_CLK_FREQ -_ez80_sysclksrc: - db _SYS_CLK_SRC +;************************************************************************** +; arch/z80/src/ez80/ez80f91_init.asm +; +; Copyright (C) 2008 Gregory Nutt. All rights reserved. +; Author: Gregory Nutt +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in +; the documentation and/or other materials provided with the +; distribution. +; 3. Neither the name NuttX nor the names of its contributors may be +; used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; +;************************************************************************** + +;************************************************************************** +; Included Files +;************************************************************************** + + include "ez80f91.inc" + +;************************************************************************** +; Constants +;************************************************************************** + +;PLL_DIV_L EQU %5C +;PLL_DIV_H EQU %5D +;PLL_CTL0 EQU %5E +;PLL_CTL1 EQU %5F + +OSC EQU 0 +PLL EQU 1 +RTC EQU 2 + +CLK_MUX_OSC EQU %00 +CLK_MUX_PLL EQU %01 +CLK_MUX_RTC EQU %02 + +CHRP_CTL_0 EQU %00 +CHRP_CTL_1 EQU %40 +CHRP_CTL_2 EQU %80 +CHRP_CTL_3 EQU %C0 + +LDS_CTL_0 EQU %00 +LDS_CTL_1 EQU %04 +LDS_CTL_2 EQU %08 +LDS_CTL_3 EQU %0C + +LCK_STATUS EQU %20 +INT_LOCK EQU %10 +INT_UNLOCK EQU %08 +INT_LOCK_EN EQU %04 +INT_UNLOCK_EN EQU %02 +PLL_ENABLE EQU %01 + +;************************************************************************** +; Global symbols used +;************************************************************************** + +; Exported symbols + xdef _ez80_init + xdef _ez80_initsysclk + +; Imported symbols + xref __CS0_LBR_INIT_PARAM + xref __CS0_UBR_INIT_PARAM + xref __CS0_CTL_INIT_PARAM + xref __CS1_LBR_INIT_PARAM + xref __CS1_UBR_INIT_PARAM + xref __CS1_CTL_INIT_PARAM + xref __CS2_LBR_INIT_PARAM + xref __CS2_UBR_INIT_PARAM + xref __CS2_CTL_INIT_PARAM + xref __CS3_LBR_INIT_PARAM + xref __CS3_UBR_INIT_PARAM + xref __CS3_CTL_INIT_PARAM + xref __CS0_BMC_INIT_PARAM + xref __CS1_BMC_INIT_PARAM + xref __CS2_BMC_INIT_PARAM + xref __CS3_BMC_INIT_PARAM + xref __FLASH_CTL_INIT_PARAM + xref __FLASH_ADDR_U_INIT_PARAM + xref __RAM_CTL_INIT_PARAM + xref __RAM_ADDR_U_INIT_PARAM + xref _SYS_CLK_SRC + xref _SYS_CLK_FREQ + xref _OSC_FREQ + xref _OSC_FREQ_MULT + xref __PLL_CTL0_INIT_PARAM + +;************************************************************************** +; Chip-specific initialization logic +;************************************************************************** +; Minimum default initialization for eZ80F91 + + define .STARTUP, space = ROM + segment .STARTUP + .assume ADL = 1 + +_ez80_init: + ; Disable internal peripheral interrupt sources + + ld a, %ff + out0 (PA_DDR), a ; GPIO + out0 (PB_DDR), a + out0 (PC_DDR), a + out0 (PD_DDR), a + ld a, %00 + out0 (PA_ALT1), a + out0 (PB_ALT1), a + out0 (PC_ALT1), a + out0 (PD_ALT1), a + out0 (PA_ALT2), a + out0 (PB_ALT2), a + out0 (PC_ALT2), a + out0 (PD_ALT2), a + out0 (PLL_CTL1), a ; PLL + out0 (TMR0_IER), a ; timers + out0 (TMR1_IER), a + out0 (TMR2_IER), a + out0 (TMR3_IER), a + out0 (UART0_IER), a ; UARTs + out0 (UART1_IER), a + out0 (I2C_CTL), a ; I2C + out0 (EMAC_IEN), a ; EMAC + out0 (FLASH_IRQ), a ; Flash + ld a, %04 + out0 (SPI_CTL), a ; SPI + in0 a, (RTC_CTRL) ; RTC, + and a, %be + out0 (RTC_CTRL), a + + ; Configure external memory/io + + ld a, __CS0_LBR_INIT_PARAM + out0 (CS0_LBR), a + ld a, __CS0_UBR_INIT_PARAM + out0 (CS0_UBR), a + ld a, __CS0_BMC_INIT_PARAM + out0 (CS0_BMC), a + ld a, __CS0_CTL_INIT_PARAM + out0 (CS0_CTL), a + + ld a, __CS1_LBR_INIT_PARAM + out0 (CS1_LBR), a + ld a, __CS1_UBR_INIT_PARAM + out0 (CS1_UBR), a + ld a, __CS1_BMC_INIT_PARAM + out0 (CS1_BMC), a + ld a, __CS1_CTL_INIT_PARAM + out0 (CS1_CTL), a + + ld a, __CS2_LBR_INIT_PARAM + out0 (CS2_LBR), a + ld a, __CS2_UBR_INIT_PARAM + out0 (CS2_UBR), a + ld a, __CS2_BMC_INIT_PARAM + out0 (CS2_BMC), a + ld a, __CS2_CTL_INIT_PARAM + out0 (CS2_CTL), a + + ld a, __CS3_LBR_INIT_PARAM + out0 (CS3_LBR), a + ld a, __CS3_UBR_INIT_PARAM + out0 (CS3_UBR), a + ld a, __CS3_BMC_INIT_PARAM + out0 (CS3_BMC), a + ld a, __CS3_CTL_INIT_PARAM + out0 (CS3_CTL), a + + ; Enable internal memory + + ld a, __FLASH_ADDR_U_INIT_PARAM + out0 (FLASH_ADDR_U), a + ld a, __FLASH_CTL_INIT_PARAM + out0 (FLASH_CTRL), a + + ld a, __RAM_ADDR_U_INIT_PARAM + out0 (RAM_ADDR_U), a + ld a, __RAM_CTL_INIT_PARAM + out0 (RAM_CTL), a + ret + +;***************************************************************************** +; eZ80F91 System Clock Initialization +;***************************************************************************** + +_ez80_initsysclk: + ; check if the PLL should be used + ld a, (_ez80_sysclksrc) + cp a, PLL + jr nz, _ez80_initsysclkdone + + ; Load PLL divider + + ld a, (_ez80_oscfreqmult) ;CR 6202 + out0 (PLL_DIV_L), a + ld a, (_ez80_oscfreqmult+1) + out0 (PLL_DIV_H), a + + ; Set charge pump and lock criteria + + ld a, __PLL_CTL0_INIT_PARAM + and a, %CC ; mask off reserved and clock source bits + out0 (PLL_CTL0), a + + ; Enable PLL + + in0 a, (PLL_CTL1) + set 0, a + out0 (PLL_CTL1), a + + ; Wait for PLL to lock +_ez80_initsysclkwait: + in0 a, (PLL_CTL1) + and a, LCK_STATUS + cp a, LCK_STATUS + jr nz, _ez80_initsysclkwait + + ; Select PLL as system clock source + + ld a, __PLL_CTL0_INIT_PARAM + set 0, a + out0 (PLL_CTL0), a + +_ez80_initsysclkdone: + ret + +;_ez80_oscfreq: +; dl _OSC_FREQ +_ez80_oscfreqmult: + dw _OSC_FREQ_MULT +;_ez80_sysclkfreq: +; dl _SYS_CLK_FREQ +_ez80_sysclksrc: + db _SYS_CLK_SRC end \ No newline at end of file diff --git a/arch/z80/src/ez80/ez80f91_spi.h b/arch/z80/src/ez80/ez80f91_spi.h index e27df2693abd712be3f644e2369308239aef67cf..9fa42917b2262018aa0f4f710ca1ac6a2ecbac0d 100644 --- a/arch/z80/src/ez80/ez80f91_spi.h +++ b/arch/z80/src/ez80/ez80f91_spi.h @@ -3,7 +3,7 @@ * arch/z80/src/chip/ez80f91_spi.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/switch.h b/arch/z80/src/ez80/switch.h index 3b7f1bd95ff7ef6d8c0af7512f1725eb0fe1d4a0..de6506490c091916e3d8e371f94f4bbceeffe1dd 100644 --- a/arch/z80/src/ez80/switch.h +++ b/arch/z80/src/ez80/switch.h @@ -3,7 +3,7 @@ * arch/z80/src/chip/switch.h * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/ez80/up_mem.h b/arch/z80/src/ez80/up_mem.h index 724facbd370475d9535829fe72a6ff3cdde35c13..62424702261ae3e17c70eacbc597c807b13125e0 100644 --- a/arch/z80/src/ez80/up_mem.h +++ b/arch/z80/src/ez80/up_mem.h @@ -3,7 +3,7 @@ * arch/z80/src/chip/up_mem.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/mkhpbase.sh b/arch/z80/src/mkhpbase.sh index 48647e822c01acf3fd19b4af2ce41856d723a378..1d7acb7d56f2863220b7fd1cc5041f1d58cec90a 100755 --- a/arch/z80/src/mkhpbase.sh +++ b/arch/z80/src/mkhpbase.sh @@ -3,7 +3,7 @@ # arch/z80/src/mkhpbase.sh # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z8/Make.defs b/arch/z80/src/z8/Make.defs index ae4f2a48c90ea15b643f4e19b75bc84c80f1d1a6..5d7a338bec1cb403d4d0343fb3adb39602412d85 100644 --- a/arch/z80/src/z8/Make.defs +++ b/arch/z80/src/z8/Make.defs @@ -2,7 +2,7 @@ # arch/z80/src/z8/Make.defs # # Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z8/chip.h b/arch/z80/src/z8/chip.h index 7635c0407c415a22822d504689d5b3c6a98f8eea..4951a27fabc181857e5819bfd9b07bcc6ba27db1 100644 --- a/arch/z80/src/z8/chip.h +++ b/arch/z80/src/z8/chip.h @@ -3,7 +3,7 @@ * arch/z80/src/chip/chip.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z8/switch.h b/arch/z80/src/z8/switch.h index c37d7bcd025c44385059807789750dc76412ffc2..7738f24362ba76fa5918a257bf5be671cda5ee4b 100644 --- a/arch/z80/src/z8/switch.h +++ b/arch/z80/src/z8/switch.h @@ -3,7 +3,7 @@ * arch/z80/src/chip/switch.h * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z8/up_mem.h b/arch/z80/src/z8/up_mem.h index 42ad293a838281319b0998366d06b8cc622a3b2f..681805e66b4aa92078bfb2fc00b8846c5c8afbba 100644 --- a/arch/z80/src/z8/up_mem.h +++ b/arch/z80/src/z8/up_mem.h @@ -3,7 +3,7 @@ * arch/z80/src/chip/up_mem.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z8/z8_head.S b/arch/z80/src/z8/z8_head.S index 550409632d616dd4aaa77d64bb4251aae814fee8..7fcd90504446f6e03055ff8a47e246dad451012f 100755 --- a/arch/z80/src/z8/z8_head.S +++ b/arch/z80/src/z8/z8_head.S @@ -1,253 +1,253 @@ -/************************************************************************** - * arch/z80/src/z8/z8_head.S - * ez8 Reset Entry Point - * - * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS or IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER or CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, or CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS or SERVICES; LOSS - * OF USE, DATA, or PROFITS; or BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, or TORT (INCLUDING NEGLIGENCE or OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************/ - -/************************************************************************** - * Included Files - **************************************************************************/ - -#include -#include -#include -#include - -/************************************************************************** - * Definitions - **************************************************************************/ - -/* Assume the large model */ - -#if !defined(CONFIG_Z8_MODEL_LARGE) && !defined(CONFIG_Z8_MODEL_SMALL) -# define CONFIG_Z8_MODEL_LARGE 1 -# undef CONFIG_Z8_MODEL_SMALL -#endif - -#ifdef __Z8F1680 -# define CONFIG_Z8_COPYPRAM -#else -# undef CONFIG_Z8_COPYPRAM -#endif - - -/************************************************************************** - * External References / External Definitions - **************************************************************************/ - - xref _z16f_clkinit:ROM - xref _z16f_lowinit:ROM -#ifdef CONFIG_ARCH_LEDS - xref _up_ledinit:ROM -#endif - xref _os_start:ROM - xref _up_doirq:ROM - xref _low_nearbss - xref _len_nearbss - xref _low_farbss - xref _len_farbss - xref _low_neardata - xref _len_neardata - xref _low_near_romdata - xref _low_fardata - xref _len_fardata - xref _low_far_romdata -#ifdef CONFIG_Z8_COPYPRAM - xref _low_pramseg - xref _len_pramseg - xref _low_pram_romdata -#endif - xref _far_stacktop - xdef _z8_reset - xdef __intrp - -/************************************************************************** - * Code - **************************************************************************/ - - segment CODE - -/************************************************************************** - * Interrupt Vectors - **************************************************************************/ - - /* Reset vector */ - - vector RESET = _z8_reset - -/************************************************************************** - * Name: _z16f_reset - * - * Description: - * Reset entry point - * - **************************************************************************/ - - define startup, space=rom - segment startup -_z8_reset: - /* Set the register pointer for working registers e0-ef */ - - srp #%e0 - - /* Initialize the stack pointer */ - - ldx spl, #low(_far_stacktop+1) - ldx sph, #high(_far_stacktop+1) - - /* Clear internal register ram area (c_nearbss) */ - - ld r0, #_low_nearbss - ld r2, #_len_nearbss - cp r2, #0 - jr z, _z8_reset2 - -_z8_reset1: - clr @r0 - inc r0 - djnz r2, _z8_reset1 - - /* Clear extended ram area (c_farbss) */ - -_z8_reset2: - ld r2, #high(_low_farbss) - ld r3, #low(_low_farbss) - ld r0, #high(_len_farbss) - ld r1, #low(_len_farbss) - - ld r4, r0 - or r4, r1 - jr z, _z8_reset4 - clr r4 - -_z8_reset3: - ldx @rr2,r4 - incw rr2 - decw rr0 - jr nz, _z8_reset3 - - /* Copy ROM data into internal RAM */ - -_z8_reset4: -#ifdef CONFIG_Z8_COPYNEARDATA - ld r0, #high(_low_near_romdata) - ld r1, #low(_low_near_romdata) - ld r3, #_len_neardata - ld r4, #_low_neardata - cp r3, #0 - jr z, _z8_reset6 - -_z8_reset5: - ldci @r4, @rr0 - djnz r3, _z8_reset5 - -_z8_reset6: -#endif - /* Copy ROM data into extended RAM */ - - ld r0, #high(_low_fardata) - ld r1, #low(_low_fardata) - ld r2, #high(_low_far_romdata) - ld r3, #low(_low_far_romdata) - ld r4, #high(_len_fardata) - ld r5, #low(_len_fardata) - - ld r6, r4 - or r6, r5 - jr z, _z8_reset8 - -_z8_reset7: - ldc r6, @rr2 - ldx @rr0, r6 - incw rr0 - incw rr2 - decw rr4 - jr nz, _z8_reset7 - - /* Copy ROM copy of code into Program RAM */ - -_z8_reset8: -#ifdef CONFIG_Z8_COPYPRAM - ld r0, #high(_low_pramseg) - ld r1, #low(_low_pramseg) - ld r2, #high(_low_pram_romdata) - ld r3, #low(_low_pram_romdata) - ld r4, #high(_len_pramseg) - ld r5, #low(_len_pramseg) - - ld r6, r4 - or r6, r5 - jr z, _z8_reset10 - -_z8_reset9: - ldc r6, @rr2 - ldc @rr0, r6 - incw rr0 - incw rr2 - decw rr4 - jr nz, _z8_reset9 - -_z8_reset10: -#endif - - /* Start NuttX */ - - ldx __intrp,#0 - xor r15, r15 - xor r14, r14 - call _os_start - - /* We should never get here */ - -_z8_reset_halt: - jr _z8_reset_halt - -/************************************************************************** - * Data - **************************************************************************/ - -#ifdef CONFIG_Z8_MODEL_LARGE - segment FAR_BSS -__intrp ds 1 -#else - segment NEAR_BSS -__intrp ds 1 -#endif - - /* Set aside area for working registers */ - - define workingreg, space=rdata, org=%e0 - segment workingreg - ds %10 - - end _z8_reset +/************************************************************************** + * arch/z80/src/z8/z8_head.S + * ez8 Reset Entry Point + * + * Copyright (C) 2008 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS or IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER or CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, or CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS or SERVICES; LOSS + * OF USE, DATA, or PROFITS; or BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, or TORT (INCLUDING NEGLIGENCE or OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************/ + +/************************************************************************** + * Included Files + **************************************************************************/ + +#include +#include +#include +#include + +/************************************************************************** + * Definitions + **************************************************************************/ + +/* Assume the large model */ + +#if !defined(CONFIG_Z8_MODEL_LARGE) && !defined(CONFIG_Z8_MODEL_SMALL) +# define CONFIG_Z8_MODEL_LARGE 1 +# undef CONFIG_Z8_MODEL_SMALL +#endif + +#ifdef __Z8F1680 +# define CONFIG_Z8_COPYPRAM +#else +# undef CONFIG_Z8_COPYPRAM +#endif + + +/************************************************************************** + * External References / External Definitions + **************************************************************************/ + + xref _z16f_clkinit:ROM + xref _z16f_lowinit:ROM +#ifdef CONFIG_ARCH_LEDS + xref _up_ledinit:ROM +#endif + xref _os_start:ROM + xref _up_doirq:ROM + xref _low_nearbss + xref _len_nearbss + xref _low_farbss + xref _len_farbss + xref _low_neardata + xref _len_neardata + xref _low_near_romdata + xref _low_fardata + xref _len_fardata + xref _low_far_romdata +#ifdef CONFIG_Z8_COPYPRAM + xref _low_pramseg + xref _len_pramseg + xref _low_pram_romdata +#endif + xref _far_stacktop + xdef _z8_reset + xdef __intrp + +/************************************************************************** + * Code + **************************************************************************/ + + segment CODE + +/************************************************************************** + * Interrupt Vectors + **************************************************************************/ + + /* Reset vector */ + + vector RESET = _z8_reset + +/************************************************************************** + * Name: _z16f_reset + * + * Description: + * Reset entry point + * + **************************************************************************/ + + define startup, space=rom + segment startup +_z8_reset: + /* Set the register pointer for working registers e0-ef */ + + srp #%e0 + + /* Initialize the stack pointer */ + + ldx spl, #low(_far_stacktop+1) + ldx sph, #high(_far_stacktop+1) + + /* Clear internal register ram area (c_nearbss) */ + + ld r0, #_low_nearbss + ld r2, #_len_nearbss + cp r2, #0 + jr z, _z8_reset2 + +_z8_reset1: + clr @r0 + inc r0 + djnz r2, _z8_reset1 + + /* Clear extended ram area (c_farbss) */ + +_z8_reset2: + ld r2, #high(_low_farbss) + ld r3, #low(_low_farbss) + ld r0, #high(_len_farbss) + ld r1, #low(_len_farbss) + + ld r4, r0 + or r4, r1 + jr z, _z8_reset4 + clr r4 + +_z8_reset3: + ldx @rr2,r4 + incw rr2 + decw rr0 + jr nz, _z8_reset3 + + /* Copy ROM data into internal RAM */ + +_z8_reset4: +#ifdef CONFIG_Z8_COPYNEARDATA + ld r0, #high(_low_near_romdata) + ld r1, #low(_low_near_romdata) + ld r3, #_len_neardata + ld r4, #_low_neardata + cp r3, #0 + jr z, _z8_reset6 + +_z8_reset5: + ldci @r4, @rr0 + djnz r3, _z8_reset5 + +_z8_reset6: +#endif + /* Copy ROM data into extended RAM */ + + ld r0, #high(_low_fardata) + ld r1, #low(_low_fardata) + ld r2, #high(_low_far_romdata) + ld r3, #low(_low_far_romdata) + ld r4, #high(_len_fardata) + ld r5, #low(_len_fardata) + + ld r6, r4 + or r6, r5 + jr z, _z8_reset8 + +_z8_reset7: + ldc r6, @rr2 + ldx @rr0, r6 + incw rr0 + incw rr2 + decw rr4 + jr nz, _z8_reset7 + + /* Copy ROM copy of code into Program RAM */ + +_z8_reset8: +#ifdef CONFIG_Z8_COPYPRAM + ld r0, #high(_low_pramseg) + ld r1, #low(_low_pramseg) + ld r2, #high(_low_pram_romdata) + ld r3, #low(_low_pram_romdata) + ld r4, #high(_len_pramseg) + ld r5, #low(_len_pramseg) + + ld r6, r4 + or r6, r5 + jr z, _z8_reset10 + +_z8_reset9: + ldc r6, @rr2 + ldc @rr0, r6 + incw rr0 + incw rr2 + decw rr4 + jr nz, _z8_reset9 + +_z8_reset10: +#endif + + /* Start NuttX */ + + ldx __intrp,#0 + xor r15, r15 + xor r14, r14 + call _os_start + + /* We should never get here */ + +_z8_reset_halt: + jr _z8_reset_halt + +/************************************************************************** + * Data + **************************************************************************/ + +#ifdef CONFIG_Z8_MODEL_LARGE + segment FAR_BSS +__intrp ds 1 +#else + segment NEAR_BSS +__intrp ds 1 +#endif + + /* Set aside area for working registers */ + + define workingreg, space=rdata, org=%e0 + segment workingreg + ds %10 + + end _z8_reset diff --git a/arch/z80/src/z8/z8_i2c.c b/arch/z80/src/z8/z8_i2c.c index be4a94eb02c63c5805cf767bfdc47d0a5d736960..e90bd40365409dcac00e49815e0418f0f53dad2b 100755 --- a/arch/z80/src/z8/z8_i2c.c +++ b/arch/z80/src/z8/z8_i2c.c @@ -2,7 +2,7 @@ * arch/z80/src/z8/z8_i2c.c * * Copyright(C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z8/z8_initialstate.c b/arch/z80/src/z8/z8_initialstate.c index 794446aacb812c72a80ea96e954974447d535f64..706347da9e53575ab2abcf9cad598d139d761be1 100644 --- a/arch/z80/src/z8/z8_initialstate.c +++ b/arch/z80/src/z8/z8_initialstate.c @@ -2,7 +2,7 @@ * arch/z80/src/z8/z8_initialstate.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z8/z8_irq.c b/arch/z80/src/z8/z8_irq.c index be732fe83e31ec6a4659838d85c8b7a8abf5b06c..82ab4d60ca1879f65e8dec3886e1dd8e058fda1e 100644 --- a/arch/z80/src/z8/z8_irq.c +++ b/arch/z80/src/z8/z8_irq.c @@ -2,7 +2,7 @@ * arch/z80/src/z8/z8_irq.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z8/z8_registerdump.c b/arch/z80/src/z8/z8_registerdump.c index d9ccdf48f87979d9a2e1d0925909657d2c6999c8..36b6cdd379fb9d66f6695d41f60f51631ea8b2ef 100644 --- a/arch/z80/src/z8/z8_registerdump.c +++ b/arch/z80/src/z8/z8_registerdump.c @@ -2,7 +2,7 @@ * arch/z80/src/z8/z8_registerdump.c * * Copyright (C) 2008-2009,2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z8/z8_restorecontext.S b/arch/z80/src/z8/z8_restorecontext.S index 4cdd0d3d0ce88e3efa5d57e692fa14ba28ca6e25..88e29781c1b8fc71639ab683ceaee6ff5b375089 100755 --- a/arch/z80/src/z8/z8_restorecontext.S +++ b/arch/z80/src/z8/z8_restorecontext.S @@ -1,164 +1,164 @@ -/************************************************************************** - * arch/z80/src/z8/z8_saveusercontext.S - * Save the state of the current user thread - * - * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS or IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER or CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, or CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS or SERVICES; LOSS - * OF USE, DATA, or PROFITS; or BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, or TORT (INCLUDING NEGLIGENCE or OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************/ - -/************************************************************************** - * Included Files - **************************************************************************/ - -#include -#include -#include - -/************************************************************************** - * Definitions - **************************************************************************/ - - xdef _z8_restorecontext - -/************************************************************************** - * Code - **************************************************************************/ - - segment CODE - -/**************************************************************************** - * Name: _z8_restorecontext - * - * Description: - * Restore the task context that was previously saved via - * _z8_saveusercontext() or by interrupt handling. Unlike the - * _z8_saveusercontext() counterpart, we do not know the context of the - * restored task and, hence, we must handle the worst case -- restore - * everythihng. - * - * Parameters: - * On entry, the following stack organization is assumed: - * - * Pointer to the context save structure - * TOS -> Return address (2) - * - * Assumptions: - * Large model, dynamic frames - * - **************************************************************************/ - -_z8_restorecontext: - /* Disable all interrupts because we are going to be using - * the IRQ register set. - */ - - di - - /* Switch to IRQ register set */ - - srp #%f0 - - /* Get the rr0 = the current value of the stack pointer */ - - ldx r0, sph /* rr0 = stack pointer */ - ldx r1, spl - - /* Get rr6 = the pointer to the context save structure */ - - ldx r6, 2(rr0) /* rr6 = pointer to context structure */ - ldx r7, 3(rr0) - - /* Copy all registers into the user register area. NOTE: we - * use the saved RP value to determine the destination adress. - */ - - clr r0 /* rr0 = destination address */ - ldx r1, XCPT_RP_OFFS(rr6) - ld r2, r6 /* rr2 = source address */ - ld r3, r7 - ld r4, #16 /* r4 = number of bytes to copy */ - -_z8_restore: - ldx r5, @rr2 - ldx @rr0, r5 - incw rr0 - incw rr2 - djnz r4, _z8_restore - - /* Set the new stack pointer */ - - ldx r0, XCPT_SPH_OFFS(rr6) - ldx r1, XCPT_SPL_OFFS(rr6) - ldx sph, r0 - ldx spl, r1 - - /* Push the return address onto the stack */ - - ldx r0, XCPT_PCH_OFFS(rr6) - ldx r1, XCPT_PCL_OFFS(rr6) - push r1 - push r0 - - /* Recover the flags and RP settings.. but don't restore them yet */ - - ldx r1, XCPT_FLAGS_OFFS(rr6) - ldx r2, XCPT_RP_OFFS(rr6) - - /* Determine whether interrupts must be enabled on return. This - * would be nicer to do below, but later we will need to preserve - * the condition codes in the flags. - */ - - ldx r0, XCPT_IRQCTL_OFFS(rr6) - tm r0, #%80 - jr nz, _z8_returnenabled - - /* Restore the flag settings */ - - ldx flags, r1 - - /* Restore the user register page and return with interrupts disabled */ - - ldx rp, r2 /* Does not effect flags */ - ret /* Does not effect flags */ - -_z8_returnenabled: - /* Restore the flag settings */ - - ldx flags, r1 - - /* Restore the user register page, re-enable interrupts and return */ - - ldx rp, r2 /* Does not effect flags */ - ei /* Does not effect flags */ - ret /* Does not effect flags */ - - end +/************************************************************************** + * arch/z80/src/z8/z8_saveusercontext.S + * Save the state of the current user thread + * + * Copyright (C) 2008 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS or IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER or CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, or CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS or SERVICES; LOSS + * OF USE, DATA, or PROFITS; or BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, or TORT (INCLUDING NEGLIGENCE or OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************/ + +/************************************************************************** + * Included Files + **************************************************************************/ + +#include +#include +#include + +/************************************************************************** + * Definitions + **************************************************************************/ + + xdef _z8_restorecontext + +/************************************************************************** + * Code + **************************************************************************/ + + segment CODE + +/**************************************************************************** + * Name: _z8_restorecontext + * + * Description: + * Restore the task context that was previously saved via + * _z8_saveusercontext() or by interrupt handling. Unlike the + * _z8_saveusercontext() counterpart, we do not know the context of the + * restored task and, hence, we must handle the worst case -- restore + * everythihng. + * + * Parameters: + * On entry, the following stack organization is assumed: + * + * Pointer to the context save structure + * TOS -> Return address (2) + * + * Assumptions: + * Large model, dynamic frames + * + **************************************************************************/ + +_z8_restorecontext: + /* Disable all interrupts because we are going to be using + * the IRQ register set. + */ + + di + + /* Switch to IRQ register set */ + + srp #%f0 + + /* Get the rr0 = the current value of the stack pointer */ + + ldx r0, sph /* rr0 = stack pointer */ + ldx r1, spl + + /* Get rr6 = the pointer to the context save structure */ + + ldx r6, 2(rr0) /* rr6 = pointer to context structure */ + ldx r7, 3(rr0) + + /* Copy all registers into the user register area. NOTE: we + * use the saved RP value to determine the destination adress. + */ + + clr r0 /* rr0 = destination address */ + ldx r1, XCPT_RP_OFFS(rr6) + ld r2, r6 /* rr2 = source address */ + ld r3, r7 + ld r4, #16 /* r4 = number of bytes to copy */ + +_z8_restore: + ldx r5, @rr2 + ldx @rr0, r5 + incw rr0 + incw rr2 + djnz r4, _z8_restore + + /* Set the new stack pointer */ + + ldx r0, XCPT_SPH_OFFS(rr6) + ldx r1, XCPT_SPL_OFFS(rr6) + ldx sph, r0 + ldx spl, r1 + + /* Push the return address onto the stack */ + + ldx r0, XCPT_PCH_OFFS(rr6) + ldx r1, XCPT_PCL_OFFS(rr6) + push r1 + push r0 + + /* Recover the flags and RP settings.. but don't restore them yet */ + + ldx r1, XCPT_FLAGS_OFFS(rr6) + ldx r2, XCPT_RP_OFFS(rr6) + + /* Determine whether interrupts must be enabled on return. This + * would be nicer to do below, but later we will need to preserve + * the condition codes in the flags. + */ + + ldx r0, XCPT_IRQCTL_OFFS(rr6) + tm r0, #%80 + jr nz, _z8_returnenabled + + /* Restore the flag settings */ + + ldx flags, r1 + + /* Restore the user register page and return with interrupts disabled */ + + ldx rp, r2 /* Does not effect flags */ + ret /* Does not effect flags */ + +_z8_returnenabled: + /* Restore the flag settings */ + + ldx flags, r1 + + /* Restore the user register page, re-enable interrupts and return */ + + ldx rp, r2 /* Does not effect flags */ + ei /* Does not effect flags */ + ret /* Does not effect flags */ + + end diff --git a/arch/z80/src/z8/z8_saveirqcontext.c b/arch/z80/src/z8/z8_saveirqcontext.c index 2d3fb7aa2febf2761fefaaccc91e2376dcb6d139..ea206c9dd37472ae7b9cfd0bdc5ec3ab73f63141 100644 --- a/arch/z80/src/z8/z8_saveirqcontext.c +++ b/arch/z80/src/z8/z8_saveirqcontext.c @@ -2,7 +2,7 @@ * arch/z80/src/z8/z8_saveirqcontext.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z8/z8_saveusercontext.S b/arch/z80/src/z8/z8_saveusercontext.S index 314cf3e77a4fd5dcb8797ce0c02d47a1ee88882a..e553515505eff31ba7f043f2ba218df544d461e0 100755 --- a/arch/z80/src/z8/z8_saveusercontext.S +++ b/arch/z80/src/z8/z8_saveusercontext.S @@ -1,165 +1,165 @@ -/************************************************************************** - * arch/z80/src/z8/z8_saveusercontext.S - * Save the state of the current user thread - * - * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS or IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER or CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, or CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS or SERVICES; LOSS - * OF USE, DATA, or PROFITS; or BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, or TORT (INCLUDING NEGLIGENCE or OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************/ - -/************************************************************************** - * Included Files - **************************************************************************/ - -#include -#include -#include - -/************************************************************************** - * Definitions - **************************************************************************/ - - xdef _z8_saveusercontext - -/************************************************************************** - * Code - **************************************************************************/ - - segment CODE - -/**************************************************************************** - * Name: _z8_saveusercontext - * - * Description: - * Save the current state of the user thread. Since this function is - * called from user code, it is only necessary to save the parts of the - * context that must be preserved between function calls. This includes - * - * - Frame pointer (r14, r15) - * - Register pointer (RP) - * - Interrupt state (flags) - * - Stack pointer (sph, spl) - * - Return address - * - * Parameters: - * On entry, the following stack organization is assumed: - * - * Pointer to the context save structure - * TOS -> Return address (2) - * - * Assumptions: - * Large model, dynamic frames - * - **************************************************************************/ - -_z8_saveusercontext: - /* Get the rr6 = the current value of the stack pointer */ - - ldx r6, sph /* rr6 = stack pointer */ - ldx r7, spl - - /* Get rr2 = the pointer to the context save structure */ - - ldx r2, 2(rr6) /* rr2 = pointer to context structure */ - ldx r3, 3(rr6) - - /* Get the value currently in the interrupt control register. - * Bit 7 (IRQE) determines whether or not interrupts are - * currently enabled (0:disabled, 1:enabled) - */ - - ldx r4, IRQCTL /* r4 = IRQCTL value */ - - /* Disable all interrupts so that there can be no concurrent - * modification of the TCB state save area. - */ - - di - - /* Fetch and save the return address from the stack */ - - ldx r0, @rr6 /* rr0 = return address */ - ldx r1, 1(rr6) - ldx XCPT_PCH_OFFS(rr2), r0 - ldx XCPT_PCL_OFFS(rr2), r1 - - /* Fetch and save the register pointer */ - - ldx r0, rp /* r0 = register pointer */ - ldx XCPT_RP_OFFS(rr2), r0 - - /* Calculate the value of the stack pointer on return - * from this function - */ - - ld r1, #3 /* rr0 = 3 */ - clr r0 - add r1, r7 /* rr0 = SP + 3 */ - adc r0, r6 - ldx XCPT_SPH_OFFS(rr2), r0 - ldx XCPT_SPL_OFFS(rr2), r1 - - /* Save the IRQCTL register value */ - - clr r0 - ldx XCPT_UNUSED_OFFS(rr2), r0 - ldx XCPT_IRQCTL_OFFS(rr2), r4 - - /* Save the frame pointer (rr14) in the context structure */ - - ldx XCPT_R14_OFFS(rr2), r14 - ldx XCPT_R15_OFFS(rr2), r15 - - /* Set the return value of 1 in the context structure. When the - * state is restored (via z8_restorecontext() or an interrupt - * return), the return value of 1 distinguishes the no-context- - * switch case. - */ - - /* clr r0 */ - ld r1, #1 - ldx XCPT_R0_OFFS(rr2), r0 - ldx XCPT_R1_OFFS(rr2), r1 - - /* Setup to return zero for the no-context-switch case */ - - /* clr r0 */ - clr r1 - - /* Now decide if we need to re-enable interrupts or not */ - - tm r4, #%80 - jr z, _z8_noenable - ei -_z8_noenable: - ret - - end - +/************************************************************************** + * arch/z80/src/z8/z8_saveusercontext.S + * Save the state of the current user thread + * + * Copyright (C) 2008 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS or IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER or CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, or CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS or SERVICES; LOSS + * OF USE, DATA, or PROFITS; or BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, or TORT (INCLUDING NEGLIGENCE or OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************/ + +/************************************************************************** + * Included Files + **************************************************************************/ + +#include +#include +#include + +/************************************************************************** + * Definitions + **************************************************************************/ + + xdef _z8_saveusercontext + +/************************************************************************** + * Code + **************************************************************************/ + + segment CODE + +/**************************************************************************** + * Name: _z8_saveusercontext + * + * Description: + * Save the current state of the user thread. Since this function is + * called from user code, it is only necessary to save the parts of the + * context that must be preserved between function calls. This includes + * + * - Frame pointer (r14, r15) + * - Register pointer (RP) + * - Interrupt state (flags) + * - Stack pointer (sph, spl) + * - Return address + * + * Parameters: + * On entry, the following stack organization is assumed: + * + * Pointer to the context save structure + * TOS -> Return address (2) + * + * Assumptions: + * Large model, dynamic frames + * + **************************************************************************/ + +_z8_saveusercontext: + /* Get the rr6 = the current value of the stack pointer */ + + ldx r6, sph /* rr6 = stack pointer */ + ldx r7, spl + + /* Get rr2 = the pointer to the context save structure */ + + ldx r2, 2(rr6) /* rr2 = pointer to context structure */ + ldx r3, 3(rr6) + + /* Get the value currently in the interrupt control register. + * Bit 7 (IRQE) determines whether or not interrupts are + * currently enabled (0:disabled, 1:enabled) + */ + + ldx r4, IRQCTL /* r4 = IRQCTL value */ + + /* Disable all interrupts so that there can be no concurrent + * modification of the TCB state save area. + */ + + di + + /* Fetch and save the return address from the stack */ + + ldx r0, @rr6 /* rr0 = return address */ + ldx r1, 1(rr6) + ldx XCPT_PCH_OFFS(rr2), r0 + ldx XCPT_PCL_OFFS(rr2), r1 + + /* Fetch and save the register pointer */ + + ldx r0, rp /* r0 = register pointer */ + ldx XCPT_RP_OFFS(rr2), r0 + + /* Calculate the value of the stack pointer on return + * from this function + */ + + ld r1, #3 /* rr0 = 3 */ + clr r0 + add r1, r7 /* rr0 = SP + 3 */ + adc r0, r6 + ldx XCPT_SPH_OFFS(rr2), r0 + ldx XCPT_SPL_OFFS(rr2), r1 + + /* Save the IRQCTL register value */ + + clr r0 + ldx XCPT_UNUSED_OFFS(rr2), r0 + ldx XCPT_IRQCTL_OFFS(rr2), r4 + + /* Save the frame pointer (rr14) in the context structure */ + + ldx XCPT_R14_OFFS(rr2), r14 + ldx XCPT_R15_OFFS(rr2), r15 + + /* Set the return value of 1 in the context structure. When the + * state is restored (via z8_restorecontext() or an interrupt + * return), the return value of 1 distinguishes the no-context- + * switch case. + */ + + /* clr r0 */ + ld r1, #1 + ldx XCPT_R0_OFFS(rr2), r0 + ldx XCPT_R1_OFFS(rr2), r1 + + /* Setup to return zero for the no-context-switch case */ + + /* clr r0 */ + clr r1 + + /* Now decide if we need to re-enable interrupts or not */ + + tm r4, #%80 + jr z, _z8_noenable + ei +_z8_noenable: + ret + + end + diff --git a/arch/z80/src/z8/z8_schedulesigaction.c b/arch/z80/src/z8/z8_schedulesigaction.c index 1f1a354712cfcddd54eaf7c7a82079185a9a9dda..7a5f6661593d938194c5d3765c419d7bf4ed7cf0 100644 --- a/arch/z80/src/z8/z8_schedulesigaction.c +++ b/arch/z80/src/z8/z8_schedulesigaction.c @@ -2,7 +2,7 @@ * arch/z80/src/z8/z8_schedulesigaction.c * * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z8/z8_sigdeliver.c b/arch/z80/src/z8/z8_sigdeliver.c index c5cf30aa6a063ba035c4fcd1c0773922b5aff968..d1153a4978f15b675eda76eb00d253ffd7e9cd29 100644 --- a/arch/z80/src/z8/z8_sigdeliver.c +++ b/arch/z80/src/z8/z8_sigdeliver.c @@ -2,7 +2,7 @@ * arch/z80/src/z8/z8_sigdeliver.c * * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z8/z8_timerisr.c b/arch/z80/src/z8/z8_timerisr.c index a317cf3b9ccb65bb82265216d2f8b4d93dfa3444..0ed61e28362586f9df8717672f7a72b1842bd099 100644 --- a/arch/z80/src/z8/z8_timerisr.c +++ b/arch/z80/src/z8/z8_timerisr.c @@ -2,7 +2,7 @@ * arch/z80/src/z8/z8_timerisr.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z8/z8_vector.S b/arch/z80/src/z8/z8_vector.S index 2d1381dfffb17698965a12962193b544447739b9..18024152171cd01072346192e9dc897cf3284243 100755 --- a/arch/z80/src/z8/z8_vector.S +++ b/arch/z80/src/z8/z8_vector.S @@ -1,873 +1,873 @@ -/************************************************************************** - * arch/z80/src/z8/z8_xdef.S - * Interrupt Handling - * - * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS or IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER or CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, or CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS or SERVICES; LOSS - * OF USE, DATA, or PROFITS; or BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, or TORT (INCLUDING NEGLIGENCE or OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************/ - -/************************************************************************** - * Included Files - **************************************************************************/ - -#include -#include - -#include -#include - -/************************************************************************** - * Definitions - **************************************************************************/ - -/************************************************************************** - * External References / External Definitions - **************************************************************************/ - - xref _up_doirq:ROM - -#if defined(ENCORE_VECTORS) - xdef _z8_wdt_handler - xdef _z8_trap_handler -if EZ8_TIMER3=1 - xdef _z8_timer2_handler -endif - xdef _z8_timer1_handler - xdef _z8_timer0_handler -if EZ8_UART0=1 - xdef _z8_uart0rx_handler - xdef _z8_uart0tx_handler -endif -if EZ8_I2C=1 - xdef _z8_i2c_handler -endif -if EZ8_SPI=1 - xdef _z8_spi_handler -endif -if EZ8_ADC=1 - xdef _z8_adc_handler -endif - xdef _z8_p7ad_handler - xdef _z8_p6ad_handler - xdef _z8_p5ad_handler - xdef _z8_p4ad_handler - xdef _z8_p3ad_handler - xdef _z8_p2ad_handler - xdef _z8_p1ad_handler - xdef _z8_p0ad_handler -if EZ8_TIMER4=1 - xdef _z8_timer3_handler -endif -if EZ8_UART1=1 - xdef _z8_uart1rx_handler - xdef _z8_uart1tx_handler -endif -if EZ8_DMA=1 - xdef _z8_dma_handler -endif -if EZ8_PORT1=0 - xdef _z8_c3_handler - xdef _z8_c2_handler - xdef _z8_c1_handler - xdef _z8_c0_handler -endif - -/**************************************************************************/ - -#elif defined(ENCORE_XP_VECTORS) - - xdef _z8_wdt_handler - xdef _z8_trap_handler -if EZ8_TIMER3=1 - xdef _z8_timer2_handler -endif - xdef _z8_timer1_handler - xdef _z8_timer0_handler -if EZ8_UART0=1 - xdef _z8_uart0rx_handler - xdef _z8_uart0tx_handler -endif -if EZ8_I2C=1 - xdef _z8_i2c_handler -endif -if EZ8_SPI=1 - xdef _z8_spi_handler -endif -if (EZ8_ADC=1) || (EZ8_ADC_NEW=1) - xdef _z8_adc_handler -endif - xdef _z8_p7ad_handler - xdef _z8_p6ad_handler - xdef _z8_p5ad_handler - xdef _z8_p4ad_handler - xdef _z8_p3ad_handler - xdef _z8_p2ad_handler - xdef _z8_p1ad_handler - xdef _z8_p0ad_handler -if EZ8_TIMER4=1 - xdef _z8_timer3_handler -endif -if EZ8_UART1=1 - xdef _z8_uart1rx_handler - xdef _z8_uart1tx_handler -endif -if EZ8_DMA=1 - xdef _z8_dma_handler -endif -if (EZ8_PORT1=0) - xdef _z8_c3_handler - xdef _z8_c2_handler - xdef _z8_c1_handler - xdef _z8_c0_handler -endif - xdef _z8_potrap_handler - xdef _z8_wotrap_handler - -/**************************************************************************/ - -#elif defined(ENCORE_XP16K_VECTORS) - - xdef _z8_wdt_handler - xdef _z8_trap_handler -if EZ8_TIMER3=1 - xdef _z8_timer2_handler -endif - xdef _z8_timer1_handler - xdef _z8_timer0_handler -if EZ8_UART0=1 - xdef _z8_uart0rx_handler - xdef _z8_uart0tx_handler -endif -if EZ8_I2C=1 - xdef _z8_i2c_handler -endif -if EZ8_ESPI=1 - xdef _z8_spi_handler -endif -if EZ8_ADC_NEW=1 - xdef _z8_adc_handler -endif - xdef _z8_p7ad_handler - xdef _z8_p6ad_handler - xdef _z8_p5ad_handler - xdef _z8_p4ad_handler - xdef _z8_p3ad_handler - xdef _z8_p2ad_handler - xdef _z8_p1ad_handler - xdef _z8_p0ad_handler -if EZ8_MCT=1 - xdef _z8_mct_handler -endif -if EZ8_UART1=1 - xdef _z8_uart1rx_handler - xdef _z8_uart1tx_handler -endif - xdef _z8_c3_handler - xdef _z8_c2_handler - xdef _z8_c1_handler - xdef _z8_c0_handler - xdef _z8_potrap_handler - xdef _z8_wotrap_handler - -/**************************************************************************/ - -#elif defined(ENCORE_MC_VECTORS) - - xdef _z8_wdt_handler - xdef _z8_trap_handler - xdef _z8_pwmtimer_handler - xdef _z8_pwmfault_handler -if EZ8_ADC_NEW=1 - xdef _z8_adc_handler -endif - xdef _z8_cmp_handler - xdef _z8_timer0_handler -if EZ8_UART0 - xdef _z8_uart0rx_handler - xdef _z8_uart0tx_handler -endif -if EZ8_SPI=1 - xdef _z8_spi_handler -endif -if EZ8_I2C=1 - xdef _z8_i2c_handler -endif - xdef _z8_c0_handler - xdef _z8_pb_handler - xdef _z8_p7ap3a_handler - xdef _z8_p6ap2a_handler - xdef _z8_p5ap1a_handler - xdef _z8_p4ap0a_handler - xdef _z8_potrap_handler - xdef _z8_wotrap_handler -#endif - -/************************************************************************** - * Macros - **************************************************************************/ - -ENTER : MACRO val - pushx rp /* Save the current RP value in the stack */ - srp #%f0 /* Load the interrupt register pointer */ - ld r0, #val /* Pass the new value in r0 */ - jr _z8_common_handler /* The rest of the handling is common */ - ENDMAC ENTER - -LEAVE : MACRO - popx rp /* Restore the user register pointer */ - iret /* And return from interrupt */ - ENDMAC LEAVE - -/************************************************************************** - * Code - **************************************************************************/ - - segment CODE - -/************************************************************************** - * Interrupt Vectors - **************************************************************************/ - -#if defined(ENCORE_VECTORS) - vector WDT = _z8_wdt_handler - vector TRAP = _z8_trap_handler -if EZ8_TIMER3=1 - vector TIMER2 = _z8_timer2_handler -endif - vector TIMER1 = _z8_timer1_handler - vector TIMER0 = _z8_timer0_handler -if EZ8_UART0=1 - vector UART0_RX = _z8_uart0rx_handler - vector UART0_TX = _z8_uart0tx_handler -endif -if EZ8_I2C=1 - vector I2C = _z8_i2c_handler -endif -if EZ8_SPI=1 - vector SPI = _z8_spi_handler -endif -if EZ8_ADC=1 - vector ADC = _z8_adc_handler -endif - vector P7AD = _z8_p7ad_handler - vector P6AD = _z8_p6ad_handler - vector P5AD = _z8_p5ad_handler - vector P4AD = _z8_p4ad_handler - vector P3AD = _z8_p3ad_handler - vector P2AD = _z8_p2ad_handler - vector P1AD = _z8_p1ad_handler - vector P0AD = _z8_p0ad_handler -if EZ8_TIMER4=1 - vector TIMER3 = _z8_timer3_handler -endif -if EZ8_UART1=1 - vector UART1_RX = _z8_uart1rx_handler - vector UART1_TX = _z8_uart1tx_handler -endif -if EZ8_DMA=1 - vector DMA = _z8_dma_handler -endif -if EZ8_PORT1=0 - vector C3 = _z8_c3_handler - vector C2 = _z8_c2_handler - vector C1 = _z8_c1_handler - vector C0 = _z8_c0_handler -endif - -/**************************************************************************/ - -#elif defined(ENCORE_XP_VECTORS) - - vector WDT = _z8_wdt_handler - vector TRAP = _z8_trap_handler -if EZ8_TIMER3=1 - vector TIMER2 = _z8_timer2_handler -endif - vector TIMER1 = _z8_timer1_handler - vector TIMER0 = _z8_timer0_handler -if EZ8_UART0=1 - vector UART0_RX = _z8_uart0rx_handler - vector UART0_TX = _z8_uart0tx_handler -endif -if EZ8_I2C=1 - vector I2C = _z8_i2c_handler -endif -if EZ8_SPI=1 - vector SPI = _z8_spi_handler -endif -if (EZ8_ADC=1) || (EZ8_ADC_NEW=1) - vector ADC = _z8_adc_handler -endif - vector P7AD = _z8_p7ad_handler - vector P6AD = _z8_p6ad_handler - vector P5AD = _z8_p5ad_handler - vector P4AD = _z8_p4ad_handler - vector P3AD = _z8_p3ad_handler - vector P2AD = _z8_p2ad_handler - vector P1AD = _z8_p1ad_handler - vector P0AD = _z8_p0ad_handler -if EZ8_TIMER4=1 - vector TIMER3 = _z8_timer3_handler -endif -if EZ8_UART1=1 - vector UART1_RX = _z8_uart1rx_handler - vector UART1_TX = _z8_uart1tx_handler -endif -if EZ8_DMA=1 - vector DMA = _z8_dma_handler -endif -if EZ8_PORT1=0 - vector C3 = _z8_c3_handler - vector C2 = _z8_c2_handler - vector C1 = _z8_c1_handler - vector C0 = _z8_c0_handler -endif - vector POTRAP = _z8_potrap_handler - vector WOTRAP = _z8_wotrap_handler - -/**************************************************************************/ - -#elif defined(ENCORE_XP16K_VECTORS) - - vector WDT = _z8_wdt_handler - vector TRAP = _z8_trap_handler -if EZ8_TIMER3=1 - vector TIMER2 = _z8_timer2_handler -endif - vector TIMER1 = _z8_timer1_handler - vector TIMER0 = _z8_timer0_handler -if EZ8_UART0=1 - vector UART0_RX = _z8_uart0rx_handler - vector UART0_TX = _z8_uart0tx_handler -endif -if EZ8_I2C=1 - vector I2C = _z8_i2c_handler -endif -if EZ8_ESPI=1 - vector SPI = _z8_spi_handler -endif -if EZ8_ADC_NEW=1 - vector ADC = _z8_adc_handler -endif - vector P7AD = _z8_p7ad_handler - vector P6AD = _z8_p6ad_handler - vector P5AD = _z8_p5ad_handler - vector P4AD = _z8_p4ad_handler - vector P3AD = _z8_p3ad_handler - vector P2AD = _z8_p2ad_handler - vector P1AD = _z8_p1ad_handler - vector P0AD = _z8_p0ad_handler -if EZ8_MCT=1 - vector MCT = _z8_mct_handler -endif -if EZ8_UART1=1 - vector UART1_RX = _z8_uart1rx_handler - vector UART1_TX = _z8_uart1tx_handler -endif - vector C3 = _z8_c3_handler - vector C2 = _z8_c2_handler - vector C1 = _z8_c1_handler - vector C0 = _z8_c0_handler - vector POTRAP = _z8_potrap_handler - vector WOTRAP = _z8_wotrap_handler - -/**************************************************************************/ - -#elif defined(ENCORE_MC_VECTORS) - - vector WDT = _z8_wdt_handler - vector TRAP = _z8_trap_handler - vector PWMTIMER = _z8_pwmtimer_handler - vector PWMFAULT = _z8_pwmfault_handler -if EZ8_ADC_NEW=1 - vector ADC = _z8_adc_handler -endif - vector CMP = _z8_cmp_handler - vector TIMER0 = _z8_timer0_handler -if EZ8_UART0 - vector UART0_RX = _z8_uart0rx_handler - vector UART0_TX = _z8_uart0tx_handler -endif -if EZ8_SPI=1 - vector SPI = _z8_spi_handler -endif -if EZ8_I2C=1 - vector I2C = _z8_i2c_handler -endif - vector C0 = _z8_c0_handler - vector PB = _z8_pb_handler - vector P7A = _z8_p7ap3a_handler - vector P6A = _z8_p6ap2a_handler - vector P5A = _z8_p5ap1a_handler - vector P4A = _z8_p4ap0a_handler - vector POTRAP = _z8_potrap_handler - vector WOTRAP = _z8_wotrap_handler -#endif - -/************************************************************************** - * Name: _z16f_*_handler - * - * Description: - * Map individual interrupts into interrupt number and branch to common - * interrupt handling logic. If higher interrupt handling performance - * for particular interrupts is required, then those interrupts should - * be picked off here and handled outside of the common logic. - * - * On entry to any of these handlers, the stack contains the following: - * - * TOS before interrupt - * PC[7:0] - * PC[15:8] - * SP -> Flags Register - * - **************************************************************************/ - -#if defined(ENCORE_VECTORS) -_z8_wdt_handler: - ENTER(Z8_WDT_IRQ) -_z8_trap_handler: - ENTER(Z8_TRAP_IRQ) -if EZ8_TIMER3=1 -_z8_timer2_handler: - ENTER(Z8_TIMER2_IRQ) -endif -_z8_timer1_handler: - ENTER(Z8_TIMER1_IRQ) -_z8_timer0_handler: - ENTER(Z8_TIMER0_IRQ) -if EZ8_UART0=1 -_z8_uart0rx_handler: - ENTER(Z8_UART0_RX_IRQ) -_z8_uart0tx_handler: - ENTER(Z8_UART0_TX_IRQ) -endif -if EZ8_I2C=1 -_z8_i2c_handler: - ENTER(Z8_I2C_IRQ) -endif -if EZ8_SPI=1 -_z8_spi_handler: - ENTER(Z8_SPI_IRQ) -endif -if EZ8_ADC=1 -_z8_adc_handler: - ENTER(Z8_ADC_IRQ) -endif -_z8_p7ad_handler: - ENTER(Z8_P7AD_IRQ) -_z8_p6ad_handler: - ENTER(Z8_P6AD_IRQ) -_z8_p5ad_handler: - ENTER(Z8_P5AD_IRQ) -_z8_p4ad_handler: - ENTER(Z8_P4AD_IRQ) -_z8_p3ad_handler: - ENTER(Z8_P3AD_IRQ) -_z8_p2ad_handler: - ENTER(Z8_P2AD_IRQ) -_z8_p1ad_handler: - ENTER(Z8_P1AD_IRQ) -_z8_p0ad_handler: - ENTER(Z8_P0AD_IRQ) -if EZ8_TIMER4=1 -_z8_timer3_handler: - ENTER(Z8_TIMER3_IRQ) -endif -if EZ8_UART1=1 -_z8_uart1rx_handler: - ENTER(Z8_UART1_RX_IRQ) -_z8_uart1tx_handler: - ENTER(Z8_UART1_TX_IRQ) -endif -if EZ8_DMA=1 -_z8_dma_handler: - ENTER(Z8_DMA_IRQ) -endif -if EZ8_PORT1=0 -_z8_c3_handler: - ENTER(Z8_C3_IRQ) -_z8_c2_handler: - ENTER(Z8_C2_IRQ) -_z8_c1_handler: - ENTER(Z8_C1_IRQ) -_z8_c0_handler: - ENTER(Z8_C0_IRQ) -endif - -/**************************************************************************/ - -#elif defined(ENCORE_XP_VECTORS) - -_z8_wdt_handler: - ENTER(Z8_WDT_IRQ) -_z8_trap_handler: - ENTER(Z8_TRAP_IRQ) -if EZ8_TIMER3=1 -_z8_timer2_handler: - ENTER(Z8_TIMER2_IRQ) -endif -_z8_timer1_handler: - ENTER(Z8_TIMER1_IRQ) -_z8_timer0_handler: - ENTER(Z8_TIMER0_IRQ) -if EZ8_UART0=1 -_z8_uart0rx_handler: - ENTER(Z8_UART0_RX_IRQ) -_z8_uart0tx_handler: - ENTER(Z8_UART0_TX_IRQ) -endif -if EZ8_I2C=1 -_z8_i2c_handler: - ENTER(Z8_I2C_IRQ) -endif -if EZ8_SPI=1 -_z8_spi_handler: - ENTER(Z8_SPI_IRQ) -endif -if (EZ8_ADC=1) || (EZ8_ADC_NEW=1) -_z8_adc_handler: - ENTER(Z8_ADC_IRQ) -endif -_z8_p7ad_handler: - ENTER(Z8_P7AD_IRQ) -_z8_p6ad_handler: - ENTER(Z8_P6AD_IRQ) -_z8_p5ad_handler: - ENTER(Z8_P5AD_IRQ) -_z8_p4ad_handler: - ENTER(Z8_P4AD_IRQ) -_z8_p3ad_handler: - ENTER(Z8_P3AD_IRQ) -_z8_p2ad_handler: - ENTER(Z8_P2AD_IRQ) -_z8_p1ad_handler: - ENTER(Z8_P1AD_IRQ) -_z8_p0ad_handler: - ENTER(Z8_P0AD_IRQ) -if EZ8_TIMER4=1 -_z8_timer3_handler: - ENTER(Z8_TIMER3_IRQ) -endif -if EZ8_UART1=1 -_z8_uart1rx_handler: - ENTER(Z8_UART1_RX_IRQ) -_z8_uart1tx_handler: - ENTER(Z8_UART1_TX_IRQ) -endif -if EZ8_DMA=1 -_z8_dma_handler: - ENTER(Z8_DMA_IRQ) -endif -if EZ8_PORT1=0 -_z8_c3_handler: - ENTER(Z8_C3_IRQ) -_z8_c2_handler: - ENTER(Z8_C2_IRQ) -_z8_c1_handler: - ENTER(Z8_C1_IRQ) -_z8_c0_handler: - ENTER(Z8_C0_IRQ) -endif -_z8_potrap_handler: - ENTER(Z8_POTRAP_IRQ) -_z8_wotrap_handler: - ENTER(Z8_WOTRAP_IRQ) - -/**************************************************************************/ - -#elif defined(ENCORE_XP16K_VECTORS) - -_z8_wdt_handler: - ENTER(Z8_WDT_IRQ) -_z8_trap_handler: - ENTER(Z8_TRAP_IRQ) -if EZ8_TIMER3=1 -_z8_timer2_handler: - ENTER(Z8_TIMER2_IRQ) -endif -_z8_timer1_handler: - ENTER(Z8_TIMER1_IRQ) -_z8_timer0_handler: - ENTER(Z8_TIMER0_IRQ) -if EZ8_UART0=1 -_z8_uart0rx_handler: - ENTER(Z8_UART0_RX_IRQ) -_z8_uart0tx_handler: - ENTER(Z8_UART0_TX_IRQ) -endif -if EZ8_I2C=1 -_z8_i2c_handler: - ENTER(Z8_I2C_IRQ) -endif -if EZ8_ESPI=1 -_z8_spi_handler: - ENTER(Z8_SPI_IRQ) -endif -if EZ8_ADC_NEW=1 -_z8_adc_handler: - ENTER(Z8_ADC_IRQ) -endif -_z8_p7ad_handler: - ENTER(Z8_P7AD_IRQ) -_z8_p6ad_handler: - ENTER(Z8_P6AD_IRQ) -_z8_p5ad_handler: - ENTER(Z8_P5AD_IRQ) -_z8_p4ad_handler: - ENTER(Z8_P4AD_IRQ) -_z8_p3ad_handler: - ENTER(Z8_P3AD_IRQ) -_z8_p2ad_handler: - ENTER(Z8_P2AD_IRQ) -_z8_p1ad_handler: - ENTER(Z8_P1AD_IRQ) -_z8_p0ad_handler: - ENTER(Z8_P0AD_IRQ) -if EZ8_MCT=1 -_z8_mct_handler: - ENTER(Z8_MCT_IRQ) -endif -if EZ8_UART1=1 -_z8_uart1rx_handler: - ENTER(Z8_UART1_RX_IRQ) -_z8_uart1tx_handler: - ENTER(Z8_UART1_TX_IRQ) -endif -_z8_c3_handler: - ENTER(Z8_C3_IRQ) -_z8_c2_handler: - ENTER(Z8_C2_IRQ) -_z8_c1_handler: - ENTER(Z8_C1_IRQ) -_z8_c0_handler: - ENTER(Z8_C0_IRQ) -_z8_potrap_handler: - ENTER(Z8_POTRAP_IRQ) -_z8_wotrap_handler: - ENTER(Z8_WOTRAP_IRQ) - -/**************************************************************************/ - -#elif defined(ENCORE_MC_VECTORS) - -_z8_wdt_handler: - ENTER(Z8_WDT_IRQ) -_z8_trap_handler: - ENTER(Z8_TRAP_IRQ) -_z8_pwmtimer_handler: - ENTER(Z8_PWMTIMER_IRQ) -_z8_pwmfault_handler: - ENTER(Z8_PWMFAULT_IRQ) -if EZ8_ADC_NEW=1 -_z8_adc_handler: - ENTER(Z8_ADC_IRQ) -endif -_z8_cmp_handler: - ENTER(Z8_CMP_IRQ) -_z8_timer0_handler: - ENTER(Z8_TIMER0_IRQ) -if EZ8_UART0 -_z8_uart0rx_handler: - ENTER(Z8_UART0_RX_IRQ) -_z8_uart0tx_handler: - ENTER(Z8_UART0_TX_IRQ) -endif -if EZ8_SPI=1 -_z8_spi_handler: - ENTER(Z8_SPI_IRQ) -endif -if EZ8_I2C=1 -_z8_i2c_handler: - ENTER(Z8_I2C_IRQ) -endif -_z8_c0_handler: - ENTER(Z8_C0_IRQ) -_z8_pb_handler: - ENTER(Z8_PB_IRQ) -_z8_p7ap3a_handler: - ENTER(Z8_P7A_IRQ) -_z8_p6ap2a_handler: - ENTER(Z8_P6AP2A_IRQ) -_z8_p5ap1a_handler: - ENTER(Z8_P5AP1A_IRQ) -_z8_p4ap0a_handler: - ENTER(Z8_P4AP0A_IRQ) -_z8_potrap_handler: - ENTER(Z8_POTRAP_IRQ) -_z8_wotrap_handler: - ENTER(Z8_WOTRAP_IRQ) -#endif - -/************************************************************************** - * Name: _z16f_common_handler - * - * Description: - * Common IRQ handling logic - * - * On entry, the stack contains the following: - * - * TOS before interrupt - * PC[7:0] - * PC[15:8] - * Flags Register - * SP -> RP - * - * R0 holds the IRQ number and the RP has been reset to %f0 - * - **************************************************************************/ - -_z8_common_handler: - /* Pass the address of the IRQ stack frame */ - - ldx r2, sph /* rr2 = stack pointer */ - ldx r3, spl - push r3 /* Pass as a parameter */ - push r2 - - /* Pass the IRQ number */ - - push r0 - - /* Process the interrupt */ - - call _up_doirq /* Call the IRQ handler */ - - /* Release arguments from the stack */ - - pop r4 /* Discard the IRQ argument */ - pop r2 /* Recover the stack pointer parameter */ - pop r3 - - /* If a interrupt level context switch occurred, then the - * return value will be the same as the input value - */ - - cp r0, r2 /* Same as the return value? */ - jr nz, _z8_switch - cp r1, r3 - jr z, _z8_noswitch - - /* A context switch occurs. Restore the use context. - * rr0 = pointer to context structgure. - */ - -_z8_switch: - - /* Destroy the interrupt return information on the stack */ - - pop r4 /* Destroy saved RP */ - pop r4 /* Destroy saved flags */ - pop r4 /* Destroy saved return address */ - pop r4 - - /* Copy all registers into the user register area. */ - - clr r2 /* rr2 = destination address */ - ldx r3, XCPT_RP_OFFS(rr0) - ld r4, r0 /* rr4 = source address */ - ld r5, r1 - ld r6, #16 /* r6 = number of bytes to copy */ - -_z8_restore: - ldx r7, @rr4 - ldx @rr2, r7 - incw rr2 - incw rr4 - djnz r6, _z8_restore - - /* Set the new stack pointer */ - - ldx r2, XCPT_SPH_OFFS(rr0) - ldx r3, XCPT_SPL_OFFS(rr0) - ldx sph, r2 - ldx spl, r3 - - /* Push the return address onto the stack */ - - ldx r2, XCPT_PCH_OFFS(rr0) - ldx r3, XCPT_PCL_OFFS(rr0) - push r3 - push r2 - - /* Recover the flags and RP settings.. but don't restore them yet */ - - ldx r3, XCPT_FLAGS_OFFS(rr0) - ldx r4, XCPT_RP_OFFS(rr0) - - /* Determine whether interrupts must be enabled on return. This - * would be nicer to do below, but later we will need to preserve - * the condition codes in the flags. - */ - - ldx r2, XCPT_IRQCTL_OFFS(rr0) - tm r2, #%80 - jr nz, _z8_returnenabled - - /* Restore the flag settings */ - - ldx flags, r3 - - /* Restore the user register page and return with interrupts disabled. - * Note that we cannot use the iret instruction because it unconditionally - * re-enabled interrupts - */ - - ldx rp, r4 /* Does not effect flags */ - ret /* Does not effect flags */ - -_z8_returnenabled: - /* Restore the flag settings */ - - ldx flags, r1 - - /* Restore the user register page, re-enable interrupts and return. - * Note that we cannot use the iret instruction because it unconditionally - * re-enabled interrupts - */ - - ldx rp, r4 /* Does not effect flags */ - ei /* Does not effect flags */ - ret /* Does not effect flags */ - -_z8_noswitch: - LEAVE - -/************************************************************************** - * Data - **************************************************************************/ - - /* Set aside area for interrupt registers */ - - define interruptreg, space=rdata, org=%f0 - segment interruptreg - ds %10 - - end _z8_common_handler +/************************************************************************** + * arch/z80/src/z8/z8_xdef.S + * Interrupt Handling + * + * Copyright (C) 2008 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS or IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER or CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, or CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS or SERVICES; LOSS + * OF USE, DATA, or PROFITS; or BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, or TORT (INCLUDING NEGLIGENCE or OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************/ + +/************************************************************************** + * Included Files + **************************************************************************/ + +#include +#include + +#include +#include + +/************************************************************************** + * Definitions + **************************************************************************/ + +/************************************************************************** + * External References / External Definitions + **************************************************************************/ + + xref _up_doirq:ROM + +#if defined(ENCORE_VECTORS) + xdef _z8_wdt_handler + xdef _z8_trap_handler +if EZ8_TIMER3=1 + xdef _z8_timer2_handler +endif + xdef _z8_timer1_handler + xdef _z8_timer0_handler +if EZ8_UART0=1 + xdef _z8_uart0rx_handler + xdef _z8_uart0tx_handler +endif +if EZ8_I2C=1 + xdef _z8_i2c_handler +endif +if EZ8_SPI=1 + xdef _z8_spi_handler +endif +if EZ8_ADC=1 + xdef _z8_adc_handler +endif + xdef _z8_p7ad_handler + xdef _z8_p6ad_handler + xdef _z8_p5ad_handler + xdef _z8_p4ad_handler + xdef _z8_p3ad_handler + xdef _z8_p2ad_handler + xdef _z8_p1ad_handler + xdef _z8_p0ad_handler +if EZ8_TIMER4=1 + xdef _z8_timer3_handler +endif +if EZ8_UART1=1 + xdef _z8_uart1rx_handler + xdef _z8_uart1tx_handler +endif +if EZ8_DMA=1 + xdef _z8_dma_handler +endif +if EZ8_PORT1=0 + xdef _z8_c3_handler + xdef _z8_c2_handler + xdef _z8_c1_handler + xdef _z8_c0_handler +endif + +/**************************************************************************/ + +#elif defined(ENCORE_XP_VECTORS) + + xdef _z8_wdt_handler + xdef _z8_trap_handler +if EZ8_TIMER3=1 + xdef _z8_timer2_handler +endif + xdef _z8_timer1_handler + xdef _z8_timer0_handler +if EZ8_UART0=1 + xdef _z8_uart0rx_handler + xdef _z8_uart0tx_handler +endif +if EZ8_I2C=1 + xdef _z8_i2c_handler +endif +if EZ8_SPI=1 + xdef _z8_spi_handler +endif +if (EZ8_ADC=1) || (EZ8_ADC_NEW=1) + xdef _z8_adc_handler +endif + xdef _z8_p7ad_handler + xdef _z8_p6ad_handler + xdef _z8_p5ad_handler + xdef _z8_p4ad_handler + xdef _z8_p3ad_handler + xdef _z8_p2ad_handler + xdef _z8_p1ad_handler + xdef _z8_p0ad_handler +if EZ8_TIMER4=1 + xdef _z8_timer3_handler +endif +if EZ8_UART1=1 + xdef _z8_uart1rx_handler + xdef _z8_uart1tx_handler +endif +if EZ8_DMA=1 + xdef _z8_dma_handler +endif +if (EZ8_PORT1=0) + xdef _z8_c3_handler + xdef _z8_c2_handler + xdef _z8_c1_handler + xdef _z8_c0_handler +endif + xdef _z8_potrap_handler + xdef _z8_wotrap_handler + +/**************************************************************************/ + +#elif defined(ENCORE_XP16K_VECTORS) + + xdef _z8_wdt_handler + xdef _z8_trap_handler +if EZ8_TIMER3=1 + xdef _z8_timer2_handler +endif + xdef _z8_timer1_handler + xdef _z8_timer0_handler +if EZ8_UART0=1 + xdef _z8_uart0rx_handler + xdef _z8_uart0tx_handler +endif +if EZ8_I2C=1 + xdef _z8_i2c_handler +endif +if EZ8_ESPI=1 + xdef _z8_spi_handler +endif +if EZ8_ADC_NEW=1 + xdef _z8_adc_handler +endif + xdef _z8_p7ad_handler + xdef _z8_p6ad_handler + xdef _z8_p5ad_handler + xdef _z8_p4ad_handler + xdef _z8_p3ad_handler + xdef _z8_p2ad_handler + xdef _z8_p1ad_handler + xdef _z8_p0ad_handler +if EZ8_MCT=1 + xdef _z8_mct_handler +endif +if EZ8_UART1=1 + xdef _z8_uart1rx_handler + xdef _z8_uart1tx_handler +endif + xdef _z8_c3_handler + xdef _z8_c2_handler + xdef _z8_c1_handler + xdef _z8_c0_handler + xdef _z8_potrap_handler + xdef _z8_wotrap_handler + +/**************************************************************************/ + +#elif defined(ENCORE_MC_VECTORS) + + xdef _z8_wdt_handler + xdef _z8_trap_handler + xdef _z8_pwmtimer_handler + xdef _z8_pwmfault_handler +if EZ8_ADC_NEW=1 + xdef _z8_adc_handler +endif + xdef _z8_cmp_handler + xdef _z8_timer0_handler +if EZ8_UART0 + xdef _z8_uart0rx_handler + xdef _z8_uart0tx_handler +endif +if EZ8_SPI=1 + xdef _z8_spi_handler +endif +if EZ8_I2C=1 + xdef _z8_i2c_handler +endif + xdef _z8_c0_handler + xdef _z8_pb_handler + xdef _z8_p7ap3a_handler + xdef _z8_p6ap2a_handler + xdef _z8_p5ap1a_handler + xdef _z8_p4ap0a_handler + xdef _z8_potrap_handler + xdef _z8_wotrap_handler +#endif + +/************************************************************************** + * Macros + **************************************************************************/ + +ENTER : MACRO val + pushx rp /* Save the current RP value in the stack */ + srp #%f0 /* Load the interrupt register pointer */ + ld r0, #val /* Pass the new value in r0 */ + jr _z8_common_handler /* The rest of the handling is common */ + ENDMAC ENTER + +LEAVE : MACRO + popx rp /* Restore the user register pointer */ + iret /* And return from interrupt */ + ENDMAC LEAVE + +/************************************************************************** + * Code + **************************************************************************/ + + segment CODE + +/************************************************************************** + * Interrupt Vectors + **************************************************************************/ + +#if defined(ENCORE_VECTORS) + vector WDT = _z8_wdt_handler + vector TRAP = _z8_trap_handler +if EZ8_TIMER3=1 + vector TIMER2 = _z8_timer2_handler +endif + vector TIMER1 = _z8_timer1_handler + vector TIMER0 = _z8_timer0_handler +if EZ8_UART0=1 + vector UART0_RX = _z8_uart0rx_handler + vector UART0_TX = _z8_uart0tx_handler +endif +if EZ8_I2C=1 + vector I2C = _z8_i2c_handler +endif +if EZ8_SPI=1 + vector SPI = _z8_spi_handler +endif +if EZ8_ADC=1 + vector ADC = _z8_adc_handler +endif + vector P7AD = _z8_p7ad_handler + vector P6AD = _z8_p6ad_handler + vector P5AD = _z8_p5ad_handler + vector P4AD = _z8_p4ad_handler + vector P3AD = _z8_p3ad_handler + vector P2AD = _z8_p2ad_handler + vector P1AD = _z8_p1ad_handler + vector P0AD = _z8_p0ad_handler +if EZ8_TIMER4=1 + vector TIMER3 = _z8_timer3_handler +endif +if EZ8_UART1=1 + vector UART1_RX = _z8_uart1rx_handler + vector UART1_TX = _z8_uart1tx_handler +endif +if EZ8_DMA=1 + vector DMA = _z8_dma_handler +endif +if EZ8_PORT1=0 + vector C3 = _z8_c3_handler + vector C2 = _z8_c2_handler + vector C1 = _z8_c1_handler + vector C0 = _z8_c0_handler +endif + +/**************************************************************************/ + +#elif defined(ENCORE_XP_VECTORS) + + vector WDT = _z8_wdt_handler + vector TRAP = _z8_trap_handler +if EZ8_TIMER3=1 + vector TIMER2 = _z8_timer2_handler +endif + vector TIMER1 = _z8_timer1_handler + vector TIMER0 = _z8_timer0_handler +if EZ8_UART0=1 + vector UART0_RX = _z8_uart0rx_handler + vector UART0_TX = _z8_uart0tx_handler +endif +if EZ8_I2C=1 + vector I2C = _z8_i2c_handler +endif +if EZ8_SPI=1 + vector SPI = _z8_spi_handler +endif +if (EZ8_ADC=1) || (EZ8_ADC_NEW=1) + vector ADC = _z8_adc_handler +endif + vector P7AD = _z8_p7ad_handler + vector P6AD = _z8_p6ad_handler + vector P5AD = _z8_p5ad_handler + vector P4AD = _z8_p4ad_handler + vector P3AD = _z8_p3ad_handler + vector P2AD = _z8_p2ad_handler + vector P1AD = _z8_p1ad_handler + vector P0AD = _z8_p0ad_handler +if EZ8_TIMER4=1 + vector TIMER3 = _z8_timer3_handler +endif +if EZ8_UART1=1 + vector UART1_RX = _z8_uart1rx_handler + vector UART1_TX = _z8_uart1tx_handler +endif +if EZ8_DMA=1 + vector DMA = _z8_dma_handler +endif +if EZ8_PORT1=0 + vector C3 = _z8_c3_handler + vector C2 = _z8_c2_handler + vector C1 = _z8_c1_handler + vector C0 = _z8_c0_handler +endif + vector POTRAP = _z8_potrap_handler + vector WOTRAP = _z8_wotrap_handler + +/**************************************************************************/ + +#elif defined(ENCORE_XP16K_VECTORS) + + vector WDT = _z8_wdt_handler + vector TRAP = _z8_trap_handler +if EZ8_TIMER3=1 + vector TIMER2 = _z8_timer2_handler +endif + vector TIMER1 = _z8_timer1_handler + vector TIMER0 = _z8_timer0_handler +if EZ8_UART0=1 + vector UART0_RX = _z8_uart0rx_handler + vector UART0_TX = _z8_uart0tx_handler +endif +if EZ8_I2C=1 + vector I2C = _z8_i2c_handler +endif +if EZ8_ESPI=1 + vector SPI = _z8_spi_handler +endif +if EZ8_ADC_NEW=1 + vector ADC = _z8_adc_handler +endif + vector P7AD = _z8_p7ad_handler + vector P6AD = _z8_p6ad_handler + vector P5AD = _z8_p5ad_handler + vector P4AD = _z8_p4ad_handler + vector P3AD = _z8_p3ad_handler + vector P2AD = _z8_p2ad_handler + vector P1AD = _z8_p1ad_handler + vector P0AD = _z8_p0ad_handler +if EZ8_MCT=1 + vector MCT = _z8_mct_handler +endif +if EZ8_UART1=1 + vector UART1_RX = _z8_uart1rx_handler + vector UART1_TX = _z8_uart1tx_handler +endif + vector C3 = _z8_c3_handler + vector C2 = _z8_c2_handler + vector C1 = _z8_c1_handler + vector C0 = _z8_c0_handler + vector POTRAP = _z8_potrap_handler + vector WOTRAP = _z8_wotrap_handler + +/**************************************************************************/ + +#elif defined(ENCORE_MC_VECTORS) + + vector WDT = _z8_wdt_handler + vector TRAP = _z8_trap_handler + vector PWMTIMER = _z8_pwmtimer_handler + vector PWMFAULT = _z8_pwmfault_handler +if EZ8_ADC_NEW=1 + vector ADC = _z8_adc_handler +endif + vector CMP = _z8_cmp_handler + vector TIMER0 = _z8_timer0_handler +if EZ8_UART0 + vector UART0_RX = _z8_uart0rx_handler + vector UART0_TX = _z8_uart0tx_handler +endif +if EZ8_SPI=1 + vector SPI = _z8_spi_handler +endif +if EZ8_I2C=1 + vector I2C = _z8_i2c_handler +endif + vector C0 = _z8_c0_handler + vector PB = _z8_pb_handler + vector P7A = _z8_p7ap3a_handler + vector P6A = _z8_p6ap2a_handler + vector P5A = _z8_p5ap1a_handler + vector P4A = _z8_p4ap0a_handler + vector POTRAP = _z8_potrap_handler + vector WOTRAP = _z8_wotrap_handler +#endif + +/************************************************************************** + * Name: _z16f_*_handler + * + * Description: + * Map individual interrupts into interrupt number and branch to common + * interrupt handling logic. If higher interrupt handling performance + * for particular interrupts is required, then those interrupts should + * be picked off here and handled outside of the common logic. + * + * On entry to any of these handlers, the stack contains the following: + * + * TOS before interrupt + * PC[7:0] + * PC[15:8] + * SP -> Flags Register + * + **************************************************************************/ + +#if defined(ENCORE_VECTORS) +_z8_wdt_handler: + ENTER(Z8_WDT_IRQ) +_z8_trap_handler: + ENTER(Z8_TRAP_IRQ) +if EZ8_TIMER3=1 +_z8_timer2_handler: + ENTER(Z8_TIMER2_IRQ) +endif +_z8_timer1_handler: + ENTER(Z8_TIMER1_IRQ) +_z8_timer0_handler: + ENTER(Z8_TIMER0_IRQ) +if EZ8_UART0=1 +_z8_uart0rx_handler: + ENTER(Z8_UART0_RX_IRQ) +_z8_uart0tx_handler: + ENTER(Z8_UART0_TX_IRQ) +endif +if EZ8_I2C=1 +_z8_i2c_handler: + ENTER(Z8_I2C_IRQ) +endif +if EZ8_SPI=1 +_z8_spi_handler: + ENTER(Z8_SPI_IRQ) +endif +if EZ8_ADC=1 +_z8_adc_handler: + ENTER(Z8_ADC_IRQ) +endif +_z8_p7ad_handler: + ENTER(Z8_P7AD_IRQ) +_z8_p6ad_handler: + ENTER(Z8_P6AD_IRQ) +_z8_p5ad_handler: + ENTER(Z8_P5AD_IRQ) +_z8_p4ad_handler: + ENTER(Z8_P4AD_IRQ) +_z8_p3ad_handler: + ENTER(Z8_P3AD_IRQ) +_z8_p2ad_handler: + ENTER(Z8_P2AD_IRQ) +_z8_p1ad_handler: + ENTER(Z8_P1AD_IRQ) +_z8_p0ad_handler: + ENTER(Z8_P0AD_IRQ) +if EZ8_TIMER4=1 +_z8_timer3_handler: + ENTER(Z8_TIMER3_IRQ) +endif +if EZ8_UART1=1 +_z8_uart1rx_handler: + ENTER(Z8_UART1_RX_IRQ) +_z8_uart1tx_handler: + ENTER(Z8_UART1_TX_IRQ) +endif +if EZ8_DMA=1 +_z8_dma_handler: + ENTER(Z8_DMA_IRQ) +endif +if EZ8_PORT1=0 +_z8_c3_handler: + ENTER(Z8_C3_IRQ) +_z8_c2_handler: + ENTER(Z8_C2_IRQ) +_z8_c1_handler: + ENTER(Z8_C1_IRQ) +_z8_c0_handler: + ENTER(Z8_C0_IRQ) +endif + +/**************************************************************************/ + +#elif defined(ENCORE_XP_VECTORS) + +_z8_wdt_handler: + ENTER(Z8_WDT_IRQ) +_z8_trap_handler: + ENTER(Z8_TRAP_IRQ) +if EZ8_TIMER3=1 +_z8_timer2_handler: + ENTER(Z8_TIMER2_IRQ) +endif +_z8_timer1_handler: + ENTER(Z8_TIMER1_IRQ) +_z8_timer0_handler: + ENTER(Z8_TIMER0_IRQ) +if EZ8_UART0=1 +_z8_uart0rx_handler: + ENTER(Z8_UART0_RX_IRQ) +_z8_uart0tx_handler: + ENTER(Z8_UART0_TX_IRQ) +endif +if EZ8_I2C=1 +_z8_i2c_handler: + ENTER(Z8_I2C_IRQ) +endif +if EZ8_SPI=1 +_z8_spi_handler: + ENTER(Z8_SPI_IRQ) +endif +if (EZ8_ADC=1) || (EZ8_ADC_NEW=1) +_z8_adc_handler: + ENTER(Z8_ADC_IRQ) +endif +_z8_p7ad_handler: + ENTER(Z8_P7AD_IRQ) +_z8_p6ad_handler: + ENTER(Z8_P6AD_IRQ) +_z8_p5ad_handler: + ENTER(Z8_P5AD_IRQ) +_z8_p4ad_handler: + ENTER(Z8_P4AD_IRQ) +_z8_p3ad_handler: + ENTER(Z8_P3AD_IRQ) +_z8_p2ad_handler: + ENTER(Z8_P2AD_IRQ) +_z8_p1ad_handler: + ENTER(Z8_P1AD_IRQ) +_z8_p0ad_handler: + ENTER(Z8_P0AD_IRQ) +if EZ8_TIMER4=1 +_z8_timer3_handler: + ENTER(Z8_TIMER3_IRQ) +endif +if EZ8_UART1=1 +_z8_uart1rx_handler: + ENTER(Z8_UART1_RX_IRQ) +_z8_uart1tx_handler: + ENTER(Z8_UART1_TX_IRQ) +endif +if EZ8_DMA=1 +_z8_dma_handler: + ENTER(Z8_DMA_IRQ) +endif +if EZ8_PORT1=0 +_z8_c3_handler: + ENTER(Z8_C3_IRQ) +_z8_c2_handler: + ENTER(Z8_C2_IRQ) +_z8_c1_handler: + ENTER(Z8_C1_IRQ) +_z8_c0_handler: + ENTER(Z8_C0_IRQ) +endif +_z8_potrap_handler: + ENTER(Z8_POTRAP_IRQ) +_z8_wotrap_handler: + ENTER(Z8_WOTRAP_IRQ) + +/**************************************************************************/ + +#elif defined(ENCORE_XP16K_VECTORS) + +_z8_wdt_handler: + ENTER(Z8_WDT_IRQ) +_z8_trap_handler: + ENTER(Z8_TRAP_IRQ) +if EZ8_TIMER3=1 +_z8_timer2_handler: + ENTER(Z8_TIMER2_IRQ) +endif +_z8_timer1_handler: + ENTER(Z8_TIMER1_IRQ) +_z8_timer0_handler: + ENTER(Z8_TIMER0_IRQ) +if EZ8_UART0=1 +_z8_uart0rx_handler: + ENTER(Z8_UART0_RX_IRQ) +_z8_uart0tx_handler: + ENTER(Z8_UART0_TX_IRQ) +endif +if EZ8_I2C=1 +_z8_i2c_handler: + ENTER(Z8_I2C_IRQ) +endif +if EZ8_ESPI=1 +_z8_spi_handler: + ENTER(Z8_SPI_IRQ) +endif +if EZ8_ADC_NEW=1 +_z8_adc_handler: + ENTER(Z8_ADC_IRQ) +endif +_z8_p7ad_handler: + ENTER(Z8_P7AD_IRQ) +_z8_p6ad_handler: + ENTER(Z8_P6AD_IRQ) +_z8_p5ad_handler: + ENTER(Z8_P5AD_IRQ) +_z8_p4ad_handler: + ENTER(Z8_P4AD_IRQ) +_z8_p3ad_handler: + ENTER(Z8_P3AD_IRQ) +_z8_p2ad_handler: + ENTER(Z8_P2AD_IRQ) +_z8_p1ad_handler: + ENTER(Z8_P1AD_IRQ) +_z8_p0ad_handler: + ENTER(Z8_P0AD_IRQ) +if EZ8_MCT=1 +_z8_mct_handler: + ENTER(Z8_MCT_IRQ) +endif +if EZ8_UART1=1 +_z8_uart1rx_handler: + ENTER(Z8_UART1_RX_IRQ) +_z8_uart1tx_handler: + ENTER(Z8_UART1_TX_IRQ) +endif +_z8_c3_handler: + ENTER(Z8_C3_IRQ) +_z8_c2_handler: + ENTER(Z8_C2_IRQ) +_z8_c1_handler: + ENTER(Z8_C1_IRQ) +_z8_c0_handler: + ENTER(Z8_C0_IRQ) +_z8_potrap_handler: + ENTER(Z8_POTRAP_IRQ) +_z8_wotrap_handler: + ENTER(Z8_WOTRAP_IRQ) + +/**************************************************************************/ + +#elif defined(ENCORE_MC_VECTORS) + +_z8_wdt_handler: + ENTER(Z8_WDT_IRQ) +_z8_trap_handler: + ENTER(Z8_TRAP_IRQ) +_z8_pwmtimer_handler: + ENTER(Z8_PWMTIMER_IRQ) +_z8_pwmfault_handler: + ENTER(Z8_PWMFAULT_IRQ) +if EZ8_ADC_NEW=1 +_z8_adc_handler: + ENTER(Z8_ADC_IRQ) +endif +_z8_cmp_handler: + ENTER(Z8_CMP_IRQ) +_z8_timer0_handler: + ENTER(Z8_TIMER0_IRQ) +if EZ8_UART0 +_z8_uart0rx_handler: + ENTER(Z8_UART0_RX_IRQ) +_z8_uart0tx_handler: + ENTER(Z8_UART0_TX_IRQ) +endif +if EZ8_SPI=1 +_z8_spi_handler: + ENTER(Z8_SPI_IRQ) +endif +if EZ8_I2C=1 +_z8_i2c_handler: + ENTER(Z8_I2C_IRQ) +endif +_z8_c0_handler: + ENTER(Z8_C0_IRQ) +_z8_pb_handler: + ENTER(Z8_PB_IRQ) +_z8_p7ap3a_handler: + ENTER(Z8_P7A_IRQ) +_z8_p6ap2a_handler: + ENTER(Z8_P6AP2A_IRQ) +_z8_p5ap1a_handler: + ENTER(Z8_P5AP1A_IRQ) +_z8_p4ap0a_handler: + ENTER(Z8_P4AP0A_IRQ) +_z8_potrap_handler: + ENTER(Z8_POTRAP_IRQ) +_z8_wotrap_handler: + ENTER(Z8_WOTRAP_IRQ) +#endif + +/************************************************************************** + * Name: _z16f_common_handler + * + * Description: + * Common IRQ handling logic + * + * On entry, the stack contains the following: + * + * TOS before interrupt + * PC[7:0] + * PC[15:8] + * Flags Register + * SP -> RP + * + * R0 holds the IRQ number and the RP has been reset to %f0 + * + **************************************************************************/ + +_z8_common_handler: + /* Pass the address of the IRQ stack frame */ + + ldx r2, sph /* rr2 = stack pointer */ + ldx r3, spl + push r3 /* Pass as a parameter */ + push r2 + + /* Pass the IRQ number */ + + push r0 + + /* Process the interrupt */ + + call _up_doirq /* Call the IRQ handler */ + + /* Release arguments from the stack */ + + pop r4 /* Discard the IRQ argument */ + pop r2 /* Recover the stack pointer parameter */ + pop r3 + + /* If a interrupt level context switch occurred, then the + * return value will be the same as the input value + */ + + cp r0, r2 /* Same as the return value? */ + jr nz, _z8_switch + cp r1, r3 + jr z, _z8_noswitch + + /* A context switch occurs. Restore the use context. + * rr0 = pointer to context structgure. + */ + +_z8_switch: + + /* Destroy the interrupt return information on the stack */ + + pop r4 /* Destroy saved RP */ + pop r4 /* Destroy saved flags */ + pop r4 /* Destroy saved return address */ + pop r4 + + /* Copy all registers into the user register area. */ + + clr r2 /* rr2 = destination address */ + ldx r3, XCPT_RP_OFFS(rr0) + ld r4, r0 /* rr4 = source address */ + ld r5, r1 + ld r6, #16 /* r6 = number of bytes to copy */ + +_z8_restore: + ldx r7, @rr4 + ldx @rr2, r7 + incw rr2 + incw rr4 + djnz r6, _z8_restore + + /* Set the new stack pointer */ + + ldx r2, XCPT_SPH_OFFS(rr0) + ldx r3, XCPT_SPL_OFFS(rr0) + ldx sph, r2 + ldx spl, r3 + + /* Push the return address onto the stack */ + + ldx r2, XCPT_PCH_OFFS(rr0) + ldx r3, XCPT_PCL_OFFS(rr0) + push r3 + push r2 + + /* Recover the flags and RP settings.. but don't restore them yet */ + + ldx r3, XCPT_FLAGS_OFFS(rr0) + ldx r4, XCPT_RP_OFFS(rr0) + + /* Determine whether interrupts must be enabled on return. This + * would be nicer to do below, but later we will need to preserve + * the condition codes in the flags. + */ + + ldx r2, XCPT_IRQCTL_OFFS(rr0) + tm r2, #%80 + jr nz, _z8_returnenabled + + /* Restore the flag settings */ + + ldx flags, r3 + + /* Restore the user register page and return with interrupts disabled. + * Note that we cannot use the iret instruction because it unconditionally + * re-enabled interrupts + */ + + ldx rp, r4 /* Does not effect flags */ + ret /* Does not effect flags */ + +_z8_returnenabled: + /* Restore the flag settings */ + + ldx flags, r1 + + /* Restore the user register page, re-enable interrupts and return. + * Note that we cannot use the iret instruction because it unconditionally + * re-enabled interrupts + */ + + ldx rp, r4 /* Does not effect flags */ + ei /* Does not effect flags */ + ret /* Does not effect flags */ + +_z8_noswitch: + LEAVE + +/************************************************************************** + * Data + **************************************************************************/ + + /* Set aside area for interrupt registers */ + + define interruptreg, space=rdata, org=%f0 + segment interruptreg + ds %10 + + end _z8_common_handler diff --git a/arch/z80/src/z80/Make.defs b/arch/z80/src/z80/Make.defs index 01564f059a88e32ded6b59d36c6ba72232fc1ee8..4f8c291c40a58b1114789b79b7d2d709b72eadc3 100644 --- a/arch/z80/src/z80/Make.defs +++ b/arch/z80/src/z80/Make.defs @@ -2,7 +2,7 @@ # arch/z80/src/z80/Make.defs # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z80/chip.h b/arch/z80/src/z80/chip.h index 5874f733b03d6362f6304cb1ba17d3591bd26046..e80b2b231baae4399ae859ee5988a14d26124a41 100644 --- a/arch/z80/src/z80/chip.h +++ b/arch/z80/src/z80/chip.h @@ -3,7 +3,7 @@ * chip/chip.h * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z80/switch.h b/arch/z80/src/z80/switch.h index 1b54ada5eedbacca58dcfce8a813d36769f3ac1c..e7f705cfda26549010eba5fe4b255b29e2ab6ee3 100644 --- a/arch/z80/src/z80/switch.h +++ b/arch/z80/src/z80/switch.h @@ -3,7 +3,7 @@ * arch/z80/src/chip/switch.h * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z80/z80_copystate.c b/arch/z80/src/z80/z80_copystate.c index b49196f93e25bbbab153748d42794e5b41f1b9b4..ca2286a2bdab81201de0c9224296eec5e1ef7295 100644 --- a/arch/z80/src/z80/z80_copystate.c +++ b/arch/z80/src/z80/z80_copystate.c @@ -2,7 +2,7 @@ * arch/z80/src/z80/z80_copystate.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z80/z80_head.asm b/arch/z80/src/z80/z80_head.asm index 0eb166af646dc37395f6a151569b08a22c2bcb4d..828a29d7766f8f5a4113354528d5352407ff1cd4 100644 --- a/arch/z80/src/z80/z80_head.asm +++ b/arch/z80/src/z80/z80_head.asm @@ -1,283 +1,283 @@ -;************************************************************************** -; arch/z80/src/z80/z80_head.asm -; -; Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. -; Author: Gregory Nutt -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions -; are met: -; -; 1. Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in -; the documentation and/or other materials provided with the -; distribution. -; 3. Neither the name NuttX nor the names of its contributors may be -; used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; -;************************************************************************** - - .title NuttX for the Z80 - .module z80_head - -;************************************************************************** -; Constants -;************************************************************************** - - ; Register save area layout - - XCPT_I == 0 ; Offset 0: Saved I w/interrupt state in carry - XCPT_BC == 2 ; Offset 1: Saved BC register - XCPT_DE == 4 ; Offset 2: Saved DE register - XCPT_IX == 6 ; Offset 3: Saved IX register - XCPT_IY == 8 ; Offset 4: Saved IY register - XCPT_SP == 10 ; Offset 5: Offset to SP at time of interrupt - XCPT_HL == 12 ; Offset 6: Saved HL register - XCPT_AF == 14 ; Offset 7: Saved AF register - XCPT_PC == 16 ; Offset 8: Offset to PC at time of interrupt - - ; Default stack base (needs to be fixed) - - .include "asm_mem.h" - -;************************************************************************** -; Global symbols used -;************************************************************************** - - .globl _os_start ; OS entry point - .globl _up_doirq ; Interrupt decoding logic - -;************************************************************************** -; Reset entry point -;************************************************************************** - - .area _HEADER (ABS) - .org 0x0000 - - di ; Disable interrupts - im 1 ; Set interrupt mode 1 - jr _up_reset ; And boot the system - -;************************************************************************** -; Other reset handlers -; -; Interrupt mode 1 behavior: -; -; 1. M1 cycle: 7 ticks -; Acknowledge interrupt and decrements SP -; 2. M2 cycle: 3 ticks -; Writes the MS byte of the PC onto the stack and decrements SP -; 3. M3 cycle: 3 ticks -; Writes the LS byte of the PC onto the stack and sets the PC to 0x0038. -; -;************************************************************************** - - .org 0x0008 ; RST 1 - - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #1 ; 1 = Z80_RST1 - jr _up_rstcommon ; Remaining RST handling is common - - .org 0x0010 ; RST 2 - - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #2 ; 2 = Z80_RST2 - jr _up_rstcommon ; Remaining RST handling is common - - .org 0x0018 ; RST 3 - - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #3 ; 1 = Z80_RST3 - jr _up_rstcommon ; Remaining RST handling is common - - .org 0x0020 ; RST 4 - - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #4 ; 1 = Z80_RST4 - jr _up_rstcommon ; Remaining RST handling is common - - .org 0x0028 ; RST 5 - - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #5 ; 1 = Z80_RST5 - jr _up_rstcommon ; Remaining RST handling is common - - .org 0x0030 ; RST 6 - - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #6 ; 1 = Z80_RST6 - jr _up_rstcommon ; Remaining RST handling is common - - .org 0x0038 ; Int mode 1 / RST 7 - - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #7 ; 7 = Z80_RST7 - jr _up_rstcommon ; Remaining RST handling is common - -;************************************************************************** -; NMI interrupt handler -;************************************************************************** - - .org 0x0066 - retn - -;************************************************************************** -; System start logic -;************************************************************************** - -_up_reset: - ; Set up the stack pointer at the location determined the Makefile - ; and stored in asm_mem.h - - ld SP, #CONFIG_STACK_END ; Set stack pointer - - ; Performed initialization unique to the SDCC toolchain - - call gsinit ; Initialize the data section - - ; Then start NuttX - - call _os_start ; jump to the OS entry point - - ; NuttX will never return, but just in case... - -_up_halt:: - halt ; We should never get here - jp _up_halt - -;************************************************************************** -; Common Interrupt handler -;************************************************************************** - -_up_rstcommon:: - ; Create a register frame. SP points to top of frame + 4, pushes - ; decrement the stack pointer. Already have - ; - ; Offset 8: Return PC is already on the stack - ; Offset 7: AF (retaining flags) - ; - ; IRQ number is in A - - push hl ; Offset 6: HL - ld hl, #(3*2) ; HL is the value of the stack pointer before - add hl, sp ; the interrupt occurred - push hl ; Offset 5: Stack pointer - push iy ; Offset 4: IY - push ix ; Offset 3: IX - push de ; Offset 2: DE - push bc ; Offset 1: BC - - ld b, a ; Save the reset number in B - ld a, i ; Parity bit holds interrupt state - push af ; Offset 0: I with interrupt state in parity - di - - ; Call the interrupt decode logic. SP points to the beggining of the reg structure - - ld hl, #0 ; Argument #2 is the beginning of the reg structure - add hl, sp ; - push hl ; Place argument #2 at the top of stack - push bc ; Argument #1 is the Reset number - inc sp ; (make byte sized) - call _up_doirq ; Decode the IRQ - - ; On return, HL points to the beginning of the reg structure to restore - ; Note that (1) the arguments pushed on the stack are not popped, and (2) the - ; original stack pointer is lost. In the normal case (no context switch), - ; HL will contain the value of the SP before the arguments wer pushed. - - ld sp, hl ; Use the new stack pointer - - ; Restore registers. HL points to the beginning of the reg structure to restore - - ex af, af' ; Select alternate AF - pop af ; Offset 0: AF' = I with interrupt state in carry - ex af, af' ; Restore original AF - pop bc ; Offset 1: BC - pop de ; Offset 2: DE - pop ix ; Offset 3: IX - pop iy ; Offset 4: IY - exx ; Use alternate BC/DE/HL - ld hl, #-2 ; Offset of SP to account for ret addr on stack - pop de ; Offset 5: HL' = Stack pointer after return - add hl, de ; HL = Stack pointer value before return - exx ; Restore original BC/DE/HL - pop hl ; Offset 6: HL - pop af ; Offset 7: AF - - ; Restore the stack pointer - - exx ; Use alternate BC/DE/HL - ld sp, hl ; Set SP = saved stack pointer value before return - exx ; Restore original BC/DE/HL - - ; Restore interrupt state - - ex af, af' ; Recover interrupt state - jp po, nointenable ; Odd parity, IFF2=0, means disabled - ex af, af' ; Restore AF (before enabling interrupts) - ei ; yes - reti -nointenable:: - ex af, af' ; Restore AF - reti - -;************************************************************************** -; Ordering of segments for the linker (SDCC only) -;************************************************************************** - - .area _HOME - .area _CODE - .area _GSINIT - .area _GSFINAL - - .area _DATA - .area _BSS - .area _HEAP - -;************************************************************************** -; Global data initialization logic (SDCC only) -;************************************************************************** - - .area _GSINIT -gsinit:: - .area _GSFINAL - ret - +;************************************************************************** +; arch/z80/src/z80/z80_head.asm +; +; Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. +; Author: Gregory Nutt +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in +; the documentation and/or other materials provided with the +; distribution. +; 3. Neither the name NuttX nor the names of its contributors may be +; used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; +;************************************************************************** + + .title NuttX for the Z80 + .module z80_head + +;************************************************************************** +; Constants +;************************************************************************** + + ; Register save area layout + + XCPT_I == 0 ; Offset 0: Saved I w/interrupt state in carry + XCPT_BC == 2 ; Offset 1: Saved BC register + XCPT_DE == 4 ; Offset 2: Saved DE register + XCPT_IX == 6 ; Offset 3: Saved IX register + XCPT_IY == 8 ; Offset 4: Saved IY register + XCPT_SP == 10 ; Offset 5: Offset to SP at time of interrupt + XCPT_HL == 12 ; Offset 6: Saved HL register + XCPT_AF == 14 ; Offset 7: Saved AF register + XCPT_PC == 16 ; Offset 8: Offset to PC at time of interrupt + + ; Default stack base (needs to be fixed) + + .include "asm_mem.h" + +;************************************************************************** +; Global symbols used +;************************************************************************** + + .globl _os_start ; OS entry point + .globl _up_doirq ; Interrupt decoding logic + +;************************************************************************** +; Reset entry point +;************************************************************************** + + .area _HEADER (ABS) + .org 0x0000 + + di ; Disable interrupts + im 1 ; Set interrupt mode 1 + jr _up_reset ; And boot the system + +;************************************************************************** +; Other reset handlers +; +; Interrupt mode 1 behavior: +; +; 1. M1 cycle: 7 ticks +; Acknowledge interrupt and decrements SP +; 2. M2 cycle: 3 ticks +; Writes the MS byte of the PC onto the stack and decrements SP +; 3. M3 cycle: 3 ticks +; Writes the LS byte of the PC onto the stack and sets the PC to 0x0038. +; +;************************************************************************** + + .org 0x0008 ; RST 1 + + ; Save AF on the stack, set the interrupt number and jump to the + ; common reset handling logic. + ; Offset 8: Return PC is already on the stack + push af ; Offset 7: AF (retaining flags) + ld a, #1 ; 1 = Z80_RST1 + jr _up_rstcommon ; Remaining RST handling is common + + .org 0x0010 ; RST 2 + + ; Save AF on the stack, set the interrupt number and jump to the + ; common reset handling logic. + ; Offset 8: Return PC is already on the stack + push af ; Offset 7: AF (retaining flags) + ld a, #2 ; 2 = Z80_RST2 + jr _up_rstcommon ; Remaining RST handling is common + + .org 0x0018 ; RST 3 + + ; Save AF on the stack, set the interrupt number and jump to the + ; common reset handling logic. + ; Offset 8: Return PC is already on the stack + push af ; Offset 7: AF (retaining flags) + ld a, #3 ; 1 = Z80_RST3 + jr _up_rstcommon ; Remaining RST handling is common + + .org 0x0020 ; RST 4 + + ; Save AF on the stack, set the interrupt number and jump to the + ; common reset handling logic. + ; Offset 8: Return PC is already on the stack + push af ; Offset 7: AF (retaining flags) + ld a, #4 ; 1 = Z80_RST4 + jr _up_rstcommon ; Remaining RST handling is common + + .org 0x0028 ; RST 5 + + ; Save AF on the stack, set the interrupt number and jump to the + ; common reset handling logic. + ; Offset 8: Return PC is already on the stack + push af ; Offset 7: AF (retaining flags) + ld a, #5 ; 1 = Z80_RST5 + jr _up_rstcommon ; Remaining RST handling is common + + .org 0x0030 ; RST 6 + + ; Save AF on the stack, set the interrupt number and jump to the + ; common reset handling logic. + ; Offset 8: Return PC is already on the stack + push af ; Offset 7: AF (retaining flags) + ld a, #6 ; 1 = Z80_RST6 + jr _up_rstcommon ; Remaining RST handling is common + + .org 0x0038 ; Int mode 1 / RST 7 + + ; Save AF on the stack, set the interrupt number and jump to the + ; common reset handling logic. + ; Offset 8: Return PC is already on the stack + push af ; Offset 7: AF (retaining flags) + ld a, #7 ; 7 = Z80_RST7 + jr _up_rstcommon ; Remaining RST handling is common + +;************************************************************************** +; NMI interrupt handler +;************************************************************************** + + .org 0x0066 + retn + +;************************************************************************** +; System start logic +;************************************************************************** + +_up_reset: + ; Set up the stack pointer at the location determined the Makefile + ; and stored in asm_mem.h + + ld SP, #CONFIG_STACK_END ; Set stack pointer + + ; Performed initialization unique to the SDCC toolchain + + call gsinit ; Initialize the data section + + ; Then start NuttX + + call _os_start ; jump to the OS entry point + + ; NuttX will never return, but just in case... + +_up_halt:: + halt ; We should never get here + jp _up_halt + +;************************************************************************** +; Common Interrupt handler +;************************************************************************** + +_up_rstcommon:: + ; Create a register frame. SP points to top of frame + 4, pushes + ; decrement the stack pointer. Already have + ; + ; Offset 8: Return PC is already on the stack + ; Offset 7: AF (retaining flags) + ; + ; IRQ number is in A + + push hl ; Offset 6: HL + ld hl, #(3*2) ; HL is the value of the stack pointer before + add hl, sp ; the interrupt occurred + push hl ; Offset 5: Stack pointer + push iy ; Offset 4: IY + push ix ; Offset 3: IX + push de ; Offset 2: DE + push bc ; Offset 1: BC + + ld b, a ; Save the reset number in B + ld a, i ; Parity bit holds interrupt state + push af ; Offset 0: I with interrupt state in parity + di + + ; Call the interrupt decode logic. SP points to the beggining of the reg structure + + ld hl, #0 ; Argument #2 is the beginning of the reg structure + add hl, sp ; + push hl ; Place argument #2 at the top of stack + push bc ; Argument #1 is the Reset number + inc sp ; (make byte sized) + call _up_doirq ; Decode the IRQ + + ; On return, HL points to the beginning of the reg structure to restore + ; Note that (1) the arguments pushed on the stack are not popped, and (2) the + ; original stack pointer is lost. In the normal case (no context switch), + ; HL will contain the value of the SP before the arguments wer pushed. + + ld sp, hl ; Use the new stack pointer + + ; Restore registers. HL points to the beginning of the reg structure to restore + + ex af, af' ; Select alternate AF + pop af ; Offset 0: AF' = I with interrupt state in carry + ex af, af' ; Restore original AF + pop bc ; Offset 1: BC + pop de ; Offset 2: DE + pop ix ; Offset 3: IX + pop iy ; Offset 4: IY + exx ; Use alternate BC/DE/HL + ld hl, #-2 ; Offset of SP to account for ret addr on stack + pop de ; Offset 5: HL' = Stack pointer after return + add hl, de ; HL = Stack pointer value before return + exx ; Restore original BC/DE/HL + pop hl ; Offset 6: HL + pop af ; Offset 7: AF + + ; Restore the stack pointer + + exx ; Use alternate BC/DE/HL + ld sp, hl ; Set SP = saved stack pointer value before return + exx ; Restore original BC/DE/HL + + ; Restore interrupt state + + ex af, af' ; Recover interrupt state + jp po, nointenable ; Odd parity, IFF2=0, means disabled + ex af, af' ; Restore AF (before enabling interrupts) + ei ; yes + reti +nointenable:: + ex af, af' ; Restore AF + reti + +;************************************************************************** +; Ordering of segments for the linker (SDCC only) +;************************************************************************** + + .area _HOME + .area _CODE + .area _GSINIT + .area _GSFINAL + + .area _DATA + .area _BSS + .area _HEAP + +;************************************************************************** +; Global data initialization logic (SDCC only) +;************************************************************************** + + .area _GSINIT +gsinit:: + .area _GSFINAL + ret + diff --git a/arch/z80/src/z80/z80_initialstate.c b/arch/z80/src/z80/z80_initialstate.c index fc65dbca555abf04937cf037f355c641d0cf254e..01cc4f00a5986d206f5caf3298c006c2c89b2492 100644 --- a/arch/z80/src/z80/z80_initialstate.c +++ b/arch/z80/src/z80/z80_initialstate.c @@ -2,7 +2,7 @@ * arch/z80/src/z80/z80_initialstate.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z80/z80_io.c b/arch/z80/src/z80/z80_io.c index 780d5f67442f7789327144b83180d29789a07227..cddaa6831f19209bc0a3857c944735df8f1b7731 100644 --- a/arch/z80/src/z80/z80_io.c +++ b/arch/z80/src/z80/z80_io.c @@ -2,7 +2,7 @@ * arch/z80/src/z80/z80_io.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z80/z80_irq.c b/arch/z80/src/z80/z80_irq.c index 5efd36b9fa60530341dc72b87d3c20166a6685ff..08b426235d64ca30c6e2aed886d496151e111446 100644 --- a/arch/z80/src/z80/z80_irq.c +++ b/arch/z80/src/z80/z80_irq.c @@ -2,7 +2,7 @@ * arch/z80/src/z80/z80_irq.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z80/z80_registerdump.c b/arch/z80/src/z80/z80_registerdump.c index f215b6dc6e7f7f2d8e7c7760fdc7df4c9f7b1bd6..0d09a243a2a1ce95665bbcea7b15f30b75ffce06 100644 --- a/arch/z80/src/z80/z80_registerdump.c +++ b/arch/z80/src/z80/z80_registerdump.c @@ -2,7 +2,7 @@ * arch/z80/src/z80/z80_registerdump.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z80/z80_restoreusercontext.asm b/arch/z80/src/z80/z80_restoreusercontext.asm index 79c3a6034dc9a677a3ce9bd345bbb52939c76b37..bab143462564b2bf46ab72422e44dc4447e3901c 100644 --- a/arch/z80/src/z80/z80_restoreusercontext.asm +++ b/arch/z80/src/z80/z80_restoreusercontext.asm @@ -1,104 +1,104 @@ -;************************************************************************** -; arch/z80/src/z80/z80_restoreusercontext.asm -; -; Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. -; Author: Gregory Nutt -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions -; are met: -; -; 1. Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in -; the documentation and/or other materials provided with the -; distribution. -; 3. Neither the name NuttX nor the names of its contributors may be -; used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; -;************************************************************************** - - ; Register save area layout - - .globl XCPT_I ; Offset 0: Saved I w/interrupt state in carry - .globl XCPT_BC ; Offset 1: Saved BC register - .globl XCPT_DE ; Offset 2: Saved DE register - .globl XCPT_IX ; Offset 3: Saved IX register - .globl XCPT_IY ; Offset 4: Saved IY register - .globl XCPT_SP ; Offset 5: Offset to SP at time of interrupt - .globl XCPT_HL ; Offset 6: Saved HL register - .globl XCPT_AF ; Offset 7: Saved AF register - .globl XCPT_PC ; Offset 8: Offset to PC at time of interrupt - -;************************************************************************** -; z80_restoreusercontext -;************************************************************************** - - .area _CODE -_z80_restoreusercontext: - ; On entry, stack contains return address (not used), then address - ; of the register save structure - - ; Discard the return address, we won't be returning - - pop hl - - ; Get the address of the beginning of the state save area. Each - ; pop will increment to the next element of the structure - - pop hl ; BC = Address of save structure - ld sp, hl ; SP points to top of storage area - - ; Disable interrupts while we muck with the alternative registers. The - ; Correct interrupt state will be restore below - - di - - ; Restore registers. HL points to the beginning of the reg structure to restore - - ex af, af' ; Select alternate AF - pop af ; Offset 0: AF' = I with interrupt state in parity - ex af, af' ; Restore original AF - pop bc ; Offset 1: BC - pop de ; Offset 2: DE - pop ix ; Offset 3: IX - pop iy ; Offset 4: IY - exx ; Use alternate BC/DE/HL - pop hl ; Offset 5: HL' = Stack pointer after return - exx ; Restore original BC/DE/HL - pop hl ; Offset 6: HL - pop af ; Offset 7: AF - - ; Restore the stack pointer - - exx ; Use alternate BC/DE/HL - pop de ; DE' = return address - ld sp, hl ; Set SP = saved stack pointer value before return - push de ; Save return address for ret instruction - exx ; Restore original BC/DE/HL - - ; Restore interrupt state - - ex af, af' ; Recover interrupt state - jp po, noinrestore ; Odd parity, IFF2=0, means disabled - ex af, af' ; Restore AF (before enabling interrupts) - ei ; yes.. Enable interrupts - ret ; and return -noinrestore: - ex af, af' ; Restore AF - ret ; Return with interrupts disabled +;************************************************************************** +; arch/z80/src/z80/z80_restoreusercontext.asm +; +; Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. +; Author: Gregory Nutt +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in +; the documentation and/or other materials provided with the +; distribution. +; 3. Neither the name NuttX nor the names of its contributors may be +; used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; +;************************************************************************** + + ; Register save area layout + + .globl XCPT_I ; Offset 0: Saved I w/interrupt state in carry + .globl XCPT_BC ; Offset 1: Saved BC register + .globl XCPT_DE ; Offset 2: Saved DE register + .globl XCPT_IX ; Offset 3: Saved IX register + .globl XCPT_IY ; Offset 4: Saved IY register + .globl XCPT_SP ; Offset 5: Offset to SP at time of interrupt + .globl XCPT_HL ; Offset 6: Saved HL register + .globl XCPT_AF ; Offset 7: Saved AF register + .globl XCPT_PC ; Offset 8: Offset to PC at time of interrupt + +;************************************************************************** +; z80_restoreusercontext +;************************************************************************** + + .area _CODE +_z80_restoreusercontext: + ; On entry, stack contains return address (not used), then address + ; of the register save structure + + ; Discard the return address, we won't be returning + + pop hl + + ; Get the address of the beginning of the state save area. Each + ; pop will increment to the next element of the structure + + pop hl ; BC = Address of save structure + ld sp, hl ; SP points to top of storage area + + ; Disable interrupts while we muck with the alternative registers. The + ; Correct interrupt state will be restore below + + di + + ; Restore registers. HL points to the beginning of the reg structure to restore + + ex af, af' ; Select alternate AF + pop af ; Offset 0: AF' = I with interrupt state in parity + ex af, af' ; Restore original AF + pop bc ; Offset 1: BC + pop de ; Offset 2: DE + pop ix ; Offset 3: IX + pop iy ; Offset 4: IY + exx ; Use alternate BC/DE/HL + pop hl ; Offset 5: HL' = Stack pointer after return + exx ; Restore original BC/DE/HL + pop hl ; Offset 6: HL + pop af ; Offset 7: AF + + ; Restore the stack pointer + + exx ; Use alternate BC/DE/HL + pop de ; DE' = return address + ld sp, hl ; Set SP = saved stack pointer value before return + push de ; Save return address for ret instruction + exx ; Restore original BC/DE/HL + + ; Restore interrupt state + + ex af, af' ; Recover interrupt state + jp po, noinrestore ; Odd parity, IFF2=0, means disabled + ex af, af' ; Restore AF (before enabling interrupts) + ei ; yes.. Enable interrupts + ret ; and return +noinrestore: + ex af, af' ; Restore AF + ret ; Return with interrupts disabled diff --git a/arch/z80/src/z80/z80_rom.asm b/arch/z80/src/z80/z80_rom.asm index b2fd76bb3b5691224794eac9e7f5322b22197508..d3bc13530667458f8c504ac4278e56351b34b828 100644 --- a/arch/z80/src/z80/z80_rom.asm +++ b/arch/z80/src/z80/z80_rom.asm @@ -1,276 +1,276 @@ -;************************************************************************** -; arch/z80/src/z80/z80_rom.asm -; -; Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. -; Author: Gregory Nutt -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions -; are met: -; -; 1. Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in -; the documentation and/or other materials provided with the -; distribution. -; 3. Neither the name NuttX nor the names of its contributors may be -; used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; -;************************************************************************** - - .title NuttX for the Z80 - .module z80_head - -;************************************************************************** -; Constants -;************************************************************************** - - ; Register save area layout - - XCPT_I == 0 ; Offset 0: Saved I w/interrupt state in parity - XCPT_BC == 2 ; Offset 1: Saved BC register - XCPT_DE == 4 ; Offset 2: Saved DE register - XCPT_IX == 6 ; Offset 3: Saved IX register - XCPT_IY == 8 ; Offset 4: Saved IY register - XCPT_SP == 10 ; Offset 5: Offset to SP at time of interrupt - XCPT_HL == 12 ; Offset 6: Saved HL register - XCPT_AF == 14 ; Offset 7: Saved AF register - XCPT_PC == 16 ; Offset 8: Offset to PC at time of interrupt - - ; Default stack base (needs to be fixed) - - .include "asm_mem.h" - -;************************************************************************** -; Global symbols used -;************************************************************************** - - .globl _os_start ; OS entry point - .globl _up_doirq ; Interrupt decoding logic - -;************************************************************************** -; System start logic -;************************************************************************** - -_up_reset: - ; Set up the stack pointer at the location determined the Makefile - ; and stored in asm_mem.h - - ld SP, #CONFIG_STACK_END ; Set stack pointer - - ; Performed initialization unique to the SDCC toolchain - - call gsinit ; Initialize the data section - - ; Copy the reset vectors - - ld hl, #_up_rstvectors ; code for RAM - ld de, #0x4000 ; move it here - ld bc, #3*7 ; 7 vectors / 3 bytes each - ldir - - ; Then start NuttX - - call _os_start ; jump to the OS entry point - - ; NuttX will never return, but just in case... - -_up_halt:: - halt ; We should never get here - jp _up_halt - - ; Data to copy to address 0x4000 - -_up_rstvectors: - jp _up_rst1 ; 0x4000 : RST 1 - jp _up_rst2 ; 0x4003 : RST 2 - jp _up_rst3 ; 0x4006 : RST 3 - jp _up_rst4 ; 0x4009 : RST 4 - jp _up_rst5 ; 0x400c : RST 5 - jp _up_rst6 ; 0x400f : RST 6 - jp _up_rst7 ; 0x4012 : RST 7 - -;************************************************************************** -; Other reset handlers -; -; Interrupt mode 1 behavior: -; -; 1. M1 cycle: 7 ticks -; Acknowledge interrupt and decrements SP -; 2. M2 cycle: 3 ticks -; Writes the MS byte of the PC onto the stack and decrements SP -; 3. M3 cycle: 3 ticks -; Writes the LS byte of the PC onto the stack and sets the PC to 0x0038. -; -;************************************************************************** - -_up_rst1: ; RST 1 - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #1 ; 1 = Z80_RST1 - jr _up_rstcommon ; Remaining RST handling is common - -_up_rst2: ; RST 2 - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #2 ; 2 = Z80_RST2 - jr _up_rstcommon ; Remaining RST handling is common - -_up_rst3: ; RST 3 - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #3 ; 1 = Z80_RST3 - jr _up_rstcommon ; Remaining RST handling is common - -_up_rst4: ; RST 4 - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #4 ; 1 = Z80_RST4 - jr _up_rstcommon ; Remaining RST handling is common - -_up_rst5: ; RST 5 - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #5 ; 1 = Z80_RST5 - jr _up_rstcommon ; Remaining RST handling is common - -_up_rst6: ; RST 6 - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #6 ; 1 = Z80_RST6 - jr _up_rstcommon ; Remaining RST handling is common - -_up_rst7: ; RST 7 - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #7 ; 7 = Z80_RST7 - jr _up_rstcommon ; Remaining RST handling is common - -;************************************************************************** -; Common Interrupt handler -;************************************************************************** - -_up_rstcommon: - ; Create a register frame. SP points to top of frame + 4, pushes - ; decrement the stack pointer. Already have - ; - ; Offset 8: Return PC is already on the stack - ; Offset 7: AF (retaining flags) - ; - ; IRQ number is in A - - push hl ; Offset 6: HL - ld hl, #(3*2) ; HL is the value of the stack pointer before - add hl, sp ; the interrupt occurred - push hl ; Offset 5: Stack pointer - push iy ; Offset 4: IY - push ix ; Offset 3: IX - push de ; Offset 2: DE - push bc ; Offset 1: BC - - ld b, a ; Save the reset number in B - ld a, i ; Parity bit holds interrupt state - push af ; Offset 0: I with interrupt state in parity - di - - ; Call the interrupt decode logic. SP points to the beginning of the reg structure - - ld hl, #0 ; Argument #2 is the beginning of the reg structure - add hl, sp ; - push hl ; Place argument #2 at the top of stack - push bc ; Argument #1 is the Reset number - inc sp ; (make byte sized) - call _up_doirq ; Decode the IRQ - - ; On return, HL points to the beginning of the reg structure to restore - ; Note that (1) the arguments pushed on the stack are not popped, and (2) the - ; original stack pointer is lost. In the normal case (no context switch), - ; HL will contain the value of the SP before the arguments were pushed. - - ld sp, hl ; Use the new stack pointer - - ; Restore registers. HL points to the beginning of the reg structure to restore - - ex af, af' ; Select alternate AF - pop af ; Offset 0: AF' = I with interrupt state in parity - ex af, af' ; Restore original AF - pop bc ; Offset 1: BC - pop de ; Offset 2: DE - pop ix ; Offset 3: IX - pop iy ; Offset 4: IY - exx ; Use alternate BC/DE/HL - ld hl, #-2 ; Offset of SP to account for ret addr on stack - pop de ; Offset 5: HL' = Stack pointer after return - add hl, de ; HL = Stack pointer value before return - exx ; Restore original BC/DE/HL - pop hl ; Offset 6: HL - pop af ; Offset 7: AF - - ; Restore the stack pointer - - exx ; Use alternate BC/DE/HL - ld sp, hl ; Set SP = saved stack pointer value before return - exx ; Restore original BC/DE/HL - - ; Restore interrupt state - - ex af, af' ; Recover interrupt state - jp po, nointenable ; Odd parity, IFF2=0, means disabled - ex af, af' ; Restore AF (before enabling interrupts) - ei ; yes - reti -nointenable:: - ex af, af' ; Restore AF - reti - -;************************************************************************** -; Ordering of segments for the linker (SDCC only) -;************************************************************************** - - .area _HOME - .area _CODE - .area _GSINIT - .area _GSFINAL - - .area _DATA - .area _BSS - .area _HEAP - -;************************************************************************** -; Global data initialization logic (SDCC only) -;************************************************************************** - - .area _GSINIT -gsinit:: - .area _GSFINAL - ret - +;************************************************************************** +; arch/z80/src/z80/z80_rom.asm +; +; Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. +; Author: Gregory Nutt +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in +; the documentation and/or other materials provided with the +; distribution. +; 3. Neither the name NuttX nor the names of its contributors may be +; used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; +;************************************************************************** + + .title NuttX for the Z80 + .module z80_head + +;************************************************************************** +; Constants +;************************************************************************** + + ; Register save area layout + + XCPT_I == 0 ; Offset 0: Saved I w/interrupt state in parity + XCPT_BC == 2 ; Offset 1: Saved BC register + XCPT_DE == 4 ; Offset 2: Saved DE register + XCPT_IX == 6 ; Offset 3: Saved IX register + XCPT_IY == 8 ; Offset 4: Saved IY register + XCPT_SP == 10 ; Offset 5: Offset to SP at time of interrupt + XCPT_HL == 12 ; Offset 6: Saved HL register + XCPT_AF == 14 ; Offset 7: Saved AF register + XCPT_PC == 16 ; Offset 8: Offset to PC at time of interrupt + + ; Default stack base (needs to be fixed) + + .include "asm_mem.h" + +;************************************************************************** +; Global symbols used +;************************************************************************** + + .globl _os_start ; OS entry point + .globl _up_doirq ; Interrupt decoding logic + +;************************************************************************** +; System start logic +;************************************************************************** + +_up_reset: + ; Set up the stack pointer at the location determined the Makefile + ; and stored in asm_mem.h + + ld SP, #CONFIG_STACK_END ; Set stack pointer + + ; Performed initialization unique to the SDCC toolchain + + call gsinit ; Initialize the data section + + ; Copy the reset vectors + + ld hl, #_up_rstvectors ; code for RAM + ld de, #0x4000 ; move it here + ld bc, #3*7 ; 7 vectors / 3 bytes each + ldir + + ; Then start NuttX + + call _os_start ; jump to the OS entry point + + ; NuttX will never return, but just in case... + +_up_halt:: + halt ; We should never get here + jp _up_halt + + ; Data to copy to address 0x4000 + +_up_rstvectors: + jp _up_rst1 ; 0x4000 : RST 1 + jp _up_rst2 ; 0x4003 : RST 2 + jp _up_rst3 ; 0x4006 : RST 3 + jp _up_rst4 ; 0x4009 : RST 4 + jp _up_rst5 ; 0x400c : RST 5 + jp _up_rst6 ; 0x400f : RST 6 + jp _up_rst7 ; 0x4012 : RST 7 + +;************************************************************************** +; Other reset handlers +; +; Interrupt mode 1 behavior: +; +; 1. M1 cycle: 7 ticks +; Acknowledge interrupt and decrements SP +; 2. M2 cycle: 3 ticks +; Writes the MS byte of the PC onto the stack and decrements SP +; 3. M3 cycle: 3 ticks +; Writes the LS byte of the PC onto the stack and sets the PC to 0x0038. +; +;************************************************************************** + +_up_rst1: ; RST 1 + ; Save AF on the stack, set the interrupt number and jump to the + ; common reset handling logic. + ; Offset 8: Return PC is already on the stack + push af ; Offset 7: AF (retaining flags) + ld a, #1 ; 1 = Z80_RST1 + jr _up_rstcommon ; Remaining RST handling is common + +_up_rst2: ; RST 2 + ; Save AF on the stack, set the interrupt number and jump to the + ; common reset handling logic. + ; Offset 8: Return PC is already on the stack + push af ; Offset 7: AF (retaining flags) + ld a, #2 ; 2 = Z80_RST2 + jr _up_rstcommon ; Remaining RST handling is common + +_up_rst3: ; RST 3 + ; Save AF on the stack, set the interrupt number and jump to the + ; common reset handling logic. + ; Offset 8: Return PC is already on the stack + push af ; Offset 7: AF (retaining flags) + ld a, #3 ; 1 = Z80_RST3 + jr _up_rstcommon ; Remaining RST handling is common + +_up_rst4: ; RST 4 + ; Save AF on the stack, set the interrupt number and jump to the + ; common reset handling logic. + ; Offset 8: Return PC is already on the stack + push af ; Offset 7: AF (retaining flags) + ld a, #4 ; 1 = Z80_RST4 + jr _up_rstcommon ; Remaining RST handling is common + +_up_rst5: ; RST 5 + ; Save AF on the stack, set the interrupt number and jump to the + ; common reset handling logic. + ; Offset 8: Return PC is already on the stack + push af ; Offset 7: AF (retaining flags) + ld a, #5 ; 1 = Z80_RST5 + jr _up_rstcommon ; Remaining RST handling is common + +_up_rst6: ; RST 6 + ; Save AF on the stack, set the interrupt number and jump to the + ; common reset handling logic. + ; Offset 8: Return PC is already on the stack + push af ; Offset 7: AF (retaining flags) + ld a, #6 ; 1 = Z80_RST6 + jr _up_rstcommon ; Remaining RST handling is common + +_up_rst7: ; RST 7 + ; Save AF on the stack, set the interrupt number and jump to the + ; common reset handling logic. + ; Offset 8: Return PC is already on the stack + push af ; Offset 7: AF (retaining flags) + ld a, #7 ; 7 = Z80_RST7 + jr _up_rstcommon ; Remaining RST handling is common + +;************************************************************************** +; Common Interrupt handler +;************************************************************************** + +_up_rstcommon: + ; Create a register frame. SP points to top of frame + 4, pushes + ; decrement the stack pointer. Already have + ; + ; Offset 8: Return PC is already on the stack + ; Offset 7: AF (retaining flags) + ; + ; IRQ number is in A + + push hl ; Offset 6: HL + ld hl, #(3*2) ; HL is the value of the stack pointer before + add hl, sp ; the interrupt occurred + push hl ; Offset 5: Stack pointer + push iy ; Offset 4: IY + push ix ; Offset 3: IX + push de ; Offset 2: DE + push bc ; Offset 1: BC + + ld b, a ; Save the reset number in B + ld a, i ; Parity bit holds interrupt state + push af ; Offset 0: I with interrupt state in parity + di + + ; Call the interrupt decode logic. SP points to the beginning of the reg structure + + ld hl, #0 ; Argument #2 is the beginning of the reg structure + add hl, sp ; + push hl ; Place argument #2 at the top of stack + push bc ; Argument #1 is the Reset number + inc sp ; (make byte sized) + call _up_doirq ; Decode the IRQ + + ; On return, HL points to the beginning of the reg structure to restore + ; Note that (1) the arguments pushed on the stack are not popped, and (2) the + ; original stack pointer is lost. In the normal case (no context switch), + ; HL will contain the value of the SP before the arguments were pushed. + + ld sp, hl ; Use the new stack pointer + + ; Restore registers. HL points to the beginning of the reg structure to restore + + ex af, af' ; Select alternate AF + pop af ; Offset 0: AF' = I with interrupt state in parity + ex af, af' ; Restore original AF + pop bc ; Offset 1: BC + pop de ; Offset 2: DE + pop ix ; Offset 3: IX + pop iy ; Offset 4: IY + exx ; Use alternate BC/DE/HL + ld hl, #-2 ; Offset of SP to account for ret addr on stack + pop de ; Offset 5: HL' = Stack pointer after return + add hl, de ; HL = Stack pointer value before return + exx ; Restore original BC/DE/HL + pop hl ; Offset 6: HL + pop af ; Offset 7: AF + + ; Restore the stack pointer + + exx ; Use alternate BC/DE/HL + ld sp, hl ; Set SP = saved stack pointer value before return + exx ; Restore original BC/DE/HL + + ; Restore interrupt state + + ex af, af' ; Recover interrupt state + jp po, nointenable ; Odd parity, IFF2=0, means disabled + ex af, af' ; Restore AF (before enabling interrupts) + ei ; yes + reti +nointenable:: + ex af, af' ; Restore AF + reti + +;************************************************************************** +; Ordering of segments for the linker (SDCC only) +;************************************************************************** + + .area _HOME + .area _CODE + .area _GSINIT + .area _GSFINAL + + .area _DATA + .area _BSS + .area _HEAP + +;************************************************************************** +; Global data initialization logic (SDCC only) +;************************************************************************** + + .area _GSINIT +gsinit:: + .area _GSFINAL + ret + diff --git a/arch/z80/src/z80/z80_saveusercontext.asm b/arch/z80/src/z80/z80_saveusercontext.asm index e23039dfc3d808bc84ed370f35e9ec50ee72102d..d53c3c5df2e953e459f91c0353f48fda2bb34e69 100644 --- a/arch/z80/src/z80/z80_saveusercontext.asm +++ b/arch/z80/src/z80/z80_saveusercontext.asm @@ -2,7 +2,7 @@ ; arch/z80/src/z80/z80_saveusercontext.asm ; ; Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. -; Author: Gregory Nutt +; Author: Gregory Nutt ; ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z80/z80_schedulesigaction.c b/arch/z80/src/z80/z80_schedulesigaction.c index 24b12731c7e7738c70e6cc26d96e10d9f978972f..3b227d5e3c2ff9c7ca809af87c63b6c5e723f129 100644 --- a/arch/z80/src/z80/z80_schedulesigaction.c +++ b/arch/z80/src/z80/z80_schedulesigaction.c @@ -2,7 +2,7 @@ * arch/z80/src/z80/z80_schedulesigaction.c * * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/z80/src/z80/z80_sigdeliver.c b/arch/z80/src/z80/z80_sigdeliver.c index c6aa5ff3c56dd30206859530f47391e87e88bb78..a8fc1e3470c6319022869c06f0436e11b907839a 100644 --- a/arch/z80/src/z80/z80_sigdeliver.c +++ b/arch/z80/src/z80/z80_sigdeliver.c @@ -2,7 +2,7 @@ * arch/z80/src/z80/z80_sigdeliver.c * * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/Makefile b/binfmt/Makefile index dd9e459cedda7a2543f1079ee2f8582f937cf5dc..b3a9269b30780bdce5f39e5939a08c6c5409e352 100644 --- a/binfmt/Makefile +++ b/binfmt/Makefile @@ -2,7 +2,7 @@ # nxflat/Makefile # # Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/binfmt/binfmt_dumpmodule.c b/binfmt/binfmt_dumpmodule.c index 945dcb3acea1658fb942c3fd842d80fe718a1959..32a3fef3e352513bcd713e8c10171cf0027e7fd2 100644 --- a/binfmt/binfmt_dumpmodule.c +++ b/binfmt/binfmt_dumpmodule.c @@ -2,7 +2,7 @@ * binfmt/binfmt_dumpmodule.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/binfmt_exec.c b/binfmt/binfmt_exec.c index cefd3aa5c75618788687df385929dae4a048b6f7..c070324c31628580f1d7f24affba8560861c7df4 100644 --- a/binfmt/binfmt_exec.c +++ b/binfmt/binfmt_exec.c @@ -2,7 +2,7 @@ * binfmt/binfmt_exec.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/binfmt_execmodule.c b/binfmt/binfmt_execmodule.c index 1965f6fa0b352517eba07176a3bdf34721100cba..1b511b0cb8a95291299b5655a72b3b5260c0e9e4 100644 --- a/binfmt/binfmt_execmodule.c +++ b/binfmt/binfmt_execmodule.c @@ -2,7 +2,7 @@ * binfmt/binfmt_execmodule.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/binfmt_globals.c b/binfmt/binfmt_globals.c index 0d0b2dbb4221dc2200c9a56ec74fe18dca52caa9..069d3a2aa9f94fcd4ead0ea50ef4bcda1f8e4799 100644 --- a/binfmt/binfmt_globals.c +++ b/binfmt/binfmt_globals.c @@ -2,7 +2,7 @@ * binfmt/binfmt_globals.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/binfmt_internal.h b/binfmt/binfmt_internal.h index 22fadcd2114a1d8993da8b2fec3c13448d673e94..da67f5350b422d8a3314bf9255857357e198b8d2 100644 --- a/binfmt/binfmt_internal.h +++ b/binfmt/binfmt_internal.h @@ -2,7 +2,7 @@ * binfmt/binfmt_internal.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/binfmt_loadmodule.c b/binfmt/binfmt_loadmodule.c index d4ef7cde2740a40a93fbc657b0f61da8592776f2..01ab8cc883222cdff3fd0faa17bf4906e991d233 100644 --- a/binfmt/binfmt_loadmodule.c +++ b/binfmt/binfmt_loadmodule.c @@ -2,7 +2,7 @@ * binfmt/binfmt_loadmodule.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/binfmt_register.c b/binfmt/binfmt_register.c index e41c7a0d98a89c8b2185bdeb910419e186342b3a..7f6eef671a6b6fa97912445e0f44669e7ee2fee0 100644 --- a/binfmt/binfmt_register.c +++ b/binfmt/binfmt_register.c @@ -2,7 +2,7 @@ * binfmt/binfmt_register.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/binfmt_unloadmodule.c b/binfmt/binfmt_unloadmodule.c index c6fa90c3960b5cc0c2eb061f960fd3114fb51725..04859a291098b9228a0c1d18985b541de390430b 100644 --- a/binfmt/binfmt_unloadmodule.c +++ b/binfmt/binfmt_unloadmodule.c @@ -2,7 +2,7 @@ * binfmt/binfmt_loadmodule.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/binfmt_unregister.c b/binfmt/binfmt_unregister.c index 1b50b2c5829abb392cc8e54430aa0bcba31a37d5..b97b9b67dd11b00c790a6b5fd9759cbbfd686405 100644 --- a/binfmt/binfmt_unregister.c +++ b/binfmt/binfmt_unregister.c @@ -2,7 +2,7 @@ * binfmt/binfmt_unregister.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/libnxflat/Make.defs b/binfmt/libnxflat/Make.defs index 9e95936519639ff76946dc30448acb8f23e23068..f979741e515797c13d1196ff955ac26c635daa92 100644 --- a/binfmt/libnxflat/Make.defs +++ b/binfmt/libnxflat/Make.defs @@ -2,7 +2,7 @@ # nxflat/lib/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/binfmt/libnxflat/gnu-nxflat.ld b/binfmt/libnxflat/gnu-nxflat.ld index 9a59c0ec0930b0affcd428ef9c681235d7685d33..e66b1dff52489abc3f4b758980cab39d1aaaab44 100644 --- a/binfmt/libnxflat/gnu-nxflat.ld +++ b/binfmt/libnxflat/gnu-nxflat.ld @@ -2,7 +2,7 @@ * examples/nxflat/nxflat.ld * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/libnxflat/libnxflat_bind.c b/binfmt/libnxflat/libnxflat_bind.c index eb65a7e63a92aa72174bf81fa19594159eb1a0c0..ca348178ddf5ebf872889abcdfe343c3a0d9d0cb 100644 --- a/binfmt/libnxflat/libnxflat_bind.c +++ b/binfmt/libnxflat/libnxflat_bind.c @@ -2,7 +2,7 @@ * binfmt/libnxflat/libnxflat_bind.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/libnxflat/libnxflat_init.c b/binfmt/libnxflat/libnxflat_init.c index 45f016e2716bdab10a81e822fedd13b094166992..5b6375ff16832dcc24b8c009eec6255d6d088cee 100644 --- a/binfmt/libnxflat/libnxflat_init.c +++ b/binfmt/libnxflat/libnxflat_init.c @@ -2,7 +2,7 @@ * binfmt/libnxflat/libnxflat_init.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/libnxflat/libnxflat_load.c b/binfmt/libnxflat/libnxflat_load.c index 25be056212c44ac9ada46e16d051f4decaf33833..0991d0c2d79d3c16155065b5e83afc3fbf1b3713 100644 --- a/binfmt/libnxflat/libnxflat_load.c +++ b/binfmt/libnxflat/libnxflat_load.c @@ -2,7 +2,7 @@ * binfmt/libnxflat/libnxflat_load.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/libnxflat/libnxflat_read.c b/binfmt/libnxflat/libnxflat_read.c index 8f1650e873f3f0edfd3da9d59c06e52ab57da004..dbcd54279150dd29599c8b012017304942a3980a 100644 --- a/binfmt/libnxflat/libnxflat_read.c +++ b/binfmt/libnxflat/libnxflat_read.c @@ -2,7 +2,7 @@ * binfmt/libnxflat/libnxflat_read.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/libnxflat/libnxflat_uninit.c b/binfmt/libnxflat/libnxflat_uninit.c index 72be6c7aedd49ba01d140ab66625fb6f22cd5d32..5d06296c795094e943b2c77b18628921f40d58df 100644 --- a/binfmt/libnxflat/libnxflat_uninit.c +++ b/binfmt/libnxflat/libnxflat_uninit.c @@ -2,7 +2,7 @@ * binfmt/libnxflat/libnxflat_uninit.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/libnxflat/libnxflat_unload.c b/binfmt/libnxflat/libnxflat_unload.c index 7dc3e87a747590f69683f96e22a946be156113b7..55a2e45e603cd4d2e1ed9d31e8214c3d1482574f 100644 --- a/binfmt/libnxflat/libnxflat_unload.c +++ b/binfmt/libnxflat/libnxflat_unload.c @@ -2,7 +2,7 @@ * binfmt/libnxflat/libnxflat_unload.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/libnxflat/libnxflat_verify.c b/binfmt/libnxflat/libnxflat_verify.c index de952774fc7bd3849f4998da877bc96e3d7f9156..f799aca4f6d06ad211b82ee3e4aadd36c2a88b29 100644 --- a/binfmt/libnxflat/libnxflat_verify.c +++ b/binfmt/libnxflat/libnxflat_verify.c @@ -2,7 +2,7 @@ * binfmt/libnxflat/nxflat_verify.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/nxflat.c b/binfmt/nxflat.c index 99b99249a11fb3eca169168b27e81db3cba79755..4f5869bd92ea34e7f84d49867164dcfe78f769fc 100644 --- a/binfmt/nxflat.c +++ b/binfmt/nxflat.c @@ -2,7 +2,7 @@ * binfmt/nxflat.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/symtab_findbyname.c b/binfmt/symtab_findbyname.c index 02b2ac22b4a88ade35d7faae2a3f5493697b6f08..201d7ba07d19866031c36d8dee043714702bac69 100644 --- a/binfmt/symtab_findbyname.c +++ b/binfmt/symtab_findbyname.c @@ -2,7 +2,7 @@ * binfmt/symtab_findbyname.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/symtab_findbyvalue.c b/binfmt/symtab_findbyvalue.c index 80df746684f8907c2e8507500172c6fbcbf67bec..4382ed5d8dd25f067e6ccb57c6c808da9ecb2553 100644 --- a/binfmt/symtab_findbyvalue.c +++ b/binfmt/symtab_findbyvalue.c @@ -2,7 +2,7 @@ * binfmt/symtab_findbyvalue.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/symtab_findorderedbyname.c b/binfmt/symtab_findorderedbyname.c index 82d68bfea4f6433df4ef267358d66d6363f6ccdf..61decf49adba43af1d71ee6945619966d0963537 100644 --- a/binfmt/symtab_findorderedbyname.c +++ b/binfmt/symtab_findorderedbyname.c @@ -2,7 +2,7 @@ * binfmt/symtab_findorderedbyname.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/binfmt/symtab_findorderedbyvalue.c b/binfmt/symtab_findorderedbyvalue.c index a995595da972270fc46ae5c9dcbe70e4b5a3ff95..92b107856dfba52acbdf1ca825626ef1f72098bc 100644 --- a/binfmt/symtab_findorderedbyvalue.c +++ b/binfmt/symtab_findorderedbyvalue.c @@ -2,7 +2,7 @@ * binfmt/symtab_findorderedbyvalue.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/amber/hello/appconfig b/configs/amber/hello/appconfig index b932c0470a048ed50eff411395deaa9e0ffb94a9..35d94bcd7280be6fb03ef30767e2aaa7d182a72a 100644 --- a/configs/amber/hello/appconfig +++ b/configs/amber/hello/appconfig @@ -2,7 +2,7 @@ # configs/amber/hello/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/amber/hello/ld.script b/configs/amber/hello/ld.script index 719f68163c992ccf6014625004d76a9dc8364c65..af7eed6f3036f361c73497dfd471e564376cff96 100644 --- a/configs/amber/hello/ld.script +++ b/configs/amber/hello/ld.script @@ -2,7 +2,7 @@ * configs/amber/hello/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/amber/hello/setenv.sh b/configs/amber/hello/setenv.sh index 4ce47684d3bc8d5c5e7f1c17e8eb389a7f7c75e1..094bad8b92b4480c8c7f2b05b1383176554ff86b 100755 --- a/configs/amber/hello/setenv.sh +++ b/configs/amber/hello/setenv.sh @@ -2,7 +2,7 @@ # configs/amber/hello/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/amber/include/board.h b/configs/amber/include/board.h index 0aaa6baa86f1d8f0579e8de5ede67b5e5bb78327..dba47cb95f568f2d6d453cb44bf58fc6bc487ea5 100755 --- a/configs/amber/include/board.h +++ b/configs/amber/include/board.h @@ -3,7 +3,7 @@ * include/arch/board/board.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/amber/src/Makefile b/configs/amber/src/Makefile index 24375992474550c7996e6638273dafeb81513370..7b30e6ff6ecf285a853eeb9dc33f0f799ae42958 100644 --- a/configs/amber/src/Makefile +++ b/configs/amber/src/Makefile @@ -2,7 +2,7 @@ # configs/amber/src/Makefile # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/amber/src/amber_internal.h b/configs/amber/src/amber_internal.h index 7f16e3d740f0c4d5febce5b549684bf38a0fdb3d..6e847bdec9462c311d96f96a81f8fef1ff68222b 100644 --- a/configs/amber/src/amber_internal.h +++ b/configs/amber/src/amber_internal.h @@ -1,101 +1,101 @@ -/**************************************************************************** - * configs/amber/src/pcblogic-internal.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __CONFIGS_AMBER_SRC_AMBER_INTERNAL_H -#define __CONFIGS_AMBER_SRC_AMBER_INTERNAL_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-Processor Definitions - ****************************************************************************/ -/* Configuration ************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Name: atmega_spiinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Amber Web Server. - * - ************************************************************************************/ - -#if defined(CONFIG_AVR_SPI1) || defined(CONFIG_AVR_SPI2) -EXTERN void weak_function atmega_spiinitialize(void); -#endif - -/************************************************************************************ - * Name: atmega_ledinit - * - * Description: - * Configure on-board LEDs if LED support has been selected. - * - ************************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -EXTERN void atmega_ledinit(void); -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __CONFIGS_AMBER_SRC_AMBER_INTERNAL_H */ +/**************************************************************************** + * configs/amber/src/amber-internal.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_AMBER_SRC_AMBER_INTERNAL_H +#define __CONFIGS_AMBER_SRC_AMBER_INTERNAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Name: atmega_spiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Amber Web Server. + * + ************************************************************************************/ + +#if defined(CONFIG_AVR_SPI1) || defined(CONFIG_AVR_SPI2) +EXTERN void weak_function atmega_spiinitialize(void); +#endif + +/************************************************************************************ + * Name: atmega_ledinit + * + * Description: + * Configure on-board LEDs if LED support has been selected. + * + ************************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +EXTERN void atmega_ledinit(void); +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_AMBER_SRC_AMBER_INTERNAL_H */ diff --git a/configs/amber/src/up_boot.c b/configs/amber/src/up_boot.c index ba80f4b8b0d2f49eef273b6f5d1c4bf5dbad0b2c..e21ab3b252cd15fccadad1ef145fd58e192822e2 100644 --- a/configs/amber/src/up_boot.c +++ b/configs/amber/src/up_boot.c @@ -3,7 +3,7 @@ * arch/mips/src/board/up_boot.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/avr32dev1/include/board.h b/configs/avr32dev1/include/board.h index c09adc56fa9cd3bc844f1524024c7fc379ddd8fb..008c5ffe34d04ca7c8a303342711f405493fbb10 100755 --- a/configs/avr32dev1/include/board.h +++ b/configs/avr32dev1/include/board.h @@ -3,7 +3,7 @@ * include/arch/board/board.h * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/avr32dev1/nsh/Make.defs b/configs/avr32dev1/nsh/Make.defs index 6be28bc8a8cfcf747c8df66407c666bba579a856..e2880edcaede4eba4c38ed1a3a81a92aacbaff0b 100755 --- a/configs/avr32dev1/nsh/Make.defs +++ b/configs/avr32dev1/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/avr32dev1/nsh/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/avr32dev1/nsh/defconfig b/configs/avr32dev1/nsh/defconfig index 4fc5089e2da6e9de1db0ddce34788469d83c5545..730d843918ffd6ff28e20c7e521fb07a177df110 100755 --- a/configs/avr32dev1/nsh/defconfig +++ b/configs/avr32dev1/nsh/defconfig @@ -2,7 +2,7 @@ # configs/avr32dev1/nsh/defconfig # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/avr32dev1/nsh/ld.script b/configs/avr32dev1/nsh/ld.script index 04a2087a1c6f0166b450a6bb74f76df289a284ae..1a7035a739760b6778c94e432060f9c268a09ad6 100755 --- a/configs/avr32dev1/nsh/ld.script +++ b/configs/avr32dev1/nsh/ld.script @@ -2,7 +2,7 @@ * configs/avr32dev1/nsh/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/avr32dev1/nsh/setenv.sh b/configs/avr32dev1/nsh/setenv.sh index c37cc08985dabd32e3b8a9229ca92691d6c7b7c9..b3ab164ad4d67d1de24c419cab19c0cb40423c7d 100755 --- a/configs/avr32dev1/nsh/setenv.sh +++ b/configs/avr32dev1/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/avr32dev1/nsh/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/avr32dev1/ostest/Make.defs b/configs/avr32dev1/ostest/Make.defs index 29e82fcd4e0d96be5f7e82183dcc0075d67d7964..b02597fe065287bc11e084c4b76b214baf791b20 100755 --- a/configs/avr32dev1/ostest/Make.defs +++ b/configs/avr32dev1/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/avr32dev1/ostest/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/avr32dev1/ostest/appconfig b/configs/avr32dev1/ostest/appconfig index e87ca0d13d8fee6ec249b3d4fd89113e8dfcf425..4e3f490dcf1274e3ebe99704a8ab3d3d81932ec4 100644 --- a/configs/avr32dev1/ostest/appconfig +++ b/configs/avr32dev1/ostest/appconfig @@ -2,7 +2,7 @@ # configs/avr32dev1/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/avr32dev1/ostest/defconfig b/configs/avr32dev1/ostest/defconfig index 0c0ffafaabf8e470a50b7ffa81ba7c2546752570..e8d8e378ad113b14d342e23e6573147c2075c269 100755 --- a/configs/avr32dev1/ostest/defconfig +++ b/configs/avr32dev1/ostest/defconfig @@ -2,7 +2,7 @@ # configs/avr32dev1/ostest/defconfig # # Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/avr32dev1/ostest/ld.script b/configs/avr32dev1/ostest/ld.script index d4d89881c856f7a1970ff097c1e5cdcef7e60edf..189a9ebe340f11b1da390949439b876e8b84bf0a 100755 --- a/configs/avr32dev1/ostest/ld.script +++ b/configs/avr32dev1/ostest/ld.script @@ -2,7 +2,7 @@ * configs/avr32dev1/ostest/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/avr32dev1/ostest/setenv.sh b/configs/avr32dev1/ostest/setenv.sh index e2eb1d2f0f12035e49ce5a48bc0510bac30e76a3..3c3bfcc4087e62964007c6b5a5eea578491a9197 100755 --- a/configs/avr32dev1/ostest/setenv.sh +++ b/configs/avr32dev1/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/avr32dev1/ostest/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/avr32dev1/src/Makefile b/configs/avr32dev1/src/Makefile index 282aaa8aa62a5d928e6b832c314b06d598059b6c..e49d457925ae090abf8e9c220fd1a9e3145e4416 100644 --- a/configs/avr32dev1/src/Makefile +++ b/configs/avr32dev1/src/Makefile @@ -2,7 +2,7 @@ # configs/avr32dev1/src/Makefile # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/avr32dev1/src/avr32dev1_internal.h b/configs/avr32dev1/src/avr32dev1_internal.h index 30f19c7dbce98ca2ca223662747025253963f357..31561c881c70d94a6d15ed4de01447f588fe522d 100644 --- a/configs/avr32dev1/src/avr32dev1_internal.h +++ b/configs/avr32dev1/src/avr32dev1_internal.h @@ -1,127 +1,127 @@ -/************************************************************************************ - * configs/avr32dev1/src/avr32dev1_internal.h - * arch/avr/src/board/avr32dev1_internal.n - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef _CONFIGS_AVR32DEV1_SRC_AVR32DEV1_INTERNAL_H -#define _CONFIGS_AVR32DEV1_SRC_AVR32DEV1_INTERNAL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include -#include "at32uc3_config.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* Configuration ********************************************************************/ - -#if (CONFIG_AVR32_GPIOIRQSETB & 4) == 1 -# define CONFIG_AVR32DEV_BUTTON1_IRQ 1 -#endif - -#if (CONFIG_AVR32_GPIOIRQSETB & 8) == 1 -# define CONFIG_AVR32DEV_BUTTON2_IRQ 1 -#endif - -/* AVRDEV1 GPIO Pin Definitions *****************************************************/ -/* LEDs - * - * The AVR32DEV1 board has 3 LEDs, two of which can be controlled through GPIO pins. - * - * PIN 13 PA7 LED1 - * PIN 14 PA8 LED2 - */ - -#define PINMUX_GPIO_LED1 (GPIO_ENABLE | GPIO_OUTPUT | GPIO_LOW | GPIO_PORTA | 7) -#define PINMUX_GPIO_LED2 (GPIO_ENABLE | GPIO_OUTPUT | GPIO_LOW | GPIO_PORTA | 8) - -/* BUTTONs - * - * The AVR32DEV1 board has 3 BUTTONs, two of which can be sensed through GPIO pins. - * - * PIN 24 PB2 KEY1 - * PIN 25 PB3 KEY2 - */ - -#if CONFIG_AVR32DEV_BUTTON1_IRQ -# define PINMUX_GPIO_BUTTON1 (GPIO_ENABLE | GPIO_INPUT | GPIO_INTR | \ - GPIO_INTMODE_BOTH | GPIO_GLITCH | GPIO_PORTB | 2) -# define GPIO_BUTTON1_IRQ AVR32_IRQ_GPIO_PB2 -#else -# define PINMUX_GPIO_BUTTON1 (GPIO_ENABLE | GPIO_INPUT | GPIO_GLITCH | \ - GPIO_PORTB | 2) -#endif - -#if CONFIG_AVR32DEV_BUTTON2_IRQ -# define PINMUX_GPIO_BUTTON2 (GPIO_ENABLE | GPIO_INPUT | GPIO_INTR | \ - GPIO_INTMODE_BOTH | GPIO_GLITCH | GPIO_PORTB | 3) -# define GPIO_BUTTON2_IRQ AVR32_IRQ_GPIO_PB3 -#else -# define PINMUX_GPIO_BUTTON2 (GPIO_ENABLE | GPIO_INPUT | GPIO_GLITCH | \ - GPIO_PORTB | 3) -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: up_ledinitialize - * - * Description: - * Configure on-board LEDs if LED support has been selected. - ************************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -extern void up_ledinitialize(void); -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* _CONFIGS_AVR32DEV1_SRC_AVR32DEV1_INTERNAL_H */ - +/************************************************************************************ + * configs/avr32dev1/src/avr32dev1_internal.h + * arch/avr/src/board/avr32dev1_internal.n + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef _CONFIGS_AVR32DEV1_SRC_AVR32DEV1_INTERNAL_H +#define _CONFIGS_AVR32DEV1_SRC_AVR32DEV1_INTERNAL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include "at32uc3_config.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Configuration ********************************************************************/ + +#if (CONFIG_AVR32_GPIOIRQSETB & 4) == 1 +# define CONFIG_AVR32DEV_BUTTON1_IRQ 1 +#endif + +#if (CONFIG_AVR32_GPIOIRQSETB & 8) == 1 +# define CONFIG_AVR32DEV_BUTTON2_IRQ 1 +#endif + +/* AVRDEV1 GPIO Pin Definitions *****************************************************/ +/* LEDs + * + * The AVR32DEV1 board has 3 LEDs, two of which can be controlled through GPIO pins. + * + * PIN 13 PA7 LED1 + * PIN 14 PA8 LED2 + */ + +#define PINMUX_GPIO_LED1 (GPIO_ENABLE | GPIO_OUTPUT | GPIO_LOW | GPIO_PORTA | 7) +#define PINMUX_GPIO_LED2 (GPIO_ENABLE | GPIO_OUTPUT | GPIO_LOW | GPIO_PORTA | 8) + +/* BUTTONs + * + * The AVR32DEV1 board has 3 BUTTONs, two of which can be sensed through GPIO pins. + * + * PIN 24 PB2 KEY1 + * PIN 25 PB3 KEY2 + */ + +#if CONFIG_AVR32DEV_BUTTON1_IRQ +# define PINMUX_GPIO_BUTTON1 (GPIO_ENABLE | GPIO_INPUT | GPIO_INTR | \ + GPIO_INTMODE_BOTH | GPIO_GLITCH | GPIO_PORTB | 2) +# define GPIO_BUTTON1_IRQ AVR32_IRQ_GPIO_PB2 +#else +# define PINMUX_GPIO_BUTTON1 (GPIO_ENABLE | GPIO_INPUT | GPIO_GLITCH | \ + GPIO_PORTB | 2) +#endif + +#if CONFIG_AVR32DEV_BUTTON2_IRQ +# define PINMUX_GPIO_BUTTON2 (GPIO_ENABLE | GPIO_INPUT | GPIO_INTR | \ + GPIO_INTMODE_BOTH | GPIO_GLITCH | GPIO_PORTB | 3) +# define GPIO_BUTTON2_IRQ AVR32_IRQ_GPIO_PB3 +#else +# define PINMUX_GPIO_BUTTON2 (GPIO_ENABLE | GPIO_INPUT | GPIO_GLITCH | \ + GPIO_PORTB | 3) +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: up_ledinitialize + * + * Description: + * Configure on-board LEDs if LED support has been selected. + ************************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +extern void up_ledinitialize(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* _CONFIGS_AVR32DEV1_SRC_AVR32DEV1_INTERNAL_H */ + diff --git a/configs/avr32dev1/src/up_boot.c b/configs/avr32dev1/src/up_boot.c index 44dd8ee5572e199a5500d96697ccf7b7ab73b61e..58716885384f7e5bbf4fd15dbdd112b8b0d63582 100644 --- a/configs/avr32dev1/src/up_boot.c +++ b/configs/avr32dev1/src/up_boot.c @@ -1,84 +1,84 @@ -/************************************************************************************ - * configs/avr32dev1/src/up_boot.c - * arch/avr/src/board/up_boot.c - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include - -#include - -#include "up_arch.h" -#include "up_internal.h" - -#include "at32uc3_internal.h" -#include "avr32dev1_internal.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: up_boardinitialize - * - * Description: - * All AVR32 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void up_boardinitialize(void) -{ - /* Configure SPI chip selects */ - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - up_ledinitialize(); -#endif -} +/************************************************************************************ + * configs/avr32dev1/src/up_boot.c + * arch/avr/src/board/up_boot.c + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "at32uc3_internal.h" +#include "avr32dev1_internal.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: up_boardinitialize + * + * Description: + * All AVR32 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void up_boardinitialize(void) +{ + /* Configure SPI chip selects */ + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + up_ledinitialize(); +#endif +} diff --git a/configs/avr32dev1/src/up_buttons.c b/configs/avr32dev1/src/up_buttons.c index 882eb6d86fa7e2f58497a022d1c2a3fc4e4497d9..5b488d72ee50680c2bfb85437085a80ccb598758 100644 --- a/configs/avr32dev1/src/up_buttons.c +++ b/configs/avr32dev1/src/up_buttons.c @@ -2,7 +2,7 @@ * configs/sam3u-ek/src/up_leds.c * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/avr32dev1/src/up_leds.c b/configs/avr32dev1/src/up_leds.c index c7f123a98a434b78ece3f0cfa3cfd7a202b7573d..62cde6b21071cc321dbe61dfb4b94125bdbdba5b 100644 --- a/configs/avr32dev1/src/up_leds.c +++ b/configs/avr32dev1/src/up_leds.c @@ -3,7 +3,7 @@ * arch/avr/src/board/up_leds.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/httpd/Make.defs b/configs/c5471evm/httpd/Make.defs index 549f98cd618bac2997da0ddc01a3f72d61786a5b..59a3bad44ff9d5f31891270db1d06ace1306c410 100644 --- a/configs/c5471evm/httpd/Make.defs +++ b/configs/c5471evm/httpd/Make.defs @@ -2,7 +2,7 @@ # configs/c5471evm/httpd/Make.defs # # Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/httpd/appconfig b/configs/c5471evm/httpd/appconfig index f08e3f7c9ec08b4daf3a9fc4190fc356b5955db7..1d9def12d26ca08e0484ada2439701d802414e87 100644 --- a/configs/c5471evm/httpd/appconfig +++ b/configs/c5471evm/httpd/appconfig @@ -2,7 +2,7 @@ # configs/c5471evm/httpd/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/httpd/defconfig b/configs/c5471evm/httpd/defconfig index 386936b7212bc02e2e25fa1c55f6e1f5bf0c0058..1e599d9a117fd2bb8ce482bb72815d29ce1e61ca 100644 --- a/configs/c5471evm/httpd/defconfig +++ b/configs/c5471evm/httpd/defconfig @@ -2,7 +2,7 @@ # configs/c5471evm/httpd/defconfig # # Copyright (C) 2007-2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/httpd/setenv.sh b/configs/c5471evm/httpd/setenv.sh index 20d841778874d961ed36acd24745704883fdcb9f..e9ab8023a6dde7003d120405ed51ca8808f074cd 100755 --- a/configs/c5471evm/httpd/setenv.sh +++ b/configs/c5471evm/httpd/setenv.sh @@ -2,7 +2,7 @@ # c5471evm/httpd/setenv.sh # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/include/board.h b/configs/c5471evm/include/board.h index 615d4723acb8098b6de035520999e004d6db7c7d..8ee4df9ccf04c01090a9e0eb15886214e0df6822 100644 --- a/configs/c5471evm/include/board.h +++ b/configs/c5471evm/include/board.h @@ -2,7 +2,7 @@ * arch/board.h * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/nettest/Make.defs b/configs/c5471evm/nettest/Make.defs index 0acc3af47d185e90e44e987dd321695310b53fd8..584a2e7fd7c17f31ae70a0b84aec07638ba597fb 100644 --- a/configs/c5471evm/nettest/Make.defs +++ b/configs/c5471evm/nettest/Make.defs @@ -2,7 +2,7 @@ # configs/c5471evm/nettest/Make.defs # # Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/nettest/appconfig b/configs/c5471evm/nettest/appconfig index f1050ef733ca148e207c269a79d29ce8bccef9d5..971aca007011bc2049aba2bb97be05d4a84ec757 100644 --- a/configs/c5471evm/nettest/appconfig +++ b/configs/c5471evm/nettest/appconfig @@ -2,7 +2,7 @@ # configs/c5471evm/nettest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/nettest/defconfig b/configs/c5471evm/nettest/defconfig index 19b865bf273fb23612b538d7a28d6d4bc1163be7..807a23f155bc455a1c6753b9a4a59c26c5acc02a 100644 --- a/configs/c5471evm/nettest/defconfig +++ b/configs/c5471evm/nettest/defconfig @@ -2,7 +2,7 @@ # configs/c5471evm/nettest/defconfig # # Copyright (C) 2007-2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/nettest/setenv.sh b/configs/c5471evm/nettest/setenv.sh index b9c7b6db27a85be8289531acfe044aa0b1169d79..67bcbc1f68ef31f52101306efdda8e4d8b99f06b 100755 --- a/configs/c5471evm/nettest/setenv.sh +++ b/configs/c5471evm/nettest/setenv.sh @@ -2,7 +2,7 @@ # c5471evm/nettest/setenv.sh # # Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/nsh/Make.defs b/configs/c5471evm/nsh/Make.defs index d5e4d54ac87f0da6fe77b0f0ff14a45c612cc4d2..1977cc23326d4f3e0c475502c9e254a80e70fba9 100644 --- a/configs/c5471evm/nsh/Make.defs +++ b/configs/c5471evm/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/c5471evm/nsh/Make.defs # # Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/nsh/defconfig b/configs/c5471evm/nsh/defconfig index 2bcb89b11566b7df8ae239f9096637cf444c5558..9f5bc6373a6ecb3ecdfe57adbdaabec7262a0a7f 100644 --- a/configs/c5471evm/nsh/defconfig +++ b/configs/c5471evm/nsh/defconfig @@ -2,7 +2,7 @@ # configs/c5471evm/nsh/defconfig # # Copyright (C) 2007-2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/nsh/setenv.sh b/configs/c5471evm/nsh/setenv.sh index 4ee41c934a945f2336b6c54fb7333be1b1cb7c0e..0693ede0ac2b7bec0b349fdaf26d6d84bb48388c 100755 --- a/configs/c5471evm/nsh/setenv.sh +++ b/configs/c5471evm/nsh/setenv.sh @@ -2,7 +2,7 @@ # c5471evm/nsh/setenv.sh # # Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/ostest/Make.defs b/configs/c5471evm/ostest/Make.defs index 7d147c9de3224802fa16f468e15dbc845b4d58d6..8773c7c68bfdccf790b10963d155f01421509bd4 100644 --- a/configs/c5471evm/ostest/Make.defs +++ b/configs/c5471evm/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/c5471evm/ostest/Make.defs # # Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/ostest/appconfig b/configs/c5471evm/ostest/appconfig index 97e30c0f8e85a267adfef5fd56e50ea95901c0b6..759015c6ac76e14857c16764264bd61b4238b54d 100644 --- a/configs/c5471evm/ostest/appconfig +++ b/configs/c5471evm/ostest/appconfig @@ -2,7 +2,7 @@ # configs/c5471evm/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/ostest/defconfig b/configs/c5471evm/ostest/defconfig index ac11ba1a1a96aedaf938f1eda06339e20191ff59..4921b59e6a661cec402445cbecf02977a0dbbf63 100644 --- a/configs/c5471evm/ostest/defconfig +++ b/configs/c5471evm/ostest/defconfig @@ -2,7 +2,7 @@ # configs/c5471evm/ostest/defconfig # # Copyright (C) 2007-2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/ostest/setenv.sh b/configs/c5471evm/ostest/setenv.sh index dc2c643764ea34cca57d7660c8d5ecc85567cdeb..e48437a4191576ff47e73998ccbaad01c6793d8e 100755 --- a/configs/c5471evm/ostest/setenv.sh +++ b/configs/c5471evm/ostest/setenv.sh @@ -2,7 +2,7 @@ # c5471evm/ostest/setenv.sh # # Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/src/Makefile b/configs/c5471evm/src/Makefile index fab7141e5874c1dd0faad3ce100c7e8b30e04166..57f52b4fee5278b5b2826f93ad9e213a0aa79810 100644 --- a/configs/c5471evm/src/Makefile +++ b/configs/c5471evm/src/Makefile @@ -2,7 +2,7 @@ # configs/c5471evm/src/Makefile # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/c5471evm/src/up_leds.c b/configs/c5471evm/src/up_leds.c index f733e9ffe0adcd6bb5827f93ed8536616ce42d80..72811a8711d42917204f44a5eca295a97db4d1a1 100644 --- a/configs/c5471evm/src/up_leds.c +++ b/configs/c5471evm/src/up_leds.c @@ -2,7 +2,7 @@ * up_leds.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/compal_e88/nsh_highram/Make.defs b/configs/compal_e88/nsh_highram/Make.defs index 4a9b3d200f25a2494b15deaf178f4ed4abb94f9d..d22675f1797f8175f8dafb44aef6804591492d3d 100644 --- a/configs/compal_e88/nsh_highram/Make.defs +++ b/configs/compal_e88/nsh_highram/Make.defs @@ -2,7 +2,7 @@ # configs/c5471evm/nsh/Make.defs # # Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/compal_e88/nsh_highram/appconfig b/configs/compal_e88/nsh_highram/appconfig index dd189fa1f7f72b40905829b15085171516f56522..00921c3614a6aa80d48a138b6e281a4a91106eed 100644 --- a/configs/compal_e88/nsh_highram/appconfig +++ b/configs/compal_e88/nsh_highram/appconfig @@ -2,7 +2,7 @@ # configs/compal_e88/nsh_highram/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/compal_e88/nsh_highram/setenv.sh b/configs/compal_e88/nsh_highram/setenv.sh index 4ee41c934a945f2336b6c54fb7333be1b1cb7c0e..0693ede0ac2b7bec0b349fdaf26d6d84bb48388c 100644 --- a/configs/compal_e88/nsh_highram/setenv.sh +++ b/configs/compal_e88/nsh_highram/setenv.sh @@ -2,7 +2,7 @@ # c5471evm/nsh/setenv.sh # # Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/compal_e88/src/Makefile b/configs/compal_e88/src/Makefile index 8996ca20a8196ed7798ef0df9e65eeed638b9a7b..13e1ae09f22818bffe4703fac7a1829638a799d9 100644 --- a/configs/compal_e88/src/Makefile +++ b/configs/compal_e88/src/Makefile @@ -2,7 +2,7 @@ # configs/compal_e88/src/Makefile # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Copyright (C) 2011 Stefan Richter. All rights reserved. # Author: Stefan Richter diff --git a/configs/compal_e99/nsh_compalram/Make.defs b/configs/compal_e99/nsh_compalram/Make.defs index 7a99f90bf57cc11abc8f47a5c5991c9a298d380c..0a93ce752576be9109f26033d175000cce5acdfb 100644 --- a/configs/compal_e99/nsh_compalram/Make.defs +++ b/configs/compal_e99/nsh_compalram/Make.defs @@ -2,7 +2,7 @@ # configs/c5471evm/nsh/Make.defs # # Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/compal_e99/nsh_compalram/appconfig b/configs/compal_e99/nsh_compalram/appconfig index b94469ee004bdb74bafe8e4d067f917ccf6e35b4..8df90adb0a61eaebe4c7a7cd3c2f881a1ac6b842 100644 --- a/configs/compal_e99/nsh_compalram/appconfig +++ b/configs/compal_e99/nsh_compalram/appconfig @@ -2,7 +2,7 @@ # configs/compal_e99/nsh_compalram/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/compal_e99/nsh_compalram/setenv.sh b/configs/compal_e99/nsh_compalram/setenv.sh index 4ee41c934a945f2336b6c54fb7333be1b1cb7c0e..0693ede0ac2b7bec0b349fdaf26d6d84bb48388c 100644 --- a/configs/compal_e99/nsh_compalram/setenv.sh +++ b/configs/compal_e99/nsh_compalram/setenv.sh @@ -2,7 +2,7 @@ # c5471evm/nsh/setenv.sh # # Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/compal_e99/nsh_highram/Make.defs b/configs/compal_e99/nsh_highram/Make.defs index 4a9b3d200f25a2494b15deaf178f4ed4abb94f9d..d22675f1797f8175f8dafb44aef6804591492d3d 100644 --- a/configs/compal_e99/nsh_highram/Make.defs +++ b/configs/compal_e99/nsh_highram/Make.defs @@ -2,7 +2,7 @@ # configs/c5471evm/nsh/Make.defs # # Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/compal_e99/nsh_highram/appconfig b/configs/compal_e99/nsh_highram/appconfig index 65eed81f792ed628f433d98dd83bd65e9dda784f..241253f8cd1a5dd29cf16f153a797eaa9562117b 100644 --- a/configs/compal_e99/nsh_highram/appconfig +++ b/configs/compal_e99/nsh_highram/appconfig @@ -2,7 +2,7 @@ # configs/compal_e99/nsh_highram/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/compal_e99/nsh_highram/setenv.sh b/configs/compal_e99/nsh_highram/setenv.sh index 4ee41c934a945f2336b6c54fb7333be1b1cb7c0e..0693ede0ac2b7bec0b349fdaf26d6d84bb48388c 100644 --- a/configs/compal_e99/nsh_highram/setenv.sh +++ b/configs/compal_e99/nsh_highram/setenv.sh @@ -2,7 +2,7 @@ # c5471evm/nsh/setenv.sh # # Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/compal_e99/src/Makefile b/configs/compal_e99/src/Makefile index 97569236fe4d848c611fc1a2b8a276201bee1680..2a5ad6783e9a96aae01662be60a972e564bca92d 100644 --- a/configs/compal_e99/src/Makefile +++ b/configs/compal_e99/src/Makefile @@ -2,7 +2,7 @@ # configs/compal_e99/src/Makefile # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Copyright (C) 2011 Stefan Richter. All rights reserved. # Author: Stefan Richter diff --git a/configs/demo9s12ne64/include/board.h b/configs/demo9s12ne64/include/board.h index ee190731cbb0769bb1c500ed97ea3bce8c17cf8f..501b2f8e096d152846748cacfd8de66828cd64cf 100755 --- a/configs/demo9s12ne64/include/board.h +++ b/configs/demo9s12ne64/include/board.h @@ -3,7 +3,7 @@ * include/arch/board/board.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/demo9s12ne64/ostest/Make.defs b/configs/demo9s12ne64/ostest/Make.defs index 1ae7b5f3944566c7aa1ad0e2334c070a4835bcff..58d502e9672f2c107a76403b55322d7b4773d827 100755 --- a/configs/demo9s12ne64/ostest/Make.defs +++ b/configs/demo9s12ne64/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/demo9s12ne64/ostest/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/demo9s12ne64/ostest/appconfig b/configs/demo9s12ne64/ostest/appconfig index 0fcb806263a08a1395b25e23ab1f70f80d0a5253..f101d01ece52e25b7c5728d7e64faba8b0dfc7b4 100644 --- a/configs/demo9s12ne64/ostest/appconfig +++ b/configs/demo9s12ne64/ostest/appconfig @@ -2,7 +2,7 @@ # configs/demo9s12ne64/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/demo9s12ne64/ostest/ld.script.banked b/configs/demo9s12ne64/ostest/ld.script.banked index 17c73dd53e1f1e6b2cc42b3b96d07ee3fb9e1f1e..798658f39e6a70812e9e72185ff1c212060ea7a3 100755 --- a/configs/demo9s12ne64/ostest/ld.script.banked +++ b/configs/demo9s12ne64/ostest/ld.script.banked @@ -2,7 +2,7 @@ * configs/demo9s12ne64/ostest/ld.script * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/demo9s12ne64/ostest/ld.script.nonbanked b/configs/demo9s12ne64/ostest/ld.script.nonbanked index 8e2a2768841429332c256a486bd9be96deb7f4e8..ab36d1c4e2cda35246c9acc1b0b6f016c6b2b324 100755 --- a/configs/demo9s12ne64/ostest/ld.script.nonbanked +++ b/configs/demo9s12ne64/ostest/ld.script.nonbanked @@ -2,7 +2,7 @@ * configs/demo9s12ne64/ostest/ld.script * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/demo9s12ne64/ostest/setenv.sh b/configs/demo9s12ne64/ostest/setenv.sh index 0010997b7c0f3fdb79a74b3c9ed4e05827e007ad..8f47650ca5e5edeb10a44cd2ebba128cb4106028 100755 --- a/configs/demo9s12ne64/ostest/setenv.sh +++ b/configs/demo9s12ne64/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/demo9s12ne64/ostest/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/demo9s12ne64/src/Makefile b/configs/demo9s12ne64/src/Makefile index 37dc21150758861c58d5262bc1d28dd56648559b..7ab12080cc8a914b98245c4c6443981a004d0aaf 100644 --- a/configs/demo9s12ne64/src/Makefile +++ b/configs/demo9s12ne64/src/Makefile @@ -2,7 +2,7 @@ # configs/demo9s12ne64/src/Makefile # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/demo9s12ne64/src/demo9s12ne64.h b/configs/demo9s12ne64/src/demo9s12ne64.h index 4ce8b46aaac82244b65a90f06756ae985228bb06..0a6c8e2c9eca8592cc578ee1f072b8cb58405e44 100644 --- a/configs/demo9s12ne64/src/demo9s12ne64.h +++ b/configs/demo9s12ne64/src/demo9s12ne64.h @@ -1,91 +1,91 @@ -/************************************************************************************ - * configs/demo9s12ne64/src/demo9s12ne64.h - * arch/arm/src/board/demo9s12ne64.n - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __CONFIGS_DEMO9S12NE64_SRC_DEMO9S12NE64_H -#define __CONFIGS_DEMO9S12NE64_SRC_DEMO9S12NE64_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* DEMO9S12NE64 GPIOs ***************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ -/************************************************************************************ - * Name: up_ledinit - * - * Description: - * Configure and initialize on-board LEDs - * - ************************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -extern void up_ledinit(void); -#endif - -/************************************************************************************ - * Name: hcs12_spiinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the STM3210E-EVAL board. - * - ************************************************************************************/ - -extern void weak_function hcs12_spiinitialize(void); - - -#endif /* __ASSEMBLY__ */ -#endif /* __CONFIGS_DEMO9S12NE64_SRC_DEMO9S12NE64_H */ - +/************************************************************************************ + * configs/demo9s12ne64/src/demo9s12ne64.h + * arch/arm/src/board/demo9s12ne64.n + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_DEMO9S12NE64_SRC_DEMO9S12NE64_H +#define __CONFIGS_DEMO9S12NE64_SRC_DEMO9S12NE64_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* DEMO9S12NE64 GPIOs ***************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ +/************************************************************************************ + * Name: up_ledinit + * + * Description: + * Configure and initialize on-board LEDs + * + ************************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +extern void up_ledinit(void); +#endif + +/************************************************************************************ + * Name: hcs12_spiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the STM3210E-EVAL board. + * + ************************************************************************************/ + +extern void weak_function hcs12_spiinitialize(void); + + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_DEMO9S12NE64_SRC_DEMO9S12NE64_H */ + diff --git a/configs/demo9s12ne64/src/up_boot.c b/configs/demo9s12ne64/src/up_boot.c index 61313618aee42b832edb25605653587f84201bc8..a98bb0d90989b6813819b741ff5e766b41e03dd7 100644 --- a/configs/demo9s12ne64/src/up_boot.c +++ b/configs/demo9s12ne64/src/up_boot.c @@ -1,89 +1,89 @@ -/************************************************************************************ - * configs/demo9s12ne64/src/up_boot.c - * arch/arm/src/board/up_boot.c - * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include - -#include - -#include "demo9s12ne64.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: hcs12_boardinitialize - * - * Description: - * All HCS12 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void hcs12_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function - * hcs12_spiinitialize() has been brought into the link. - */ - -#if defined(CONFIG_INCLUDE_HCS12_ARCH_SPI) - if (hcs12_spiinitialize) - { - hcs12_spiinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - up_ledinit(); -#endif -} +/************************************************************************************ + * configs/demo9s12ne64/src/up_boot.c + * arch/arm/src/board/up_boot.c + * + * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +#include "demo9s12ne64.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: hcs12_boardinitialize + * + * Description: + * All HCS12 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void hcs12_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function + * hcs12_spiinitialize() has been brought into the link. + */ + +#if defined(CONFIG_INCLUDE_HCS12_ARCH_SPI) + if (hcs12_spiinitialize) + { + hcs12_spiinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + up_ledinit(); +#endif +} diff --git a/configs/demo9s12ne64/src/up_buttons.c b/configs/demo9s12ne64/src/up_buttons.c index fa015585de5f5696542a86c8bac1351bf3f01933..b895f45a363438304a05ac705883b8f8a1797d37 100644 --- a/configs/demo9s12ne64/src/up_buttons.c +++ b/configs/demo9s12ne64/src/up_buttons.c @@ -2,7 +2,7 @@ * configs/demo9s12ne64/src/up_leds.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/demo9s12ne64/src/up_leds.c b/configs/demo9s12ne64/src/up_leds.c index f84f83cddc12a0716a75ecc0603a34b7c63026dc..1984d8165250fb1a8db4db480df84bf15625dc60 100644 --- a/configs/demo9s12ne64/src/up_leds.c +++ b/configs/demo9s12ne64/src/up_leds.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_leds.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/demo9s12ne64/src/up_nsh.c b/configs/demo9s12ne64/src/up_nsh.c index 451ea901d6bb1fb9fef2fac0c5310cffad8ba415..7e53f7f076eb66dd8186f5c4c456a66f5a377893 100644 --- a/configs/demo9s12ne64/src/up_nsh.c +++ b/configs/demo9s12ne64/src/up_nsh.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_nsh.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/demo9s12ne64/src/up_spi.c b/configs/demo9s12ne64/src/up_spi.c index 5f33d0776a73d94874f6f04a1ccc33237f541d83..8514b48ed15a000ceedbec60160fb83c090a6b3d 100644 --- a/configs/demo9s12ne64/src/up_spi.c +++ b/configs/demo9s12ne64/src/up_spi.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_spi.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ea3131/include/board.h b/configs/ea3131/include/board.h index 7e0a01b6acff1322ca53b67182582993df04cb57..2154af545bf76cba2870b92cdad377e572ea648f 100644 --- a/configs/ea3131/include/board.h +++ b/configs/ea3131/include/board.h @@ -3,7 +3,7 @@ * include/arch/board/board.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ea3131/include/board_memorymap.h b/configs/ea3131/include/board_memorymap.h index 2604865c10ab70d5121667b5ccc870ee431f12c6..69fe0ae961d8f4fab838ed126b82d2abb6cced00 100644 --- a/configs/ea3131/include/board_memorymap.h +++ b/configs/ea3131/include/board_memorymap.h @@ -3,7 +3,7 @@ * include/arch/board/board_memorymap.h * * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ea3131/locked/Makefile b/configs/ea3131/locked/Makefile index 1108132ac0d901c8eb55e2aa67cd4ac16303ff90..79fa82610c5b35c6d9afbc8e4f1a1dcb16513571 100644 --- a/configs/ea3131/locked/Makefile +++ b/configs/ea3131/locked/Makefile @@ -2,7 +2,7 @@ # configs/ea3131/locked/Makefile # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ea3131/locked/ld-locked.script b/configs/ea3131/locked/ld-locked.script index ddc865b2fae5e509f9da01bd1a5b94e20bf423ac..955505364f4b54d23188a59e60657bd4eed1f690 100644 --- a/configs/ea3131/locked/ld-locked.script +++ b/configs/ea3131/locked/ld-locked.script @@ -2,7 +2,7 @@ * configs/ea3131/locked/ld-locked.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ea3131/nsh/Make.defs b/configs/ea3131/nsh/Make.defs index bff75e8e0128ff52125c4e8f551feeec3b5d6f59..01b83a5a638821330649aff6c3a7e0c09f75bc79 100644 --- a/configs/ea3131/nsh/Make.defs +++ b/configs/ea3131/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/ea3131/nsh/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ea3131/nsh/setenv.sh b/configs/ea3131/nsh/setenv.sh index 671df47f1900e0311c35f34599fb3f57f5dfe32c..00b1e0c4365d99f58ee92e8d16a5957163fc7a4e 100755 --- a/configs/ea3131/nsh/setenv.sh +++ b/configs/ea3131/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/ea3131/nsh/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ea3131/ostest/appconfig b/configs/ea3131/ostest/appconfig index aa56dd4c1c30c3817b47f8f8f9529eb8586d0149..c665ea7b2a649ed91b90bde87398261b988a5976 100644 --- a/configs/ea3131/ostest/appconfig +++ b/configs/ea3131/ostest/appconfig @@ -2,7 +2,7 @@ # configs/ea3131/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ea3131/ostest/setenv.sh b/configs/ea3131/ostest/setenv.sh index a8155ab79c977a5dce837c036ab87f52e49dd3fd..cd894a300af92f60c7312b6889144b5dafdea075 100755 --- a/configs/ea3131/ostest/setenv.sh +++ b/configs/ea3131/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/ea3131/ostest/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ea3131/pgnsh/setenv.sh b/configs/ea3131/pgnsh/setenv.sh index 82205c45238621a87fda9a0b2971789240c17ff8..ead7c9ffadaa040979e16d84c2a0199b47886108 100755 --- a/configs/ea3131/pgnsh/setenv.sh +++ b/configs/ea3131/pgnsh/setenv.sh @@ -2,7 +2,7 @@ # configs/ea3131/pgnsh/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ea3131/src/up_buttons.c b/configs/ea3131/src/up_buttons.c index f7c13b93aac8cbf1e1d76b9ed0369cd5d10c0fb3..8dd468a9e607c79c26c56f1975a24afef9773403 100644 --- a/configs/ea3131/src/up_buttons.c +++ b/configs/ea3131/src/up_buttons.c @@ -2,7 +2,7 @@ * configs/ea3131/src/up_leds.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ea3131/src/up_clkinit.c b/configs/ea3131/src/up_clkinit.c index a0eba9c75d2b7a00bd95b2f98a3e562c2887bce9..247844a81bc7a3bbe3c0346aa62075661ef30765 100644 --- a/configs/ea3131/src/up_clkinit.c +++ b/configs/ea3131/src/up_clkinit.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_clkinit.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009 diff --git a/configs/ea3131/src/up_leds.c b/configs/ea3131/src/up_leds.c index a0bec01b02d6fcfeb107e603bcf145f2c386afb2..ab22c7657cb81893512c9d31a2799bbd2744763e 100644 --- a/configs/ea3131/src/up_leds.c +++ b/configs/ea3131/src/up_leds.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_leds.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ea3131/src/up_usbmsc.c b/configs/ea3131/src/up_usbmsc.c index b1d07ac55f9568422c26c48fc88fbdd9857c9bdb..5f4850ea1c6e6d053c6dc1ed12498039cf952ba3 100644 --- a/configs/ea3131/src/up_usbmsc.c +++ b/configs/ea3131/src/up_usbmsc.c @@ -2,7 +2,7 @@ * configs/ea3131/src/up_usbmsc.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Configure and register the SAM3U MMC/SD SDIO block driver. * diff --git a/configs/ea3131/tools/Makefile b/configs/ea3131/tools/Makefile index 6c3362d8c17329430e4ae2a7b01d0c9620b9e7f1..0d6f43d09e847b5c48248cfc3441a0b6e3fabbc3 100644 --- a/configs/ea3131/tools/Makefile +++ b/configs/ea3131/tools/Makefile @@ -2,7 +2,7 @@ # configs/ea3131/tools/Makefile # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ea3131/tools/lpchdr.c b/configs/ea3131/tools/lpchdr.c index 9325c881359d3cb9c83b96b7492a5cbce83cd3d4..d21cf3906f7bd9fd8c0a5c522db4223b3ffbd798 100644 --- a/configs/ea3131/tools/lpchdr.c +++ b/configs/ea3131/tools/lpchdr.c @@ -2,7 +2,7 @@ * configs/ea3131/tools/lpchdr.c * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ea3131/tools/lpchdr.h b/configs/ea3131/tools/lpchdr.h index 46cc91076236786598fe42d7cb667eaee6cb6ac7..7ada6bb35953d668a3f0dc3f2cd48b1c12f6493e 100644 --- a/configs/ea3131/tools/lpchdr.h +++ b/configs/ea3131/tools/lpchdr.h @@ -2,7 +2,7 @@ * configs/ea3131/tools/lpchdr.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ea3131/usbserial/appconfig b/configs/ea3131/usbserial/appconfig index 32c385dc896b59941d5f96db5a46f366cd93dff2..76ec23eb0cb60bca4a17920a888c72f6f1e09dbf 100644 --- a/configs/ea3131/usbserial/appconfig +++ b/configs/ea3131/usbserial/appconfig @@ -2,7 +2,7 @@ # configs/ea3131/usbserial/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ea3131/usbserial/setenv.sh b/configs/ea3131/usbserial/setenv.sh index d48e40756de2344d66bc23d2a1e4af885f555e3b..69a6bb4421dd76765993bf8a074c499551f1fe0e 100755 --- a/configs/ea3131/usbserial/setenv.sh +++ b/configs/ea3131/usbserial/setenv.sh @@ -2,7 +2,7 @@ # configs/ea3131/usbserial/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ea3131/usbstorage/appconfig b/configs/ea3131/usbstorage/appconfig index 9022fd3ad1541b3c60475e5736de76d5f8d4d2b1..8db7e05d68f48bb132a8d96069caa0d6719309ff 100644 --- a/configs/ea3131/usbstorage/appconfig +++ b/configs/ea3131/usbstorage/appconfig @@ -2,7 +2,7 @@ # configs/ea3131/usbstorage/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ea3131/usbstorage/setenv.sh b/configs/ea3131/usbstorage/setenv.sh index 2a20e7ba9ce1e8b56c6216456288389b7d3851a8..6481502283b753b14aec74013228c72aa340a15d 100755 --- a/configs/ea3131/usbstorage/setenv.sh +++ b/configs/ea3131/usbstorage/setenv.sh @@ -2,7 +2,7 @@ # configs/ea3131/usbstorage/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/httpd/Make.defs b/configs/eagle100/httpd/Make.defs index b19de754721502116185a7124e7755598c2bccd3..6d9f86db5778017dd4f94127af5c31e0a2d6c4cb 100644 --- a/configs/eagle100/httpd/Make.defs +++ b/configs/eagle100/httpd/Make.defs @@ -2,7 +2,7 @@ # configs/eagle100/httpd/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/httpd/appconfig b/configs/eagle100/httpd/appconfig index adfe0291bf219cdb81eaa42b86b8d8634e21dee1..fbb81805db95d46733af74e3b667e341b7c69f8a 100644 --- a/configs/eagle100/httpd/appconfig +++ b/configs/eagle100/httpd/appconfig @@ -2,7 +2,7 @@ # configs/eagle100/httpd/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/httpd/defconfig b/configs/eagle100/httpd/defconfig index 93565d4aa8d7c424eede066484396cc8243ffe47..3ad9220977dffa9577061e9c44f6b1c74e161474 100644 --- a/configs/eagle100/httpd/defconfig +++ b/configs/eagle100/httpd/defconfig @@ -2,7 +2,7 @@ # configs/eagle100/httpd/defconfig # # Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/httpd/setenv.sh b/configs/eagle100/httpd/setenv.sh index 337ecc9676972743590ae15252916a32c892d712..e17655b0a36df958a3e49782923a22901050303f 100755 --- a/configs/eagle100/httpd/setenv.sh +++ b/configs/eagle100/httpd/setenv.sh @@ -2,7 +2,7 @@ # configs/eagle100/httpd/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/include/board.h b/configs/eagle100/include/board.h index d05d45f43a9f40d07d686a74afacf2b8575552a5..40a12327fb60c3d1f9ed6d8acf0ef0025e988f69 100644 --- a/configs/eagle100/include/board.h +++ b/configs/eagle100/include/board.h @@ -3,7 +3,7 @@ * include/arch/board/board.h * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/eagle100/nettest/Make.defs b/configs/eagle100/nettest/Make.defs index 295d0b0cc904b50b66127107d3117780b6553ebb..2bfabeade969ab3fcbc7f589f73569cea3c19481 100644 --- a/configs/eagle100/nettest/Make.defs +++ b/configs/eagle100/nettest/Make.defs @@ -2,7 +2,7 @@ # configs/eagle100/nettest/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/nettest/appconfig b/configs/eagle100/nettest/appconfig index 9c6b56824797e83d5468a6740562bb79ce17c2c0..e5ff507b89b7fa1ec7fcc479e6475a3c0124a26a 100644 --- a/configs/eagle100/nettest/appconfig +++ b/configs/eagle100/nettest/appconfig @@ -2,7 +2,7 @@ # configs/eagle100/nettest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/nettest/setenv.sh b/configs/eagle100/nettest/setenv.sh index 555e6b553a9cc4c74d06758a899bf744a77312fc..ce89c68aac6421eb843fc1bd6d1e8c8e9c40c232 100755 --- a/configs/eagle100/nettest/setenv.sh +++ b/configs/eagle100/nettest/setenv.sh @@ -2,7 +2,7 @@ # configs/eagle100/nettest/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/nsh/Make.defs b/configs/eagle100/nsh/Make.defs index 7fbd738f5d68b0867d461e51e7bc957fe1285d05..066b00ceea57b5efa9b5c8b0ada81ca856e69c2e 100644 --- a/configs/eagle100/nsh/Make.defs +++ b/configs/eagle100/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/eagle100/nsh/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/nsh/setenv.sh b/configs/eagle100/nsh/setenv.sh index 6e487c2a358c8437b5b930fd6eea7247f6fd8351..93396cb736b59a279475f1becd7c9b33c8310cff 100755 --- a/configs/eagle100/nsh/setenv.sh +++ b/configs/eagle100/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/eagle100/nsh/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/nxflat/Make.defs b/configs/eagle100/nxflat/Make.defs index 2c7ef9583810ddd3e84d8da536ba17d1a59de127..2cd0a3b6cfb0721f0484773720e347f73cbb1193 100644 --- a/configs/eagle100/nxflat/Make.defs +++ b/configs/eagle100/nxflat/Make.defs @@ -2,7 +2,7 @@ # configs/eagle100/nxflat/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/nxflat/appconfig b/configs/eagle100/nxflat/appconfig index dae39407d243e89c33b932629f4b4b6e213e2668..44dc4bf96d2b8961639229d828a5129f42828b1b 100644 --- a/configs/eagle100/nxflat/appconfig +++ b/configs/eagle100/nxflat/appconfig @@ -2,7 +2,7 @@ # configs/eagle100/nxflat/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/nxflat/defconfig b/configs/eagle100/nxflat/defconfig index f917f91a0f6d5efb00d70c38f8c1d349b84ce9e6..7befde172c786ea7402057e498d761fd8c3664d3 100644 --- a/configs/eagle100/nxflat/defconfig +++ b/configs/eagle100/nxflat/defconfig @@ -2,7 +2,7 @@ # configs/eagle100/nxflat/defconfig # # Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/nxflat/setenv.sh b/configs/eagle100/nxflat/setenv.sh index 4e0c8e040b0b3181d71fec66b1e6e7c3291595b5..39afe386f7ed06f2dfd0e35ed6629181ab4f135e 100755 --- a/configs/eagle100/nxflat/setenv.sh +++ b/configs/eagle100/nxflat/setenv.sh @@ -2,7 +2,7 @@ # configs/eagle100/nxflat/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/ostest/Make.defs b/configs/eagle100/ostest/Make.defs index edc1afd19a39ffd3f56afa4ba4d060930d01b928..1694942a89fb1c950f2cff8e409e1afb9dc6a4a0 100644 --- a/configs/eagle100/ostest/Make.defs +++ b/configs/eagle100/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/eagle100/ostest/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/ostest/appconfig b/configs/eagle100/ostest/appconfig index 7bf44797adcfedc09e237eb205906fe174365d5b..1be133dec8f253fa382726a9a4ea039fc3922a2e 100644 --- a/configs/eagle100/ostest/appconfig +++ b/configs/eagle100/ostest/appconfig @@ -2,7 +2,7 @@ # configs/eagle100/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/ostest/setenv.sh b/configs/eagle100/ostest/setenv.sh index b370ce372639c1934a50a3cd9766a8446de7ad3a..c3c1f581dbdebd54ddd955831c9b0f19efc15176 100755 --- a/configs/eagle100/ostest/setenv.sh +++ b/configs/eagle100/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/eagle100/ostest/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/src/Makefile b/configs/eagle100/src/Makefile index 23311f40bf49c3b647064b94806ee93b415bca1f..123aa8139812af48dc9cf5fddb76520f9cc68fac 100644 --- a/configs/eagle100/src/Makefile +++ b/configs/eagle100/src/Makefile @@ -2,7 +2,7 @@ # configs/eagle100/src/Makefile # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/src/eagle100_internal.h b/configs/eagle100/src/eagle100_internal.h index 68a64bde19428edd3a58c2983d3219d6f98086a6..88d2bf3b0e8f201e8bcdc42d0f5355385bb5d484 100644 --- a/configs/eagle100/src/eagle100_internal.h +++ b/configs/eagle100/src/eagle100_internal.h @@ -1,106 +1,106 @@ -/************************************************************************************ - * configs/eagle100/src/eagle100_internal.h - * arch/arm/src/board/eagle100_internal.n - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __CONFIGS_EAGLE100_SRC_EAGLE100_INTERNAL_H -#define __CONFIGS_EAGLE100_SRC_EAGLE100_INTERNAL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#include "chip.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* How many SSI modules does this chip support? The LM3S6918 supports 2 SSI - * modules (others may support more -- in such case, the following must be - * expanded). - */ - -#if LM3S_NSSI == 0 -# undef CONFIG_SSI0_DISABLE -# define CONFIG_SSI0_DISABLE 1 -# undef CONFIG_SSI1_DISABLE -# define CONFIG_SSI1_DISABLE 1 -#elif LM3S_NSSI == 1 -# undef CONFIG_SSI1_DISABLE -# define CONFIG_SSI1_DISABLE 1 -#endif - -/* Eagle-100 GPIOs ******************************************************************/ - -/* GPIO for microSD card chip select */ - -#define SDCCS_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STDWPU | GPIO_STRENGTH_4MA | \ - GPIO_VALUE_ONE | GPIO_PORTG | 1) -#define LED_GPIO (GPIO_FUNC_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTE | 1) - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Name: lm3s_ssiinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Eagle100 board. - * - ************************************************************************************/ - -extern void weak_function lm3s_ssiinitialize(void); - -/**************************************************************************** - * Name: up_ledinit - * - * Description: - * Initialize on-board LEDs. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -extern void up_ledinit(void); -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __CONFIGS_EAGLE100_SRC_EAGLE100_INTERNAL_H */ - +/************************************************************************************ + * configs/eagle100/src/eagle100_internal.h + * arch/arm/src/board/eagle100_internal.n + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_EAGLE100_SRC_EAGLE100_INTERNAL_H +#define __CONFIGS_EAGLE100_SRC_EAGLE100_INTERNAL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "chip.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* How many SSI modules does this chip support? The LM3S6918 supports 2 SSI + * modules (others may support more -- in such case, the following must be + * expanded). + */ + +#if LM3S_NSSI == 0 +# undef CONFIG_SSI0_DISABLE +# define CONFIG_SSI0_DISABLE 1 +# undef CONFIG_SSI1_DISABLE +# define CONFIG_SSI1_DISABLE 1 +#elif LM3S_NSSI == 1 +# undef CONFIG_SSI1_DISABLE +# define CONFIG_SSI1_DISABLE 1 +#endif + +/* Eagle-100 GPIOs ******************************************************************/ + +/* GPIO for microSD card chip select */ + +#define SDCCS_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STDWPU | GPIO_STRENGTH_4MA | \ + GPIO_VALUE_ONE | GPIO_PORTG | 1) +#define LED_GPIO (GPIO_FUNC_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTE | 1) + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Name: lm3s_ssiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Eagle100 board. + * + ************************************************************************************/ + +extern void weak_function lm3s_ssiinitialize(void); + +/**************************************************************************** + * Name: up_ledinit + * + * Description: + * Initialize on-board LEDs. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +extern void up_ledinit(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_EAGLE100_SRC_EAGLE100_INTERNAL_H */ + diff --git a/configs/eagle100/src/up_boot.c b/configs/eagle100/src/up_boot.c index 61dab1653205c0ac82f9a3530d038986905ba839..44f003e0b0c50df6d3fc20eb4d7b21faac638a51 100644 --- a/configs/eagle100/src/up_boot.c +++ b/configs/eagle100/src/up_boot.c @@ -1,91 +1,91 @@ -/************************************************************************************ - * configs/eagle100/src/up_boot.c - * arch/arm/src/board/up_boot.c - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include - -#include - -#include "up_arch.h" -#include "eagle100_internal.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: lm3s_boardinitialize - * - * Description: - * All LM3S architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - ************************************************************************************/ - -void lm3s_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SSI is not disabled, and 2) the weak function - * lm3s_ssiinitialize() has been brought into the link. - */ - -/* The Eagle100 microSD CS is on SSI0 */ - -#if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */ - if (lm3s_ssiinitialize) - { - lm3s_ssiinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - up_ledinit(); -#endif -} +/************************************************************************************ + * configs/eagle100/src/up_boot.c + * arch/arm/src/board/up_boot.c + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +#include "up_arch.h" +#include "eagle100_internal.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lm3s_boardinitialize + * + * Description: + * All LM3S architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + ************************************************************************************/ + +void lm3s_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SSI is not disabled, and 2) the weak function + * lm3s_ssiinitialize() has been brought into the link. + */ + +/* The Eagle100 microSD CS is on SSI0 */ + +#if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */ + if (lm3s_ssiinitialize) + { + lm3s_ssiinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + up_ledinit(); +#endif +} diff --git a/configs/eagle100/src/up_ethernet.c b/configs/eagle100/src/up_ethernet.c index 54145ff589e8ffe7bc773a46839c1ec167142248..a071fcca9a3592db0ec4366b81847c02184ac25b 100644 --- a/configs/eagle100/src/up_ethernet.c +++ b/configs/eagle100/src/up_ethernet.c @@ -1,98 +1,98 @@ -/************************************************************************************ - * configs/eagle100/src/up_ethernet.c - * arch/arm/src/board/up_ethernet.c - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "up_arch.h" -#include "chip.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: lm3s_ethernetmac - * - * Description: - * For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile - * USER0 and USER1 registers. If CONFIG_LM3S_BOARDMAC is defined, this function - * will obtain the MAC address from these registers. - * - ************************************************************************************/ - -#ifdef CONFIG_LM3S_BOARDMAC -void lm3s_ethernetmac(struct ether_addr *ethaddr) -{ - uint32_t user0; - uint32_t user1; - - /* Get the current value of the user registers */ - - user0 = getreg32(LM3S_FLASH_USERREG0); - user1 = getreg32(LM3S_FLASH_USERREG1); - - nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff); - DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff); - - /* Re-format that MAC address the way that uIP expects to see it */ - - ethaddr->ether_addr_octet[0] = ((user0 >> 0) & 0xff); - ethaddr->ether_addr_octet[1] = ((user0 >> 8) & 0xff); - ethaddr->ether_addr_octet[2] = ((user0 >> 16) & 0xff); - ethaddr->ether_addr_octet[3] = ((user1 >> 0) & 0xff); - ethaddr->ether_addr_octet[4] = ((user1 >> 8) & 0xff); - ethaddr->ether_addr_octet[5] = ((user1 >> 16) & 0xff); -} -#endif +/************************************************************************************ + * configs/eagle100/src/up_ethernet.c + * arch/arm/src/board/up_ethernet.c + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "chip.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lm3s_ethernetmac + * + * Description: + * For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile + * USER0 and USER1 registers. If CONFIG_LM3S_BOARDMAC is defined, this function + * will obtain the MAC address from these registers. + * + ************************************************************************************/ + +#ifdef CONFIG_LM3S_BOARDMAC +void lm3s_ethernetmac(struct ether_addr *ethaddr) +{ + uint32_t user0; + uint32_t user1; + + /* Get the current value of the user registers */ + + user0 = getreg32(LM3S_FLASH_USERREG0); + user1 = getreg32(LM3S_FLASH_USERREG1); + + nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff); + DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff); + + /* Re-format that MAC address the way that uIP expects to see it */ + + ethaddr->ether_addr_octet[0] = ((user0 >> 0) & 0xff); + ethaddr->ether_addr_octet[1] = ((user0 >> 8) & 0xff); + ethaddr->ether_addr_octet[2] = ((user0 >> 16) & 0xff); + ethaddr->ether_addr_octet[3] = ((user1 >> 0) & 0xff); + ethaddr->ether_addr_octet[4] = ((user1 >> 8) & 0xff); + ethaddr->ether_addr_octet[5] = ((user1 >> 16) & 0xff); +} +#endif diff --git a/configs/eagle100/src/up_leds.c b/configs/eagle100/src/up_leds.c index e567955b3450ba0a742af37d97d3fc8b38eadd0c..59b489c11482a644c4ed8bc05b4e34f307144edd 100644 --- a/configs/eagle100/src/up_leds.c +++ b/configs/eagle100/src/up_leds.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_leds.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/eagle100/src/up_ssi.c b/configs/eagle100/src/up_ssi.c index 2d0237266a4a2509dcfc62d440e9f9b2adcf4384..fb5f99df34373bd50035ef7a42c8c11b62cc1646 100644 --- a/configs/eagle100/src/up_ssi.c +++ b/configs/eagle100/src/up_ssi.c @@ -1,152 +1,152 @@ -/************************************************************************************ - * configs/eagle100/src/up_ssi.c - * arch/arm/src/board/up_ssi.c - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "up_arch.h" -#include "chip.h" -#include "lm3s_internal.h" -#include "eagle100_internal.h" - -/* The Eagle100 microSD CS is on SSI0 */ - -#if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */ - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* Enables debug output from this file (needs CONFIG_DEBUG too) */ - -#undef SSI_DEBUG /* Define to enable debug */ -#undef SSI_VERBOSE /* Define to enable verbose debug */ - -#ifdef SSI_DEBUG -# define ssidbg lldbg -# ifdef SSI_VERBOSE -# define ssivdbg lldbg -# else -# define ssivdbg(x...) -# endif -#else -# undef SSI_VERBOSE -# define ssidbg(x...) -# define ssivdbg(x...) -#endif - -/* Dump GPIO registers */ - -#ifdef SSI_VERBOSE -# define ssi_dumpgpio(m) lm3s_dumpgpio(SDCCS_GPIO, m) -#else -# define ssi_dumpgpio(m) -#endif - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: lm3s_ssiinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Eagle100 board. - * - ************************************************************************************/ - -void weak_function lm3s_ssiinitialize(void) -{ - /* Configure the SPI-based microSD CS GPIO */ - - ssi_dumpgpio("lm3s_ssiinitialize() before lm3s_configgpio()"); - lm3s_configgpio(SDCCS_GPIO); - ssi_dumpgpio("lm3s_ssiinitialize() after lm3s_configgpio()"); -} - -/**************************************************************************** - * The external functions, lm3s_spiselect and lm3s_spistatus must be provided - * by board-specific logic. The are implementations of the select and status - * methods SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h). - * All othermethods (including up_spiinitialize()) are provided by common - * logic. To use this common SPI logic on your board: - * - * 1. Provide lm3s_spiselect() and lm3s_spistatus() functions in your - * board-specific logic. This function will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 2. Add a call to up_spiinitialize() in your low level initialization - * logic - * 3. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) -{ - ssidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - if (devid == SPIDEV_MMCSD) - { - /* Assert the CS pin to the card */ - - ssi_dumpgpio("lm3s_spiselect() before lm3s_gpiowrite()"); - lm3s_gpiowrite(SDCCS_GPIO, !selected); - ssi_dumpgpio("lm3s_spiselect() after lm3s_gpiowrite()"); - } -} - -uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) -{ - ssidbg("Returning SPI_STATUS_PRESENT\n"); - return SPI_STATUS_PRESENT; -} - -#endif /* !CONFIG_SSI0_DISABLE || !CONFIG_SSI1_DISABLE */ +/************************************************************************************ + * configs/eagle100/src/up_ssi.c + * arch/arm/src/board/up_ssi.c + * + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "chip.h" +#include "lm3s_internal.h" +#include "eagle100_internal.h" + +/* The Eagle100 microSD CS is on SSI0 */ + +#if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Enables debug output from this file (needs CONFIG_DEBUG too) */ + +#undef SSI_DEBUG /* Define to enable debug */ +#undef SSI_VERBOSE /* Define to enable verbose debug */ + +#ifdef SSI_DEBUG +# define ssidbg lldbg +# ifdef SSI_VERBOSE +# define ssivdbg lldbg +# else +# define ssivdbg(x...) +# endif +#else +# undef SSI_VERBOSE +# define ssidbg(x...) +# define ssivdbg(x...) +#endif + +/* Dump GPIO registers */ + +#ifdef SSI_VERBOSE +# define ssi_dumpgpio(m) lm3s_dumpgpio(SDCCS_GPIO, m) +#else +# define ssi_dumpgpio(m) +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lm3s_ssiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Eagle100 board. + * + ************************************************************************************/ + +void weak_function lm3s_ssiinitialize(void) +{ + /* Configure the SPI-based microSD CS GPIO */ + + ssi_dumpgpio("lm3s_ssiinitialize() before lm3s_configgpio()"); + lm3s_configgpio(SDCCS_GPIO); + ssi_dumpgpio("lm3s_ssiinitialize() after lm3s_configgpio()"); +} + +/**************************************************************************** + * The external functions, lm3s_spiselect and lm3s_spistatus must be provided + * by board-specific logic. The are implementations of the select and status + * methods SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h). + * All othermethods (including up_spiinitialize()) are provided by common + * logic. To use this common SPI logic on your board: + * + * 1. Provide lm3s_spiselect() and lm3s_spistatus() functions in your + * board-specific logic. This function will perform chip selection and + * status operations using GPIOs in the way your board is configured. + * 2. Add a call to up_spiinitialize() in your low level initialization + * logic + * 3. The handle returned by up_spiinitialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +{ + ssidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + if (devid == SPIDEV_MMCSD) + { + /* Assert the CS pin to the card */ + + ssi_dumpgpio("lm3s_spiselect() before lm3s_gpiowrite()"); + lm3s_gpiowrite(SDCCS_GPIO, !selected); + ssi_dumpgpio("lm3s_spiselect() after lm3s_gpiowrite()"); + } +} + +uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ + ssidbg("Returning SPI_STATUS_PRESENT\n"); + return SPI_STATUS_PRESENT; +} + +#endif /* !CONFIG_SSI0_DISABLE || !CONFIG_SSI1_DISABLE */ diff --git a/configs/eagle100/thttpd/Make.defs b/configs/eagle100/thttpd/Make.defs index f984d3a8de3dbc8d9038d517dcaf6ef5779cb7d3..cbc3b4a92ac0bdf5d18580a5a43a7be559fb998d 100644 --- a/configs/eagle100/thttpd/Make.defs +++ b/configs/eagle100/thttpd/Make.defs @@ -2,7 +2,7 @@ # configs/eagle100/thttpd/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/thttpd/appconfig b/configs/eagle100/thttpd/appconfig index e692157372f445dd043ddd11d8afdffbca4941c3..45c2605ba474dd15dbc8227387eef0b58daf596f 100644 --- a/configs/eagle100/thttpd/appconfig +++ b/configs/eagle100/thttpd/appconfig @@ -2,7 +2,7 @@ # configs/eagle100/thttpd/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/eagle100/thttpd/setenv.sh b/configs/eagle100/thttpd/setenv.sh index 793c31a49d3527a431dcbcc0afd0ac1a3f587b5f..4dc148e65a9ccf438c17ae42a8534d1a9bcff32d 100755 --- a/configs/eagle100/thttpd/setenv.sh +++ b/configs/eagle100/thttpd/setenv.sh @@ -2,7 +2,7 @@ # configs/eagle100/thttpd/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200kitg/include/board.h b/configs/ez80f910200kitg/include/board.h index 99b44ec08a7139cf0367df3a9ba883c94a9052f0..80a8afb23a3cfdb8cd27d50603e457b837c02d0c 100644 --- a/configs/ez80f910200kitg/include/board.h +++ b/configs/ez80f910200kitg/include/board.h @@ -2,7 +2,7 @@ * arch/ez80f910200kitg/include/board.h * * Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200kitg/ostest/Make.defs b/configs/ez80f910200kitg/ostest/Make.defs index 8ac31611c19abff19e9ef5e8aa1606f9e4a21852..2ec06aadd3444d120cd5700fd933f2f3d8431b4b 100644 --- a/configs/ez80f910200kitg/ostest/Make.defs +++ b/configs/ez80f910200kitg/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/ez80f910200kitg/ostest/Make.defs # # Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200kitg/ostest/appconfig b/configs/ez80f910200kitg/ostest/appconfig index 68892459cac248bc1eea5b625777fabacac58033..64d83b55ee55504a5db92af35cd9c5539f984177 100644 --- a/configs/ez80f910200kitg/ostest/appconfig +++ b/configs/ez80f910200kitg/ostest/appconfig @@ -2,7 +2,7 @@ # configs/ez80f910200kitg/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200kitg/ostest/defconfig b/configs/ez80f910200kitg/ostest/defconfig index 6eeda0cb8dbcb846b1187480a1b90412bfbc52fc..adc92f87966ce3d32e8cfc5569d38a3d45703166 100644 --- a/configs/ez80f910200kitg/ostest/defconfig +++ b/configs/ez80f910200kitg/ostest/defconfig @@ -2,7 +2,7 @@ # configs/ez80f910200kitg/ostest/defconfig # # Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200kitg/ostest/ostest.linkcmd b/configs/ez80f910200kitg/ostest/ostest.linkcmd index 14b482dceae69e5b90e481818b3dcbb141c205a6..3ddee5f855ac0d944819b08769d9f6e2cce5d101 100755 --- a/configs/ez80f910200kitg/ostest/ostest.linkcmd +++ b/configs/ez80f910200kitg/ostest/ostest.linkcmd @@ -2,7 +2,7 @@ /* configs/ez80f910200kitg/ostest/ostest.linkcmd */ /* */ /* Copyright (C) 2008 Gregory Nutt. All rights reserved. */ -/* Author: Gregory Nutt */ +/* Author: Gregory Nutt */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ diff --git a/configs/ez80f910200kitg/ostest/setenv.sh b/configs/ez80f910200kitg/ostest/setenv.sh index 83273e37dec97c610ad1e7a025bbdc59642c02b0..e692029ae49d6a189fdabefc9ede0294615f60e2 100755 --- a/configs/ez80f910200kitg/ostest/setenv.sh +++ b/configs/ez80f910200kitg/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/ez80f910200kitg/ostest/setenv.sh # # Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200kitg/src/Makefile b/configs/ez80f910200kitg/src/Makefile index ae4ffd6854cf5ff4306dd88f75ef856e65b0c6f0..a1f0f6035ff60a29f26f23f9ed36289b8ffb3221 100644 --- a/configs/ez80f910200kitg/src/Makefile +++ b/configs/ez80f910200kitg/src/Makefile @@ -2,7 +2,7 @@ # configs/ez80f910200kitg/Makefile # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200kitg/src/ez80_leds.c b/configs/ez80f910200kitg/src/ez80_leds.c index 12cfe11c6ff167c1d06accce3e729af0620195ce..588410c8e6bba148c785db6fa24e8e43adc25211 100644 --- a/configs/ez80f910200kitg/src/ez80_leds.c +++ b/configs/ez80f910200kitg/src/ez80_leds.c @@ -2,7 +2,7 @@ * configs/ez80f910200kitg/src/ez80_leds.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200kitg/src/ez80_lowinit.c b/configs/ez80f910200kitg/src/ez80_lowinit.c index f56ac52ce3af297238a584efb1789d03d66345e9..e96a1ec07aaa1ad11ebbcd747d64eb10b7bfd4a3 100644 --- a/configs/ez80f910200kitg/src/ez80_lowinit.c +++ b/configs/ez80f910200kitg/src/ez80_lowinit.c @@ -1,66 +1,66 @@ -/*************************************************************************** - * configs/ez80f910200kitg/src/ez80_lowinit.c - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Based upon sample code included with the Zilog ZDS-II toolchain. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -/*************************************************************************** - * Included Files - ***************************************************************************/ - -#include - -#include "chip/chip.h" - -/*************************************************************************** - * Pre-processor Definitions - ***************************************************************************/ - -/*************************************************************************** - * Private Functions - ***************************************************************************/ - -static void ez80_gpioinit(void) -{ -} - -/*************************************************************************** - * Public Functions - ***************************************************************************/ - -void ez80_lowinit(void) -{ - ez80_gpioinit(); -} - +/*************************************************************************** + * configs/ez80f910200kitg/src/ez80_lowinit.c + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Based upon sample code included with the Zilog ZDS-II toolchain. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#include + +#include "chip/chip.h" + +/*************************************************************************** + * Pre-processor Definitions + ***************************************************************************/ + +/*************************************************************************** + * Private Functions + ***************************************************************************/ + +static void ez80_gpioinit(void) +{ +} + +/*************************************************************************** + * Public Functions + ***************************************************************************/ + +void ez80_lowinit(void) +{ + ez80_gpioinit(); +} + diff --git a/configs/ez80f910200zco/dhcpd/Make.defs b/configs/ez80f910200zco/dhcpd/Make.defs index cf69788f5963e0ccc1b8439fda86675660c72ba7..367f60ca7f5ad62c4a3fa4b7b90ee53d9ae8a1bb 100644 --- a/configs/ez80f910200zco/dhcpd/Make.defs +++ b/configs/ez80f910200zco/dhcpd/Make.defs @@ -2,7 +2,7 @@ # configs/ez80f910200zco/dhcpd/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/dhcpd/appconfig b/configs/ez80f910200zco/dhcpd/appconfig index 5506cff4e77afbbd85192d04d3c25a7623df52ee..97b7565216584207ed3421f1ec65b22e367c628c 100644 --- a/configs/ez80f910200zco/dhcpd/appconfig +++ b/configs/ez80f910200zco/dhcpd/appconfig @@ -2,7 +2,7 @@ # configs/ez80f910200zco/dhcpd/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/dhcpd/defconfig b/configs/ez80f910200zco/dhcpd/defconfig index 650af3f2b0db7b54f4a90f7954903934d0852d7f..8f7b6479f74f627a6e4c378069f66747867c6f74 100644 --- a/configs/ez80f910200zco/dhcpd/defconfig +++ b/configs/ez80f910200zco/dhcpd/defconfig @@ -2,7 +2,7 @@ # configs/ez80f910200zco/dhcpd/defconfig # # Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/dhcpd/dhcpd.linkcmd b/configs/ez80f910200zco/dhcpd/dhcpd.linkcmd index dcf816ae8e1bcbf41d1943f2c0674e58ab144930..9a4ae3a77d6d89490187ac6e2589ad1c4baea09a 100755 --- a/configs/ez80f910200zco/dhcpd/dhcpd.linkcmd +++ b/configs/ez80f910200zco/dhcpd/dhcpd.linkcmd @@ -2,7 +2,7 @@ /* configs/ez80f910200zco/dhcpd/dhcpd.linkcmd */ /* */ /* Copyright (C) 2009 Gregory Nutt. All rights reserved. */ -/* Author: Gregory Nutt */ +/* Author: Gregory Nutt */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ diff --git a/configs/ez80f910200zco/dhcpd/setenv.sh b/configs/ez80f910200zco/dhcpd/setenv.sh index 2cdf7b9f69ec4ad8fe9a9315181d2f580684bd44..3d1c4aecbc753935ea5064842e228411da23aa40 100755 --- a/configs/ez80f910200zco/dhcpd/setenv.sh +++ b/configs/ez80f910200zco/dhcpd/setenv.sh @@ -2,7 +2,7 @@ # configs/ez80f910200zco/dhcpd/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/httpd/Make.defs b/configs/ez80f910200zco/httpd/Make.defs index 37aac8fed7a2295eba51adbacba48f58da6149af..ec5a70ca69416c5812d8c6df10307543525e98a2 100644 --- a/configs/ez80f910200zco/httpd/Make.defs +++ b/configs/ez80f910200zco/httpd/Make.defs @@ -2,7 +2,7 @@ # configs/ez80f910200zco/httpd/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/httpd/appconfig b/configs/ez80f910200zco/httpd/appconfig index 33d384dfe44595df926f8dca1e35cb40b66771d8..c37580834a180813712a3e21ada9ec755c4c1380 100644 --- a/configs/ez80f910200zco/httpd/appconfig +++ b/configs/ez80f910200zco/httpd/appconfig @@ -2,7 +2,7 @@ # configs/ez80f910200zco/httpd/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/httpd/defconfig b/configs/ez80f910200zco/httpd/defconfig index 55cd915ace3dc1088388d921e5762048ab8fb78e..296521a9e03af94faf4dcc48fca067605b48ec1b 100644 --- a/configs/ez80f910200zco/httpd/defconfig +++ b/configs/ez80f910200zco/httpd/defconfig @@ -2,7 +2,7 @@ # configs/ez80f910200zco/httpd/defconfig # # Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/httpd/httpd.linkcmd b/configs/ez80f910200zco/httpd/httpd.linkcmd index 19910368d57d965ace2c8cf539f6406fb6c2ca85..4ecc8f1ca75cd603a8346c266ca13b292675dfd3 100755 --- a/configs/ez80f910200zco/httpd/httpd.linkcmd +++ b/configs/ez80f910200zco/httpd/httpd.linkcmd @@ -2,7 +2,7 @@ /* configs/ez80f910200zco/httpd/httpd.linkcmd */ /* */ /* Copyright (C) 2009 Gregory Nutt. All rights reserved. */ -/* Author: Gregory Nutt */ +/* Author: Gregory Nutt */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ diff --git a/configs/ez80f910200zco/httpd/setenv.sh b/configs/ez80f910200zco/httpd/setenv.sh index 2cdf7b9f69ec4ad8fe9a9315181d2f580684bd44..3d1c4aecbc753935ea5064842e228411da23aa40 100755 --- a/configs/ez80f910200zco/httpd/setenv.sh +++ b/configs/ez80f910200zco/httpd/setenv.sh @@ -2,7 +2,7 @@ # configs/ez80f910200zco/dhcpd/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/include/board.h b/configs/ez80f910200zco/include/board.h index cbcabc8038551d75c87e470546c40360fcf39be2..84767437f9d9943dc29f5c048168d44e4f1c756a 100644 --- a/configs/ez80f910200zco/include/board.h +++ b/configs/ez80f910200zco/include/board.h @@ -2,7 +2,7 @@ * arch/ez80f910200zco/include/board.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/nettest/Make.defs b/configs/ez80f910200zco/nettest/Make.defs index 51a9ababb0e8094417bed46543a6caf0e1de0aa7..04074c1bf75b2b8933fa24ca0ea35ec3ef68187c 100644 --- a/configs/ez80f910200zco/nettest/Make.defs +++ b/configs/ez80f910200zco/nettest/Make.defs @@ -2,7 +2,7 @@ # configs/ez80f910200zco/nettest/Make.defs # # Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/nettest/appconfig b/configs/ez80f910200zco/nettest/appconfig index f02619a796558e18a2f521e2df757b7843575129..b3d97d6e900ef8f15c7ae756106bc6f00ee949d0 100644 --- a/configs/ez80f910200zco/nettest/appconfig +++ b/configs/ez80f910200zco/nettest/appconfig @@ -2,7 +2,7 @@ # configs/ez80f910200zco/nettest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/nettest/defconfig b/configs/ez80f910200zco/nettest/defconfig index e3b783307935ecda7bfe011e5f99cc36ab61afb0..fb424a7669591b735d68a0b9469ce6d49ad3d351 100644 --- a/configs/ez80f910200zco/nettest/defconfig +++ b/configs/ez80f910200zco/nettest/defconfig @@ -2,7 +2,7 @@ # configs/ez80f910200zco/nettest/defconfig # # Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/nettest/nettest.linkcmd b/configs/ez80f910200zco/nettest/nettest.linkcmd index f1608c2a18eb966ecbf875d216483f5a2b53f22e..a2338024acf0735d0655d6086cb8ee0786e8b17c 100755 --- a/configs/ez80f910200zco/nettest/nettest.linkcmd +++ b/configs/ez80f910200zco/nettest/nettest.linkcmd @@ -2,7 +2,7 @@ /* configs/ez80f910200zco/nettest/nettest.linkcmd */ /* */ /* Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. */ -/* Author: Gregory Nutt */ +/* Author: Gregory Nutt */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ diff --git a/configs/ez80f910200zco/nettest/setenv.sh b/configs/ez80f910200zco/nettest/setenv.sh index ccc66b1a15a031cc63d1429ae31f0636e1f9c6c6..86823697cba798c3c5e281aa805029bd92b8eb31 100755 --- a/configs/ez80f910200zco/nettest/setenv.sh +++ b/configs/ez80f910200zco/nettest/setenv.sh @@ -2,7 +2,7 @@ # configs/ez80f910200zco/nettest/setenv.sh # # Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/nsh/Make.defs b/configs/ez80f910200zco/nsh/Make.defs index fb9b40ab56ab71d82804b572de909878bd112d61..3f740ac34e6d0e54d95329b921648f8fdd71e32a 100644 --- a/configs/ez80f910200zco/nsh/Make.defs +++ b/configs/ez80f910200zco/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/ez80f910200zco/nst/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/nsh/defconfig b/configs/ez80f910200zco/nsh/defconfig index aa62a9b65965572777a5696c9ff1554fd8ad724b..9c4b5aaee3c7d283925184d7e29bb90080ea4320 100644 --- a/configs/ez80f910200zco/nsh/defconfig +++ b/configs/ez80f910200zco/nsh/defconfig @@ -2,7 +2,7 @@ # configs/ez80f910200zco/nsh/defconfig # # Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/nsh/nsh.linkcmd b/configs/ez80f910200zco/nsh/nsh.linkcmd index 256e7a11370272d6b968b76cb489dcbf56755961..c9e730615badb7f15c28ac42e4879e56d6b6babd 100755 --- a/configs/ez80f910200zco/nsh/nsh.linkcmd +++ b/configs/ez80f910200zco/nsh/nsh.linkcmd @@ -2,7 +2,7 @@ /* configs/ez80f910200zco/nsh/nsh.linkcmd */ /* */ /* Copyright (C) 2009 Gregory Nutt. All rights reserved. */ -/* Author: Gregory Nutt */ +/* Author: Gregory Nutt */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ diff --git a/configs/ez80f910200zco/nsh/setenv.sh b/configs/ez80f910200zco/nsh/setenv.sh index f399d0f4f35635159973d3284781841907f7e806..37bc6e3aa75449c119e08dbe87f148e836ee9d6b 100755 --- a/configs/ez80f910200zco/nsh/setenv.sh +++ b/configs/ez80f910200zco/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/ez80f910200zco/nst/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/ostest/Make.defs b/configs/ez80f910200zco/ostest/Make.defs index 36cfdc191c5c96fcabed80318f7afd200fe74c1f..7c738c4b317e6a8027f51daaccb7b3805b5062ee 100644 --- a/configs/ez80f910200zco/ostest/Make.defs +++ b/configs/ez80f910200zco/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/ez80f910200zco/ostest/Make.defs # # Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/ostest/appconfig b/configs/ez80f910200zco/ostest/appconfig index 6d2ad84ae1c9cb649c1a921a48cef050408ec64d..987de079e8afb3b29b09fd813d1b39650566bdc5 100644 --- a/configs/ez80f910200zco/ostest/appconfig +++ b/configs/ez80f910200zco/ostest/appconfig @@ -2,7 +2,7 @@ # configs/ez80f910200zco/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/ostest/defconfig b/configs/ez80f910200zco/ostest/defconfig index 11a7fda4945ab36f75324ccb7c8fb00c994a4123..548ce3376cedbdaefed094a235e5f4284efce28e 100644 --- a/configs/ez80f910200zco/ostest/defconfig +++ b/configs/ez80f910200zco/ostest/defconfig @@ -2,7 +2,7 @@ # configs/ez80f910200zco/ostest/defconfig # # Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/ostest/ostest.linkcmd b/configs/ez80f910200zco/ostest/ostest.linkcmd index 0bdd5776eb10489908a46950da56e4c356c3c6ad..808d79f358e3897c8f9c859fd8d7e1fafcc1fb93 100755 --- a/configs/ez80f910200zco/ostest/ostest.linkcmd +++ b/configs/ez80f910200zco/ostest/ostest.linkcmd @@ -2,7 +2,7 @@ /* configs/ez80f910200zco/ostest/ostest.linkcmd */ /* */ /* Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. */ -/* Author: Gregory Nutt */ +/* Author: Gregory Nutt */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ diff --git a/configs/ez80f910200zco/ostest/setenv.sh b/configs/ez80f910200zco/ostest/setenv.sh index 6a1446c04517f721639cc262817197e2f77bb573..028eb6ad475ecd71c28107eac75b8939e0c8d733 100755 --- a/configs/ez80f910200zco/ostest/setenv.sh +++ b/configs/ez80f910200zco/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/ez80f910200zco/ostest/setenv.sh # # Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/poll/Make.defs b/configs/ez80f910200zco/poll/Make.defs index 085700d0471b5c039338beb91120bb6b3e219384..65d3ca2f78f96bb623403233e5ccc33c7989ae55 100644 --- a/configs/ez80f910200zco/poll/Make.defs +++ b/configs/ez80f910200zco/poll/Make.defs @@ -2,7 +2,7 @@ # configs/ez80f910200zco/poll/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/poll/appconfig b/configs/ez80f910200zco/poll/appconfig index 181f2e1dbd6e781189b0c76a3be5a279c59d91bd..8377851cca7e7720c4e548b9c20648b0784b2f6c 100644 --- a/configs/ez80f910200zco/poll/appconfig +++ b/configs/ez80f910200zco/poll/appconfig @@ -2,7 +2,7 @@ # configs/ez80f910200zco/poll/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/poll/defconfig b/configs/ez80f910200zco/poll/defconfig index 79a94820276b129efb7365f6880a6cd1ee20e50f..0334ebc26066121e176ddb38d47756682e5ea15d 100644 --- a/configs/ez80f910200zco/poll/defconfig +++ b/configs/ez80f910200zco/poll/defconfig @@ -2,7 +2,7 @@ # configs/ez80f910200zco/poll/defconfig # # Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/poll/poll.linkcmd b/configs/ez80f910200zco/poll/poll.linkcmd index 274464450dbf37b5d91d92e68b9469dbf27e3e1e..ecfa93e6ebadfcbee4a413e3baee19e68053f078 100755 --- a/configs/ez80f910200zco/poll/poll.linkcmd +++ b/configs/ez80f910200zco/poll/poll.linkcmd @@ -2,7 +2,7 @@ /* configs/ez80f910200zco/poll/poll.linkcmd */ /* */ /* Copyright (C) 2009 Gregory Nutt. All rights reserved. */ -/* Author: Gregory Nutt */ +/* Author: Gregory Nutt */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ diff --git a/configs/ez80f910200zco/poll/setenv.sh b/configs/ez80f910200zco/poll/setenv.sh index 71af2dcd1fe8ddc7cfec3e572381b6e7f5d2efa0..38252f8f65c9f9c0ade6ff1d468a5e8150e30063 100755 --- a/configs/ez80f910200zco/poll/setenv.sh +++ b/configs/ez80f910200zco/poll/setenv.sh @@ -2,7 +2,7 @@ # configs/ez80f910200zco/poll/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/src/Makefile b/configs/ez80f910200zco/src/Makefile index d8e41a4f7d23bef386ece04856d37ada167a7bbd..994bb68a6778a04d5fb88f7f7537d3169377d090 100644 --- a/configs/ez80f910200zco/src/Makefile +++ b/configs/ez80f910200zco/src/Makefile @@ -2,7 +2,7 @@ # configs/ez80f910200zco/Makefile # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/src/ez80_buttons.c b/configs/ez80f910200zco/src/ez80_buttons.c index 11ead57b3e7bf4567074a1cb88e069c87ff3be8c..babf13b7e16906f7f936b8fe7dae8e236607705b 100644 --- a/configs/ez80f910200zco/src/ez80_buttons.c +++ b/configs/ez80f910200zco/src/ez80_buttons.c @@ -1,174 +1,174 @@ -/**************************************************************************** - * configs/ez80f910200zco/src/ez80_leds.c - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "chip.h" -#include "up_arch.h" -#include "up_internal.h" - -/**************************************************************************** - * Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_PB/1/2interrupt - * - * Description: - * These could be exteneded to provide interrupt driven button input - * - ****************************************************************************/ - -#if 0 -void up_PBinterrupt(void) -{ - uint8_t regval; - - regval = inp(EZ80_PB_DR); /* Clear interrupt flag for eZ80F91 date codes before 0611 */ - regval |= 7; - outp(EZ80_PB_DR, regval); - - regval = inp(EZ80_PB_ALT0); /* Clear interrupt flag for eZ80F91 date codes 0611 and after */ - regval |= 1; - outp(EZ80_PB_ALT0, regval); -} - -void up_pb1interrupt(void) -{ - uint8_t regval; - - regval = inp(EZ80_PB_DR); /* Clear interrupt flag for eZ80F91 date codes before 0611 */ - regval |= 7; - outp(EZ80_PB_DR, regval); - - regval = inp(EZ80_PB_ALT0); /* Clear interrupt flag for eZ80F91 date codes 0611 and after */ - regval |= 2; - outp(EZ80_PB_ALT0, regval); -} - -void up_pb2interrupt(void) -{ - uint8_t regval; - - regval = inp(EZ80_PB_DR); /* Clear interrupt flag for eZ80F91 date codes before 0611 */ - regval |= 7; - outp(EZ80_PB_DR, regval); - - regval = inp(EZ80_PB_ALT0); - regval |= 4; - outp(EZ80_PB_ALT0, regval); /* Clear interrupt flag for eZ80F91 date codes 0611 and after */ -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_buttoninit - ****************************************************************************/ - -#ifdef CONFIG_ARCH_BUTTONS -void up_buttoninit(void) -{ - uint8_t regval; - -#if 0 /* Interrupts are not used */ - - /* Attach GIO interrupts */ - - irq_attach(EZ80_PB_IRQ, up_PBinterrupt); - irq_attach(EZ80_PB1_IRQ, up_pb1interrupt); - irq_attach(EZ80_PB2_IRQ, up_pb2interrupt); - - /* Configure PB0,1,2 as interrupt, rising edge */ - - regval = inp(EZ80_PB_DR); - regval |= 7; - outp(EZ80_PB_DR, regval); - - regval = inp(EZ80_PB_DDR); - regval |= 7; - outp(EZ80_PB_DDR, regval); - - regval = inp(EZ80_PB_ALT1); - regval |= 7; - outp(EZ80_PB_ALT1, regval); - - regval = inp(EZ80_PB_ALT2); - regval |= 7; - outp(EZ80_PB_ALT2, regval); -#else - /* Configure PB0,1,2 as inputs */ - - regval = inp(EZ80_PB_DDR); - regval |= 7; - outp(EZ80_PB_DDR, regval); - - regval = inp(EZ80_PB_ALT1); - regval &= ~7; - outp(EZ80_PB_ALT1, regval); - - regval = inp(EZ80_PB_ALT2); - regval &= ~7; - outp(EZ80_PB_ALT2, regval); -#endif -} - -/**************************************************************************** - * Name: up_buttons - ****************************************************************************/ - -uint8_t up_buttons(void) -{ - return inp(EZ80_PB_DDR) & 7; -} -#endif /* CONFIG_ARCH_BUTTONS */ +/**************************************************************************** + * configs/ez80f910200zco/src/ez80_leds.c + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_PB/1/2interrupt + * + * Description: + * These could be exteneded to provide interrupt driven button input + * + ****************************************************************************/ + +#if 0 +void up_PBinterrupt(void) +{ + uint8_t regval; + + regval = inp(EZ80_PB_DR); /* Clear interrupt flag for eZ80F91 date codes before 0611 */ + regval |= 7; + outp(EZ80_PB_DR, regval); + + regval = inp(EZ80_PB_ALT0); /* Clear interrupt flag for eZ80F91 date codes 0611 and after */ + regval |= 1; + outp(EZ80_PB_ALT0, regval); +} + +void up_pb1interrupt(void) +{ + uint8_t regval; + + regval = inp(EZ80_PB_DR); /* Clear interrupt flag for eZ80F91 date codes before 0611 */ + regval |= 7; + outp(EZ80_PB_DR, regval); + + regval = inp(EZ80_PB_ALT0); /* Clear interrupt flag for eZ80F91 date codes 0611 and after */ + regval |= 2; + outp(EZ80_PB_ALT0, regval); +} + +void up_pb2interrupt(void) +{ + uint8_t regval; + + regval = inp(EZ80_PB_DR); /* Clear interrupt flag for eZ80F91 date codes before 0611 */ + regval |= 7; + outp(EZ80_PB_DR, regval); + + regval = inp(EZ80_PB_ALT0); + regval |= 4; + outp(EZ80_PB_ALT0, regval); /* Clear interrupt flag for eZ80F91 date codes 0611 and after */ +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_buttoninit + ****************************************************************************/ + +#ifdef CONFIG_ARCH_BUTTONS +void up_buttoninit(void) +{ + uint8_t regval; + +#if 0 /* Interrupts are not used */ + + /* Attach GIO interrupts */ + + irq_attach(EZ80_PB_IRQ, up_PBinterrupt); + irq_attach(EZ80_PB1_IRQ, up_pb1interrupt); + irq_attach(EZ80_PB2_IRQ, up_pb2interrupt); + + /* Configure PB0,1,2 as interrupt, rising edge */ + + regval = inp(EZ80_PB_DR); + regval |= 7; + outp(EZ80_PB_DR, regval); + + regval = inp(EZ80_PB_DDR); + regval |= 7; + outp(EZ80_PB_DDR, regval); + + regval = inp(EZ80_PB_ALT1); + regval |= 7; + outp(EZ80_PB_ALT1, regval); + + regval = inp(EZ80_PB_ALT2); + regval |= 7; + outp(EZ80_PB_ALT2, regval); +#else + /* Configure PB0,1,2 as inputs */ + + regval = inp(EZ80_PB_DDR); + regval |= 7; + outp(EZ80_PB_DDR, regval); + + regval = inp(EZ80_PB_ALT1); + regval &= ~7; + outp(EZ80_PB_ALT1, regval); + + regval = inp(EZ80_PB_ALT2); + regval &= ~7; + outp(EZ80_PB_ALT2, regval); +#endif +} + +/**************************************************************************** + * Name: up_buttons + ****************************************************************************/ + +uint8_t up_buttons(void) +{ + return inp(EZ80_PB_DDR) & 7; +} +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/configs/ez80f910200zco/src/ez80_leds.c b/configs/ez80f910200zco/src/ez80_leds.c index 908d9fc61ac8244ee82aef84802454ef8ae91bdd..7f5af2075020706caba1ee564b090a8c1e9c075a 100644 --- a/configs/ez80f910200zco/src/ez80_leds.c +++ b/configs/ez80f910200zco/src/ez80_leds.c @@ -2,7 +2,7 @@ * configs/ez80f910200zco/src/ez80_leds.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ez80f910200zco/src/ez80_lowinit.c b/configs/ez80f910200zco/src/ez80_lowinit.c index e08670df6a796cd209ac8934d83c474930a42280..cd52ae15886d5a23673925bad9d9ec16806a32a4 100644 --- a/configs/ez80f910200zco/src/ez80_lowinit.c +++ b/configs/ez80f910200zco/src/ez80_lowinit.c @@ -1,66 +1,66 @@ -/*************************************************************************** - * configs/ez80f910200zco/src/ez80_lowinit.c - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Based upon sample code included with the Zilog ZDS-II toolchain. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -/*************************************************************************** - * Included Files - ***************************************************************************/ - -#include - -#include "chip/chip.h" - -/*************************************************************************** - * Definitions - ***************************************************************************/ - -/*************************************************************************** - * Private Functions - ***************************************************************************/ - -static void ez80_gpioinit(void) -{ -} - -/*************************************************************************** - * Public Functions - ***************************************************************************/ - -void ez80_lowinit(void) -{ - ez80_gpioinit(); -} - +/*************************************************************************** + * configs/ez80f910200zco/src/ez80_lowinit.c + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Based upon sample code included with the Zilog ZDS-II toolchain. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#include + +#include "chip/chip.h" + +/*************************************************************************** + * Definitions + ***************************************************************************/ + +/*************************************************************************** + * Private Functions + ***************************************************************************/ + +static void ez80_gpioinit(void) +{ +} + +/*************************************************************************** + * Public Functions + ***************************************************************************/ + +void ez80_lowinit(void) +{ + ez80_gpioinit(); +} + diff --git a/configs/ez80f910200zco/src/ez80f910200zco.h b/configs/ez80f910200zco/src/ez80f910200zco.h index f7612d694bcf49ae1bdf3958d93ac4c20becc623..b26a0dd3c6714ac4643b5f6005e363db2d403f78 100644 --- a/configs/ez80f910200zco/src/ez80f910200zco.h +++ b/configs/ez80f910200zco/src/ez80f910200zco.h @@ -2,7 +2,7 @@ * arch/ez80f910200zco/src/ez80f910200zco.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/kwikstik-k40/include/board.h b/configs/kwikstik-k40/include/board.h index 19653e74e1bf1fc19c91b4c61d3fa4693c14d676..86434ca7c43b1dff9aeec6c6a8a79aabcff0406e 100755 --- a/configs/kwikstik-k40/include/board.h +++ b/configs/kwikstik-k40/include/board.h @@ -3,7 +3,7 @@ * include/arch/board/board.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/kwikstik-k40/ostest/Make.defs b/configs/kwikstik-k40/ostest/Make.defs index c6d3bb651b136304a794fbb142fe676af951e28d..f78ea44fd10842e9e892a758fc776ea329a918d4 100644 --- a/configs/kwikstik-k40/ostest/Make.defs +++ b/configs/kwikstik-k40/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/kwikstik-k40/ostest/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/kwikstik-k40/ostest/appconfig b/configs/kwikstik-k40/ostest/appconfig index 05f1034b61299b6281db994b1ce825849d5a23e0..9fa43afb8fcc227449512f7b1df9cc777d06ca97 100644 --- a/configs/kwikstik-k40/ostest/appconfig +++ b/configs/kwikstik-k40/ostest/appconfig @@ -2,7 +2,7 @@ # configs/kwikstik-k40/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/kwikstik-k40/ostest/defconfig b/configs/kwikstik-k40/ostest/defconfig index 2006686b9e87745caf757f618b2a3b697fe16210..4d90473398809ab63363d6ed473ed4777c28494b 100755 --- a/configs/kwikstik-k40/ostest/defconfig +++ b/configs/kwikstik-k40/ostest/defconfig @@ -2,7 +2,7 @@ # configs/kwikstik-k40/ostest/defconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/kwikstik-k40/ostest/ld.script b/configs/kwikstik-k40/ostest/ld.script index f4f3f2e69aa10e1cbc947e2e1270e3edafd364c5..2b7b517fa30aacc3189705a9759bffda99f01c31 100755 --- a/configs/kwikstik-k40/ostest/ld.script +++ b/configs/kwikstik-k40/ostest/ld.script @@ -2,7 +2,7 @@ * configs/kwikstik-k40/ostest/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/kwikstik-k40/ostest/setenv.sh b/configs/kwikstik-k40/ostest/setenv.sh index e7f74bc48ebbbbdd60221b703ad0f4bb6ce241e1..089419ac73fcf3ebf2fb0967fbd1a58cbb925924 100755 --- a/configs/kwikstik-k40/ostest/setenv.sh +++ b/configs/kwikstik-k40/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/kwikstik-k40/ostest/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/kwikstik-k40/src/Makefile b/configs/kwikstik-k40/src/Makefile index 8c61af8af56267241f09e2ae4732ac8fbdeb86db..ae935f6d91859069bc9a922af537bcffb3c8b82c 100644 --- a/configs/kwikstik-k40/src/Makefile +++ b/configs/kwikstik-k40/src/Makefile @@ -2,7 +2,7 @@ # configs/kwikstik-k40/src/Makefile # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/kwikstik-k40/src/kwikstik-internal.h b/configs/kwikstik-k40/src/kwikstik-internal.h index 015f0bc86f5e557b9ae90ced07771f3f7aedb9cd..145b62d5f63e497cdf58851cee242af30fc9cd7b 100644 --- a/configs/kwikstik-k40/src/kwikstik-internal.h +++ b/configs/kwikstik-k40/src/kwikstik-internal.h @@ -3,7 +3,7 @@ * arch/arm/src/board/kwikstik-internal.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/kwikstik-k40/src/up_boot.c b/configs/kwikstik-k40/src/up_boot.c index 350294d2c44b0ff1b9c244c5c029a0c6f81a94bd..cf5bba4e75415f4d2399a07eea6cebbe55c2d588 100644 --- a/configs/kwikstik-k40/src/up_boot.c +++ b/configs/kwikstik-k40/src/up_boot.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_boot.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/kwikstik-k40/src/up_buttons.c b/configs/kwikstik-k40/src/up_buttons.c index 3c944c5087987665f9a6c4bc50557235318e0635..a30a480bcb99964101caff4193ea775d0dbe67fc 100644 --- a/configs/kwikstik-k40/src/up_buttons.c +++ b/configs/kwikstik-k40/src/up_buttons.c @@ -2,7 +2,7 @@ * configs/kwikstik-k40/src/up_buttons.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/kwikstik-k40/src/up_lcd.c b/configs/kwikstik-k40/src/up_lcd.c index b4f499f16c1d3434a3b5c8855c7491eb4841517f..c8a8a900827c0de0db0b739835471ac2ad1d8404 100644 --- a/configs/kwikstik-k40/src/up_lcd.c +++ b/configs/kwikstik-k40/src/up_lcd.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_lcd.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/kwikstik-k40/src/up_leds.c b/configs/kwikstik-k40/src/up_leds.c index f86c77aef513ddae6d922de633f7d7ea99d137e7..a455fcc34cf4699380bcdc770db0dc0296850a1c 100644 --- a/configs/kwikstik-k40/src/up_leds.c +++ b/configs/kwikstik-k40/src/up_leds.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_leds.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/kwikstik-k40/src/up_nsh.c b/configs/kwikstik-k40/src/up_nsh.c index fa4cc5fa959547ef751fd8fdb082e20c073fb59c..884ff3c44cde1b7cbae0c3dda24d263205140de8 100644 --- a/configs/kwikstik-k40/src/up_nsh.c +++ b/configs/kwikstik-k40/src/up_nsh.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_nsh.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/kwikstik-k40/src/up_spi.c b/configs/kwikstik-k40/src/up_spi.c index 9468c16ae0ee902fe218d5c108e26704043c0c02..e88721dda5d7e7d9cff87a13e58c35a61526e974 100644 --- a/configs/kwikstik-k40/src/up_spi.c +++ b/configs/kwikstik-k40/src/up_spi.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_spi.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/kwikstik-k40/src/up_usbdev.c b/configs/kwikstik-k40/src/up_usbdev.c index 60e54af7cf3f3be30fffcf91ffb6a054d8513d36..38e3413c7a82cddd46155ca2c3622b989f764771 100644 --- a/configs/kwikstik-k40/src/up_usbdev.c +++ b/configs/kwikstik-k40/src/up_usbdev.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_boot.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/kwikstik-k40/src/up_usbmsc.c b/configs/kwikstik-k40/src/up_usbmsc.c index 378295cfacfcd498a351b5ace7b2afa26fd66664..8051ea1bad5c5cc108369c9b5809b066fde52603 100644 --- a/configs/kwikstik-k40/src/up_usbmsc.c +++ b/configs/kwikstik-k40/src/up_usbmsc.c @@ -2,7 +2,7 @@ * configs/kwikstik-k40/src/up_usbmsc.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Configure and register the Kinetis MMC/SD block driver. * diff --git a/configs/lm3s6432-s2e/include/board.h b/configs/lm3s6432-s2e/include/board.h index 872f784fecd9f1b34c8fbc541d52720d5d32c022..06504ec4f8c8e0e03b451905062b6018d0e559af 100644 --- a/configs/lm3s6432-s2e/include/board.h +++ b/configs/lm3s6432-s2e/include/board.h @@ -3,7 +3,7 @@ * include/arch/board/board.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s6432-s2e/nsh/Make.defs b/configs/lm3s6432-s2e/nsh/Make.defs index 36b463c5c5fea974f990b0ffae2e5c85c92471a6..73f7007e866255c84b5198b8270b6d9b47f98656 100644 --- a/configs/lm3s6432-s2e/nsh/Make.defs +++ b/configs/lm3s6432-s2e/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/lm3s6432-s2e/nsh/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6432-s2e/nsh/defconfig b/configs/lm3s6432-s2e/nsh/defconfig index b4c02b5345c9a5ad723cf52423a631c7569c12fd..a5f2466c200e243cabd6925367bd7f4caa81df1b 100644 --- a/configs/lm3s6432-s2e/nsh/defconfig +++ b/configs/lm3s6432-s2e/nsh/defconfig @@ -2,7 +2,7 @@ # configs/lm3s6432-s2e/nsh/defconfig # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6432-s2e/nsh/ld.script b/configs/lm3s6432-s2e/nsh/ld.script index 675f8753bb19b2c30a4cf5da8948263fcf725a1a..0701841c5a1c141889303b6a093df79babd4785e 100644 --- a/configs/lm3s6432-s2e/nsh/ld.script +++ b/configs/lm3s6432-s2e/nsh/ld.script @@ -2,7 +2,7 @@ * configs/lm3s6432-s2e/nsh/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s6432-s2e/nsh/setenv.sh b/configs/lm3s6432-s2e/nsh/setenv.sh index 522ac07bf4159c8d0177f38188f9f01b893d989b..3cd011f121ed6a91465e90f4325711196b4528e6 100644 --- a/configs/lm3s6432-s2e/nsh/setenv.sh +++ b/configs/lm3s6432-s2e/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/lm3s6432-s2e/nsh/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6432-s2e/ostest/Make.defs b/configs/lm3s6432-s2e/ostest/Make.defs index c59ee3adb7c8d4417505c7cfde4e3a5bebcf51e0..41c1ba32c8df2390a233c9183c94a5c3eddd2a7a 100644 --- a/configs/lm3s6432-s2e/ostest/Make.defs +++ b/configs/lm3s6432-s2e/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/lm3s6432-s2e/ostest/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6432-s2e/ostest/appconfig b/configs/lm3s6432-s2e/ostest/appconfig index 459dfc1cbbe991c28df136036d06696cea099e4c..59851765a119e351866788ee672c24cf9c5c93fa 100644 --- a/configs/lm3s6432-s2e/ostest/appconfig +++ b/configs/lm3s6432-s2e/ostest/appconfig @@ -2,7 +2,7 @@ # configs/lm3s6432-s2e/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6432-s2e/ostest/defconfig b/configs/lm3s6432-s2e/ostest/defconfig index 03a3b30eb70c3ae5cc6891c2b9a3960bc57a8555..bc9ce20f057f22da5e6cca54da0c6275afa50d31 100644 --- a/configs/lm3s6432-s2e/ostest/defconfig +++ b/configs/lm3s6432-s2e/ostest/defconfig @@ -2,7 +2,7 @@ # configs/lm3s6432-s2e/nsh/defconfig # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6432-s2e/ostest/ld.script b/configs/lm3s6432-s2e/ostest/ld.script index 900e15e43f74183cfc002df5503121acd7418142..bfbf8d3024e62fc31762a92e2aa8185fdd0cdabf 100644 --- a/configs/lm3s6432-s2e/ostest/ld.script +++ b/configs/lm3s6432-s2e/ostest/ld.script @@ -2,7 +2,7 @@ * configs/lm3s6432-s2e/ostest/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s6432-s2e/ostest/setenv.sh b/configs/lm3s6432-s2e/ostest/setenv.sh index c45468cb0c5da61c17033ba278483d854709f565..2cccdc70e6de18751d44c81e6e465a9ad121a770 100644 --- a/configs/lm3s6432-s2e/ostest/setenv.sh +++ b/configs/lm3s6432-s2e/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/lm3s6432-s2e/ostest/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6432-s2e/src/Makefile b/configs/lm3s6432-s2e/src/Makefile index 7a0b883f870379ef00cda25ac76a9b2253f0ac61..eefaa50394eccfc5c70321490c85c55637587193 100644 --- a/configs/lm3s6432-s2e/src/Makefile +++ b/configs/lm3s6432-s2e/src/Makefile @@ -2,7 +2,7 @@ # configs/lm3s6432-s2e/src/Makefile # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h b/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h index cc474bd80ab6babd05961e04f51dbc3691c0ddf9..bd4cff77fc01e2c29112f99a5fbdb0d95a6c6e99 100644 --- a/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h +++ b/configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h @@ -2,7 +2,7 @@ * configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s6432-s2e/src/up_boot.c b/configs/lm3s6432-s2e/src/up_boot.c index 4b8fc3fcf55d9d63b41f5390c9a89e915abd0a4f..3c5787f99a51ae04e74e5614c7e48c83e612c1ea 100644 --- a/configs/lm3s6432-s2e/src/up_boot.c +++ b/configs/lm3s6432-s2e/src/up_boot.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_boot.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s6432-s2e/src/up_ethernet.c b/configs/lm3s6432-s2e/src/up_ethernet.c index 6040c167c621a97094b4673ac796a6bade815556..09d5040c41097b6a5c3f60bcd851537574773109 100644 --- a/configs/lm3s6432-s2e/src/up_ethernet.c +++ b/configs/lm3s6432-s2e/src/up_ethernet.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_ethernet.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s6432-s2e/src/up_leds.c b/configs/lm3s6432-s2e/src/up_leds.c index 9a3e337930cbeb2b045ca29d7f35d792d138666e..80fea934f91c6f2cd72b90d5d8a30fc82c1f9099 100644 --- a/configs/lm3s6432-s2e/src/up_leds.c +++ b/configs/lm3s6432-s2e/src/up_leds.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_leds.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s6432-s2e/src/up_nsh.c b/configs/lm3s6432-s2e/src/up_nsh.c index 6b44eafafa43c8650dd61d6b5e3e98829c323d17..46726e753ef4ed603c2bd5934d795c6cbdf4bee0 100644 --- a/configs/lm3s6432-s2e/src/up_nsh.c +++ b/configs/lm3s6432-s2e/src/up_nsh.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_nsh.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s6432-s2e/src/up_ssi.c b/configs/lm3s6432-s2e/src/up_ssi.c index 7ca33c8bea4ae69c3c259a67af2c3aeb365d2cc4..d20e1d978badcb3b1db650abad224fa80edf09d4 100644 --- a/configs/lm3s6432-s2e/src/up_ssi.c +++ b/configs/lm3s6432-s2e/src/up_ssi.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_ssi.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/include/board.h b/configs/lm3s6965-ek/include/board.h index 45fa0dfb049cdb6dd8eb2ce8df0d9822f460d86c..e8eaf9dd1a96632fd0178d6aed828d671f42cccc 100755 --- a/configs/lm3s6965-ek/include/board.h +++ b/configs/lm3s6965-ek/include/board.h @@ -3,7 +3,7 @@ * include/arch/board/board.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/nsh/Make.defs b/configs/lm3s6965-ek/nsh/Make.defs index 555d188437c88d226269b6ae08eba3bab81136bd..b25fa4bb625b55ac50115a10ee1fc6d532696a82 100755 --- a/configs/lm3s6965-ek/nsh/Make.defs +++ b/configs/lm3s6965-ek/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/lm3s6965-ek/nsh/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/nsh/defconfig b/configs/lm3s6965-ek/nsh/defconfig index 39d6807140d1f54c08d45b7fd96b19615ac91ccc..145c992c9af32b25fdef639ea8f18cba5cf3cfe0 100755 --- a/configs/lm3s6965-ek/nsh/defconfig +++ b/configs/lm3s6965-ek/nsh/defconfig @@ -2,7 +2,7 @@ # configs/lm3s6965-ek/nsh/defconfig # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/nsh/ld.script b/configs/lm3s6965-ek/nsh/ld.script index 61fe04c0ebc9a5a52fcb4426962deeb8c9882530..d3a0d668e48982c4f1db6754d7bbb1ced18fc213 100755 --- a/configs/lm3s6965-ek/nsh/ld.script +++ b/configs/lm3s6965-ek/nsh/ld.script @@ -2,7 +2,7 @@ * configs/lm3s6965-ek/nsh/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/nsh/setenv.sh b/configs/lm3s6965-ek/nsh/setenv.sh index 3490a47d8e26f9b8675c0f05ea7d4e0888f2d9cf..0b9389f49e5180ceeb130b7992e55f4e762772ff 100755 --- a/configs/lm3s6965-ek/nsh/setenv.sh +++ b/configs/lm3s6965-ek/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/lm3s6965-ek/nsh/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/nx/Make.defs b/configs/lm3s6965-ek/nx/Make.defs index a9756cb36e8c680712fe8c43d22e76d41424b8a1..388caffb61ce4c216d36451bed56393d23d4b9f5 100755 --- a/configs/lm3s6965-ek/nx/Make.defs +++ b/configs/lm3s6965-ek/nx/Make.defs @@ -2,7 +2,7 @@ # configs/lm3s6965-ek/nx/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/nx/appconfig b/configs/lm3s6965-ek/nx/appconfig index c7fbe82ee32d7b3e5b252d748b53a8d6a64783d0..69f92ce3a5b13f6ecc75bb9d3a4f5be746507128 100644 --- a/configs/lm3s6965-ek/nx/appconfig +++ b/configs/lm3s6965-ek/nx/appconfig @@ -2,7 +2,7 @@ # configs/lm3s6965-ek/nx/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/nx/defconfig b/configs/lm3s6965-ek/nx/defconfig index 713420b38578c9b56252c405557fcf1cd465a16c..c6340c76b54599276b64ccace0c0e0db97ff622f 100755 --- a/configs/lm3s6965-ek/nx/defconfig +++ b/configs/lm3s6965-ek/nx/defconfig @@ -2,7 +2,7 @@ # configs/lm3s6965-ek/nx/defconfig # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/nx/ld.script b/configs/lm3s6965-ek/nx/ld.script index 1b900bed4438d4e1b7b75f815b67590c1b0b749c..dcb12fa99a726462b868302dc63a3924371ca42b 100755 --- a/configs/lm3s6965-ek/nx/ld.script +++ b/configs/lm3s6965-ek/nx/ld.script @@ -2,7 +2,7 @@ * configs/lm3s6965-ek/nx/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/nx/setenv.sh b/configs/lm3s6965-ek/nx/setenv.sh index c18c43c15978411de2b36a2b31eae3c015632d03..a364c2017277911769885989686804e861d42903 100755 --- a/configs/lm3s6965-ek/nx/setenv.sh +++ b/configs/lm3s6965-ek/nx/setenv.sh @@ -2,7 +2,7 @@ # configs/lm3s6965-ek/nx/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/ostest/Make.defs b/configs/lm3s6965-ek/ostest/Make.defs index 4233287a4b7581fabcae1ce8ed2fcf2846ddf971..74eed679e0b14bbfd6ffe03dac8e249fca23ebe5 100755 --- a/configs/lm3s6965-ek/ostest/Make.defs +++ b/configs/lm3s6965-ek/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/lm3s6965-ek/ostest/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/ostest/appconfig b/configs/lm3s6965-ek/ostest/appconfig index 1e12db1f02a73476dcba68b3011f9114198337b2..dabf1f2b44b2ad2f18202fd03ae60066d22b01a3 100644 --- a/configs/lm3s6965-ek/ostest/appconfig +++ b/configs/lm3s6965-ek/ostest/appconfig @@ -2,7 +2,7 @@ # configs/lm3s6965-ek/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/ostest/defconfig b/configs/lm3s6965-ek/ostest/defconfig index 667c93b15314cd7209a825f284cabf7493a087ec..1ef498dd8e0e8b2376be09da2f025f3c90b350ad 100755 --- a/configs/lm3s6965-ek/ostest/defconfig +++ b/configs/lm3s6965-ek/ostest/defconfig @@ -2,7 +2,7 @@ # configs/lm3s6965-ek/ostest/defconfig # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/ostest/ld.script b/configs/lm3s6965-ek/ostest/ld.script index 2bd910d91708c03b8cc6f7962401a2790eea5498..e330f35ae459af8dd72a2218e3da25a9e1a92709 100755 --- a/configs/lm3s6965-ek/ostest/ld.script +++ b/configs/lm3s6965-ek/ostest/ld.script @@ -2,7 +2,7 @@ * configs/lm3s6965-ek/ostest/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/ostest/setenv.sh b/configs/lm3s6965-ek/ostest/setenv.sh index be32a282c76e7feaebc994f896487e8307f3fb55..6e907ae7a613af8423f56013c553bb17ca6852f8 100755 --- a/configs/lm3s6965-ek/ostest/setenv.sh +++ b/configs/lm3s6965-ek/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/lm3s6965-ek/ostest/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/src/Makefile b/configs/lm3s6965-ek/src/Makefile index bd9b4f9caa8489f35d258f6cc1a5b85c16491e20..90833fc31966683a79143e361f0863ab578ccb97 100644 --- a/configs/lm3s6965-ek/src/Makefile +++ b/configs/lm3s6965-ek/src/Makefile @@ -2,7 +2,7 @@ # configs/lm3s6965-ek/src/Makefile # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/src/lm3s6965ek_internal.h b/configs/lm3s6965-ek/src/lm3s6965ek_internal.h index fb3a8a4eaec217c14f7a6f32f3c0b76393bc8056..621f00148cbc13dc30d5540b29c9ca7772616be7 100644 --- a/configs/lm3s6965-ek/src/lm3s6965ek_internal.h +++ b/configs/lm3s6965-ek/src/lm3s6965ek_internal.h @@ -1,136 +1,136 @@ -/************************************************************************************ - * configs/lm3s6965-ek/src/lm3s6965ek_internal.h - * arch/arm/src/board/lm3s6965ek_internal.n - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __CONFIGS_LM3S6965_EK_SRC_LM3S6965EK_INTERNAL_H -#define __CONFIGS_LM3S6965_EK_SRC_LM3S6965EK_INTERNAL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#include "chip.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* How many SSI modules does this chip support? The LM3S6965 supports 1 SSI - * module (others may support more than 2 -- in such case, the following must be - * expanded). - */ - -#if LM3S_NSSI == 0 -# undef CONFIG_SSI0_DISABLE -# define CONFIG_SSI0_DISABLE 1 -# undef CONFIG_SSI1_DISABLE -# define CONFIG_SSI1_DISABLE 1 -#elif LM3S_NSSI == 1 -# undef CONFIG_SSI1_DISABLE -# define CONFIG_SSI1_DISABLE 1 -#endif - -/* LM3S6965 Eval Kit ***************************************************************/ - -/* GPIO Usage - * - * PIN SIGNAL EVB Function - * --- ----------- --------------------------------------- - * 26 PA0/U0RX Virtual COM port receive - * 27 PA1/U0TX Virtual COM port transmit - * 10 PD0/IDX0 SD card chip select - * 11 PD1/PWM1 Sound - * 30 PA4/SSI0RX SD card data out - * 31 PA5/SSI0TX SD card and OLED display data in - * 28 PA2/SSI0CLK SD card and OLED display clock - * 22 PC7/PHB0 OLED display data/control select - * 29 PA3/SSI0FSS OLED display chip select - * 73 PE1/PWM5 Down switch - * 74 PE2/PHB1 Left switch - * 72 PE0/PWM4 Up switch - * 75 PE3/PHA1 Right switch - * 61 PF1/IDX1 Select switch - * 47 PF0/PWM0 User LED - * 23 PC6/CCP3 Enable +15 V - */ - -/* GPIO for microSD card chip select: - * - PD0: SD card chip select (CARDCSn) - */ - -#define SDCCS_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STDWPU | GPIO_STRENGTH_4MA | \ - GPIO_VALUE_ONE | GPIO_PORTD | 0) - -/* GPIO for single LED: - * - PF0: User LED - */ - -#define LED_GPIO (GPIO_FUNC_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTF | 0) - -/* GPIOs for OLED: - * - PC7: OLED display data/control select (D/Cn) - * - PA3: OLED display chip select (CSn) - * - PC6: Enable +15V needed by OLED (EN+15V) - */ - -#define OLEDDC_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STD | GPIO_STRENGTH_8MA | \ - GPIO_VALUE_ONE | GPIO_PORTC | 7) -#define OLEDCS_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STDWPU | GPIO_STRENGTH_4MA | \ - GPIO_VALUE_ONE | GPIO_PORTA | 3) -#define OLEDEN_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STD | GPIO_STRENGTH_8MA | \ - GPIO_VALUE_ONE | GPIO_PORTC | 6) - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Name: lm3s_ssiinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit. - * - ************************************************************************************/ - -extern void weak_function lm3s_ssiinitialize(void); - -#endif /* __ASSEMBLY__ */ -#endif /* __CONFIGS_LM3S6965_EK_SRC_LM3S6965EK_INTERNAL_H */ - +/************************************************************************************ + * configs/lm3s6965-ek/src/lm3s6965ek_internal.h + * arch/arm/src/board/lm3s6965ek_internal.n + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_LM3S6965_EK_SRC_LM3S6965EK_INTERNAL_H +#define __CONFIGS_LM3S6965_EK_SRC_LM3S6965EK_INTERNAL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "chip.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* How many SSI modules does this chip support? The LM3S6965 supports 1 SSI + * module (others may support more than 2 -- in such case, the following must be + * expanded). + */ + +#if LM3S_NSSI == 0 +# undef CONFIG_SSI0_DISABLE +# define CONFIG_SSI0_DISABLE 1 +# undef CONFIG_SSI1_DISABLE +# define CONFIG_SSI1_DISABLE 1 +#elif LM3S_NSSI == 1 +# undef CONFIG_SSI1_DISABLE +# define CONFIG_SSI1_DISABLE 1 +#endif + +/* LM3S6965 Eval Kit ***************************************************************/ + +/* GPIO Usage + * + * PIN SIGNAL EVB Function + * --- ----------- --------------------------------------- + * 26 PA0/U0RX Virtual COM port receive + * 27 PA1/U0TX Virtual COM port transmit + * 10 PD0/IDX0 SD card chip select + * 11 PD1/PWM1 Sound + * 30 PA4/SSI0RX SD card data out + * 31 PA5/SSI0TX SD card and OLED display data in + * 28 PA2/SSI0CLK SD card and OLED display clock + * 22 PC7/PHB0 OLED display data/control select + * 29 PA3/SSI0FSS OLED display chip select + * 73 PE1/PWM5 Down switch + * 74 PE2/PHB1 Left switch + * 72 PE0/PWM4 Up switch + * 75 PE3/PHA1 Right switch + * 61 PF1/IDX1 Select switch + * 47 PF0/PWM0 User LED + * 23 PC6/CCP3 Enable +15 V + */ + +/* GPIO for microSD card chip select: + * - PD0: SD card chip select (CARDCSn) + */ + +#define SDCCS_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STDWPU | GPIO_STRENGTH_4MA | \ + GPIO_VALUE_ONE | GPIO_PORTD | 0) + +/* GPIO for single LED: + * - PF0: User LED + */ + +#define LED_GPIO (GPIO_FUNC_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTF | 0) + +/* GPIOs for OLED: + * - PC7: OLED display data/control select (D/Cn) + * - PA3: OLED display chip select (CSn) + * - PC6: Enable +15V needed by OLED (EN+15V) + */ + +#define OLEDDC_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STD | GPIO_STRENGTH_8MA | \ + GPIO_VALUE_ONE | GPIO_PORTC | 7) +#define OLEDCS_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STDWPU | GPIO_STRENGTH_4MA | \ + GPIO_VALUE_ONE | GPIO_PORTA | 3) +#define OLEDEN_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STD | GPIO_STRENGTH_8MA | \ + GPIO_VALUE_ONE | GPIO_PORTC | 6) + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Name: lm3s_ssiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit. + * + ************************************************************************************/ + +extern void weak_function lm3s_ssiinitialize(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_LM3S6965_EK_SRC_LM3S6965EK_INTERNAL_H */ + diff --git a/configs/lm3s6965-ek/src/up_boot.c b/configs/lm3s6965-ek/src/up_boot.c index 3fb75cf54363b756b7e1359262cd87a600862669..7f887be620b632f21d8e42ec581320b9f8247e2a 100644 --- a/configs/lm3s6965-ek/src/up_boot.c +++ b/configs/lm3s6965-ek/src/up_boot.c @@ -1,92 +1,92 @@ -/************************************************************************************ - * configs/lm3s6965-ek/src/up_boot.c - * arch/arm/src/board/up_boot.c - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include - -#include - -#include "up_arch.h" -#include "up_internal.h" -#include "lm3s6965ek_internal.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: lm3s_boardinitialize - * - * Description: - * All LM3S architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - ************************************************************************************/ - -void lm3s_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SSI is not disabled, and 2) the weak function - * lm3s_ssiinitialize() has been brought into the link. - */ - - /* The LM3S6965 Eval Kit microSD CS and OLED are on SSI0 (Duh! There is no SSI1) */ - -#if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */ - if (lm3s_ssiinitialize) - { - lm3s_ssiinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - up_ledinit(); -#endif -} +/************************************************************************************ + * configs/lm3s6965-ek/src/up_boot.c + * arch/arm/src/board/up_boot.c + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" +#include "lm3s6965ek_internal.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lm3s_boardinitialize + * + * Description: + * All LM3S architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + ************************************************************************************/ + +void lm3s_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SSI is not disabled, and 2) the weak function + * lm3s_ssiinitialize() has been brought into the link. + */ + + /* The LM3S6965 Eval Kit microSD CS and OLED are on SSI0 (Duh! There is no SSI1) */ + +#if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */ + if (lm3s_ssiinitialize) + { + lm3s_ssiinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + up_ledinit(); +#endif +} diff --git a/configs/lm3s6965-ek/src/up_ethernet.c b/configs/lm3s6965-ek/src/up_ethernet.c index 1cea3d022806ab13f2029047492b7ead734a71d7..4f402cae70e0e20297e3ed23ca8d7c2f61785dbd 100644 --- a/configs/lm3s6965-ek/src/up_ethernet.c +++ b/configs/lm3s6965-ek/src/up_ethernet.c @@ -1,98 +1,98 @@ -/************************************************************************************ - * configs/lm3s6965-ek/src/up_ethernet.c - * arch/arm/src/board/up_ethernet.c - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "up_arch.h" -#include "chip.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: lm3s_ethernetmac - * - * Description: - * For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile - * USER0 and USER1 registers. If CONFIG_LM3S_BOARDMAC is defined, this function - * will obtain the MAC address from these registers. - * - ************************************************************************************/ - -#ifdef CONFIG_LM3S_BOARDMAC -void lm3s_ethernetmac(struct ether_addr *ethaddr) -{ - uint32_t user0; - uint32_t user1; - - /* Get the current value of the user registers */ - - user0 = getreg32(LM3S_FLASH_USERREG0); - user1 = getreg32(LM3S_FLASH_USERREG1); - - nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff); - DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff); - - /* Re-format that MAC address the way that uIP expects to see it */ - - ethaddr->ether_addr_octet[0] = ((user0 >> 0) & 0xff); - ethaddr->ether_addr_octet[1] = ((user0 >> 8) & 0xff); - ethaddr->ether_addr_octet[2] = ((user0 >> 16) & 0xff); - ethaddr->ether_addr_octet[3] = ((user1 >> 0) & 0xff); - ethaddr->ether_addr_octet[4] = ((user1 >> 8) & 0xff); - ethaddr->ether_addr_octet[5] = ((user1 >> 16) & 0xff); -} -#endif +/************************************************************************************ + * configs/lm3s6965-ek/src/up_ethernet.c + * arch/arm/src/board/up_ethernet.c + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "chip.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lm3s_ethernetmac + * + * Description: + * For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile + * USER0 and USER1 registers. If CONFIG_LM3S_BOARDMAC is defined, this function + * will obtain the MAC address from these registers. + * + ************************************************************************************/ + +#ifdef CONFIG_LM3S_BOARDMAC +void lm3s_ethernetmac(struct ether_addr *ethaddr) +{ + uint32_t user0; + uint32_t user1; + + /* Get the current value of the user registers */ + + user0 = getreg32(LM3S_FLASH_USERREG0); + user1 = getreg32(LM3S_FLASH_USERREG1); + + nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff); + DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff); + + /* Re-format that MAC address the way that uIP expects to see it */ + + ethaddr->ether_addr_octet[0] = ((user0 >> 0) & 0xff); + ethaddr->ether_addr_octet[1] = ((user0 >> 8) & 0xff); + ethaddr->ether_addr_octet[2] = ((user0 >> 16) & 0xff); + ethaddr->ether_addr_octet[3] = ((user1 >> 0) & 0xff); + ethaddr->ether_addr_octet[4] = ((user1 >> 8) & 0xff); + ethaddr->ether_addr_octet[5] = ((user1 >> 16) & 0xff); +} +#endif diff --git a/configs/lm3s6965-ek/src/up_leds.c b/configs/lm3s6965-ek/src/up_leds.c index f817f8261c55036539ee20df8c1cb9c92cca430e..933c114467b44d878bb27dcf32fa929770013fc7 100644 --- a/configs/lm3s6965-ek/src/up_leds.c +++ b/configs/lm3s6965-ek/src/up_leds.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_leds.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/src/up_nsh.c b/configs/lm3s6965-ek/src/up_nsh.c index 952ee4298dfc475f12778667e06ac06cf8772cec..409b351f061e3207c11f4025908ac1bdbd8b2d58 100644 --- a/configs/lm3s6965-ek/src/up_nsh.c +++ b/configs/lm3s6965-ek/src/up_nsh.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_nsh.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/src/up_oled.c b/configs/lm3s6965-ek/src/up_oled.c index 8a26e1eb2ec06e0f9fbb0740717fab528e83626c..586927d5369aa43ba6799b533a2c91762d87cd24 100644 --- a/configs/lm3s6965-ek/src/up_oled.c +++ b/configs/lm3s6965-ek/src/up_oled.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_oled.c * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s6965-ek/src/up_ssi.c b/configs/lm3s6965-ek/src/up_ssi.c index 4dcd231c060732ed09467cb0591a1f0292b01d5e..16111fcdaf5018cc0c0f3fa2e9947b33b5c4ac10 100644 --- a/configs/lm3s6965-ek/src/up_ssi.c +++ b/configs/lm3s6965-ek/src/up_ssi.c @@ -1,164 +1,164 @@ -/************************************************************************************ - * configs/lm3s6965-ek/src/up_ssi.c - * arch/arm/src/board/up_ssi.c - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "up_arch.h" -#include "chip.h" -#include "lm3s_internal.h" -#include "lm3s6965ek_internal.h" - -/* The LM3S6965 Eval Kit microSD CS is on SSI0 */ - -#if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */ - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* Enables debug output from this file (needs CONFIG_DEBUG too) */ - -#undef SSI_DEBUG /* Define to enable debug */ -#undef SSI_VERBOSE /* Define to enable verbose debug */ - -#ifdef SSI_DEBUG -# define ssidbg lldbg -# ifdef SSI_VERBOSE -# define ssivdbg lldbg -# else -# define ssivdbg(x...) -# endif -#else -# undef SSI_VERBOSE -# define ssidbg(x...) -# define ssivdbg(x...) -#endif - -/* Dump GPIO registers */ - -#ifdef SSI_VERBOSE -# define ssi_dumpgpio(m) lm3s_dumpgpio(SDCCS_GPIO, m) -#else -# define ssi_dumpgpio(m) -#endif - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: lm3s_ssiinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit. - * - ************************************************************************************/ - -void weak_function lm3s_ssiinitialize(void) -{ - /* Configure the SPI-based microSD CS GPIO */ - - ssi_dumpgpio("lm3s_ssiinitialize() Entry)"); - lm3s_configgpio(SDCCS_GPIO); -#ifdef CONFIG_NX_LCDDRIVER - lm3s_configgpio(OLEDCS_GPIO); -#endif - ssi_dumpgpio("lm3s_ssiinitialize() Exit"); -} - -/**************************************************************************** - * The external functions, lm3s_spiselect and lm3s_spistatus must be provided - * by board-specific logic. The are implementations of the select and status - * methods SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h). - * All othermethods (including up_spiinitialize()) are provided by common - * logic. To use this common SPI logic on your board: - * - * 1. Provide lm3s_spiselect() and lm3s_spistatus() functions in your - * board-specific logic. This function will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 2. Add a call to up_spiinitialize() in your low level initialization - * logic - * 3. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) -{ - ssidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssi_dumpgpio("lm3s_spiselect() Entry"); - - if (devid == SPIDEV_MMCSD) - { - /* Assert the CS pin to the card */ - - lm3s_gpiowrite(SDCCS_GPIO, !selected); - } -#ifdef CONFIG_NX_LCDDRIVER - else if (devid == SPIDEV_DISPLAY) - { - /* Assert the CS pin to the display */ - - lm3s_gpiowrite(OLEDCS_GPIO, !selected); - } -#endif - ssi_dumpgpio("lm3s_spiselect() Exit"); -} - -uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) -{ - ssidbg("Returning SPI_STATUS_PRESENT\n"); - return SPI_STATUS_PRESENT; -} - -#endif /* !CONFIG_SSI0_DISABLE || !CONFIG_SSI1_DISABLE */ +/************************************************************************************ + * configs/lm3s6965-ek/src/up_ssi.c + * arch/arm/src/board/up_ssi.c + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "chip.h" +#include "lm3s_internal.h" +#include "lm3s6965ek_internal.h" + +/* The LM3S6965 Eval Kit microSD CS is on SSI0 */ + +#if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Enables debug output from this file (needs CONFIG_DEBUG too) */ + +#undef SSI_DEBUG /* Define to enable debug */ +#undef SSI_VERBOSE /* Define to enable verbose debug */ + +#ifdef SSI_DEBUG +# define ssidbg lldbg +# ifdef SSI_VERBOSE +# define ssivdbg lldbg +# else +# define ssivdbg(x...) +# endif +#else +# undef SSI_VERBOSE +# define ssidbg(x...) +# define ssivdbg(x...) +#endif + +/* Dump GPIO registers */ + +#ifdef SSI_VERBOSE +# define ssi_dumpgpio(m) lm3s_dumpgpio(SDCCS_GPIO, m) +#else +# define ssi_dumpgpio(m) +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lm3s_ssiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit. + * + ************************************************************************************/ + +void weak_function lm3s_ssiinitialize(void) +{ + /* Configure the SPI-based microSD CS GPIO */ + + ssi_dumpgpio("lm3s_ssiinitialize() Entry)"); + lm3s_configgpio(SDCCS_GPIO); +#ifdef CONFIG_NX_LCDDRIVER + lm3s_configgpio(OLEDCS_GPIO); +#endif + ssi_dumpgpio("lm3s_ssiinitialize() Exit"); +} + +/**************************************************************************** + * The external functions, lm3s_spiselect and lm3s_spistatus must be provided + * by board-specific logic. The are implementations of the select and status + * methods SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h). + * All othermethods (including up_spiinitialize()) are provided by common + * logic. To use this common SPI logic on your board: + * + * 1. Provide lm3s_spiselect() and lm3s_spistatus() functions in your + * board-specific logic. This function will perform chip selection and + * status operations using GPIOs in the way your board is configured. + * 2. Add a call to up_spiinitialize() in your low level initialization + * logic + * 3. The handle returned by up_spiinitialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +{ + ssidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + ssi_dumpgpio("lm3s_spiselect() Entry"); + + if (devid == SPIDEV_MMCSD) + { + /* Assert the CS pin to the card */ + + lm3s_gpiowrite(SDCCS_GPIO, !selected); + } +#ifdef CONFIG_NX_LCDDRIVER + else if (devid == SPIDEV_DISPLAY) + { + /* Assert the CS pin to the display */ + + lm3s_gpiowrite(OLEDCS_GPIO, !selected); + } +#endif + ssi_dumpgpio("lm3s_spiselect() Exit"); +} + +uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ + ssidbg("Returning SPI_STATUS_PRESENT\n"); + return SPI_STATUS_PRESENT; +} + +#endif /* !CONFIG_SSI0_DISABLE || !CONFIG_SSI1_DISABLE */ diff --git a/configs/lm3s8962-ek/include/board.h b/configs/lm3s8962-ek/include/board.h index 016cf54ce75a727a309ffee889909ece483ab8cb..0b03f96f042413d59f51151c9367883a88ed4389 100755 --- a/configs/lm3s8962-ek/include/board.h +++ b/configs/lm3s8962-ek/include/board.h @@ -3,7 +3,7 @@ * include/arch/board/board.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/nsh/Make.defs b/configs/lm3s8962-ek/nsh/Make.defs index ed81aa0964c1ce764c34ce7070ad0c9a4ec8ef3c..cd183ed15edfd82a67a4dcfc98a695be4b15b446 100755 --- a/configs/lm3s8962-ek/nsh/Make.defs +++ b/configs/lm3s8962-ek/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/lm3s8962-ek/nsh/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/nsh/defconfig b/configs/lm3s8962-ek/nsh/defconfig index 4c51b681aedeb1f5674a36231a0c5359078162e4..439165c904e4d9512b6a9fb478797fee3a4910c9 100755 --- a/configs/lm3s8962-ek/nsh/defconfig +++ b/configs/lm3s8962-ek/nsh/defconfig @@ -2,7 +2,7 @@ # configs/lm3s8962-ek/nsh/defconfig # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/nsh/ld.script b/configs/lm3s8962-ek/nsh/ld.script index 34b8a6bd7d5dedc681eed59d836f70719f59b449..fdf7c896897c20528ff0bd5fec88de64bcc07fe3 100755 --- a/configs/lm3s8962-ek/nsh/ld.script +++ b/configs/lm3s8962-ek/nsh/ld.script @@ -2,7 +2,7 @@ * configs/lm3s8962-ek/nsh/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/nsh/setenv.sh b/configs/lm3s8962-ek/nsh/setenv.sh index 417ed66a1d93e9b32785db2e5d56b68db1c123f7..4ed5385b639c39c620a55ff8f8bae37d82c7bbc4 100755 --- a/configs/lm3s8962-ek/nsh/setenv.sh +++ b/configs/lm3s8962-ek/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/lm3s8962-ek/nsh/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/nx/Make.defs b/configs/lm3s8962-ek/nx/Make.defs index 8f1b3837dfa406499780132a2ed8258646312547..8417734772349479275e6a90f30dffe735c10cbc 100755 --- a/configs/lm3s8962-ek/nx/Make.defs +++ b/configs/lm3s8962-ek/nx/Make.defs @@ -2,7 +2,7 @@ # configs/lm3s8962-ek/nx/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/nx/appconfig b/configs/lm3s8962-ek/nx/appconfig index 1c730279b270ec5f1badb899fb8d75a7a86d7ec1..ace182b6291df64e495c83352ca9f0fb3856462d 100644 --- a/configs/lm3s8962-ek/nx/appconfig +++ b/configs/lm3s8962-ek/nx/appconfig @@ -2,7 +2,7 @@ # configs/lm3s8962-ek/nx/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/nx/defconfig b/configs/lm3s8962-ek/nx/defconfig index d3e0f2ffd2e80f7a03e06efbeb2d33c7c7945a08..823d62ae958be9c9d01477bbaa991f9c34eb6f5c 100755 --- a/configs/lm3s8962-ek/nx/defconfig +++ b/configs/lm3s8962-ek/nx/defconfig @@ -2,7 +2,7 @@ # configs/lm3s8962-ek/nx/defconfig # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/nx/ld.script b/configs/lm3s8962-ek/nx/ld.script index fa4c9e11095765dcf57f578592b62e4cfd0be079..71f0be6c517939bbf53906c9c687fce64633d5a2 100755 --- a/configs/lm3s8962-ek/nx/ld.script +++ b/configs/lm3s8962-ek/nx/ld.script @@ -2,7 +2,7 @@ * configs/lm3s8962-ek/nx/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/nx/setenv.sh b/configs/lm3s8962-ek/nx/setenv.sh index 2122e811fef3c5fc7ae64695e3ff8cd0ab73a342..4c76fd736925fcda6bceebec5c1490b7995a1d63 100755 --- a/configs/lm3s8962-ek/nx/setenv.sh +++ b/configs/lm3s8962-ek/nx/setenv.sh @@ -2,7 +2,7 @@ # configs/lm3s8962-ek/nx/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/ostest/Make.defs b/configs/lm3s8962-ek/ostest/Make.defs index d10957130b891cb4d29c6da9e2387c5940ac4a8a..914e96eb6106cbb9c58b84aa6ef88ae4f4f4596a 100755 --- a/configs/lm3s8962-ek/ostest/Make.defs +++ b/configs/lm3s8962-ek/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/lm3s8962-ek/ostest/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/ostest/appconfig b/configs/lm3s8962-ek/ostest/appconfig index 3ff28ef03e4a5bda40e0e2ee6ae53506b3bf09d0..f7475bcedfda04ddda8cbbcd80f10e859e8c1a4d 100644 --- a/configs/lm3s8962-ek/ostest/appconfig +++ b/configs/lm3s8962-ek/ostest/appconfig @@ -2,7 +2,7 @@ # configs/lm3s8962-ek/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/ostest/defconfig b/configs/lm3s8962-ek/ostest/defconfig index cea2d5c1e5d49c3e9196b6f21235d26095555b71..291f4e1f26877c6bbb49acc871e79e366f6268b3 100755 --- a/configs/lm3s8962-ek/ostest/defconfig +++ b/configs/lm3s8962-ek/ostest/defconfig @@ -2,7 +2,7 @@ # configs/lm3s8962-ek/ostest/defconfig # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/ostest/ld.script b/configs/lm3s8962-ek/ostest/ld.script index 08ea906bf12108cca60e48e473e9389684d1e21f..6aa9f5f3743f51b4d0a58c7192139d97c81e78df 100755 --- a/configs/lm3s8962-ek/ostest/ld.script +++ b/configs/lm3s8962-ek/ostest/ld.script @@ -2,7 +2,7 @@ * configs/lm3s8962-ek/ostest/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/ostest/setenv.sh b/configs/lm3s8962-ek/ostest/setenv.sh index ff8e4432ec3b38bca59dbf0518afaa4572a78de8..b5ee8be314284e492e01b423709d30c84ebf8f29 100755 --- a/configs/lm3s8962-ek/ostest/setenv.sh +++ b/configs/lm3s8962-ek/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/lm3s8962-ek/ostest/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/src/Makefile b/configs/lm3s8962-ek/src/Makefile index 7721e7e9411621ca2c1bbbf51c96d54d071cb032..2d44db56c9812ca230d11a663a4a452adb54da67 100644 --- a/configs/lm3s8962-ek/src/Makefile +++ b/configs/lm3s8962-ek/src/Makefile @@ -2,7 +2,7 @@ # configs/lm3s8962-ek/src/Makefile # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/src/lm3s8962ek_internal.h b/configs/lm3s8962-ek/src/lm3s8962ek_internal.h index 0c21e5d4b48e60d98db6b07d55496001affe0e5c..3b6175661b654af7a28feebf93197d88b6163435 100644 --- a/configs/lm3s8962-ek/src/lm3s8962ek_internal.h +++ b/configs/lm3s8962-ek/src/lm3s8962ek_internal.h @@ -1,136 +1,136 @@ -/************************************************************************************ - * configs/lm3s8962-ek/src/lm3s8962ek_internal.h - * arch/arm/src/board/lm3s8962ek_internal.n - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __CONFIGS_LM3S8962_EK_SRC_LM3S8962EK_INTERNAL_H -#define __CONFIGS_LM3S8962_EK_SRC_LM3S8962EK_INTERNAL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#include "chip.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* How many SSI modules does this chip support? The LM3S8962 supports 1 SSI - * module (others may support more than 2 -- in such case, the following must be - * expanded). - */ - -#if LM3S_NSSI == 0 -# undef CONFIG_SSI0_DISABLE -# define CONFIG_SSI0_DISABLE 1 -# undef CONFIG_SSI1_DISABLE -# define CONFIG_SSI1_DISABLE 1 -#elif LM3S_NSSI == 1 -# undef CONFIG_SSI1_DISABLE -# define CONFIG_SSI1_DISABLE 1 -#endif - -/* LM3S8962 Eval Kit ***************************************************************/ - -/* GPIO Usage - * - * PIN SIGNAL EVB Function - * --- ----------- --------------------------------------- - * 26 PA0/U0RX Virtual COM port receive - * 27 PA1/U0TX Virtual COM port transmit - * 10 PD0/IDX0 SD card chip select - * 11 PD1/PWM1 Sound - * 30 PA4/SSI0RX SD card data out - * 31 PA5/SSI0TX SD card and OLED display data in - * 28 PA2/SSI0CLK SD card and OLED display clock - * 22 PC7/PHB0 OLED display data/control select - * 29 PA3/SSI0FSS OLED display chip select - * 73 PE1/PWM5 Down switch - * 74 PE2/PHB1 Left switch - * 72 PE0/PWM4 Up switch - * 75 PE3/PHA1 Right switch - * 61 PF1/IDX1 Select switch - * 47 PF0/PWM0 User LED - * 23 PC6/CCP3 Enable +15 V - */ - -/* GPIO for microSD card chip select: - * - PD0: SD card chip select (CARDCSn) - */ - -#define SDCCS_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STDWPU | GPIO_STRENGTH_4MA | \ - GPIO_VALUE_ONE | GPIO_PORTD | 0) - -/* GPIO for single LED: - * - PF0: User LED - */ - -#define LED_GPIO (GPIO_FUNC_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTF | 0) - -/* GPIOs for OLED: - * - PC7: OLED display data/control select (D/Cn) - * - PA3: OLED display chip select (CSn) - * - PC6: Enable +15V needed by OLED (EN+15V) - */ - -#define OLEDDC_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STD | GPIO_STRENGTH_8MA | \ - GPIO_VALUE_ONE | GPIO_PORTC | 7) -#define OLEDCS_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STDWPU | GPIO_STRENGTH_4MA | \ - GPIO_VALUE_ONE | GPIO_PORTA | 3) -#define OLEDEN_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STD | GPIO_STRENGTH_8MA | \ - GPIO_VALUE_ONE | GPIO_PORTC | 6) - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Name: lm3s_ssiinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the LM3S8962 Eval Kit. - * - ************************************************************************************/ - -extern void weak_function lm3s_ssiinitialize(void); - -#endif /* __ASSEMBLY__ */ -#endif /* __CONFIGS_LM3S8962_EK_SRC_LM3S8962EK_INTERNAL_H */ - +/************************************************************************************ + * configs/lm3s8962-ek/src/lm3s8962ek_internal.h + * arch/arm/src/board/lm3s8962ek_internal.n + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_LM3S8962_EK_SRC_LM3S8962EK_INTERNAL_H +#define __CONFIGS_LM3S8962_EK_SRC_LM3S8962EK_INTERNAL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "chip.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* How many SSI modules does this chip support? The LM3S8962 supports 1 SSI + * module (others may support more than 2 -- in such case, the following must be + * expanded). + */ + +#if LM3S_NSSI == 0 +# undef CONFIG_SSI0_DISABLE +# define CONFIG_SSI0_DISABLE 1 +# undef CONFIG_SSI1_DISABLE +# define CONFIG_SSI1_DISABLE 1 +#elif LM3S_NSSI == 1 +# undef CONFIG_SSI1_DISABLE +# define CONFIG_SSI1_DISABLE 1 +#endif + +/* LM3S8962 Eval Kit ***************************************************************/ + +/* GPIO Usage + * + * PIN SIGNAL EVB Function + * --- ----------- --------------------------------------- + * 26 PA0/U0RX Virtual COM port receive + * 27 PA1/U0TX Virtual COM port transmit + * 10 PD0/IDX0 SD card chip select + * 11 PD1/PWM1 Sound + * 30 PA4/SSI0RX SD card data out + * 31 PA5/SSI0TX SD card and OLED display data in + * 28 PA2/SSI0CLK SD card and OLED display clock + * 22 PC7/PHB0 OLED display data/control select + * 29 PA3/SSI0FSS OLED display chip select + * 73 PE1/PWM5 Down switch + * 74 PE2/PHB1 Left switch + * 72 PE0/PWM4 Up switch + * 75 PE3/PHA1 Right switch + * 61 PF1/IDX1 Select switch + * 47 PF0/PWM0 User LED + * 23 PC6/CCP3 Enable +15 V + */ + +/* GPIO for microSD card chip select: + * - PD0: SD card chip select (CARDCSn) + */ + +#define SDCCS_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STDWPU | GPIO_STRENGTH_4MA | \ + GPIO_VALUE_ONE | GPIO_PORTD | 0) + +/* GPIO for single LED: + * - PF0: User LED + */ + +#define LED_GPIO (GPIO_FUNC_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTF | 0) + +/* GPIOs for OLED: + * - PC7: OLED display data/control select (D/Cn) + * - PA3: OLED display chip select (CSn) + * - PC6: Enable +15V needed by OLED (EN+15V) + */ + +#define OLEDDC_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STD | GPIO_STRENGTH_8MA | \ + GPIO_VALUE_ONE | GPIO_PORTC | 7) +#define OLEDCS_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STDWPU | GPIO_STRENGTH_4MA | \ + GPIO_VALUE_ONE | GPIO_PORTA | 3) +#define OLEDEN_GPIO (GPIO_FUNC_OUTPUT | GPIO_PADTYPE_STD | GPIO_STRENGTH_8MA | \ + GPIO_VALUE_ONE | GPIO_PORTC | 6) + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Name: lm3s_ssiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the LM3S8962 Eval Kit. + * + ************************************************************************************/ + +extern void weak_function lm3s_ssiinitialize(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_LM3S8962_EK_SRC_LM3S8962EK_INTERNAL_H */ + diff --git a/configs/lm3s8962-ek/src/up_boot.c b/configs/lm3s8962-ek/src/up_boot.c index 2992b00c125c641d5ef77420ecf01b145855f2d6..0a976e85723cf1bad980f1e3b1de270331e2685a 100644 --- a/configs/lm3s8962-ek/src/up_boot.c +++ b/configs/lm3s8962-ek/src/up_boot.c @@ -1,92 +1,92 @@ -/************************************************************************************ - * configs/lm3s8962-ek/src/up_boot.c - * arch/arm/src/board/up_boot.c - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include - -#include - -#include "up_arch.h" -#include "up_internal.h" -#include "lm3s8962ek_internal.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: lm3s_boardinitialize - * - * Description: - * All LM3S architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - ************************************************************************************/ - -void lm3s_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SSI is not disabled, and 2) the weak function - * lm3s_ssiinitialize() has been brought into the link. - */ - - /* The LM3S8962 Eval Kit microSD CS and OLED are on SSI0 (Duh! There is no SSI1) */ - -#if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */ - if (lm3s_ssiinitialize) - { - lm3s_ssiinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - up_ledinit(); -#endif -} +/************************************************************************************ + * configs/lm3s8962-ek/src/up_boot.c + * arch/arm/src/board/up_boot.c + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" +#include "lm3s8962ek_internal.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lm3s_boardinitialize + * + * Description: + * All LM3S architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + ************************************************************************************/ + +void lm3s_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SSI is not disabled, and 2) the weak function + * lm3s_ssiinitialize() has been brought into the link. + */ + + /* The LM3S8962 Eval Kit microSD CS and OLED are on SSI0 (Duh! There is no SSI1) */ + +#if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */ + if (lm3s_ssiinitialize) + { + lm3s_ssiinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + up_ledinit(); +#endif +} diff --git a/configs/lm3s8962-ek/src/up_ethernet.c b/configs/lm3s8962-ek/src/up_ethernet.c index 457e5609138aba02e1eb4d6dc44dd4bd52292cc6..2cad50bef96c7dbcdfac283ad31dab39933ef670 100644 --- a/configs/lm3s8962-ek/src/up_ethernet.c +++ b/configs/lm3s8962-ek/src/up_ethernet.c @@ -1,98 +1,98 @@ -/************************************************************************************ - * configs/lm3s8962-ek/src/up_ethernet.c - * arch/arm/src/board/up_ethernet.c - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "up_arch.h" -#include "chip.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: lm3s_ethernetmac - * - * Description: - * For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile - * USER0 and USER1 registers. If CONFIG_LM3S_BOARDMAC is defined, this function - * will obtain the MAC address from these registers. - * - ************************************************************************************/ - -#ifdef CONFIG_LM3S_BOARDMAC -void lm3s_ethernetmac(struct ether_addr *ethaddr) -{ - uint32_t user0; - uint32_t user1; - - /* Get the current value of the user registers */ - - user0 = getreg32(LM3S_FLASH_USERREG0); - user1 = getreg32(LM3S_FLASH_USERREG1); - - nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff); - DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff); - - /* Re-format that MAC address the way that uIP expects to see it */ - - ethaddr->ether_addr_octet[0] = ((user0 >> 0) & 0xff); - ethaddr->ether_addr_octet[1] = ((user0 >> 8) & 0xff); - ethaddr->ether_addr_octet[2] = ((user0 >> 16) & 0xff); - ethaddr->ether_addr_octet[3] = ((user1 >> 0) & 0xff); - ethaddr->ether_addr_octet[4] = ((user1 >> 8) & 0xff); - ethaddr->ether_addr_octet[5] = ((user1 >> 16) & 0xff); -} -#endif +/************************************************************************************ + * configs/lm3s8962-ek/src/up_ethernet.c + * arch/arm/src/board/up_ethernet.c + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "chip.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lm3s_ethernetmac + * + * Description: + * For the Ethernet Eval Kits, the MAC address will be stored in the non-volatile + * USER0 and USER1 registers. If CONFIG_LM3S_BOARDMAC is defined, this function + * will obtain the MAC address from these registers. + * + ************************************************************************************/ + +#ifdef CONFIG_LM3S_BOARDMAC +void lm3s_ethernetmac(struct ether_addr *ethaddr) +{ + uint32_t user0; + uint32_t user1; + + /* Get the current value of the user registers */ + + user0 = getreg32(LM3S_FLASH_USERREG0); + user1 = getreg32(LM3S_FLASH_USERREG1); + + nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff); + DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff); + + /* Re-format that MAC address the way that uIP expects to see it */ + + ethaddr->ether_addr_octet[0] = ((user0 >> 0) & 0xff); + ethaddr->ether_addr_octet[1] = ((user0 >> 8) & 0xff); + ethaddr->ether_addr_octet[2] = ((user0 >> 16) & 0xff); + ethaddr->ether_addr_octet[3] = ((user1 >> 0) & 0xff); + ethaddr->ether_addr_octet[4] = ((user1 >> 8) & 0xff); + ethaddr->ether_addr_octet[5] = ((user1 >> 16) & 0xff); +} +#endif diff --git a/configs/lm3s8962-ek/src/up_leds.c b/configs/lm3s8962-ek/src/up_leds.c index 1592168d787c03e5d17d1f3ae3639dbb1f41242c..bff920434150d55a4d3089a7566dcf40e83c1edb 100644 --- a/configs/lm3s8962-ek/src/up_leds.c +++ b/configs/lm3s8962-ek/src/up_leds.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_leds.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/src/up_nsh.c b/configs/lm3s8962-ek/src/up_nsh.c index c95dce7a93238084406c46e937223bcaf1a89617..693862184565ccace3a3b18efbd305845793dd24 100644 --- a/configs/lm3s8962-ek/src/up_nsh.c +++ b/configs/lm3s8962-ek/src/up_nsh.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_nsh.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/src/up_oled.c b/configs/lm3s8962-ek/src/up_oled.c index 55f76889402b28c5e24a106b6999bfe28945d36b..7611872794ac7cb7c0ef55ae0a8b67a6634b38b8 100644 --- a/configs/lm3s8962-ek/src/up_oled.c +++ b/configs/lm3s8962-ek/src/up_oled.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_oled.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lm3s8962-ek/src/up_ssi.c b/configs/lm3s8962-ek/src/up_ssi.c index 27899b5bfa081dcf49b4f4b580a6dd3afb0dc8e9..00e07c85d0a98b501d560de0581424c035895399 100644 --- a/configs/lm3s8962-ek/src/up_ssi.c +++ b/configs/lm3s8962-ek/src/up_ssi.c @@ -1,164 +1,164 @@ -/************************************************************************************ - * configs/lm3s8962-ek/src/up_ssi.c - * arch/arm/src/board/up_ssi.c - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "up_arch.h" -#include "chip.h" -#include "lm3s_internal.h" -#include "lm3s8962ek_internal.h" - -/* The LM3S8962 Eval Kit microSD CS is on SSI0 */ - -#if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */ - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* Enables debug output from this file (needs CONFIG_DEBUG too) */ - -#undef SSI_DEBUG /* Define to enable debug */ -#undef SSI_VERBOSE /* Define to enable verbose debug */ - -#ifdef SSI_DEBUG -# define ssidbg lldbg -# ifdef SSI_VERBOSE -# define ssivdbg lldbg -# else -# define ssivdbg(x...) -# endif -#else -# undef SSI_VERBOSE -# define ssidbg(x...) -# define ssivdbg(x...) -#endif - -/* Dump GPIO registers */ - -#ifdef SSI_VERBOSE -# define ssi_dumpgpio(m) lm3s_dumpgpio(SDCCS_GPIO, m) -#else -# define ssi_dumpgpio(m) -#endif - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: lm3s_ssiinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the LM3S8962 Eval Kit. - * - ************************************************************************************/ - -void weak_function lm3s_ssiinitialize(void) -{ - /* Configure the SPI-based microSD CS GPIO */ - - ssi_dumpgpio("lm3s_ssiinitialize() Entry)"); - lm3s_configgpio(SDCCS_GPIO); -#ifdef CONFIG_NX_LCDDRIVER - lm3s_configgpio(OLEDCS_GPIO); -#endif - ssi_dumpgpio("lm3s_ssiinitialize() Exit"); -} - -/**************************************************************************** - * The external functions, lm3s_spiselect and lm3s_spistatus must be provided - * by board-specific logic. The are implementations of the select and status - * methods SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h). - * All othermethods (including up_spiinitialize()) are provided by common - * logic. To use this common SPI logic on your board: - * - * 1. Provide lm3s_spiselect() and lm3s_spistatus() functions in your - * board-specific logic. This function will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 2. Add a call to up_spiinitialize() in your low level initialization - * logic - * 3. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) -{ - ssidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssi_dumpgpio("lm3s_spiselect() Entry"); - - if (devid == SPIDEV_MMCSD) - { - /* Assert the CS pin to the card */ - - lm3s_gpiowrite(SDCCS_GPIO, !selected); - } -#ifdef CONFIG_NX_LCDDRIVER - else if (devid == SPIDEV_DISPLAY) - { - /* Assert the CS pin to the display */ - - lm3s_gpiowrite(OLEDCS_GPIO, !selected); - } -#endif - ssi_dumpgpio("lm3s_spiselect() Exit"); -} - -uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) -{ - ssidbg("Returning SPI_STATUS_PRESENT\n"); - return SPI_STATUS_PRESENT; -} - -#endif /* !CONFIG_SSI0_DISABLE || !CONFIG_SSI1_DISABLE */ +/************************************************************************************ + * configs/lm3s8962-ek/src/up_ssi.c + * arch/arm/src/board/up_ssi.c + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "chip.h" +#include "lm3s_internal.h" +#include "lm3s8962ek_internal.h" + +/* The LM3S8962 Eval Kit microSD CS is on SSI0 */ + +#if !defined(CONFIG_SSI0_DISABLE) /* || !defined(CONFIG_SSI1_DISABLE) */ + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Enables debug output from this file (needs CONFIG_DEBUG too) */ + +#undef SSI_DEBUG /* Define to enable debug */ +#undef SSI_VERBOSE /* Define to enable verbose debug */ + +#ifdef SSI_DEBUG +# define ssidbg lldbg +# ifdef SSI_VERBOSE +# define ssivdbg lldbg +# else +# define ssivdbg(x...) +# endif +#else +# undef SSI_VERBOSE +# define ssidbg(x...) +# define ssivdbg(x...) +#endif + +/* Dump GPIO registers */ + +#ifdef SSI_VERBOSE +# define ssi_dumpgpio(m) lm3s_dumpgpio(SDCCS_GPIO, m) +#else +# define ssi_dumpgpio(m) +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lm3s_ssiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the LM3S8962 Eval Kit. + * + ************************************************************************************/ + +void weak_function lm3s_ssiinitialize(void) +{ + /* Configure the SPI-based microSD CS GPIO */ + + ssi_dumpgpio("lm3s_ssiinitialize() Entry)"); + lm3s_configgpio(SDCCS_GPIO); +#ifdef CONFIG_NX_LCDDRIVER + lm3s_configgpio(OLEDCS_GPIO); +#endif + ssi_dumpgpio("lm3s_ssiinitialize() Exit"); +} + +/**************************************************************************** + * The external functions, lm3s_spiselect and lm3s_spistatus must be provided + * by board-specific logic. The are implementations of the select and status + * methods SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h). + * All othermethods (including up_spiinitialize()) are provided by common + * logic. To use this common SPI logic on your board: + * + * 1. Provide lm3s_spiselect() and lm3s_spistatus() functions in your + * board-specific logic. This function will perform chip selection and + * status operations using GPIOs in the way your board is configured. + * 2. Add a call to up_spiinitialize() in your low level initialization + * logic + * 3. The handle returned by up_spiinitialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +void lm3s_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +{ + ssidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + ssi_dumpgpio("lm3s_spiselect() Entry"); + + if (devid == SPIDEV_MMCSD) + { + /* Assert the CS pin to the card */ + + lm3s_gpiowrite(SDCCS_GPIO, !selected); + } +#ifdef CONFIG_NX_LCDDRIVER + else if (devid == SPIDEV_DISPLAY) + { + /* Assert the CS pin to the display */ + + lm3s_gpiowrite(OLEDCS_GPIO, !selected); + } +#endif + ssi_dumpgpio("lm3s_spiselect() Exit"); +} + +uint8_t lm3s_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ + ssidbg("Returning SPI_STATUS_PRESENT\n"); + return SPI_STATUS_PRESENT; +} + +#endif /* !CONFIG_SSI0_DISABLE || !CONFIG_SSI1_DISABLE */ diff --git a/configs/lpc4330-xplorer/nsh/setenv.sh b/configs/lpc4330-xplorer/nsh/setenv.sh index 65e410fc64d8a86f5912428b3b14ed0f40c2392c..64109ce38ccd27a4000cc687d54fdf6eda194429 100755 --- a/configs/lpc4330-xplorer/nsh/setenv.sh +++ b/configs/lpc4330-xplorer/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/lpc4330-xplorer/nsh/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpc4330-xplorer/ostest/setenv.sh b/configs/lpc4330-xplorer/ostest/setenv.sh index ec93482fd2ffd102c09be803d64ee3a9ba611b73..8ac6da66b1038ff3eddd9c0936ab5296d3e4a652 100755 --- a/configs/lpc4330-xplorer/ostest/setenv.sh +++ b/configs/lpc4330-xplorer/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/lpc4330-xplorer/ostest/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/dhcpd/Make.defs b/configs/lpcxpresso-lpc1768/dhcpd/Make.defs index 6c583c2d1c8a638cbbe2ab79e05b030d696204ad..2c91b76b5e73251ceffcd8c28fb6f7ca25ba8f62 100755 --- a/configs/lpcxpresso-lpc1768/dhcpd/Make.defs +++ b/configs/lpcxpresso-lpc1768/dhcpd/Make.defs @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/dhcpd/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/dhcpd/appconfig b/configs/lpcxpresso-lpc1768/dhcpd/appconfig index 6a901d09fe54a0289796b13404beb0c49af5e711..76a9d2e71f9644590c8638d5375fab60686d7a03 100644 --- a/configs/lpcxpresso-lpc1768/dhcpd/appconfig +++ b/configs/lpcxpresso-lpc1768/dhcpd/appconfig @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/dhcpd/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/dhcpd/ld.script b/configs/lpcxpresso-lpc1768/dhcpd/ld.script index d57e8f4183fa4a5ee628122382752435b9a8ea4b..d8f44447534c0227c5e53ffd6af8c4b101c67f76 100755 --- a/configs/lpcxpresso-lpc1768/dhcpd/ld.script +++ b/configs/lpcxpresso-lpc1768/dhcpd/ld.script @@ -2,7 +2,7 @@ * configs/lpcxpresso-lpc1768/dhcpd/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/dhcpd/setenv.sh b/configs/lpcxpresso-lpc1768/dhcpd/setenv.sh index bab486c18bd8ae7e77581d22e0c37fca3986323d..6bc6e10c97d8032961f6b3df9026a77aae5fb20c 100755 --- a/configs/lpcxpresso-lpc1768/dhcpd/setenv.sh +++ b/configs/lpcxpresso-lpc1768/dhcpd/setenv.sh @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/dhcpd/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/include/board.h b/configs/lpcxpresso-lpc1768/include/board.h index fe4dc7144483c8b168740a08c1c2d4adf4f13cb8..10af5dfc1a339b5d3750fd012b5836f774a2c4d4 100755 --- a/configs/lpcxpresso-lpc1768/include/board.h +++ b/configs/lpcxpresso-lpc1768/include/board.h @@ -3,7 +3,7 @@ * include/arch/board/board.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/nsh/Make.defs b/configs/lpcxpresso-lpc1768/nsh/Make.defs index c902e94f7703cc0b3ffa512db0d11b979bb5399d..7a29f704326bdf7c10fca4772b953caef267a440 100755 --- a/configs/lpcxpresso-lpc1768/nsh/Make.defs +++ b/configs/lpcxpresso-lpc1768/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/nsh/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/nsh/ld.script b/configs/lpcxpresso-lpc1768/nsh/ld.script index 0d8103b2e161a99e63df9784f6272ac26b73ba5c..f37c4accb05276dbff5d559a708afddf97278d45 100755 --- a/configs/lpcxpresso-lpc1768/nsh/ld.script +++ b/configs/lpcxpresso-lpc1768/nsh/ld.script @@ -2,7 +2,7 @@ * configs/lpcxpresso-lpc1768/nsh/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/nsh/setenv.sh b/configs/lpcxpresso-lpc1768/nsh/setenv.sh index fea794e86d0f5d560acf7ddc2629a7b8ede8b333..77f745c76a8b9ccc93545019003da8f78960611c 100755 --- a/configs/lpcxpresso-lpc1768/nsh/setenv.sh +++ b/configs/lpcxpresso-lpc1768/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/nsh/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/nx/Make.defs b/configs/lpcxpresso-lpc1768/nx/Make.defs index ce07973f24b92e8fad5319eae05268a6f3a70fc8..061d4ff68f5538c115150b7ae689ce25868b4bb3 100755 --- a/configs/lpcxpresso-lpc1768/nx/Make.defs +++ b/configs/lpcxpresso-lpc1768/nx/Make.defs @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/nx/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/nx/appconfig b/configs/lpcxpresso-lpc1768/nx/appconfig index 9523a5a0a2bd2e22e72352fd03faeb7dc823a256..a590ace67d4a0ec091d9cc1b00be52ff3581b19a 100644 --- a/configs/lpcxpresso-lpc1768/nx/appconfig +++ b/configs/lpcxpresso-lpc1768/nx/appconfig @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/nx/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/nx/ld.script b/configs/lpcxpresso-lpc1768/nx/ld.script index d59cfda3832fbadba29e1923fffd6749bd414acf..f1a49e3aab67434176e7731d3373e3f757622f6c 100755 --- a/configs/lpcxpresso-lpc1768/nx/ld.script +++ b/configs/lpcxpresso-lpc1768/nx/ld.script @@ -2,7 +2,7 @@ * configs/lpcxpresso-lpc1768/nx/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/nx/setenv.sh b/configs/lpcxpresso-lpc1768/nx/setenv.sh index b4f3faa3f9d86e94c12f4c01059152290d7e1e6d..711d92ea479a83736e62dc8b86657d21b57304e7 100755 --- a/configs/lpcxpresso-lpc1768/nx/setenv.sh +++ b/configs/lpcxpresso-lpc1768/nx/setenv.sh @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/nx/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/ostest/Make.defs b/configs/lpcxpresso-lpc1768/ostest/Make.defs index e7350094ee1daf31f8962fdbf9686c199c22b67c..496c54be44176f3e3d1a42f602b1e9e19b444098 100755 --- a/configs/lpcxpresso-lpc1768/ostest/Make.defs +++ b/configs/lpcxpresso-lpc1768/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/ostest/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/ostest/appconfig b/configs/lpcxpresso-lpc1768/ostest/appconfig index 055914983a0a29dd71b033746b94544f98219bd7..f20cf33dc48cec16f0a1ace03ee0cabc79ecde82 100644 --- a/configs/lpcxpresso-lpc1768/ostest/appconfig +++ b/configs/lpcxpresso-lpc1768/ostest/appconfig @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/ostest/ld.script b/configs/lpcxpresso-lpc1768/ostest/ld.script index a85bc2b048f82add10c408551398abe598e97029..da29a1482ecb6fe77180c73d714bd244ffa118f2 100755 --- a/configs/lpcxpresso-lpc1768/ostest/ld.script +++ b/configs/lpcxpresso-lpc1768/ostest/ld.script @@ -2,7 +2,7 @@ * configs/lpcxpresso-lpc1768/ostest/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/ostest/setenv.sh b/configs/lpcxpresso-lpc1768/ostest/setenv.sh index 7f902d549bbc2ac2e88cb01632b5dbd842a757e3..db976c9469c8c63dbe66d7e0cf14cd6dcfa4aebf 100755 --- a/configs/lpcxpresso-lpc1768/ostest/setenv.sh +++ b/configs/lpcxpresso-lpc1768/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/ostest/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/src/Makefile b/configs/lpcxpresso-lpc1768/src/Makefile index abc43d41c0787b3e5161a862324501e410dd28f8..7384b04d47bff039717dd90be3aaa0aac92d4049 100644 --- a/configs/lpcxpresso-lpc1768/src/Makefile +++ b/configs/lpcxpresso-lpc1768/src/Makefile @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/src/Makefile # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/src/lpcxpresso_internal.h b/configs/lpcxpresso-lpc1768/src/lpcxpresso_internal.h index 43237a0c2bd5424fab0332e1c46d1b65d5f6a661..41ec1ce111b3bdd319e33d9601ca185a70c26440 100644 --- a/configs/lpcxpresso-lpc1768/src/lpcxpresso_internal.h +++ b/configs/lpcxpresso-lpc1768/src/lpcxpresso_internal.h @@ -3,7 +3,7 @@ * arch/arm/src/board/lpcxpresso_internal.n * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/src/up_boot.c b/configs/lpcxpresso-lpc1768/src/up_boot.c index 137df2f18680d36789acebcdf6680b234ac6635b..f672c4517d9b3cf9bbc0bfa2537e5c8ddf199b9f 100644 --- a/configs/lpcxpresso-lpc1768/src/up_boot.c +++ b/configs/lpcxpresso-lpc1768/src/up_boot.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_boot.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/src/up_leds.c b/configs/lpcxpresso-lpc1768/src/up_leds.c index 39c12e791627224f168edab1eeae92ad58d15ded..cebf3a143dde74a1e77a6197ba33223b6a3cc8f5 100644 --- a/configs/lpcxpresso-lpc1768/src/up_leds.c +++ b/configs/lpcxpresso-lpc1768/src/up_leds.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_leds.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/src/up_nsh.c b/configs/lpcxpresso-lpc1768/src/up_nsh.c index 0b643f27633af41e6c314738debb223c63c7d231..b9c39ed1631a21773a338f56d6b45ed6230367bf 100644 --- a/configs/lpcxpresso-lpc1768/src/up_nsh.c +++ b/configs/lpcxpresso-lpc1768/src/up_nsh.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_nsh.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/src/up_oled.c b/configs/lpcxpresso-lpc1768/src/up_oled.c index f3d884bb3963716cac6f483de959f653badc62be..7060a92e69fa856d436d8c3c2ba7084781f83a74 100644 --- a/configs/lpcxpresso-lpc1768/src/up_oled.c +++ b/configs/lpcxpresso-lpc1768/src/up_oled.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_oled.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/src/up_ssp.c b/configs/lpcxpresso-lpc1768/src/up_ssp.c index 6c81c7a0dde6f1795de67d95fc01a77904129819..894404cc2b6f2b76ee82c31ee2515c064d3f570f 100644 --- a/configs/lpcxpresso-lpc1768/src/up_ssp.c +++ b/configs/lpcxpresso-lpc1768/src/up_ssp.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_ssp.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/src/up_usbmsc.c b/configs/lpcxpresso-lpc1768/src/up_usbmsc.c index d368801226543dc7a57cfbfa68fad8bfb7bb63e4..c43028f1e344afc6c907ffe7473c157d54e203ba 100644 --- a/configs/lpcxpresso-lpc1768/src/up_usbmsc.c +++ b/configs/lpcxpresso-lpc1768/src/up_usbmsc.c @@ -2,7 +2,7 @@ * configs/lpcxpresso-lpc1768/src/up_usbmsc.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Configure and register the LPC17xx MMC/SD SPI block driver. * diff --git a/configs/lpcxpresso-lpc1768/thttpd/Make.defs b/configs/lpcxpresso-lpc1768/thttpd/Make.defs index 730638bbca1efcbaaa664dd5435e3b34222733e8..8f2823d0f7769f452ca21dd610c72f12df27e374 100755 --- a/configs/lpcxpresso-lpc1768/thttpd/Make.defs +++ b/configs/lpcxpresso-lpc1768/thttpd/Make.defs @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/thttpd/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/thttpd/appconfig b/configs/lpcxpresso-lpc1768/thttpd/appconfig index aaaa7c55c0a5e134798eb81b2fa15ce5840415fb..b6cac656abb8dfba5fff1470b170f0a7965c4f51 100644 --- a/configs/lpcxpresso-lpc1768/thttpd/appconfig +++ b/configs/lpcxpresso-lpc1768/thttpd/appconfig @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/thttpd/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/thttpd/ld.script b/configs/lpcxpresso-lpc1768/thttpd/ld.script index 4a897eb42b3be35e26730a19b71d9b868f53b67d..37ec2553275ebaf18cc341ed2adabccf281ba83d 100755 --- a/configs/lpcxpresso-lpc1768/thttpd/ld.script +++ b/configs/lpcxpresso-lpc1768/thttpd/ld.script @@ -2,7 +2,7 @@ * configs/lpcxpresso-lpc1768/thttpd/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/thttpd/setenv.sh b/configs/lpcxpresso-lpc1768/thttpd/setenv.sh index 932b23065612722b997de0b4068f4ac1c8ef074e..158c8a44242401227f958735ff805cbeeb4445dc 100755 --- a/configs/lpcxpresso-lpc1768/thttpd/setenv.sh +++ b/configs/lpcxpresso-lpc1768/thttpd/setenv.sh @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/thttpd/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/tools/flash.sh b/configs/lpcxpresso-lpc1768/tools/flash.sh index 0dc285132792c734d2bf0834339a06b7f40849c9..4faa709ca0eb7e10c5a53e606772cf7a3854808a 100755 --- a/configs/lpcxpresso-lpc1768/tools/flash.sh +++ b/configs/lpcxpresso-lpc1768/tools/flash.sh @@ -3,7 +3,7 @@ # flash.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/usbstorage/Make.defs b/configs/lpcxpresso-lpc1768/usbstorage/Make.defs index 9033e3e2e55f750ab76679d138ead03d4ec2339e..5a60371428ccb1e96f1ce964dc3e5355ad215d51 100755 --- a/configs/lpcxpresso-lpc1768/usbstorage/Make.defs +++ b/configs/lpcxpresso-lpc1768/usbstorage/Make.defs @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/usbstorage/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/usbstorage/appconfig b/configs/lpcxpresso-lpc1768/usbstorage/appconfig index 1f158cd5e8ecf867c30e31e1a11ab99d1a27a8bc..a562cb91819397bbf3a245cae80db56da3dc023f 100644 --- a/configs/lpcxpresso-lpc1768/usbstorage/appconfig +++ b/configs/lpcxpresso-lpc1768/usbstorage/appconfig @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/usbstorage/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/usbstorage/ld.script b/configs/lpcxpresso-lpc1768/usbstorage/ld.script index bc431cb947fa179ad438a75fe48c8f0d079b73ea..7cccb8421fc92f8312d65bb312ae73c06c2d2f94 100755 --- a/configs/lpcxpresso-lpc1768/usbstorage/ld.script +++ b/configs/lpcxpresso-lpc1768/usbstorage/ld.script @@ -2,7 +2,7 @@ * configs/lpcxpresso-lpc1768/usbstorage/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/lpcxpresso-lpc1768/usbstorage/setenv.sh b/configs/lpcxpresso-lpc1768/usbstorage/setenv.sh index 4a6b1613d3169e41b48b16e1702d9daca07f874f..036de7aef15ce1b914e86e66e52af5f822366372 100755 --- a/configs/lpcxpresso-lpc1768/usbstorage/setenv.sh +++ b/configs/lpcxpresso-lpc1768/usbstorage/setenv.sh @@ -2,7 +2,7 @@ # configs/lpcxpresso-lpc1768/usbstorage/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/m68332evb/Make.defs b/configs/m68332evb/Make.defs index 897fb74da3e1b6a199d668041256c739884e5f66..a0e6aa1ea16e3b4590e35b4f66400c11a1345008 100644 --- a/configs/m68332evb/Make.defs +++ b/configs/m68332evb/Make.defs @@ -2,7 +2,7 @@ # configs/m68332evb/Make.defs # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/m68332evb/appconfig b/configs/m68332evb/appconfig index 779ae9305200fa5cc3675b565a60954cb7e29b94..4972941a6e6b70c766d17abfe977529a21617eb3 100644 --- a/configs/m68332evb/appconfig +++ b/configs/m68332evb/appconfig @@ -2,7 +2,7 @@ # configs/m68332evb/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/m68332evb/defconfig b/configs/m68332evb/defconfig index bad7f83420c1877b8c141c4b83b1068a200c726d..e3e8110a7dec697ab666b6e1219e81f05d3dd05c 100644 --- a/configs/m68332evb/defconfig +++ b/configs/m68332evb/defconfig @@ -2,7 +2,7 @@ # configs/m68332evb/defconfig # # Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/m68332evb/ld.script b/configs/m68332evb/ld.script index 0054ff1d17f782b7d50b4dcad136c3803da90386..ab65751aa5692d5b477a3081b41770f3e244f5b9 100644 --- a/configs/m68332evb/ld.script +++ b/configs/m68332evb/ld.script @@ -2,7 +2,7 @@ * ld.script * * Copyright (C) 2007 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/m68332evb/setenv.sh b/configs/m68332evb/setenv.sh index a5bb0f3b31dd32d118907820fa0765f9eea67859..2882011fdbb793c80037e3d706d7806f53b0e15c 100755 --- a/configs/m68332evb/setenv.sh +++ b/configs/m68332evb/setenv.sh @@ -2,7 +2,7 @@ # m68322evb/setenv.sh # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/m68332evb/src/Makefile b/configs/m68332evb/src/Makefile index 58bf0faf30514033522695d2c1faeb9ea7d382ae..f510c22190954c1f24f41419187fa7413cee3526 100644 --- a/configs/m68332evb/src/Makefile +++ b/configs/m68332evb/src/Makefile @@ -2,7 +2,7 @@ # configs/m68332evb/src/Makefile # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mbed/hidkbd/Make.defs b/configs/mbed/hidkbd/Make.defs index 16725d3d28ae8883f8b9ee7d226f8a2713ed81c6..d588e12fc20e859399ef38a0afa8351d8f9839f0 100644 --- a/configs/mbed/hidkbd/Make.defs +++ b/configs/mbed/hidkbd/Make.defs @@ -2,7 +2,7 @@ # configs/mbed/hidkbd/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mbed/hidkbd/appconfig b/configs/mbed/hidkbd/appconfig index 820167020e3fd426f7bf433a84f568dc7e464284..fa7e5e3c2ce1d6a9f2b5ea86bb3758996726c10f 100644 --- a/configs/mbed/hidkbd/appconfig +++ b/configs/mbed/hidkbd/appconfig @@ -2,7 +2,7 @@ # configs/mbed/hidkbd/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mbed/hidkbd/ld.script b/configs/mbed/hidkbd/ld.script index 0d497e7e51198f93c5e81965c550d4903acbeb00..152f8bc2a8487049ed75db5dded55de0e4eed728 100644 --- a/configs/mbed/hidkbd/ld.script +++ b/configs/mbed/hidkbd/ld.script @@ -2,7 +2,7 @@ * configs/olimex-lpc1766stk/hidkbd/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/mbed/hidkbd/setenv.sh b/configs/mbed/hidkbd/setenv.sh index f4063ee4a3ac6c1f4c53c8cc78b2eee2a3c03856..c3ca070e33873590c71c0994c8dcbbb95c0ef89f 100644 --- a/configs/mbed/hidkbd/setenv.sh +++ b/configs/mbed/hidkbd/setenv.sh @@ -2,7 +2,7 @@ # configs/mbed/hidkbd/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mbed/include/board.h b/configs/mbed/include/board.h index bec90d10f8a1a9dbe5a9d47719646ccec460de73..b2bda1f4c187c578fe9727794ce33038cd3fced9 100755 --- a/configs/mbed/include/board.h +++ b/configs/mbed/include/board.h @@ -3,7 +3,7 @@ * include/arch/board/board.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/mbed/nsh/Make.defs b/configs/mbed/nsh/Make.defs index 044361af4b50d83d53e17528faa0a8c056aa9598..dfc0a79689130d5bad80dd84cb094dd633548f4a 100755 --- a/configs/mbed/nsh/Make.defs +++ b/configs/mbed/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/mbed/nsh/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mbed/nsh/ld.script b/configs/mbed/nsh/ld.script index 75b47d36000d7939c6bf09ae36d1178decc6d9ef..d96d51dd9dfab7f4c278b4f05c103b42b940d6b4 100755 --- a/configs/mbed/nsh/ld.script +++ b/configs/mbed/nsh/ld.script @@ -2,7 +2,7 @@ * configs/mbed/nsh/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/mbed/nsh/setenv.sh b/configs/mbed/nsh/setenv.sh index 515d1c44cb61c58a764f701c3f570a59574fae69..f29d97589234a68e178d69ef0c4189599e3db0fc 100755 --- a/configs/mbed/nsh/setenv.sh +++ b/configs/mbed/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/mbed/nsh/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mbed/src/Makefile b/configs/mbed/src/Makefile index 9841a90a5f93e1e6f291d3ba8f23e83f2198c1be..a29ddca86845cb461a3f4262e8bf7dd1a0cb3c5d 100644 --- a/configs/mbed/src/Makefile +++ b/configs/mbed/src/Makefile @@ -2,7 +2,7 @@ # configs/mbed/src/Makefile # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mbed/src/mbed_internal.h b/configs/mbed/src/mbed_internal.h index 95b3da41ee0002904e12b0485ae2ae96582c495c..6b966b47a13bec39f20809e67160867f09f7d260 100644 --- a/configs/mbed/src/mbed_internal.h +++ b/configs/mbed/src/mbed_internal.h @@ -1,94 +1,94 @@ -/************************************************************************************ - * configs/mbed/src/mbed_internal.h - * arch/arm/src/board/mbed_internal.n - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef _CONFIGS_MBED_SRC_MBED_INTERNAL_H -#define _CONFIGS_MBED_SRC_MBED_INTERNAL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* MBED GPIO Pin Definitions ********************************************************/ - -#define MBED_LED1 (GPIO_OUTPUT | GPIO_PORT1 | GPIO_PIN18) -#define MBED_LED1_OFF MBED_LED1 -#define MBED_LED1_ON (MBED_LED1 | GPIO_VALUE_ONE) -#define MBED_LED2 (GPIO_OUTPUT | GPIO_PORT1 | GPIO_PIN20) -#define MBED_LED2_OFF MBED_LED2 -#define MBED_LED2_ON (MBED_LED2 | GPIO_VALUE_ONE) -#define MBED_LED3 (GPIO_OUTPUT | GPIO_PORT1 | GPIO_PIN21) -#define MBED_LED3_OFF MBED_LED3 -#define MBED_LED3_ON (MBED_LED3 | GPIO_VALUE_ONE) -#define MBED_LED4 (GPIO_OUTPUT | GPIO_PORT1 | GPIO_PIN23) -#define MBED_LED4_OFF MBED_LED4 -#define MBED_LED4_ON (MBED_LED 4| GPIO_VALUE_ONE) - -#define MBED_HEARTBEAT MBED_LED4 - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: lpc17_sspinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the NUCLEUS-2G board. - * - ************************************************************************************/ - -extern void weak_function lpc17_sspinitialize(void); - -#endif /* __ASSEMBLY__ */ -#endif /* _CONFIGS_MBED_SRC_MBED_INTERNAL_H */ - +/************************************************************************************ + * configs/mbed/src/mbed_internal.h + * arch/arm/src/board/mbed_internal.n + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef _CONFIGS_MBED_SRC_MBED_INTERNAL_H +#define _CONFIGS_MBED_SRC_MBED_INTERNAL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* MBED GPIO Pin Definitions ********************************************************/ + +#define MBED_LED1 (GPIO_OUTPUT | GPIO_PORT1 | GPIO_PIN18) +#define MBED_LED1_OFF MBED_LED1 +#define MBED_LED1_ON (MBED_LED1 | GPIO_VALUE_ONE) +#define MBED_LED2 (GPIO_OUTPUT | GPIO_PORT1 | GPIO_PIN20) +#define MBED_LED2_OFF MBED_LED2 +#define MBED_LED2_ON (MBED_LED2 | GPIO_VALUE_ONE) +#define MBED_LED3 (GPIO_OUTPUT | GPIO_PORT1 | GPIO_PIN21) +#define MBED_LED3_OFF MBED_LED3 +#define MBED_LED3_ON (MBED_LED3 | GPIO_VALUE_ONE) +#define MBED_LED4 (GPIO_OUTPUT | GPIO_PORT1 | GPIO_PIN23) +#define MBED_LED4_OFF MBED_LED4 +#define MBED_LED4_ON (MBED_LED 4| GPIO_VALUE_ONE) + +#define MBED_HEARTBEAT MBED_LED4 + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc17_sspinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the NUCLEUS-2G board. + * + ************************************************************************************/ + +extern void weak_function lpc17_sspinitialize(void); + +#endif /* __ASSEMBLY__ */ +#endif /* _CONFIGS_MBED_SRC_MBED_INTERNAL_H */ + diff --git a/configs/mbed/src/up_boot.c b/configs/mbed/src/up_boot.c index 93d69bf50542a46da78e3213863e3cba80b08a86..42dd54bf56b11e55fc490089cf744d7106a65708 100644 --- a/configs/mbed/src/up_boot.c +++ b/configs/mbed/src/up_boot.c @@ -1,82 +1,82 @@ -/************************************************************************************ - * configs/mbed/src/up_boot.c - * arch/arm/src/board/up_boot.c - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include - -#include - -#include "up_arch.h" -#include "up_internal.h" - -#include "lpc17_internal.h" -#include "mbed_internal.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: lpc17_boardinitialize - * - * Description: - * All LPC17xx architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void lpc17_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - up_ledinit(); -#endif -} +/************************************************************************************ + * configs/mbed/src/up_boot.c + * arch/arm/src/board/up_boot.c + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "lpc17_internal.h" +#include "mbed_internal.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc17_boardinitialize + * + * Description: + * All LPC17xx architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void lpc17_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + up_ledinit(); +#endif +} diff --git a/configs/mbed/src/up_leds.c b/configs/mbed/src/up_leds.c index 572e63a363cebf5c8c1b636f86072aa40af3ba73..bc8a8704522d04c7e7a8195758088bb76839b56f 100644 --- a/configs/mbed/src/up_leds.c +++ b/configs/mbed/src/up_leds.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_leds.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/mbed/src/up_nsh.c b/configs/mbed/src/up_nsh.c index 562b67cd94cf4042f19c2e59476b58a9bdaefe86..3a23ca7a51ec99865fdbb342a872469499ede29f 100644 --- a/configs/mbed/src/up_nsh.c +++ b/configs/mbed/src/up_nsh.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_nsh.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/mcu123-lpc214x/composite/appconfig b/configs/mcu123-lpc214x/composite/appconfig index 47d5346369b1125b571bd5820c2a4528b69fc08c..4c29b6523414bf3589fec702b0423552881bfa69 100644 --- a/configs/mcu123-lpc214x/composite/appconfig +++ b/configs/mcu123-lpc214x/composite/appconfig @@ -2,7 +2,7 @@ # configs/mcu123-lpc214x/composite/appconfig # # Copyright (C) 2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mcu123-lpc214x/include/board.h b/configs/mcu123-lpc214x/include/board.h index 04dab43f98eae43b79609667b73fa57e49fc7f4c..aa2b689572602b972ecf4f008fa5f9f80ebe3ea0 100644 --- a/configs/mcu123-lpc214x/include/board.h +++ b/configs/mcu123-lpc214x/include/board.h @@ -2,7 +2,7 @@ * configs/mcu123-lpc214x/include/board.h * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/mcu123-lpc214x/nsh/Make.defs b/configs/mcu123-lpc214x/nsh/Make.defs index b883cf06f870379cd5fb8643b250d1a97ed6b9b9..85b8bf89073c697d6a42f72a7d8c94e942b79932 100644 --- a/configs/mcu123-lpc214x/nsh/Make.defs +++ b/configs/mcu123-lpc214x/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/mcu123-lpc214x/nsh/Make.defs # # Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mcu123-lpc214x/nsh/setenv.sh b/configs/mcu123-lpc214x/nsh/setenv.sh index 7a79f8fcbda1be3c3deeff677728c163dd356126..97295dbd7cb27d9e7e8e9d40616ce65ce4fd7919 100755 --- a/configs/mcu123-lpc214x/nsh/setenv.sh +++ b/configs/mcu123-lpc214x/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/mcu123-lpc2148/nsh/setenv.sh # # Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mcu123-lpc214x/ostest/Make.defs b/configs/mcu123-lpc214x/ostest/Make.defs index c3da596abbbbb3596860b7daa5e3b22f821421ea..04d444c5dfae87d1fbd2b8dfe3504b9b27e8048a 100644 --- a/configs/mcu123-lpc214x/ostest/Make.defs +++ b/configs/mcu123-lpc214x/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/mcu123-lpc214x/ostest/Make.defs # # Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mcu123-lpc214x/ostest/appconfig b/configs/mcu123-lpc214x/ostest/appconfig index 7086a745ea6b49b05c473440a205d46340233acb..33846aafb0abe54b8417e43c9cd09335609a4640 100644 --- a/configs/mcu123-lpc214x/ostest/appconfig +++ b/configs/mcu123-lpc214x/ostest/appconfig @@ -2,7 +2,7 @@ # configs/mcu123-lpc214x/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mcu123-lpc214x/ostest/setenv.sh b/configs/mcu123-lpc214x/ostest/setenv.sh index c4b3b42bd23861e73f1b68dd6cd27540face1178..67d8b5d65a11a62f112d7b3288a504e673a7f98b 100755 --- a/configs/mcu123-lpc214x/ostest/setenv.sh +++ b/configs/mcu123-lpc214x/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/mcu123-lpc2148/ostest/setenv.sh # # Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mcu123-lpc214x/scripts/lpc21isp.sh b/configs/mcu123-lpc214x/scripts/lpc21isp.sh index ccb2025dd94690798868208e5a4d13003cb4eeb5..6dae9b704e7f013ad02365d6673e6eef595e9f99 100755 --- a/configs/mcu123-lpc214x/scripts/lpc21isp.sh +++ b/configs/mcu123-lpc214x/scripts/lpc21isp.sh @@ -3,7 +3,7 @@ # configs/mcu123-lpc214x/lpc21isp.sh # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mcu123-lpc214x/src/up_leds.c b/configs/mcu123-lpc214x/src/up_leds.c index 1cc7167532ce36a2b4f460abb8e6670e5bfc6e44..9d399c8cc924822164819b63fc96ddb5213d477a 100644 --- a/configs/mcu123-lpc214x/src/up_leds.c +++ b/configs/mcu123-lpc214x/src/up_leds.c @@ -2,7 +2,7 @@ * configs/mcu123-lpc214x/src/up_leds.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/mcu123-lpc214x/src/up_nsh.c b/configs/mcu123-lpc214x/src/up_nsh.c index caef0c3b5e175a577ae13062b66f8d3e577b42d6..14b5d7d97ec330714ee7d2c99f52b187843c35b2 100644 --- a/configs/mcu123-lpc214x/src/up_nsh.c +++ b/configs/mcu123-lpc214x/src/up_nsh.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_nsh.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/mcu123-lpc214x/src/up_usbmsc.c b/configs/mcu123-lpc214x/src/up_usbmsc.c index f25486d89087531bd3b6ef12d02ef2addc41c3e4..79d9344a4aaae74b3d1094a50396089f17e7a5fe 100644 --- a/configs/mcu123-lpc214x/src/up_usbmsc.c +++ b/configs/mcu123-lpc214x/src/up_usbmsc.c @@ -2,7 +2,7 @@ * configs/mcu123-lpc214x/src/up_usbmsc.c * * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Configure and register the LPC214x MMC/SD SPI block driver. * diff --git a/configs/mcu123-lpc214x/usbserial/Make.defs b/configs/mcu123-lpc214x/usbserial/Make.defs index 20fb8b55d1d7401fb8812078fca9fff5da8996f5..a5163d88217c960dbc24fbb6adeac0b8b226cdac 100644 --- a/configs/mcu123-lpc214x/usbserial/Make.defs +++ b/configs/mcu123-lpc214x/usbserial/Make.defs @@ -2,7 +2,7 @@ # configs/mcu123-lpc214x/usbserial/Make.defs # # Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mcu123-lpc214x/usbserial/appconfig b/configs/mcu123-lpc214x/usbserial/appconfig index d4cf7893da65a3711f8ec7cdd372c1763ddc7aec..31ecbf24e0c9f84a5b10cea78f5c9b9f14241712 100644 --- a/configs/mcu123-lpc214x/usbserial/appconfig +++ b/configs/mcu123-lpc214x/usbserial/appconfig @@ -2,7 +2,7 @@ # configs/mcu123-lpc214x/usbserial/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mcu123-lpc214x/usbserial/setenv.sh b/configs/mcu123-lpc214x/usbserial/setenv.sh index f68750d884b812935b4c7c8eb62e6ae286c726bd..8661ee0cb76dba3f0c681809f61c92299d81706d 100755 --- a/configs/mcu123-lpc214x/usbserial/setenv.sh +++ b/configs/mcu123-lpc214x/usbserial/setenv.sh @@ -2,7 +2,7 @@ # configs/mcu123-lpc2148/usbserial/setenv.sh # # Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mcu123-lpc214x/usbstorage/appconfig b/configs/mcu123-lpc214x/usbstorage/appconfig index ffc6bb82065cb1ae5d7cdf52f067e417cffea469..1ed11ca5e38f14037745bfa72ba0c3b44bd01bf8 100644 --- a/configs/mcu123-lpc214x/usbstorage/appconfig +++ b/configs/mcu123-lpc214x/usbstorage/appconfig @@ -2,7 +2,7 @@ # configs/mcu123-lpc214x/usbstorage/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mcu123-lpc214x/usbstorage/setenv.sh b/configs/mcu123-lpc214x/usbstorage/setenv.sh index 4be2cb49ab77cab1dcdf1a8c7c7498856c70ddca..f27530656f57435f34351b7c01b1663fbc550d7a 100755 --- a/configs/mcu123-lpc214x/usbstorage/setenv.sh +++ b/configs/mcu123-lpc214x/usbstorage/setenv.sh @@ -2,7 +2,7 @@ # configs/mcu123-lpc2148/usbstorage/setenv.sh # # Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/micropendous3/hello/appconfig b/configs/micropendous3/hello/appconfig index 17771a42715f5111bd552a481183ab3c143f2c29..334bdaa1afd48553c7b1c0e2e9882d4f1742e346 100644 --- a/configs/micropendous3/hello/appconfig +++ b/configs/micropendous3/hello/appconfig @@ -2,7 +2,7 @@ # configs/micropendous3/hello/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/micropendous3/hello/ld.script b/configs/micropendous3/hello/ld.script index 5492abda9046b76ec171a53a1cafb362012f81e8..1a0c4b3f467e36ebee36de9c071fe9f1b0669213 100644 --- a/configs/micropendous3/hello/ld.script +++ b/configs/micropendous3/hello/ld.script @@ -2,7 +2,7 @@ * configs/micropendous3/hello/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/micropendous3/hello/setenv.sh b/configs/micropendous3/hello/setenv.sh index 4736838b9a51cab0cd1456a449159636c3105bd9..8e8830dc785182a8dd5b1fdc43c74481531f85d3 100755 --- a/configs/micropendous3/hello/setenv.sh +++ b/configs/micropendous3/hello/setenv.sh @@ -2,7 +2,7 @@ # configs/micropendous3/hello/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/micropendous3/include/board.h b/configs/micropendous3/include/board.h index 8fd35e890870ca07a45d2a7529b827c9d11a5546..a63de7cc11a04de4ae29221df6a2e80c6c5a62e3 100755 --- a/configs/micropendous3/include/board.h +++ b/configs/micropendous3/include/board.h @@ -3,7 +3,7 @@ * include/arch/board/board.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/micropendous3/src/Makefile b/configs/micropendous3/src/Makefile index b027183c483cc6d79b1bbcd710b521e29b9e19aa..ff1c872f090f339ac14a900bffbd6129f564dadd 100644 --- a/configs/micropendous3/src/Makefile +++ b/configs/micropendous3/src/Makefile @@ -2,7 +2,7 @@ # configs/micropendous3/src/Makefile # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/micropendous3/src/micropendous3_internal.h b/configs/micropendous3/src/micropendous3_internal.h index 8425bfb8f6a0f792a342b54e7768cdab0d3e5a9e..df22a265fd73a025fd9f7bb526a5cd36ff8b3fa6 100644 --- a/configs/micropendous3/src/micropendous3_internal.h +++ b/configs/micropendous3/src/micropendous3_internal.h @@ -1,101 +1,101 @@ -/**************************************************************************** - * configs/micropendous3/src/pcblogic-internal.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __CONFIGS_MICROPENDOUS3_SRC_MICROPENDOUS3_INTERNAL_H -#define __CONFIGS_MICROPENDOUS3_SRC_MICROPENDOUS3_INTERNAL_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-Processor Definitions - ****************************************************************************/ -/* Configuration ************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Name: at90usb_spiinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Micropendous3 board. - * - ************************************************************************************/ - -#if defined(CONFIG_AVR_SPI1) || defined(CONFIG_AVR_SPI2) -EXTERN void weak_function at90usb_spiinitialize(void); -#endif - -/************************************************************************************ - * Name: at90usb_ledinit - * - * Description: - * Configure on-board LEDs if LED support has been selected. - * - ************************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -EXTERN void at90usb_ledinit(void); -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __CONFIGS_MICROPENDOUS3_SRC_MICROPENDOUS3_INTERNAL_H */ +/**************************************************************************** + * configs/micropendous3/src/micropendous3-internal.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_MICROPENDOUS3_SRC_MICROPENDOUS3_INTERNAL_H +#define __CONFIGS_MICROPENDOUS3_SRC_MICROPENDOUS3_INTERNAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Name: at90usb_spiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Micropendous3 board. + * + ************************************************************************************/ + +#if defined(CONFIG_AVR_SPI1) || defined(CONFIG_AVR_SPI2) +EXTERN void weak_function at90usb_spiinitialize(void); +#endif + +/************************************************************************************ + * Name: at90usb_ledinit + * + * Description: + * Configure on-board LEDs if LED support has been selected. + * + ************************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +EXTERN void at90usb_ledinit(void); +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_MICROPENDOUS3_SRC_MICROPENDOUS3_INTERNAL_H */ diff --git a/configs/micropendous3/src/up_boot.c b/configs/micropendous3/src/up_boot.c index 6c9a879a8f785dd80459a147cc4218d52dd544e0..912440c192c8b9c5d28584d3d230a38ad4fcef6f 100644 --- a/configs/micropendous3/src/up_boot.c +++ b/configs/micropendous3/src/up_boot.c @@ -3,7 +3,7 @@ * arch/mips/src/board/up_boot.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/mx1ads/include/board.h b/configs/mx1ads/include/board.h index 7fa096b2547e83aed4e81d02c8db5ec2cb8d4cb3..1180e67ccf4d353acb236aaf2d7e3bf65e0bfb74 100644 --- a/configs/mx1ads/include/board.h +++ b/configs/mx1ads/include/board.h @@ -3,7 +3,7 @@ * include/arch/board/board.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/mx1ads/ostest/Make.defs b/configs/mx1ads/ostest/Make.defs index 4eba91c3f58aa6a01fcd6df32ee375095ec50392..ffcb4662c770104c0a51c9333a300d403c003f9e 100644 --- a/configs/mx1ads/ostest/Make.defs +++ b/configs/mx1ads/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/mx1ads/ostest/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mx1ads/ostest/appconfig b/configs/mx1ads/ostest/appconfig index 0f761bdb7d0c3b16191dcefa6312a4ad0d4d527b..2f61aa07c2cf8d4d55596a8eea6f89e8049dbebb 100644 --- a/configs/mx1ads/ostest/appconfig +++ b/configs/mx1ads/ostest/appconfig @@ -2,7 +2,7 @@ # configs/mx1ads/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mx1ads/ostest/defconfig b/configs/mx1ads/ostest/defconfig index e58fb27018546df9cbdce8cabafbcb174ddeda61..f20216aa81a302ea31aab007c1adc2d5c5374472 100644 --- a/configs/mx1ads/ostest/defconfig +++ b/configs/mx1ads/ostest/defconfig @@ -2,7 +2,7 @@ # configs/mx1ads/ostest/defconfig # # Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mx1ads/ostest/ld.script b/configs/mx1ads/ostest/ld.script index 445c2c574b228ccd708764f3bf25e71db0797b12..e16f9de24916d29b5ffd8728cf50813b1e5681d8 100644 --- a/configs/mx1ads/ostest/ld.script +++ b/configs/mx1ads/ostest/ld.script @@ -2,7 +2,7 @@ * configs/mx1ads/ostest/ld.script * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/mx1ads/ostest/setenv.sh b/configs/mx1ads/ostest/setenv.sh index 9089b26b09b0afec36ce7cd0394e70210b1ca94f..e73858fc76e686d1683b3a2e8d1c1cb4a5e3b53e 100755 --- a/configs/mx1ads/ostest/setenv.sh +++ b/configs/mx1ads/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/mx1ads/ostest/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mx1ads/src/Makefile b/configs/mx1ads/src/Makefile index 56d3af3f3d9419f02aebc149c25bf862fba5caf4..4a2c02ef1a8080bf306e155a3a0d94b8c7ea1998 100644 --- a/configs/mx1ads/src/Makefile +++ b/configs/mx1ads/src/Makefile @@ -2,7 +2,7 @@ # configs/mx1ads/src/Makefile # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/mx1ads/src/up_boot.c b/configs/mx1ads/src/up_boot.c index a65c9b4db45e09dc9174dfd598efb0a382a0a57c..67ac4ce1763ce01a12aa08818b3c3c375249c840 100644 --- a/configs/mx1ads/src/up_boot.c +++ b/configs/mx1ads/src/up_boot.c @@ -1,107 +1,107 @@ -/************************************************************************************ - * configs/mx1ads/src/up_boot.c - * arch/arm/src/board/up_boot.c - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include - -#include - -#include "chip.h" -#include "up_arch.h" -#include "imx_gpio.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: imx_boardinitialize - * - * Description: - * All i.MX architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - ************************************************************************************/ - -void imx_boardinitialize(void) -{ - uint32_t regval; - - putreg32(0x000003ab, IMX_SC_GPCR); /* I/O pad driving strength */ - putreg32(IMX_MPCTL0_VALUE, IMX_PLL_MPCTL0); - putreg32(IMX_SPCTL0_VALUE, IMX_PLL_SPCTL0); - - regval = (CSCR_CLKOSEL_FCLK | /* Output FCLK on CLK0 */ - (IMX_CSCR_USBDIV << PLL_CSCR_USBDIV_SHIFT) | /* USB divider */ - CSCR_SDCNT_4thEDGE | /* Shutdown on 4th edge */ - (IMX_CSCR_BCLKDIV << PLL_CSCR_BCLKDIV_SHIFT) | /* Bclock divider */ - PLL_CSCR_SPEN | PLL_CSCR_MPEN); /* Enable MUC and System PLL */ - putreg32(regval, IMX_PLL_CSCR); - - /* Use these new frequencies now */ - - putreg32(IMX_PLL_CSCR, regval | (PLL_CSCR_MPLLRESTART|PLL_CSCR_SPLLRESTART)); - - /* Setup peripheral clocking */ - - putreg32(IMX_PCDR_VALUE, IMX_PLL_PCDR); - - /* Configure CS4 for cs8900 Ethernet */ - -#ifdef CONFIG_NET - putreg32(0x00000f00, IMX_EIM_CS4H); - putreg32(0x00001501, IMX_EIM_CS4L); - - imxgpio_configprimary(GPIOA, 21); - imxgpio_configprimary(GPIOA, 22); - - regval = getreg32(IMX_CS4_VSECTION + 0x0c); - regval = getreg32(IMX_CS4_VSECTION + 0x0c); -#endif -} +/************************************************************************************ + * configs/mx1ads/src/up_boot.c + * arch/arm/src/board/up_boot.c + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +#include "chip.h" +#include "up_arch.h" +#include "imx_gpio.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: imx_boardinitialize + * + * Description: + * All i.MX architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + ************************************************************************************/ + +void imx_boardinitialize(void) +{ + uint32_t regval; + + putreg32(0x000003ab, IMX_SC_GPCR); /* I/O pad driving strength */ + putreg32(IMX_MPCTL0_VALUE, IMX_PLL_MPCTL0); + putreg32(IMX_SPCTL0_VALUE, IMX_PLL_SPCTL0); + + regval = (CSCR_CLKOSEL_FCLK | /* Output FCLK on CLK0 */ + (IMX_CSCR_USBDIV << PLL_CSCR_USBDIV_SHIFT) | /* USB divider */ + CSCR_SDCNT_4thEDGE | /* Shutdown on 4th edge */ + (IMX_CSCR_BCLKDIV << PLL_CSCR_BCLKDIV_SHIFT) | /* Bclock divider */ + PLL_CSCR_SPEN | PLL_CSCR_MPEN); /* Enable MUC and System PLL */ + putreg32(regval, IMX_PLL_CSCR); + + /* Use these new frequencies now */ + + putreg32(IMX_PLL_CSCR, regval | (PLL_CSCR_MPLLRESTART|PLL_CSCR_SPLLRESTART)); + + /* Setup peripheral clocking */ + + putreg32(IMX_PCDR_VALUE, IMX_PLL_PCDR); + + /* Configure CS4 for cs8900 Ethernet */ + +#ifdef CONFIG_NET + putreg32(0x00000f00, IMX_EIM_CS4H); + putreg32(0x00001501, IMX_EIM_CS4L); + + imxgpio_configprimary(GPIOA, 21); + imxgpio_configprimary(GPIOA, 22); + + regval = getreg32(IMX_CS4_VSECTION + 0x0c); + regval = getreg32(IMX_CS4_VSECTION + 0x0c); +#endif +} diff --git a/configs/mx1ads/src/up_leds.c b/configs/mx1ads/src/up_leds.c index ff9a9b63824258901bc6013fb0c5fbb3ec2d34d8..30ba2bdbea66c7a155582d6a121f619ba59bc73b 100644 --- a/configs/mx1ads/src/up_leds.c +++ b/configs/mx1ads/src/up_leds.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_leds.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/mx1ads/src/up_network.c b/configs/mx1ads/src/up_network.c index 5eb0460eaed11a9a38179d2e9da1b4aeaae0c8f6..20fc766e3b185afb7c089007e8da2ea5ba831add 100644 --- a/configs/mx1ads/src/up_network.c +++ b/configs/mx1ads/src/up_network.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_network.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ne64badge/include/board.h b/configs/ne64badge/include/board.h index aea9358b10e50d518f0b2e11c6ffcc79dce50bb8..ba4ce3631bbdac4203405a617f1aa05cf2baaf9d 100755 --- a/configs/ne64badge/include/board.h +++ b/configs/ne64badge/include/board.h @@ -3,7 +3,7 @@ * include/arch/board/board.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ne64badge/ostest/Make.defs b/configs/ne64badge/ostest/Make.defs index d72a137592b049b0914208a83e13cdf495868fd2..fcd01d1127445b64c669d20443f86b15d1a4e8d9 100755 --- a/configs/ne64badge/ostest/Make.defs +++ b/configs/ne64badge/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/ne64badge/ostest/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ne64badge/ostest/appconfig b/configs/ne64badge/ostest/appconfig index 185e346d881900c33692ea649e0d22372ea08fe1..013a78d05949f6ff76188e2c3a37dd6dd130aebd 100644 --- a/configs/ne64badge/ostest/appconfig +++ b/configs/ne64badge/ostest/appconfig @@ -2,7 +2,7 @@ # configs/ne64badge/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ne64badge/ostest/ld.script.banked b/configs/ne64badge/ostest/ld.script.banked index ef0673aac0f583b1649c962e6fe4346780eaf6af..5f466e64912d7a0722c982279ab37d33a0930738 100755 --- a/configs/ne64badge/ostest/ld.script.banked +++ b/configs/ne64badge/ostest/ld.script.banked @@ -2,7 +2,7 @@ * configs/ne64badge/ostest/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ne64badge/ostest/ld.script.nonbanked b/configs/ne64badge/ostest/ld.script.nonbanked index 1ec41e919f539d8f9f0e451710c836bc2468d590..dfa8b15b21d4ed0521f91ec8a00ad982520ffd86 100755 --- a/configs/ne64badge/ostest/ld.script.nonbanked +++ b/configs/ne64badge/ostest/ld.script.nonbanked @@ -2,7 +2,7 @@ * configs/ne64badge/ostest/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ne64badge/ostest/setenv.sh b/configs/ne64badge/ostest/setenv.sh index f34038eba6b15f494cc19bdabe08247efe5c4b03..c5aa591b494a78ed10b5d0f8581d36189e065a3d 100755 --- a/configs/ne64badge/ostest/setenv.sh +++ b/configs/ne64badge/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/ne64badge/ostest/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ne64badge/src/Makefile b/configs/ne64badge/src/Makefile index 6808224cde5656af43c66e1438291672aedca18a..657fedddc160ba3dd15b5380543cfc44db357c48 100644 --- a/configs/ne64badge/src/Makefile +++ b/configs/ne64badge/src/Makefile @@ -2,7 +2,7 @@ # configs/ne64badge/src/Makefile # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ne64badge/src/ne64badge_internal.h b/configs/ne64badge/src/ne64badge_internal.h index 7cba3a91c7e578292045aa29ae49e94800067a69..d10618c9a4323e8ac1c53de55b8440bc96427ca5 100644 --- a/configs/ne64badge/src/ne64badge_internal.h +++ b/configs/ne64badge/src/ne64badge_internal.h @@ -1,205 +1,205 @@ -/************************************************************************************ - * configs/ne64badge/src/ne64badge_internal.h - * arch/arm/src/board/ne64badge_internal.n - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __CONFIGS_NE64BADGE_SRC_NE64BADGE_INTERNAL_H -#define __CONFIGS_NE64BADGE_SRC_NE64BADGE_INTERNAL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#include "m9s12_internal.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* NE64BADGE Pin Usage **************************************************************/ -/* PIN PIN NAME BOARD SIGNAL NOTES - * --- ------------------- -------------- ---------------------- - * 44 RESET J3 RESET_L Also to SW3 - * 57 BKGD/MODC/TAGHI_B BDM BKGD CON6A - * - * 85 PAD0 VR1 Potentiometer - * 86 PAD1 J3 ANALOG_IN0 Not used on board - * 87 PAD2 J3 ANALOG_IN1 " " " " "" " " - * 88 PAD3 J3 ANALOG_IN2 " " " " "" " " - * 89 PAD4 J3 ANALOG_IN3 " " " " "" " " - * - * 70 PHY_TXP J7 TD+ RJ45 connector - * 71 PHY_TXN J7 TD- RJ45 connector - * 73 PHY_RXP J7 RD+ RJ45 connector - * 74 PHY_RXN J7 RD- RJ45 connector - * - * Ports A,B,E,K managed by the MEBI block - * --------------------------------------- - * 60 PA0/ADDR8/DATA8 J3 ADDR_DATA8 Not used on board - * 61 PA1/ADDR9/DATA9 J3 ADDR_DATA9 " " " " "" " " - * 62 PA2/ADDR10/DATA10 J3 ADDR_DATA10 " " " " "" " " - * 63 PA3/ADDR11/DATA11 J3 ADDR_DATA11 " " " " "" " " - * 77 PA4/ADDR12/DATA12 J3 ADDR_DATA12 " " " " "" " " - * 78 PA5/ADDR13/DATA13 J3 ADDR_DATA13 " " " " "" " " - * 79 PA6/ADDR14/DATA14 J3 ADDR_DATA14 " " " " "" " " - * 80 PA7/ADDR15/DATA15 J3 ADDR_DATA15 " " " " "" " " - * - * 10 PB0/ADDR0/DATA0 J3 ADDR_DATA0 Not used on board - * 11 PB1/ADDR1/DATA1 J3 ADDR_DATA1 " " " " "" " " - * 12 PB2/ADDR2/DATA2 J3 ADDR_DATA2 " " " " "" " " - * 13 PB3/ADDR3/DATA3 J3 ADDR_DATA3 " " " " "" " " - * 16 PB4/ADDR4/DATA4 J3 ADDR_DATA4 " " " " "" " " - * 17 PB5/ADDR5/DATA5 J3 ADDR_DATA5 " " " " "" " " - * 18 PB6/ADDR6/DATA6 J3 ADDR_DATA6 " " " " "" " " - * 19 PB7/ADDR7/DATA7 J3 ADDR_DATA7 " " " " "" " " - * - * 56 PE0/XIRQ_B BUTTON1 SW1 - * 55 PE1/IRQ_B J3 IRQ Not used on board - * 54 PE2/R_W J3 RW " " " " "" " " - * 53 PE3/LSTRB_B/TAGLO_B J3 LSTRB " " " " "" " " - * 41 PE4/ECLK J3 ECLK " " " " "" " " - * 40 PE5/IPIPE0/MODA J3 MODA " " " " "" " " - * 39 PE6/IPIPE1/MODB J3 MODB " " " " "" " " - * 38 PE7/NOACC/XCLKS_B pulled low pulled low - */ - -#define NE64BADGE_BUTTON1 (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT_E | GPIO_PIN_0) - -/* 97 PK0/XADR14 N/C N/C - * 98 PK1/XADR15 N/C N/C - * 99 PK2/XADR16 N/C N/C - * 100 PK3/XADR17 N/C N/C - * 103 PK4/XADR18 N/C N/C - * 104 PK5/XADR19 N/C N/C - * 105 PK6/XCS_B J3 XCS Not used on board - * 106 PK7/ECS_B/ROMCTL J3 ECS " " " " "" " " - * - * Ports T,S,G,H,J,L managed by the PIM Block - * ------------------------------------------ - * 110 PT4/IOC1_4 J3 GPIO8 Not used on board - * 109 PT5/IOC1_5 J3 GPIO9 " " " " "" " " - * 108 PT6/IOC1_6 J3 GPIO10 " " " " "" " " - * 107 PT7/IOC1_7 N/C N/C - * - * 30 PS0/RXD0 RS232_RX Eventually maps to J2 RXD - * 31 PS1/TXD0 RS232_TX Eventually maps to J2 TXD - * 32 PS2/RXD1 J3&J4 UART_RX Not used on board - * 33 PS3/TXD1 J3&J4 UART_TX " " " " "" " " - * 34 PS4/MISO J3 SPI_MISO " " " " "" " " - * 35 PS5/MOSI J3 SPI_MOSI " " " " "" " " - * 36 PS6/SCK J3 SPI_CLOCK " " " " "" " " - * 37 PS7/SS_B J3 SPI_SS " " " " "" " " - * - * 22 PG0/RXD0/KWG0 J3 GPIO0 Not used on board - * 23 PG1/RXD1/KWG1 J3 GPIO1 " " " " "" " " - * 24 PG2/RXD2/KWG2 J3 GPIO2 " " " " "" " " - * 25 PG3/RXD3/KWG3 J3 GPIO3 " " " " "" " " - * 26 PG4/RXCLK/KWG4 J3 GPIO4 " " " " "" " " - * 27 PG5/RXDV/KWG5 J3 GPIO5 " " " " "" " " - * 28 PG6/RXER/KWG6 J3 GPIO6 " " " " "" " " - * 29 PG7/KWG7 J3 GPIO7 " " " " "" " " - * - * 7 PH0/TXD0/KWH0 N/C N/C - * 6 PH1/TXD1/KWH1 N/C N/C - * 5 PH2/TXD2/KWH2 J4 XBEE_RESET Not used on board - * 4 PH3/TXD3/KWH3 J4 XBEE_RSSI Not used on board - * 3 PH4/TXCLK/KWH4 BUTTON2 SW2 - * 2 PH5/TXDV/KWH5 J5 XBEE_LOAD_H Not used on board - * 1 PH6/TXER/KWH6 J4 XBEE_LOAD_L Not used on board - */ - -#define NE64BADGE_BUTTON2 (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT_H | GPIO_PIN_4) - -/* 8 PJ0/MDC/KWJ0 LED1 D21, red - * 9 PJ1/MDIO/KWJ1 LED2 D22, red - * 20 PJ2/CRS/KWJ2 J3 SPI_CS Not used on board - * 21 PJ3/COL/KWJ3 N/C - * 112 PJ6/SDA/KWJ6 J3 I2C_DATA Not used on board - * 111 PJ7/SCL/KWJ7 J3 I2C_CLOCK " " " " "" " " - */ - -#define NE64BADGE_LED1 (GPIO_OUTPUT | GPIO_OUTPUT_HIGH | GPIO_PORT_J | GPIO_PIN_0) -#define NE64BADGE_LED2 (GPIO_OUTPUT | GPIO_OUTPUT_HIGH | GPIO_PORT_J | GPIO_PIN_1) - -/* 51 PL6/TXER/KWL6 N/C N/C - * 52 PL5/TXDV/KWL5 N/C N/C - * 58 PL4/COLLED Collision LED red - * 59 PL3/DUPLED Full Duplex LED yellow - * 81 PL2/SPDLED 100Mbps Speed LED yellow - * 83 PL1/LNKLED Link Good LED green - * 84 PL0/ACTLED Activity LED yellow - */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ -/************************************************************************************ - * Name: up_ledinit - * - * Description: - * Configure and initialize on-board LEDs - * - ************************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -extern void up_ledinit(void); -#endif - -/************************************************************************************ - * Name: hcs12_spiinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the STM3210E-EVAL board. - * - ************************************************************************************/ - -extern void weak_function hcs12_spiinitialize(void); - - -#endif /* __ASSEMBLY__ */ -#endif /* __CONFIGS_NE64BADGE_SRC_NE64BADGE_INTERNAL_H */ - +/************************************************************************************ + * configs/ne64badge/src/ne64badge_internal.h + * arch/arm/src/board/ne64badge_internal.n + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_NE64BADGE_SRC_NE64BADGE_INTERNAL_H +#define __CONFIGS_NE64BADGE_SRC_NE64BADGE_INTERNAL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "m9s12_internal.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* NE64BADGE Pin Usage **************************************************************/ +/* PIN PIN NAME BOARD SIGNAL NOTES + * --- ------------------- -------------- ---------------------- + * 44 RESET J3 RESET_L Also to SW3 + * 57 BKGD/MODC/TAGHI_B BDM BKGD CON6A + * + * 85 PAD0 VR1 Potentiometer + * 86 PAD1 J3 ANALOG_IN0 Not used on board + * 87 PAD2 J3 ANALOG_IN1 " " " " "" " " + * 88 PAD3 J3 ANALOG_IN2 " " " " "" " " + * 89 PAD4 J3 ANALOG_IN3 " " " " "" " " + * + * 70 PHY_TXP J7 TD+ RJ45 connector + * 71 PHY_TXN J7 TD- RJ45 connector + * 73 PHY_RXP J7 RD+ RJ45 connector + * 74 PHY_RXN J7 RD- RJ45 connector + * + * Ports A,B,E,K managed by the MEBI block + * --------------------------------------- + * 60 PA0/ADDR8/DATA8 J3 ADDR_DATA8 Not used on board + * 61 PA1/ADDR9/DATA9 J3 ADDR_DATA9 " " " " "" " " + * 62 PA2/ADDR10/DATA10 J3 ADDR_DATA10 " " " " "" " " + * 63 PA3/ADDR11/DATA11 J3 ADDR_DATA11 " " " " "" " " + * 77 PA4/ADDR12/DATA12 J3 ADDR_DATA12 " " " " "" " " + * 78 PA5/ADDR13/DATA13 J3 ADDR_DATA13 " " " " "" " " + * 79 PA6/ADDR14/DATA14 J3 ADDR_DATA14 " " " " "" " " + * 80 PA7/ADDR15/DATA15 J3 ADDR_DATA15 " " " " "" " " + * + * 10 PB0/ADDR0/DATA0 J3 ADDR_DATA0 Not used on board + * 11 PB1/ADDR1/DATA1 J3 ADDR_DATA1 " " " " "" " " + * 12 PB2/ADDR2/DATA2 J3 ADDR_DATA2 " " " " "" " " + * 13 PB3/ADDR3/DATA3 J3 ADDR_DATA3 " " " " "" " " + * 16 PB4/ADDR4/DATA4 J3 ADDR_DATA4 " " " " "" " " + * 17 PB5/ADDR5/DATA5 J3 ADDR_DATA5 " " " " "" " " + * 18 PB6/ADDR6/DATA6 J3 ADDR_DATA6 " " " " "" " " + * 19 PB7/ADDR7/DATA7 J3 ADDR_DATA7 " " " " "" " " + * + * 56 PE0/XIRQ_B BUTTON1 SW1 + * 55 PE1/IRQ_B J3 IRQ Not used on board + * 54 PE2/R_W J3 RW " " " " "" " " + * 53 PE3/LSTRB_B/TAGLO_B J3 LSTRB " " " " "" " " + * 41 PE4/ECLK J3 ECLK " " " " "" " " + * 40 PE5/IPIPE0/MODA J3 MODA " " " " "" " " + * 39 PE6/IPIPE1/MODB J3 MODB " " " " "" " " + * 38 PE7/NOACC/XCLKS_B pulled low pulled low + */ + +#define NE64BADGE_BUTTON1 (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT_E | GPIO_PIN_0) + +/* 97 PK0/XADR14 N/C N/C + * 98 PK1/XADR15 N/C N/C + * 99 PK2/XADR16 N/C N/C + * 100 PK3/XADR17 N/C N/C + * 103 PK4/XADR18 N/C N/C + * 104 PK5/XADR19 N/C N/C + * 105 PK6/XCS_B J3 XCS Not used on board + * 106 PK7/ECS_B/ROMCTL J3 ECS " " " " "" " " + * + * Ports T,S,G,H,J,L managed by the PIM Block + * ------------------------------------------ + * 110 PT4/IOC1_4 J3 GPIO8 Not used on board + * 109 PT5/IOC1_5 J3 GPIO9 " " " " "" " " + * 108 PT6/IOC1_6 J3 GPIO10 " " " " "" " " + * 107 PT7/IOC1_7 N/C N/C + * + * 30 PS0/RXD0 RS232_RX Eventually maps to J2 RXD + * 31 PS1/TXD0 RS232_TX Eventually maps to J2 TXD + * 32 PS2/RXD1 J3&J4 UART_RX Not used on board + * 33 PS3/TXD1 J3&J4 UART_TX " " " " "" " " + * 34 PS4/MISO J3 SPI_MISO " " " " "" " " + * 35 PS5/MOSI J3 SPI_MOSI " " " " "" " " + * 36 PS6/SCK J3 SPI_CLOCK " " " " "" " " + * 37 PS7/SS_B J3 SPI_SS " " " " "" " " + * + * 22 PG0/RXD0/KWG0 J3 GPIO0 Not used on board + * 23 PG1/RXD1/KWG1 J3 GPIO1 " " " " "" " " + * 24 PG2/RXD2/KWG2 J3 GPIO2 " " " " "" " " + * 25 PG3/RXD3/KWG3 J3 GPIO3 " " " " "" " " + * 26 PG4/RXCLK/KWG4 J3 GPIO4 " " " " "" " " + * 27 PG5/RXDV/KWG5 J3 GPIO5 " " " " "" " " + * 28 PG6/RXER/KWG6 J3 GPIO6 " " " " "" " " + * 29 PG7/KWG7 J3 GPIO7 " " " " "" " " + * + * 7 PH0/TXD0/KWH0 N/C N/C + * 6 PH1/TXD1/KWH1 N/C N/C + * 5 PH2/TXD2/KWH2 J4 XBEE_RESET Not used on board + * 4 PH3/TXD3/KWH3 J4 XBEE_RSSI Not used on board + * 3 PH4/TXCLK/KWH4 BUTTON2 SW2 + * 2 PH5/TXDV/KWH5 J5 XBEE_LOAD_H Not used on board + * 1 PH6/TXER/KWH6 J4 XBEE_LOAD_L Not used on board + */ + +#define NE64BADGE_BUTTON2 (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT_H | GPIO_PIN_4) + +/* 8 PJ0/MDC/KWJ0 LED1 D21, red + * 9 PJ1/MDIO/KWJ1 LED2 D22, red + * 20 PJ2/CRS/KWJ2 J3 SPI_CS Not used on board + * 21 PJ3/COL/KWJ3 N/C + * 112 PJ6/SDA/KWJ6 J3 I2C_DATA Not used on board + * 111 PJ7/SCL/KWJ7 J3 I2C_CLOCK " " " " "" " " + */ + +#define NE64BADGE_LED1 (GPIO_OUTPUT | GPIO_OUTPUT_HIGH | GPIO_PORT_J | GPIO_PIN_0) +#define NE64BADGE_LED2 (GPIO_OUTPUT | GPIO_OUTPUT_HIGH | GPIO_PORT_J | GPIO_PIN_1) + +/* 51 PL6/TXER/KWL6 N/C N/C + * 52 PL5/TXDV/KWL5 N/C N/C + * 58 PL4/COLLED Collision LED red + * 59 PL3/DUPLED Full Duplex LED yellow + * 81 PL2/SPDLED 100Mbps Speed LED yellow + * 83 PL1/LNKLED Link Good LED green + * 84 PL0/ACTLED Activity LED yellow + */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ +/************************************************************************************ + * Name: up_ledinit + * + * Description: + * Configure and initialize on-board LEDs + * + ************************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +extern void up_ledinit(void); +#endif + +/************************************************************************************ + * Name: hcs12_spiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the STM3210E-EVAL board. + * + ************************************************************************************/ + +extern void weak_function hcs12_spiinitialize(void); + + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_NE64BADGE_SRC_NE64BADGE_INTERNAL_H */ + diff --git a/configs/ne64badge/src/up_boot.c b/configs/ne64badge/src/up_boot.c index b277be76e9b8c15e19759ae46882ec1147735bcc..a1d0071d9cb3845d55c04d6dff9c25c878ffa7ff 100644 --- a/configs/ne64badge/src/up_boot.c +++ b/configs/ne64badge/src/up_boot.c @@ -1,89 +1,89 @@ -/************************************************************************************ - * configs/ne64badge/src/up_boot.c - * arch/arm/src/board/up_boot.c - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include - -#include - -#include "ne64badge_internal.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: hcs12_boardinitialize - * - * Description: - * All HCS12 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void hcs12_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function - * hcs12_spiinitialize() has been brought into the link. - */ - -#if defined(CONFIG_INCLUDE_HCS12_ARCH_SPI) - if (hcs12_spiinitialize) - { - hcs12_spiinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - up_ledinit(); -#endif -} +/************************************************************************************ + * configs/ne64badge/src/up_boot.c + * arch/arm/src/board/up_boot.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +#include "ne64badge_internal.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: hcs12_boardinitialize + * + * Description: + * All HCS12 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void hcs12_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function + * hcs12_spiinitialize() has been brought into the link. + */ + +#if defined(CONFIG_INCLUDE_HCS12_ARCH_SPI) + if (hcs12_spiinitialize) + { + hcs12_spiinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + up_ledinit(); +#endif +} diff --git a/configs/ne64badge/src/up_buttons.c b/configs/ne64badge/src/up_buttons.c index ec43c3bedb8ea6fc3c90681e72262cc2d195a6c1..70c57f2ccecf4d33f61e48225fb1a3e0388535af 100644 --- a/configs/ne64badge/src/up_buttons.c +++ b/configs/ne64badge/src/up_buttons.c @@ -2,7 +2,7 @@ * configs/ne64badge/src/up_buttons.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ne64badge/src/up_leds.c b/configs/ne64badge/src/up_leds.c index e6660b0c03c0dd0396db68c3b7b37e018639a9d1..73991f5708d2fb4b6978710ca674222692576186 100644 --- a/configs/ne64badge/src/up_leds.c +++ b/configs/ne64badge/src/up_leds.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_leds.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ne64badge/src/up_nsh.c b/configs/ne64badge/src/up_nsh.c index f3851fcf6d9a9b27efc891e9dbcc7657192f0d01..17a52819bced8d6798b22cba63c82e09cadd3622 100644 --- a/configs/ne64badge/src/up_nsh.c +++ b/configs/ne64badge/src/up_nsh.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_nsh.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ne64badge/src/up_spi.c b/configs/ne64badge/src/up_spi.c index 08681fa2d271e45dbcd780a694eeedc22b65e5c2..8d52b7570836362438732bb3d0387e9bc3dba1a4 100644 --- a/configs/ne64badge/src/up_spi.c +++ b/configs/ne64badge/src/up_spi.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_spi.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/include/board.h b/configs/ntosd-dm320/include/board.h index 10fcec68b9e42e4df812899d04c312db9b6991b9..cf302a1ffc7e31715a04cb0982b98df5640506c5 100644 --- a/configs/ntosd-dm320/include/board.h +++ b/configs/ntosd-dm320/include/board.h @@ -2,7 +2,7 @@ * arch/board/board.h * * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/nettest/Make.defs b/configs/ntosd-dm320/nettest/Make.defs index bc44d0487502f5238ec5f24ee3b5daa27d3b2d6e..c3b25f9cb558d54bcb7d9d6405e53380bcce5fc5 100644 --- a/configs/ntosd-dm320/nettest/Make.defs +++ b/configs/ntosd-dm320/nettest/Make.defs @@ -2,7 +2,7 @@ # configs/ntosd-dm320/nettest/Make.defs # # Copyright (C) 2007-2008, 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/nettest/appconfig b/configs/ntosd-dm320/nettest/appconfig index 6e57e8bd0be2a2474d6ddc42b90f64a78d026dbb..de2ad4fb45adfedf171ff2be1194b4b005e9faf1 100644 --- a/configs/ntosd-dm320/nettest/appconfig +++ b/configs/ntosd-dm320/nettest/appconfig @@ -2,7 +2,7 @@ # configs/ntosd-dm320/nettest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/nettest/defconfig b/configs/ntosd-dm320/nettest/defconfig index 3a5b0190092e8f73a7ba5e9336975c106bc73169..848cf2f9da80e6415c6ebad7496ed9b492d23e8f 100644 --- a/configs/ntosd-dm320/nettest/defconfig +++ b/configs/ntosd-dm320/nettest/defconfig @@ -2,7 +2,7 @@ # configs/ntosd-dm320/nettest/defconfig # # Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/nettest/ld.script b/configs/ntosd-dm320/nettest/ld.script index 55e763fad63f2374e746fa36ea2e9076edef4e8a..1b0b18500963dd39ea57061a94ba4fdb7a55e0e0 100644 --- a/configs/ntosd-dm320/nettest/ld.script +++ b/configs/ntosd-dm320/nettest/ld.script @@ -2,7 +2,7 @@ * configs/ntosd-dm320/nettest/ld.script * * Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/nettest/setenv.sh b/configs/ntosd-dm320/nettest/setenv.sh index e007fae48650ccc1eea2bd5fba30de511329c16f..8a7788cfd9a850da3bd4b9e7da5e0023135427ee 100755 --- a/configs/ntosd-dm320/nettest/setenv.sh +++ b/configs/ntosd-dm320/nettest/setenv.sh @@ -2,7 +2,7 @@ # configs/ntosd-dm320/nettest/setenv.sh # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/nsh/Make.defs b/configs/ntosd-dm320/nsh/Make.defs index 00a4ae2b2ad111ccc4bc528793f77e4524034aa9..5c7d88265d20d719867ba91217664f7408b035c2 100644 --- a/configs/ntosd-dm320/nsh/Make.defs +++ b/configs/ntosd-dm320/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/ntosd-dm320/nsh/Make.defs # # Copyright (C) 2007-2008, 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/nsh/defconfig b/configs/ntosd-dm320/nsh/defconfig index 3cf421f16cb516da7f7faf312390940ca5b845e1..d824f55fc2f97c890252070698227788d4d2d219 100644 --- a/configs/ntosd-dm320/nsh/defconfig +++ b/configs/ntosd-dm320/nsh/defconfig @@ -2,7 +2,7 @@ # configs/ntosd-dm320/nsh/defconfig # # Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/nsh/ld.script b/configs/ntosd-dm320/nsh/ld.script index c1a27e453577330ee5974e665a97e3ac0694d268..6155a1429548555689a2de618a5e1b3bda501d18 100644 --- a/configs/ntosd-dm320/nsh/ld.script +++ b/configs/ntosd-dm320/nsh/ld.script @@ -2,7 +2,7 @@ * configs/ntosd-dm320/nsh/ld.script * * Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/nsh/setenv.sh b/configs/ntosd-dm320/nsh/setenv.sh index 0dda8cba6ff4d60d9180607fbc3bc5ad8d3bc7bd..bf3f497adb7fdd794c2be605b4291b2eb2ee05d0 100755 --- a/configs/ntosd-dm320/nsh/setenv.sh +++ b/configs/ntosd-dm320/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/ntosd-dm320/nsh/setenv.sh # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/ostest/Make.defs b/configs/ntosd-dm320/ostest/Make.defs index 7e12a8c70d2a3d6d9e7bbb512514cca3e01c1f5a..7b1976cddb60d2ae40a73188626a41765162af2c 100644 --- a/configs/ntosd-dm320/ostest/Make.defs +++ b/configs/ntosd-dm320/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/ntosd-dm320/ostest/Make.defs # # Copyright (C) 2007-2008, 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/ostest/appconfig b/configs/ntosd-dm320/ostest/appconfig index 1c5f6ab7b8b32bf71e9df286f28ac0340c0ffdd2..4e74fabc60b06b7fa19a2da6d25bafc5deb7875f 100644 --- a/configs/ntosd-dm320/ostest/appconfig +++ b/configs/ntosd-dm320/ostest/appconfig @@ -2,7 +2,7 @@ # configs/ntosd-dm320/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/ostest/defconfig b/configs/ntosd-dm320/ostest/defconfig index 08ea8be97be5829377007a31a9ab34bc8c327a5d..edc991880d816a3301657c050c3c9e60ccfd7d66 100644 --- a/configs/ntosd-dm320/ostest/defconfig +++ b/configs/ntosd-dm320/ostest/defconfig @@ -2,7 +2,7 @@ # configs/ntosd-dm320/ostest/defconfig # # Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/ostest/ld.script b/configs/ntosd-dm320/ostest/ld.script index e5bb77257152ca8537a95ee85b4d10445fb38077..f475f99f2f06383fe5b69e23e05ab98218b24d06 100644 --- a/configs/ntosd-dm320/ostest/ld.script +++ b/configs/ntosd-dm320/ostest/ld.script @@ -2,7 +2,7 @@ * configs/ntosd-dm320/ostest/ld.script * * Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/ostest/setenv.sh b/configs/ntosd-dm320/ostest/setenv.sh index 23948092b1f1447a16e5933ece6bd66e27fbcf0e..6ce1e04a85e15272b5fe7cc7dc222488c59067c1 100755 --- a/configs/ntosd-dm320/ostest/setenv.sh +++ b/configs/ntosd-dm320/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/ntosd-dm320/ostest/setenv.sh # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/poll/Make.defs b/configs/ntosd-dm320/poll/Make.defs index 7ec6c0aad0ec9e6dcac2540d22cb55bbf9a9434c..9e63120b12dcad9672f2ccd00589e50fe9e9fa32 100644 --- a/configs/ntosd-dm320/poll/Make.defs +++ b/configs/ntosd-dm320/poll/Make.defs @@ -2,7 +2,7 @@ # configs/ntosd-dm320/poll/Make.defs # # Copyright (C) 2007-2008, 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/poll/appconfig b/configs/ntosd-dm320/poll/appconfig index ff5abf976ae29ea645d841b8ca0d96763b115880..e16589d1d3d6b52efc94f1bafe791bb5636e27c8 100644 --- a/configs/ntosd-dm320/poll/appconfig +++ b/configs/ntosd-dm320/poll/appconfig @@ -2,7 +2,7 @@ # configs/ntosd-dm320/poll/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/poll/defconfig b/configs/ntosd-dm320/poll/defconfig index ec845c7ed6e0668c9849071fb9ce6db7465bcaeb..7386ff966df664ff9c993e64665c070324e0d592 100644 --- a/configs/ntosd-dm320/poll/defconfig +++ b/configs/ntosd-dm320/poll/defconfig @@ -2,7 +2,7 @@ # configs/ntosd-dm320/poll/defconfig # # Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/poll/ld.script b/configs/ntosd-dm320/poll/ld.script index 8db7a0fed14ca37ad38212914e6c70e8c2753ec1..f8bdf223b05db93362cb1a59c021094ffdbc5092 100644 --- a/configs/ntosd-dm320/poll/ld.script +++ b/configs/ntosd-dm320/poll/ld.script @@ -2,7 +2,7 @@ * configs/ntosd-dm320/poll/ld.script * * Copyright (C) 2008, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/poll/setenv.sh b/configs/ntosd-dm320/poll/setenv.sh index 9a94a9894fee503a094f76fc7a485653e4f716c2..a3479fb1809ac9c7d9585c8b950a9535768bd8e3 100755 --- a/configs/ntosd-dm320/poll/setenv.sh +++ b/configs/ntosd-dm320/poll/setenv.sh @@ -2,7 +2,7 @@ # configs/ntosd-dm320/poll/setenv.sh # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/src/Makefile b/configs/ntosd-dm320/src/Makefile index 1bd4b6291ba4304081c69d1c42ece92da6d3a3cd..1d0a1e614aad6e90a282547c6b7f5860d1ebf86d 100644 --- a/configs/ntosd-dm320/src/Makefile +++ b/configs/ntosd-dm320/src/Makefile @@ -2,7 +2,7 @@ # configs/ntosd-dm320/src/Makefile # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/src/up_leds.c b/configs/ntosd-dm320/src/up_leds.c index 15cf7b99f688e4db5ac99f64c556a26abbed2db6..9e2336e3681f4923f94767fc1c0201af4b5a25ee 100644 --- a/configs/ntosd-dm320/src/up_leds.c +++ b/configs/ntosd-dm320/src/up_leds.c @@ -2,7 +2,7 @@ * confgs/ntosd-dm320/src/up_leds.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/src/up_network.c b/configs/ntosd-dm320/src/up_network.c index df2f76ca745c7f4bc8be7b6ecc890f735a6f102d..c94c81433054acc4a354b4444603a91880eae51c 100644 --- a/configs/ntosd-dm320/src/up_network.c +++ b/configs/ntosd-dm320/src/up_network.c @@ -2,7 +2,7 @@ * board/up_network.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/thttpd/Make.defs b/configs/ntosd-dm320/thttpd/Make.defs index ec5581bbba80fee8eff1e137c44a860be5a8b5d0..aca2218710f209f1364d5bc8069b2f08edd3796a 100644 --- a/configs/ntosd-dm320/thttpd/Make.defs +++ b/configs/ntosd-dm320/thttpd/Make.defs @@ -2,7 +2,7 @@ # configs/ntosd-dm320/thttpd/Make.defs # # Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/thttpd/appconfig b/configs/ntosd-dm320/thttpd/appconfig index 42bcab4d43d008d979a670d8c956ca3009e460e0..bf47bf59f1f25ffeaa2a5c67b5a859e741db33a6 100644 --- a/configs/ntosd-dm320/thttpd/appconfig +++ b/configs/ntosd-dm320/thttpd/appconfig @@ -2,7 +2,7 @@ # configs/ntosd-dm320/thttpd/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/thttpd/defconfig b/configs/ntosd-dm320/thttpd/defconfig index 19680b2e9d75eee9ef61b4e05209b03b9c44839f..90f84c5e382c110fc3bd86979965cd37544bd317 100644 --- a/configs/ntosd-dm320/thttpd/defconfig +++ b/configs/ntosd-dm320/thttpd/defconfig @@ -2,7 +2,7 @@ # configs/ntosd-dm320/thttpd/defconfig # # Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/thttpd/ld.script b/configs/ntosd-dm320/thttpd/ld.script index 6646ec2f72c5b1630553eed94bdc4989e14f7e24..63199aa5a25a006bd6472dbac331df1cc2f6f894 100644 --- a/configs/ntosd-dm320/thttpd/ld.script +++ b/configs/ntosd-dm320/thttpd/ld.script @@ -2,7 +2,7 @@ * configs/ntosd-dm320/thttpd/ld.script * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/thttpd/setenv.sh b/configs/ntosd-dm320/thttpd/setenv.sh index 516766b4294a5d85b76bbd3d4b676cdc3e7a1ced..54700fb6b3526158aac762d77b08e955a4c023b1 100755 --- a/configs/ntosd-dm320/thttpd/setenv.sh +++ b/configs/ntosd-dm320/thttpd/setenv.sh @@ -2,7 +2,7 @@ # configs/ntosd-dm320/thttpd/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/udp/Make.defs b/configs/ntosd-dm320/udp/Make.defs index 54df969e0a1e7d48c4a80f219c68687efd77c917..003df0778dc85dd7952f6bc7b89de3e06d6d4ed2 100644 --- a/configs/ntosd-dm320/udp/Make.defs +++ b/configs/ntosd-dm320/udp/Make.defs @@ -2,7 +2,7 @@ # configs/ntosd-dm320/udp/Make.defs # # Copyright (C) 2007-2008, 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/udp/appconfig b/configs/ntosd-dm320/udp/appconfig index 30e21e185006a47304edf14e509c661e637cdb3e..1a1eb12fc529a5e9c8113198491ec46d646d6f79 100644 --- a/configs/ntosd-dm320/udp/appconfig +++ b/configs/ntosd-dm320/udp/appconfig @@ -2,7 +2,7 @@ # configs/ntosd-dm320/udp/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/udp/defconfig b/configs/ntosd-dm320/udp/defconfig index bc2bf86511ddd4413b98a46c2cbbfb84f794431f..4bc4b4bc8022a21f6f643eb66f93f8ee83afc103 100644 --- a/configs/ntosd-dm320/udp/defconfig +++ b/configs/ntosd-dm320/udp/defconfig @@ -2,7 +2,7 @@ # configs/ntosd-dm320/udp/defconfig # # Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/udp/ld.script b/configs/ntosd-dm320/udp/ld.script index d921a28add917fc402aed46e1fcd3206ce1015a3..89dd8f823f7708cc34a0716eb54a209d75f4ec78 100644 --- a/configs/ntosd-dm320/udp/ld.script +++ b/configs/ntosd-dm320/udp/ld.script @@ -2,7 +2,7 @@ * configs/ntosd-dm320/udp/ld.script * * Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/udp/setenv.sh b/configs/ntosd-dm320/udp/setenv.sh index 8e14be32f929746c3474313bb085a31dee648633..a2e1ffec73886e9d94fbe4ca2d8a6669f8f99305 100755 --- a/configs/ntosd-dm320/udp/setenv.sh +++ b/configs/ntosd-dm320/udp/setenv.sh @@ -2,7 +2,7 @@ # configs/ntosd-dm320/udp/setenv.sh # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/uip/Make.defs b/configs/ntosd-dm320/uip/Make.defs index 40394e77b4bb1edb39b6045ac373856158021483..e759a8dcc66aeb79c893891b7c529ee6518edb03 100644 --- a/configs/ntosd-dm320/uip/Make.defs +++ b/configs/ntosd-dm320/uip/Make.defs @@ -2,7 +2,7 @@ # configs/ntosd-dm320/uip/Make.defs # # Copyright (C) 2007-2008, 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/uip/appconfig b/configs/ntosd-dm320/uip/appconfig index cfd75d6a89f3d240e7588ff41b218be60db02e78..73bf15ba360d9724ef03ffd320e1ec4fc8ef9d66 100644 --- a/configs/ntosd-dm320/uip/appconfig +++ b/configs/ntosd-dm320/uip/appconfig @@ -2,7 +2,7 @@ # configs/ntosd-dm320/uip/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/uip/ld.script b/configs/ntosd-dm320/uip/ld.script index e9bee2f8c847c0203706b688a3d124b7acf9e149..57d763c8e1a817980c1bd07ecef2bc0d06ede3ae 100644 --- a/configs/ntosd-dm320/uip/ld.script +++ b/configs/ntosd-dm320/uip/ld.script @@ -2,7 +2,7 @@ * configs/ntosd-dm320/uip/ld.script * * Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/ntosd-dm320/uip/setenv.sh b/configs/ntosd-dm320/uip/setenv.sh index afc63692e1b755337c8a1384e5d07d6f94a587fa..ccc74829d8fba23ceae07dcdb054f55616e8b0da 100755 --- a/configs/ntosd-dm320/uip/setenv.sh +++ b/configs/ntosd-dm320/uip/setenv.sh @@ -2,7 +2,7 @@ # configs/ntosd-dm320/uip/setenv.sh # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/nsh/Make.defs b/configs/nucleus2g/nsh/Make.defs index 5bce6965174d6fc65b052e234cbf89d02e14ae11..44cab10a491691f03f645a7f90fa4fb71f77deb1 100755 --- a/configs/nucleus2g/nsh/Make.defs +++ b/configs/nucleus2g/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/nucleus2g/nsh/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/nsh/ld.script b/configs/nucleus2g/nsh/ld.script index 82170d40c969c25476012c423f94feb8a8d8bdc2..bc4d89cf175104b167d26ac0e70d46987213e419 100755 --- a/configs/nucleus2g/nsh/ld.script +++ b/configs/nucleus2g/nsh/ld.script @@ -2,7 +2,7 @@ * configs/nucleus2g/nsh/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/nsh/setenv.sh b/configs/nucleus2g/nsh/setenv.sh index 243490cc613927569e464f20f8074ab0610d9c68..ffdc74e9b907b576046878b0881b9b6986e93739 100755 --- a/configs/nucleus2g/nsh/setenv.sh +++ b/configs/nucleus2g/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/nucleus2g/nsh/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/ostest/Make.defs b/configs/nucleus2g/ostest/Make.defs index 359c012f843b7f38e8fe218bd192711b1c452461..614654a8fbed38e08e9bd9334b9484de29542f09 100755 --- a/configs/nucleus2g/ostest/Make.defs +++ b/configs/nucleus2g/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/nucleus2g/ostest/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/ostest/appconfig b/configs/nucleus2g/ostest/appconfig index 32b848f2d7f8ce6685c5907e1a9c13dd696a1ac9..835b8e1dc0b08244cad25e91fe0fe3f5b7ae9933 100644 --- a/configs/nucleus2g/ostest/appconfig +++ b/configs/nucleus2g/ostest/appconfig @@ -2,7 +2,7 @@ # configs/nucleus2g/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/ostest/ld.script b/configs/nucleus2g/ostest/ld.script index 1959ea88d6eda0d4335e88ee82dd0421b6e4599a..5d3b874af2b714b89027c10442b6ddb67e1a5d8e 100755 --- a/configs/nucleus2g/ostest/ld.script +++ b/configs/nucleus2g/ostest/ld.script @@ -2,7 +2,7 @@ * configs/nucleus2g/ostest/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/ostest/setenv.sh b/configs/nucleus2g/ostest/setenv.sh index 32d3b23c1e543e32819f8f8259b7ccc06aad44e4..6a78a5c239b84f1f9e3af5c1322564c7d168108f 100755 --- a/configs/nucleus2g/ostest/setenv.sh +++ b/configs/nucleus2g/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/nucleus2g/ostest/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/src/Makefile b/configs/nucleus2g/src/Makefile index 42a8b5cd2d70129b1df3f0d65b863ef69651e979..6e3fc94d2db9b2769e9e681262548a6ba6dfe801 100644 --- a/configs/nucleus2g/src/Makefile +++ b/configs/nucleus2g/src/Makefile @@ -2,7 +2,7 @@ # configs/nucleus2g/src/Makefile # # Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/src/up_leds.c b/configs/nucleus2g/src/up_leds.c index 64eaad65e0c2abb0d87ac922268fc155cd0f813d..41f955af4818419f1c08578b0097abf06e601caa 100644 --- a/configs/nucleus2g/src/up_leds.c +++ b/configs/nucleus2g/src/up_leds.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_leds.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/src/up_nsh.c b/configs/nucleus2g/src/up_nsh.c index 0707eaa35712f6e31e2e657ccf726071ebd57ef2..9986c82823796ebeb1b7067ad3ad49d7d821f52f 100644 --- a/configs/nucleus2g/src/up_nsh.c +++ b/configs/nucleus2g/src/up_nsh.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_nsh.c * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/src/up_ssp.c b/configs/nucleus2g/src/up_ssp.c index 1c7e3b5b07904abe90544c59dc4e600ce7ae8f7f..5515d49686a687772dc30aee6146cac872666cd6 100644 --- a/configs/nucleus2g/src/up_ssp.c +++ b/configs/nucleus2g/src/up_ssp.c @@ -1,185 +1,185 @@ -/************************************************************************************ - * configs/nucleus2g/src/up_ssp.c - * arch/arm/src/board/up_ssp.c - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "up_arch.h" -#include "chip.h" -#include "lpc17_internal.h" -#include "nucleus2g_internal.h" - -/* The LM3S6965 Eval Kit microSD CS is on SSI0 */ - -#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* Enables debug output from this file (needs CONFIG_DEBUG too) */ - -#undef SSP_DEBUG /* Define to enable debug */ -#undef SSP_VERBOSE /* Define to enable verbose debug */ - -#ifdef SSP_DEBUG -# define sspdbg lldbg -# ifdef SSP_VERBOSE -# define sspvdbg lldbg -# else -# define sspvdbg(x...) -# endif -#else -# undef SSP_VERBOSE -# define sspdbg(x...) -# define sspvdbg(x...) -#endif - -/* Dump GPIO registers */ - -#ifdef SSP_VERBOSE -# define ssp_dumpgpio(m) lpc17_dumpgpio(SDCCS_GPIO, m) -#else -# define ssp_dumpgpio(m) -#endif - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: lpc17_sspinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit. - * - ************************************************************************************/ - -void weak_function lpc17_sspinitialize(void) -{ - /* Configure the SPI-based microSD CS GPIO */ - - ssp_dumpgpio("lpc17_sspinitialize() Entry)"); - - /* SSP0 connects only to the MMC/SD slot on the Nucleus 1G board. - * P0[15]/TXD1/SCK0/SCK MMC_CLK - * P0[16]/RXD1/SSEL0/SSEL MMC_CD - * P0[17]/CTS1/MISO0/MISO MMC_DATA0 - * P0[18]/DCD1/MOSI0/MOSI MMC_MISO - * - * In SPI mode the MMC/SD DATA3/CD functions as the SPI chip select. - */ - -#ifdef CONFIG_LPC17_SSP0 - lpc17_configgpio(NUCLEUS2G_MMCSD_CS); -#endif - - /* SSP1 goes off the Nucleus 2G board to the Babel CAN board along with 3 chip - * select pins. However, it is currently not used on that board. - */ - -#ifdef CONFIG_LPC17_SSP1 -# warning "SSP1 chip selects not known" -#endif - ssp_dumpgpio("lpc17_sspinitialize() Exit"); -} - -/************************************************************************************ - * Name: lpc17_ssp0/ssp1select and lpc17_ssp0/ssp1status - * - * Description: - * The external functions, lpc17_ssp0/ssp1select and lpc17_ssp0/ssp1status - * must be provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi.h). All other methods (including up_spiinitialize()) - * are provided by common LPC17xx logic. To use this common SPI logic on your - * board: - * - * 1. Provide logic in lpc17_boardinitialize() to configure SPI/SSP chip select - * pins. - * 2. Provide lpc17_ssp0/ssp1select() and lpc17_ssp0/ssp1status() functions - * in your board-specific logic. These functions will perform chip selection - * and status operations using GPIOs in the way your board is configured. - * 3. Add a calls to up_spiinitialize() in your low level application - * initialization logic - * 4. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ************************************************************************************/ - -#ifdef CONFIG_LPC17_SSP0 -void lpc17_ssp0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) -{ - sspdbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - ssp_dumpgpio("lpc17_spiselect() Entry"); - - if (devid == SPIDEV_MMCSD) - { - /* Assert the CS pin to the card */ - - lpc17_gpiowrite(NUCLEUS2G_MMCSD_CS, !selected); - } - ssp_dumpgpio("lpc17_spiselect() Exit"); -} - -uint8_t lpc17_ssp0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) -{ - sspdbg("Returning SPI_STATUS_PRESENT\n"); - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_LPC17_SSP1 -# warning "SSP1 chip selects not known" -#endif - -#endif /* CONFIG_LPC17_SSP0 || CONFIG_LPC17_SSP1 */ +/************************************************************************************ + * configs/nucleus2g/src/up_ssp.c + * arch/arm/src/board/up_ssp.c + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "chip.h" +#include "lpc17_internal.h" +#include "nucleus2g_internal.h" + +/* The LM3S6965 Eval Kit microSD CS is on SSI0 */ + +#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1) + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Enables debug output from this file (needs CONFIG_DEBUG too) */ + +#undef SSP_DEBUG /* Define to enable debug */ +#undef SSP_VERBOSE /* Define to enable verbose debug */ + +#ifdef SSP_DEBUG +# define sspdbg lldbg +# ifdef SSP_VERBOSE +# define sspvdbg lldbg +# else +# define sspvdbg(x...) +# endif +#else +# undef SSP_VERBOSE +# define sspdbg(x...) +# define sspvdbg(x...) +#endif + +/* Dump GPIO registers */ + +#ifdef SSP_VERBOSE +# define ssp_dumpgpio(m) lpc17_dumpgpio(SDCCS_GPIO, m) +#else +# define ssp_dumpgpio(m) +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc17_sspinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit. + * + ************************************************************************************/ + +void weak_function lpc17_sspinitialize(void) +{ + /* Configure the SPI-based microSD CS GPIO */ + + ssp_dumpgpio("lpc17_sspinitialize() Entry)"); + + /* SSP0 connects only to the MMC/SD slot on the Nucleus 1G board. + * P0[15]/TXD1/SCK0/SCK MMC_CLK + * P0[16]/RXD1/SSEL0/SSEL MMC_CD + * P0[17]/CTS1/MISO0/MISO MMC_DATA0 + * P0[18]/DCD1/MOSI0/MOSI MMC_MISO + * + * In SPI mode the MMC/SD DATA3/CD functions as the SPI chip select. + */ + +#ifdef CONFIG_LPC17_SSP0 + lpc17_configgpio(NUCLEUS2G_MMCSD_CS); +#endif + + /* SSP1 goes off the Nucleus 2G board to the Babel CAN board along with 3 chip + * select pins. However, it is currently not used on that board. + */ + +#ifdef CONFIG_LPC17_SSP1 +# warning "SSP1 chip selects not known" +#endif + ssp_dumpgpio("lpc17_sspinitialize() Exit"); +} + +/************************************************************************************ + * Name: lpc17_ssp0/ssp1select and lpc17_ssp0/ssp1status + * + * Description: + * The external functions, lpc17_ssp0/ssp1select and lpc17_ssp0/ssp1status + * must be provided by board-specific logic. They are implementations of the select + * and status methods of the SPI interface defined by struct spi_ops_s (see + * include/nuttx/spi.h). All other methods (including up_spiinitialize()) + * are provided by common LPC17xx logic. To use this common SPI logic on your + * board: + * + * 1. Provide logic in lpc17_boardinitialize() to configure SPI/SSP chip select + * pins. + * 2. Provide lpc17_ssp0/ssp1select() and lpc17_ssp0/ssp1status() functions + * in your board-specific logic. These functions will perform chip selection + * and status operations using GPIOs in the way your board is configured. + * 3. Add a calls to up_spiinitialize() in your low level application + * initialization logic + * 4. The handle returned by up_spiinitialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ************************************************************************************/ + +#ifdef CONFIG_LPC17_SSP0 +void lpc17_ssp0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +{ + sspdbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + ssp_dumpgpio("lpc17_spiselect() Entry"); + + if (devid == SPIDEV_MMCSD) + { + /* Assert the CS pin to the card */ + + lpc17_gpiowrite(NUCLEUS2G_MMCSD_CS, !selected); + } + ssp_dumpgpio("lpc17_spiselect() Exit"); +} + +uint8_t lpc17_ssp0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ + sspdbg("Returning SPI_STATUS_PRESENT\n"); + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_LPC17_SSP1 +# warning "SSP1 chip selects not known" +#endif + +#endif /* CONFIG_LPC17_SSP0 || CONFIG_LPC17_SSP1 */ diff --git a/configs/nucleus2g/src/up_usbmsc.c b/configs/nucleus2g/src/up_usbmsc.c index c3d074b54e8258f29f7d2ae3c55e4344da85cbb2..8c71a5ce713980e4b420ce296acc3ac05b7d2a2d 100644 --- a/configs/nucleus2g/src/up_usbmsc.c +++ b/configs/nucleus2g/src/up_usbmsc.c @@ -2,7 +2,7 @@ * configs/nucleus2g/src/up_usbmsc.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Configure and register the LPC17xx MMC/SD SPI block driver. * diff --git a/configs/nucleus2g/usbserial/Make.defs b/configs/nucleus2g/usbserial/Make.defs index f711eac39d75c2f82fd14c3b5c980ab74303a351..92f540a1f6b530f4412f2cc05404803f1776078e 100755 --- a/configs/nucleus2g/usbserial/Make.defs +++ b/configs/nucleus2g/usbserial/Make.defs @@ -2,7 +2,7 @@ # configs/nucleus2g/usbserial/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/usbserial/appconfig b/configs/nucleus2g/usbserial/appconfig index dffbbd1fb5f49e962c7908cd194d62d48d7f258c..fe16aa81fa6f460223b16235b4da7f0af82081a5 100644 --- a/configs/nucleus2g/usbserial/appconfig +++ b/configs/nucleus2g/usbserial/appconfig @@ -2,7 +2,7 @@ # configs/nucleus2g/usbserial/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/usbserial/ld.script b/configs/nucleus2g/usbserial/ld.script index 2acba4f5ba73c687446560cb7884734eff88e16e..2fa9249ff7f45c909e296d9e0df90cfaa2aece3b 100755 --- a/configs/nucleus2g/usbserial/ld.script +++ b/configs/nucleus2g/usbserial/ld.script @@ -2,7 +2,7 @@ * configs/nucleus2g/usbserial/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/usbserial/setenv.sh b/configs/nucleus2g/usbserial/setenv.sh index 8f405b4195a063090c703be9ac30d1bbf887009b..9333b3a2f596a82eb72384dbb1fe922de1687505 100755 --- a/configs/nucleus2g/usbserial/setenv.sh +++ b/configs/nucleus2g/usbserial/setenv.sh @@ -2,7 +2,7 @@ # configs/nucleus2g/usbserial/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/usbstorage/Make.defs b/configs/nucleus2g/usbstorage/Make.defs index 272bdd88c2bc2b48f3233a2087974c358cc1a3dd..c71349c740c92f09e792258f6c7bcd3f9d847567 100755 --- a/configs/nucleus2g/usbstorage/Make.defs +++ b/configs/nucleus2g/usbstorage/Make.defs @@ -2,7 +2,7 @@ # configs/nucleus2g/usbstorage/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/usbstorage/appconfig b/configs/nucleus2g/usbstorage/appconfig index 24b3343490032e14ee57c8a25f813fd36a3447a5..9653e14a3f448ec44516fa28723e3f2fd55b897a 100644 --- a/configs/nucleus2g/usbstorage/appconfig +++ b/configs/nucleus2g/usbstorage/appconfig @@ -2,7 +2,7 @@ # configs/nucleus2g/usbstorage/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/usbstorage/ld.script b/configs/nucleus2g/usbstorage/ld.script index d5f0c086bd5920972cc13384177a8a5fe6bc12b9..a1056f8a7cfb87bc1358a5601245b136bdb2ca0b 100755 --- a/configs/nucleus2g/usbstorage/ld.script +++ b/configs/nucleus2g/usbstorage/ld.script @@ -2,7 +2,7 @@ * configs/nucleus2g/usbstorage/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/nucleus2g/usbstorage/setenv.sh b/configs/nucleus2g/usbstorage/setenv.sh index 702de2b02311cefeb02da31bba3bd5748a2ca743..e6f7197fd747744b0483a6951a790daaae2b3d39 100755 --- a/configs/nucleus2g/usbstorage/setenv.sh +++ b/configs/nucleus2g/usbstorage/setenv.sh @@ -2,7 +2,7 @@ # configs/nucleus2g/usbstorage/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/ftpc/Make.defs b/configs/olimex-lpc1766stk/ftpc/Make.defs index 255d832540f0717228a4f722cb8d6ac8107ab503..178287e8a6303a63d6331b67b235c69d6f11444f 100755 --- a/configs/olimex-lpc1766stk/ftpc/Make.defs +++ b/configs/olimex-lpc1766stk/ftpc/Make.defs @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/ftpc/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/ftpc/setenv.sh b/configs/olimex-lpc1766stk/ftpc/setenv.sh index 04c426b5218dfb5b42f7b3da6589deadabc1a799..85d20db32488c680b7542e6ca8ba86933edc95cc 100755 --- a/configs/olimex-lpc1766stk/ftpc/setenv.sh +++ b/configs/olimex-lpc1766stk/ftpc/setenv.sh @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/ftpc/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/hidkbd/Make.defs b/configs/olimex-lpc1766stk/hidkbd/Make.defs index 036e5f40b8c98c1b8d7c07adb4b69b298cc8bc51..50c8515cecf1223acc2b7565a7c94144f0d6d66b 100755 --- a/configs/olimex-lpc1766stk/hidkbd/Make.defs +++ b/configs/olimex-lpc1766stk/hidkbd/Make.defs @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/hidkbd/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/hidkbd/appconfig b/configs/olimex-lpc1766stk/hidkbd/appconfig index 74c50061340f9ce5f749139251b3e0010280b634..79a7c50abef8da09acf88ec395413814e5fbc732 100644 --- a/configs/olimex-lpc1766stk/hidkbd/appconfig +++ b/configs/olimex-lpc1766stk/hidkbd/appconfig @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/hidkbd/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/hidkbd/setenv.sh b/configs/olimex-lpc1766stk/hidkbd/setenv.sh index 1add4fe5c35f781873b3181831d46bf7fc94f863..7bdba25d768f45ca4de916cba6c3065a0b70ed81 100755 --- a/configs/olimex-lpc1766stk/hidkbd/setenv.sh +++ b/configs/olimex-lpc1766stk/hidkbd/setenv.sh @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/hidkbd/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/nettest/Make.defs b/configs/olimex-lpc1766stk/nettest/Make.defs index a9764339a2a1dc299aceb629aa5bb2e1e9676efd..69e01144b7b6235aa17cf4aa817f737b3f36f221 100755 --- a/configs/olimex-lpc1766stk/nettest/Make.defs +++ b/configs/olimex-lpc1766stk/nettest/Make.defs @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/nettest/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/nettest/appconfig b/configs/olimex-lpc1766stk/nettest/appconfig index 11b02d4c9e800b2349aa6ff796105a1363e65fb6..a54371a1dcbf8c44977eb86d24fd64e93ab61170 100644 --- a/configs/olimex-lpc1766stk/nettest/appconfig +++ b/configs/olimex-lpc1766stk/nettest/appconfig @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/nettest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/nettest/setenv.sh b/configs/olimex-lpc1766stk/nettest/setenv.sh index f481146df9b921b1db4181ac2b4e9d61457cbc76..58951dc840f024ec0f5147d920bf8a0105ba8738 100755 --- a/configs/olimex-lpc1766stk/nettest/setenv.sh +++ b/configs/olimex-lpc1766stk/nettest/setenv.sh @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/nettest/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/nsh/Make.defs b/configs/olimex-lpc1766stk/nsh/Make.defs index fcabaa38fa2e2c1c9f44d054427533026dc376a9..241d3644a6eae68625d567b3dc07281dd8ddaa0c 100755 --- a/configs/olimex-lpc1766stk/nsh/Make.defs +++ b/configs/olimex-lpc1766stk/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/nsh/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/nsh/setenv.sh b/configs/olimex-lpc1766stk/nsh/setenv.sh index 557d4ef6f7bd11dd711796a293f39b6fdefdc397..4b9bec6d049790635fbc9a8a5d1cc875cfd41eed 100755 --- a/configs/olimex-lpc1766stk/nsh/setenv.sh +++ b/configs/olimex-lpc1766stk/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/nsh/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/nx/Make.defs b/configs/olimex-lpc1766stk/nx/Make.defs index 5ca7cb0ea62152a6429e9a6bc3daf0a518641069..d6e00b56b604e207e5f2bd330e2fc57d05b135f8 100755 --- a/configs/olimex-lpc1766stk/nx/Make.defs +++ b/configs/olimex-lpc1766stk/nx/Make.defs @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/nx/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/nx/appconfig b/configs/olimex-lpc1766stk/nx/appconfig index 37c3b34d62330e08ad1a4fb61664deda061a642b..24d3641978da1ecd2e5c8edd5a0f96ee7cbfbde8 100644 --- a/configs/olimex-lpc1766stk/nx/appconfig +++ b/configs/olimex-lpc1766stk/nx/appconfig @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/nx/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/nx/setenv.sh b/configs/olimex-lpc1766stk/nx/setenv.sh index 3272035248ac84b7c29215c733193a4655bcc100..a2027d727ccb1a4e3a5d27e2aca132a604fe6f35 100755 --- a/configs/olimex-lpc1766stk/nx/setenv.sh +++ b/configs/olimex-lpc1766stk/nx/setenv.sh @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/nx/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/ostest/Make.defs b/configs/olimex-lpc1766stk/ostest/Make.defs index f8a169db7a565e11eec9a7d55b2c0922b1461e84..f5cc92b55df2a0ce2624db81473b7b06264488aa 100755 --- a/configs/olimex-lpc1766stk/ostest/Make.defs +++ b/configs/olimex-lpc1766stk/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/ostest/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/ostest/appconfig b/configs/olimex-lpc1766stk/ostest/appconfig index fd93a1e6573eba7f3dc445a256c80eeec54636a9..b83368c4753f175ad55e60122ce9501b118219a0 100644 --- a/configs/olimex-lpc1766stk/ostest/appconfig +++ b/configs/olimex-lpc1766stk/ostest/appconfig @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/ostest/setenv.sh b/configs/olimex-lpc1766stk/ostest/setenv.sh index e97d102b36181f09df13d5d504e195e22847356d..996cefc4e870021315cf40e55f4a051ba6b5ec23 100755 --- a/configs/olimex-lpc1766stk/ostest/setenv.sh +++ b/configs/olimex-lpc1766stk/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/ostest/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/slip-httpd/Make.defs b/configs/olimex-lpc1766stk/slip-httpd/Make.defs index db632f4e2cb3afc3282dafb561aae20b61c57ce1..ccdc4879f42b0a934f38004cb41543adea6a5b78 100755 --- a/configs/olimex-lpc1766stk/slip-httpd/Make.defs +++ b/configs/olimex-lpc1766stk/slip-httpd/Make.defs @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/slip-httpd/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/slip-httpd/appconfig b/configs/olimex-lpc1766stk/slip-httpd/appconfig index 1bc609e76e090889a7ff78531cbbcf86701d9fe5..2daaefbce678b2f27e0abd6cceb8655868d5d3c3 100644 --- a/configs/olimex-lpc1766stk/slip-httpd/appconfig +++ b/configs/olimex-lpc1766stk/slip-httpd/appconfig @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/slip-httpd/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/slip-httpd/setenv.sh b/configs/olimex-lpc1766stk/slip-httpd/setenv.sh index f5598a8653741ffbf00b9d7cea6798797d86bfd6..546ca1e3a4c156fdb79b4d19d33688f3d8ddcf57 100755 --- a/configs/olimex-lpc1766stk/slip-httpd/setenv.sh +++ b/configs/olimex-lpc1766stk/slip-httpd/setenv.sh @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/slip-httpd/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/src/up_lcd.c b/configs/olimex-lpc1766stk/src/up_lcd.c index e9fe0aa367ef663798907757aa88db9ee5f0afa0..93923b91a3191bd5b777b538b2e4d22cf9e69d27 100644 --- a/configs/olimex-lpc1766stk/src/up_lcd.c +++ b/configs/olimex-lpc1766stk/src/up_lcd.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_lcd.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/src/up_ssp.c b/configs/olimex-lpc1766stk/src/up_ssp.c index b3d1b0540724d04cf455a57cd3d5648265c68ef0..272a1706503a0ffb414467d93b1895f1f00c8911 100644 --- a/configs/olimex-lpc1766stk/src/up_ssp.c +++ b/configs/olimex-lpc1766stk/src/up_ssp.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_ssp.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/src/up_usbmsc.c b/configs/olimex-lpc1766stk/src/up_usbmsc.c index b92a9dc9e8a9a03be44c36c596f29d2fad5e7514..08c5fb88741b3fef13400de7c9c3ae94370c00a9 100644 --- a/configs/olimex-lpc1766stk/src/up_usbmsc.c +++ b/configs/olimex-lpc1766stk/src/up_usbmsc.c @@ -2,7 +2,7 @@ * configs/olimex-lpc1766stk/src/up_usbmsc.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Configure and register the LPC17xx MMC/SD SPI block driver. * diff --git a/configs/olimex-lpc1766stk/thttpd/Make.defs b/configs/olimex-lpc1766stk/thttpd/Make.defs index 312bceb2e65659b0d92aff2938398b2dd65d1c66..3f00495f55687e67ffad44b1848286126067276e 100755 --- a/configs/olimex-lpc1766stk/thttpd/Make.defs +++ b/configs/olimex-lpc1766stk/thttpd/Make.defs @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/thttpd/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/thttpd/appconfig b/configs/olimex-lpc1766stk/thttpd/appconfig index 6681a6bd96bdece5f82c19fe6dd86e804542d359..8357e2cb242a80852171452d0e1a2ba8f17638bb 100644 --- a/configs/olimex-lpc1766stk/thttpd/appconfig +++ b/configs/olimex-lpc1766stk/thttpd/appconfig @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/thttpd/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/thttpd/setenv.sh b/configs/olimex-lpc1766stk/thttpd/setenv.sh index 80e519cc9d92a19104e0a3d5f9241ca2e3eac321..09288f04c027ead0e6fbb31fc5a99a8241f42f20 100755 --- a/configs/olimex-lpc1766stk/thttpd/setenv.sh +++ b/configs/olimex-lpc1766stk/thttpd/setenv.sh @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/thttpd/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/usbserial/Make.defs b/configs/olimex-lpc1766stk/usbserial/Make.defs index deb7525fab1f76e3fc3c42110760b4b9a28f9d8f..18e30e664c6280b106be7df9da925d4603598c03 100755 --- a/configs/olimex-lpc1766stk/usbserial/Make.defs +++ b/configs/olimex-lpc1766stk/usbserial/Make.defs @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/usbserial/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/usbserial/appconfig b/configs/olimex-lpc1766stk/usbserial/appconfig index 5126ff19e0bb4ffaf63f22a206742b47918e2199..2b73ffd794c06ed478b5ee30d1e8f4957b94e138 100644 --- a/configs/olimex-lpc1766stk/usbserial/appconfig +++ b/configs/olimex-lpc1766stk/usbserial/appconfig @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/usbserial/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/usbserial/setenv.sh b/configs/olimex-lpc1766stk/usbserial/setenv.sh index eff7d8483b24168dace6b4a64a8a880c29d66e24..f755b6afe90913de354f2e94d3f5a98145c67f24 100755 --- a/configs/olimex-lpc1766stk/usbserial/setenv.sh +++ b/configs/olimex-lpc1766stk/usbserial/setenv.sh @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/usbserial/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/usbstorage/Make.defs b/configs/olimex-lpc1766stk/usbstorage/Make.defs index 6b719602d7b38ec871e2c9a507a9df9c510a9533..1999989f75f80992b4062d14c5c06dd10add11fc 100755 --- a/configs/olimex-lpc1766stk/usbstorage/Make.defs +++ b/configs/olimex-lpc1766stk/usbstorage/Make.defs @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/usbstorage/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/usbstorage/appconfig b/configs/olimex-lpc1766stk/usbstorage/appconfig index 6b56f9785fb599b4dd78073cbf125156b0a5e09e..073634d41b1e175ae28a00af93eb88fb59cfc89d 100644 --- a/configs/olimex-lpc1766stk/usbstorage/appconfig +++ b/configs/olimex-lpc1766stk/usbstorage/appconfig @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/usbstorage/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/usbstorage/setenv.sh b/configs/olimex-lpc1766stk/usbstorage/setenv.sh index 5c150cf07d65c6f723fc3cd0620b3b3fb7f0466a..e41283c43885e796b0e4413d4e9f39e43f706fe1 100755 --- a/configs/olimex-lpc1766stk/usbstorage/setenv.sh +++ b/configs/olimex-lpc1766stk/usbstorage/setenv.sh @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/usbstorage/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/wlan/Make.defs b/configs/olimex-lpc1766stk/wlan/Make.defs index 0ae00ae6c2de0037b85b2611c2880e37788d31b3..0fcde7accefd950b7c4dac271670391843ca058b 100755 --- a/configs/olimex-lpc1766stk/wlan/Make.defs +++ b/configs/olimex-lpc1766stk/wlan/Make.defs @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/wlan/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/wlan/appconfig b/configs/olimex-lpc1766stk/wlan/appconfig index 17055072aeaf35a000d9049d910fd77b6b8ffe94..7fb2871aaf263b2d60ff19af4c4648e46a05f922 100644 --- a/configs/olimex-lpc1766stk/wlan/appconfig +++ b/configs/olimex-lpc1766stk/wlan/appconfig @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/wlan/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc1766stk/wlan/setenv.sh b/configs/olimex-lpc1766stk/wlan/setenv.sh index 84cb7c5bba30108ab6cdc47bd61a26f6db4137bf..1b87dab69c9be584c852dcd5970cd97b0f42c4ec 100755 --- a/configs/olimex-lpc1766stk/wlan/setenv.sh +++ b/configs/olimex-lpc1766stk/wlan/setenv.sh @@ -2,7 +2,7 @@ # configs/olimex-lpc1766stk/wlan/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc2378/include/board.h b/configs/olimex-lpc2378/include/board.h index c6dd70c1d22c094ae6378f9d6fcc23a39793e918..44919c46c82fe1b951ac214ce9d1bbe51534c74b 100755 --- a/configs/olimex-lpc2378/include/board.h +++ b/configs/olimex-lpc2378/include/board.h @@ -1,90 +1,90 @@ -/**************************************************************************** - * configs/olimex-lpc2378/include/board.h - * - * Copyright (C) 2010 Rommel Marcelo. All rights reserved. - * Author: Rommel Marcelo - * - * This is part of the NuttX RTOS and based on the LPC2148 port: - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_BOARD_BOARD_H -#define __ARCH_BOARD_BOARD_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* If USB is enabled, PLL must be configured for 48MHz to provide USB clocking */ -//-- F_pll = (2 * M * F_in)/N -//-- F_out = ((2 * (PLL_M + 1 ) * FOSC)/(0+1))/(CCLK_DIV+1) = 288/5 = 57 600 000 Hz -//~ #ifdef CONFIG_USBDEV - //~ # define FOSC (12000000) /* Oscillator frequency */ - //~ # define CCLK (57600000) /* CPU running clock */ - //~ # define FCCO (288000000) /* CPU CCO clock */ -//~ #else - # define FOSC (12000000) /* Oscillator frequency */ - # define CCLK (57600000) /* CPU running clock */ - # define FCCO (288000000) /* CPU CCO clock */ - //~ # define CCLK (72000000) /* CPU running clock */ - //~ # define FCCO (360000000) /* CPU CCO clock */ -//~ #endif - -//~#define PLL_M ( (FCCO / (2 * FOSC))-1 ) -//~ #define PLL_N ( ((2 * PLL_M * FOSC) / FCCO)-1 ) -#define PLL_M 11 -#define PLL_N 0 - -#define CCLK_DIV 4 -#define USBCLK_DIV 6 - - /* LED definitions **********************************************************/ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 1 -#define LED_IRQSENABLED 2 -#define LED_STACKCREATED 3 -#define LED_INIRQ 4 -#define LED_SIGNAL 5 -#define LED_ASSERTION 6 -#define LED_PANIC 7 - -#ifdef __cplusplus - } -#endif - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -#endif /* __ARCH_BOARD_BOARD_H */ +/**************************************************************************** + * configs/olimex-lpc2378/include/board.h + * + * Copyright (C) 2010 Rommel Marcelo. All rights reserved. + * Author: Rommel Marcelo + * + * This is part of the NuttX RTOS and based on the LPC2148 port: + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_BOARD_BOARD_H +#define __ARCH_BOARD_BOARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* If USB is enabled, PLL must be configured for 48MHz to provide USB clocking */ +//-- F_pll = (2 * M * F_in)/N +//-- F_out = ((2 * (PLL_M + 1 ) * FOSC)/(0+1))/(CCLK_DIV+1) = 288/5 = 57 600 000 Hz +//~ #ifdef CONFIG_USBDEV + //~ # define FOSC (12000000) /* Oscillator frequency */ + //~ # define CCLK (57600000) /* CPU running clock */ + //~ # define FCCO (288000000) /* CPU CCO clock */ +//~ #else + # define FOSC (12000000) /* Oscillator frequency */ + # define CCLK (57600000) /* CPU running clock */ + # define FCCO (288000000) /* CPU CCO clock */ + //~ # define CCLK (72000000) /* CPU running clock */ + //~ # define FCCO (360000000) /* CPU CCO clock */ +//~ #endif + +//~#define PLL_M ( (FCCO / (2 * FOSC))-1 ) +//~ #define PLL_N ( ((2 * PLL_M * FOSC) / FCCO)-1 ) +#define PLL_M 11 +#define PLL_N 0 + +#define CCLK_DIV 4 +#define USBCLK_DIV 6 + + /* LED definitions **********************************************************/ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 1 +#define LED_IRQSENABLED 2 +#define LED_STACKCREATED 3 +#define LED_INIRQ 4 +#define LED_SIGNAL 5 +#define LED_ASSERTION 6 +#define LED_PANIC 7 + +#ifdef __cplusplus + } +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#endif /* __ARCH_BOARD_BOARD_H */ diff --git a/configs/olimex-lpc2378/nsh/Make.defs b/configs/olimex-lpc2378/nsh/Make.defs index 956c7a1027adc458e7f749e2a8f1ca01e9845b48..c970a93d16948c59fc940ecf41cb3c837163a06d 100755 --- a/configs/olimex-lpc2378/nsh/Make.defs +++ b/configs/olimex-lpc2378/nsh/Make.defs @@ -7,7 +7,7 @@ # This is part of the NuttX RTOS and based on the LPC2148 port: # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc2378/nsh/defconfig b/configs/olimex-lpc2378/nsh/defconfig index a9ce391b34c7d7be14f0d7ec6d37d999b636e6bd..98cd2b5fe1289f61380d966f41ec882204a2b21d 100755 --- a/configs/olimex-lpc2378/nsh/defconfig +++ b/configs/olimex-lpc2378/nsh/defconfig @@ -7,7 +7,7 @@ # This is part of the NuttX RTOS and based on the LPC2148 port: # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc2378/nsh/ld.script b/configs/olimex-lpc2378/nsh/ld.script index cf8ba46bd6461b2631df51e7f43c164caf08171a..d591fcd66391f91911f6e5800ba430226d0f2a55 100755 --- a/configs/olimex-lpc2378/nsh/ld.script +++ b/configs/olimex-lpc2378/nsh/ld.script @@ -7,7 +7,7 @@ * This is part of the NuttX RTOS and based on the LPC2148 port: * * Copyright (C) 2010, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc2378/nsh/setenv.sh b/configs/olimex-lpc2378/nsh/setenv.sh index 90871fd6239a5d8e6f1d02e7cf88f22576065240..9a2e92e432419f79aa4bba5f29f49bb6f7e5c268 100755 --- a/configs/olimex-lpc2378/nsh/setenv.sh +++ b/configs/olimex-lpc2378/nsh/setenv.sh @@ -7,7 +7,7 @@ # This is part of the NuttX RTOS and based on the LPC2148 port: # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc2378/ostest/Make.defs b/configs/olimex-lpc2378/ostest/Make.defs index 4e1aa9d0deff85190b8c6f7c471e9d0c2b2a3c14..ea419290833659a3385bc6ea3b97c4748997ba70 100755 --- a/configs/olimex-lpc2378/ostest/Make.defs +++ b/configs/olimex-lpc2378/ostest/Make.defs @@ -7,7 +7,7 @@ # This is part of the NuttX RTOS and based on the LPC2148 port: # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc2378/ostest/appconfig b/configs/olimex-lpc2378/ostest/appconfig index 2669ab4325b5d42b4b1769716d7e9122f26de2b7..e7452911616df151a98b32b2142b6714117ed19e 100644 --- a/configs/olimex-lpc2378/ostest/appconfig +++ b/configs/olimex-lpc2378/ostest/appconfig @@ -2,7 +2,7 @@ # configs/olimex-lpc2378/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc2378/ostest/defconfig b/configs/olimex-lpc2378/ostest/defconfig index d1a4c83d6862f118d894077bde6810360d1e5685..df6c0e1cb0b4839eb2a1f03fd1caba10351900b6 100755 --- a/configs/olimex-lpc2378/ostest/defconfig +++ b/configs/olimex-lpc2378/ostest/defconfig @@ -7,7 +7,7 @@ # This is part of the NuttX RTOS and based on the LPC2148 port: # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc2378/ostest/ld.script b/configs/olimex-lpc2378/ostest/ld.script index 74c798b57fc5d010578ba39414819ca8a7bf7776..e9ffbb4508afb94380bf9cba4ce34d6fbf984508 100755 --- a/configs/olimex-lpc2378/ostest/ld.script +++ b/configs/olimex-lpc2378/ostest/ld.script @@ -7,7 +7,7 @@ * This is part of the NuttX RTOS and based on the LPC2148 port: * * Copyright (C) 2010, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc2378/ostest/setenv.sh b/configs/olimex-lpc2378/ostest/setenv.sh index c55ede833e6a5f940d22e8173410e74f479f3a49..73bf3d2239979ba0ee560b2b2f4af112a93b29ea 100755 --- a/configs/olimex-lpc2378/ostest/setenv.sh +++ b/configs/olimex-lpc2378/ostest/setenv.sh @@ -7,7 +7,7 @@ # This is part of the NuttX RTOS and based on the LPC2148 port: # # Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc2378/src/Makefile b/configs/olimex-lpc2378/src/Makefile index 1319a49155d32bef3f76260a2dd45e3311fb030f..a9fa9fc70f0d7c2b06fd066e18332f39fc63b62a 100644 --- a/configs/olimex-lpc2378/src/Makefile +++ b/configs/olimex-lpc2378/src/Makefile @@ -7,7 +7,7 @@ # This is part of the NuttX RTOS and based on the LPC2148 port: # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc2378/src/up_leds.c b/configs/olimex-lpc2378/src/up_leds.c index e360eb5cd116005d5068601d7a254342ca12d545..a5bb955f5144351e69fa0b0514766522494a6b47 100644 --- a/configs/olimex-lpc2378/src/up_leds.c +++ b/configs/olimex-lpc2378/src/up_leds.c @@ -7,7 +7,7 @@ * This is part of the NuttX RTOS and based on the LPC2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/olimex-lpc2378/src/up_nsh.c b/configs/olimex-lpc2378/src/up_nsh.c index 9e3a0f6951959159852dca9055da393da2ad00b2..6279a7668f487696f15d8ec0deaa1c9336575256 100644 --- a/configs/olimex-lpc2378/src/up_nsh.c +++ b/configs/olimex-lpc2378/src/up_nsh.c @@ -8,7 +8,7 @@ * This is part of the NuttX RTOS and based on the LPC2148 port: * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/olimex-stm32-p107/nsh/appconfig b/configs/olimex-stm32-p107/nsh/appconfig index 56daadc52926aaf8344b44d55de607034320c8f9..99e845ffbd3dfb9577412d99c77271c4ed9ec903 100644 --- a/configs/olimex-stm32-p107/nsh/appconfig +++ b/configs/olimex-stm32-p107/nsh/appconfig @@ -2,7 +2,7 @@ # configs/olimex-stm32-p107/nsh/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-stm32-p107/nsh/setenv.sh b/configs/olimex-stm32-p107/nsh/setenv.sh index 6884313cda46db0416f0f8c3d95564faf09b010d..004f025b8f1fe28012c370ae6f5bacddbc0f3b06 100755 --- a/configs/olimex-stm32-p107/nsh/setenv.sh +++ b/configs/olimex-stm32-p107/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/olimex-stm32-p107/nsh/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-stm32-p107/ostest/appconfig b/configs/olimex-stm32-p107/ostest/appconfig index 18d8040abeb46d378b7cd3c7163ff4d8ee91557a..fca902395eb9df80307264bdb7ed6c3c9bdb89f1 100644 --- a/configs/olimex-stm32-p107/ostest/appconfig +++ b/configs/olimex-stm32-p107/ostest/appconfig @@ -2,7 +2,7 @@ # configs/olimex-stm32-p107/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-stm32-p107/ostest/setenv.sh b/configs/olimex-stm32-p107/ostest/setenv.sh index 009c5ce22fb0f18ea0f2b66467a11d9c5a57eb61..fe40c0bc19be5d9592f45969561fd23c824431df 100755 --- a/configs/olimex-stm32-p107/ostest/setenv.sh +++ b/configs/olimex-stm32-p107/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/olimex-stm32-p107/ostest/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-strp711/include/board.h b/configs/olimex-strp711/include/board.h index 1d4b503c4beca0b023f8f777f4660d16e9f09526..1a68ec74133f5cc67dd01973b95118526543e250 100644 --- a/configs/olimex-strp711/include/board.h +++ b/configs/olimex-strp711/include/board.h @@ -2,7 +2,7 @@ * configs/olimex-strp711/include/board.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/olimex-strp711/nettest/Make.defs b/configs/olimex-strp711/nettest/Make.defs index 6e6680dff05c03e66f1b1357e31094193eb1d404..f160c16f7014642777460741a15e68ce217c3080 100755 --- a/configs/olimex-strp711/nettest/Make.defs +++ b/configs/olimex-strp711/nettest/Make.defs @@ -2,7 +2,7 @@ # configs/olimex-strp711/nettest/Make.defs # # Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-strp711/nettest/appconfig b/configs/olimex-strp711/nettest/appconfig index 68aa1f56b1d4f8b7057aad890c4112c6cfacc392..bbe7abc022bbfb07ebe74824b7f14576420d49e1 100644 --- a/configs/olimex-strp711/nettest/appconfig +++ b/configs/olimex-strp711/nettest/appconfig @@ -2,7 +2,7 @@ # configs/olimex-strp711/nettest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-strp711/nettest/ld.script b/configs/olimex-strp711/nettest/ld.script index 4d91c5c7510b0864ff1cd3689f35c730bd372e5a..b3b5c6ff87b68fffd6b0f394dedf3369207c3839 100755 --- a/configs/olimex-strp711/nettest/ld.script +++ b/configs/olimex-strp711/nettest/ld.script @@ -2,7 +2,7 @@ * configs/olimex-strp711/nettest/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/olimex-strp711/nettest/setenv.sh b/configs/olimex-strp711/nettest/setenv.sh index 419731319b72a54b63ed18c86c564138f8f540a9..bc47c3ed8a2ac392b8d20a25d66f66f4653fd890 100755 --- a/configs/olimex-strp711/nettest/setenv.sh +++ b/configs/olimex-strp711/nettest/setenv.sh @@ -2,7 +2,7 @@ # configs/olimex-strp711/nettest/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-strp711/nsh/Make.defs b/configs/olimex-strp711/nsh/Make.defs index 8dd122bcbe261d5dd5df8043d5aa2ec92a1aa9de..229da6bff3e0596f5ed0d64006853954e22df88a 100644 --- a/configs/olimex-strp711/nsh/Make.defs +++ b/configs/olimex-strp711/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/olimex-strp711/nsh/Make.defs # # Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-strp711/nsh/defconfig b/configs/olimex-strp711/nsh/defconfig index a5eda6d0132151d58d92f5b030db97eb184b7ba5..985e3690ee252b21133d2de390a66d61bdd0ae53 100644 --- a/configs/olimex-strp711/nsh/defconfig +++ b/configs/olimex-strp711/nsh/defconfig @@ -2,7 +2,7 @@ # configs/olimes-strp711/nsh/defconfig # # Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-strp711/nsh/ld.script b/configs/olimex-strp711/nsh/ld.script index a4ee85eabe914f13a39e17ce917989842e121e40..7a95410f4736aee6040c4eb9f417b042ffc8c3bb 100644 --- a/configs/olimex-strp711/nsh/ld.script +++ b/configs/olimex-strp711/nsh/ld.script @@ -2,7 +2,7 @@ * configs/olimex-strp711/nsh/ld.script * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/olimex-strp711/nsh/setenv.sh b/configs/olimex-strp711/nsh/setenv.sh index 42fef8da64ffaf94e0d6aaaa97949f7ede465bbf..6724741f6976a68d3f3aefe80cd91a2d667955af 100755 --- a/configs/olimex-strp711/nsh/setenv.sh +++ b/configs/olimex-strp711/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/olimex-strp711/nsh/setenv.sh # # Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-strp711/ostest/Make.defs b/configs/olimex-strp711/ostest/Make.defs index f126151b15cb61adbf30cbeb851aa8a303ddc346..6c563295046ef533ac9079ea319cc6b9b9636b30 100644 --- a/configs/olimex-strp711/ostest/Make.defs +++ b/configs/olimex-strp711/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/olimex-strp711/ostest/Make.defs # # Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-strp711/ostest/appconfig b/configs/olimex-strp711/ostest/appconfig index 52724f1cfe97fc81678bd257f20f07421d092524..422014304138c332669c7adadb69e17e9a2df0e9 100644 --- a/configs/olimex-strp711/ostest/appconfig +++ b/configs/olimex-strp711/ostest/appconfig @@ -2,7 +2,7 @@ # configs/olimex-strp711/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-strp711/ostest/defconfig b/configs/olimex-strp711/ostest/defconfig index 87ce49749a67df5df07a02d4ea598947b2d0cf51..cdac22b9f6ece1969b80f013a0d02026ca11e65b 100644 --- a/configs/olimex-strp711/ostest/defconfig +++ b/configs/olimex-strp711/ostest/defconfig @@ -2,7 +2,7 @@ # configs/olimes-strp711/ostest/defconfig # # Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-strp711/ostest/ld.script b/configs/olimex-strp711/ostest/ld.script index 017d8f4dd5e299580d8f701fdb656f9f7d1d273f..9a5c45745356585778dda23a7cbc7641b53c570d 100644 --- a/configs/olimex-strp711/ostest/ld.script +++ b/configs/olimex-strp711/ostest/ld.script @@ -2,7 +2,7 @@ * configs/olimex-strp711/ostest/ld.script * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/olimex-strp711/ostest/setenv.sh b/configs/olimex-strp711/ostest/setenv.sh index 726ef404db7d745dad63edcaeb02013d9cc6822b..c9454d26f6ad2463b6cd438a9ffd8d8ff021a8dd 100755 --- a/configs/olimex-strp711/ostest/setenv.sh +++ b/configs/olimex-strp711/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/olimex-strp711/ostest/setenv.sh # # Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/olimex-strp711/src/up_buttons.c b/configs/olimex-strp711/src/up_buttons.c index 1a10fd4002be40626a812e99ed99cb0756470ded..e8737954cca57a63e7568fe4cc695250993d9274 100644 --- a/configs/olimex-strp711/src/up_buttons.c +++ b/configs/olimex-strp711/src/up_buttons.c @@ -2,7 +2,7 @@ * configs/olimex-strp711/src/up_leds.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/olimex-strp711/src/up_leds.c b/configs/olimex-strp711/src/up_leds.c index 08b6cbb6fbac0ac6b35b9c392498da4e7e59275f..2d099f6bc679ee2669159e6c00af197752b12a6c 100644 --- a/configs/olimex-strp711/src/up_leds.c +++ b/configs/olimex-strp711/src/up_leds.c @@ -2,7 +2,7 @@ * configs/olimex-strp711/src/up_leds.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/olimex-strp711/src/up_nsh.c b/configs/olimex-strp711/src/up_nsh.c index 249898933b4c168bfcff72d3d71149dffcb39379..21c3efb83e28891c9e962dbecb2a18c3070f6b0e 100644 --- a/configs/olimex-strp711/src/up_nsh.c +++ b/configs/olimex-strp711/src/up_nsh.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_nsh.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/pcblogic-pic32mx/nsh/Make.defs b/configs/pcblogic-pic32mx/nsh/Make.defs index e6362ee874e074e760386d3df1f76b87e87829dc..ffefef7ff67d4f27bed4d6d3e7d174c6634e55a0 100644 --- a/configs/pcblogic-pic32mx/nsh/Make.defs +++ b/configs/pcblogic-pic32mx/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/pcblogic-pic32mx/nsh/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/pcblogic-pic32mx/nsh/ld.script b/configs/pcblogic-pic32mx/nsh/ld.script index 4d3b71b285d3b2549e57258cddd98ad4a5c88913..ff1618acfb0cfd30bc7d0d3829a808292c332e75 100644 --- a/configs/pcblogic-pic32mx/nsh/ld.script +++ b/configs/pcblogic-pic32mx/nsh/ld.script @@ -2,7 +2,7 @@ * configs/pcblogic-pic32mx/nsh/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/pcblogic-pic32mx/ostest/Make.defs b/configs/pcblogic-pic32mx/ostest/Make.defs index 488e7d4de75e967a4c1c805cac7b1c0bc059a6fe..639466f22be0cb8e0740cfa13b00b2cdfe1c788b 100644 --- a/configs/pcblogic-pic32mx/ostest/Make.defs +++ b/configs/pcblogic-pic32mx/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/pcblogic-pic32mx/ostest/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/pcblogic-pic32mx/ostest/appconfig b/configs/pcblogic-pic32mx/ostest/appconfig index 048de1768c55633682a7ed86540bac032ac02819..fc81262497d1b22e997f9905e3131d347459df1f 100644 --- a/configs/pcblogic-pic32mx/ostest/appconfig +++ b/configs/pcblogic-pic32mx/ostest/appconfig @@ -2,7 +2,7 @@ # configs/pcblogic-pic32mx/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/pcblogic-pic32mx/ostest/ld.script b/configs/pcblogic-pic32mx/ostest/ld.script index ff4015be167facbaac27bd551b533c589f4991d8..dd181b4d98d6f17c99e9c6cd769381398410ed78 100644 --- a/configs/pcblogic-pic32mx/ostest/ld.script +++ b/configs/pcblogic-pic32mx/ostest/ld.script @@ -2,7 +2,7 @@ * configs/pcblogic-pic32mx/ostest/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/pcblogic-pic32mx/src/Makefile b/configs/pcblogic-pic32mx/src/Makefile index 42301c59cbb295ecd6103b6d57f72d0c246050bb..9ca5c4f57d93a3febb15764d2f53ed893f58c814 100644 --- a/configs/pcblogic-pic32mx/src/Makefile +++ b/configs/pcblogic-pic32mx/src/Makefile @@ -2,7 +2,7 @@ # configs/pcblogic-pic32mx/src/Makefile # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/pcblogic-pic32mx/src/pcblogic-internal.h b/configs/pcblogic-pic32mx/src/pcblogic-internal.h index f01ec46ee900a059471703530f3bad1d025ee215..2e0963e269e31a3f30f29c76ef48a8e1855cfdea 100644 --- a/configs/pcblogic-pic32mx/src/pcblogic-internal.h +++ b/configs/pcblogic-pic32mx/src/pcblogic-internal.h @@ -2,7 +2,7 @@ * configs/pcblogic-pic32mx/src/pcblogic-internal.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/pcblogic-pic32mx/src/up_boot.c b/configs/pcblogic-pic32mx/src/up_boot.c index a377d79ad6ef5ff786073d869467171b4b8f9f91..2c9634fc06f71aa44276e5fc6cda6ac80c983d68 100644 --- a/configs/pcblogic-pic32mx/src/up_boot.c +++ b/configs/pcblogic-pic32mx/src/up_boot.c @@ -3,7 +3,7 @@ * arch/mips/src/board/up_boot.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/pjrc-8051/appconfig b/configs/pjrc-8051/appconfig index d88edca753f5989be8a19cf3f33f683b2df67261..7beb0d69109484e0311eeb33636dec1e065ea302 100644 --- a/configs/pjrc-8051/appconfig +++ b/configs/pjrc-8051/appconfig @@ -2,7 +2,7 @@ # configs/pjrc-8051/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/pjrc-8051/include/board.h b/configs/pjrc-8051/include/board.h index fe036da8c3d7e7873d92e61efb90fc5930a24caf..9f518f81ee9f330ed3e5ba7b5212e70e07097749 100644 --- a/configs/pjrc-8051/include/board.h +++ b/configs/pjrc-8051/include/board.h @@ -2,7 +2,7 @@ * board/board.h * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/pjrc-8051/include/pjrc.h b/configs/pjrc-8051/include/pjrc.h index 50dfe01f2c82c047cced119a7a60e3a39371a45a..9d0d9482a1ae409fc2ff20e89ae47f8e2bb38475 100644 --- a/configs/pjrc-8051/include/pjrc.h +++ b/configs/pjrc-8051/include/pjrc.h @@ -2,7 +2,7 @@ * pjrc.h * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/pjrc-8051/setenv.sh b/configs/pjrc-8051/setenv.sh index 35f5fffeded41076d3d630fc6d2e75664951eca2..d71c234ba29feab331076567b055e786f085aabb 100755 --- a/configs/pjrc-8051/setenv.sh +++ b/configs/pjrc-8051/setenv.sh @@ -2,7 +2,7 @@ # pjrc-8051/setenv.sh # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/pjrc-8051/src/Makefile b/configs/pjrc-8051/src/Makefile index d6af2a6fe7b57c803b911452bd3a30742887df80..7783ad1fbc38ada7d1f2912ac5deb9c8c428d0f0 100644 --- a/configs/pjrc-8051/src/Makefile +++ b/configs/pjrc-8051/src/Makefile @@ -2,7 +2,7 @@ # configs/pjrc-8051/src/Makefile # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/pjrc-8051/src/up_leds.c b/configs/pjrc-8051/src/up_leds.c index 5ac842d1e76eb3374359817ec963d352cc790b06..64446b5e397262bb01c39a642f27d5ecdf85702b 100644 --- a/configs/pjrc-8051/src/up_leds.c +++ b/configs/pjrc-8051/src/up_leds.c @@ -2,7 +2,7 @@ * up_leds.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/qemu-i486/include/board.h b/configs/qemu-i486/include/board.h index 31ae72dc4dd8b6e54228bc68f4617d01ef6f23c8..4dcd9d7a8b97d46ed9a7d2803c1ed1861544f2fc 100755 --- a/configs/qemu-i486/include/board.h +++ b/configs/qemu-i486/include/board.h @@ -3,7 +3,7 @@ * include/arch/board/board.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/qemu-i486/nsh/Make.defs b/configs/qemu-i486/nsh/Make.defs index 043c072beae62f185438e6ae6373de80a93156a8..398c11496f36f26e72acc08685d4e5f3d2ae2395 100644 --- a/configs/qemu-i486/nsh/Make.defs +++ b/configs/qemu-i486/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/qemu-i486/nsh/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/qemu-i486/nsh/defconfig b/configs/qemu-i486/nsh/defconfig index 8fb1fff89f1fd2e2733627f0745967e9be355841..72e97539a3fd47fe62118de83c0b66107106d3db 100644 --- a/configs/qemu-i486/nsh/defconfig +++ b/configs/qemu-i486/nsh/defconfig @@ -2,7 +2,7 @@ # configs/qemu-i486/nsh/defconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/qemu-i486/nsh/ld.script b/configs/qemu-i486/nsh/ld.script index d0abd245dbf1eddeeeb385bc73b55d3c15dae053..3fffc84592bd49f862f9a909359acbd69420c747 100755 --- a/configs/qemu-i486/nsh/ld.script +++ b/configs/qemu-i486/nsh/ld.script @@ -2,7 +2,7 @@ * configs/qemu-i486/nsh/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/qemu-i486/nsh/setenv.sh b/configs/qemu-i486/nsh/setenv.sh index de427d2b66c1b9c089e46f03a53794348abcdb13..25ae59d71bd344afa61d560f5a725e3429445ad5 100755 --- a/configs/qemu-i486/nsh/setenv.sh +++ b/configs/qemu-i486/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/qemu-i486/nsh/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/qemu-i486/ostest/Make.defs b/configs/qemu-i486/ostest/Make.defs index 1221a83d475cb120d847f2f69306eaea18f4d9b7..1bd0b63d64d4662673b6a35cf381157d0a180f77 100644 --- a/configs/qemu-i486/ostest/Make.defs +++ b/configs/qemu-i486/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/qemu-i486/ostest/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/qemu-i486/ostest/appconfig b/configs/qemu-i486/ostest/appconfig index 73b5540a09f94286d0dfd6689b67704a65986293..c78f650b27c7fe12fcd635aa4a9d63b8b87d6a4c 100644 --- a/configs/qemu-i486/ostest/appconfig +++ b/configs/qemu-i486/ostest/appconfig @@ -2,7 +2,7 @@ # configs/qemu-i486/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/qemu-i486/ostest/defconfig b/configs/qemu-i486/ostest/defconfig index 0fa5f5cb6dbdcbbc00300f6ecbf61b0a2c5645d6..3f87e11cd8a94d70cf4aecdc9a1b8ed479edf5bf 100644 --- a/configs/qemu-i486/ostest/defconfig +++ b/configs/qemu-i486/ostest/defconfig @@ -2,7 +2,7 @@ # configs/qemu-i486/ostest/defconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/qemu-i486/ostest/ld.script b/configs/qemu-i486/ostest/ld.script index 5b3053f56c9e772f3b729c82e949348ac5a26047..d597710783322382929206d14de928398e397879 100755 --- a/configs/qemu-i486/ostest/ld.script +++ b/configs/qemu-i486/ostest/ld.script @@ -2,7 +2,7 @@ * configs/qemu-i486/ostest/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/qemu-i486/ostest/setenv.sh b/configs/qemu-i486/ostest/setenv.sh index 50ace04dde90d44c2f803078eda28dbc3c747230..f9c3bdec8d6d2e8c66b5c6f8c39feae7562da0cf 100755 --- a/configs/qemu-i486/ostest/setenv.sh +++ b/configs/qemu-i486/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/qemu-i486/ostest/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/qemu-i486/src/Makefile b/configs/qemu-i486/src/Makefile index 0271a6be5d5494c60f6d1c2ccfcb8e1b4dd0a56a..287e4e7285d30e28486f6a72a75cca1c7d1cc895 100644 --- a/configs/qemu-i486/src/Makefile +++ b/configs/qemu-i486/src/Makefile @@ -2,7 +2,7 @@ # configs/qemu-i486/src/Makefile # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/qemu-i486/src/qemui486_internal.h b/configs/qemu-i486/src/qemui486_internal.h index b6a2fea487fc2762ceef0c16d0974208eb36e716..6a0466149b95af37f0fa7e3cec52484b3f65e962 100644 --- a/configs/qemu-i486/src/qemui486_internal.h +++ b/configs/qemu-i486/src/qemui486_internal.h @@ -1,69 +1,69 @@ -/************************************************************************************ - * configs/qemu-i486/src/qemui486_internal.h - * arch/x86/src/board/qemui486_internal.n - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef _CONFIGS_QEMU_I486_SRC_QEMUI486_INTERNAL_H -#define _CONFIGS_QEMU_I486_SRC_QEMUI486_INTERNAL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* GPIO Pin Definitions *************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ASSEMBLY__ */ -#endif /* _CONFIGS_QEMU_I486_SRC_QEMUI486_INTERNAL_H */ - +/************************************************************************************ + * configs/qemu-i486/src/qemui486_internal.h + * arch/x86/src/board/qemui486_internal.n + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef _CONFIGS_QEMU_I486_SRC_QEMUI486_INTERNAL_H +#define _CONFIGS_QEMU_I486_SRC_QEMUI486_INTERNAL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* GPIO Pin Definitions *************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ASSEMBLY__ */ +#endif /* _CONFIGS_QEMU_I486_SRC_QEMUI486_INTERNAL_H */ + diff --git a/configs/qemu-i486/src/up_boot.c b/configs/qemu-i486/src/up_boot.c index a3081bdf778abbaee314535300ccd15f1f237f93..bd76469921f3096875135b9bf099c4403b95d9a2 100644 --- a/configs/qemu-i486/src/up_boot.c +++ b/configs/qemu-i486/src/up_boot.c @@ -1,82 +1,82 @@ -/************************************************************************************ - * configs/qemu-i486/src/up_boot.c - * arch/x86/src/board/up_boot.c - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include - -#include - -#include "up_arch.h" -#include "up_internal.h" - -#include "qemu_internal.h" -#include "qemui486_internal.h" - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: up_boardinitialize - * - * Description: - * All x86 architectures must provide the following entry point. This entry point - * is called early in the intitialization -- after all memory has been configured - * and mapped but before any devices have been initialized. - * - ************************************************************************************/ - -void up_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - up_ledinit(); -#endif -} +/************************************************************************************ + * configs/qemu-i486/src/up_boot.c + * arch/x86/src/board/up_boot.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "qemu_internal.h" +#include "qemui486_internal.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: up_boardinitialize + * + * Description: + * All x86 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void up_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + up_ledinit(); +#endif +} diff --git a/configs/rgmp/arm/default/Make.defs b/configs/rgmp/arm/default/Make.defs index 981872363c8c9f537104bf4b8b125de6319431b1..fdb39e6d617ca35f89ef4eac47f1960ddb64c452 100644 --- a/configs/rgmp/arm/default/Make.defs +++ b/configs/rgmp/arm/default/Make.defs @@ -4,7 +4,7 @@ # Copyright (C) 2011 Yu Qiang. All rights reserved. # Copyright (C) 2011 Gregory Nutt. All rights reserved. # Authors: Yu Qiang -# Gregory Nutt +# Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/rgmp/arm/default/appconfig b/configs/rgmp/arm/default/appconfig index e1397db204f0b6d4de91322d7d33e526c707897f..c57f8696b4f2a6f94d77e43de1cc95a85310b345 100644 --- a/configs/rgmp/arm/default/appconfig +++ b/configs/rgmp/arm/default/appconfig @@ -2,7 +2,7 @@ # configs/sim/default/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/rgmp/arm/default/defconfig b/configs/rgmp/arm/default/defconfig index a44a7505621565349f7729a19659acd2e3e33e4a..d722dd5e77758c6549c06178de0c9bfc67ecc9fa 100644 --- a/configs/rgmp/arm/default/defconfig +++ b/configs/rgmp/arm/default/defconfig @@ -4,7 +4,7 @@ # Copyright (C) 2011 Yu Qiang. All rights reserved. # Copyright (C) 2011 Gregory Nutt. All rights reserved. # Authors: Yu Qiang -# Gregory Nutt +# Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/rgmp/arm/default/setenv.sh b/configs/rgmp/arm/default/setenv.sh index a6a533e477cc29970cdc716f5fb7c581020b9dd8..bfb02549bd4817af97a105e83286aff6683c57af 100644 --- a/configs/rgmp/arm/default/setenv.sh +++ b/configs/rgmp/arm/default/setenv.sh @@ -4,7 +4,7 @@ # Copyright (C) 2011 Yu Qiang. All rights reserved. # Copyright (C) 2011 Gregory Nutt. All rights reserved. # Authors: Yu Qiang -# Gregory Nutt +# Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/rgmp/arm/nsh/Make.defs b/configs/rgmp/arm/nsh/Make.defs index 8ee0aad634d5e8b0ad1a61401acdbb50d4458483..3e97c6153c55bfd649d7f510dce4d3b3caa6d0db 100644 --- a/configs/rgmp/arm/nsh/Make.defs +++ b/configs/rgmp/arm/nsh/Make.defs @@ -4,7 +4,7 @@ # Copyright (C) 2011 Yu Qiang. All rights reserved. # Copyright (C) 2011 Gregory Nutt. All rights reserved. # Authors: Yu Qiang -# Gregory Nutt +# Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/rgmp/arm/nsh/appconfig b/configs/rgmp/arm/nsh/appconfig index e5220a258ee2cd93c91f7ce2a532cd12531568f8..b5e5d0203f81a34d407ae84de0c0913ea44a42b7 100644 --- a/configs/rgmp/arm/nsh/appconfig +++ b/configs/rgmp/arm/nsh/appconfig @@ -2,7 +2,7 @@ # configs/rgmp/nsh/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/rgmp/arm/nsh/defconfig b/configs/rgmp/arm/nsh/defconfig index 23d2f43167b1528a16b4afde1e2378e22e48d3f7..279437d4779569faf74afd6d9eaf0bf16792a8b4 100644 --- a/configs/rgmp/arm/nsh/defconfig +++ b/configs/rgmp/arm/nsh/defconfig @@ -4,7 +4,7 @@ # Copyright (C) 2011 Yu Qiang. All rights reserved. # Copyright (C) 2011 Gregory Nutt. All rights reserved. # Authors: Yu Qiang -# Gregory Nutt +# Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/rgmp/arm/nsh/setenv.sh b/configs/rgmp/arm/nsh/setenv.sh index 6caf8de84b4aca20386ba1521b166b0c570feeb5..b2180473be88bd929e3b09fd39ed6b7574196298 100644 --- a/configs/rgmp/arm/nsh/setenv.sh +++ b/configs/rgmp/arm/nsh/setenv.sh @@ -4,7 +4,7 @@ # Copyright (C) 2011 Yu Qiang. All rights reserved. # Copyright (C) 2011 Gregory Nutt. All rights reserved. # Authors: Yu Qiang -# Gregory Nutt +# Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/rgmp/x86/default/Make.defs b/configs/rgmp/x86/default/Make.defs index 9f970a19808fe237a747065cc2939f726976693b..e69ed7078552bbb68808551a0de39d7454613694 100644 --- a/configs/rgmp/x86/default/Make.defs +++ b/configs/rgmp/x86/default/Make.defs @@ -4,7 +4,7 @@ # Copyright (C) 2011 Yu Qiang. All rights reserved. # Copyright (C) 2011 Gregory Nutt. All rights reserved. # Authors: Yu Qiang -# Gregory Nutt +# Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/rgmp/x86/default/appconfig b/configs/rgmp/x86/default/appconfig index e1397db204f0b6d4de91322d7d33e526c707897f..c57f8696b4f2a6f94d77e43de1cc95a85310b345 100644 --- a/configs/rgmp/x86/default/appconfig +++ b/configs/rgmp/x86/default/appconfig @@ -2,7 +2,7 @@ # configs/sim/default/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/rgmp/x86/default/defconfig b/configs/rgmp/x86/default/defconfig index 6ecf662a9032e562b4c069a15fbf106cca6d5cde..4e37d90922a67fd99825ae374c1ff5e0cf0b66d6 100644 --- a/configs/rgmp/x86/default/defconfig +++ b/configs/rgmp/x86/default/defconfig @@ -4,7 +4,7 @@ # Copyright (C) 2011 Yu Qiang. All rights reserved. # Copyright (C) 2011 Gregory Nutt. All rights reserved. # Authors: Yu Qiang -# Gregory Nutt +# Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/rgmp/x86/default/setenv.sh b/configs/rgmp/x86/default/setenv.sh index a6a533e477cc29970cdc716f5fb7c581020b9dd8..bfb02549bd4817af97a105e83286aff6683c57af 100644 --- a/configs/rgmp/x86/default/setenv.sh +++ b/configs/rgmp/x86/default/setenv.sh @@ -4,7 +4,7 @@ # Copyright (C) 2011 Yu Qiang. All rights reserved. # Copyright (C) 2011 Gregory Nutt. All rights reserved. # Authors: Yu Qiang -# Gregory Nutt +# Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/rgmp/x86/nsh/Make.defs b/configs/rgmp/x86/nsh/Make.defs index 22ad89da9859cfce8524abe3b44592e8d90487c6..8d1bde092f2b0579acb8a12bc803f6d62d456892 100644 --- a/configs/rgmp/x86/nsh/Make.defs +++ b/configs/rgmp/x86/nsh/Make.defs @@ -4,7 +4,7 @@ # Copyright (C) 2011 Yu Qiang. All rights reserved. # Copyright (C) 2011 Gregory Nutt. All rights reserved. # Authors: Yu Qiang -# Gregory Nutt +# Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/rgmp/x86/nsh/appconfig b/configs/rgmp/x86/nsh/appconfig index e5220a258ee2cd93c91f7ce2a532cd12531568f8..b5e5d0203f81a34d407ae84de0c0913ea44a42b7 100644 --- a/configs/rgmp/x86/nsh/appconfig +++ b/configs/rgmp/x86/nsh/appconfig @@ -2,7 +2,7 @@ # configs/rgmp/nsh/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/rgmp/x86/nsh/defconfig b/configs/rgmp/x86/nsh/defconfig index 9c10ec92048983f81c826f2113d888754b117e85..363ef609da0820a776ad6501feaf1f33eff8e1bc 100644 --- a/configs/rgmp/x86/nsh/defconfig +++ b/configs/rgmp/x86/nsh/defconfig @@ -4,7 +4,7 @@ # Copyright (C) 2011 Yu Qiang. All rights reserved. # Copyright (C) 2011 Gregory Nutt. All rights reserved. # Authors: Yu Qiang -# Gregory Nutt +# Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/rgmp/x86/nsh/setenv.sh b/configs/rgmp/x86/nsh/setenv.sh index 6caf8de84b4aca20386ba1521b166b0c570feeb5..b2180473be88bd929e3b09fd39ed6b7574196298 100644 --- a/configs/rgmp/x86/nsh/setenv.sh +++ b/configs/rgmp/x86/nsh/setenv.sh @@ -4,7 +4,7 @@ # Copyright (C) 2011 Yu Qiang. All rights reserved. # Copyright (C) 2011 Gregory Nutt. All rights reserved. # Authors: Yu Qiang -# Gregory Nutt +# Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/kernel/Makefile b/configs/sam3u-ek/kernel/Makefile index 64b53f2f058b14025826e89abf6765a7e7406aa0..24934c4794727e534a26e02962246e63a10f8076 100755 --- a/configs/sam3u-ek/kernel/Makefile +++ b/configs/sam3u-ek/kernel/Makefile @@ -2,7 +2,7 @@ # configs/sam3u-ek/kernel/Makefile # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/kernel/kernel.ld b/configs/sam3u-ek/kernel/kernel.ld index 8b0ea0244cfbe10f612042c9cb0410dcd37015e4..9388bf88c26aefba5b8941ce35b473af3a714359 100644 --- a/configs/sam3u-ek/kernel/kernel.ld +++ b/configs/sam3u-ek/kernel/kernel.ld @@ -2,7 +2,7 @@ * configs/sam3u-ek/kernal/kernel.ld * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/knsh/Make.defs b/configs/sam3u-ek/knsh/Make.defs index 16a292c29581bbb5cf68a8d0fc509359da9735c6..313d15b52047d924efaa91a8698398a647c12922 100755 --- a/configs/sam3u-ek/knsh/Make.defs +++ b/configs/sam3u-ek/knsh/Make.defs @@ -2,7 +2,7 @@ # configs/sam3u-ek/knsh/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/knsh/defconfig b/configs/sam3u-ek/knsh/defconfig index 6110732e4d7770774f33fb61fd91b2d1a130d54f..06b93cc13c7e2be77c4300e364adb66e1596aa2e 100755 --- a/configs/sam3u-ek/knsh/defconfig +++ b/configs/sam3u-ek/knsh/defconfig @@ -2,7 +2,7 @@ # configs/sam3u-ek/knsh/defconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/knsh/ld.script b/configs/sam3u-ek/knsh/ld.script index c3a31090c2150f086ef95035fed533b0dc4a9d5a..34c4fbb3220ed63b4b77b5a6392b301d446ffd9a 100755 --- a/configs/sam3u-ek/knsh/ld.script +++ b/configs/sam3u-ek/knsh/ld.script @@ -2,7 +2,7 @@ * configs/sam3u-ek/knsh/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/knsh/setenv.sh b/configs/sam3u-ek/knsh/setenv.sh index 14969737d05f579c96ec4be701f120cf4b0b9139..3b27c3d9f98bdd4697dd46d433dc260b8d276f96 100755 --- a/configs/sam3u-ek/knsh/setenv.sh +++ b/configs/sam3u-ek/knsh/setenv.sh @@ -2,7 +2,7 @@ # configs/sam3u-ek/knsh/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/nsh/Make.defs b/configs/sam3u-ek/nsh/Make.defs index 467e8298f4aab3cb4518fa8c74cd3c846de6ea04..ad48c1d8286e14d2847d46d61065a0b90efd19cf 100755 --- a/configs/sam3u-ek/nsh/Make.defs +++ b/configs/sam3u-ek/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/sam3u-ek/nsh/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/nsh/defconfig b/configs/sam3u-ek/nsh/defconfig index ba5b78b48b000d242804f46ae437f10f5d56fd9c..a336861f5897f60e20045cd03b72eed12aa04343 100755 --- a/configs/sam3u-ek/nsh/defconfig +++ b/configs/sam3u-ek/nsh/defconfig @@ -2,7 +2,7 @@ # configs/sam3u-ek/nsh/defconfig # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/nsh/ld.script b/configs/sam3u-ek/nsh/ld.script index 72aa4de3e7505d4ab4c85a89b0cf143c9c3edbe2..94ae47403385bd375b612ecf9c2e86b7be9ed8a7 100755 --- a/configs/sam3u-ek/nsh/ld.script +++ b/configs/sam3u-ek/nsh/ld.script @@ -2,7 +2,7 @@ * configs/sam3u-ek/nsh/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/nsh/setenv.sh b/configs/sam3u-ek/nsh/setenv.sh index d9f9e136e4f30f6701b7c33075f5dc857ddadfff..3f4e60221c5f9244819cffca4c2117f8cceba950 100755 --- a/configs/sam3u-ek/nsh/setenv.sh +++ b/configs/sam3u-ek/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/sam3u-ek/nsh/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/nx/Make.defs b/configs/sam3u-ek/nx/Make.defs index a4eb8887599507913a718519d3c6d5491d725c08..119e4d321ba81fbf5ad59471a541a55d5e43ad84 100755 --- a/configs/sam3u-ek/nx/Make.defs +++ b/configs/sam3u-ek/nx/Make.defs @@ -2,7 +2,7 @@ # configs/sam3u-ek/nx/Make.defs # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/nx/appconfig b/configs/sam3u-ek/nx/appconfig index 8c5e733743318a6a2071a24f913ef1219bc1824d..a5ea3cccc4e5bcd31a99f100d3a22e229f47ef5c 100644 --- a/configs/sam3u-ek/nx/appconfig +++ b/configs/sam3u-ek/nx/appconfig @@ -2,7 +2,7 @@ # configs/sam3u-ek/nx/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/nx/defconfig b/configs/sam3u-ek/nx/defconfig index 377d3ce1d9f32b030bed9e0a1d4aeb90300d75fa..5bf51a0fbbd34021c0424b5fd81c644891463669 100755 --- a/configs/sam3u-ek/nx/defconfig +++ b/configs/sam3u-ek/nx/defconfig @@ -2,7 +2,7 @@ # configs/sam3u-ek/nx/defconfig # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/nx/ld.script b/configs/sam3u-ek/nx/ld.script index 8d2c39cdb2caec32d33e3ac2cfc6707e657442f8..56ae5d6a4effd45ff6c34417a02e7ad23b9b1267 100755 --- a/configs/sam3u-ek/nx/ld.script +++ b/configs/sam3u-ek/nx/ld.script @@ -2,7 +2,7 @@ * configs/sam3u-ek/nx/ld.script * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/nx/setenv.sh b/configs/sam3u-ek/nx/setenv.sh index 28c6f48666c610bb3e80cb943302610665632a48..a7e9efc843781c839fe3321143cb8d0d08aa09e5 100755 --- a/configs/sam3u-ek/nx/setenv.sh +++ b/configs/sam3u-ek/nx/setenv.sh @@ -2,7 +2,7 @@ # configs/sam3u-ek/nx/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/ostest/Make.defs b/configs/sam3u-ek/ostest/Make.defs index dc8bfca28348c8c46a5cc583914288afb6c1c36b..79ff50e140920b1b47e41dac2835ecc3e20f24cb 100755 --- a/configs/sam3u-ek/ostest/Make.defs +++ b/configs/sam3u-ek/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/sam3u-ek/ostest/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/ostest/appconfig b/configs/sam3u-ek/ostest/appconfig index b46e563e57102741a89b3d3b70df94b39b0f665a..687a5c13fcdec297386d6df1d7e0f5b95bf66c24 100644 --- a/configs/sam3u-ek/ostest/appconfig +++ b/configs/sam3u-ek/ostest/appconfig @@ -2,7 +2,7 @@ # configs/sam3u-ek/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/ostest/defconfig b/configs/sam3u-ek/ostest/defconfig index a18c10ec23ed30815d4ded47da63fcbee126a1fc..2757531f02f5b5d2c04ebc3336438dd388a31e76 100755 --- a/configs/sam3u-ek/ostest/defconfig +++ b/configs/sam3u-ek/ostest/defconfig @@ -2,7 +2,7 @@ # configs/sam3u-ek/ostest/defconfig # # Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/ostest/ld.script b/configs/sam3u-ek/ostest/ld.script index b447ef89f8511a8c046abc308f8397d5996663d9..70fd611e7446a21fed67a07ebce5311e384b1276 100755 --- a/configs/sam3u-ek/ostest/ld.script +++ b/configs/sam3u-ek/ostest/ld.script @@ -2,7 +2,7 @@ * configs/sam3u-ek/ostest/ld.script * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/ostest/setenv.sh b/configs/sam3u-ek/ostest/setenv.sh index 8a13a10c2392b6a625739663cba9e40ff5727f91..06d5eb5473385376a5050051b4f53a0a0719ecea 100755 --- a/configs/sam3u-ek/ostest/setenv.sh +++ b/configs/sam3u-ek/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/sam3u-ek/ostest/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/src/Makefile b/configs/sam3u-ek/src/Makefile index 61826cc4a2a80604936472299c7511412da926d4..193be03d029e0619a9fd5fe131871faf63a4c976 100644 --- a/configs/sam3u-ek/src/Makefile +++ b/configs/sam3u-ek/src/Makefile @@ -2,7 +2,7 @@ # configs/sam3u-ek/src/Makefile # # Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/src/up_buttons.c b/configs/sam3u-ek/src/up_buttons.c index f56a685f803a2749b6400951756bb5a66533d0ec..a4b8e0fd7b1907d0492c63086cb36897fa456f08 100644 --- a/configs/sam3u-ek/src/up_buttons.c +++ b/configs/sam3u-ek/src/up_buttons.c @@ -2,7 +2,7 @@ * configs/sam3u-ek/src/up_leds.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/src/up_lcd.c b/configs/sam3u-ek/src/up_lcd.c index 22cbeca88d816991702844953bd4e7ea831117a4..de897ab9f8aa7f3aafcc6454bd8494ec2c4fbd48 100644 --- a/configs/sam3u-ek/src/up_lcd.c +++ b/configs/sam3u-ek/src/up_lcd.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_lcd.c * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/src/up_leds.c b/configs/sam3u-ek/src/up_leds.c index c75896a364c0356cc3bc9bc4dadefd6753589085..28a2cead545d55b45fa074f03419c85189a644ef 100644 --- a/configs/sam3u-ek/src/up_leds.c +++ b/configs/sam3u-ek/src/up_leds.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_leds.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/src/up_mmcsd.c b/configs/sam3u-ek/src/up_mmcsd.c index 2f19c9cede3f62dd47144d56ad85f0fafb8d6bd7..bfa4ce4a75532a35210205844a1f9d53637d2097 100644 --- a/configs/sam3u-ek/src/up_mmcsd.c +++ b/configs/sam3u-ek/src/up_mmcsd.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_mmcsd.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/src/up_nsh.c b/configs/sam3u-ek/src/up_nsh.c index 5c8bf022d0b8ac58f5718692f7008e64601b27c6..e8c0df87be404f5d9e7e751e25963c3a9d011db3 100644 --- a/configs/sam3u-ek/src/up_nsh.c +++ b/configs/sam3u-ek/src/up_nsh.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_nsh.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/src/up_usbdev.c b/configs/sam3u-ek/src/up_usbdev.c index 9d97d65b550f700e7dcb5ebade1d3a6c183a73bf..0fc4a61ec4d45620a82c589dd62f2eb4db859ab0 100644 --- a/configs/sam3u-ek/src/up_usbdev.c +++ b/configs/sam3u-ek/src/up_usbdev.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_usbdev.c * * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/src/up_usbmsc.c b/configs/sam3u-ek/src/up_usbmsc.c index 8f2e4b254dcbade6514c027bce7d3612979da913..7e04ee04a9b3f95a8e164116f751463fe074031b 100644 --- a/configs/sam3u-ek/src/up_usbmsc.c +++ b/configs/sam3u-ek/src/up_usbmsc.c @@ -2,7 +2,7 @@ * configs/sam3u-ek/src/up_usbmsc.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Configure and register the SAM3U MMC/SD SDIO block driver. * diff --git a/configs/sam3u-ek/touchscreen/Make.defs b/configs/sam3u-ek/touchscreen/Make.defs index 07ba9085d68310f1774181631032398b866348b5..aa1277da4398eca9818ec600d5707e4e2fd5cbc5 100755 --- a/configs/sam3u-ek/touchscreen/Make.defs +++ b/configs/sam3u-ek/touchscreen/Make.defs @@ -2,7 +2,7 @@ # configs/sam3u-ek/touchscreen/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/touchscreen/ld.script b/configs/sam3u-ek/touchscreen/ld.script index 91b0e4b31439dbfd487490a647ca74f2c87a4d7d..dd30648a2834f138ff67bf30c2f99096b014f3df 100755 --- a/configs/sam3u-ek/touchscreen/ld.script +++ b/configs/sam3u-ek/touchscreen/ld.script @@ -2,7 +2,7 @@ * configs/sam3u-ek/touchscreen/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/sam3u-ek/touchscreen/setenv.sh b/configs/sam3u-ek/touchscreen/setenv.sh index 59ffbe6edcb49ed58f6dd86af1f737fb305e9b23..d5af12280f7a23a50b21ab5afd7ca511b23232cf 100755 --- a/configs/sam3u-ek/touchscreen/setenv.sh +++ b/configs/sam3u-ek/touchscreen/setenv.sh @@ -2,7 +2,7 @@ # configs/sam3u-ek/toolchain/setenv.sh # # Copyright (C) 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/mount/appconfig b/configs/sim/mount/appconfig index 47fb2cabc8a580aed83b072011630e38a60593cb..ca9cf3df44e5030f85007d20cbf1d87b27e53d3d 100644 --- a/configs/sim/mount/appconfig +++ b/configs/sim/mount/appconfig @@ -2,7 +2,7 @@ # configs/sim/mount/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/mount/defconfig b/configs/sim/mount/defconfig index 3871fe3306b1427c53b60c02cab22128feab2263..f5d28054fc4ed8f249d45f4a73296e20a2cd2433 100644 --- a/configs/sim/mount/defconfig +++ b/configs/sim/mount/defconfig @@ -2,7 +2,7 @@ # sim/mount/defconfig # # Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/mount/setenv.sh b/configs/sim/mount/setenv.sh index cb28f8df79ed4e481e9e821a29cbbcfd17cf97af..318e1628e5ab56034e9fdff588af0d337ea1a0de 100755 --- a/configs/sim/mount/setenv.sh +++ b/configs/sim/mount/setenv.sh @@ -2,7 +2,7 @@ # sim/setenv.sh # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/nettest/appconfig b/configs/sim/nettest/appconfig index a123273d7761747bef55bc29e3dde85e16c21c20..ce5961c146dbc727448833798688b9e73513639d 100644 --- a/configs/sim/nettest/appconfig +++ b/configs/sim/nettest/appconfig @@ -2,7 +2,7 @@ # configs/sim/nettest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/nettest/defconfig b/configs/sim/nettest/defconfig index 5965f02d82daf0271299eb9e287ee026bb352cd8..83de44c368c1a0498a5394b8eb53d9b8fa85b94c 100644 --- a/configs/sim/nettest/defconfig +++ b/configs/sim/nettest/defconfig @@ -2,7 +2,7 @@ # configs/sim/nettest/defconfig # # Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/nettest/setenv.sh b/configs/sim/nettest/setenv.sh index 9b3df2015b096d5afc65e04dfe4046dcf8c7441c..273e418ee12b8b6209634e7a347835ba26d958b0 100755 --- a/configs/sim/nettest/setenv.sh +++ b/configs/sim/nettest/setenv.sh @@ -2,7 +2,7 @@ # sim/setenv.sh # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/nsh/setenv.sh b/configs/sim/nsh/setenv.sh index 006beb5e2288b0f611f0dd2708dceb1f0fcf0217..c629c5a1ec18fffcc59939deb48afcdd1aca22ce 100755 --- a/configs/sim/nsh/setenv.sh +++ b/configs/sim/nsh/setenv.sh @@ -2,7 +2,7 @@ # sim/nsh/setenv.sh # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/nx/setenv.sh b/configs/sim/nx/setenv.sh index 6a5a7e6c098820c2432be66ffa7bba8d80da9c8d..764d2a8be7238820e4106c9878e6cec02a98497b 100755 --- a/configs/sim/nx/setenv.sh +++ b/configs/sim/nx/setenv.sh @@ -2,7 +2,7 @@ # sim/nx/setenv.sh # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/nx11/setenv.sh b/configs/sim/nx11/setenv.sh index dd51ecec2558cf5f6dd2ebc5928d046ab1128285..a9371a9d230a76b364e134eb64b8687d4985e600 100755 --- a/configs/sim/nx11/setenv.sh +++ b/configs/sim/nx11/setenv.sh @@ -2,7 +2,7 @@ # sim/nx11/setenv.sh # # Copyright (C) 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/nxffs/appconfig b/configs/sim/nxffs/appconfig index 8170a0edd8510f10f73a87354a6a8311d9fb9f97..6eb93ac775bd83ddd98c852ab111c2e340942a61 100644 --- a/configs/sim/nxffs/appconfig +++ b/configs/sim/nxffs/appconfig @@ -2,7 +2,7 @@ # configs/sim/nxffs/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/nxffs/defconfig b/configs/sim/nxffs/defconfig index 6b40cf3e4cae14f006f50694266b762026837684..22746a2f60117a1971f9bcd5dd76e57d2e85e10e 100644 --- a/configs/sim/nxffs/defconfig +++ b/configs/sim/nxffs/defconfig @@ -2,7 +2,7 @@ # configs/sim/nxffs/defconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/nxffs/setenv.sh b/configs/sim/nxffs/setenv.sh index 2733778439b2be9358b4f19b9ee5591107e4b454..3aa03bc9887e89db686b843698e0fb6650acecaa 100755 --- a/configs/sim/nxffs/setenv.sh +++ b/configs/sim/nxffs/setenv.sh @@ -2,7 +2,7 @@ # confisgs/sim/nxffs/setenv.sh # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/ostest/appconfig b/configs/sim/ostest/appconfig index 77707484ea75a851a92a99ec99e191891adde32b..0827435048fcf2007ba87f3e361b6b2757f7c365 100644 --- a/configs/sim/ostest/appconfig +++ b/configs/sim/ostest/appconfig @@ -2,7 +2,7 @@ # configs/sim/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/ostest/defconfig b/configs/sim/ostest/defconfig index 91316af6b930d7ff26aada8329fc327291e4836e..92c696dc611d4e022bedabd008c1aa26bf9a6788 100644 --- a/configs/sim/ostest/defconfig +++ b/configs/sim/ostest/defconfig @@ -2,7 +2,7 @@ # configs/sim/ostest/defconfig # # Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/ostest/setenv.sh b/configs/sim/ostest/setenv.sh index 9b3df2015b096d5afc65e04dfe4046dcf8c7441c..273e418ee12b8b6209634e7a347835ba26d958b0 100755 --- a/configs/sim/ostest/setenv.sh +++ b/configs/sim/ostest/setenv.sh @@ -2,7 +2,7 @@ # sim/setenv.sh # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/pashello/appconfig b/configs/sim/pashello/appconfig index d4adbcce11ac1634afae5d802a3a0be61a57411d..85af74b20d5a6ff8b3894b96dc963adeb6433613 100644 --- a/configs/sim/pashello/appconfig +++ b/configs/sim/pashello/appconfig @@ -2,7 +2,7 @@ # configs/sim/pashello/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/pashello/defconfig b/configs/sim/pashello/defconfig index a5c4a6f45d49deb667f8d647d057d0559ceac1bb..57530d3bbcd1c31c2bd23db94c73dbc87c048149 100644 --- a/configs/sim/pashello/defconfig +++ b/configs/sim/pashello/defconfig @@ -2,7 +2,7 @@ # configs/sim/pashello/defconfig # # Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/pashello/setenv.sh b/configs/sim/pashello/setenv.sh index 9b3df2015b096d5afc65e04dfe4046dcf8c7441c..273e418ee12b8b6209634e7a347835ba26d958b0 100755 --- a/configs/sim/pashello/setenv.sh +++ b/configs/sim/pashello/setenv.sh @@ -2,7 +2,7 @@ # sim/setenv.sh # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/src/Makefile b/configs/sim/src/Makefile index 59494276596db9c10a0fd7699370b376a955a302..69e2ca9e7184d47283d28b16aaa7d8dc4f70ae01 100644 --- a/configs/sim/src/Makefile +++ b/configs/sim/src/Makefile @@ -2,7 +2,7 @@ # configs/sim/src/Makefile # # Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/src/up_touchscreen.c b/configs/sim/src/up_touchscreen.c index ef3686288479a1f5c1b8b5d2e454cc4a1ac3a6f8..c951c5c690e7d5020595cd701267bf2d6d2ea20c 100644 --- a/configs/sim/src/up_touchscreen.c +++ b/configs/sim/src/up_touchscreen.c @@ -2,7 +2,7 @@ * config/sim/src/up_touchscreen.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/sim/touchscreen/appconfig b/configs/sim/touchscreen/appconfig index 5dc25b81a5fc95acdc64a240b8db602e1afc816d..4bcbabeb43f28b0b8059332306ceaef600153d20 100644 --- a/configs/sim/touchscreen/appconfig +++ b/configs/sim/touchscreen/appconfig @@ -2,7 +2,7 @@ # configs/sim/touchscreen/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/touchscreen/defconfig b/configs/sim/touchscreen/defconfig index a78bbcc5033384b3a91c1ee863392410cf81612b..b9630c8e2c89c0d0d9d10f5182cdfbc6c7e5ec15 100644 --- a/configs/sim/touchscreen/defconfig +++ b/configs/sim/touchscreen/defconfig @@ -2,7 +2,7 @@ # sim/touchscreen/defconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sim/touchscreen/setenv.sh b/configs/sim/touchscreen/setenv.sh index ffaeb5126d17e872523d83d114f1e2af16a9b671..4cc3bba57690761980bacc19d59a36d07978c046 100755 --- a/configs/sim/touchscreen/setenv.sh +++ b/configs/sim/touchscreen/setenv.sh @@ -2,7 +2,7 @@ # sim/touchscreen/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/skp16c26/include/board.h b/configs/skp16c26/include/board.h index 32a08f2edecd615a817da35c4df0484efb509f13..cf0a1c15beb1b9a3986ddfbbf862044c2b283dc3 100644 --- a/configs/skp16c26/include/board.h +++ b/configs/skp16c26/include/board.h @@ -3,7 +3,7 @@ * arch/board/board.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/skp16c26/ostest/Make.defs b/configs/skp16c26/ostest/Make.defs index 22cee90f63fc6af78550599a542d527896311738..bad496656ca71f477b0a52976e082e16181b973c 100644 --- a/configs/skp16c26/ostest/Make.defs +++ b/configs/skp16c26/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/skp16c26/ostest/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/skp16c26/ostest/appconfig b/configs/skp16c26/ostest/appconfig index ad98de5db0d57e77e551fa85975bdba0e8a779ff..7475e5818016af9573857bdc80f95a4632de377a 100644 --- a/configs/skp16c26/ostest/appconfig +++ b/configs/skp16c26/ostest/appconfig @@ -2,7 +2,7 @@ # configs/skp16c26/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/skp16c26/ostest/defconfig b/configs/skp16c26/ostest/defconfig index fc7640ef85f27285f7f8dec759c777678243f236..91917f8f08edf9d843d49f3bb532d54905948d5f 100644 --- a/configs/skp16c26/ostest/defconfig +++ b/configs/skp16c26/ostest/defconfig @@ -2,7 +2,7 @@ # configs/skp16c26/ostest/defconfig # # Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/skp16c26/ostest/ld.script b/configs/skp16c26/ostest/ld.script index f94ae9a27a499afc2b707e4562a4667e4b497fb5..8ae1a8697d632eb6a293edd328fadaad21b72034 100644 --- a/configs/skp16c26/ostest/ld.script +++ b/configs/skp16c26/ostest/ld.script @@ -2,7 +2,7 @@ * configs/skp16c26/ostest/ld.script * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/skp16c26/ostest/setenv.sh b/configs/skp16c26/ostest/setenv.sh index a6fd82439a0a354f2a114be5bd9c0273ea5ee03f..a74258fb840a81229847409fbd98644c449a8808 100755 --- a/configs/skp16c26/ostest/setenv.sh +++ b/configs/skp16c26/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/skp16c26/ostest/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/skp16c26/src/Makefile b/configs/skp16c26/src/Makefile index 5a983a2f705cc5282cc177c9b642558fe4f006e7..483c24498882492d0f1c46ea5af6370830e64861 100644 --- a/configs/skp16c26/src/Makefile +++ b/configs/skp16c26/src/Makefile @@ -2,7 +2,7 @@ # configs/skp16c26/src/Makefile # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/skp16c26/src/skp16c26_internal.h b/configs/skp16c26/src/skp16c26_internal.h index 5d8f235f8011a801f1c1ebec9549f9f1f69b8f21..048292048d28eec0573b8de8bd8ede07b1f10aa7 100644 --- a/configs/skp16c26/src/skp16c26_internal.h +++ b/configs/skp16c26/src/skp16c26_internal.h @@ -2,7 +2,7 @@ * configs/skp16c26/src/scp16c26_internal.h * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/skp16c26/src/up_buttons.c b/configs/skp16c26/src/up_buttons.c index 828269a8e9b425efe2a59629d26f1231d0e30a41..a483aaeaa482792553966d7aa577f7fb4d490fb8 100644 --- a/configs/skp16c26/src/up_buttons.c +++ b/configs/skp16c26/src/up_buttons.c @@ -2,7 +2,7 @@ * configs/skp16c26/src/up_buttons.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/skp16c26/src/up_lcd.c b/configs/skp16c26/src/up_lcd.c index 197b670844546f0a0788fbc9a5726d62ad9a1623..a47f4af510c83d48ef7589072e2c479c0be22386 100644 --- a/configs/skp16c26/src/up_lcd.c +++ b/configs/skp16c26/src/up_lcd.c @@ -2,7 +2,7 @@ * configs/scp16c26/src/up_lcd.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/skp16c26/src/up_leds.c b/configs/skp16c26/src/up_leds.c index b64b8b7d0e9051a91a1605d7f95afbc6d0008443..024d8f143bcdfe1d66564fea4452c2a1a07c7912 100644 --- a/configs/skp16c26/src/up_leds.c +++ b/configs/skp16c26/src/up_leds.c @@ -2,7 +2,7 @@ * configs/scp16c26/src/up_leds.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/sure-pic32mx/ostest/Make.defs b/configs/sure-pic32mx/ostest/Make.defs index e0742562db6645ce1efd280f9656fe2670ddd29a..3a41786e4c63c266a927fb2ff1f45211e4af7501 100644 --- a/configs/sure-pic32mx/ostest/Make.defs +++ b/configs/sure-pic32mx/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/sure-pic32mx/ostest/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sure-pic32mx/ostest/appconfig b/configs/sure-pic32mx/ostest/appconfig index 2565d3b074727f3c51030bf729d2316d838323cd..3b96b3d6d66f35949ea6b464ec7d6f8beb7941b0 100644 --- a/configs/sure-pic32mx/ostest/appconfig +++ b/configs/sure-pic32mx/ostest/appconfig @@ -2,7 +2,7 @@ # configs/sure-pic32mx/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/sure-pic32mx/ostest/ld.script b/configs/sure-pic32mx/ostest/ld.script index 08bc50df1bdc330c60d333d9ad2f8ec3318c171e..7b5ffa3c4a5cca91cf424222bb846ad35a1aa880 100644 --- a/configs/sure-pic32mx/ostest/ld.script +++ b/configs/sure-pic32mx/ostest/ld.script @@ -2,7 +2,7 @@ * configs/sure-pic32mx/ostest/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/sure-pic32mx/src/up_boot.c b/configs/sure-pic32mx/src/up_boot.c index fe633abd4753d65d6068265def8f1b5a8131f361..2982cdbf41beed86cbda624c98ca95dce4311ecf 100644 --- a/configs/sure-pic32mx/src/up_boot.c +++ b/configs/sure-pic32mx/src/up_boot.c @@ -3,7 +3,7 @@ * arch/mips/src/board/up_boot.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/teensy/hello/appconfig b/configs/teensy/hello/appconfig index da49cbd292bdeb1bc971b24ef1276206aebd4417..c3440d8275d6380c84504f278ef871a2b1ef7517 100644 --- a/configs/teensy/hello/appconfig +++ b/configs/teensy/hello/appconfig @@ -2,7 +2,7 @@ # configs/teensy/hello/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/teensy/hello/defconfig b/configs/teensy/hello/defconfig index 5441e9005a0aac4328a4da62c40e80e87d463416..29c7194e3a5f812d0fe01256242b7a5afe76c6a1 100644 --- a/configs/teensy/hello/defconfig +++ b/configs/teensy/hello/defconfig @@ -2,7 +2,7 @@ # configs/teensy/hello/defconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/teensy/hello/ld.script b/configs/teensy/hello/ld.script index 791e96bfce1fd813ff586e2607129df2889e5f9a..2115c848f68de646904f8ad3e74c2d7f380241fa 100644 --- a/configs/teensy/hello/ld.script +++ b/configs/teensy/hello/ld.script @@ -2,7 +2,7 @@ * configs/teensy/hello/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/teensy/hello/setenv.sh b/configs/teensy/hello/setenv.sh index 35827ca177e31d8236d3a4c56a78fbd817cf2e88..d0100778ac8b24678d60fa68b14501e03fa9040f 100755 --- a/configs/teensy/hello/setenv.sh +++ b/configs/teensy/hello/setenv.sh @@ -2,7 +2,7 @@ # configs/teensy/hello/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/teensy/include/board.h b/configs/teensy/include/board.h index 9e9c1205f16227a1fac6da80409fb5e4fcbdcede..4fe6911181256bf95431e40544e6350c25409db0 100755 --- a/configs/teensy/include/board.h +++ b/configs/teensy/include/board.h @@ -3,7 +3,7 @@ * include/arch/board/board.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/teensy/nsh/ld.script b/configs/teensy/nsh/ld.script index 272b24ea8fa9db2a2bb5fb94221af826f40557b1..eaeccd9ef527daa5b52adc33bd9615750594cfb1 100755 --- a/configs/teensy/nsh/ld.script +++ b/configs/teensy/nsh/ld.script @@ -2,7 +2,7 @@ * configs/teensy/nsh/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/teensy/nsh/setenv.sh b/configs/teensy/nsh/setenv.sh index 9d232e53eea7a05e410ba6d46b5816ae536584ce..f0c035bba58bb73e942e0d5b815fdf37dc48f981 100755 --- a/configs/teensy/nsh/setenv.sh +++ b/configs/teensy/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/teensy/nsh/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/teensy/src/Makefile b/configs/teensy/src/Makefile index 36e887b74af83a39be49ad2929e24a0ab69029c8..6b68e63bbefbdbeb972d7973b39467fd6b34eeba 100644 --- a/configs/teensy/src/Makefile +++ b/configs/teensy/src/Makefile @@ -2,7 +2,7 @@ # configs/teensy/src/Makefile # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/teensy/src/teensy_internal.h b/configs/teensy/src/teensy_internal.h index c593c49ce0c43afbeea7f0abe033fd791b665144..f253b590f86c7e4abf883620d3d676047794ef96 100644 --- a/configs/teensy/src/teensy_internal.h +++ b/configs/teensy/src/teensy_internal.h @@ -1,101 +1,101 @@ -/**************************************************************************** - * configs/teensy/src/pcblogic-internal.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __CONFIGS_TEENSY_SRC_TEENSY_INTERNAL_H -#define __CONFIGS_TEENSY_SRC_TEENSY_INTERNAL_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-Processor Definitions - ****************************************************************************/ -/* Configuration ************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/************************************************************************************ - * Name: at90usb_spiinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Teensy++ 2.0 board. - * - ************************************************************************************/ - -#ifdef CONFIG_AVR_SPI -EXTERN void weak_function at90usb_spiinitialize(void); -#endif - -/************************************************************************************ - * Name: at90usb_ledinit - * - * Description: - * Configure on-board LEDs if LED support has been selected. - * - ************************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -EXTERN void at90usb_ledinit(void); -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __CONFIGS_TEENSY_SRC_TEENSY_INTERNAL_H */ +/**************************************************************************** + * configs/teensy/src/pcblogic-internal.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_TEENSY_SRC_TEENSY_INTERNAL_H +#define __CONFIGS_TEENSY_SRC_TEENSY_INTERNAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Name: at90usb_spiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Teensy++ 2.0 board. + * + ************************************************************************************/ + +#ifdef CONFIG_AVR_SPI +EXTERN void weak_function at90usb_spiinitialize(void); +#endif + +/************************************************************************************ + * Name: at90usb_ledinit + * + * Description: + * Configure on-board LEDs if LED support has been selected. + * + ************************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +EXTERN void at90usb_ledinit(void); +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_TEENSY_SRC_TEENSY_INTERNAL_H */ diff --git a/configs/teensy/src/up_boot.c b/configs/teensy/src/up_boot.c index ad054c7023a942f55e63652436160732be7968ee..7c881127243a6b3da0ddfc1974456cecde621cc3 100644 --- a/configs/teensy/src/up_boot.c +++ b/configs/teensy/src/up_boot.c @@ -3,7 +3,7 @@ * arch/mips/src/board/up_boot.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/teensy/src/up_leds.c b/configs/teensy/src/up_leds.c index 7aabae5c3d66c1c22cc7c3b0c8d9dc75b1410ec4..ce83b499926adc28a8f5de39410bd01c6d430ab9 100644 --- a/configs/teensy/src/up_leds.c +++ b/configs/teensy/src/up_leds.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_leds.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/teensy/src/up_spi.c b/configs/teensy/src/up_spi.c index e3284be0813483b405383d54c4afacfa821b53cd..a4eed983642eed2e0e469115b191c227c1e757a6 100644 --- a/configs/teensy/src/up_spi.c +++ b/configs/teensy/src/up_spi.c @@ -1,202 +1,202 @@ -/************************************************************************************ - * configs/teensy/src/up_spi.c - * arch/arm/src/board/up_spi.c - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "up_arch.h" -#include "chip.h" -#include "at90usb_internal.h" -#include "teensy_internal.h" - -#ifdef CONFIG_AVR_SPI - -/************************************************************************************ - * Definitions - ************************************************************************************/ -/* Teensy SPI Connection - * - * -- ---- -- ------------------------- ------- - * J2 NAME PIN NAME PAD - * -- ---- -- ------------------------- ------- - * 1 VIN -- Connected to USB +RV - * 2 GND -- Connected to USB GND - * 3 3V3 -- Not used --- - * 4 NC -- Not used - * 5 CS 10 (SS/PCINT0) PB0 Pad B0 - * 6 DI 12 (PDI/PCINT2/MOSI) PB2 Pad B2 - * 7 SCK 11 (PCINT1/SCLK) PB1 Pad B1 - * 8 DO 13 (PDO/PCINT3/MISO) PB3 Pad B3 - * 9 IRQ -- Not used --- - * 10 CD 14 (PCINT4/OC.2A) PB4 Pad B4 - * 11 WP 15 (PCINT5/OC.1A) PB5 Pad B5 - * -- ---- -- ------------------------- ------- - */ - -#define TEENSY_CS (1 << 0) -#define TEENSY_CD (1 << 4) -#define TEENSY_WP (1 << 5) - -/* The following enable debug output from this file (needs CONFIG_DEBUG too). - * - * CONFIG_SPI_DEBUG - Define to enable basic SSP debug - * CONFIG_SPI_VERBOSE - Define to enable verbose SSP debug - */ - -#ifdef CONFIG_SPI_DEBUG -# define sspdbg lldbg -# ifdef CONFIG_SPI_VERBOSE -# define sspvdbg lldbg -# else -# define sspvdbg(x...) -# endif -#else -# undef CONFIG_SPI_VERBOSE -# define sspdbg(x...) -# define sspvdbg(x...) -#endif - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: at90usb_spiinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the LPC1766-STK. - * - ************************************************************************************/ - -void weak_function at90usb_spiinitialize(void) -{ - /* The Teensy board has no dedicated SPI devices so we assume that SS is used - * for chip select: - * - * "When the SPI is configured as a Master (MSTR in SPCR is set), the user - * can determine the direction of the SS pin. If SS is configured as an - * output, the pin is a general output pin which does not affect the SPI - * system. ... - * - * "If SS is configured as an input, it must be held high to ensure Master - * SPI operation. If the SS pin is driven low by peripheral circuitry when - * the SPI is configured as a Master with the SS pin defined as an input, - * the SPI system interprets this as another master selecting the SPI ... - */ - - DDRB |= TEENSY_CS; /* B0 is an output */ - PORTB |= TEENSY_CS; /* Low de-selects */ - DDRB &= ~(TEENSY_CD | TEENSY_WP); /* B4 and B5 are inputs */ - PORTB |= (TEENSY_CD | TEENSY_WP); /* Pull high */ -} - -/************************************************************************************ - * Name: avr_spiselect and avr_spistatus - * - * Description: - * The external functions, avr_spiselect and avr_spistatus must be provided by - * board-specific logic. They are implementations of the select and status methods - * of the SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h). All - * other methods (including up_spiinitialize()) are provided by common AVR logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in avr_sspinitialize() to configure SPI chip select pins. - * 2. Provide avr_spiselect() and avr_spistatus() functions in your board-specific - * logic. These functions will perform chip selection and status operations - * in the way your board is configured. - * 3. Add a calls to at90usb_spiinitialize() in your low level application - * initialization logic - * 4. The handle returned by up_spiinitialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(), - * for example, will bind the SPI driver to the SPI MMC/SD driver). - * - ************************************************************************************/ - -void avr_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) -{ - sspdbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - - /* Assert/de-assert the CS pin to the card */ - - if (selected) - { - PORTB &= ~TEENSY_CS; - } - else - { - PORTB |= TEENSY_CS; - } -} - -uint8_t avr_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) -{ - uint8_t ret = 0; - uint8_t regval = PINB; - - /* Both the CD and WP pins are pull high by the AT90USB and will be - * grounded it a card is inserted or write protected. - */ - - if ((regval & TEENSY_CD) == 0) - { - ret |= SPI_STATUS_PRESENT; - } - - if ((regval & TEENSY_WP) == 0) - { - ret |= SPI_STATUS_WRPROTECTED; - } - - sspdbg("Returning %02x\n", ret); - return ret; -} - -#endif /* CONFIG_AVR_SPI */ +/************************************************************************************ + * configs/teensy/src/up_spi.c + * arch/arm/src/board/up_spi.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "chip.h" +#include "at90usb_internal.h" +#include "teensy_internal.h" + +#ifdef CONFIG_AVR_SPI + +/************************************************************************************ + * Definitions + ************************************************************************************/ +/* Teensy SPI Connection + * + * -- ---- -- ------------------------- ------- + * J2 NAME PIN NAME PAD + * -- ---- -- ------------------------- ------- + * 1 VIN -- Connected to USB +RV + * 2 GND -- Connected to USB GND + * 3 3V3 -- Not used --- + * 4 NC -- Not used + * 5 CS 10 (SS/PCINT0) PB0 Pad B0 + * 6 DI 12 (PDI/PCINT2/MOSI) PB2 Pad B2 + * 7 SCK 11 (PCINT1/SCLK) PB1 Pad B1 + * 8 DO 13 (PDO/PCINT3/MISO) PB3 Pad B3 + * 9 IRQ -- Not used --- + * 10 CD 14 (PCINT4/OC.2A) PB4 Pad B4 + * 11 WP 15 (PCINT5/OC.1A) PB5 Pad B5 + * -- ---- -- ------------------------- ------- + */ + +#define TEENSY_CS (1 << 0) +#define TEENSY_CD (1 << 4) +#define TEENSY_WP (1 << 5) + +/* The following enable debug output from this file (needs CONFIG_DEBUG too). + * + * CONFIG_SPI_DEBUG - Define to enable basic SSP debug + * CONFIG_SPI_VERBOSE - Define to enable verbose SSP debug + */ + +#ifdef CONFIG_SPI_DEBUG +# define sspdbg lldbg +# ifdef CONFIG_SPI_VERBOSE +# define sspvdbg lldbg +# else +# define sspvdbg(x...) +# endif +#else +# undef CONFIG_SPI_VERBOSE +# define sspdbg(x...) +# define sspvdbg(x...) +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: at90usb_spiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the LPC1766-STK. + * + ************************************************************************************/ + +void weak_function at90usb_spiinitialize(void) +{ + /* The Teensy board has no dedicated SPI devices so we assume that SS is used + * for chip select: + * + * "When the SPI is configured as a Master (MSTR in SPCR is set), the user + * can determine the direction of the SS pin. If SS is configured as an + * output, the pin is a general output pin which does not affect the SPI + * system. ... + * + * "If SS is configured as an input, it must be held high to ensure Master + * SPI operation. If the SS pin is driven low by peripheral circuitry when + * the SPI is configured as a Master with the SS pin defined as an input, + * the SPI system interprets this as another master selecting the SPI ... + */ + + DDRB |= TEENSY_CS; /* B0 is an output */ + PORTB |= TEENSY_CS; /* Low de-selects */ + DDRB &= ~(TEENSY_CD | TEENSY_WP); /* B4 and B5 are inputs */ + PORTB |= (TEENSY_CD | TEENSY_WP); /* Pull high */ +} + +/************************************************************************************ + * Name: avr_spiselect and avr_spistatus + * + * Description: + * The external functions, avr_spiselect and avr_spistatus must be provided by + * board-specific logic. They are implementations of the select and status methods + * of the SPI interface defined by struct spi_ops_s (see include/nuttx/spi.h). All + * other methods (including up_spiinitialize()) are provided by common AVR logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in avr_sspinitialize() to configure SPI chip select pins. + * 2. Provide avr_spiselect() and avr_spistatus() functions in your board-specific + * logic. These functions will perform chip selection and status operations + * in the way your board is configured. + * 3. Add a calls to at90usb_spiinitialize() in your low level application + * initialization logic + * 4. The handle returned by up_spiinitialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(), + * for example, will bind the SPI driver to the SPI MMC/SD driver). + * + ************************************************************************************/ + +void avr_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +{ + sspdbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + + /* Assert/de-assert the CS pin to the card */ + + if (selected) + { + PORTB &= ~TEENSY_CS; + } + else + { + PORTB |= TEENSY_CS; + } +} + +uint8_t avr_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ + uint8_t ret = 0; + uint8_t regval = PINB; + + /* Both the CD and WP pins are pull high by the AT90USB and will be + * grounded it a card is inserted or write protected. + */ + + if ((regval & TEENSY_CD) == 0) + { + ret |= SPI_STATUS_PRESENT; + } + + if ((regval & TEENSY_WP) == 0) + { + ret |= SPI_STATUS_WRPROTECTED; + } + + sspdbg("Returning %02x\n", ret); + return ret; +} + +#endif /* CONFIG_AVR_SPI */ diff --git a/configs/teensy/src/up_usbmsc.c b/configs/teensy/src/up_usbmsc.c index 7eb3307c66fd3ebb40590ed2da8f5c3b2175ec6b..fcf7fe2f56171c7ec5b10cf005bc9449eec1a4a8 100644 --- a/configs/teensy/src/up_usbmsc.c +++ b/configs/teensy/src/up_usbmsc.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_usbmsc.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Configure and register the AVR MMC/SD SPI block driver. * diff --git a/configs/teensy/usbstorage/appconfig b/configs/teensy/usbstorage/appconfig index 3f25250305dc4b35f7e1384d5868c9abbc450d92..76df13884bb22f66df122acf4a3fe0c49dc94a88 100644 --- a/configs/teensy/usbstorage/appconfig +++ b/configs/teensy/usbstorage/appconfig @@ -2,7 +2,7 @@ # configs/teensy/usbstorage/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/teensy/usbstorage/defconfig b/configs/teensy/usbstorage/defconfig index 42ec5fd1383aa7d5483a2aedf80145b00f2c27b4..a0f90666539d7c6d07c4545730dbbc261b42299d 100755 --- a/configs/teensy/usbstorage/defconfig +++ b/configs/teensy/usbstorage/defconfig @@ -2,7 +2,7 @@ # configs/teensy/usbstorage/defconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/teensy/usbstorage/ld.script b/configs/teensy/usbstorage/ld.script index 7a57ef66cd93b2fb2ba3795011e1f31f9551b992..54163f002a0fbe4bcf694c8884464219692c770d 100755 --- a/configs/teensy/usbstorage/ld.script +++ b/configs/teensy/usbstorage/ld.script @@ -2,7 +2,7 @@ * configs/teensy/usbstorage/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/teensy/usbstorage/setenv.sh b/configs/teensy/usbstorage/setenv.sh index 7cefcdaecab6f1eee8cea93df50da1361c44724c..a455f560a33d6f1094f85deacb48fe309a82f64c 100755 --- a/configs/teensy/usbstorage/setenv.sh +++ b/configs/teensy/usbstorage/setenv.sh @@ -2,7 +2,7 @@ # configs/teensy/usbstorage/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/include/board.h b/configs/twr-k60n512/include/board.h index 76039f7199c81d3d64052aa794faa7f6db9ccf95..ca060c654d1a4e9b58cb06afc5b57a81d1cd927a 100755 --- a/configs/twr-k60n512/include/board.h +++ b/configs/twr-k60n512/include/board.h @@ -3,7 +3,7 @@ * include/arch/board/board.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/nsh/Make.defs b/configs/twr-k60n512/nsh/Make.defs index 5ae6ca061e2175079404c1bebda5f3b38bcc901c..c055c9b45f512305aedff315b96ba97d6deac29d 100644 --- a/configs/twr-k60n512/nsh/Make.defs +++ b/configs/twr-k60n512/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/twr-k60n512/nsh/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/nsh/defconfig b/configs/twr-k60n512/nsh/defconfig index 16e33799d7702b0fa8ba6b83be3a8e85cb61b7dc..0f91b67214b8695391b9cd98a8e4b47e28632efc 100644 --- a/configs/twr-k60n512/nsh/defconfig +++ b/configs/twr-k60n512/nsh/defconfig @@ -2,7 +2,7 @@ # configs/twr-k60n512/nsh/defconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/nsh/ld.script b/configs/twr-k60n512/nsh/ld.script index fe6bd15501fe658f6ba29e2e1950fd6f7aa0af02..e8e5e7de15e80c2414e637766a7c66d83eb5c30d 100644 --- a/configs/twr-k60n512/nsh/ld.script +++ b/configs/twr-k60n512/nsh/ld.script @@ -2,7 +2,7 @@ * configs/twr-k60n512/nsh/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/nsh/setenv.sh b/configs/twr-k60n512/nsh/setenv.sh index 7acb0e7f601a5cffb65a66f281ae83834c109cc4..a780a15a7ded3b2a56a9fdcbc814f0aaef6d419b 100644 --- a/configs/twr-k60n512/nsh/setenv.sh +++ b/configs/twr-k60n512/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/twr-k60n512/nsh/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/ostest/Make.defs b/configs/twr-k60n512/ostest/Make.defs index e737d718990318c14300092294544cd79142f8c3..8c4a629bb23529503728d7cf3e42b08a142ec711 100644 --- a/configs/twr-k60n512/ostest/Make.defs +++ b/configs/twr-k60n512/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/twr-k60n512/ostest/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/ostest/appconfig b/configs/twr-k60n512/ostest/appconfig index efb1f2f3339efa3f2a4fae2e4476bb538d81d8f5..d1ec3edb262d174922db086c700c10fb62e5fbb4 100644 --- a/configs/twr-k60n512/ostest/appconfig +++ b/configs/twr-k60n512/ostest/appconfig @@ -2,7 +2,7 @@ # configs/twr-k60n512/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/ostest/defconfig b/configs/twr-k60n512/ostest/defconfig index af92a0c3ecd65ae1fc713b1efd24c4dc7713b436..461b795f1e0864dd157d7b96cb318b7ceda1cfcf 100644 --- a/configs/twr-k60n512/ostest/defconfig +++ b/configs/twr-k60n512/ostest/defconfig @@ -2,7 +2,7 @@ # configs/twr-k60n512/ostest/defconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/ostest/ld.script b/configs/twr-k60n512/ostest/ld.script index d7692e1d3884ffd71b3126c831a3b8ac3485d491..717a4574740889d1e70d16011f337ac1c48a83f3 100644 --- a/configs/twr-k60n512/ostest/ld.script +++ b/configs/twr-k60n512/ostest/ld.script @@ -2,7 +2,7 @@ * configs/twr-k60n512/ostest/ld.script * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/ostest/setenv.sh b/configs/twr-k60n512/ostest/setenv.sh index 6dedfbded766fbb5a2892d5011298b878fd0865c..86b6099dcda1099478d83c94a6af4fa1276d94ca 100644 --- a/configs/twr-k60n512/ostest/setenv.sh +++ b/configs/twr-k60n512/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/twr-k60n512/ostest/setenv.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/src/Makefile b/configs/twr-k60n512/src/Makefile index 18a9c118f7e0fd9afb2f5cf2a45af05234f7e975..6e43aa69a4a725909c42ffb9fdd392bd319ebb55 100644 --- a/configs/twr-k60n512/src/Makefile +++ b/configs/twr-k60n512/src/Makefile @@ -2,7 +2,7 @@ # configs/twr-k60n512/src/Makefile # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/src/twrk60-internal.h b/configs/twr-k60n512/src/twrk60-internal.h index df60daae46f9b81638ed2a84d0ffcb9789dafba6..9a8b16c9ca37486176b582ad58d9502f37eb7799 100644 --- a/configs/twr-k60n512/src/twrk60-internal.h +++ b/configs/twr-k60n512/src/twrk60-internal.h @@ -3,7 +3,7 @@ * arch/arm/src/board/twrk60-internal.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/src/up_boot.c b/configs/twr-k60n512/src/up_boot.c index d6cd382d167fbb3822a7db502e22ef67e19da9de..d811658c3ce6d83ccbf86e870f15421278c233a2 100644 --- a/configs/twr-k60n512/src/up_boot.c +++ b/configs/twr-k60n512/src/up_boot.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_boot.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/src/up_buttons.c b/configs/twr-k60n512/src/up_buttons.c index c5f3209235dad1ade0a8ac4630b525fe3068190a..5b449dbe89cd1b2232b7b9ecf49440f9807db198 100644 --- a/configs/twr-k60n512/src/up_buttons.c +++ b/configs/twr-k60n512/src/up_buttons.c @@ -2,7 +2,7 @@ * configs/twr-k60n512/src/up_buttons.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/src/up_leds.c b/configs/twr-k60n512/src/up_leds.c index fe03db3684d69066e6e77f23bfcd664335862acc..df7aeeaa5891dff177be86224e151f9cb298539d 100644 --- a/configs/twr-k60n512/src/up_leds.c +++ b/configs/twr-k60n512/src/up_leds.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_leds.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/src/up_nsh.c b/configs/twr-k60n512/src/up_nsh.c index e59265f91226ba6100be2f68114b9369b239983c..3bb4e8527bb8081a8c05979576f284c596ca3f12 100644 --- a/configs/twr-k60n512/src/up_nsh.c +++ b/configs/twr-k60n512/src/up_nsh.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_nsh.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/src/up_spi.c b/configs/twr-k60n512/src/up_spi.c index 6f8c3995b81dd5ced00db3cd12cc51011f58501c..074dc5cd7f0413c7eb80b6002f85c6aee1bee89f 100644 --- a/configs/twr-k60n512/src/up_spi.c +++ b/configs/twr-k60n512/src/up_spi.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_spi.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/src/up_usbdev.c b/configs/twr-k60n512/src/up_usbdev.c index 938ef43b56b60cd5ba40a4879f34489a69e0e5f5..8a07e8f874407c3f4891f6cf1bfbbefef1dbe5f6 100644 --- a/configs/twr-k60n512/src/up_usbdev.c +++ b/configs/twr-k60n512/src/up_usbdev.c @@ -3,7 +3,7 @@ * arch/arm/src/board/up_boot.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/twr-k60n512/src/up_usbmsc.c b/configs/twr-k60n512/src/up_usbmsc.c index bebedd02f63eabf37164fccec8b932906792edb6..1a8f7a70de8261129b2c33ef48b67d80847d1a5c 100644 --- a/configs/twr-k60n512/src/up_usbmsc.c +++ b/configs/twr-k60n512/src/up_usbmsc.c @@ -2,7 +2,7 @@ * configs/twr-k60n512/src/up_usbmsc.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Configure and register the Kinetis MMC/SD block driver. * diff --git a/configs/us7032evb1/include/board.h b/configs/us7032evb1/include/board.h index c0d03aad5903ec8bbd8e8c338a20e783fe9ad063..3ca3476dad2be458c730a0bde2761c3c9558fb97 100644 --- a/configs/us7032evb1/include/board.h +++ b/configs/us7032evb1/include/board.h @@ -2,7 +2,7 @@ * configs/us7032evb1/include/board.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/us7032evb1/nsh/Make.defs b/configs/us7032evb1/nsh/Make.defs index 410d0cea67ff97d52cd2fd170183d81a073cc783..623eb82d51022a22ef871a9dbae46d280e139183 100644 --- a/configs/us7032evb1/nsh/Make.defs +++ b/configs/us7032evb1/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/us7032evb1/nsh/Make.defs # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/us7032evb1/nsh/defconfig b/configs/us7032evb1/nsh/defconfig index 51c967ce5ae8d49937d9740157632dbd75c1309f..02d42aebe5568956f0aba001b16b049b8f1c2c69 100644 --- a/configs/us7032evb1/nsh/defconfig +++ b/configs/us7032evb1/nsh/defconfig @@ -2,7 +2,7 @@ # configs/us7032evb1/nsh/defconfig # # Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/us7032evb1/nsh/ld.script b/configs/us7032evb1/nsh/ld.script index 6deaddeb60df91ac8d00203dcbccc9171f4130fc..e21bdfa006f8cc620cfcbb1c999b098a627cc6f5 100644 --- a/configs/us7032evb1/nsh/ld.script +++ b/configs/us7032evb1/nsh/ld.script @@ -2,7 +2,7 @@ * configs/us7032evb1/nsh/ld.script * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/us7032evb1/nsh/setenv.sh b/configs/us7032evb1/nsh/setenv.sh index 93f7c2b3288a77ff9834f465b38823bf5925fc72..d2313361286ea6661f885d9e519a78c23fa3f46f 100755 --- a/configs/us7032evb1/nsh/setenv.sh +++ b/configs/us7032evb1/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/us7032evb1/nsh/setenv.sh # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/us7032evb1/ostest/Make.defs b/configs/us7032evb1/ostest/Make.defs index f924dc56fe12dd7dbb991e3735ba3571861af378..dcbaefdf85d135d85d7b82ac2dbf860081c20c64 100644 --- a/configs/us7032evb1/ostest/Make.defs +++ b/configs/us7032evb1/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/us7032evb1/ostest/Make.defs # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/us7032evb1/ostest/appconfig b/configs/us7032evb1/ostest/appconfig index 6381f59bc14eb8844179cd857aca1a5522794760..ba7253e3f181f7a76bf317c89df40a3fe2a97ee7 100644 --- a/configs/us7032evb1/ostest/appconfig +++ b/configs/us7032evb1/ostest/appconfig @@ -2,7 +2,7 @@ # configs/us7032evb1/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/us7032evb1/ostest/defconfig b/configs/us7032evb1/ostest/defconfig index da3feb8b165c899fd5045c1334bc985c649d5e33..f92a55461e991e846a9e6befa22aaf97a1d65351 100644 --- a/configs/us7032evb1/ostest/defconfig +++ b/configs/us7032evb1/ostest/defconfig @@ -2,7 +2,7 @@ # configs/us7032evb1/ostest/defconfig # # Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/us7032evb1/ostest/ld.script b/configs/us7032evb1/ostest/ld.script index 15bc1b2fdd1908185bc779b12eae4eeb124401a5..36c9b0d9a8d0bcb0fce5c3504740921e94b804d1 100644 --- a/configs/us7032evb1/ostest/ld.script +++ b/configs/us7032evb1/ostest/ld.script @@ -2,7 +2,7 @@ * configs/us7032evb1/ostest/ld.script * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/us7032evb1/ostest/setenv.sh b/configs/us7032evb1/ostest/setenv.sh index 9002ddff2c5a33f2f7f17178130943ad9d9688cf..ac37e9150f6fc91ae7856171599c7c9034815412 100755 --- a/configs/us7032evb1/ostest/setenv.sh +++ b/configs/us7032evb1/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/us7032evb1/ostest/setenv.sh # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/us7032evb1/shterm/Makefile b/configs/us7032evb1/shterm/Makefile index 9395f743de8df7b0f15d23060bf33e0702150f58..2ea23db3314436dd7075fc7edd4214d7f724c84a 100644 --- a/configs/us7032evb1/shterm/Makefile +++ b/configs/us7032evb1/shterm/Makefile @@ -2,7 +2,7 @@ # config/us7032evb1/shterm/Makefile # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/us7032evb1/shterm/shterm.c b/configs/us7032evb1/shterm/shterm.c index 0a1e143b1db2ed4630f9398999c1616eea836a44..f9ff2994aaa57525f0db177b99ba991d9474565a 100644 --- a/configs/us7032evb1/shterm/shterm.c +++ b/configs/us7032evb1/shterm/shterm.c @@ -2,7 +2,7 @@ * config/us7032evb1/shterm/shterm.c * * Copyright(C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/us7032evb1/src/Makefile b/configs/us7032evb1/src/Makefile index 421b67ac7e1a74422ee123c1231c1dbf255b9cd8..4ced0ac9ed396c68cd84e461c678a46f82ca7037 100644 --- a/configs/us7032evb1/src/Makefile +++ b/configs/us7032evb1/src/Makefile @@ -2,7 +2,7 @@ # configs/us7032evb1/src/Makefile # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/us7032evb1/src/up_leds.c b/configs/us7032evb1/src/up_leds.c index 4d6e213dbd311e753651f4d796b51eb160a6b327..d532bc3559690dec2acaaab50a9a68ce142e7931 100644 --- a/configs/us7032evb1/src/up_leds.c +++ b/configs/us7032evb1/src/up_leds.c @@ -2,7 +2,7 @@ * configs/us7032evb1/src/up_leds.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/vsn/include/board.h b/configs/vsn/include/board.h index f2c6f48cb34d519b8c0f9cd6b951f06f26ccbe1e..dbed25c191a1a15e00992cb68b85eb8508010553 100644 --- a/configs/vsn/include/board.h +++ b/configs/vsn/include/board.h @@ -5,7 +5,7 @@ * Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (C) 2011 Uros Platise. All rights reserved * - * Authors: Gregory Nutt + * Authors: Gregory Nutt * Uros Platise * * Redistribution and use in source and binary forms, with or without diff --git a/configs/vsn/nsh/Make.defs b/configs/vsn/nsh/Make.defs index 0487609ea71346c3d61254ed5ca86935e79537fe..db6f64896de20f5d86851df5eea00807c66f059d 100644 --- a/configs/vsn/nsh/Make.defs +++ b/configs/vsn/nsh/Make.defs @@ -2,7 +2,7 @@ # configs/stm3210e-eval/nsh/Make.defs # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/vsn/nsh/ld.script b/configs/vsn/nsh/ld.script index f7b4ba78bac7149d41ff6f149af3307e0040e86d..63c8585ebf27b5f33bc88bb5b06f49d3c33de68d 100755 --- a/configs/vsn/nsh/ld.script +++ b/configs/vsn/nsh/ld.script @@ -2,7 +2,7 @@ * configs/stm3210e-eval/nsh/ld.script * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/vsn/nsh/ld.script.dfu b/configs/vsn/nsh/ld.script.dfu index 2837fd04ceaf896304fd83428be93375ceeeedc9..aa077ba3b778b3a8a2a5264b14cc90eeff78a7a9 100755 --- a/configs/vsn/nsh/ld.script.dfu +++ b/configs/vsn/nsh/ld.script.dfu @@ -2,7 +2,7 @@ * configs/stm3210e-eval/nsh/ld.script.dfu * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/vsn/nsh/setenv.sh b/configs/vsn/nsh/setenv.sh index cbd45aa50b1318952ce9b7a7a833480e3c51ba78..3b9f7f8967ad9268c593fa0631944c06beabdffc 100755 --- a/configs/vsn/nsh/setenv.sh +++ b/configs/vsn/nsh/setenv.sh @@ -2,7 +2,7 @@ # configs/stm3210e-eval/dfu/setenv.sh # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/vsn/src/Makefile b/configs/vsn/src/Makefile index 03559cb4ab6f51bcaf1b5a9b30541c930b130206..fe40db2a716b576c64a2282d779aa46ea969b75f 100644 --- a/configs/vsn/src/Makefile +++ b/configs/vsn/src/Makefile @@ -4,7 +4,7 @@ # Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. # Copyright (c) 2011 Uros Platise. All rights reserved. # -# Authors: Gregory Nutt +# Authors: Gregory Nutt # Uros Platise # # Redistribution and use in source and binary forms, with or without diff --git a/configs/vsn/src/boot.c b/configs/vsn/src/boot.c index 846f707b76e88ee95949e49b34128b1d1ff0398d..94dcd00435ccd0fbd5d9ff366753c63f673f92fe 100644 --- a/configs/vsn/src/boot.c +++ b/configs/vsn/src/boot.c @@ -5,7 +5,7 @@ * Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (c) 2011 Uros Platise. All rights reserved. * - * Authors: Gregory Nutt + * Authors: Gregory Nutt * Uros Platise * * Redistribution and use in source and binary forms, with or without diff --git a/configs/vsn/src/spi.c b/configs/vsn/src/spi.c index f3be9f5bf6949e1cde10bfa49a5a47e04cf737dd..e8e15e54b83be97e1eab87aa29422524b9281f59 100644 --- a/configs/vsn/src/spi.c +++ b/configs/vsn/src/spi.c @@ -5,7 +5,7 @@ * Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (C) 2011 Uros Platise. All rights reserved. * - * Authors: Gregory Nutt + * Authors: Gregory Nutt * Uros Platise * * Redistribution and use in source and binary forms, with or without diff --git a/configs/vsn/src/usbdev.c b/configs/vsn/src/usbdev.c index db7fd1d9a2e83331230a2a6074639c00dd64d6b5..deb1e9b2d6d67034c269b7bdab94c1078f19eb46 100644 --- a/configs/vsn/src/usbdev.c +++ b/configs/vsn/src/usbdev.c @@ -5,7 +5,7 @@ * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. * Copyright (c) 2011 Uros Platise. All rights reserved. * - * Authors: Gregory Nutt + * Authors: Gregory Nutt * Uros Platise * * Redistribution and use in source and binary forms, with or without diff --git a/configs/vsn/src/usbmsc.c b/configs/vsn/src/usbmsc.c index 264ae77a66600e80969719b99fdb829da4692ebb..c0eebf6bf002861a954753be7c849e545e4bfa51 100644 --- a/configs/vsn/src/usbmsc.c +++ b/configs/vsn/src/usbmsc.c @@ -4,7 +4,7 @@ * Copyright (C) 2009 Gregory Nutt. All rights reserved. * Copyright (c) 2011 Uros Platise. All rights reserved. * - * Authors: Gregory Nutt + * Authors: Gregory Nutt * Uros Platise * * Configure and register the STM32 MMC/SD SDIO block driver. diff --git a/configs/xtrs/include/board.h b/configs/xtrs/include/board.h index 7a3050d6f91fe1569879e39f6a67e720c293beba..f8f74b2193aff4b85efb7d825b9b091de131dcba 100644 --- a/configs/xtrs/include/board.h +++ b/configs/xtrs/include/board.h @@ -2,7 +2,7 @@ * board/board.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/xtrs/nsh/setenv.sh b/configs/xtrs/nsh/setenv.sh index dadab845df5e529d77c3571f3b678f7deb0414ae..c59e0abc1f149f339b02a3210e0ccc4c9d2fe2d5 100755 --- a/configs/xtrs/nsh/setenv.sh +++ b/configs/xtrs/nsh/setenv.sh @@ -2,7 +2,7 @@ # xtrs/setenv.sh # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/xtrs/ostest/appconfig b/configs/xtrs/ostest/appconfig index 906020daed497f9cd0e3fbf1cb4128fa8e649cc1..d998929853aad9b7220ddf8c0e927e3567b28371 100644 --- a/configs/xtrs/ostest/appconfig +++ b/configs/xtrs/ostest/appconfig @@ -2,7 +2,7 @@ # configs/xtrs/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/xtrs/ostest/setenv.sh b/configs/xtrs/ostest/setenv.sh index d62ae86dee8cc7883e9da8c53ce64d6da834faec..cf7b5d796aaaf29dd6c2763b259af5b786983666 100755 --- a/configs/xtrs/ostest/setenv.sh +++ b/configs/xtrs/ostest/setenv.sh @@ -2,7 +2,7 @@ # xtrs/setenv.sh # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/xtrs/pashello/appconfig b/configs/xtrs/pashello/appconfig index 0deb0b01b015ad410e946f49643771e690442b6b..7cb5a7cf2aecc80b94dd791243567f6901d310fc 100644 --- a/configs/xtrs/pashello/appconfig +++ b/configs/xtrs/pashello/appconfig @@ -2,7 +2,7 @@ # configs/xtrs/pashello/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/xtrs/pashello/setenv.sh b/configs/xtrs/pashello/setenv.sh index d62ae86dee8cc7883e9da8c53ce64d6da834faec..cf7b5d796aaaf29dd6c2763b259af5b786983666 100755 --- a/configs/xtrs/pashello/setenv.sh +++ b/configs/xtrs/pashello/setenv.sh @@ -2,7 +2,7 @@ # xtrs/setenv.sh # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/xtrs/src/Make.defs b/configs/xtrs/src/Make.defs index d077ca64597d6d78c600ff3d3ff6e5b8c24032c5..e20f03a4e56bc78c328bfd4cc6c1984081fb026d 100644 --- a/configs/xtrs/src/Make.defs +++ b/configs/xtrs/src/Make.defs @@ -2,7 +2,7 @@ # configs/xtrs/src/Make.defs # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/xtrs/src/Makefile b/configs/xtrs/src/Makefile index ca08c9a339c3bc3634b49c6ae6731b2bb591c15d..9b14cf417871f894f30f49bcff6dbf9ab5566e26 100644 --- a/configs/xtrs/src/Makefile +++ b/configs/xtrs/src/Makefile @@ -2,7 +2,7 @@ # configs/xtrs/src/Makefile # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/xtrs/src/xtr_irq.c b/configs/xtrs/src/xtr_irq.c index 1186f34f8e4b2f631409e5d0fc460db16c4443bd..4e17c37bcac72433b47f2248ed7ed72366ab20a7 100644 --- a/configs/xtrs/src/xtr_irq.c +++ b/configs/xtrs/src/xtr_irq.c @@ -2,7 +2,7 @@ * board/xtr_irq.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/xtrs/src/xtr_timerisr.c b/configs/xtrs/src/xtr_timerisr.c index de0109534c15367744a6ef601e1aa6bde0a45c7b..21a77706f65d3fa5614921023b05af7211289315 100644 --- a/configs/xtrs/src/xtr_timerisr.c +++ b/configs/xtrs/src/xtr_timerisr.c @@ -2,7 +2,7 @@ * board/xtr_timerisr.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/xtrs/src/xtrs_head.asm b/configs/xtrs/src/xtrs_head.asm index 5fb33c3c8d9658cc1f5779e1bec8d13bea6adfdc..bd7156f590c5500d2baa09e7102db54dc39aa68b 100644 --- a/configs/xtrs/src/xtrs_head.asm +++ b/configs/xtrs/src/xtrs_head.asm @@ -2,7 +2,7 @@ ; configs/xtrs/src/xtrs_head.asm ; ; Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. -; Author: Gregory Nutt +; Author: Gregory Nutt ; ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions diff --git a/configs/z16f2800100zcog/include/board.h b/configs/z16f2800100zcog/include/board.h index f5e562e310820ddc7378b70d4e72c56bae560f89..e9b37d85d998af62c8582e96690010201a1fc11b 100644 --- a/configs/z16f2800100zcog/include/board.h +++ b/configs/z16f2800100zcog/include/board.h @@ -2,7 +2,7 @@ * board/board.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/z16f2800100zcog/ostest/Make.defs b/configs/z16f2800100zcog/ostest/Make.defs index 64eda832f8405f908779cd677d63de4d377448a1..8440224cab14f68b03a8ecdbd33fd2d4bae328a5 100644 --- a/configs/z16f2800100zcog/ostest/Make.defs +++ b/configs/z16f2800100zcog/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/z16f2800100zcog/ostest/Make.defs # # Copyright (C) 2008, 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z16f2800100zcog/ostest/appconfig b/configs/z16f2800100zcog/ostest/appconfig index 627b24deb891b656b5a6e5949724b8ab8485c867..a0f5d2462f4b9f3158b46e444c76035d9367dc16 100644 --- a/configs/z16f2800100zcog/ostest/appconfig +++ b/configs/z16f2800100zcog/ostest/appconfig @@ -2,7 +2,7 @@ # configs/z16f2800100zcog/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z16f2800100zcog/ostest/defconfig b/configs/z16f2800100zcog/ostest/defconfig index cf200025304acd3ed3ea65ca105e430d44e0d19d..24cca2a6aad3ab9c2891c72de48c3fcf7a0333ea 100644 --- a/configs/z16f2800100zcog/ostest/defconfig +++ b/configs/z16f2800100zcog/ostest/defconfig @@ -2,7 +2,7 @@ # configs/z16f2800100zcog/ostest/defconfig # # Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z16f2800100zcog/ostest/ostest.linkcmd b/configs/z16f2800100zcog/ostest/ostest.linkcmd index 5ab69bb46f9e60fb1b2956e6b908c844909e6a4b..17539ad5728c816505f4d8ee19dd12526178b0df 100755 --- a/configs/z16f2800100zcog/ostest/ostest.linkcmd +++ b/configs/z16f2800100zcog/ostest/ostest.linkcmd @@ -2,7 +2,7 @@ /* configs/z16f2800100zcog/ostest/ostest.linkcmd */ /* */ /* Copyright (C) 2008 Gregory Nutt. All rights reserved. */ -/* Author: Gregory Nutt */ +/* Author: Gregory Nutt */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ diff --git a/configs/z16f2800100zcog/ostest/setenv.sh b/configs/z16f2800100zcog/ostest/setenv.sh index 5a7bf2779af3ff267f310314e5b3b4a59ae677c1..bddcad2b5b75df62f564fa514dd725fda3ef288c 100755 --- a/configs/z16f2800100zcog/ostest/setenv.sh +++ b/configs/z16f2800100zcog/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/z16f2800100zcog/ostest/setenv.sh # # Copyright (C) 2008, 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z16f2800100zcog/pashello/Make.defs b/configs/z16f2800100zcog/pashello/Make.defs index 999f25e625269fd5b18eda5bcc5c321f856eb85d..1c3e277ad9890d2acf27e5db765438a19709d983 100644 --- a/configs/z16f2800100zcog/pashello/Make.defs +++ b/configs/z16f2800100zcog/pashello/Make.defs @@ -2,7 +2,7 @@ # configs/z16f2800100zcog/pashello/Make.defs # # Copyright (C) 2008, 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z16f2800100zcog/pashello/appconfig b/configs/z16f2800100zcog/pashello/appconfig index 07a95ee0fcb164b15e257f1193a1f181a5fa0bd4..d35185f5f0f5d505493ad2029c6601a7533ae2fc 100644 --- a/configs/z16f2800100zcog/pashello/appconfig +++ b/configs/z16f2800100zcog/pashello/appconfig @@ -2,7 +2,7 @@ # configs/z16f2800100zcog/pashello/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z16f2800100zcog/pashello/defconfig b/configs/z16f2800100zcog/pashello/defconfig index 176d3a3876455275cdb573adf87bb7ee3fce4fbd..daf98c7d6e80e136a41643c81bb7ccef6fd59ba8 100644 --- a/configs/z16f2800100zcog/pashello/defconfig +++ b/configs/z16f2800100zcog/pashello/defconfig @@ -2,7 +2,7 @@ # configs/z16f2800100zcog/pashello/defconfig # # Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z16f2800100zcog/pashello/pashello.linkcmd b/configs/z16f2800100zcog/pashello/pashello.linkcmd index e254578f1fd4aa552dc1f49431b0ab0dcf60deec..f519219fb2827fa888b5e512ca9454713ab54a62 100755 --- a/configs/z16f2800100zcog/pashello/pashello.linkcmd +++ b/configs/z16f2800100zcog/pashello/pashello.linkcmd @@ -2,7 +2,7 @@ /* configs/z16f2800100zcog/pashello/pashello.linkcmd */ /* */ /* Copyright (C) 2008 Gregory Nutt. All rights reserved. */ -/* Author: Gregory Nutt */ +/* Author: Gregory Nutt */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ diff --git a/configs/z16f2800100zcog/pashello/setenv.sh b/configs/z16f2800100zcog/pashello/setenv.sh index 982461b2469c283d9dd209d7b9538e32622c889b..f957b23cbbf25d5af5ecee05217d6b7e761a625d 100755 --- a/configs/z16f2800100zcog/pashello/setenv.sh +++ b/configs/z16f2800100zcog/pashello/setenv.sh @@ -2,7 +2,7 @@ # z16f2800100zcog/setenv.sh # # Copyright (C) 2008, 2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z16f2800100zcog/src/Makefile b/configs/z16f2800100zcog/src/Makefile index e683d4b7191c601256c20e55515adc9209c9535e..b8eedadd4a371f4a19592967d8105360a4f9d88e 100644 --- a/configs/z16f2800100zcog/src/Makefile +++ b/configs/z16f2800100zcog/src/Makefile @@ -2,7 +2,7 @@ # configs/z16f2800100zcog/Makefile # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z16f2800100zcog/src/z16f_leds.c b/configs/z16f2800100zcog/src/z16f_leds.c index 0d7f571acbb5ae002191e742794c5f0843a43f4b..dfcf96fec0711eb153e709d09ebb7b39ce992bc3 100644 --- a/configs/z16f2800100zcog/src/z16f_leds.c +++ b/configs/z16f2800100zcog/src/z16f_leds.c @@ -2,7 +2,7 @@ * configs/z16f2800100zcog/z16f_leds.c * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/z16f2800100zcog/src/z16f_lowinit.c b/configs/z16f2800100zcog/src/z16f_lowinit.c index 3c2c43ec81ab9e711e4d71e37cd0bf94d7de54d5..2eb7d701bae70a9180f4c55e633213a98ade001e 100644 --- a/configs/z16f2800100zcog/src/z16f_lowinit.c +++ b/configs/z16f2800100zcog/src/z16f_lowinit.c @@ -1,90 +1,90 @@ -/*************************************************************************** - * configs/z16f2800100zcog/src/z16f_lowinit.c - * - * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Based upon sample code included with the Zilog ZDS-II toolchain. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -/*************************************************************************** - * Included Files - ***************************************************************************/ - -#include - -#include "chip/chip.h" - -/*************************************************************************** - * Definitions - ***************************************************************************/ - -/*************************************************************************** - * Private Functions - ***************************************************************************/ - -static void z16f_gpioinit(void) -{ - /* Configure LEDs and Run/Stop switch port */ - - putreg8(getreg8(Z16F_GPIOA_DD) | 0x87, Z16F_GPIOA_DD); - putreg8(getreg8(Z16F_GPIOA_OUT) | 0x07, Z16F_GPIOA_OUT); - putreg8(getreg8(Z16F_GPIOA_DD) & 0xF8, Z16F_GPIOA_DD); - - /* Configure rate switch port */ - - putreg8(getreg8(Z16F_GPIOB_DD) | 0x20, Z16F_GPIOB_DD); - putreg8(getreg8(Z16F_GPIOB_AFL) | 0x20, Z16F_GPIOB_AFL); - -#if 0 /* Not yet */ - putreg8(0x05, Z16F_ADC0_MAX); - putreg8(0xf5, Z16F_ADC0_CTL); -#endif - - /* Configure Direction switch port */ - - putreg8(getreg8(Z16F_GPIOC_DD) | 0x01, Z16F_GPIOC_DD); - - /* Configure to use both UART0 and 1 */ - - putreg8(getreg8(Z16F_GPIOA_AFL) | 0x30, Z16F_GPIOA_AFL); - putreg8(getreg8(Z16F_GPIOD_AFL) | 0x30, Z16F_GPIOD_AFL); -} - -/*************************************************************************** - * Public Functions - ***************************************************************************/ - -void z16f_lowinit(void) -{ - z16f_gpioinit(); -} - +/*************************************************************************** + * configs/z16f2800100zcog/src/z16f_lowinit.c + * + * Copyright (C) 2008 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Based upon sample code included with the Zilog ZDS-II toolchain. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#include + +#include "chip/chip.h" + +/*************************************************************************** + * Definitions + ***************************************************************************/ + +/*************************************************************************** + * Private Functions + ***************************************************************************/ + +static void z16f_gpioinit(void) +{ + /* Configure LEDs and Run/Stop switch port */ + + putreg8(getreg8(Z16F_GPIOA_DD) | 0x87, Z16F_GPIOA_DD); + putreg8(getreg8(Z16F_GPIOA_OUT) | 0x07, Z16F_GPIOA_OUT); + putreg8(getreg8(Z16F_GPIOA_DD) & 0xF8, Z16F_GPIOA_DD); + + /* Configure rate switch port */ + + putreg8(getreg8(Z16F_GPIOB_DD) | 0x20, Z16F_GPIOB_DD); + putreg8(getreg8(Z16F_GPIOB_AFL) | 0x20, Z16F_GPIOB_AFL); + +#if 0 /* Not yet */ + putreg8(0x05, Z16F_ADC0_MAX); + putreg8(0xf5, Z16F_ADC0_CTL); +#endif + + /* Configure Direction switch port */ + + putreg8(getreg8(Z16F_GPIOC_DD) | 0x01, Z16F_GPIOC_DD); + + /* Configure to use both UART0 and 1 */ + + putreg8(getreg8(Z16F_GPIOA_AFL) | 0x30, Z16F_GPIOA_AFL); + putreg8(getreg8(Z16F_GPIOD_AFL) | 0x30, Z16F_GPIOD_AFL); +} + +/*************************************************************************** + * Public Functions + ***************************************************************************/ + +void z16f_lowinit(void) +{ + z16f_gpioinit(); +} + diff --git a/configs/z80sim/include/board.h b/configs/z80sim/include/board.h index 4cc4b97daf8171c99b2ae2e33454b20124e026bf..5bf8eb82d684abfe0fe336c0fd78163bac166ae9 100644 --- a/configs/z80sim/include/board.h +++ b/configs/z80sim/include/board.h @@ -2,7 +2,7 @@ * board/board.h * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/z80sim/nsh/defconfig b/configs/z80sim/nsh/defconfig index a87e7a9288785d2999f6b5a76bf4d4c8bded9eac..9d4d81a74cd921eb13d31badacea111dfa14fb8e 100644 --- a/configs/z80sim/nsh/defconfig +++ b/configs/z80sim/nsh/defconfig @@ -2,7 +2,7 @@ # sim/z80sim/nsh/defconfig # # Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z80sim/nsh/setenv.sh b/configs/z80sim/nsh/setenv.sh index cdb5e67d768ea6ba9cc13af72dfbd2d83e249987..fa65934f183e42bd23b380ce0cd70676879932ae 100755 --- a/configs/z80sim/nsh/setenv.sh +++ b/configs/z80sim/nsh/setenv.sh @@ -2,7 +2,7 @@ # z80sim/setenv.sh # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z80sim/ostest/appconfig b/configs/z80sim/ostest/appconfig index e4dda3c7804d38504f67fcb932c00891040c2355..59f1211b124938f3a5682d09266e3f7e675e1e3a 100644 --- a/configs/z80sim/ostest/appconfig +++ b/configs/z80sim/ostest/appconfig @@ -2,7 +2,7 @@ # configs/z80sim/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z80sim/ostest/setenv.sh b/configs/z80sim/ostest/setenv.sh index cdb5e67d768ea6ba9cc13af72dfbd2d83e249987..fa65934f183e42bd23b380ce0cd70676879932ae 100755 --- a/configs/z80sim/ostest/setenv.sh +++ b/configs/z80sim/ostest/setenv.sh @@ -2,7 +2,7 @@ # z80sim/setenv.sh # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z80sim/pashello/appconfig b/configs/z80sim/pashello/appconfig index faa2589ab313a9f03b5ca3c3ee55f2730e09e380..38d7b91f8075ce3fc6f8a30410a049db69bdb7c5 100644 --- a/configs/z80sim/pashello/appconfig +++ b/configs/z80sim/pashello/appconfig @@ -2,7 +2,7 @@ # configs/z80sim/pashello/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z80sim/pashello/defconfig b/configs/z80sim/pashello/defconfig index 42ffdb0f3fe064ca9e5564f9cf2eb5347a8fbc78..1c50f71ff02f5f008bba8dc26013be8f8647c44b 100644 --- a/configs/z80sim/pashello/defconfig +++ b/configs/z80sim/pashello/defconfig @@ -2,7 +2,7 @@ # configs/z80sim/pashello/defconfig # # Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z80sim/pashello/setenv.sh b/configs/z80sim/pashello/setenv.sh index cdb5e67d768ea6ba9cc13af72dfbd2d83e249987..fa65934f183e42bd23b380ce0cd70676879932ae 100755 --- a/configs/z80sim/pashello/setenv.sh +++ b/configs/z80sim/pashello/setenv.sh @@ -2,7 +2,7 @@ # z80sim/setenv.sh # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z80sim/src/Makefile b/configs/z80sim/src/Makefile index 46767d13954066d5a6a93bafae9c23b88c55c515..0511d00fe6d14aedbe4b065f3266fb4fb3d095fc 100644 --- a/configs/z80sim/src/Makefile +++ b/configs/z80sim/src/Makefile @@ -2,7 +2,7 @@ # configs/z80sim/src/Makefile # # Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z80sim/src/z80_irq.c b/configs/z80sim/src/z80_irq.c index 7312f66e300e449ec75a326cb1bd3a407c19319f..0fc5d95de9690e33b9e2206c0d3328209c3a0688 100644 --- a/configs/z80sim/src/z80_irq.c +++ b/configs/z80sim/src/z80_irq.c @@ -2,7 +2,7 @@ * board/z80_irq.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/z80sim/src/z80_lowputc.c b/configs/z80sim/src/z80_lowputc.c index 58615ea24eeafdb8b1c1eff805d29ea0a67e2df3..0909929d77c7ea7f37d7c2de04ba8ae56bc2fecc 100644 --- a/configs/z80sim/src/z80_lowputc.c +++ b/configs/z80sim/src/z80_lowputc.c @@ -2,7 +2,7 @@ * board/z80_lowputc.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/z80sim/src/z80_timerisr.c b/configs/z80sim/src/z80_timerisr.c index 85210eca49b4e62a585223a5a32feee1d65707eb..1bcfda04987d911f72935e6a055ae27fe6cabe7b 100644 --- a/configs/z80sim/src/z80_timerisr.c +++ b/configs/z80sim/src/z80_timerisr.c @@ -2,7 +2,7 @@ * board/z80_timerisr.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/z8encore000zco/include/board.h b/configs/z8encore000zco/include/board.h index dca9ca7d8c796fc229c4dd73afa9fb96c5679ee1..4690ee093397b6634b5c271b8ba2d89a8b1e51c4 100644 --- a/configs/z8encore000zco/include/board.h +++ b/configs/z8encore000zco/include/board.h @@ -2,7 +2,7 @@ * arch/z8encore000zco/include/board.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/z8encore000zco/ostest/Make.defs b/configs/z8encore000zco/ostest/Make.defs index 000ee4a63fdc716bbe6126b5b0b016af08707696..cf310e0ff48103a9c2a14aaaf033e3568e600938 100644 --- a/configs/z8encore000zco/ostest/Make.defs +++ b/configs/z8encore000zco/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/z8encore000zco/ostest/Make.defs # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z8encore000zco/ostest/appconfig b/configs/z8encore000zco/ostest/appconfig index cf434eea6f7c93319fea688edb34e66f6c36d1eb..212b52f727b6c31e9eb83d7dcf0cc373f2e9fb97 100644 --- a/configs/z8encore000zco/ostest/appconfig +++ b/configs/z8encore000zco/ostest/appconfig @@ -2,7 +2,7 @@ # configs/z8encore000zco/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z8encore000zco/ostest/ostest.linkcmd b/configs/z8encore000zco/ostest/ostest.linkcmd index befb1ac713806e40ba26c02dded49dfaf5762f53..14fcd81f680af1bca630506142bf23f760735a1f 100755 --- a/configs/z8encore000zco/ostest/ostest.linkcmd +++ b/configs/z8encore000zco/ostest/ostest.linkcmd @@ -2,7 +2,7 @@ /* configs/z8encore000zco/ostest/ostest.linkcmd */ /* */ /* Copyright (C) 2008 Gregory Nutt. All rights reserved. */ -/* Author: Gregory Nutt */ +/* Author: Gregory Nutt */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ diff --git a/configs/z8encore000zco/ostest/setenv.sh b/configs/z8encore000zco/ostest/setenv.sh index 50a1db1abdb6540231bae0124f665d85f3e675a1..5aa816dd962029cf36ce03271e13585a3cf104d1 100755 --- a/configs/z8encore000zco/ostest/setenv.sh +++ b/configs/z8encore000zco/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/z8encore000zco/ostest/setenv.sh # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z8encore000zco/src/Makefile b/configs/z8encore000zco/src/Makefile index 6982efe1728bed487b1e7c5ff3f30560f6313e7d..ca9de460cf0f862dac5ce08d91ee6cdc51c16465 100644 --- a/configs/z8encore000zco/src/Makefile +++ b/configs/z8encore000zco/src/Makefile @@ -2,7 +2,7 @@ # configs/z8encore000zco/Makefile # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z8encore000zco/src/z8_leds.c b/configs/z8encore000zco/src/z8_leds.c index f14dae6efef1c999701ee8ca05773a4240a861a0..097b27efa968124dec4597d9f7d2848e16f98713 100644 --- a/configs/z8encore000zco/src/z8_leds.c +++ b/configs/z8encore000zco/src/z8_leds.c @@ -2,7 +2,7 @@ * configs/z8encore000zco/src/z8_leds.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/z8encore000zco/src/z8_lowinit.c b/configs/z8encore000zco/src/z8_lowinit.c index 7443dbb654f73688ed007e54e2415dc7fb871b22..1604fb82c6d93baec9b8c3598c4b62e6f720a027 100644 --- a/configs/z8encore000zco/src/z8_lowinit.c +++ b/configs/z8encore000zco/src/z8_lowinit.c @@ -1,66 +1,66 @@ -/*************************************************************************** - * configs/z8encore000zco/src/z8_lowinit.c - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Based upon sample code included with the Zilog ZDS-II toolchain. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -/*************************************************************************** - * Included Files - ***************************************************************************/ - -#include - -#include "chip/chip.h" - -/*************************************************************************** - * Definitions - ***************************************************************************/ - -/*************************************************************************** - * Private Functions - ***************************************************************************/ - -static void z8_gpioinit(void) -{ -} - -/*************************************************************************** - * Public Functions - ***************************************************************************/ - -void z8_lowinit(void) -{ - z8_gpioinit(); -} - +/*************************************************************************** + * configs/z8encore000zco/src/z8_lowinit.c + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Based upon sample code included with the Zilog ZDS-II toolchain. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#include + +#include "chip/chip.h" + +/*************************************************************************** + * Definitions + ***************************************************************************/ + +/*************************************************************************** + * Private Functions + ***************************************************************************/ + +static void z8_gpioinit(void) +{ +} + +/*************************************************************************** + * Public Functions + ***************************************************************************/ + +void z8_lowinit(void) +{ + z8_gpioinit(); +} + diff --git a/configs/z8f64200100kit/include/board.h b/configs/z8f64200100kit/include/board.h index 0b87c7c8b91439f68f783a8725458e435dbb5df9..87ca98adcf2b5948e3bb3ed2bf8787458f612474 100644 --- a/configs/z8f64200100kit/include/board.h +++ b/configs/z8f64200100kit/include/board.h @@ -2,7 +2,7 @@ * arch/z8f64200100kit/include/board.h * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/z8f64200100kit/ostest/Make.defs b/configs/z8f64200100kit/ostest/Make.defs index 9334377a26556db968d552da29883d6d3eaefa8f..894df0855f3a20f9325e489bf59acff5620c0279 100644 --- a/configs/z8f64200100kit/ostest/Make.defs +++ b/configs/z8f64200100kit/ostest/Make.defs @@ -2,7 +2,7 @@ # configs/z8f64200100kit/ostest/Make.defs # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z8f64200100kit/ostest/appconfig b/configs/z8f64200100kit/ostest/appconfig index 77aa77727924189c103b541aae82e95b32d07c68..e6f0c237501db91dd85f31f8e533ece91e77a166 100644 --- a/configs/z8f64200100kit/ostest/appconfig +++ b/configs/z8f64200100kit/ostest/appconfig @@ -2,7 +2,7 @@ # configs/z8f64200100kit/ostest/appconfig # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z8f64200100kit/ostest/ostest.linkcmd b/configs/z8f64200100kit/ostest/ostest.linkcmd index dde2462209d38aeb862b63bd3b4b7d4bb15eb3e8..87ea00085e4d8ed2658b6b5be5fc253ad3f98d19 100755 --- a/configs/z8f64200100kit/ostest/ostest.linkcmd +++ b/configs/z8f64200100kit/ostest/ostest.linkcmd @@ -2,7 +2,7 @@ /* configs/z8f64200100kit/ostest/ostest.linkcmd */ /* */ /* Copyright (C) 2008 Gregory Nutt. All rights reserved. */ -/* Author: Gregory Nutt */ +/* Author: Gregory Nutt */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ diff --git a/configs/z8f64200100kit/ostest/setenv.sh b/configs/z8f64200100kit/ostest/setenv.sh index 1c4e29504e40b19eec1ca0d4344b4ba04c006a96..166ed9e0c9d9cfaeb5c21f496532a209a3ac3a84 100755 --- a/configs/z8f64200100kit/ostest/setenv.sh +++ b/configs/z8f64200100kit/ostest/setenv.sh @@ -2,7 +2,7 @@ # configs/z8f64200100kit/ostest/setenv.sh # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z8f64200100kit/src/Makefile b/configs/z8f64200100kit/src/Makefile index f4ce2333d8e00b974ef6540f1c27a791aa2351c2..c9c9b36e298037c6c4b6a83130a98c9b919f874e 100644 --- a/configs/z8f64200100kit/src/Makefile +++ b/configs/z8f64200100kit/src/Makefile @@ -2,7 +2,7 @@ # configs/z8f64200100kit/Makefile # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/configs/z8f64200100kit/src/z8_leds.c b/configs/z8f64200100kit/src/z8_leds.c index b83167c0afaf818304010c5509136373da66f909..c5b6ec8af863097e35d5eb217b68c631226b1cfe 100644 --- a/configs/z8f64200100kit/src/z8_leds.c +++ b/configs/z8f64200100kit/src/z8_leds.c @@ -2,7 +2,7 @@ * configs/z8f64200100kit/src/z8_leds.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/configs/z8f64200100kit/src/z8_lowinit.c b/configs/z8f64200100kit/src/z8_lowinit.c index a3cb0163a865b6dac03b3d8457086b60c1eb1c2f..41782e69fe8ea3510313df20e5008859f211b55a 100644 --- a/configs/z8f64200100kit/src/z8_lowinit.c +++ b/configs/z8f64200100kit/src/z8_lowinit.c @@ -1,66 +1,66 @@ -/*************************************************************************** - * configs/z8f64200100kit/src/z8_lowinit.c - * - * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Based upon sample code included with the Zilog ZDS-II toolchain. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -/*************************************************************************** - * Included Files - ***************************************************************************/ - -#include - -#include "chip/chip.h" - -/*************************************************************************** - * Definitions - ***************************************************************************/ - -/*************************************************************************** - * Private Functions - ***************************************************************************/ - -static void z8_gpioinit(void) -{ -} - -/*************************************************************************** - * Public Functions - ***************************************************************************/ - -void z8_lowinit(void) -{ - z8_gpioinit(); -} - +/*************************************************************************** + * configs/z8f64200100kit/src/z8_lowinit.c + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Based upon sample code included with the Zilog ZDS-II toolchain. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#include + +#include "chip/chip.h" + +/*************************************************************************** + * Definitions + ***************************************************************************/ + +/*************************************************************************** + * Private Functions + ***************************************************************************/ + +static void z8_gpioinit(void) +{ +} + +/*************************************************************************** + * Public Functions + ***************************************************************************/ + +void z8_lowinit(void) +{ + z8_gpioinit(); +} + diff --git a/drivers/analog/Make.defs b/drivers/analog/Make.defs index 10b0db47851278576f27c14021b9a839a54d6e8c..d94e397587c7198f9e262e916a62f83e34a06098 100644 --- a/drivers/analog/Make.defs +++ b/drivers/analog/Make.defs @@ -2,7 +2,7 @@ # drivers/analog/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/drivers/analog/dac.c b/drivers/analog/dac.c index 9371e3414cbcb38a9946f84397a72fedbd2525d3..e1fc3049ffff7e82ce16a9d143949f1846923d3f 100644 --- a/drivers/analog/dac.c +++ b/drivers/analog/dac.c @@ -8,7 +8,7 @@ * Derived from drivers/can.c * * Copyright (C) 2008-2009Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/input/Make.defs b/drivers/input/Make.defs index aaf08b827015d5eec487e62e74d9c131ee2cbf45..6dbae268e5af5c0edfb22d02c9694ed1f0c71a94 100644 --- a/drivers/input/Make.defs +++ b/drivers/input/Make.defs @@ -2,7 +2,7 @@ # drivers/input/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/drivers/lcd/nokia6100.c b/drivers/lcd/nokia6100.c index d450e05dbfb3ac78ce8f889c6d374b685e809b7c..7354b8a91749864fc81232313916a76de96419ac 100644 --- a/drivers/lcd/nokia6100.c +++ b/drivers/lcd/nokia6100.c @@ -3,7 +3,7 @@ * Nokia 6100 LCD Display Driver * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: * "Nokia 6100 LCD Display Driver," Revision 1, James P. Lynch ("Nokia 6100 LCD diff --git a/drivers/lcd/pcf8833.h b/drivers/lcd/pcf8833.h index b0a7e14d41782266fb6ebb1a0558952574e70832..36dc65ac3f5d4735ac2d7ca0e092b525c29f7e27 100644 --- a/drivers/lcd/pcf8833.h +++ b/drivers/lcd/pcf8833.h @@ -1,152 +1,152 @@ -/************************************************************************************** - * drivers/lcd/pcf8833.h - * Definitions for the Phillips PCF8833 LCD controller - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * References: "Data Sheet, PCF8833 STN RGB 132x132x3 driver," Phillips, 2003 Feb 14. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************/ - -#ifndef __DRIVERS_LCD_PCF8833_H -#define __DRIVERS_LCD_PCF8833_H - -/************************************************************************************** - * Included Files - **************************************************************************************/ - -/************************************************************************************** - * Pre-processor Definitions - **************************************************************************************/ -/* Pixel format codes */ - -#define PCF8833_FMT_8BPS (2) -#define PCF8833_FMT_12BPS (3) -#define PCF8833_FMT_16BPS (5) - -/* LCD Commands */ - -#define PCF8833_NOP 0x00 /* No operation; Data: none */ -#define PCF8833_SWRESET 0x01 /* Software reset ; Data: none */ -#define PCF8833_BSTROFF 0x02 /* Booster voltage off; Data: none */ -#define PCF8833_BSTRON 0x03 /* Booster voltage on; Data: none */ -#define PCF8833_RDDIDIF 0x04 /* Read display identification; Data: none */ -#define PCF8833_RDDST 0x09 /* Read display status; Data: none */ -#define PCF8833_SLEEPIN 0x10 /* Sleep_IN; Data: none */ -#define PCF8833_SLEEPOUT 0x11 /* Sleep_OUT; Data: none */ -#define PCF8833_PTLON 0x12 /* Partial mode on; Data: none */ -#define PCF8833_NORON 0x13 /* Normal Display mode on; Data: none */ -#define PCF8833_INVOFF 0x20 /* Display inversion off; Data: none */ -#define PCF8833_INVON 0x21 /* Display inversion on; Data: none */ -#define PCF8833_DALO 0x22 /* All pixel off; Data: none */ -#define PCF8833_DAL 0x23 /* All pixel on; Data: none */ -#define PCF8833_SETCON 0x25 /* Set contrast; Data: (1) contrast */ -#define PCF8833_DISPOFF 0x28 /* Display off; Data: none */ -#define PCF8833_DISPON 0x29 /* Display on; Data: none */ -#define PCF8833_CASET 0x2a /* Column address set; Data: (1) X start (2) X end */ -#define PCF8833_PASET 0x2b /* Page address set Data: (1) Y start (2) Y end */ -#define PCF8833_RAMWR 0x2c /* Memory write; Data: (1) write data */ -#define PCF8833_RGBSET 0x2d /* Colour set; Data: (1-8) red tones, (9-16) green tones, (17-20) blue tones */ -#define PCF8833_PTLAR 0x30 /* Partial area; Data: (1) start address (2) end address */ -#define PCF8833_VSCRDEF 0x33 /* Vertical scroll definition; Data: (1) top fixed, (2) scrol area, (3) bottom fixed */ -#define PCF8833_TEOFF 0x34 /* Tearing line off; Data: none */ -#define PCF8833_TEON 0x35 /* Tearing line on; Data: (1) don't care */ -#define PCF8833_MADCTL 0x36 /* Memory data access control; Data: (1) access control settings */ -#define PCF8833_SEP 0x37 /* Set Scroll Entry Point; Data: (1) scroll entry point */ -#define PCF8833_IDMOFF 0x38 /* Idle mode off; Data: none */ -#define PCF8833_IDMON 0x39 /* Idle mode on; Data: none */ -#define PCF8833_COLMOD 0x3a /* Interface pixel format; Data: (1) color interface format */ -#define PCF8833_SETVOP 0xb0 /* Set VOP; Data: (1) VOP5-8 (2) VOP0-4 */ -#define PCF8833_BRS 0xb4 /* Bottom Row Swap; Data: none */ -#define PCF8833_TRS 0xb6 /* Top Row Swap; Data: none */ -#define PCF8833_FINV 0xb9 /* Super Frame INVersion; Data: none */ -#define PCF8833_DOR 0xba /* Data ORder; Data: none */ -#define PCF8833_TCDFE 0xbd /* Enable/disable DF temp comp; Data: none */ -#define PCF8833_TCVOPE 0xbf /* Enable or disable VOP temp comp; Data: none */ -#define PCF8833_EC 0xc0 /* Internal or external oscillator; Data: none */ -#define PCF8833_SETMUL 0xc2 /* Set multiplication factor; Data: (1) Multiplication factor */ -#define PCF8833_TCVOPAB 0xc3 /* Set TCVOP slopes A and B; Data: (1) SLB and SLA */ -#define PCF8833_TCVOPCD 0xc4 /* Set TCVOP slopes C and D; Data: (1) SLD and SLC */ -#define PCF8833_TCDF 0xc5 /* Set divider frequency; Data: Divider factor in region (1) A (2) B (3) C (4) D */ -#define PCF8833_DF8COLOR 0xc6 /* Set divider frequency 8-colour mode; Data: (1) DF80-6 */ -#define PCF8833_SETBS 0xc7 /* Set bias system; Data: (1) Bias systems */ -#define PCF8833_RDTEMP 0xc8 /* Temperature read back; Data: none */ -#define PCF8833_NLI 0xc9 /* N-Line Inversion; Data: (1) NLI time slots invervsion */ -#define PCF8833_RDID1 0xda /* Read ID1; Data: none */ -#define PCF8833_RDID2 0xdb /* Read ID2; Data: none */ -#define PCF8833_RDID3 0xdc /* Read ID3; Data: none */ -#define PCF8833_SFD 0xef /* Select factory defaults; Data: none */ -#define PCF8833_ECM 0xf0 /* Enter Calibration mode; Data: (1) Calibration control settings */ -#define PCF8833_OTPSHTIN 0xf1 /* Shift data in OTP shift registers; Data: Any number of bytes */ - -/* Memory data access control (MADCTL) bit definitions */ - -#define MADCTL_RGB (1 << 3) /* Bit 3: BGR */ -#define MADCTL_LAO (1 << 4) /* Bit 4: Line address order bottom to top */ -#define MADCTL_V (1 << 5) /* Bit 5: Vertical RAM write; in Y direction */ -#define MADCTL_MX (1 << 6) /* Bit 6: Mirror X */ -#define MADCTL_MY (1 << 7) /* Bit 7: Mirror Y */ - -/* PCF8833 status register bit definitions */ -/* CMD format: RDDST command followed by four status bytes: */ -/* Byte 1: D31 d30 D29 D28 D27 D26 --- --- */ - -#define PCF8833_ST_RGB (1 << 2) /* Bit 2: D26 - RGB/BGR order */ -#define PCF8833_ST_LINEADDR (1 << 3) /* Bit 3: D27 - Line address order */ -#define PCF8833_ST_ADDRMODE (1 << 4) /* Bit 4: D28 - Vertical/horizontal addressing mode */ -#define PCF8833_ST_XADDR (1 << 5) /* Bit 5: D29 - X address order */ -#define PCF8833_ST_YADDR (1 << 6) /* Bit 6: D30 - Y address order */ -#define PCF8833_ST_BOOSTER (1 << 7) /* Bit 7: D31 - Booster voltage status */ - -/* Byte 2: --- D22 D21 D20 D19 D18 D17 D16 */ - -#define PCF8833_ST_NORMAL (1 << 0) /* Bit 0: D16 - Normal display mode */ -#define PCF8833_ST_SLEEPIN (1 << 1) /* Bit 1: D17 - Sleep in selected */ -#define PCF8833_ST_PARTIAL (1 << 2) /* Bit 2: D18 - Partial mode on */ -#define PCF8833_ST_IDLE (1 << 3) /* Bit 3: D19 - Idle mode selected */ -#define PCF8833_ST_PIXELFMT_SHIFT (4) /* Bits 4-6: D20-D22 - Interface pixel format */ -#define PCF8833_ST_PIXELFMT_MASK (7 << PCF8833_ST_PIXELFMT_SHIFT) -# define PCF8833_ST_PIXELFMT_8BPS (PCF8833_FMT_8BPS << PCF8833_ST_PIXELFMT_SHIFT) -# define PCF8833_ST_PIXELFMT_12BPS (PCF8833_FMT_12BPS << PCF8833_ST_PIXELFMT_SHIFT) -# define PCF8833_ST_PIXELFMT_16BPS (PCF8833_FMT_16BPS << PCF8833_ST_PIXELFMT_SHIFT) - -/* Byte 3: D15 -- D13 D12 D11 D10 D9 --- */ - -#define PCF8833_ST_TEARING (1 << 1) /* Bit 1: D9 - Tearing effect on */ -#define PCF8833_ST_DISPLAYON (1 << 2) /* Bit 2: D10 - Display on */ -#define PCF8833_ST_PIXELSOFF (1 << 3) /* Bit 3: D11 - All pixels off */ -#define PCF8833_ST_PIXELSON (1 << 4) /* Bit 4: D12 - All pixels on */ -#define PCF8833_ST_INV (1 << 5) /* Bit 5: D13 - Display inversion */ -#define PCF8833_ST_VSCROLL (1 << 7) /* Bit 6: D15 - Vertical scroll mode */ - -/* Byte 4: All zero */ - +/************************************************************************************** + * drivers/lcd/pcf8833.h + * Definitions for the Phillips PCF8833 LCD controller + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: "Data Sheet, PCF8833 STN RGB 132x132x3 driver," Phillips, 2003 Feb 14. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************/ + +#ifndef __DRIVERS_LCD_PCF8833_H +#define __DRIVERS_LCD_PCF8833_H + +/************************************************************************************** + * Included Files + **************************************************************************************/ + +/************************************************************************************** + * Pre-processor Definitions + **************************************************************************************/ +/* Pixel format codes */ + +#define PCF8833_FMT_8BPS (2) +#define PCF8833_FMT_12BPS (3) +#define PCF8833_FMT_16BPS (5) + +/* LCD Commands */ + +#define PCF8833_NOP 0x00 /* No operation; Data: none */ +#define PCF8833_SWRESET 0x01 /* Software reset ; Data: none */ +#define PCF8833_BSTROFF 0x02 /* Booster voltage off; Data: none */ +#define PCF8833_BSTRON 0x03 /* Booster voltage on; Data: none */ +#define PCF8833_RDDIDIF 0x04 /* Read display identification; Data: none */ +#define PCF8833_RDDST 0x09 /* Read display status; Data: none */ +#define PCF8833_SLEEPIN 0x10 /* Sleep_IN; Data: none */ +#define PCF8833_SLEEPOUT 0x11 /* Sleep_OUT; Data: none */ +#define PCF8833_PTLON 0x12 /* Partial mode on; Data: none */ +#define PCF8833_NORON 0x13 /* Normal Display mode on; Data: none */ +#define PCF8833_INVOFF 0x20 /* Display inversion off; Data: none */ +#define PCF8833_INVON 0x21 /* Display inversion on; Data: none */ +#define PCF8833_DALO 0x22 /* All pixel off; Data: none */ +#define PCF8833_DAL 0x23 /* All pixel on; Data: none */ +#define PCF8833_SETCON 0x25 /* Set contrast; Data: (1) contrast */ +#define PCF8833_DISPOFF 0x28 /* Display off; Data: none */ +#define PCF8833_DISPON 0x29 /* Display on; Data: none */ +#define PCF8833_CASET 0x2a /* Column address set; Data: (1) X start (2) X end */ +#define PCF8833_PASET 0x2b /* Page address set Data: (1) Y start (2) Y end */ +#define PCF8833_RAMWR 0x2c /* Memory write; Data: (1) write data */ +#define PCF8833_RGBSET 0x2d /* Colour set; Data: (1-8) red tones, (9-16) green tones, (17-20) blue tones */ +#define PCF8833_PTLAR 0x30 /* Partial area; Data: (1) start address (2) end address */ +#define PCF8833_VSCRDEF 0x33 /* Vertical scroll definition; Data: (1) top fixed, (2) scrol area, (3) bottom fixed */ +#define PCF8833_TEOFF 0x34 /* Tearing line off; Data: none */ +#define PCF8833_TEON 0x35 /* Tearing line on; Data: (1) don't care */ +#define PCF8833_MADCTL 0x36 /* Memory data access control; Data: (1) access control settings */ +#define PCF8833_SEP 0x37 /* Set Scroll Entry Point; Data: (1) scroll entry point */ +#define PCF8833_IDMOFF 0x38 /* Idle mode off; Data: none */ +#define PCF8833_IDMON 0x39 /* Idle mode on; Data: none */ +#define PCF8833_COLMOD 0x3a /* Interface pixel format; Data: (1) color interface format */ +#define PCF8833_SETVOP 0xb0 /* Set VOP; Data: (1) VOP5-8 (2) VOP0-4 */ +#define PCF8833_BRS 0xb4 /* Bottom Row Swap; Data: none */ +#define PCF8833_TRS 0xb6 /* Top Row Swap; Data: none */ +#define PCF8833_FINV 0xb9 /* Super Frame INVersion; Data: none */ +#define PCF8833_DOR 0xba /* Data ORder; Data: none */ +#define PCF8833_TCDFE 0xbd /* Enable/disable DF temp comp; Data: none */ +#define PCF8833_TCVOPE 0xbf /* Enable or disable VOP temp comp; Data: none */ +#define PCF8833_EC 0xc0 /* Internal or external oscillator; Data: none */ +#define PCF8833_SETMUL 0xc2 /* Set multiplication factor; Data: (1) Multiplication factor */ +#define PCF8833_TCVOPAB 0xc3 /* Set TCVOP slopes A and B; Data: (1) SLB and SLA */ +#define PCF8833_TCVOPCD 0xc4 /* Set TCVOP slopes C and D; Data: (1) SLD and SLC */ +#define PCF8833_TCDF 0xc5 /* Set divider frequency; Data: Divider factor in region (1) A (2) B (3) C (4) D */ +#define PCF8833_DF8COLOR 0xc6 /* Set divider frequency 8-colour mode; Data: (1) DF80-6 */ +#define PCF8833_SETBS 0xc7 /* Set bias system; Data: (1) Bias systems */ +#define PCF8833_RDTEMP 0xc8 /* Temperature read back; Data: none */ +#define PCF8833_NLI 0xc9 /* N-Line Inversion; Data: (1) NLI time slots invervsion */ +#define PCF8833_RDID1 0xda /* Read ID1; Data: none */ +#define PCF8833_RDID2 0xdb /* Read ID2; Data: none */ +#define PCF8833_RDID3 0xdc /* Read ID3; Data: none */ +#define PCF8833_SFD 0xef /* Select factory defaults; Data: none */ +#define PCF8833_ECM 0xf0 /* Enter Calibration mode; Data: (1) Calibration control settings */ +#define PCF8833_OTPSHTIN 0xf1 /* Shift data in OTP shift registers; Data: Any number of bytes */ + +/* Memory data access control (MADCTL) bit definitions */ + +#define MADCTL_RGB (1 << 3) /* Bit 3: BGR */ +#define MADCTL_LAO (1 << 4) /* Bit 4: Line address order bottom to top */ +#define MADCTL_V (1 << 5) /* Bit 5: Vertical RAM write; in Y direction */ +#define MADCTL_MX (1 << 6) /* Bit 6: Mirror X */ +#define MADCTL_MY (1 << 7) /* Bit 7: Mirror Y */ + +/* PCF8833 status register bit definitions */ +/* CMD format: RDDST command followed by four status bytes: */ +/* Byte 1: D31 d30 D29 D28 D27 D26 --- --- */ + +#define PCF8833_ST_RGB (1 << 2) /* Bit 2: D26 - RGB/BGR order */ +#define PCF8833_ST_LINEADDR (1 << 3) /* Bit 3: D27 - Line address order */ +#define PCF8833_ST_ADDRMODE (1 << 4) /* Bit 4: D28 - Vertical/horizontal addressing mode */ +#define PCF8833_ST_XADDR (1 << 5) /* Bit 5: D29 - X address order */ +#define PCF8833_ST_YADDR (1 << 6) /* Bit 6: D30 - Y address order */ +#define PCF8833_ST_BOOSTER (1 << 7) /* Bit 7: D31 - Booster voltage status */ + +/* Byte 2: --- D22 D21 D20 D19 D18 D17 D16 */ + +#define PCF8833_ST_NORMAL (1 << 0) /* Bit 0: D16 - Normal display mode */ +#define PCF8833_ST_SLEEPIN (1 << 1) /* Bit 1: D17 - Sleep in selected */ +#define PCF8833_ST_PARTIAL (1 << 2) /* Bit 2: D18 - Partial mode on */ +#define PCF8833_ST_IDLE (1 << 3) /* Bit 3: D19 - Idle mode selected */ +#define PCF8833_ST_PIXELFMT_SHIFT (4) /* Bits 4-6: D20-D22 - Interface pixel format */ +#define PCF8833_ST_PIXELFMT_MASK (7 << PCF8833_ST_PIXELFMT_SHIFT) +# define PCF8833_ST_PIXELFMT_8BPS (PCF8833_FMT_8BPS << PCF8833_ST_PIXELFMT_SHIFT) +# define PCF8833_ST_PIXELFMT_12BPS (PCF8833_FMT_12BPS << PCF8833_ST_PIXELFMT_SHIFT) +# define PCF8833_ST_PIXELFMT_16BPS (PCF8833_FMT_16BPS << PCF8833_ST_PIXELFMT_SHIFT) + +/* Byte 3: D15 -- D13 D12 D11 D10 D9 --- */ + +#define PCF8833_ST_TEARING (1 << 1) /* Bit 1: D9 - Tearing effect on */ +#define PCF8833_ST_DISPLAYON (1 << 2) /* Bit 2: D10 - Display on */ +#define PCF8833_ST_PIXELSOFF (1 << 3) /* Bit 3: D11 - All pixels off */ +#define PCF8833_ST_PIXELSON (1 << 4) /* Bit 4: D12 - All pixels on */ +#define PCF8833_ST_INV (1 << 5) /* Bit 5: D13 - Display inversion */ +#define PCF8833_ST_VSCROLL (1 << 7) /* Bit 6: D15 - Vertical scroll mode */ + +/* Byte 4: All zero */ + #endif /* __DRIVERS_LCD_PCF8833_H */ \ No newline at end of file diff --git a/drivers/lcd/s1d15g10.h b/drivers/lcd/s1d15g10.h index df2dd8be27e00b9ccdbb9b6536e2fe53be87a33a..9b5f7738fe2b09b0334aecde1f68ac633a5d51b2 100644 --- a/drivers/lcd/s1d15g10.h +++ b/drivers/lcd/s1d15g10.h @@ -1,141 +1,141 @@ -/************************************************************************************** - * drivers/lcd/s1d15g10.h - * Definitions for the Epson S1D15G0 LCD controller - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * References: S1D15G0D08B000, Seiko Epson Corportation, 2002. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************/ - -#ifndef __DRIVERS_LCD_S1D15G10_H -#define __DRIVERS_LCD_S1D15G10_H - -/************************************************************************************** - * Included Files - **************************************************************************************/ - -/************************************************************************************** - * Pre-processor Definitions - **************************************************************************************/ - -/* Epson S1D15G10 Command Set */ - -#define S1D15G10_DISON 0xaf /* Display on; Data: none */ -#define S1D15G10_DISOFF 0xae /* Display off; Data: none */ -#define S1D15G10_DISNOR 0xa6 /* Normal display; Data: none */ -#define S1D15G10_DISINV 0xa7 /* Inverse display; Data: none */ -#define S1D15G10_COMSCN 0xbb /* Common scan direction; Data: (1) common scan direction */ -#define S1D15G10_DISCTL 0xca /* Display control; Data: Data: (1) CL div, F1/2 pat, (2) duty, (3) FR inverse (4) dispersion */ -#define S1D15G10_SLPIN 0x95 /* Sleep in; Data: none */ -#define S1D15G10_SLPOUT 0x94 /* Sleep out; Data: none */ -#define S1D15G10_PASET 0x75 /* Page address set; Data: (1) start page, (2) end page */ -#define S1D15G10_CASET 0x15 /* Column address set; Data: (1) start addr, (2) end addr */ -#define S1D15G10_DATCTL 0xbc /* Data scan direction, etc.; Data: (1) inverse, scan dir (2) RGB, (3) gray-scale */ -#define S1D15G10_RGBSET8 0xce /* 256-color position set; Data: (1-8) red tones, (9-16) green tones, (17-20) blue tones */ -#define S1D15G10_RAMWR 0x5c /* Writing to memory; Data: (1) write data */ -#define S1D15G10_RAMRD 0x5d /* Reading from memory; Data: (1) read data */ -#define S1D15G10_PTLIN 0xa8 /* Partial display in; Data: (1) start addr, (2) end addr */ -#define S1D15G10_PTLOUT 0xa9 /* Partial display out; Data: none */ -#define S1D15G10_RMWIN 0xe0 /* Read and modify write; Data: none */ -#define S1D15G10_RMWOUT 0xee /* End; Data: none */ -#define S1D15G10_ASCSET 0xaa /* Area scroll set; Data: (1) top addr, (2) bottom addr, (3) Num blocks, (4) scroll mode */ -#define S1D15G10_SCSTART 0xab /* Scroll start set; Data: (1) start block addr */ -#define S1D15G10_OSCON 0xd1 /* Internal oscillation on; Data: none */ -#define S1D15G10_OSCOFF 0xd2 /* Internal oscillation off; Data: none */ -#define S1D15G10_PWRCTR 0x20 /* Power control; Data: (1) LCD drive power */ -#define S1D15G10_VOLCTR 0x81 /* Electronic volume control; Data: (1) volume value, (2) resistance ratio */ -#define S1D15G10_VOLUP 0xd6 /* Increment electronic control by 1; Data: none */ -#define S1D15G10_VOLDOWN 0xd7 /* Decrement electronic control by 1; Data: none */ -#define S1D15G10_TMPGRD 0x82 /* Temperature gradient set; Data: (1-14) temperature gradient */ -#define S1D15G10_EPCTIN 0xcd /* Control EEPROM; Data: (1) read/write */ -#define S1D15G10_EPCOUT 0xcc /* Cancel EEPROM control; Data: none */ -#define S1D15G10_EPMWR 0xfc /* Write into EEPROM; Data: none */ -#define S1D15G10_EPMRD 0xfd /* Read from EEPROM; Data: none */ -#define S1D15G10_EPSRRD1 0x7c /* Read register 1; Data: none */ -#define S1D15G10_EPSRRD2 0x7d /* Read regiser 2; Data: none */ -#define S1D15G10_NOP 0x25 /* NOP intruction (0x45?); Data: none */ -#define S1D15G10_STREAD 0x20 /* Status read; Data: none */ - -/* Display control (DISCTL) bit definitions */ - -#define DISCTL_PERIOD_SHIFT (0) /* P1: Bits 0-1, F1 and F2 drive-pattern switching period */ -#define DISCTL_PERIOD_MASK (3 << DISCTL_PERIOD_SHIFT) -# define DISCTL_PERIOD_8 (0 << DISCTL_PERIOD_SHIFT) -# define DISCTL_PERIOD_4 (1 << DISCTL_PERIOD_SHIFT) -# define DISCTL_PERIOD_16 (2 << DISCTL_PERIOD_SHIFT) -# define DISCTL_PERIOD_FLD (3 << DISCTL_PERIOD_SHIFT) -#define DISCTL_CLDIV_SHIFT (2) /* P1: Bits 2-4, Clock divider */ -#define DISCTL_CLDIV_MASK (7 << DISCTL_CLDIV_SHIFT) -# define DISCTL_CLDIV_2 (0 << DISCTL_CLDIV_SHIFT) -# define DISCTL_CLDIV_4 (1 << DISCTL_CLDIV_SHIFT) -# define DISCTL_CLDIV_8 (2 << DISCTL_CLDIV_SHIFT) -# define DISCTL_CLDIV_NONE (3 << DISCTL_CLDIV_SHIFT) - -/* Power control (PWRCTR) bit definitions */ - -#define PWCTR_REFVOLTAGE (1 << 0) /* P1: Bit 0, Turn on reference voltage generation circuit. */ -#define PWCTR_REGULATOR (1 << 1) /* P1: Bit 1, Turn on voltage regulator and circuit voltage follower. */ -#define PWCTR_BOOSTER2 (1 << 2) /* P1: Bit 2, Turn on secondary booster/step-down circuit. */ -#define PWCTR_BOOSTER1 (1 << 3) /* P1: Bit 3, Turn on primary booster circuit. */ -#define PWCTR_EXTR (1 << 4) /* P1: Bit 4, Use external resistance to adjust voltage. */ - -/* Data control (DATCTL) bit definitions */ - -#define DATCTL_PGADDR_INV (1 << 0) /* P1: Bit 0, Inverse display of the page address. */ -#define DATCTL_COLADDR_REV (1 << 1) /* P1: Bit 1, Reverse turn of column address. */ -#define DATCTL_ADDR_PGDIR (1 << 2) /* P1: Bit 2, Address-scan direction in page (vs column) direction. */ - -#define DATCTL_BGR (1 << 0) /* P2: Bit0, RGB->BGR */ - -#define DATCTL_8GRAY (1) /* P3: Bits 0-2 = 001, 8 gray-scale */ -#define DATCTL_16GRAY_A (2) /* P3: Bits 0-2 = 010, 16 gray-scale display type A */ -#define DATCTL_16GRAY_B (4) /* P3: Bits 0-2 = 100, 16 gray-scale display type B */ - -/* Status register bit definions (after reset or NOP) */ - -#define S1D15G10_SR_PARTIAL (1 << 0) /* Bit 0: Partial display */ -#define S1D15G10_SR_NORMAL (1 << 1) /* Bit 1: Normal (vs. inverse) display */ -#define S1D15G10_SR_EEPROM (1 << 2) /* Bit 2: EEPROM access */ -#define S1D15G10_SR_DISPON (1 << 3) /* Bit 3: Display on */ -#define S1D15G10_SR_COLSCAN (1 << 4) /* Bit 4: Column (vs. page) scan direction */ -#define S1D15G10_SR_RMW (1 << 5) /* Bit 5: Read modify write */ -#define S1D15G10_SR_SCROLL (3 << 6) /* Bits 6-7: Area scroll mode */ - -/* Status register bit definions (after EPSRRD1) */ - -#define S1D15G10_SR_VOLUME 0x3f /* Bits 0-5: Electronic volume control values */ - -/* Status register bit definions (after EPSRRD2) */ - -#define S1D15G10_SR_RRATIO 0x07 /* Bits 0-2: Built-in resistance ratio */ - +/************************************************************************************** + * drivers/lcd/s1d15g10.h + * Definitions for the Epson S1D15G0 LCD controller + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: S1D15G0D08B000, Seiko Epson Corportation, 2002. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************/ + +#ifndef __DRIVERS_LCD_S1D15G10_H +#define __DRIVERS_LCD_S1D15G10_H + +/************************************************************************************** + * Included Files + **************************************************************************************/ + +/************************************************************************************** + * Pre-processor Definitions + **************************************************************************************/ + +/* Epson S1D15G10 Command Set */ + +#define S1D15G10_DISON 0xaf /* Display on; Data: none */ +#define S1D15G10_DISOFF 0xae /* Display off; Data: none */ +#define S1D15G10_DISNOR 0xa6 /* Normal display; Data: none */ +#define S1D15G10_DISINV 0xa7 /* Inverse display; Data: none */ +#define S1D15G10_COMSCN 0xbb /* Common scan direction; Data: (1) common scan direction */ +#define S1D15G10_DISCTL 0xca /* Display control; Data: Data: (1) CL div, F1/2 pat, (2) duty, (3) FR inverse (4) dispersion */ +#define S1D15G10_SLPIN 0x95 /* Sleep in; Data: none */ +#define S1D15G10_SLPOUT 0x94 /* Sleep out; Data: none */ +#define S1D15G10_PASET 0x75 /* Page address set; Data: (1) start page, (2) end page */ +#define S1D15G10_CASET 0x15 /* Column address set; Data: (1) start addr, (2) end addr */ +#define S1D15G10_DATCTL 0xbc /* Data scan direction, etc.; Data: (1) inverse, scan dir (2) RGB, (3) gray-scale */ +#define S1D15G10_RGBSET8 0xce /* 256-color position set; Data: (1-8) red tones, (9-16) green tones, (17-20) blue tones */ +#define S1D15G10_RAMWR 0x5c /* Writing to memory; Data: (1) write data */ +#define S1D15G10_RAMRD 0x5d /* Reading from memory; Data: (1) read data */ +#define S1D15G10_PTLIN 0xa8 /* Partial display in; Data: (1) start addr, (2) end addr */ +#define S1D15G10_PTLOUT 0xa9 /* Partial display out; Data: none */ +#define S1D15G10_RMWIN 0xe0 /* Read and modify write; Data: none */ +#define S1D15G10_RMWOUT 0xee /* End; Data: none */ +#define S1D15G10_ASCSET 0xaa /* Area scroll set; Data: (1) top addr, (2) bottom addr, (3) Num blocks, (4) scroll mode */ +#define S1D15G10_SCSTART 0xab /* Scroll start set; Data: (1) start block addr */ +#define S1D15G10_OSCON 0xd1 /* Internal oscillation on; Data: none */ +#define S1D15G10_OSCOFF 0xd2 /* Internal oscillation off; Data: none */ +#define S1D15G10_PWRCTR 0x20 /* Power control; Data: (1) LCD drive power */ +#define S1D15G10_VOLCTR 0x81 /* Electronic volume control; Data: (1) volume value, (2) resistance ratio */ +#define S1D15G10_VOLUP 0xd6 /* Increment electronic control by 1; Data: none */ +#define S1D15G10_VOLDOWN 0xd7 /* Decrement electronic control by 1; Data: none */ +#define S1D15G10_TMPGRD 0x82 /* Temperature gradient set; Data: (1-14) temperature gradient */ +#define S1D15G10_EPCTIN 0xcd /* Control EEPROM; Data: (1) read/write */ +#define S1D15G10_EPCOUT 0xcc /* Cancel EEPROM control; Data: none */ +#define S1D15G10_EPMWR 0xfc /* Write into EEPROM; Data: none */ +#define S1D15G10_EPMRD 0xfd /* Read from EEPROM; Data: none */ +#define S1D15G10_EPSRRD1 0x7c /* Read register 1; Data: none */ +#define S1D15G10_EPSRRD2 0x7d /* Read regiser 2; Data: none */ +#define S1D15G10_NOP 0x25 /* NOP intruction (0x45?); Data: none */ +#define S1D15G10_STREAD 0x20 /* Status read; Data: none */ + +/* Display control (DISCTL) bit definitions */ + +#define DISCTL_PERIOD_SHIFT (0) /* P1: Bits 0-1, F1 and F2 drive-pattern switching period */ +#define DISCTL_PERIOD_MASK (3 << DISCTL_PERIOD_SHIFT) +# define DISCTL_PERIOD_8 (0 << DISCTL_PERIOD_SHIFT) +# define DISCTL_PERIOD_4 (1 << DISCTL_PERIOD_SHIFT) +# define DISCTL_PERIOD_16 (2 << DISCTL_PERIOD_SHIFT) +# define DISCTL_PERIOD_FLD (3 << DISCTL_PERIOD_SHIFT) +#define DISCTL_CLDIV_SHIFT (2) /* P1: Bits 2-4, Clock divider */ +#define DISCTL_CLDIV_MASK (7 << DISCTL_CLDIV_SHIFT) +# define DISCTL_CLDIV_2 (0 << DISCTL_CLDIV_SHIFT) +# define DISCTL_CLDIV_4 (1 << DISCTL_CLDIV_SHIFT) +# define DISCTL_CLDIV_8 (2 << DISCTL_CLDIV_SHIFT) +# define DISCTL_CLDIV_NONE (3 << DISCTL_CLDIV_SHIFT) + +/* Power control (PWRCTR) bit definitions */ + +#define PWCTR_REFVOLTAGE (1 << 0) /* P1: Bit 0, Turn on reference voltage generation circuit. */ +#define PWCTR_REGULATOR (1 << 1) /* P1: Bit 1, Turn on voltage regulator and circuit voltage follower. */ +#define PWCTR_BOOSTER2 (1 << 2) /* P1: Bit 2, Turn on secondary booster/step-down circuit. */ +#define PWCTR_BOOSTER1 (1 << 3) /* P1: Bit 3, Turn on primary booster circuit. */ +#define PWCTR_EXTR (1 << 4) /* P1: Bit 4, Use external resistance to adjust voltage. */ + +/* Data control (DATCTL) bit definitions */ + +#define DATCTL_PGADDR_INV (1 << 0) /* P1: Bit 0, Inverse display of the page address. */ +#define DATCTL_COLADDR_REV (1 << 1) /* P1: Bit 1, Reverse turn of column address. */ +#define DATCTL_ADDR_PGDIR (1 << 2) /* P1: Bit 2, Address-scan direction in page (vs column) direction. */ + +#define DATCTL_BGR (1 << 0) /* P2: Bit0, RGB->BGR */ + +#define DATCTL_8GRAY (1) /* P3: Bits 0-2 = 001, 8 gray-scale */ +#define DATCTL_16GRAY_A (2) /* P3: Bits 0-2 = 010, 16 gray-scale display type A */ +#define DATCTL_16GRAY_B (4) /* P3: Bits 0-2 = 100, 16 gray-scale display type B */ + +/* Status register bit definions (after reset or NOP) */ + +#define S1D15G10_SR_PARTIAL (1 << 0) /* Bit 0: Partial display */ +#define S1D15G10_SR_NORMAL (1 << 1) /* Bit 1: Normal (vs. inverse) display */ +#define S1D15G10_SR_EEPROM (1 << 2) /* Bit 2: EEPROM access */ +#define S1D15G10_SR_DISPON (1 << 3) /* Bit 3: Display on */ +#define S1D15G10_SR_COLSCAN (1 << 4) /* Bit 4: Column (vs. page) scan direction */ +#define S1D15G10_SR_RMW (1 << 5) /* Bit 5: Read modify write */ +#define S1D15G10_SR_SCROLL (3 << 6) /* Bits 6-7: Area scroll mode */ + +/* Status register bit definions (after EPSRRD1) */ + +#define S1D15G10_SR_VOLUME 0x3f /* Bits 0-5: Electronic volume control values */ + +/* Status register bit definions (after EPSRRD2) */ + +#define S1D15G10_SR_RRATIO 0x07 /* Bits 0-2: Built-in resistance ratio */ + #endif /* __DRIVERS_LCD_S1D15G10_H */ \ No newline at end of file diff --git a/drivers/lcd/skeleton.c b/drivers/lcd/skeleton.c index 1cb8b5955bcee7521a039b27091de6c1fec74eca..83aa92018c58708e25b9c586fac07336508c8dd8 100644 --- a/drivers/lcd/skeleton.c +++ b/drivers/lcd/skeleton.c @@ -2,7 +2,7 @@ * drivers/lcd/skeleton.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/lcd/ssd1305.h b/drivers/lcd/ssd1305.h index 87c955de4d0545f7fd1cf1ae6515beeb41c570ce..34678fa80d6182ba6fa40a48b91b301e6c7bce87 100644 --- a/drivers/lcd/ssd1305.h +++ b/drivers/lcd/ssd1305.h @@ -1,211 +1,211 @@ -/************************************************************************************** - * drivers/lcd/ssd1305.h - * Definitions for the Solomon Systech SSD1305 132x64 Dot Matrix OLED/PLED - * Segment/Common Driver with C - * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * References: SSD1305.pdf, "Solomon Systech SSD1305 132x64 Dot Matrix OLED/PLED - * Segment/Common Driver with Controller," Solomon Systech Limited, - * http://www.solomon-systech.com, May, 2008. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************/ - -#ifndef __DRIVERS_LCD_SSD1305_H -#define __DRIVERS_LCD_SSD1305_H - -/************************************************************************************** - * Included Files - **************************************************************************************/ - -/************************************************************************************** - * Pre-processor Definitions - **************************************************************************************/ -/* General Definitions ******************************************************/ - -#define SSD1305_COLORA 0 -#define SSD1305_COLORB 1 -#define SSD1305_COLORC 2 -#define SSD1305_COLORD 3 - -/* Fundamental Commands *****************************************************/ -#define SSD1305_SETCOLL 0x00 /* 0x00-0x0f: Set lower column address */ -# define SSD1305_COLL_MASK 0x0f -#define SSD1305_SETCOLH 0x10 /* 0x10-0x1f: Set higher column address */ -# define SSD1305_COLH_MASK 0x0f -#define SSD1305_ADDRMODE 0x20 /* 0x20: Set memory address mode */ -# define SSD1305_ADDRMODE_HOR 0x00 /* Data 1: Set horizontal address mode */ -# define SSD1305_ADDRMODE_VIRT 0x01 /* Data 1: Set virtal address mode */ -# define SSD1305_ADDRMODE_PAGE 0x02 /* Data 1: Set page address mode */ -#define SSD1305_SETCOLADDR 0x21 /* 0x21: Set column address */ - /* Data 1: Column start address: 0-131 */ - /* Data 2: Column end address: 0-131 */ -#define SSD1305_SETPAGEADDR 0x22 /* 0x22: Set page address */ - /* Data 1: Page start address: 0x00-0x7d */ - /* Data 2: Page end address: 0x00-0x7d */ -#define SSD1305_SETSTARTLINE 0x40 /* 0x40-7f: Set display start line */ -# define SSD1305_STARTLINE_MASK 0x3f - -#define SSD1305_SETCONTRAST 0x81 /* 0x81: Set contrast control */ - /* Data 1: Set 1 of 256 contrast steps */ -#define SSD1305_SETBRIGHTNESS 0x82 /* 0x82: Set brightness */ - /* Data 1: Set 1 of 256 contrast steps */ -#define SSD1305_SETLUT 0x91 /* 0x01: Set lookup table */ - /* Data 1: Pulse width: 31-63 */ - /* Data 2: Color A: 31-63 */ - /* Data 3: Color B: 31-63 */ - /* Data 4: Color C: 31-63 */ -#define SSD1305_SETBANKCOLOR1 0x92 /* 0x92: Set bank 1-16 color */ -# define SSD1305_SETBANK1(c) (c) /* Data 1, Bits 0-1: Bank 1 color */ -# define SSD1305_SETBANK2(c) (c << 2) /* Data 1, Bits 2-3: Bank 2 color */ -# define SSD1305_SETBANK3(c) (c << 4) /* Data 1, Bits 4-5: Bank 3 color */ -# define SSD1305_SETBANK4(c) (c << 6) /* Data 1, Bits 6-7: Bank 4 color */ -# define SSD1305_SETBANK5(c) (c) /* Data 2, Bits 0-1: Bank 5 color */ -# define SSD1305_SETBANK6(c) (c << 2) /* Data 2, Bits 2-3: Bank 6 color */ -# define SSD1305_SETBANK7(c) (c << 4) /* Data 2, Bits 4-5: Bank 7 color */ -# define SSD1305_SETBANK8(c) (c << 6) /* Data 2, Bits 6-7: Bank 8 color */ -# define SSD1305_SETBANK9(c) (c) /* Data 3, Bits 0-1: Bank 9 color */ -# define SSD1305_SETBANK10(c) (c << 2) /* Data 3, Bits 2-3: Bank 10 color */ -# define SSD1305_SETBANK11(c) (c << 4) /* Data 3, Bits 4-5: Bank 11 color */ -# define SSD1305_SETBANK12(c) (c << 6) /* Data 3, Bits 6-7: Bank 12 color */ -# define SSD1305_SETBANK13(c) (c) /* Data 4, Bits 0-1: Bank 13 color */ -# define SSD1305_SETBANK14(c) (c << 2) /* Data 4, Bits 2-3: Bank 14 color */ -# define SSD1305_SETBANK15(c) (c << 4) /* Data 4, Bits 4-5: Bank 15 color */ -# define SSD1305_SETBANK16(c) (c << 6) /* Data 4, Bits 6-7: Bank 16 color */ -#define SSD1305_SETBANKCOLOR2 0x93 /* 0x93: Set bank 17-32 color */ -# define SSD1305_SETBANK17(c) (c) /* Data 1, Bits 0-1: Bank 17 color */ -# define SSD1305_SETBANK18(c) (c << 2) /* Data 1, Bits 2-3: Bank 18 color */ -# define SSD1305_SETBANK19(c) (c << 4) /* Data 1, Bits 4-5: Bank 19 color */ -# define SSD1305_SETBANK20(c) (c << 6) /* Data 1, Bits 6-7: Bank 20 color */ -# define SSD1305_SETBANK21(c) (c) /* Data 2, Bits 0-1: Bank 21 color */ -# define SSD1305_SETBANK22(c) (c << 2) /* Data 2, Bits 2-3: Bank 22 color */ -# define SSD1305_SETBANK23(c) (c << 4) /* Data 2, Bits 4-5: Bank 23 color */ -# define SSD1305_SETBANK24(c) (c << 6) /* Data 2, Bits 6-7: Bank 24 color */ -# define SSD1305_SETBANK25(c) (c) /* Data 3, Bits 0-1: Bank 25 color */ -# define SSD1305_SETBANK26(c) (c << 2) /* Data 3, Bits 2-3: Bank 26 color */ -# define SSD1305_SETBANK27(c) (c << 4) /* Data 3, Bits 4-5: Bank 27 color */ -# define SSD1305_SETBANK28(c) (c << 6) /* Data 3, Bits 6-7: Bank 28 color */ -# define SSD1305_SETBANK29(c) (c) /* Data 4, Bits 0-1: Bank 29 color */ -# define SSD1305_SETBANK30(c) (c << 2) /* Data 4, Bits 2-3: Bank 30 color */ -# define SSD1305_SETBANK31(c) (c << 4) /* Data 4, Bits 4-5: Bank 31 color */ -# define SSD1305_SETBANK32(c) (c << 6) /* Data 4, Bits 6-7: Bank 32 color */ -#define SSD1305_MAPCOL0 0xa0 /* 0xa0: Column address 0 is mapped to SEG0 */ -#define SSD1305_MAPCOL131 0xa1 /* 0xa1: Column address 131 is mapped to SEG0 */ -#define SSD1305_DISPRAM 0xa4 /* 0xa4: Resume to RAM content display */ -#define SSD1305_DISPENTIRE 0xa5 /* 0xa5: Entire display ON */ -#define SSD1305_DISPNORMAL 0xa6 /* 0xa6: Normal display */ -#define SSD1305_DISPINVERTED 0xa7 /* 0xa7: Inverse display */ - -#define SSD1305_SETMUX 0xa8 /* 0xa8: Set Multiplex Ratio*/ - /* Data 1: MUX ratio -1: 15-63 */ -#define SSD1305_DIMMODE 0xab /* 0xab: Dim mode setting */ - /* Data 1: Reserverd, must be zero */ - /* Data 2: Contrast for bank1: 0-255 */ - /* Data 3: Brightness for color bank: 0-255 */ -#define SSD1305_MSTRCONFIG 0xad /* 0xad: Master configuration */ -# define SSD1305_MSTRCONFIG_EXTVCC 0x8e /* Data 1: Select external Vcc */ -#define SSD1305_DISPONDIM 0xac /* 0xac: Display ON in dim mode */ -#define SSD1305_DISPOFF 0xae /* 0xae: Display OFF (sleep mode) */ -#define SSD1305_DISPON 0xaf /* 0xaf: Display ON in normal mode */ -#define SSD1305_SETPAGESTART 0xb0 /* 0xb0-b7: Set page start address */ -# define SSD1305_PAGESTART_MASK 0x07 -#define SSD1305_SETCOMNORMAL 0xc0 /* 0xc0: Set COM output, normal mode */ -#define SSD1305_SETCOMREMAPPED 0xc8 /* 0xc8: Set COM output, remapped mode */ - -#define SSD1305_SETOFFSET 0xd3 /* 0xd3: Set display offset */ - /* Data 1: Vertical shift by COM: 0-63 */ -#define SSD1305_SETDCLK 0xd5 /* 0xd5: Set display clock divide ratio/oscillator */ -# define SSD1305_DCLKDIV_SHIFT (0) /* Data 1, Bits 0-3: DCLK divide ratio/frequency*/ -# define SSD1305_DCLKDIV_MASK 0x0f -# define SSD1305_DCLKFREQ_SHIFT (4) /* Data 1, Bits 4-7: DCLK divide oscillator frequency */ -# define SSD1305_DCLKFREQ_MASK 0xf0 -#define SSD1305_SETCOLORMODE 0xd8 /* 0xd: Set area color and low power display modes */ -# define SSD1305_COLORMODE_MONO 0x00 /* Data 1, Bits 4-5: 00=monochrome */ -# define SSD1305_COLORMODE_COLOR 0x30 /* Data 1, Bits 4-5: 11=area color enable */ -# define SSD1305_POWERMODE_NORMAL 0x00 /* Data 1, Bits 0,2: 00=normal power mode */ -# define SSD1305_POWERMODE_LOW 0x05 /* Data 1, Bits 0,2: 11=low power display mode */ -#define SSD1305_SETPRECHARGE 0xd9 /* 0xd9: Set pre-charge period */ -# define SSD1305_PHASE1_SHIFT (0) /* Data 1, Bits 0-3: Phase 1 period of up to 15 DCLK clocks */ -# define SSD1305_PHASE1_MASK 0x0f -# define SSD1305_PHASE2_SHIFT (4) /* Data 1, Bits 4-7: Phase 2 period of up to 15 DCLK clocks */ -# define SSD1305_PHASE2_MASK 0xf0 -#define SSD1305_SETCOMCONFIG 0xda /* 0xda: Set COM configuration */ -# define SSD1305_COMCONFIG_SEQ 0x02 /* Data 1, Bit 4: 0=Sequential COM pin configuration */ -# define SSD1305_COMCONFIG_ALT 0x12 /* Data 1, Bit 4: 1=Alternative COM pin configuration */ -# define SSD1305_COMCONFIG_NOREMAP 0x02 /* Data 1, Bit 5: 0=Disable COM Left/Right remap */ -# define SSD1305_COMCONFIG_REMAP 0x22 /* Data 1, Bit 5: 1=Enable COM Left/Right remap */ -#define SSD1305_SETVCOMHDESEL 0xdb /* 0xdb: Set VCOMH delselect level */ -# define SSD1305_VCOMH_x4p3 0x00 /* Data 1: ~0.43 x Vcc */ -# define SSD1305_VCOMH_x7p7 0x34 /* Data 1: ~0.77 x Vcc */ -# define SSD1305_VCOMH_x8p3 0x3c /* Data 1: ~0.83 x Vcc */ -#define SSD1305_ENTER_RMWMODE 0xe0 /* 0xe0: Enter the Read Modify Write mode */ -#define SSD1305_NOP 0xe3 /* 0xe3: NOP Command for no operation */ -#define SSD1305_EXIT_RMWMODE 0xee /* 0xee: Leave the Read Modify Write mode */ - -/* Graphic Acceleration Commands ********************************************/ - -#define SSD1305_HSCROLL_RIGHT 0x26 /* 0x26: Right horizontal scroll */ -#define SSD1305_HSCROLL_LEFT 0x27 /* 0x27: Left horizontal scroll */ - /* Data 1, Bits 0-2: Column scroll offset: 0-4 */ - /* Data 2, Bits 0-2: Start page address: 0-7 */ -#define SSD1305_HSCROLL_FRAMES6 0x00 /* Data 3, Bits 0-2: Timer interval, 000=6 frames */ -#define SSD1305_HSCROLL_FRAMES32 0x01 /* Data 3, Bits 0-2: Timer interval, 001=32 frames */ -#define SSD1305_HSCROLL_FRAMES64 0x02 /* Data 3, Bits 0-2: Timer interval, 010=64 frames */ -#define SSD1305_HSCROLL_FRAMES128 0x03 /* Data 3, Bits 0-2: Timer interval, 011=128 frames */ -#define SSD1305_HSCROLL_FRAMES3 0x04 /* Data 3, Bits 0-2: Timer interval, 100=3 frames */ -#define SSD1305_HSCROLL_FRAMES4 0x05 /* Data 3, Bits 0-2: Timer interval, 101=4 frames */ -#define SSD1305_HSCROLL_FRAMES2 0x06 /* Data 3, Bits 0-2: Timer interval, 110=2 frames */ - /* Data 4, Bits 0-2: End page address: 0-7 */ - -#define SSD1305_VSCROLL_RIGHT 0x29 /* 0x26: Vertical and right horizontal scroll */ -#define SSD1305_VSCROLL_LEFT 0x2a /* 0x27: Vertical and left horizontal scroll */ - /* Data 1, Bits 0-2: Column scroll offset: 0-4 */ - /* Data 2, Bits 0-2: Start page address: 0-7 */ -#define SSD1305_VSCROLL_FRAMES6 0x00 /* Data 3, Bits 0-2: Timer interval, 000=6 frames */ -#define SSD1305_VSCROLL_FRAMES32 0x01 /* Data 3, Bits 0-2: Timer interval, 001=32 frames */ -#define SSD1305_VSCROLL_FRAMES64 0x02 /* Data 3, Bits 0-2: Timer interval, 010=64 frames */ -#define SSD1305_VSCROLL_FRAMES128 0x03 /* Data 3, Bits 0-2: Timer interval, 011=128 frames */ -#define SSD1305_VSCROLL_FRAMES3 0x04 /* Data 3, Bits 0-2: Timer interval, 100=3 frames */ -#define SSD1305_VSCROLL_FRAMES4 0x05 /* Data 3, Bits 0-2: Timer interval, 101=4 frames */ -#define SSD1305_VSCROLL_FRAMES2 0x06 /* Data 3, Bits 0-2: Timer interval, 110=2 frames */ - /* Data 4, Bits 0-2: End page address: 0-7 */ - /* Data 5, Bits 0-5: Vertical scrolling offset: 0-63 */ -#define SSD1305_SCROLL_STOP 0x2e /* 0x2e: Deactivate scroll */ -#define SSD1305_SCROLL_START 0x2f /* 0x2f: Activate scroll */ -#define SSD1305_VSCROLL_AREA 0xa3 /* 0xa3: Set vertical scroll area */ - /* Data 1: Number of rows in the top fixed area */ - /* Data 1: Number of rows in the scroll area */ - -/* Status register bit definitions ******************************************/ - -#define SSD1305_STATUS_DISPOFF (1 << 6) /* Bit 6: 1=Display off */ - -#endif /* __DRIVERS_LCD_SSD1305_H */ +/************************************************************************************** + * drivers/lcd/ssd1305.h + * Definitions for the Solomon Systech SSD1305 132x64 Dot Matrix OLED/PLED + * Segment/Common Driver with C + * + * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: SSD1305.pdf, "Solomon Systech SSD1305 132x64 Dot Matrix OLED/PLED + * Segment/Common Driver with Controller," Solomon Systech Limited, + * http://www.solomon-systech.com, May, 2008. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************************/ + +#ifndef __DRIVERS_LCD_SSD1305_H +#define __DRIVERS_LCD_SSD1305_H + +/************************************************************************************** + * Included Files + **************************************************************************************/ + +/************************************************************************************** + * Pre-processor Definitions + **************************************************************************************/ +/* General Definitions ******************************************************/ + +#define SSD1305_COLORA 0 +#define SSD1305_COLORB 1 +#define SSD1305_COLORC 2 +#define SSD1305_COLORD 3 + +/* Fundamental Commands *****************************************************/ +#define SSD1305_SETCOLL 0x00 /* 0x00-0x0f: Set lower column address */ +# define SSD1305_COLL_MASK 0x0f +#define SSD1305_SETCOLH 0x10 /* 0x10-0x1f: Set higher column address */ +# define SSD1305_COLH_MASK 0x0f +#define SSD1305_ADDRMODE 0x20 /* 0x20: Set memory address mode */ +# define SSD1305_ADDRMODE_HOR 0x00 /* Data 1: Set horizontal address mode */ +# define SSD1305_ADDRMODE_VIRT 0x01 /* Data 1: Set virtal address mode */ +# define SSD1305_ADDRMODE_PAGE 0x02 /* Data 1: Set page address mode */ +#define SSD1305_SETCOLADDR 0x21 /* 0x21: Set column address */ + /* Data 1: Column start address: 0-131 */ + /* Data 2: Column end address: 0-131 */ +#define SSD1305_SETPAGEADDR 0x22 /* 0x22: Set page address */ + /* Data 1: Page start address: 0x00-0x7d */ + /* Data 2: Page end address: 0x00-0x7d */ +#define SSD1305_SETSTARTLINE 0x40 /* 0x40-7f: Set display start line */ +# define SSD1305_STARTLINE_MASK 0x3f + +#define SSD1305_SETCONTRAST 0x81 /* 0x81: Set contrast control */ + /* Data 1: Set 1 of 256 contrast steps */ +#define SSD1305_SETBRIGHTNESS 0x82 /* 0x82: Set brightness */ + /* Data 1: Set 1 of 256 contrast steps */ +#define SSD1305_SETLUT 0x91 /* 0x01: Set lookup table */ + /* Data 1: Pulse width: 31-63 */ + /* Data 2: Color A: 31-63 */ + /* Data 3: Color B: 31-63 */ + /* Data 4: Color C: 31-63 */ +#define SSD1305_SETBANKCOLOR1 0x92 /* 0x92: Set bank 1-16 color */ +# define SSD1305_SETBANK1(c) (c) /* Data 1, Bits 0-1: Bank 1 color */ +# define SSD1305_SETBANK2(c) (c << 2) /* Data 1, Bits 2-3: Bank 2 color */ +# define SSD1305_SETBANK3(c) (c << 4) /* Data 1, Bits 4-5: Bank 3 color */ +# define SSD1305_SETBANK4(c) (c << 6) /* Data 1, Bits 6-7: Bank 4 color */ +# define SSD1305_SETBANK5(c) (c) /* Data 2, Bits 0-1: Bank 5 color */ +# define SSD1305_SETBANK6(c) (c << 2) /* Data 2, Bits 2-3: Bank 6 color */ +# define SSD1305_SETBANK7(c) (c << 4) /* Data 2, Bits 4-5: Bank 7 color */ +# define SSD1305_SETBANK8(c) (c << 6) /* Data 2, Bits 6-7: Bank 8 color */ +# define SSD1305_SETBANK9(c) (c) /* Data 3, Bits 0-1: Bank 9 color */ +# define SSD1305_SETBANK10(c) (c << 2) /* Data 3, Bits 2-3: Bank 10 color */ +# define SSD1305_SETBANK11(c) (c << 4) /* Data 3, Bits 4-5: Bank 11 color */ +# define SSD1305_SETBANK12(c) (c << 6) /* Data 3, Bits 6-7: Bank 12 color */ +# define SSD1305_SETBANK13(c) (c) /* Data 4, Bits 0-1: Bank 13 color */ +# define SSD1305_SETBANK14(c) (c << 2) /* Data 4, Bits 2-3: Bank 14 color */ +# define SSD1305_SETBANK15(c) (c << 4) /* Data 4, Bits 4-5: Bank 15 color */ +# define SSD1305_SETBANK16(c) (c << 6) /* Data 4, Bits 6-7: Bank 16 color */ +#define SSD1305_SETBANKCOLOR2 0x93 /* 0x93: Set bank 17-32 color */ +# define SSD1305_SETBANK17(c) (c) /* Data 1, Bits 0-1: Bank 17 color */ +# define SSD1305_SETBANK18(c) (c << 2) /* Data 1, Bits 2-3: Bank 18 color */ +# define SSD1305_SETBANK19(c) (c << 4) /* Data 1, Bits 4-5: Bank 19 color */ +# define SSD1305_SETBANK20(c) (c << 6) /* Data 1, Bits 6-7: Bank 20 color */ +# define SSD1305_SETBANK21(c) (c) /* Data 2, Bits 0-1: Bank 21 color */ +# define SSD1305_SETBANK22(c) (c << 2) /* Data 2, Bits 2-3: Bank 22 color */ +# define SSD1305_SETBANK23(c) (c << 4) /* Data 2, Bits 4-5: Bank 23 color */ +# define SSD1305_SETBANK24(c) (c << 6) /* Data 2, Bits 6-7: Bank 24 color */ +# define SSD1305_SETBANK25(c) (c) /* Data 3, Bits 0-1: Bank 25 color */ +# define SSD1305_SETBANK26(c) (c << 2) /* Data 3, Bits 2-3: Bank 26 color */ +# define SSD1305_SETBANK27(c) (c << 4) /* Data 3, Bits 4-5: Bank 27 color */ +# define SSD1305_SETBANK28(c) (c << 6) /* Data 3, Bits 6-7: Bank 28 color */ +# define SSD1305_SETBANK29(c) (c) /* Data 4, Bits 0-1: Bank 29 color */ +# define SSD1305_SETBANK30(c) (c << 2) /* Data 4, Bits 2-3: Bank 30 color */ +# define SSD1305_SETBANK31(c) (c << 4) /* Data 4, Bits 4-5: Bank 31 color */ +# define SSD1305_SETBANK32(c) (c << 6) /* Data 4, Bits 6-7: Bank 32 color */ +#define SSD1305_MAPCOL0 0xa0 /* 0xa0: Column address 0 is mapped to SEG0 */ +#define SSD1305_MAPCOL131 0xa1 /* 0xa1: Column address 131 is mapped to SEG0 */ +#define SSD1305_DISPRAM 0xa4 /* 0xa4: Resume to RAM content display */ +#define SSD1305_DISPENTIRE 0xa5 /* 0xa5: Entire display ON */ +#define SSD1305_DISPNORMAL 0xa6 /* 0xa6: Normal display */ +#define SSD1305_DISPINVERTED 0xa7 /* 0xa7: Inverse display */ + +#define SSD1305_SETMUX 0xa8 /* 0xa8: Set Multiplex Ratio*/ + /* Data 1: MUX ratio -1: 15-63 */ +#define SSD1305_DIMMODE 0xab /* 0xab: Dim mode setting */ + /* Data 1: Reserverd, must be zero */ + /* Data 2: Contrast for bank1: 0-255 */ + /* Data 3: Brightness for color bank: 0-255 */ +#define SSD1305_MSTRCONFIG 0xad /* 0xad: Master configuration */ +# define SSD1305_MSTRCONFIG_EXTVCC 0x8e /* Data 1: Select external Vcc */ +#define SSD1305_DISPONDIM 0xac /* 0xac: Display ON in dim mode */ +#define SSD1305_DISPOFF 0xae /* 0xae: Display OFF (sleep mode) */ +#define SSD1305_DISPON 0xaf /* 0xaf: Display ON in normal mode */ +#define SSD1305_SETPAGESTART 0xb0 /* 0xb0-b7: Set page start address */ +# define SSD1305_PAGESTART_MASK 0x07 +#define SSD1305_SETCOMNORMAL 0xc0 /* 0xc0: Set COM output, normal mode */ +#define SSD1305_SETCOMREMAPPED 0xc8 /* 0xc8: Set COM output, remapped mode */ + +#define SSD1305_SETOFFSET 0xd3 /* 0xd3: Set display offset */ + /* Data 1: Vertical shift by COM: 0-63 */ +#define SSD1305_SETDCLK 0xd5 /* 0xd5: Set display clock divide ratio/oscillator */ +# define SSD1305_DCLKDIV_SHIFT (0) /* Data 1, Bits 0-3: DCLK divide ratio/frequency*/ +# define SSD1305_DCLKDIV_MASK 0x0f +# define SSD1305_DCLKFREQ_SHIFT (4) /* Data 1, Bits 4-7: DCLK divide oscillator frequency */ +# define SSD1305_DCLKFREQ_MASK 0xf0 +#define SSD1305_SETCOLORMODE 0xd8 /* 0xd: Set area color and low power display modes */ +# define SSD1305_COLORMODE_MONO 0x00 /* Data 1, Bits 4-5: 00=monochrome */ +# define SSD1305_COLORMODE_COLOR 0x30 /* Data 1, Bits 4-5: 11=area color enable */ +# define SSD1305_POWERMODE_NORMAL 0x00 /* Data 1, Bits 0,2: 00=normal power mode */ +# define SSD1305_POWERMODE_LOW 0x05 /* Data 1, Bits 0,2: 11=low power display mode */ +#define SSD1305_SETPRECHARGE 0xd9 /* 0xd9: Set pre-charge period */ +# define SSD1305_PHASE1_SHIFT (0) /* Data 1, Bits 0-3: Phase 1 period of up to 15 DCLK clocks */ +# define SSD1305_PHASE1_MASK 0x0f +# define SSD1305_PHASE2_SHIFT (4) /* Data 1, Bits 4-7: Phase 2 period of up to 15 DCLK clocks */ +# define SSD1305_PHASE2_MASK 0xf0 +#define SSD1305_SETCOMCONFIG 0xda /* 0xda: Set COM configuration */ +# define SSD1305_COMCONFIG_SEQ 0x02 /* Data 1, Bit 4: 0=Sequential COM pin configuration */ +# define SSD1305_COMCONFIG_ALT 0x12 /* Data 1, Bit 4: 1=Alternative COM pin configuration */ +# define SSD1305_COMCONFIG_NOREMAP 0x02 /* Data 1, Bit 5: 0=Disable COM Left/Right remap */ +# define SSD1305_COMCONFIG_REMAP 0x22 /* Data 1, Bit 5: 1=Enable COM Left/Right remap */ +#define SSD1305_SETVCOMHDESEL 0xdb /* 0xdb: Set VCOMH delselect level */ +# define SSD1305_VCOMH_x4p3 0x00 /* Data 1: ~0.43 x Vcc */ +# define SSD1305_VCOMH_x7p7 0x34 /* Data 1: ~0.77 x Vcc */ +# define SSD1305_VCOMH_x8p3 0x3c /* Data 1: ~0.83 x Vcc */ +#define SSD1305_ENTER_RMWMODE 0xe0 /* 0xe0: Enter the Read Modify Write mode */ +#define SSD1305_NOP 0xe3 /* 0xe3: NOP Command for no operation */ +#define SSD1305_EXIT_RMWMODE 0xee /* 0xee: Leave the Read Modify Write mode */ + +/* Graphic Acceleration Commands ********************************************/ + +#define SSD1305_HSCROLL_RIGHT 0x26 /* 0x26: Right horizontal scroll */ +#define SSD1305_HSCROLL_LEFT 0x27 /* 0x27: Left horizontal scroll */ + /* Data 1, Bits 0-2: Column scroll offset: 0-4 */ + /* Data 2, Bits 0-2: Start page address: 0-7 */ +#define SSD1305_HSCROLL_FRAMES6 0x00 /* Data 3, Bits 0-2: Timer interval, 000=6 frames */ +#define SSD1305_HSCROLL_FRAMES32 0x01 /* Data 3, Bits 0-2: Timer interval, 001=32 frames */ +#define SSD1305_HSCROLL_FRAMES64 0x02 /* Data 3, Bits 0-2: Timer interval, 010=64 frames */ +#define SSD1305_HSCROLL_FRAMES128 0x03 /* Data 3, Bits 0-2: Timer interval, 011=128 frames */ +#define SSD1305_HSCROLL_FRAMES3 0x04 /* Data 3, Bits 0-2: Timer interval, 100=3 frames */ +#define SSD1305_HSCROLL_FRAMES4 0x05 /* Data 3, Bits 0-2: Timer interval, 101=4 frames */ +#define SSD1305_HSCROLL_FRAMES2 0x06 /* Data 3, Bits 0-2: Timer interval, 110=2 frames */ + /* Data 4, Bits 0-2: End page address: 0-7 */ + +#define SSD1305_VSCROLL_RIGHT 0x29 /* 0x26: Vertical and right horizontal scroll */ +#define SSD1305_VSCROLL_LEFT 0x2a /* 0x27: Vertical and left horizontal scroll */ + /* Data 1, Bits 0-2: Column scroll offset: 0-4 */ + /* Data 2, Bits 0-2: Start page address: 0-7 */ +#define SSD1305_VSCROLL_FRAMES6 0x00 /* Data 3, Bits 0-2: Timer interval, 000=6 frames */ +#define SSD1305_VSCROLL_FRAMES32 0x01 /* Data 3, Bits 0-2: Timer interval, 001=32 frames */ +#define SSD1305_VSCROLL_FRAMES64 0x02 /* Data 3, Bits 0-2: Timer interval, 010=64 frames */ +#define SSD1305_VSCROLL_FRAMES128 0x03 /* Data 3, Bits 0-2: Timer interval, 011=128 frames */ +#define SSD1305_VSCROLL_FRAMES3 0x04 /* Data 3, Bits 0-2: Timer interval, 100=3 frames */ +#define SSD1305_VSCROLL_FRAMES4 0x05 /* Data 3, Bits 0-2: Timer interval, 101=4 frames */ +#define SSD1305_VSCROLL_FRAMES2 0x06 /* Data 3, Bits 0-2: Timer interval, 110=2 frames */ + /* Data 4, Bits 0-2: End page address: 0-7 */ + /* Data 5, Bits 0-5: Vertical scrolling offset: 0-63 */ +#define SSD1305_SCROLL_STOP 0x2e /* 0x2e: Deactivate scroll */ +#define SSD1305_SCROLL_START 0x2f /* 0x2f: Activate scroll */ +#define SSD1305_VSCROLL_AREA 0xa3 /* 0xa3: Set vertical scroll area */ + /* Data 1: Number of rows in the top fixed area */ + /* Data 1: Number of rows in the scroll area */ + +/* Status register bit definitions ******************************************/ + +#define SSD1305_STATUS_DISPOFF (1 << 6) /* Bit 6: 1=Display off */ + +#endif /* __DRIVERS_LCD_SSD1305_H */ diff --git a/drivers/lcd/ug-9664hswag01.c b/drivers/lcd/ug-9664hswag01.c index bb49f20e6b5bcf1ea94ff5b08ec8a82e0e115341..e0e8e8e3a05ba5e469d1a0f59b68e48971de776a 100644 --- a/drivers/lcd/ug-9664hswag01.c +++ b/drivers/lcd/ug-9664hswag01.c @@ -4,7 +4,7 @@ * controller. * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Reference: "Product Specification, OEL Display Module, UG-9664HSWAG01", Univision * Technology Inc., SAS1-6020-B, January 3, 2008. diff --git a/drivers/mmcsd/Make.defs b/drivers/mmcsd/Make.defs index 48e5d4fb6edd4469ad38c1b210da4e68b3651b88..850456597244482d22181b80ca4dc32bc94e80a1 100644 --- a/drivers/mmcsd/Make.defs +++ b/drivers/mmcsd/Make.defs @@ -2,7 +2,7 @@ # drivers/mmcsd/Make.defs # # Copyright (C) 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/drivers/mmcsd/mmcsd_csd.h b/drivers/mmcsd/mmcsd_csd.h index e35eacad5bf965ad6646fd6fd97d11e9d6450b80..d5343aa8419050e8bee3bffd7e4fb0d759ec8582 100644 --- a/drivers/mmcsd/mmcsd_csd.h +++ b/drivers/mmcsd/mmcsd_csd.h @@ -2,7 +2,7 @@ * drivers/mmcsd/mmcsd_csd.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/mmcsd/mmcsd_debug.c b/drivers/mmcsd/mmcsd_debug.c index 03872f5cf96553be104b6ad27cd130565c2d4587..0bd7f896ebae5da98c4437e46c68aa8dd34e69bc 100644 --- a/drivers/mmcsd/mmcsd_debug.c +++ b/drivers/mmcsd/mmcsd_debug.c @@ -2,7 +2,7 @@ * drivers/mmcsd/mmcsd_debug.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/mmcsd/mmcsd_internal.h b/drivers/mmcsd/mmcsd_internal.h index 577ebbba9320ccb9153c0434004baafeeda56576..ed669cdfacb1bc0bcc8073e6e7f9817aea0605ff 100644 --- a/drivers/mmcsd/mmcsd_internal.h +++ b/drivers/mmcsd/mmcsd_internal.h @@ -2,7 +2,7 @@ * drivers/mmcsd/mmcsd_internal.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/mmcsd/mmcsd_sdio.h b/drivers/mmcsd/mmcsd_sdio.h index 75c97bd65ab0a051c747a8887d642945432f2d5d..9e3794e257c7cb4cdca527a28480d36b31e5d462 100644 --- a/drivers/mmcsd/mmcsd_sdio.h +++ b/drivers/mmcsd/mmcsd_sdio.h @@ -1,339 +1,339 @@ -/******************************************************************************************** - * drivers/mmcsd/mmcsd_sdio.h - * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************/ - -#ifndef __DRIVERS_MMCSD_MMCSD_SDIO_H -#define __DRIVERS_MMCSD_MMCSD_SDIO_H - -/******************************************************************************************** - * Included Files - ********************************************************************************************/ - -#include -#include - -/******************************************************************************************** - * Pre-Processor Definitions - ********************************************************************************************/ - -/* CMD8 Argument: - * [31:12]: Reserved (shall be set to '0') - * [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) - * [7:0]: Check Pattern (recommended 0xaa) - * CMD8 Response: R7 - */ - -#define MMCSD_CMD8VOLTAGE_SHIFT (8) /* Bits 8-11: Supply voltage */ -#define MMCSD_CMD8VOLTAGE_MASK ((uint32_t)0x0f << MMCSD_CMD8VOLTAGE_SHIFT) -# define MMCSD_CMD8VOLTAGE_27 ((uint32_t)0x01 << MMCSD_CMD8VOLTAGE_SHIFT) /* 2.7-3.6V */ -#define MMCSD_CMD8ECHO_SHIFT (0) /* Bits 0-7: Check pattern */ -#define MMCSD_CMD8ECHO_MASK ((uint32_t)0xff << MMCSD_CMD8ECHO_SHIFT) -# define MMCSD_CMD8CHECKPATTERN ((uint32_t)0xaa << MMCSD_CMD8ECHO_SHIFT) - -/* ACMD6 argument */ - -#define MMCSD_ACMD6_BUSWIDTH_1 ((uint32_t)0) /* Bus width = 1-bit */ -#define MMCSD_ACMD6_BUSWIDTH_4 ((uint32_t)2) /* Bus width = 4-bit */ - -/* ACMD41 argument */ - -#define MMCSD_ACMD41_VOLTAGEWINDOW ((uint32_t)0x80100000) -#define MMCSD_ACMD41_HIGHCAPACITY ((uint32_t)1 << 30) -#define MMCSD_ACMD41_STDCAPACITY ((uint32_t)0) - -/* ACMD42 argument */ - -#define MMCSD_ACMD42_CD_DISCONNECT ((uint32_t)0) /* Disconnect card detection logic */ -#define MMCSD_ACMD42_CD_CONNECT ((uint32_t)1) /* Connect card detection logic */ - -/* R1 Card Status bit definitions */ - -#define MMCSD_R1_OUTOFRANGE ((uint32_t)1 << 31) /* Bad argument */ -#define MMCSD_R1_ADDRESSERROR ((uint32_t)1 << 30) /* Bad address */ -#define MMCSD_R1_BLOCKLENERROR ((uint32_t)1 << 29) /* Bad block length */ -#define MMCSD_R1_ERASESEQERROR ((uint32_t)1 << 28) /* Erase cmd error */ -#define MMCSD_R1_ERASEPARAM ((uint32_t)1 << 27) /* Bad write blocks */ -#define MMCSD_R1_WPVIOLATION ((uint32_t)1 << 26) /* Erase access failure */ -#define MMCSD_R1_CARDISLOCKED ((uint32_t)1 << 25) /* Card is locked */ -#define MMCSD_R1_LOCKUNLOCKFAILED ((uint32_t)1 << 24) /* Password error */ -#define MMCSD_R1_COMCRCERROR ((uint32_t)1 << 23) /* CRC error */ -#define MMCSD_R1_ILLEGALCOMMAND ((uint32_t)1 << 22) /* Bad command */ -#define MMCSD_R1_CARDECCFAILED ((uint32_t)1 << 21) /* Failed to correct data */ -#define MMCSD_R1_CCERROR ((uint32_t)1 << 20) /* Card controller error */ -#define MMCSD_R1_ERROR ((uint32_t)1 << 19) /* General error */ -#define MMCSD_R1_UNDERRUN ((uint32_t)1 << 18) /* Underrun (MMC only) */ -#define MMCSD_R1_OVERRRUN ((uint32_t)1 << 17) /* Overrun (MMC only) */ -#define MMCSD_R1_CIDCSDOVERWRITE ((uint32_t)1 << 16) /* CID/CSD error */ -#define MMCSD_R1_WPERASESKIP ((uint32_t)1 << 15) /* Not all erased */ -#define MMCSD_R1_CARDECCDISABLED ((uint32_t)1 << 14) /* Internal ECC not used */ -#define MMCSD_R1_ERASERESET ((uint32_t)1 << 13) /* Reset sequence cleared */ -#define MMCSD_R1_STATE_SHIFT (9) /* Current card state */ -#define MMCSD_R1_STATE_MASK ((uint32_t)15 << MMCSD_R1_STATE_SHIFT) - /* Card identification mode states */ -# define MMCSD_R1_STATE_IDLE ((uint32_t)0 << MMCSD_R1_STATE_SHIFT) /* 0=Idle state */ -# define MMCSD_R1_STATE_READY ((uint32_t)1 << MMCSD_R1_STATE_SHIFT) /* 1=Ready state */ -# define MMCSD_R1_STATE_IDENT ((uint32_t)2 << MMCSD_R1_STATE_SHIFT) /* 2=Identification state */ - /* Data transfer states */ -# define MMCSD_R1_STATE_STBY ((uint32_t)3 << MMCSD_R1_STATE_SHIFT) /* 3=Standby state */ -# define MMCSD_R1_STATE_TRAN ((uint32_t)4 << MMCSD_R1_STATE_SHIFT) /* 4=Transfer state */ -# define MMCSD_R1_STATE_DATA ((uint32_t)5 << MMCSD_R1_STATE_SHIFT) /* 5=Sending data state */ -# define MMCSD_R1_STATE_RCV ((uint32_t)6 << MMCSD_R1_STATE_SHIFT) /* 6=Receiving data state */ -# define MMCSD_R1_STATE_PRG ((uint32_t)7 << MMCSD_R1_STATE_SHIFT) /* 7=Programming state */ -# define MMCSD_R1_STATE_DIS ((uint32_t)8 << MMCSD_R1_STATE_SHIFT) /* 8=Disconnect state */ -#define MMCSD_R1_READYFORDATA ((uint32_t)1 << 8) /* Buffer empty */ -#define MMCSD_R1_APPCMD ((uint32_t)1 << 5) /* Next CMD is ACMD */ -#define MMCSD_R1_AKESEQERROR ((uint32_t)1 << 3) /* Authentication error */ -#define MMCSD_R1_ERRORMASK ((uint32_t)0xfdffe008) /* Error mask */ - -#define IS_STATE(v,s) ((((uint32_t)v)&MMCSD_R1_STATE_MASK)==(s)) - -/* R3 (OCR) */ - -#define MMC_VDD_20_36 ((uint32_t)0x00ffff00) /* VDD voltage 2.0-3.6 */ - -#define MMCSD_VDD_145_150 ((uint32_t)1 << 0) /* VDD voltage 1.45 - 1.50 */ -#define MMCSD_VDD_150_155 ((uint32_t)1 << 1) /* VDD voltage 1.50 - 1.55 */ -#define MMCSD_VDD_155_160 ((uint32_t)1 << 2) /* VDD voltage 1.55 - 1.60 */ -#define MMCSD_VDD_160_165 ((uint32_t)1 << 3) /* VDD voltage 1.60 - 1.65 */ -#define MMCSD_VDD_165_170 ((uint32_t)1 << 4) /* VDD voltage 1.65 - 1.70 */ -#define MMCSD_VDD_17_18 ((uint32_t)1 << 5) /* VDD voltage 1.7 - 1.8 */ -#define MMCSD_VDD_18_19 ((uint32_t)1 << 6) /* VDD voltage 1.8 - 1.9 */ -#define MMCSD_VDD_19_20 ((uint32_t)1 << 7) /* VDD voltage 1.9 - 2.0 */ -#define MMCSD_VDD_20_21 ((uint32_t)1 << 8) /* VDD voltage 2.0-2.1 */ -#define MMCSD_VDD_21_22 ((uint32_t)1 << 9) /* VDD voltage 2.1-2.2 */ -#define MMCSD_VDD_22_23 ((uint32_t)1 << 10) /* VDD voltage 2.2-2.3 */ -#define MMCSD_VDD_23_24 ((uint32_t)1 << 11) /* VDD voltage 2.3-2.4 */ -#define MMCSD_VDD_24_25 ((uint32_t)1 << 12) /* VDD voltage 2.4-2.5 */ -#define MMCSD_VDD_25_26 ((uint32_t)1 << 13) /* VDD voltage 2.5-2.6 */ -#define MMCSD_VDD_26_27 ((uint32_t)1 << 14) /* VDD voltage 2.6-2.7 */ -#define MMCSD_VDD_27_28 ((uint32_t)1 << 15) /* VDD voltage 2.7-2.8 */ -#define MMCSD_VDD_28_29 ((uint32_t)1 << 16) /* VDD voltage 2.8-2.9 */ -#define MMCSD_VDD_29_30 ((uint32_t)1 << 17) /* VDD voltage 2.9-3.0 */ -#define MMCSD_VDD_30_31 ((uint32_t)1 << 18) /* VDD voltage 3.0-3.1 */ -#define MMCSD_VDD_31_32 ((uint32_t)1 << 19) /* VDD voltage 3.1-3.2 */ -#define MMCSD_VDD_32_33 ((uint32_t)1 << 20) /* VDD voltage 3.2-3.3 */ -#define MMCSD_VDD_33_34 ((uint32_t)1 << 21) /* VDD voltage 3.3-3.4 */ -#define MMCSD_VDD_34_35 ((uint32_t)1 << 22) /* VDD voltage 3.4-3.5 */ -#define MMCSD_VDD_35_36 ((uint32_t)1 << 23) /* VDD voltage 3.5-3.6 */ -#define MMCSD_R3_HIGHCAPACITY ((uint32_t)1 << 30) /* true: Card supports block addressing */ -#define MMCSD_CARD_BUSY ((uint32_t)1 << 31) /* Card power-up busy bit */ - -/* R6 Card Status bit definitions */ - -#define MMCSD_R6_RCA_SHIFT (16) /* New published RCA */ -#define MMCSD_R6_RCA_MASK ((uint32_t)0xffff << MMCSD_R6_RCA_SHIFT) -#define MMCSD_R6_COMCRCERROR ((uint32_t)1 << 15) /* CRC error */ -#define MMCSD_R6_ILLEGALCOMMAND ((uint32_t)1 << 14) /* Bad command */ -#define MMCSD_R6_ERROR ((uint32_t)1 << 13) /* General error */ -#define MMCSD_R6_STATE_SHIFT (9) /* Current card state */ -#define MMCSD_R6_STATE_MASK ((uint32_t)15 << MMCSD_R6_STATE_SHIFT) - /* Card identification mode states */ -# define MMCSD_R6_STATE_IDLE ((uint32_t)0 << MMCSD_R6_STATE_SHIFT) /* 0=Idle state */ -# define MMCSD_R6_STATE_READY ((uint32_t)1 << MMCSD_R6_STATE_SHIFT) /* 1=Ready state */ -# define MMCSD_R6_STATE_IDENT ((uint32_t)2 << MMCSD_R6_STATE_SHIFT) /* 2=Identification state */ - /* Data transfer states */ -# define MMCSD_R6_STATE_STBY ((uint32_t)3 << MMCSD_R6_STATE_SHIFT) /* 3=Standby state */ -# define MMCSD_R6_STATE_TRAN ((uint32_t)4 << MMCSD_R6_STATE_SHIFT) /* 4=Transfer state */ -# define MMCSD_R6_STATE_DATA (5(uint32_t) << MMCSD_R6_STATE_SHIFT) /* 5=Sending data state */ -# define MMCSD_R6_STATE_RCV ((uint32_t)6 << MMCSD_R6_STATE_SHIFT) /* 6=Receiving data state */ -# define MMCSD_R6_STATE_PRG ((uint32_t)7 << MMCSD_R6_STATE_SHIFT) /* 7=Programming state */ -# define MMCSD_R6_STATE_DIS ((uint32_t) << MMCSD_R6_STATE_SHIFT) /* 8=Disconnect state */ -#define MMCSD_R6_ERRORMASK ((uint32_t)0x0000e000) /* Error mask */ - -/* SD Configuration Register (SCR) encoding */ - -#define MMCSD_SCR_BUSWIDTH_1BIT (1) -#define MMCSD_SCR_BUSWIDTH_2BIT (2) -#define MMCSD_SCR_BUSWIDTH_4BIT (4) -#define MMCSD_SCR_BUSWIDTH_8BIT (8) - -/* Last 4 bytes of the 48-bit R7 response */ - -#define MMCSD_R7VERSION_SHIFT (28) /* Bits 28-31: Command version number */ -#define MMCSD_R7VERSION_MASK ((uint32_t)0x0f << MMCSD_R7VERSION_SHIFT) -#define MMCSD_R7VOLTAGE_SHIFT (8) /* Bits 8-11: Voltage accepted */ -#define MMCSD_R7VOLTAGE_MASK ((uint32_t)0x0f << MMCSD_R7VOLTAGE_SHIFT) -# define MMCSD_R7VOLTAGE_27 ((uint32_t)0x01 << MMCSD_R7VOLTAGE_SHIFT) /* 2.7-3.6V */ -#define MMCSD_R7ECHO_SHIFT (0) /* Bits 0-7: Echoed check pattern */ -#define MMCSD_R7ECHO_MASK ((uint32_t)0xff << MMCSD_R7ECHO_SHIFT) -# define MMCSD_R7CHECKPATTERN ((uint32_t)0xaa << MMCSD_R7ECHO_SHIFT) - -/******************************************************************************************** - * Public Types - ********************************************************************************************/ - -/* Decoded Card Identification (CID) register */ - -struct mmcsd_cid_s -{ - uint8_t mid; /* 127:120 8-bit Manufacturer ID */ - uint16_t oid; /* 119:104 16-bit OEM/Application ID (ascii) */ - uint8_t pnm[6]; /* 103:64 40-bit Product Name (ascii) + null terminator */ - uint8_t prv; /* 63:56 8-bit Product revision */ - uint32_t psn; /* 55:24 32-bit Product serial number */ - /* 23:20 4-bit (reserved) */ - uint16_t mdt; /* 19:8 12-bit Manufacturing date */ - uint8_t crc; /* 7:1 7-bit CRC7 */ - /* 0:0 1-bit (not used) */ -}; - -/* Decoded Card Specific Data (CSD) register */ - -struct mmcsd_csd_s -{ - uint8_t csdstructure; /* 127:126 CSD structure */ - uint8_t mmcspecvers; /* 125:122 MMC Spec version (MMC only) */ - - struct - { - uint8_t timeunit; /* 2:0 Time exponent */ - uint8_t timevalue; /* 6:3 Time mantissa */ - } taac; /* 119:112 Data read access-time-1 */ - - uint8_t nsac; /* 111:104 Data read access-time-2 in CLK cycle(NSAC*100) */ - - struct - { - uint8_t transferrateunit; /* 2:0 Rate exponent */ - uint8_t timevalue; /* 6:3 Rate mantissa */ - } transpeed; /* 103:96 Max. data transfer rate */ - - uint16_t ccc; /* 95:84 Card command classes */ - uint8_t readbllen; /* 83:80 Max. read data block length */ - uint8_t readblpartial; /* 79:79 Partial blocks for read allowed */ - uint8_t writeblkmisalign; /* 78:78 Write block misalignment */ - uint8_t readblkmisalign; /* 77:77 Read block misalignment */ - uint8_t dsrimp; /* 76:76 DSR implemented */ - - union - { -#ifdef CONFIG_MMCSD_MMCSUPPORT - struct - { - uint16_t csize; /* 73:62 Device size */ - uint8_t vddrcurrmin; /* 61:59 Max. read current at Vdd min */ - uint8_t vddrcurrmax; /* 58:56 Max. read current at Vdd max */ - uint8_t vddwcurrmin; /* 55:53 Max. write current at Vdd min */ - uint8_t vddwcurrmax; /* 52:50 Max. write current at Vdd max */ - uint8_t csizemult; /* 49:47 Device size multiplier */ - - union - { - struct /* MMC system specification version 3.1 */ - { - uint8_t ergrpsize; /* 46:42 Erase group size (MMC 3.1) */ - uint8_t ergrpmult; /* 41:37 Erase group multiplier (MMC 3.1) */ - } mmc31; - struct /* MMC system specification version 2.2 */ - { - uint8_t sectorsize; /* 46:42 Erase sector size (MMC 2.2) */ - uint8_t ergrpsize; /* 41:37 Erase group size (MMC 2.2) */ - } mmc22; - } er; - - uint8_t mmcwpgrpsize; /* 36:32 Write protect group size (MMC) */ - } mmc; -#endif - struct - { - uint16_t csize; /* 73:62 Device size */ - uint8_t vddrcurrmin; /* 61:59 Max. read current at Vdd min */ - uint8_t vddrcurrmax; /* 58:56 Max. read current at Vdd max */ - uint8_t vddwcurrmin; /* 55:53 Max. write current at Vdd min */ - uint8_t vddwcurrmax; /* 52:50 Max. write current at Vdd max */ - uint8_t csizemult; /* 49:47 Device size multiplier */ - uint8_t sderblen; /* 46:46 Erase single block enable (SD) */ - uint8_t sdsectorsize; /* 45:39 Erase sector size (SD) */ - uint8_t sdwpgrpsize; /* 38:32 Write protect group size (SD) */ - } sdbyte; - - struct - { - /* 73:70 (reserved) */ - uint32_t csize; /* 69:48 Device size */ - /* 47:47 (reserved) */ - uint8_t sderblen; /* 46:46 Erase single block enable (SD) */ - uint8_t sdsectorsize; /* 45:39 Erase sector size (SD) */ - uint8_t sdwpgrpsize; /* 38:32 Write protect group size (SD) */ - } sdblock; - } u; - - uint8_t wpgrpen; /* 31:31 Write protect group enable */ - uint8_t mmcdfltecc; /* 30:29 Manufacturer default ECC (MMC) */ - uint8_t r2wfactor; /* 28:26 Write speed factor */ - uint8_t writebllen; /* 25:22 Max. write data block length */ - uint8_t writeblpartial; /* 21:21 Partial blocks for write allowed */ - uint8_t fileformatgrp; /* 15:15 File format group */ - uint8_t copy; /* 14:14 Copy flag (OTP) */ - uint8_t permwriteprotect; /* 13:13 Permanent write protection */ - uint8_t tmpwriteprotect; /* 12:12 Temporary write protection */ - uint8_t fileformat; /* 10:11 File format */ - uint8_t mmcecc; /* 9:8 ECC (MMC) */ - uint8_t crc; /* 7:1 CRC */ - /* 0:0 Not used */ -}; - -struct mmcsd_scr_s -{ - uint8_t scrversion; /* 63:60 Version of SCR structure */ - uint8_t sdversion; /* 59:56 SD memory card physical layer version */ - uint8_t erasestate; /* 55:55 Data state after erase (1 or 0) */ - uint8_t security; /* 54:52 SD security support */ - uint8_t buswidth; /* 51:48 DAT bus widthes supported */ - /* 47:32 SD reserved space */ - uint32_t mfgdata; /* 31:0 Reserved for manufacturing data */ -}; - -/******************************************************************************************** - * Public Data - ********************************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ - - -#undef EXTERN -#if defined(__cplusplus) -} -#endif -#endif /* __DRIVERS_MMCSD_MMCSD_SDIO_H */ +/******************************************************************************************** + * drivers/mmcsd/mmcsd_sdio.h + * + * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __DRIVERS_MMCSD_MMCSD_SDIO_H +#define __DRIVERS_MMCSD_MMCSD_SDIO_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include +#include + +/******************************************************************************************** + * Pre-Processor Definitions + ********************************************************************************************/ + +/* CMD8 Argument: + * [31:12]: Reserved (shall be set to '0') + * [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + * [7:0]: Check Pattern (recommended 0xaa) + * CMD8 Response: R7 + */ + +#define MMCSD_CMD8VOLTAGE_SHIFT (8) /* Bits 8-11: Supply voltage */ +#define MMCSD_CMD8VOLTAGE_MASK ((uint32_t)0x0f << MMCSD_CMD8VOLTAGE_SHIFT) +# define MMCSD_CMD8VOLTAGE_27 ((uint32_t)0x01 << MMCSD_CMD8VOLTAGE_SHIFT) /* 2.7-3.6V */ +#define MMCSD_CMD8ECHO_SHIFT (0) /* Bits 0-7: Check pattern */ +#define MMCSD_CMD8ECHO_MASK ((uint32_t)0xff << MMCSD_CMD8ECHO_SHIFT) +# define MMCSD_CMD8CHECKPATTERN ((uint32_t)0xaa << MMCSD_CMD8ECHO_SHIFT) + +/* ACMD6 argument */ + +#define MMCSD_ACMD6_BUSWIDTH_1 ((uint32_t)0) /* Bus width = 1-bit */ +#define MMCSD_ACMD6_BUSWIDTH_4 ((uint32_t)2) /* Bus width = 4-bit */ + +/* ACMD41 argument */ + +#define MMCSD_ACMD41_VOLTAGEWINDOW ((uint32_t)0x80100000) +#define MMCSD_ACMD41_HIGHCAPACITY ((uint32_t)1 << 30) +#define MMCSD_ACMD41_STDCAPACITY ((uint32_t)0) + +/* ACMD42 argument */ + +#define MMCSD_ACMD42_CD_DISCONNECT ((uint32_t)0) /* Disconnect card detection logic */ +#define MMCSD_ACMD42_CD_CONNECT ((uint32_t)1) /* Connect card detection logic */ + +/* R1 Card Status bit definitions */ + +#define MMCSD_R1_OUTOFRANGE ((uint32_t)1 << 31) /* Bad argument */ +#define MMCSD_R1_ADDRESSERROR ((uint32_t)1 << 30) /* Bad address */ +#define MMCSD_R1_BLOCKLENERROR ((uint32_t)1 << 29) /* Bad block length */ +#define MMCSD_R1_ERASESEQERROR ((uint32_t)1 << 28) /* Erase cmd error */ +#define MMCSD_R1_ERASEPARAM ((uint32_t)1 << 27) /* Bad write blocks */ +#define MMCSD_R1_WPVIOLATION ((uint32_t)1 << 26) /* Erase access failure */ +#define MMCSD_R1_CARDISLOCKED ((uint32_t)1 << 25) /* Card is locked */ +#define MMCSD_R1_LOCKUNLOCKFAILED ((uint32_t)1 << 24) /* Password error */ +#define MMCSD_R1_COMCRCERROR ((uint32_t)1 << 23) /* CRC error */ +#define MMCSD_R1_ILLEGALCOMMAND ((uint32_t)1 << 22) /* Bad command */ +#define MMCSD_R1_CARDECCFAILED ((uint32_t)1 << 21) /* Failed to correct data */ +#define MMCSD_R1_CCERROR ((uint32_t)1 << 20) /* Card controller error */ +#define MMCSD_R1_ERROR ((uint32_t)1 << 19) /* General error */ +#define MMCSD_R1_UNDERRUN ((uint32_t)1 << 18) /* Underrun (MMC only) */ +#define MMCSD_R1_OVERRRUN ((uint32_t)1 << 17) /* Overrun (MMC only) */ +#define MMCSD_R1_CIDCSDOVERWRITE ((uint32_t)1 << 16) /* CID/CSD error */ +#define MMCSD_R1_WPERASESKIP ((uint32_t)1 << 15) /* Not all erased */ +#define MMCSD_R1_CARDECCDISABLED ((uint32_t)1 << 14) /* Internal ECC not used */ +#define MMCSD_R1_ERASERESET ((uint32_t)1 << 13) /* Reset sequence cleared */ +#define MMCSD_R1_STATE_SHIFT (9) /* Current card state */ +#define MMCSD_R1_STATE_MASK ((uint32_t)15 << MMCSD_R1_STATE_SHIFT) + /* Card identification mode states */ +# define MMCSD_R1_STATE_IDLE ((uint32_t)0 << MMCSD_R1_STATE_SHIFT) /* 0=Idle state */ +# define MMCSD_R1_STATE_READY ((uint32_t)1 << MMCSD_R1_STATE_SHIFT) /* 1=Ready state */ +# define MMCSD_R1_STATE_IDENT ((uint32_t)2 << MMCSD_R1_STATE_SHIFT) /* 2=Identification state */ + /* Data transfer states */ +# define MMCSD_R1_STATE_STBY ((uint32_t)3 << MMCSD_R1_STATE_SHIFT) /* 3=Standby state */ +# define MMCSD_R1_STATE_TRAN ((uint32_t)4 << MMCSD_R1_STATE_SHIFT) /* 4=Transfer state */ +# define MMCSD_R1_STATE_DATA ((uint32_t)5 << MMCSD_R1_STATE_SHIFT) /* 5=Sending data state */ +# define MMCSD_R1_STATE_RCV ((uint32_t)6 << MMCSD_R1_STATE_SHIFT) /* 6=Receiving data state */ +# define MMCSD_R1_STATE_PRG ((uint32_t)7 << MMCSD_R1_STATE_SHIFT) /* 7=Programming state */ +# define MMCSD_R1_STATE_DIS ((uint32_t)8 << MMCSD_R1_STATE_SHIFT) /* 8=Disconnect state */ +#define MMCSD_R1_READYFORDATA ((uint32_t)1 << 8) /* Buffer empty */ +#define MMCSD_R1_APPCMD ((uint32_t)1 << 5) /* Next CMD is ACMD */ +#define MMCSD_R1_AKESEQERROR ((uint32_t)1 << 3) /* Authentication error */ +#define MMCSD_R1_ERRORMASK ((uint32_t)0xfdffe008) /* Error mask */ + +#define IS_STATE(v,s) ((((uint32_t)v)&MMCSD_R1_STATE_MASK)==(s)) + +/* R3 (OCR) */ + +#define MMC_VDD_20_36 ((uint32_t)0x00ffff00) /* VDD voltage 2.0-3.6 */ + +#define MMCSD_VDD_145_150 ((uint32_t)1 << 0) /* VDD voltage 1.45 - 1.50 */ +#define MMCSD_VDD_150_155 ((uint32_t)1 << 1) /* VDD voltage 1.50 - 1.55 */ +#define MMCSD_VDD_155_160 ((uint32_t)1 << 2) /* VDD voltage 1.55 - 1.60 */ +#define MMCSD_VDD_160_165 ((uint32_t)1 << 3) /* VDD voltage 1.60 - 1.65 */ +#define MMCSD_VDD_165_170 ((uint32_t)1 << 4) /* VDD voltage 1.65 - 1.70 */ +#define MMCSD_VDD_17_18 ((uint32_t)1 << 5) /* VDD voltage 1.7 - 1.8 */ +#define MMCSD_VDD_18_19 ((uint32_t)1 << 6) /* VDD voltage 1.8 - 1.9 */ +#define MMCSD_VDD_19_20 ((uint32_t)1 << 7) /* VDD voltage 1.9 - 2.0 */ +#define MMCSD_VDD_20_21 ((uint32_t)1 << 8) /* VDD voltage 2.0-2.1 */ +#define MMCSD_VDD_21_22 ((uint32_t)1 << 9) /* VDD voltage 2.1-2.2 */ +#define MMCSD_VDD_22_23 ((uint32_t)1 << 10) /* VDD voltage 2.2-2.3 */ +#define MMCSD_VDD_23_24 ((uint32_t)1 << 11) /* VDD voltage 2.3-2.4 */ +#define MMCSD_VDD_24_25 ((uint32_t)1 << 12) /* VDD voltage 2.4-2.5 */ +#define MMCSD_VDD_25_26 ((uint32_t)1 << 13) /* VDD voltage 2.5-2.6 */ +#define MMCSD_VDD_26_27 ((uint32_t)1 << 14) /* VDD voltage 2.6-2.7 */ +#define MMCSD_VDD_27_28 ((uint32_t)1 << 15) /* VDD voltage 2.7-2.8 */ +#define MMCSD_VDD_28_29 ((uint32_t)1 << 16) /* VDD voltage 2.8-2.9 */ +#define MMCSD_VDD_29_30 ((uint32_t)1 << 17) /* VDD voltage 2.9-3.0 */ +#define MMCSD_VDD_30_31 ((uint32_t)1 << 18) /* VDD voltage 3.0-3.1 */ +#define MMCSD_VDD_31_32 ((uint32_t)1 << 19) /* VDD voltage 3.1-3.2 */ +#define MMCSD_VDD_32_33 ((uint32_t)1 << 20) /* VDD voltage 3.2-3.3 */ +#define MMCSD_VDD_33_34 ((uint32_t)1 << 21) /* VDD voltage 3.3-3.4 */ +#define MMCSD_VDD_34_35 ((uint32_t)1 << 22) /* VDD voltage 3.4-3.5 */ +#define MMCSD_VDD_35_36 ((uint32_t)1 << 23) /* VDD voltage 3.5-3.6 */ +#define MMCSD_R3_HIGHCAPACITY ((uint32_t)1 << 30) /* true: Card supports block addressing */ +#define MMCSD_CARD_BUSY ((uint32_t)1 << 31) /* Card power-up busy bit */ + +/* R6 Card Status bit definitions */ + +#define MMCSD_R6_RCA_SHIFT (16) /* New published RCA */ +#define MMCSD_R6_RCA_MASK ((uint32_t)0xffff << MMCSD_R6_RCA_SHIFT) +#define MMCSD_R6_COMCRCERROR ((uint32_t)1 << 15) /* CRC error */ +#define MMCSD_R6_ILLEGALCOMMAND ((uint32_t)1 << 14) /* Bad command */ +#define MMCSD_R6_ERROR ((uint32_t)1 << 13) /* General error */ +#define MMCSD_R6_STATE_SHIFT (9) /* Current card state */ +#define MMCSD_R6_STATE_MASK ((uint32_t)15 << MMCSD_R6_STATE_SHIFT) + /* Card identification mode states */ +# define MMCSD_R6_STATE_IDLE ((uint32_t)0 << MMCSD_R6_STATE_SHIFT) /* 0=Idle state */ +# define MMCSD_R6_STATE_READY ((uint32_t)1 << MMCSD_R6_STATE_SHIFT) /* 1=Ready state */ +# define MMCSD_R6_STATE_IDENT ((uint32_t)2 << MMCSD_R6_STATE_SHIFT) /* 2=Identification state */ + /* Data transfer states */ +# define MMCSD_R6_STATE_STBY ((uint32_t)3 << MMCSD_R6_STATE_SHIFT) /* 3=Standby state */ +# define MMCSD_R6_STATE_TRAN ((uint32_t)4 << MMCSD_R6_STATE_SHIFT) /* 4=Transfer state */ +# define MMCSD_R6_STATE_DATA (5(uint32_t) << MMCSD_R6_STATE_SHIFT) /* 5=Sending data state */ +# define MMCSD_R6_STATE_RCV ((uint32_t)6 << MMCSD_R6_STATE_SHIFT) /* 6=Receiving data state */ +# define MMCSD_R6_STATE_PRG ((uint32_t)7 << MMCSD_R6_STATE_SHIFT) /* 7=Programming state */ +# define MMCSD_R6_STATE_DIS ((uint32_t) << MMCSD_R6_STATE_SHIFT) /* 8=Disconnect state */ +#define MMCSD_R6_ERRORMASK ((uint32_t)0x0000e000) /* Error mask */ + +/* SD Configuration Register (SCR) encoding */ + +#define MMCSD_SCR_BUSWIDTH_1BIT (1) +#define MMCSD_SCR_BUSWIDTH_2BIT (2) +#define MMCSD_SCR_BUSWIDTH_4BIT (4) +#define MMCSD_SCR_BUSWIDTH_8BIT (8) + +/* Last 4 bytes of the 48-bit R7 response */ + +#define MMCSD_R7VERSION_SHIFT (28) /* Bits 28-31: Command version number */ +#define MMCSD_R7VERSION_MASK ((uint32_t)0x0f << MMCSD_R7VERSION_SHIFT) +#define MMCSD_R7VOLTAGE_SHIFT (8) /* Bits 8-11: Voltage accepted */ +#define MMCSD_R7VOLTAGE_MASK ((uint32_t)0x0f << MMCSD_R7VOLTAGE_SHIFT) +# define MMCSD_R7VOLTAGE_27 ((uint32_t)0x01 << MMCSD_R7VOLTAGE_SHIFT) /* 2.7-3.6V */ +#define MMCSD_R7ECHO_SHIFT (0) /* Bits 0-7: Echoed check pattern */ +#define MMCSD_R7ECHO_MASK ((uint32_t)0xff << MMCSD_R7ECHO_SHIFT) +# define MMCSD_R7CHECKPATTERN ((uint32_t)0xaa << MMCSD_R7ECHO_SHIFT) + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/* Decoded Card Identification (CID) register */ + +struct mmcsd_cid_s +{ + uint8_t mid; /* 127:120 8-bit Manufacturer ID */ + uint16_t oid; /* 119:104 16-bit OEM/Application ID (ascii) */ + uint8_t pnm[6]; /* 103:64 40-bit Product Name (ascii) + null terminator */ + uint8_t prv; /* 63:56 8-bit Product revision */ + uint32_t psn; /* 55:24 32-bit Product serial number */ + /* 23:20 4-bit (reserved) */ + uint16_t mdt; /* 19:8 12-bit Manufacturing date */ + uint8_t crc; /* 7:1 7-bit CRC7 */ + /* 0:0 1-bit (not used) */ +}; + +/* Decoded Card Specific Data (CSD) register */ + +struct mmcsd_csd_s +{ + uint8_t csdstructure; /* 127:126 CSD structure */ + uint8_t mmcspecvers; /* 125:122 MMC Spec version (MMC only) */ + + struct + { + uint8_t timeunit; /* 2:0 Time exponent */ + uint8_t timevalue; /* 6:3 Time mantissa */ + } taac; /* 119:112 Data read access-time-1 */ + + uint8_t nsac; /* 111:104 Data read access-time-2 in CLK cycle(NSAC*100) */ + + struct + { + uint8_t transferrateunit; /* 2:0 Rate exponent */ + uint8_t timevalue; /* 6:3 Rate mantissa */ + } transpeed; /* 103:96 Max. data transfer rate */ + + uint16_t ccc; /* 95:84 Card command classes */ + uint8_t readbllen; /* 83:80 Max. read data block length */ + uint8_t readblpartial; /* 79:79 Partial blocks for read allowed */ + uint8_t writeblkmisalign; /* 78:78 Write block misalignment */ + uint8_t readblkmisalign; /* 77:77 Read block misalignment */ + uint8_t dsrimp; /* 76:76 DSR implemented */ + + union + { +#ifdef CONFIG_MMCSD_MMCSUPPORT + struct + { + uint16_t csize; /* 73:62 Device size */ + uint8_t vddrcurrmin; /* 61:59 Max. read current at Vdd min */ + uint8_t vddrcurrmax; /* 58:56 Max. read current at Vdd max */ + uint8_t vddwcurrmin; /* 55:53 Max. write current at Vdd min */ + uint8_t vddwcurrmax; /* 52:50 Max. write current at Vdd max */ + uint8_t csizemult; /* 49:47 Device size multiplier */ + + union + { + struct /* MMC system specification version 3.1 */ + { + uint8_t ergrpsize; /* 46:42 Erase group size (MMC 3.1) */ + uint8_t ergrpmult; /* 41:37 Erase group multiplier (MMC 3.1) */ + } mmc31; + struct /* MMC system specification version 2.2 */ + { + uint8_t sectorsize; /* 46:42 Erase sector size (MMC 2.2) */ + uint8_t ergrpsize; /* 41:37 Erase group size (MMC 2.2) */ + } mmc22; + } er; + + uint8_t mmcwpgrpsize; /* 36:32 Write protect group size (MMC) */ + } mmc; +#endif + struct + { + uint16_t csize; /* 73:62 Device size */ + uint8_t vddrcurrmin; /* 61:59 Max. read current at Vdd min */ + uint8_t vddrcurrmax; /* 58:56 Max. read current at Vdd max */ + uint8_t vddwcurrmin; /* 55:53 Max. write current at Vdd min */ + uint8_t vddwcurrmax; /* 52:50 Max. write current at Vdd max */ + uint8_t csizemult; /* 49:47 Device size multiplier */ + uint8_t sderblen; /* 46:46 Erase single block enable (SD) */ + uint8_t sdsectorsize; /* 45:39 Erase sector size (SD) */ + uint8_t sdwpgrpsize; /* 38:32 Write protect group size (SD) */ + } sdbyte; + + struct + { + /* 73:70 (reserved) */ + uint32_t csize; /* 69:48 Device size */ + /* 47:47 (reserved) */ + uint8_t sderblen; /* 46:46 Erase single block enable (SD) */ + uint8_t sdsectorsize; /* 45:39 Erase sector size (SD) */ + uint8_t sdwpgrpsize; /* 38:32 Write protect group size (SD) */ + } sdblock; + } u; + + uint8_t wpgrpen; /* 31:31 Write protect group enable */ + uint8_t mmcdfltecc; /* 30:29 Manufacturer default ECC (MMC) */ + uint8_t r2wfactor; /* 28:26 Write speed factor */ + uint8_t writebllen; /* 25:22 Max. write data block length */ + uint8_t writeblpartial; /* 21:21 Partial blocks for write allowed */ + uint8_t fileformatgrp; /* 15:15 File format group */ + uint8_t copy; /* 14:14 Copy flag (OTP) */ + uint8_t permwriteprotect; /* 13:13 Permanent write protection */ + uint8_t tmpwriteprotect; /* 12:12 Temporary write protection */ + uint8_t fileformat; /* 10:11 File format */ + uint8_t mmcecc; /* 9:8 ECC (MMC) */ + uint8_t crc; /* 7:1 CRC */ + /* 0:0 Not used */ +}; + +struct mmcsd_scr_s +{ + uint8_t scrversion; /* 63:60 Version of SCR structure */ + uint8_t sdversion; /* 59:56 SD memory card physical layer version */ + uint8_t erasestate; /* 55:55 Data state after erase (1 or 0) */ + uint8_t security; /* 54:52 SD security support */ + uint8_t buswidth; /* 51:48 DAT bus widthes supported */ + /* 47:32 SD reserved space */ + uint32_t mfgdata; /* 31:0 Reserved for manufacturing data */ +}; + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __DRIVERS_MMCSD_MMCSD_SDIO_H */ diff --git a/drivers/mmcsd/mmcsd_spi.h b/drivers/mmcsd/mmcsd_spi.h index 055862bebdae4a421099fe795afd010e809489e5..8c6f9bae716d5b75e0f524f4ec0f06a09a469901 100644 --- a/drivers/mmcsd/mmcsd_spi.h +++ b/drivers/mmcsd/mmcsd_spi.h @@ -2,7 +2,7 @@ * drivers/mmcsd/mmcsd_spi.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/mtd/at45db.c b/drivers/mtd/at45db.c index f4a695de01370af4dc14d99da068acf50296ca81..f3c0c72c14ac4e4772389f57ed826054f0f55ca4 100644 --- a/drivers/mtd/at45db.c +++ b/drivers/mtd/at45db.c @@ -3,7 +3,7 @@ * Driver for SPI-based AT45DB161D (16Mbit) * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/mtd/flash_eraseall.c b/drivers/mtd/flash_eraseall.c index 77666ff03df0c0b8e356fb84a8a33618e465be81..ce0cfe64916f27cd34a9fe115f0186da8ac843c1 100644 --- a/drivers/mtd/flash_eraseall.c +++ b/drivers/mtd/flash_eraseall.c @@ -2,7 +2,7 @@ * drivers/mtd/flash_eraseall.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/mtd/ftl.c b/drivers/mtd/ftl.c index b16397883f78beb0839e3d07678f2ff8f2414e90..cdb35aa5cdfc8783da716c99527474b0a337e7cf 100644 --- a/drivers/mtd/ftl.c +++ b/drivers/mtd/ftl.c @@ -2,7 +2,7 @@ * drivers/mtd/ftl.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/mtd/skeleton.c b/drivers/mtd/skeleton.c index 673ddadb354db590f79a2419799a5eb935d26002..a2fb98238760d34ed0fb1f2529fe2acaa01cd219 100644 --- a/drivers/mtd/skeleton.c +++ b/drivers/mtd/skeleton.c @@ -2,7 +2,7 @@ * drivers/mtd/skeleton.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/net/cs89x0.c b/drivers/net/cs89x0.c index 0f301ee00377ff56f1d4f2f4615c5833dd40bf99..22b9b87a5f13d10c627394b452f79466f20b5a11 100644 --- a/drivers/net/cs89x0.c +++ b/drivers/net/cs89x0.c @@ -2,7 +2,7 @@ * drivers/net/cs89x0.c * * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/net/cs89x0.h b/drivers/net/cs89x0.h index c2073eb9885fcdc36de20bcae57a85aba46f6ea0..f6d99120ab6dd6588a83fdf1e5665ff4e8b9da3c 100644 --- a/drivers/net/cs89x0.h +++ b/drivers/net/cs89x0.h @@ -1,326 +1,326 @@ -/**************************************************************************** - * drivers/net/cs89x0.h - * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __DRIVERS_NET_CS89x0_H -#define __DRIVERS_NET_CS89x0_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* CONFIG_CS89x0_ALIGN16/32 determines if the 16-bit CS89x0 registers are - * aligned to 16-bit or 32-bit address boundaries. NOTE: If there multiple - * CS89x00 parts in the board architecture, we assume that the address - * alignment is the same for all implementations. If that is not the - * case, then it will be necessary to move a shift value into - * the cs89x0_driver_s structure and calculate the offsets dynamically in - * the putreg and getreg functions. - */ - -#if defined(CONFIG_CS89x0_ALIGN16) -# define CS89x0_RTDATA_OFFSET (0 << 1) -# define CS89x0_TxCMD_OFFSET (2 << 1) -# define CS89x0_TxLEN_OFFSET (3 << 1) -# define CS89x0_ISQ_OFFSET (4 << 1) -# define CS89x0_PPTR_OFFSET (5 << 1) -# define CS89x0_PDATA_OFFSET (6 << 1) -#elif defined(CONFIG_CS89x0_ALIGN32) -# define CS89x0_RTDATA_OFFSET (0 << 2) -# define CS89x0_TxCMD_OFFSET (2 << 2) -# define CS89x0_TxLEN_OFFSET (3 << 2) -# define CS89x0_ISQ_OFFSET (4 << 2) -# define CS89x0_PPTR_OFFSET (5 << 2) -# define CS89x0_PDATA_OFFSET (6 << 2) -#else -# error "CS89x00 address alignment is not defined" -#endif - -/* ISQ register bit definitions */ - -#define ISQ_EVENTMASK 0x003f /* Bits 0-5 indicate the status register */ -#define ISQ_RXEVENT 0x0004 -#define ISQ_TXEVENT 0x0008 -#define ISQ_BUFEVENT 0x000c -#define ISQ_RXMISSEVENT 0x0010 -#define ISQ_TXCOLEVENT 0x0012 - -/* ISQ register TxEVENT bit definitions*/ - -#define ISQ_RXEVENT_IAHASH (1 << 6) -#define ISQ_RXEVENT_DRIBBLE (1 << 7) -#define ISQ_RXEVENT_RXOK (1 << 8) -#define ISQ_RXEVENT_HASHED (1 << 9) -#define ISQ_RXEVENT_HASHNDX_SHIFT 10 -#define ISQ_RXEVENT_HASHNDX_MASK (0x3f << ISQ_RXEVENT_HASHNDX_SHIFT) - -/* ISQ register TxEVENT bit definitions*/ - -#define ISQ_TXEVENT_LOSSOFCRS (1 << 6) -#define ISQ_TXEVENT_SQEERROR (1 << 7) -#define ISQ_TXEVENT_TXOK (1 << 8) -#define ISQ_TXEVENT_OUTWINDOW (1 << 9) -#define ISQ_TXEVENT_JABBER (1 << 10) -#define ISQ_TXEVENT_NCOLLISION_SHIFT 11 -#define ISQ_TXEVENT_NCOLLISION_MASK (15 << ISQ_TXEVENT_NCOLLISION_SHIFT) -#define ISQ_TXEVENT_16COLL (1 << 15) - -/* ISQ register BufEVENT bit definitions */ - -#define ISQ_BUFEVENT_SWINT (1 << 6) -#define ISQ_BUFEVENT_RXDMAFRAME (1 << 7) -#define ISQ_BUFEVENT_RDY4TX (1 << 8) -#define ISQ_BUFEVENT_TXUNDERRUN (1 << 9) -#define ISQ_BUFEVENT_RXMISS (1 << 10) -#define ISQ_BUFEVENT_RX128 (1 << 11) -#define ISQ_BUFEVENT_RXDEST (1 << 15) - -/* Packet page register offsets *********************************************/ - -/* 0x0000 Bus interface registers */ - -#define PPR_CHIPID 0x0000 /* Chip identifier - must be 0x630E */ -#define PPR_CHIPREV 0x0002 /* Chip revision, model codes */ -#define PPR_IOBASEADDRESS 0x0020 /* I/O Base Address */ -#define PPR_INTREG 0x0022 /* Interrupt configuration */ -# define PPR_INTREG_IRQ0 0x0000 /* Use INTR0 pin */ -# define PPR_INTREG_IRQ1 0x0001 /* Use INTR1 pin */ -# define PPR_INTREG_IRQ2 0x0002 /* Use INTR2 pin */ -# define PPR_INTREG_IRQ3 0x0003 /* Use INTR3 pin */ - -#define PPR_DMACHANNELNUMBER 0x0024 /* DMA Channel Number (0,1, or 2) */ -#define PPR_DMASTARTOFFRAME 0x0026 /* DMA Start of Frame */ -#define PPR_DMAFRAMECOUNT 0x0028 /* DMA Frame Count (12-bits) */ -#define PPR_RXDMABYTECOUNT 0x002a /* Rx DMA Byte Count */ -#define PPR_MEMORYBASEADDRESS 0x002c /* Memory Base Address Register (20-bit) */ -#define PPR_BOOTPROMBASEADDRESS 0x0030 /* Boot PROM Base Address */ -#define PPR_BOOTPROMADDRESSMASK 0x0034 /* Boot PROM Address Mask */ -#define PPR_EEPROMCOMMAND 0x0040 /* EEPROM Command */ -#define PPR_EEPROMDATA 0x0042 /* EEPROM Data */ -#define PPR_RECVFRAMEBYTES 0x0050 /* Received Frame Byte Counter */ - -/* 0x0100 - Configuration and control registers */ - -#define PPR_RXCFG 0x0102 /* Receiver configuration */ -# define PPR_RXCFG_SKIP1 (1 << 6) /* Skip (discard) current frame */ -# define PPR_RXCFG_STREAM (1 << 7) /* Enable streaming mode */ -# define PPR_RXCFG_RXOK (1 << 8) /* RxOK interrupt enable */ -# define PPR_RxCFG_RxDMAonly (1 << 9) /* Use RxDMA for all frames */ -# define PPR_RxCFG_AutoRxDMA (1 << 10) /* Select RxDMA automatically */ -# define PPR_RxCFG_BufferCRC (1 << 11) /* Include CRC characters in frame */ -# define PPR_RxCFG_CRC (1 << 12) /* Enable interrupt on CRC error */ -# define PPR_RxCFG_RUNT (1 << 13) /* Enable interrupt on RUNT frames */ -# define PPR_RxCFG_EXTRA (1 << 14) /* Enable interrupt on frames with extra data */ - -#define PPR_RXCTL 0x0104 /* Receiver control */ -# define PPR_RXCTL_IAHASH (1 << 6) /* Accept frames that match hash */ -# define PPR_RXCTL_PROMISCUOUS (1 << 7) /* Accept any frame */ -# define PPR_RXCTL_RXOK (1 << 8) /* Accept well formed frames */ -# define PPR_RXCTL_MULTICAST (1 << 9) /* Accept multicast frames */ -# define PPR_RXCTL_IA (1 << 10) /* Accept frame that matches IA */ -# define PPR_RXCTL_BROADCAST (1 << 11) /* Accept broadcast frames */ -# define PPR_RXCTL_CRC (1 << 12) /* Accept frames with bad CRC */ -# define PPR_RXCTL_RUNT (1 << 13) /* Accept runt frames */ -# define PPR_RXCTL_EXTRA (1 << 14) /* Accept frames that are too long */ - -#define PPR_TXCFG 0x0106 /* Transmit configuration */ -# define PPR_TXCFG_CRS (1 << 6) /* Enable interrupt on loss of carrier */ -# define PPR_TXCFG_SQE (1 << 7) /* Enable interrupt on Signal Quality Error */ -# define PPR_TXCFG_TXOK (1 << 8) /* Enable interrupt on successful xmits */ -# define PPR_TXCFG_LATE (1 << 9) /* Enable interrupt on "out of window" */ -# define PPR_TXCFG_JABBER (1 << 10) /* Enable interrupt on jabber detect */ -# define PPR_TXCFG_COLLISION (1 << 11) /* Enable interrupt if collision */ -# define PPR_TXCFG_16COLLISIONS (1 << 15) /* Enable interrupt if > 16 collisions */ - -#define PPR_TXCMD 0x0108 /* Transmit command status */ -# define PPR_TXCMD_TXSTART5 (0 << 6) /* Start after 5 bytes in buffer */ -# define PPR_TXCMD_TXSTART381 (1 << 6) /* Start after 381 bytes in buffer */ -# define PPR_TXCMD_TXSTART1021 (2 << 6) /* Start after 1021 bytes in buffer */ -# define PPR_TXCMD_TXSTARTFULL (3 << 6) /* Start after all bytes loaded */ -# define PPR_TXCMD_FORCE (1 << 8) /* Discard any pending packets */ -# define PPR_TXCMD_ONECOLLISION (1 << 9) /* Abort after a single collision */ -# define PPR_TXCMD_NOCRC (1 << 12) /* Do not add CRC */ -# define PPR_TXCMD_NOPAD (1 << 13) /* Do not pad short packets */ - -#define PPR_BUFCFG 0x010a /* Buffer configuration */ -# define PPR_BUFCFG_SWI (1 << 6) /* Force interrupt via software */ -# define PPR_BUFCFG_RXDMA (1 << 7) /* Enable interrupt on Rx DMA */ -# define PPR_BUFCFG_TXRDY (1 << 8) /* Enable interrupt when ready for Tx */ -# define PPR_BUFCFG_TXUE (1 << 9) /* Enable interrupt in Tx underrun */ -# define PPR_BUFCFG_RXMISS (1 << 10) /* Enable interrupt on missed Rx packets */ -# define PPR_BUFCFG_RX128 (1 << 11) /* Enable Rx interrupt after 128 bytes */ -# define PPR_BUFCFG_TXCOL (1 << 12) /* Enable int on Tx collision ctr overflow */ -# define PPR_BUFCFG_MISS (1 << 13) /* Enable int on Rx miss ctr overflow */ -# define PPR_BUFCFG_RXDEST (1 << 15) /* Enable int on Rx dest addr match */ - -#define PPR_LINECTL 0x0112 /* Line control */ -# define PPR_LINECTL_RX (1 << 6) /* Enable receiver */ -# define PPR_LINECTL_TX (1 << 7) /* Enable transmitter */ -# define PPR_LINECTL_AUIONLY (1 << 8) /* AUI interface only */ -# define PPR_LINECTL_AUTOAUI10BT (1 << 9) /* Autodetect AUI or 10BaseT interface */ -# define PPR_LINECTL_MODBACKOFFE (1 << 11) /* Enable modified backoff algorithm */ -# define PPR_LINECTL_POLARITYDIS (1 << 12) /* Disable Rx polarity autodetect */ -# define PPR_LINECTL_2PARTDEFDIS (1 << 13) /* Disable two-part defferal */ -# define PPR_LINECTL_LORXSQUELCH (1 << 14) /* Reduce receiver squelch threshold */ - -#define PPR_SELFCTL 0x0114 /* Chip self control */ -# define PPR_SELFCTL_RESET (1 << 6) /* Self-clearing reset */ -# define PPR_SELFCTL_SWSUSPEND (1 << 8) /* Initiate suspend mode */ -# define PPR_SELFCTL_HWSLEEPE (1 << 9) /* Enable SLEEP input */ -# define PPR_SELFCTL_HWSTANDBYE (1 << 10) /* Enable standby mode */ -# define PPR_SELFCTL_HC0E (1 << 12) /* Use HCB0 for LINK LED */ -# define PPR_SELFCTL_HC1E (1 << 13) /* Use HCB1 for BSTATUS LED */ -# define PPR_SELFCTL_HCB0 (1 << 14) /* Control LINK LED if HC0E set */ -# define PPR_SELFCTL_HCB1 (1 << 15) /* Cntrol BSTATUS LED if HC1E set */ - -#define PPR_BUSCTL 0x0116 /* Bus control */ -# define PPR_BUSCTL_RESETRXDMA (1 << 6) /* Reset RxDMA pointer */ -# define PPR_BUSCTL_DMAEXTEND (1 << 8) /* Extend DMA cycle */ -# define PPR_BUSCTL_USESA (1 << 9) /* Assert MEMCS16 on address decode */ -# define PPR_BUSCTL_MEMORYE (1 << 10) /* Enable memory mode */ -# define PPR_BUSCTL_DMABURST (1 << 11) /* Limit DMA access burst */ -# define PPR_BUSCTL_IOCHRDYE (1 << 12) /* Set IOCHRDY high impedence */ -# define PPR_BUSCTL_RXDMASIZE (1 << 13) /* Set DMA buffer size 64KB */ -# define PPR_BUSCTL_ENABLEIRQ (1 << 15) /* Generate interrupt on interrupt event */ - -#define PPR_TESTCTL 0x0118 /* Test control */ -# define PPR_TESTCTL_DISABLELT (1 << 7) /* Disable link status */ -# define PPR_TESTCTL_ENDECLOOP (1 << 9) /* Internal loopback */ -# define PPR_TESTCTL_AUILOOP (1 << 10) /* AUI loopback */ -# define PPR_TESTCTL_DISBACKOFF (1 << 11) /* Disable backoff algorithm */ -# define PPR_TESTCTL_FDX (1 << 14) /* Enable full duplex mode */ - -/* 0x0120 - Status and Event Registers */ - -#define PPR_ISQ 0x0120 /* Interrupt Status Queue */ -#define PPR_RER 0x0124 /* Receive event */ -# define PPR_RER_IAHASH (1 << 6) /* Frame hash match */ -# define PPR_RER_DRIBBLE (1 << 7) /* Frame had 1-7 extra bits after last byte */ -# define PPR_RER_RXOK (1 << 8) /* Frame received with no errors */ -# define PPR_RER_HASHED (1 << 9) /* Frame address hashed OK */ -# define PPR_RER_IA (1 << 10) /* Frame address matched IA */ -# define PPR_RER_BROADCAST (1 << 11) /* Broadcast frame */ -# define PPR_RER_CRC (1 << 12) /* Frame had CRC error */ -# define PPR_RER_RUNT (1 << 13) /* Runt frame */ -# define PPR_RER_EXTRA (1 << 14) /* Frame was too long */ - -#define PPR_TER 0x0128 /* Transmit event */ -# define PPR_TER_CRS (1 << 6) /* Carrier lost */ -# define PPR_TER_SQE (1 << 7) /* Signal Quality Error */ -# define PPR_TER_TXOK (1 << 8) /* Packet sent without error */ -# define PPR_TER_LATE (1 << 9) /* Out of window */ -# define PPR_TER_JABBER (1 << 10) /* Stuck transmit? */ -# define PPR_TER_NUMCOLLISIONS_SHIFT 11 -# define PPR_TER_NUMCOLLISIONS_MASK (15 << PPR_TER_NUMCOLLISIONS_SHIFT) -# define PPR_TER_16COLLISIONS (1 << 15) /* > 16 collisions */ - -#define PPR_BER 0x012C /* Buffer event */ -# define PPR_BER_SWINT (1 << 6) /* Software interrupt */ -# define PPR_BER_RXDMAFRAME (1 << 7) /* Received framed DMAed */ -# define PPR_BER_RDY4TX (1 << 8) /* Ready for transmission */ -# define PPR_BER_TXUNDERRUN (1 << 9) /* Transmit underrun */ -# define PPR_BER_RXMISS (1 << 10) /* Received frame missed */ -# define PPR_BER_RX128 (1 << 11) /* 128 bytes received */ -# define PPR_BER_RXDEST (1 << 15) /* Received framed passed address filter */ - -#define PPR_RXMISS 0x0130 /* Receiver miss counter */ -#define PPR_TXCOL 0x0132 /* Transmit collision counter */ -#define PPR_LINESTAT 0x0134 /* Line status */ -# define PPR_LINESTAT_LINKOK (1 << 7) /* Line is connected and working */ -# define PPR_LINESTAT_AUI (1 << 8) /* Connected via AUI */ -# define PPR_LINESTAT_10BT (1 << 9) /* Connected via twisted pair */ -# define PPR_LINESTAT_POLARITY (1 << 12) /* Line polarity OK (10BT only) */ -# define PPR_LINESTAT_CRS (1 << 14) /* Frame being received */ - -#define PPR_SELFSTAT 0x0136 /* Chip self status */ -# define PPR_SELFSTAT_33VACTIVE (1 << 6) /* supply voltage is 3.3V */ -# define PPR_SELFSTAT_INITD (1 << 7) /* Chip initialization complete */ -# define PPR_SELFSTAT_SIBSY (1 << 8) /* EEPROM is busy */ -# define PPR_SELFSTAT_EEPROM (1 << 9) /* EEPROM present */ -# define PPR_SELFSTAT_EEPROMOK (1 << 10) /* EEPROM checks out */ -# define PPR_SELFSTAT_ELPRESENT (1 << 11) /* External address latch logic available */ -# define PPR_SELFSTAT_EESIZE (1 << 12) /* Size of EEPROM */ - -#define PPR_BUSSTAT 0x0138 /* Bus status */ -# define PPR_BUSSTAT_TXBID (1 << 7) /* Tx error */ -# define PPR_BUSSTAT_TXRDY (1 << 8) /* Ready for Tx data */ - -#define PPR_TDR 0x013C /* AUI Time Domain Reflectometer */ - -/* 0x0144 - Initiate transmit registers */ - -#define PPR_TXCOMMAND 0x0144 /* Tx Command */ -#define PPR_TXLENGTH 0x0146 /* Tx Length */ - -/* 0x0150 - Address filter registers */ - -#define PPR_LAF 0x0150 /* Logical address filter (6 bytes) */ -#define PPR_IA 0x0158 /* Individual address (MAC) */ - -/* 0x0400 - Frame location registers */ - -#define PPR_RXSTATUS 0x0400 /* Rx Status */ -#define PPR_RXLENGTH 0x0402 /* Rx Length */ -#define PPR_RXFRAMELOCATION 0x0404 /* Rx Frame Location */ -#define PPR_TXFRAMELOCATION 0x0a00 /* Tx Frame Location */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __DRIVERS_NET_CS89x0_H */ +/**************************************************************************** + * drivers/net/cs89x0.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __DRIVERS_NET_CS89x0_H +#define __DRIVERS_NET_CS89x0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* CONFIG_CS89x0_ALIGN16/32 determines if the 16-bit CS89x0 registers are + * aligned to 16-bit or 32-bit address boundaries. NOTE: If there multiple + * CS89x00 parts in the board architecture, we assume that the address + * alignment is the same for all implementations. If that is not the + * case, then it will be necessary to move a shift value into + * the cs89x0_driver_s structure and calculate the offsets dynamically in + * the putreg and getreg functions. + */ + +#if defined(CONFIG_CS89x0_ALIGN16) +# define CS89x0_RTDATA_OFFSET (0 << 1) +# define CS89x0_TxCMD_OFFSET (2 << 1) +# define CS89x0_TxLEN_OFFSET (3 << 1) +# define CS89x0_ISQ_OFFSET (4 << 1) +# define CS89x0_PPTR_OFFSET (5 << 1) +# define CS89x0_PDATA_OFFSET (6 << 1) +#elif defined(CONFIG_CS89x0_ALIGN32) +# define CS89x0_RTDATA_OFFSET (0 << 2) +# define CS89x0_TxCMD_OFFSET (2 << 2) +# define CS89x0_TxLEN_OFFSET (3 << 2) +# define CS89x0_ISQ_OFFSET (4 << 2) +# define CS89x0_PPTR_OFFSET (5 << 2) +# define CS89x0_PDATA_OFFSET (6 << 2) +#else +# error "CS89x00 address alignment is not defined" +#endif + +/* ISQ register bit definitions */ + +#define ISQ_EVENTMASK 0x003f /* Bits 0-5 indicate the status register */ +#define ISQ_RXEVENT 0x0004 +#define ISQ_TXEVENT 0x0008 +#define ISQ_BUFEVENT 0x000c +#define ISQ_RXMISSEVENT 0x0010 +#define ISQ_TXCOLEVENT 0x0012 + +/* ISQ register TxEVENT bit definitions*/ + +#define ISQ_RXEVENT_IAHASH (1 << 6) +#define ISQ_RXEVENT_DRIBBLE (1 << 7) +#define ISQ_RXEVENT_RXOK (1 << 8) +#define ISQ_RXEVENT_HASHED (1 << 9) +#define ISQ_RXEVENT_HASHNDX_SHIFT 10 +#define ISQ_RXEVENT_HASHNDX_MASK (0x3f << ISQ_RXEVENT_HASHNDX_SHIFT) + +/* ISQ register TxEVENT bit definitions*/ + +#define ISQ_TXEVENT_LOSSOFCRS (1 << 6) +#define ISQ_TXEVENT_SQEERROR (1 << 7) +#define ISQ_TXEVENT_TXOK (1 << 8) +#define ISQ_TXEVENT_OUTWINDOW (1 << 9) +#define ISQ_TXEVENT_JABBER (1 << 10) +#define ISQ_TXEVENT_NCOLLISION_SHIFT 11 +#define ISQ_TXEVENT_NCOLLISION_MASK (15 << ISQ_TXEVENT_NCOLLISION_SHIFT) +#define ISQ_TXEVENT_16COLL (1 << 15) + +/* ISQ register BufEVENT bit definitions */ + +#define ISQ_BUFEVENT_SWINT (1 << 6) +#define ISQ_BUFEVENT_RXDMAFRAME (1 << 7) +#define ISQ_BUFEVENT_RDY4TX (1 << 8) +#define ISQ_BUFEVENT_TXUNDERRUN (1 << 9) +#define ISQ_BUFEVENT_RXMISS (1 << 10) +#define ISQ_BUFEVENT_RX128 (1 << 11) +#define ISQ_BUFEVENT_RXDEST (1 << 15) + +/* Packet page register offsets *********************************************/ + +/* 0x0000 Bus interface registers */ + +#define PPR_CHIPID 0x0000 /* Chip identifier - must be 0x630E */ +#define PPR_CHIPREV 0x0002 /* Chip revision, model codes */ +#define PPR_IOBASEADDRESS 0x0020 /* I/O Base Address */ +#define PPR_INTREG 0x0022 /* Interrupt configuration */ +# define PPR_INTREG_IRQ0 0x0000 /* Use INTR0 pin */ +# define PPR_INTREG_IRQ1 0x0001 /* Use INTR1 pin */ +# define PPR_INTREG_IRQ2 0x0002 /* Use INTR2 pin */ +# define PPR_INTREG_IRQ3 0x0003 /* Use INTR3 pin */ + +#define PPR_DMACHANNELNUMBER 0x0024 /* DMA Channel Number (0,1, or 2) */ +#define PPR_DMASTARTOFFRAME 0x0026 /* DMA Start of Frame */ +#define PPR_DMAFRAMECOUNT 0x0028 /* DMA Frame Count (12-bits) */ +#define PPR_RXDMABYTECOUNT 0x002a /* Rx DMA Byte Count */ +#define PPR_MEMORYBASEADDRESS 0x002c /* Memory Base Address Register (20-bit) */ +#define PPR_BOOTPROMBASEADDRESS 0x0030 /* Boot PROM Base Address */ +#define PPR_BOOTPROMADDRESSMASK 0x0034 /* Boot PROM Address Mask */ +#define PPR_EEPROMCOMMAND 0x0040 /* EEPROM Command */ +#define PPR_EEPROMDATA 0x0042 /* EEPROM Data */ +#define PPR_RECVFRAMEBYTES 0x0050 /* Received Frame Byte Counter */ + +/* 0x0100 - Configuration and control registers */ + +#define PPR_RXCFG 0x0102 /* Receiver configuration */ +# define PPR_RXCFG_SKIP1 (1 << 6) /* Skip (discard) current frame */ +# define PPR_RXCFG_STREAM (1 << 7) /* Enable streaming mode */ +# define PPR_RXCFG_RXOK (1 << 8) /* RxOK interrupt enable */ +# define PPR_RxCFG_RxDMAonly (1 << 9) /* Use RxDMA for all frames */ +# define PPR_RxCFG_AutoRxDMA (1 << 10) /* Select RxDMA automatically */ +# define PPR_RxCFG_BufferCRC (1 << 11) /* Include CRC characters in frame */ +# define PPR_RxCFG_CRC (1 << 12) /* Enable interrupt on CRC error */ +# define PPR_RxCFG_RUNT (1 << 13) /* Enable interrupt on RUNT frames */ +# define PPR_RxCFG_EXTRA (1 << 14) /* Enable interrupt on frames with extra data */ + +#define PPR_RXCTL 0x0104 /* Receiver control */ +# define PPR_RXCTL_IAHASH (1 << 6) /* Accept frames that match hash */ +# define PPR_RXCTL_PROMISCUOUS (1 << 7) /* Accept any frame */ +# define PPR_RXCTL_RXOK (1 << 8) /* Accept well formed frames */ +# define PPR_RXCTL_MULTICAST (1 << 9) /* Accept multicast frames */ +# define PPR_RXCTL_IA (1 << 10) /* Accept frame that matches IA */ +# define PPR_RXCTL_BROADCAST (1 << 11) /* Accept broadcast frames */ +# define PPR_RXCTL_CRC (1 << 12) /* Accept frames with bad CRC */ +# define PPR_RXCTL_RUNT (1 << 13) /* Accept runt frames */ +# define PPR_RXCTL_EXTRA (1 << 14) /* Accept frames that are too long */ + +#define PPR_TXCFG 0x0106 /* Transmit configuration */ +# define PPR_TXCFG_CRS (1 << 6) /* Enable interrupt on loss of carrier */ +# define PPR_TXCFG_SQE (1 << 7) /* Enable interrupt on Signal Quality Error */ +# define PPR_TXCFG_TXOK (1 << 8) /* Enable interrupt on successful xmits */ +# define PPR_TXCFG_LATE (1 << 9) /* Enable interrupt on "out of window" */ +# define PPR_TXCFG_JABBER (1 << 10) /* Enable interrupt on jabber detect */ +# define PPR_TXCFG_COLLISION (1 << 11) /* Enable interrupt if collision */ +# define PPR_TXCFG_16COLLISIONS (1 << 15) /* Enable interrupt if > 16 collisions */ + +#define PPR_TXCMD 0x0108 /* Transmit command status */ +# define PPR_TXCMD_TXSTART5 (0 << 6) /* Start after 5 bytes in buffer */ +# define PPR_TXCMD_TXSTART381 (1 << 6) /* Start after 381 bytes in buffer */ +# define PPR_TXCMD_TXSTART1021 (2 << 6) /* Start after 1021 bytes in buffer */ +# define PPR_TXCMD_TXSTARTFULL (3 << 6) /* Start after all bytes loaded */ +# define PPR_TXCMD_FORCE (1 << 8) /* Discard any pending packets */ +# define PPR_TXCMD_ONECOLLISION (1 << 9) /* Abort after a single collision */ +# define PPR_TXCMD_NOCRC (1 << 12) /* Do not add CRC */ +# define PPR_TXCMD_NOPAD (1 << 13) /* Do not pad short packets */ + +#define PPR_BUFCFG 0x010a /* Buffer configuration */ +# define PPR_BUFCFG_SWI (1 << 6) /* Force interrupt via software */ +# define PPR_BUFCFG_RXDMA (1 << 7) /* Enable interrupt on Rx DMA */ +# define PPR_BUFCFG_TXRDY (1 << 8) /* Enable interrupt when ready for Tx */ +# define PPR_BUFCFG_TXUE (1 << 9) /* Enable interrupt in Tx underrun */ +# define PPR_BUFCFG_RXMISS (1 << 10) /* Enable interrupt on missed Rx packets */ +# define PPR_BUFCFG_RX128 (1 << 11) /* Enable Rx interrupt after 128 bytes */ +# define PPR_BUFCFG_TXCOL (1 << 12) /* Enable int on Tx collision ctr overflow */ +# define PPR_BUFCFG_MISS (1 << 13) /* Enable int on Rx miss ctr overflow */ +# define PPR_BUFCFG_RXDEST (1 << 15) /* Enable int on Rx dest addr match */ + +#define PPR_LINECTL 0x0112 /* Line control */ +# define PPR_LINECTL_RX (1 << 6) /* Enable receiver */ +# define PPR_LINECTL_TX (1 << 7) /* Enable transmitter */ +# define PPR_LINECTL_AUIONLY (1 << 8) /* AUI interface only */ +# define PPR_LINECTL_AUTOAUI10BT (1 << 9) /* Autodetect AUI or 10BaseT interface */ +# define PPR_LINECTL_MODBACKOFFE (1 << 11) /* Enable modified backoff algorithm */ +# define PPR_LINECTL_POLARITYDIS (1 << 12) /* Disable Rx polarity autodetect */ +# define PPR_LINECTL_2PARTDEFDIS (1 << 13) /* Disable two-part defferal */ +# define PPR_LINECTL_LORXSQUELCH (1 << 14) /* Reduce receiver squelch threshold */ + +#define PPR_SELFCTL 0x0114 /* Chip self control */ +# define PPR_SELFCTL_RESET (1 << 6) /* Self-clearing reset */ +# define PPR_SELFCTL_SWSUSPEND (1 << 8) /* Initiate suspend mode */ +# define PPR_SELFCTL_HWSLEEPE (1 << 9) /* Enable SLEEP input */ +# define PPR_SELFCTL_HWSTANDBYE (1 << 10) /* Enable standby mode */ +# define PPR_SELFCTL_HC0E (1 << 12) /* Use HCB0 for LINK LED */ +# define PPR_SELFCTL_HC1E (1 << 13) /* Use HCB1 for BSTATUS LED */ +# define PPR_SELFCTL_HCB0 (1 << 14) /* Control LINK LED if HC0E set */ +# define PPR_SELFCTL_HCB1 (1 << 15) /* Cntrol BSTATUS LED if HC1E set */ + +#define PPR_BUSCTL 0x0116 /* Bus control */ +# define PPR_BUSCTL_RESETRXDMA (1 << 6) /* Reset RxDMA pointer */ +# define PPR_BUSCTL_DMAEXTEND (1 << 8) /* Extend DMA cycle */ +# define PPR_BUSCTL_USESA (1 << 9) /* Assert MEMCS16 on address decode */ +# define PPR_BUSCTL_MEMORYE (1 << 10) /* Enable memory mode */ +# define PPR_BUSCTL_DMABURST (1 << 11) /* Limit DMA access burst */ +# define PPR_BUSCTL_IOCHRDYE (1 << 12) /* Set IOCHRDY high impedence */ +# define PPR_BUSCTL_RXDMASIZE (1 << 13) /* Set DMA buffer size 64KB */ +# define PPR_BUSCTL_ENABLEIRQ (1 << 15) /* Generate interrupt on interrupt event */ + +#define PPR_TESTCTL 0x0118 /* Test control */ +# define PPR_TESTCTL_DISABLELT (1 << 7) /* Disable link status */ +# define PPR_TESTCTL_ENDECLOOP (1 << 9) /* Internal loopback */ +# define PPR_TESTCTL_AUILOOP (1 << 10) /* AUI loopback */ +# define PPR_TESTCTL_DISBACKOFF (1 << 11) /* Disable backoff algorithm */ +# define PPR_TESTCTL_FDX (1 << 14) /* Enable full duplex mode */ + +/* 0x0120 - Status and Event Registers */ + +#define PPR_ISQ 0x0120 /* Interrupt Status Queue */ +#define PPR_RER 0x0124 /* Receive event */ +# define PPR_RER_IAHASH (1 << 6) /* Frame hash match */ +# define PPR_RER_DRIBBLE (1 << 7) /* Frame had 1-7 extra bits after last byte */ +# define PPR_RER_RXOK (1 << 8) /* Frame received with no errors */ +# define PPR_RER_HASHED (1 << 9) /* Frame address hashed OK */ +# define PPR_RER_IA (1 << 10) /* Frame address matched IA */ +# define PPR_RER_BROADCAST (1 << 11) /* Broadcast frame */ +# define PPR_RER_CRC (1 << 12) /* Frame had CRC error */ +# define PPR_RER_RUNT (1 << 13) /* Runt frame */ +# define PPR_RER_EXTRA (1 << 14) /* Frame was too long */ + +#define PPR_TER 0x0128 /* Transmit event */ +# define PPR_TER_CRS (1 << 6) /* Carrier lost */ +# define PPR_TER_SQE (1 << 7) /* Signal Quality Error */ +# define PPR_TER_TXOK (1 << 8) /* Packet sent without error */ +# define PPR_TER_LATE (1 << 9) /* Out of window */ +# define PPR_TER_JABBER (1 << 10) /* Stuck transmit? */ +# define PPR_TER_NUMCOLLISIONS_SHIFT 11 +# define PPR_TER_NUMCOLLISIONS_MASK (15 << PPR_TER_NUMCOLLISIONS_SHIFT) +# define PPR_TER_16COLLISIONS (1 << 15) /* > 16 collisions */ + +#define PPR_BER 0x012C /* Buffer event */ +# define PPR_BER_SWINT (1 << 6) /* Software interrupt */ +# define PPR_BER_RXDMAFRAME (1 << 7) /* Received framed DMAed */ +# define PPR_BER_RDY4TX (1 << 8) /* Ready for transmission */ +# define PPR_BER_TXUNDERRUN (1 << 9) /* Transmit underrun */ +# define PPR_BER_RXMISS (1 << 10) /* Received frame missed */ +# define PPR_BER_RX128 (1 << 11) /* 128 bytes received */ +# define PPR_BER_RXDEST (1 << 15) /* Received framed passed address filter */ + +#define PPR_RXMISS 0x0130 /* Receiver miss counter */ +#define PPR_TXCOL 0x0132 /* Transmit collision counter */ +#define PPR_LINESTAT 0x0134 /* Line status */ +# define PPR_LINESTAT_LINKOK (1 << 7) /* Line is connected and working */ +# define PPR_LINESTAT_AUI (1 << 8) /* Connected via AUI */ +# define PPR_LINESTAT_10BT (1 << 9) /* Connected via twisted pair */ +# define PPR_LINESTAT_POLARITY (1 << 12) /* Line polarity OK (10BT only) */ +# define PPR_LINESTAT_CRS (1 << 14) /* Frame being received */ + +#define PPR_SELFSTAT 0x0136 /* Chip self status */ +# define PPR_SELFSTAT_33VACTIVE (1 << 6) /* supply voltage is 3.3V */ +# define PPR_SELFSTAT_INITD (1 << 7) /* Chip initialization complete */ +# define PPR_SELFSTAT_SIBSY (1 << 8) /* EEPROM is busy */ +# define PPR_SELFSTAT_EEPROM (1 << 9) /* EEPROM present */ +# define PPR_SELFSTAT_EEPROMOK (1 << 10) /* EEPROM checks out */ +# define PPR_SELFSTAT_ELPRESENT (1 << 11) /* External address latch logic available */ +# define PPR_SELFSTAT_EESIZE (1 << 12) /* Size of EEPROM */ + +#define PPR_BUSSTAT 0x0138 /* Bus status */ +# define PPR_BUSSTAT_TXBID (1 << 7) /* Tx error */ +# define PPR_BUSSTAT_TXRDY (1 << 8) /* Ready for Tx data */ + +#define PPR_TDR 0x013C /* AUI Time Domain Reflectometer */ + +/* 0x0144 - Initiate transmit registers */ + +#define PPR_TXCOMMAND 0x0144 /* Tx Command */ +#define PPR_TXLENGTH 0x0146 /* Tx Length */ + +/* 0x0150 - Address filter registers */ + +#define PPR_LAF 0x0150 /* Logical address filter (6 bytes) */ +#define PPR_IA 0x0158 /* Individual address (MAC) */ + +/* 0x0400 - Frame location registers */ + +#define PPR_RXSTATUS 0x0400 /* Rx Status */ +#define PPR_RXLENGTH 0x0402 /* Rx Length */ +#define PPR_RXFRAMELOCATION 0x0404 /* Rx Frame Location */ +#define PPR_TXFRAMELOCATION 0x0a00 /* Tx Frame Location */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __DRIVERS_NET_CS89x0_H */ diff --git a/drivers/net/dm90x0.c b/drivers/net/dm90x0.c index 15433e0f80777d94e05094faedf8ccc2e4815872..2f5b26abb66177f74d3b530bb298f7246b69ad98 100644 --- a/drivers/net/dm90x0.c +++ b/drivers/net/dm90x0.c @@ -2,7 +2,7 @@ * drivers/net/dm9x.c * * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: Davicom data sheets (DM9000-DS-F03-041906.pdf, * DM9010-DS-F01-103006.pdf) and looking at lots of other DM90x0 diff --git a/drivers/net/enc28j60.h b/drivers/net/enc28j60.h index 6ca1a524d104e484351e202e723994c8f3f5bd98..3c787c53390ee928c9fa390a8e245946aed93163 100644 --- a/drivers/net/enc28j60.h +++ b/drivers/net/enc28j60.h @@ -2,7 +2,7 @@ * drivers/net/enc28j60.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: * - ENC28J60 Data Sheet, Stand-Alone Ethernet Controller with SPI Interface, diff --git a/drivers/power/pm_activity.c b/drivers/power/pm_activity.c index f52fc93ff31cc2ddd62202748eb9018eb33c6e7d..d3c8a52e777a59513ded5e7aebd9c2d32caf6f4d 100644 --- a/drivers/power/pm_activity.c +++ b/drivers/power/pm_activity.c @@ -2,7 +2,7 @@ * drivers/power/pm_activity.c * * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/sensors/Make.defs b/drivers/sensors/Make.defs index d04e7541e1ee9ad61f50523e93f947d11d58551a..866ccb05362aef575d49b3702702eae6665e90e8 100644 --- a/drivers/sensors/Make.defs +++ b/drivers/sensors/Make.defs @@ -2,7 +2,7 @@ # drivers/sensors/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/drivers/sensors/lm75.c b/drivers/sensors/lm75.c index 8e1a0fb4b6b242ebdefda0620822bdf6b19dd8e3..2d3346447b15746e624a5c56bf40a84528342903 100644 --- a/drivers/sensors/lm75.c +++ b/drivers/sensors/lm75.c @@ -3,7 +3,7 @@ * Character driver for the STMicro LM-75 Temperature Sensor * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/sercomm/Make.defs b/drivers/sercomm/Make.defs index 3585f53146e4ff4d5470637b20351261d1ff6e89..0cf93d4c805ba915b653c45af95a2d63844a5931 100644 --- a/drivers/sercomm/Make.defs +++ b/drivers/sercomm/Make.defs @@ -2,7 +2,7 @@ # drivers/serial/Make.defs # # Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/drivers/usbhost/Make.defs b/drivers/usbhost/Make.defs index cc28e874d494b6b4d8e98a7b1cd950974196c50d..fd54ab53e7a0b629c85fee917428d8ad2174edae 100644 --- a/drivers/usbhost/Make.defs +++ b/drivers/usbhost/Make.defs @@ -2,7 +2,7 @@ # drivers/usbhost/Make.defs # # Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/drivers/usbhost/usbhost_findclass.c b/drivers/usbhost/usbhost_findclass.c index f08aff580e89ba50cd90d0a52333b220fb38badc..3e38670cf88f03f564f86e9ddf0488b8aa8d0b2b 100644 --- a/drivers/usbhost/usbhost_findclass.c +++ b/drivers/usbhost/usbhost_findclass.c @@ -2,7 +2,7 @@ * drivers/usbhost/usbhost_findclass.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/usbhost/usbhost_hidkbd.c b/drivers/usbhost/usbhost_hidkbd.c index bb3ecad9e4af10ebee4a60392f78188a37589859..e69d68e7b26fcd717de8d83cc20e0cfc573526be 100644 --- a/drivers/usbhost/usbhost_hidkbd.c +++ b/drivers/usbhost/usbhost_hidkbd.c @@ -2,7 +2,7 @@ * drivers/usbhost/usbhost_hidkbd.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/usbhost/usbhost_registerclass.c b/drivers/usbhost/usbhost_registerclass.c index 76ef511af80fde5a2f1801118ec50c4061ecc3c3..f4d1b64afb985cf80ae97210170b432327b7a6d2 100644 --- a/drivers/usbhost/usbhost_registerclass.c +++ b/drivers/usbhost/usbhost_registerclass.c @@ -2,7 +2,7 @@ * drivers/usbhost/usbhost_registerclass.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/usbhost/usbhost_registry.c b/drivers/usbhost/usbhost_registry.c index 56c03e2dc5513bee21cd0cc5fd016097d7f7e1b6..fb2e900e26dd3ad86a6e13396ef19d9c51956d13 100644 --- a/drivers/usbhost/usbhost_registry.c +++ b/drivers/usbhost/usbhost_registry.c @@ -2,7 +2,7 @@ * drivers/usbhost/usbhost_registry.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/usbhost/usbhost_registry.h b/drivers/usbhost/usbhost_registry.h index 63436af5d6a591d2e3d7ad56a34c1f9ec2e31164..759a1c66e7d24ac1978b7ca940fe56facaec547f 100644 --- a/drivers/usbhost/usbhost_registry.h +++ b/drivers/usbhost/usbhost_registry.h @@ -2,7 +2,7 @@ * drivers/usbhost/usbdev_registry.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/drivers/wireless/Make.defs b/drivers/wireless/Make.defs index ac73c8d85efc6f4f6447d981f039fc2ae275531f..f47f7666a545c1ad118b4ed5fb64551d56345a4f 100644 --- a/drivers/wireless/Make.defs +++ b/drivers/wireless/Make.defs @@ -2,7 +2,7 @@ # drivers/wireless/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/fs/fat/Make.defs b/fs/fat/Make.defs index 96be43961450e596b8e223ce507964be4a4419cb..136302b86f0f1fe2f5d4fcde209c2f5412af446d 100644 --- a/fs/fat/Make.defs +++ b/fs/fat/Make.defs @@ -2,7 +2,7 @@ # Make.defs # # Copyright (C) 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/fs/fat/fs_configfat.c b/fs/fat/fs_configfat.c index 3a55a5215c413f307e238e88bf8726c4f81a4fd3..2075caa9fa6092d4ee9782494ce397ecc81d4210 100644 --- a/fs/fat/fs_configfat.c +++ b/fs/fat/fs_configfat.c @@ -2,7 +2,7 @@ * fs/fat/fs_configfat.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/fs/fat/fs_fat32dirent.c b/fs/fat/fs_fat32dirent.c index 742fa1eeb3c339c623eb75ff6ebeb53df5bea3e8..18cf6784796c50dd549110d7e04bfb877c7d817b 100644 --- a/fs/fat/fs_fat32dirent.c +++ b/fs/fat/fs_fat32dirent.c @@ -2,7 +2,7 @@ * fs/fat/fs_fat32dirent.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/fs/fat/fs_mkfatfs.c b/fs/fat/fs_mkfatfs.c index 7a8b2ab92161a2d85128bac89eb9395d33692913..384aa93567374a2ff7f63d1631b9d781ede440e7 100644 --- a/fs/fat/fs_mkfatfs.c +++ b/fs/fat/fs_mkfatfs.c @@ -2,7 +2,7 @@ * fs/fat/fs_writefat.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/fs/fat/fs_mkfatfs.h b/fs/fat/fs_mkfatfs.h index 214697c5192021c763763c504089eb9ad110023b..05801c92d7c71168b926792bb0c2a8c95264d12e 100644 --- a/fs/fat/fs_mkfatfs.h +++ b/fs/fat/fs_mkfatfs.h @@ -2,7 +2,7 @@ * fs/fat/fs_mkfat.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/fs/fat/fs_writefat.c b/fs/fat/fs_writefat.c index 02d55d62589295d461b57bb85ff2597ee2c9b4d2..564be5b50c3512a1c6872d2a0fcd3930f4c1b62c 100644 --- a/fs/fat/fs_writefat.c +++ b/fs/fat/fs_writefat.c @@ -2,7 +2,7 @@ * fs/fat/fs_writefat.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/fs/mmap/Make.defs b/fs/mmap/Make.defs index 2d3d006949352fb9d7c4f173871fed90e8a3ac07..59857fe9c4afc0963df34b07ea12e1177a286e78 100644 --- a/fs/mmap/Make.defs +++ b/fs/mmap/Make.defs @@ -2,7 +2,7 @@ # fs/mmap/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/fs/mmap/fs_mmap.c b/fs/mmap/fs_mmap.c index 5764b16f1ddde9a2a39bafd3cd71632f25ca63e4..85d796586acc81306135c3c235c2f5d62ea555d5 100644 --- a/fs/mmap/fs_mmap.c +++ b/fs/mmap/fs_mmap.c @@ -2,7 +2,7 @@ * fs/mmap/fs_mmap.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/fs/mmap/fs_munmap.c b/fs/mmap/fs_munmap.c index a4b9dc6091d551a6af403e7a796aa2fbbf05b507..5d9416d454304e0040f575ecfad00bb8881162bc 100644 --- a/fs/mmap/fs_munmap.c +++ b/fs/mmap/fs_munmap.c @@ -2,7 +2,7 @@ * fs/mmap/fs_munmap.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/fs/mmap/fs_rammap.c b/fs/mmap/fs_rammap.c index d2bda4fb5b3fe065a57b04fe148db7ed4ab99187..f43541cc9b31dd4a8135c12002e71f8d33884d45 100644 --- a/fs/mmap/fs_rammap.c +++ b/fs/mmap/fs_rammap.c @@ -2,7 +2,7 @@ * fs/mmap/fs_rammmap.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/fs/mmap/fs_rammap.h b/fs/mmap/fs_rammap.h index 9076d73432958503171624516236f3b8634571cf..293a91ffb18ee87bc5780d821b01d21adffa8c3d 100644 --- a/fs/mmap/fs_rammap.h +++ b/fs/mmap/fs_rammap.h @@ -2,7 +2,7 @@ * fs/mmap/rammap.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt * diff --git a/fs/nfs/nfs_util.c b/fs/nfs/nfs_util.c index 33c5f0a8998060e9265aaaf4187bdc8a9cdc7eee..73fda72a7dad66e65913786e5c727cb18f9916f1 100644 --- a/fs/nfs/nfs_util.c +++ b/fs/nfs/nfs_util.c @@ -2,7 +2,7 @@ * fs/nfs/nfs_util.c * * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/fs/nxffs/Make.defs b/fs/nxffs/Make.defs index a73950c3f689f50068e3ed6a027c0973eaf38c9f..b67ae4472d29bf7d6fbc1428fee3e9e04a4c521c 100644 --- a/fs/nxffs/Make.defs +++ b/fs/nxffs/Make.defs @@ -2,7 +2,7 @@ # fs/nxffs/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/fs/nxffs/nxffs_block.c b/fs/nxffs/nxffs_block.c index a069048b894bff55913ea1db22bc75520e45de1c..6701b6e6be1ae43e37471594e86051856ce30f97 100644 --- a/fs/nxffs/nxffs_block.c +++ b/fs/nxffs/nxffs_block.c @@ -2,7 +2,7 @@ * fs/nxffs/nxffs_block.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt * diff --git a/fs/nxffs/nxffs_blockstats.c b/fs/nxffs/nxffs_blockstats.c index 590aa2ad035c63b5946fb935ac1c51d1ba21db84..348374e670bd13142dce31a7da8b7e07bee75d1c 100644 --- a/fs/nxffs/nxffs_blockstats.c +++ b/fs/nxffs/nxffs_blockstats.c @@ -2,7 +2,7 @@ * fs/nxffs/nxffs_blockstats.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt * diff --git a/fs/nxffs/nxffs_cache.c b/fs/nxffs/nxffs_cache.c index 5c5cbaa18759829dd54dfd882845252da917809b..0cc97980eae58bc46fdf473ced6fe4861a4c8464 100644 --- a/fs/nxffs/nxffs_cache.c +++ b/fs/nxffs/nxffs_cache.c @@ -2,7 +2,7 @@ * fs/nxffs/nxffs_cache.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt * diff --git a/fs/nxffs/nxffs_dirent.c b/fs/nxffs/nxffs_dirent.c index 562a5320b92c09707e87cb6972f3d0306c496fc4..221549438f2f542cc7112d85a71b183a0bedc5d3 100644 --- a/fs/nxffs/nxffs_dirent.c +++ b/fs/nxffs/nxffs_dirent.c @@ -2,7 +2,7 @@ * fs/nxffs/nxffs_dirent.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt * diff --git a/fs/nxffs/nxffs_dump.c b/fs/nxffs/nxffs_dump.c index d816ba6ca9ba6a7fd480ae94474442a25bf46617..6a89aaf1daeeea1ad36f86fbd4821bae31a3ad30 100644 --- a/fs/nxffs/nxffs_dump.c +++ b/fs/nxffs/nxffs_dump.c @@ -2,7 +2,7 @@ * fs/nxffs/nxffs_dump.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt * diff --git a/fs/nxffs/nxffs_ioctl.c b/fs/nxffs/nxffs_ioctl.c index 41fabfbeef875c6d371db26305b1f8d81d322fe3..332878eb0c76b16428742aac208ec51fe915a46f 100644 --- a/fs/nxffs/nxffs_ioctl.c +++ b/fs/nxffs/nxffs_ioctl.c @@ -2,7 +2,7 @@ * fs/nxffs/nxffs_ioctl.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt * diff --git a/fs/nxffs/nxffs_open.c b/fs/nxffs/nxffs_open.c index 339e25edc73e4461e93b3bb848b00619a0daaa7a..eb7817c57e740b361cc6993f37ba599186568b87 100644 --- a/fs/nxffs/nxffs_open.c +++ b/fs/nxffs/nxffs_open.c @@ -2,7 +2,7 @@ * fs/nxffs/nxffs_open.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt * diff --git a/fs/nxffs/nxffs_read.c b/fs/nxffs/nxffs_read.c index 6ba49ca72f2250565a8704d035f91051f7881010..b638dbfd4f398daa9f711ea927243704156b4d11 100644 --- a/fs/nxffs/nxffs_read.c +++ b/fs/nxffs/nxffs_read.c @@ -2,7 +2,7 @@ * fs/nxffs/nxffs_read.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt * diff --git a/fs/nxffs/nxffs_reformat.c b/fs/nxffs/nxffs_reformat.c index cb10862ff0104d56ee92573ce0b1bd22343cc6af..d3c00893d1878c0b66d21026f05753f7a13f19bb 100644 --- a/fs/nxffs/nxffs_reformat.c +++ b/fs/nxffs/nxffs_reformat.c @@ -2,7 +2,7 @@ * fs/nxffs/nxffs_reformat.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt * diff --git a/fs/nxffs/nxffs_stat.c b/fs/nxffs/nxffs_stat.c index afb18093ca8259f06ebe01c9e3a18ad5fe3cf781..d4d58a72c96e5151f2bb296b9a22db990ec9ba1c 100644 --- a/fs/nxffs/nxffs_stat.c +++ b/fs/nxffs/nxffs_stat.c @@ -2,7 +2,7 @@ * fs/nxffs/nxffs_stat.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt * diff --git a/fs/nxffs/nxffs_unlink.c b/fs/nxffs/nxffs_unlink.c index 9d0d5b49e39c97eab9e8a4acc06f37a6f9849e29..73b0f360a3b86279263a31d6dd3252486c851898 100644 --- a/fs/nxffs/nxffs_unlink.c +++ b/fs/nxffs/nxffs_unlink.c @@ -2,7 +2,7 @@ * fs/nxffs/nxffs_unlink.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt * diff --git a/fs/nxffs/nxffs_util.c b/fs/nxffs/nxffs_util.c index ea2e97967e7736fa0a1b735950abd73e2e349994..f424e71e070aae9eb01509bd1c134f8611d28822 100644 --- a/fs/nxffs/nxffs_util.c +++ b/fs/nxffs/nxffs_util.c @@ -2,7 +2,7 @@ * fs/nxffs/nxffs_util.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt * diff --git a/fs/romfs/Make.defs b/fs/romfs/Make.defs index 56b4c9862ad033d5329293c90f0e5e159879939d..77de93c05487e38bea4f18d752d53f1528eb931c 100644 --- a/fs/romfs/Make.defs +++ b/fs/romfs/Make.defs @@ -2,7 +2,7 @@ # fs/romfs/Make.defs # # Copyright (C) 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/fs/romfs/fs_romfs.c b/fs/romfs/fs_romfs.c index 8a2e696654734e5dd2d01c5615b56c11f7c4a4c5..b95619d759e541fd2c132bd8c5abebb9d6dc61e9 100644 --- a/fs/romfs/fs_romfs.c +++ b/fs/romfs/fs_romfs.c @@ -2,7 +2,7 @@ * rm/romfs/fs_romfs.h * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt * diff --git a/fs/romfs/fs_romfs.h b/fs/romfs/fs_romfs.h index f89196ff7ae670584fc1641b9679e0fc320e7565..4081517fb86737bb91a21460c447c02d87238f96 100644 --- a/fs/romfs/fs_romfs.h +++ b/fs/romfs/fs_romfs.h @@ -2,7 +2,7 @@ * fs/romfs/fs_romfs.h * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt * diff --git a/fs/romfs/fs_romfsutil.c b/fs/romfs/fs_romfsutil.c index cb3f9f9ace441e45a70f8a924a2824e0bb288c49..6ea114b5e1a418c04811fe1fdb3b4db04ca91133 100644 --- a/fs/romfs/fs_romfsutil.c +++ b/fs/romfs/fs_romfsutil.c @@ -2,7 +2,7 @@ * rm/romfs/fs_romfsutil.h * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * References: Linux/Documentation/filesystems/romfs.txt * diff --git a/graphics/nxbe/nxbe_clipper.c b/graphics/nxbe/nxbe_clipper.c index 580c8bc4c8c42d0f2f260ed62f922878387a22e2..cdbd421c059e8086b1c8084150d8a728dea15b45 100644 --- a/graphics/nxbe/nxbe_clipper.c +++ b/graphics/nxbe/nxbe_clipper.c @@ -2,7 +2,7 @@ * graphics/nxbe/nxbe_clipper.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxbe/nxbe_closewindow.c b/graphics/nxbe/nxbe_closewindow.c index 3c583fcfbf47eb8f640000811b5e1e1e6f729150..e632ebf011c712201f02a93a2c3f0966c262eccb 100644 --- a/graphics/nxbe/nxbe_closewindow.c +++ b/graphics/nxbe/nxbe_closewindow.c @@ -2,7 +2,7 @@ * graphics/nxbe/nxbe_closewindow.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxbe/nxbe_colormap.c b/graphics/nxbe/nxbe_colormap.c index 14431751904acc54ca2cc4fdcf9aeb5e677481b9..e33877382080e1640846bd1b4814eae192bca082 100644 --- a/graphics/nxbe/nxbe_colormap.c +++ b/graphics/nxbe/nxbe_colormap.c @@ -2,7 +2,7 @@ * graphics/nxbe/nxbe_colormap.c * * Copyright (C) 2008-2009,2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxbe/nxbe_fill.c b/graphics/nxbe/nxbe_fill.c index f4aec74773a537c9c9c82fd9410e09e40b128153..c2b4266b047509376683c00b3ad3b962bba94c4f 100644 --- a/graphics/nxbe/nxbe_fill.c +++ b/graphics/nxbe/nxbe_fill.c @@ -2,7 +2,7 @@ * graphics/nxbe/nxbe_fill.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxbe/nxbe_redraw.c b/graphics/nxbe/nxbe_redraw.c index 3226ccf32874b7d964cc254b4cc777cff19274f0..d52ff71e5862a1df1187ed6ebc2cf0e0dcf144af 100644 --- a/graphics/nxbe/nxbe_redraw.c +++ b/graphics/nxbe/nxbe_redraw.c @@ -2,7 +2,7 @@ * graphics/nxbe/nxbe_redraw.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxbe/nxbe_setposition.c b/graphics/nxbe/nxbe_setposition.c index f407eea3fa3429dded9db6fadee5288f26518ad2..6f680df04019c7a68a673b95ceb0fe9bea6fa3bc 100644 --- a/graphics/nxbe/nxbe_setposition.c +++ b/graphics/nxbe/nxbe_setposition.c @@ -2,7 +2,7 @@ * graphics/nxbe/nxbe_setposition.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxbe/nxbe_setsize.c b/graphics/nxbe/nxbe_setsize.c index 367f5d7dc9760ebe6cb552eb529128b1256538e9..99775c715ba8a28715e78db862db6125e67ffcb7 100644 --- a/graphics/nxbe/nxbe_setsize.c +++ b/graphics/nxbe/nxbe_setsize.c @@ -2,7 +2,7 @@ * graphics/nxbe/nxbe_setsize.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxbe/nxbe_visible.c b/graphics/nxbe/nxbe_visible.c index 6b8b9291bbdee64b85cf15a78cd9185643e105ae..ca62aeab6cc8fdb3ddd187b46caa56e0ec17e399 100644 --- a/graphics/nxbe/nxbe_visible.c +++ b/graphics/nxbe/nxbe_visible.c @@ -2,7 +2,7 @@ * graphics/nxbe/nxbe_redraw.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxfonts/Make.defs b/graphics/nxfonts/Make.defs index 95665ad362d240cf7235410935b6b00a4fab9870..bc65d7ad7a5617e1cc6d0644827e8108e6c5adcb 100644 --- a/graphics/nxfonts/Make.defs +++ b/graphics/nxfonts/Make.defs @@ -2,7 +2,7 @@ # graphics/nxfonts/Make.defs # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/graphics/nxfonts/Makefile.sources b/graphics/nxfonts/Makefile.sources index 2867425798dacc370e60d46ddf937a02a9ac3d80..f2aa87cafd3caae5db982a09ad3a7e64483ebc70 100644 --- a/graphics/nxfonts/Makefile.sources +++ b/graphics/nxfonts/Makefile.sources @@ -2,7 +2,7 @@ # graphics/nxfonts/Makefile.sources # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/graphics/nxfonts/nxfonts_bitmaps.c b/graphics/nxfonts/nxfonts_bitmaps.c index 9b255b97a6a9442844c5b667e40a12625cbaded7..2efc34b87ffc6d58c1d82e3bd046ba935b079115 100644 --- a/graphics/nxfonts/nxfonts_bitmaps.c +++ b/graphics/nxfonts/nxfonts_bitmaps.c @@ -2,7 +2,7 @@ * graphics/nxfonts/nxfonts_bitmaps.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxfonts/nxfonts_convert.c b/graphics/nxfonts/nxfonts_convert.c index 00cd61a6cd0d8105a2a1823c81b45e34e9c2e23b..a3c31996449c97c2a1ea59fb0a83e5223d72a334 100644 --- a/graphics/nxfonts/nxfonts_convert.c +++ b/graphics/nxfonts/nxfonts_convert.c @@ -2,7 +2,7 @@ * graphics/nxfonts/nxfonts_convert.c * * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxfonts/nxfonts_getfont.c b/graphics/nxfonts/nxfonts_getfont.c index e17d3be3108bada23841e2ecce421b41f7632454..23e5c44744a9bd08fd5994c1809d10ed95d342c8 100644 --- a/graphics/nxfonts/nxfonts_getfont.c +++ b/graphics/nxfonts/nxfonts_getfont.c @@ -2,7 +2,7 @@ * graphics/nxfonts/nxfonts_getfont.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxfonts/nxfonts_internal.h b/graphics/nxfonts/nxfonts_internal.h index fa7864170df4a20f0ddd37787a115fcda599087c..057200cd56b72d1153b7dae8b219d03725e3d732 100644 --- a/graphics/nxfonts/nxfonts_internal.h +++ b/graphics/nxfonts/nxfonts_internal.h @@ -2,7 +2,7 @@ * graphics/nxfonts/nxfonts_internal.h * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/fb/nxglib_copyrectangle.c b/graphics/nxglib/fb/nxglib_copyrectangle.c index 4ad792a4cbb6aa695ea1cce624d6cf85b92fa836..bf9812ac370a2663c08140bfec69d70e3d21368a 100644 --- a/graphics/nxglib/fb/nxglib_copyrectangle.c +++ b/graphics/nxglib/fb/nxglib_copyrectangle.c @@ -2,7 +2,7 @@ * graphics/nxglib/fb/nxsglib_copyrectangle.c * * Copyright (C) 2008-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/fb/nxglib_fillrectangle.c b/graphics/nxglib/fb/nxglib_fillrectangle.c index cb9483c989602a2b5bfa4c8355ecc58d8db76eee..777a906a4fb100e4287af7e3c1eba42fa8fadba4 100644 --- a/graphics/nxglib/fb/nxglib_fillrectangle.c +++ b/graphics/nxglib/fb/nxglib_fillrectangle.c @@ -2,7 +2,7 @@ * graphics/nxglib/fb/nxglib_fillrectangle.c * * Copyright (C) 2008-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/lcd/nxglib_copyrectangle.c b/graphics/nxglib/lcd/nxglib_copyrectangle.c index 988b6cb944296a0f641f69417cc15a9e4402b7b2..40989acef23d4073378ccb6568908778139f39bb 100644 --- a/graphics/nxglib/lcd/nxglib_copyrectangle.c +++ b/graphics/nxglib/lcd/nxglib_copyrectangle.c @@ -2,7 +2,7 @@ * graphics/nxglib/lcd/nxsglib_copyrectangle.c * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/lcd/nxglib_fillrectangle.c b/graphics/nxglib/lcd/nxglib_fillrectangle.c index c1a30d66ffa065fa607d6f53a5b7e6cc0660024e..b9554e1cc3a68d429577ff6860c60a802f9a1773 100644 --- a/graphics/nxglib/lcd/nxglib_fillrectangle.c +++ b/graphics/nxglib/lcd/nxglib_fillrectangle.c @@ -2,7 +2,7 @@ * graphics/nxglib/lcd/nxglib_fillrectangle.c * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/lcd/nxglib_moverectangle.c b/graphics/nxglib/lcd/nxglib_moverectangle.c index f82187ae3b5b00f5e1d5567efd1142e72ca292bd..b46a17e61a8b175f6288f02468010a720d066690 100644 --- a/graphics/nxglib/lcd/nxglib_moverectangle.c +++ b/graphics/nxglib/lcd/nxglib_moverectangle.c @@ -2,7 +2,7 @@ * graphics/nxglib/lcd/nxglib_moverectangle.c * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_bitblit.h b/graphics/nxglib/nxglib_bitblit.h index a737a064740ada4b6fa60b41320fcadad37bb519..0182337d1b6328e77bbb2600ef1772e8af462823 100644 --- a/graphics/nxglib/nxglib_bitblit.h +++ b/graphics/nxglib/nxglib_bitblit.h @@ -2,7 +2,7 @@ * graphics/nxglib/nxglib_bitblit.h * * Copyright (C) 2008-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_circlepts.c b/graphics/nxglib/nxglib_circlepts.c index a6d59280d76896a233966c8242baf93ccace2809..811953dfc671f9a6cbf427062678c20110737ac9 100644 --- a/graphics/nxglib/nxglib_circlepts.c +++ b/graphics/nxglib/nxglib_circlepts.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxglib_circlepts.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_circletraps.c b/graphics/nxglib/nxglib_circletraps.c index 7c2cd1d7b532952403e7365204cfceaedbc927d4..8ee287795f837b2dbe056dad58a15e2da65045bc 100644 --- a/graphics/nxglib/nxglib_circletraps.c +++ b/graphics/nxglib/nxglib_circletraps.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxglib_circletraps.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_colorcopy.c b/graphics/nxglib/nxglib_colorcopy.c index f99b9950505659edd673a3dae11df62d1eb8639d..42c0d0d4510c5fcaf0dff03afb1a30f285e41fca 100644 --- a/graphics/nxglib/nxglib_colorcopy.c +++ b/graphics/nxglib/nxglib_colorcopy.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_colorcopy.c * * Copyright (C) 2008-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_copyrun.h b/graphics/nxglib/nxglib_copyrun.h index b97372bf77c4f281e2c8515e1099e3bdc88d204e..a52af22463c591f71ef249946bf48b3a8eaa4ff4 100644 --- a/graphics/nxglib/nxglib_copyrun.h +++ b/graphics/nxglib/nxglib_copyrun.h @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_copyrun.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_fillrun.h b/graphics/nxglib/nxglib_fillrun.h index b1d8a3a7fbe3403c8384189d85e275f46c7e2a8c..1dcf85dd977a51577659d55cf15f1266dedd2e27 100644 --- a/graphics/nxglib/nxglib_fillrun.h +++ b/graphics/nxglib/nxglib_fillrun.h @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_fullrun.h * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_intersecting.c b/graphics/nxglib/nxglib_intersecting.c index c495a9e3d97e697653fb799a905c6f87050d8022..e1370c1404565312d8ca011886b99ae8d9b9876c 100644 --- a/graphics/nxglib/nxglib_intersecting.c +++ b/graphics/nxglib/nxglib_intersecting.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_intersecting.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_nonintersecting.c b/graphics/nxglib/nxglib_nonintersecting.c index 9cb2ec29c5170b24101c4b49a4e8f4b6a2858530..d78da994e894602b37d40a8b310edf8e7a15ef49 100644 --- a/graphics/nxglib/nxglib_nonintersecting.c +++ b/graphics/nxglib/nxglib_nonintersecting.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_rectnonintersecting.c * * Copyright (C) 2008-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_rectadd.c b/graphics/nxglib/nxglib_rectadd.c index b53e6b04c6b31c2915f3069102988826883db363..f4eda341d57cb7b989f4469910d7c834353135ad 100644 --- a/graphics/nxglib/nxglib_rectadd.c +++ b/graphics/nxglib/nxglib_rectadd.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_rectadd.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_rectcopy.c b/graphics/nxglib/nxglib_rectcopy.c index 998f5b716f69629f1e17659b4f24663ab1aa8617..67e5f6d69106cc90d5771b10a16f83887f83cfcd 100644 --- a/graphics/nxglib/nxglib_rectcopy.c +++ b/graphics/nxglib/nxglib_rectcopy.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_rectcopy.c * * Copyright (C) 2008-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_rectinside.c b/graphics/nxglib/nxglib_rectinside.c index 1c1f17a2e376a77bab1541d3e8be597bdf7446ee..6ca29ddb6e5bbe16f21a881250b9b5fea76b79de 100644 --- a/graphics/nxglib/nxglib_rectinside.c +++ b/graphics/nxglib/nxglib_rectinside.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_rectinside.c * * Copyright (C) 2008-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_rectintersect.c b/graphics/nxglib/nxglib_rectintersect.c index 961635710405731ce011e6934292ef59a61a4c78..6af24ee26839eb7d7e0db5b1a054e90d2e18e537 100644 --- a/graphics/nxglib/nxglib_rectintersect.c +++ b/graphics/nxglib/nxglib_rectintersect.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_rectintersect.c * * Copyright (C) 2008-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_rectoffset.c b/graphics/nxglib/nxglib_rectoffset.c index 93481b0de57d0ee4d598ed69930c8700068eeb7b..2392d64486581ec9385bdabe3c08f2f864fc5d8d 100644 --- a/graphics/nxglib/nxglib_rectoffset.c +++ b/graphics/nxglib/nxglib_rectoffset.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_rectoffset.c * * Copyright (C) 2008-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_rectoverlap.c b/graphics/nxglib/nxglib_rectoverlap.c index 75d7a464117760874dd21c469273e62df2eb09c1..779951881be2adee280b866fffc2264bc64f302d 100644 --- a/graphics/nxglib/nxglib_rectoverlap.c +++ b/graphics/nxglib/nxglib_rectoverlap.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_nulloverlap.c * * Copyright (C) 2008-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_rectsize.c b/graphics/nxglib/nxglib_rectsize.c index 17a6c9214acea16aabb2931993f96315653616ef..37d86359687ee0f2a085dedb03694ccfcb8de406 100644 --- a/graphics/nxglib/nxglib_rectsize.c +++ b/graphics/nxglib/nxglib_rectsize.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxglib_rectsize.c * * Copyright (C) 2008-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_rectunion.c b/graphics/nxglib/nxglib_rectunion.c index 8500c919cf132e167b08ff58a958810c347a59f1..36c0968fa302cde81173dd28f1fb5dff3cd73c7d 100644 --- a/graphics/nxglib/nxglib_rectunion.c +++ b/graphics/nxglib/nxglib_rectunion.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_rectunion.c * * Copyright (C) 2008-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_rgb2yuv.c b/graphics/nxglib/nxglib_rgb2yuv.c index c439c4fe00c7e105b997b0bd7a95190841cde12d..31eff23fa79978c4fc9d0c8d00689928671072c7 100644 --- a/graphics/nxglib/nxglib_rgb2yuv.c +++ b/graphics/nxglib/nxglib_rgb2yuv.c @@ -2,7 +2,7 @@ * graphics/color/nxglib_rgb2yuv.c * * Copyright (C) 2008, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_runcopy.c b/graphics/nxglib/nxglib_runcopy.c index 4b5372f149eb15e4d8aec8c0e1b19e8a5bd5882e..b6170638c285fe9b536040038c9fee773c3374ec 100644 --- a/graphics/nxglib/nxglib_runcopy.c +++ b/graphics/nxglib/nxglib_runcopy.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_runcopy.c * * Copyright (C) 2008-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_runoffset.c b/graphics/nxglib/nxglib_runoffset.c index f66d73674169d0698d37bc03133f0ae991e1d8ed..0c569ce2f2de9f60624b035c10b3344e745797c0 100644 --- a/graphics/nxglib/nxglib_runoffset.c +++ b/graphics/nxglib/nxglib_runoffset.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_runoffset.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_splitline.c b/graphics/nxglib/nxglib_splitline.c index eff516db3897732ae320c53e5e1ad604d7ef813a..84892b67e3028f6bf9d42601ca37c23ae2189c39 100644 --- a/graphics/nxglib/nxglib_splitline.c +++ b/graphics/nxglib/nxglib_splitline.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxglib_splitline.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_trapcopy.c b/graphics/nxglib/nxglib_trapcopy.c index 63bc0ecd81a747a9ad609df3e377f86d7ce43576..f35da18e1efb3caef9900f159466d3ca2b7d05eb 100644 --- a/graphics/nxglib/nxglib_trapcopy.c +++ b/graphics/nxglib/nxglib_trapcopy.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_trapcopy.c * * Copyright (C) 2008-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_trapoffset.c b/graphics/nxglib/nxglib_trapoffset.c index 872a3107287fe87ab016ca35799991b8a3c8353f..a90631f0658493bb1a990f657a6d4aa7fcaf8dd3 100644 --- a/graphics/nxglib/nxglib_trapoffset.c +++ b/graphics/nxglib/nxglib_trapoffset.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_trapoffset.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_vectoradd.c b/graphics/nxglib/nxglib_vectoradd.c index b206effa6039df0405233fb832376b109c8c31e8..7da5eb13715b0f94df15cff62c047b75f223a4f0 100644 --- a/graphics/nxglib/nxglib_vectoradd.c +++ b/graphics/nxglib/nxglib_vectoradd.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_vectoradd.c * * Copyright (C) 2008-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_vectsubtract.c b/graphics/nxglib/nxglib_vectsubtract.c index 81ffc86fb0998965b8b55789744d0da92f254d13..c830a1a33b415a74ba54638d9a445c3684184617 100644 --- a/graphics/nxglib/nxglib_vectsubtract.c +++ b/graphics/nxglib/nxglib_vectsubtract.c @@ -2,7 +2,7 @@ * graphics/nxglib/nxsglib_vectorsubtract.c * * Copyright (C) 2008-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxglib/nxglib_yuv2rgb.c b/graphics/nxglib/nxglib_yuv2rgb.c index 9a3cb1f228229c2c7a2daab02ef4885d4a45f581..cb4bb9f2fb5843a9f445fe398142cea7a79fe463 100644 --- a/graphics/nxglib/nxglib_yuv2rgb.c +++ b/graphics/nxglib/nxglib_yuv2rgb.c @@ -2,7 +2,7 @@ * graphics/color/nxglib_yuv2rgb.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxmu/nx_drawcircle.c b/graphics/nxmu/nx_drawcircle.c index 5a0780e1a0be917319c018bcab38041a22af4405..22424c19d93075d670c8550356248efaa3ed52ed 100644 --- a/graphics/nxmu/nx_drawcircle.c +++ b/graphics/nxmu/nx_drawcircle.c @@ -2,7 +2,7 @@ * graphics/nxmu/nx_drawcircle.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxmu/nx_drawline.c b/graphics/nxmu/nx_drawline.c index 0267d8058b0a779190d57ba499daebd6825dd04e..7de0af1c1d373711b4d899b780aa77fd2b5b1d81 100644 --- a/graphics/nxmu/nx_drawline.c +++ b/graphics/nxmu/nx_drawline.c @@ -2,7 +2,7 @@ * graphics/nxmu/nx_drawline.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxmu/nx_eventnotify.c b/graphics/nxmu/nx_eventnotify.c index 1892413618c5e9985815349c4d8d9f36c251a308..556c9fa93b7e1f2c156a1883b740ec44e16b2e96 100644 --- a/graphics/nxmu/nx_eventnotify.c +++ b/graphics/nxmu/nx_eventnotify.c @@ -2,7 +2,7 @@ * graphics/nxmu/nx_eventnotify.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxmu/nx_fillcircle.c b/graphics/nxmu/nx_fillcircle.c index bfc1dc9e3987defb5f52844d1bd6be3a7f638778..5c96716953da0f9efbb2a3598891544659f591eb 100644 --- a/graphics/nxmu/nx_fillcircle.c +++ b/graphics/nxmu/nx_fillcircle.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_fillcircle.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxmu/nxmu_openwindow.c b/graphics/nxmu/nxmu_openwindow.c index 4cd6e661ce38ab3f1e30de898f2fe24008c926cb..395f0a77014cad1b02612a6a78aa7b6a59e4597d 100644 --- a/graphics/nxmu/nxmu_openwindow.c +++ b/graphics/nxmu/nxmu_openwindow.c @@ -2,7 +2,7 @@ * graphics/nxmu/nxmu_openwindow.c * * Copyright (C) 2008-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxmu/nxmu_releasebkgd.c b/graphics/nxmu/nxmu_releasebkgd.c index 3d1f24b79223a7b3b4fbcfcf4726ef8f3a00a922..4183b223d328201fa6c8d7199e330a15f890c2fc 100644 --- a/graphics/nxmu/nxmu_releasebkgd.c +++ b/graphics/nxmu/nxmu_releasebkgd.c @@ -2,7 +2,7 @@ * graphics/nxmu/nxmu_releasebkgd.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxmu/nxmu_requestbkgd.c b/graphics/nxmu/nxmu_requestbkgd.c index 0e69351e6f43c682d25390ab72bbcd74faf10703..47b1ad13fb6d50e1433e0de8284612cbe1f358bb 100644 --- a/graphics/nxmu/nxmu_requestbkgd.c +++ b/graphics/nxmu/nxmu_requestbkgd.c @@ -2,7 +2,7 @@ * graphics/nxmu/nxmu_requestbkgd.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxmu/nxmu_semtake.c b/graphics/nxmu/nxmu_semtake.c index 10fd5bd4a654e42329ee62164f0b063138dbd834..164a099b87c133d21c622b87cd7cf6f9e639e535 100644 --- a/graphics/nxmu/nxmu_semtake.c +++ b/graphics/nxmu/nxmu_semtake.c @@ -2,7 +2,7 @@ * graphics/nxmu/nxmu_semtake.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_bitmap.c b/graphics/nxsu/nx_bitmap.c index 696b94afe01d36a68b380f158b673c8670599643..99fcbbb7013762c1bbfa0499541c026b82143003 100644 --- a/graphics/nxsu/nx_bitmap.c +++ b/graphics/nxsu/nx_bitmap.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_bitmap.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_close.c b/graphics/nxsu/nx_close.c index a3fa9b74d28195c0439be48ab9279ee94935b256..b48a2fca2dccc744f639d587f1ab45ca850d4e00 100644 --- a/graphics/nxsu/nx_close.c +++ b/graphics/nxsu/nx_close.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_close.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_closewindow.c b/graphics/nxsu/nx_closewindow.c index c5a2799eaf4c9c36693c03b0489c5bbc7af7e70b..879d049d4de35e1a9a9438cc553b61b6d5b39c54 100644 --- a/graphics/nxsu/nx_closewindow.c +++ b/graphics/nxsu/nx_closewindow.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_closewindow.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_drawcircle.c b/graphics/nxsu/nx_drawcircle.c index 8d5c1245490a88526738bf33977559e5d4ca3311..30b3072190ab96d94193a4c9510fa6528b0023e4 100644 --- a/graphics/nxsu/nx_drawcircle.c +++ b/graphics/nxsu/nx_drawcircle.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_drawcircle.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_drawline.c b/graphics/nxsu/nx_drawline.c index ca4ddaf188af8c53bd44675bad5608c10bc05eff..99e3494b9e3391d019929c2fe5b779fd93b9a4eb 100644 --- a/graphics/nxsu/nx_drawline.c +++ b/graphics/nxsu/nx_drawline.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_drawline.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_fill.c b/graphics/nxsu/nx_fill.c index 9075f82c010d619907654ad09f68c458b300cbc8..037cb5e13b2823ef073a1d5dbbae8fc1df0166ec 100644 --- a/graphics/nxsu/nx_fill.c +++ b/graphics/nxsu/nx_fill.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_fill.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_fillcircle.c b/graphics/nxsu/nx_fillcircle.c index 12c47f80a1efbb47907936485e8820a71a23c341..f3876057a272cea6f1c5181bcef8cbe4ac50143e 100644 --- a/graphics/nxsu/nx_fillcircle.c +++ b/graphics/nxsu/nx_fillcircle.c @@ -2,7 +2,7 @@ * graphics/nxmu/nx_fillcircle.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_filltrapezoid.c b/graphics/nxsu/nx_filltrapezoid.c index 869ce3e1a0e5ca4f9db5df05a848f1b19a9f7d91..353b91f6e4e3fdbed83d94e3daf99f62964e5ce8 100644 --- a/graphics/nxsu/nx_filltrapezoid.c +++ b/graphics/nxsu/nx_filltrapezoid.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_filltrapezoid.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_getposition.c b/graphics/nxsu/nx_getposition.c index 8760d84c165e4384a81c936803f8ba92566c58c7..acc63308715ccb99157234d9743cf9feb0ca0a96 100644 --- a/graphics/nxsu/nx_getposition.c +++ b/graphics/nxsu/nx_getposition.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_getposition.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_kbdchin.c b/graphics/nxsu/nx_kbdchin.c index 7ecea5db95c62d89a336c75023397703b11f632a..f07462f22943e87cfabab826dafd15e234591868 100644 --- a/graphics/nxsu/nx_kbdchin.c +++ b/graphics/nxsu/nx_kbdchin.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_kbdchin.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_kbdin.c b/graphics/nxsu/nx_kbdin.c index 9fc8460bdd7eb11a15204c6c5e075cbbe976868a..6acd96a72fef5e9f2cb9b13a9db07540f04b39b0 100644 --- a/graphics/nxsu/nx_kbdin.c +++ b/graphics/nxsu/nx_kbdin.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_kbdin.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_lower.c b/graphics/nxsu/nx_lower.c index dbfd278c411eca2f775efea17f706be6951cafcd..5c47185f8d11c0d650273ef8ecf03c6bb49617ae 100644 --- a/graphics/nxsu/nx_lower.c +++ b/graphics/nxsu/nx_lower.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_lower.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_move.c b/graphics/nxsu/nx_move.c index b16cf3525e0626f05dcfe45847a35f209a25aeae..9fb303147a4037f45e8e34ba3ee8192a7b7b2851 100644 --- a/graphics/nxsu/nx_move.c +++ b/graphics/nxsu/nx_move.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_move.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_open.c b/graphics/nxsu/nx_open.c index f5e07dc5ec0cc55592bb22f668917d38ff3152e8..72a2db05896adfc0e1f5a4c8c84994c2cf774d78 100644 --- a/graphics/nxsu/nx_open.c +++ b/graphics/nxsu/nx_open.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_open.c * * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_raise.c b/graphics/nxsu/nx_raise.c index cf4e38b64cb12899b6705d056ed96f030f3b4d6c..e0ede540066ceecbaaa8411aa99c6256ed0e1e84 100644 --- a/graphics/nxsu/nx_raise.c +++ b/graphics/nxsu/nx_raise.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_raise.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_requestbkgd.c b/graphics/nxsu/nx_requestbkgd.c index 5bd4554bc9d9a1cca90719f509e02fc06ec4252d..7f0ab12f259fe3f79a25bf67174e633fe0db1918 100644 --- a/graphics/nxsu/nx_requestbkgd.c +++ b/graphics/nxsu/nx_requestbkgd.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_requestbkgd.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_setbgcolor.c b/graphics/nxsu/nx_setbgcolor.c index d8c2159efa1df2f4b3c8065cb014befe9d9c85be..5f9818855f3a68b2d81aa8adc8990857a1d786b4 100644 --- a/graphics/nxsu/nx_setbgcolor.c +++ b/graphics/nxsu/nx_setbgcolor.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_setbgcolor.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nx_setsize.c b/graphics/nxsu/nx_setsize.c index 171e26faed0eb2ce7ed881c36e029a9863cbb5b3..4872abf03419dbf85f0e6c858de288aa535d6762 100644 --- a/graphics/nxsu/nx_setsize.c +++ b/graphics/nxsu/nx_setsize.c @@ -2,7 +2,7 @@ * graphics/nxsu/nx_setsize.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nxfe.h b/graphics/nxsu/nxfe.h index 59f5b7e61c3a009db68c4f8c56373cceb639911b..528224fc162c377a9fdb2765ca675b24e66f8795 100644 --- a/graphics/nxsu/nxfe.h +++ b/graphics/nxsu/nxfe.h @@ -2,7 +2,7 @@ * graphics/nxsu/nxfe.h * * Copyright (C) 2008-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nxsu_redrawreq.c b/graphics/nxsu/nxsu_redrawreq.c index 9efa828a51cc58d3528c2d9c4d51051283da0f14..21845f16fae9e29902bc9ce398e182d63fff1db8 100644 --- a/graphics/nxsu/nxsu_redrawreq.c +++ b/graphics/nxsu/nxsu_redrawreq.c @@ -2,7 +2,7 @@ * graphics/nxsu/nxsu_redrawreq.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxsu/nxsu_reportposition.c b/graphics/nxsu/nxsu_reportposition.c index d87dac0f6bc4d7c7e14030f264080cfec2a2e0b4..b795a81e6337bdbdb9444c8d7928852028edbde4 100644 --- a/graphics/nxsu/nxsu_reportposition.c +++ b/graphics/nxsu/nxsu_reportposition.c @@ -2,7 +2,7 @@ * graphics/nxsu/nxsu_reportposition.c * * Copyright (C) 2008-2009,2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_bitmapwindow.c b/graphics/nxtk/nxtk_bitmapwindow.c index a439f5f797a42d15d5b4b4f8ea8a3480f934270c..6847c44d460de9b9c6cbc9a66fd0d3b1de7132f7 100644 --- a/graphics/nxtk/nxtk_bitmapwindow.c +++ b/graphics/nxtk/nxtk_bitmapwindow.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_bitmapwindow.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_closetoolbar.c b/graphics/nxtk/nxtk_closetoolbar.c index dff621a44f18034e7e2f2172ad0626d3d1ad13de..7ad36f9d87157469968e862b5650bc2c18cf4776 100644 --- a/graphics/nxtk/nxtk_closetoolbar.c +++ b/graphics/nxtk/nxtk_closetoolbar.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_closetoolbar.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_closewindow.c b/graphics/nxtk/nxtk_closewindow.c index e921f669e0141a00c0702e431c7fcba191067744..e80cd0c665cd40033df72c4c313c0fac851f66a5 100644 --- a/graphics/nxtk/nxtk_closewindow.c +++ b/graphics/nxtk/nxtk_closewindow.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_closewindow.c * * Copyright (C) 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_containerclip.c b/graphics/nxtk/nxtk_containerclip.c index 3671851f1721dc1eebae1740aebe5e1cb0af4686..a2fbcd0f8fdff3c05ebb54a7d9f1f93c3d37c8a5 100644 --- a/graphics/nxtk/nxtk_containerclip.c +++ b/graphics/nxtk/nxtk_containerclip.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_containerclip.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_drawcircletoolbar.c b/graphics/nxtk/nxtk_drawcircletoolbar.c index e9d9ca8ffba68991336b5a33086cc286950ece69..a36ed32eefc0929ea3550fd2888aa2946a2d9117 100644 --- a/graphics/nxtk/nxtk_drawcircletoolbar.c +++ b/graphics/nxtk/nxtk_drawcircletoolbar.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_drawcircletoolbar.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_drawcirclewindow.c b/graphics/nxtk/nxtk_drawcirclewindow.c index f70c1c3515ced01e5821b14ee486a93a042651a8..080e802ec11bbf2c7211c5378f55de8ce2199dc5 100644 --- a/graphics/nxtk/nxtk_drawcirclewindow.c +++ b/graphics/nxtk/nxtk_drawcirclewindow.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_drawcirclewindow.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_drawlinetoolbar.c b/graphics/nxtk/nxtk_drawlinetoolbar.c index 4af8b373271b058a2327d2fb0af9daefe0655d3f..f2a559d6900a6f930cd1078ab7597e8bd4ee97e3 100644 --- a/graphics/nxtk/nxtk_drawlinetoolbar.c +++ b/graphics/nxtk/nxtk_drawlinetoolbar.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_drawlinetoolbar.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_drawlinewindow.c b/graphics/nxtk/nxtk_drawlinewindow.c index 2dfd7e8452169d9d9306f8dbb9c49dd51933ab1a..a5534fa59e4991e1f62a2f374d4decff2c5561fb 100644 --- a/graphics/nxtk/nxtk_drawlinewindow.c +++ b/graphics/nxtk/nxtk_drawlinewindow.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_drawlinewindow.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_fillcircletoolbar.c b/graphics/nxtk/nxtk_fillcircletoolbar.c index d0bb09edd243a8032336447c34f20555a3565316..92dee7e27f2b6f12a6749890855dae71597955e2 100644 --- a/graphics/nxtk/nxtk_fillcircletoolbar.c +++ b/graphics/nxtk/nxtk_fillcircletoolbar.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_fillcircletoolbar.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_fillcirclewindow.c b/graphics/nxtk/nxtk_fillcirclewindow.c index 34c9458650ec6515bb902498c437931067ba00bd..5f093e0354fd31a10a40df9cbdf0923addc98f68 100644 --- a/graphics/nxtk/nxtk_fillcirclewindow.c +++ b/graphics/nxtk/nxtk_fillcirclewindow.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_fillcirclewindow.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_filltoolbar.c b/graphics/nxtk/nxtk_filltoolbar.c index c39199e6a89bfc5ea75d78ee89d994100bda4ec2..931fa7decb38c3028dc82149bf870ef9fce708ab 100644 --- a/graphics/nxtk/nxtk_filltoolbar.c +++ b/graphics/nxtk/nxtk_filltoolbar.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_filltoolbar.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_filltraptoolbar.c b/graphics/nxtk/nxtk_filltraptoolbar.c index 1f04e9b43ea7872b60db0786a4483e5850232b93..7108f42eb66f5d57146bdb2a002c4d4544fb1194 100644 --- a/graphics/nxtk/nxtk_filltraptoolbar.c +++ b/graphics/nxtk/nxtk_filltraptoolbar.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_filltraptoolbar.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_filltrapwindow.c b/graphics/nxtk/nxtk_filltrapwindow.c index c84c055f8859a847114a7270af545f914bda098d..c1032f1e75ad882cd19722ce6f7f7930bb65ae83 100644 --- a/graphics/nxtk/nxtk_filltrapwindow.c +++ b/graphics/nxtk/nxtk_filltrapwindow.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_filltrapwindow.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_fillwindow.c b/graphics/nxtk/nxtk_fillwindow.c index e971ce06bc9910c17af847341734c0f02104fda1..c76dbfbb4687a7c28da90797e1c19fd151b8aeb3 100644 --- a/graphics/nxtk/nxtk_fillwindow.c +++ b/graphics/nxtk/nxtk_fillwindow.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_fillwindow.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_getposition.c b/graphics/nxtk/nxtk_getposition.c index e6cce602620c6e4d9143cee8fc4aba9e01c22e2c..7850f771442a48c577476aaedf77a3614739e6d7 100644 --- a/graphics/nxtk/nxtk_getposition.c +++ b/graphics/nxtk/nxtk_getposition.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_getposition.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_lower.c b/graphics/nxtk/nxtk_lower.c index 256ed27dabbbce7c01d9a631d0e24016ad87e815..e37e020fc0382f91987ddb6e5597c83957f44bad 100644 --- a/graphics/nxtk/nxtk_lower.c +++ b/graphics/nxtk/nxtk_lower.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_lower.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_movetoolbar.c b/graphics/nxtk/nxtk_movetoolbar.c index 088611382adbc55e698c19014dfb6ba450691286..9170394f1de149a4122c6db81cff86d5dad213b2 100644 --- a/graphics/nxtk/nxtk_movetoolbar.c +++ b/graphics/nxtk/nxtk_movetoolbar.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_movetoolbar.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_movewindow.c b/graphics/nxtk/nxtk_movewindow.c index 4c45c101c5a05d187d01fd7257eecf2fdd700d91..83d95b3a4e5f1bdcac3d52bd024238959c37ee0f 100644 --- a/graphics/nxtk/nxtk_movewindow.c +++ b/graphics/nxtk/nxtk_movewindow.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_movewindow.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_opentoolbar.c b/graphics/nxtk/nxtk_opentoolbar.c index 56ca941b8f424d4d219e981c4578f5ff2f9589af..e82dbed6fd8cb5e5b4eec0ae70f49041b60799f6 100644 --- a/graphics/nxtk/nxtk_opentoolbar.c +++ b/graphics/nxtk/nxtk_opentoolbar.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_opentoolbar.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_raise.c b/graphics/nxtk/nxtk_raise.c index 1e35f3ab2afa53356042bb016bcb35ec7393669c..f20b258992448d5da45e59b1b10d126ca9ec5792 100644 --- a/graphics/nxtk/nxtk_raise.c +++ b/graphics/nxtk/nxtk_raise.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_raise.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_setsize.c b/graphics/nxtk/nxtk_setsize.c index aeeebf1500854cfb339bd2e89a944129f51f6f9b..332ea00b576671c2e71a6f61ee5501c5800a81ac 100644 --- a/graphics/nxtk/nxtk_setsize.c +++ b/graphics/nxtk/nxtk_setsize.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_setsize.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_setsubwindows.c b/graphics/nxtk/nxtk_setsubwindows.c index 2510083610679ffb91d938e977d2adb06f696c2d..143909ea4cac79f916577409685c58f97b79ef06 100644 --- a/graphics/nxtk/nxtk_setsubwindows.c +++ b/graphics/nxtk/nxtk_setsubwindows.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_setsubwindows.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_subwindowclip.c b/graphics/nxtk/nxtk_subwindowclip.c index 4d453eecafe0715804574bcab145a4e4a02e620d..2dbefb6481e7b0c387067ac006245b3a47643f5d 100644 --- a/graphics/nxtk/nxtk_subwindowclip.c +++ b/graphics/nxtk/nxtk_subwindowclip.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_subwindowclip.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/graphics/nxtk/nxtk_subwindowmove.c b/graphics/nxtk/nxtk_subwindowmove.c index ed6a264e73538714eab149e3d27069df96830103..a6fd9f5ddb6a423860f02898c9324287d9484360 100644 --- a/graphics/nxtk/nxtk_subwindowmove.c +++ b/graphics/nxtk/nxtk_subwindowmove.c @@ -2,7 +2,7 @@ * graphics/nxtk/nxtk_subwindowmove.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/mqueue/mq_getattr.c b/lib/mqueue/mq_getattr.c index 005ec0f24576efeea1770dfded944adfd59330e0..9c9f47fdce05ea52ac3d9d2fbc792b520191cca9 100644 --- a/lib/mqueue/mq_getattr.c +++ b/lib/mqueue/mq_getattr.c @@ -2,7 +2,7 @@ * lib/mqueue/mq_getattr.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/mqueue/mq_setattr.c b/lib/mqueue/mq_setattr.c index 5d82299fe738f8bcc436c0a7cd40554272dcf01d..1276d64e8aefeb45c1c96a3a8a6206c4bb531586 100644 --- a/lib/mqueue/mq_setattr.c +++ b/lib/mqueue/mq_setattr.c @@ -2,7 +2,7 @@ * lib/mqueue/mq_setattr.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/queue/dq_addafter.c b/lib/queue/dq_addafter.c index e9f0d9a3ec39019a8a6bb091671df011b3e33a76..bfbe0052d8e9becaa52906fffb0e1cbca7947e27 100644 --- a/lib/queue/dq_addafter.c +++ b/lib/queue/dq_addafter.c @@ -2,7 +2,7 @@ * lib/queue/dq_addafter.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/queue/dq_addbefore.c b/lib/queue/dq_addbefore.c index c49dff78b7d560f84413837725b0bcab79419791..d740ea83092509cf5a30f526ff1f146f8eba9f6d 100644 --- a/lib/queue/dq_addbefore.c +++ b/lib/queue/dq_addbefore.c @@ -2,7 +2,7 @@ * lib/queue/dq_addbefore.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/queue/dq_addfirst.c b/lib/queue/dq_addfirst.c index 27da2c491c1440b8777af67ec27e4918e0c658d2..7c7312de3b77fcec2c37f96d32314460d4ceaa77 100644 --- a/lib/queue/dq_addfirst.c +++ b/lib/queue/dq_addfirst.c @@ -2,7 +2,7 @@ * lib/queue/dq_addfirst.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/queue/dq_addlast.c b/lib/queue/dq_addlast.c index c7a06096121bac5810153a9407e5830f5e63559e..745deb27d1e32d9b8812121fa91b3e95748e5051 100644 --- a/lib/queue/dq_addlast.c +++ b/lib/queue/dq_addlast.c @@ -2,7 +2,7 @@ * lib/queue/dq_addlast.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/queue/dq_rem.c b/lib/queue/dq_rem.c index adf99efed206b0090af6f8e2db76ed62e7e981dc..218427bf8497c15fd7ed6b751f505320ee43784a 100644 --- a/lib/queue/dq_rem.c +++ b/lib/queue/dq_rem.c @@ -2,7 +2,7 @@ * lib/queue/dq_rem.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/queue/dq_remfirst.c b/lib/queue/dq_remfirst.c index c42f3f2cc5bf529bf5e9664bb2983007b084e85f..26c5fd7a67dfc6857bdf11f3b84186ec29b564f9 100644 --- a/lib/queue/dq_remfirst.c +++ b/lib/queue/dq_remfirst.c @@ -2,7 +2,7 @@ * lib/queue/dq_remfirst.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/queue/dq_remlast.c b/lib/queue/dq_remlast.c index 6280a0e516518df15f50a8a12dc5927c288c2765..35adc73e2dd9cc1039fb26f9a90ca88cb0ef994e 100644 --- a/lib/queue/dq_remlast.c +++ b/lib/queue/dq_remlast.c @@ -2,7 +2,7 @@ * lib/queue/dq_remlast.c * * Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/queue/sq_addafter.c b/lib/queue/sq_addafter.c index 05e1157fd4dd2095b4104b5e7fa731ef024af79d..965ac284440d6a04b220a225faad191326573665 100644 --- a/lib/queue/sq_addafter.c +++ b/lib/queue/sq_addafter.c @@ -2,7 +2,7 @@ * lib/queue/sq_addafter.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/queue/sq_addfirst.c b/lib/queue/sq_addfirst.c index 8f55053d41d576fb0a793ff4204ef9f0b6579c49..8fc8e061990c5cb7156417062ae283801ac109b2 100644 --- a/lib/queue/sq_addfirst.c +++ b/lib/queue/sq_addfirst.c @@ -2,7 +2,7 @@ * lib/queue/sq_addfirst.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/queue/sq_addlast.c b/lib/queue/sq_addlast.c index 15054a70337f380ff642a85e99eab1015b1c11f9..f9f9625cc0b1866cac6097218aa691cab3ea203a 100644 --- a/lib/queue/sq_addlast.c +++ b/lib/queue/sq_addlast.c @@ -2,7 +2,7 @@ * lib/queue/sq_addlast.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/queue/sq_rem.c b/lib/queue/sq_rem.c index 972e8e1c329a1f2d3fb99718203b73e24c27143d..6ba52354d446db040b722c03fb76e767f52489ec 100644 --- a/lib/queue/sq_rem.c +++ b/lib/queue/sq_rem.c @@ -2,7 +2,7 @@ * lib/queue/sq_rem.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/queue/sq_remafter.c b/lib/queue/sq_remafter.c index 781a2b6ad2cf09f0ce786b763569001716780e5c..4dcfb06e443120440b42c5425ec342a4115b9286 100644 --- a/lib/queue/sq_remafter.c +++ b/lib/queue/sq_remafter.c @@ -2,7 +2,7 @@ * lib/queue/sq_remafter.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/queue/sq_remfirst.c b/lib/queue/sq_remfirst.c index 5a273ad6af0d107a66e3a1f1131f5eeafebeb74a..43df6de417317be5cc2906528421885038391e02 100644 --- a/lib/queue/sq_remfirst.c +++ b/lib/queue/sq_remfirst.c @@ -2,7 +2,7 @@ * lib/queue/sq_remfirst.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/queue/sq_remlast.c b/lib/queue/sq_remlast.c index a66c6bcbb78419b0b04b264f7786ea46894aedfe..92cdbde985fe21d9595306c038bf99316fd705b2 100644 --- a/lib/queue/sq_remlast.c +++ b/lib/queue/sq_remlast.c @@ -2,7 +2,7 @@ * lib/queue/sq_remlast.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_checkbase.c b/lib/string/lib_checkbase.c index bec131b5c71733b21279efc92cb2c5bbeb99dc28..bc79ab2cec7d9d29fea1cd81dbb8a614bac097c9 100644 --- a/lib/string/lib_checkbase.c +++ b/lib/string/lib_checkbase.c @@ -2,7 +2,7 @@ * lib/string/lib_checkbase.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_isbasedigit.c b/lib/string/lib_isbasedigit.c index 26426e8213e5141c247a056a04b85f148ac8d049..a2421bf2a49ba6be9adc504918c9b2c821f8f023 100644 --- a/lib/string/lib_isbasedigit.c +++ b/lib/string/lib_isbasedigit.c @@ -2,7 +2,7 @@ * lib/string/lib_isbasedigit.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_memcmp.c b/lib/string/lib_memcmp.c index cd874a85e499c9bd46418ba88a4336646502dbc8..eb2e1fd1253803ca9d860d77d75ff48e31e21507 100644 --- a/lib/string/lib_memcmp.c +++ b/lib/string/lib_memcmp.c @@ -2,7 +2,7 @@ * lib/string/lib_memcmp.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_memmove.c b/lib/string/lib_memmove.c index 97bac99ed9078b6f1dab0935a95a7de03fc58990..ecaeb54cf2fb1288c0e464422978a86d13584c7b 100644 --- a/lib/string/lib_memmove.c +++ b/lib/string/lib_memmove.c @@ -2,7 +2,7 @@ * lib/string/lib_memmove.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_memset.c b/lib/string/lib_memset.c index f3a5497a9aee6e9db0d39f3bdb583f4d469e7b8c..916351b974ab090ad1b9a94b646f2c228a7efb43 100644 --- a/lib/string/lib_memset.c +++ b/lib/string/lib_memset.c @@ -2,7 +2,7 @@ * lib/string/lib_memset.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_skipspace.c b/lib/string/lib_skipspace.c index 826559efedb4c8b28c4b770f8b927ecf4b3219ad..b4e6588e59439a7fbb44fc84aefdf791a7d0a0ed 100644 --- a/lib/string/lib_skipspace.c +++ b/lib/string/lib_skipspace.c @@ -2,7 +2,7 @@ * lib/string/lib_skipspace.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strcasecmp.c b/lib/string/lib_strcasecmp.c index ed5217831f4399ff6ff73fe8ed2a73516682939b..d4aa8cc0315344141e2ddde41f2f4069f8387835 100644 --- a/lib/string/lib_strcasecmp.c +++ b/lib/string/lib_strcasecmp.c @@ -2,7 +2,7 @@ * lib/string/lib_strcasecmp.c * * Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strcat.c b/lib/string/lib_strcat.c index 2d12dd5a64849b63456b194ac740067d80a1af19..20350fec076fdba347092ef31efa74cb7bcad7aa 100644 --- a/lib/string/lib_strcat.c +++ b/lib/string/lib_strcat.c @@ -1,62 +1,62 @@ -/**************************************************************************** - * lib/string/lib_strcat.c - * - * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -/**************************************************************************** - * Global Functions - ****************************************************************************/ - -#ifndef CONFIG_ARCH_STRCAT -char *strcat(char *dest, const char *src) -{ - char *ret = dest; - - dest += strlen(dest); - while (*src != '\0') - { - *dest++ = *src++; - } - *dest = '\0'; - - return ret; -} -#endif +/**************************************************************************** + * lib/string/lib_strcat.c + * + * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +#ifndef CONFIG_ARCH_STRCAT +char *strcat(char *dest, const char *src) +{ + char *ret = dest; + + dest += strlen(dest); + while (*src != '\0') + { + *dest++ = *src++; + } + *dest = '\0'; + + return ret; +} +#endif diff --git a/lib/string/lib_strcmp.c b/lib/string/lib_strcmp.c index 1d78cb0495434a90d897f46003e85b7de796a313..0e3eee89007afcff56907bb049e11dbb98930655 100644 --- a/lib/string/lib_strcmp.c +++ b/lib/string/lib_strcmp.c @@ -2,7 +2,7 @@ * lib/string/lib_strcmp.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strcpy.c b/lib/string/lib_strcpy.c index 774e155347ec4c2506b62c4e42c248e72313264c..e2f70b94e324bd49dff138701b46e3611f5da2c0 100644 --- a/lib/string/lib_strcpy.c +++ b/lib/string/lib_strcpy.c @@ -2,7 +2,7 @@ * lib/string/lib_strcpy.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strcspn.c b/lib/string/lib_strcspn.c index b28f223431a4750a03f12c4cd8b7799da02eaf48..9da89241c530425f14d34eadf23bc975ab4ed94e 100644 --- a/lib/string/lib_strcspn.c +++ b/lib/string/lib_strcspn.c @@ -2,7 +2,7 @@ * lib/string/lib_strcspn.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strdup.c b/lib/string/lib_strdup.c index a353c629da84876d4cb897161e7cee952d498501..44a0cbc0d8cc335c1f33775f86b0bc2e0bcd5381 100644 --- a/lib/string/lib_strdup.c +++ b/lib/string/lib_strdup.c @@ -2,7 +2,7 @@ * lib/string//lib_strdup.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strlen.c b/lib/string/lib_strlen.c index ee964c1371506851de6345d8db32f6b4579186e6..8333058091c742d0575d3f1992116c2f4b10ea44 100644 --- a/lib/string/lib_strlen.c +++ b/lib/string/lib_strlen.c @@ -2,7 +2,7 @@ * lib/string/lib_strlen.c * * Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strncasecmp.c b/lib/string/lib_strncasecmp.c index 78b18a3fb856fb9fa44b9782b199846bd931317e..be369cf0d819668c83def940b180f44c9dce0258 100644 --- a/lib/string/lib_strncasecmp.c +++ b/lib/string/lib_strncasecmp.c @@ -2,7 +2,7 @@ * lib/string/lib_strncasecmp.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strncat.c b/lib/string/lib_strncat.c index 6b7d54f8166f5351efcb481b44e247c1b6a285d9..af893e0f9bb8e944f9ac3e0e2d5284824ccdf425 100644 --- a/lib/string/lib_strncat.c +++ b/lib/string/lib_strncat.c @@ -2,7 +2,7 @@ * lib/string/lib_strncat.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strncmp.c b/lib/string/lib_strncmp.c index 147dfc536987ad689e26b3156cf512b62148805a..ce22820249823cccb73f16125e281976781898eb 100644 --- a/lib/string/lib_strncmp.c +++ b/lib/string/lib_strncmp.c @@ -2,7 +2,7 @@ * lib/lib_strncmp.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strncpy.c b/lib/string/lib_strncpy.c index b5702cae21840369fdf75c37edddcdd73d72472d..149369d5088b9b9b9304d553e3864772e3a850a5 100644 --- a/lib/string/lib_strncpy.c +++ b/lib/string/lib_strncpy.c @@ -2,7 +2,7 @@ * lib/string/lib_strncpy.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strndup.c b/lib/string/lib_strndup.c index 68b7c74c3615ac11799dc92af5601552546f0d33..ffaf892eaae7e3e7a42527d0afad9b5f1ad773f5 100644 --- a/lib/string/lib_strndup.c +++ b/lib/string/lib_strndup.c @@ -2,7 +2,7 @@ * lib/string//lib_strndup.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strnlen.c b/lib/string/lib_strnlen.c index c2ffc248e62a909426a6304bb2c8ec16ebd1e721..2b64fe9845d9628bf36291750542fa216681d3a1 100644 --- a/lib/string/lib_strnlen.c +++ b/lib/string/lib_strnlen.c @@ -9,7 +9,7 @@ * Derives from the file lib/lib_strlen.c: * * Copyright (C) 2007, 2008, 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strpbrk.c b/lib/string/lib_strpbrk.c index 134058775031f447977ca6be18e68787b66ab963..02e2ea2c70a5a51e2c6e91e0fd64174be9a4bb8e 100644 --- a/lib/string/lib_strpbrk.c +++ b/lib/string/lib_strpbrk.c @@ -2,7 +2,7 @@ * lib/string/lib_strpbrk.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use str source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strrchr.c b/lib/string/lib_strrchr.c index e89b26d523aa14d469ab427a706592f3875175f5..91243ce5899dcc5cb8cf46ad77f1bf1f52176b1d 100644 --- a/lib/string/lib_strrchr.c +++ b/lib/string/lib_strrchr.c @@ -2,7 +2,7 @@ * lib/string/lib_strrchr.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strspn.c b/lib/string/lib_strspn.c index e5cab9ad6574d6c27623d221ad457ec65f21b546..e7b5ea0a5b23e65be6b3816d4809cfffefbb56e0 100644 --- a/lib/string/lib_strspn.c +++ b/lib/string/lib_strspn.c @@ -2,7 +2,7 @@ * lib/string/lib_strspn.c * * Copyright (C) 2007, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strstr.c b/lib/string/lib_strstr.c index 27ca6e19bbdfa2aecb0061f73f5fd3849312acf2..b8c896fa2ec1004a774b81fe39a9b9c5cd98322c 100644 --- a/lib/string/lib_strstr.c +++ b/lib/string/lib_strstr.c @@ -2,7 +2,7 @@ * lib/string/lib_strstr.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use str source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strtok.c b/lib/string/lib_strtok.c index bafa94853e83f6b4a698529121701b24c06131bc..c409931359f0130b16d9aec454b2d216b7d53539 100644 --- a/lib/string/lib_strtok.c +++ b/lib/string/lib_strtok.c @@ -2,7 +2,7 @@ * lib/string/lib_strtok.c * * Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strtokr.c b/lib/string/lib_strtokr.c index 0d12a2381528bdad63dc70c143207cc2389052a6..1c571b6ae57b73d003ad61522d9efda1d5f1d1fc 100644 --- a/lib/string/lib_strtokr.c +++ b/lib/string/lib_strtokr.c @@ -2,7 +2,7 @@ * lib/string/lib_strtokr.c * * Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strtol.c b/lib/string/lib_strtol.c index 4f69047934bfce12d19c8690204b8f8924eb0c14..c17d87e6355805c02bb944a145e8c896183bbc7f 100644 --- a/lib/string/lib_strtol.c +++ b/lib/string/lib_strtol.c @@ -2,7 +2,7 @@ * lib/string/lib_strtol.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strtoll.c b/lib/string/lib_strtoll.c index 9c730b43102e8630820ab43d9109ea435940c20a..242e025c07565b01d37ecc988e5b261cfc2db082 100644 --- a/lib/string/lib_strtoll.c +++ b/lib/string/lib_strtoll.c @@ -2,7 +2,7 @@ * lib/string/lib_strtoll.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strtoul.c b/lib/string/lib_strtoul.c index 2aacc7cea85d2fb5f61ab0c25ad7b5b01c3bbbd7..b0d2d090e6be38af2d27df5979616d08419779d2 100644 --- a/lib/string/lib_strtoul.c +++ b/lib/string/lib_strtoul.c @@ -2,7 +2,7 @@ * /lib/string/lib_strtoul.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/lib/string/lib_strtoull.c b/lib/string/lib_strtoull.c index 334162148125463cbb0d7803091bb1d1fa8d9259..6567457c0ef1063a182122f0020515e6a6dffaad 100644 --- a/lib/string/lib_strtoull.c +++ b/lib/string/lib_strtoull.c @@ -2,7 +2,7 @@ * /lib/string/lib_strtoull.c * * Copyright (C) 2009, 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/libxx/Makefile b/libxx/Makefile index f34a5260008213bf1f746f27b6d35df73848c25f..4122931ac91ad49b296dba8a18ca68dc970c1c99 100644 --- a/libxx/Makefile +++ b/libxx/Makefile @@ -2,7 +2,7 @@ # libxx/Makefile # # Copyright (C) 2009 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/libxx/libxx_delete.cxx b/libxx/libxx_delete.cxx index 223a7bea90261db68404115f21f8c36e3f8c3631..d9203a2280c103fe0cc9f82d62f593e3fb403867 100644 --- a/libxx/libxx_delete.cxx +++ b/libxx/libxx_delete.cxx @@ -2,7 +2,7 @@ // libxx/libxx_new.cxx // // Copyright (C) 2009 Gregory Nutt. All rights reserved. -// Author: Gregory Nutt +// Author: Gregory Nutt // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions diff --git a/libxx/libxx_deletea.cxx b/libxx/libxx_deletea.cxx index 3c519bd2ceb19383840efe49787ed4b223483a1c..e7cfee647bb325a036f55946d3a288b80b0fa16e 100644 --- a/libxx/libxx_deletea.cxx +++ b/libxx/libxx_deletea.cxx @@ -2,7 +2,7 @@ // libxx/libxx_newa.cxx // // Copyright (C) 2009 Gregory Nutt. All rights reserved. -// Author: Gregory Nutt +// Author: Gregory Nutt // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions diff --git a/libxx/libxx_new.cxx b/libxx/libxx_new.cxx index 8ec725ca8b37724a0dfaebb1c9ba1193bd27c04a..0563b658053e378736d6a33f7fd678813044fbc8 100644 --- a/libxx/libxx_new.cxx +++ b/libxx/libxx_new.cxx @@ -2,7 +2,7 @@ // libxx/libxx_new.cxx // // Copyright (C) 2009 Gregory Nutt. All rights reserved. -// Author: Gregory Nutt +// Author: Gregory Nutt // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions diff --git a/libxx/libxx_newa.cxx b/libxx/libxx_newa.cxx index 855160c4120631da9fe9abfa781dfd68dd687227..ad78068653c67ea1ffc5c7a328b4bb22d51306ff 100644 --- a/libxx/libxx_newa.cxx +++ b/libxx/libxx_newa.cxx @@ -2,7 +2,7 @@ // libxx/libxx_newa.cxx // // Copyright (C) 2009 Gregory Nutt. All rights reserved. -// Author: Gregory Nutt +// Author: Gregory Nutt // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions diff --git a/net/listen.c b/net/listen.c index bddb0ab08006a6e4f137c137317407e814fe75f2..5e3c62f6924bc4b1645f0e22e6b429e8f7d39989 100644 --- a/net/listen.c +++ b/net/listen.c @@ -2,7 +2,7 @@ * net/listen.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/net/net_arptimer.c b/net/net_arptimer.c index 89db9f656249ef8853afb4e63889bae8addb53f6..2c5d33c91406a0056b2c4de9bc0cdf0c67b1beb3 100644 --- a/net/net_arptimer.c +++ b/net/net_arptimer.c @@ -2,7 +2,7 @@ * net/net_arptimer.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/net/net_checksd.c b/net/net_checksd.c index 3da3cea62faf1eb65d2b839b7fb6067bfc7204e9..0a6975cad4027ca83937e0462c3c3d4b24b2339a 100644 --- a/net/net_checksd.c +++ b/net/net_checksd.c @@ -2,7 +2,7 @@ * net/net_checksd.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/net/net_dsec2timeval.c b/net/net_dsec2timeval.c index c9d3aeb66f77dc1c8538ed12929020eba5f5793c..0f570cb394b11f850a8fa4d9e127495e2e408f40 100644 --- a/net/net_dsec2timeval.c +++ b/net/net_dsec2timeval.c @@ -2,7 +2,7 @@ * net/net_dsec2timeval.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/net/net_dup.c b/net/net_dup.c index 8465b7ce446548f91957427a6d850c27e2dd5514..3004595445bbf9d1c08683e28aa10e2133112261 100644 --- a/net/net_dup.c +++ b/net/net_dup.c @@ -2,7 +2,7 @@ * net/net_dup.c * * Copyright (C) 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/net/net_dup2.c b/net/net_dup2.c index b27bb69675580fc2a33747121e19dfec1558cfb8..3403a70c31933a3a83d91272c56e3a66b2b6ea87 100644 --- a/net/net_dup2.c +++ b/net/net_dup2.c @@ -2,7 +2,7 @@ * net/net_dup2.c * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/net/net_timeval2dsec.c b/net/net_timeval2dsec.c index 4ca5ecb5f1310e4e3da98cf41333220f4902fc71..e0b25db98109b7896286cc4aa153929069cb9af2 100644 --- a/net/net_timeval2dsec.c +++ b/net/net_timeval2dsec.c @@ -2,7 +2,7 @@ * net/net_timeval2dsec.c * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/net/netdev_count.c b/net/netdev_count.c index 17f0894da6926e7bb391956ea9879973b933d99f..8db1191a29035d9cad297c589fb2a92deac92b17 100644 --- a/net/netdev_count.c +++ b/net/netdev_count.c @@ -2,7 +2,7 @@ * net/netdev_count.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/net/netdev_findbyaddr.c b/net/netdev_findbyaddr.c index 50a246f67e1c30fb90f28ebb12b94af46d46c45c..e8083e4d0c181ea9e3e92342176cab02cc9b7ede 100644 --- a/net/netdev_findbyaddr.c +++ b/net/netdev_findbyaddr.c @@ -2,7 +2,7 @@ * net/netdev_findbyaddr.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/net/netdev_findbyname.c b/net/netdev_findbyname.c index a6ddf0452df2e1ed9c588a603c27ea0aae249028..9f6f895aca26d31c69764feedb4b25ff334c9dcb 100644 --- a/net/netdev_findbyname.c +++ b/net/netdev_findbyname.c @@ -2,7 +2,7 @@ * net/netdev_findbyname.c * * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/net/netdev_unregister.c b/net/netdev_unregister.c index e1aec0e4d8d374e1fc5eaeeb00b9454f00f3e47f..39927340a7cc2b5af1ea3cad450f5b428a2e25b0 100644 --- a/net/netdev_unregister.c +++ b/net/netdev_unregister.c @@ -2,7 +2,7 @@ * net/netdev_unregister.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/net/uip/Make.defs b/net/uip/Make.defs index 8bd8d18396750a10e0cd1879720681f054d17d03..c5d915e6149760113af310a79c4092fdcc3bb36e 100644 --- a/net/uip/Make.defs +++ b/net/uip/Make.defs @@ -2,7 +2,7 @@ # Make.defs # # Copyright (C) 2007, 2009-20010 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/net/uip/uip_arptab.c b/net/uip/uip_arptab.c index 1a29f25df418718f95a78e86905686460dff78d4..3dff97070226c248124efc439394b609441c95d5 100644 --- a/net/uip/uip_arptab.c +++ b/net/uip/uip_arptab.c @@ -3,7 +3,7 @@ * Implementation of the ARP Address Resolution Protocol. * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Based originally on uIP which also has a BSD style license: * diff --git a/net/uip/uip_callback.c b/net/uip/uip_callback.c index 730aa7758c823238cb41a5502b4c9215f88747a6..0c8c3aaa01f30ffa86edd3fa5747e3d985c134e3 100644 --- a/net/uip/uip_callback.c +++ b/net/uip/uip_callback.c @@ -2,7 +2,7 @@ * net/uip/uip_callback.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/net/uip/uip_icmppoll.c b/net/uip/uip_icmppoll.c index ca1d684c01d8b108b6d23758b292c669ddf22b5b..bcf7fe94b348ab2ce9f4f61876bf0c79f5bdf8b6 100644 --- a/net/uip/uip_icmppoll.c +++ b/net/uip/uip_icmppoll.c @@ -2,7 +2,7 @@ * net/uip/uip_icmppoll.c * * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/net/uip/uip_igmpgroup.c b/net/uip/uip_igmpgroup.c index 220de047e502dcdd8e928861eea8d51618f4c826..b92db5476c9f4e08175f6e12a8587ed0e0ce6a39 100755 --- a/net/uip/uip_igmpgroup.c +++ b/net/uip/uip_igmpgroup.c @@ -3,7 +3,7 @@ * IGMP group data structure management logic * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * The NuttX implementation of IGMP was inspired by the IGMP add-on for the * lwIP TCP/IP stack by Steve Reynolds: diff --git a/net/uip/uip_igmpinit.c b/net/uip/uip_igmpinit.c index 7954e7b3e836b69a078f6405f1cbbdd55e34e045..740ddf44b5fe59d8571c896da2eabd06dc5056e4 100755 --- a/net/uip/uip_igmpinit.c +++ b/net/uip/uip_igmpinit.c @@ -3,7 +3,7 @@ * IGMP initialization logic * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * The NuttX implementation of IGMP was inspired by the IGMP add-on for the * lwIP TCP/IP stack by Steve Reynolds: diff --git a/net/uip/uip_igmpinput.c b/net/uip/uip_igmpinput.c index 5b4fbefa426b6a5a8d6b1f449907f8bfc7a8e3a3..40c1cf3ba222b2414f9c8969a726681da7a7194c 100755 --- a/net/uip/uip_igmpinput.c +++ b/net/uip/uip_igmpinput.c @@ -2,7 +2,7 @@ * net/uip/uip_igminput.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * The NuttX implementation of IGMP was inspired by the IGMP add-on for the * lwIP TCP/IP stack by Steve Reynolds: diff --git a/net/uip/uip_igmpjoin.c b/net/uip/uip_igmpjoin.c index eb6e888379334722e30f4a1ece95b1850d377067..c02b0bb8f4c87cdfbf58993188c30d59dfb50ec9 100755 --- a/net/uip/uip_igmpjoin.c +++ b/net/uip/uip_igmpjoin.c @@ -2,7 +2,7 @@ * net/uip/uip_igmpjoin.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * The NuttX implementation of IGMP was inspired by the IGMP add-on for the * lwIP TCP/IP stack by Steve Reynolds: diff --git a/net/uip/uip_igmpleave.c b/net/uip/uip_igmpleave.c index 7e2a31a1962eef7e00fe1dafe52afe6813318d6d..4e08df57672b3ead6682393e10c08bda6b13fd68 100755 --- a/net/uip/uip_igmpleave.c +++ b/net/uip/uip_igmpleave.c @@ -2,7 +2,7 @@ * net/uip/uip_igmpleave.c * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * The NuttX implementation of IGMP was inspired by the IGMP add-on for the * lwIP TCP/IP stack by Steve Reynolds: diff --git a/net/uip/uip_igmpmsg.c b/net/uip/uip_igmpmsg.c index 9ea3daa4eb29a41a6b41ba58cf3110234a4e49a9..5209eaf7aa84756bee87948bc38390a33cce03f7 100755 --- a/net/uip/uip_igmpmsg.c +++ b/net/uip/uip_igmpmsg.c @@ -2,7 +2,7 @@ * net/uip/uip_igmpmgs.c * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * The NuttX implementation of IGMP was inspired by the IGMP add-on for the * lwIP TCP/IP stack by Steve Reynolds: diff --git a/net/uip/uip_igmppoll.c b/net/uip/uip_igmppoll.c index cec2a5e1b7c85891aba85e880f2d0acbb4301be8..e86eb687bed81aadb2ba0afb10e24acd8455185d 100755 --- a/net/uip/uip_igmppoll.c +++ b/net/uip/uip_igmppoll.c @@ -2,7 +2,7 @@ * net/uip/uip_igmppoll.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * The NuttX implementation of IGMP was inspired by the IGMP add-on for the * lwIP TCP/IP stack by Steve Reynolds: diff --git a/net/uip/uip_igmpsend.c b/net/uip/uip_igmpsend.c index 21fc2beb039d8a7b4374fbfdc6863394bc005b62..f22282b62a4e173b388fae0684a7fbe760443b70 100755 --- a/net/uip/uip_igmpsend.c +++ b/net/uip/uip_igmpsend.c @@ -2,7 +2,7 @@ * net/uip/uip_igmpsend.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/net/uip/uip_igmptimer.c b/net/uip/uip_igmptimer.c index 27e2f9ff05722558c2bf96d2ad60f8bac2d1bf06..4655f3a2f33aab2ffadeb2edea4192697e06acbe 100755 --- a/net/uip/uip_igmptimer.c +++ b/net/uip/uip_igmptimer.c @@ -2,7 +2,7 @@ * net/uip/uip_igmptimer.c * * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * The NuttX implementation of IGMP was inspired by the IGMP add-on for the * lwIP TCP/IP stack by Steve Reynolds: diff --git a/net/uip/uip_initialize.c b/net/uip/uip_initialize.c index 8839836c4432f2f21884951827e2f5c1eb09ea6f..e737d646ed95bf22c8358e3ed260ad988f96df9d 100644 --- a/net/uip/uip_initialize.c +++ b/net/uip/uip_initialize.c @@ -2,7 +2,7 @@ * net/uip/uip_initialize.c * * Copyright (C) 2007-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Adapted for NuttX from logic in uIP which also has a BSD-like license: * diff --git a/net/uip/uip_listen.c b/net/uip/uip_listen.c index 5f867fef2d9951a4b5bab5e32f8fd7f4705beb6b..420fbb07061392b6d0f2b91f08de4909d580c4f5 100644 --- a/net/uip/uip_listen.c +++ b/net/uip/uip_listen.c @@ -2,7 +2,7 @@ * net/uip/uip_listen.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * A direct leverage of logic from uIP which also has b BSD style license * diff --git a/net/uip/uip_mcastmac.c b/net/uip/uip_mcastmac.c index 7795becab5f76346cff416eb2d8cabd227c2ea1d..9bd1461987aecb07f206c020b7a7ab607e11d84e 100755 --- a/net/uip/uip_mcastmac.c +++ b/net/uip/uip_mcastmac.c @@ -2,7 +2,7 @@ * net/uip/uip_mcastmac.c * * Copyright (C) 2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * The NuttX implementation of IGMP was inspired by the IGMP add-on for the * lwIP TCP/IP stack by Steve Reynolds: diff --git a/net/uip/uip_neighbor.h b/net/uip/uip_neighbor.h index eac08f9382e19b64069068b943f52b2f9933dd93..b55835b74e0f84bd80accde74dbf817d420bef32 100644 --- a/net/uip/uip_neighbor.h +++ b/net/uip/uip_neighbor.h @@ -3,7 +3,7 @@ * to be used by future ARP code. * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * A direct leverage of logic from uIP which also has b BSD style license * diff --git a/net/uip/uip_send.c b/net/uip/uip_send.c index fd0f4f7da2da754dffb8c83809afe4450886853c..b26c799a04ebd24fdf0cf93d4b635095f854b62e 100644 --- a/net/uip/uip_send.c +++ b/net/uip/uip_send.c @@ -2,7 +2,7 @@ * net/uip/uip_send.c * * Copyright (C) 2007i, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Based in part on uIP which also has a BSD stylie license: * diff --git a/net/uip/uip_setipid.c b/net/uip/uip_setipid.c index f9d13cc9d791949d5882f5caf85e69ceed48ea69..12a94860b86d234b2d99e2608067eeca910b4597 100644 --- a/net/uip/uip_setipid.c +++ b/net/uip/uip_setipid.c @@ -2,7 +2,7 @@ * net/uip/uip_setipid.c * * Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * * Redistribution and use in source and binary forms, with or without diff --git a/net/uip/uip_tcpappsend.c b/net/uip/uip_tcpappsend.c index d8a1875034986c9c4264e9ea45dff9e8b95186fb..dfddbcff9bbc202d9c48b730171c144914a0ba4d 100644 --- a/net/uip/uip_tcpappsend.c +++ b/net/uip/uip_tcpappsend.c @@ -2,7 +2,7 @@ * net/uip/uip_tcpappsend.c * * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Adapted for NuttX from logic in uIP which also has a BSD-like license: * diff --git a/net/uip/uip_tcpcallback.c b/net/uip/uip_tcpcallback.c index 9ce8eb132af1fd80c43192aa480b9067f304aa73..8ac1351f70234bb5503c069e552756f73c04b5ed 100644 --- a/net/uip/uip_tcpcallback.c +++ b/net/uip/uip_tcpcallback.c @@ -2,7 +2,7 @@ * net/uip/uip_tcpcallback.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/net/uip/uip_tcpconn.c b/net/uip/uip_tcpconn.c index c2b64ad898286fff61bb9c654a97e842b64390e8..31e020f63110bf2d1222e48d9987ba8b2a0ee809 100644 --- a/net/uip/uip_tcpconn.c +++ b/net/uip/uip_tcpconn.c @@ -2,7 +2,7 @@ * net/uip/uip_tcpconn.c * * Copyright (C) 2007-2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Large parts of this file were leveraged from uIP logic: * diff --git a/net/uip/uip_tcppoll.c b/net/uip/uip_tcppoll.c index 29cb6d4b4330e0613d0e624e411b0231ee7aafce..ddc8ab029b09112d8977ebdb48a6f667ce468ac7 100644 --- a/net/uip/uip_tcppoll.c +++ b/net/uip/uip_tcppoll.c @@ -3,7 +3,7 @@ * Poll for the availability of TCP TX data * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Adapted for NuttX from logic in uIP which also has a BSD-like license: * diff --git a/net/uip/uip_tcpreadahead.c b/net/uip/uip_tcpreadahead.c index 21ed58b99cef437f23fed6aa0de557c69756d100..a304925a8710c4ecec491f99b73e4d174997f676 100644 --- a/net/uip/uip_tcpreadahead.c +++ b/net/uip/uip_tcpreadahead.c @@ -2,7 +2,7 @@ * net/uip/uip_tcpreadahead.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/net/uip/uip_tcpseqno.c b/net/uip/uip_tcpseqno.c index eab3a054a66fa44d3ab33897d22ba0655a49c3a2..2eca06e85bb8bf293d752d215c3e3db85461ea6d 100755 --- a/net/uip/uip_tcpseqno.c +++ b/net/uip/uip_tcpseqno.c @@ -2,7 +2,7 @@ * net/uip/uip_tcpseqno.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Large parts of this file were leveraged from uIP logic: * diff --git a/net/uip/uip_tcptimer.c b/net/uip/uip_tcptimer.c index c95376ab0c01d093c42052cba15eb82294344ed7..a0772136e885557415aab9bcecbba4ea128ecff4 100644 --- a/net/uip/uip_tcptimer.c +++ b/net/uip/uip_tcptimer.c @@ -3,7 +3,7 @@ * Poll for the availability of TCP TX data * * Copyright (C) 2007-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Adapted for NuttX from logic in uIP which also has a BSD-like license: * diff --git a/net/uip/uip_udpcallback.c b/net/uip/uip_udpcallback.c index f00c5e0f81dea3b4fcbf8afea2f75b5906f1f2eb..ef4b36e4954bd231065b0fc4b95aee0f474732a6 100644 --- a/net/uip/uip_udpcallback.c +++ b/net/uip/uip_udpcallback.c @@ -2,7 +2,7 @@ * net/uip/uip_udpcallback.c * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/net/uip/uip_udpinput.c b/net/uip/uip_udpinput.c index 456c34799b1213361c2751538aab8b8a4e110ddb..fa7bf8c41c484dcf29bf8855db62355fa2d789a6 100644 --- a/net/uip/uip_udpinput.c +++ b/net/uip/uip_udpinput.c @@ -3,7 +3,7 @@ * Handling incoming UDP input * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Adapted for NuttX from logic in uIP which also has a BSD-like license: * diff --git a/net/uip/uip_udppoll.c b/net/uip/uip_udppoll.c index 984566ed46e84582ea4a553df63d83343bc72c93..05c2508bca65a1aa87ec9e91f064e811df2d0331 100644 --- a/net/uip/uip_udppoll.c +++ b/net/uip/uip_udppoll.c @@ -3,7 +3,7 @@ * Poll for the availability of UDP TX data * * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Adapted for NuttX from logic in uIP which also has a BSD-like license: * diff --git a/net/uip/uip_udpsend.c b/net/uip/uip_udpsend.c index 1dc33bbd180747f4128851b0388c48e3e16ce131..9ba8ec8f5661b84bf21213e9b76997a5c16eb827 100644 --- a/net/uip/uip_udpsend.c +++ b/net/uip/uip_udpsend.c @@ -2,7 +2,7 @@ * net/uip/uip_udpsend.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Adapted for NuttX from logic in uIP which also has a BSD-like license: * diff --git a/syscall/Makefile b/syscall/Makefile index 7ef1a46295b7b798d569a546838e4b0f6d129d5e..88365759d1641eb4e9560908534f9826bb6da248 100644 --- a/syscall/Makefile +++ b/syscall/Makefile @@ -2,7 +2,7 @@ # syscall/Makefile # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/syscall/proxies/Make.defs b/syscall/proxies/Make.defs index abd6c0102624131e636ac4432f085c0878ccc622..a14e3562e12441f2742c53c8fcd13ca075f022ca 100644 --- a/syscall/proxies/Make.defs +++ b/syscall/proxies/Make.defs @@ -2,7 +2,7 @@ # syscall/proxies/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/syscall/stub_lookup.h b/syscall/stub_lookup.h index 9b4a928144b1cfad1f01449dfa24c5d69e1a254b..1c749ee621dc62981d509430bb550de8e79df604 100644 --- a/syscall/stub_lookup.h +++ b/syscall/stub_lookup.h @@ -2,7 +2,7 @@ * syscall/stub_lookup.h * * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/syscall/stubs/Make.defs b/syscall/stubs/Make.defs index 10d10c08a2d53c4ee3d487d31f6cd9d96760e79b..0f40052c0a3425d21ff55d3c493154a0354c68ad 100644 --- a/syscall/stubs/Make.defs +++ b/syscall/stubs/Make.defs @@ -2,7 +2,7 @@ # syscall/stubs/Make.defs # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/tools/unlink.sh b/tools/unlink.sh index 47079f08522e6fbe031923784881def2aaf2626f..485db36917ae41d8e096e82db54b7862759b873f 100755 --- a/tools/unlink.sh +++ b/tools/unlink.sh @@ -3,7 +3,7 @@ # tools/unlink.sh # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/tools/version.sh b/tools/version.sh index 7cad7ee03274433d22dbd7da227b7389c1425f3a..d15adb186c74753202e5e8df1a4c715d8f7f372e 100755 --- a/tools/version.sh +++ b/tools/version.sh @@ -2,7 +2,7 @@ # version.sh # # Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/tools/winlink.sh b/tools/winlink.sh index c081cee35f1badabeb33311c9f730752a2e63353..f79eda2bd75626875e4c009692851766865e4ca6 100755 --- a/tools/winlink.sh +++ b/tools/winlink.sh @@ -3,7 +3,7 @@ # tools/winlink.sh # # Copyright (C) 2008 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions diff --git a/tools/zipme.sh b/tools/zipme.sh index a10beaaab43f947e122c193d8b69057897cf190f..a8cd160ab3cfb68d2a0180274629bc7303310d42 100755 --- a/tools/zipme.sh +++ b/tools/zipme.sh @@ -2,7 +2,7 @@ # zipme.sh # # Copyright (C) 2007-2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt +# Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions