@@ -4872,7 +4986,7 @@ Mem: 29232 5920 23312 23312
STATUS:
The basic port is code complete and fully verified in NuttX 6.13.
Available configurations include the NuttShell (NSH - see the NSH User Guide).
- Refer to the NuttX board README file for further information.
+ Refer to the NuttX board README file for further information.
No workaround is known at this time. This is a show stopper for M16C.
- Refer to the NuttX board README file for further information.
+ Refer to the NuttX board README file for further information.
@@ -5120,7 +5234,7 @@ BFD_ASSERT (*plt_offset != (bfd_vma) -1);
The initial release of support for the z16f was made available in NuttX version 0.3.7.
A working NuttShell (NSH) configuration as added in NuttX-6.33 (although a patch is required to work around an issue with a ZDS-II 5.0.1 tool problem).
An ESPI driver was added in NuttX-7.2.
- Refer to the NuttX board
+ The NuttX implementation does not support any special formatting characters beyond those supported by printf().
+
+
+ REVISIT: Per POSIX the SYSLOG mask should be a per-process value but in NuttX, the scope of the mask is dependent on the nature of the build:
+
+
+ In NuttX, syslog output is really synonymous to debug output and, herefore, the debugging interface macros defined in the header file
+ include/debug.h are also syslogging interfaces. Those macros are simply wrappers around syslog(). The debugging interfaces differ from the syslog interfaces in that:
+
+
+ Each debug macro has a base name that represents the priority and a prefix that represents the sub-system. Each macro is individually initialized by both priority and sub-system. For example, uerr() is the macro used for error level messages from the USB subsystem and is enabled with CONFIG_DEBUG_USB_ERROR.
+
+
+ The base debug macro names, their priority, and configuration variable are summarized below:
+
+
+ In the NuttX SYSLOG implementation, the underlying device logic the supports the SYSLOG output is referred to as a SYSLOG channel. Each SYSLOG channel is represented by an interface defined in include/nuttx/syslog/syslog.h:
+
+
+ The initial, default SYSLOG channel is established with statically initialized global variables so that some level of SYSLOG output may be available immediately upon reset. This initialized data is in the file drivers/syslog/syslog_channel.c. The initial SYSLOG capability is determined by the selected SYSLOG channel:
+
+
+ Different types of SYSLOG devices have different OS initialization
+ requirements. Some are available immediately at reset, some are available
+ after some basic OS initialization, and some only after OS is fully
+ initialized. In order to satisfy these different initialization
+ requirements, syslog_initialize() is called twice from the boot-up logic:
+
+
+ There are other types of SYSLOG channel devices that may require even further initialization. For example, the file SYSLOG channel (described below) cannot be initialized until the necessary file systems have been mounted.
+
+
+
+ As a general statement, SYSLOG output only supports //normal// output from NuttX tasks. However, for debugging purposes, it is also useful to get SYSLOG output from interrupt level logic. In an embedded system, that is often where the most critical operations are performed.
+
+
+ There are three conditions under which SYSLOG output generated from interrupt level processing can a included the SYSLOG output stream:
+
+
+ The typical SYSLOG device is the system console. If you are using a serial console, for example, then the SYSLOG output will appear on that serial port.
+
+
+ Interrupt level SYSLOG output will be lost unless: (1) the interrupt buffer
+ is enabled to support serialization, or (2) a serial console is used and
+ up_putc() is supported.
+
+
+ Files can also be used as the sink for SYSLOG output. There is, however, a very fundamental difference in using a file as opposed the system console, a RAM buffer, or character device: You must first mount the file system that supports the SYSLOG file. That difference means that the file SYSLOG channel cannot be supported during the boot-up phase but can be instantiated later when board level logic configures the application environment, including mounting of the file systems.
+
+
+ File SYSLOG channels differ from other SYSLOG channels in that they cannot be established until after fully booting and mounting the target file system. This function would need to be called from board-specific bring-up logic AFTER mounting the file system containing devpath.
+
+
+ NOTE interrupt level SYSLOG output will be lost in this case unless the interrupt buffer is used.
+
+
+
+ The RAMLOG is a standalone feature that can be used to buffer any
+ character data in memory. There are, however, special configurations
+ that can be used to configure the RAMLOG as a SYSLOG channel. The RAMLOG
+ functionality is described in a more general way in the following
+ paragraphs.
+
+
+
+ The RAM logging driver can also accept debug output data from interrupt handler with no special serialization buffering. As an added benefit, the RAM logging driver is much less invasive. Since no actual I/O is performed with the debug output is generated, the RAM logger tends to be much faster and will interfere much less when used with time critical drivers.
+
+
+ The RAM logging driver is similar to a pipe in that it saves the debugging output in a circular buffer in RAM. It differs from a pipe in numerous details as needed to support logging.
+
+
+ When the RAMLOG (with SYSLOG) is enabled, a new NuttShell (NSH) command will appear: dmesg. The dmesg command will dump the contents of the circular buffer to the console (and also clear the circular buffer).
+
+
+
diff --git a/Documentation/UsbTrace.html b/Documentation/UsbTrace.html
index a6800983d5bcb272c099f6bfba24de374b9a707a..25c8736b7b3a45d131cb0725eac59c2811b55df5 100644
--- a/Documentation/UsbTrace.html
+++ b/Documentation/UsbTrace.html
@@ -396,7 +396,7 @@ static int pl2303_setup(FAR struct uart_dev_s *dev)
- CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y
- CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y
- CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y
- CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y
- CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y
+ CONFIG_USBMONITOR_TRACEINIT=y
+ CONFIG_USBMONITOR_TRACECLASS=y
+ CONFIG_USBMONITOR_TRACETRANSFERS=y
+ CONFIG_USBMONITOR_TRACECONTROLLER=y
+ CONFIG_USBMONITOR_TRACEINTERRUPTS=y
|
Selects which USB event(s) that you want to be traced.
diff --git a/FlatLibs.mk b/FlatLibs.mk
index 13dcc6c3400f0b24f52fe5bfd140265af0a8c6f3..69fe6a9fa067419996c597ec493e4273d519c0a8 100644
--- a/FlatLibs.mk
+++ b/FlatLibs.mk
@@ -45,6 +45,12 @@
NUTTXLIBS = lib$(DELIM)libsched$(LIBEXT)
USERLIBS =
+# Driver support. Generally depends on file descriptor support but there
+# are some components in the drivers directory that are needed even if file
+# descriptors are not supported.
+
+NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
+
# Add libraries for board support
NUTTXLIBS += lib$(DELIM)libconfigs$(LIBEXT)
@@ -89,11 +95,8 @@ ifeq ($(CONFIG_NFILE_DESCRIPTORS),0)
ifneq ($(CONFIG_NSOCKET_DESCRIPTORS),0)
NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT)
endif
-ifeq ($(CONFIG_NET),y)
-NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
-endif
else
-NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libdrivers$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
+NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
endif
# Add libraries for the NX graphics sub-system
diff --git a/Kconfig b/Kconfig
index 7e9ae4eed3c74e08804073f6646e01a3e8084edf..bf1f1c7b4b31ee0a3c8e9cbb0c9077289dbc4d91 100644
--- a/Kconfig
+++ b/Kconfig
@@ -339,10 +339,10 @@ config ARCH_MATH_H
default n
---help---
There is also a re-directing version of math.h in the source tree.
- However, it resides out-of-the-way at include/nuttx/math.h because it
+ However, it resides out-of-the-way at include/nuttx/lib/math.h because it
conflicts too often with the system math.h. If ARCH_MATH_H=y is
defined, however, the top-level makefile will copy the redirecting
- math.h header file from include/nuttx/math.h to include/math.h. math.h
+ math.h header file from include/nuttx/lib/math.h to include/math.h. math.h
will then include the architecture-specific version of math.h that you
must provide at nuttx/arch/>architecture/include/stdarg.h
If ARCH_STDARG_H=y is defined, the top-level makefile will copy the
- re-directing stdarg.h header file from include/nuttx/stdarg.h to
+ re-directing stdarg.h header file from include/nuttx/lib/stdarg.h to
include/stdarg.h. So for the architectures that cannot use their
toolchain's stdarg.h file, they can use this alternative by defining
ARCH_STDARG_H=y and providing. If ARCH_STDARG_H, is not defined, then
@@ -395,9 +395,14 @@ endmenu # Customize Header Files
menu "Debug Options"
+config DEBUG_ALERT
+ bool
+ default n
+
config DEBUG_FEATURES
bool "Enable Debug Features"
default n
+ select DEBUG_ALERT
---help---
Enables built-in debug features. Selecting this option will (1) Enable
debug assertions in the code, (2) enable extended parameter testing in
@@ -1362,7 +1367,6 @@ endif # DEBUG_SPI
config DEBUG_TIMER
bool "Timer Debug Features"
default n
- depends on TIMER
---help---
Enable timer debug features.
diff --git a/KernelLibs.mk b/KernelLibs.mk
index a7888d714dceec8e15641311fc2fe46a6886d748..719430b6c9be4d435f414d62813dd4b87022f35b 100644
--- a/KernelLibs.mk
+++ b/KernelLibs.mk
@@ -45,6 +45,12 @@
NUTTXLIBS = lib$(DELIM)libsched$(LIBEXT)
USERLIBS =
+# Driver support. Generally depends on file descriptor support but there
+# are some components in the drivers directory that are needed even if file
+# descriptors are not supported.
+
+NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
+
# Add libraries for board support
NUTTXLIBS += lib$(DELIM)libconfigs$(LIBEXT)
@@ -83,11 +89,8 @@ ifeq ($(CONFIG_NFILE_DESCRIPTORS),0)
ifneq ($(CONFIG_NSOCKET_DESCRIPTORS),0)
NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT)
endif
-ifeq ($(CONFIG_NET),y)
-NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
-endif
else
-NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libdrivers$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
+NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
endif
# Add libraries for the NX graphics sub-system
diff --git a/Makefile.unix b/Makefile.unix
index 022c7962169728566385ea3666e8b05b01815b47..d1ee224a67ea74a81053268d7437fee03d7b0351 100644
--- a/Makefile.unix
+++ b/Makefile.unix
@@ -181,18 +181,18 @@ endif
BIN = nuttx$(EXEEXT)
all: $(BIN)
-.PHONY: context clean_context check_context export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean
+.PHONY: dirlinks context clean_context check_context export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean
-# Target used to copy include/nuttx/math.h. If CONFIG_ARCH_MATH_H is
+# Target used to copy include/nuttx/lib/math.h. If CONFIG_ARCH_MATH_H is
# defined, then there is an architecture specific math.h header file
# that will be included indirectly from include/math.h. But first, we
# have to copy math.h from include/nuttx/. to include/. Logic within
-# include/nuttx/math.h will hand the redirection to the architecture-
+# include/nuttx/lib/math.h will hand the redirection to the architecture-
# specific math.h header file.
#
# If the CONFIG_LIBM is defined, the Rhombus libm will be built at libc/math.
# Definitions and prototypes for the Rhombus libm are also contained in
-# include/nuttx/math.h and so the file must also be copied in that case.
+# include/nuttx/lib/math.h and so the file must also be copied in that case.
#
# If neither CONFIG_ARCH_MATH_H nor CONFIG_LIBM is defined, then no math.h
# header file will be provided. You would want that behavior if (1) you
@@ -208,8 +208,8 @@ endif
endif
ifeq ($(NEED_MATH_H),y)
-include/math.h: include/nuttx/math.h
- $(Q) cp -f include/nuttx/math.h include/math.h
+include/math.h: include/nuttx/lib/math.h
+ $(Q) cp -f include/nuttx/lib/math.h include/math.h
else
include/math.h:
endif
@@ -221,20 +221,20 @@ endif
# the settings in this float.h are actually correct for your platform!
ifeq ($(CONFIG_ARCH_FLOAT_H),y)
-include/float.h: include/nuttx/float.h
- $(Q) cp -f include/nuttx/float.h include/float.h
+include/float.h: include/nuttx/lib/float.h
+ $(Q) cp -f include/nuttx/lib/float.h include/float.h
else
include/float.h:
endif
-# Target used to copy include/nuttx/stdarg.h. If CONFIG_ARCH_STDARG_H is
+# Target used to copy include/nuttx/lib/stdarg.h. If CONFIG_ARCH_STDARG_H is
# defined, then there is an architecture specific stdarg.h header file
-# that will be included indirectly from include/stdarg.h. But first, we
+# that will be included indirectly from include/lib/stdarg.h. But first, we
# have to copy stdarg.h from include/nuttx/. to include/.
ifeq ($(CONFIG_ARCH_STDARG_H),y)
-include/stdarg.h: include/nuttx/stdarg.h
- $(Q) cp -f include/nuttx/stdarg.h include/stdarg.h
+include/stdarg.h: include/nuttx/lib/stdarg.h
+ $(Q) cp -f include/nuttx/lib/stdarg.h include/stdarg.h
else
include/stdarg.h:
endif
@@ -280,16 +280,6 @@ tools/cnvwindeps$(HOSTEXEEXT):
# setting up symbolic links with 'generic' directory names to specific,
# configured directories.
#
-# Link the apps/include directory to include/apps
-
-include/apps: Make.defs
-ifneq ($(APPDIR),)
- @echo "LN: include/apps to $(APPDIR)/include"
- $(Q) if [ -d $(TOPDIR)/$(APPDIR)/include ]; then \
- $(DIRLINK) $(TOPDIR)/$(APPDIR)/include include/apps; \
- fi
-endif
-
# Link the arch//include directory to include/arch
include/arch: Make.defs
@@ -324,7 +314,9 @@ ifneq ($(CONFIG_ARCH_CHIP),)
$(Q) $(DIRLINK) $(TOPDIR)/$(ARCH_INC)/$(CONFIG_ARCH_CHIP) include/arch/chip
endif
-dirlinks: include/arch include/arch/board include/arch/chip $(ARCH_SRC)/board $(ARCH_SRC)/chip include/apps
+dirlinks: include/arch include/arch/board include/arch/chip $(ARCH_SRC)/board $(ARCH_SRC)/chip
+ $(Q) $(MAKE) -C configs dirlinks TOPDIR="$(TOPDIR)"
+ $(Q) $(MAKE) -C $(CONFIG_APPS_DIR) dirlinks TOPDIR="$(TOPDIR)"
# context
#
@@ -344,6 +336,7 @@ context: check_context include/nuttx/config.h include/nuttx/version.h include/ma
# and symbolic links created by the context target.
clean_context:
+ $(Q) $(MAKE) -C configs TOPDIR="$(TOPDIR)" clean_context
$(call DELFILE, include/nuttx/config.h)
$(call DELFILE, include/nuttx/version.h)
$(call DELFILE, include/math.h)
@@ -353,7 +346,6 @@ clean_context:
$(Q) $(DIRUNLINK) include/arch
$(Q) $(DIRUNLINK) $(ARCH_SRC)/board
$(Q) $(DIRUNLINK) $(ARCH_SRC)/chip
- $(Q) $(DIRUNLINK) include/apps
# check_context
#
@@ -480,24 +472,36 @@ pass2dep: context tools/mkdeps$(HOSTEXEEXT) tools/cnvwindeps$(HOSTEXEEXT)
# location: http://ymorin.is-a-geek.org/projects/kconfig-frontends. See
# README.txt file in the NuttX tools GIT repository for additional information.
-config: apps_preconfig
+do_config: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf Kconfig
-oldconfig: apps_preconfig
+config: do_config clean_context
+
+do_oldconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf --oldconfig Kconfig
-olddefconfig: apps_preconfig
+oldconfig: do_oldconfig clean_context
+
+do_olddefconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf --olddefconfig Kconfig
-menuconfig: apps_preconfig
+olddefconfig: do_olddefconfig clean_context
+
+do_menuconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-mconf Kconfig
-qconfig: apps_preconfig
+menuconfig: do_menuconfig clean_context
+
+do_qconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-qconf Kconfig
-gconfig: apps_preconfig
+qconfig: do_qconfig clean_context
+
+gconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-gconf Kconfig
+gconfig: do_gconfig clean_context
+
# export
#
# The export target will package the NuttX libraries and header files into
diff --git a/Makefile.win b/Makefile.win
index 5a71a42122b76d51fa96d2422549c6f45480c04a..b15052f16cad8716eeb4dc86e171d183b6f8ea1c 100644
--- a/Makefile.win
+++ b/Makefile.win
@@ -174,7 +174,7 @@ endif
BIN = nuttx$(EXEEXT)
all: $(BIN)
-.PHONY: context clean_context check_context configenv config oldconfig menuconfig export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean
+.PHONY: dirlinks context clean_context check_context configenv config oldconfig menuconfig export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean
# Target used to copy include\nuttx\math.h. If CONFIG_ARCH_MATH_H is
# defined, then there is an architecture specific math.h header file
@@ -275,19 +275,6 @@ tools\mkdeps$(HOSTEXEEXT):
# setting up symbolic links with 'generic' directory names to specific,
# configured directories.
#
-# Link the apps\include directory to include\apps
-
-include\apps: Make.defs
-ifneq ($(APPDIR),)
- @echo LN: include\apps $(APPDIR)\include
-ifeq ($(CONFIG_WINDOWS_MKLINK),y)
- $(Q) /user:administrator mklink /d include\apps $(APPDIR)\include
-else
- $(Q) xcopy $(APPDIR)\include include\apps /c /q /s /e /y /i
- $(Q) echo FAKELNK > include\apps\.fakelnk
-endif
-endif
-
# Link the arch\\include directory to include\arch
include\arch: Make.defs
@@ -347,7 +334,9 @@ else
endif
endif
-dirlinks: include\arch include\arch\board include\arch\chip $(ARCH_SRC)\board $(ARCH_SRC)\chip include\apps
+dirlinks: include\arch include\arch\board include\arch\chip $(ARCH_SRC)\board $(ARCH_SRC)\chip
+ $(Q) $(MAKE) -C configs dirlinks TOPDIR="$(TOPDIR)"
+ $(Q) $(MAKE) -C $(CONFIG_APPS_DIR) dirlinks TOPDIR="$(TOPDIR)"
# context
#
@@ -374,7 +363,6 @@ clean_context:
$(call DELDIR, include\arch)
$(call DELDIR, $(ARCH_SRC)\board)
$(call DELDIR, $(ARCH_SRC)\chip)
- $(call DELDIR, include\apps)
# check_context
#
@@ -480,18 +468,26 @@ pass2dep: context tools\mkdeps$(HOSTEXEEXT)
# location: http://ymorin.is-a-geek.org/projects/kconfig-frontends. See
# misc\tools\README.txt for additional information.
-config: apps_preconfig
+do_config: dirlinks apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf Kconfig
-oldconfig: apps_preconfig
+config: do_config clean_context
+
+do_oldconfig: dirlinks apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf --oldconfig Kconfig
-olddefconfig: apps_preconfig
+oldconfig: do_oldconfig clean_context
+
+do_olddefconfig: dirlinks apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf --olddefconfig Kconfig
-menuconfig: configenv apps_preconfig
+olddefconfig: do_olddefconfig clean_context
+
+do_menuconfig: dirlinks configenv apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-mconf Kconfig
+menuconfig: do_menuconfig clean_context
+
# export
#
# The export target will package the NuttX libraries and header files into
diff --git a/ProtectedLibs.mk b/ProtectedLibs.mk
index 70185eacf47162a4f850a36919d398786f3f97b2..4f2e2c6072d35fc34030967de75fa7fe93434c5d 100644
--- a/ProtectedLibs.mk
+++ b/ProtectedLibs.mk
@@ -45,6 +45,12 @@
NUTTXLIBS = lib$(DELIM)libsched$(LIBEXT)
USERLIBS =
+# Driver support. Generally depends on file descriptor support but there
+# are some components in the drivers directory that are needed even if file
+# descriptors are not supported.
+
+NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
+
# Add libraries for board support
NUTTXLIBS += lib$(DELIM)libconfigs$(LIBEXT)
@@ -89,11 +95,8 @@ ifeq ($(CONFIG_NFILE_DESCRIPTORS),0)
ifneq ($(CONFIG_NSOCKET_DESCRIPTORS),0)
NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT)
endif
-ifeq ($(CONFIG_NET),y)
-NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
-endif
else
-NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libdrivers$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
+NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
endif
# Add libraries for the NX graphics sub-system
diff --git a/README.txt b/README.txt
index b3cb19a407d1186cd21c99a0e3c7c5ec67d60efc..599200988d25ce7b174f29ee4544597fccca1502 100644
--- a/README.txt
+++ b/README.txt
@@ -15,6 +15,7 @@ README
- NuttX Configuration Tool
- Finding Selections in the Configuration Menus
- Reveal Hidden Configuration Options
+ - Make Sure that You on on the Right Platform
- Comparing Two Configurations
- Incompatibilities with Older Configurations
- NuttX Configuration Tool under DOS
@@ -321,13 +322,13 @@ Notes about Header Files
If you have a custom, architecture specific math.h header file, then
that header file should be placed at arch//include/math.h. There
- is a stub math.h header file located at include/nuttx/math.h. This stub
+ is a stub math.h header file located at include/nuttx/lib/math.h. This stub
header file can be used to "redirect" the inclusion to an architecture-
specific math.h header file. If you add an architecture specific math.h
header file then you should also define CONFIG_ARCH_MATH_H=y in your
NuttX Configuration file. If CONFIG_ARCH_MATH_H is selected, then the
top-level Makefile will copy the stub math.h header file from
- include/nuttx/math.h to include/math.h where it will become the system
+ include/nuttx/lib/math.h to include/math.h where it will become the system
math.h header file. The stub math.h header file does nothing other
than to include that architecture-specific math.h header file as the
system math.h header file.
@@ -576,6 +577,38 @@ Reveal Hidden Configuration Options
cannot be selected and has no value). About all you do is to select
the option to see what the dependencies are.
+Make Sure that You on on the Right Platform
+-------------------------------------------
+
+ Saved configurations may run on Linux, Cygwin (32- or 64-bit), or other
+ platforms. The platform characteristics can be changed use 'make
+ menuconfig'. Sometimes this can be confusing due to the differences
+ between the platforms. Enter sethost.sh
+
+ sethost.sh is a simple script that changes a configuration to your
+ host platform. This can greatly simplify life if you use many different
+ configurations. For example, if you are running on Linux and you
+ configure like this:
+
+ $ cd tools
+ $ ./configure.sh board/configuration
+ $ cd ..
+
+ The you can use the following command to both (1) make sure that the
+ configuration is up to date, AND (2) the configuration is set up
+ correctly for Linux:
+
+ $ tools/sethost.sh -l
+
+ Or, if you are on a Windows/Cygwin 64-bit platform:
+
+ $ tools/sethost.sh -w
+
+ Other options are available from the help option built into the
+ script. You can see all options with:
+
+ $ tools/sethost.sh -h
+
Comparing Two Configurations
----------------------------
@@ -948,9 +981,13 @@ Native Windows Build
--------------------
The beginnings of a Windows native build are in place but still not often
- used as of this writing. The windows native build logic initiated
- if CONFIG_WINDOWS_NATIVE=y is defined in the NuttX configuration file:
+ used as of this writing. The build was functional but because of lack of
+ use may find some issues to be resolved with this build configuration.
+ The windows native build logic initiated if CONFIG_WINDOWS_NATIVE=y is
+ defined in the NuttX configuration file:
+
+
This build:
- Uses all Windows style paths
@@ -1213,7 +1250,7 @@ nuttx/
| |- arm/
| | `- src
| | `- lpc214x/README.txt
- | |- sh/
+ | |- renesas/
| | |- include/
| | | `-README.txt
| | |- src/
@@ -1283,6 +1320,8 @@ nuttx/
| | `- README.txt
| |- fire-stm32v2/
| | `- README.txt
+ | |- freedom-k64f/
+ | | `- README.txt
| |- freedom-kl25z/
| | `- README.txt
| |- freedom-kl26z/
@@ -1325,8 +1364,6 @@ nuttx/
| | `- README.txt
| |- mirtoo/
| | `- README.txt
- | |- mt-db-x3/
- | | `- README.txt
| |- moteino-mega/
| | `- README.txt
| |- mx1ads/
@@ -1444,6 +1481,8 @@ nuttx/
| | `- README.txt
| |- stm32f746g-disco/
| | `- README.txt
+ | |- stm32l476-mdk/
+ | | `- README.txt
| |- stm32l476vg-disco/
| | `- README.txt
| |- stm32ldiscovery/
@@ -1524,6 +1563,8 @@ nuttx/
|- lib/
| `- README.txt
|- libc/
+ | |- zoneinfo
+ | | `- README.txt
| `- README.txt
|- libnx/
| `- README.txt
@@ -1590,9 +1631,7 @@ apps/
| | `- README.txt
| |- usbmsc
| | `- README.txt
- | |- zmodem
- | | `- README.txt
- | `- zoneinfo
+ | `- zmodem
| `- README.txt
`- README.txt
diff --git a/ReleaseNotes b/ReleaseNotes
index c760fca73723f71cf5a0ac0ae51f45a043ffefad..66e1c712c1e652d5be08c0d5a46a525ef27ccb0a 100644
--- a/ReleaseNotes
+++ b/ReleaseNotes
@@ -2570,7 +2570,7 @@ New features and extended functionality:
particular for a CDC/ACM with MSC USB composite driver).
Added a new RAM logging driver. This will allow debug output into
- a RAM buffer associated with a character driver at /dev/syslog.
+ a RAM buffer associated with a character driver at /dev/ramlog.
Added the new command 'dmesg' to NSH that can be used to dump the
current contents of the log. This is useful for systems that do not
have the usual serial console (for example, if you only have a
@@ -8905,25 +8905,25 @@ Additional new features and extended functionality:
This is based on the similar SAMD20 Xplained Pro board.
* Freescale/NXP KL:
-
+
- KL25Z64: Added support for the KL25Z64. The KL25Z64 is a lower
memory variant of the KL25Z128 and is used on the Teensy LC. From
Michael as SourceForge patch 50.
* Freescale/NXP KL Boards:
-
+
- Teensy-LC: Add board support for the Teensy LC board. Support is
based off the Freedom KL25Z board. LED, PWM, and UART0 have been
tested. The SPI pins are mapped correctly but have not yet been
tested. From Michael Hope as SourceForge patch 51.
* NXP LPC111x:
-
+
- LPC111x: Support for the LPC11xx family (the LPC1115 MCU in
particular). Contributed by Alan Carvalho de Assis.
* NXP LPC111x Boards:
-
+
- LPCXpresso LPC1115: Support for the LPCXpression LPC1115
board. Contributed by Alan Carvalho de Assis.
@@ -8991,7 +8991,7 @@ Additional new features and extended functionality:
* Applications: apps/system:
- - apps/system/zoneinfo: Add logic to build a ROMFS file system
+ - nuttx/zoneinfo: Add logic to build a ROMFS file system
containing the timezone data.
* Applications: apps/nshlib:
@@ -9063,7 +9063,7 @@ detailed bugfix information):
for mq_setattr() and mq_getattr(). This is necessary in protected
and kernel builds because in those cases the message queue
structure is protected and cannot be accessed directly from user
- mode code. Noted by Jouko Holopainen.
+ mode code.
* File Systems/Block Drivers/MTD:
@@ -9158,7 +9158,7 @@ detailed bugfix information):
- LPC17 USB OHCI: Correct some initialization of data structures.
When hub support is enabled, it would overwrite the end of an array
and clobber some OS data structures.
- - LPC17xx Ethernet: Review, update, and modify the Ethernet driver so
+ - LPC17xx Ethernet: Review, update, and modify the Ethernet driver so
that it works better with CONFIG_NET_NOINTS=y. Also, update all
LPC17xx networking configurations so that they have
CONFIG_NET_NOTINTS=y selected.
@@ -9585,7 +9585,7 @@ detailed bugfix information):
* ARMv7-A:
- Cortex-A5 vfork(): Fix a Cortex-A compilation error when system
- calls are enabled in modes other than CONFIG_BUILD_KERNEL.
+ calls are enabled in modes other than CONFIG_BUILD_KERNEL.
* Atmel SAMA5 Drivers:
@@ -10099,7 +10099,7 @@ Additional new features and extended functionality:
- ps command: The 'ps' command now uses /proc// to obtain task
status information. A consequence of this is that you cannot use
the 'ps' command if the procfs is not enabled and mounted at /proc.
-
+
* Applications: apps/system:
- apps/system/hexed: Port the hexed command line hexadeciamal editor
@@ -10144,7 +10144,7 @@ detailed bugfix information):
* Graphics/Graphic Drivers:
- - ILI9432: Fixed errors in orientation. Portrait, RPortrait, and
+ - ILI9432: Fixed errors in orientation. Portrait, RPortrait, and
Landscript should work correly now. They were displayed mirrored.
From Marco Krahl.
@@ -10321,7 +10321,7 @@ Additional new features and extended functionality:
pointer indicates that the referenced object may reside either in
flash or in RAM. The compiler automatically makes 32-bit pointer
with flag indicating whether referenced object is in flash or RAM
- and generates code to access either in run-time. Thus, any function
+ and generates code to access either in run-time. Thus, any function
hat accepts __memx object can transparently work with RAM and flash
objects.
For platforms with a Harvard architecture and a very small RAM like
@@ -10350,7 +10350,7 @@ Additional new features and extended functionality:
dependencies generated by a Windows compiler so that they can be
used with the Cygwin make.
- tools/mkwindeps.sh: A script that coordinates use of cnvwindeps.exe.
- Dependencies now work on the Cygwin platform when using a Windows
+ Dependencies now work on the Cygwin platform when using a Windows
ative toolchain.
* Applications: NSH
@@ -10516,7 +10516,7 @@ Additional new features and extended functionality:
implemented via ioctl calls. However, it does not yet implement
the standard ADC interface. From Alexander Entinger.
- U-Blox Modem: Add an upper half driver for the U-Blox Modem. From
- Vladimir Komendantskiy.
+ Vladimir Komendantskiy.
- I2C: Add an I2C, "upper half", character drivers to support raw I2C
data transfers for test applications.
- RGB LED: Add a driver to manage a RGB LED via PWM. From Alan
@@ -10857,7 +10857,7 @@ Additional new features and extended functionality:
Neil Hancock.
- STM32 L4 QSPI: Add a QSPI driver with DMA support and (optional
memory mapped mode support. From Dave ziggurat29).
- - STM32, STM32 L4, and STM32 F7 Serial: Add support for compliant
+ - STM32, STM32 L4, and STM32 F7 Serial: Add support for compliant
SD-style breaks. From David Sidrane.
- STM32 L4 CAN: Add CAN support for STM32L4. From Sebastien Lorquet.
- STM32 1-Wire: Add support for a custom 1-wire driver. The serial
@@ -11079,3 +11079,699 @@ detailed bugfix information):
- Several Makefiles: Add .PHONY definitions to prevent 'clean up to date'
message weirdness when 'make clean' is done with no .config or
Make.defs file.
+
+NuttX-7.17 Release Notes
+------------------------
+
+The 117th release of NuttX, Version 7.17, was made on July 25, 2016,
+and is available for download from the Bitbucket.org website. Note
+that release consists of two tarballs: nuttx-7.17.tar.gz and
+apps-7.17.tar.gz. These are available from:
+
+ https://bitbucket.org/nuttx/nuttx/downloads
+ https://bitbucket.org/nuttx/apps/downloads
+
+Both may be needed (see the top-level nuttx/README.txt file for build
+information).
+
+Additional new features and extended functionality:
+
+ * File System and Block and MTD Drivers:
+
+ - drivers/mtd: Add a driver of IS25xP SPI flash devices. Based on
+ sst25xx driver. From Marten Svanfeldt.
+
+ * Networking and Network Drivers:
+
+ - Break out internal interface psock_ioctl().
+
+ * Common Device Drivers:
+
+ - PTYs: Added support for pseduo-terminals: Device drivers that can be
+ used for communications between tasks (usually with re-directed I/O).
+ Based on existing pipe logic.
+ - Button upper half driver: Added support for poll().
+ - CAN: Add support for poll. From Paul Alexander Patience.
+ - GPIO: Add support for a simple GPIO driver. It supports only pre-
+ configured input, output, and interrupting pins with basic input and
+ output operations. Interrupt events can lead to notification via a
+ signal.
+ - I/O Expander: Shadow-Mode: The output- and configuration registers of
+ the IO-Expander are held in the microcontrollers memory and only
+ written to the IO-Expander. This reduces bus traffic and is more
+ error-proof than the normal read-modify-write operation. Retry Mode:
+ If enabled and an error occurs while writing to the IO-Expander the
+ current transmission is automatically repeated once. From Michael
+ Spahlinger.
+ - Pipes/FIFOs: Add support to allocating different sizes for pipe and
+ fifo buffers. Adds mkfifo2() and pipe2() which are just like mkfifo()
+ and pipe(), but allow control of the size of the underlying, in-memory
+ circular buffer. Move pipe() and mkpipe() to the C library, they are
+ no longer core OS interfaces. Capability currenty used only by PTY
+ logic to support, configurable, smaller buffers for PTYs.
+
+ * SYSLOG/Debug Output:
+
+ - SYSLOG: Consolidated all SYSLOG logic in drivers/syslog. Added an
+ abstraction layer that supports: (1) redirection of SYSLOG outpout.
+ This is usually so that you can boot with one SYSLOG output but
+ transition to another SYSLOG output when the OS has initialialized,
+ (2) adds common serialization of interrupt output as a configuration
+ option. Without this configuration setting, interrupt level output
+ will be asynchronous. And (3) vsyslog is now a system call and is
+ usable with other-than-FLAT builds.
+ - SYSLOG: syslog() will now automatically redirect output to
+ lowsyslog() if called from an interrupt handler.
+ - Extended SYSLOG logic so that we can send SYSLOG output to a file.
+ - SYSLOG character device channel will now expand LF to CR-LF.
+ Controllable with a configuration option.
+ - Add a SYSLOG character device that can be used to re-direct output
+ to the SYSLOG channel (Not be be confused the the SYSLGO output to a
+ character device).
+ - Debug features are now enabled separately from debug output.
+ (1) CONFIG_DEBUG is gone. It is replaced with CONFIG_DEBUG_FEATURES.
+ (2) The macros dbg() and vdbg() have renamed as _err() and _info(),
+ respectively. This also applies to all of the variants as well,
+ XXdbg() and XXvdbg(). (3) Add a new debug level, _warn() (and
+ all variants XXwarn(), XXvwarn(), etc.). (4) Debug assertions can
+ now be enabled separately from debug output. (5) You can now enable
+ subsystem/device driver debug output at different output levels. For
+ example, CONFIG_DEBUG_FS no longer enables file system debug output
+ It enables general file system debug logic and enables selection of
+ CONFIG_DEBUG_FS_ERROR, CONFIG_DEBUG_FS_WARN, and CONFIG_DEBUG_FS_INFO.
+ - Since the SYSLOG layer now automatically handles low-level vs.
+ high-level output, the low-level (ll) variants of the debug macros
+ were eliminated.
+ - Reviewed all uses of *err(). These macro family should indicate
+ only error conditions. Convert *err() to either *info() or add
+ ERROR:, depending on if an error is reported.
+ - _alert(): New debug macro: _alert(). This is high priority,
+ unconditional output and is used to simplify and standardize crash
+ error reporting.
+ - Many CONFIG_DEBUG_* options did not have matching macros defined in
+ include/debug.h. Rather, there were various definitions scattered
+ throughout the sourse tree. These were collected together and
+ centralized with single macro definitions in include/debug.h
+
+ * Simulation Platform:
+
+ - Added the simulated QSPI (N25Q) flash to the simulation and extened
+ flash simulation capabilities to run with MTD drivers based on config
+ options (currently m25p, sst26 and w25). From Ken Pettit.
+
+ * Atmel SAMV7 Drivers:
+
+ - SPI: SPI-Freq. 40MHz; VARSELECT; hw-features This change adds the
+ following improvements:
+
+ o Increase the allowed SPI-Frequency from 20 to 40 MHz.
+ o Correct and rename the "VARSELECT" option This option was
+ included in the code as "CONFIG_SPI_VARSELECT" but nowhere
+ defined in a Kconfig file. The change renames it to
+ "CONFIG_SAMV7_SPI_VARSELECT" and corrects the implementation
+ according the datasheet of Atmel. In short, this option
+ switches the processor from "fixed peripheral selection"
+ (single device) to "variable peripheral selection" (multiple
+ devices on the bus).
+ o Add a new Function to the interface to control the timing and
+ delays of the chip according the ChipSelect lines. This function
+ can control the delay between the assertion of the ChipSelect and
+ the first bit, between the last bit and the de-assertion of the
+ ChipSelect and between two ChipSelects. This is needed to tune
+ the transfer according the specification of the connected devices.
+ o Add three "hw-features" for the SAMV7, which controls the behavior
+ of the ChipSelect:
+ - force CS inactive after transfer: this forces a (short) de-
+ assertion of the CS after a transfer, even if more data is
+ available in time
+ - force CS active after transfer: this forces the CS to stay
+ active after a transfer, even if the chip runs out of data.
+ Btw.: this is a prerequisit to make the LASTXFER bit working
+ at all.
+ - escape LASTXFER: this suppresses the LASTXFER bit at the end
+ of the next transfer. The "escape"-Flag is reset automatically.
+
+ From Frank Benkert
+ - TWISHS: Driver improvements from Michael Spahlinger.
+ - GPIO-Driver fixed for Open-Drain Pins:
+
+ o sam_gpioread: Now the actual line level from the pin is read
+ back. This is extremely important for Open-Drain Pins, which
+ can be used bidirectionally
+ o Re-Implemented twi_reset-function and enhanced it so it can be
+ called from inside the driver (see next point)
+ o Glitch-Filter: Added a configuration option to enable the twi-
+ built-in glitch filter
+ o Added a "Single Master Mode": In EMC Testing the TWI-Bus got
+ stuck because the TWI-Master detected a Multi-Master access (but
+ there is no second master). With the option "Single Master" we
+ detect these events and automatically trigger a twi_reset. We
+ also do an automatic recovery if a slave got stuck (SDA stays
+ low).
+
+ With the above changes IC-Bus reliability in harsh environments (eg.
+ EMC) is greatly improved. The small change in the GPIO-Driver was
+ necessary because otherwise you cannot read back the correct line
+ status of Open-Drain Outputs and this is needed by the twi_reset
+ function. From Michael Spahlinger
+
+ * NXP Freescale LPC43xx Drivers:
+
+ - EMC: Extend LPC43xx EMC code to support SDRAM on a dynamic memory
+ interface. From Vytautas Lukenskas.
+
+ * NXP Freescale Kinetis:
+
+ - Kinetis K64: Add basic support for the K64 family. I leveraged the
+ changes from https://github.com/jmacintyre/nuttx-k64f and merged
+ into the existing kinetis code with a lot of changes and additions
+ (like pin multiplexing definitions).
+
+ * NXP Freescale Kinetis Drivers:
+
+ - Add a KinetisUSB device controller driver. Derived from the pic32mx
+ usb driver, which uses the same usb controller. From kfazz.
+ - Kinetis pwm support, based on the KL pwm driver. From kfazz.
+ - Kinetis Ethernet: Add support for the KSZ8081 PHY.
+ - Kinetis Ethernet: Modified Ethernet driver to try all PHY addresses
+ and then only fail if the driver cannot find a usable PHY address.
+ This means that you no longer have to specific the PHY address in
+ advance.
+ - Kinetis Ethernet: Add support for CONFIG_NET_NOINTS. The driver no
+ longer runs the networking at interrupt level but can defer interrupt
+ work to the high-priority work queue.
+
+ * NXP Freescale Kinetis Boards:
+
+ - Teensy-3.x: Add USB support and a usbnsh configuration.
+ From kfazz (2016-06).
+ - Freedom-K64F: Add support for the NXP Freedom-K64F board at 120MHz.
+ This is primarily the work of Jordan Macintyre. I leveraged this
+ code from https://github.com/jmacintyre/nuttx-k64f which was, itself,
+ a leverage from the old K60 TWR configuration. This includes
+ significant corrections (LEDs, buttons, README, etc) and extensions
+ and updates to match more recent BSPs.
+ - Freedom-K64F: Added a configuration that supports networking.
+
+ * STMicro STM32:
+
+ - STM32 F1-4: Added support for the STM32F105R. From Konstantin
+ Berezenko.
+ - STM32 F4: Added support for the STM32FF76xxx and STM32FF7xx
+ families. From David Sidrane.
+ - STM32 F1-4: Add support for Tickless mode (two timer
+ implementation). From Max Neklyudov.
+ - STM32 L4: Add support for tickless OS, and incidentally timers,
+ PWM, oneshot, free-running.... From ziggurat29.
+
+ * STMicro STM32 Drivers:
+
+ - STM32 F1-4: Add the up_getc() function to STM32 in order to support
+ the minnsh configuration. From Alan Carvalho de Assis.
+ - STM32 F7: Add SPI driver. From David Sidrane.
+ - STM32 F7: Add SPI, I2C, and ADC drivers. From Lok Tep.
+ - STM32 L4: Add ioctls to set/get CAN bit timing in stm32l4. Add
+ ioctl hooks to allow future management of can id filters. From
+ Sebastien Lorquet.
+ - STM32 L4: Add some CAN mode IOCTL calls. These will be useful for
+ device autotest when the application boots. They are redundant
+ with the CONFIG_CAN_LOOPBACK option, which can now just be
+ interpreted as a default setting. From Sebastien Lorquet.
+ - STM32 F1-4: Port STM32L4 CAN IOCTLs to STM32. From Sebastien Lorquet.
+ - STM32 L4: Implementation of loopback IOCTLs. From Sebastien
+ Lorquet.
+ - STM32 F7: Added SDMMC1 support for stm32F7 74-75. From Lok Tep.
+ - STM32 F7: Add USB support. From Lok Tep.
+ - STM32 F7: Added PWR, RTC, and BBSRAM support for stm32f7. From David
+ Sidrane.
+ - STM32 F7: Added STMF7xxx RTC. From David Sidrane.
+ - STM32 F7: Added STM32F7 DBGMCU. From David Sidrane.
+ - STM32 L4: Port support for both RX FIFOs from STM32 CAN. From Paul
+ Alexander Patience.
+
+ * STMicro STM32 Boards:
+
+ - Added a minnsh configuration for the STM32F103-Minimum board. From
+ Alan Carvalho de Assis .
+ - Added support for the Nucleo-F767ZI board. From David Sidrane.
+ - Nucleo-144/Nucleo-F767ZI: Add test for STM32 F7 SPI. From David
+ Sidrane.
+ - Nucleo-144: Added SDMMC support to Nucleo-144. From David Sidrane.
+ - Olimex STM32-E4077: Add support for Olimex STM32 E407 board. From
+ Mateusz Szafoni.
+ - Nucleo-144: Added USB OTG device to Nucleo-144. From David Sidrane.
+ - Nucleo-144: Added bbsram test to Nucleo-144. From David Sidrane.
+ - STM32F4 Disovery: add CAN support for STM32F4 Discovery. From
+ Matthias Renner.
+ - STM32F4 Disovery: added a canard configuration files. From
+ Matthias Renner.
+ - STM32F4 Discovery: Add FPU support for ostest for the STM32F4
+ Disovery platform. From David Alessio.
+ - STM32L476 Discovery: Update stm32l476 disco to include init code for
+ smartfs and nxffs for cases where those fs are included in build.
+ From ziggurat29.
+
+ * C Library/Header Files:
+
+ - include/assert.h: Check if NDEBUG is defined. From Paul Alexander
+ Patience.
+ - assert.h: Define static assert for C++ usage. From Paul Alexander
+ Patience.
+ - Add crc64 support. From Paul Alexander Patience.
+ - hex2bin: Move the portable library portion of apps/system/hex2bin
+ the C library with the OS internals. It is used in certain internal
+ boot-loader builds.
+ - Add raise().
+ - libm: This change should significantly improve the performance of
+ single precision floating point math library functions. The vast
+ majority of changes have to do with preventing the compiler from
+ needlessly promoting floats to doubles, performing the calculation
+ with doubles, only to demote the result to float. These changes only
+ affect the math lib functions that return float. From David Alessio.
+ - printf(): If there are no streams, let printf() fall back to use
+ syslog() for output.
+ - Move pipe() and mkpipe() to nuttx/libc, they are no
+ longer core OS interfaces. Capability currenty used only by PTY logi
+ to support, configurable, smaller buffers for PTYs.
+ - Move driver-related files from include/nuttx to include/nuttx/drivers.
+ Move driver related prototypes out of include/nuttx/fs/fs.h and into
+ new include/drivers/drivers.h.
+ - include /nuttx/lib: Move library-related files from include/nuttx to
+ include/nuttx/lib.
+
+ * Build/Configuration System:
+
+ - Custom Board Configuration: Add logic to support custom board
+ directories that include a Kconfig file. During the context phase
+ of the build, any Kconfig file in the custom board directory is
+ copied into configs/dummy, replacing the existing Kconfig file with
+ the target Kconfig file.
+ - Remove the includes/apps link to apps/include. It is no longer
+ used. From Sebastien Lorquet.
+
+ * Tools:
+
+ - tools/tesbuild.sh will now build NxWM configurations.
+
+ * Appplication Build/Configuration System:
+
+ - Change to the way that apps/ Kconfig files are generated in
+ order to better support reuse of the apps/ directory in NuttX
+ products. Changes include: Make the full tree use wildcards
+ make.defs, Add empty preconfig rules to 'leaf' makefiles, Use
+ directory.mk for recursive dir makefiles, Individual app kconfig
+ fixes, Recursive Kconfig autogeneration, Add kconfig files for
+ pcode and tiff, and fix a gitignore rule, From Sbastien Lorquet.
+ - apps/include directory structure reorganized. There are no longer
+ any header files in the apps/include/. directory. Rather, sub-
+ directories were added to match the partitioning of apps/ sub-
+ directories and the header files were moved into the appropriate
+ sub-directory. This change is intended to help with some changes
+ being considered by Sbastien Lorquet.
+ - Call all includes from to "bla/bla.h". From Sebastien
+ Lorquet.
+ - Add apps/include to include path in top-level Make.defs file.
+
+ * Applications: apps/nshlib:
+
+ - Make NSH net-initialization be a configuration option. From Marten
+ Svanfeld.
+ - Add NTP client initialization in NSH network startup logic. From
+ David S. Alessio .
+ - 'ps' command now prints out the stack usage if stack coloration is
+ enabled. From Frank Benkert.
+ - Allow stack usage to be disabled on constrained systems. From David
+ Sidrane.
+
+ * Applications: apps/netutils:
+
+ - NTP Client: Add retries. From David S. Alessio.
+ - NTP Client: The NTP client will now optionally use pool.ntp.org as
+ the NTP server; and reset the retry count upon success -- more robust.
+ From David Alessio.
+ - ESP8266: Add logic to set the BAUD rate. From Pierre-noel Bouteville.
+ - ESP8266: In Kconfig, select ARCH_HAVE_NET when NETUTILS_ESP8266 is
+ selected. This allows, among other things, support for network debug
+ output. From Pierre-noel Bouteville.
+
+ * Applications: apps/fsutils:
+
+ - flash_eraseall: IOCTL wrapper for MDCIO_BULKERASE command. Was in
+ nuttx/drivers/mtd. Moved to apps/fsutils because the call directly into
+ the OS was incorrect.
+
+ * Applications: apps/canutils:
+
+ - canlib: Basic CAN utility library. From Sebastien Lorquet.
+
+ * Platforms: apps/system:
+
+ - flash_eraseall: Now uses the IOCTL wrapper at apps/fsutils/flash_eraseall.
+
+ * Platforms: apps/platform:
+
+ - Add platform files for Olimex STM32 E407. From Mateusz Szafoni.
+
+ * Applications: apps/examples:
+
+ - apps/examples/canard: Add canard example application. From
+ Matthias Renner.
+ - apps/examples/pty_test: PTY test program. From Alan Carvalho de
+ Assis.
+
+Works-In-Progress:
+
+ * IEEE802.14.5/6LowPAN. Hooks and framework for this effort were
+ introduced in NuttX-7.15. Work has continued on this effort on
+ forks from the main repositories, albeit with many interruptions.
+ The completion of this wireless feature will postponed until at
+ least NuttX-7.18.
+
+ * i.MX6 SMP. Partially functional, but there is more that still
+ needs to be done.
+
+Bugfixes. Only the most critical bugfixes are listed here (see the
+ChangeLog for the complete list of bugfixes and for additional, more
+detailed bugfix information):
+
+ * Core OS:
+
+ - semaphores: Need to set errno to EINVAL on errors in sem_post()
+ and sem_wait(). From Paul Alexander Patience.
+
+ * File System/Block Drivers/MTD Drivers:
+
+ - Several MTD FLASH drivers nullify the freed 'priv' structure and
+ failed to return NULL as stated in the comments. Result, will
+ operate on a NULL pointer later. Noted by David Sidrane.
+ - VFS ioctl(). Per comments from David Sidrane, file_ioctl() should
+ not return succeed if the ioctl method is not supported. It
+ probably should return ENOTTY in that case.
+ - SST26 Driver: Before accessing the sst26 flash, the "Global Unlock"
+ command must me executed, which I do in the sst26 driver. BUT re-
+ reading the datasheet, the WREN instruction is required to enable
+ the execution of this command. This was not done. I have no idea how
+ the driver currently works except by chance. The writes should never
+ happen at all, the flash is half-enabled! From Sebastien Lorquet.
+ - N25Qxx Driver: Alter the notion of 'blocksize' to be equivalent to
+ 'flash write page size' in order to align with assumptions in the
+ smartfs driver (at least, maybe other things do as well). Correct a
+ bug that was previously masked by having blocksize=eraseblocksize
+ which would cause buffer overflows and delicious hardfaults.
+ Trivial spelling changes in comments, etc. From ziggurat29.
+ - SmartFS: Fix a 32-byte memory leak. From Ken Pettit.
+ - SMART MTD layer: Fixes freesector logic error when sectorsPerBlk=256,
+ adds DEBUGASSERT for invalid geometry and additional memory debug
+ logic. Also fixes the dangling pointer on error bug. From Ken
+ Pettit.
+
+ * Common Drivers:
+
+ - USB CDC/ACM Device Class: cdcacm_unbind leaks write request objects.
+ This arises due to freeing the bulk IN endpoint before the loop
+ that frees the requests via cdcasm_freereq. That function checks
+ the parameters and skips the freeing if either is NULL. Freeing
+ the bulk IN enpoint will cause the first param to be NULL, thereby
+ bypassing the free operation. To fix, I moved the release of the
+ bulk IN endpoint until after to loop (much as was the case for the
+ OUT and read requests, which did not exhibit the problem). From
+ ziggurat29.
+ - Pipes and FIFOs: Add missing configuration for pipe ring buffer
+ size. From Frank Benkert.
+ - UART 16550: Handle when CONFIG_SERIAL_UART_ARCH_IOCTL is not
+ enabled. From Heath Petersen.
+ - Common Serial Upper Half: Fix a race condition noted by Stefan
+ Kolb. Between the test if the TX buffer is full and entering a
+ critical section, bytes may be removed from the TX buffer making
+ the wait unnecessary. The unnecessary wait is an inefficiency,
+ but not really a problem. But with USB CDC/ACM it can be a problem
+ because the entire TX buffer may be emptied when we lose the race.
+ If that happens that uart_putxmitchar() can hang waiting for data
+ to be removed from an empty TX buffer.
+ - USB MSC Device Class: Add locks when removing request from queue.
+ From Wolfgang Reissnegger.
+ - USB MSC Device Class: Fix reversed logic on waiting for SCSI thread
+ start. The scsi thread was waiting for the wrong condition.
+ However, this was masked by the fact that the code creating the
+ scsi thread was also holding usbmsc_scsi_lock(priv) while
+ initializing data, hence this lock synchronized the scsi thread
+ start with init completion. From Wolfgang Reissnegger.
+
+ * Graphics and Graphic Drivers:
+
+ - Correct conditional compilation in ST7565 LCD driver. From Pierre-
+ noel Bouteville
+
+ * Networking:
+
+ - In both IPv6 and IPv4 incoming logic: (1) Should check if the
+ packet size is large enough before trying to access the packet
+ length in the IP header. (2) In the comparison between the IP
+ length and the full packet length, need to subtract the size of
+ he link layer header before making the comparison or we will get
+ false positives (i.e., the packet is really too small)
+ - TCP Networking: While working with version 7.10 I discovered a
+ problem in TCP stack that could be observed on high network load.
+ Generally speaking, the problem is that RST flag is set in
+ unnecessary case, in which between loss of some TCP packet and its
+ proper retransmission, another packets had been successfully sent.
+ The scenario is as follows: NuttX did not receive ACK for some sent
+ packet, so it has been probably lost somewhere. But before its
+ retransmission starts, NuttX is correctly issuing next TCP packets,
+ with sequence numbers increasing properly. When the retransmission
+ of previously lost packet finally succeeds, tcp_input receives the
+ accumulated ACK value, which acknowledges also the packets sent in
+ the meantime (i.e. between unsuccessful sending of lost packet and
+ its proper retransmission). However, variable unackseq is still set
+ to conn->isn + conn->sent, which is truth only if no further
+ packets transmission occurred in the meantime. Because of incorrect
+ (in such specific case) unackseq value, few lines further condition
+ if (ackseq <= unackseq)is not met, and, as a result, we are going to
+ reset label. From Jakub Lagwa.
+
+ * ARMv7-M:
+
+ - ARM stack check: Fix double fault on IDLE task with stack size = 0.
+ From David Sidrane.
+
+ * Atmel SAMV7 Drivers:
+
+ - CAN: CAN Message Filtering fixed: (1) stdfilters didn't work because
+ the filter was never enabled (wrong number of bits to shift), and
+ (2) Filters were never used because the configuration register
+ cannot be written without using the initialization mode. Both bugs
+ are fixed by this change. Filtering has been tested with both
+ standard and extended identifiers and is now working properly. From
+ Michael Spahlinger.
+
+ * Atmel SAMA5:
+
+
+ * Atmel SAM3/4 Drivers:
+
+ - Fix some errors in AFEC header file. From OrbitalFox.
+ - DAC: DACC_WPMR_WPKEY_MASK -> DACC_WPMR_WPKEY. From Wolfgang
+ Reissnegge.
+ - Timer: Fix ops check in TCIOC_STOP. From Wolfgang Reissnegge.
+ - I2C: Fix reversed logic in twi_startmessage(). From Wolfgang
+ Reissnegger.
+ - SAM3/4 UDP: Fix handling of endpoint RX FIFO banks. This fixes
+ a race condition where the HW fills a FIFO bank while the SW is
+ busy, resulting in out of sequence USB packets.
+
+ * Atmel SAMV7 Drivers:
+
+ - USBHS Device: This change solves a problem which causes data loss
+ while sending data via USB. This problem is caused by an incorrect
+ handling of the endpoint state in the USB driver sam_usbdevhs. This
+ leads under some circumstances to situations in which an DMA
+ transfer is setup while a previous DMA transfer is currently active.
+ Amongst other things I introduced the new endpoint state
+ USBHS_EPSTATE_SENDING_DMA for the fix. To reproduce the problem, I
+ used a program which send as many data as possible via a CDC/ACM
+ device and verified the received data on the PC. From Stefan Kolb.
+
+ * NXP Freescale Kinetis Drivers:
+
+ - Timers: Support up to 8 channels per timer. From kfazz.
+
+ * NXP Freescale Kinetis Boards:
+
+ - Teensy 3.x clock fixes: The High Gain bit in MCG_C1 was preventing
+ teensy from booting except after a programming session. The second
+ change doesn't appear to change any functionality, but complies with
+ restrictions in the k20 family reference manual on FEI -> FBE clock
+ transiions. From kfazz.
+
+ * NXP Freescale LPC17xx Drivers:
+
+ - LPC17 Ethernet: Needs to correctly ignore PHYID2 revision number
+ when comparing PHY IDs.
+
+ * NXP Freescale LPC43xx Drivers:
+
+ - Fix errors in GPIO interrupt logic. From v01d (phreakuencies)
+ - Ethernet: Correct auto-negotiation mode in the LPC43xx Ethernet.
+ From Alexander Vasiljev
+ - Writing zero to NVIC_IRQ_ENABLE has no effect. Disable interrupts
+ with NVIC_IRQ_CLEAR. From Paul Alexander Patience.
+ - SPIFI: If CONFIG_SPIFI_SECTOR512 undefined, lpc43_bwrite doesn't do
+ actual write (probably copy/paste errors). Still not sure about
+ current state of lpc43_spifi implementation, but for me NXFFS works
+ with this change. From Vytautas Lukenskas.
+
+ * Qemu-i486:
+
+ - Fix qemu-i486/ostest/Make.defs test for M32. From Heath Petersen.
+
+ * SiLabs EFM32 Drivers:
+
+ - Fix EFM32 FLASH conditional compilation. From Pierre-noel
+ Bouteville
+ - Writing zero to NVIC_IRQ_ENABLE has no effect. Disable interrupts
+ with NVIC_IRQ_CLEAR. From Paul Alexander Patience.
+
+ * STMicro STM32:
+
+ - STM32 F1-F4: In PWM driver, just update duty if frequency is not
+ changed and PSM started. This removeis glitch or blinking when
+ only duty is frequently changed. From Pierre-noel Bouteville.
+
+ * STMicro STM32 Drivers:
+
+ - STM32 F7: Fixed STM32F7 DMA stm32_dmacapable. DMA working on SDMMC.
+ From David Sidrane.
+ - STM32 F1-F4 Timer Driver: Change calculation of per- timer pre-scaler
+ value. Add support for all timers
+ - STM32 F1-F4: Correct conditional compilation in STM32 timer capture
+ logic. From Pierre-noel Bouteville
+ - STM32 F1-F4: Fix STM32 DMA code and configuration for STM32F37X chips.
+ From Marten Svanfeldt.
+ - STM32 F1-F4: Fix compilation errors in debug mode of stm32_pwm.c.
+ From Konstantin Berezenko.
+ - STM32 F1-F4: Correct the CAN2 RX IRQ number for stm32f10xx chips.
+ From Konstantin Berezenko.
+ - STM32 F1-F4: Move backup domain reset to to earlier in the
+ initialization sequence (stm32_rcc.c() in order to avoid disabling
+ LSE during RTC initialiation. From Alan Carvalho de Assis.
+ - STM32 F1-F4: When configuring a GPIO via stm32_configgpio() the
+ function will first set the mode to output and then set the initial
+ state of the gpio later on. If you have an application with an
+ externaly pulled-up pin, this would lead to a glitch on the line
+ that may be dangerous in some applications (e.G. Reset Line for
+ other chips, etc). This changes sets the output state before
+ configuring the pin as an output. From Pascal Speck .
+ - STM32 F7: Apply Pascal Speck's GPIO STM32 change to STM32 L4.
+ - STM32 L4: Apply Pascal Speck's GPIO STM32 change to STM32 L4.
+ From Sebastien Lorquet.
+ - STM32 F7: BUGFIX: PLLs IS2 and SAI P Calculation. From David
+ Sidrane.
+ - STM32 L4: STM32 CAN fixes need to be backported to STM32L4 as well.
+ - STM32 F1-F4 and L4: Writing zero to NVIC_IRQ_ENABLE has no effect.
+ Disable interrupts with NVIC_IRQ_CLEAR. From Paul Alexander
+ Patience.
+ - STM32 F7: STMF7xxx RTC: (1) Remove proxy #defines, (2) Ensure the
+ LSE(ON) etal are set and remembered in a) A cold start (RTC_MAGIC
+ invalid) of the RTC, and b) A warm start (RTC_MAGIC valid) of the
+ RTC but a clock change. The change was needed because in bench
+ testing a merge of the latest's STM32 53ec3ca (and friends) it
+ became apparent that the sequence of operation is wrong in the
+ reset of the Backup Domain in the RCC code. PWR is required before
+ the Backup Domain can be futzed with. !!!This Code should be tested
+ on STM32 and if needed rippled to the STM32 families. From David
+ Sidrane.
+ - STM32 F1-F4: STM32 BBSRAM fixed (and formatted) flags. From David
+ Sidrane.
+ - STM32 F7: STM32F7 BBSRAM fixed (and formatted) flags. From David
+ Sidrane.
+ - STM32 L4: Fix incorrect clock setup for LPTIM1. From ziggurat29.
+ - STM32 F4/L4 RTC ALARM: were enabling interrupts too early in the
+ power-up sequence, BEFORE the interrupt system was being
+ initialized.
+
+ * STMicro STM32 Boards:
+
+ - STM32 board.h: Fix STM32 timer input clock definitions. From David
+ Sidrane.
+
+ * TI Tiva Drivers:
+
+ - Bug Fix in tiva_serial.c - UART5, UART6 and UART7 were not being
+ configured as TTYS0 for printing over serial console. From Shirshak
+ Sengupta.
+
+ * C Library/Header Files:
+
+ - include/signal.h: Change type of SIG_ERR, SIG_IGN, ... to
+ _sa_handler_t. The type void does not work with the IAR toolchain.
+ From Aleksandr Vyhovanec.
+ - crc16: fix error. From Paul Alexander Patience.
+ - strtoul() and strtoull(): Fix errno settings required by function
+ definition. Resolved Bitbucket Issue #1. From Sebastien Lorquet.
+
+ * Build/Configuration System:
+
+ - Build system: This change fixes a build problem that only occurs
+ when reconfiguring from Linux to Windows or vice-versa. It is a
+ problem that was present but not usually experienced until two
+ things happened: (1) The pre_config target was added to run before
+ the menconfig operation and (2) the context target was added before
+ the pre_config target in order to set up the correct symbolic links
+ (in the apps/platform directory) needed by the pre_config target.
+ But then now if you start with a Linux system and run 'make
+ menuconfig' to switch to Linux, the context target will execute
+ first and set up POSIX style symbolic links before doing the
+ menuconfig. Then after the menuconfig, the make will fail on
+ Windows if you are using a Windows native toolchain because that
+ native toolchain cannot follow the Cygwin- style symbolic links.
+ The fix here is to also execute the clean_context AFTER executing
+ menuconfig. A lot more happens now: It used to be that doing
+ 'make menuconfig' only did the menuconfig operation. Now it does
+ context, pre_config, menuconfig, clean_context. Not nearly as
+ snappy as it used to be.
+ - Need to build the drivers/ directory even it file descriptors are
+ not supported. There are things in the drivers/ directory that are
+ still needed (like SYSLOG logic).
+ - Remove all inclusion of header files from the apps/include
+ directory from NuttX core logic. There should be no dependency on
+ logic within NuttX on logic within apps/. This caused a lot of
+ reshuffling of logic: binfmt pcode support, usbmonitor is now a
+ kernel thread, TZ/Olson database moved to libc/zoneinfo.
+
+ * Application Build/Configuration System:
+
+ - Make sure that APPNAME is defined in all Makefiles that generate
+ applications. From Sebastien Lorquet.
+
+ * apps/builtins:
+
+ - apps/builtins: exec_builtin was not using the provided open flags.
+ As a result >> redirection was not working; it was treated the same
+ as >.
+
+ * apps/nshlib:
+
+ - apps/nshilib: PS Command: When Priority Inheritance is enabled, the
+ format of /proc//status changes to show both the current
+ priority and the threads base priority. This messes up the format
+ of cmd_ps. From David Alessio.
+
+ * apps/netutils:
+
+ - apps/netutils, uIP webserver: Fix a data declaration in a header
+ file.
+
+ * apps/canutils:
+
+ - apps/canutils/libuavcan: Fix for recent change to STM32 timer
+ frequency definiitions.
+
+ * apps/examples:
+
+ - apps/examples/alarm: ioctl call was clobbering file descriptor.
+ - apps/examples/can: Some variables were not declared in all required
+ cases. From Sebastien Lorquet.
+ - apps/examples/media: media example was intended to take either a
+ command line argument, or a compiled-in default value from config.
+ However, the default was ignored, leading to confusing error
+ messages. From ziggurat29.
diff --git a/TODO b/TODO
index a4c960e2e18b5004b1242728731a7c3ee3caa424..5372b0aec5044cb7c37a920b531f1bdfdc5ad877 100644
--- a/TODO
+++ b/TODO
@@ -1,4 +1,4 @@
-NuttX TODO List (Last updated June 6, 2016)
+NuttX TODO List (Last updated July 20, 2016)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -17,7 +17,7 @@ nuttx/:
(9) Kernel/Protected Build
(3) C++ Support
(6) Binary loaders (binfmt/)
- (12) Network (net/, drivers/net)
+ (11) Network (net/, drivers/net)
(4) USB (drivers/usbdev, drivers/usbhost)
(0) Other drivers (drivers/)
(11) Libraries (libc/, libm/)
@@ -219,7 +219,7 @@ o Task/Scheduler (sched/)
Description: Task control information is retained in simple lists. This
is completely appropriate for small embedded systems where
the number of tasks, N, is relatively small. Most list
- operations are O(N). This could become as issue if N gets
+ operations are O(N). This could become an issue if N gets
very large.
In that case, these simple lists should be replaced with
@@ -447,6 +447,7 @@ o Kernel/Protected Build
mkfatfs mkfatfs
mkrd ramdisk_register()
ping icmp_ping()
+ mount foreach_mountpoint()
The busybox mkfatfs does not involve any OS calls; it does
its job by simply opening the block driver (using open/xopen)
@@ -818,7 +819,7 @@ o Binary loaders (binfmt/)
"Read-Only Data in RAM" at
http://nuttx.org/Documentation/NuttXNxFlat.html#limitations).
- The newer 4.6.3compiler generated PC relative relocations to the strings:
+ The newer 4.6.3 compiler generated PC relative relocations to the strings:
.L2:
.word .LC0-(.LPIC0+4)
@@ -926,8 +927,7 @@ o Network (net/, drivers/net)
CONFIG_NET_NOINTS). This is really a very bad use of CPU
resources; All of the network stack processing should be
modified to use a work queue (and, all use of CONFIG_NET_NOINTS=n
- should be eliminated). This applies to almost all Ethernet
- drivers:
+ should be eliminated). This applies to many Ethernet drivers:
ARCHITECTURE CONFIG_NET_NOINTS? ADDRESS FILTER SUPPORT?
C5471 NO NO
@@ -937,7 +937,9 @@ o Network (net/, drivers/net)
LM3S NO NO
TM4C YES YES
eZ80 NO NO
+ Kinetis YES YES (not tested)
LPC17xx YES YES (not tested)
+ LPC43xx YES YES (not tested)
DMxxx NIC NO NO
PIC32 NO NO
RGMP ??? ???
@@ -1337,6 +1339,8 @@ o Libraries (libc/)
UPDATE: 2015-09-01: A fix for the noted problems with asin()
has been applied.
+ 2016-07-30: Numerous fixes and performance improvements from
+ David Alessio.
Status: Open
Priority: Low for casual users but clearly high if you need care about
@@ -1352,12 +1356,6 @@ o File system / Generic drivers (fs/, drivers/)
Status: Open
Priority: Low
- Title: CAN POLL SUPPORT
- Description: At present, the CAN driver does not support the poll() method.
- See drivers/can.c
- Status: Open
- Priority: Low
-
Title: ROMFS CHECKSUMS
Description: The ROMFS file system does not verify checksums on either
volume header on on the individual files.
@@ -1403,6 +1401,15 @@ o File system / Generic drivers (fs/, drivers/)
socket structures. There really should be one array that
is a union of file and socket descriptors. Then socket and
file descriptors could lie in the same range.
+
+ Another example of how the current implementation limits
+ functionality: I recently started an implement of the FILEMAX
+ (using pctl() instead sysctl()). My objective was to be able
+ to control the number of available file descriptors on a task-
+ by-task basis. The complexity due to the partitioning of
+ desciptor space in a range for file descriptors and a range
+ for socket descriptors made this feature nearly impossible to
+ implement.
Status: Open
Priority: Low
@@ -1602,7 +1609,7 @@ o Build system
Priority: Low.
Title: NATIVE WINDOWS BUILD BROKEN
- Description: The way that apps/ no generates Kmenu files depends on changes added
+ Description: The way that apps/ now generates Kmenu files depends on changes added
to apps/tools/mkkconfig.sh. Similar changes need to be made to
apps/tools/mkkconfig.bat to restore the Windows Native build.
UPDATE: The mkkconfig.bat script has been updated and appears to work.
@@ -1729,7 +1736,7 @@ o ARM (arch/arm/)
upon return. This could be improved as well: If there is no
context switch, then the static registers need not be restored
because they will not be modified by the called C code.
- (see arch/sh/src/sh1/sh1_vector.S for example)
+ (see arch/renesas/src/sh1/sh1_vector.S for example)
Status: Open
Priority: Low
diff --git a/arch/Kconfig b/arch/Kconfig
index fd61f2fbf55f96b6af107d6dc625c9454d389d94..319419bb2d13e9f2781ceed045b25099104e9fbb 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -45,7 +45,7 @@ config ARCH_RGMP
RTOS and GPOS on Multi-Processor (RGMP) architecture. See
http://rgmp.sourceforge.net/wiki/index.php/Main_Page.
-config ARCH_SH
+config ARCH_RENESAS
bool "Renesas"
select ARCH_NOINTC
select ARCH_HAVE_INTERRUPTSTACK
@@ -58,6 +58,7 @@ config ARCH_SIM
select ARCH_HAVE_TLS
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_POWEROFF
+ select SERIAL_CONSOLE
---help---
Linux/Cywgin user-mode simulation.
@@ -82,23 +83,23 @@ endchoice
config ARCH
string
- default "arm" if ARCH_ARM
- default "avr" if ARCH_AVR
- default "hc" if ARCH_HC
- default "mips" if ARCH_MIPS
- default "rgmp" if ARCH_RGMP
- default "sh" if ARCH_SH
- default "sim" if ARCH_SIM
- default "x86" if ARCH_X86
- default "z16" if ARCH_Z16
- default "z80" if ARCH_Z80
+ default "arm" if ARCH_ARM
+ default "avr" if ARCH_AVR
+ default "hc" if ARCH_HC
+ default "mips" if ARCH_MIPS
+ default "rgmp" if ARCH_RGMP
+ default "renesas" if ARCH_RENESAS
+ default "sim" if ARCH_SIM
+ default "x86" if ARCH_X86
+ default "z16" if ARCH_Z16
+ default "z80" if ARCH_Z80
source arch/arm/Kconfig
source arch/avr/Kconfig
source arch/hc/Kconfig
source arch/mips/Kconfig
source arch/rgmp/Kconfig
-source arch/sh/Kconfig
+source arch/renesas/Kconfig
source arch/sim/Kconfig
source arch/x86/Kconfig
source arch/z16/Kconfig
@@ -525,6 +526,7 @@ config ARCH_IRQPRIO
config ARCH_STACKDUMP
bool "Dump stack on assertions"
default n
+ select DEBUG_ALERT
---help---
Enable to do stack dumps after assertions
diff --git a/arch/README.txt b/arch/README.txt
index 114f2f6f1e7e430067cf244458edbc5a37ffada5..bd49fb31a7c2a6b430fdb73cb1f79fd730105b2c 100644
--- a/arch/README.txt
+++ b/arch/README.txt
@@ -150,11 +150,13 @@ arch/arm - ARM-based micro-controllers
Architecture Support
arch/arm/include and arch/arm/src/common
arch/arm/src/arm and arch/arm/include/arm
+ arch/arm/src/armv7-a and arch/arm/include/armv6-m
arch/arm/src/armv7-a and arch/arm/include/armv7-a
arch/arm/src/armv7-m and arch/arm/include/armv7-m
- arch/arm/src/armv7-r and arch/arm/include/armv7-4
+ arch/arm/src/armv7-r and arch/arm/include/armv7-r
MCU support
+ arch/arm/include/a1x and arch/arm/src/a1x
arch/arm/include/c5471 and arch/arm/src/c5471
arch/arm/include/calypso and arch/arm/src/calypso
arch/arm/include/dm320 and arch/arm/src/dm320
@@ -210,6 +212,16 @@ arch/mips
arch/mips/include/pic32mx and arch/mips/src/pic32mx
arch/mips/include/pic32mz and arch/mips/src/pic32mz
+arch/renesas - Support for Renesas and legacy Hitachi microcontrollers.
+ This include SuperH and M16C.
+
+ Architecture Support
+ arch/renesas/include and arch/renesas/src/common
+
+ MCU support
+ arch/renesas/include/m16c and arch/renesas/src/m16c
+ arch/renesas/include/sh1 and arch/renesas/src/sh1
+
arch/rgmp
RGMP stands for RTOS and GPOS on Multi-Processor. RGMP is a project
@@ -221,15 +233,6 @@ arch/rgmp
See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further
information about RGMP.
-arch/sh - SuperH and related Hitachi/Renesas microcontrollers
-
- Architecture Support
- arch/sh/include and arch/sh/src/common
-
- MCU support
- arch/sh/include/m16c and arch/sh/src/m16c
- arch/sh/include/sh1 and arch/sh/src/sh1
-
arch/x86 - Intel x86 architectures
This directory holds related, 32- and 64-bit architectures from Intel.
At present, this includes the following subdirectories:
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f31f81277830e7249f328ecf6073c4173cc8e48a..63af8acafc96f30946a27c8371244ff4b442e1fc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -51,6 +51,7 @@ config ARCH_CHIP_DM320
config ARCH_CHIP_EFM32
bool "Energy Micro"
select ARCH_HAVE_CMNVECTOR
+ select ARCH_HAVE_SPI_BITORDER
select ARMV7M_CMNVECTOR
---help---
Energy Micro EFM32 microcontrollers (ARM Cortex-M).
@@ -206,12 +207,14 @@ config ARCH_CHIP_SAM34
config ARCH_CHIP_SAMV7
bool "Atmel SAMV7"
select ARCH_HAVE_CMNVECTOR
- select ARMV7M_CMNVECTOR
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
- select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_I2CRESET
+ select ARCH_HAVE_SPI_CS_CONTROL
+ select ARM_HAVE_MPU_UNIFIED
+ select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK
---help---
Atmel SAMV7 (ARM Cortex-M7) architectures
@@ -220,9 +223,12 @@ config ARCH_CHIP_STM32
bool "STMicro STM32 F1/F2/F3/F4"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
- select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
+ select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_TIMEKEEPING
+ select ARCH_HAVE_SPI_BITORDER
+ select ARM_HAVE_MPU_UNIFIED
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M3/4).
@@ -230,12 +236,13 @@ config ARCH_CHIP_STM32
config ARCH_CHIP_STM32F7
bool "STMicro STM32 F7"
select ARCH_HAVE_CMNVECTOR
- select ARMV7M_CMNVECTOR
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
- select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
+ select ARCH_HAVE_SPI_BITORDER
+ select ARM_HAVE_MPU_UNIFIED
+ select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M7).
@@ -243,12 +250,14 @@ config ARCH_CHIP_STM32F7
config ARCH_CHIP_STM32L4
bool "STMicro STM32 L4"
select ARCH_HAVE_CMNVECTOR
- select ARMV7M_CMNVECTOR
select ARCH_CORTEXM4
select ARCH_HAVE_MPU
- select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
+ select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_SPI_BITORDER
+ select ARM_HAVE_MPU_UNIFIED
+ select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M4).
diff --git a/arch/arm/include/calypso/clock.h b/arch/arm/include/calypso/clock.h
index abcfde1d449d947a14904a36f100e5bfea0b95a8..a10a607a5d232d960e1f2861ef101fcab6cd42ef 100644
--- a/arch/arm/include/calypso/clock.h
+++ b/arch/arm/include/calypso/clock.h
@@ -1,5 +1,5 @@
-#ifndef _CALYPSO_CLK_H
-#define _CALYPSO_CLK_H
+#ifndef __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H
+#define __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H
#include
@@ -64,4 +64,4 @@ void calypso_debugunit(int enable);
void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout,
uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1);
-#endif /* _CALYPSO_CLK_H */
+#endif /* __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H */
diff --git a/arch/arm/include/calypso/debug.h b/arch/arm/include/calypso/debug.h
index 8c7b9aabfbdd132ae439b765f0d4318ec31c4144..9596946775756250a5b5dd9dabef3230503dc9d7 100644
--- a/arch/arm/include/calypso/debug.h
+++ b/arch/arm/include/calypso/debug.h
@@ -1,5 +1,5 @@
-#ifndef _DEBUG_H
-#define _DEBUG_H
+#ifndef __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H
+#define __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
@@ -28,4 +28,4 @@
#define printd(x, args ...)
#endif
-#endif /* _DEBUG_H */
+#endif /* __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H */
diff --git a/arch/arm/include/calypso/defines.h b/arch/arm/include/calypso/defines.h
index 3c8732f92f8c086b825e70d7d51c980e41a79e40..4f29560c8332f41b0eba7db613b64b037921b597 100644
--- a/arch/arm/include/calypso/defines.h
+++ b/arch/arm/include/calypso/defines.h
@@ -1,6 +1,5 @@
-
-#ifndef _DEFINES_H
-#define _DEFINES_H
+#ifndef __ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H
+#define __ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H
#define __attribute_const__ __attribute__((__const__))
@@ -15,4 +14,4 @@
/* force placement in zero-waitstate memory */
#define __ramtext __section(".ramtext")
-#endif /* !_DEFINES_H */
+#endif /* !__ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H */
diff --git a/arch/arm/include/calypso/irq.h b/arch/arm/include/calypso/irq.h
index baea3de5a3f690f6b2a6411e6adfb12f03290325..0dda3f312feec579d446f491cd1b04f479fa1398 100644
--- a/arch/arm/include/calypso/irq.h
+++ b/arch/arm/include/calypso/irq.h
@@ -41,8 +41,8 @@
#error "This file should never be included directly! Use "
#endif
-#ifndef _CALYPSO_IRQ_H
-#define _CALYPSO_IRQ_H
+#ifndef __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H
+#define __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H
#ifndef __ASSEMBLY__
@@ -78,4 +78,4 @@ enum irq_nr {
#define IRQ_SYSTIMER IRQ_TIMER2
-#endif /* _CALYPSO_IRQ_H */
+#endif /* __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H */
diff --git a/arch/arm/include/calypso/memory.h b/arch/arm/include/calypso/memory.h
index b0a0490cec1c3f8d44714ef9826fed115163be02..a4ce1e890ee2c57b98cdfe61e0814600cc6cc4ee 100644
--- a/arch/arm/include/calypso/memory.h
+++ b/arch/arm/include/calypso/memory.h
@@ -1,5 +1,5 @@
-#ifndef _MEMORY_H
-#define _MEMORY_H
+#ifndef __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H
+#define __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H
#define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getw(a) (*(volatile unsigned short *)(a))
@@ -25,4 +25,4 @@
#define readw(a) __arch_getw(a)
#define readl(a) __arch_getl(a)
-#endif /* _MEMORY_H */
+#endif /* __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H */
diff --git a/arch/arm/include/calypso/timer.h b/arch/arm/include/calypso/timer.h
index 694e4ebc92efb1d4031508354f4366f9079df243..93a1bd1492508a27af51a76edb776b175badd86b 100644
--- a/arch/arm/include/calypso/timer.h
+++ b/arch/arm/include/calypso/timer.h
@@ -1,5 +1,5 @@
-#ifndef _CAL_TIMER_H
-#define _CAL_TIMER_H
+#ifndef __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H
+#define __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H
/* Enable or Disable a timer */
void hwtimer_enable(int num, int on);
@@ -22,4 +22,4 @@ void wdog_reset(void);
/* power up the timers */
void hwtimer_init(void);
-#endif /* _CAL_TIMER_H */
+#endif /* __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H */
diff --git a/arch/arm/include/calypso/uwire.h b/arch/arm/include/calypso/uwire.h
index 19a277bccb5754cb938ce3593e8abe5492936068..0ca6c376ca7c326618db38f025f4a84d531bbfa0 100644
--- a/arch/arm/include/calypso/uwire.h
+++ b/arch/arm/include/calypso/uwire.h
@@ -1,5 +1,5 @@
-#ifndef _CALYPSO_UWIRE_H
-#define _CALYPSO_UWIRE_H
+#ifndef __ARCH_ARM_INCLUDE_CALYPSO_UWIRE_H
+#define __ARCH_ARM_INCLUDE_CALYPSO_UWIRE_H
void uwire_init(void);
int uwire_xfer(int cs, int bitlen, const void *dout, void *din);
#endif
diff --git a/arch/arm/include/kinetis/chip.h b/arch/arm/include/kinetis/chip.h
index dd8582e564fc8e78472ed6b53c9e4eaf200d10a1..f2fa5fbb4e707b0732f369f6a4d9e0e27dc9a117 100644
--- a/arch/arm/include/kinetis/chip.h
+++ b/arch/arm/include/kinetis/chip.h
@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/include/kinetis/chip.h
*
- * Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2013, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -72,6 +72,7 @@
# define KINETIS_K20 1 /* Kinetics K20 family */
# undef KINETIS_K40 /* Not Kinetics K40 family */
# undef KINETIS_K60 /* Not Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
#if defined(CONFIG_ARCH_CHIP_MK20DN32VLH5)
# define KINETIS_FLASH_SIZE (64*1024) /* 32Kb */
@@ -153,6 +154,7 @@
# define KINETIS_K20 1 /* Kinetics K20 family */
# undef KINETIS_K40 /* Not Kinetics K40 family */
# undef KINETIS_K60 /* Not Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
#if defined(CONFIG_ARCH_CHIP_MK20DX64VLH7)
# define KINETIS_FLASH_SIZE (64*1024) /* 64Kb */
@@ -207,6 +209,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# define KINETIS_K40 1 /* Kinetics K40 family */
# undef KINETIS_K60 /* Not Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (64*1024) /* 64Kb */
# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
# define KINETIS_SRAM_SIZE (16*1024) /* 16Kb */
@@ -257,6 +260,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# define KINETIS_K40 1 /* Kinetics K40 family */
# undef KINETIS_K60 /* Not Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */
# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */
@@ -299,6 +303,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# define KINETIS_K40 1 /* Kinetics K40 family */
# undef KINETIS_K60 /* Not Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
# define KINETIS_SRAM_SIZE (32*1024) /* 64Kb */
@@ -340,6 +345,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# define KINETIS_K40 1 /* Kinetics K40 family */
# undef KINETIS_K60 /* Not Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */
# define KINETIS_FLEXMEM_SIZE (128*1024) /* 128Kb */
# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */
@@ -381,6 +387,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# define KINETIS_K40 1 /* Kinetics K40 family */
# undef KINETIS_K60 /* Not Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXMEM_SIZE (256*1024) /* 256Kb */
# define KINETIS_SRAM_SIZE (64*1024) /* 32Kb */
@@ -424,6 +431,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# define KINETIS_K40 1 /* Kinetics K40 family */
# undef KINETIS_K60 /* Not Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */
# undef KINETIS_FLEXMEM_SIZE /* No FlexMemory */
# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
@@ -465,6 +473,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# undef KINETIS_K40 /* Not Kinetics K40 family */
# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
@@ -509,6 +518,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# undef KINETIS_K40 /* Not Kinetics K40 family */
# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXRAM_SIZE (4*1024) /* 32Kb */
@@ -553,6 +563,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# undef KINETIS_K40 /* Not Kinetics K40 family */
# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
@@ -598,6 +609,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# undef KINETIS_K40 /* Not Kinetics K40 family */
# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
@@ -642,6 +654,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# undef KINETIS_K40 /* Not Kinetics K40 family */
# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
@@ -686,6 +699,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# undef KINETIS_K40 /* Not Kinetics K40 family */
# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
@@ -730,6 +744,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# undef KINETIS_K40 /* Not Kinetics K40 family */
# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
@@ -774,6 +789,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# undef KINETIS_K40 /* Not Kinetics K40 family */
# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
@@ -818,6 +834,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# undef KINETIS_K40 /* Not Kinetics K40 family */
# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
@@ -862,6 +879,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# undef KINETIS_K40 /* Not Kinetics K40 family */
# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
@@ -906,6 +924,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# undef KINETIS_K40 /* Not Kinetics K40 family */
# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
@@ -950,6 +969,7 @@
# undef KINETIS_K20 /* Not Kinetis K20 family */
# undef KINETIS_K40 /* Not Kinetics K40 family */
# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
@@ -990,6 +1010,278 @@
# undef KINETIS_NTAMPER /* No tamper detect */
# define KINETIS_NCRC 1 /* CRC */
+#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12)
+# undef KINETIS_K20 /* Not Kinetics K20 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K64 1 /* Kinetis K64 family */
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NUART 6 /* Six UART modues */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 1 /* One CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 2 /* Four 16-bit ADC */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */
+# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# define KINETIS_NCRC 1 /* CRC */
+
+#elif defined(CONFIG_ARCH_CHIP_MK64FX512VLL12)
+# undef KINETIS_K20 /* Not Kinetics K20 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K64 1 /* Kinetis K64 family */
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NUART 6 /* Six UART modues */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 1 /* One CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 2 /* Four 16-bit ADC */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */
+# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# define KINETIS_NCRC 1 /* CRC */
+
+#elif defined(CONFIG_ARCH_CHIP_MK64FX512VDC12)
+# undef KINETIS_K20 /* Not Kinetics K20 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K64 1 /* Kinetis K64 family */
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NUART 6 /* Six UART modues */
+# define KINETIS_NSPI 3 Three SPI modules
+# define KINETIS_NCAN 1 /* One CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 2 /* Four 16-bit ADC */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */
+# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# define KINETIS_NCRC 1 /* CRC */
+
+#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12)
+# undef KINETIS_K20 /* Not Kinetics K20 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K64 1 /* Kinetis K64 family */
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NUART 6 /* Six UART modues */
+# define KINETIS_NSPI 3 Three SPI modules
+# define KINETIS_NCAN 1 /* One CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 2 /* Four 16-bit ADC */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */
+# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# define KINETIS_NCRC 1 /* CRC */
+
+#elif defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12)
+# undef KINETIS_K20 /* Not Kinetics K20 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K64 1 /* Kinetis K64 family */
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NUART 6 /* Six UART modues */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 1 /* One CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 2 /* Four 16-bit ADC */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */
+# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# define KINETIS_NCRC 1 /* CRC */
+
+#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12)
+# undef KINETIS_K20 /* Not Kinetics K20 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K64 1 /* Kinetis K64 family */
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NUART 6 /* Six UART modues */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 1 /* One CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 2 /* Four 16-bit ADC */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */
+# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# define KINETIS_NCRC 1 /* CRC */
+
+#elif defined(CONFIG_ARCH_CHIP_MK64FX512VMD12)
+# undef KINETIS_K20 /* Not Kinetics K20 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K64 1 /* Kinetis K64 family */
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NUART 6 /* Six UART modues */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 1 /* One CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 2 /* Four 16-bit ADC */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */
+# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# define KINETIS_NCRC 1 /* CRC */
+
+#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
+# undef KINETIS_K20 /* Not Kinetics K20 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K64 1 /* Kinetis K64 family */
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NUART 6 /* Six UART modues */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 1 /* One CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 2 /* Four 16-bit ADC */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */
+# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# define KINETIS_NCRC 1 /* CRC */
+
#else
# error "Unsupported Kinetis chip"
#endif
diff --git a/arch/arm/include/kinetis/irq.h b/arch/arm/include/kinetis/irq.h
index 16b59ab8ae96fc4054e91e16ac849c0cb2f2293f..1e45a5b4c63be0f1c6ee3cd1a5009fb165f02885 100644
--- a/arch/arm/include/kinetis/irq.h
+++ b/arch/arm/include/kinetis/irq.h
@@ -83,7 +83,7 @@
* K20P64M72SF1RM
*/
-#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
+#if defined(CONFIG_ARCH_FAMILY_K20)
# define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */
# define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */
# define KINETIS_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */
@@ -162,9 +162,7 @@
* K40P144M100SF2RM
*/
-#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
+#elif defined(CONFIG_ARCH_FAMILY_K40)
# define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */
# define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */
@@ -274,10 +272,7 @@
* K60P144M100SF2RM
*/
-#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) || defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) || \
- defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK60N256VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK60X256VMD100) || defined(CONFIG_ARCH_CHIP_MK60N512VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK60N512VLL100)
+#elif defined(CONFIG_ARCH_FAMILY_K60)
# define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */
# define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */
@@ -383,6 +378,105 @@
# define NR_VECTORS (120) /* 120 vectors */
# define NR_IRQS (108) /* 120 interrupts but 108 IRQ numbers */
+/* K64 Family ***********************************************************************
+ *
+ * The memory map for the following parts is defined in NXP document
+ * K64P144M120SF5RM.pdf
+ */
+
+#elif defined(CONFIG_ARCH_FAMILY_K64)
+
+# define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */
+# define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */
+# define KINETIS_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */
+# define KINETIS_IRQ_DMACH3 (19) /* Vector 19: DMA channel 3 transfer complete */
+# define KINETIS_IRQ_DMACH4 (20) /* Vector 20: DMA channel 4 transfer complete */
+# define KINETIS_IRQ_DMACH5 (21) /* Vector 21: DMA channel 5 transfer complete */
+# define KINETIS_IRQ_DMACH6 (22) /* Vector 22: DMA channel 6 transfer complete */
+# define KINETIS_IRQ_DMACH7 (23) /* Vector 23: DMA channel 7 transfer complete */
+# define KINETIS_IRQ_DMACH8 (24) /* Vector 24: DMA channel 8 transfer complete */
+# define KINETIS_IRQ_DMACH9 (25) /* Vector 25: DMA channel 9 transfer complete */
+# define KINETIS_IRQ_DMACH10 (26) /* Vector 26: DMA channel 10 transfer complete */
+# define KINETIS_IRQ_DMACH11 (27) /* Vector 27: DMA channel 11 transfer complete */
+# define KINETIS_IRQ_DMACH12 (28) /* Vector 28: DMA channel 12 transfer complete */
+# define KINETIS_IRQ_DMACH13 (29) /* Vector 29: DMA channel 13 transfer complete */
+# define KINETIS_IRQ_DMACH14 (30) /* Vector 30: DMA channel 14 transfer complete */
+# define KINETIS_IRQ_DMACH15 (31) /* Vector 31: DMA channel 15 transfer complete */
+# define KINETIS_IRQ_DMAERR (32) /* Vector 32: DMA error interrupt channels 0-15 */
+# define KINETIS_IRQ_MCM (33) /* Vector 33: MCM Normal interrupt */
+# define KINETIS_IRQ_FLASHCC (34) /* Vector 34: Flash memory command complete */
+# define KINETIS_IRQ_FLASHRC (35) /* Vector 35: Flash memory read collision */
+# define KINETIS_IRQ_SMCLVD (36) /* Vector 36: Mode Controller low-voltage
+ * detect, low-voltage warning */
+# define KINETIS_IRQ_LLWU (37) /* Vector 37: LLWU Normal Low Leakage Wakeup */
+# define KINETIS_IRQ_WDOG (38) /* Vector 38: Watchdog */
+# define KINETIS_IRQ_RNGB (39) /* Vector 39: Random number generator */
+# define KINETIS_IRQ_I2C0 (40) /* Vector 40: I2C0 */
+# define KINETIS_IRQ_I2C1 (41) /* Vector 41: I2C1 */
+# define KINETIS_IRQ_SPI0 (42) /* Vector 42: SPI0 all sources */
+# define KINETIS_IRQ_SPI1 (43) /* Vector 43: SPI1 all sources */
+# define KINETIS_IRQ_I2S0 (44) /* Vector 44: Transmit */
+# define KINETIS_IRQ_I2S1 (45) /* Vector 45: Transmit */
+ /* Vector 46: Reserved */
+# define KINETIS_IRQ_UART0S (47) /* Vector 47: UART0 status */
+# define KINETIS_IRQ_UART0E (48) /* Vector 48: UART0 error */
+# define KINETIS_IRQ_UART1S (49) /* Vector 49: UART1 status */
+# define KINETIS_IRQ_UART1E (50) /* Vector 50: UART1 error */
+# define KINETIS_IRQ_UART2S (51) /* Vector 51: UART2 status */
+# define KINETIS_IRQ_UART2E (52) /* Vector 52: UART2 error */
+# define KINETIS_IRQ_UART3S (53) /* Vector 53: UART3 status */
+# define KINETIS_IRQ_UART3E (54) /* Vector 54: UART3 error */
+# define KINETIS_IRQ_ADC0 (55) /* Vector 55: ADC0 */
+# define KINETIS_IRQ_CMP0 (56) /* Vector 56: CMP0 */
+# define KINETIS_IRQ_CMP1 (57) /* Vector 57: CMP1 */
+# define KINETIS_IRQ_FTM0 (58) /* Vector 58: FTM0 all sources */
+# define KINETIS_IRQ_FTM1 (59) /* Vector 59: FTM1 all sources */
+# define KINETIS_IRQ_FTM2 (60) /* Vector 60: FTM2 all sources */
+# define KINETIS_IRQ_CMT (61) /* Vector 61: CMT */
+# define KINETIS_IRQ_RTC0 (62) /* Vector 62: RTC alarm interrupt */
+# define KINETIS_IRQ_RTC1 (63) /* Vector 63: RTC seconds interrupt */
+# define KINETIS_IRQ_PITCH0 (64) /* Vector 64: PIT channel 0 */
+# define KINETIS_IRQ_PITCH1 (65) /* Vector 65: PIT channel 1 */
+# define KINETIS_IRQ_PITCH2 (66) /* Vector 66: PIT channel 2 */
+# define KINETIS_IRQ_PITCH3 (67) /* Vector 67: PIT channel 3 */
+# define KINETIS_IRQ_PDB (68) /* Vector 68: PDB */
+# define KINETIS_IRQ_USBOTG (69) /* Vector 68: USB OTG */
+# define KINETIS_IRQ_USBCD (70) /* Vector 70: USB charger detect */
+ /* Vector 71: Reserved */
+# define KINETIS_IRQ_DAC0 (72) /* Vector 72: DAC0 */
+# define KINETIS_IRQ_MCG (73) /* Vector 73: MCG */
+# define KINETIS_IRQ_LPT (74) /* Vector 74: Low power timer */
+# define KINETIS_IRQ_PORTA (75) /* Vector 75: Pin detect port A */
+# define KINETIS_IRQ_PORTB (76) /* Vector 76: Pin detect port B */
+# define KINETIS_IRQ_PORTC (77) /* Vector 77: Pin detect port C */
+# define KINETIS_IRQ_PORTD (78) /* Vector 78: Pin detect port D */
+# define KINETIS_IRQ_PORTE (79) /* Vector 79: Pin detect port E */
+# define KINETIS_IRQ_SOFTWARE (80) /* Vector 80: Software interrupt */
+# define KINETIS_IRQ_SPI2 (81) /* Vector 81: SPI2 all sources */
+# define KINETIS_IRQ_UART4S (82) /* Vector 82: UART4 status */
+# define KINETIS_IRQ_UART4E (83) /* Vector 83: UART4 error */
+# define KINETIS_IRQ_UART5S (84) /* Vector 84: UART5 status */
+# define KINETIS_IRQ_UART5E (85) /* Vector 85: UART5 error */
+# define KINETIS_IRQ_CMP2 (86) /* Vector 86: CMP2 */
+# define KINETIS_IRQ_FTM3 (87) /* Vector 87: FTM3 all sources */
+# define KINETIS_IRQ_DAC1 (88) /* Vector 88: DAC1 */
+# define KINETIS_IRQ_ADC1 (89) /* Vector 89: ADC1 */
+# define KINETIS_IRQ_I2C2 (90) /* Vector 90: I2C2 */
+# define KINETIS_IRQ_CAN0MB (91) /* Vector 91: CAN0 OR'ed Message buffer (0-15) */
+# define KINETIS_IRQ_CAN0BO (92) /* Vector 92: CAN0 Bus Off */
+# define KINETIS_IRQ_CAN0ERR (93) /* Vector 93: CAN0 Error */
+# define KINETIS_IRQ_CAN0TW (94) /* Vector 94: CAN0 Transmit Warning */
+# define KINETIS_IRQ_CAN0RW (95) /* Vector 95: CAN0 Receive Warning */
+# define KINETIS_IRQ_CAN0WU (96) /* Vector 96: CAN0 Wake UP */
+# define KINETIS_IRQ_SDHC (97) /* Vector 97: SDHC */
+# define KINETIS_IRQ_EMACTMR (98) /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */
+# define KINETIS_IRQ_EMACTX (99) /* Vector 92: Ethernet MAC transmit interrupt */
+# define KINETIS_IRQ_EMACRX (100) /* Vector 93: Ethernet MAC receive interrupt */
+# define KINETIS_IRQ_EMACMISC (101) /* Vector 94: Ethernet MAC error and misc interrupt */
+
+# define NR_VECTORS (102) /* 102 vectors */
+# define NR_IRQS (102) /* 85 interrupts but 102 IRQ numbers */
+
#else
/* The interrupt vectors for other parts are defined in other documents and may or
* may not be the same as above (the family members are all very similar) This
diff --git a/arch/arm/include/lpc17xx/lpc176x_irq.h b/arch/arm/include/lpc17xx/lpc176x_irq.h
index 248c5c47d66070842bed5b0dda851ec236a2b7dd..b844b33d652abd27ccaf2ae87a2b01359cd77c89 100644
--- a/arch/arm/include/lpc17xx/lpc176x_irq.h
+++ b/arch/arm/include/lpc17xx/lpc176x_irq.h
@@ -147,7 +147,7 @@
* 42
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
# define LPC17_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrupt set */
# define LPC17_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */
diff --git a/arch/arm/include/lpc17xx/lpc178x_irq.h b/arch/arm/include/lpc17xx/lpc178x_irq.h
index 76c749045282f80dac2bf2be47d93fee0f991c99..52ed1731a5ceb6fa7af3c93ddaeb0b2fc13007bb 100644
--- a/arch/arm/include/lpc17xx/lpc178x_irq.h
+++ b/arch/arm/include/lpc17xx/lpc178x_irq.h
@@ -166,7 +166,7 @@
* 42
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
# define LPC17_VALID_GPIOINT0 (0xfffffffful) /* GPIO port 0 interrupt set */
# define LPC17_VALID_GPIOINT2 (0xfffffffful) /* GPIO port 2 interrupt set */
diff --git a/arch/arm/include/lpc214x/irq.h b/arch/arm/include/lpc214x/irq.h
index a4737c38d4bade9651ecb5304accf205dd9ae6bf..852dd0c6495f4dd1993c979bf523100b2170f650 100644
--- a/arch/arm/include/lpc214x/irq.h
+++ b/arch/arm/include/lpc214x/irq.h
@@ -37,8 +37,8 @@
* only indirectly through nuttx/irq.h
*/
-#ifndef __ARCH_LPC214X_IRQ_H
-#define __ARCH_LPC214X_IRQ_H
+#ifndef __ARCH_ARM_INCLUDE_LPC214X_IRQ_H
+#define __ARCH_ARM_INCLUDE_LPC214X_IRQ_H
/****************************************************************************
* Included Files
@@ -127,5 +127,5 @@ void up_detach_vector(int vector);
#endif
#endif
-#endif /* __ARCH_LPC214X_IRQ_H */
+#endif /* __ARCH_ARM_INCLUDE_LPC214X_IRQ_H */
diff --git a/arch/arm/include/lpc2378/irq.h b/arch/arm/include/lpc2378/irq.h
index 18ef58604b737fa269dc9dbba6febcf9dab137ba..8fa2067fc970ca1be862b1967ca2e02544a32758 100644
--- a/arch/arm/include/lpc2378/irq.h
+++ b/arch/arm/include/lpc2378/irq.h
@@ -43,8 +43,8 @@
* only indirectly through nuttx/irq.h
*/
-#ifndef __ARCH_LPC2378_IRQ_H
-#define __ARCH_LPC2378_IRQ_H
+#ifndef __ARCH_ARM_INCLUDE_LPC2378_IRQ_H
+#define __ARCH_ARM_INCLUDE_LPC2378_IRQ_H
/****************************************************************************
* Included Files
@@ -149,4 +149,4 @@ void up_detach_vector(int vector);
#endif
#endif
-#endif /* __ARCH_LPC2378_IRQ_H */
+#endif /* __ARCH_ARM_INCLUDE_LPC2378_IRQ_H */
diff --git a/arch/arm/include/samdl/samd20_irq.h b/arch/arm/include/samdl/samd20_irq.h
index 01361e8e00e5b8d9d7e9574fbdacf5b13deca5ee..709fddaeac891120c423746105fa696dcc3580e5 100644
--- a/arch/arm/include/samdl/samd20_irq.h
+++ b/arch/arm/include/samdl/samd20_irq.h
@@ -81,7 +81,7 @@
/* GPIO interrupts. Up to 16 pins may be configured to support interrupts */
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_SAMDL_GPIOIRQ
# define SAM_IRQ_EXTINT0 (SAM_IRQ_NIRQS+0) /* External interrupt 0 */
# define SAM_IRQ_EXTINT1 (SAM_IRQ_NIRQS+1) /* External interrupt 1 */
# define SAM_IRQ_EXTINT2 (SAM_IRQ_NIRQS+2) /* External interrupt 2 */
diff --git a/arch/arm/include/samdl/samd21_irq.h b/arch/arm/include/samdl/samd21_irq.h
index 2ea4db825795737185aeda5fdea09c6c10357645..7b5c633ef62bffe9675a20ced0096a3c5d75bcf3 100644
--- a/arch/arm/include/samdl/samd21_irq.h
+++ b/arch/arm/include/samdl/samd21_irq.h
@@ -88,7 +88,7 @@
/* GPIO interrupts. Up to 16 pins may be configured to support interrupts */
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_SAMDL_GPIOIRQ
# define SAM_IRQ_EXTINT0 (SAM_IRQ_NIRQS+0) /* External interrupt 0 */
# define SAM_IRQ_EXTINT1 (SAM_IRQ_NIRQS+1) /* External interrupt 1 */
# define SAM_IRQ_EXTINT2 (SAM_IRQ_NIRQS+2) /* External interrupt 2 */
diff --git a/arch/arm/include/samdl/saml21_irq.h b/arch/arm/include/samdl/saml21_irq.h
index 9622a0321523cc257ab1de0f09435cea89c86439..24c774dbd0f4421e56f97c5e1eedf73d4083d51d 100644
--- a/arch/arm/include/samdl/saml21_irq.h
+++ b/arch/arm/include/samdl/saml21_irq.h
@@ -89,7 +89,7 @@
/* GPIO interrupts. Up to 16 pins may be configured to support interrupts */
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_SAMDL_GPIOIRQ
# define SAM_IRQ_EXTINT0 (SAM_IRQ_NIRQS+0) /* External interrupt 0 */
# define SAM_IRQ_EXTINT1 (SAM_IRQ_NIRQS+1) /* External interrupt 1 */
# define SAM_IRQ_EXTINT2 (SAM_IRQ_NIRQS+2) /* External interrupt 2 */
diff --git a/arch/arm/src/a1x/a1x_serial.c b/arch/arm/src/a1x/a1x_serial.c
index a87c3d4ed3cb5609eb4663ba245093cf4a53648e..7dae40aa997d827feaba429f65fb27fef106f7cb 100644
--- a/arch/arm/src/a1x/a1x_serial.c
+++ b/arch/arm/src/a1x/a1x_serial.c
@@ -1192,7 +1192,7 @@ static int uart_interrupt(struct uart_dev_s *dev)
default:
{
- _llerr("ERROR: Unexpected IIR: %02x\n", status);
+ _err("ERROR: Unexpected IIR: %02x\n", status);
break;
}
}
diff --git a/arch/arm/src/arm/up_assert.c b/arch/arm/src/arm/up_assert.c
index 27788451dafe22d6a67ef5c32410a7fcbad03681..3d188174b3d3ea661b7d508ef738cbef6fb73761 100644
--- a/arch/arm/src/arm/up_assert.c
+++ b/arch/arm/src/arm/up_assert.c
@@ -151,7 +151,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
/* Let vsyslog do the real work */
va_start(ap, fmt);
- ret = lowvsyslog(LOG_INFO, fmt, ap);
+ ret = vsyslog(LOG_EMERG, fmt, ap);
va_end(ap);
return ret;
}
@@ -311,7 +311,7 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
struct tcb_s *rtcb = this_task();
#endif
diff --git a/arch/arm/src/arm/up_dataabort.c b/arch/arm/src/arm/up_dataabort.c
index 8cba1aa40606de1fa23431dcdeeb6391c02a8749..318c59232c46ab0464c2a6c3be1ec2885247cdf7 100644
--- a/arch/arm/src/arm/up_dataabort.c
+++ b/arch/arm/src/arm/up_dataabort.c
@@ -107,7 +107,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
* fatal error.
*/
- pgllinfo("FSR: %08x FAR: %08x\n", fsr, far);
+ pginfo("FSR: %08x FAR: %08x\n", fsr, far);
if ((fsr & FSR_MASK) != FSR_PAGE)
{
goto segfault;
@@ -118,7 +118,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
* (It has not yet been saved in the register context save area).
*/
- pgllinfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
+ pginfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
if (far < PG_PAGED_VBASE || far >= PG_PAGED_VEND)
{
goto segfault;
diff --git a/arch/arm/src/arm/up_prefetchabort.c b/arch/arm/src/arm/up_prefetchabort.c
index c6ec5cccb8118a570f437fef466bc93b19c4611c..ab97efd5737264712b8b8e4b20e68e35d7ad9f00 100644
--- a/arch/arm/src/arm/up_prefetchabort.c
+++ b/arch/arm/src/arm/up_prefetchabort.c
@@ -99,8 +99,8 @@ void up_prefetchabort(uint32_t *regs)
* virtual addresses.
*/
- pgllinfo("VADDR: %08x VBASE: %08x VEND: %08x\n",
- regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
+ pginfo("VADDR: %08x VBASE: %08x VEND: %08x\n",
+ regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
if (regs[REG_R15] >= PG_PAGED_VBASE && regs[REG_R15] < PG_PAGED_VEND)
{
diff --git a/arch/arm/src/arm/up_releasepending.c b/arch/arm/src/arm/up_releasepending.c
index d6d82573d60a5f1e7b170574c19fdc453a396d4c..c0ee7e6e727051e418f6e8638db3f8e9cbafe3ef 100644
--- a/arch/arm/src/arm/up_releasepending.c
+++ b/arch/arm/src/arm/up_releasepending.c
@@ -67,7 +67,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
- sllinfo("From TCB=%p\n", rtcb);
+ sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */
diff --git a/arch/arm/src/arm/up_reprioritizertr.c b/arch/arm/src/arm/up_reprioritizertr.c
index 18c79696e2acced003d565aa9b231a4d37b3dfe7..95679e31dd7276d9b11c1c24d8a8dfa25e7c1e1c 100644
--- a/arch/arm/src/arm/up_reprioritizertr.c
+++ b/arch/arm/src/arm/up_reprioritizertr.c
@@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
- sllinfo("TCB=%p PRI=%d\n", tcb, priority);
+ sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just
diff --git a/arch/arm/src/armv6-m/up_assert.c b/arch/arm/src/armv6-m/up_assert.c
index 93ff4a9f6fbc800896a1c2606d85232c2746c2cf..f218cd477b028866ec07d179ca4daeedda62f1a7 100644
--- a/arch/arm/src/armv6-m/up_assert.c
+++ b/arch/arm/src/armv6-m/up_assert.c
@@ -193,7 +193,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
/* Let vsyslog do the real work */
va_start(ap, fmt);
- ret = lowvsyslog(LOG_INFO, fmt, ap);
+ ret = vsyslog(LOG_EMERG, fmt, ap);
va_end(ap);
return ret;
}
@@ -366,7 +366,7 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
struct tcb_s *rtcb = this_task();
#endif
diff --git a/arch/arm/src/armv6-m/up_dumpnvic.c b/arch/arm/src/armv6-m/up_dumpnvic.c
index ba4974a0ac04f40c9fa5d38fd7ea7baf260998d1..8439ac6a2a91f7005ea86a5fe762fdf560dbce8b 100644
--- a/arch/arm/src/armv6-m/up_dumpnvic.c
+++ b/arch/arm/src/armv6-m/up_dumpnvic.c
@@ -72,27 +72,27 @@ void up_dumpnvic(FAR const char *msg)
flags = enter_critical_section();
- _llinfo("NVIC: %s\n", msg);
- _llinfo(" ISER: %08x ICER: %08x ISPR: %08x ICPR: %08x\n",
- getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER),
- getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
+ _info("NVIC: %s\n", msg);
+ _info(" ISER: %08x ICER: %08x ISPR: %08x ICPR: %08x\n",
+ getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER),
+ getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
for (i = 0 ; i < 8; i += 4)
{
- _llinfo(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n",
- i, getreg32(ARMV6M_NVIC_IPR(i)),
- i+1, getreg32(ARMV6M_NVIC_IPR(i+1)),
- i+2, getreg32(ARMV6M_NVIC_IPR(i+2)),
- i+3, getreg32(ARMV6M_NVIC_IPR(i+3)));
+ _info(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n",
+ i, getreg32(ARMV6M_NVIC_IPR(i)),
+ i+1, getreg32(ARMV6M_NVIC_IPR(i+1)),
+ i+2, getreg32(ARMV6M_NVIC_IPR(i+2)),
+ i+3, getreg32(ARMV6M_NVIC_IPR(i+3)));
}
- _llinfo("SYSCON:\n");
- _llinfo(" CPUID: %08x ICSR: %08x AIRCR: %08x SCR: %08x\n",
- getreg32(ARMV6M_SYSCON_CPUID), getreg32(ARMV6M_SYSCON_ICSR),
- getreg32(ARMV6M_SYSCON_AIRCR), getreg32(ARMV6M_SYSCON_SCR));
- _llinfo(" CCR: %08x SHPR2: %08x SHPR3: %08x\n",
- getreg32(ARMV6M_SYSCON_CCR), getreg32(ARMV6M_SYSCON_SHPR2),
- getreg32(ARMV6M_SYSCON_SHPR3));
+ _info("SYSCON:\n");
+ _info(" CPUID: %08x ICSR: %08x AIRCR: %08x SCR: %08x\n",
+ getreg32(ARMV6M_SYSCON_CPUID), getreg32(ARMV6M_SYSCON_ICSR),
+ getreg32(ARMV6M_SYSCON_AIRCR), getreg32(ARMV6M_SYSCON_SCR));
+ _info(" CCR: %08x SHPR2: %08x SHPR3: %08x\n",
+ getreg32(ARMV6M_SYSCON_CCR), getreg32(ARMV6M_SYSCON_SHPR2),
+ getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
#endif
diff --git a/arch/arm/src/armv6-m/up_releasepending.c b/arch/arm/src/armv6-m/up_releasepending.c
index 8c41277f8262072e7918943672cae6adf161c3f4..3c925a02b816280902308c6f314ef8baadc8dc9c 100644
--- a/arch/arm/src/armv6-m/up_releasepending.c
+++ b/arch/arm/src/armv6-m/up_releasepending.c
@@ -66,7 +66,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
- sllinfo("From TCB=%p\n", rtcb);
+ sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */
diff --git a/arch/arm/src/armv6-m/up_reprioritizertr.c b/arch/arm/src/armv6-m/up_reprioritizertr.c
index 1b91a105fba80d60479bdda410800d4d74cc5d3d..41f0c8700d33b9b6859c372b6a134087d4ed89e7 100644
--- a/arch/arm/src/armv6-m/up_reprioritizertr.c
+++ b/arch/arm/src/armv6-m/up_reprioritizertr.c
@@ -94,7 +94,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
- sllinfo("TCB=%p PRI=%d\n", tcb, priority);
+ sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just removed the head
diff --git a/arch/arm/src/armv6-m/up_svcall.c b/arch/arm/src/armv6-m/up_svcall.c
index 971b6d2c1e7a399713fe10019e982cd51645679a..1cd7e3a33b058a55747d143080c9610ae4fbc779 100644
--- a/arch/arm/src/armv6-m/up_svcall.c
+++ b/arch/arm/src/armv6-m/up_svcall.c
@@ -147,19 +147,19 @@ int up_svcall(int irq, FAR void *context)
if (cmd > SYS_switch_context)
# endif
{
- svcllinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
- svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
# ifdef CONFIG_BUILD_PROTECTED
- svcllinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
- regs[REG_XPSR], regs[REG_PRIMASK], regs[REG_EXC_RETURN]);
+ svcinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
+ regs[REG_XPSR], regs[REG_PRIMASK], regs[REG_EXC_RETURN]);
# else
- svcllinfo(" PSR: %08x PRIMASK: %08x\n",
- regs[REG_XPSR], regs[REG_PRIMASK]);
+ svcinfo(" PSR: %08x PRIMASK: %08x\n",
+ regs[REG_XPSR], regs[REG_PRIMASK]);
# endif
}
#endif
@@ -444,7 +444,7 @@ int up_svcall(int irq, FAR void *context)
regs[REG_R0] -= CONFIG_SYS_RESERVED;
#else
- svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
+ svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
#endif
}
break;
@@ -459,30 +459,30 @@ int up_svcall(int irq, FAR void *context)
if (regs != CURRENT_REGS)
# endif
{
- svcllinfo("SVCall Return:\n");
- svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
- CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
- CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
- CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
- svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
- CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
- CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
- CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
+ svcinfo("SVCall Return:\n");
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
+ CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
+ CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
+ CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
+ CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
+ CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
+ CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
#ifdef CONFIG_BUILD_PROTECTED
- svcllinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
- CURRENT_REGS[REG_EXC_RETURN]);
+ svcinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
+ CURRENT_REGS[REG_EXC_RETURN]);
#else
- svcllinfo(" PSR: %08x PRIMASK: %08x\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
+ svcinfo(" PSR: %08x PRIMASK: %08x\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
#endif
}
# ifdef CONFIG_DEBUG_SVCALL
else
{
- svcllinfo("SVCall Return: %d\n", regs[REG_R0]);
+ svcinfo("SVCall Return: %d\n", regs[REG_R0]);
}
# endif
#endif
diff --git a/arch/arm/src/armv7-a/arm_assert.c b/arch/arm/src/armv7-a/arm_assert.c
index bdeffa763cfced204b6bbf0282795bec2a9f909f..3c798d33a0d832f98753fb80496b695c51969b03 100644
--- a/arch/arm/src/armv7-a/arm_assert.c
+++ b/arch/arm/src/armv7-a/arm_assert.c
@@ -185,7 +185,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
/* Let vsyslog do the real work */
va_start(ap, fmt);
- ret = lowvsyslog(LOG_INFO, fmt, ap);
+ ret = vsyslog(LOG_EMERG, fmt, ap);
va_end(ap);
return ret;
}
@@ -372,7 +372,7 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
struct tcb_s *rtcb = this_task();
#endif
board_autoled_on(LED_ASSERTION);
diff --git a/arch/arm/src/armv7-a/arm_cpustart.c b/arch/arm/src/armv7-a/arm_cpustart.c
index 8df2ee95a23903e9e3cb1073c87519d81cb00b1b..88906a717ded5441a01f73310458fff480089ffc 100644
--- a/arch/arm/src/armv7-a/arm_cpustart.c
+++ b/arch/arm/src/armv7-a/arm_cpustart.c
@@ -64,19 +64,19 @@ static inline void arm_registerdump(FAR struct tcb_s *tcb)
{
int regndx;
- _llinfo("CPU%d:\n", up_cpu_index());
+ _info("CPU%d:\n", up_cpu_index());
/* Dump the startup registers */
for (regndx = REG_R0; regndx <= REG_R15; regndx += 8)
{
uint32_t *ptr = (uint32_t *)&tcb->xcp.regs[regndx];
- _llinfo("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regndx, ptr[0], ptr[1], ptr[2], ptr[3],
- ptr[4], ptr[5], ptr[6], ptr[7]);
+ _info("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regndx, ptr[0], ptr[1], ptr[2], ptr[3],
+ ptr[4], ptr[5], ptr[6], ptr[7]);
}
- _llinfo("CPSR: %08x\n", tcb->xcp.regs[REG_CPSR]);
+ _info("CPSR: %08x\n", tcb->xcp.regs[REG_CPSR]);
}
#else
# define arm_registerdump(tcb)
@@ -106,7 +106,7 @@ int arm_start_handler(int irq, FAR void *context)
{
FAR struct tcb_s *tcb;
- sllinfo("CPU%d Started\n", up_cpu_index());
+ sinfo("CPU%d Started\n", up_cpu_index());
/* Reset scheduler parameters */
@@ -155,7 +155,7 @@ int arm_start_handler(int irq, FAR void *context)
int up_cpu_start(int cpu)
{
- sllinfo("Starting CPU%d\n", cpu);
+ sinfo("Starting CPU%d\n", cpu);
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
diff --git a/arch/arm/src/armv7-a/arm_dataabort.c b/arch/arm/src/armv7-a/arm_dataabort.c
index 189b19639ef62777fa34271e12c32868a4626a97..50c95a20188001fd7013b49f8822ce9ec930d9bc 100644
--- a/arch/arm/src/armv7-a/arm_dataabort.c
+++ b/arch/arm/src/armv7-a/arm_dataabort.c
@@ -104,7 +104,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
* fatal error.
*/
- pgllinfo("DFSR: %08x DFAR: %08x\n", dfsr, dfar);
+ pginfo("DFSR: %08x DFAR: %08x\n", dfsr, dfar);
if ((dfsr & FSR_MASK) != FSR_PAGE)
{
goto segfault;
@@ -115,7 +115,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
* (It has not yet been saved in the register context save area).
*/
- pgllinfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
+ pginfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
if (dfar < PG_PAGED_VBASE || dfar >= PG_PAGED_VEND)
{
goto segfault;
diff --git a/arch/arm/src/armv7-a/arm_gicv2.c b/arch/arm/src/armv7-a/arm_gicv2.c
index b342c2fe8229f87121e3c7b6dc2165c1703fa951..e99eb540fdef6e55cd24f9c9cd30aeae5f380630 100644
--- a/arch/arm/src/armv7-a/arm_gicv2.c
+++ b/arch/arm/src/armv7-a/arm_gicv2.c
@@ -387,7 +387,7 @@ uint32_t *arm_decodeirq(uint32_t *regs)
regval = getreg32(GIC_ICCIAR);
irq = (regval & GIC_ICCIAR_INTID_MASK) >> GIC_ICCIAR_INTID_SHIFT;
- irqllinfo("irq=%d\n", irq);
+ irqinfo("irq=%d\n", irq);
/* Ignore spurions IRQs. ICCIAR will report 1023 if there is no pending
* interrupt.
diff --git a/arch/arm/src/armv7-a/arm_gicv2_dump.c b/arch/arm/src/armv7-a/arm_gicv2_dump.c
index c71ef444a32ea0f2723c7b2135920f46c62ade43..23e43738da24a1716663f518a2294a08c1306a4f 100644
--- a/arch/arm/src/armv7-a/arm_gicv2_dump.c
+++ b/arch/arm/src/armv7-a/arm_gicv2_dump.c
@@ -69,22 +69,22 @@
static inline void arm_gic_dump_cpu(bool all, int irq, int nlines)
{
- irqllinfo(" CPU Interface Registers:\n");
- irqllinfo(" ICR: %08x PMR: %08x BPR: %08x IAR: %08x\n",
- getreg32(GIC_ICCICR), getreg32(GIC_ICCPMR),
- getreg32(GIC_ICCBPR), getreg32(GIC_ICCIAR));
- irqllinfo(" RPR: %08x HPIR: %08x ABPR: %08x\n",
- getreg32(GIC_ICCRPR), getreg32(GIC_ICCHPIR),
- getreg32(GIC_ICCABPR));
- irqllinfo(" AIAR: %08x AHPIR: %08x IDR: %08x\n",
- getreg32(GIC_ICCAIAR), getreg32(GIC_ICCAHPIR),
- getreg32(GIC_ICCIDR));
- irqllinfo(" APR1: %08x APR2: %08x APR3: %08x APR4: %08x\n",
- getreg32(GIC_ICCAPR1), getreg32(GIC_ICCAPR2),
- getreg32(GIC_ICCAPR3), getreg32(GIC_ICCAPR4));
- irqllinfo(" NSAPR1: %08x NSAPR2: %08x NSAPR3: %08x NSAPR4: %08x\n",
- getreg32(GIC_ICCNSAPR1), getreg32(GIC_ICCNSAPR2),
- getreg32(GIC_ICCNSAPR3), getreg32(GIC_ICCNSAPR4));
+ irqinfo(" CPU Interface Registers:\n");
+ irqinfo(" ICR: %08x PMR: %08x BPR: %08x IAR: %08x\n",
+ getreg32(GIC_ICCICR), getreg32(GIC_ICCPMR),
+ getreg32(GIC_ICCBPR), getreg32(GIC_ICCIAR));
+ irqinfo(" RPR: %08x HPIR: %08x ABPR: %08x\n",
+ getreg32(GIC_ICCRPR), getreg32(GIC_ICCHPIR),
+ getreg32(GIC_ICCABPR));
+ irqinfo(" AIAR: %08x AHPIR: %08x IDR: %08x\n",
+ getreg32(GIC_ICCAIAR), getreg32(GIC_ICCAHPIR),
+ getreg32(GIC_ICCIDR));
+ irqinfo(" APR1: %08x APR2: %08x APR3: %08x APR4: %08x\n",
+ getreg32(GIC_ICCAPR1), getreg32(GIC_ICCAPR2),
+ getreg32(GIC_ICCAPR3), getreg32(GIC_ICCAPR4));
+ irqinfo(" NSAPR1: %08x NSAPR2: %08x NSAPR3: %08x NSAPR4: %08x\n",
+ getreg32(GIC_ICCNSAPR1), getreg32(GIC_ICCNSAPR2),
+ getreg32(GIC_ICCNSAPR3), getreg32(GIC_ICCNSAPR4));
}
/****************************************************************************
@@ -110,9 +110,9 @@ static void arm_gic_dumpregs(uintptr_t regaddr, int nlines, int incr)
incr <<= 2;
for (i = 0; i < nlines; i += incr, regaddr += 16)
{
- irqllinfo(" %08x %08x %08x %08x\n",
- getreg32(regaddr), getreg32(regaddr + 4),
- getreg32(regaddr + 8), getreg32(regaddr + 12));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(regaddr), getreg32(regaddr + 4),
+ getreg32(regaddr + 8), getreg32(regaddr + 12));
}
}
@@ -135,7 +135,7 @@ static void arm_gic_dumpregs(uintptr_t regaddr, int nlines, int incr)
static inline void arm_gic_dump4(const char *name, uintptr_t regaddr,
int nlines)
{
- irqllinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
+ irqinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 4);
}
@@ -158,7 +158,7 @@ static inline void arm_gic_dump4(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump8(const char *name, uintptr_t regaddr,
int nlines)
{
- irqllinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
+ irqinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 8);
}
@@ -181,7 +181,7 @@ static inline void arm_gic_dump8(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump16(const char *name, uintptr_t regaddr,
int nlines)
{
- irqllinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
+ irqinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 16);
}
@@ -204,7 +204,7 @@ static inline void arm_gic_dump16(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump32(const char *name, uintptr_t regaddr,
int nlines)
{
- irqllinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
+ irqinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 32);
}
@@ -226,10 +226,10 @@ static inline void arm_gic_dump32(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump_distributor(bool all, int irq, int nlines)
{
- irqllinfo(" Distributor Registers:\n");
- irqllinfo(" DCR: %08x ICTR: %08x IIDR: %08x\n",
- getreg32(GIC_ICDDCR), getreg32(GIC_ICDICTR),
- getreg32(GIC_ICDIIDR));
+ irqinfo(" Distributor Registers:\n");
+ irqinfo(" DCR: %08x ICTR: %08x IIDR: %08x\n",
+ getreg32(GIC_ICDDCR), getreg32(GIC_ICDICTR),
+ getreg32(GIC_ICDIIDR));
if (all)
{
@@ -246,27 +246,27 @@ static inline void arm_gic_dump_distributor(bool all, int irq, int nlines)
}
else
{
- irqllinfo(" ISR: %08x ISER: %08x ISPR: %08x SAR: %08x\n",
- getreg32(GIC_ICDISR(irq)), getreg32(GIC_ICDISER(irq)),
- getreg32(GIC_ICDISPR(irq)), getreg32(GIC_ICDSAR(irq)));
- irqllinfo(" IPR: %08x IPTR: %08x ICFR: %08x SPISR: %08x\n",
- getreg32(GIC_ICDIPR(irq)), getreg32(GIC_ICDIPTR(irq)),
- getreg32(GIC_ICDICFR(irq)), getreg32(GIC_ICDSPISR(irq)));
- irqllinfo(" NSACR: %08x SCPR: %08x\n",
- getreg32(GIC_ICDNSACR(irq)), getreg32(GIC_ICDSCPR(irq)));
+ irqinfo(" ISR: %08x ISER: %08x ISPR: %08x SAR: %08x\n",
+ getreg32(GIC_ICDISR(irq)), getreg32(GIC_ICDISER(irq)),
+ getreg32(GIC_ICDISPR(irq)), getreg32(GIC_ICDSAR(irq)));
+ irqinfo(" IPR: %08x IPTR: %08x ICFR: %08x SPISR: %08x\n",
+ getreg32(GIC_ICDIPR(irq)), getreg32(GIC_ICDIPTR(irq)),
+ getreg32(GIC_ICDICFR(irq)), getreg32(GIC_ICDSPISR(irq)));
+ irqinfo(" NSACR: %08x SCPR: %08x\n",
+ getreg32(GIC_ICDNSACR(irq)), getreg32(GIC_ICDSCPR(irq)));
}
- irqllinfo(" PIDR[%08lx]:\n", (unsigned long)GIC_ICDPIDR(0));
- irqllinfo(" %08x %08x %08x %08x\n",
- getreg32(GIC_ICDPIDR(0)), getreg32(GIC_ICDPIDR(1)),
- getreg32(GIC_ICDPIDR(2)), getreg32(GIC_ICDPIDR(3)));
- irqllinfo(" %08x %08x %08x %08x\n",
- getreg32(GIC_ICDPIDR(4)), getreg32(GIC_ICDPIDR(5)),
- getreg32(GIC_ICDPIDR(6)));
- irqllinfo(" CIDR[%08lx]:\n", (unsigned long)GIC_ICDCIDR(0));
- irqllinfo(" %08x %08x %08x %08x\n",
- getreg32(GIC_ICDCIDR(0)), getreg32(GIC_ICDCIDR(1)),
- getreg32(GIC_ICDCIDR(2)), getreg32(GIC_ICDCIDR(3)));
+ irqinfo(" PIDR[%08lx]:\n", (unsigned long)GIC_ICDPIDR(0));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(GIC_ICDPIDR(0)), getreg32(GIC_ICDPIDR(1)),
+ getreg32(GIC_ICDPIDR(2)), getreg32(GIC_ICDPIDR(3)));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(GIC_ICDPIDR(4)), getreg32(GIC_ICDPIDR(5)),
+ getreg32(GIC_ICDPIDR(6)));
+ irqinfo(" CIDR[%08lx]:\n", (unsigned long)GIC_ICDCIDR(0));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(GIC_ICDCIDR(0)), getreg32(GIC_ICDCIDR(1)),
+ getreg32(GIC_ICDCIDR(2)), getreg32(GIC_ICDCIDR(3)));
}
/****************************************************************************
@@ -295,11 +295,11 @@ void arm_gic_dump(const char *msg, bool all, int irq)
if (all)
{
- irqllinfo("GIC: %s NLINES=%u\n", msg, nlines);
+ irqinfo("GIC: %s NLINES=%u\n", msg, nlines);
}
else
{
- irqllinfo("GIC: %s IRQ=%d\n", msg, irq);
+ irqinfo("GIC: %s IRQ=%d\n", msg, irq);
}
arm_gic_dump_cpu(all, irq, nlines);
diff --git a/arch/arm/src/armv7-a/arm_prefetchabort.c b/arch/arm/src/armv7-a/arm_prefetchabort.c
index 898a6145aeb8760a45ce4cb5ee76db2da58aa5d4..0bb8cd37932f68ed9c101f5ad575b3a7f7f16f38 100644
--- a/arch/arm/src/armv7-a/arm_prefetchabort.c
+++ b/arch/arm/src/armv7-a/arm_prefetchabort.c
@@ -86,8 +86,8 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
* virtual addresses.
*/
- pgllinfo("VADDR: %08x VBASE: %08x VEND: %08x\n",
- regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
+ pginfo("VADDR: %08x VBASE: %08x VEND: %08x\n",
+ regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
if (regs[REG_R15] >= PG_PAGED_VBASE && regs[REG_R15] < PG_PAGED_VEND)
{
diff --git a/arch/arm/src/armv7-a/arm_releasepending.c b/arch/arm/src/armv7-a/arm_releasepending.c
index 5cabfe7a8b525fcd10451d4b84a8ccbe8298e63e..7afc6989a75829f647ee14ba35e2a6b3ef991415 100644
--- a/arch/arm/src/armv7-a/arm_releasepending.c
+++ b/arch/arm/src/armv7-a/arm_releasepending.c
@@ -67,7 +67,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
- sllinfo("From TCB=%p\n", rtcb);
+ sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */
diff --git a/arch/arm/src/armv7-a/arm_reprioritizertr.c b/arch/arm/src/armv7-a/arm_reprioritizertr.c
index d177510c85b484b0c8f92d832ea3872e85f66791..4381178e05b311e620c620b6d9465e10cec5a333 100644
--- a/arch/arm/src/armv7-a/arm_reprioritizertr.c
+++ b/arch/arm/src/armv7-a/arm_reprioritizertr.c
@@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
- sllinfo("TCB=%p PRI=%d\n", tcb, priority);
+ sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just
diff --git a/arch/arm/src/armv7-a/arm_syscall.c b/arch/arm/src/armv7-a/arm_syscall.c
index 0259acb5c6fa81ad90f473d878b8de38ec302ead..77b33b45f4be7954bc50389d3c3d8ccade7776eb 100644
--- a/arch/arm/src/armv7-a/arm_syscall.c
+++ b/arch/arm/src/armv7-a/arm_syscall.c
@@ -156,14 +156,14 @@ uint32_t *arm_syscall(uint32_t *regs)
* and R1..R7 = variable number of arguments depending on the system call.
*/
- svcllinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
- svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
- svcllinfo("CPSR: %08x\n", regs[REG_CPSR]);
+ svcinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
/* Handle the SVCall according to the command in R0 */
@@ -456,7 +456,7 @@ uint32_t *arm_syscall(uint32_t *regs)
regs[REG_R0] -= CONFIG_SYS_RESERVED;
#else
- svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
+ svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
@@ -479,14 +479,14 @@ uint32_t *arm_syscall(uint32_t *regs)
/* Report what happened */
- svcllinfo("SYSCALL Exit: regs: %p\n", regs);
- svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
- svcllinfo("CPSR: %08x\n", regs[REG_CPSR]);
+ svcinfo("SYSCALL Exit: regs: %p\n", regs);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
/* Return the last value of curent_regs. This supports context switches
* on return from the exception. That capability is only used with the
diff --git a/arch/arm/src/armv7-m/Kconfig b/arch/arm/src/armv7-m/Kconfig
index 406e2e46624be926494b130312a91d539bc3c02b..404dce07538ef771a6b176e8109dedf20fc6313e 100644
--- a/arch/arm/src/armv7-m/Kconfig
+++ b/arch/arm/src/armv7-m/Kconfig
@@ -160,6 +160,7 @@ config ARMV7M_STACKCHECK
config ARMV7M_ITMSYSLOG
bool "ITM SYSLOG support"
default n
+ select ARCH_SYSLOG
select SYSLOG
---help---
Enable hooks to support ITM syslog output. This requires additional
diff --git a/arch/arm/src/armv7-m/itm_syslog.h b/arch/arm/src/armv7-m/itm_syslog.h
index 1b42be2ea8e442ee412ebf9169103b7c8fa9f289..40f71624f57dad9714603f428ef48e839f0d843d 100644
--- a/arch/arm/src/armv7-m/itm_syslog.h
+++ b/arch/arm/src/armv7-m/itm_syslog.h
@@ -57,7 +57,7 @@
*
****************************************************************************/
-#if defined(CONFIG_SYSLOG) || defined(CONFIG_ARMV7M_ITMSYSLOG)
+#ifdef CONFIG_ARMV7M_ITMSYSLOG
void itm_syslog_initialize(void);
#else
# define itm_syslog_initialize()
diff --git a/arch/arm/src/armv7-m/up_assert.c b/arch/arm/src/armv7-m/up_assert.c
index eedfa522d81e72add68636805b442d8bcc917942..b34cfc73950343db2ab09940953f55a9daf14fab 100644
--- a/arch/arm/src/armv7-m/up_assert.c
+++ b/arch/arm/src/armv7-m/up_assert.c
@@ -198,7 +198,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
/* Let vsyslog do the real work */
va_start(ap, fmt);
- ret = lowvsyslog(LOG_INFO, fmt, ap);
+ ret = vsyslog(LOG_EMERG, fmt, ap);
va_end(ap);
return ret;
}
@@ -375,7 +375,7 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
struct tcb_s *rtcb = this_task();
#endif
diff --git a/arch/arm/src/armv7-m/up_itm_syslog.c b/arch/arm/src/armv7-m/up_itm_syslog.c
index 94b499879a79b9111a9225f50f6990a66e6059fb..d63fed09adb238e571c2cdd74f731759cb67e848 100644
--- a/arch/arm/src/armv7-m/up_itm_syslog.c
+++ b/arch/arm/src/armv7-m/up_itm_syslog.c
@@ -2,7 +2,7 @@
* arch/arm/src/armv7-m/up_itm_syslog.c
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- * Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
* Authors: Pierre-noel Bouteville
* Gregory Nutt
*
@@ -52,7 +52,7 @@
#include "up_arch.h"
#include "itm_syslog.h"
-#if defined(CONFIG_SYSLOG) || defined(CONFIG_ARMV7M_ITMSYSLOG)
+#ifdef CONFIG_ARMV7M_ITMSYSLOG
/****************************************************************************
* Pre-processor Definitions
@@ -72,6 +72,73 @@
# define CONFIG_ARMV7M_ITMSYSLOG_PORT 0
#endif
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* SYSLOG channel methods */
+
+static int itm_putc(int ch);
+static int itm_flush(void);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* This structure describes the ITM SYSLOG channel */
+
+static const struct syslog_channel_s g_itm_channel =
+{
+ .sc_putc = itm_putc,
+ .sc_force = itm_putc,
+ .sc_flush = itm_flush,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: itm_putc
+ *
+ * Description:
+ * This is the low-level system logging interface.
+ *
+ ****************************************************************************/
+
+static int itm_putc(int ch)
+{
+ /* ITM enabled */
+
+ if ((getreg32(ITM_TCR) & ITM_TCR_ITMENA_Msk) == 0)
+ {
+ return EOF;
+ }
+
+ /* ITM Port "CONFIG_ARMV7M_ITMSYSLOG_PORT" enabled */
+
+ if (getreg32(ITM_TER) & (1 << CONFIG_ARMV7M_ITMSYSLOG_PORT))
+ {
+ while (getreg32(ITM_PORT(CONFIG_ARMV7M_ITMSYSLOG_PORT)) == 0);
+ putreg8((uint8_t)ch, ITM_PORT(CONFIG_ARMV7M_ITMSYSLOG_PORT));
+ }
+
+ return ch;
+}
+
+/****************************************************************************
+ * Name: itm_flush
+ *
+ * Description:
+ * A dummy FLUSH method
+ *
+ ****************************************************************************/
+
+static int itm_flush(void)
+{
+ return OK;
+}
+
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -116,38 +183,10 @@ void itm_syslog_initialize(void)
putreg32(0x0001000d, ITM_TCR);
putreg32(0x00000100, TPI_FFCR);
putreg32(0xffffffff, ITM_TER); /* Enable 32 Ports */
-}
-/****************************************************************************
- * Name: syslog_putc
- *
- * Description:
- * This is the low-level system logging interface. The debugging/syslogging
- * interfaces are syslog() and lowsyslog(). The difference is that
- * the syslog() internface writes to fd=1 (stdout) whereas lowsyslog() uses
- * a lower level interface that works from interrupt handlers. This
- * function is the low-level interface used to implement lowsyslog().
- *
- ****************************************************************************/
+ /* Setup the SYSLOG channel */
-int syslog_putc(int ch)
-{
- /* ITM enabled */
-
- if ((getreg32(ITM_TCR) & ITM_TCR_ITMENA_Msk) == 0)
- {
- return EOF;
- }
-
- /* ITM Port "CONFIG_ARMV7M_ITMSYSLOG_PORT" enabled */
-
- if (getreg32(ITM_TER) & (1 << CONFIG_ARMV7M_ITMSYSLOG_PORT))
- {
- while (getreg32(ITM_PORT(CONFIG_ARMV7M_ITMSYSLOG_PORT)) == 0);
- putreg8((uint8_t)ch, ITM_PORT(CONFIG_ARMV7M_ITMSYSLOG_PORT));
- }
-
- return ch;
+ (void)syslog_channel(&g_itm_channel);
}
-#endif /* CONFIG_SYSLOG && CONFIG_ARMV7M_ITMSYSLOG */
+#endif /* CONFIG_ARMV7M_ITMSYSLOG */
diff --git a/arch/arm/src/armv7-m/up_releasepending.c b/arch/arm/src/armv7-m/up_releasepending.c
index 683a9864aaf53833d32d2a31abf83661ac9df794..83be88094e75072d3bc5c8020673c247465829cf 100644
--- a/arch/arm/src/armv7-m/up_releasepending.c
+++ b/arch/arm/src/armv7-m/up_releasepending.c
@@ -66,7 +66,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
- sllinfo("From TCB=%p\n", rtcb);
+ sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */
diff --git a/arch/arm/src/armv7-m/up_reprioritizertr.c b/arch/arm/src/armv7-m/up_reprioritizertr.c
index 845e7578e4a96b66d9b3e3abe6775c711021bb7b..5e65a3d33837b16d3928614b6fbd726d2009b34d 100644
--- a/arch/arm/src/armv7-m/up_reprioritizertr.c
+++ b/arch/arm/src/armv7-m/up_reprioritizertr.c
@@ -94,7 +94,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
- sllinfo("TCB=%p PRI=%d\n", tcb, priority);
+ sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just removed the head
diff --git a/arch/arm/src/armv7-m/up_svcall.c b/arch/arm/src/armv7-m/up_svcall.c
index 63f229a0481daffb09a8f039e579f6757a293e54..8e78de3a4329cfbb117dab28455b2f94922882ce 100644
--- a/arch/arm/src/armv7-m/up_svcall.c
+++ b/arch/arm/src/armv7-m/up_svcall.c
@@ -142,18 +142,18 @@ int up_svcall(int irq, FAR void *context)
if (cmd > SYS_switch_context)
# endif
{
- svcllinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
- svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
# ifdef REG_EXC_RETURN
- svcllinfo(" PSR: %08x EXC_RETURN: %08x\n",
- regs[REG_XPSR], regs[REG_EXC_RETURN]);
+ svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
+ regs[REG_XPSR], regs[REG_EXC_RETURN]);
# else
- svcllinfo(" PSR: %08x\n", regs[REG_XPSR]);
+ svcinfo(" PSR: %08x\n", regs[REG_XPSR]);
# endif
}
#endif
@@ -446,7 +446,7 @@ int up_svcall(int irq, FAR void *context)
regs[REG_R0] -= CONFIG_SYS_RESERVED;
#else
- svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
+ svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
#endif
}
break;
@@ -461,28 +461,28 @@ int up_svcall(int irq, FAR void *context)
if (regs != CURRENT_REGS)
# endif
{
- svcllinfo("SVCall Return:\n");
- svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
- CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
- CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
- CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
- svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
- CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
- CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
- CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
+ svcinfo("SVCall Return:\n");
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
+ CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
+ CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
+ CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
+ CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
+ CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
+ CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
# ifdef REG_EXC_RETURN
- svcllinfo(" PSR: %08x EXC_RETURN: %08x\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]);
+ svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]);
# else
- svcllinfo(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]);
+ svcinfo(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]);
# endif
}
# ifdef CONFIG_DEBUG_SVCALL
else
{
- svcllinfo("SVCall Return: %d\n", regs[REG_R0]);
+ svcinfo("SVCall Return: %d\n", regs[REG_R0]);
}
# endif
#endif
diff --git a/arch/arm/src/armv7-r/arm_assert.c b/arch/arm/src/armv7-r/arm_assert.c
index ccf011604574b5d066133582ba5142a8fcf80e72..b841416450be9d4b20e612b6d2fea91c4d305c6a 100644
--- a/arch/arm/src/armv7-r/arm_assert.c
+++ b/arch/arm/src/armv7-r/arm_assert.c
@@ -186,7 +186,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
/* Let vsyslog do the real work */
va_start(ap, fmt);
- ret = lowvsyslog(LOG_INFO, fmt, ap);
+ ret = vsyslog(LOG_EMERG, fmt, ap);
va_end(ap);
return ret;
}
@@ -367,7 +367,7 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
-#if CONFIG_TASK_NAME_SIZE > 0
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
struct tcb_s *rtcb = this_task();
#endif
board_autoled_on(LED_ASSERTION);
diff --git a/arch/arm/src/armv7-r/arm_doirq.c b/arch/arm/src/armv7-r/arm_doirq.c
index fdf392d3384d5ceab1b845f49c83b511221c0032..5d492f5ddc7efb134a332b74f2c98a712def7ec9 100644
--- a/arch/arm/src/armv7-r/arm_doirq.c
+++ b/arch/arm/src/armv7-r/arm_doirq.c
@@ -52,22 +52,6 @@
#include "group/group.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/arch/arm/src/armv7-r/arm_l2cc_pl310.c b/arch/arm/src/armv7-r/arm_l2cc_pl310.c
index d10e2051605526df82f4775a85c2ddf424cc6e95..18c3d224a2c6cbfb6e10d62007f55c42f3c0709f 100644
--- a/arch/arm/src/armv7-r/arm_l2cc_pl310.c
+++ b/arch/arm/src/armv7-r/arm_l2cc_pl310.c
@@ -411,7 +411,7 @@ void up_l2ccinitialize(void)
putreg32(L2CC_CR_L2CEN, L2CC_CR);
}
- sllinfo("(%d ways) * (%d bytes/way) = %d bytes\n",
+ sinfo("(%d ways) * (%d bytes/way) = %d bytes\n",
PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE);
}
diff --git a/arch/arm/src/armv7-r/arm_releasepending.c b/arch/arm/src/armv7-r/arm_releasepending.c
index 87fa34a3666feb044c173c14d7c8577bd1b3643c..a66de941356278880015b60eeeec25132b261cdf 100644
--- a/arch/arm/src/armv7-r/arm_releasepending.c
+++ b/arch/arm/src/armv7-r/arm_releasepending.c
@@ -67,7 +67,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
- sllinfo("From TCB=%p\n", rtcb);
+ sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */
diff --git a/arch/arm/src/armv7-r/arm_reprioritizertr.c b/arch/arm/src/armv7-r/arm_reprioritizertr.c
index af70900b3416acf44c4d2932e3e7c77ed7ad82fc..db96424eb2f4d6042c672334f327784d4fcecbee 100644
--- a/arch/arm/src/armv7-r/arm_reprioritizertr.c
+++ b/arch/arm/src/armv7-r/arm_reprioritizertr.c
@@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
- sllinfo("TCB=%p PRI=%d\n", tcb, priority);
+ sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just
diff --git a/arch/arm/src/armv7-r/arm_syscall.c b/arch/arm/src/armv7-r/arm_syscall.c
index 7d36ccb0d9ce4d38bc4cb077c91753af06b019b8..49290d5509ef138578d1f52f66b62982f21f17cf 100644
--- a/arch/arm/src/armv7-r/arm_syscall.c
+++ b/arch/arm/src/armv7-r/arm_syscall.c
@@ -154,14 +154,14 @@ uint32_t *arm_syscall(uint32_t *regs)
* and R1..R7 = variable number of arguments depending on the system call.
*/
- svcllinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
- svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
- svcllinfo("CPSR: %08x\n", regs[REG_CPSR]);
+ svcinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
/* Handle the SVCall according to the command in R0 */
@@ -454,7 +454,7 @@ uint32_t *arm_syscall(uint32_t *regs)
regs[REG_R0] -= CONFIG_SYS_RESERVED;
#else
- svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
+ svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
@@ -477,14 +477,14 @@ uint32_t *arm_syscall(uint32_t *regs)
/* Report what happened */
- svcllinfo("SYSCALL Exit: regs: %p\n", regs);
- svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
- svcllinfo("CPSR: %08x\n", regs[REG_CPSR]);
+ svcinfo("SYSCALL Exit: regs: %p\n", regs);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
/* Return the last value of curent_regs. This supports context switches
* on return from the exception. That capability is only used with the
diff --git a/arch/arm/src/c5471/c5471_ethernet.c b/arch/arm/src/c5471/c5471_ethernet.c
index 8d08b48e4a4c7b6debd8efb2437b83b1e9e52037..b7563aa0545b5909eb66f29080f050120a840245 100644
--- a/arch/arm/src/c5471/c5471_ethernet.c
+++ b/arch/arm/src/c5471/c5471_ethernet.c
@@ -1267,7 +1267,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllinfo("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@@ -1310,7 +1310,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllinfo("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@@ -2241,7 +2241,7 @@ void up_netinitialize(void)
{
/* We could not attach the ISR to the ISR */
- nllerr("ERROR: irq_attach() failed\n");
+ nerr("ERROR: irq_attach() failed\n");
return;
}
diff --git a/arch/arm/src/c5471/c5471_watchdog.c b/arch/arm/src/c5471/c5471_watchdog.c
index 0329d7057c73f9d8b1bcb25465d733ac4707d07c..d1381f45d46d217e635fe48cfc751bf6a1c2fc65 100644
--- a/arch/arm/src/c5471/c5471_watchdog.c
+++ b/arch/arm/src/c5471/c5471_watchdog.c
@@ -234,17 +234,17 @@ static int wdt_setusec(uint32_t usec)
static int wdt_interrupt(int irq, void *context)
{
- wdllinfo("expired\n");
+ wdinfo("expired\n");
#if defined(CONFIG_SOFTWARE_REBOOT)
# if defined(CONFIG_SOFTWARE_TEST)
- wdllinfo(" Test only\n");
+ wdinfo(" Test only\n");
# else
- wdllinfo(" Re-booting\n");
+ wdinfo(" Re-booting\n");
# warning "Add logic to reset CPU here"
# endif
#else
- wdllinfo(" No reboot\n");
+ wdinfo(" No reboot\n");
#endif
return OK;
}
diff --git a/arch/arm/src/c5471/chip.h b/arch/arm/src/c5471/chip.h
index 580ae075dcd6a8fef32e505b78ef45e2cd249253..e1f40e58d3e9999a08b232b58e0c5787cbc4e561 100644
--- a/arch/arm/src/c5471/chip.h
+++ b/arch/arm/src/c5471/chip.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * c5471/chip.h
+ * arch/arm/src/c5471/chip.h
*
* Copyright (C) 2007 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef __C5471_CHIP_H
-#define __C5471_CHIP_H
+#ifndef __ARCH_ARM_SRC_C5471_CHIP_H
+#define __ARCH_ARM_SRC_C5471_CHIP_H
/****************************************************************************
* Included Files
@@ -368,4 +368,4 @@
* Public Function Prototypes
****************************************************************************/
-#endif /* __C5471_CHIP_H */
+#endif /* __ARCH_ARM_SRC_C5471_CHIP_H */
diff --git a/arch/arm/src/calypso/chip.h b/arch/arm/src/calypso/chip.h
index 824fdce8935f609f55780cba31853a8859373972..bea381cc385a082fd86bb136b02e84aaa6b5615a 100644
--- a/arch/arm/src/calypso/chip.h
+++ b/arch/arm/src/calypso/chip.h
@@ -37,8 +37,8 @@
*
****************************************************************************/
-#ifndef __CALYPSO_CHIP_H
-#define __CALYPSO_CHIP_H
+#ifndef __ARCH_ARM_SRC_CALYPSO_CHIP_H
+#define __ARCH_ARM_SRC_CALYPSO_CHIP_H
/****************************************************************************
* Included Files
@@ -208,4 +208,4 @@
* Public Function Prototypes
****************************************************************************/
-#endif /* __CALYPSO_CHIP_H */
+#endif /* __ARCH_ARM_SRC_CALYPSO_CHIP_H */
diff --git a/arch/arm/src/common/up_checkstack.c b/arch/arm/src/common/up_checkstack.c
index 55f89388e3ee983d72ce5ccabdf23acb71677733..f6b4034cbcb588c62a5e1d970d956c5573b9667d 100644
--- a/arch/arm/src/common/up_checkstack.c
+++ b/arch/arm/src/common/up_checkstack.c
@@ -84,7 +84,13 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size)
FAR uint32_t *ptr;
size_t mark;
+ if (size == 0)
+ {
+ return 0;
+ }
+
/* Get aligned addresses of the top and bottom of the stack */
+
#ifdef CONFIG_TLS
/* Skip over the TLS data structure at the bottom of the stack */
@@ -122,7 +128,8 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size)
#if 0
if (mark + 16 > nwords)
{
- int i, j;
+ int i;
+ int j;
ptr = (FAR uint32_t *)start;
for (i = 0; i < size; i += 4*64)
diff --git a/arch/arm/src/common/up_exit.c b/arch/arm/src/common/up_exit.c
index 4df8bf3463129f150ed7f8264f0d12382b4bf0d5..4d16f2a8a55c2c0fe8ebf12b55c6fe61118f316c 100644
--- a/arch/arm/src/common/up_exit.c
+++ b/arch/arm/src/common/up_exit.c
@@ -146,10 +146,10 @@ void _exit(int status)
(void)up_irq_save();
- sllinfo("TCB=%p exiting\n", this_task());
+ sinfo("TCB=%p exiting\n", this_task());
#ifdef CONFIG_DUMP_ON_EXIT
- sllinfo("Other tasks:\n");
+ sinfo("Other tasks:\n");
sched_foreach(_up_dumponexit, NULL);
#endif
diff --git a/arch/arm/src/common/up_initialize.c b/arch/arm/src/common/up_initialize.c
index f926b7f0381de1057b1d61c16edf5d1a02319706..a97cd40a92e2c56755f8e5aec229472e765d7dfd 100644
--- a/arch/arm/src/common/up_initialize.c
+++ b/arch/arm/src/common/up_initialize.c
@@ -44,14 +44,16 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
#include
-#include
+#include
#include
+#include
#include
+#include
#include
@@ -77,13 +79,13 @@ static void up_calibratedelay(void)
{
int i;
- _llwarn("Beginning 100s delay\n");
+ _warn("Beginning 100s delay\n");
for (i = 0; i < 100; i++)
{
up_mdelay(1000);
}
- _llwarn("End 100s delay\n");
+ _warn("End 100s delay\n");
}
#else
# define up_calibratedelay()
@@ -158,21 +160,21 @@ void up_initialize(void)
up_irqinitialize();
+#ifdef CONFIG_PM
/* Initialize the power management subsystem. This MCU-specific function
* must be called *very* early in the initialization sequence *before* any
* other device drivers are initialized (since they may attempt to register
* with the power management subsystem).
*/
-#ifdef CONFIG_PM
up_pminitialize();
#endif
+#ifdef CONFIG_ARCH_DMA
/* Initialize the DMA subsystem if the weak function up_dmainitialize has been
* brought into the build
*/
-#ifdef CONFIG_ARCH_DMA
#ifdef CONFIG_HAVE_WEAKFUNCTIONS
if (up_dmainitialize)
#endif
@@ -196,6 +198,14 @@ void up_initialize(void)
devnull_register(); /* Standard /dev/null */
#endif
+#if defined(CONFIG_DEV_RANDOM)
+ devrandom_register(); /* Standard /dev/random */
+#endif
+
+#if defined(CONFIG_DEV_URANDOM)
+ devurandom_register(); /* Standard /dev/urandom */
+#endif
+
#if defined(CONFIG_DEV_ZERO)
devzero_register(); /* Standard /dev/zero */
#endif
@@ -222,37 +232,33 @@ void up_initialize(void)
#if defined(CONFIG_DEV_LOWCONSOLE)
lowconsole_init();
-#elif defined(CONFIG_SYSLOG_CONSOLE)
+#elif defined(CONFIG_CONSOLE_SYSLOG)
syslog_console_init();
#elif defined(CONFIG_RAMLOG_CONSOLE)
ramlog_consoleinit();
#endif
- /* Initialize the HW crypto and /dev/crypto */
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_PSEUDOTERM_SUSV1)
+ /* Register the master pseudo-terminal multiplexor device */
-#if defined(CONFIG_CRYPTO)
- up_cryptoinitialize();
+ (void)ptmx_register();
#endif
-#if CONFIG_NFILE_DESCRIPTORS > 0
-#if defined(CONFIG_CRYPTO_CRYPTODEV)
- devcrypto_register();
-#endif
-#endif
-
- /* Initialize the Random Number Generator (RNG) */
+ /* Early initialization of the system logging device. Some SYSLOG channel
+ * can be initialized early in the initialization sequence because they
+ * depend on only minimal OS initialization.
+ */
-#ifdef CONFIG_DEV_RANDOM
- up_rnginitialize();
-#endif
+ syslog_initialize(SYSLOG_INIT_EARLY);
- /* Initialize the system logging device */
+#if defined(CONFIG_CRYPTO)
+ /* Initialize the HW crypto and /dev/crypto */
-#ifdef CONFIG_SYSLOG_CHAR
- syslog_initialize();
+ up_cryptoinitialize();
#endif
-#ifdef CONFIG_RAMLOG_SYSLOG
- ramlog_sysloginit();
+
+#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_CRYPTO_CRYPTODEV)
+ devcrypto_register();
#endif
#ifndef CONFIG_NETDEV_LATEINIT
diff --git a/arch/arm/src/common/up_internal.h b/arch/arm/src/common/up_internal.h
index af3da01e5e96fb54a1723598a69031a33864cbb8..36095a87a45b9f10bcc6732bb06607408383ef9c 100644
--- a/arch/arm/src/common/up_internal.h
+++ b/arch/arm/src/common/up_internal.h
@@ -101,13 +101,6 @@
# define USE_SERIALDRIVER 1
#endif
-/* Determine which device to use as the system logging device */
-
-#ifndef CONFIG_SYSLOG
-# undef CONFIG_SYSLOG_CHAR
-# undef CONFIG_RAMLOG_SYSLOG
-#endif
-
/* Check if an interrupt stack size is configured */
#ifndef CONFIG_ARCH_INTERRUPTSTACK
@@ -552,12 +545,6 @@ void up_usbuninitialize(void);
# define up_usbuninitialize()
#endif
-/* Random Number Generator (RNG) ********************************************/
-
-#ifdef CONFIG_DEV_RANDOM
-void up_rnginitialize(void);
-#endif
-
/* Debug ********************************************************************/
#ifdef CONFIG_STACK_COLORATION
void up_stack_color(FAR void *stackbase, size_t nbytes);
diff --git a/arch/arm/src/dm320/chip.h b/arch/arm/src/dm320/chip.h
index 73e53b68317bc91e2cac994345a12ced92f3d117..20c722ab6a1e93c937833babf60d864aa003a5f5 100644
--- a/arch/arm/src/dm320/chip.h
+++ b/arch/arm/src/dm320/chip.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __DM320_CHIP_H
-#define __DM320_CHIP_H
+#ifndef __ARCH_ARM_SRC_DM320_CHIP_H
+#define __ARCH_ARM_SRC_DM320_CHIP_H
/************************************************************************************
* Included Files
@@ -58,4 +58,4 @@
* Inline Functions
************************************************************************************/
-#endif /* __DM320_CHIP_H */
+#endif /* __ARCH_ARM_SRC_DM320_CHIP_H */
diff --git a/arch/arm/src/dm320/dm320_decodeirq.c b/arch/arm/src/dm320/dm320_decodeirq.c
index 5d36a6bdc65685f41bc4bdb50e6710b3d82b6071..5d7e709588192ac5e9ad2f0dd0b3aa61e2cbf64e 100644
--- a/arch/arm/src/dm320/dm320_decodeirq.c
+++ b/arch/arm/src/dm320/dm320_decodeirq.c
@@ -51,22 +51,6 @@
#include "group/group.h"
-/********************************************************************************
- * Pre-processor Definitions
- ********************************************************************************/
-
-/********************************************************************************
- * Public Data
- ********************************************************************************/
-
-/********************************************************************************
- * Private Data
- ********************************************************************************/
-
-/********************************************************************************
- * Private Functions
- ********************************************************************************/
-
/********************************************************************************
* Public Functions
********************************************************************************/
@@ -74,8 +58,8 @@
void up_decodeirq(uint32_t *regs)
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
- lowsyslog(LOG_ERR, "Unexpected IRQ\n");
CURRENT_REGS = regs;
+ err("ERROR: Unexpected IRQ\n");
PANIC();
#else
/* Decode the interrupt. First, fetch the interrupt id register. */
diff --git a/arch/arm/src/dm320/dm320_emif.h b/arch/arm/src/dm320/dm320_emif.h
index 653e20fe0d5532f4970971a19b48e8e653e0630f..72d4e8947dc5d29d88f91016da5622ac8ca4cf4a 100644
--- a/arch/arm/src/dm320/dm320_emif.h
+++ b/arch/arm/src/dm320/dm320_emif.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __DM320_DM320_EMIF_H
-#define __DM320_DM320_EMIF_H
+#ifndef __ARCH_ARM_SRC_DM320_DM320_EMIF_H
+#define __ARCH_ARM_SRC_DM320_DM320_EMIF_H
/************************************************************************************
* Included Files
@@ -105,4 +105,4 @@
#endif
-#endif /* __DM320_DM320_EMIF_H */
+#endif /* __ARCH_ARM_SRC_DM320_DM320_EMIF_H */
diff --git a/arch/arm/src/dm320/dm320_gio.h b/arch/arm/src/dm320/dm320_gio.h
index 136e96118ce096717dda1ae61ba41fe3dbecd496..5c0fdc73c3b9f9efa0f740cda30ca9e4dd2d4fbd 100644
--- a/arch/arm/src/dm320/dm320_gio.h
+++ b/arch/arm/src/dm320/dm320_gio.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __DM320_DM320GIO_H
-#define __DM320_DM320GIO_H
+#ifndef __ARCH_ARM_SRC_DM320_DM320_GIO_H
+#define __ARCH_ARM_SRC_DM320_DM320_GIO_H
/************************************************************************************
* Included Files
diff --git a/arch/arm/src/dm320/dm320_intc.h b/arch/arm/src/dm320/dm320_intc.h
index f05febb2f953ac5a118f0e6e5f23da64700cf27c..57bc5c1f346d0e90bbaa54f3e133a3dd9f5052f0 100644
--- a/arch/arm/src/dm320/dm320_intc.h
+++ b/arch/arm/src/dm320/dm320_intc.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __DM320_DM320_INTC_H
-#define __DM320_DM320_INTC_H
+#ifndef __ARCH_ARM_SRC_DM320_DM320_INTC_H
+#define __ARCH_ARM_SRC_DM320_DM320_INTC_H
/************************************************************************************
* Included Files
@@ -98,4 +98,4 @@
#endif
-#endif /* __DM320_DM320_INTC_H */
+#endif /* __ARCH_ARM_SRC_DM320_DM320_INTC_H */
diff --git a/arch/arm/src/dm320/dm320_memorymap.h b/arch/arm/src/dm320/dm320_memorymap.h
index 67923b1507403702bb105d53b86f023431882150..a5db5963615fee61d2d1a6807db12962c9e1dff5 100644
--- a/arch/arm/src/dm320/dm320_memorymap.h
+++ b/arch/arm/src/dm320/dm320_memorymap.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __DM320_MEMORYMAP_H
-#define __DM320_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_DM320_DM320_MEMORYMAP_H
+#define __ARCH_ARM_SRC_DM320_DM320_MEMORYMAP_H
/************************************************************************************
* Included Files
@@ -261,4 +261,4 @@
#endif
-#endif /* __DM320_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_DM320_DM320_MEMORYMAP_H */
diff --git a/arch/arm/src/dm320/dm320_timer.h b/arch/arm/src/dm320/dm320_timer.h
index 2ef40790673b0e4e2a90cc2f6bf2641973d14c5e..5b1830b98c7f975f6d486509179942f69a5ad085 100644
--- a/arch/arm/src/dm320/dm320_timer.h
+++ b/arch/arm/src/dm320/dm320_timer.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __DM320_TIMER_H
-#define __DM320_TIMER_H
+#ifndef __ARCH_ARM_SRC_DM320_DM320_TIMER_H
+#define __ARCH_ARM_SRC_DM320_DM320_TIMER_H
/************************************************************************************
* Included Files
@@ -105,4 +105,4 @@
#endif
-#endif /* __DM320_TIMER_H */
+#endif /* __ARCH_ARM_SRC_DM320_DM320_TIMER_H */
diff --git a/arch/arm/src/dm320/dm320_uart.h b/arch/arm/src/dm320/dm320_uart.h
index d668489412075518199c52a170475331f8e97dfd..af9c1df91f8ff4001dd187c3194681e9d4a6661e 100644
--- a/arch/arm/src/dm320/dm320_uart.h
+++ b/arch/arm/src/dm320/dm320_uart.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __DM320_UART_H
-#define __DM320_UART_H
+#ifndef __ARCH_ARM_SRC_DM320_DM320_UART_H
+#define __ARCH_ARM_SRC_DM320_DM320_UART_H
/************************************************************************************
* Included Files
@@ -173,4 +173,4 @@
* Inline Functions
************************************************************************************/
-#endif /* __DM320_UART_H */
+#endif /* __ARCH_ARM_SRC_DM320_DM320_UART_H */
diff --git a/arch/arm/src/dm320/dm320_usbdev.c b/arch/arm/src/dm320/dm320_usbdev.c
index 673eba7e4bbf02b6b15ac64bc42e96475d813f69..df25123b09ec08ed7062a6572bd1448877386802 100644
--- a/arch/arm/src/dm320/dm320_usbdev.c
+++ b/arch/arm/src/dm320/dm320_usbdev.c
@@ -443,7 +443,7 @@ static uint8_t dm320_getreg8(uint32_t addr)
{
if (count == 4)
{
- ullinfo("...\n");
+ uinfo("...\n");
}
return val;
@@ -460,7 +460,7 @@ static uint8_t dm320_getreg8(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- ullinfo("[repeats %d more times]\n", count-3);
+ uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -472,7 +472,7 @@ static uint8_t dm320_getreg8(uint32_t addr)
/* Show the register value read */
- ullinfo("%08x->%02x\n", addr, val);
+ uinfo("%08x->%02x\n", addr, val);
return val;
}
#endif
@@ -506,7 +506,7 @@ static uint32_t dm320_getreg16(uint32_t addr)
{
if (count == 4)
{
- ullinfo("...\n");
+ uinfo("...\n");
}
return val;
@@ -523,7 +523,7 @@ static uint32_t dm320_getreg16(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- ullinfo("[repeats %d more times]\n", count-3);
+ uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -535,7 +535,7 @@ static uint32_t dm320_getreg16(uint32_t addr)
/* Show the register value read */
- ullinfo("%08x->%04x\n", addr, val);
+ uinfo("%08x->%04x\n", addr, val);
return val;
}
#endif
@@ -569,7 +569,7 @@ static uint32_t dm320_getreg32(uint32_t addr)
{
if (count == 4)
{
- ullinfo("...\n");
+ uinfo("...\n");
}
return val;
@@ -586,7 +586,7 @@ static uint32_t dm320_getreg32(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- ullinfo("[repeats %d more times]\n", count-3);
+ uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -598,7 +598,7 @@ static uint32_t dm320_getreg32(uint32_t addr)
/* Show the register value read */
- ullinfo("%08x->%08x\n", addr, val);
+ uinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@@ -616,7 +616,7 @@ static void dm320_putreg8(uint8_t val, uint32_t addr)
{
/* Show the register value being written */
- ullinfo("%08x<-%02x\n", addr, val);
+ uinfo("%08x<-%02x\n", addr, val);
/* Write the value */
@@ -637,7 +637,7 @@ static void dm320_putreg16(uint16_t val, uint32_t addr)
{
/* Show the register value being written */
- ullinfo("%08x<-%04x\n", addr, val);
+ uinfo("%08x<-%04x\n", addr, val);
/* Write the value */
@@ -658,7 +658,7 @@ static void dm320_putreg32(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- ullinfo("%08x<-%08x\n", addr, val);
+ uinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@@ -1216,8 +1216,8 @@ static inline void dm320_ep0setup(struct dm320_usbdev_s *priv)
value = GETUINT16(ctrl.value);
len = GETUINT16(ctrl.len);
- ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- ctrl.type, ctrl.req, value, index, len);
+ uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ ctrl.type, ctrl.req, value, index, len);
/* Dispatch any non-standard requests */
@@ -1618,7 +1618,7 @@ static int dm320_ctlrinterrupt(int irq, FAR void *context)
}
else
{
- ullinfo("Pending data on OUT endpoint\n");
+ uinfo("Pending data on OUT endpoint\n");
priv->rxpending = 1;
}
}
@@ -2417,7 +2417,7 @@ void up_usbinitialize(void)
#ifdef CONFIG_DEBUG_USB_INFO
chiprev = dm320_getreg16(DM320_BUSC_REVR);
- ullinfo("DM320 revision : %d.%d\n", chiprev >> 4, chiprev & 0x0f);
+ uinfo("DM320 revision : %d.%d\n", chiprev >> 4, chiprev & 0x0f);
#endif
/* Enable USB clock & GIO clock */
diff --git a/arch/arm/src/efm32/efm32_adc.c b/arch/arm/src/efm32/efm32_adc.c
index 20deacf2bc1f766a40d4a49adeaada48d902244f..c9e339e6ea27e8495b2eafddd16892bb0cf14873 100644
--- a/arch/arm/src/efm32/efm32_adc.c
+++ b/arch/arm/src/efm32/efm32_adc.c
@@ -1191,7 +1191,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
adcsr = adc_getreg(priv, EFM32_ADC_SR_OFFSET);
if ((adcsr & ADC_SR_AWD) != 0)
{
- allwarn("WARNING: Analog Watchdog, Value converted out of range!\n");
+ awarn("WARNING: Analog Watchdog, Value converted out of range!\n");
}
/* EOC: End of conversion */
diff --git a/arch/arm/src/efm32/efm32_clockconfig.c b/arch/arm/src/efm32/efm32_clockconfig.c
index d59740781189b99663b08fa87c1fad7d8cfc4ca8..aeef784326b1d08107ce811c7946921d42de39c9 100644
--- a/arch/arm/src/efm32/efm32_clockconfig.c
+++ b/arch/arm/src/efm32/efm32_clockconfig.c
@@ -884,7 +884,7 @@ static inline void efm32_gpioclock(void)
*
****************************************************************************/
-#if defined(CONFIG_SYSLOG) || defined(CONFIG_ARMV7M_ITMSYSLOG)
+#ifdef CONFIG_ARMV7M_ITMSYSLOG
static inline void efm32_itm_syslog(void)
{
int regval;
@@ -909,9 +909,6 @@ static inline void efm32_itm_syslog(void)
efm32_enable_auxhfrco();
- /* Then perform ARMv7-M ITM SYSLOG initialization */
-
- itm_syslog_initialize();
}
#else
# define efm32_itm_syslog()
diff --git a/arch/arm/src/efm32/efm32_config.h b/arch/arm/src/efm32/efm32_config.h
index b60c3a60e4dcb267198c7bd710df888e5c5937fe..f0bf6335d96aa4f9eb6171cc499352bec686af34 100644
--- a/arch/arm/src/efm32/efm32_config.h
+++ b/arch/arm/src/efm32/efm32_config.h
@@ -127,7 +127,7 @@
#undef HAVE_UART_CONSOLE
#undef HAVE_LEUART_CONSOLE
-#if defined(CONFIG_SYSLOG_CONSOLE)
+#if defined(CONFIG_CONSOLE_SYSLOG)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_UART0_SERIAL_CONSOLE
diff --git a/arch/arm/src/efm32/efm32_dma.c b/arch/arm/src/efm32/efm32_dma.c
index 667773232136976993cd056c521751e94ac633b1..4bf901500b604b5498b2f9bdbef98625c4dc0f97 100644
--- a/arch/arm/src/efm32/efm32_dma.c
+++ b/arch/arm/src/efm32/efm32_dma.c
@@ -270,7 +270,7 @@ void weak_function up_dmainitialize(void)
uint32_t regval;
int i;
- dmallinfo("Initialize XDMAC0\n");
+ dmainfo("Initialize XDMAC0\n");
/* Initialize the channel list */
diff --git a/arch/arm/src/efm32/efm32_idle.c b/arch/arm/src/efm32/efm32_idle.c
index b5a2278a1a21c33ae18df287359b1e3a2acad0ef..9a6d9f7e155142fa1a099ec3627a862514c377cf 100644
--- a/arch/arm/src/efm32/efm32_idle.c
+++ b/arch/arm/src/efm32/efm32_idle.c
@@ -110,7 +110,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
- _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
+ _info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
diff --git a/arch/arm/src/efm32/efm32_irq.c b/arch/arm/src/efm32/efm32_irq.c
index 63fa4b18ec7bc2e873cfeb0a8a91215691797480..db5992dea7b57f620fbbfb75c7e815a2a947db12 100644
--- a/arch/arm/src/efm32/efm32_irq.c
+++ b/arch/arm/src/efm32/efm32_irq.c
@@ -93,10 +93,6 @@ volatile uint32_t *g_current_regs[1];
extern uint32_t _vectors[];
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -251,61 +247,19 @@ static inline void efm32_prioritize_syscall(int priority)
static int efm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
+ int n;
+
DEBUGASSERT(irq >= EFM32_IRQ_NMI && irq < NR_IRQS);
- /* Check for external interrupt or (a second level GPIO interrupt) */
+ /* Check for external interrupt or a second level GPIO interrupt */
if (irq >= EFM32_IRQ_INTERRUPTS)
{
- /* Is this an external interrupt? */
-
if (irq < NR_VECTORS)
{
- /* Yes.. We have support implemented for vectors 0-95 */
-
- DEBUGASSERT(irq < (EFM32_IRQ_INTERRUPTS + 96));
-
-#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 32)
- /* Check for vectors 0-31 */
-
- if (irq < EFM32_IRQ_INTERRUPTS + 32)
-#endif
- {
- *regaddr = (NVIC_IRQ0_31_ENABLE + offset);
- *bit = 1 << (irq - EFM32_IRQ_INTERRUPTS);
- }
-#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 32)
- /* Yes.. Check for vectors 32-63 */
-
- else
-#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 64)
- if (irq < EFM32_IRQ_INTERRUPTS + 64)
-#endif
- {
- *regaddr = (NVIC_IRQ32_63_ENABLE + offset);
- *bit = 1 << (irq - EFM32_IRQ_INTERRUPTS - 32);
- }
-#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 64)
- /* Yes.. Check for vectors 64-95 */
-
- else
-#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 96)
- /* Yes.. Check for vectors 64-95 */
-
- if (irq < NR_VECTORS)
-#endif
- {
- *regaddr = (NVIC_IRQ64_95_ENABLE + offset);
- *bit = 1 << (irq - EFM32_IRQ_INTERRUPTS - 64);
- }
-#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 96)
- else
- {
- return -EINVAL; /* We should never get here */
- }
-#endif
-#endif
-#endif
+ n = irq - EFM32_IRQ_INTERRUPTS;
+ *regaddr = NVIC_IRQ_ENABLE(n) + offset;
+ *bit = (uint32_t)1 << (n & 0x1f);
}
else
{
@@ -356,16 +310,14 @@ void up_irqinitialize(void)
{
uint32_t regaddr;
int num_priority_registers;
+ int i;
/* Disable all interrupts */
- putreg32(0, NVIC_IRQ0_31_ENABLE);
-#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 32)
- putreg32(0, NVIC_IRQ32_63_ENABLE);
-#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 64)
- putreg32(0, NVIC_IRQ64_95_ENABLE);
-#endif
-#endif
+ for (i = 0; i < NR_VECTORS - EFM32_IRQ_INTERRUPTS; i += 32)
+ {
+ putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
+ }
#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
/* Colorize the interrupt stack for debug purposes */
diff --git a/arch/arm/src/efm32/efm32_leserial.c b/arch/arm/src/efm32/efm32_leserial.c
index 02126a92f3d2db32e531cea566dfb9adc4f03e1b..8a5de9378880d1ccffa5f89d037a6b1165536a9f 100644
--- a/arch/arm/src/efm32/efm32_leserial.c
+++ b/arch/arm/src/efm32/efm32_leserial.c
@@ -518,7 +518,7 @@ static int efm32_interrupt(struct uart_dev_s *dev)
* FERR - Framing Error Interrupt Enable
*/
- _llerr("RX ERROR: %08x\n", intflags);
+ _err("RX ERROR: %08x\n", intflags);
}
/* Check for transmit errors */
@@ -527,7 +527,7 @@ static int efm32_interrupt(struct uart_dev_s *dev)
{
/* TXOF - TX Overflow Interrupt Enable */
- _llerr("RX ERROR: %08x\n", intflags);
+ _err("RX ERROR: %08x\n", intflags);
}
#endif
diff --git a/arch/arm/src/efm32/efm32_pwm.c b/arch/arm/src/efm32/efm32_pwm.c
index b73c9bbdd8d1e03422a74f9eda2cc73c532f75d2..f07a3eed4b78794bde0766a296ffda896238edf5 100644
--- a/arch/arm/src/efm32/efm32_pwm.c
+++ b/arch/arm/src/efm32/efm32_pwm.c
@@ -47,7 +47,7 @@
#include
#include
-#include
+#include
#include
#include "up_arch.h"
@@ -522,8 +522,8 @@ static int pwm_interrupt(struct efm32_pwmtimer_s *priv)
/* Now all of the time critical stuff is done so we can do some debug output */
- pwmllinfo("Update interrupt SR: %04x prev: %d curr: %d count: %d\n",
- regval, priv->prev, priv->curr, priv->count);
+ pwminfo("Update interrupt SR: %04x prev: %d curr: %d count: %d\n",
+ regval, priv->prev, priv->curr, priv->count);
return OK;
#else
diff --git a/arch/arm/src/efm32/efm32_pwm.h b/arch/arm/src/efm32/efm32_pwm.h
index af46c3b6f8bccea22bb397435a0b3ce16293ebe1..61e4f5f116db095177b47f3aeed3e6c45c7ae1a2 100644
--- a/arch/arm/src/efm32/efm32_pwm.h
+++ b/arch/arm/src/efm32/efm32_pwm.h
@@ -39,7 +39,7 @@
/* The EFM32 does not have dedicated PWM hardware. Rather, pulsed output
* control is a capability of the EFM32 timers. The logic in this file
* implements the lower half of the standard, NuttX PWM interface using the
- * EFM32 timers. That interface is described in include/nuttx/pwm.h.
+ * EFM32 timers. That interface is described in include/nuttx/drivers/pwm.h.
*/
/****************************************************************************
diff --git a/arch/arm/src/efm32/efm32_rmu.h b/arch/arm/src/efm32/efm32_rmu.h
index 709c53e48deb5f056e47d7e92fb6a8f044e7449d..1bcfec2d33f0952fbd1bc9753dcc1aec951dcda1 100644
--- a/arch/arm/src/efm32/efm32_rmu.h
+++ b/arch/arm/src/efm32/efm32_rmu.h
@@ -55,9 +55,9 @@
#endif
#ifdef CONFIG_EFM32_RMU_DEBUG
-# define rmuerr _llerr
-# define rmuwarn _llwarn
-# define rmuinfo _llinfo
+# define rmuerr _err
+# define rmuwarn _warn
+# define rmuinfo _info
#else
# define rmuerr(x...)
# define rmuwarn(x...)
diff --git a/arch/arm/src/efm32/efm32_serial.c b/arch/arm/src/efm32/efm32_serial.c
index ff8c0f7dac6acc5333614d04eabd732ffe65df6b..52848fcd03d67af9589a519370860a9f4ed18dda 100644
--- a/arch/arm/src/efm32/efm32_serial.c
+++ b/arch/arm/src/efm32/efm32_serial.c
@@ -780,7 +780,7 @@ static int efm32_rxinterrupt(struct uart_dev_s *dev)
* FERR - Framing Error Interrupt Enable
*/
- _llerr("RX ERROR: %08x\n", intflags);
+ _err("RX ERROR: %08x\n", intflags);
}
#endif
@@ -863,7 +863,7 @@ static int efm32_txinterrupt(struct uart_dev_s *dev)
{
/* TXOF - TX Overflow Interrupt Enable */
- _llerr("RX ERROR: %08x\n", intflags);
+ _err("RX ERROR: %08x\n", intflags);
}
#endif
diff --git a/arch/arm/src/efm32/efm32_spi.c b/arch/arm/src/efm32/efm32_spi.c
index c4dbb3b282d9cf926688eae0b9d0a30e8946095b..0bf2c31a86a6a07b9d9be971e70d93aa204232e2 100644
--- a/arch/arm/src/efm32/efm32_spi.c
+++ b/arch/arm/src/efm32/efm32_spi.c
@@ -185,6 +185,10 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev,
uint32_t frequency);
static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode);
static void spi_setbits(struct spi_dev_s *dev, int nbits);
+#ifdef CONFIG_SPI_HWFEATURES
+static int spi_hwfeatures(FAR struct spi_dev_s *dev,
+ spi_hwfeatures_t features);
+#endif
static uint8_t spi_status(struct spi_dev_s *dev, enum spi_dev_e devid);
#ifdef CONFIG_SPI_CMDDATA
static int spi_cmddata(struct spi_dev_s *dev, enum spi_dev_e devid,
@@ -218,7 +222,7 @@ static const struct spi_ops_s g_spiops =
.setmode = spi_setmode,
.setbits = spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
- .hwfeatures = 0,
+ .hwfeatures = spi_hwfeatures,
#endif
.status = spi_status,
#ifdef CONFIG_SPI_CMDDATA
@@ -976,47 +980,16 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
const struct efm32_spiconfig_s *config;
uint32_t regval;
uint32_t setting;
- bool lsbfirst;
spiinfo("nbits=%d\n", nbits);
DEBUGASSERT(priv && priv->config);
config = priv->config;
- /* Bit order is encoded by the sign of nbits */
+ /* Has the number of bits changed? */
- if (nbits < 0)
+ if (nbits != priv->nbits)
{
- /* LSB first */
-
- lsbfirst = true;
- nbits = -nbits;
- }
- else
- {
- /* MSH first */
-
- lsbfirst = false;
- }
-
- /* Has the number of bits or the bit order changed? */
-
- if (nbits != priv->nbits || lsbfirst != priv->lsbfirst)
- {
- /* Set the new bit order */
-
- regval = spi_getreg(config, EFM32_USART_CTRL_OFFSET);
- if (lsbfirst)
- {
- regval &= ~USART_CTRL_MSBF;
- }
- else
- {
- regval |= USART_CTRL_MSBF;
- }
-
- spi_putreg(config, EFM32_USART_CTRL_OFFSET, regval);
-
/* Select the new number of bits */
switch (nbits)
@@ -1086,10 +1059,77 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
* faster
*/
- priv->nbits = nbits;
+ priv->nbits = nbits;
+ }
+}
+
+/****************************************************************************
+ * Name: spi_hwfeatures
+ *
+ * Description:
+ * Set hardware-specific feature flags.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ * features - H/W feature flags
+ *
+ * Returned Value:
+ * Zero (OK) if the selected H/W features are enabled; A negated errno
+ * value if any H/W feature is not supportable.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SPI_HWFEATURES
+static int spi_hwfeatures(FAR struct spi_dev_s *dev, spi_hwfeatures_t features)
+{
+#ifdef CONFIG_SPI_BITORDER
+ struct efm32_spidev_s *priv = (struct efm32_spidev_s *)dev;
+ const struct efm32_spiconfig_s *config;
+ uint32_t regval;
+ bool lsbfirst;
+
+ spiinfo("features=%08x\n", features);
+
+ DEBUGASSERT(priv && priv->config);
+ config = priv->config;
+
+ /* Bit order is encoded by the sign of nbits */
+
+ lsbfirst = ((features & HWFEAT_LSBFIRST) != 0);
+
+ /* Has the number of bits or the bit order changed? */
+
+ if (lsbfirst != priv->lsbfirst)
+ {
+ /* Set the new bit order */
+
+ regval = spi_getreg(config, EFM32_USART_CTRL_OFFSET);
+ if (lsbfirst)
+ {
+ regval &= ~USART_CTRL_MSBF;
+ }
+ else
+ {
+ regval |= USART_CTRL_MSBF;
+ }
+
+ spi_putreg(config, EFM32_USART_CTRL_OFFSET, regval);
+
+ /* Save the selection so the subsequence re-configurations will be
+ * faster
+ */
+
priv->lsbfirst = lsbfirst;
}
+
+ /* Other H/W features are not supported */
+
+ return ((features & ~HWFEAT_LSBFIRST) == 0) ? OK : -ENOSYS;
+#else
+ return -ENOSYS;
+#endif
}
+#endif
/****************************************************************************
* Name: spi_status
diff --git a/arch/arm/src/efm32/efm32_start.c b/arch/arm/src/efm32/efm32_start.c
index f62e1461d51e9476adf440eae9634365b4e9e90c..59c45afaa3253fc14a803a67374d47094aa8edf6 100644
--- a/arch/arm/src/efm32/efm32_start.c
+++ b/arch/arm/src/efm32/efm32_start.c
@@ -275,6 +275,12 @@ void __start(void)
showprogress('C');
+#ifdef CONFIG_ARMV7M_ITMSYSLOG
+ /* Perform ARMv7-M ITM SYSLOG initialization */
+
+ itm_syslog_initialize();
+#endif
+
/* Perform early serial initialization */
up_earlyserialinit();
diff --git a/arch/arm/src/efm32/efm32_usbdev.c b/arch/arm/src/efm32/efm32_usbdev.c
index 7bea4d4c4d8b25334926f53fab87e99df553f5de..26753dd3ff4d64965a3cf95552148658e8c10c83 100644
--- a/arch/arm/src/efm32/efm32_usbdev.c
+++ b/arch/arm/src/efm32/efm32_usbdev.c
@@ -819,7 +819,7 @@ static uint32_t efm32_getreg(uint32_t addr)
{
if (count == 4)
{
- ullinfo("...\n");
+ uinfo("...\n");
}
return val;
@@ -836,7 +836,7 @@ static uint32_t efm32_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- ullinfo("[repeats %d more times]\n", count-3);
+ uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -848,7 +848,7 @@ static uint32_t efm32_getreg(uint32_t addr)
/* Show the register value read */
- ullinfo("%08x->%08x\n", addr, val);
+ uinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@@ -866,7 +866,7 @@ static void efm32_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- ullinfo("%08x<-%08x\n", addr, val);
+ uinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@@ -1224,9 +1224,9 @@ static void efm32_epin_request(FAR struct efm32_usbdev_s *priv,
return;
}
- ullinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
- privep->epphy, privreq, privreq->req.len,
- privreq->req.xfrd, privep->zlp);
+ uinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
+ privep->epphy, privreq, privreq->req.len,
+ privreq->req.xfrd, privep->zlp);
/* Check for a special case: If we are just starting a request (xfrd==0) and
* the class driver is trying to send a zero-length packet (len==0). Then set
@@ -1490,8 +1490,8 @@ static void efm32_epout_complete(FAR struct efm32_usbdev_s *priv,
return;
}
- ullinfo("EP%d: len=%d xfrd=%d\n",
- privep->epphy, privreq->req.len, privreq->req.xfrd);
+ uinfo("EP%d: len=%d xfrd=%d\n",
+ privep->epphy, privreq->req.len, privreq->req.xfrd);
/* Return the completed read request to the class driver and mark the state
* IDLE.
@@ -1525,7 +1525,7 @@ static inline void efm32_ep0out_receive(FAR struct efm32_ep_s *privep, int bcnt)
DEBUGASSERT(privep && privep->ep.priv);
priv = (FAR struct efm32_usbdev_s *)privep->ep.priv;
- ullinfo("EP0: bcnt=%d\n", bcnt);
+ uinfo("EP0: bcnt=%d\n", bcnt);
usbtrace(TRACE_READ(EP0), bcnt);
/* Verify that an OUT SETUP request as received before this data was
@@ -1618,7 +1618,8 @@ static inline void efm32_epout_receive(FAR struct efm32_ep_s *privep, int bcnt)
return;
}
- ullinfo("EP%d: len=%d xfrd=%d\n", privep->epphy, privreq->req.len, privreq->req.xfrd);
+ uinfo("EP%d: len=%d xfrd=%d\n",
+ privep->epphy, privreq->req.len, privreq->req.xfrd);
usbtrace(TRACE_READ(privep->epphy), bcnt);
/* Get the number of bytes to transfer from the RxFIFO */
@@ -1702,7 +1703,7 @@ static void efm32_epout_request(FAR struct efm32_usbdev_s *priv,
return;
}
- ullinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len);
+ uinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len);
/* Ignore any attempt to receive a zero length packet (this really
* should not happen.
@@ -2498,8 +2499,8 @@ static inline void efm32_ep0out_setup(struct efm32_usbdev_s *priv)
ctrlreq.index = GETUINT16(priv->ctrlreq.index);
ctrlreq.len = GETUINT16(priv->ctrlreq.len);
- ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
+ uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
/* Check for a standard request */
@@ -2633,7 +2634,7 @@ static inline void efm32_epout_interrupt(FAR struct efm32_usbdev_s *priv)
if ((daint & 1) != 0)
{
regval = efm32_getreg(EFM32_USB_DOEPINT(epno));
- ullinfo("DOEPINT(%d) = %08x\n", epno, regval);
+ uinfo("DOEPINT(%d) = %08x\n", epno, regval);
efm32_putreg(0xFF, EFM32_USB_DOEPINT(epno));
}
@@ -2863,8 +2864,8 @@ static inline void efm32_epin_interrupt(FAR struct efm32_usbdev_s *priv)
{
if ((daint & 1) != 0)
{
- ullinfo("DIEPINT(%d) = %08x\n",
- epno, efm32_getreg(EFM32_USB_DIEPINT(epno)));
+ uinfo("DIEPINT(%d) = %08x\n",
+ epno, efm32_getreg(EFM32_USB_DIEPINT(epno)));
efm32_putreg(0xFF, EFM32_USB_DIEPINT(epno));
}
@@ -4337,7 +4338,8 @@ static int efm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_INVALIDPARMS), 0);
- ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+ uinfo("req=%p callback=%p buf=%p ep=%p\n",
+ req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
diff --git a/arch/arm/src/efm32/efm32_usbhost.c b/arch/arm/src/efm32/efm32_usbhost.c
index 83ee505105539ec45367c2967b58396971a6f28c..19f80bc43d4322b130e47cf29eb866d7dd65f0fc 100644
--- a/arch/arm/src/efm32/efm32_usbhost.c
+++ b/arch/arm/src/efm32/efm32_usbhost.c
@@ -582,7 +582,7 @@ static const struct efm32_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] =
#ifdef CONFIG_EFM32_USBHOST_REGDEBUG
static void efm32_printreg(uint32_t addr, uint32_t val, bool iswrite)
{
- ullinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
+ uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
}
#endif
@@ -632,7 +632,7 @@ static void efm32_checkreg(uint32_t addr, uint32_t val, bool iswrite)
{
/* No.. More than one. */
- ullinfo("[repeats %d more times]\n", count);
+ uinfo("[repeats %d more times]\n", count);
}
}
@@ -2448,7 +2448,7 @@ static inline void efm32_gint_hcinisr(FAR struct efm32_usbhost_s *priv,
/* AND the two to get the set of enabled, pending HC interrupts */
pending &= regval;
- ullinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
+ uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
@@ -2709,7 +2709,7 @@ static inline void efm32_gint_hcoutisr(FAR struct efm32_usbhost_s *priv,
/* AND the two to get the set of enabled, pending HC interrupts */
pending &= regval;
- ullinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
+ uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending);
/* Check for a pending ACK response received/transmitted (ACK) interrupt */
@@ -3012,7 +3012,7 @@ static inline void efm32_gint_rxflvlisr(FAR struct efm32_usbhost_s *priv)
/* Read and pop the next status from the Rx FIFO */
grxsts = efm32_getreg(EFM32_USB_GRXSTSP);
- ullinfo("GRXSTS: %08x\n", grxsts);
+ uinfo("GRXSTS: %08x\n", grxsts);
/* Isolate the channel number/index in the status word */
@@ -3166,8 +3166,8 @@ static inline void efm32_gint_nptxfeisr(FAR struct efm32_usbhost_s *priv)
/* Write the next group of packets into the Tx FIFO */
- ullinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
- regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
+ uinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
+ regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
efm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
}
@@ -3254,8 +3254,8 @@ static inline void efm32_gint_ptxfeisr(FAR struct efm32_usbhost_s *priv)
/* Write the next group of packets into the Tx FIFO */
- ullinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
- regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
+ uinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n",
+ regval, chidx, avail, chan->buflen, chan->xfrd, wrsize);
efm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize);
}
@@ -4795,7 +4795,8 @@ static int efm32_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
- ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+ uinfo("Hub port %d connected: %s\n",
+ hport->port, connected ? "YES" : "NO");
/* Report the connection event */
diff --git a/arch/arm/src/imx1/imx_decodeirq.c b/arch/arm/src/imx1/imx_decodeirq.c
index 5c35e68fab2dbc619aeea11cc6146698c74a09b4..48164d9099c465561c9cb65e30b0b14c140c5404 100644
--- a/arch/arm/src/imx1/imx_decodeirq.c
+++ b/arch/arm/src/imx1/imx_decodeirq.c
@@ -74,8 +74,8 @@
void up_decodeirq(uint32_t *regs)
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
- lowsyslog(LOG_ERR, "Unexpected IRQ\n");
CURRENT_REGS = regs;
+ err("ERROR: Unexpected IRQ\n");
PANIC();
#else
uint32_t regval;
diff --git a/arch/arm/src/kinetis/Kconfig b/arch/arm/src/kinetis/Kconfig
index 5710c2d32ce6c7e4067fcc53e430f3aa734dde0b..17923818b5a495dcba8bbe649f1b1e223b47f1cd 100644
--- a/arch/arm/src/kinetis/Kconfig
+++ b/arch/arm/src/kinetis/Kconfig
@@ -37,66 +37,130 @@ config ARCH_CHIP_MK20DX128VLH5
config ARCH_CHIP_MK20DX64VLH7
bool "MK20DX64VLH7"
select ARCH_FAMILY_K20
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK20DX128VLH7
bool "MK20DX128VLH7"
select ARCH_FAMILY_K20
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK20DX256VLH7
bool "MK20DX256VLH7"
select ARCH_FAMILY_K20
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40N512VLQ100
bool "MK40N512VLQ100"
select ARCH_FAMILY_K40
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40N512VMD100
bool "MK40N512VMD100"
select ARCH_FAMILY_K40
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40X128VLQ100
bool "MK40X128VLQ100"
select ARCH_FAMILY_K40
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40X128VMD100
bool "MK40X128VMD100"
select ARCH_FAMILY_K40
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40X256VLQ100
bool "MK40X256VLQ100"
select ARCH_FAMILY_K40
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK40X256VMD100
bool "MK40X256VMD100"
select ARCH_FAMILY_K40
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK60N256VLQ100
bool "MK60N256VLQ100"
select ARCH_FAMILY_K60
+ select KINETIS_HAVE_I2C1
config ARCH_CHIP_MK60N256VMD100
bool "MK60N256VMD100"
select ARCH_FAMILY_K60
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK60N512VLL100
bool "MK60N512VLL100"
select ARCH_FAMILY_K60
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK60N512VLQ100
bool "MK60N512VLQ100"
select ARCH_FAMILY_K60
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK60N512VMD100
bool "MK60N512VMD100"
select ARCH_FAMILY_K60
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK60X256VLQ100
bool "MK60X256VLQ100"
select ARCH_FAMILY_K60
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
config ARCH_CHIP_MK60X256VMD100
bool "MK60X256VMD100"
select ARCH_FAMILY_K60
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
+
+config ARCH_CHIP_MK64FN1M0VLL12
+ bool "MK64FN1M0VLL12"
+ select ARCH_FAMILY_K64
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
+
+config ARCH_CHIP_MK64FX512VLL12
+ bool "MK64FX512VLL12"
+ select ARCH_FAMILY_K64
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
+
+config ARCH_CHIP_MK64FX512VDC12
+ bool "MK64FX512VDC12"
+ select ARCH_FAMILY_K64
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
+
+config ARCH_CHIP_MK64FN1M0VDC12
+ bool "MK64FN1M0VDC12"
+ select ARCH_FAMILY_K64
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
+
+config ARCH_CHIP_MK64FX512VLQ12
+ bool "MK64FX512VLQ12"
+ select ARCH_FAMILY_K64
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
+
+config ARCH_CHIP_MK64FX512VMD12
+ bool "MK64FX512VMD12"
+ select ARCH_FAMILY_K64
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
+
+config ARCH_CHIP_MK64FN1M0VMD12
+ bool "MK64FN1M0VMD12"
+ select ARCH_FAMILY_K64
+ select KINETIS_HAVE_I2C1
+ select KINETIS_HAVE_I2C2
endchoice
@@ -114,8 +178,20 @@ config ARCH_FAMILY_K60
bool
default n
+config ARCH_FAMILY_K64
+ bool
+ default n
+
menu "Kinetis Peripheral Support"
+config KINETIS_HAVE_I2C1
+ bool
+ default n
+
+config KINETIS_HAVE_I2C2
+ bool
+ default n
+
config KINETIS_TRACE
bool "Trace"
default n
@@ -173,19 +249,22 @@ config KINETIS_UART5
config KINETIS_ENET
bool "Ethernet"
default n
- depends on ARCH_FAMILY_K60
- select NET
+ depends on ARCH_FAMILY_K60 || ARCH_FAMILY_K64
+ select ARCH_HAVE_PHY
select ARCH_HAVE_NETDEV_STATISTICS
+ select NET
+ select NETDEVICES
+ select NET_MULTIBUFFER
---help---
- Support Ethernet (K60 only)
+ Support Ethernet (K6x only)
config KINETIS_RNGB
bool "Random number generator"
default n
- depends on ARCH_FAMILY_K60
+ depends on ARCH_FAMILY_K60 || ARCH_FAMILY_K64
select ARCH_HAVE_RNG
---help---
- Support the random number generator(K60 only)
+ Support the random number generator(K6x only)
config KINETIS_FLEXCAN0
bool "FlexCAN0"
@@ -220,12 +299,23 @@ config KINETIS_SPI2
config KINETIS_I2C0
bool "I2C0"
default n
+ select I2C
---help---
Support I2C0
config KINETIS_I2C1
bool "I2C1"
default n
+ select I2C
+ depends on KINETIS_HAVE_I2C1
+ ---help---
+ Support I2C1
+
+config KINETIS_I2C2
+ bool "I2C2"
+ default n
+ select I2C
+ depends on KINETIS_HAVE_I2C2
---help---
Support I2C1
@@ -383,6 +473,9 @@ config KINETIS_PIT
endmenu
+menu "Kinetis FTM PWM Configuration"
+ depends on KINETIS_FTM0 || KINETIS_FTM1 || KINETIS_FTM2
+
config KINETIS_FTM0_PWM
bool "FTM0 PWM"
default n
@@ -446,14 +539,16 @@ config KINETIS_FTM2_CHANNEL
If FTM2 is enabled for PWM usage, you also need specifies the timer output
channel {0,..,1}
-comment "Kinetis GPIO Interrupt Configuration"
+endmenu # Kinetis FTM PWM Configuration
-config GPIO_IRQ
+menu "Kinetis GPIO Interrupt Configuration"
+
+config KINETIS_GPIOIRQ
bool "GPIO pin interrupts"
---help---
Enable support for interrupting GPIO pins
-if GPIO_IRQ
+if KINETIS_GPIOIRQ
config KINETIS_PORTAINTS
bool "GPIOA interrupts"
@@ -481,55 +576,63 @@ config KINETIS_PORTEINTS
Enable support for 32 interrupts from GPIO port E pins
endif
+endmenu # Kinetis GPIO Interrupt Configuration
-if KINETIS_ENET
-
-comment "Kinetis Ethernet Configuration"
+menu "Kinetis Ethernet Configuration"
+ depends on KINETIS_ENET
-config ENET_ENHANCEDBD
+config KINETIS_ENETENHANCEDBD
bool "Use enhanced buffer descriptors"
default n
---help---
Use enhanced, 32-byte buffer descriptors
-config ENET_NETHIFS
+config KINETIS_ENETNETHIFS
int "Number of Ethernet interfaces"
default 1
---help---
Number of Ethernet interfaces supported by the hardware. Must be
one for now.
-config ENET_NRXBUFFERS
+config KINETIS_ENETNRXBUFFERS
int "Number of Ethernet Rx buffers"
default 6
---help---
Number of Ethernet Rx buffers to use. The size of one buffer is
determined by NET_BUFSIZE
-config ENET_NTXBUFFERS
+config KINETIS_ENETNTXBUFFERS
int "Number of Ethernet Tx buffers"
default 2
---help---
Number of Ethernet Tx buffers to use. The size of one buffer is
determined by NET_BUFSIZE
-config ENET_PHYADDR
- int "PHY address"
- default 1
- ---help---
- MII/RMII address of the PHY
-
-config ENET_USEMII
+config KINETIS_ENETUSEMII
bool "Use MII interface"
default n
---help---
The the MII PHY interface. Default: Use RMII interface
-endif
+config KINETIS_ENET_MDIOPULLUP
+ bool "MDIO pull-up"
+ default n
+ ---help---
+ If there is no on-board pull-up resister on the MII/RMII MDIO line,
+ then this option may be selected in order to configure an internal
+ pull-up on MDIO.
-if KINETIS_SDHC
+config KINETIS_ENET_NORXER
+ bool "Suppress RXER"
+ default n
+ ---help---
+ If selected, then the MII/RMII RXER output will be configured as a
+ GPIO and pulled low.
-comment "Kinetis SDHC Configuration"
+endmenu # Kinetis Ethernet Configuration
+
+menu "Kinetis SDHC Configuration"
+ depends on KINETIS_SDHC
config KINETIS_SDHC_ABSFREQ
bool "Custom transfer frequencies"
@@ -572,18 +675,13 @@ config KINETIS_SD4BIT_FREQ
Frequency to use for transferring data to/from an SD card using all four data lines.
endif
+endmenu # Kinetis SDHC Configuration
-config KINETIS_SDHC_DMAPRIO
- int "SDHC DMA priority"
- depends on SDIO_DMA
- ---help---
- SDHC DMA priority
-
-endif
-
-comment "Kinetis UART Configuration"
+menu "Kinetis UART Configuration"
config KINETIS_UARTFIFOS
bool "Enable UART0 FIFO"
default n
depends on KINETIS_UART0
+
+endmenu # Kinetis UART Configuration
diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs
index 662dd618737f74b868560d730be62f3c6e6a209a..bb7f54d87bb7b7530c675a2df9142134268e9c97 100644
--- a/arch/arm/src/kinetis/Make.defs
+++ b/arch/arm/src/kinetis/Make.defs
@@ -1,7 +1,7 @@
############################################################################
# arch/arm/src/kinetis/Make.defs
#
-# Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved.
+# Copyright (C) 2011, 2013-2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt
#
# Redistribution and use in source and binary forms, with or without
@@ -103,7 +103,7 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += kinetis_userspace.c kinetis_mpuinit.c
endif
-ifeq ($(CONFIG_GPIO_IRQ),y)
+ifeq ($(CONFIG_KINETIS_GPIOIRQ),y)
CHIP_CSRCS += kinetis_pinirq.c
endif
@@ -131,6 +131,14 @@ ifeq ($(CONFIG_PWM),y)
CHIP_CSRCS += kinetis_pwm.c
endif
+ifeq ($(CONFIG_I2C),y)
+CHIP_CSRCS += kinetis_i2c.c
+endif
+
+ifeq ($(CONFIG_RTC),y)
+CHIP_CSRCS += kinetis_rtc.c
+endif
+
ifeq ($(CONFIG_NET),y)
ifeq ($(CONFIG_KINETIS_ENET),y)
CHIP_CSRCS += kinetis_enet.c
diff --git a/arch/arm/src/kinetis/chip.h b/arch/arm/src/kinetis/chip.h
index 0ed152bac2f52203fe3ac39ebe4a6a48b6eac622..26fa7e38a0daaed85b59748db1c91cf6a1ba7ac1 100644
--- a/arch/arm/src/kinetis/chip.h
+++ b/arch/arm/src/kinetis/chip.h
@@ -47,7 +47,7 @@
*/
#include
-#include "kinetis_memorymap.h"
+#include "chip/kinetis_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
diff --git a/arch/arm/src/kinetis/kinetis_adc.h b/arch/arm/src/kinetis/chip/kinetis_adc.h
similarity index 93%
rename from arch/arm/src/kinetis/kinetis_adc.h
rename to arch/arm/src/kinetis/chip/kinetis_adc.h
index a17aa06c7f4274ca8a612e933cafec3c43c9bd71..6b3b74fa9c32c51efdddcaa71d5b4bd7bbbbe0c7 100644
--- a/arch/arm/src/kinetis/kinetis_adc.h
+++ b/arch/arm/src/kinetis/chip/kinetis_adc.h
@@ -1,7 +1,7 @@
/********************************************************************************************
- * arch/arm/src/kinetis/kinetis_adc.h
+ * arch/arm/src/kinetis/chip/kinetis_adc.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
********************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_ADC_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_ADC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ADC_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ADC_H
/********************************************************************************************
* Included Files
@@ -70,7 +70,9 @@
#define KINETIS_ADC_CLP2_OFFSET 0x0044 /* ADC plus-side general calibration value register */
#define KINETIS_ADC_CLP1_OFFSET 0x0048 /* ADC plus-side general calibration value register */
#define KINETIS_ADC_CLP0_OFFSET 0x004c /* ADC plus-side general calibration value register */
-#define KINETIS_ADC_PGA_OFFSET 0x0050 /* ADC PGA register */
+#ifndef KINETIS_K64
+# define KINETIS_ADC_PGA_OFFSET 0x0050 /* ADC PGA register */
+#endif
#define KINETIS_ADC_CLMD_OFFSET 0x0054 /* ADC minus-side general calibration value register */
#define KINETIS_ADC_CLMS_OFFSET 0x0058 /* ADC minus-side general calibration value register */
#define KINETIS_ADC_CLM4_OFFSET 0x005c /* ADC minus-side general calibration value register */
@@ -80,7 +82,7 @@
#define KINETIS_ADC_CLM0_OFFSET 0x006c /* ADC minus-side general calibration value register */
/* Register Addresses ***********************************************************************/
-# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
+# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
#define KINETIS_ADC0_SC1A (KINETIS_ADC0_BASE+KINETIS_ADC_SC1A_OFFSET)
#define KINETIS_ADC0_SC1B (KINETIS_ADC0_BASE+KINETIS_ADC_SC1B_OFFSET)
@@ -102,7 +104,9 @@
#define KINETIS_ADC0_CLP2 (KINETIS_ADC0_BASE+KINETIS_ADC_CLP2_OFFSET)
#define KINETIS_ADC0_CLP1 (KINETIS_ADC0_BASE+KINETIS_ADC_CLP1_OFFSET)
#define KINETIS_ADC0_CLP0 (KINETIS_ADC0_BASE+KINETIS_ADC_CLP0_OFFSET)
-#define KINETIS_ADC0_PGA (KINETIS_ADC0_BASE+KINETIS_ADC_PGA_OFFSET)
+#ifndef KINETIS_K64
+# define KINETIS_ADC0_PGA (KINETIS_ADC0_BASE+KINETIS_ADC_PGA_OFFSET)
+#endif
#define KINETIS_ADC0_CLMD (KINETIS_ADC0_BASE+KINETIS_ADC_CLMD_OFFSET)
#define KINETIS_ADC0_CLMS (KINETIS_ADC0_BASE+KINETIS_ADC_CLMS_OFFSET)
#define KINETIS_ADC0_CLM4 (KINETIS_ADC0_BASE+KINETIS_ADC_CLM4_OFFSET)
@@ -131,7 +135,9 @@
#define KINETIS_ADC1_CLP2 (KINETIS_ADC1_BASE+KINETIS_ADC_CLP2_OFFSET)
#define KINETIS_ADC1_CLP1 (KINETIS_ADC1_BASE+KINETIS_ADC_CLP1_OFFSET)
#define KINETIS_ADC1_CLP0 (KINETIS_ADC1_BASE+KINETIS_ADC_CLP0_OFFSET)
-#define KINETIS_ADC1_PGA (KINETIS_ADC1_BASE+KINETIS_ADC_PGA_OFFSET)
+#ifndef KINETIS_K64
+# define KINETIS_ADC1_PGA (KINETIS_ADC1_BASE+KINETIS_ADC_PGA_OFFSET)
+#endif
#define KINETIS_ADC1_CLMD (KINETIS_ADC1_BASE+KINETIS_ADC_CLMD_OFFSET)
#define KINETIS_ADC1_CLMS (KINETIS_ADC1_BASE+KINETIS_ADC_CLMS_OFFSET)
#define KINETIS_ADC1_CLM4 (KINETIS_ADC1_BASE+KINETIS_ADC_CLM4_OFFSET)
@@ -272,22 +278,26 @@
#define ADC_CLP0_MASK (0x3f) /* Bits 0-5: Calibration value */
/* ADC PGA register */
+
+#ifndef KINETIS_K64
/* Bits 0-15: Reserved */
-#define ADC_PGA_PGAG_SHIFT (16) /* Bits 16-19: PGA gain setting*/
-#define ADC_PGA_PGAG_MASK (15 << ADC_PGA_PGAG_SHIFT)
-# define ADC_PGA_PGAG_1 (0 << ADC_PGA_PGAG_SHIFT)
-# define ADC_PGA_PGAG_2 (1 << ADC_PGA_PGAG_SHIFT)
-# define ADC_PGA_PGAG_4 (2 << ADC_PGA_PGAG_SHIFT)
-# define ADC_PGA_PGAG_8 (3 << ADC_PGA_PGAG_SHIFT)
-# define ADC_PGA_PGAG_16 (4 << ADC_PGA_PGAG_SHIFT)
-# define ADC_PGA_PGAG_32 (5 << ADC_PGA_PGAG_SHIFT)
-# define ADC_PGA_PGAG_64 (6 << ADC_PGA_PGAG_SHIFT)
-#ifdef KINETIS_K40
-# define ADC_PGA_PGALP (1 << 20) /* Bit 20: PGA low-power mode control */
-#endif
+# define ADC_PGA_PGAG_SHIFT (16) /* Bits 16-19: PGA gain setting*/
+# define ADC_PGA_PGAG_MASK (15 << ADC_PGA_PGAG_SHIFT)
+# define ADC_PGA_PGAG_1 (0 << ADC_PGA_PGAG_SHIFT)
+# define ADC_PGA_PGAG_2 (1 << ADC_PGA_PGAG_SHIFT)
+# define ADC_PGA_PGAG_4 (2 << ADC_PGA_PGAG_SHIFT)
+# define ADC_PGA_PGAG_8 (3 << ADC_PGA_PGAG_SHIFT)
+# define ADC_PGA_PGAG_16 (4 << ADC_PGA_PGAG_SHIFT)
+# define ADC_PGA_PGAG_32 (5 << ADC_PGA_PGAG_SHIFT)
+# define ADC_PGA_PGAG_64 (6 << ADC_PGA_PGAG_SHIFT)
+# ifdef KINETIS_K40
+# define ADC_PGA_PGALP (1 << 20) /* Bit 20: PGA low-power mode control */
+# endif
/* Bits 21-22: Reserved */
-#define ADC_PGA_PGAEN (1 << 23) /* Bit 23: PGA enable*/
+# define ADC_PGA_PGAEN (1 << 23) /* Bit 23: PGA enable*/
/* Bits 24-31: Reserved */
+#endif
+
/* ADC minus-side general calibration value registers */
#define ADC_CLMD_MASK (0x3f) /* Bits 0-5: Calibration value */
@@ -310,4 +320,4 @@
* Public Functions
********************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_ADC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ADC_H */
diff --git a/arch/arm/src/kinetis/kinetis_aips.h b/arch/arm/src/kinetis/chip/kinetis_aips.h
similarity index 87%
rename from arch/arm/src/kinetis/kinetis_aips.h
rename to arch/arm/src/kinetis/chip/kinetis_aips.h
index 8f460567f76125052a24664fdc02843624729dba..a8050fb61397771f32b90c52fe0387920e39f285 100644
--- a/arch/arm/src/kinetis/kinetis_aips.h
+++ b/arch/arm/src/kinetis/chip/kinetis_aips.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_aips.h
+ * arch/arm/src/kinetis/chip/kinetis_aips.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_AIPS_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_AIPS_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AIPS_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AIPS_H
/************************************************************************************
* Included Files
@@ -68,6 +68,9 @@
#define KINETIS_AIPS_PACRN_OFFSET 0x0064 /* Peripheral Access Control Register */
#define KINETIS_AIPS_PACRO_OFFSET 0x0068 /* Peripheral Access Control Register */
#define KINETIS_AIPS_PACRP_OFFSET 0x006c /* Peripheral Access Control Register */
+#ifdef KINETIS_K64
+# define KINETIS_AIPS_PACRU_OFFSET 0x0080 /* Peripheral Access Control Register */
+#endif
/* Register Addresses ***************************************************************/
@@ -88,24 +91,30 @@
#define KINETIS_AIPS0_PACRN (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRN_OFFSET)
#define KINETIS_AIPS0_PACRO (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRO_OFFSET)
#define KINETIS_AIPS0_PACRP (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRP_OFFSET)
-
-#define KINETIS_AIPS1_MPRA (KINETIS_AIPS0_BASE+KINETIS_AIPS_MPRA_OFFSET)
-#define KINETIS_AIPS1_PACRA (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRA_OFFSET)
-#define KINETIS_AIPS1_PACRB (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRB_OFFSET)
-#define KINETIS_AIPS1_PACRC (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRC_OFFSET)
-#define KINETIS_AIPS1_PACRD (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRD_OFFSET)
-#define KINETIS_AIPS1_PACRE (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRE_OFFSET)
-#define KINETIS_AIPS1_PACRF (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRF_OFFSET)
-#define KINETIS_AIPS1_PACRG (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRG_OFFSET)
-#define KINETIS_AIPS1_PACRH (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRH_OFFSET)
-#define KINETIS_AIPS1_PACRI (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRI_OFFSET)
-#define KINETIS_AIPS1_PACRJ (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRJ_OFFSET)
-#define KINETIS_AIPS1_PACRK (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRK_OFFSET)
-#define KINETIS_AIPS1_PACRL (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRL_OFFSET)
-#define KINETIS_AIPS1_PACRM (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRM_OFFSET)
-#define KINETIS_AIPS1_PACRN (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRN_OFFSET)
-#define KINETIS_AIPS1_PACRO (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRO_OFFSET)
-#define KINETIS_AIPS1_PACRP (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRP_OFFSET)
+#ifdef KINETIS_K64
+# define KINETIS_AIPS0_PACRU (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRU_OFFSET)
+#endif
+
+#define KINETIS_AIPS1_MPRA (KINETIS_AIPS1_BASE+KINETIS_AIPS_MPRA_OFFSET)
+#define KINETIS_AIPS1_PACRA (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRA_OFFSET)
+#define KINETIS_AIPS1_PACRB (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRB_OFFSET)
+#define KINETIS_AIPS1_PACRC (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRC_OFFSET)
+#define KINETIS_AIPS1_PACRD (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRD_OFFSET)
+#define KINETIS_AIPS1_PACRE (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRE_OFFSET)
+#define KINETIS_AIPS1_PACRF (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRF_OFFSET)
+#define KINETIS_AIPS1_PACRG (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRG_OFFSET)
+#define KINETIS_AIPS1_PACRH (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRH_OFFSET)
+#define KINETIS_AIPS1_PACRI (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRI_OFFSET)
+#define KINETIS_AIPS1_PACRJ (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRJ_OFFSET)
+#define KINETIS_AIPS1_PACRK (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRK_OFFSET)
+#define KINETIS_AIPS1_PACRL (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRL_OFFSET)
+#define KINETIS_AIPS1_PACRM (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRM_OFFSET)
+#define KINETIS_AIPS1_PACRN (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRN_OFFSET)
+#define KINETIS_AIPS1_PACRO (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRO_OFFSET)
+#define KINETIS_AIPS1_PACRP (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRP_OFFSET)
+#ifdef KINETIS_K64
+# define KINETIS_AIPS1_PACRU (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRU_OFFSET)
+#endif
/* Register Bit Definitions *********************************************************/
@@ -205,4 +214,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_AIPS_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AIPS_H */
diff --git a/arch/arm/src/kinetis/kinetis_axbs.h b/arch/arm/src/kinetis/chip/kinetis_axbs.h
similarity index 98%
rename from arch/arm/src/kinetis/kinetis_axbs.h
rename to arch/arm/src/kinetis/chip/kinetis_axbs.h
index bf8543d4dac5a5dc5b13a4b110e447483d1dcdb7..7aab308593c3a3b56a32ef8c9703f55e4b9cec92 100644
--- a/arch/arm/src/kinetis/kinetis_axbs.h
+++ b/arch/arm/src/kinetis/chip/kinetis_axbs.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_axbs.h
+ * arch/arm/src/kinetis/chip/kinetis_axbs.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_AXBS_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_AXBS_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AXBS_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AXBS_H
/************************************************************************************
* Included Files
@@ -248,4 +248,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_AXBS_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AXBS_H */
diff --git a/arch/arm/src/kinetis/kinetis_cmp.h b/arch/arm/src/kinetis/chip/kinetis_cmp.h
similarity index 96%
rename from arch/arm/src/kinetis/kinetis_cmp.h
rename to arch/arm/src/kinetis/chip/kinetis_cmp.h
index 822b7a339f5de9603af3e3236f03d1e5b47068ba..09e9eb19f6a9846b58fb0be5f686a1c0c49da08f 100644
--- a/arch/arm/src/kinetis/kinetis_cmp.h
+++ b/arch/arm/src/kinetis/chip/kinetis_cmp.h
@@ -1,7 +1,7 @@
/********************************************************************************************
- * arch/arm/src/kinetis/kinetis_cmp.h
+ * arch/arm/src/kinetis/chip/kinetis_cmp.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
********************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_CMP_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_CMP_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMP_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMP_H
/********************************************************************************************
* Included Files
@@ -172,7 +172,9 @@
# define CMP_MUXCR_PSEL_IN5 (5 << CMP_MUXCR_PSEL_SHIFT)
# define CMP_MUXCR_PSEL_IN6 (6 << CMP_MUXCR_PSEL_SHIFT)
# define CMP_MUXCR_PSEL_IN7 (7 << CMP_MUXCR_PSEL_SHIFT)
-#define CMP_MUXCR_MEN (1 << 6) /* Bit 6: MMUX Enable */
+#ifndef KINETIS_K64
+# define CMP_MUXCR_MEN (1 << 6) /* Bit 6: MMUX Enable */
+#endif
#define CMP_MUXCR_PEN (1 << 7) /* Bit 7: PMUX Enable */
/********************************************************************************************
@@ -187,4 +189,4 @@
* Public Functions
********************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_CMP_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMP_H */
diff --git a/arch/arm/src/kinetis/kinetis_cmt.h b/arch/arm/src/kinetis/chip/kinetis_cmt.h
similarity index 96%
rename from arch/arm/src/kinetis/kinetis_cmt.h
rename to arch/arm/src/kinetis/chip/kinetis_cmt.h
index c3c47bb6761254a0ce4c86484a43e41809433cdf..e86720db91e02a4d55df9c9baec355c9a51f152f 100644
--- a/arch/arm/src/kinetis/kinetis_cmt.h
+++ b/arch/arm/src/kinetis/chip/kinetis_cmt.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_cmt.h
+ * arch/arm/src/kinetis/chip/kinetis_cmt.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_CMT_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_CMT_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMT_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMT_H
/************************************************************************************
* Included Files
@@ -135,4 +135,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_CMT_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMT_H */
diff --git a/arch/arm/src/kinetis/kinetis_crc.h b/arch/arm/src/kinetis/chip/kinetis_crc.h
similarity index 85%
rename from arch/arm/src/kinetis/kinetis_crc.h
rename to arch/arm/src/kinetis/chip/kinetis_crc.h
index 7b590cf3a9a0c39374982f0c8b747da54bb71ccf..d2f0fc7fddb10ecae0286603b9d50c7f4139477f 100644
--- a/arch/arm/src/kinetis/kinetis_crc.h
+++ b/arch/arm/src/kinetis/chip/kinetis_crc.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_crc.h
+ * arch/arm/src/kinetis/chip/kinetis_crc.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_CRC_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_CRC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CRC_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CRC_H
/************************************************************************************
* Included Files
@@ -52,13 +52,13 @@
/* Register Offsets *****************************************************************/
-#define KINETIS_CRC_CRC_OFFSET 0x0000 /* CRC Data Register */
+#define KINETIS_CRC_DATA_OFFSET 0x0000 /* CRC Data Register */
#define KINETIS_CRC_GPOLY_OFFSET 0x0004 /* CRC Polynomial Register */
#define KINETIS_CRC_CTRL_OFFSET 0x0008 /* CRC Control Register */
/* Register Addresses ***************************************************************/
-#define KINETIS_CRC_CRC (KINETIS_CRC_BASE+KINETIS_CRC_CRC_OFFSET)
+#define KINETIS_CRC_DATA (KINETIS_CRC_BASE+KINETIS_CRC_DATA_OFFSET)
#define KINETIS_CRC_GPOLY (KINETIS_CRC_BASE+KINETIS_CRC_GPOLY_OFFSET)
#define KINETIS_CRC_CTRL (KINETIS_CRC_BASE+KINETIS_CRC_CTRL_OFFSET)
@@ -66,14 +66,14 @@
/* CRC Data Register (32-bit) */
-#define CRC_CRC_LL_SHIFT (0) /* Bits 0-7: CRC Low Lower Byte */
-#define CRC_CRC_LL_MASK (0xff << CRC_CRC_LL_SHIFT)
-#define CRC_CRC_LU_SHIFT (8) /* Bits 8-15: CRC Low Upper Byte */
-#define CRC_CRC_LU_MASK (0xff << CRC_CRC_LU_SHIFT)
-#define CRC_CRC_HL_SHIFT (16) /* Bits 16-23: CRC High Lower Byte */
-#define CRC_CRC_HL_MASK (0xff << CRC_CRC_HL_SHIFT)
-#define CRC_CRC_HU_SHIFT (24) /* Bits 24-31: CRC High Upper Byte */
-#define CRC_CRC_HU_MASK (0xff << CRC_CRC_HU_SHIFT)
+#define CRC_DATA_LL_SHIFT (0) /* Bits 0-7: CRC Low Lower Byte */
+#define CRC_DATA_LL_MASK (0xff << CRC_DATA_LL_SHIFT)
+#define CRC_DATA_LU_SHIFT (8) /* Bits 8-15: CRC Low Upper Byte */
+#define CRC_DATA_LU_MASK (0xff << CRC_DATA_LU_SHIFT)
+#define CRC_DATA_HL_SHIFT (16) /* Bits 16-23: CRC High Lower Byte */
+#define CRC_DATA_HL_MASK (0xff << CRC_DATA_HL_SHIFT)
+#define CRC_DATA_HU_SHIFT (24) /* Bits 24-31: CRC High Upper Byte */
+#define CRC_DATA_HU_MASK (0xff << CRC_DATA_HU_SHIFT)
/* CRC Polynomial Register */
@@ -114,4 +114,4 @@
************************************************************************************/
#endif /* KINETIS_NCRC && KINETIS_NCRC > 0 */
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_CRC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CRC_H */
diff --git a/arch/arm/src/kinetis/kinetis_dac.h b/arch/arm/src/kinetis/chip/kinetis_dac.h
similarity index 98%
rename from arch/arm/src/kinetis/kinetis_dac.h
rename to arch/arm/src/kinetis/chip/kinetis_dac.h
index 5c3b5c0c037503fc669c2427f5581f6b2322285d..bf2184382632158f1270fec96d536a0e9ff363d7 100644
--- a/arch/arm/src/kinetis/kinetis_dac.h
+++ b/arch/arm/src/kinetis/chip/kinetis_dac.h
@@ -1,7 +1,7 @@
/********************************************************************************************
- * arch/arm/src/kinetis/kinetis_dac.h
+ * arch/arm/src/kinetis/chip/kinetis_dac.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
********************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_DACE_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_DACE_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DAC_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DAC_H
/********************************************************************************************
* Included Files
@@ -232,4 +232,4 @@
* Public Functions
********************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_DACE_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DAC_H */
diff --git a/arch/arm/src/kinetis/kinetis_dma.h b/arch/arm/src/kinetis/chip/kinetis_dma.h
similarity index 96%
rename from arch/arm/src/kinetis/kinetis_dma.h
rename to arch/arm/src/kinetis/chip/kinetis_dma.h
index 9876a46a0f0fdc794f55676c284e2f446ea5dd8a..aec14d32f4fd5d7e88adf8082560486bbd608345 100644
--- a/arch/arm/src/kinetis/kinetis_dma.h
+++ b/arch/arm/src/kinetis/chip/kinetis_dma.h
@@ -1,7 +1,7 @@
/****************************************************************************************************
- * arch/arm/src/kinetis/kinetis_dma.h
+ * arch/arm/src/kinetis/chip/kinetis_dma.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
****************************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_DMA_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_DMA_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMA_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMA_H
/****************************************************************************************************
* Included Files
@@ -83,18 +83,20 @@
#define KINETIS_DMA_DCHPRI13_OFFSET 0x010e /* Channel 13 Priority Register */
#define KINETIS_DMA_DCHPRI12_OFFSET 0x010f /* Channel 12 Priority Register */
-#define KINETIS_DMA_TCD_OFFSET(n) (0x0000+((n) << 5))
-#define KINETIS_DMA_TCD_SADDR_OFFSET 0x0000 /* TCD Source Address */
-#define KINETIS_DMA_TCD_SOFF_OFFSET 0x0004 /* TCD Signed Source Address Offset */
-#define KINETIS_DMA_TCD_ATTR_OFFSET 0x0006 /* TCD Transfer Attributes */
-#define KINETIS_DMA_TCD_NBYTES_OFFSET 0x0008 /* TCD Minor Byte Count */
-#define KINETIS_DMA_TCD_SLAST_OFFSET 0x000c /* TCD Last Source Address Adjustment */
-#define KINETIS_DMA_TCD_DADDR_OFFSET 0x0010 /* TCD Destination Address */
-#define KINETIS_DMA_TCD_DOFF_OFFSET 0x0014 /* TCD Signed Destination Address Offset */
-#define KINETIS_DMA_TCD_CITER_OFFSET 0x0016 /* TCD Current Minor Loop Link, Major Loop Count */
-#define KINETIS_DMA_TCD_DLASTSGA_OFFSET 0x0018 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
-#define KINETIS_DMA_TCD_CSR_OFFSET 0x001c /* TCD Control and Status */
-#define KINETIS_DMA_TCD_BITER_OFFSET 0x001e /* TCD Beginning Minor Loop Link, Major Loop Count */
+#ifndef KINETIS_K64
+# define KINETIS_DMA_TCD_OFFSET(n) (0x0000+((n) << 5))
+# define KINETIS_DMA_TCD_SADDR_OFFSET 0x0000 /* TCD Source Address */
+# define KINETIS_DMA_TCD_SOFF_OFFSET 0x0004 /* TCD Signed Source Address Offset */
+# define KINETIS_DMA_TCD_ATTR_OFFSET 0x0006 /* TCD Transfer Attributes */
+# define KINETIS_DMA_TCD_NBYTES_OFFSET 0x0008 /* TCD Minor Byte Count */
+# define KINETIS_DMA_TCD_SLAST_OFFSET 0x000c /* TCD Last Source Address Adjustment */
+# define KINETIS_DMA_TCD_DADDR_OFFSET 0x0010 /* TCD Destination Address */
+# define KINETIS_DMA_TCD_DOFF_OFFSET 0x0014 /* TCD Signed Destination Address Offset */
+# define KINETIS_DMA_TCD_CITER_OFFSET 0x0016 /* TCD Current Minor Loop Link, Major Loop Count */
+# define KINETIS_DMA_TCD_DLASTSGA_OFFSET 0x0018 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
+# define KINETIS_DMA_TCD_CSR_OFFSET 0x001c /* TCD Control and Status */
+# define KINETIS_DMA_TCD_BITER_OFFSET 0x001e /* TCD Beginning Minor Loop Link, Major Loop Count */
+#endif
#define KINETIS_DMA_TCD0_SADDR_OFFSET 0x0000 /* TCD Source Address */
#define KINETIS_DMA_TCD0_SOFF_OFFSET 0x0004 /* TCD Signed Source Address Offset */
@@ -323,19 +325,21 @@
#define KINETIS_DMA_DCHPRI13 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI13_OFFSET)
#define KINETIS_DMA_DCHPRI12 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI12_OFFSET)
-#define KINETIS_DMA_TCD_BASE(n) (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD_OFFSET(n))
-
-#define KINETIS_DMA_TCD_SADDR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SADDR_OFFSET)
-#define KINETIS_DMA_TCD_SOFF(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SOFF_OFFSET)
-#define KINETIS_DMA_TCD_ATTR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_ATTR_OFFSET)
-#define KINETIS_DMA_TCD_NBYTES(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_NBYTES_OFFSET)
-#define KINETIS_DMA_TCD_SLAST(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SLAST_OFFSET)
-#define KINETIS_DMA_TCD_DADDR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DADDR_OFFSET)
-#define KINETIS_DMA_TCD_DOFF(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DOFF_OFFSET)
-#define KINETIS_DMA_TCD_CITER(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_CITER_OFFSET)
-#define KINETIS_DMA_TCD_DLASTSGA(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DLASTSGA_OFFSET)
-#define KINETIS_DMA_TCD_CSR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_CSR_OFFSET)
-#define KINETIS_DMA_TCD_BITER(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_BITER_OFFSET)
+#ifndef KINETIS_K64
+# define KINETIS_DMA_TCD_BASE(n) (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD_OFFSET(n))
+
+# define KINETIS_DMA_TCD_SADDR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SADDR_OFFSET)
+# define KINETIS_DMA_TCD_SOFF(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SOFF_OFFSET)
+# define KINETIS_DMA_TCD_ATTR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_ATTR_OFFSET)
+# define KINETIS_DMA_TCD_NBYTES(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_NBYTES_OFFSET)
+# define KINETIS_DMA_TCD_SLAST(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SLAST_OFFSET)
+# define KINETIS_DMA_TCD_DADDR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DADDR_OFFSET)
+# define KINETIS_DMA_TCD_DOFF(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DOFF_OFFSET)
+# define KINETIS_DMA_TCD_CITER(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_CITER_OFFSET)
+# define KINETIS_DMA_TCD_DLASTSGA(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DLASTSGA_OFFSET)
+# define KINETIS_DMA_TCD_CSR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_CSR_OFFSET)
+# define KINETIS_DMA_TCD_BITER(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_BITER_OFFSET)
+#endif
#define KINETIS_DMA_TCD0_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD0_SADDR_OFFSET)
#define KINETIS_DMA_TCD0_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD0_SOFF_OFFSET)
@@ -772,4 +776,4 @@
* Public Functions
****************************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_DMA_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMA_H */
diff --git a/arch/arm/src/kinetis/kinetis_dmamux.h b/arch/arm/src/kinetis/chip/kinetis_dmamux.h
similarity index 95%
rename from arch/arm/src/kinetis/kinetis_dmamux.h
rename to arch/arm/src/kinetis/chip/kinetis_dmamux.h
index b83579180ea0ca53d2d0b99d55ac6de604ab51e8..d63feb8da31e3d562ea1c033afc094a7d1121f67 100644
--- a/arch/arm/src/kinetis/kinetis_dmamux.h
+++ b/arch/arm/src/kinetis/chip/kinetis_dmamux.h
@@ -1,7 +1,7 @@
/********************************************************************************************
- * arch/arm/src/kinetis/kinetis_dmamux.h
+ * arch/arm/src/kinetis/chip/kinetis_dmamux.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
********************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_DMAMUX_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_DMAMUX_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMAMUX_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMAMUX_H
/********************************************************************************************
* Included Files
@@ -108,4 +108,4 @@
* Public Functions
********************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_DMAMUX_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMAMUX_H */
diff --git a/arch/arm/src/kinetis/kinetis_dspi.h b/arch/arm/src/kinetis/chip/kinetis_dspi.h
similarity index 98%
rename from arch/arm/src/kinetis/kinetis_dspi.h
rename to arch/arm/src/kinetis/chip/kinetis_dspi.h
index e682ef23e8555ab5f706903846579803d7c16e39..99507cb9e851bb1ab1c1274617205eec2c532e72 100644
--- a/arch/arm/src/kinetis/kinetis_dspi.h
+++ b/arch/arm/src/kinetis/chip/kinetis_dspi.h
@@ -1,7 +1,7 @@
/********************************************************************************************
- * arch/arm/src/kinetis/kinetis_dspi.h
+ * arch/arm/src/kinetis/chip/kinetis_dspi.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
********************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_DSPI_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_DSPI_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DSPI_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DSPI_H
/********************************************************************************************
* Included Files
@@ -318,4 +318,4 @@
* Public Functions
********************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_DSPI_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DSPI_H */
diff --git a/arch/arm/src/kinetis/kinetis_enet.h b/arch/arm/src/kinetis/chip/kinetis_enet.h
similarity index 99%
rename from arch/arm/src/kinetis/kinetis_enet.h
rename to arch/arm/src/kinetis/chip/kinetis_enet.h
index cadd006d8ce114644b37fc9a77b5c2cb87dd67f3..8f34d0c7f6468ecfd1f6fd9ed32442786d240107 100644
--- a/arch/arm/src/kinetis/kinetis_enet.h
+++ b/arch/arm/src/kinetis/chip/kinetis_enet.h
@@ -1,7 +1,7 @@
/********************************************************************************************
- * arch/arm/src/kinetis/kinetis_enet.h
+ * arch/arm/src/kinetis/chip/kinetis_enet.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
********************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_ENET_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_ENET_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ENET_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ENET_H
/********************************************************************************************
* Included Files
@@ -649,4 +649,4 @@ struct enet_desc_s
********************************************************************************************/
#endif /* KINETIS_NENET && KINETIS_NENET > 0 */
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_ENET_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ENET_H */
diff --git a/arch/arm/src/kinetis/kinetis_ewm.h b/arch/arm/src/kinetis/chip/kinetis_ewm.h
similarity index 93%
rename from arch/arm/src/kinetis/kinetis_ewm.h
rename to arch/arm/src/kinetis/chip/kinetis_ewm.h
index e259a3cf29af2f891e40532f4afd01ff3e5626bc..e91bc28c2c60fda5d1397b45092b62bd81f6618e 100644
--- a/arch/arm/src/kinetis/kinetis_ewm.h
+++ b/arch/arm/src/kinetis/chip/kinetis_ewm.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_ewm.h
+ * arch/arm/src/kinetis/chip/kinetis_ewm.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_EWM_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_EWM_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_EWM_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_EWM_H
/************************************************************************************
* Included Files
@@ -87,4 +87,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_EWM_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_EWM_H */
diff --git a/arch/arm/src/kinetis/kinetis_flexbus.h b/arch/arm/src/kinetis/chip/kinetis_flexbus.h
similarity index 97%
rename from arch/arm/src/kinetis/kinetis_flexbus.h
rename to arch/arm/src/kinetis/chip/kinetis_flexbus.h
index 37992320fb18804f50c1d985bcfe5a3e13a85bef..7c063d086976a06e039aa101ffccfe775084b21d 100644
--- a/arch/arm/src/kinetis/kinetis_flexbus.h
+++ b/arch/arm/src/kinetis/chip/kinetis_flexbus.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_flexbus.h
+ * arch/arm/src/kinetis/chip/kinetis_flexbus.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXBUS_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXBUS_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXBUS_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXBUS_H
/************************************************************************************
* Included Files
@@ -210,4 +210,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXBUS_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXBUS_H */
diff --git a/arch/arm/src/kinetis/kinetis_flexcan.h b/arch/arm/src/kinetis/chip/kinetis_flexcan.h
similarity index 98%
rename from arch/arm/src/kinetis/kinetis_flexcan.h
rename to arch/arm/src/kinetis/chip/kinetis_flexcan.h
index db151d5403474d7dd1dc48ee249a8043846ae774..9d3ec74a38168c2a7ef7a0de6897dd401fdbb17e 100644
--- a/arch/arm/src/kinetis/kinetis_flexcan.h
+++ b/arch/arm/src/kinetis/chip/kinetis_flexcan.h
@@ -1,7 +1,7 @@
/****************************************************************************************************
- * arch/arm/src/kinetis/kinetis_flexcan.h
+ * arch/arm/src/kinetis/chip/kinetis_flexcan.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
****************************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXCAN_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXCAN_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXCAN_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXCAN_H
/****************************************************************************************************
* Included Files
@@ -315,4 +315,4 @@
* Public Functions
****************************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXCAN_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXCAN_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_fmc.h b/arch/arm/src/kinetis/chip/kinetis_fmc.h
new file mode 100644
index 0000000000000000000000000000000000000000..d189d657ddd135af9d3b45b70ee36953c5717296
--- /dev/null
+++ b/arch/arm/src/kinetis/chip/kinetis_fmc.h
@@ -0,0 +1,75 @@
+/********************************************************************************************
+ * arch/arm/src/kinetis/chip/kinetis_fmc.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FMC_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FMC_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+/* This file is just a wrapper around pin muxing header files for the Kinetis family selected
+ * by the logic in chip.h.
+ */
+
+#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K60)
+# include "chip/kinetis_k20k40k60fmc.h"
+#elif defined(KINETIS_K64)
+# include "chip/kinetis_k64fmc.h"
+#else
+# error "No FMC definitions for this Kinetis part"
+#endif
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FMC_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_ftfe.h b/arch/arm/src/kinetis/chip/kinetis_ftfe.h
new file mode 100644
index 0000000000000000000000000000000000000000..13794d97dbe08a6ad7809ac2a5380fde12fd0c95
--- /dev/null
+++ b/arch/arm/src/kinetis/chip/kinetis_ftfe.h
@@ -0,0 +1,159 @@
+/************************************************************************************
+ * arch/arm/src/kinetis/chip/kinetis_ftfe.h
+ *
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTFE_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTFE_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define KINETIS_FTFE_FSTAT_OFFSET 0x0000 /* Flash Status Register */
+#define KINETIS_FTFE_FCNFG_OFFSET 0x0001 /* Flash Configuration Register */
+#define KINETIS_FTFE_FSEC_OFFSET 0x0002 /* Flash Security Register */
+#define KINETIS_FTFE_FOPT_OFFSET 0x0003 /* Flash Option Register */
+
+#define KINETIS_FTFE_FCCOB3_OFFSET 0x0004 /* Flash Common Command Object Registers */
+#define KINETIS_FTFE_FCCOB2_OFFSET 0x0005 /* Flash Common Command Object Registers */
+#define KINETIS_FTFE_FCCOB1_OFFSET 0x0006 /* Flash Common Command Object Registers */
+#define KINETIS_FTFE_FCCOB0_OFFSET 0x0007 /* Flash Common Command Object Registers */
+#define KINETIS_FTFE_FCCOB7_OFFSET 0x0008 /* Flash Common Command Object Registers */
+#define KINETIS_FTFE_FCCOB6_OFFSET 0x0009 /* Flash Common Command Object Registers */
+#define KINETIS_FTFE_FCCOB5_OFFSET 0x000a /* Flash Common Command Object Registers */
+#define KINETIS_FTFE_FCCOB4_OFFSET 0x000b /* Flash Common Command Object Registers */
+#define KINETIS_FTFE_FCCOBB_OFFSET 0x000c /* Flash Common Command Object Registers */
+#define KINETIS_FTFE_FCCOBA_OFFSET 0x000d /* Flash Common Command Object Registers */
+#define KINETIS_FTFE_FCCOB9_OFFSET 0x000e /* Flash Common Command Object Registers */
+#define KINETIS_FTFE_FCCOB8_OFFSET 0x000f /* Flash Common Command Object Registers */
+#define KINETIS_FTFE_FPROT3_OFFSET 0x0010 /* Program Flash Protection Registers */
+#define KINETIS_FTFE_FPROT2_OFFSET 0x0011 /* Program Flash Protection Registers */
+#define KINETIS_FTFE_FPROT1_OFFSET 0x0012 /* Program Flash Protection Registers */
+#define KINETIS_FTFE_FPROT0_OFFSET 0x0013 /* Program Flash Protection Registers */
+#define KINETIS_FTFE_FEPROT_OFFSET 0x0016 /* EEPROM Protection Register */
+#define KINETIS_FTFE_FDPROT_OFFSET 0x0017 /* Data Flash Protection Register */
+
+/* Register Addresses ***************************************************************/
+
+#define KINETIS_FTFE_FSTAT (KINETIS_FTFE_BASE+KINETIS_FTFE_FSTAT_OFFSET)
+#define KINETIS_FTFE_FCNFG (KINETIS_FTFE_BASE+KINETIS_FTFE_FCNFG_OFFSET)
+#define KINETIS_FTFE_FSEC (KINETIS_FTFE_BASE+KINETIS_FTFE_FSEC_OFFSET)
+#define KINETIS_FTFE_FOPT (KINETIS_FTFE_BASE+KINETIS_FTFE_FOPT_OFFSET)
+#define KINETIS_FTFE_FCCOB3 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB3_OFFSET)
+#define KINETIS_FTFE_FCCOB2 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB2_OFFSET)
+#define KINETIS_FTFE_FCCOB1 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB1_OFFSET)
+#define KINETIS_FTFE_FCCOB0 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB0_OFFSET)
+#define KINETIS_FTFE_FCCOB7 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB7_OFFSET)
+#define KINETIS_FTFE_FCCOB6 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB6_OFFSET)
+#define KINETIS_FTFE_FCCOB5 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB5_OFFSET)
+#define KINETIS_FTFE_FCCOB4 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB4_OFFSET)
+#define KINETIS_FTFE_FCCOBB (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOBB_OFFSET)
+#define KINETIS_FTFE_FCCOBA (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOBA_OFFSET)
+#define KINETIS_FTFE_FCCOB9 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB9_OFFSET)
+#define KINETIS_FTFE_FCCOB8 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB8_OFFSET)
+#define KINETIS_FTFE_FPROT3 (KINETIS_FTFE_BASE+KINETIS_FTFE_FPROT3_OFFSET)
+#define KINETIS_FTFE_FPROT2 (KINETIS_FTFE_BASE+KINETIS_FTFE_FPROT2_OFFSET)
+#define KINETIS_FTFE_FPROT1 (KINETIS_FTFE_BASE+KINETIS_FTFE_FPROT1_OFFSET)
+#define KINETIS_FTFE_FPROT0 (KINETIS_FTFE_BASE+KINETIS_FTFE_FPROT0_OFFSET)
+#define KINETIS_FTFE_FEPROT (KINETIS_FTFE_BASE+KINETIS_FTFE_FEPROT_OFFSET)
+#define KINETIS_FTFE_FDPROT (KINETIS_FTFE_BASE+KINETIS_FTFE_FDPROT_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* Flash Status Register */
+
+#define FTFE_FSTAT_MGSTAT0 (1 << 0) /* Bit 0: Memory Controller Command Completion Status Flag */
+ /* Bits 1-3: Reserved */
+#define FTFE_FSTAT_FPVIOL (1 << 4) /* Bit 4: Flash Protection Violation Flag */
+#define FTFE_FSTAT_ACCERR (1 << 5) /* Bit 5: Flash Access Error Flag */
+#define FTFE_FSTAT_RDCOLERR (1 << 6) /* Bit 6: FTFE Read Collision Error Flag */
+#define FTFE_FSTAT_CCIF (1 << 7) /* Bit 7: Command Complete Interrupt Flag */
+
+/* Flash Configuration Register */
+
+#define FTFE_FCNFG_EEERDY (1 << 0) /* Bit 0: FEEPROM backup data copied to FlexRAM */
+#define FTFE_FCNFG_RAMRDY (1 << 1) /* Bit 1: RAM Ready */
+#define FTFE_FCNFG_PFLSH (1 << 2) /* Bit 2: FTFE configuration */
+#define FTFE_FCNFG_SWAP (1 << 3) /* Bit 3: Swap */
+#define FTFE_FCNFG_ERSSUSP (1 << 4) /* Bit 4: Erase Suspend */
+#define FTFE_FCNFG_ERSAREQ (1 << 5) /* Bit 5: Erase All Request */
+#define FTFE_FCNFG_RDCOLLIE (1 << 6) /* Bit 6: Read Collision Error Interrupt Enable */
+#define FTFE_FCNFG_CCIE (1 << 7) /* Bit 7: Command Complete Interrupt Enable */
+
+/* Flash Security Register */
+
+#define FTFE_FSEC_SEC_SHIFT (0) /* Bits 0-1: Flash Security */
+#define FTFE_FSEC_SEC_MASK (3 << FTFE_FSEC_SEC_SHIFT)
+# define FTFE_FSEC_SEC_SECURE (0 << FTFE_FSEC_SEC_SHIFT) /* 00,01,11: status is secure */
+# define FTFE_FSEC_SEC_UNSECURE (2 << FTFE_FSEC_SEC_SHIFT) /* 10: status is insecure */
+#define FTFE_FSEC_FSLACC_SHIFT (2) /* Bits 2-3: Freescale Failure Analysis Access Code */
+#define FTFE_FSEC_FSLACC_MASK (3 << FTFE_FSEC_FSLACC_SHIFT)
+# define FTFE_FSEC_FSLACC_GRANTED (0 << FTFE_FSEC_FSLACC_SHIFT) /* 00 or 11: Access granted */
+# define FTFE_FSEC_FSLACC_DENIED (1 << FTFE_FSEC_FSLACC_SHIFT) /* 01 or 10: Access denied */
+#define FTFE_FSEC_MEEN_SHIFT (4) /* Bits 4-5: Mass Erase Enable Bits */
+#define FTFE_FSEC_MEEN_MASK (3 << FTFE_FSEC_MEEN_SHIFT)
+# define FTFE_FSEC_MEEN_ENABLED (0 << FTFE_FSEC_MEEN_SHIFT) /* All values are enabled */
+#define FTFE_FSEC_KEYEN_SHIFT (6) /* Bits 6-7: Backdoor Key Security Enable */
+#define FTFE_FSEC_KEYEN_MASK (3 << FTFE_FSEC_KEYEN_SHIFT)
+# define FTFE_FSEC_KEYEN_DISABLED (1 << FTFE_FSEC_KEYEN_SHIFT) /* All values are disabled */
+
+/* Flash Option Register (32-bits, see Chip Configuration details) */
+/* Flash Common Command Object Registers (8-bit flash command data) */
+/* Program Flash Protection Registers (8-bit flash protection data) */
+/* EEPROM Protection Register (8-bit eeprom protection data) */
+/* Data Flash Protection Register (8-bit data flash protection data) */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTFE_H */
diff --git a/arch/arm/src/kinetis/kinetis_ftm.h b/arch/arm/src/kinetis/chip/kinetis_ftm.h
similarity index 90%
rename from arch/arm/src/kinetis/kinetis_ftm.h
rename to arch/arm/src/kinetis/chip/kinetis_ftm.h
index 2f031b5dd9b68e6e1d71831b638a213f72478d04..1402f5e8d8a3af88caace4bc3e0d17d6d12b8b0d 100644
--- a/arch/arm/src/kinetis/kinetis_ftm.h
+++ b/arch/arm/src/kinetis/chip/kinetis_ftm.h
@@ -1,7 +1,7 @@
/********************************************************************************************
- * arch/arm/src/kinetis/kinetis_ftm.h
+ * arch/arm/src/kinetis/chip/kinetis_ftm.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
********************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_FTM_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_FTM_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTM_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTM_H
/********************************************************************************************
* Included Files
@@ -228,6 +228,50 @@
#define KINETIS_FTM2_SWOCTRL (KINETIS_FTM2_BASE+KINETIS_FTM_SWOCTRL_OFFSET)
#define KINETIS_FTM2_PWMLOAD (KINETIS_FTM2_BASE+KINETIS_FTM_PWMLOAD_OFFSET)
+#define KINETIS_FTM3_SC (KINETIS_FTM3_BASE+KINETIS_FTM_SC_OFFSET)
+#define KINETIS_FTM3_CNT (KINETIS_FTM3_BASE+KINETIS_FTM_CNT_OFFSET)
+#define KINETIS_FTM3_MOD (KINETIS_FTM3_BASE+KINETIS_FTM_MOD_OFFSET)
+
+#define KINETIS_FTM3_CSC(n) (KINETIS_FTM3_BASE+KINETIS_FTM_CSC_OFFSET(n))
+#define KINETIS_FTM3_CV(n) (KINETIS_FTM3_BASE+KINETIS_FTM_CV_OFFSET(n))
+#define KINETIS_FTM3_C0SC (KINETIS_FTM3_BASE+KINETIS_FTM_C0SC_OFFSET)
+#define KINETIS_FTM3_C0V (KINETIS_FTM3_BASE+KINETIS_FTM_C0V_OFFSET)
+#define KINETIS_FTM3_C1SC (KINETIS_FTM3_BASE+KINETIS_FTM_C1SC_OFFSET)
+#define KINETIS_FTM3_C1V (KINETIS_FTM3_BASE+KINETIS_FTM_C1V_OFFSET)
+#define KINETIS_FTM3_C2SC (KINETIS_FTM3_BASE+KINETIS_FTM_C2SC_OFFSET)
+#define KINETIS_FTM3_C2V (KINETIS_FTM3_BASE+KINETIS_FTM_C2V_OFFSET)
+#define KINETIS_FTM3_C3SC (KINETIS_FTM3_BASE+KINETIS_FTM_C3SC_OFFSET)
+#define KINETIS_FTM3_C3V (KINETIS_FTM3_BASE+KINETIS_FTM_C3V_OFFSET)
+#define KINETIS_FTM3_C4SC (KINETIS_FTM3_BASE+KINETIS_FTM_C4SC_OFFSET)
+#define KINETIS_FTM3_C4V (KINETIS_FTM3_BASE+KINETIS_FTM_C4V_OFFSET)
+#define KINETIS_FTM3_C5SC (KINETIS_FTM3_BASE+KINETIS_FTM_C5SC_OFFSET)
+#define KINETIS_FTM3_C5V (KINETIS_FTM3_BASE+KINETIS_FTM_C5V_OFFSET)
+#define KINETIS_FTM3_C6SC (KINETIS_FTM3_BASE+KINETIS_FTM_C6SC_OFFSET)
+#define KINETIS_FTM3_C6V (KINETIS_FTM3_BASE+KINETIS_FTM_C6V_OFFSET)
+#define KINETIS_FTM3_C7SC (KINETIS_FTM3_BASE+KINETIS_FTM_C7SC_OFFSET)
+#define KINETIS_FTM3_C7V (KINETIS_FTM3_BASE+KINETIS_FTM_C7V_OFFSET)
+
+#define KINETIS_FTM3_CNTIN (KINETIS_FTM3_BASE+KINETIS_FTM_CNTIN_OFFSET)
+#define KINETIS_FTM3_STATUS (KINETIS_FTM3_BASE+KINETIS_FTM_STATUS_OFFSET)
+#define KINETIS_FTM3_MODE (KINETIS_FTM3_BASE+KINETIS_FTM_MODE_OFFSET)
+#define KINETIS_FTM3_SYNC (KINETIS_FTM3_BASE+KINETIS_FTM_SYNC_OFFSET)
+#define KINETIS_FTM3_OUTINIT (KINETIS_FTM3_BASE+KINETIS_FTM_OUTINIT_OFFSET)
+#define KINETIS_FTM3_OUTMASK (KINETIS_FTM3_BASE+KINETIS_FTM_OUTMASK_OFFSET)
+#define KINETIS_FTM3_COMBINE (KINETIS_FTM3_BASE+KINETIS_FTM_COMBINE_OFFSET)
+#define KINETIS_FTM3_DEADTIME (KINETIS_FTM3_BASE+KINETIS_FTM_DEADTIME_OFFSET)
+#define KINETIS_FTM3_EXTTRIG (KINETIS_FTM3_BASE+KINETIS_FTM_EXTTRIG_OFFSET)
+#define KINETIS_FTM3_POL (KINETIS_FTM3_BASE+KINETIS_FTM_POL_OFFSET)
+#define KINETIS_FTM3_FMS (KINETIS_FTM3_BASE+KINETIS_FTM_FMS_OFFSET)
+#define KINETIS_FTM3_FILTER (KINETIS_FTM3_BASE+KINETIS_FTM_FILTER_OFFSET)
+#define KINETIS_FTM3_FLTCTRL (KINETIS_FTM3_BASE+KINETIS_FTM_FLTCTRL_OFFSET)
+#define KINETIS_FTM3_QDCTRL (KINETIS_FTM3_BASE+KINETIS_FTM_QDCTRL_OFFSET)
+#define KINETIS_FTM3_CONF (KINETIS_FTM3_BASE+KINETIS_FTM_CONF_OFFSET)
+#define KINETIS_FTM3_FLTPOL (KINETIS_FTM3_BASE+KINETIS_FTM_FLTPOL_OFFSET)
+#define KINETIS_FTM3_SYNCONF (KINETIS_FTM3_BASE+KINETIS_FTM_SYNCONF_OFFSET)
+#define KINETIS_FTM3_INVCTRL (KINETIS_FTM3_BASE+KINETIS_FTM_INVCTRL_OFFSET)
+#define KINETIS_FTM3_SWOCTRL (KINETIS_FTM3_BASE+KINETIS_FTM_SWOCTRL_OFFSET)
+#define KINETIS_FTM3_PWMLOAD (KINETIS_FTM3_BASE+KINETIS_FTM_PWMLOAD_OFFSET)
+
/* Register Bit Definitions *****************************************************************/
/* Status and Control */
@@ -525,4 +569,4 @@
* Public Functions
********************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_FTM_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTM_H */
diff --git a/arch/arm/src/kinetis/kinetis_gpio.h b/arch/arm/src/kinetis/chip/kinetis_gpio.h
similarity index 100%
rename from arch/arm/src/kinetis/kinetis_gpio.h
rename to arch/arm/src/kinetis/chip/kinetis_gpio.h
diff --git a/arch/arm/src/kinetis/chip/kinetis_i2c.h b/arch/arm/src/kinetis/chip/kinetis_i2c.h
new file mode 100644
index 0000000000000000000000000000000000000000..71f7624a46bd12943fa24f53f4f0e5ae849b839c
--- /dev/null
+++ b/arch/arm/src/kinetis/chip/kinetis_i2c.h
@@ -0,0 +1,295 @@
+/********************************************************************************************
+ * arch/arm/src/kinetis/chip/kinetis_i2c.h
+ *
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2CE_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2CE_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+/* Register Offsets *************************************************************************/
+
+#define KINETIS_I2C_A1_OFFSET 0x0000 /* I2C Address Register 1 */
+#define KINETIS_I2C_F_OFFSET 0x0001 /* I2C Frequency Divider register */
+#define KINETIS_I2C_C1_OFFSET 0x0002 /* I2C Control Register 1 */
+#define KINETIS_I2C_S_OFFSET 0x0003 /* I2C Status Register */
+#define KINETIS_I2C_D_OFFSET 0x0004 /* I2C Data I/O register */
+#define KINETIS_I2C_C2_OFFSET 0x0005 /* I2C Control Register 2 */
+#define KINETIS_I2C_FLT_OFFSET 0x0006 /* I2C Programmable Input Glitch Filter register */
+#define KINETIS_I2C_RA_OFFSET 0x0007 /* I2C Range Address register */
+#define KINETIS_I2C_SMB_OFFSET 0x0008 /* I2C SMBus Control and Status register */
+#define KINETIS_I2C_A2_OFFSET 0x0009 /* I2C Address Register 2 */
+#define KINETIS_I2C_SLTH_OFFSET 0x000a /* I2C SCL Low Timeout Register High */
+#define KINETIS_I2C_SLTL_OFFSET 0x000b /* I2C SCL Low Timeout Register Low */
+
+/* Register Addresses ***********************************************************************/
+
+#define KINETIS_I2C0_A1 (KINETIS_I2C0_BASE+KINETIS_I2C_A1_OFFSET)
+#define KINETIS_I2C0_F (KINETIS_I2C0_BASE+KINETIS_I2C_F_OFFSET)
+#define KINETIS_I2C0_C1 (KINETIS_I2C0_BASE+KINETIS_I2C_C1_OFFSET)
+#define KINETIS_I2C0_S (KINETIS_I2C0_BASE+KINETIS_I2C_S_OFFSET)
+#define KINETIS_I2C0_D (KINETIS_I2C0_BASE+KINETIS_I2C_D_OFFSET)
+#define KINETIS_I2C0_C2 (KINETIS_I2C0_BASE+KINETIS_I2C_C2_OFFSET)
+#define KINETIS_I2C0_FLT (KINETIS_I2C0_BASE+KINETIS_I2C_FLT_OFFSET)
+#define KINETIS_I2C0_RA (KINETIS_I2C0_BASE+KINETIS_I2C_RA_OFFSET)
+#define KINETIS_I2C0_SMB (KINETIS_I2C0_BASE+KINETIS_I2C_SMB_OFFSET)
+#define KINETIS_I2C0_A2 (KINETIS_I2C0_BASE+KINETIS_I2C_A2_OFFSET)
+#define KINETIS_I2C0_SLTH (KINETIS_I2C0_BASE+KINETIS_I2C_SLTH_OFFSET)
+#define KINETIS_I2C0_SLTL (KINETIS_I2C0_BASE+KINETIS_I2C_SLTL_OFFSET)
+
+#ifdef CONFIG_KINETIS_HAVE_I2C1
+# define KINETIS_I2C1_A1 (KINETIS_I2C1_BASE+KINETIS_I2C_A1_OFFSET)
+# define KINETIS_I2C1_F (KINETIS_I2C1_BASE+KINETIS_I2C_F_OFFSET)
+# define KINETIS_I2C1_C1 (KINETIS_I2C1_BASE+KINETIS_I2C_C1_OFFSET)
+# define KINETIS_I2C1_S (KINETIS_I2C1_BASE+KINETIS_I2C_S_OFFSET)
+# define KINETIS_I2C1_D (KINETIS_I2C1_BASE+KINETIS_I2C_D_OFFSET)
+# define KINETIS_I2C1_C2 (KINETIS_I2C1_BASE+KINETIS_I2C_C2_OFFSET)
+# define KINETIS_I2C1_FLT (KINETIS_I2C1_BASE+KINETIS_I2C_FLT_OFFSET)
+# define KINETIS_I2C1_RA (KINETIS_I2C1_BASE+KINETIS_I2C_RA_OFFSET)
+# define KINETIS_I2C1_SMB (KINETIS_I2C1_BASE+KINETIS_I2C_SMB_OFFSET)
+# define KINETIS_I2C1_A2 (KINETIS_I2C1_BASE+KINETIS_I2C_A2_OFFSET)
+# define KINETIS_I2C1_SLTH (KINETIS_I2C1_BASE+KINETIS_I2C_SLTH_OFFSET)
+# define KINETIS_I2C1_SLTL (KINETIS_I2C1_BASE+KINETIS_I2C_SLTL_OFFSET)
+#endif
+
+#ifdef CONFIG_KINETIS_HAVE_I2C2
+# define KINETIS_I2C2_A1 (KINETIS_I2C2_BASE+KINETIS_I2C_A1_OFFSET)
+# define KINETIS_I2C2_F (KINETIS_I2C2_BASE+KINETIS_I2C_F_OFFSET)
+# define KINETIS_I2C2_C1 (KINETIS_I2C2_BASE+KINETIS_I2C_C1_OFFSET)
+# define KINETIS_I2C2_S (KINETIS_I2C2_BASE+KINETIS_I2C_S_OFFSET)
+# define KINETIS_I2C2_D (KINETIS_I2C2_BASE+KINETIS_I2C_D_OFFSET)
+# define KINETIS_I2C2_C2 (KINETIS_I2C2_BASE+KINETIS_I2C_C2_OFFSET)
+# define KINETIS_I2C2_FLT (KINETIS_I2C2_BASE+KINETIS_I2C_FLT_OFFSET)
+# define KINETIS_I2C2_RA (KINETIS_I2C2_BASE+KINETIS_I2C_RA_OFFSET)
+# define KINETIS_I2C2_SMB (KINETIS_I2C2_BASE+KINETIS_I2C_SMB_OFFSET)
+# define KINETIS_I2C2_A2 (KINETIS_I2C2_BASE+KINETIS_I2C_A2_OFFSET)
+# define KINETIS_I2C2_SLTH (KINETIS_I2C2_BASE+KINETIS_I2C_SLTH_OFFSET)
+# define KINETIS_I2C2_SLTL (KINETIS_I2C2_BASE+KINETIS_I2C_SLTL_OFFSET)
+#endif
+
+/* Register Bit Definitions *****************************************************************/
+
+/* I2C Address Register 1 (8-bit) */
+ /* Bit 0: Reserved */
+#define I2C_A1_SHIFT (1) /* Bits 1-7: Address */
+#define I2C_A1_MASK (0x7f << I2C_A1_SHIFT)
+
+/* I2C Frequency Divider register (8-bit) */
+
+#define I2C_F_ICR_SHIFT (0) /* Bits 0-5: Clock rate */
+#define I2C_F_ICR_MASK (0x3f << I2C_F_ICR_SHIFT)
+# define I2C_F_ICR(n) ((uint8_t)(n) << I2C_F_ICR_SHIFT)
+#define I2C_F_MULT_SHIFT (6) /* Bits 6-7: Multiplier factor */
+#define I2C_F_MULT_MASK (3 << I2C_F_MULT_SHIFT)
+# define I2C_F_MULT_1 (0 << I2C_F_MULT_SHIFT)
+# define I2C_F_MULT_2 (1 << I2C_F_MULT_SHIFT)
+# define I2C_F_MULT_4 (2 << I2C_F_MULT_SHIFT)
+
+/* From Table 51-54. I2C divider and hold values. Duplicate divider values differ in hold
+ * times. Refer to the Table 51-54. in the K64 Sub-Family Reference Manual.
+ */
+
+#define I2C_F_DIV20 ((uint8_t)0x00)
+#define I2C_F_DIV22 ((uint8_t)0x01)
+#define I2C_F_DIV24 ((uint8_t)0x02)
+#define I2C_F_DIV26 ((uint8_t)0x03)
+#define I2C_F_DIV28 ((uint8_t)0x04)
+#define I2C_F_DIV30 ((uint8_t)0x05)
+#define I2C_F_DIV34 ((uint8_t)0x06)
+#define I2C_F_DIV36 ((uint8_t)0x0a)
+#define I2C_F_DIV40_1 ((uint8_t)0x07)
+#define I2C_F_DIV41 ((uint8_t)0x08)
+
+#define I2C_F_DIV32 ((uint8_t)0x09)
+#define I2C_F_DIV36 ((uint8_t)0x0a)
+#define I2C_F_DIV40_2 ((uint8_t)0x0b)
+#define I2C_F_DIV44 ((uint8_t)0x0c)
+#define I2C_F_DIV48_1 ((uint8_t)0x0d)
+#define I2C_F_DIV56_1 ((uint8_t)0x0e)
+#define I2C_F_DIV68 ((uint8_t)0x0f)
+
+#define I2C_F_DIV48_2 ((uint8_t)0x10)
+#define I2C_F_DIV56_2 ((uint8_t)0x11)
+#define I2C_F_DIV64 ((uint8_t)0x12)
+#define I2C_F_DIV72 ((uint8_t)0x13)
+#define I2C_F_DIV80_1 ((uint8_t)0x14)
+#define I2C_F_DIV88 ((uint8_t)0x15)
+#define I2C_F_DIV104 ((uint8_t)0x16)
+#define I2C_F_DIV128_1 ((uint8_t)0x17)
+
+#define I2C_F_DIV80_2 ((uint8_t)0x18)
+#define I2C_F_DIV96 ((uint8_t)0x19)
+#define I2C_F_DIV112 ((uint8_t)0x1a)
+#define I2C_F_DIV128_2 ((uint8_t)0x1b)
+#define I2C_F_DIV144 ((uint8_t)0x1c)
+#define I2C_F_DIV160_1 ((uint8_t)0x1d)
+#define I2C_F_DIV192_1 ((uint8_t)0x1e)
+#define I2C_F_DIV240 ((uint8_t)0x1f)
+
+#define I2C_F_DIV160_2 ((uint8_t)0x20)
+#define I2C_F_DIV192_2 ((uint8_t)0x1e)
+#define I2C_F_DIV224 ((uint8_t)0x22)
+#define I2C_F_DIV256 ((uint8_t)0x23)
+#define I2C_F_DIV288 ((uint8_t)0x24)
+#define I2C_F_DIV320_1 ((uint8_t)0x25)
+#define I2C_F_DIV384_1 ((uint8_t)0x26)
+#define I2C_F_DIV480 ((uint8_t)0x27)
+
+#define I2C_F_DIV320_2 ((uint8_t)0x28)
+#define I2C_F_DIV384_2 ((uint8_t)0x29)
+#define I2C_F_DIV448 ((uint8_t)0x2a)
+#define I2C_F_DIV512 ((uint8_t)0x2b)
+#define I2C_F_DIV576 ((uint8_t)0x2c)
+#define I2C_F_DIV640_1 ((uint8_t)0x2d)
+#define I2C_F_DIV768_1 ((uint8_t)0x2e)
+#define I2C_F_DIV960 ((uint8_t)0x2f)
+
+#define I2C_F_DIV640_2 ((uint8_t)0x30)
+#define I2C_F_DIV768_3 ((uint8_t)0x31)
+#define I2C_F_DIV896 ((uint8_t)0x32)
+#define I2C_F_DIV1024 ((uint8_t)0x33)
+#define I2C_F_DIV1152 ((uint8_t)0x34)
+#define I2C_F_DIV1280_1 ((uint8_t)0x35)
+#define I2C_F_DIV1536_1 ((uint8_t)0x36)
+#define I2C_F_DIV1920 ((uint8_t)0x37)
+
+#define I2C_F_DIV1280_2 ((uint8_t)0x38)
+#define I2C_F_DIV1536_2 ((uint8_t)0x39)
+#define I2C_F_DIV1792 ((uint8_t)0x3a)
+#define I2C_F_DIV2048 ((uint8_t)0x3b)
+#define I2C_F_DIV2304 ((uint8_t)0x3c)
+#define I2C_F_DIV2560 ((uint8_t)0x3d)
+#define I2C_F_DIV3072 ((uint8_t)0x3e)
+#define I2C_F_DIV3840 ((uint8_t)0x3f)
+
+/* I2C Control Register 1 (8-bit) */
+
+#define I2C_C1_DMAEN (1 << 0) /* Bit 0: DMA enable */
+#define I2C_C1_WUEN (1 << 1) /* Bit 1: Wakeup enable */
+#define I2C_C1_RSTA (1 << 2) /* Bit 2: Repeat START */
+#define I2C_C1_TXAK (1 << 3) /* Bit 3: Transmit acknowledge enable */
+#define I2C_C1_TX (1 << 4) /* Bit 4: Transmit mode select */
+#define I2C_C1_MST (1 << 5) /* Bit 5: Master mode select */
+#define I2C_C1_IICIE (1 << 6) /* Bit 6: I2C interrupt enable */
+#define I2C_C1_IICEN (1 << 7) /* Bit 7: I2C enable */
+
+/* I2C Status Register (8-bit) */
+
+#define I2C_S_RXAK (1 << 0) /* Bit 0: Receive acknowledge */
+#define I2C_S_IICIF (1 << 1) /* Bit 1: Interrupt flag */
+#define I2C_S_SRW (1 << 2) /* Bit 2: Slave read/write */
+#define I2C_S_RAM (1 << 3) /* Bit 3: Range address match */
+#define I2C_S_ARBL (1 << 4) /* Bit 4: Arbitration lost */
+#define I2C_S_BUSY (1 << 5) /* Bit 5: Bus busy */
+#define I2C_S_IAAS (1 << 6) /* Bit 6: Addressed as a slave */
+#define I2C_S_TCF (1 << 7) /* Bit 7: Transfer complete flag */
+
+/* I2C Data I/O register (8-bit data register) */
+
+/* I2C Control Register 2 (8-bit) */
+
+#define I2C_C2_AD_SHIFT (0) /* Bits 0-2: Slave address */
+#define I2C_C2_AD_MASK (7 << I2C_C2_AD_SHIFT)
+# define I2C_C2_AD(n) ((uint8_t)(n) << I2C_C2_AD_SHIFT)
+#define I2C_C2_RMEN (1 << 3) /* Bit 3: Range address matching enable */
+#define I2C_C2_SBRC (1 << 4) /* Bit 4: Slave baud rate control */
+#define I2C_C2_HDRS (1 << 5) /* Bit 5: High drive select */
+#define I2C_C2_ADEXT (1 << 6) /* Bit 6: Address extension */
+#define I2C_C2_GCAEN (1 << 7) /* Bit 7: General call address enable */
+
+/* I2C Programmable Input Glitch Filter register (8-bit) */
+
+#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K60)
+# define I2C_FLT_SHIFT (0) /* Bits 0-4: I2C programmable filter factor */
+# define I2C_FLT_MASK (31 << I2C_FLT_SHIFT)
+# define I2C_FLT(n) ((uint8_t)(n) << I2C_FLT_SHIFT)
+ /* Bits 5-7: Reserved */
+#endif
+
+#ifdef KINETIS_K64
+# define I2C_FLT_SHIFT (0) /* Bits 0-3: I2C programmable filter factor */
+# define I2C_FLT_MASK (15 << I2C_FLT_SHIFT)
+# define I2C_FLT(n) ((uint8_t)(n) << I2C_FLT_SHIFT)
+# define I2C_FLT_STARTF (1 << 4) /* I2C bus start detect flag */
+# define I2C_FLT_SSIE (1 << 5) /* I2C bus stop or start interrupt enable */
+# define I2C_FLT_STOPF (1 << 6) /* I2C bus stop detect flag */
+# define I2C_FLT_SHEN (1 << 7) /* Stop hold enable */
+#endif
+
+/* I2C Range Address register (8-bit) */
+ /* Bit 0: Reserved */
+#define I2C_RA_SHIFT (1) /* Bits 1-7: Range slave address */
+#define I2C_RA_MASK (0x7f << I2C_RA_SHIFT)
+
+/* I2C SMBus Control and Status register (8-bit) */
+
+#define I2C_SMB_SHTF2IE (1 << 0) /* Bit 0: SHTF2 interrupt enable */
+#define I2C_SMB_SHTF2 (1 << 1) /* Bit 1: SCL high timeout flag 2 */
+#define I2C_SMB_SHTF1 (1 << 2) /* Bit 2: SCL high timeout flag 1 */
+#define I2C_SMB_SLTF (1 << 3) /* Bit 3: SCL low timeout flag */
+#define I2C_SMB_TCKSEL (1 << 4) /* Bit 4: Timeout counter clock select */
+#define I2C_SMB_SIICAEN (1 << 5) /* Bit 5: Second I2C address enable */
+#define I2C_SMB_ALERTEN (1 << 6) /* Bit 6: SMBus alert response address enable */
+#define I2C_SMB_FACK (1 << 7) /* Bit 7: Fast NACK/ACK enable */
+
+/* I2C Address Register 2 (8-bit) */
+ /* Bit 0: Reserved */
+#define I2C_A2_SHIFT (1) /* Bits 1-7: SMBus address */
+#define I2C_A2_MASK (0x7f << I2C_A2_SHIFT)
+
+/* I2C SCL Low Timeout Register High/Low (16-bit data in two 8-bit registers) */
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2CE_H */
diff --git a/arch/arm/src/kinetis/kinetis_i2s.h b/arch/arm/src/kinetis/chip/kinetis_i2s.h
similarity index 98%
rename from arch/arm/src/kinetis/kinetis_i2s.h
rename to arch/arm/src/kinetis/chip/kinetis_i2s.h
index 11bcc0995562bbb550a7380bf8191bf8534e2c42..5de08843bb078e71422f3b61270dbb821306489f 100644
--- a/arch/arm/src/kinetis/kinetis_i2s.h
+++ b/arch/arm/src/kinetis/chip/kinetis_i2s.h
@@ -1,7 +1,7 @@
/****************************************************************************************************
- * arch/arm/src/kinetis/kinetis_i2s.h
+ * arch/arm/src/kinetis/chip/kinetis_i2s.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
****************************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_I2S_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_I2S_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2S_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2S_H
/****************************************************************************************************
* Included Files
@@ -294,4 +294,4 @@
* Public Functions
****************************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_I2S_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2S_H */
diff --git a/arch/arm/src/kinetis/kinetis_fmc.h b/arch/arm/src/kinetis/chip/kinetis_k20k40k60fmc.h
similarity index 97%
rename from arch/arm/src/kinetis/kinetis_fmc.h
rename to arch/arm/src/kinetis/chip/kinetis_k20k40k60fmc.h
index 66f3a390926777330a36fed3374cc2a7632741d7..8dce4d682ef0289abb74d260a66c4b7b27b4633b 100644
--- a/arch/arm/src/kinetis/kinetis_fmc.h
+++ b/arch/arm/src/kinetis/chip/kinetis_k20k40k60fmc.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_fmc.h
+ * arch/arm/src/kinetis/kinetis_k20k40k60fmc.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_FMC_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_FMC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20K40K60FMC_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20K40K60FMC_H
/************************************************************************************
* Included Files
@@ -50,13 +50,13 @@
/* Register Offsets *****************************************************************/
-#define KINETIS_FMC_PFAPR_OFFSET 0x0000 /* Flash Access Protection Register */
-#define KINETIS_FMC_PFB0CR_OFFSET 0x0004 /* Flash Bank 0 Control Register */
-#define KINETIS_FMC_PFB1CR_OFFSET 0x0008 /* Flash Bank 1 Control Register */
+#define KINETIS_FMC_PFAPR_OFFSET 0x0000 /* Flash Access Protection Register */
+#define KINETIS_FMC_PFB0CR_OFFSET 0x0004 /* Flash Bank 0 Control Register */
+#define KINETIS_FMC_PFB1CR_OFFSET 0x0008 /* Flash Bank 1 Control Register */
/* Cache Directory Storage for way=w and set=s, w=0..3, s=0..7 */
-#define KINETIS_FMC_TAGVD_OFFSET(w,s) (0x100+((w)<<5)+((s)<<2))
+#define KINETIS_FMC_TAGVD_OFFSET(w,s) (0x100 + ((w) << 5) + ((s) << 2))
#define KINETIS_FMC_TAGVDW0S0_OFFSET 0x0100 /* Cache Directory Storage */
#define KINETIS_FMC_TAGVDW0S1_OFFSET 0x0104 /* Cache Directory Storage */
@@ -96,8 +96,8 @@
/* Cache Data Storage (upper and lower) for way=w and set=s, w=0..3, s=0..7 */
-#define KINETIS_FMC_DATAU_OFFSET(w,s) (0x200+((w)<<6)+((s)<<2))
-#define KINETIS_FMC_DATAL_OFFSET(w,s) (0x204+((w)<<6)+((s)<<2))
+#define KINETIS_FMC_DATAU_OFFSET(w,s) (0x200 + ((w) << 6) + ((s) << 2))
+#define KINETIS_FMC_DATAL_OFFSET(w,s) (0x204 + ((w) << 6) + ((s) << 2))
#define KINETIS_FMC_DATAW0S0U_OFFSET 0x0200 /* Cache Data Storage (upper word) */
#define KINETIS_FMC_DATAW0S0L_OFFSET 0x0204 /* Cache Data Storage (lower word) */
@@ -386,4 +386,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_FMC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20K40K60FMC_H */
diff --git a/arch/arm/src/kinetis/kinetis_mpu.h b/arch/arm/src/kinetis/chip/kinetis_k20k40k60mpu.h
similarity index 100%
rename from arch/arm/src/kinetis/kinetis_mpu.h
rename to arch/arm/src/kinetis/chip/kinetis_k20k40k60mpu.h
diff --git a/arch/arm/src/kinetis/chip/kinetis_k20memorymap.h b/arch/arm/src/kinetis/chip/kinetis_k20memorymap.h
new file mode 100644
index 0000000000000000000000000000000000000000..7d5aa615cd3512c74c66304030e973ea17f3a229
--- /dev/null
+++ b/arch/arm/src/kinetis/chip/kinetis_k20memorymap.h
@@ -0,0 +1,180 @@
+/************************************************************************************
+ * arch/arm/src/kinetis/chip/kinetis_k20memorymap.h
+ *
+ * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20MEMORYMAP_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+#ifdef KINETIS_K20
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Memory Map ***********************************************************************/
+/* K20 Family
+ *
+ * The memory map for the following parts is defined in Freescale document
+ * K20P64M72SF1RM
+ */
+
+#define KINETIS_FLASH_BASE 0x00000000 /* –0x0fffffff Program flash and read-
+ * only data (Includes exception
+ * vectors in first 1024 bytes) */
+#if !defined(KINETIS_FLEXMEM_SIZE)
+# define KINETIS_FLEXNVM_BASE 0x10000000 /* –0x13ffffff FlexNVM */
+# define KINETIS_FLEXRAM_BASE 0x14000000 /* –0x17ffffff FlexRAM */
+#endif
+ /* 0x18000000 * –0x1bffffff Reserved */
+#define KINETIS_SRAML_BASE 0x1c000000 /* –0x1fffffff SRAM_L: Lower SRAM
+ * (ICODE/DCODE) */
+#define KINETIS_SRAMU_BASE 0x20000000 /* –0x200fffff SRAM_U: Upper SRAM bitband
+ * region */
+ /* 0x20100000 * –0x21ffffff Reserved */
+#define KINETIS_SALIAS_BASE 0x22000000 /* –0x23ffffff Aliased to SRAM_U bitband */
+ /* 0x24000000 * –0x3fffffff Reserved */
+#define KINETIS_BRIDGE0_BASE 0x40000000 /* –0x4007ffff Bitband region for peripheral
+ * bridge 0 (AIPS-Lite0) */
+#define KINETIS_BRIDGE1_BASE 0x40080000 /* –0x400fffff Bitband region for peripheral
+ * bridge 1 (AIPS-Lite1) */
+#define KINETIS_GPIOBB_BASE 0x400ff000 /* –0x400fffff Bitband region for general
+ * purpose input/output (GPIO) */
+ /* 0x40100000 * –0x41ffffff Reserved */
+#define KINETIS_PALIAS_BASE 0x42000000 /* –0x43ffffff Aliased to peripheral bridge
+ * (AIPS-Lite) and general purpose
+ * input/output (GPIO) bitband */
+ /* 0x44000000 * –0xdfffffff Reserved */
+#define KINETIS_PERIPH_BASE 0xe0000000 /* –0xe00fffff Private peripherals */
+ /* 0xe0100000 * –0xffffffff Reserved */
+
+/* Peripheral Bridge 0 Memory Map ***************************************************/
+
+#define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
+#define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
+#define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
+#define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
+#define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
+#define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */
+#define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */
+#define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
+#define KINETIS_SPI0_BASE 0x4002c000 /* SPI 0 */
+#define KINETIS_SPI1_BASE 0x4002d000 /* SPI 1 */
+#define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
+#define KINETIS_CRC_BASE 0x40032000 /* CRC */
+#define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
+#define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
+#define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
+#define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer 0 */
+#define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer 1 */
+#define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
+#define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
+#define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
+#define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
+#define KINETIS_SYSR_BASE 0x40041000 /* System register file */
+#define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
+#define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
+#define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
+#define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
+#define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
+#define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
+#define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
+#define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
+#define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
+#define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
+#define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
+#define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
+#define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
+#define KINETIS_OSC_BASE 0x40065000 /* System oscillator (OSC) */
+#define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
+#define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
+#define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
+#define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
+#define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
+#define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
+#define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
+#define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
+#define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
+#define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
+#define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
+
+/* Peripheral Bridge 1 Memory Map ***************************************************/
+
+#define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
+#define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */
+#define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
+#define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
+
+#define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
+ * purpose input/output module that shares the
+ * crossbar switch slave port with the AIPS-Lite
+ * is accessed at this address. */
+#define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
+#define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
+#define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
+#define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
+#define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
+#define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
+
+/* Private Peripheral Bus (PPB) Memory Map ******************************************/
+
+#define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
+#define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
+#define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
+#define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
+#define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
+#define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
+#define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* KINETIS_K20 */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20MEMORYMAP_H */
diff --git a/arch/arm/src/kinetis/kinetis_k20pinmux.h b/arch/arm/src/kinetis/chip/kinetis_k20pinmux.h
similarity index 98%
rename from arch/arm/src/kinetis/kinetis_k20pinmux.h
rename to arch/arm/src/kinetis/chip/kinetis_k20pinmux.h
index a4ca3eda29b7dfd8ee96ff4d4be9b89133adf717..ca708acfdf8aa4b6c6252384a16c0c31dfd6ac05 100644
--- a/arch/arm/src/kinetis/kinetis_k20pinmux.h
+++ b/arch/arm/src/kinetis/chip/kinetis_k20pinmux.h
@@ -1,7 +1,7 @@
/********************************************************************************************
- * arch/arm/src/kinetis/kinetis_k40pinmux.h
+ * arch/arm/src/kinetis/chip/kinetis_k20pinmux.h
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
********************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_K20PINMUX_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_K20PINMUX_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20PINMUX_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20PINMUX_H
/********************************************************************************************
* Included Files
@@ -349,4 +349,4 @@
* Public Functions
********************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_K20PINMUX_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20PINMUX_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k40memorymap.h b/arch/arm/src/kinetis/chip/kinetis_k40memorymap.h
new file mode 100644
index 0000000000000000000000000000000000000000..65f2788ab6c3ba84c069173531f5db7cd5387ccd
--- /dev/null
+++ b/arch/arm/src/kinetis/chip/kinetis_k40memorymap.h
@@ -0,0 +1,199 @@
+/************************************************************************************
+ * arch/arm/src/kinetis/chip/kinetis_k40memorymap.h
+ *
+ * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40MEMORYMAP_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+#ifdef KINETIS_K40
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Memory Map ***********************************************************************/
+/* K40 Family
+ *
+ * The memory map for the following parts is defined in Freescale document
+ * K40P144M100SF2RM
+ */
+
+#define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read-
+ * only data (Includes exception
+ * vectors in first 1024 bytes) */
+# if !defined(KINETIS_FLEXMEM_SIZE)
+# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */
+# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */
+# endif
+#define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM
+ * (ICODE/DCODE) */
+#define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
+ * region */
+ /* 0x20100000 * -0x21ffffff Reserved */
+#define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
+ /* 0x24000000 * -0x3fffffff Reserved */
+#define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral
+ * bridge 0 (AIPS-Lite0) */
+#define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral
+ * bridge 1 (AIPS-Lite1) */
+#define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
+ * purpose input/output (GPIO) */
+ /* 0x40100000 * -0x41ffffff Reserved */
+#define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
+ * (AIPS-Lite) and general purpose
+ * input/output (GPIO) bitband */
+ /* 0x44000000 * -0x5fffffff Reserved */
+#define KINETIS_FLEXBUS_WBBASE 0x60000000 /* -0x7fffffff FlexBus (External Memory -
+ * Write-back) */
+#define KINETIS_FLEXBUS_WTBASE 0x80000000 /* -0x9fffffff FlexBus (External Memory -
+ * Write-through) */
+#define KINETIS_FLEXBUS_NXBASE 0xa0000000 /* -0xdfffffff FlexBus (External Memory -
+ * Non-executable) */
+#define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
+ /* 0xe0100000 * -0xffffffff Reserved */
+
+/* Peripheral Bridge 0 Memory Map ***************************************************/
+
+#define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
+#define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
+#define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
+#define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
+#define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
+#define KINETIS_MPU_BASE 0x4000d000 /* MPU */
+#define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
+#define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */
+#define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */
+#define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
+#define KINETIS_SPI0_BASE 0x4002c000 /* SPI 0 */
+#define KINETIS_SPI1_BASE 0x4002d000 /* SPI 1 */
+#define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
+#define KINETIS_CRC_BASE 0x40032000 /* CRC */
+#define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
+#define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
+#define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
+#define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer 0 */
+#define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer 1 */
+#define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
+#define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
+#define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
+#define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
+#define KINETIS_SYSR_BASE 0x40041000 /* System register file */
+#define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
+#define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */
+#define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
+#define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
+#define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
+#define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
+#define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
+#define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
+#define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
+#define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
+#define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
+#define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
+#define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
+#define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
+#define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
+#define KINETIS_OSC_BASE 0x40065000 /* System oscillator (OSC) */
+#define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
+#define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
+#define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
+#define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
+#define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
+#define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
+#define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
+#define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
+#define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
+#define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
+#define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
+#define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
+
+/* Peripheral Bridge 1 Memory Map ***************************************************/
+
+#define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
+#define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
+#define KINETIS_SPI2_BASE 0x400ac000 /* SPI 2 */
+#define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */
+#define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */
+#define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
+#define KINETIS_SLCD_BASE 0x400be000 /* Segment LCD */
+#define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
+#define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
+#define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
+#define KINETIS_UART5_BASE 0x400eb000 /* UART5 */
+#define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
+ * purpose input/output module that shares the
+ * crossbar switch slave port with the AIPS-Lite
+ * is accessed at this address. */
+#define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
+#define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
+#define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
+#define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
+#define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
+#define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
+
+/* Private Peripheral Bus (PPB) Memory Map ******************************************/
+
+#define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
+#define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
+#define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
+#define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
+#define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
+#define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
+#define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
+#define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
+#define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
+#define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* KINETIS_K40 */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40MEMORYMAP_H */
diff --git a/arch/arm/src/kinetis/kinetis_k40pinmux.h b/arch/arm/src/kinetis/chip/kinetis_k40pinmux.h
similarity index 99%
rename from arch/arm/src/kinetis/kinetis_k40pinmux.h
rename to arch/arm/src/kinetis/chip/kinetis_k40pinmux.h
index 9798eda6be1522e19bf0b7fc2bc1d176a61a0fed..7083b0caf7c5dccde1573fcc508ffd8e47ef9a17 100644
--- a/arch/arm/src/kinetis/kinetis_k40pinmux.h
+++ b/arch/arm/src/kinetis/chip/kinetis_k40pinmux.h
@@ -1,7 +1,7 @@
/********************************************************************************************
- * arch/arm/src/kinetis/kinetis_k40pinmux.h
+ * arch/arm/src/kinetis/chip/kinetis_k40pinmux.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
********************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_K40PINMUX_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_K40PINMUX_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40PINMUX_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40PINMUX_H
/********************************************************************************************
* Included Files
@@ -515,4 +515,4 @@
* Public Functions
********************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_K40PINMUX_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40PINMUX_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k60memorymap.h b/arch/arm/src/kinetis/chip/kinetis_k60memorymap.h
new file mode 100644
index 0000000000000000000000000000000000000000..135da4755366ed9870f4c2bad2771f6fe9d0d5ec
--- /dev/null
+++ b/arch/arm/src/kinetis/chip/kinetis_k60memorymap.h
@@ -0,0 +1,196 @@
+/************************************************************************************
+ * arch/arm/src/kinetis/chip/kinetis_k60memorymap.h
+ *
+ * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60MEMORYMAP_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+#ifdef KINETIS_K60
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Memory Map ***********************************************************************/
+/* K60 Family
+ *
+ * The memory map for the following parts is defined in Freescale document
+ * K60P144M100SF2RM
+ */
+
+#define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read-
+ * only data (Includes exception
+ * vectors in first 1024 bytes) */
+#if !defined(KINETIS_FLEXMEM_SIZE)
+# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */
+# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */
+#endif
+#define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM
+ * (ICODE/DCODE) */
+#define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
+ * region */
+ /* 0x20100000 * -0x21ffffff Reserved */
+#define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
+ /* 0x24000000 * -0x3fffffff Reserved */
+#define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral
+ * bridge 0 (AIPS-Lite0) */
+#define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral
+ * bridge 1 (AIPS-Lite1) */
+#define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
+ * purpose input/output (GPIO) */
+ /* 0x40100000 * -0x41ffffff Reserved */
+#define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
+ * (AIPS-Lite) and general purpose
+ * input/output (GPIO) bitband */
+ /* 0x44000000 * -0x5fffffff Reserved */
+#define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus */
+#define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
+ /* 0xe0100000 * -0xffffffff Reserved */
+
+/* Peripheral Bridge 0 Memory Map ***************************************************/
+
+#define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
+#define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
+#define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
+#define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
+#define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
+#define KINETIS_MPU_BASE 0x4000d000 /* MPU */
+#define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
+#define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */
+#define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */
+#define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
+#define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */
+#define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */
+#define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
+#define KINETIS_CRC_BASE 0x40032000 /* CRC */
+#define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
+#define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
+#define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
+#define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */
+#define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */
+#define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
+#define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
+#define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
+#define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
+#define KINETIS_SYSR_BASE 0x40041000 /* System register file */
+#define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
+#define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */
+#define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
+#define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
+#define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
+#define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
+#define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
+#define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
+#define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
+#define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
+#define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
+#define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
+#define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
+#define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
+#define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
+#define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */
+#define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
+#define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
+#define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
+#define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
+#define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
+#define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
+#define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
+#define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
+#define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
+#define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
+#define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
+#define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
+
+/* Peripheral Bridge 1 Memory Map ***************************************************/
+
+#define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
+#define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */
+#define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
+#define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */
+#define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */
+#define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */
+#define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
+#define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */
+#define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
+#define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
+#define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
+#define KINETIS_UART5_BASE 0x400eb000 /* UART5 */
+#define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
+ * purpose input/output module that shares the
+ * crossbar switch slave port with the AIPS-Lite
+ * is accessed at this address. */
+#define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
+#define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
+#define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
+#define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
+#define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
+#define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
+
+/* Private Peripheral Bus (PPB) Memory Map ******************************************/
+
+#define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
+#define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
+#define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
+#define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
+#define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
+#define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
+#define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
+#define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
+#define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
+#define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */
+#define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* KINETIS_K60 */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60MEMORYMAP_H */
diff --git a/arch/arm/src/kinetis/kinetis_k60pinmux.h b/arch/arm/src/kinetis/chip/kinetis_k60pinmux.h
similarity index 98%
rename from arch/arm/src/kinetis/kinetis_k60pinmux.h
rename to arch/arm/src/kinetis/chip/kinetis_k60pinmux.h
index 7fd69a0813e7f3c3bad938e38e69b5a77deb1719..4e7619c18fb38e9fabe5d9239b3469c96d623a9d 100644
--- a/arch/arm/src/kinetis/kinetis_k60pinmux.h
+++ b/arch/arm/src/kinetis/chip/kinetis_k60pinmux.h
@@ -1,7 +1,7 @@
/********************************************************************************************
- * arch/arm/src/kinetis/kinetis_k60pinset.h
+ * arch/arm/src/kinetis/chip/kinetis_k60pinset.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
********************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_K60PINMUX_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_K60PINMUX_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60PINMUX_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60PINMUX_H
/********************************************************************************************
* Included Files
@@ -83,12 +83,12 @@
#define PIN_FTM0_CH1_1 (PIN_ALT3 | PIN_PORTA | PIN4)
#define PIN_NMI (PIN_ALT7 | PIN_PORTA | PIN4)
#define PIN_FTM0_CH2_1 (PIN_ALT3 | PIN_PORTA | PIN5)
-#if 0
+#ifdef CONFIG_KINETIS_ENET_NORXER
+# define PIN_RMII0_RXER (GPIO_PULLDOWN | PIN_PORTA | PIN5)
+# define PIN_MII0_RXER (GPIO_PULLDOWN | PIN_PORTA | PIN5)
+#else
# define PIN_RMII0_RXER (PIN_ALT4 | PIN_PORTA | PIN5)
# define PIN_MII0_RXER (PIN_ALT4 | PIN_PORTA | PIN5)
-#else
-# define PIN_RMII0_RXER (GPIO_PULLDOWN | PIN_PORTA | PIN5)
-# define PIN_MII0_RXER (GPIO_PULLDOWN | PIN_PORTA | PIN5)
#endif
#define PIN_CMP2_OUT_1 (PIN_ALT5 | PIN_PORTA | PIN5)
#define PIN_I2S0_RX_BCLK_1 (PIN_ALT6 | PIN_PORTA | PIN5)
@@ -174,7 +174,11 @@
#define PIN_TSI0_CH0 (PIN_ANALOG | PIN_PORTB | PIN0)
#define PIN_I2C0_SCL_1 (PIN_ALT2 | PIN_PORTB | PIN0)
#define PIN_FTM1_CH0_3 (PIN_ALT3 | PIN_PORTB | PIN0)
-#define PIN_RMII0_MDIO (PIN_ALT4 | PIN_PORTB | PIN0)
+#ifdef CONFIG_KINETIS_ENET_MDIOPULLUP
+# define PIN_RMII0_MDIO (PIN_ALT4_PULLUP | PIN_PORTB | PIN0)
+#else
+# define PIN_RMII0_MDIO (PIN_ALT4 | PIN_PORTB | PIN0)
+#endif
#define PIN_MII0_MDIO (PIN_ALT4 | PIN_PORTB | PIN0)
#define PIN_FTM1_QD_PHA_3 (PIN_ALT6 | PIN_PORTB | PIN0)
#define PIN_ADC0_SE9 (PIN_ANALOG | PIN_PORTB | PIN1)
@@ -479,4 +483,4 @@
* Public Functions
********************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_K60PINMUX_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60PINMUX_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k64fmc.h b/arch/arm/src/kinetis/chip/kinetis_k64fmc.h
new file mode 100644
index 0000000000000000000000000000000000000000..036e38f1299075c3268146a460b03119bfd098dc
--- /dev/null
+++ b/arch/arm/src/kinetis/chip/kinetis_k64fmc.h
@@ -0,0 +1,293 @@
+/************************************************************************************
+ * arch/arm/src/kinetis/kinetis_k64fmc.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64FMC_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64FMC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define KINETIS_FMC_PFAPR_OFFSET 0x0000 /* Flash Access Protection Register */
+#define KINETIS_FMC_PFB0CR_OFFSET 0x0004 /* Flash Bank 0 Control Register */
+#define KINETIS_FMC_PFB1CR_OFFSET 0x0008 /* Flash Bank 1 Control Register */
+
+/* Cache Directory Storage for way=w and set=s, w=0..3, s=0..7 */
+
+#define KINETIS_FMC_TAGVD_OFFSET(w,s) (0x100 + ((w) << 5) + ((s) << 2))
+
+#define KINETIS_FMC_TAGVDW0S0_OFFSET 0x0100 /* Cache Directory Storage */
+#define KINETIS_FMC_TAGVDW0S1_OFFSET 0x0104 /* Cache Directory Storage */
+#define KINETIS_FMC_TAGVDW0S2_OFFSET 0x0108 /* Cache Directory Storage */
+#define KINETIS_FMC_TAGVDW0S3_OFFSET 0x010c /* Cache Directory Storage */
+
+#define KINETIS_FMC_TAGVDW1S0_OFFSET 0x0110 /* Cache Directory Storage */
+#define KINETIS_FMC_TAGVDW1S1_OFFSET 0x0114 /* Cache Directory Storage */
+#define KINETIS_FMC_TAGVDW1S2_OFFSET 0x0118 /* Cache Directory Storage */
+#define KINETIS_FMC_TAGVDW1S3_OFFSET 0x011c /* Cache Directory Storage */
+
+#define KINETIS_FMC_TAGVDW2S0_OFFSET 0x0120 /* Cache Directory Storage */
+#define KINETIS_FMC_TAGVDW2S1_OFFSET 0x0124 /* Cache Directory Storage */
+#define KINETIS_FMC_TAGVDW2S2_OFFSET 0x0128 /* Cache Directory Storage */
+#define KINETIS_FMC_TAGVDW2S3_OFFSET 0x012c /* Cache Directory Storage */
+
+#define KINETIS_FMC_TAGVDW3S0_OFFSET 0x0130 /* Cache Directory Storage */
+#define KINETIS_FMC_TAGVDW3S1_OFFSET 0x0134 /* Cache Directory Storage */
+#define KINETIS_FMC_TAGVDW3S2_OFFSET 0x0138 /* Cache Directory Storage */
+#define KINETIS_FMC_TAGVDW3S3_OFFSET 0x013c /* Cache Directory Storage */
+
+/* Cache Data Storage (upper and lower) for way=w and set=s, w=0..3, s=0..7 */
+
+#define KINETIS_FMC_DATAU_OFFSET(w,s) (0x200 + ((w) << 6) + ((s) << 2))
+#define KINETIS_FMC_DATAL_OFFSET(w,s) (0x204 + ((w) << 6) + ((s) << 2))
+
+#define KINETIS_FMC_DATAW0S0U_OFFSET 0x0200 /* Cache Data Storage (upper word) */
+#define KINETIS_FMC_DATAW0S0L_OFFSET 0x0204 /* Cache Data Storage (lower word) */
+#define KINETIS_FMC_DATAW0S1U_OFFSET 0x0208 /* Cache Data Storage (upper word) */
+#define KINETIS_FMC_DATAW0S1L_OFFSET 0x020c /* Cache Data Storage (lower word) */
+#define KINETIS_FMC_DATAW0S2U_OFFSET 0x0210 /* Cache Data Storage (upper word) */
+#define KINETIS_FMC_DATAW0S2L_OFFSET 0x0214 /* Cache Data Storage (lower word) */
+#define KINETIS_FMC_DATAW0S3U_OFFSET 0x0218 /* Cache Data Storage (upper word) */
+#define KINETIS_FMC_DATAW0S3L_OFFSET 0x021c /* Cache Data Storage (lower word) */
+
+#define KINETIS_FMC_DATAW1S0U_OFFSET 0x0220 /* Cache Data Storage (upper word) */
+#define KINETIS_FMC_DATAW1S0L_OFFSET 0x0224 /* Cache Data Storage (lower word) */
+#define KINETIS_FMC_DATAW1S1U_OFFSET 0x0228 /* Cache Data Storage (upper word) */
+#define KINETIS_FMC_DATAW1S1L_OFFSET 0x022c /* Cache Data Storage (lower word) */
+#define KINETIS_FMC_DATAW1S2U_OFFSET 0x0230 /* Cache Data Storage (upper word) */
+#define KINETIS_FMC_DATAW1S2L_OFFSET 0x0234 /* Cache Data Storage (lower word) */
+#define KINETIS_FMC_DATAW1S3U_OFFSET 0x0238 /* Cache Data Storage (upper word) */
+#define KINETIS_FMC_DATAW1S3L_OFFSET 0x023c /* Cache Data Storage (lower word) */
+
+#define KINETIS_FMC_DATAW2S0U_OFFSET 0x0240 /* Cache Data Storage (upper word) */
+#define KINETIS_FMC_DATAW2S0L_OFFSET 0x0244 /* Cache Data Storage (lower word) */
+#define KINETIS_FMC_DATAW2S1U_OFFSET 0x0248 /* Cache Data Storage (upper word) */
+#define KINETIS_FMC_DATAW2S1L_OFFSET 0x024c /* Cache Data Storage (lower word) */
+#define KINETIS_FMC_DATAW2S2U_OFFSET 0x0250 /* Cache Data Storage (upper word) */
+#define KINETIS_FMC_DATAW2S2L_OFFSET 0x0254 /* Cache Data Storage (lower word) */
+#define KINETIS_FMC_DATAW2S3U_OFFSET 0x0258 /* Cache Data Storage (upper word) */
+#define KINETIS_FMC_DATAW2S3L_OFFSET 0x025c /* Cache Data Storage (lower word) */
+
+#define KINETIS_FMC_DATAW3S0U_OFFSET 0x0260 /* Cache Data Storage (upper word) */
+#define KINETIS_FMC_DATAW3S0L_OFFSET 0x0264 /* Cache Data Storage (lower word) */
+#define KINETIS_FMC_DATAW3S1U_OFFSET 0x0268 /* Cache Data Storage (upper word) */
+#define KINETIS_FMC_DATAW3S1L_OFFSET 0x026c /* Cache Data Storage (lower word) */
+#define KINETIS_FMC_DATAW3S2U_OFFSET 0x0270 /* Cache Data Storage (upper word) */
+#define KINETIS_FMC_DATAW3S2L_OFFSET 0x0274 /* Cache Data Storage (lower word) */
+#define KINETIS_FMC_DATAW3S3U_OFFSET 0x0278 /* Cache Data Storage (upper word) */
+#define KINETIS_FMC_DATAW3S3L_OFFSET 0x027c /* Cache Data Storage (lower word) */
+
+/* Register Addresses ***************************************************************/
+
+#define KINETIS_FMC_PFAPR (KINETIS_FMC_BASE+KINETIS_FMC_PFAPR_OFFSET)
+#define KINETIS_FMC_PFB0CR (KINETIS_FMC_BASE+KINETIS_FMC_PFB0CR_OFFSET)
+#define KINETIS_FMC_PFB1CR (KINETIS_FMC_BASE+KINETIS_FMC_PFB1CR_OFFSET)
+
+/* Cache Directory Storage for way=w and set=s, w=0..3, s=0..7 */
+
+#define KINETIS_FMC_TAGVD(w,s) (KINETIS_FMC_BASE+KINETIS_FMC_TAGVD_OFFSET(w,s))
+
+#define KINETIS_FMC_TAGVDW0S0 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW0S0_OFFSET)
+#define KINETIS_FMC_TAGVDW0S1 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW0S1_OFFSET)
+#define KINETIS_FMC_TAGVDW0S2 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW0S2_OFFSET)
+#define KINETIS_FMC_TAGVDW0S3 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW0S3_OFFSET)
+
+#define KINETIS_FMC_TAGVDW1S0 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW1S0_OFFSET)
+#define KINETIS_FMC_TAGVDW1S1 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW1S1_OFFSET)
+#define KINETIS_FMC_TAGVDW1S2 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW1S2_OFFSET)
+#define KINETIS_FMC_TAGVDW1S3 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW1S3_OFFSET)
+
+#define KINETIS_FMC_TAGVDW2S0 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW2S0_OFFSET)
+#define KINETIS_FMC_TAGVDW2S1 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW2S1_OFFSET)
+#define KINETIS_FMC_TAGVDW2S2 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW2S2_OFFSET)
+#define KINETIS_FMC_TAGVDW2S3 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW2S3_OFFSET)
+
+#define KINETIS_FMC_TAGVDW3S0 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW3S0_OFFSET)
+#define KINETIS_FMC_TAGVDW3S1 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW3S1_OFFSET)
+#define KINETIS_FMC_TAGVDW3S2 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW3S2_OFFSET)
+#define KINETIS_FMC_TAGVDW3S3 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW3S3_OFFSET)
+
+/* Cache Data Storage (upper and lower) for way=w and set=s, w=0..3, s=0..7 */
+
+#define KINETIS_FMC_DATAU(w,s) (KINETIS_FMC_BASE+KINETIS_FMC_DATAU_OFFSET(w,s))
+#define KINETIS_FMC_DATAL(w,s) (KINETIS_FMC_BASE+KINETIS_FMC_DATAL_OFFSET(w,s))
+
+#define KINETIS_FMC_DATAW0S0U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW0S0U_OFFSET)
+#define KINETIS_FMC_DATAW0S0L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW0S0L_OFFSET)
+#define KINETIS_FMC_DATAW0S1U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW0S1U_OFFSET)
+#define KINETIS_FMC_DATAW0S1L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW0S1L_OFFSET)
+#define KINETIS_FMC_DATAW0S2U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW0S2U_OFFSET)
+#define KINETIS_FMC_DATAW0S2L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW0S2L_OFFSET)
+#define KINETIS_FMC_DATAW0S3U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW0S3U_OFFSET)
+#define KINETIS_FMC_DATAW0S3L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW0S3L_OFFSET)
+
+#define KINETIS_FMC_DATAW1S0U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW1S0U_OFFSET)
+#define KINETIS_FMC_DATAW1S0L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW1S0L_OFFSET)
+#define KINETIS_FMC_DATAW1S1U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW1S1U_OFFSET)
+#define KINETIS_FMC_DATAW1S1L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW1S1L_OFFSET)
+#define KINETIS_FMC_DATAW1S2U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW1S2U_OFFSET)
+#define KINETIS_FMC_DATAW1S2L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW1S2L_OFFSET)
+#define KINETIS_FMC_DATAW1S3U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW1S3U_OFFSET)
+#define KINETIS_FMC_DATAW1S3L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW1S3L_OFFSET)
+
+#define KINETIS_FMC_DATAW2S0U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW2S0U_OFFSET)
+#define KINETIS_FMC_DATAW2S0L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW2S0L_OFFSET)
+#define KINETIS_FMC_DATAW2S1U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW2S1U_OFFSET)
+#define KINETIS_FMC_DATAW2S1L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW2S1L_OFFSET)
+#define KINETIS_FMC_DATAW2S2U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW2S2U_OFFSET)
+#define KINETIS_FMC_DATAW2S2L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW2S2L_OFFSET)
+#define KINETIS_FMC_DATAW2S3U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW2S3U_OFFSET)
+#define KINETIS_FMC_DATAW2S3L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW2S3L_OFFSET)
+
+#define KINETIS_FMC_DATAW3S0U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S0U_OFFSET)
+#define KINETIS_FMC_DATAW3S0L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S0L_OFFSET)
+#define KINETIS_FMC_DATAW3S1U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S1U_OFFSET)
+#define KINETIS_FMC_DATAW3S1L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S1L_OFFSET)
+#define KINETIS_FMC_DATAW3S2U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S2U_OFFSET)
+#define KINETIS_FMC_DATAW3S2L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S2L_OFFSET)
+#define KINETIS_FMC_DATAW3S3U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S3U_OFFSET)
+#define KINETIS_FMC_DATAW3S3L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S3L_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* Flash Access Protection Register */
+/* Access protection bits (all masters) */
+
+#define FMC_PFAPR_NONE 0 /* No access may be performed by this master */
+#define FMC_PFAPR_RDONLY 1 /* Only read accesses may be performed by this master */
+#define FMC_PFAPR_WRONLY 2 /* Only write accesses may be performed by this master */
+#define FMC_PFAPR_RDWR 3 /* Both read and write accesses may be performed by this master */
+
+#define FMC_PFAPR_M0AP_SHIFT (0) /* Bits 0-1: Master 0 Access Protection */
+#define FMC_PFAPR_M0AP_MASK (3 << FMC_PFAPR_M0AP_SHIFT)
+#define FMC_PFAPR_M1AP_SHIFT (2) /* Bits 2-3: Master 1 Access Protection */
+#define FMC_PFAPR_M1AP_MASK (3 << FMC_PFAPR_M1AP_SHIFT)
+#define FMC_PFAPR_M2AP_SHIFT (4) /* Bits 4-5: Master 2 Access Protection */
+#define FMC_PFAPR_M2AP_MASK (3 << FMC_PFAPR_M2AP_SHIFT)
+#define FMC_PFAPR_M3AP_SHIFT (6) /* Bits 6-7: Master 3 Access Protection */
+#define FMC_PFAPR_M3AP_MASK (3 << FMC_PFAPR_M3AP_SHIFT)
+#define FMC_PFAPR_M4AP_SHIFT (8) /* Bits 8-9: Master 4 Access Protection */
+#define FMC_PFAPR_M4AP_MASK (3 << FMC_PFAPR_M4AP_SHIFT)
+#define FMC_PFAPR_M5AP_SHIFT (10) /* Bits 10-11: Master 5 Access Protection */
+#define FMC_PFAPR_M5AP_MASK (3 << FMC_PFAPR_M5AP_SHIFT)
+#define FMC_PFAPR_M6AP_SHIFT (12) /* Bits 12-13: Master 6 Access Protection */
+#define FMC_PFAPR_M6AP_MASK (3 << FMC_PFAPR_M6AP_SHIFT)
+#define FMC_PFAPR_M7AP_SHIFT (14) /* Bits 14-15: Master 7 Access Protection */
+#define FMC_PFAPR_M7AP_MASK (3 << FMC_PFAPR_M7AP_SHIFT)
+#define FMC_PFAPR_M0PFD (1 << 16) /* Bit 16: Master 0 Prefetch Disable */
+#define FMC_PFAPR_M1PFD (1 << 17) /* Bit 17: Master 1 Prefetch Disable */
+#define FMC_PFAPR_M2PFD (1 << 18) /* Bit 18: Master 2 Prefetch Disable */
+#define FMC_PFAPR_M3PFD (1 << 19) /* Bit 19: Master 3 Prefetch Disable */
+#define FMC_PFAPR_M4PFD (1 << 20) /* Bit 20: Master 4 Prefetch Disable */
+#define FMC_PFAPR_M5PFD (1 << 21) /* Bit 21: Master 5 Prefetch Disable */
+#define FMC_PFAPR_M6PFD (1 << 22) /* Bit 22: Master 6 Prefetch Disable */
+#define FMC_PFAPR_M7PFD (1 << 23) /* Bit 23: Master 7 Prefetch Disable */
+ /* Bits 24-31: Reserved */
+/* Flash Bank 0 Control Register */
+
+#define FMC_PFB0CR_B0SEBE (1 << 0) /* Bit 0: Bank 0 Single Entry Buffer Enable */
+#define FMC_PFB0CR_B0IPE (1 << 1) /* Bit 1: Bank 0 Instruction Prefetch Enable */
+#define FMC_PFB0CR_B0DPE (1 << 2) /* Bit 2: Bank 0 Data Prefetch Enable */
+#define FMC_PFB0CR_B0ICE (1 << 3) /* Bit 3: Bank 0 Instruction Cache Enable */
+#define FMC_PFB0CR_B0DCE (1 << 4) /* Bit 4: Bank 0 Data Cache Enable */
+#define FMC_PFB0CR_CRC_SHIFT (5) /* Bits 5-7: Cache Replacement Control */
+#define FMC_PFB0CR_CRC_MASK (7 << FMC_PFB0CR_CRC_SHIFT)
+# define FMC_PFB0CR_CRC_ALL (0 << FMC_PFB0CR_CRC_SHIFT) /* LRU all four ways */
+# define FMC_PFB0CR_CRC_I01D23 (2 << FMC_PFB0CR_CRC_SHIFT) /* LRU ifetches 0-1 data 2-3 */
+# define FMC_PFB0CR_CRC_I012D3 (3 << FMC_PFB0CR_CRC_SHIFT) /* LRU ifetches 0-3 data 3 */
+ /* Bits 8-16: Reserved */
+#define FMC_PFB0CR_B0MW_SHIFT (17) /* Bits 17-18: Bank 0 Memory Width */
+#define FMC_PFB0CR_B0MW_MASK (3 << FMC_PFB0CR_B0MW_SHIFT)
+# define FMC_PFB0CR_B0MW_32BITS (0 << FMC_PFB0CR_B0MW_SHIFT) /* 32 bits */
+# define FMC_PFB0CR_B0MW_64BITS (1 << FMC_PFB0CR_B0MW_SHIFT) /* 64 bits */
+#define FMC_PFB0CR_S_B_INV (1 << 19) /* Bit 19: Invalidate Prefetch Speculation Buffer */
+#define FMC_PFB0CR_CINV_WAY_SHIFT (20) /* Bits 20-23: Cache Invalidate Way x */
+#define FMC_PFB0CR_CINV_WAY_MASK (15 << FMC_PFB0CR_CINV_WAY_SHIFT)
+#define FMC_PFB0CR_CLCK_WAY_SHIFT (24) /* Bits 24-27: Cache Lock Way x */
+#define FMC_PFB0CR_CLCK_WAY_MASK (15 << FMC_PFB0CR_CLCK_WAY_SHIFT)
+#define FMC_PFB0CR_B0RWSC_SHIFT (28) /* Bits 28-31: Bank 0 Read Wait State Control */
+#define FMC_PFB0CR_B0RWSC_MASK (15 << FMC_PFB0CR_B0RWSC_SHIFT)
+
+/* Flash Bank 1 Control Register */
+
+#define FMC_PFB1CR_B1SEBE (1 << 0) /* Bit 0: Bank 1 Single Entry Buffer Enable */
+#define FMC_PFB1CR_B1IPE (1 << 1) /* Bit 1: Bank 1 Instruction Prefetch Enable */
+#define FMC_PFB1CR_B1DPE (1 << 2) /* Bit 2: Bank 1 Data Prefetch Enable */
+#define FMC_PFB1CR_B1ICE (1 << 3) /* Bit 3: Bank 1 Instruction Cache Enable */
+#define FMC_PFB1CR_B1DCE (1 << 4) /* Bit 4: Bank 1 Data Cache Enable */
+ /* Bits 5-16: Reserved */
+#define FMC_PFB1CR_B1MW_SHIFT (17) /* Bits 17-18: Bank 1 Memory Width */
+#define FMC_PFB1CR_B1MW_MASK (3 << FMC_PFB1CR_B1MW_SHIFT)
+# define FMC_PFB1CR_B1MW_32BITS (0 << FMC_PFB1CR_B1MW_SHIFT) /* 32 bits */
+# define FMC_PFB1CR_B1MW_64BITS (1 << FMC_PFB1CR_B1MW_SHIFT) /* 64 bits */
+ /* Bits 19-27: Reserved */
+#define FMC_PFB1CR_B1RWSC_SHIFT (28) /* Bits 28-31: Bank 1 Read Wait State Control */
+#define FMC_PFB1CR_B1RWSC_MASK (15 << FMC_PFB1CR_B0RWSC_SHIFT)
+
+/* Cache Directory Storage for way=w and set=s, w=0..3, s=0..7 */
+
+#define FMC_TAGVD_VALID (1 << 0) /* Bit 0: 1-bit valid for cache entry */
+ /* Bits 1-4: Reserved */
+#define FMC_TAGVD_TAG_SHIFT (5) /* Bits 5-18: 13-bit tag for cache entry */
+#define FMC_TAGVD_TAG_MASK (0x1fff << FMC_TAGVD_TAG_SHIFT)
+ /* Bits 19-31: Reserved */
+
+/* Cache Data Storage (upper and lower) for way=w and set=s, w=0..3, s=0..7.
+ * 64-bit data in two 32-bit registers.
+ */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64FMC_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k64memorymap.h b/arch/arm/src/kinetis/chip/kinetis_k64memorymap.h
new file mode 100644
index 0000000000000000000000000000000000000000..235343de89dca36385c028a03ea5223e80c9903b
--- /dev/null
+++ b/arch/arm/src/kinetis/chip/kinetis_k64memorymap.h
@@ -0,0 +1,213 @@
+/************************************************************************************
+ * arch/arm/src/kinetis/chip/kinetis_k64memorymap.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64MEMORYMAP_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+#ifdef KINETIS_K64
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Memory Map ***********************************************************************/
+/* K64 Family
+ *
+ * The memory map for the following parts is defined in NXP document
+ * K64P144M120SF5RM.pdf
+ */
+
+#if defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || \
+ defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \
+ defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || \
+ defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
+
+# define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read-
+ * only data (Includes exception
+ * vectors in first 1024 bytes) */
+# if !defined(KINETIS_FLEXMEM_SIZE)
+# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */
+# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */
+# endif
+# define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM
+ * (ICODE/DCODE) */
+# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
+ * region */
+ /* 0x20100000 * -0x21ffffff Reserved */
+# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
+ /* 0x24000000 * -0x3fffffff Reserved */
+# define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral
+ * bridge 0 (AIPS-Lite0) */
+# define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral
+ * bridge 1 (AIPS-Lite1) */
+# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
+ * purpose input/output (GPIO) */
+ /* 0x40100000 * -0x41ffffff Reserved */
+# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
+ * (AIPS-Lite) and general purpose
+ * input/output (GPIO) bitband */
+ /* 0x44000000 * -0x5fffffff Reserved */
+# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus */
+# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
+ /* 0xe0100000 * -0xffffffff Reserved */
+
+/* Peripheral Bridge 0 Memory Map ***************************************************/
+
+# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
+# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
+# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
+# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
+# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
+# define KINETIS_MPU_BASE 0x4000d000 /* MPU */
+# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
+# define KINETIS_FTFE_BASE 0x40020000 /* Flash memory */
+# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */
+# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
+# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */
+# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */
+# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
+# define KINETIS_CRC_BASE 0x40032000 /* CRC */
+# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
+# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
+# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
+# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */
+# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */
+# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
+# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
+# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
+# define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
+# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
+# define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
+# define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */
+# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
+# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
+# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
+# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
+# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
+# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
+# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
+# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
+# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
+# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
+# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
+# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
+# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
+# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */
+# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
+# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
+# define KINETIS_I2C2_BASE 0x400E6000 /* I2C 2 */
+# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
+# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
+# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
+# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
+# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
+# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
+# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
+# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
+# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
+# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
+
+/* Peripheral Bridge 1 Memory Map ***************************************************/
+
+# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
+# define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */
+# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
+# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */
+# define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */
+# define KINETIS_FTM2_BASE 0x4003a000 /* FlexTimer 2 */
+# define KINETIS_FTM3_BASE 0x400b9000 /* FlexTimer 3 */
+# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
+# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */
+# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
+# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
+# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
+# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */
+# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
+ * purpose input/output module that shares the
+ * crossbar switch slave port with the AIPS-Lite
+ * is accessed at this address. */
+# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
+# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
+# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
+# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
+# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
+# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
+
+/* Private Peripheral Bus (PPB) Memory Map ******************************************/
+
+# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
+# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
+# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
+# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
+# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
+# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
+# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
+# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
+# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
+# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */
+# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
+
+#else
+ /* The memory map for other parts is defined in other documents and may or may not
+ * be the same as above (the family members are all very similar) This error just
+ * means that you have to look at the document and determine for yourself if the
+ * memory map is the same.
+ */
+
+# error "No memory map for this K64 part"
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* KINETIS_K64 */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64MEMORYMAP_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k64mpu.h b/arch/arm/src/kinetis/chip/kinetis_k64mpu.h
new file mode 100644
index 0000000000000000000000000000000000000000..808ff15be220fd21526815e5ed769eff8f95e638
--- /dev/null
+++ b/arch/arm/src/kinetis/chip/kinetis_k64mpu.h
@@ -0,0 +1,358 @@
+/****************************************************************************************************
+ * arch/arm/src/kinetis/kinetis_mpu.h
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MPU_H
+#define __ARCH_ARM_SRC_KINETIS_KINETIS_MPU_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Register Offsets *********************************************************************************/
+
+#define KINETIS_MPU_CESR_OFFSET 0x0000 /* Control/Error Status Register */
+
+#define KINETIS_MPU_EAR_OFFSET(n) (0x0010+((n)<<3)) /* Error Address Register, Slave Port n */
+#define KINETIS_MPU_EDR_OFFSET(n) (0x0014+((n)<<3)) /* Error Detail Register, Slave Port n */
+
+#define KINETIS_MPU_EAR0_OFFSET 0x0010 /* Error Address Register, Slave Port 0 */
+#define KINETIS_MPU_EDR0_OFFSET 0x0014 /* Error Detail Register, Slave Port 0 */
+#define KINETIS_MPU_EAR1_OFFSET 0x0018 /* Error Address Register, Slave Port 1 */
+#define KINETIS_MPU_EDR1_OFFSET 0x001c /* Error Detail Register, Slave Port 1 */
+#define KINETIS_MPU_EAR2_OFFSET 0x0020 /* Error Address Register, Slave Port 2 */
+#define KINETIS_MPU_EDR2_OFFSET 0x0024 /* Error Detail Register, Slave Port 2 */
+#define KINETIS_MPU_EAR3_OFFSET 0x0028 /* Error Address Register, Slave Port 3 */
+#define KINETIS_MPU_EDR3_OFFSET 0x002c /* Error Detail Register, Slave Port 3 */
+#define KINETIS_MPU_EAR4_OFFSET 0x0030 /* Error Address Register, Slave Port 4 */
+#define KINETIS_MPU_EDR4_OFFSET 0x0034 /* Error Detail Register, Slave Port 4 */
+
+#define KINETIS_MPU_RGD_WORD_OFFSET(n,m) (x0400+((n)<<4)+((m)<< 2) /* Region Descriptor n, Word m */
+
+#define KINETIS_MPU_RGD0_WORD0_OFFSET 0x0400 /* Region Descriptor 0, Word 0 */
+#define KINETIS_MPU_RGD0_WORD1_OFFSET 0x0404 /* Region Descriptor 0, Word 1 */
+#define KINETIS_MPU_RGD0_WORD2_OFFSET 0x0408 /* Region Descriptor 0, Word 2 */
+#define KINETIS_MPU_RGD0_WORD3_OFFSET 0x040c /* Region Descriptor 0, Word 3 */
+#define KINETIS_MPU_RGD1_WORD0_OFFSET 0x0410 /* Region Descriptor 1, Word 0 */
+#define KINETIS_MPU_RGD1_WORD1_OFFSET 0x0414 /* Region Descriptor 1, Word 1 */
+#define KINETIS_MPU_RGD1_WORD2_OFFSET 0x0418 /* Region Descriptor 1, Word 2 */
+#define KINETIS_MPU_RGD1_WORD3_OFFSET 0x041c /* Region Descriptor 1, Word 3 */
+#define KINETIS_MPU_RGD2_WORD0_OFFSET 0x0420 /* Region Descriptor 2, Word 0 */
+#define KINETIS_MPU_RGD2_WORD1_OFFSET 0x0424 /* Region Descriptor 2, Word 1 */
+#define KINETIS_MPU_RGD2_WORD2_OFFSET 0x0428 /* Region Descriptor 2, Word 2 */
+#define KINETIS_MPU_RGD2_WORD3_OFFSET 0x042c /* Region Descriptor 2, Word 3 */
+#define KINETIS_MPU_RGD3_WORD0_OFFSET 0x0430 /* Region Descriptor 3, Word 0 */
+#define KINETIS_MPU_RGD3_WORD1_OFFSET 0x0434 /* Region Descriptor 3, Word 1 */
+#define KINETIS_MPU_RGD3_WORD2_OFFSET 0x0438 /* Region Descriptor 3, Word 2 */
+#define KINETIS_MPU_RGD3_WORD3_OFFSET 0x043c /* Region Descriptor 3, Word 3 */
+#define KINETIS_MPU_RGD4_WORD0_OFFSET 0x0440 /* Region Descriptor 4, Word 0 */
+#define KINETIS_MPU_RGD4_WORD1_OFFSET 0x0444 /* Region Descriptor 4, Word 1 */
+#define KINETIS_MPU_RGD4_WORD2_OFFSET 0x0448 /* Region Descriptor 4, Word 2 */
+#define KINETIS_MPU_RGD4_WORD3_OFFSET 0x044c /* Region Descriptor 4, Word 3 */
+#define KINETIS_MPU_RGD5_WORD0_OFFSET 0x0450 /* Region Descriptor 5, Word 0 */
+#define KINETIS_MPU_RGD5_WORD1_OFFSET 0x0454 /* Region Descriptor 5, Word 1 */
+#define KINETIS_MPU_RGD5_WORD2_OFFSET 0x0458 /* Region Descriptor 5, Word 2 */
+#define KINETIS_MPU_RGD5_WORD3_OFFSET 0x045c /* Region Descriptor 5, Word 3 */
+#define KINETIS_MPU_RGD6_WORD0_OFFSET 0x0460 /* Region Descriptor 6, Word 0 */
+#define KINETIS_MPU_RGD6_WORD1_OFFSET 0x0464 /* Region Descriptor 6, Word 1 */
+#define KINETIS_MPU_RGD6_WORD2_OFFSET 0x0468 /* Region Descriptor 6, Word 2 */
+#define KINETIS_MPU_RGD6_WORD3_OFFSET 0x046c /* Region Descriptor 6, Word 3 */
+#define KINETIS_MPU_RGD7_WORD0_OFFSET 0x0470 /* Region Descriptor 7, Word 0 */
+#define KINETIS_MPU_RGD7_WORD1_OFFSET 0x0474 /* Region Descriptor 7, Word 1 */
+#define KINETIS_MPU_RGD7_WORD2_OFFSET 0x0478 /* Region Descriptor 7, Word 2 */
+#define KINETIS_MPU_RGD7_WORD3_OFFSET 0x047c /* Region Descriptor 7, Word 3 */
+#define KINETIS_MPU_RGD8_WORD0_OFFSET 0x0480 /* Region Descriptor 8, Word 0 */
+#define KINETIS_MPU_RGD8_WORD1_OFFSET 0x0484 /* Region Descriptor 8, Word 1 */
+#define KINETIS_MPU_RGD8_WORD2_OFFSET 0x0488 /* Region Descriptor 8, Word 2 */
+#define KINETIS_MPU_RGD8_WORD3_OFFSET 0x048c /* Region Descriptor 8, Word 3 */
+#define KINETIS_MPU_RGD9_WORD0_OFFSET 0x0490 /* Region Descriptor 9, Word 0 */
+#define KINETIS_MPU_RGD9_WORD1_OFFSET 0x0494 /* Region Descriptor 9, Word 1 */
+#define KINETIS_MPU_RGD9_WORD2_OFFSET 0x0498 /* Region Descriptor 9, Word 2 */
+#define KINETIS_MPU_RGD9_WORD3_OFFSET 0x049c /* Region Descriptor 9, Word 3 */
+#define KINETIS_MPU_RGD10_WORD0_OFFSET 0x04a0 /* Region Descriptor 10, Word 0 */
+#define KINETIS_MPU_RGD10_WORD1_OFFSET 0x04a4 /* Region Descriptor 10, Word 1 */
+#define KINETIS_MPU_RGD10_WORD2_OFFSET 0x04a8 /* Region Descriptor 10, Word 2 */
+#define KINETIS_MPU_RGD10_WORD3_OFFSET 0x04ac /* Region Descriptor 10, Word 3 */
+#define KINETIS_MPU_RGD11_WORD0_OFFSET 0x04b0 /* Region Descriptor 11, Word 0 */
+#define KINETIS_MPU_RGD11_WORD1_OFFSET 0x04b4 /* Region Descriptor 11, Word 1 */
+#define KINETIS_MPU_RGD11_WORD2_OFFSET 0x04b8 /* Region Descriptor 11, Word 2 */
+#define KINETIS_MPU_RGD11_WORD3_OFFSET 0x04bc /* Region Descriptor 11, Word 3 */
+
+#define KINETIS_MPU_RGDAAC_OFFSET(n) (0x0800+((n)<<2)) /* Region Descriptor Alternate Access Control n */
+
+#define KINETIS_MPU_RGDAAC0_OFFSET 0x0800 /* Region Descriptor Alternate Access Control 0 */
+#define KINETIS_MPU_RGDAAC1_OFFSET 0x0804 /* Region Descriptor Alternate Access Control 1 */
+#define KINETIS_MPU_RGDAAC2_OFFSET 0x0808 /* Region Descriptor Alternate Access Control 2 */
+#define KINETIS_MPU_RGDAAC3_OFFSET 0x080c /* Region Descriptor Alternate Access Control 3 */
+#define KINETIS_MPU_RGDAAC4_OFFSET 0x0810 /* Region Descriptor Alternate Access Control 4 */
+#define KINETIS_MPU_RGDAAC5_OFFSET 0x0814 /* Region Descriptor Alternate Access Control 5 */
+#define KINETIS_MPU_RGDAAC6_OFFSET 0x0818 /* Region Descriptor Alternate Access Control 6 */
+#define KINETIS_MPU_RGDAAC7_OFFSET 0x081c /* Region Descriptor Alternate Access Control 7 */
+#define KINETIS_MPU_RGDAAC8_OFFSET 0x0820 /* Region Descriptor Alternate Access Control 8 */
+#define KINETIS_MPU_RGDAAC9_OFFSET 0x0824 /* Region Descriptor Alternate Access Control 9 */
+#define KINETIS_MPU_RGDAAC10_OFFSET 0x0828 /* Region Descriptor Alternate Access Control 10 */
+#define KINETIS_MPU_RGDAAC11_OFFSET 0x082c /* Region Descriptor Alternate Access Control 11 */
+
+/* Register Addresses *******************************************************************************/
+
+#define KINETIS_MPU_CESR (KINETIS_MPU_BASE+KINETIS_MPU_CESR_OFFSET)
+
+#define KINETIS_MPU_EAR(n) (KINETIS_MPU_BASE+KINETIS_MPU_EAR_OFFSET(n))
+#define KINETIS_MPU_EDR(n) (KINETIS_MPU_BASE+KINETIS_MPU_EDR_OFFSET(n))
+
+#define KINETIS_MPU_EAR0 (KINETIS_MPU_BASE+KINETIS_MPU_EAR0_OFFSET)
+#define KINETIS_MPU_EDR0 (KINETIS_MPU_BASE+KINETIS_MPU_EDR0_OFFSET)
+#define KINETIS_MPU_EAR1 (KINETIS_MPU_BASE+KINETIS_MPU_EAR1_OFFSET)
+#define KINETIS_MPU_EDR1 (KINETIS_MPU_BASE+KINETIS_MPU_EDR1_OFFSET)
+#define KINETIS_MPU_EAR2 (KINETIS_MPU_BASE+KINETIS_MPU_EAR2_OFFSET)
+#define KINETIS_MPU_EDR2 (KINETIS_MPU_BASE+KINETIS_MPU_EDR2_OFFSET)
+#define KINETIS_MPU_EAR3 (KINETIS_MPU_BASE+KINETIS_MPU_EAR3_OFFSET)
+#define KINETIS_MPU_EDR3 (KINETIS_MPU_BASE+KINETIS_MPU_EDR3_OFFSET)
+#define KINETIS_MPU_EAR4 (KINETIS_MPU_BASE+KINETIS_MPU_EAR4_OFFSET)
+#define KINETIS_MPU_EDR4 (KINETIS_MPU_BASE+KINETIS_MPU_EDR4_OFFSET)
+
+#define KINETIS_MPU_RGD_WORD(n,m) (KINETIS_MPU_BASE+KINETIS_MPU_RGD_WORD_OFFSET(n,m))
+
+#define KINETIS_MPU_RGD0_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD0_WORD0_OFFSET)
+#define KINETIS_MPU_RGD0_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD0_WORD1_OFFSET)
+#define KINETIS_MPU_RGD0_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD0_WORD2_OFFSET)
+#define KINETIS_MPU_RGD0_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD0_WORD3_OFFSET)
+#define KINETIS_MPU_RGD1_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD1_WORD0_OFFSET)
+#define KINETIS_MPU_RGD1_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD1_WORD1_OFFSET)
+#define KINETIS_MPU_RGD1_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD1_WORD2_OFFSET)
+#define KINETIS_MPU_RGD1_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD1_WORD3_OFFSET)
+#define KINETIS_MPU_RGD2_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD2_WORD0_OFFSET)
+#define KINETIS_MPU_RGD2_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD2_WORD1_OFFSET)
+#define KINETIS_MPU_RGD2_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD2_WORD2_OFFSET)
+#define KINETIS_MPU_RGD2_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD2_WORD3_OFFSET)
+#define KINETIS_MPU_RGD3_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD3_WORD0_OFFSET)
+#define KINETIS_MPU_RGD3_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD3_WORD1_OFFSET)
+#define KINETIS_MPU_RGD3_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD3_WORD2_OFFSET)
+#define KINETIS_MPU_RGD3_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD3_WORD3_OFFSET)
+#define KINETIS_MPU_RGD4_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD4_WORD0_OFFSET)
+#define KINETIS_MPU_RGD4_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD4_WORD1_OFFSET)
+#define KINETIS_MPU_RGD4_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD4_WORD2_OFFSET)
+#define KINETIS_MPU_RGD4_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD4_WORD3_OFFSET)
+#define KINETIS_MPU_RGD5_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD5_WORD0_OFFSET)
+#define KINETIS_MPU_RGD5_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD5_WORD1_OFFSET)
+#define KINETIS_MPU_RGD5_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD5_WORD2_OFFSET)
+#define KINETIS_MPU_RGD5_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD5_WORD3_OFFSET)
+#define KINETIS_MPU_RGD6_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD6_WORD0_OFFSET)
+#define KINETIS_MPU_RGD6_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD6_WORD1_OFFSET)
+#define KINETIS_MPU_RGD6_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD6_WORD2_OFFSET)
+#define KINETIS_MPU_RGD6_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD6_WORD3_OFFSET)
+#define KINETIS_MPU_RGD7_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD7_WORD0_OFFSET)
+#define KINETIS_MPU_RGD7_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD7_WORD1_OFFSET)
+#define KINETIS_MPU_RGD7_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD7_WORD2_OFFSET)
+#define KINETIS_MPU_RGD7_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD7_WORD3_OFFSET)
+#define KINETIS_MPU_RGD8_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD8_WORD0_OFFSET)
+#define KINETIS_MPU_RGD8_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD8_WORD1_OFFSET)
+#define KINETIS_MPU_RGD8_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD8_WORD2_OFFSET)
+#define KINETIS_MPU_RGD8_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD8_WORD3_OFFSET)
+#define KINETIS_MPU_RGD9_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD9_WORD0_OFFSET)
+#define KINETIS_MPU_RGD9_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD9_WORD1_OFFSET)
+#define KINETIS_MPU_RGD9_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD9_WORD2_OFFSET)
+#define KINETIS_MPU_RGD9_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD9_WORD3_OFFSET)
+#define KINETIS_MPU_RGD10_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD10_WORD0_OFFSET)
+#define KINETIS_MPU_RGD10_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD10_WORD1_OFFSET)
+#define KINETIS_MPU_RGD10_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD10_WORD2_OFFSET)
+#define KINETIS_MPU_RGD10_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD10_WORD3_OFFSET)
+#define KINETIS_MPU_RGD11_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD11_WORD0_OFFSET)
+#define KINETIS_MPU_RGD11_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD11_WORD1_OFFSET)
+#define KINETIS_MPU_RGD11_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD11_WORD2_OFFSET)
+#define KINETIS_MPU_RGD11_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD11_WORD3_OFFSET)
+
+#define KINETIS_MPU_RGDAAC(n) (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC_OFFSET(n))
+
+#define KINETIS_MPU_RGDAAC0 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC0_OFFSET)
+#define KINETIS_MPU_RGDAAC1 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC1_OFFSET)
+#define KINETIS_MPU_RGDAAC2 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC2_OFFSET)
+#define KINETIS_MPU_RGDAAC3 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC3_OFFSET)
+#define KINETIS_MPU_RGDAAC4 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC4_OFFSET)
+#define KINETIS_MPU_RGDAAC5 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC5_OFFSET)
+#define KINETIS_MPU_RGDAAC6 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC6_OFFSET)
+#define KINETIS_MPU_RGDAAC7 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC7_OFFSET)
+#define KINETIS_MPU_RGDAAC8 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC8_OFFSET)
+#define KINETIS_MPU_RGDAAC9 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC9_OFFSET)
+#define KINETIS_MPU_RGDAAC10 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC10_OFFSET)
+#define KINETIS_MPU_RGDAAC11 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC11_OFFSET)
+
+/* Register Bit Definitions *************************************************************************/
+
+/* Control/Error Status Register */
+
+#define MPU_CESR_VLD (1 << 0) /* Bit 0: Valid (global enable/disable for the MPU) */
+ /* Bits 1-7: Reserved */
+#define MPU_CESR_NRGD_SHIFT (8) /* Bits 8-11: Number of region descriptors */
+#define MPU_CESR_NRGD_MASK (15 << MPU_CESR_NRGD_SHIFT)
+# define MPU_CESR_NRGD_8DESC (0 << MPU_CESR_NRGD_SHIFT) /* 8 region descriptors */
+# define MPU_CESR_NRGD_12DESC (1 << MPU_CESR_NRGD_SHIFT) /* 12 region descriptors */
+# define MPU_CESR_NRGD_16DESC (2 << MPU_CESR_NRGD_SHIFT) /* 16 region descriptors */
+#define MPU_CESR_NSP_SHIFT (12) /* Bits 12-15: Number of slave ports */
+#define MPU_CESR_NSP_MASK (15 << MPU_CESR_NSP_SHIFT)
+#define MPU_CESR_HRL_SHIFT (16) /* Bits 16-19: Hardware revision level */
+#define MPU_CESR_HRL_MASK (15 << MPU_CESR_HRL_SHIFT)
+ /* Bits 20-26: Reserved */
+#define MPU_CESR_SPERR_SHIFT (27) /* Bits 27-31: Slave port n error */
+#define MPU_CESR_SPERR_MASK (31 << MPU_CESR_SPERR_SHIFT)
+# define MPU_CESR_SPERR_SPORT(n) ((1 << (4-(n))) << MPU_CESR_SPERR_SHIFT) /* Slave port nn */
+# define MPU_CESR_SPERR_SPORT0 (16 << MPU_CESR_SPERR_SHIFT) /* Slave port 0 */
+# define MPU_CESR_SPERR_SPORT1 (8 << MPU_CESR_SPERR_SHIFT) /* Slave port 1 */
+# define MPU_CESR_SPERR_SPORT2 (4 << MPU_CESR_SPERR_SHIFT) /* Slave port 2 */
+# define MPU_CESR_SPERR_SPORT3 (2 << MPU_CESR_SPERR_SHIFT) /* Slave port 3 */
+# define MPU_CESR_SPERR_SPORT4 (1 << MPU_CESR_SPERR_SHIFT) /* Slave port 4 */
+
+/* Error Address Register, Slave Port n. 32-bit error address. */
+
+/* Error Detail Register, Slave Port n */
+
+#define MPU_EDR_ERW (1 << 0) /* Bit 0: Error read/write */
+#define MPU_EDR_EATTR_SHIFT (1) /* Bits 1-3: Error attributes */
+#define MPU_EDR_EATTR_MASK (7 << MPU_EDR_EATTR_SHIFT)
+# define MPU_EDR_EATTR_USRINST (0 << MPU_EDR_EATTR_SHIFT) /* User mode, instruction access */
+# define MPU_EDR_EATTR_USRDATA (1 << MPU_EDR_EATTR_SHIFT) /* User mode, data access */
+# define MPU_EDR_EATTR_SUPINST (2 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, instruction access */
+# define MPU_EDR_EATTR_SUPDATA (3 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, data access */
+#define MPU_EDR_EMN_SHIFT (4) /* Bits 4-7: Error master number */
+#define MPU_EDR_EMN_MASK (15 << MPU_EDR_EMN_SHIFT)
+ /* Bits 8-15: Reserved */
+#define MPU_EDR_EACD_SHIFT (26) /* Bits 16-31: Error access control detail */
+#define MPU_EDR_EACD_MASK (0xffff << MPU_EDR_EACD_SHIFT)
+
+/* Region Descriptor n, Word 0 */
+ /* Bits 0-4: Reserved */
+#define MPU_RGD_WORD0_SRTADDR_SHIFT (5) /* Bits 5-31: Start address */
+#define MPU_RGD_WORD0_SRTADDR_MASK (0xffffffe0)
+
+/* Region Descriptor n, Word 1 */
+ /* Bits 0-4: Reserved */
+#define MPU_RGD_WORD1_ENDADDR_SHIFT (5) /* Bits 5-31: End address */
+#define MPU_RGD_WORD1_ENDADDR_MASK (0xffffffe0)
+
+/* Region Descriptor n, Word 2 */
+
+#define MPU_RGD_MSM_RWX 0 /* R/W/X; read, write and execute allowed */
+#define MPU_RGD_MSM_RX 1 /* R/X; read and execute allowed, but no write */
+#define MPU_RGD_MSM_RW 2 /* R/W; read and write allowed, but no execute */
+#define MPU_RGD_MSM_UM 3 /* Same as user mode defined in MUM */
+
+#define MPU_RGD_MUM_R 4 /* Read allowed */
+#define MPU_RGD_MUM_W 2 /* Write allowed */
+#define MPU_RGD_MUM_X 1 /* Execute allocated */
+
+#define MPU_RGD_WORD2_M0UM_SHIFT (0) /* Bits 0-2: Bus master 0 user mode access control */
+#define MPU_RGD_WORD2_M0UM_MASK (7 << MPU_RGD_WORD2_M0UM_SHIFT)
+#define MPU_RGD_WORD2_M0SM_SHIFT (3) /* Bits 3-4: Bus master 0 supervisor mode access control */
+#define MPU_RGD_WORD2_M0SM_MASK (3 << MPU_RGD_WORD2_M0SM_SHIFT)
+#define MPU_RGD_WORD2_M0PE (1 << 5) /* Bit 5: Bus Master 0 Process Identifier Enable */
+#define MPU_RGD_WORD2_M1UM_SHIFT (6) /* Bits 6-8: Bus master 1 user mode access control */
+#define MPU_RGD_WORD2_M1UM_MASK (7 << MPU_RGD_WORD2_M1UM_SHIFT)
+#define MPU_RGD_WORD2_M1SM_SHIFT (9) /* Bits 9-10: Bus master 1 supervisor mode access control */
+#define MPU_RGD_WORD2_M1SM_MASK (3 << MPU_RGD_WORD2_M1SM_SHIFT)
+#define MPU_RGD_WORD2_M1PE (1 << 11) /* Bit 11: Bus Master 1 Process Identifier Enable */
+#define MPU_RGD_WORD2_M2UM_SHIFT (12) /* Bits 12-14: Bus master 2 user mode access control */
+#define MPU_RGD_WORD2_M2UM_MASK (7 << MPU_RGD_WORD2_M2UM_SHIFT)
+#define MPU_RGD_WORD2_M2SM_SHIFT (15) /* Bits 15-16: Bus master 2 supervisor mode access control */
+#define MPU_RGD_WORD2_M2SM_MASK (3 << MPU_RGD_WORD2_M2SM_SHIFT)
+#define MPU_RGD_WORD2_M2PE (1 << 17) /* Bit 17: Bus Master 2 Process Identifier Enable */
+#define MPU_RGD_WORD2_M3UM_SHIFT (18) /* Bits 18-20: Bus master 3 user mode access control */
+#define MPU_RGD_WORD2_M3UM_MASK (7 << MPU_RGD_WORD2_M3UM_SHIFT)
+#define MPU_RGD_WORD2_M3SM_SHIFT (21) /* Bits 21-22: Bus master 3 supervisor mode access control */
+#define MPU_RGD_WORD2_M3SM_MASK (3 << MPU_RGD_WORD2_M3SM_SHIFT)
+#define MPU_RGD_WORD2_M3PE (1 << 23) /* Bit 23: Bus Master 3 Process Identifier Enable */
+#define MPU_RGD_WORD2_M4WE (1 << 24) /* Bit 24: Bus master 4 write enable */
+#define MPU_RGD_WORD2_M4RE (1 << 25) /* Bit 25: Bus master 4 read enable */
+#define MPU_RGD_WORD2_M5WE (1 << 26) /* Bit 26: Bus master 5 write enable */
+#define MPU_RGD_WORD2_M5RE (1 << 27) /* Bit 27: Bus master 5 read enable */
+#define MPU_RGD_WORD2_M6WE (1 << 28) /* Bit 28: Bus master 6 write enable */
+#define MPU_RGD_WORD2_M6RE (1 << 29) /* Bit 29: Bus master 6 read enable */
+#define MPU_RGD_WORD2_M7WE (1 << 30) /* Bit 30: Bus master 7 write enable */
+#define MPU_RGD_WORD2_M7RE (1 << 31) /* Bit 31: Bus master 7 read enable */
+
+/* Region Descriptor n, Word 3 */
+
+#define MPU_RGD_WORD3_VLD (1 << 0) /* Bit 0: Valid */
+ /* Bits 1-31: Reserved */
+/* Region Descriptor Alternate Access Control n */
+
+#define MPU_RGD_RBDACC_M0UM_SHIFT (0) /* Bits 0-2: Bus master 0 user mode access control */
+#define MPU_RGD_RBDACC_M0UM_MASK (7 << MPU_RGD_RBDACC_M0UM_SHIFT)
+#define MPU_RGD_RBDACC_M0SM_SHIFT (3) /* Bits 3-4: Bus master 0 supervisor mode access control */
+#define MPU_RGD_RBDACC_M0SM_MASK (3 << MPU_RGD_RBDACC_M0SM_SHIFT)
+ /* Bit 5: Reserved */
+#define MPU_RGD_RBDACC_M1UM_SHIFT (6) /* Bits 6-8: Bus master 1 user mode access control */
+#define MPU_RGD_RBDACC_M1UM_MASK (7 << MPU_RGD_RBDACC_M1UM_SHIFT)
+#define MPU_RGD_RBDACC_M1SM_SHIFT (9) /* Bits 9-10: Bus master 1 supervisor mode access control */
+#define MPU_RGD_RBDACC_M1SM_MASK (3 << MPU_RGD_RBDACC_M1SM_SHIFT)
+ /* Bit 11: Reserved */
+#define MPU_RGD_RBDACC_M2UM_SHIFT (12) /* Bits 12-14: Bus master 2 user mode access control */
+#define MPU_RGD_RBDACC_M2UM_MASK (7 << MPU_RGD_RBDACC_M2UM_SHIFT)
+#define MPU_RGD_RBDACC_M2SM_SHIFT (15) /* Bits 15-16: Bus master 2 supervisor mode access control */
+#define MPU_RGD_RBDACC_M2SM_MASK (3 << MPU_RGD_RBDACC_M2SM_SHIFT)
+ /* Bit 17: Reserved */
+#define MPU_RGD_RBDACC_M3UM_SHIFT (18) /* Bits 18-20: Bus master 3 user mode access control */
+#define MPU_RGD_RBDACC_M3UM_MASK (7 << MPU_RGD_RBDACC_M3UM_SHIFT)
+#define MPU_RGD_RBDACC_M3SM_SHIFT (21) /* Bits 21-22: Bus master 3 supervisor mode access control */
+#define MPU_RGD_RBDACC_M3SM_MASK (3 << MPU_RGD_RBDACC_M3SM_SHIFT)
+ /* Bit 23: Reserved */
+#define MPU_RGD_RBDACC_M4WE (1 << 24) /* Bit 24: Bus master 4 write enable */
+#define MPU_RGD_RBDACC_M4RE (1 << 25) /* Bit 25: Bus master 4 read enable */
+#define MPU_RGD_RBDACC_M5WE (1 << 26) /* Bit 26: Bus master 5 write enable */
+#define MPU_RGD_RBDACC_M5RE (1 << 27) /* Bit 27: Bus master 5 read enable */
+#define MPU_RGD_RBDACC_M6WE (1 << 28) /* Bit 28: Bus master 6 write enable */
+#define MPU_RGD_RBDACC_M6RE (1 << 29) /* Bit 29: Bus master 6 read enable */
+#define MPU_RGD_RBDACC_M7WE (1 << 30) /* Bit 30: Bus master 7 write enable */
+#define MPU_RGD_RBDACC_M7RE (1 << 31) /* Bit 31: Bus master 7 read enable */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_MPU_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k64pinmux.h b/arch/arm/src/kinetis/chip/kinetis_k64pinmux.h
new file mode 100644
index 0000000000000000000000000000000000000000..3479099bf6c99c2275611636ded8721fe11f1526
--- /dev/null
+++ b/arch/arm/src/kinetis/chip/kinetis_k64pinmux.h
@@ -0,0 +1,640 @@
+/********************************************************************************************
+ * arch/arm/src/kinetis/chip/kinetis_k64pinmux.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_CHP_KINETIS_K64PINMUX_H
+#define __ARCH_ARM_SRC_KINETIS_CHP_KINETIS_K64PINMUX_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+#ifdef KINETIS_K64
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+/* In most cases, there are alternative configurations for various pins. Those alternative
+ * pins are labeled with a suffix like _1, _2, etc. in order to distinguish them. Logic in
+ * the board.h file must select the correct pin configuration for the board by defining a pin
+ * configuration (with no suffix) that maps to the correct alternative.
+ *
+ * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific GPIO options such as frequency,
+ * open-drain/push-pull, and pull-up/down! Just the basics are defined for most
+ * pins in the initial version of this file.
+ */
+
+/* ADC */
+
+#define PIN_ADC0_DM2 (PIN_ANALOG | PIN_PORTE | PIN3)
+#define PIN_ADC0_DP2 (PIN_ANALOG | PIN_PORTE | PIN2)
+#define PIN_ADC0_SE4B (PIN_ANALOG | PIN_PORTC | PIN2)
+#define PIN_ADC0_SE5B (PIN_ANALOG | PIN_PORTD | PIN1)
+#define PIN_ADC0_SE6B (PIN_ANALOG | PIN_PORTD | PIN5)
+#define PIN_ADC0_SE7B (PIN_ANALOG | PIN_PORTD | PIN6)
+#define PIN_ADC0_SE8 (PIN_ANALOG | PIN_PORTB | PIN0)
+#define PIN_ADC0_SE9 (PIN_ANALOG | PIN_PORTB | PIN1)
+#define PIN_ADC0_SE10 (PIN_ANALOG | PIN_PORTA | PIN7)
+#define PIN_ADC0_SE11 (PIN_ANALOG | PIN_PORTA | PIN8)
+#define PIN_ADC0_SE12 (PIN_ANALOG | PIN_PORTB | PIN2)
+#define PIN_ADC0_SE13 (PIN_ANALOG | PIN_PORTB | PIN3)
+#define PIN_ADC0_SE14 (PIN_ANALOG | PIN_PORTC | PIN0)
+#define PIN_ADC0_SE15 (PIN_ANALOG | PIN_PORTC | PIN1)
+#define PIN_ADC0_SE17 (PIN_ANALOG | PIN_PORTE | PIN24)
+#define PIN_ADC0_SE18 (PIN_ANALOG | PIN_PORTE | PIN25)
+
+#define PIN_ADC1_SE4A (PIN_ANALOG | PIN_PORTE | PIN0)
+#define PIN_ADC1_SE4B (PIN_ANALOG | PIN_PORTC | PIN8)
+#define PIN_ADC1_SE5A (PIN_ANALOG | PIN_PORTE | PIN1)
+#define PIN_ADC1_SE5B (PIN_ANALOG | PIN_PORTC | PIN9)
+#define PIN_ADC1_SE6A (PIN_ANALOG | PIN_PORTE | PIN2)
+#define PIN_ADC1_SE6B (PIN_ANALOG | PIN_PORTC | PIN10)
+#define PIN_ADC1_SE7A (PIN_ANALOG | PIN_PORTE | PIN3)
+#define PIN_ADC1_SE7B (PIN_ANALOG | PIN_PORTC | PIN11)
+#define PIN_ADC1_SE8 (PIN_ANALOG | PIN_PORTB | PIN0)
+#define PIN_ADC1_SE9 (PIN_ANALOG | PIN_PORTB | PIN1)
+#define PIN_ADC1_SE10 (PIN_ANALOG | PIN_PORTB | PIN4)
+#define PIN_ADC1_SE11 (PIN_ANALOG | PIN_PORTB | PIN5)
+#define PIN_ADC1_SE12 (PIN_ANALOG | PIN_PORTB | PIN6)
+#define PIN_ADC1_SE13 (PIN_ANALOG | PIN_PORTB | PIN7)
+#define PIN_ADC1_SE14 (PIN_ANALOG | PIN_PORTB | PIN10)
+#define PIN_ADC1_SE15 (PIN_ANALOG | PIN_PORTB | PIN11)
+#define PIN_ADC1_SE17 (PIN_ANALOG | PIN_PORTA | PIN17)
+
+/* CAN */
+
+#define PIN_CAN0_RX_1 (PIN_ALT2 | PIN_PORTA | PIN13)
+#define PIN_CAN0_RX_2 (PIN_ALT2 | PIN_PORTB | PIN19)
+#define PIN_CAN0_TX_1 (PIN_ALT2 | PIN_PORTA | PIN12)
+#define PIN_CAN0_TX_2 (PIN_ALT2 | PIN_PORTB | PIN18)
+
+/* Output clock */
+
+#define PIN_CLKOUT_1 (PIN_ALT5 | PIN_PORTA | PIN6)
+#define PIN_CLKOUT_2 (PIN_ALT5 | PIN_PORTC | PIN3)
+
+/* Comparators */
+
+#define PIN_CMP0_IN0 (PIN_ANALOG | PIN_PORTC | PIN6)
+#define PIN_CMP0_IN1 (PIN_ANALOG | PIN_PORTC | PIN7)
+#define PIN_CMP0_IN2 (PIN_ANALOG | PIN_PORTC | PIN8)
+#define PIN_CMP0_IN3 (PIN_ANALOG | PIN_PORTC | PIN9)
+#define PIN_CMP0_OUT_1 (PIN_ALT6 | PIN_PORTB | PIN20)
+#define PIN_CMP0_OUT_2 (PIN_ALT6 | PIN_PORTC | PIN5)
+
+#define PIN_CMP1_IN0 (PIN_ANALOG | PIN_PORTC | PIN2)
+#define PIN_CMP1_IN1 (PIN_ANALOG | PIN_PORTC | PIN3)
+#define PIN_CMP1_OUT_1 (PIN_ALT6 | PIN_PORTB | PIN21)
+#define PIN_CMP1_OUT_2 (PIN_ALT6 | PIN_PORTC | PIN4)
+
+#define PIN_CMP2_IN0 (PIN_ANALOG | PIN_PORTA | PIN12)
+#define PIN_CMP2_IN1 (PIN_ANALOG | PIN_PORTA | PIN13)
+#define PIN_CMP2_OUT_1 (PIN_ALT5 | PIN_PORTA | PIN5)
+#define PIN_CMP2_OUT_2 (PIN_ALT6 | PIN_PORTB | PIN22)
+
+/* Carrier Modulator Transmittor (CMT) */
+
+#define PIN_CMT_IRO (PIN_ALT2 | PIN_PORTD | PIN7)
+
+/* Ethernet */
+
+#define PIN_ENET_1588_CLKIN (PIN_ALT2 | PIN_PORTE | PIN26)
+#define PIN_ENET0_1588_TMR0_1 (PIN_ALT4 | PIN_PORTB | PIN2)
+#define PIN_ENET0_1588_TMR0_2 (PIN_ALT4 | PIN_PORTC | PIN16)
+#define PIN_ENET0_1588_TMR1_1 (PIN_ALT4 | PIN_PORTB | PIN3)
+#define PIN_ENET0_1588_TMR1_2 (PIN_ALT4 | PIN_PORTC | PIN17)
+#define PIN_ENET0_1588_TMR2_1 (PIN_ALT4 | PIN_PORTB | PIN4)
+#define PIN_ENET0_1588_TMR2_2 (PIN_ALT4 | PIN_PORTC | PIN18)
+#define PIN_ENET0_1588_TMR3_1 (PIN_ALT4 | PIN_PORTB | PIN5)
+#define PIN_ENET0_1588_TMR3_2 (PIN_ALT4 | PIN_PORTC | PIN19)
+
+/* External Watchdog Monitor (EWM) */
+
+#define PIN_EWM_IN_1 (PIN_ALT6 | PIN_PORTB | PIN16)
+#define PIN_EWM_IN_2 (PIN_ALT6 | PIN_PORTD | PIN4)
+#define PIN_EWM_IN_3 (PIN_ALT6 | PIN_PORTE | PIN25)
+#define PIN_EWM_OUT_1 (PIN_ALT6 | PIN_PORTB | PIN17)
+#define PIN_EWM_OUT_2 (PIN_ALT6 | PIN_PORTD | PIN5)
+#define PIN_EWM_OUT_3 (PIN_ALT6 | PIN_PORTE | PIN24)
+
+/* FlexBus */
+
+#define PIN_FB_A16 (PIN_ALT6 | PIN_PORTD | PIN8)
+#define PIN_FB_A17 (PIN_ALT6 | PIN_PORTD | PIN9)
+#define PIN_FB_A18 (PIN_ALT6 | PIN_PORTD | PIN10)
+#define PIN_FB_A19 (PIN_ALT6 | PIN_PORTD | PIN11)
+#define PIN_FB_A20 (PIN_ALT6 | PIN_PORTD | PIN12)
+#define PIN_FB_A21 (PIN_ALT6 | PIN_PORTD | PIN13)
+#define PIN_FB_A22 (PIN_ALT6 | PIN_PORTD | PIN14)
+#define PIN_FB_A23 (PIN_ALT6 | PIN_PORTD | PIN15)
+#define PIN_FB_A24 (PIN_ALT6 | PIN_PORTA | PIN29)
+#define PIN_FB_A25 (PIN_ALT6 | PIN_PORTA | PIN28)
+#define PIN_FB_A26 (PIN_ALT6 | PIN_PORTA | PIN27)
+#define PIN_FB_A27 (PIN_ALT6 | PIN_PORTA | PIN26)
+#define PIN_FB_A28 (PIN_ALT6 | PIN_PORTA | PIN25)
+#define PIN_FB_A29 (PIN_ALT6 | PIN_PORTA | PIN24)
+#define PIN_FB_AD0 (PIN_ALT5 | PIN_PORTD | PIN6)
+#define PIN_FB_AD1 (PIN_ALT5 | PIN_PORTD | PIN5)
+#define PIN_FB_AD2 (PIN_ALT5 | PIN_PORTD | PIN4)
+#define PIN_FB_AD3 (PIN_ALT5 | PIN_PORTD | PIN3)
+#define PIN_FB_AD4 (PIN_ALT5 | PIN_PORTD | PIN2)
+#define PIN_FB_AD5 (PIN_ALT5 | PIN_PORTC | PIN10)
+#define PIN_FB_AD6 (PIN_ALT5 | PIN_PORTC | PIN9)
+#define PIN_FB_AD7 (PIN_ALT5 | PIN_PORTC | PIN8)
+#define PIN_FB_AD8 (PIN_ALT5 | PIN_PORTC | PIN7)
+#define PIN_FB_AD9 (PIN_ALT5 | PIN_PORTC | PIN6)
+#define PIN_FB_AD10 (PIN_ALT5 | PIN_PORTC | PIN5)
+#define PIN_FB_AD11 (PIN_ALT5 | PIN_PORTC | PIN4)
+#define PIN_FB_AD12 (PIN_ALT5 | PIN_PORTC | PIN2)
+#define PIN_FB_AD13 (PIN_ALT5 | PIN_PORTC | PIN1)
+#define PIN_FB_AD14 (PIN_ALT5 | PIN_PORTC | PIN0)
+#define PIN_FB_AD15 (PIN_ALT5 | PIN_PORTB | PIN18)
+#define PIN_FB_AD16 (PIN_ALT5 | PIN_PORTB | PIN17)
+#define PIN_FB_AD17 (PIN_ALT5 | PIN_PORTB | PIN16)
+#define PIN_FB_AD18 (PIN_ALT5 | PIN_PORTB | PIN11)
+#define PIN_FB_AD19 (PIN_ALT5 | PIN_PORTB | PIN10)
+#define PIN_FB_AD20 (PIN_ALT5 | PIN_PORTB | PIN9)
+#define PIN_FB_AD21 (PIN_ALT5 | PIN_PORTB | PIN8)
+#define PIN_FB_AD22 (PIN_ALT5 | PIN_PORTB | PIN7)
+#define PIN_FB_AD23 (PIN_ALT5 | PIN_PORTB | PIN6)
+#define PIN_FB_AD24 (PIN_ALT5 | PIN_PORTC | PIN15)
+#define PIN_FB_AD25 (PIN_ALT5 | PIN_PORTC | PIN14)
+#define PIN_FB_AD26 (PIN_ALT5 | PIN_PORTC | PIN13)
+#define PIN_FB_AD27 (PIN_ALT5 | PIN_PORTC | PIN12)
+#define PIN_FB_AD28 (PIN_ALT5 | PIN_PORTB | PIN23)
+#define PIN_FB_AD29 (PIN_ALT5 | PIN_PORTB | PIN22)
+#define PIN_FB_AD30 (PIN_ALT5 | PIN_PORTB | PIN21)
+#define PIN_FB_AD31 (PIN_ALT5 | PIN_PORTB | PIN20)
+#define PIN_FB_ALE (PIN_ALT5 | PIN_PORTD | PIN0)
+#define PIN_FB_BE15_8_BLS23_16 (PIN_ALT5 | PIN_PORTC | PIN18)
+#define PIN_FB_BE23_16_BLS15_8 (PIN_ALT5 | PIN_PORTC | PIN16)
+#define PIN_FB_BE31_24_BLS7_0 (PIN_ALT5 | PIN_PORTC | PIN17)
+#define PIN_FB_BE7_0_BLS31_24 (PIN_ALT5 | PIN_PORTC | PIN19)
+#define PIN_FB_CS0 (PIN_ALT5 | PIN_PORTD | PIN1)
+#define PIN_FB_CS1 (PIN_ALT5 | PIN_PORTD | PIN0)
+#define PIN_FB_CS2 (PIN_ALT5 | PIN_PORTC | PIN18)
+#define PIN_FB_CS3 (PIN_ALT5 | PIN_PORTC | PIN19)
+#define PIN_FB_CS4 (PIN_ALT5 | PIN_PORTC | PIN17)
+#define PIN_FB_CS5 (PIN_ALT5 | PIN_PORTC | PIN16)
+#define PIN_FB_OE (PIN_ALT5 | PIN_PORTB | PIN19)
+#define PIN_FB_RW (PIN_ALT5 | PIN_PORTC | PIN11)
+#define PIN_FB_TA (PIN_ALT6 | PIN_PORTC | PIN19)
+#define PIN_FB_TBST (PIN_ALT5 | PIN_PORTC | PIN18)
+#define PIN_FB_TS (PIN_ALT5 | PIN_PORTD | PIN0)
+#define PIN_FB_TSIZ0 (PIN_ALT5 | PIN_PORTC | PIN17)
+#define PIN_FB_TSIZ1 (PIN_ALT5 | PIN_PORTC | PIN16)
+
+/* FlexTimer Module (FTM) */
+
+#define PIN_FTM_CLKIN0_1 (PIN_ALT4 | PIN_PORTA | PIN18)
+#define PIN_FTM_CLKIN0_2 (PIN_ALT4 | PIN_PORTB | PIN16)
+#define PIN_FTM_CLKIN1_1 (PIN_ALT4 | PIN_PORTA | PIN19)
+#define PIN_FTM_CLKIN1_2 (PIN_ALT4 | PIN_PORTB | PIN17)
+
+#define PIN_FTM0_CH0_1 (PIN_ALT3 | PIN_PORTA | PIN3)
+#define PIN_FTM0_CH0_2 (PIN_ALT4 | PIN_PORTC | PIN1)
+#define PIN_FTM0_CH1_1 (PIN_ALT3 | PIN_PORTA | PIN4)
+#define PIN_FTM0_CH1_2 (PIN_ALT4 | PIN_PORTC | PIN2)
+#define PIN_FTM0_CH2_1 (PIN_ALT3 | PIN_PORTA | PIN5)
+#define PIN_FTM0_CH2_2 (PIN_ALT4 | PIN_PORTC | PIN3)
+#define PIN_FTM0_CH2_3 (PIN_ALT7 | PIN_PORTC | PIN5)
+#define PIN_FTM0_CH3_1 (PIN_ALT3 | PIN_PORTA | PIN6)
+#define PIN_FTM0_CH3_2 (PIN_ALT4 | PIN_PORTC | PIN4)
+#define PIN_FTM0_CH4_1 (PIN_ALT3 | PIN_PORTA | PIN7)
+#define PIN_FTM0_CH4_2 (PIN_ALT4 | PIN_PORTB | PIN12)
+#define PIN_FTM0_CH4_3 (PIN_ALT4 | PIN_PORTD | PIN4)
+#define PIN_FTM0_CH5_1 (PIN_ALT3 | PIN_PORTA | PIN0)
+#define PIN_FTM0_CH5_2 (PIN_ALT4 | PIN_PORTB | PIN13)
+#define PIN_FTM0_CH5_3 (PIN_ALT4 | PIN_PORTD | PIN5)
+#define PIN_FTM0_CH6_1 (PIN_ALT3 | PIN_PORTA | PIN1)
+#define PIN_FTM0_CH6_2 (PIN_ALT4 | PIN_PORTD | PIN6)
+#define PIN_FTM0_CH7_1 (PIN_ALT3 | PIN_PORTA | PIN2)
+#define PIN_FTM0_CH7_2 (PIN_ALT4 | PIN_PORTD | PIN7)
+#define PIN_FTM0_FLT0_1 (PIN_ALT6 | PIN_PORTB | PIN3)
+#define PIN_FTM0_FLT0_2 (PIN_ALT6 | PIN_PORTD | PIN6)
+#define PIN_FTM0_FLT1_1 (PIN_ALT6 | PIN_PORTB | PIN10)
+#define PIN_FTM0_FLT1_2 (PIN_ALT6 | PIN_PORTD | PIN7)
+#define PIN_FTM0_FLT2_1 (PIN_ALT3 | PIN_PORTA | PIN18)
+#define PIN_FTM0_FLT2_2 (PIN_ALT6 | PIN_PORTB | PIN11)
+#define PIN_FTM0_FLT3 (PIN_ALT6 | PIN_PORTB | PIN2)
+
+#define PIN_FTM1_CH0_1 (PIN_ALT3 | PIN_PORTA | PIN12)
+#define PIN_FTM1_CH0_2 (PIN_ALT3 | PIN_PORTA | PIN8)
+#define PIN_FTM1_CH0_3 (PIN_ALT3 | PIN_PORTB | PIN0)
+#define PIN_FTM1_CH0_4 (PIN_ALT3 | PIN_PORTB | PIN12)
+#define PIN_FTM1_CH1_1 (PIN_ALT3 | PIN_PORTA | PIN13)
+#define PIN_FTM1_CH1_2 (PIN_ALT3 | PIN_PORTA | PIN9)
+#define PIN_FTM1_CH1_3 (PIN_ALT3 | PIN_PORTB | PIN1)
+#define PIN_FTM1_CH1_4 (PIN_ALT3 | PIN_PORTB | PIN13)
+#define PIN_FTM1_FLT0_1 (PIN_ALT3 | PIN_PORTA | PIN19)
+#define PIN_FTM1_FLT0_2 (PIN_ALT6 | PIN_PORTB | PIN4)
+#define PIN_FTM1_QD_PHA_1 (PIN_ALT6 | PIN_PORTA | PIN8)
+#define PIN_FTM1_QD_PHA_2 (PIN_ALT6 | PIN_PORTB | PIN0)
+#define PIN_FTM1_QD_PHA_3 (PIN_ALT6 | PIN_PORTB | PIN12)
+#define PIN_FTM1_QD_PHA_4 (PIN_ALT7 | PIN_PORTA | PIN12)
+#define PIN_FTM1_QD_PHB_1 (PIN_ALT6 | PIN_PORTA | PIN9)
+#define PIN_FTM1_QD_PHB_2 (PIN_ALT6 | PIN_PORTB | PIN1)
+#define PIN_FTM1_QD_PHB_3 (PIN_ALT6 | PIN_PORTB | PIN13)
+#define PIN_FTM1_QD_PHB_4 (PIN_ALT7 | PIN_PORTA | PIN13)
+
+#define PIN_FTM2_CH0_1 (PIN_ALT3 | PIN_PORTA | PIN10)
+#define PIN_FTM2_CH0_2 (PIN_ALT3 | PIN_PORTB | PIN18)
+#define PIN_FTM2_CH1_1 (PIN_ALT3 | PIN_PORTA | PIN11)
+#define PIN_FTM2_CH1_2 (PIN_ALT3 | PIN_PORTB | PIN19)
+#define PIN_FTM2_FLT0_1 (PIN_ALT6 | PIN_PORTB | PIN5)
+#define PIN_FTM2_FLT0_2 (PIN_ALT6 | PIN_PORTC | PIN9)
+#define PIN_FTM2_QD_PHA_1 (PIN_ALT6 | PIN_PORTA | PIN10)
+#define PIN_FTM2_QD_PHA_2 (PIN_ALT6 | PIN_PORTB | PIN18)
+#define PIN_FTM2_QD_PHB_1 (PIN_ALT6 | PIN_PORTA | PIN11)
+#define PIN_FTM2_QD_PHB_2 (PIN_ALT6 | PIN_PORTB | PIN19)
+
+#define PIN_FTM3_CH0_1 (PIN_ALT4 | PIN_PORTD | PIN0)
+#define PIN_FTM3_CH0_2 (PIN_ALT6 | PIN_PORTE | PIN5)
+#define PIN_FTM3_CH1_1 (PIN_ALT4 | PIN_PORTD | PIN1)
+#define PIN_FTM3_CH1_2 (PIN_ALT6 | PIN_PORTE | PIN6)
+#define PIN_FTM3_CH2_1 (PIN_ALT4 | PIN_PORTD | PIN2)
+#define PIN_FTM3_CH2_2 (PIN_ALT6 | PIN_PORTE | PIN7)
+#define PIN_FTM3_CH3_1 (PIN_ALT4 | PIN_PORTD | PIN3)
+#define PIN_FTM3_CH3_2 (PIN_ALT6 | PIN_PORTE | PIN8)
+#define PIN_FTM3_CH4_1 (PIN_ALT3 | PIN_PORTC | PIN8)
+#define PIN_FTM3_CH4_2 (PIN_ALT6 | PIN_PORTE | PIN9)
+#define PIN_FTM3_CH5_1 (PIN_ALT3 | PIN_PORTC | PIN9)
+#define PIN_FTM3_CH5_2 (PIN_ALT6 | PIN_PORTE | PIN10)
+#define PIN_FTM3_CH6_1 (PIN_ALT3 | PIN_PORTC | PIN10)
+#define PIN_FTM3_CH6_2 (PIN_ALT6 | PIN_PORTE | PIN11)
+#define PIN_FTM3_CH7_1 (PIN_ALT3 | PIN_PORTC | PIN11)
+#define PIN_FTM3_CH7_2 (PIN_ALT6 | PIN_PORTE | PIN12)
+#define PIN_FTM3_FLT0_1 (PIN_ALT3 | PIN_PORTD | PIN12)
+#define PIN_FTM3_FLT0_2 (PIN_ALT6 | PIN_PORTC | PIN12)
+
+/* I2C */
+
+#define PIN_I2C0_SCL_1 (PIN_ALT2 | PIN_PORTB | PIN0)
+#define PIN_I2C0_SCL_2 (PIN_ALT2 | PIN_PORTB | PIN2)
+#define PIN_I2C0_SCL_3 (PIN_ALT2 | PIN_PORTD | PIN8)
+#define PIN_I2C0_SCL_4 (PIN_ALT5 | PIN_PORTE | PIN24)
+#define PIN_I2C0_SCL_5 (PIN_ALT7 | PIN_PORTD | PIN2)
+#define PIN_I2C0_SDA_1 (PIN_ALT2 | PIN_PORTB | PIN1)
+#define PIN_I2C0_SDA_2 (PIN_ALT2 | PIN_PORTB | PIN3)
+#define PIN_I2C0_SDA_3 (PIN_ALT2 | PIN_PORTD | PIN9)
+#define PIN_I2C0_SDA_4 (PIN_ALT5 | PIN_PORTE | PIN25)
+#define PIN_I2C0_SDA_5 (PIN_ALT7 | PIN_PORTD | PIN3)
+
+#define PIN_I2C1_SCL_1 (PIN_ALT2 | PIN_PORTC | PIN10)
+#define PIN_I2C1_SCL_2 (PIN_ALT6 | PIN_PORTE | PIN1)
+#define PIN_I2C1_SDA_1 (PIN_ALT2 | PIN_PORTC | PIN11)
+#define PIN_I2C1_SDA_2 (PIN_ALT6 | PIN_PORTE | PIN0)
+
+#define PIN_I2C2_SCL_1 (PIN_ALT5 | PIN_PORTA | PIN12)
+#define PIN_I2C2_SCL_2 (PIN_ALT5 | PIN_PORTA | PIN14)
+#define PIN_I2C2_SDA_1 (PIN_ALT5 | PIN_PORTA | PIN11)
+#define PIN_I2C2_SDA_2 (PIN_ALT5 | PIN_PORTA | PIN13)
+
+/* I2S */
+
+#define PIN_I2S0_MCLK_1 (PIN_ALT4 | PIN_PORTC | PIN8)
+#define PIN_I2S0_MCLK_2 (PIN_ALT4 | PIN_PORTE | PIN6)
+#define PIN_I2S0_MCLK_3 (PIN_ALT6 | PIN_PORTA | PIN17)
+#define PIN_I2S0_MCLK_4 (PIN_ALT6 | PIN_PORTC | PIN6)
+#define PIN_I2S0_RX_BCLK_1 (PIN_ALT4 | PIN_PORTC | PIN6)
+#define PIN_I2S0_RX_BCLK_2 (PIN_ALT4 | PIN_PORTC | PIN9)
+#define PIN_I2S0_RX_BCLK_3 (PIN_ALT4 | PIN_PORTE | PIN9)
+#define PIN_I2S0_RX_BCLK_4 (PIN_ALT6 | PIN_PORTA | PIN14)
+#define PIN_I2S0_RX_FS_1 (PIN_ALT4 | PIN_PORTC | PIN10)
+#define PIN_I2S0_RX_FS_2 (PIN_ALT4 | PIN_PORTC | PIN7)
+#define PIN_I2S0_RX_FS_3 (PIN_ALT4 | PIN_PORTE | PIN8)
+#define PIN_I2S0_RX_FS_4 (PIN_ALT6 | PIN_PORTA | PIN16)
+#define PIN_I2S0_RXD0_1 (PIN_ALT4 | PIN_PORTC | PIN5)
+#define PIN_I2S0_RXD0_2 (PIN_ALT4 | PIN_PORTE | PIN7)
+#define PIN_I2S0_RXD0_3 (PIN_ALT6 | PIN_PORTA | PIN15)
+#define PIN_I2S0_RXD1_1 (PIN_ALT2 | PIN_PORTE | PIN8)
+#define PIN_I2S0_RXD1_2 (PIN_ALT4 | PIN_PORTC | PIN11)
+#define PIN_I2S0_RXD1_3 (PIN_ALT7 | PIN_PORTA | PIN16)
+#define PIN_I2S0_TX_BCLK_1 (PIN_ALT4 | PIN_PORTB | PIN18)
+#define PIN_I2S0_TX_BCLK_2 (PIN_ALT4 | PIN_PORTE | PIN12)
+#define PIN_I2S0_TX_BCLK_3 (PIN_ALT6 | PIN_PORTA | PIN5)
+#define PIN_I2S0_TX_BCLK_4 (PIN_ALT6 | PIN_PORTC | PIN3)
+#define PIN_I2S0_TX_FS_1 (PIN_ALT4 | PIN_PORTB | PIN19)
+#define PIN_I2S0_TX_FS_2 (PIN_ALT4 | PIN_PORTE | PIN11)
+#define PIN_I2S0_TX_FS_3 (PIN_ALT6 | PIN_PORTA | PIN13)
+#define PIN_I2S0_TX_FS_4 (PIN_ALT6 | PIN_PORTC | PIN2)
+#define PIN_I2S0_TXD0_1 (PIN_ALT4 | PIN_PORTE | PIN10)
+#define PIN_I2S0_TXD0_2 (PIN_ALT6 | PIN_PORTA | PIN12)
+#define PIN_I2S0_TXD0_3 (PIN_ALT6 | PIN_PORTC | PIN1)
+#define PIN_I2S0_TXD1_1 (PIN_ALT2 | PIN_PORTE | PIN9)
+#define PIN_I2S0_TXD1_2 (PIN_ALT6 | PIN_PORTC | PIN0)
+#define PIN_I2S0_TXD1_3 (PIN_ALT7 | PIN_PORTA | PIN14)
+
+/* JTAG */
+
+#define PIN_JTAG_TCLK (PIN_ALT7 | PIN_PORTA | PIN0)
+#define PIN_JTAG_TDI (PIN_ALT7 | PIN_PORTA | PIN1)
+#define PIN_JTAG_TDO (PIN_ALT7 | PIN_PORTA | PIN2)
+#define PIN_JTAG_TMS (PIN_ALT7 | PIN_PORTA | PIN3)
+#define PIN_JTAG_TRST (PIN_ALT7 | PIN_PORTA | PIN5)
+
+/* Low-leakage wakeup module (LLWU, actually GPIO configurations) */
+
+#define PIN_LLWU_P0 (PIN_ALT1 | PIN_PORTE | PIN1)
+#define PIN_LLWU_P1 (PIN_ALT1 | PIN_PORTE | PIN2)
+#define PIN_LLWU_P2 (PIN_ALT1 | PIN_PORTE | PIN4)
+#define PIN_LLWU_P3 (PIN_ALT1 | PIN_PORTA | PIN4)
+#define PIN_LLWU_P4 (PIN_ALT1 | PIN_PORTA | PIN13)
+#define PIN_LLWU_P5 (PIN_ALT1 | PIN_PORTB | PIN0)
+#define PIN_LLWU_P6 (PIN_ALT1 | PIN_PORTC | PIN1)
+#define PIN_LLWU_P7 (PIN_ALT1 | PIN_PORTC | PIN3)
+#define PIN_LLWU_P8 (PIN_ALT1 | PIN_PORTC | PIN4)
+#define PIN_LLWU_P9 (PIN_ALT1 | PIN_PORTC | PIN5)
+#define PIN_LLWU_P10 (PIN_ALT1 | PIN_PORTC | PIN6)
+#define PIN_LLWU_P11 (PIN_ALT1 | PIN_PORTC | PIN11)
+#define PIN_LLWU_P12 (PIN_ALT1 | PIN_PORTD | PIN0)
+#define PIN_LLWU_P13 (PIN_ALT1 | PIN_PORTD | PIN2)
+#define PIN_LLWU_P14 (PIN_ALT1 | PIN_PORTD | PIN4)
+#define PIN_LLWU_P15 (PIN_ALT1 | PIN_PORTD | PIN6)
+
+/* Low-Power Timer (LPTMR) */
+
+#define PIN_LPTMR0_ALT1 (PIN_ALT6 | PIN_PORTA | PIN19)
+#define PIN_LPTMR0_ALT2 (PIN_ALT3 | PIN_PORTC | PIN5)
+
+/* MII */
+
+#define PIN_MII0_COL (PIN_ALT4 | PIN_PORTA | PIN29)
+#define PIN_MII0_CRS (PIN_ALT4 | PIN_PORTA | PIN27)
+#define PIN_MII0_MDC (PIN_ALT4 | PIN_PORTB | PIN1)
+#ifdef CONFIG_KINETIS_ENET_MDIOPULLUP
+# define PIN_MII0_MDIO (PIN_ALT4_PULLUP | PIN_PORTB | PIN0)
+#else
+# define PIN_MII0_MDIO (PIN_ALT4 | PIN_PORTB | PIN0)
+#endif
+#define PIN_MII0_RXCLK (PIN_ALT4 | PIN_PORTA | PIN11)
+#define PIN_MII0_RXD0 (PIN_ALT4 | PIN_PORTA | PIN13)
+#define PIN_MII0_RXD1 (PIN_ALT4 | PIN_PORTA | PIN12)
+#define PIN_MII0_RXD2 (PIN_ALT4 | PIN_PORTA | PIN10)
+#define PIN_MII0_RXD3 (PIN_ALT4 | PIN_PORTA | PIN9)
+#define PIN_MII0_RXDV (PIN_ALT4 | PIN_PORTA | PIN14)
+#ifdef CONFIG_KINETIS_ENET_NORXER
+# define PIN_MII0_RXER (GPIO_PULLDOWN | PIN_PORTA | PIN5)
+#else
+# define PIN_MII0_RXER (PIN_ALT4 | PIN_PORTA | PIN5)
+#endif
+#define PIN_MII0_TXCLK (PIN_ALT4 | PIN_PORTA | PIN25)
+#define PIN_MII0_TXD0 (PIN_ALT4 | PIN_PORTA | PIN16)
+#define PIN_MII0_TXD1 (PIN_ALT4 | PIN_PORTA | PIN17)
+#define PIN_MII0_TXD2 (PIN_ALT4 | PIN_PORTA | PIN24)
+#define PIN_MII0_TXD3 (PIN_ALT4 | PIN_PORTA | PIN26)
+#define PIN_MII0_TXEN (PIN_ALT4 | PIN_PORTA | PIN15)
+#define PIN_MII0_TXER (PIN_ALT4 | PIN_PORTA | PIN28)
+
+/* NMI */
+
+#define PIN_NMI (PIN_ALT7 | PIN_PORTA | PIN4)
+
+/* Programmable Delay Block (PDB) */
+
+#define PIN_PDB0_EXTRG_1 (PIN_ALT3 | PIN_PORTC | PIN0)
+#define PIN_PDB0_EXTRG_2 (PIN_ALT3 | PIN_PORTC | PIN6)
+
+/* RMII */
+
+#define PIN_RMII0_CRS_DV (PIN_ALT4 | PIN_PORTA | PIN14)
+#define PIN_RMII0_MDC (PIN_ALT4 | PIN_PORTB | PIN1)
+#ifdef CONFIG_KINETIS_ENET_MDIOPULLUP
+# define PIN_RMII0_MDIO (PIN_ALT4_PULLUP | PIN_PORTB | PIN0)
+#else
+# define PIN_RMII0_MDIO (PIN_ALT4 | PIN_PORTB | PIN0)
+#endif
+#define PIN_RMII0_RXD0 (PIN_ALT4 | PIN_PORTA | PIN13)
+#define PIN_RMII0_RXD1 (PIN_ALT4 | PIN_PORTA | PIN12)
+#ifdef CONFIG_KINETIS_ENET_NORXER
+# define PIN_RMII0_RXER (GPIO_PULLDOWN | PIN_PORTA | PIN5)
+#else
+# define PIN_RMII0_RXER (PIN_ALT4 | PIN_PORTA | PIN5)
+#endif
+#define PIN_RMII0_TXD0 (PIN_ALT4 | PIN_PORTA | PIN16)
+#define PIN_RMII0_TXD1 (PIN_ALT4 | PIN_PORTA | PIN17)
+#define PIN_RMII0_TXEN (PIN_ALT4 | PIN_PORTA | PIN15)
+
+/* Real-Time Clock (RTC) */
+
+#define PIN_RTC_CLKOUT_1 (PIN_ALT6 | PIN_PORTE | PIN26)
+#define PIN_RTC_CLKOUT_2 (PIN_ALT7 | PIN_PORTE | PIN0)
+
+/* Secured digital host controller (SDHC) */
+
+#define PIN_SDHC0_CLKIN (PIN_ALT4 | PIN_PORTD | PIN11)
+#define PIN_SDHC0_CMD (PIN_ALT4 | PIN_PORTE | PIN3)
+#define PIN_SDHC0_D0 (PIN_ALT4 | PIN_PORTE | PIN1)
+#define PIN_SDHC0_D1 (PIN_ALT4 | PIN_PORTE | PIN0)
+#define PIN_SDHC0_D2 (PIN_ALT4 | PIN_PORTE | PIN5)
+#define PIN_SDHC0_D3 (PIN_ALT4 | PIN_PORTE | PIN4)
+#define PIN_SDHC0_D4 (PIN_ALT4 | PIN_PORTD | PIN12)
+#define PIN_SDHC0_D5 (PIN_ALT4 | PIN_PORTD | PIN13)
+#define PIN_SDHC0_D6 (PIN_ALT4 | PIN_PORTD | PIN14)
+#define PIN_SDHC0_D7 (PIN_ALT4 | PIN_PORTD | PIN15)
+#define PIN_SDHC0_DCLK (PIN_ALT4 | PIN_PORTE | PIN2)
+
+/* SPI */
+
+#define PIN_SPI0_PCS0_1 (PIN_ALT2 | PIN_PORTA | PIN14)
+#define PIN_SPI0_PCS0_2 (PIN_ALT2 | PIN_PORTC | PIN4)
+#define PIN_SPI0_PCS0_3 (PIN_ALT2 | PIN_PORTD | PIN0)
+#define PIN_SPI0_PCS1_1 (PIN_ALT2 | PIN_PORTC | PIN3)
+#define PIN_SPI0_PCS1_2 (PIN_ALT2 | PIN_PORTD | PIN4)
+#define PIN_SPI0_PCS2_1 (PIN_ALT2 | PIN_PORTC | PIN2)
+#define PIN_SPI0_PCS2_3 (PIN_ALT2 | PIN_PORTD | PIN5)
+#define PIN_SPI0_PCS3_1 (PIN_ALT2 | PIN_PORTC | PIN1)
+#define PIN_SPI0_PCS3_2 (PIN_ALT2 | PIN_PORTD | PIN6)
+#define PIN_SPI0_PCS4 (PIN_ALT2 | PIN_PORTC | PIN0)
+#define PIN_SPI0_PCS5 (PIN_ALT3 | PIN_PORTB | PIN23)
+#define PIN_SPI0_SCK_1 (PIN_ALT2 | PIN_PORTA | PIN15)
+#define PIN_SPI0_SCK_2 (PIN_ALT2 | PIN_PORTC | PIN5)
+#define PIN_SPI0_SCK_3 (PIN_ALT2 | PIN_PORTD | PIN1)
+#define PIN_SPI0_SIN_1 (PIN_ALT2 | PIN_PORTA | PIN17)
+#define PIN_SPI0_SIN_2 (PIN_ALT2 | PIN_PORTC | PIN7)
+#define PIN_SPI0_SIN_3 (PIN_ALT2 | PIN_PORTD | PIN3)
+#define PIN_SPI0_SOUT_1 (PIN_ALT2 | PIN_PORTA | PIN16)
+#define PIN_SPI0_SOUT_2 (PIN_ALT2 | PIN_PORTC | PIN6)
+#define PIN_SPI0_SOUT_3 (PIN_ALT2 | PIN_PORTD | PIN2)
+
+#define PIN_SPI1_PCS0_1 (PIN_ALT2 | PIN_PORTB | PIN10)
+#define PIN_SPI1_PCS0_2 (PIN_ALT2 | PIN_PORTE | PIN4)
+#define PIN_SPI1_PCS0_3 (PIN_ALT7 | PIN_PORTD | PIN4)
+#define PIN_SPI1_PCS1_1 (PIN_ALT2 | PIN_PORTB | PIN9)
+#define PIN_SPI1_PCS1_2 (PIN_ALT2 | PIN_PORTE | PIN0)
+#define PIN_SPI1_PCS2 (PIN_ALT2 | PIN_PORTE | PIN5)
+#define PIN_SPI1_PCS3 (PIN_ALT2 | PIN_PORTE | PIN6)
+#define PIN_SPI1_SCK_1 (PIN_ALT2 | PIN_PORTB | PIN11)
+#define PIN_SPI1_SCK_2 (PIN_ALT2 | PIN_PORTE | PIN2)
+#define PIN_SPI1_SCK_3 (PIN_ALT7 | PIN_PORTD | PIN5)
+#define PIN_SPI1_SIN_1 (PIN_ALT2 | PIN_PORTB | PIN17)
+#define PIN_SPI1_SIN_2 (PIN_ALT2 | PIN_PORTE | PIN3)
+#define PIN_SPI1_SIN_3 (PIN_ALT7 | PIN_PORTD | PIN7)
+#define PIN_SPI1_SIN_4 (PIN_ALT7 | PIN_PORTE | PIN1)
+#define PIN_SPI1_SOUT_1 (PIN_ALT2 | PIN_PORTB | PIN16)
+#define PIN_SPI1_SOUT_2 (PIN_ALT2 | PIN_PORTE | PIN1)
+#define PIN_SPI1_SOUT_3 (PIN_ALT7 | PIN_PORTD | PIN6)
+#define PIN_SPI1_SOUT_4 (PIN_ALT7 | PIN_PORTE | PIN3)
+
+#define PIN_SPI2_PCS0_1 (PIN_ALT2 | PIN_PORTB | PIN20)
+#define PIN_SPI2_PCS0_2 (PIN_ALT2 | PIN_PORTD | PIN11)
+#define PIN_SPI2_PCS1 (PIN_ALT2 | PIN_PORTD | PIN15)
+#define PIN_SPI2_SCK_1 (PIN_ALT2 | PIN_PORTB | PIN21)
+#define PIN_SPI2_SCK_2 (PIN_ALT2 | PIN_PORTD | PIN12)
+#define PIN_SPI2_SIN_1 (PIN_ALT2 | PIN_PORTB | PIN23)
+#define PIN_SPI2_SIN_2 (PIN_ALT2 | PIN_PORTD | PIN14)
+#define PIN_SPI2_SOUT_1 (PIN_ALT2 | PIN_PORTB | PIN22)
+#define PIN_SPI2_SOUT_2 (PIN_ALT2 | PIN_PORTD | PIN13)
+
+/* SWD */
+
+#define PIN_SWD_CLK (PIN_ALT7 | PIN_PORTA | PIN0)
+#define PIN_SWD_DIO (PIN_ALT7 | PIN_PORTA | PIN3)
+
+/* Trace */
+
+#define PIN_TRACE_CLKOUT_1 (PIN_ALT5 | PIN_PORTE | PIN0)
+#define PIN_TRACE_CLKOUT_2 (PIN_ALT7 | PIN_PORTA | PIN6)
+#define PIN_TRACE_D0_1 (PIN_ALT5 | PIN_PORTE | PIN4)
+#define PIN_TRACE_D0_2 (PIN_ALT7 | PIN_PORTA | PIN10)
+#define PIN_TRACE_D1_1 (PIN_ALT5 | PIN_PORTE | PIN3)
+#define PIN_TRACE_D1_2 (PIN_ALT7 | PIN_PORTA | PIN9)
+#define PIN_TRACE_D2_1 (PIN_ALT5 | PIN_PORTE | PIN2)
+#define PIN_TRACE_D2_2 (PIN_ALT7 | PIN_PORTA | PIN8)
+#define PIN_TRACE_D3_1 (PIN_ALT5 | PIN_PORTE | PIN1)
+#define PIN_TRACE_D3_2 (PIN_ALT7 | PIN_PORTA | PIN7)
+#define PIN_TRACE_SWO (PIN_ALT7 | PIN_PORTA | PIN2)
+
+/* UARTs */
+
+#define PIN_UART0_COL_1 (PIN_ALT2 | PIN_PORTA | PIN0)
+#define PIN_UART0_COL_2 (PIN_ALT3 | PIN_PORTA | PIN16)
+#define PIN_UART0_COL_3 (PIN_ALT3 | PIN_PORTB | PIN3)
+#define PIN_UART0_COL_4 (PIN_ALT3 | PIN_PORTD | PIN5)
+#define PIN_UART0_CTS_1 (PIN_ALT2 | PIN_PORTA | PIN0)
+#define PIN_UART0_CTS_2 (PIN_ALT3 | PIN_PORTA | PIN16)
+#define PIN_UART0_CTS_3 (PIN_ALT3 | PIN_PORTB | PIN3)
+#define PIN_UART0_CTS_4 (PIN_ALT3 | PIN_PORTD | PIN5)
+#define PIN_UART0_RTS_1 (PIN_ALT2 | PIN_PORTA | PIN3)
+#define PIN_UART0_RTS_2 (PIN_ALT3 | PIN_PORTA | PIN17)
+#define PIN_UART0_RTS_3 (PIN_ALT3 | PIN_PORTB | PIN2)
+#define PIN_UART0_RTS_4 (PIN_ALT3 | PIN_PORTD | PIN4)
+#define PIN_UART0_RX_1 (PIN_ALT2 | PIN_PORTA | PIN1)
+#define PIN_UART0_RX_2 (PIN_ALT3 | PIN_PORTA | PIN15)
+#define PIN_UART0_RX_3 (PIN_ALT3 | PIN_PORTB | PIN16)
+#define PIN_UART0_RX_4 (PIN_ALT3 | PIN_PORTD | PIN6)
+#define PIN_UART0_TX_1 (PIN_ALT2 | PIN_PORTA | PIN2)
+#define PIN_UART0_TX_2 (PIN_ALT3 | PIN_PORTA | PIN14)
+#define PIN_UART0_TX_3 (PIN_ALT3 | PIN_PORTB | PIN17)
+#define PIN_UART0_TX_4 (PIN_ALT3 | PIN_PORTD | PIN7)
+
+#define PIN_UART1_CTS_1 (PIN_ALT3 | PIN_PORTC | PIN2)
+#define PIN_UART1_CTS_2 (PIN_ALT3 | PIN_PORTE | PIN2)
+#define PIN_UART1_RTS_1 (PIN_ALT3 | PIN_PORTC | PIN1)
+#define PIN_UART1_RTS_2 (PIN_ALT3 | PIN_PORTE | PIN3)
+#define PIN_UART1_RX_1 (PIN_ALT3 | PIN_PORTC | PIN3)
+#define PIN_UART1_RX_2 (PIN_ALT3 | PIN_PORTE | PIN1)
+#define PIN_UART1_TX_1 (PIN_ALT3 | PIN_PORTC | PIN4)
+#define PIN_UART1_TX_2 (PIN_ALT3 | PIN_PORTE | PIN0)
+
+#define PIN_UART2_CTS (PIN_ALT3 | PIN_PORTD | PIN1)
+#define PIN_UART2_RTS (PIN_ALT3 | PIN_PORTD | PIN0)
+#define PIN_UART2_RX (PIN_ALT3 | PIN_PORTD | PIN2)
+#define PIN_UART2_TX (PIN_ALT3 | PIN_PORTD | PIN3)
+
+#define PIN_UART3_CTS_1 (PIN_ALT2 | PIN_PORTB | PIN13)
+#define PIN_UART3_CTS_2 (PIN_ALT3 | PIN_PORTB | PIN9)
+#define PIN_UART3_CTS_3 (PIN_ALT3 | PIN_PORTC | PIN19)
+#define PIN_UART3_CTS_4 (PIN_ALT3 | PIN_PORTE | PIN6)
+#define PIN_UART3_RTS_1 (PIN_ALT2 | PIN_PORTB | PIN12)
+#define PIN_UART3_RTS_2 (PIN_ALT3 | PIN_PORTB | PIN8)
+#define PIN_UART3_RTS_3 (PIN_ALT3 | PIN_PORTC | PIN18)
+#define PIN_UART3_RTS_4 (PIN_ALT3 | PIN_PORTE | PIN7)
+#define PIN_UART3_RX_1 (PIN_ALT3 | PIN_PORTB | PIN10)
+#define PIN_UART3_RX_2 (PIN_ALT3 | PIN_PORTC | PIN16)
+#define PIN_UART3_RX_3 (PIN_ALT3 | PIN_PORTE | PIN5)
+#define PIN_UART3_TX_1 (PIN_ALT3 | PIN_PORTB | PIN11)
+#define PIN_UART3_TX_2 (PIN_ALT3 | PIN_PORTC | PIN17)
+#define PIN_UART3_TX_3 (PIN_ALT3 | PIN_PORTE | PIN4)
+
+#define PIN_UART4_CTS_1 (PIN_ALT3 | PIN_PORTC | PIN13)
+#define PIN_UART4_CTS_2 (PIN_ALT3 | PIN_PORTE | PIN26)
+#define PIN_UART4_RTS_1 (PIN_ALT3 | PIN_PORTC | PIN12)
+#define PIN_UART4_RTS_2 (PIN_ALT3 | PIN_PORTE | PIN27)
+#define PIN_UART4_RX_1 (PIN_ALT3 | PIN_PORTC | PIN14)
+#define PIN_UART4_RX_2 (PIN_ALT3 | PIN_PORTE | PIN25)
+#define PIN_UART4_TX_1 (PIN_ALT3 | PIN_PORTC | PIN15)
+#define PIN_UART4_TX_2 (PIN_ALT3 | PIN_PORTE | PIN24)
+
+#define PIN_UART5_CTS_1 (PIN_ALT3 | PIN_PORTD | PIN11)
+#define PIN_UART5_CTS_2 (PIN_ALT3 | PIN_PORTE | PIN10)
+#define PIN_UART5_RTS_1 (PIN_ALT3 | PIN_PORTD | PIN10)
+#define PIN_UART5_RTS_2 (PIN_ALT3 | PIN_PORTE | PIN11)
+#define PIN_UART5_RX_1 (PIN_ALT3 | PIN_PORTD | PIN8)
+#define PIN_UART5_RX_2 (PIN_ALT3 | PIN_PORTE | PIN9)
+#define PIN_UART5_TX_1 (PIN_ALT3 | PIN_PORTD | PIN9)
+#define PIN_UART5_TX_2 (PIN_ALT3 | PIN_PORTE | PIN8)
+
+/* USB */
+
+#define PIN_USB_CLKIN_1 (PIN_ALT2 | PIN_PORTA | PIN5)
+#define PIN_USB_CLKIN_2 (PIN_ALT7 | PIN_PORTE | PIN26)
+#define PIN_USB_SOF_OUT_1 (PIN_ALT3 | PIN_PORTC | PIN7)
+#define PIN_USB_SOF_OUT_2 (PIN_ALT4 | PIN_PORTC | PIN0)
+#define PIN_USB_SOF_OUT_3 (PIN_ALT7 | PIN_PORTE | PIN6)
+
+/* External Crystal */
+
+#define PIN_EXTAL0 (PIN_ANALOG | PIN_PORTA | PIN18)
+#define PIN_XTAL0 (PIN_ANALOG | PIN_PORTA | PIN19)
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+#endif /* KINETIS_K64 */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHP_KINETIS_K64PINMUX_H */
diff --git a/arch/arm/src/kinetis/kinetis_llwu.h b/arch/arm/src/kinetis/chip/kinetis_llwu.h
similarity index 98%
rename from arch/arm/src/kinetis/kinetis_llwu.h
rename to arch/arm/src/kinetis/chip/kinetis_llwu.h
index 4324a76251b412e0a542816025f408c85514f8a2..ae5c6c8b04c1edf2e7031037505af25869e55b51 100644
--- a/arch/arm/src/kinetis/kinetis_llwu.h
+++ b/arch/arm/src/kinetis/chip/kinetis_llwu.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_llwu.h
+ * arch/arm/src/kinetis/chip/kinetis_llwu.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_LLWU_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_LLWU_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LLWU_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LLWU_H
/************************************************************************************
* Included Files
@@ -249,4 +249,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_LLWU_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LLWU_H */
diff --git a/arch/arm/src/kinetis/kinetis_lptmr.h b/arch/arm/src/kinetis/chip/kinetis_lptmr.h
similarity index 96%
rename from arch/arm/src/kinetis/kinetis_lptmr.h
rename to arch/arm/src/kinetis/chip/kinetis_lptmr.h
index 863b24108eacec47e4808534cc2a7e93ff602132..15aeb4a5614c386f5a78b8a8c321ca6acf139fce 100644
--- a/arch/arm/src/kinetis/kinetis_lptmr.h
+++ b/arch/arm/src/kinetis/chip/kinetis_lptmr.h
@@ -1,7 +1,7 @@
/****************************************************************************************************
- * arch/arm/src/kinetis/kinetis_lptmr.h
+ * arch/arm/src/kinetis/chip/kinetis_lptmr.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
****************************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_LPTMR_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_LPTMR_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPTMR_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPTMR_H
/****************************************************************************************************
* Included Files
@@ -130,4 +130,4 @@
* Public Functions
****************************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_LPTMR_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPTMR_H */
diff --git a/arch/arm/src/kinetis/kinetis_mcg.h b/arch/arm/src/kinetis/chip/kinetis_mcg.h
similarity index 92%
rename from arch/arm/src/kinetis/kinetis_mcg.h
rename to arch/arm/src/kinetis/chip/kinetis_mcg.h
index 60f13cd2a0b788ef8e897b0c9adbeee28387aae0..fe8dccc60e1d8419634d008d9af9aa184c32bbe7 100644
--- a/arch/arm/src/kinetis/kinetis_mcg.h
+++ b/arch/arm/src/kinetis/chip/kinetis_mcg.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_mcg.h
+ * arch/arm/src/kinetis/chip/kinetis_mcg.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MCG_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_MCG_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCG_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCG_H
/************************************************************************************
* Included Files
@@ -60,6 +60,10 @@
#define KINETIS_MCG_ATC_OFFSET 0x0008 /* MCG Auto Trim Control Register */
#define KINETIS_MCG_ATCVH_OFFSET 0x000a /* MCG Auto Trim Compare Value High Register */
#define KINETIS_MCG_ATCVL_OFFSET 0x000b /* MCG Auto Trim Compare Value Low Register */
+#ifdef KINETIS_K64
+# define KINETIS_MCG_C7_OFFSET 0x000c /* MCG Control 7 Register */
+# define KINETIS_MCG_C8_OFFSET 0x000d /* MCG Control 8 Register */
+#endif
/* Register Addresses ***************************************************************/
@@ -73,6 +77,10 @@
#define KINETIS_MCG_ATC (KINETIS_MCG_BASE+KINETIS_MCG_ATC_OFFSET)
#define KINETIS_MCG_ATCVH (KINETIS_MCG_BASE+KINETIS_MCG_ATCVH_OFFSET)
#define KINETIS_MCG_ATCVL (KINETIS_MCG_BASE+KINETIS_MCG_ATCVL_OFFSET)
+#ifdef KINETIS_K64
+# define KINETIS_MCG_C7 (KINETIS_MCG_BASE+KINETIS_MCG_C7_OFFSET)
+# define KINETIS_MCG_C8 (KINETIS_MCG_BASE+KINETIS_MCG_C8_OFFSET)
+#endif
/* Register Bit Definitions *********************************************************/
@@ -134,7 +142,7 @@
#define MCG_C5_PRDIV_SHIFT (0) /* Bits 0-4: PLL External Reference Divider */
#define MCG_C5_PRDIV_MASK (31 << MCG_C5_PRDIV_SHIFT)
-# define MCG_C5_PRDIV(n) (((n)-1) << MCG_C5_PRDIV_SHIFT) /* Divide factor n=1..25 */
+# define MCG_C5_PRDIV(n) ((uint32_t)((n)-1) << MCG_C5_PRDIV_SHIFT) /* n=1..25 */
#define MCG_C5_PLLSTEN (1 << 5) /* Bit 5: PLL Stop Enable */
#define MCG_C5_PLLCLKEN (1 << 6) /* Bit 6: PLL Clock Enable */
/* Bit 7: Reserved */
@@ -143,7 +151,7 @@
#define MCG_C6_VDIV_SHIFT (0) /* Bits 0-4: VCO Divider */
#define MCG_C6_VDIV_MASK (31 << MCG_C6_VDIV_SHIFT)
-# define MCG_C6_VDIV(n) (((n)-24) << MCG_C6_VDIV_SHIFT) /* Divide factor n=24..55 */
+# define MCG_C6_VDIV(n) ((uint32_t)((n)-24) << MCG_C6_VDIV_SHIFT) /* n=24..55 */
#define MCG_C6_CME (1 << 5) /* Bit 5: Clock Monitor Enable */
#define MCG_C6_PLLS (1 << 6) /* Bit 6: PLL Select */
#define MCG_C6_LOLIE (1 << 7) /* Bit 7: Loss of Lock Interrrupt Enable */
@@ -171,6 +179,10 @@
/* MCG Auto Trim Compare Value High/Low Registers (8-bit compare value) */
+/* MCG Control 7 Register */
+
+/* MCG Control 8 Register */
+
/************************************************************************************
* Public Types
************************************************************************************/
@@ -183,4 +195,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_MCG_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCG_H */
diff --git a/arch/arm/src/kinetis/kinetis_mcm.h b/arch/arm/src/kinetis/chip/kinetis_mcm.h
similarity index 94%
rename from arch/arm/src/kinetis/kinetis_mcm.h
rename to arch/arm/src/kinetis/chip/kinetis_mcm.h
index d899b77027ac135150314bfaf214ef3cc7ba6c29..f46305056ef84f13d7cc8766a0ecfdaf26c45f9e 100644
--- a/arch/arm/src/kinetis/kinetis_mcm.h
+++ b/arch/arm/src/kinetis/chip/kinetis_mcm.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_mcm.h
+ * arch/arm/src/kinetis/chip/kinetis_mcm.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MCM_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_MCM_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCM_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCM_H
/************************************************************************************
* Included Files
@@ -57,6 +57,9 @@
#define KINETIS_MCM_ETBCC_OFFSET 0x0014 /* ETB counter control register */
#define KINETIS_MCM_ETBRL_OFFSET 0x0018 /* ETB reload register */
#define KINETIS_MCM_ETBCNT_OFFSET 0x001c /* ETB counter value register */
+#ifdef KINETIS_K64
+# define KINETIS_MCM_PID_OFFSET 0x0030 /* Process ID register */
+#endif
/* Register Addresses ***************************************************************/
@@ -67,6 +70,9 @@
#define KINETIS_MCM_ETBCC (KINETIS_MCM_BASE+KINETIS_MCM_ETBCC_OFFSET)
#define KINETIS_MCM_ETBRL (KINETIS_MCM_BASE+KINETIS_MCM_ETBRL_OFFSET)
#define KINETIS_MCM_ETBCNT (KINETIS_MCM_BASE+KINETIS_MCM_ETBCNT_OFFSET)
+#ifdef KINETIS_K64
+# define KINETIS_MCM_PID (KINETIS_MCM_BASE+KINETIS_MCM_PID_OFFSET)
+#endif
/* Register Bit Definitions *********************************************************/
@@ -148,4 +154,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_MCM_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCM_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_memorymap.h b/arch/arm/src/kinetis/chip/kinetis_memorymap.h
new file mode 100644
index 0000000000000000000000000000000000000000..ec67d42820dc8cbea8c1a60409314365a3a28c06
--- /dev/null
+++ b/arch/arm/src/kinetis/chip/kinetis_memorymap.h
@@ -0,0 +1,79 @@
+/********************************************************************************************
+ * arch/arm/src/kinetis/chip/kinetis_memorymap.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MEMORYMAP_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MEMORYMAP_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+/* This file is just a wrapper around pin muxing header files for the Kinetis family selected
+ * by the logic in chip.h.
+ */
+
+#if defined(KINETIS_K20)
+# include "chip/kinetis_k20memorymap.h"
+#elif defined(KINETIS_K40)
+# include "chip/kinetis_k40memorymap.h"
+#elif defined(KINETIS_K60)
+# include "chip/kinetis_k60memorymap.h"
+#elif defined(KINETIS_K64)
+# include "chip/kinetis_k64memorymap.h"
+#else
+# error "No memory map for this Kinetis part"
+#endif
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MEMORYMAP_H */
diff --git a/arch/arm/src/kinetis/kinetis_mmcau.h b/arch/arm/src/kinetis/chip/kinetis_mmcau.h
similarity index 89%
rename from arch/arm/src/kinetis/kinetis_mmcau.h
rename to arch/arm/src/kinetis/chip/kinetis_mmcau.h
index 7468a1d0bfe3b3563918e57adf8a99bdfb0aed86..90c9cf6552cdf60eafd0b00f4d924d3aac2f2326 100644
--- a/arch/arm/src/kinetis/kinetis_mmcau.h
+++ b/arch/arm/src/kinetis/chip/kinetis_mmcau.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_mmcau.h
+ * arch/arm/src/kinetis/chip/kinetis_mmcau.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MMCAU_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_MMCAU_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MMCAU_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MMCAU_H
/************************************************************************************
* Included Files
@@ -61,9 +61,11 @@
#define KINETIS_CAU_CA3_OFFSET 0x0005 /* General Purpose Register 3 */
#define KINETIS_CAU_CA4_OFFSET 0x0006 /* General Purpose Register 4 */
#define KINETIS_CAU_CA5_OFFSET 0x0007 /* General Purpose Register 5 */
-#define KINETIS_CAU_CA6_OFFSET 0x0008 /* General Purpose Register 6 */
-#define KINETIS_CAU_CA7_OFFSET 0x0009 /* General Purpose Register 7 */
-#define KINETIS_CAU_CA8_OFFSET 0x000a /* General Purpose Register 8 */
+#ifndef KINETIS_K64
+# define KINETIS_CAU_CA6_OFFSET 0x0008 /* General Purpose Register 6 */
+# define KINETIS_CAU_CA7_OFFSET 0x0009 /* General Purpose Register 7 */
+# define KINETIS_CAU_CA8_OFFSET 0x000a /* General Purpose Register 8 */
+#endif
/* Register Addresses ***************************************************************/
@@ -77,9 +79,11 @@
#define KINETIS_CAU_CA3 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA3_OFFSET)
#define KINETIS_CAU_CA4 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA4_OFFSET)
#define KINETIS_CAU_CA5 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA5_OFFSET)
-#define KINETIS_CAU_CA6 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA6_OFFSET)
-#define KINETIS_CAU_CA7 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA7_OFFSET)
-#define KINETIS_CAU_CA8 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA8_OFFSET)
+#ifndef KINETIS_K64
+# define KINETIS_CAU_CA6 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA6_OFFSET)
+# define KINETIS_CAU_CA7 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA7_OFFSET)
+# define KINETIS_CAU_CA8 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA8_OFFSET)
+#endif
/* Register Bit Definitions *********************************************************/
@@ -135,4 +139,4 @@
************************************************************************************/
#endif /* KINETIS_NMMCAU && KINETIS_NMMCAU > 0 */
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_MMCAU_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MMCAU_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_mpu.h b/arch/arm/src/kinetis/chip/kinetis_mpu.h
new file mode 100644
index 0000000000000000000000000000000000000000..1faa605d75bc91be58b7425930549c7facd947d6
--- /dev/null
+++ b/arch/arm/src/kinetis/chip/kinetis_mpu.h
@@ -0,0 +1,75 @@
+/********************************************************************************************
+ * arch/arm/src/kinetis/chip/kinetis_mpu.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MPU_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MPU_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+/* This file is just a wrapper around pin muxing header files for the Kinetis family selected
+ * by the logic in chip.h.
+ */
+
+#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K60)
+# include "chip/kinetis_k20k40k60mpu.h"
+#elif defined(KINETIS_K64)
+# include "chip/kinetis_k64mpu.h"
+#else
+# error "No MPU definitions for this Kinetis part"
+#endif
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MPU_H */
diff --git a/arch/arm/src/kinetis/kinetis_osc.h b/arch/arm/src/kinetis/chip/kinetis_osc.h
similarity index 93%
rename from arch/arm/src/kinetis/kinetis_osc.h
rename to arch/arm/src/kinetis/chip/kinetis_osc.h
index 16efcf328266055cf0ac411838a8b948dd520f93..69a7b8a30c8cabb5d7fd8ea17946893363f1437e 100644
--- a/arch/arm/src/kinetis/kinetis_osc.h
+++ b/arch/arm/src/kinetis/chip/kinetis_osc.h
@@ -1,7 +1,7 @@
/********************************************************************************************
- * arch/arm/src/kinetis/kinetis_osc.h
+ * arch/arm/src/kinetis/chip/kinetis_osc.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
********************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_OSC_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_OSC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIHP_KINETIS_OSC_H
+#define __ARCH_ARM_SRC_KINETIS_CHIHP_KINETIS_OSC_H
/********************************************************************************************
* Included Files
@@ -81,4 +81,4 @@
* Public Functions
********************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_OSC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIHP_KINETIS_OSC_H */
diff --git a/arch/arm/src/kinetis/kinetis_pdb.h b/arch/arm/src/kinetis/chip/kinetis_pdb.h
similarity index 95%
rename from arch/arm/src/kinetis/kinetis_pdb.h
rename to arch/arm/src/kinetis/chip/kinetis_pdb.h
index 9cfab9b99f187b3dbe0440f2c486d32c84784ce5..d0238240dfabe07583762fbc2a77cc1d94fbb4bd 100644
--- a/arch/arm/src/kinetis/kinetis_pdb.h
+++ b/arch/arm/src/kinetis/chip/kinetis_pdb.h
@@ -1,7 +1,7 @@
/********************************************************************************************
- * arch/arm/src/kinetis/kinetis_pdb.h
+ * arch/arm/src/kinetis/chip/kinetis_pdb.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
********************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_PDB_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_PDB_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PDB_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PDB_H
/********************************************************************************************
* Included Files
@@ -83,6 +83,10 @@
#define KINETIS_PDB_PO0EN_OFFSET 0x0190 /* Pulse-Out 0 Enable Register */
#define KINETIS_PDB_PO0DLY_OFFSET 0x0194 /* Pulse-Out 0 Delay Register */
+#ifdef KINETIS_K64
+# define KINETIS_PDB_PO1DLY_OFFSET 0x0198 /* Pulse-Out 1 Delay Register */
+# define KINETIS_PDB_PO2DLY_OFFSET 0x019c /* Pulse-Out 2 Delay Register */
+#endif
/* Register Addresses ***********************************************************************/
@@ -119,6 +123,10 @@
#define KINETIS_PDB0_PO0EN (KINETIS_PDB0_BASE+KINETIS_PDB_PO0EN_OFFSET)
#define KINETIS_PDB0_PO0DLY (KINETIS_PDB0_BASE+KINETIS_PDB_PO0DLY_OFFSET)
+#ifdef KINETIS_K64
+# define KINETIS_PDB0_PO1DLY (KINETIS_PDB0_BASE+KINETIS_PDB_PO1DLY_OFFSET)
+# define KINETIS_PDB0_PO2DLY (KINETIS_PDB0_BASE+KINETIS_PDB_PO2DLY_OFFSET)
+#endif
/* Register Bit Definitions *****************************************************************/
@@ -252,4 +260,4 @@
* Public Functions
********************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_PDB_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PDB_H */
diff --git a/arch/arm/src/kinetis/kinetis_pinmux.h b/arch/arm/src/kinetis/chip/kinetis_pinmux.h
similarity index 87%
rename from arch/arm/src/kinetis/kinetis_pinmux.h
rename to arch/arm/src/kinetis/chip/kinetis_pinmux.h
index 589184ffdd2ceb507fa865da22fd9f0b37d54bb0..0a6aeb82532b8c506b5aa07c4434d36d2683748b 100644
--- a/arch/arm/src/kinetis/kinetis_pinmux.h
+++ b/arch/arm/src/kinetis/chip/kinetis_pinmux.h
@@ -1,7 +1,7 @@
/********************************************************************************************
- * arch/arm/src/kinetis/kinetis_pinmux.h
+ * arch/arm/src/kinetis/chip/kinetis_pinmux.h
*
- * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
********************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_PINMUX_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_PINMUX_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PINMUX_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PINMUX_H
/********************************************************************************************
* Included Files
@@ -49,11 +49,13 @@
*/
#if defined(KINETIS_K20)
-# include "kinetis_k20pinmux.h"
+# include "chip/kinetis_k20pinmux.h"
#elif defined(KINETIS_K40)
-# include "kinetis_k40pinmux.h"
+# include "chip/kinetis_k40pinmux.h"
#elif defined(KINETIS_K60)
-# include "kinetis_k60pinmux.h"
+# include "chip/kinetis_k60pinmux.h"
+#elif defined(KINETIS_K64)
+# include "chip/kinetis_k64pinmux.h"
#else
# error "No pin multiplexing for this Kinetis part"
#endif
@@ -74,4 +76,4 @@
* Public Functions
********************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_PINMUX_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PINMUX_H */
diff --git a/arch/arm/src/kinetis/kinetis_pit.h b/arch/arm/src/kinetis/chip/kinetis_pit.h
similarity index 96%
rename from arch/arm/src/kinetis/kinetis_pit.h
rename to arch/arm/src/kinetis/chip/kinetis_pit.h
index 808508f8fedd17be9e6af540338c248095be02fc..26cd6caea6dd16ed146060852473da3708811cb9 100644
--- a/arch/arm/src/kinetis/kinetis_pit.h
+++ b/arch/arm/src/kinetis/chip/kinetis_pit.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_pit.h
+ * arch/arm/src/kinetis/chip/kinetis_pit.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_PIT_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_PIT_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PIT_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PIT_H
/************************************************************************************
* Included Files
@@ -121,4 +121,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_PIT_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PIT_H */
diff --git a/arch/arm/src/kinetis/kinetis_pmc.h b/arch/arm/src/kinetis/chip/kinetis_pmc.h
similarity index 95%
rename from arch/arm/src/kinetis/kinetis_pmc.h
rename to arch/arm/src/kinetis/chip/kinetis_pmc.h
index 065847da3d5a6f5bc702e8f7f44b8b1d7273ccad..c0ffe575b3615a691239db95ba764631c63dd686 100644
--- a/arch/arm/src/kinetis/kinetis_pmc.h
+++ b/arch/arm/src/kinetis/chip/kinetis_pmc.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_pmc.h
+ * arch/arm/src/kinetis/chip/kinetis_pmc.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_PMC_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_PMC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PMC_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PMC_H
/************************************************************************************
* Included Files
@@ -108,4 +108,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_PMC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PMC_H */
diff --git a/arch/arm/src/kinetis/kinetis_port.h b/arch/arm/src/kinetis/chip/kinetis_port.h
similarity index 99%
rename from arch/arm/src/kinetis/kinetis_port.h
rename to arch/arm/src/kinetis/chip/kinetis_port.h
index 5a568537b01ed8845c61eaa891734226a191ca2d..36dfa4e0983aed0df88034a7acebace36d123ad2 100644
--- a/arch/arm/src/kinetis/kinetis_port.h
+++ b/arch/arm/src/kinetis/chip/kinetis_port.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_port.h
+ * arch/arm/src/kinetis/chip/kinetis_port.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_PORT_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_PORT_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PORT_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PORT_H
/************************************************************************************
* Included Files
@@ -426,4 +426,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_PORT_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PORT_H */
diff --git a/arch/arm/src/kinetis/kinetis_rngb.h b/arch/arm/src/kinetis/chip/kinetis_rngb.h
similarity index 97%
rename from arch/arm/src/kinetis/kinetis_rngb.h
rename to arch/arm/src/kinetis/chip/kinetis_rngb.h
index a4f677555030cd5be5f25fd5898407986aeeb40e..1e005c08ae30a1b2a95b7991a7b42bf38ff1da8a 100644
--- a/arch/arm/src/kinetis/kinetis_rngb.h
+++ b/arch/arm/src/kinetis/chip/kinetis_rngb.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_rngb.h
+ * arch/arm/src/kinetis/chip/kinetis_rngb.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_RNGB_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_RNGB_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RNGB_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RNGB_H
/************************************************************************************
* Included Files
@@ -158,4 +158,4 @@
************************************************************************************/
#endif /* KINETIS_NRNG && KINETIS_NRNG > 0 */
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_RNGB_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RNGB_H */
diff --git a/arch/arm/src/kinetis/kinetis_rtc.h b/arch/arm/src/kinetis/chip/kinetis_rtc.h
similarity index 94%
rename from arch/arm/src/kinetis/kinetis_rtc.h
rename to arch/arm/src/kinetis/chip/kinetis_rtc.h
index 69c097a7c950627992f577b40e61cede1480ccf4..948c6ce87719dc21176d860fcf13fdec5270bc0b 100644
--- a/arch/arm/src/kinetis/kinetis_rtc.h
+++ b/arch/arm/src/kinetis/chip/kinetis_rtc.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_rtc.h
+ * arch/arm/src/kinetis/chip/kinetis_rtc.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_RTC_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_RTC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RTC_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RTC_H
/************************************************************************************
* Included Files
@@ -59,7 +59,7 @@
#define KINETIS_RTC_CR_OFFSET 0x0010 /* RTC Control Register */
#define KINETIS_RTC_SR_OFFSET 0x0014 /* RTC Status Register */
#define KINETIS_RTC_LR_OFFSET 0x0018 /* RTC Lock Register */
-#ifdef KINETIS_K40
+#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K64)
# define KINETIS_RTC_IER_OFFSET 0x001c /* RTC Interrupt Enable Register (K40) */
#endif
#ifdef KINETIS_K60
@@ -77,7 +77,7 @@
#define KINETIS_RTC_CR (KINETIS_RTC_BASE+KINETIS_RTC_CR_OFFSET)
#define KINETIS_RTC_SR (KINETIS_RTC_BASE+KINETIS_RTC_SR_OFFSET)
#define KINETIS_RTC_LR (KINETIS_RTC_BASE+KINETIS_RTC_LR_OFFSET)
-#ifdef KINETIS_K40
+#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K64)
# define KINETIS_RTC_IER (KINETIS_RTC_BASE+KINETIS_RTC_IER_OFFSET)
#endif
#ifdef KINETIS_K60
@@ -135,13 +135,13 @@
#define RTC_LR_TCL (1 << 3) /* Bit 3: Time Compensation Lock */
#define RTC_LR_CRL (1 << 4) /* Bit 4: Control Register Lock */
#define RTC_LR_SRL (1 << 5) /* Bit 5: Status Register Lock */
-#ifdef KINETIS_K40
+#if defined(KINETIS_K20) || defined(KINETIS_K40)
# define RTC_LR_LRL (1 << 6) /* Bit 6: Lock Register Lock (K40) */
#endif
/* Bits 7-31: Reserved */
/* RTC Interrupt Enable Register (32-bits, K40) */
-#ifdef KINETIS_K40
+#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K64)
# define RTC_IER_TIIE (1 << 0) /* Bit 0: Time Invalid Interrupt Enable */
# define RTC_IER_TOIE (1 << 1) /* Bit 1: Time Overflow Interrupt Enable */
# define RTC_IER_TAIE (1 << 2) /* Bit 2: Time Alarm Interrupt Enable */
@@ -167,7 +167,7 @@
#define RTC_WAR_CRW (1 << 4) /* Bit 4: Control Register Write */
#define RTC_WAR_SRW (1 << 5) /* Bit 5: Status Register Write */
#define RTC_WAR_LRW (1 << 6) /* Bit 6: Lock Register Write */
-#ifdef KINETIS_K40
+#if defined(KINETIS_K40) || defined(KINETIS_K64)
# define RTC_WAR_IERW (1 << 7) /* Bit 7: Interrupt Enable Register Write */
#endif
#ifdef KINETIS_K60
@@ -183,7 +183,7 @@
#define RTC_RAR_CRR (1 << 4) /* Bit 4: Control Register Read */
#define RTC_RAR_SRR (1 << 5) /* Bit 5: Status Register Read */
#define RTC_RAR_LRR (1 << 6) /* Bit 6: Lock Register Read */
-#ifdef KINETIS_K40
+#if defined(KINETIS_K40) || defined(KINETIS_K64)
# define RTC_RAR_IERR (1 << 7) /* Bit 7: Interrupt Enable Register Read */
#endif
#ifdef KINETIS_K60
@@ -204,4 +204,4 @@
************************************************************************************/
#endif /* KINETIS_NRTC && KINETIS_NRTC > 0 */
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_RTC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RTC_H */
diff --git a/arch/arm/src/kinetis/kinetis_sdhc.h b/arch/arm/src/kinetis/chip/kinetis_sdhc.h
similarity index 99%
rename from arch/arm/src/kinetis/kinetis_sdhc.h
rename to arch/arm/src/kinetis/chip/kinetis_sdhc.h
index 5d122315a9d2efa426865fd396748ac3e0372434..b57b85c94e70e83d72f12e2e6101ca42c3c83c35 100644
--- a/arch/arm/src/kinetis/kinetis_sdhc.h
+++ b/arch/arm/src/kinetis/chip/kinetis_sdhc.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_sdhc.h
+ * arch/arm/src/kinetis/chip/kinetis_sdhc.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_SDHC_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_SDHC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SDHC_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SDHC_H
/************************************************************************************
* Included Files
@@ -385,4 +385,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_SDHC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SDHC_H */
diff --git a/arch/arm/src/kinetis/kinetis_sim.h b/arch/arm/src/kinetis/chip/kinetis_sim.h
similarity index 95%
rename from arch/arm/src/kinetis/kinetis_sim.h
rename to arch/arm/src/kinetis/chip/kinetis_sim.h
index aad17e923e80c2bc7513fba4ff707c3825e2d5a3..ae56504ff085ac1be8929e0275125f04b19a29c4 100644
--- a/arch/arm/src/kinetis/kinetis_sim.h
+++ b/arch/arm/src/kinetis/chip/kinetis_sim.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_sim.h
+ * arch/arm/src/kinetis/chip/kinetis_sim.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_SIM_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_SIM_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SIM_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SIM_H
/************************************************************************************
* Included Files
@@ -207,7 +207,7 @@
/* Bits 0-23: Reserved */
#define SIM_SOPT6_RSTFLTSEL_SHIFT (24) /* Bits 24-28: Reset pin filter select */
#define SIM_SOPT6_RSTFLTSEL_MASK (31 << SIM_SOPT6_RSTFLTSEL_SHIFT)
-# define SIM_SOPT6_RSTFLTSEL(n) (((n)-1) << SIM_SOPT6_RSTFLTSEL_SHIFT) /* Bux clock filter count n, n=1..32 */
+# define SIM_SOPT6_RSTFLTSEL(n) ((uint32_t)((n)-1) << SIM_SOPT6_RSTFLTSEL_SHIFT) /* n=1..32 */
#define SIM_SOPT6_RSTFLTEN_SHIFT (29) /* Bits 29-31: Reset pin filter enable */
#define SIM_SOPT6_RSTFLTEN_MASK (7 << SIM_SOPT6_RSTFLTEN_SHIFT)
#define SIM_SOPT6_RSTFLTEN_DISABLED (0 << SIM_SOPT6_RSTFLTEN_SHIFT) /* All filtering disabled */
@@ -385,7 +385,7 @@
/* Bits 0-15: Reserved */
#define SIM_CLKDIV1_OUTDIV4_SHIFT (16) /* Bits 16-19: Clock 4 output divider value */
#define SIM_CLKDIV1_OUTDIV4_MASK (15 << SIM_CLKDIV1_OUTDIV4_SHIFT)
-# define SIM_CLKDIV1_OUTDIV4(n) (((n)-1) << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by n, n=1..16 */
+# define SIM_CLKDIV1_OUTDIV4(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV4_SHIFT) /* n=1..16 */
# define SIM_CLKDIV1_OUTDIV4_1 (0 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 1 */
# define SIM_CLKDIV1_OUTDIV4_2 (1 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 2 */
# define SIM_CLKDIV1_OUTDIV4_3 (2 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 3 */
@@ -404,7 +404,7 @@
# define SIM_CLKDIV1_OUTDIV4_16 (15 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 16 */
#define SIM_CLKDIV1_OUTDIV3_SHIFT (20) /* Bits 20-23: Clock 3 output divider value */
#define SIM_CLKDIV1_OUTDIV3_MASK (15 << SIM_CLKDIV1_OUTDIV3_SHIFT)
-# define SIM_CLKDIV1_OUTDIV3(n) (((n)-1) << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by n, n=1..16 */
+# define SIM_CLKDIV1_OUTDIV3(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV3_SHIFT) /* n=1..16 */
# define SIM_CLKDIV1_OUTDIV3_1 (0 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 1 */
# define SIM_CLKDIV1_OUTDIV3_2 (1 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 2 */
# define SIM_CLKDIV1_OUTDIV3_3 (2 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 3 */
@@ -423,7 +423,7 @@
# define SIM_CLKDIV1_OUTDIV3_16 (15 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 16 */
#define SIM_CLKDIV1_OUTDIV2_SHIFT (24) /* Bits 24-27: Clock 2 output divider value */
#define SIM_CLKDIV1_OUTDIV2_MASK (15 << SIM_CLKDIV1_OUTDIV2_SHIFT)
-# define SIM_CLKDIV1_OUTDIV2(n) (((n)-1) << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by n, n=1..16 */
+# define SIM_CLKDIV1_OUTDIV2(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV2_SHIFT) /* n=1..16 */
# define SIM_CLKDIV1_OUTDIV2_1 (0 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 1 */
# define SIM_CLKDIV1_OUTDIV2_2 (1 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 2 */
# define SIM_CLKDIV1_OUTDIV2_3 (2 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 3 */
@@ -442,7 +442,7 @@
# define SIM_CLKDIV1_OUTDIV2_16 (15 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 16 */
#define SIM_CLKDIV1_OUTDIV1_SHIFT (28) /* Bits 28-31: Clock 1 output divider value */
#define SIM_CLKDIV1_OUTDIV1_MASK (15 << SIM_CLKDIV1_OUTDIV1_SHIFT)
-# define SIM_CLKDIV1_OUTDIV1(n) (((n)-1) << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by n, n=1..16 */
+# define SIM_CLKDIV1_OUTDIV1(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV1_SHIFT) /* n=1..16 */
# define SIM_CLKDIV1_OUTDIV1_1 (0 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 1 */
# define SIM_CLKDIV1_OUTDIV1_2 (1 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 2 */
# define SIM_CLKDIV1_OUTDIV1_3 (2 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 3 */
@@ -489,29 +489,29 @@
# define SIM_FCFG1_EESIZE_32B (9 << SIM_FCFG1_EESIZE_SHIFT) /* 32 Bytes */
# define SIM_FCFG1_EESIZE_NONE (15 << SIM_FCFG1_EESIZE_SHIFT) /* 0 Bytes */
/* Bits 20-23: Reserved */
-#ifdef KINETIS_K40
-#define SIM_FCFG1_PFSIZE_SHIFT (24) /* Bits 24-27: Program flash size (K40) */
-#define SIM_FCFG1_PFSIZE_MASK (15 << SIM_FCFG1_PFSIZE_SHIFT)
-# define SIM_FCFG1_PFSIZE_128KB (7 << SIM_FCFG1_PFSIZE_SHIFT) /* 128KB program flash, 4KB protection region */
-# define SIM_FCFG1_PFSIZE_256KB (9 << SIM_FCFG1_PFSIZE_SHIFT) /* 256KB program flash, 8KB protection region */
-# define SIM_FCFG1_PFSIZE_512KB (11 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */
-# define SIM_FCFG1_PFSIZE_512KB2 (15 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */
-#define SIM_FCFG1_NVMSIZE_SHIFT (28) /* Bits 28-31: FlexNVM size (K40)*/
-#define SIM_FCFG1_NVMSIZE_MASK (15 << SIM_FCFG1_NVMSIZE_SHIFT)
-# define SIM_FCFG1_NVMSIZE_NONE (0 << SIM_FCFG1_NVMSIZE_SHIFT) /* 0KB FlexNVM */
-# define SIM_FCFG1_NVMSIZE_128KB (7 << SIM_FCFG1_NVMSIZE_SHIFT) /* 128KB FlexNVM, 16KB protection region */
-# define SIM_FCFG1_NVMSIZE_256KB (9 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */
-# define SIM_FCFG1_NVMSIZE_256KB2 (15 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */
+#if defined(KINETIS_K40) || defined(KINETIS_K64)
+# define SIM_FCFG1_PFSIZE_SHIFT (24) /* Bits 24-27: Program flash size (K40) */
+# define SIM_FCFG1_PFSIZE_MASK (15 << SIM_FCFG1_PFSIZE_SHIFT)
+# define SIM_FCFG1_PFSIZE_128KB (7 << SIM_FCFG1_PFSIZE_SHIFT) /* 128KB program flash, 4KB protection region */
+# define SIM_FCFG1_PFSIZE_256KB (9 << SIM_FCFG1_PFSIZE_SHIFT) /* 256KB program flash, 8KB protection region */
+# define SIM_FCFG1_PFSIZE_512KB (11 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */
+# define SIM_FCFG1_PFSIZE_512KB2 (15 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */
+# define SIM_FCFG1_NVMSIZE_SHIFT (28) /* Bits 28-31: FlexNVM size (K40)*/
+# define SIM_FCFG1_NVMSIZE_MASK (15 << SIM_FCFG1_NVMSIZE_SHIFT)
+# define SIM_FCFG1_NVMSIZE_NONE (0 << SIM_FCFG1_NVMSIZE_SHIFT) /* 0KB FlexNVM */
+# define SIM_FCFG1_NVMSIZE_128KB (7 << SIM_FCFG1_NVMSIZE_SHIFT) /* 128KB FlexNVM, 16KB protection region */
+# define SIM_FCFG1_NVMSIZE_256KB (9 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */
+# define SIM_FCFG1_NVMSIZE_256KB2 (15 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */
#endif
#ifdef KINETIS_K60
-#define SIM_FCFG1_FSIZE_SHIFT (24) /* Bits 24-31: Flash size (K60)*/
-#define SIM_FCFG1_FSIZE_MASK (0xff << SIM_FCFG1_FSIZE_SHIFT)
-# define SIM_FCFG1_FSIZE_32KB (2 << SIM_FCFG1_FSIZE_SHIFT) /* 32KB program flash, 1KB protection region */
-# define SIM_FCFG1_FSIZE_64KB (4 << SIM_FCFG1_FSIZE_SHIFT) /* 64KB program flash, 2KB protection region */
-# define SIM_FCFG1_FSIZE_128KB (6 << SIM_FCFG1_FSIZE_SHIFT) /* 128KB program flash, 4KB protection region */
-# define SIM_FCFG1_FSIZE_256KB (8 << SIM_FCFG1_FSIZE_SHIFT) /* 256KB program flash, 8KB protection region */
-# define SIM_FCFG1_FSIZE_512KB (12 << SIM_FCFG1_FSIZE_SHIFT) /* 512KB program flash, 16KB protection region */
+# define SIM_FCFG1_FSIZE_SHIFT (24) /* Bits 24-31: Flash size (K60)*/
+# define SIM_FCFG1_FSIZE_MASK (0xff << SIM_FCFG1_FSIZE_SHIFT)
+# define SIM_FCFG1_FSIZE_32KB (2 << SIM_FCFG1_FSIZE_SHIFT) /* 32KB program flash, 1KB protection region */
+# define SIM_FCFG1_FSIZE_64KB (4 << SIM_FCFG1_FSIZE_SHIFT) /* 64KB program flash, 2KB protection region */
+# define SIM_FCFG1_FSIZE_128KB (6 << SIM_FCFG1_FSIZE_SHIFT) /* 128KB program flash, 4KB protection region */
+# define SIM_FCFG1_FSIZE_256KB (8 << SIM_FCFG1_FSIZE_SHIFT) /* 256KB program flash, 8KB protection region */
+# define SIM_FCFG1_FSIZE_512KB (12 << SIM_FCFG1_FSIZE_SHIFT) /* 512KB program flash, 16KB protection region */
#endif
/* Flash Configuration Register 2 */
@@ -542,4 +542,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_SIM_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SIM_H */
diff --git a/arch/arm/src/kinetis/kinetis_slcd.h b/arch/arm/src/kinetis/chip/kinetis_slcd.h
similarity index 99%
rename from arch/arm/src/kinetis/kinetis_slcd.h
rename to arch/arm/src/kinetis/chip/kinetis_slcd.h
index d56ee5c41eac0e547aeb67874a94d8b76bf95d34..d4a68f07f5a977efaa980bde2dfd00e3edd72b7c 100644
--- a/arch/arm/src/kinetis/kinetis_slcd.h
+++ b/arch/arm/src/kinetis/chip/kinetis_slcd.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_slcd.h
+ * arch/arm/src/kinetis/chip/kinetis_slcd.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_SLCD_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_SLCD_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SLCD_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SLCD_H
/************************************************************************************
* Included Files
@@ -417,4 +417,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_SLCD_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SLCD_H */
diff --git a/arch/arm/src/kinetis/kinetis_smc.h b/arch/arm/src/kinetis/chip/kinetis_smc.h
similarity index 96%
rename from arch/arm/src/kinetis/kinetis_smc.h
rename to arch/arm/src/kinetis/chip/kinetis_smc.h
index 213ea80775972d3f6537b77ec3b36e492b1a0e2d..19a9d9d14b81dbe4c45ce8188adf3bc19c3d4ea1 100644
--- a/arch/arm/src/kinetis/kinetis_smc.h
+++ b/arch/arm/src/kinetis/chip/kinetis_smc.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_smc.h
+ * arch/arm/src/kinetis/chip/kinetis_smc.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_SMC_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_SMC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SMC_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SMC_H
/************************************************************************************
* Included Files
@@ -119,4 +119,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_SMC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SMC_H */
diff --git a/arch/arm/src/kinetis/kinetis_tsi.h b/arch/arm/src/kinetis/chip/kinetis_tsi.h
similarity index 98%
rename from arch/arm/src/kinetis/kinetis_tsi.h
rename to arch/arm/src/kinetis/chip/kinetis_tsi.h
index ea52c0fd1db765848316645b2d9a5b9be5c1e56d..6881150160fe0ef2e41ae4b47b7942dfa3f5937b 100644
--- a/arch/arm/src/kinetis/kinetis_tsi.h
+++ b/arch/arm/src/kinetis/chip/kinetis_tsi.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_tsi.h
+ * arch/arm/src/kinetis/chip/kinetis_tsi.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_TSI_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_TSI_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_TSI_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_TSI_H
/************************************************************************************
* Included Files
@@ -308,4 +308,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_TSI_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_TSI_H */
diff --git a/arch/arm/src/kinetis/kinetis_uart.h b/arch/arm/src/kinetis/chip/kinetis_uart.h
similarity index 99%
rename from arch/arm/src/kinetis/kinetis_uart.h
rename to arch/arm/src/kinetis/chip/kinetis_uart.h
index fbdf7a3192a86cb4536100ef092b38beed3256a8..537332ee78644febc3f678add0b43675fffa0b85 100644
--- a/arch/arm/src/kinetis/kinetis_uart.h
+++ b/arch/arm/src/kinetis/chip/kinetis_uart.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_uart.h
+ * arch/arm/src/kinetis/chip/kinetis_uart.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_UART_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_UART_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_UART_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_UART_H
/************************************************************************************
* Included Files
@@ -42,7 +42,7 @@
#include
-#include "kinetis_memorymap.h"
+#include "chip/kinetis_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
@@ -508,4 +508,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_UART_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_UART_H */
diff --git a/arch/arm/src/kinetis/kinetis_usbdcd.h b/arch/arm/src/kinetis/chip/kinetis_usbdcd.h
similarity index 87%
rename from arch/arm/src/kinetis/kinetis_usbdcd.h
rename to arch/arm/src/kinetis/chip/kinetis_usbdcd.h
index fad76d1500e8771666c3dc123a676dd905d72712..6c4297ff7afec566aa555d6dcc8c875db18bedbe 100644
--- a/arch/arm/src/kinetis/kinetis_usbdcd.h
+++ b/arch/arm/src/kinetis/chip/kinetis_usbdcd.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/src/kinetis/kinetis_usbdcd.h
+ * arch/arm/src/kinetis/chip/kinetis_usbdcd.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_USBDCD_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_USBDCD_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBDCD_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBDCD_H
/************************************************************************************
* Included Files
@@ -50,12 +50,17 @@
/* Register Offsets *****************************************************************/
-#define KINETIS_USBDCD_CONTROL_OFFSET 0x0000 /* Control Register */
-#define KINETIS_USBDCD_CLOCK_OFFSET 0x0004 /* Clock Register */
-#define KINETIS_USBDCD_STATUS_OFFSET 0x0008 /* Status Register */
-#define KINETIS_USBDCD_TIMER0_OFFSET 0x0010 /* TIMER0 Register */
-#define KINETIS_USBDCD_TIMER1_OFFSET 0x0014 /* TIMER1 Register */
-#define KINETIS_USBDCD_TIMER2_OFFSET 0x0018 /* TIMER2 Register */
+#define KINETIS_USBDCD_CONTROL_OFFSET 0x0000 /* Control Register */
+#define KINETIS_USBDCD_CLOCK_OFFSET 0x0004 /* Clock Register */
+#define KINETIS_USBDCD_STATUS_OFFSET 0x0008 /* Status Register */
+#define KINETIS_USBDCD_TIMER0_OFFSET 0x0010 /* TIMER0 Register */
+#define KINETIS_USBDCD_TIMER1_OFFSET 0x0014 /* TIMER1 Register */
+#ifdef KINETIS_K64
+# define KINETIS_USBDCD_TIMER2_BC11_OFFSET 0x0018 /* TIMER2_BC11 Register */
+# define KINETIS_USBDCD_TIMER2_BC12_OFFSET 0x001c /* TIMER2_BC12 Register */
+#else
+# define KINETIS_USBDCD_TIMER2_OFFSET 0x0018 /* TIMER2 Register */
+#endif
/* Register Addresses ***************************************************************/
@@ -64,7 +69,12 @@
#define KINETIS_USBDCD_STATUS (KINETIS_USBDCD_BASE+KINETIS_USBDCD_STATUS_OFFSET)
#define KINETIS_USBDCD_TIMER0 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER0_OFFSET)
#define KINETIS_USBDCD_TIMER1 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER1_OFFSET)
-#define KINETIS_USBDCD_TIMER2 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER2_OFFSET)
+#ifdef KINETIS_K64
+# define KINETIS_USBDCD_TIMER2_BC11 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER2_BC11_OFFSET)
+# define KINETIS_USBDCD_TIMER2_BC12 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER2_BC12_OFFSET)
+#else
+# define KINETIS_USBDCD_TIMER2 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER2_OFFSET)
+#endif
/* Register Bit Definitions *********************************************************/
@@ -138,4 +148,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_USBDCD_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBDCD_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_usbotg.h b/arch/arm/src/kinetis/chip/kinetis_usbotg.h
new file mode 100644
index 0000000000000000000000000000000000000000..16cecc22610fb3c0a9a75adbf2c89d7bbe6f25f6
--- /dev/null
+++ b/arch/arm/src/kinetis/chip/kinetis_usbotg.h
@@ -0,0 +1,377 @@
+/********************************************************************************************
+ * arch/arm/src/kinetis/chip/kinetis_usbotg.h
+ *
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBOTG_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBOTG_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include
+
+#include "chip.h"
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+/* Register Offsets *************************************************************************/
+
+#define KINETIS_USB_PERID_OFFSET 0x0000 /* Peripheral ID Register */
+#define KINETIS_USB_IDCOMP_OFFSET 0x0004 /* Peripheral ID Complement Register */
+#define KINETIS_USB_REV_OFFSET 0x0008 /* Peripheral Revision Register */
+#define KINETIS_USB_ADDINFO_OFFSET 0x000c /* Peripheral Additional Info Register */
+#define KINETIS_USB_OTGISTAT_OFFSET 0x0010 /* OTG Interrupt Status Register */
+#define KINETIS_USB_OTGICR_OFFSET 0x0014 /* OTG Interrupt Control Register */
+#define KINETIS_USB_OTGSTAT_OFFSET 0x0018 /* OTG Status Register */
+#define KINETIS_USB_OTGCTL_OFFSET 0x001c /* OTG Control Register */
+#define KINETIS_USB_ISTAT_OFFSET 0x0080 /* Interrupt Status Register */
+#define KINETIS_USB_INTEN_OFFSET 0x0084 /* Interrupt Enable Register */
+#define KINETIS_USB_ERRSTAT_OFFSET 0x0088 /* Error Interrupt Status Register */
+#define KINETIS_USB_ERREN_OFFSET 0x008c /* Error Interrupt Enable Register */
+#define KINETIS_USB_STAT_OFFSET 0x0090 /* Status Register */
+#define KINETIS_USB_CTL_OFFSET 0x0094 /* Control Register */
+#define KINETIS_USB_ADDR_OFFSET 0x0098 /* Address Register */
+#define KINETIS_USB_BDTPAGE1_OFFSET 0x009c /* BDT Page Register 1 */
+#define KINETIS_USB_FRMNUML_OFFSET 0x00a0 /* Frame Number Register Low */
+#define KINETIS_USB_FRMNUMH_OFFSET 0x00a4 /* Frame Number Register High */
+#define KINETIS_USB_TOKEN_OFFSET 0x00a8 /* Token Register */
+#define KINETIS_USB_SOFTHLD_OFFSET 0x00ac /* SOF Threshold Register */
+#define KINETIS_USB_BDTPAGE2_OFFSET 0x00b0 /* BDT Page Register 2 */
+#define KINETIS_USB_BDTPAGE3_OFFSET 0x00b4 /* BDT Page Register 3 */
+
+#define KINETIS_USB_ENDPT_OFFSET(n) (0x00c0+((n)<<2)) /* Endpoint n Control Register */
+#define KINETIS_USB_ENDPT0_OFFSET 0x00c0 /* Endpoint 0 Control Register */
+#define KINETIS_USB_ENDPT1_OFFSET 0x00c4 /* Endpoint 1 Control Register */
+#define KINETIS_USB_ENDPT2_OFFSET 0x00c8 /* Endpoint 2 Control Register */
+#define KINETIS_USB_ENDPT3_OFFSET 0x00cc /* Endpoint 3 Control Register */
+#define KINETIS_USB_ENDPT4_OFFSET 0x00d0 /* Endpoint 4 Control Register */
+#define KINETIS_USB_ENDPT5_OFFSET 0x00d4 /* Endpoint 5 Control Register */
+#define KINETIS_USB_ENDPT6_OFFSET 0x00d8 /* Endpoint 6 Control Register */
+#define KINETIS_USB_ENDPT7_OFFSET 0x00dc /* Endpoint 7 Control Register */
+#define KINETIS_USB_ENDPT8_OFFSET 0x00e0 /* Endpoint 8 Control Register */
+#define KINETIS_USB_ENDPT9_OFFSET 0x00e4 /* Endpoint 9 Control Register */
+#define KINETIS_USB_ENDPT10_OFFSET 0x00e8 /* Endpoint 10 Control Register */
+#define KINETIS_USB_ENDPT11_OFFSET 0x00ec /* Endpoint 11 Control Register */
+#define KINETIS_USB_ENDPT12_OFFSET 0x00f0 /* Endpoint 12 Control Register */
+#define KINETIS_USB_ENDPT13_OFFSET 0x00f4 /* Endpoint 13 Control Register */
+#define KINETIS_USB_ENDPT14_OFFSET 0x00f8 /* Endpoint 14 Control Register */
+#define KINETIS_USB_ENDPT15_OFFSET 0x00fc /* Endpoint 15 Control Register */
+
+#define KINETIS_USB_USBCTRL_OFFSET 0x0100 /* USB Control Register */
+#define KINETIS_USB_OBSERVE_OFFSET 0x0104 /* USB OTG Observe Register */
+#define KINETIS_USB_CONTROL_OFFSET 0x0108 /* USB OTG Control Register */
+#define KINETIS_USB_USBTRC0_OFFSET 0x010c /* USB Transceiver Control Register 0 */
+
+#ifdef KINETIS_K64
+# define KINETIS_USB_USBFRMADJUST_OFFSET 0x114 /* Frame Adjust Register */
+# define KINETIS_USB_USB0_CLK_RECOVER_CTRL_OFFSET 0x140 /* USB Clock recovery control */
+# define KINETIS_USB_USB0_CLK_RECOVER_IRC_EN_OFFSET 0x144 /* IRC48M oscillator enable register */
+# define KINETIS_USB_USB0_CLK_RECOVER_INT_STATUS_OFFSET 0x15c /* Clock recovery sperated interrupt status */
+#endif
+
+/* Register Addresses ***********************************************************************/
+
+#define KINETIS_USB0_PERID (KINETIS_USB0_BASE+KINETIS_USB_PERID_OFFSET)
+#define KINETIS_USB0_IDCOMP (KINETIS_USB0_BASE+KINETIS_USB_IDCOMP_OFFSET)
+#define KINETIS_USB0_REV (KINETIS_USB0_BASE+KINETIS_USB_REV_OFFSET)
+#define KINETIS_USB0_ADDINFO (KINETIS_USB0_BASE+KINETIS_USB_ADDINFO_OFFSET)
+#define KINETIS_USB0_OTGISTAT (KINETIS_USB0_BASE+KINETIS_USB_OTGISTAT_OFFSET)
+#define KINETIS_USB0_OTGICR (KINETIS_USB0_BASE+KINETIS_USB_OTGICR_OFFSET)
+#define KINETIS_USB0_OTGSTAT (KINETIS_USB0_BASE+KINETIS_USB_OTGSTAT_OFFSET)
+#define KINETIS_USB0_OTGCTL (KINETIS_USB0_BASE+KINETIS_USB_OTGCTL_OFFSET)
+#define KINETIS_USB0_ISTAT (KINETIS_USB0_BASE+KINETIS_USB_ISTAT_OFFSET)
+#define KINETIS_USB0_INTEN (KINETIS_USB0_BASE+KINETIS_USB_INTEN_OFFSET)
+#define KINETIS_USB0_ERRSTAT (KINETIS_USB0_BASE+KINETIS_USB_ERRSTAT_OFFSET)
+#define KINETIS_USB0_ERREN (KINETIS_USB0_BASE+KINETIS_USB_ERREN_OFFSET)
+#define KINETIS_USB0_STAT (KINETIS_USB0_BASE+KINETIS_USB_STAT_OFFSET)
+#define KINETIS_USB0_CTL (KINETIS_USB0_BASE+KINETIS_USB_CTL_OFFSET)
+#define KINETIS_USB0_ADDR (KINETIS_USB0_BASE+KINETIS_USB_ADDR_OFFSET)
+#define KINETIS_USB0_BDTPAGE1 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE1_OFFSET)
+#define KINETIS_USB0_FRMNUML (KINETIS_USB0_BASE+KINETIS_USB_FRMNUML_OFFSET)
+#define KINETIS_USB0_FRMNUMH (KINETIS_USB0_BASE+KINETIS_USB_FRMNUMH_OFFSET)
+#define KINETIS_USB0_TOKEN (KINETIS_USB0_BASE+KINETIS_USB_TOKEN_OFFSET)
+#define KINETIS_USB0_SOFTHLD (KINETIS_USB0_BASE+KINETIS_USB_SOFTHLD_OFFSET)
+#define KINETIS_USB0_BDTPAGE2 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE2_OFFSET)
+#define KINETIS_USB0_BDTPAGE3 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE3_OFFSET)
+
+#define KINETIS_USB0_ENDPT(n) (KINETIS_USB0_BASE+KINETIS_USB_ENDPT_OFFSET(n))
+#define KINETIS_USB0_ENDPT0 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT0_OFFSET)
+#define KINETIS_USB0_ENDPT1 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT1_OFFSET)
+#define KINETIS_USB0_ENDPT2 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT2_OFFSET)
+#define KINETIS_USB0_ENDPT3 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT3_OFFSET)
+#define KINETIS_USB0_ENDPT4 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT4_OFFSET)
+#define KINETIS_USB0_ENDPT5 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT5_OFFSET)
+#define KINETIS_USB0_ENDPT6 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT6_OFFSET)
+#define KINETIS_USB0_ENDPT7 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT7_OFFSET)
+#define KINETIS_USB0_ENDPT8 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT8_OFFSET)
+#define KINETIS_USB0_ENDPT9 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT9_OFFSET)
+#define KINETIS_USB0_ENDPT10 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT10_OFFSET)
+#define KINETIS_USB0_ENDPT11 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT11_OFFSET)
+#define KINETIS_USB0_ENDPT12 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT12_OFFSET)
+#define KINETIS_USB0_ENDPT13 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT13_OFFSET)
+#define KINETIS_USB0_ENDPT14 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT14_OFFSET)
+#define KINETIS_USB0_ENDPT15 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT15_OFFSET)
+
+#define KINETIS_USB0_USBCTRL (KINETIS_USB0_BASE+KINETIS_USB_USBCTRL_OFFSET)
+#define KINETIS_USB0_OBSERVE (KINETIS_USB0_BASE+KINETIS_USB_OBSERVE_OFFSET)
+#define KINETIS_USB0_CONTROL (KINETIS_USB0_BASE+KINETIS_USB_CONTROL_OFFSET)
+#define KINETIS_USB0_USBTRC0 (KINETIS_USB0_BASE+KINETIS_USB_USBTRC0_OFFSET)
+
+#ifdef KINETIS_K64
+# define KINETIS_USB_USBFRMADJUST \
+ (KINETIS_USB0_BASE+KINETIS_USB_USBFRMADJUST_OFFSET)
+# define KINETIS_USB_USB0_CLK_RECOVER_CTRL \
+ (KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_CTRL_OFFSET)
+# define KINETIS_USB_USB0_CLK_RECOVER_IRC_EN \
+ (KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_IRC_EN_OFFSET)
+# define KINETIS_USB_USB0_CLK_RECOVER_INT_STATUS \
+ (KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_INT_STATUS_OFFSET)
+#endif
+
+/* Register Bit Definitions *****************************************************************/
+
+/* Peripheral ID Register (8-bit) */
+ /* Bits 6-7: Reserved */
+#define USB_PERID_MASK (0x3f) /* Bits 0-5: Peripheral identification bits */
+
+/* Peripheral ID Complement Register (8-bit) */
+#define USB_IDCOMP_
+ /* Bits 6-7: Reserved */
+#define USB_IDCOMP_MASK (0x3f) /* Bits 0-5: Ones complement of peripheral identification bits */
+
+/* Peripheral Revision Register (8-bit revision number) */
+
+/* Peripheral Additional Info Register (8-bit) */
+
+#define USB_ADDINFO_IEHOST (1 << 0) /* Bit 0: This bit is set if host mode is enabled */
+ /* Bits 1-2: Reserved */
+#define USB_ADDINFO_IRQNUM_SHIFT (3) /* Bits 3-7: Assigned Interrupt Request Number */
+#define USB_ADDINFO_IRQNUM_MASK (31 << USB_ADDINFO_IRQNUM_SHIFT)
+
+/* OTG Interrupt Status Register(8-bit) */
+
+#define USB_OTGISTAT_AVBUSCHG (1 << 0) /* Bit 0: Change in VBUS is detected on an A device */
+ /* Bit 1: Reserved */
+#define USB_OTGISTAT_B_SESS_CHG (1 << 2) /* Bit 2: Change in VBUS is detected on a B device */
+#define USB_OTGISTAT_SESSVLDCHG (1 << 3) /* Bit 3: Change in VBUS is detected */
+ /* Bit 4: Reserved */
+#define USB_OTGISTAT_LINE_STATE_CHG (1 << 5) /* Bit 5: Change USB line state */
+#define USB_OTGISTAT_ONEMSEC (1 << 6) /* Bit 6: Set when the 1 millisecond timer expires */
+#define USB_OTGISTAT_IDCHG (1 << 7) /* Bit 7: Change in ID Signal from the USB connector */
+
+/* OTG Interrupt Control Register (8-bit) */
+
+#define USB_OTGICR_AVBUSEN (1 << 0) /* Bit 0: A VBUS Valid interrupt enable */
+ /* Bit 1: Reserved */
+#define USB_OTGICR_BSESSEN (1 << 2) /* Bit 2: B Session END interrupt enable */
+#define USB_OTGICR_SESSVLDEN (1 << 3) /* Bit 3: Session valid interrupt enable */
+ /* Bit 4: Reserved */
+#define USB_OTGICR_LINESTATEEN (1 << 5) /* Bit 5: Line State change interrupt enable */
+#define USB_OTGICR_ONEMSECEN (1 << 6) /* Bit 6: 1 millisecond interrupt enable */
+#define USB_OTGICR_IDEN (1 << 7) /* Bit 7: ID interrupt enable */
+
+/* OTG Status Register (8-bit) */
+
+#define USB_OTGSTAT_AVBUSVLD (1 << 0) /* Bit 0: A VBUS Valid */
+ /* Bit 1: Reserved */
+#define USB_OTGSTAT_BSESSEND (1 << 2) /* Bit 2: B Session END */
+#define USB_OTGSTAT_SESS_VLD (1 << 3) /* Bit 3: Session valid */
+ /* Bit 4: Reserved */
+#define USB_OTGSTAT_LINESTATESTABLE (1 << 5) /* Bit 5: OTGISTAT LINE_STATE_CHG bit stable */
+#define USB_OTGSTAT_ONEMSECEN (1 << 6) /* Bit 6: Reserved for the 1msec count */
+#define USB_OTGSTAT_ID (1 << 7) /* Bit 7: Current state of the ID pin on the USB connector */
+
+/* OTG Control Register (8-bit) */
+ /* Bits 0-1: Reserved */
+#define USB_OTGCTL_OTGEN (1 << 2) /* Bit 2: On-The-Go pullup/pulldown resistor enable */
+ /* Bit 3: Reserved */
+#define USB_OTGCTL_DMLOW (1 << 4) /* Bit 4: D- Data Line pull-down resistor enable */
+#define USB_OTGCTL_DPLOW (1 << 5) /* Bit 5: D+ Data Line pull-down resistor enable */
+ /* Bit 6: Reserved */
+#define USB_OTGCTL_DPHIGH (1 << 7) /* Bit 7: D+ Data Line pullup resistor enable */
+
+/* Interrupt Status Register Interrupt Enable Register (8-bit) */
+
+#define USB_INT_USBRST (1 << 0) /* Bit 0: USB Module has decoded a valid USB reset */
+#define USB_INT_ERROR (1 << 1) /* Bit 1: Any of the error conditions within the ERRSTAT register */
+#define USB_INT_SOFTOK (1 << 2) /* Bit 2: USB Module received a Start Of Frame (SOF) token */
+#define USB_INT_TOKDNE (1 << 3) /* Bit 3: Current token being processed has completed */
+#define USB_INT_SLEEP (1 << 4) /* Bit 4: Constant idle on the USB bus for 3 milliseconds */
+#define USB_INT_RESUME (1 << 5) /* Bit 5: Signal remote wake-up signaling */
+#define USB_INT_ATTACH (1 << 6) /* Bit 6: Attach Interrupt */
+#define USB_INT_STALL (1 << 7) /* Bit 7: Stall Interrupt */
+
+#define USB_INT_ALL 0xFF
+
+/* Error Interrupt Status Register and Error Interrupt Enable Register (8-bit) */
+
+#define USB_ERRSTAT_PIDERR (1 << 0) /* Bit 0: This bit is set when the PID check field fails */
+#define USB_ERRSTAT_CRC5EOF (1 << 1) /* Bit 1: Host data CRC error or End of frame errors */
+#define USB_ERRSTAT_CRC16 (1 << 2) /* Bit 2: Data packet is rejected due to a CRC16 error */
+#define USB_ERRSTAT_DFN8 (1 << 3) /* Bit 3: Data field received was not 8 bits in length */
+#define USB_ERRSTAT_BTOERR (1 << 4) /* Bit 4: Bus turnaround timeout error occurred */
+#define USB_ERRSTAT_DMAERR (1 << 5) /* Bit 5: DMA error */
+ /* Bit 6: Reserved */
+#define USB_ERRSTAT_BTSERR (1 << 7) /* Bit 7: Bit stuff error is detected */
+
+#define USB_EINT_ALL 0xBF
+
+/* Status Register (8-bit) */
+
+ /* Bits 0-1: Reserved */
+#define USB_STAT_ODD (1 << 2) /* Bit 2: Last Buffer Descriptor was in the odd bank of the BDT */
+#define USB_STAT_TX (1 << 3) /* Bit 3: Transmit Indicator */
+#define USB_STAT_ENDP_SHIFT (4) /* Bits 4-7: Endpoint address that received or transmitted the token */
+#define USB_STAT_ENDP_MASK (15 << USB_STAT_ENDP_SHIFT)
+
+/* Control Register (8-bit) */
+
+#define USB_CTL_USBENSOFEN (1 << 0) /* Bit 0: USB Enable */
+#define USB_CTL_ODDRST (1 << 1) /* Bit 1: Resets all the BDT ODD ping/pong bits to 0 */
+#define USB_CTL_RESUME (1 << 2) /* Bit 2: Enables the USB Module to execute resume signaling */
+#define USB_CTL_HOSTMODEEN (1 << 3) /* Bit 3: Enables the USB Module to operate in Host mode */
+#define USB_CTL_RESET (1 << 4) /* Bit 4: Enables the USB Module to generate USB reset signaling */
+#define USB_CTL_TXSUSPENDTOKENBUSY (1 << 5) /* Bit 5: USB Module is busy executing a USB token */
+#define USB_CTL_SE0 (1 << 6) /* Bit 6: Live USB Single Ended Zero signal */
+#define USB_CTL_JSTATE (1 << 7) /* Bit 7: Live USB differential receiver JSTATE signal */
+
+/* Address Register (8-bit) */
+
+#define USB_ADDR_LSEN (1 << 7) /* Bit 7: Low Speed Enable bit */
+#define USB_ADDR_SHIFT (0) /* Bits 0-6: USB address */
+#define USB_ADDR_MASK (0x7f << USB_ADDR_SHIFT)
+
+/* BDT Page Register 1 (8-bit) */
+ /* Bit 0: Reserved */
+#define USB_BDTPAGE1_SHIFT (1) /* Bits 1-7: Address bits 9-15 of the BDT base address */
+#define USB_BDTPAGE1_MASK (0x7f << USB_BDTPAGE1_SHIFT)
+
+/* Frame Number Register Low (8-bit, bits 0-7 of the 11 bit frame number) */
+#define USB_FRMNUML_MASK 0xFF
+/* Frame Number Register High (8-bit) */
+ /* Bits 3-7: Reserved */
+#define USB_FRMNUMH_SHIFT (0) /* Bits 0-2: Bits 8-10 of the 11-bit frame number */
+#define USB_FRMNUMH_MASK (7 << USB_FRMNUMH_SHIFT)
+
+/* Token Register (8-bit) */
+
+#define USB_TOKEN_ENDPT_SHIFT (0) /* Bits 0-3: Endpoint address for the token command */
+#define USB_TOKEN_ENDPT_MASK (15 << USB_TOKEN_ENDPT_SHIFT)
+#define USB_TOKEN_PID_SHIFT (4) /* Bits 4-7: Token type executed by the USB Module */
+#define USB_TOKEN_PID_MASK (15 << USB_TOKEN_PID_SHIFT)
+# define USB_TOKEN_PID_OUT (1 << USB_TOKEN_PID_SHIFT) /* OUT Token */
+# define USB_TOKEN_PID_IN (9 << USB_TOKEN_PID_SHIFT) /* IN Token */
+# define USB_TOKEN_PID_SETUP (13 << USB_TOKEN_PID_SHIFT) /* SETUP Token */
+
+/* SOF Threshold Register (8-bit count value) */
+/* BDT Page Register 2/3 (16 bit address in two 8-bit registers) */
+
+/* Endpoint n Control Register (8-bit) */
+
+#define USB_ENDPT_EPHSHK (1 << 0) /* Bit 0: Enable handshaking during a transaction to the endpoint */
+#define USB_ENDPT_EPSTALL (1 << 1) /* Bit 1: Endpoint is stalled */
+#define USB_ENDPT_EPTXEN (1 << 2) /* Bit 2: Enable the endpoint for TX transfers */
+#define USB_ENDPT_EPRXEN (1 << 3) /* Bit 3: Enable the endpoint for RX transfers */
+#define USB_ENDPT_EPCTLDIS (1 << 4) /* Bit 4: Disable control (SETUP) transfers */
+ /* Bit 5: Reserved */
+#define USB_ENDPT_RETRYDIS (1 << 6) /* Bit 6: Disable host retry NAK'ed transactions (host EP0) */
+#define USB_ENDPT_HOSTWOHUB (1 << 7) /* Bit 7: Allows the host to communicate to a low speed device (host EP0) */
+
+/* USB Control Register (8-bit) */
+ /* Bits 0-5: Reserved */
+#define USB_USBCTRL_PDE (1 << 6) /* Bit 6: Enables the weak pulldowns on the USB transceiver */
+#define USB_USBCTRL_SUSP (1 << 7) /* Bit 7: Places the USB transceiver into the suspend state */
+
+/* USB OTG Observe Register (8-bit) */
+ /* Bits 0-3: Reserved */
+#define USB_OBSERVE_DMPD (1 << 4) /* Bit 4: D- Pull Down signal output from the USB OTG module */
+ /* Bit 5: Reserved */
+#define USB_OBSERVE_DPPD (1 << 6) /* Bit 6: D+ Pull Down signal output from the USB OTG module */
+#define USB_OBSERVE_DPPU (1 << 7) /* Bit 7: D+ Pull Up signal output from the USB OTG module */
+
+/* USB OTG Control Register (8-bit) */
+ /* Bits 0-3: Reserved */
+#define USB_CONTROL_DPPULLUPNONOTG (1 << 4) /* Bit 4: Controls of the DP PULLUP in the USB OTG module */
+ /* Bits 5-7: Reserved */
+/* USB Transceiver Control Register 0 (8-bit) */
+
+#define USB_USBTRC0_USBRESET (1 << 7) /* Bit 7: USB reset */
+ /* Bit 6: Reserved */
+#define USB_USBTRC0_USBRESMEN (1 << 5) /* Bit 5: Asynchronous Resume Interrupt Enable */
+ /* Bits 2-4: Reserved */
+#define USB_USBTRC0_SYNC_DET (1 << 1) /* Bit 1: Synchronous USB Interrupt Detect */
+#define USB_USBTRC0_RESUME_INT (1 << 0) /* Bit 0: USB Asynchronous Interrupt */
+
+/* Buffer Descriptor Table (BDT) ****************************************************/
+/* Offset 0: On write (software->hardware) */
+
+#define USB_BDT_STATUS_MASK 0xfc /* Bits 2-7: Status bits */
+#define USB_BDT_BSTALL (1 << 2) /* Bit 2: Buffer Stall Enable bit */
+#define USB_BDT_DTS (1 << 3) /* Bit 3: Data Toggle Synchronization Enable bit */
+#define USB_BDT_NINC (1 << 4) /* Bit 4: DMA Address Increment Disable bit */
+#define USB_BDT_KEEP (1 << 5) /* Bit 5: BD Keep Enable bit */
+#define USB_BDT_DATA01 (1 << 6) /* Bit 6: Data Toggle Packet bit */
+#define USB_BDT_UOWN (1 << 7) /* Bit 7: USB Own bit */
+#define USB_BDT_BYTECOUNT_SHIFT (16) /* Bits 16-25: Byte Count bits */
+#define USB_BDT_BYTECOUNT_MASK (0x3ff << USB_BDT_BYTECOUNT_SHIFT)
+
+#define USB_BDT_DATA0 0 /* DATA0 packet expected next */
+#define USB_BDT_DATA1 USB_BDT_DATA01 /* DATA1 packet expected next */
+#define USB_BDT_COWN 0 /* CPU owns the descriptor */
+
+/* Offset 0: On read (hardware->software) */
+
+#define USB_BDT_PID_SHIFT (2) /* Bits 2-5: Packet Identifier bits */
+#define USB_BDT_PID_MASK (15 << USB_BDT_PID_SHIFT)
+ /* Bit 7: USB Own bit (same) */
+ /* Bits 16-25: Byte Count bits (same) */
+
+/* Offset 4: BUFFER_ADDRESS, 32-bit Buffer Address bits */
+
+#define USB_BDT_BYTES_SIZE 8 /* Eight bytes per BDT */
+#define USB_BDT_WORD_SIZE 2 /* Two 32-bit words per BDT */
+#define USB_NBDTS_PER_EP 4 /* Number of BDTS per endpoint: IN/OUT and EVEN/ODD */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBOTG_H */
diff --git a/arch/arm/src/kinetis/kinetis_vrefv1.h b/arch/arm/src/kinetis/chip/kinetis_vrefv1.h
similarity index 94%
rename from arch/arm/src/kinetis/kinetis_vrefv1.h
rename to arch/arm/src/kinetis/chip/kinetis_vrefv1.h
index ed9a1ff95c5dc51779b89864f9ac29f5f73f371c..29c871dd22d10fb2066d2ea564a93be9eadc036d 100644
--- a/arch/arm/src/kinetis/kinetis_vrefv1.h
+++ b/arch/arm/src/kinetis/chip/kinetis_vrefv1.h
@@ -1,7 +1,7 @@
/********************************************************************************************
- * arch/arm/src/kinetis/kinetis_vrefv1.h
+ * arch/arm/src/kinetis/chip/kinetis_vrefv1.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
********************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_VREFV1_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_VREFV1_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_VREFV1_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_VREFV1_H
/********************************************************************************************
* Included Files
@@ -89,4 +89,4 @@
* Public Functions
********************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_VREFV1_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_VREFV1_H */
diff --git a/arch/arm/src/kinetis/kinetis_wdog.h b/arch/arm/src/kinetis/chip/kinetis_wdog.h
similarity index 95%
rename from arch/arm/src/kinetis/kinetis_wdog.h
rename to arch/arm/src/kinetis/chip/kinetis_wdog.h
index 326c2cf628fe360fc904dc2f51ebe09008fd24ed..6f50386049900167f4930e4ab19dc3775a51e696 100644
--- a/arch/arm/src/kinetis/kinetis_wdog.h
+++ b/arch/arm/src/kinetis/chip/kinetis_wdog.h
@@ -1,7 +1,7 @@
/********************************************************************************************
- * arch/arm/src/kinetis/kinetis_wdog.h
+ * arch/arm/src/kinetis/chip/kinetis_wdog.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +33,8 @@
*
********************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_WDOG_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_WDOG_H
+#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_WDOG_H
+#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_WDOG_H
/********************************************************************************************
* Included Files
@@ -90,7 +90,9 @@
#define WDOG_STCTRLH_DBGEN (1 << 5) /* Bit 5: Enables or disables WDOG in Debug mode */
#define WDOG_STCTRLH_STOPEN (1 << 6) /* Bit 6: Enables or disables WDOG in stop mode */
#define WDOG_STCTRLH_WAITEN (1 << 7) /* Bit 7: Enables or disables WDOG in wait mode */
-#define WDOG_STCTRLH_STNDBYEN (1 << 8) /* Bit 8: Enables or disables WDOG in Standby mode */
+#ifndef KINETIS_K64
+# define WDOG_STCTRLH_STNDBYEN (1 << 8) /* Bit 8: Enables or disables WDOG in Standby mode */
+#endif
/* Bit 9: Reserved */
#define WDOG_STCTRLH_TESTWDOG (1 << 10) /* Bit 10: Selects functional test mode */
#define WDOG_STCTRLH_TESTSEL (1 << 11) /* Bit 11: Selects the test to be run */
@@ -132,4 +134,4 @@
* Public Functions
********************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_WDOG_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_WDOG_H */
diff --git a/arch/arm/src/kinetis/kinetis.h b/arch/arm/src/kinetis/kinetis.h
index ae02ce7e4f81aae52892db227f2874b25d47dd0b..bb02f01e92cc3ae81ac9c375f18f85efa0f11200 100644
--- a/arch/arm/src/kinetis/kinetis.h
+++ b/arch/arm/src/kinetis/kinetis.h
@@ -52,7 +52,7 @@
#include "up_internal.h"
#include "kinetis_config.h"
#include "chip.h"
-#include "kinetis_port.h"
+#include "chip/kinetis_port.h"
/************************************************************************************
* Pre-processor Definitions
@@ -476,7 +476,7 @@ bool kinetis_gpioread(uint32_t pinset);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KINETIS_GPIOIRQ
void kinetis_pinirqinitialize(void);
#else
# define kinetis_pinirqinitialize()
@@ -514,7 +514,7 @@ xcpt_t kinetis_pinirqattach(uint32_t pinset, xcpt_t pinisr);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KINETIS_GPIOIRQ
void kinetis_pinirqenable(uint32_t pinset);
#else
# define kinetis_pinirqenable(pinset)
@@ -528,7 +528,7 @@ void kinetis_pinirqenable(uint32_t pinset);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KINETIS_GPIOIRQ
void kinetis_pinirqdisable(uint32_t pinset);
#else
# define kinetis_pinirqdisable(pinset)
diff --git a/arch/arm/src/kinetis/kinetis_alarm.h b/arch/arm/src/kinetis/kinetis_alarm.h
new file mode 100644
index 0000000000000000000000000000000000000000..751cfd8cf059b6f5669a090563b478da97931de8
--- /dev/null
+++ b/arch/arm/src/kinetis/kinetis_alarm.h
@@ -0,0 +1,113 @@
+/****************************************************************************
+ * arch/arm/src/kinetis/kinetis_alarm.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Matias v01d
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_ALARM_H
+#define __ARCH_ARM_SRC_KINETIS_ALARM_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include "chip.h"
+
+#ifdef CONFIG_RTC_ALARM
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* The form of an alarm callback */
+
+typedef CODE void (*alarmcb_t)(void);
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: kinetis_rtc_setalarm
+ *
+ * Description:
+ * Set up an alarm.
+ *
+ * Input Parameters:
+ * tp - the time to set the alarm
+ * callback - the function to call when the alarm expires.
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+struct timespec;
+int kinetis_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback);
+
+/****************************************************************************
+ * Name: kinetis_rtc_cancelalarm
+ *
+ * Description:
+ * Cancel a pending alarm alarm
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+int kinetis_rtc_cancelalarm(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_RTC_ALARM */
+#endif /* __ARCH_ARM_SRC_KINETIS_ALARM_H */
diff --git a/arch/arm/src/kinetis/kinetis_clockconfig.c b/arch/arm/src/kinetis/kinetis_clockconfig.c
index 7221b9dc6e76416e6edc83b1ef9b1ddac09e7f34..7d3d6ecb22ac812bdbd19921a4d6dc01b99662ff 100644
--- a/arch/arm/src/kinetis/kinetis_clockconfig.c
+++ b/arch/arm/src/kinetis/kinetis_clockconfig.c
@@ -39,16 +39,16 @@
#include
-#include
-
#include "up_arch.h"
#include "kinetis.h"
-#include "kinetis_mcg.h"
-#include "kinetis_sim.h"
-#include "kinetis_fmc.h"
-#include "kinetis_llwu.h"
-#include "kinetis_pinmux.h"
+#include "chip/kinetis_mcg.h"
+#include "chip/kinetis_sim.h"
+#include "chip/kinetis_fmc.h"
+#include "chip/kinetis_llwu.h"
+#include "chip/kinetis_pinmux.h"
+
+#include
/****************************************************************************
* Pre-processor Definitions
@@ -373,6 +373,3 @@ kinesis_setdividers(uint32_t div1, uint32_t div2, uint32_t div3, uint32_t div4)
putreg32(regval, KINETIS_FMC_PFAPR);
}
-
-
-
diff --git a/arch/arm/src/kinetis/kinetis_config.h b/arch/arm/src/kinetis/kinetis_config.h
index ce1c6efedf79b6d7348ef4a04fb77b12d3cc1d15..1ce2e7ee5e3e6b80a4a27aec8b5d92e861e44791 100644
--- a/arch/arm/src/kinetis/kinetis_config.h
+++ b/arch/arm/src/kinetis/kinetis_config.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETISXX_KINETIS_CONFIG_H
-#define __ARCH_ARM_SRC_KINETISXX_KINETIS_CONFIG_H
+#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_CONFIG_H
+#define __ARCH_ARM_SRC_KINETIS_KINETIS_CONFIG_H
/************************************************************************************
* Included Files
@@ -232,4 +232,4 @@
* Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KINETISXX_KINETIS_CONFIG_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_CONFIG_H */
diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c
index f31dfd06ba23925503c1ca4fbb8b785a04fa16b2..dc0be25e1640b36ac77a36960cf6b50a5561a536 100644
--- a/arch/arm/src/kinetis/kinetis_enet.c
+++ b/arch/arm/src/kinetis/kinetis_enet.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * drivers/net/kinetis_enet.c
+ * arch/arm/src/kinetis/kinetis_enet.c
*
* Copyright (C) 2011-2012, 2014-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -57,6 +57,10 @@
#include
#include
+#ifdef CONFIG_NET_NOINTS
+# include
+#endif
+
#ifdef CONFIG_NET_PKT
# include
#endif
@@ -65,10 +69,10 @@
#include "chip.h"
#include "kinetis.h"
#include "kinetis_config.h"
-#include "kinetis_pinmux.h"
-#include "kinetis_sim.h"
-#include "kinetis_mpu.h"
-#include "kinetis_enet.h"
+#include "chip/kinetis_pinmux.h"
+#include "chip/kinetis_sim.h"
+#include "chip/kinetis_mpu.h"
+#include "chip/kinetis_enet.h"
#if defined(KINETIS_NENET) && KINETIS_NENET > 0
@@ -76,29 +80,40 @@
* Pre-processor Definitions
****************************************************************************/
-/* CONFIG_ENET_NETHIFS determines the number of physical interfaces
+/* If processing is not done at the interrupt level, then high priority
+ * work queue support is required.
+ */
+
+#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_HPWORK)
+# error High priority work queue support is required
+#endif
+
+/* CONFIG_KINETIS_ENETNETHIFS determines the number of physical interfaces
* that will be supported.
*/
-#if CONFIG_ENET_NETHIFS != 1
-# error "CONFIG_ENET_NETHIFS must be one for now"
+#if CONFIG_KINETIS_ENETNETHIFS != 1
+# error "CONFIG_KINETIS_ENETNETHIFS must be one for now"
#endif
-#if CONFIG_ENET_NTXBUFFERS < 1
+#if CONFIG_KINETIS_ENETNTXBUFFERS < 1
# error "Need at least one TX buffer"
#endif
-#if CONFIG_ENET_NRXBUFFERS < 1
+#if CONFIG_KINETIS_ENETNRXBUFFERS < 1
# error "Need at least one RX buffer"
#endif
-#define NENET_NBUFFERS (CONFIG_ENET_NTXBUFFERS+CONFIG_ENET_NRXBUFFERS)
+#define NENET_NBUFFERS \
+ (CONFIG_KINETIS_ENETNTXBUFFERS+CONFIG_KINETIS_ENETNRXBUFFERS)
#ifndef CONFIG_NET_MULTIBUFFER
# error "CONFIG_NET_MULTIBUFFER is required in the configuration"
#endif
-/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */
+/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
+ * second.
+ */
#define KINETIS_WDDELAY (1*CLK_TCK)
@@ -108,14 +123,47 @@
#define MII_MAXPOLLS (0x1ffff)
#define LINK_WAITUS (500*1000)
-/* PHY hardware specifics. This was copied from the FreeScale code examples.
- * this is a vendor specific register and bit settings. I really should
- * do the research and find out what this really is.
+/* PHY definitions.
+ *
+ * The selected PHY must be selected from the drivers/net/Kconfig PHY menu.
+ * A description of the PHY must be provided here. That description must
+ * include:
+ *
+ * 1. BOARD_PHY_NAME: A PHY name string (for debug output),
+ * 2. BOARD_PHYID1 and BOARD_PHYID2: The PHYID1 and PHYID2 values (from
+ * include/nuttx/net/mii.h)
+ * 3. BOARD_PHY_STATUS: The address of the status register to use when
+ * querying link status (from include/nuttx/net/mii.h)
+ * 4. BOARD_PHY_ISDUPLEX: A macro that can convert the status register
+ * value into a boolean: true=duplex mode, false=half-duplex mode
+ * 5. BOARD_PHY_10BASET: A macro that can convert the status register
+ * value into a boolean: true=10Base-T, false=Not 10Base-T
+ * 6. BOARD_PHY_100BASET: A macro that can convert the status register
+ * value into a boolean: true=100Base-T, false=Not 100Base-T
+ *
+ * The Tower SER board uses a KSZ8041 PHY.
+ * The Freedom K64F board uses a KSZ8081 PHY
*/
-#define PHY_STATUS (0x1f)
-#define PHY_DUPLEX_STATUS (4 << 2)
-#define PHY_SPEED_STATUS (1 << 2)
+#if defined(CONFIG_ETH0_PHY_KSZ8041)
+# define BOARD_PHY_NAME "KSZ8041"
+# define BOARD_PHYID1 MII_PHYID1_KSZ8041
+# define BOARD_PHYID2 MII_PHYID2_KSZ8041
+# define BOARD_PHY_STATUS MII_KSZ8041_PHYCTRL2
+# define BOARD_PHY_ISDUPLEX(s) (((s) & (4 << MII_PHYCTRL2_MODE_SHIFT)) != 0)
+# define BOARD_PHY_10BASET(s) (((s) & (1 << MII_PHYCTRL2_MODE_SHIFT)) != 0)
+# define BOARD_PHY_100BASET(s) (((s) & (2 << MII_PHYCTRL2_MODE_SHIFT)) != 0)
+#elif defined(CONFIG_ETH0_PHY_KSZ8081)
+# define BOARD_PHY_NAME "KSZ8081"
+# define BOARD_PHYID1 MII_PHYID1_KSZ8081
+# define BOARD_PHYID2 MII_PHYID2_KSZ8081
+# define BOARD_PHY_STATUS MII_KSZ8081_PHYCTRL2
+# define BOARD_PHY_ISDUPLEX(s) (((s) & (4 << MII_PHYCTRL2_MODE_SHIFT)) != 0)
+# define BOARD_PHY_10BASET(s) (((s) & (1 << MII_PHYCTRL2_MODE_SHIFT)) != 0)
+# define BOARD_PHY_100BASET(s) (((s) & (2 << MII_PHYCTRL2_MODE_SHIFT)) != 0)
+#else
+# error "Unrecognized or missing PHY selection"
+#endif
/* Estimate the hold time to use based on the peripheral (bus) clock:
*
@@ -160,8 +208,12 @@ struct kinetis_driver_s
uint8_t txtail; /* The oldest busy TX descriptor */
uint8_t txhead; /* The next TX descriptor to use */
uint8_t rxtail; /* The next RX descriptor to use */
+ uint8_t phyaddr; /* Selected PHY address */
WDOG_ID txpoll; /* TX poll timer */
WDOG_ID txtimeout; /* TX timeout timer */
+#ifdef CONFIG_NET_NOINTS
+ struct work_s work; /* For deferring work to the work queue */
+#endif
struct enet_desc_s *txdesc; /* A pointer to the list of TX descriptor */
struct enet_desc_s *rxdesc; /* A pointer to the list of RX descriptors */
@@ -188,7 +240,7 @@ struct kinetis_driver_s
* Private Data
****************************************************************************/
-static struct kinetis_driver_s g_enet[CONFIG_ENET_NETHIFS];
+static struct kinetis_driver_s g_enet[CONFIG_KINETIS_ENETNETHIFS];
/****************************************************************************
* Private Function Prototypes
@@ -218,22 +270,43 @@ static int kinetis_txpoll(struct net_driver_s *dev);
static void kinetis_receive(FAR struct kinetis_driver_s *priv);
static void kinetis_txdone(FAR struct kinetis_driver_s *priv);
+
+static inline void kinetis_interrupt_process(FAR struct kinetis_driver_s *priv);
+#ifdef CONFIG_NET_NOINTS
+static void kinetis_interrupt_work(FAR void *arg);
+#endif
static int kinetis_interrupt(int irq, FAR void *context);
/* Watchdog timer expirations */
-static void kinetis_polltimer(int argc, uint32_t arg, ...);
-static void kinetis_txtimeout(int argc, uint32_t arg, ...);
+static inline void kinetis_txtimeout_process(FAR struct kinetis_driver_s *priv);
+#ifdef CONFIG_NET_NOINTS
+static void kinetis_txtimeout_work(FAR void *arg);
+#endif
+static void kinetis_txtimeout_expiry(int argc, uint32_t arg, ...);
+
+static inline void kinetis_poll_process(FAR struct kinetis_driver_s *priv);
+#ifdef CONFIG_NET_NOINTS
+static void kinetis_poll_work(FAR void *arg);
+#endif
+static void kinetis_polltimer_expiry(int argc, uint32_t arg, ...);
/* NuttX callback functions */
static int kinetis_ifup(struct net_driver_s *dev);
static int kinetis_ifdown(struct net_driver_s *dev);
+
+static inline void kinetis_txavail_process(FAR struct kinetis_driver_s *priv);
+#ifdef CONFIG_NET_NOINTS
+static void kinetis_txavail_work(FAR void *arg);
+#endif
static int kinetis_txavail(struct net_driver_s *dev);
+
#ifdef CONFIG_NET_IGMP
static int kinetis_addmac(struct net_driver_s *dev, FAR const uint8_t *mac);
static int kinetis_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac);
#endif
+
#ifdef CONFIG_NETDEV_PHY_IOCTL
static int kinetis_ioctl(struct net_driver_s *dev, int cmd, long arg);
#endif
@@ -241,7 +314,11 @@ static int kinetis_ioctl(struct net_driver_s *dev, int cmd, long arg);
/* PHY/MII support */
static inline void kinetis_initmii(struct kinetis_driver_s *priv);
-static inline void kinetis_initphy(struct kinetis_driver_s *priv);
+static int kinetis_writemii(struct kinetis_driver_s *priv, uint8_t phyaddr,
+ uint8_t regaddr, uint16_t data);
+static int kinetis_readmii(struct kinetis_driver_s *priv, uint8_t phyaddr,
+ uint8_t regaddr, uint16_t *data);
+static inline int kinetis_initphy(struct kinetis_driver_s *priv);
/* Initialization */
@@ -323,7 +400,7 @@ static bool kinetics_txringfull(FAR struct kinetis_driver_s *priv)
*/
txnext = priv->txhead + 1;
- if (txnext >= CONFIG_ENET_NTXBUFFERS)
+ if (txnext >= CONFIG_KINETIS_ENETNTXBUFFERS)
{
txnext = 0;
}
@@ -375,7 +452,7 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv)
txdesc = &priv->txdesc[priv->txhead];
priv->txhead++;
- if (priv->txhead >= CONFIG_ENET_NTXBUFFERS)
+ if (priv->txhead >= CONFIG_KINETIS_ENETNTXBUFFERS)
{
priv->txhead = 0;
}
@@ -392,7 +469,7 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv)
*/
txdesc->length = kinesis_swap16(priv->dev.d_len);
-#ifdef CONFIG_ENET_ENHANCEDBD
+#ifdef CONFIG_KINETIS_ENETENHANCEDBD
txdesc->bdu = 0x00000000;
txdesc->status2 = TXDESC_INT | TXDESC_TS; /* | TXDESC_IINS | TXDESC_PINS; */
#endif
@@ -426,8 +503,8 @@ static int kinetis_transmit(FAR struct kinetis_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
- (void)wd_start(priv->txtimeout, KINETIS_TXTIMEOUT, kinetis_txtimeout, 1,
- (uint32_t)priv);
+ (void)wd_start(priv->txtimeout, KINETIS_TXTIMEOUT, kinetis_txtimeout_expiry, 1,
+ (wdparm_t)priv);
return OK;
}
@@ -557,7 +634,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllinfo("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
NETDEV_RXIPV4(&priv->dev);
/* Handle ARP on input then give the IPv4 packet to the network
@@ -598,7 +675,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllinfo("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
NETDEV_RXIPV6(&priv->dev);
/* Give the IPv6 packet to the network layer */
@@ -668,7 +745,7 @@ static void kinetis_receive(FAR struct kinetis_driver_s *priv)
/* Update the index to the next descriptor */
priv->rxtail++;
- if (priv->rxtail >= CONFIG_ENET_NRXBUFFERS)
+ if (priv->rxtail >= CONFIG_KINETIS_ENETNRXBUFFERS)
{
priv->rxtail = 0;
}
@@ -708,7 +785,7 @@ static void kinetis_txdone(FAR struct kinetis_driver_s *priv)
/* Yes.. bump up the tail pointer, making space for a new TX descriptor */
priv->txtail++;
- if (priv->txtail >= CONFIG_ENET_NTXBUFFERS)
+ if (priv->txtail >= CONFIG_KINETIS_ENETNTXBUFFERS)
{
priv->txtail = 0;
}
@@ -739,28 +816,25 @@ static void kinetis_txdone(FAR struct kinetis_driver_s *priv)
}
/****************************************************************************
- * Function: kinetis_interrupt
+ * Function: kinetis_interrupt_process
*
* Description:
- * Three interrupt sources will vector this this function:
- * 1. Ethernet MAC transmit interrupt handler
- * 2. Ethernet MAC receive interrupt handler
- * 3.
+ * Interrupt processing. This may be performed either within the interrupt
+ * handler or on the worker thread, depending upon the configuration
*
* Parameters:
- * irq - Number of the IRQ that generated the interrupt
- * context - Interrupt register state save info (architecture-specific)
+ * priv - Reference to the driver state structure
*
* Returned Value:
- * OK on success
+ * None
*
* Assumptions:
+ * The network is locked.
*
****************************************************************************/
-static int kinetis_interrupt(int irq, FAR void *context)
+static inline void kinetis_interrupt_process(FAR struct kinetis_driver_s *priv)
{
- register FAR struct kinetis_driver_s *priv = &g_enet[0];
uint32_t pending;
/* Get the set of unmasked, pending interrupt. */
@@ -810,33 +884,130 @@ static int kinetis_interrupt(int irq, FAR void *context)
putreg32(ENET_RDAR, KINETIS_ENET_RDAR);
}
-
- return OK;
}
/****************************************************************************
- * Function: kinetis_txtimeout
+ * Function: kinetis_interrupt_work
*
* Description:
- * Our TX watchdog timed out. Called from the timer interrupt handler.
- * The last TX never completed. Reset the hardware and start again.
+ * Perform interrupt related work from the worker thread
*
* Parameters:
- * argc - The number of available arguments
- * arg - The first argument
+ * arg - The argument passed when work_queue() was called.
*
* Returned Value:
- * None
+ * OK on success
*
* Assumptions:
- * Global interrupts are disabled by the watchdog logic.
+ * The network is locked.
*
****************************************************************************/
-static void kinetis_txtimeout(int argc, uint32_t arg, ...)
+#ifdef CONFIG_NET_NOINTS
+static void kinetis_interrupt_work(FAR void *arg)
{
FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg;
+ net_lock_t state;
+
+ /* Process pending Ethernet interrupts */
+
+ state = net_lock();
+ kinetis_interrupt_process(priv);
+ net_unlock(state);
+ /* Re-enable Ethernet interrupts */
+
+#if 0
+ up_enable_irq(KINETIS_IRQ_EMACTMR);
+#endif
+ up_enable_irq(KINETIS_IRQ_EMACTX);
+ up_enable_irq(KINETIS_IRQ_EMACRX);
+ up_enable_irq(KINETIS_IRQ_EMACMISC);
+}
+#endif
+
+/****************************************************************************
+ * Function: kinetis_interrupt
+ *
+ * Description:
+ * Three interrupt sources will vector this this function:
+ * 1. Ethernet MAC transmit interrupt handler
+ * 2. Ethernet MAC receive interrupt handler
+ * 3.
+ *
+ * Parameters:
+ * irq - Number of the IRQ that generated the interrupt
+ * context - Interrupt register state save info (architecture-specific)
+ *
+ * Returned Value:
+ * OK on success
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int kinetis_interrupt(int irq, FAR void *context)
+{
+ register FAR struct kinetis_driver_s *priv = &g_enet[0];
+
+#ifdef CONFIG_NET_NOINTS
+ /* Disable further Ethernet interrupts. Because Ethernet interrupts are
+ * also disabled if the TX timeout event occurs, there can be no race
+ * condition here.
+ */
+
+ up_disable_irq(KINETIS_IRQ_EMACTMR);
+ up_disable_irq(KINETIS_IRQ_EMACTX);
+ up_disable_irq(KINETIS_IRQ_EMACRX);
+ up_disable_irq(KINETIS_IRQ_EMACMISC);
+
+ /* TODO: Determine if a TX transfer just completed */
+
+ {
+ /* If a TX transfer just completed, then cancel the TX timeout so
+ * there will be do race condition between any subsequent timeout
+ * expiration and the deferred interrupt processing.
+ */
+
+ wd_cancel(priv->txtimeout);
+ }
+
+ /* Cancel any pending poll work */
+
+ work_cancel(HPWORK, &priv->work);
+
+ /* Schedule to perform the interrupt processing on the worker thread. */
+
+ work_queue(HPWORK, &priv->work, kinetis_interrupt_work, priv, 0);
+
+#else
+ /* Process the interrupt now */
+
+ kinetis_interrupt_process(priv);
+#endif
+
+ return OK;
+}
+
+/****************************************************************************
+ * Function: kinetis_txtimeout_process
+ *
+ * Description:
+ * Process a TX timeout. Called from the either the watchdog timer
+ * expiration logic or from the worker thread, depending upon the
+ * configuration. The timeout means that the last TX never completed.
+ * Reset the hardware and start again.
+ *
+ * Parameters:
+ * priv - Reference to the driver state structure
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static inline void kinetis_txtimeout_process(FAR struct kinetis_driver_s *priv)
+{
/* Increment statistics and dump debug info */
NETDEV_TXTIMEOUTS(&priv->dev);
@@ -854,10 +1025,42 @@ static void kinetis_txtimeout(int argc, uint32_t arg, ...)
}
/****************************************************************************
- * Function: kinetis_polltimer
+ * Function: kinetis_txtimeout_work
*
* Description:
- * Periodic timer handler. Called from the timer interrupt handler.
+ * Perform TX timeout related work from the worker thread
+ *
+ * Parameters:
+ * arg - The argument passed when work_queue() as called.
+ *
+ * Returned Value:
+ * OK on success
+ *
+ * Assumptions:
+ * The network is locked.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NET_NOINTS
+static void kinetis_txtimeout_work(FAR void *arg)
+{
+ FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg;
+ net_lock_t state;
+
+ /* Process pending Ethernet interrupts */
+
+ state = net_lock();
+ kinetis_txtimeout_process(priv);
+ net_unlock(state);
+}
+#endif
+
+/****************************************************************************
+ * Function: kinetis_txtimeout_expiry
+ *
+ * Description:
+ * Our TX watchdog timed out. Called from the timer interrupt handler.
+ * The last TX never completed. Reset the hardware and start again.
*
* Parameters:
* argc - The number of available arguments
@@ -871,10 +1074,56 @@ static void kinetis_txtimeout(int argc, uint32_t arg, ...)
*
****************************************************************************/
-static void kinetis_polltimer(int argc, uint32_t arg, ...)
+static void kinetis_txtimeout_expiry(int argc, uint32_t arg, ...)
{
FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg;
+#ifdef CONFIG_NET_NOINTS
+ /* Disable further Ethernet interrupts. This will prevent some race
+ * conditions with interrupt work. There is still a potential race
+ * condition with interrupt work that is already queued and in progress.
+ */
+
+ up_disable_irq(KINETIS_IRQ_EMACTMR);
+ up_disable_irq(KINETIS_IRQ_EMACTX);
+ up_disable_irq(KINETIS_IRQ_EMACRX);
+ up_disable_irq(KINETIS_IRQ_EMACMISC);
+
+ /* Cancel any pending poll or interrupt work. This will have no effect
+ * on work that has already been started.
+ */
+
+ work_cancel(HPWORK, &priv->work);
+
+ /* Schedule to perform the TX timeout processing on the worker thread. */
+
+ work_queue(HPWORK, &priv->work, kinetis_txtimeout_work, priv, 0);
+#else
+ /* Process the timeout now */
+
+ kinetis_txtimeout_process(priv);
+#endif
+}
+
+/****************************************************************************
+ * Function: kinetis_poll_process
+ *
+ * Description:
+ * Perform the periodic poll. This may be called either from watchdog
+ * timer logic or from the worker thread, depending upon the configuration.
+ *
+ * Parameters:
+ * priv - Reference to the driver state structure
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static inline void kinetis_poll_process(FAR struct kinetis_driver_s *priv)
+{
/* Check if there is there is a transmission in progress. We cannot perform
* the TX poll if he are unable to accept another packet for transmission.
*/
@@ -891,7 +1140,89 @@ static void kinetis_polltimer(int argc, uint32_t arg, ...)
/* Setup the watchdog poll timer again in any case */
- (void)wd_start(priv->txpoll, KINETIS_WDDELAY, kinetis_polltimer, 1, arg);
+ (void)wd_start(priv->txpoll, KINETIS_WDDELAY, kinetis_polltimer_expiry,
+ 1, (wdparm_t)priv);
+}
+
+/****************************************************************************
+ * Function: kinetis_poll_work
+ *
+ * Description:
+ * Perform periodic polling from the worker thread
+ *
+ * Parameters:
+ * arg - The argument passed when work_queue() as called.
+ *
+ * Returned Value:
+ * OK on success
+ *
+ * Assumptions:
+ * The network is locked.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NET_NOINTS
+static void kinetis_poll_work(FAR void *arg)
+{
+ FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg;
+ net_lock_t state;
+
+ /* Perform the poll */
+
+ state = net_lock();
+ kinetis_poll_process(priv);
+ net_unlock(state);
+}
+#endif
+
+/****************************************************************************
+ * Function: kinetis_polltimer_expiry
+ *
+ * Description:
+ * Periodic timer handler. Called from the timer interrupt handler.
+ *
+ * Parameters:
+ * argc - The number of available arguments
+ * arg - The first argument
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ * Global interrupts are disabled by the watchdog logic.
+ *
+ ****************************************************************************/
+
+static void kinetis_polltimer_expiry(int argc, uint32_t arg, ...)
+{
+ FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg;
+
+#ifdef CONFIG_NET_NOINTS
+ /* Is our single work structure available? It may not be if there are
+ * pending interrupt actions.
+ */
+
+ if (work_available(&priv->work))
+ {
+ /* Schedule to perform the interrupt processing on the worker thread. */
+
+ work_queue(HPWORK, &priv->work, kinetis_poll_work, priv, 0);
+ }
+ else
+ {
+ /* No.. Just re-start the watchdog poll timer, missing one polling
+ * cycle.
+ */
+
+ (void)wd_start(priv->txpoll, KINETIS_WDDELAY, kinetis_polltimer_expiry,
+ 1, (wdparm_t)arg);
+ }
+
+#else
+ /* Process the interrupt now */
+
+ kinetis_poll_process(priv);
+#endif
}
/****************************************************************************
@@ -917,6 +1248,7 @@ static int kinetis_ifup(struct net_driver_s *dev)
(FAR struct kinetis_driver_s *)dev->d_private;
uint8_t *mac = dev->d_mac.ether_addr_octet;
uint32_t regval;
+ int ret;
ninfo("Bringing up: %d.%d.%d.%d\n",
dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
@@ -949,7 +1281,12 @@ static int kinetis_ifup(struct net_driver_s *dev)
/* Configure the PHY */
- kinetis_initphy(priv);
+ ret = kinetis_initphy(priv);
+ if (ret < 0)
+ {
+ nerr("ERROR: Failed to configure the PHY: %d\n", ret);
+ return ret;
+ }
/* Handle promiscuous mode */
@@ -961,7 +1298,7 @@ static int kinetis_ifup(struct net_driver_s *dev)
/* Select legacy of enhanced buffer descriptor format */
-#ifdef CONFIG_ENET_ENHANCEDBD
+#ifdef CONFIG_KINETIS_ENETENHANCEDBD
putreg32(ENET_ECR_EN1588, KINETIS_ENET_ECR);
#else
putreg32(0, KINETIS_ENET_ECR);
@@ -995,8 +1332,8 @@ static int kinetis_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
- (void)wd_start(priv->txpoll, KINETIS_WDDELAY, kinetis_polltimer, 1,
- (uint32_t)priv);
+ (void)wd_start(priv->txpoll, KINETIS_WDDELAY, kinetis_polltimer_expiry, 1,
+ (wdparm_t)priv);
/* Clear all pending ENET interrupt */
@@ -1072,15 +1409,13 @@ static int kinetis_ifdown(struct net_driver_s *dev)
}
/****************************************************************************
- * Function: kinetis_txavail
+ * Function: kinetis_txavail_process
*
* Description:
- * Driver callback invoked when new TX data is available. This is a
- * stimulus perform an out-of-cycle poll and, thereby, reduce the TX
- * latency.
+ * Perform an out-of-cycle poll.
*
* Parameters:
- * dev - Reference to the NuttX driver state structure
+ * dev - Reference to the NuttX driver state structure
*
* Returned Value:
* None
@@ -1090,20 +1425,13 @@ static int kinetis_ifdown(struct net_driver_s *dev)
*
****************************************************************************/
-static int kinetis_txavail(struct net_driver_s *dev)
+static inline void kinetis_txavail_process(FAR struct kinetis_driver_s *priv)
{
- FAR struct kinetis_driver_s *priv =
- (FAR struct kinetis_driver_s *)dev->d_private;
- irqstate_t flags;
-
- /* Disable interrupts because this function may be called from interrupt
- * level processing.
- */
-
- flags = enter_critical_section();
+ net_lock_t state;
/* Ignore the notification if the interface is not yet up */
+ state = net_lock();
if (priv->bifup)
{
/* Check if there is room in the hardware to hold another outgoing
@@ -1120,7 +1448,80 @@ static int kinetis_txavail(struct net_driver_s *dev)
}
}
- leave_critical_section(flags);
+ net_unlock(state);
+}
+
+/****************************************************************************
+ * Function: kinetis_txavail_work
+ *
+ * Description:
+ * Perform an out-of-cycle poll on the worker thread.
+ *
+ * Parameters:
+ * arg - Reference to the NuttX driver state structure (cast to void*)
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ * Called on the higher priority worker thread.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NET_NOINTS
+static void kinetis_txavail_work(FAR void *arg)
+{
+ FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg;
+
+ /* Perform the poll */
+
+ kinetis_txavail_process(priv);
+}
+#endif
+
+/****************************************************************************
+ * Function: kinetis_txavail
+ *
+ * Description:
+ * Driver callback invoked when new TX data is available. This is a
+ * stimulus perform an out-of-cycle poll and, thereby, reduce the TX
+ * latency.
+ *
+ * Parameters:
+ * dev - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ * Called in normal user mode
+ *
+ ****************************************************************************/
+
+static int kinetis_txavail(struct net_driver_s *dev)
+{
+ FAR struct kinetis_driver_s *priv =
+ (FAR struct kinetis_driver_s *)dev->d_private;
+
+#ifdef CONFIG_NET_NOINTS
+ /* Is our single work structure available? It may not be if there are
+ * pending interrupt actions and we will have to ignore the Tx
+ * availability action.
+ */
+
+ if (work_available(&priv->work))
+ {
+ /* Schedule to serialize the poll on the worker thread. */
+
+ work_queue(HPWORK, &priv->work, kinetis_txavail_work, priv, 0);
+ }
+
+#else
+ /* Perform the out-of-cycle poll now */
+
+ kinetis_txavail_process(priv);
+#endif
+
return OK;
}
@@ -1216,7 +1617,7 @@ static int kinetis_ioctl(struct net_driver_s *dev, int cmd, long arg)
{
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
- req->phy_id = CONFIG_ENET_PHYADDR;
+ req->phy_id = priv->phyaddr;
ret = OK;
}
break;
@@ -1381,6 +1782,7 @@ static int kinetis_readmii(struct kinetis_driver_s *priv, uint8_t phyaddr,
if (timeout >= MII_MAXPOLLS)
{
+ nerr("ERROR: Timed out waiting for transfer to complete\n");
return -ETIMEDOUT;
}
@@ -1404,33 +1806,95 @@ static int kinetis_readmii(struct kinetis_driver_s *priv, uint8_t phyaddr,
* priv - Reference to the private ENET driver state structure
*
* Returned Value:
- * None
+ * Zero (OK) returned on success; a negated errno value is returned on any
+ * failure;
*
* Assumptions:
*
****************************************************************************/
-static inline void kinetis_initphy(struct kinetis_driver_s *priv)
+static inline int kinetis_initphy(struct kinetis_driver_s *priv)
{
uint32_t rcr;
uint32_t tcr;
uint16_t phydata;
+ uint8_t phyaddr;
+ int retries;
+ int ret;
/* Loop (potentially infinitely?) until we successfully communicate with
* the PHY.
*/
- do
+ for (phyaddr = 0; phyaddr < 32; phyaddr++)
{
- usleep(LINK_WAITUS);
- phydata = 0xffff;
- kinetis_readmii(priv, CONFIG_ENET_PHYADDR, MII_PHYID1, &phydata);
+ ninfo("%s: Try phyaddr: %u\n", BOARD_PHY_NAME, phyaddr);
+
+ /* Try to read PHYID1 few times using this address */
+
+ retries = 0;
+ do
+ {
+ usleep(LINK_WAITUS);
+ ninfo("%s: Read PHYID1, retries=%d\n", BOARD_PHY_NAME, retries + 1);
+ phydata = 0xffff;
+ ret = kinetis_readmii(priv, phyaddr, MII_PHYID1, &phydata);
+ }
+ while ((ret < 0 || phydata == 0xffff) && ++retries < 3);
+
+ /* If we successfully read anything then break out, using this PHY address */
+
+ if (retries < 3)
+ {
+ break;
+ }
+ }
+
+ if (phyaddr >= 32)
+ {
+ nerr("ERROR: Failed to read %s PHYID1 at any address\n");
+ return -ENOENT;
+ }
+
+ ninfo("%s: Using PHY address %u\n", BOARD_PHY_NAME, phyaddr);
+ priv->phyaddr = phyaddr;
+
+ /* Verify PHYID1. Compare OUI bits 3-18 */
+
+ ninfo("%s: PHYID1: %04x\n", BOARD_PHY_NAME, phydata);
+ if (phydata != BOARD_PHYID1)
+ {
+ nerr("ERROR: PHYID1=%04x incorrect for %s. Expected %04x\n",
+ phydata, BOARD_PHY_NAME, BOARD_PHYID1);
+ return -ENXIO;
+ }
+
+ /* Read PHYID2 */
+
+ ret = kinetis_readmii(priv, phyaddr, MII_PHYID2, &phydata);
+ if (ret < 0)
+ {
+ nerr("ERROR: Failed to read %s PHYID2: %d\n", BOARD_PHY_NAME, ret);
+ return ret;
+ }
+
+ ninfo("%s: PHYID2: %04x\n", BOARD_PHY_NAME, phydata);
+
+ /* Verify PHYID2: Compare OUI bits 19-24 and the 6-bit model number
+ * (ignoring the 4-bit revision number).
+ */
+
+ if ((phydata & 0xfff0) != (BOARD_PHYID2 & 0xfff0))
+ {
+ nerr("ERROR: PHYID2=%04x incorrect for %s. Expected %04x\n",
+ (phydata & 0xfff0), BOARD_PHY_NAME, (BOARD_PHYID2 & 0xfff0));
+ return -ENXIO;
}
- while (phydata == 0xffff);
/* Start auto negotiation */
- kinetis_writemii(priv, CONFIG_ENET_PHYADDR, MII_MCR,
+ ninfo("%s: Start autonegotiation...\n", BOARD_PHY_NAME);
+ kinetis_writemii(priv, phyaddr, MII_MCR,
(MII_MCR_ANRESTART | MII_MCR_ANENABLE));
/* Wait (potentially forever) for auto negotiation to complete */
@@ -1438,21 +1902,38 @@ static inline void kinetis_initphy(struct kinetis_driver_s *priv)
do
{
usleep(LINK_WAITUS);
- kinetis_readmii(priv, CONFIG_ENET_PHYADDR, MII_MSR, &phydata);
-
+ ret = kinetis_readmii(priv, phyaddr, MII_MSR, &phydata);
+ if (ret < 0)
+ {
+ nerr("ERROR: Failed to read %s MII_MSR: %d\n",
+ BOARD_PHY_NAME, ret);
+ return ret;
+ }
}
while ((phydata & MII_MSR_ANEGCOMPLETE) == 0);
+ ninfo("%s: Autonegotiation complete\n", BOARD_PHY_NAME);
+ ninfo("%s: MII_MSR: %04x\n", BOARD_PHY_NAME, phydata);
+
/* When we get here we have a link - Find the negotiated speed and duplex. */
phydata = 0;
- kinetis_readmii(priv, CONFIG_ENET_PHYADDR, PHY_STATUS, &phydata);
+ ret = kinetis_readmii(priv, phyaddr, BOARD_PHY_STATUS, &phydata);
+ if (ret < 0)
+ {
+ nerr("ERROR: Failed to read %s BOARD_PHY_STATUS{%02x]: %d\n",
+ BOARD_PHY_NAME, BOARD_PHY_STATUS, ret);
+ return ret;
+ }
+
- /* Set up the transmit and receive contrel registers based on the
+ ninfo("%s: BOARD_PHY_STATUS: %04x\n", BOARD_PHY_NAME, phydata);
+
+ /* Set up the transmit and receive control registers based on the
* configuration and the auto negotiation results.
*/
-#ifdef CONFIG_ENET_USEMII
+#ifdef CONFIG_KINETIS_ENETUSEMII
rcr = ENET_RCR_MII_MODE | ENET_RCR_CRCFWD |
CONFIG_NET_ETH_MTU << ENET_RCR_MAX_FL_SHIFT |
ENET_RCR_MII_MODE;
@@ -1468,28 +1949,46 @@ static inline void kinetis_initphy(struct kinetis_driver_s *priv)
/* Setup half or full duplex */
- if ((phydata & PHY_DUPLEX_STATUS) != 0)
+ if (BOARD_PHY_ISDUPLEX(phydata))
{
/* Full duplex */
+ ninfo("%s: Full duplex\n", BOARD_PHY_NAME);
tcr |= ENET_TCR_FDEN;
}
else
{
/* Half duplex */
+ ninfo("%s: Half duplex\n", BOARD_PHY_NAME);
rcr |= ENET_RCR_DRT;
}
- if ((phydata & PHY_SPEED_STATUS) != 0)
+ if (BOARD_PHY_10BASET(phydata))
{
- /* 10Mbps */
+ /* 10 Mbps */
+ ninfo("%s: 10 Base-T\n", BOARD_PHY_NAME);
rcr |= ENET_RCR_RMII_10T;
}
+ else if (!BOARD_PHY_100BASET(phydata))
+ {
+ /* 100 Mbps */
+
+ ninfo("%s: 100 Base-T\n", BOARD_PHY_NAME);
+ }
+ else
+ {
+ /* This might happen if autonegotiation did not complete(?) */
+
+ nerr("ERROR: Neither 10- nor 100-BaseT reported: PHY STATUS=%04x\n",
+ phydata);
+ return -EIO;
+ }
putreg32(rcr, KINETIS_ENET_RCR);
putreg32(tcr, KINETIS_ENET_TCR);
+ return OK;
}
/****************************************************************************
@@ -1520,7 +2019,7 @@ static void kinetis_initbuffers(struct kinetis_driver_s *priv)
/* Get an aligned RX descriptor (array) address */
- addr += CONFIG_ENET_NTXBUFFERS * sizeof(struct enet_desc_s);
+ addr += CONFIG_KINETIS_ENETNTXBUFFERS * sizeof(struct enet_desc_s);
priv->rxdesc = (struct enet_desc_s *)addr;
/* Get the beginning of the first aligned buffer */
@@ -1529,12 +2028,12 @@ static void kinetis_initbuffers(struct kinetis_driver_s *priv)
/* Then fill in the TX descriptors */
- for (i = 0; i < CONFIG_ENET_NTXBUFFERS; i++)
+ for (i = 0; i < CONFIG_KINETIS_ENETNTXBUFFERS; i++)
{
priv->txdesc[i].status1 = 0;
priv->txdesc[i].length = 0;
priv->txdesc[i].data = (uint8_t *)kinesis_swap32((uint32_t)addr);
-#ifdef CONFIG_ENET_ENHANCEDBD
+#ifdef CONFIG_KINETIS_ENETENHANCEDBD
priv->txdesc[i].status2 = TXDESC_IINS | TXDESC_PINS;
#endif
addr += KINETIS_BUF_SIZE;
@@ -1542,12 +2041,12 @@ static void kinetis_initbuffers(struct kinetis_driver_s *priv)
/* Then fill in the RX descriptors */
- for (i = 0; i < CONFIG_ENET_NRXBUFFERS; i++)
+ for (i = 0; i < CONFIG_KINETIS_ENETNRXBUFFERS; i++)
{
priv->rxdesc[i].status1 = RXDESC_E;
priv->rxdesc[i].length = 0;
priv->rxdesc[i].data = (uint8_t *)kinesis_swap32((uint32_t)addr);
-#ifdef CONFIG_ENET_ENHANCEDBD
+#ifdef CONFIG_KINETIS_ENETENHANCEDBD
priv->rxdesc[i].bdu = 0;
priv->rxdesc[i].status2 = RXDESC_INT;
#endif
@@ -1556,8 +2055,8 @@ static void kinetis_initbuffers(struct kinetis_driver_s *priv)
/* Set the wrap bit in the last descriptors to form a ring */
- priv->txdesc[CONFIG_ENET_NTXBUFFERS-1].status1 |= TXDESC_W;
- priv->rxdesc[CONFIG_ENET_NRXBUFFERS-1].status1 |= RXDESC_W;
+ priv->txdesc[CONFIG_KINETIS_ENETNTXBUFFERS-1].status1 |= TXDESC_W;
+ priv->rxdesc[CONFIG_KINETIS_ENETNRXBUFFERS-1].status1 |= RXDESC_W;
/* We start with RX descriptor 0 and with no TX descriptors in use */
@@ -1631,7 +2130,7 @@ int kinetis_netinitialize(int intf)
/* Get the interface structure associated with this interface number. */
- DEBUGASSERT(intf < CONFIG_ENET_NETHIFS);
+ DEBUGASSERT(intf < CONFIG_KINETIS_ENETNETHIFS);
priv = &g_enet[intf];
/* Enable the ENET clock */
@@ -1646,9 +2145,9 @@ int kinetis_netinitialize(int intf)
putreg32(0, KINETIS_MPU_CESR);
+#ifdef CONFIG_KINETIS_ENETUSEMII
/* Configure all ENET/MII pins */
-#ifdef CONFIG_ENET_USEMII
kinetis_pinconfig(PIN_MII0_MDIO);
kinetis_pinconfig(PIN_MII0_MDC);
kinetis_pinconfig(PIN_MII0_RXDV);
@@ -1668,6 +2167,8 @@ int kinetis_netinitialize(int intf)
kinetis_pinconfig(PIN_MII0_CRS);
kinetis_pinconfig(PIN_MII0_COL);
#else
+ /* Use RMII subset */
+
kinetis_pinconfig(PIN_RMII0_MDIO);
kinetis_pinconfig(PIN_RMII0_MDC);
kinetis_pinconfig(PIN_RMII0_CRS_DV);
@@ -1773,7 +2274,7 @@ int kinetis_netinitialize(int intf)
*
****************************************************************************/
-#if CONFIG_ENET_NETHIFS == 1
+#if CONFIG_KINETIS_ENETNETHIFS == 1
void up_netinitialize(void)
{
(void)kinetis_netinitialize(0);
diff --git a/arch/arm/src/kinetis/kinetis_ftfl.h b/arch/arm/src/kinetis/kinetis_ftfl.h
deleted file mode 100644
index 92e53b650d03d2cfbaf6ba3b3cd9427304069d8d..0000000000000000000000000000000000000000
--- a/arch/arm/src/kinetis/kinetis_ftfl.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/************************************************************************************
- * arch/arm/src/kinetis/kinetis_ftfl.h
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_FTFL_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_FTFL_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include
-
-#include "chip.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Register Offsets *****************************************************************/
-
-#define KINETIS_FTFL_FSTAT_OFFSET 0x0000 /* Flash Status Register */
-#define KINETIS_FTFL_FCNFG_OFFSET 0x0001 /* Flash Configuration Register */
-#define KINETIS_FTFL_FSEC_OFFSET 0x0002 /* Flash Security Register */
-#define KINETIS_FTFL_FOPT_OFFSET 0x0003 /* Flash Option Register */
-
-#define KINETIS_FTFL_FCCOB3_OFFSET 0x0004 /* Flash Common Command Object Registers */
-#define KINETIS_FTFL_FCCOB2_OFFSET 0x0005 /* Flash Common Command Object Registers */
-#define KINETIS_FTFL_FCCOB1_OFFSET 0x0006 /* Flash Common Command Object Registers */
-#define KINETIS_FTFL_FCCOB0_OFFSET 0x0007 /* Flash Common Command Object Registers */
-#define KINETIS_FTFL_FCCOB7_OFFSET 0x0008 /* Flash Common Command Object Registers */
-#define KINETIS_FTFL_FCCOB6_OFFSET 0x0009 /* Flash Common Command Object Registers */
-#define KINETIS_FTFL_FCCOB5_OFFSET 0x000a /* Flash Common Command Object Registers */
-#define KINETIS_FTFL_FCCOB4_OFFSET 0x000b /* Flash Common Command Object Registers */
-#define KINETIS_FTFL_FCCOBB_OFFSET 0x000c /* Flash Common Command Object Registers */
-#define KINETIS_FTFL_FCCOBA_OFFSET 0x000d /* Flash Common Command Object Registers */
-#define KINETIS_FTFL_FCCOB9_OFFSET 0x000e /* Flash Common Command Object Registers */
-#define KINETIS_FTFL_FCCOB8_OFFSET 0x000f /* Flash Common Command Object Registers */
-#define KINETIS_FTFL_FPROT3_OFFSET 0x0010 /* Program Flash Protection Registers */
-#define KINETIS_FTFL_FPROT2_OFFSET 0x0011 /* Program Flash Protection Registers */
-#define KINETIS_FTFL_FPROT1_OFFSET 0x0012 /* Program Flash Protection Registers */
-#define KINETIS_FTFL_FPROT0_OFFSET 0x0013 /* Program Flash Protection Registers */
-#define KINETIS_FTFL_FEPROT_OFFSET 0x0016 /* EEPROM Protection Register */
-#define KINETIS_FTFL_FDPROT_OFFSET 0x0017 /* Data Flash Protection Register */
-
-/* Register Addresses ***************************************************************/
-
-#define KINETIS_FTFL_FSTAT (KINETIS_FTFL_BASE+KINETIS_FTFL_FSTAT_OFFSET)
-#define KINETIS_FTFL_FCNFG (KINETIS_FTFL_BASE+KINETIS_FTFL_FCNFG_OFFSET)
-#define KINETIS_FTFL_FSEC (KINETIS_FTFL_BASE+KINETIS_FTFL_FSEC_OFFSET)
-#define KINETIS_FTFL_FOPT (KINETIS_FTFL_BASE+KINETIS_FTFL_FOPT_OFFSET)
-#define KINETIS_FTFL_FCCOB3 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB3_OFFSET)
-#define KINETIS_FTFL_FCCOB2 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB2_OFFSET)
-#define KINETIS_FTFL_FCCOB1 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB1_OFFSET)
-#define KINETIS_FTFL_FCCOB0 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB0_OFFSET)
-#define KINETIS_FTFL_FCCOB7 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB7_OFFSET)
-#define KINETIS_FTFL_FCCOB6 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB6_OFFSET)
-#define KINETIS_FTFL_FCCOB5 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB5_OFFSET)
-#define KINETIS_FTFL_FCCOB4 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB4_OFFSET)
-#define KINETIS_FTFL_FCCOBB (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOBB_OFFSET)
-#define KINETIS_FTFL_FCCOBA (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOBA_OFFSET)
-#define KINETIS_FTFL_FCCOB9 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB9_OFFSET)
-#define KINETIS_FTFL_FCCOB8 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB8_OFFSET)
-#define KINETIS_FTFL_FPROT3 (KINETIS_FTFL_BASE+KINETIS_FTFL_FPROT3_OFFSET)
-#define KINETIS_FTFL_FPROT2 (KINETIS_FTFL_BASE+KINETIS_FTFL_FPROT2_OFFSET)
-#define KINETIS_FTFL_FPROT1 (KINETIS_FTFL_BASE+KINETIS_FTFL_FPROT1_OFFSET)
-#define KINETIS_FTFL_FPROT0 (KINETIS_FTFL_BASE+KINETIS_FTFL_FPROT0_OFFSET)
-#define KINETIS_FTFL_FEPROT (KINETIS_FTFL_BASE+KINETIS_FTFL_FEPROT_OFFSET)
-#define KINETIS_FTFL_FDPROT (KINETIS_FTFL_BASE+KINETIS_FTFL_FDPROT_OFFSET)
-
-/* Register Bit Definitions *********************************************************/
-
-/* Flash Status Register */
-
-#define FTFL_FSTAT_MGSTAT0 (1 << 0) /* Bit 0: Memory Controller Command Completion Status Flag */
- /* Bits 1-3: Reserved */
-#define FTFL_FSTAT_FPVIOL (1 << 4) /* Bit 4: Flash Protection Violation Flag */
-#define FTFL_FSTAT_ACCERR (1 << 5) /* Bit 5: Flash Access Error Flag */
-#define FTFL_FSTAT_RDCOLERR (1 << 6) /* Bit 6: FTFL Read Collision Error Flag */
-#define FTFL_FSTAT_CCIF (1 << 7) /* Bit 7: Command Complete Interrupt Flag */
-
-/* Flash Configuration Register */
-
-#define FTFL_FCNFG_EEERDY (1 << 0) /* Bit 0: FEEPROM backup data copied to FlexRAM */
-#define FTFL_FCNFG_RAMRDY (1 << 1) /* Bit 1: RAM Ready */
-#define FTFL_FCNFG_PFLSH (1 << 2) /* Bit 2: FTFL configuration */
-#define FTFL_FCNFG_SWAP (1 << 3) /* Bit 3: Swap */
-#define FTFL_FCNFG_ERSSUSP (1 << 4) /* Bit 4: Erase Suspend */
-#define FTFL_FCNFG_ERSAREQ (1 << 5) /* Bit 5: Erase All Request */
-#define FTFL_FCNFG_RDCOLLIE (1 << 6) /* Bit 6: Read Collision Error Interrupt Enable */
-#define FTFL_FCNFG_CCIE (1 << 7) /* Bit 7: Command Complete Interrupt Enable */
-
-/* Flash Security Register */
-
-#define FTFL_FSEC_SEC_SHIFT (0) /* Bits 0-1: Flash Security */
-#define FTFL_FSEC_SEC_MASK (3 << FTFL_FSEC_SEC_SHIFT)
-# define FTFL_FSEC_SEC_SECURE (0 << FTFL_FSEC_SEC_SHIFT) /* 00,01,11: status is secure */
-# define FTFL_FSEC_SEC_UNSECURE (2 << FTFL_FSEC_SEC_SHIFT) /* 10: status is insecure */
-#define FTFL_FSEC_FSLACC_SHIFT (2) /* Bits 2-3: Freescale Failure Analysis Access Code */
-#define FTFL_FSEC_FSLACC_MASK (3 << FTFL_FSEC_FSLACC_SHIFT)
-# define FTFL_FSEC_FSLACC_GRANTED (0 << FTFL_FSEC_FSLACC_SHIFT) /* 00 or 11: Access granted */
-# define FTFL_FSEC_FSLACC_DENIED (1 << FTFL_FSEC_FSLACC_SHIFT) /* 01 or 10: Access denied */
-#define FTFL_FSEC_MEEN_SHIFT (4) /* Bits 4-5: Mass Erase Enable Bits */
-#define FTFL_FSEC_MEEN_MASK (3 << FTFL_FSEC_MEEN_SHIFT)
-# define FTFL_FSEC_MEEN_ENABLED (0 << FTFL_FSEC_MEEN_SHIFT) /* All values are enabled */
-#define FTFL_FSEC_KEYEN_SHIFT (6) /* Bits 6-7: Backdoor Key Security Enable */
-#define FTFL_FSEC_KEYEN_MASK (3 << FTFL_FSEC_KEYEN_SHIFT)
-# define FTFL_FSEC_KEYEN_DISABLED (1 << FTFL_FSEC_KEYEN_SHIFT) /* All values are disabled */
-
-/* Flash Option Register (32-bits, see Chip Configuration details) */
-/* Flash Common Command Object Registers (8-bit flash command data) */
-/* Program Flash Protection Registers (8-bit flash protection data) */
-/* EEPROM Protection Register (8-bit eeprom protection data) */
-/* Data Flash Protection Register (8-bit data flash protection data) */
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_FTFL_H */
diff --git a/arch/arm/src/kinetis/kinetis_i2c.c b/arch/arm/src/kinetis/kinetis_i2c.c
new file mode 100644
index 0000000000000000000000000000000000000000..1713bdbbb1d64d7f326620d83d97c6418867fbbe
--- /dev/null
+++ b/arch/arm/src/kinetis/kinetis_i2c.c
@@ -0,0 +1,1151 @@
+/****************************************************************************
+ * arch/arm/src/kinetis/kinetis_i2c.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Matias v01d
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "kinetis_config.h"
+#include "chip.h"
+#include "chip/kinetis_i2c.h"
+#include "chip/kinetis_sim.h"
+#include "chip/kinetis_pinmux.h"
+#include "kinetis.h"
+#include "kinetis_i2c.h"
+
+#if defined(CONFIG_KINETIS_I2C0) || defined(CONFIG_KINETIS_I2C1) || \
+ defined(CONFIG_KINETIS_I2C2)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define I2C_TIMEOUT (20*1000/CONFIG_USEC_PER_TICK) /* 20 mS */
+
+#define I2C_DEFAULT_FREQUENCY 400000
+
+#define STATE_OK 0
+#define STATE_ARBITRATION_ERROR 1
+#define STATE_TIMEOUT 2
+#define STATE_NAK 3
+
+/* TODO:
+ * - revisar tamanio de todos los registros (getreg/putreg)
+ */
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* I2C device state structure */
+
+struct kinetis_i2cdev_s
+{
+ struct i2c_master_s dev; /* Generic I2C device */
+ uintptr_t base; /* Base address of registers */
+ uint32_t basefreq; /* Branch frequency */
+ uint32_t frequency; /* Current I2C frequency */
+ uint16_t irqid; /* IRQ for this device */
+ uint16_t nmsg; /* Number of transfer remaining */
+ uint16_t wrcnt; /* number of bytes sent to tx fifo */
+ uint16_t rdcnt; /* number of bytes read from rx fifo */
+ volatile uint8_t state; /* State of state machine */
+ bool restart; /* Should next transfer restart or not */
+ sem_t mutex; /* Only one thread can access at a time */
+ sem_t wait; /* Place to wait for state machine completion */
+ WDOG_ID timeout; /* watchdog to timeout when bus hung */
+ struct i2c_msg_s *msgs; /* Remaining transfers - first one is in
+ * progress */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Register access */
+
+static uint8_t kinetis_i2c_getreg(struct kinetis_i2cdev_s *priv,
+ uint8_t offset);
+static void kinetis_i2c_putreg(struct kinetis_i2cdev_s *priv,
+ uint8_t value, uint8_t offset);
+
+/* I2C helpers */
+
+static void kinetis_i2c_setfrequency(struct kinetis_i2cdev_s *priv,
+ uint32_t frequency);
+static int kinetis_i2c_start(struct kinetis_i2cdev_s *priv);
+static void kinetis_i2c_stop(struct kinetis_i2cdev_s *priv);
+static int kinetis_i2c_interrupt(struct kinetis_i2cdev_s *priv);
+#ifdef CONFIG_KINETIS_I2C0
+static int kinetis_i2c0_interrupt(int irq, void *context);
+#endif
+#ifdef CONFIG_KINETIS_I2C1
+static int kinetis_i2c1_interrupt(int irq, void *context);
+#endif
+#ifdef CONFIG_KINETIS_I2C2
+static int kinetis_i2c2_interrupt(int irq, void *context);
+#endif
+static void kinetis_i2c_timeout(int argc, uint32_t arg, ...);
+static void kinetis_i2c_setfrequency(struct kinetis_i2cdev_s *priv,
+ uint32_t frequency);
+
+/* I2C lower half driver methods */
+
+static int kinetis_i2c_transfer(struct i2c_master_s *dev,
+ struct i2c_msg_s *msgs, int count);
+#ifdef CONFIG_I2C_RESET
+static int kinetis_i2c_reset(struct i2c_master_s *dev);
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* I2C lower half driver operations */
+
+static const struct i2c_ops_s g_i2c_ops =
+{
+ .transfer = kinetis_i2c_transfer
+#ifdef CONFIG_I2C_RESET
+ ,.reset = kinetis_i2c_reset
+#endif
+};
+
+/* I2C device state instances */
+
+#ifdef CONFIG_KINETIS_I2C0
+static struct kinetis_i2cdev_s g_i2c0_dev;
+#endif
+#ifdef CONFIG_KINETIS_I2C1
+static struct kinetis_i2cdev_s g_i2c1_dev;
+#endif
+#ifdef CONFIG_KINETIS_I2C2
+static struct kinetis_i2cdev_s g_i2c2_dev;
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: kinetis_i2c_getreg
+ *
+ * Description:
+ * Get a 16-bit register value by offset
+ *
+ ****************************************************************************/
+
+static uint8_t kinetis_i2c_getreg(struct kinetis_i2cdev_s *priv,
+ uint8_t offset)
+{
+ return getreg8(priv->base + offset);
+}
+
+/****************************************************************************
+ * Name: kinetis_i2c_putreg
+ *
+ * Description:
+ * Put a 16-bit register value by offset
+ *
+ ****************************************************************************/
+
+static void kinetis_i2c_putreg(struct kinetis_i2cdev_s *priv, uint8_t offset,
+ uint8_t value)
+{
+ putreg8(value, priv->base + offset);
+}
+
+/****************************************************************************
+ * Name: kinetis_i2c_setfrequency
+ *
+ * Description:
+ * Set the frequency for the next transfer
+ *
+ ****************************************************************************/
+
+static void kinetis_i2c_setfrequency(struct kinetis_i2cdev_s *priv,
+ uint32_t frequency)
+{
+ i2cinfo("frequency=%lu\n", (unsigned long)frequency);
+
+ if (frequency == priv->frequency)
+ {
+ return;
+ }
+
+#if BOARD_BUS_FREQ == 120000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV1152, KINETIS_I2C_F_OFFSET); /* 104 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV288, KINETIS_I2C_F_OFFSET); /* 416 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV128, KINETIS_I2C_F_OFFSET); /* 0.94 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 108000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV1024, KINETIS_I2C_F_OFFSET); /* 105 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV256, KINETIS_I2C_F_OFFSET); /* 422 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV112, KINETIS_I2C_F_OFFSET); /* 0.96 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 96000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV960, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV240, KINETIS_I2C_F_OFFSET); /* 400 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV96, KINETIS_I2C_F_OFFSET); /* 1.0 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 90000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV896, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV224, KINETIS_I2C_F_OFFSET); /* 402 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV88, KINETIS_I2C_F_OFFSET); /* 1.02 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 80000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV768, KINETIS_I2C_F_OFFSET); /* 104 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV192, KINETIS_I2C_F_OFFSET); /* 416 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV80, KINETIS_I2C_F_OFFSET); /* 1.0 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 72000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV640, KINETIS_I2C_F_OFFSET); /* 112 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV192, KINETIS_I2C_F_OFFSET); /* 375 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV72, KINETIS_I2C_F_OFFSET); /* 1.0 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 64000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV640, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV160, KINETIS_I2C_F_OFFSET); /* 400 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV64, KINETIS_I2C_F_OFFSET); /* 1.0 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 60000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV576, KINETIS_I2C_F_OFFSET); /* 104 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV144, KINETIS_I2C_F_OFFSET); /* 416 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV64, KINETIS_I2C_F_OFFSET); /* 938 kHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 56000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV512, KINETIS_I2C_F_OFFSET); /* 109 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV144, KINETIS_I2C_F_OFFSET); /* 389 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV56_1, KINETIS_I2C_F_OFFSET); /* 1 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 54000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV512, KINETIS_I2C_F_OFFSET); /* 105 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV128, KINETIS_I2C_F_OFFSET); /* 422 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV56, KINETIS_I2C_F_OFFSET); /* 0.96 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 48000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV480, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV112, KINETIS_I2C_F_OFFSET); /* 400 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV48_1, KINETIS_I2C_F_OFFSET); /* 1 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(4), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 40000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV384_2, KINETIS_I2C_F_OFFSET); /* 104 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV96, KINETIS_I2C_F_OFFSET); /* 416 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV40_2, KINETIS_I2C_F_OFFSET); /* 1 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(3), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 36000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV320_2, KINETIS_I2C_F_OFFSET); /* 113 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV96, KINETIS_I2C_F_OFFSET); /* 375 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV36, KINETIS_I2C_F_OFFSET); /* 1 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(3), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 24000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV240, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV64, KINETIS_I2C_F_OFFSET); /* 375 kHz */
+ }
+ else
+ {161
+ kinetis_i2c_putreg(priv, I2C_F_DIV24, KINETIS_I2C_F_OFFSET); /* 1 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(2), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 16000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV160_2, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ }
+ else if (frequency < 1000000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV40_1, KINETIS_I2C_F_OFFSET); /* 400 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV20, KINETIS_I2C_F_OFFSET); /* 800 MHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(1), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 8000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV80_1, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV20, KINETIS_I2C_F_OFFSET); /* 400 kHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(1), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 4000000
+ if (frequency < 400000)
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV40_1, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ }
+ else
+ {
+ kinetis_i2c_putreg(priv, I2C_F_DIV20, KINETIS_I2C_F_OFFSET); /* 200 kHz */
+ }
+
+ kinetis_i2c_putreg(priv, I2C_FLT(1), KINETIS_I2C_FLT_OFFSET);
+
+#elif BOARD_BUS_FREQ == 2000000
+ kinetis_i2c_putreg(priv, I2C_F_DIV20, KINETIS_I2C_F_OFFSET); /* 100 kHz */
+ kinetis_i2c_putreg(priv, I2C_FLT(1), KINETIS_I2C_FLT_OFFSET);
+
+#else
+# error "F_BUS must be 120, 108, 96, 9, 80, 72, 64, 60, 56, 54, 48, 40, 36, 24, 16, 8, 4 or 2 MHz"
+#endif
+
+ priv->frequency = frequency;
+}
+
+/****************************************************************************
+ * Name: kinetis_i2c_start
+ *
+ * Description:
+ * Initiate I2C transfer (START/RSTART + address)
+ *
+ ****************************************************************************/
+
+static int kinetis_i2c_start(struct kinetis_i2cdev_s *priv)
+{
+ struct i2c_msg_s *msg;
+
+ i2cinfo("START msg=%p\n", priv->msgs);
+ msg = priv->msgs;
+
+ /* Now take control of the bus */
+
+ if (kinetis_i2c_getreg(priv, KINETIS_I2C_C1_OFFSET) & I2C_C1_MST)
+ {
+ /* We are already the bus master, so send a repeated start */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE | I2C_C1_MST |
+ I2C_C1_RSTA | I2C_C1_TX, KINETIS_I2C_C1_OFFSET);
+ }
+ else
+ {
+ /* We are not currently the bus master, so wait for bus ready */
+
+ while (kinetis_i2c_getreg(priv, KINETIS_I2C_S_OFFSET) & I2C_S_BUSY);
+
+ /* Become the bus master in transmit mode (send start) */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE | I2C_C1_MST |
+ I2C_C1_TX, KINETIS_I2C_C1_OFFSET);
+ }
+
+ if (I2C_M_READ & msg->flags) /* DEBUG: should happen always */
+ {
+ /* Wait until start condition establishes control of the bus */
+
+ while (1)
+ {
+ if (kinetis_i2c_getreg(priv, KINETIS_I2C_S_OFFSET) & I2C_S_BUSY)
+ {
+ break;
+ }
+ }
+ }
+
+ /* Initiate actual transfer (send address) */
+
+ kinetis_i2c_putreg(priv, (I2C_M_READ & msg->flags) == I2C_M_READ ?
+ I2C_READADDR8(msg->addr) : I2C_WRITEADDR8(msg->addr),
+ KINETIS_I2C_D_OFFSET);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: kinetis_i2c_stop
+ *
+ * Description:
+ * Perform a I2C transfer stop
+ *
+ ****************************************************************************/
+
+static void kinetis_i2c_stop(struct kinetis_i2cdev_s *priv)
+{
+ i2cinfo("STOP msg=%p\n", priv->msgs);
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE,
+ KINETIS_I2C_C1_OFFSET);
+ sem_post(&priv->wait);
+}
+
+/****************************************************************************
+ * Name: kinetis_i2c_timeout
+ *
+ * Description:
+ * Watchdog timer for timeout of I2C operation
+ *
+ ****************************************************************************/
+
+static void kinetis_i2c_timeout(int argc, uint32_t arg, ...)
+{
+ struct kinetis_i2cdev_s *priv = (struct kinetis_i2cdev_s *)arg;
+
+ DEBUGASSERT(priv != NULL);
+ i2cinfo("Timeout msg=%p\n", priv->msgs);
+
+ irqstate_t flags = enter_critical_section();
+ priv->state = STATE_TIMEOUT;
+ sem_post(&priv->wait);
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: kinetis_i2c_nextmsg
+ *
+ * Description:
+ * Setup for the next message.
+ *
+ ****************************************************************************/
+
+void kinetis_i2c_nextmsg(struct kinetis_i2cdev_s *priv)
+{
+ priv->nmsg--;
+ i2cinfo("nmsg=%u\n", priv->nmsg);
+
+ if (priv->nmsg > 0)
+ {
+ priv->msgs++;
+ i2cinfo("msg=%p\n", priv->msgs);
+
+ priv->wrcnt = 0;
+ priv->rdcnt = 0;
+
+ if (priv->restart)
+ {
+ sem_post(&priv->wait);
+ }
+ }
+ else
+ {
+ kinetis_i2c_stop(priv);
+ }
+}
+
+/****************************************************************************
+ * Name: kinetis_i2c_interrupt
+ *
+ * Description:
+ * The I2C common interrupt handler
+ *
+ ****************************************************************************/
+
+static int kinetis_i2c_interrupt(struct kinetis_i2cdev_s *priv)
+{
+ struct i2c_msg_s *msg;
+ uint32_t state;
+ int regval;
+ int dummy;
+ UNUSED(dummy);
+
+ /* Get current state */
+
+ state = kinetis_i2c_getreg(priv, KINETIS_I2C_S_OFFSET);
+ msg = priv->msgs;
+
+ /* Arbitration lost */
+
+ if (state & I2C_S_ARBL)
+ {
+ kinetis_i2c_putreg(priv, I2C_S_IICIF | I2C_S_ARBL,
+ KINETIS_I2C_S_OFFSET);
+ priv->state = STATE_ARBITRATION_ERROR;
+ kinetis_i2c_stop(priv);
+ }
+ else
+ {
+ /* Clear interrupt */
+
+ kinetis_i2c_putreg(priv, I2C_S_IICIF, KINETIS_I2C_S_OFFSET);
+ regval = kinetis_i2c_getreg(priv, KINETIS_I2C_C1_OFFSET);
+
+ /* TX mode */
+
+ if (regval & I2C_C1_TX)
+ {
+ /* Last write was not acknowledged */
+
+ if (state & I2C_S_RXAK)
+ {
+ priv->state = STATE_NAK; /* Set error flag */
+ kinetis_i2c_stop(priv); /* Send STOP */
+ }
+ else
+ {
+ /* Actually intending to write */
+
+ if ((I2C_M_READ & msg->flags) == 0)
+ {
+ /* Wrote everything */
+
+ if (priv->wrcnt == msg->length)
+ {
+ /* Continue with next message */
+
+ kinetis_i2c_nextmsg(priv);
+
+ if (!priv->restart)
+ {
+ /* Initiate transfer of following message */
+
+ kinetis_i2c_putreg(priv,
+ priv->msgs->buffer[priv->wrcnt],
+ KINETIS_I2C_D_OFFSET);
+ priv->wrcnt++;
+
+ sem_post(&priv->wait);
+ }
+ }
+ else
+ {
+ /* Put next byte */
+
+ kinetis_i2c_putreg(priv, msg->buffer[priv->wrcnt],
+ KINETIS_I2C_D_OFFSET);
+ priv->wrcnt++;
+ }
+ }
+
+ /* Actually intending to read (address was just sent) */
+
+ else
+ {
+ if (msg->length == 1 && priv->restart)
+ {
+ /* Go to RX mode, do not send ACK */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE |
+ I2C_C1_MST | I2C_C1_TXAK,
+ KINETIS_I2C_C1_OFFSET);
+ }
+ else
+ {
+ /* Go to RX mode */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE |
+ I2C_C1_MST, KINETIS_I2C_C1_OFFSET);
+ }
+
+ /* TODO: handle zero-length reads */
+ /* Dummy read to initiate reception */
+
+ dummy = kinetis_i2c_getreg(priv, KINETIS_I2C_D_OFFSET);
+ }
+ }
+ }
+
+ /* RX: mode */
+
+ else
+ {
+ /* If last receiving byte */
+
+ if (priv->rdcnt == (msg->length - 1))
+ {
+ if (priv->restart)
+ {
+ /* Go to TX mode before last read, otherwise a new read is
+ * triggered.
+ */
+
+ /* Go to TX mode */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE |
+ I2C_C1_MST | I2C_C1_TX,
+ KINETIS_I2C_C1_OFFSET);
+ }
+ else if ((priv->msgs + 1)->length == 1)
+ {
+ /* We will continue reception on next message.
+ * if next message is length == 1, this is actually the
+ * 2nd to last byte, so do not send ACK.
+ */
+
+ /* Do not ACK any more */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE |
+ I2C_C1_MST | I2C_C1_TXAK,
+ KINETIS_I2C_C1_OFFSET);
+ }
+
+ msg->buffer[priv->rdcnt] =
+ kinetis_i2c_getreg(priv, KINETIS_I2C_D_OFFSET);
+ priv->rdcnt++;
+
+ kinetis_i2c_nextmsg(priv);
+ }
+
+ /* Second to last receiving byte */
+
+ else if (priv->rdcnt == (msg->length - 2))
+ {
+ if (priv->restart)
+ {
+ /* Do not ACK any more */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN | I2C_C1_IICIE |
+ I2C_C1_MST | I2C_C1_TXAK, KINETIS_I2C_C1_OFFSET);
+ }
+
+ msg->buffer[priv->rdcnt] =
+ kinetis_i2c_getreg(priv, KINETIS_I2C_D_OFFSET);
+ priv->rdcnt++;
+ }
+ else
+ {
+ msg->buffer[priv->rdcnt] =
+ kinetis_i2c_getreg(priv, KINETIS_I2C_D_OFFSET);
+ priv->rdcnt++;
+ }
+ }
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: kinetis_i2cN_interrupt
+ *
+ * Description:
+ * The I2CN interrupt handlers
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_KINETIS_I2C0
+static int kinetis_i2c0_interrupt(int irq, void *context)
+{
+ i2cinfo("I2C0 Interrupt...\n");
+ return kinetis_i2c_interrupt(&g_i2c0_dev);
+}
+#endif
+
+#ifdef CONFIG_KINETIS_I2C1
+static int kinetis_i2c1_interrupt(int irq, void *context)
+{
+ i2cinfo("I2C1 Interrupt...\n");
+ return kinetis_i2c_interrupt(&g_i2c1_dev);
+}
+#endif
+
+#ifdef CONFIG_KINETIS_I2C2
+static int kinetis_i2c2_interrupt(int irq, void *context)
+{
+ i2cinfo("I2C2 Interrupt...\n");
+ return kinetis_i2c_interrupt(&g_i2c2_dev);
+}
+#endif
+
+/****************************************************************************
+ * Name: kinetis_i2c_transfer
+ *
+ * Description:
+ * Perform a sequence of I2C transfers
+ *
+ ****************************************************************************/
+
+static int kinetis_i2c_transfer(struct i2c_master_s *dev,
+ struct i2c_msg_s *msgs, int count)
+{
+ struct kinetis_i2cdev_s *priv = (struct kinetis_i2cdev_s *)dev;
+ int msg_n;
+
+ i2cinfo("msgs=%p count=%d\n", msgs, count);
+ DEBUGASSERT(dev != NULL && msgs != NULL && (unsigned)count <= UINT16_MAX);
+
+ /* Get exclusive access to the I2C bus */
+
+ sem_wait(&priv->mutex);
+
+ /* Set up for the transfer */
+
+ msg_n = 0;
+ priv->msgs = msgs;
+ priv->nmsg = count;
+ priv->state = STATE_OK;
+ priv->wrcnt = 0;
+ priv->rdcnt = 0;
+
+ /* Configure the I2C frequency. REVISIT: Note that the frequency is set
+ * only on the first message. This could be extended to support
+ * different transfer frequencies for each message segment.
+ */
+
+ kinetis_i2c_setfrequency(priv, msgs->frequency);
+
+ /* Clear the status flags */
+
+ kinetis_i2c_putreg(priv, I2C_S_IICIF | I2C_S_ARBL, KINETIS_I2C_S_OFFSET);
+
+ /* Process every message */
+
+ while (priv->nmsg > 0 && priv->state == STATE_OK)
+ {
+ priv->restart = true;
+
+ /* Process NORESTART flag */
+
+ if (priv->nmsg > 1)
+ {
+ struct i2c_msg_s* nextmsg = (priv->msgs + 1);
+
+ /* If there is a following message with "norestart" flag of
+ * the same type as the current one, we can avoid the restart
+ */
+
+ if ((nextmsg->flags & I2C_M_NORESTART) &&
+ nextmsg->addr == priv->msgs->addr &&
+ nextmsg->frequency == priv->msgs->frequency &&
+ (nextmsg->flags & I2C_M_READ) == (priv->msgs->flags & I2C_M_READ))
+ {
+ /* "no restart" can be performed */
+
+ priv->restart = false;
+ }
+ }
+
+ /* Only send start when required (we are trusting the flags setting to
+ * be correctly used here).
+ */
+
+ if (!(priv->msgs->flags & I2C_M_NORESTART))
+ {
+ /* Initiate the transfer, in case restart is required */
+
+ kinetis_i2c_start(priv);
+ }
+
+ /* Wait for transfer complete */
+
+ wd_start(priv->timeout, I2C_TIMEOUT, kinetis_i2c_timeout, 1,
+ (uint32_t) priv);
+ sem_wait(&priv->wait);
+
+ wd_cancel(priv->timeout);
+
+ msg_n++;
+ }
+
+ /* Disable interrupts */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN, KINETIS_I2C_C1_OFFSET);
+
+ /* Release access to I2C bus */
+
+ sem_post(&priv->mutex);
+
+ if (priv->state != STATE_OK)
+ {
+ return -EIO;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+/************************************************************************************
+ * Name: kinetis_i2c_reset
+ *
+ * Description:
+ * Perform an I2C bus reset in an attempt to break loose stuck I2C devices.
+ *
+ * Input Parameters:
+ * dev - Device-specific state data
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno value on failure.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_I2C_RESET
+static int kinetis_i2c_reset(struct i2c_master_s *dev)
+{
+ i2cinfo("No reset...\n");
+ return OK;
+}
+#endif /* CONFIG_I2C_RESET */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: kinetis_i2cbus_initialize
+ *
+ * Description:
+ * Initialise an I2C device
+ *
+ ****************************************************************************/
+
+struct i2c_master_s *kinetis_i2cbus_initialize(int port)
+{
+ struct kinetis_i2cdev_s *priv;
+ xcpt_t handler;
+
+ i2cinfo("port=%d\n", port);
+
+ if (port > 1)
+ {
+ i2cerr("ERROR: Kinetis I2C Only suppors ports 0 and 1\n");
+ return NULL;
+ }
+
+ irqstate_t flags;
+ uint32_t regval;
+
+ flags = enter_critical_section();
+
+#ifdef CONFIG_KINETIS_I2C0
+ if (port == 0)
+ {
+ priv = &g_i2c0_dev;
+ priv->base = KINETIS_I2C0_BASE;
+ priv->irqid = KINETIS_IRQ_I2C0;
+ priv->basefreq = BOARD_BUS_FREQ;
+
+ handler = kinetis_i2c0_interrupt;
+
+ /* Enable clock */
+
+ regval = getreg32(KINETIS_SIM_SCGC4);
+ regval |= SIM_SCGC4_I2C0;
+ putreg32(regval, KINETIS_SIM_SCGC4);
+
+ /* Disable while configuring */
+
+ kinetis_i2c_putreg(priv, 0, KINETIS_I2C_C1_OFFSET);
+
+ /* Configure pins */
+
+ kinetis_pinconfig(PIN_I2C0_SCL);
+ kinetis_pinconfig(PIN_I2C0_SDA);
+ }
+ else
+#endif
+#ifdef CONFIG_KINETIS_I2C1
+ if (port == 1)
+ {
+ priv = &g_i2c1_dev;
+ priv->base = KINETIS_I2C1_BASE;
+ priv->irqid = KINETIS_IRQ_I2C1;
+ priv->basefreq = BOARD_BUS_FREQ;
+
+ handler = kinetis_i2c1_interrupt;
+
+ /* Enable clock */
+
+ regval = getreg32(KINETIS_SIM_SCGC4);
+ regval |= SIM_SCGC4_I2C1;
+ putreg32(regval, KINETIS_SIM_SCGC4);
+
+ /* Disable while configuring */
+
+ kinetis_i2c_putreg(priv, 0, KINETIS_I2C_C1_OFFSET);
+
+ /* Configure pins */
+
+ kinetis_pinconfig(PIN_I2C1_SCL);
+ kinetis_pinconfig(PIN_I2C1_SDA);
+ }
+ else
+#endif
+#ifdef CONFIG_KINETIS_I2C2
+ if (port == 2)
+ {
+ priv = &g_i2c2_dev;
+ priv->base = KINETIS_I2C2_BASE;
+ priv->irqid = KINETIS_IRQ_I2C2;
+ priv->basefreq = BOARD_BUS_FREQ;
+
+ handler = kinetis_i2c2_interrupt;
+
+ /* Enable clock */
+
+ regval = getreg32(KINETIS_SIM_SCGC4);
+ regval |= SIM_SCGC4_I2C2;
+ putreg32(regval, KINETIS_SIM_SCGC4);
+
+ /* Disable while configuring */
+
+ kinetis_i2c_putreg(priv, 0, KINETIS_I2C_C1_OFFSET);
+
+ /* Configure pins */
+
+ kinetis_pinconfig(PIN_I2C2_SCL);
+ kinetis_pinconfig(PIN_I2C2_SDA);
+ }
+ else
+#endif
+ {
+ leave_critical_section(flags);
+ i2cerr("ERROR: Unsupport I2C bus: %d\n", port);
+ return NULL;
+ }
+
+ /* Set the default I2C frequency */
+
+ kinetis_i2c_setfrequency(priv, I2C_DEFAULT_FREQUENCY);
+
+ /* Enable */
+
+ kinetis_i2c_putreg(priv, I2C_C1_IICEN, KINETIS_I2C_C1_OFFSET);
+
+ /* High-drive select (TODO: why)? */
+
+ regval = kinetis_i2c_getreg(priv, KINETIS_I2C_C2_OFFSET);
+ regval |= I2C_C2_HDRS;
+ kinetis_i2c_putreg(priv, regval, KINETIS_I2C_C2_OFFSET);
+
+ leave_critical_section(flags);
+
+ sem_init(&priv->mutex, 0, 1);
+ sem_init(&priv->wait, 0, 0);
+
+ /* Allocate a watchdog timer */
+
+ priv->timeout = wd_create();
+ DEBUGASSERT(priv->timeout != 0);
+
+ /* Attach Interrupt Handler */
+
+ irq_attach(priv->irqid, handler);
+
+ /* Enable Interrupt Handler */
+
+ up_enable_irq(priv->irqid);
+
+ /* Install our operations */
+
+ priv->dev.ops = &g_i2c_ops;
+ return &priv->dev;
+}
+
+/****************************************************************************
+ * Name: kinetis_i2cbus_uninitialize
+ *
+ * Description:
+ * Uninitialise an I2C device
+ *
+ ****************************************************************************/
+
+int kinetis_i2cbus_uninitialize(struct i2c_master_s *dev)
+{
+ struct kinetis_i2cdev_s *priv = (struct kinetis_i2cdev_s *)dev;
+
+ DEBUGASSERT(priv != NULL);
+
+ kinetis_i2c_putreg(priv, 0, KINETIS_I2C_C1_OFFSET);
+
+ up_disable_irq(priv->irqid);
+ irq_detach(priv->irqid);
+ return OK;
+}
+
+#endif /* CONFIG_KINETIS_I2C0 || CONFIG_KINETIS_I2C1 || CONFIG_KINETIS_I2C2 */
diff --git a/arch/arm/src/kinetis/kinetis_i2c.h b/arch/arm/src/kinetis/kinetis_i2c.h
index bee9ef92db16c19ffe2dc0eb1815140211295345..098e4d39add5981788688eff46db049908210a33 100644
--- a/arch/arm/src/kinetis/kinetis_i2c.h
+++ b/arch/arm/src/kinetis/kinetis_i2c.h
@@ -1,8 +1,8 @@
-/********************************************************************************************
+/****************************************************************************
* arch/arm/src/kinetis/kinetis_i2c.h
*
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Matias v01d
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -31,155 +31,57 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ********************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_I2CE_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_I2CE_H
+#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_I2C_H
+#define __ARCH_ARM_SRC_KINETIS_KINETIS_I2C_H
-/********************************************************************************************
+/****************************************************************************
* Included Files
- ********************************************************************************************/
+ ****************************************************************************/
#include
+#include
+#include "chip/kinetis_i2c.h"
-#include "chip.h"
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
-/********************************************************************************************
- * Pre-processor Definitions
- ********************************************************************************************/
-
-/* Register Offsets *************************************************************************/
-
-#define KINETIS_I2C_A1_OFFSET 0x0000 /* I2C Address Register 1 */
-#define KINETIS_I2C_F_OFFSET 0x0001 /* I2C Frequency Divider register */
-#define KINETIS_I2C_C1_OFFSET 0x0002 /* I2C Control Register 1 */
-#define KINETIS_I2C_S_OFFSET 0x0003 /* I2C Status Register */
-#define KINETIS_I2C_D_OFFSET 0x0004 /* I2C Data I/O register */
-#define KINETIS_I2C_C2_OFFSET 0x0005 /* I2C Control Register 2 */
-#define KINETIS_I2C_FLT_OFFSET 0x0006 /* I2C Programmable Input Glitch Filter register */
-#define KINETIS_I2C_RA_OFFSET 0x0007 /* I2C Range Address register */
-#define KINETIS_I2C_SMB_OFFSET 0x0008 /* I2C SMBus Control and Status register */
-#define KINETIS_I2C_A2_OFFSET 0x0009 /* I2C Address Register 2 */
-#define KINETIS_I2C_SLTH_OFFSET 0x000a /* I2C SCL Low Timeout Register High */
-#define KINETIS_I2C_SLTL_OFFSET 0x000b /* I2C SCL Low Timeout Register Low */
-
-/* Register Addresses ***********************************************************************/
-
-#define KINETIS_I2C0_A1 (KINETIS_I2C0_BASE+KINETIS_I2C_A1_OFFSET)
-#define KINETIS_I2C0_F (KINETIS_I2C0_BASE+KINETIS_I2C_F_OFFSET)
-#define KINETIS_I2C0_C1 (KINETIS_I2C0_BASE+KINETIS_I2C_C1_OFFSET)
-#define KINETIS_I2C0_S (KINETIS_I2C0_BASE+KINETIS_I2C_S_OFFSET)
-#define KINETIS_I2C0_D (KINETIS_I2C0_BASE+KINETIS_I2C_D_OFFSET)
-#define KINETIS_I2C0_C2 (KINETIS_I2C0_BASE+KINETIS_I2C_C2_OFFSET)
-#define KINETIS_I2C0_FLT (KINETIS_I2C0_BASE+KINETIS_I2C_FLT_OFFSET)
-#define KINETIS_I2C0_RA (KINETIS_I2C0_BASE+KINETIS_I2C_RA_OFFSET)
-#define KINETIS_I2C0_SMB (KINETIS_I2C0_BASE+KINETIS_I2C_SMB_OFFSET)
-#define KINETIS_I2C0_A2 (KINETIS_I2C0_BASE+KINETIS_I2C_A2_OFFSET)
-#define KINETIS_I2C0_SLTH (KINETIS_I2C0_BASE+KINETIS_I2C_SLTH_OFFSET)
-#define KINETIS_I2C0_SLTL (KINETIS_I2C0_BASE+KINETIS_I2C_SLTL_OFFSET)
-
-#define KINETIS_I2C1_A1 (KINETIS_I2C1_BASE+KINETIS_I2C_A1_OFFSET)
-#define KINETIS_I2C1_F (KINETIS_I2C1_BASE+KINETIS_I2C_F_OFFSET)
-#define KINETIS_I2C1_C1 (KINETIS_I2C1_BASE+KINETIS_I2C_C1_OFFSET)
-#define KINETIS_I2C1_S (KINETIS_I2C1_BASE+KINETIS_I2C_S_OFFSET)
-#define KINETIS_I2C1_D (KINETIS_I2C1_BASE+KINETIS_I2C_D_OFFSET)
-#define KINETIS_I2C1_C2 (KINETIS_I2C1_BASE+KINETIS_I2C_C2_OFFSET)
-#define KINETIS_I2C1_FLT (KINETIS_I2C1_BASE+KINETIS_I2C_FLT_OFFSET)
-#define KINETIS_I2C1_RA (KINETIS_I2C1_BASE+KINETIS_I2C_RA_OFFSET)
-#define KINETIS_I2C1_SMB (KINETIS_I2C1_BASE+KINETIS_I2C_SMB_OFFSET)
-#define KINETIS_I2C1_A2 (KINETIS_I2C1_BASE+KINETIS_I2C_A2_OFFSET)
-#define KINETIS_I2C1_SLTH (KINETIS_I2C1_BASE+KINETIS_I2C_SLTH_OFFSET)
-#define KINETIS_I2C1_SLTL (KINETIS_I2C1_BASE+KINETIS_I2C_SLTL_OFFSET)
-
-/* Register Bit Definitions *****************************************************************/
-
-/* I2C Address Register 1 (8-bit) */
- /* Bit 0: Reserved */
-#define I2C_A1_SHIFT (1) /* Bits 1-7: Address */
-#define I2C_A1_MASK (0x7f << I2C_A1_SHIFT)
-
-/* I2C Frequency Divider register (8-bit) */
-
-#define I2C_F_ICR_SHIFT (0) /* Bits 0-5: Clock rate */
-#define I2C_F_ICR_MASK (0x3f << I2C_F_ICR_SHIFT)
-#define I2C_F_MULT_SHIFT (6) /* Bits 6-7: Multiplier factor */
-#define I2C_F_MULT_MASK (3 << I2C_F_MULT_SHIFT)
-# define I2C_F_MULT_1 (0 << I2C_F_MULT_SHIFT)
-# define I2C_F_MULT_2 (1 << I2C_F_MULT_SHIFT)
-# define I2C_F_MULT_4 (2 << I2C_F_MULT_SHIFT)
-
-/* I2C Control Register 1 (8-bit) */
-
-#define I2C_C1_DMAEN (1 << 0) /* Bit 0: DMA enable */
-#define I2C_C1_WUEN (1 << 1) /* Bit 1: Wakeup enable */
-#define I2C_C1_RSTA (1 << 2) /* Bit 2: Repeat START */
-#define I2C_C1_TXAK (1 << 3) /* Bit 3: Transmit acknowledge enable */
-#define I2C_C1_TX (1 << 4) /* Bit 4: Transmit mode select */
-#define I2C_C1_MST (1 << 5) /* Bit 5: Master mode select */
-#define I2C_C1_IICIE (1 << 6) /* Bit 6: I2C interrupt enable */
-#define I2C_C1_IICEN (1 << 7) /* Bit 7: I2C enable */
-
-/* I2C Status Register (8-bit) */
-
-#define I2C_S_RXAK (1 << 0) /* Bit 0: Receive acknowledge */
-#define I2C_S_IICIF (1 << 1) /* Bit 1: Interrupt flag */
-#define I2C_S_SRW (1 << 2) /* Bit 2: Slave read/write */
-#define I2C_S_RAM (1 << 3) /* Bit 3: Range address match */
-#define I2C_S_ARBL (1 << 4) /* Bit 4: Arbitration lost */
-#define I2C_S_BUSY (1 << 5) /* Bit 5: Bus busy */
-#define I2C_S_IAAS (1 << 6) /* Bit 6: Addressed as a slave */
-#define I2C_S_TCF (1 << 7) /* Bit 7: Transfer complete flag */
-
-/* I2C Data I/O register (8-bit data register) */
-
-/* I2C Control Register 2 (8-bit) */
-
-#define I2C_C2_AD_SHIFT (0) /* Bits 0-2: Slave address */
-#define I2C_C2_AD_MASK (7 << I2C_C2_AD_SHIFT)
-#define I2C_C2_RMEN (1 << 3) /* Bit 3: Range address matching enable */
-#define I2C_C2_SBRC (1 << 4) /* Bit 4: Slave baud rate control */
-#define I2C_C2_HDRS (1 << 5) /* Bit 5: High drive select */
-#define I2C_C2_ADEXT (1 << 6) /* Bit 6: Address extension */
-#define I2C_C2_GCAEN (1 << 7) /* Bit 7: General call address enable */
-
-/* I2C Programmable Input Glitch Filter register (8-bit) */
- /* Bits 5-7: Reserved */
-#define I2C_FLT_SHIFT (0) /* Bits 0-4: I2C programmable filter factor */
-#define I2C_FLT_MASK (31 << I2C_FLT_SHIFT)
-
-/* I2C Range Address register (8-bit) */
- /* Bit 0: Reserved */
-#define I2C_RA_SHIFT (1) /* Bits 1-7: Range slave address */
-#define I2C_RA_MASK (0x7f << I2C_RA_SHIFT)
-
-/* I2C SMBus Control and Status register (8-bit) */
-
-#define I2C_SMB_SHTF2IE (1 << 0) /* Bit 0: SHTF2 interrupt enable */
-#define I2C_SMB_SHTF2 (1 << 1) /* Bit 1: SCL high timeout flag 2 */
-#define I2C_SMB_SHTF1 (1 << 2) /* Bit 2: SCL high timeout flag 1 */
-#define I2C_SMB_SLTF (1 << 3) /* Bit 3: SCL low timeout flag */
-#define I2C_SMB_TCKSEL (1 << 4) /* Bit 4: Timeout counter clock select */
-#define I2C_SMB_SIICAEN (1 << 5) /* Bit 5: Second I2C address enable */
-#define I2C_SMB_ALERTEN (1 << 6) /* Bit 6: SMBus alert response address enable */
-#define I2C_SMB_FACK (1 << 7) /* Bit 7: Fast NACK/ACK enable */
-
-/* I2C Address Register 2 (8-bit) */
- /* Bit 0: Reserved */
-#define I2C_A2_SHIFT (1) /* Bits 1-7: SMBus address */
-#define I2C_A2_MASK (0x7f << I2C_A2_SHIFT)
-
-/* I2C SCL Low Timeout Register High/Low (16-bit data in two 8-bit registers) */
+/****************************************************************************
+ * Name: kinetis_i2cbus_initialize
+ *
+ * Description:
+ * Initialize the selected I2C port. And return a unique instance of struct
+ * struct i2c_master_s. This function may be called to obtain multiple
+ * instances of the interface, each of which may be set up with a
+ * different frequency and slave address.
+ *
+ * Input Parameter:
+ * Port number (for hardware that has multiple I2C interfaces)
+ *
+ * Returned Value:
+ * Valid I2C device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
-/********************************************************************************************
- * Public Types
- ********************************************************************************************/
+FAR struct i2c_master_s *kinetis_i2cbus_initialize(int port);
-/********************************************************************************************
- * Public Data
- ********************************************************************************************/
+/****************************************************************************
+ * Name: kinetis_i2cbus_uninitialize
+ *
+ * Description:
+ * De-initialize the selected I2C port, and power down the device.
+ *
+ * Input Parameter:
+ * Device structure as returned by the lpc43_i2cbus_initialize()
+ *
+ * Returned Value:
+ * OK on success, ERROR when internal reference count mismatch or dev
+ * points to invalid hardware device.
+ *
+ ****************************************************************************/
-/********************************************************************************************
- * Public Functions
- ********************************************************************************************/
+int kinetis_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_I2CE_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_I2C_H */
diff --git a/arch/arm/src/kinetis/kinetis_irq.c b/arch/arm/src/kinetis/kinetis_irq.c
index d2a04de3ae6c1e9e6fe51f345fa9ee18774e5b05..a969bbacd7abbabf1d2ac3347fda9d3d585a71b8 100644
--- a/arch/arm/src/kinetis/kinetis_irq.c
+++ b/arch/arm/src/kinetis/kinetis_irq.c
@@ -439,7 +439,7 @@ void up_irqinitialize(void)
* configured pin interrupts.
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KINETIS_GPIOIRQ
kinetis_pinirqinitialize();
#endif
diff --git a/arch/arm/src/kinetis/kinetis_lowputc.c b/arch/arm/src/kinetis/kinetis_lowputc.c
index bd3b27a8769bd97d4945ad5d32e2d6e3637bfd52..ec85713c9331564ff3c7a2c6baed916ef561faff 100644
--- a/arch/arm/src/kinetis/kinetis_lowputc.c
+++ b/arch/arm/src/kinetis/kinetis_lowputc.c
@@ -49,9 +49,9 @@
#include "kinetis_config.h"
#include "kinetis.h"
-#include "kinetis_uart.h"
-#include "kinetis_sim.h"
-#include "kinetis_pinmux.h"
+#include "chip/kinetis_uart.h"
+#include "chip/kinetis_sim.h"
+#include "chip/kinetis_pinmux.h"
/****************************************************************************
* Pre-processor Definitions
diff --git a/arch/arm/src/kinetis/kinetis_memorymap.h b/arch/arm/src/kinetis/kinetis_memorymap.h
deleted file mode 100644
index 1e7d2820de451ebfd117c086c31a2de30e2ba3ff..0000000000000000000000000000000000000000
--- a/arch/arm/src/kinetis/kinetis_memorymap.h
+++ /dev/null
@@ -1,461 +0,0 @@
-/************************************************************************************
- * arch/arm/src/kinetis/kinetis_memorymap.h
- *
- * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MEMORYMAP_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_MEMORYMAP_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include
-
-#include "chip.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Memory Map ***********************************************************************/
-/* K20 Family
- *
- * The memory map for the following parts is defined in Freescale document
- * K20P64M72SF1RM
- */
-
-#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
-
-# define KINETIS_FLASH_BASE 0x00000000 /* –0x0fffffff Program flash and read-
- * only data (Includes exception
- * vectors in first 1024 bytes) */
-# if !defined(KINETIS_FLEXMEM_SIZE)
-# define KINETIS_FLEXNVM_BASE 0x10000000 /* –0x13ffffff FlexNVM */
-# define KINETIS_FLEXRAM_BASE 0x14000000 /* –0x17ffffff FlexRAM */
-# endif
- /* 0x18000000 * –0x1bffffff Reserved */
-# define KINETIS_SRAML_BASE 0x1c000000 /* –0x1fffffff SRAM_L: Lower SRAM
- * (ICODE/DCODE) */
-# define KINETIS_SRAMU_BASE 0x20000000 /* –0x200fffff SRAM_U: Upper SRAM bitband
- * region */
- /* 0x20100000 * –0x21ffffff Reserved */
-# define KINETIS_SALIAS_BASE 0x22000000 /* –0x23ffffff Aliased to SRAM_U bitband */
- /* 0x24000000 * –0x3fffffff Reserved */
-# define KINETIS_BRIDGE0_BASE 0x40000000 /* –0x4007ffff Bitband region for peripheral
- * bridge 0 (AIPS-Lite0) */
-# define KINETIS_BRIDGE1_BASE 0x40080000 /* –0x400fffff Bitband region for peripheral
- * bridge 1 (AIPS-Lite1) */
-# define KINETIS_GPIOBB_BASE 0x400ff000 /* –0x400fffff Bitband region for general
- * purpose input/output (GPIO) */
- /* 0x40100000 * –0x41ffffff Reserved */
-# define KINETIS_PALIAS_BASE 0x42000000 /* –0x43ffffff Aliased to peripheral bridge
- * (AIPS-Lite) and general purpose
- * input/output (GPIO) bitband */
- /* 0x44000000 * –0xdfffffff Reserved */
-# define KINETIS_PERIPH_BASE 0xe0000000 /* –0xe00fffff Private peripherals */
- /* 0xe0100000 * –0xffffffff Reserved */
-
-/* Peripheral Bridge 0 Memory Map ***************************************************/
-
-# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
-# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
-# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
-# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
-# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
-# define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */
-# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */
-# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
-# define KINETIS_SPI0_BASE 0x4002c000 /* SPI 0 */
-# define KINETIS_SPI1_BASE 0x4002d000 /* SPI 1 */
-# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
-# define KINETIS_CRC_BASE 0x40032000 /* CRC */
-# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
-# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
-# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
-# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer 0 */
-# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer 1 */
-# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
-# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
-# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
-# define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
-# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
-# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
-# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
-# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
-# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
-# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
-# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
-# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
-# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
-# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
-# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
-# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
-# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
-# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
-# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (OSC) */
-# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
-# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
-# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
-# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
-# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
-# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
-# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
-# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
-# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
-# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
-# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
-
-/* Peripheral Bridge 1 Memory Map ***************************************************/
-
-# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
-# define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */
-# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
-# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
-
-# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
- * purpose input/output module that shares the
- * crossbar switch slave port with the AIPS-Lite
- * is accessed at this address. */
-# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
-# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
-# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
-# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
-# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
-# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
-
-/* Private Peripheral Bus (PPB) Memory Map ******************************************/
-
-# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
-# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
-# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
-# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
-# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
-# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
-# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
-
-/* Memory Map ***********************************************************************/
-/* K40 Family
- *
- * The memory map for the following parts is defined in Freescale document
- * K40P144M100SF2RM
- */
-
-#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
-
-# define KINETIS_FLASH_BASE 0x00000000 /* 0x0fffffff Program flash and read-
- * only data (Includes exception
- * vectors in first 1024 bytes) */
-# if !defined(KINETIS_FLEXMEM_SIZE)
-# define KINETIS_FLEXNVM_BASE 0x10000000 /* 0x13ffffff FlexNVM */
-# define KINETIS_FLEXRAM_BASE 0x14000000 /* 0x17ffffff FlexRAM */
-# endif
-# define KINETIS_SRAML_BASE 0x18000000 /* 0x1fffffff SRAM_L: Lower SRAM
- * (ICODE/DCODE) */
-# define KINETIS_SRAMU_BASE 0x20000000 /* 0x200fffff SRAM_U: Upper SRAM bitband
- * region */
- /* 0x20100000 * 0x21ffffff Reserved */
-# define KINETIS_SALIAS_BASE 0x22000000 /* 0x23ffffff Aliased to SRAM_U bitband */
- /* 0x24000000 * 0x3fffffff Reserved */
-# define KINETIS_BRIDGE0_BASE 0x40000000 /* 0x4007ffff Bitband region for peripheral
- * bridge 0 (AIPS-Lite0) */
-# define KINETIS_BRIDGE1_BASE 0x40080000 /* 0x400fffff Bitband region for peripheral
- * bridge 1 (AIPS-Lite1) */
-# define KINETIS_GPIOBB_BASE 0x400ff000 /* 0x400fffff Bitband region for general
- * purpose input/output (GPIO) */
- /* 0x40100000 * 0x41ffffff Reserved */
-# define KINETIS_PALIAS_BASE 0x42000000 /* 0x43ffffff Aliased to peripheral bridge
- * (AIPS-Lite) and general purpose
- * input/output (GPIO) bitband */
- /* 0x44000000 * 0x5fffffff Reserved */
-# define KINETIS_FLEXBUS_WBBASE 0x60000000 /* 0x7fffffff FlexBus (External Memory -
- * Write-back) */
-# define KINETIS_FLEXBUS_WTBASE 0x80000000 /* 0x9fffffff FlexBus (External Memory -
- * Write-through) */
-# define KINETIS_FLEXBUS_NXBASE 0xa0000000 /* 0xdfffffff FlexBus (External Memory -
- * Non-executable) */
-# define KINETIS_PERIPH_BASE 0xe0000000 /* 0xe00fffff Private peripherals */
- /* 0xe0100000 * 0xffffffff Reserved */
-
-/* Peripheral Bridge 0 Memory Map ***************************************************/
-
-# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
-# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
-# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
-# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
-# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
-# define KINETIS_MPU_BASE 0x4000d000 /* MPU */
-# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
-# define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */
-# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */
-# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
-# define KINETIS_SPI0_BASE 0x4002c000 /* SPI 0 */
-# define KINETIS_SPI1_BASE 0x4002d000 /* SPI 1 */
-# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
-# define KINETIS_CRC_BASE 0x40032000 /* CRC */
-# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
-# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
-# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
-# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer 0 */
-# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer 1 */
-# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
-# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
-# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
-# define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
-# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
-# define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
-# define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */
-# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
-# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
-# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
-# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
-# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
-# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
-# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
-# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
-# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
-# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
-# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
-# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
-# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
-# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (OSC) */
-# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
-# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
-# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
-# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
-# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
-# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
-# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
-# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
-# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
-# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
-# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
-# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
-
-/* Peripheral Bridge 1 Memory Map ***************************************************/
-
-# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
-# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
-# define KINETIS_SPI2_BASE 0x400ac000 /* SPI 2 */
-# define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */
-# define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */
-# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
-# define KINETIS_SLCD_BASE 0x400be000 /* Segment LCD */
-# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
-# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
-# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
-# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */
-# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
- * purpose input/output module that shares the
- * crossbar switch slave port with the AIPS-Lite
- * is accessed at this address. */
-# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
-# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
-# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
-# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
-# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
-# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
-
-/* Private Peripheral Bus (PPB) Memory Map ******************************************/
-
-# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
-# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
-# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
-# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
-# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
-# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
-# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
-# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
-# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
-# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
-
-/* Memory Map ***********************************************************************/
-/* K60 Family
- *
- * The memory map for the following parts is defined in Freescale document
- * K60P144M100SF2RM
- */
-
-#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) || defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) || \
- defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK60N256VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK60X256VMD100) || defined(CONFIG_ARCH_CHIP_MK60N512VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK60N512VLL100)
-
-# define KINETIS_FLASH_BASE 0x00000000 /* 0x0fffffff Program flash and read-
- * only data (Includes exception
- * vectors in first 1024 bytes) */
-# if !defined(KINETIS_FLEXMEM_SIZE)
-# define KINETIS_FLEXNVM_BASE 0x10000000 /* 0x13ffffff FlexNVM */
-# define KINETIS_FLEXRAM_BASE 0x14000000 /* 0x17ffffff FlexRAM */
-# endif
-# define KINETIS_SRAML_BASE 0x18000000 /* 0x1fffffff SRAM_L: Lower SRAM
- * (ICODE/DCODE) */
-# define KINETIS_SRAMU_BASE 0x20000000 /* 0x200fffff SRAM_U: Upper SRAM bitband
- * region */
- /* 0x20100000 * 0x21ffffff Reserved */
-# define KINETIS_SALIAS_BASE 0x22000000 /* 0x23ffffff Aliased to SRAM_U bitband */
- /* 0x24000000 * 0x3fffffff Reserved */
-# define KINETIS_BRIDGE0_BASE 0x40000000 /* 0x4007ffff Bitband region for peripheral
- * bridge 0 (AIPS-Lite0) */
-# define KINETIS_BRIDGE1_BASE 0x40080000 /* 0x400fffff Bitband region for peripheral
- * bridge 1 (AIPS-Lite1) */
-# define KINETIS_GPIOBB_BASE 0x400ff000 /* 0x400fffff Bitband region for general
- * purpose input/output (GPIO) */
- /* 0x40100000 * 0x41ffffff Reserved */
-# define KINETIS_PALIAS_BASE 0x42000000 /* 0x43ffffff Aliased to peripheral bridge
- * (AIPS-Lite) and general purpose
- * input/output (GPIO) bitband */
- /* 0x44000000 * 0x5fffffff Reserved */
-# define KINETIS_FLEXBUS_BASE 0x60000000 /* 0x7fffffff FlexBus */
-# define KINETIS_PERIPH_BASE 0xe0000000 /* 0xe00fffff Private peripherals */
- /* 0xe0100000 * 0xffffffff Reserved */
-
-/* Peripheral Bridge 0 Memory Map ***************************************************/
-
-# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
-# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
-# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
-# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
-# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
-# define KINETIS_MPU_BASE 0x4000d000 /* MPU */
-# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
-# define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */
-# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */
-# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
-# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */
-# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */
-# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
-# define KINETIS_CRC_BASE 0x40032000 /* CRC */
-# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
-# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
-# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
-# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */
-# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */
-# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
-# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
-# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
-# define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */
-# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
-# define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
-# define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */
-# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
-# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
-# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
-# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
-# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
-# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
-# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
-# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
-# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
-# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
-# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
-# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
-# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
-# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */
-# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
-# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
-# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
-# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
-# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
-# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
-# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
-# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
-# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
-# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
-# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
-# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
-
-/* Peripheral Bridge 1 Memory Map ***************************************************/
-
-# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
-# define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */
-# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
-# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */
-# define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */
-# define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */
-# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
-# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */
-# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
-# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
-# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
-# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */
-# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
- * purpose input/output module that shares the
- * crossbar switch slave port with the AIPS-Lite
- * is accessed at this address. */
-# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
-# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
-# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
-# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
-# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
-# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
-
-/* Private Peripheral Bus (PPB) Memory Map ******************************************/
-
-# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
-# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
-# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
-# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
-# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
-# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
-# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
-# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
-# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
-# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */
-# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
-
-#else
- /* The memory map for other parts is defined in other documents and may or may not
- * be the same as above (the family members are all very similar) This error just
- * means that you have to look at the document and determine for yourself if the
- * memory map is the same.
- */
-
-# error "No memory map for this Kinetis part"
-#endif
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_MEMORYMAP_H */
diff --git a/arch/arm/src/kinetis/kinetis_mpuinit.h b/arch/arm/src/kinetis/kinetis_mpuinit.h
index f3cf95370efc9addeb53f17871c50b370aa1239f..3327176841b742c3c652ceb7539e3ce3d5bf84fb 100644
--- a/arch/arm/src/kinetis/kinetis_mpuinit.h
+++ b/arch/arm/src/kinetis/kinetis_mpuinit.h
@@ -42,18 +42,6 @@
#include
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
/************************************************************************************
* Public Functions
************************************************************************************/
diff --git a/arch/arm/src/kinetis/kinetis_pin.c b/arch/arm/src/kinetis/kinetis_pin.c
index 851d0c9d9cf885a9eab330d5d06502dc10535183..8a2e3294321a6ce237c2dd19be73404fa4751d50 100644
--- a/arch/arm/src/kinetis/kinetis_pin.c
+++ b/arch/arm/src/kinetis/kinetis_pin.c
@@ -48,22 +48,9 @@
#include "up_arch.h"
#include "up_internal.h"
-#include "kinetis_memorymap.h"
#include "kinetis.h"
-#include "kinetis_port.h"
-#include "kinetis_gpio.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
+#include "chip/kinetis_port.h"
+#include "chip/kinetis_gpio.h"
/****************************************************************************
* Public Functions
diff --git a/arch/arm/src/kinetis/kinetis_pindump.c b/arch/arm/src/kinetis/kinetis_pindump.c
index 579c01bb4d2c9d1752e29d6002664b4d9e910500..a660c87307c014bcb1ae255116d7124a1f63fa2c 100644
--- a/arch/arm/src/kinetis/kinetis_pindump.c
+++ b/arch/arm/src/kinetis/kinetis_pindump.c
@@ -46,8 +46,8 @@
#include "up_arch.h"
#include "kinetis.h"
-#include "kinetis_gpio.h"
-#include "kinetis_port.h"
+#include "chip/kinetis_gpio.h"
+#include "chip/kinetis_port.h"
#ifdef CONFIG_DEBUG_GPIO_INFO
diff --git a/arch/arm/src/kinetis/kinetis_pingpio.c b/arch/arm/src/kinetis/kinetis_pingpio.c
index 3663a92399f8c58e6523394970d5285912889ba0..b8879208164ef1bb05e36ac126e6e3624df41681 100644
--- a/arch/arm/src/kinetis/kinetis_pingpio.c
+++ b/arch/arm/src/kinetis/kinetis_pingpio.c
@@ -48,21 +48,8 @@
#include "up_arch.h"
#include "up_internal.h"
-#include "kinetis_memorymap.h"
#include "kinetis.h"
-#include "kinetis_gpio.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
+#include "chip/kinetis_gpio.h"
/****************************************************************************
* Public Functions
diff --git a/arch/arm/src/kinetis/kinetis_pinirq.c b/arch/arm/src/kinetis/kinetis_pinirq.c
index 0ec0d64176b30e8882154adc9fb6a4261745ab07..cc5933e715af6b6a79698f79f0b5e07d3cc8452e 100644
--- a/arch/arm/src/kinetis/kinetis_pinirq.c
+++ b/arch/arm/src/kinetis/kinetis_pinirq.c
@@ -50,9 +50,9 @@
#include "up_internal.h"
#include "kinetis.h"
-#include "kinetis_port.h"
+#include "chip/kinetis_port.h"
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KINETIS_GPIOIRQ
/****************************************************************************
* Pre-processor Definitions
@@ -450,4 +450,4 @@ void kinetis_pinirqdisable(uint32_t pinset)
}
#endif /* HAVE_PORTINTS */
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_KINETIS_GPIOIRQ */
diff --git a/arch/arm/src/kinetis/kinetis_pwm.c b/arch/arm/src/kinetis/kinetis_pwm.c
index 0730bf8dd835beb841ae70c14eea92e4f0ced95f..4eea85bd42001c9ea03dc971b818d5a56619dbd6 100644
--- a/arch/arm/src/kinetis/kinetis_pwm.c
+++ b/arch/arm/src/kinetis/kinetis_pwm.c
@@ -49,7 +49,7 @@
#include
#include
-#include
+#include
#include
#include "up_internal.h"
@@ -59,9 +59,9 @@
#include "kinetis.h"
#include "kinetis_pwm.h"
-#include "kinetis_gpio.h"
-#include "kinetis_ftm.h"
-#include "kinetis_sim.h"
+#include "chip/kinetis_gpio.h"
+#include "chip/kinetis_ftm.h"
+#include "chip/kinetis_sim.h"
/* This module then only compiles if there is at least one enabled timer
* intended for use with the PWM upper half driver.
diff --git a/arch/arm/src/kinetis/kinetis_pwm.h b/arch/arm/src/kinetis/kinetis_pwm.h
index 09508d4bfea7a1433bb7865600a1d924c4fa4e63..8e6070279634ecff1ec4494debeed76e4a989e2f 100644
--- a/arch/arm/src/kinetis/kinetis_pwm.h
+++ b/arch/arm/src/kinetis/kinetis_pwm.h
@@ -73,7 +73,7 @@
defined(CONFIG_KINETIS_FTM2_PWM)
#include
-#include "kinetis_pinmux.h"
+#include "chip/kinetis_pinmux.h"
/* For each timer that is enabled for PWM usage, we need the following additional
* configuration settings:
diff --git a/arch/arm/src/kinetis/kinetis_rtc.c b/arch/arm/src/kinetis/kinetis_rtc.c
new file mode 100644
index 0000000000000000000000000000000000000000..ca0f4848d19ff0f48ffe15434596d89ef8ff116e
--- /dev/null
+++ b/arch/arm/src/kinetis/kinetis_rtc.c
@@ -0,0 +1,373 @@
+/****************************************************************************
+ * arch/arm/src/kinetis/kinetis_rtc.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Matias v01d
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "up_arch.h"
+
+#include "kinetis_config.h"
+#include "chip.h"
+#include "chip/kinetis_rtc.h"
+#include "chip/kinetis_sim.h"
+#include "kinetis.h"
+#include "kinetis_alarm.h"
+
+#if defined(CONFIG_RTC)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_ALARM
+static alarmcb_t g_alarmcb;
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+volatile bool g_rtc_enabled = false;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: kinetis_rtc_interrupt
+ *
+ * Description:
+ * RTC interrupt service routine
+ *
+ * Input Parameters:
+ * irq - The IRQ number that generated the interrupt
+ * context - Architecture specific register save information.
+ *
+ * Returned Value:
+ * Zero (OK) on success; A negated errno value on failure.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_RTC_ALARM)
+static int kinetis_rtc_interrupt(int irq, void *context)
+{
+ if (g_alarmcb != NULL)
+ {
+ /* Alarm callback */
+
+ g_alarmcb();
+ g_alarmcb = NULL;
+ }
+
+ /* Clear pending flags, disable alarm */
+
+ putreg32(0, KINETIS_RTC_TAR); /* unset alarm (resets flags) */
+ putreg32(0, KINETIS_RTC_IER); /* disable alarm interrupt */
+
+ return 0;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_rtc_initialize
+ *
+ * Description:
+ * Initialize the hardware RTC per the selected configuration. This
+ * function is called once during the OS initialization sequence
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+int up_rtc_initialize(void)
+{
+ int regval;
+
+ /* Enable RTC module */
+
+ regval = getreg32(KINETIS_SIM_SCGC6);
+ regval |= SIM_SCGC6_RTC;
+ putreg32(regval, KINETIS_SIM_SCGC6);
+
+ /* Disable counters (just in case) */
+
+ putreg32(0, KINETIS_RTC_SR);
+
+ /* Enable oscilator */
+ /* capacitance values from teensyduino */
+
+ putreg32(RTC_CR_SC16P | RTC_CR_SC4P | RTC_CR_OSCE, KINETIS_RTC_CR);
+
+ /* TODO: delay some time (1024 cycles? would be 30ms) */
+
+ /* Disable interrupts */
+
+ putreg32(0, KINETIS_RTC_IER);
+
+ /* Reset flags requires writing the seconds register, the following line
+ * avoids altering any stored time value.
+ */
+
+ putreg32(getreg32(KINETIS_RTC_TSR), KINETIS_RTC_TSR);
+
+#if defined(CONFIG_RTC_ALARM)
+ /* Enable alarm interrupts. REVISIT: This will not work. up_rtc_initialize()
+ * is called very early in initialization BEFORE the interrupt system will be
+ * enabled. All interrupts will disabled later when the interrupt system is
+ * disabled. This must be done later when the alarm is first set.
+ */
+
+ irq_attach(KINETIS_IRQ_RTC, kinetis_rtc_interrupt);
+ up_enable_irq(KINETIS_IRQ_RTC);
+#endif
+
+ /* Enable counters */
+
+ putreg32(RTC_SR_TCE, KINETIS_RTC_SR);
+
+ /* Mark RTC enabled */
+
+ g_rtc_enabled = true;
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: up_rtc_time
+ *
+ * Description:
+ * Get the current time in seconds. This is similar to the standard
+ * time() function. This interface is only required if the low-resolution
+ * RTC/counter hardware implementation selected. It is only used by the
+ * RTOS during initialization to set up the system time when CONFIG_RTC is
+ * set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * The current time in seconds
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_RTC_HIRES
+time_t up_rtc_time(void)
+{
+ return getreg32(KINETIS_RTC_TSR);
+}
+#endif
+
+/****************************************************************************
+ * Name: up_rtc_gettime
+ *
+ * Description:
+ * Get the current time from the high resolution RTC clock/counter. This
+ * interface is only supported by the high-resolution RTC/counter hardware
+ * implementation. It is used to replace the system timer.
+ *
+ * Input Parameters:
+ * tp - The location to return the high resolution time value.
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_HIRES
+int up_rtc_gettime(FAR struct timespec *tp)
+{
+ irqstate_t flags;
+ uint32_t seconds, prescaler, prescaler2;
+
+ /* Get prescaler and seconds register. this is in a loop which ensures that
+ * registers will be re-read if during the reads the prescaler has
+ * wrapped-around.
+ */
+
+ flags = enter_critical_section();
+ do
+ {
+ prescaler = getreg32(KINETIS_RTC_TPR);
+ seconds = getreg32(KINETIS_RTC_TSR);
+ prescaler2 = getreg32(KINETIS_RTC_TPR);
+ }
+ while (prescaler > prescaler2);
+
+ leave_critical_section(flags);
+
+ /* Build seconds + nanoseconds from seconds and prescaler register */
+
+ tp->tv_sec = seconds;
+ tp->tv_nsec = prescaler * (1000000000 / CONFIG_RTC_FREQUENCY);
+ return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: up_rtc_settime
+ *
+ * Description:
+ * Set the RTC to the provided time. All RTC implementations must be able
+ * to set their time based on a standard timespec.
+ *
+ * Input Parameters:
+ * tp - the time to use
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+int up_rtc_settime(FAR const struct timespec *tp)
+{
+ irqstate_t flags;
+ uint32_t seconds, prescaler;
+
+ seconds = tp->tv_sec;
+ prescaler = tp->tv_nsec * (CONFIG_RTC_FREQUENCY / 1000000000);
+
+ flags = enter_critical_section();
+
+ putreg32(0, KINETIS_RTC_SR); /* Disable counter */
+
+ putreg32(prescaler, KINETIS_RTC_TPR); /* Always write prescaler first */
+ putreg32(seconds, KINETIS_RTC_TSR);
+
+ putreg32(RTC_SR_TCE, KINETIS_RTC_SR); /* Re-enable counter */
+
+ leave_critical_section(flags);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: kinetis_rtc_setalarm
+ *
+ * Description:
+ * Set up an alarm.
+ *
+ * Input Parameters:
+ * tp - the time to set the alarm
+ * callback - the function to call when the alarm expires.
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_ALARM
+int kinetis_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback)
+{
+ /* Is there already something waiting on the ALARM? */
+
+ if (g_alarmcb == NULL)
+ {
+ /* No.. Save the callback function pointer */
+
+ g_alarmcb = callback;
+
+ /* Enable and set RTC alarm */
+
+ putreg32(tp->tv_sec, KINETIS_RTC_TAR); /* Set alarm (also resets
+ * flags) */
+ putreg32(RTC_IER_TAIE, KINETIS_RTC_IER); /* Enable alarm interrupt */
+
+ return OK;
+ }
+ else
+ {
+ return -EBUSY;
+ }
+}
+#endif
+
+/****************************************************************************
+ * Name: kinetis_rtc_cancelalarm
+ *
+ * Description:
+ * Cancel a pending alarm alarm
+ *
+ * Input Parameters:
+ * none
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_RTC_ALARM
+int kinetis_rtc_cancelalarm(void)
+{
+ if (g_alarmcb != NULL)
+ {
+ /* Cancel the global callback function */
+
+ g_alarmcb = NULL;
+
+ /* Unset the alarm */
+
+ putreg32(0, KINETIS_RTC_IER); /* disable alarm interrupt */
+
+ return OK;
+ }
+ else
+ {
+ return -ENODATA;
+ }
+}
+#endif
+
+#endif /* KINETIS_RTC */
diff --git a/arch/arm/src/kinetis/kinetis_sdhc.c b/arch/arm/src/kinetis/kinetis_sdhc.c
index 46b49438317db23da207c6e7f5e974e4a6b26ec0..0f1197b6e7b9d08420d8a3906d7a1a0a11155b31 100644
--- a/arch/arm/src/kinetis/kinetis_sdhc.c
+++ b/arch/arm/src/kinetis/kinetis_sdhc.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/kinetis/kinetis_sdhc.c
*
- * Copyright (C) 2011-2012, 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -61,9 +61,9 @@
#include "up_arch.h"
#include "kinetis.h"
-#include "kinetis_pinmux.h"
-#include "kinetis_sim.h"
-#include "kinetis_sdhc.h"
+#include "chip/kinetis_pinmux.h"
+#include "chip/kinetis_sim.h"
+#include "chip/kinetis_sdhc.h"
#ifdef CONFIG_KINETIS_SDHC
@@ -85,10 +85,6 @@
# define CONFIG_KINETIS_SDHC_PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
-#ifndef CONFIG_KINETIS_SDHC_DMAPRIO
-# define CONFIG_KINETIS_SDHC_DMAPRIO DMA_CCR_PRIMED
-#endif
-
#ifndef CONFIG_DEBUG_MEMCARD_INFO
# undef CONFIG_SDIO_XFRDEBUG
#endif
@@ -791,8 +787,8 @@ static void kinetis_transmit(struct kinetis_dev_s *priv)
* ready (BWR)
*/
- mcllinfo("Entry: remaining: %d IRQSTAT: %08x\n",
- priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
+ mcinfo("Entry: remaining: %d IRQSTAT: %08x\n",
+ priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
while (priv->remaining > 0 &&
(getreg32(KINETIS_SDHC_IRQSTAT) & SDHC_INT_BWR) != 0)
@@ -837,8 +833,8 @@ static void kinetis_transmit(struct kinetis_dev_s *priv)
putreg32(data.w, KINETIS_SDHC_DATPORT);
}
- mcllinfo("Exit: remaining: %d IRQSTAT: %08x\n",
- priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
+ mcinfo("Exit: remaining: %d IRQSTAT: %08x\n",
+ priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
}
#endif
@@ -876,8 +872,8 @@ static void kinetis_receive(struct kinetis_dev_s *priv)
* ready (BRR)
*/
- mcllinfo("Entry: remaining: %d IRQSTAT: %08x\n",
- priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
+ mcinfo("Entry: remaining: %d IRQSTAT: %08x\n",
+ priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
while (priv->remaining > 0 &&
(getreg32(KINETIS_SDHC_IRQSTAT) & SDHC_INT_BRR) != 0)
@@ -928,9 +924,9 @@ static void kinetis_receive(struct kinetis_dev_s *priv)
putreg32(watermark << SDHC_WML_RD_SHIFT, KINETIS_SDHC_WML);
- mcllinfo("Exit: remaining: %d IRQSTAT: %08x WML: %08x\n",
- priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT),
- getreg32(KINETIS_SDHC_WML));
+ mcinfo("Exit: remaining: %d IRQSTAT: %08x WML: %08x\n",
+ priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT),
+ getreg32(KINETIS_SDHC_WML));
}
#endif
@@ -971,7 +967,7 @@ static void kinetis_eventtimeout(int argc, uint32_t arg)
/* Wake up any waiting threads */
kinetis_endwait(priv, SDIOWAIT_TIMEOUT);
- mcllerr("ERROR: Timeout: remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Timeout: remaining: %d\n", priv->remaining);
}
}
@@ -1103,8 +1099,8 @@ static int kinetis_interrupt(int irq, void *context)
regval = getreg32(KINETIS_SDHC_IRQSIGEN);
enabled = getreg32(KINETIS_SDHC_IRQSTAT) & regval;
- mcllinfo("IRQSTAT: %08x IRQSIGEN %08x enabled: %08x\n",
- getreg32(KINETIS_SDHC_IRQSTAT), regval, enabled);
+ mcinfo("IRQSTAT: %08x IRQSIGEN %08x enabled: %08x\n",
+ getreg32(KINETIS_SDHC_IRQSTAT), regval, enabled);
/* Disable card interrupts to clear the card interrupt to the host system. */
@@ -1160,7 +1156,7 @@ static int kinetis_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- mcllerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
kinetis_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
@@ -1170,7 +1166,7 @@ static int kinetis_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- mcllerr("ERROR: Data timeout, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Data timeout, remaining: %d\n", priv->remaining);
kinetis_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT);
}
}
diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c
index 8f7e2b1595b4e762b8f7c14edcf15f833b9a05cd..53fd7e2b4ab32418dd048d393a7ca5dd1c1771c7 100644
--- a/arch/arm/src/kinetis/kinetis_serial.c
+++ b/arch/arm/src/kinetis/kinetis_serial.c
@@ -59,7 +59,7 @@
#include "kinetis_config.h"
#include "chip.h"
-#include "kinetis_uart.h"
+#include "chip/kinetis_uart.h"
#include "kinetis.h"
/****************************************************************************
@@ -805,7 +805,7 @@ static int up_interrupt(int irq, void *context)
*/
regval = up_serialin(priv, KINETIS_UART_S1_OFFSET);
- _llinfo("S1: %02x\n", regval);
+ _info("S1: %02x\n", regval);
UNUSED(regval);
regval = up_serialin(priv, KINETIS_UART_D_OFFSET);
diff --git a/arch/arm/src/kinetis/kinetis_start.c b/arch/arm/src/kinetis/kinetis_start.c
index f9665a04c4bf629c3588954a77ef412d7fa94e49..21885d926823fdaaaf592fff9639b81b11fd6ef3 100644
--- a/arch/arm/src/kinetis/kinetis_start.c
+++ b/arch/arm/src/kinetis/kinetis_start.c
@@ -51,7 +51,7 @@
#include "up_internal.h"
#include "kinetis.h"
-#include "kinetis_smc.h"
+#include "chip/kinetis_smc.h"
#include "kinetis_userspace.h"
/****************************************************************************
@@ -156,8 +156,8 @@ void __start(void)
/* Show reset status */
- _llwarn("Reset status: %02x:%02x\n",
- getreg8(KINETIS_SMC_SRSH), getreg8(KINETIS_SMC_SRSL));
+ _warn("Reset status: %02x:%02x\n",
+ getreg8(KINETIS_SMC_SRSH), getreg8(KINETIS_SMC_SRSL));
/* Then start NuttX */
diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c
index d48757f9299745b7b5230e0f04427ab62ca3b36a..231fc01430316ac13a235b23a356d31e2012bf90 100644
--- a/arch/arm/src/kinetis/kinetis_usbdev.c
+++ b/arch/arm/src/kinetis/kinetis_usbdev.c
@@ -67,8 +67,8 @@
#include "up_arch.h"
#include "kinetis.h"
#include "kinetis_usbotg.h"
-#include "kinetis_sim.h"
-#include "kinetis_fmc.h"
+#include "chip/kinetis_sim.h"
+#include "chip/kinetis_fmc.h"
#if defined(CONFIG_USBDEV) && defined(CONFIG_KINETIS_USBOTG)
@@ -375,8 +375,8 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
/* CONFIG_KHCI_USBDEV_BDTDEBUG dumps most BDT settings */
#ifdef CONFIG_KHCI_USBDEV_BDTDEBUG
-# define bdterr ullerr
-# define bdtinfo ullinfo
+# define bdterr uerr
+# define bdtinfo uinfo
#else
# define bdterr(x...)
# define bdtinfo(x...)
@@ -693,7 +693,7 @@ static uint16_t khci_getreg(uint32_t addr)
{
if (count == 4)
{
- ullinfo("...\n");
+ uinfo("...\n");
}
return val;
}
@@ -709,7 +709,7 @@ static uint16_t khci_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- ullinfo("[repeats %d more times]\n", count-3);
+ uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -721,7 +721,7 @@ static uint16_t khci_getreg(uint32_t addr)
/* Show the register value read */
- ullinfo("%08x->%04x\n", addr, val);
+ uinfo("%08x->%04x\n", addr, val);
return val;
}
#endif
@@ -735,7 +735,7 @@ static void khci_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- ullinfo("%08x<-%04x\n", addr, val);
+ uinfo("%08x<-%04x\n", addr, val);
/* Write the value */
@@ -966,15 +966,15 @@ static void khci_wrcomplete(struct khci_usbdev_s *priv,
epno = USB_EPNO(privep->ep.eplog);
#ifdef CONFIG_USBDEV_NOWRITEAHEAD
- ullinfo("EP%d: len=%d xfrd=%d inflight=%d\n",
- epno, privreq->req.len, privreq->req.xfrd, privreq->inflight[0]);
+ uinfo("EP%d: len=%d xfrd=%d inflight=%d\n",
+ epno, privreq->req.len, privreq->req.xfrd, privreq->inflight[0]);
#else
- ullinfo("EP%d: len=%d xfrd=%d inflight={%d, %d}\n",
- epno, privreq->req.len, privreq->req.xfrd,
- privreq->inflight[0], privreq->inflight[1]);
+ uinfo("EP%d: len=%d xfrd=%d inflight={%d, %d}\n",
+ epno, privreq->req.len, privreq->req.xfrd,
+ privreq->inflight[0], privreq->inflight[1]);
#endif
bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n",
- epno, bdtin, bdtin->status, bdtin->addr);
+ epno, bdtin, bdtin->status, bdtin->addr);
/* We should own the BDT that just completed. But NULLify the entire BDT IN.
* Why? So that we can tell later that the BDT available. No, it is not
@@ -1282,8 +1282,8 @@ static int khci_wrstart(struct khci_usbdev_s *priv,
bytesleft = privreq->req.len;
}
- ullinfo("epno=%d req=%p: len=%d xfrd=%d index=%d nullpkt=%d\n",
- epno, privreq, privreq->req.len, xfrd, index, privep->txnullpkt);
+ uinfo("epno=%d req=%p: len=%d xfrd=%d index=%d nullpkt=%d\n",
+ epno, privreq, privreq->req.len, xfrd, index, privep->txnullpkt);
/* Get the number of bytes left to be sent in the packet */
@@ -1396,10 +1396,10 @@ static int khci_rdcomplete(struct khci_usbdev_s *priv,
bdtout = privep->bdtout;
epno = USB_EPNO(privep->ep.eplog);
- ullinfo("EP%d: len=%d xfrd=%d\n",
- epno, privreq->req.len, privreq->req.xfrd);
+ uinfo("EP%d: len=%d xfrd=%d\n",
+ epno, privreq->req.len, privreq->req.xfrd);
bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n",
- epno, bdtout, bdtout->status, bdtout->addr);
+ epno, bdtout, bdtout->status, bdtout->addr);
/* We should own the BDT that just completed */
@@ -1685,7 +1685,7 @@ static int khci_rdrequest(struct khci_usbdev_s *priv,
return OK;
}
- ullinfo("EP%d: len=%d\n", USB_EPNO(privep->ep.eplog), privreq->req.len);
+ uinfo("EP%d: len=%d\n", USB_EPNO(privep->ep.eplog), privreq->req.len);
/* Ignore any attempt to receive a zero length packet */
@@ -1975,8 +1975,8 @@ static void khci_ep0setup(struct khci_usbdev_s *priv)
index.w = GETUINT16(priv->ctrl.index);
len.w = GETUINT16(priv->ctrl.len);
- ullinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
+ uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
/* Dispatch any non-standard requests */
@@ -2219,7 +2219,7 @@ static void khci_ep0setup(struct khci_usbdev_s *priv)
{
/* Special case recipient=device test mode */
- ullinfo("test mode: %d\n", index.w);
+ uinfo("test mode: %d\n", index.w);
}
else
{
@@ -2738,7 +2738,7 @@ static int khci_interrupt(int irq, void *context)
#ifdef CONFIG_USBOTG
/* Session Request Protocol (SRP) Time Out Check */
- /* if USB OTG SRP is ready */
+ /* Check if USB OTG SRP is ready */
# warning "Missing logic"
{
/* Check if the 1 millisecond timer has expired */
@@ -2893,7 +2893,7 @@ x
if ((usbir & USB_INT_ERROR) != 0)
{
usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_UERR), usbir);
- ullerr("ERROR: EIR=%04x\n", khci_getreg(KINETIS_USB0_ERRSTAT));
+ uerr("ERROR: EIR=%04x\n", khci_getreg(KINETIS_USB0_ERRSTAT));
/* Clear all pending USB error interrupts */
@@ -2960,6 +2960,8 @@ x
}
}
+ UNUSED(otgir); /* May not be used, depending on above conditional logic */
+
/* Clear the pending USB interrupt. Goto is used in the above to assure
* that all interrupt exists pass through this logic.
*/
@@ -3221,7 +3223,7 @@ static int khci_epconfigure(struct usbdev_ep_s *ep,
if (!ep || !desc)
{
usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
- ullerr("ERROR: ep=%p desc=%p\n");
+ uerr("ERROR: ep=%p desc=%p\n");
return -EINVAL;
}
#endif
@@ -3352,7 +3354,7 @@ static int khci_epdisable(struct usbdev_ep_s *ep)
if (!ep)
{
usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
- ullerr("ERROR: ep=%p\n", ep);
+ uerr("ERROR: ep=%p\n", ep);
return -EINVAL;
}
#endif
@@ -3451,8 +3453,8 @@ static int khci_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0);
- ullerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
- req, req->callback, req->buf, ep);
+ uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
+ req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
@@ -3464,7 +3466,7 @@ static int khci_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (!priv->driver)
{
usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
- ullerr("ERROR: driver=%p\n", priv->driver);
+ uerr("ERROR: driver=%p\n", priv->driver);
return -ESHUTDOWN;
}
#endif
@@ -4233,10 +4235,10 @@ static void khci_hwreset(struct khci_usbdev_s *priv)
khci_putreg((uint8_t)((uint32_t)g_bdt >> 16), KINETIS_USB0_BDTPAGE2);
khci_putreg((uint8_t)(((uint32_t)g_bdt >> 8) & USB_BDTPAGE1_MASK), KINETIS_USB0_BDTPAGE1);
- ullinfo("BDT Address %hhx \n" ,&g_bdt);
- ullinfo("BDTPAGE3 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE3));
- ullinfo("BDTPAGE2 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE2));
- ullinfo("BDTPAGE1 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE1));
+ uinfo("BDT Address %hhx \n" ,&g_bdt);
+ uinfo("BDTPAGE3 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE3));
+ uinfo("BDTPAGE2 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE2));
+ uinfo("BDTPAGE1 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE1));
/* Clear any pending interrupts */
diff --git a/arch/arm/src/kinetis/kinetis_usbotg.h b/arch/arm/src/kinetis/kinetis_usbotg.h
index de53d512933301f567c5089c9276d7480d544b7d..655c7ccee9c622e1aaa6a4cb4528f52c43b7c054 100644
--- a/arch/arm/src/kinetis/kinetis_usbotg.h
+++ b/arch/arm/src/kinetis/kinetis_usbotg.h
@@ -42,311 +42,7 @@
#include
-#include "chip.h"
-
-/********************************************************************************************
- * Pre-processor Definitions
- ********************************************************************************************/
-
-/* Register Offsets *************************************************************************/
-
-#define KINETIS_USB_PERID_OFFSET 0x0000 /* Peripheral ID Register */
-#define KINETIS_USB_IDCOMP_OFFSET 0x0004 /* Peripheral ID Complement Register */
-#define KINETIS_USB_REV_OFFSET 0x0008 /* Peripheral Revision Register */
-#define KINETIS_USB_ADDINFO_OFFSET 0x000c /* Peripheral Additional Info Register */
-#define KINETIS_USB_OTGISTAT_OFFSET 0x0010 /* OTG Interrupt Status Register */
-#define KINETIS_USB_OTGICR_OFFSET 0x0014 /* OTG Interrupt Control Register */
-#define KINETIS_USB_OTGSTAT_OFFSET 0x0018 /* OTG Status Register */
-#define KINETIS_USB_OTGCTL_OFFSET 0x001c /* OTG Control Register */
-#define KINETIS_USB_ISTAT_OFFSET 0x0080 /* Interrupt Status Register */
-#define KINETIS_USB_INTEN_OFFSET 0x0084 /* Interrupt Enable Register */
-#define KINETIS_USB_ERRSTAT_OFFSET 0x0088 /* Error Interrupt Status Register */
-#define KINETIS_USB_ERREN_OFFSET 0x008c /* Error Interrupt Enable Register */
-#define KINETIS_USB_STAT_OFFSET 0x0090 /* Status Register */
-#define KINETIS_USB_CTL_OFFSET 0x0094 /* Control Register */
-#define KINETIS_USB_ADDR_OFFSET 0x0098 /* Address Register */
-#define KINETIS_USB_BDTPAGE1_OFFSET 0x009c /* BDT Page Register 1 */
-#define KINETIS_USB_FRMNUML_OFFSET 0x00a0 /* Frame Number Register Low */
-#define KINETIS_USB_FRMNUMH_OFFSET 0x00a4 /* Frame Number Register High */
-#define KINETIS_USB_TOKEN_OFFSET 0x00a8 /* Token Register */
-#define KINETIS_USB_SOFTHLD_OFFSET 0x00ac /* SOF Threshold Register */
-#define KINETIS_USB_BDTPAGE2_OFFSET 0x00b0 /* BDT Page Register 2 */
-#define KINETIS_USB_BDTPAGE3_OFFSET 0x00b4 /* BDT Page Register 3 */
-
-#define KINETIS_USB_ENDPT_OFFSET(n) (0x00c0+((n)<<2)) /* Endpoint n Control Register */
-#define KINETIS_USB_ENDPT0_OFFSET 0x00c0 /* Endpoint 0 Control Register */
-#define KINETIS_USB_ENDPT1_OFFSET 0x00c4 /* Endpoint 1 Control Register */
-#define KINETIS_USB_ENDPT2_OFFSET 0x00c8 /* Endpoint 2 Control Register */
-#define KINETIS_USB_ENDPT3_OFFSET 0x00cc /* Endpoint 3 Control Register */
-#define KINETIS_USB_ENDPT4_OFFSET 0x00d0 /* Endpoint 4 Control Register */
-#define KINETIS_USB_ENDPT5_OFFSET 0x00d4 /* Endpoint 5 Control Register */
-#define KINETIS_USB_ENDPT6_OFFSET 0x00d8 /* Endpoint 6 Control Register */
-#define KINETIS_USB_ENDPT7_OFFSET 0x00dc /* Endpoint 7 Control Register */
-#define KINETIS_USB_ENDPT8_OFFSET 0x00e0 /* Endpoint 8 Control Register */
-#define KINETIS_USB_ENDPT9_OFFSET 0x00e4 /* Endpoint 9 Control Register */
-#define KINETIS_USB_ENDPT10_OFFSET 0x00e8 /* Endpoint 10 Control Register */
-#define KINETIS_USB_ENDPT11_OFFSET 0x00ec /* Endpoint 11 Control Register */
-#define KINETIS_USB_ENDPT12_OFFSET 0x00f0 /* Endpoint 12 Control Register */
-#define KINETIS_USB_ENDPT13_OFFSET 0x00f4 /* Endpoint 13 Control Register */
-#define KINETIS_USB_ENDPT14_OFFSET 0x00f8 /* Endpoint 14 Control Register */
-#define KINETIS_USB_ENDPT15_OFFSET 0x00fc /* Endpoint 15 Control Register */
-
-#define KINETIS_USB_USBCTRL_OFFSET 0x0100 /* USB Control Register */
-#define KINETIS_USB_OBSERVE_OFFSET 0x0104 /* USB OTG Observe Register */
-#define KINETIS_USB_CONTROL_OFFSET 0x0108 /* USB OTG Control Register */
-#define KINETIS_USB_USBTRC0_OFFSET 0x010c /* USB Transceiver Control Register 0 */
-
-/* Register Addresses ***********************************************************************/
-
-#define KINETIS_USB0_PERID (KINETIS_USB0_BASE+KINETIS_USB_PERID_OFFSET)
-#define KINETIS_USB0_IDCOMP (KINETIS_USB0_BASE+KINETIS_USB_IDCOMP_OFFSET)
-#define KINETIS_USB0_REV (KINETIS_USB0_BASE+KINETIS_USB_REV_OFFSET)
-#define KINETIS_USB0_ADDINFO (KINETIS_USB0_BASE+KINETIS_USB_ADDINFO_OFFSET)
-#define KINETIS_USB0_OTGISTAT (KINETIS_USB0_BASE+KINETIS_USB_OTGISTAT_OFFSET)
-#define KINETIS_USB0_OTGICR (KINETIS_USB0_BASE+KINETIS_USB_OTGICR_OFFSET)
-#define KINETIS_USB0_OTGSTAT (KINETIS_USB0_BASE+KINETIS_USB_OTGSTAT_OFFSET)
-#define KINETIS_USB0_OTGCTL (KINETIS_USB0_BASE+KINETIS_USB_OTGCTL_OFFSET)
-#define KINETIS_USB0_ISTAT (KINETIS_USB0_BASE+KINETIS_USB_ISTAT_OFFSET)
-#define KINETIS_USB0_INTEN (KINETIS_USB0_BASE+KINETIS_USB_INTEN_OFFSET)
-#define KINETIS_USB0_ERRSTAT (KINETIS_USB0_BASE+KINETIS_USB_ERRSTAT_OFFSET)
-#define KINETIS_USB0_ERREN (KINETIS_USB0_BASE+KINETIS_USB_ERREN_OFFSET)
-#define KINETIS_USB0_STAT (KINETIS_USB0_BASE+KINETIS_USB_STAT_OFFSET)
-#define KINETIS_USB0_CTL (KINETIS_USB0_BASE+KINETIS_USB_CTL_OFFSET)
-#define KINETIS_USB0_ADDR (KINETIS_USB0_BASE+KINETIS_USB_ADDR_OFFSET)
-#define KINETIS_USB0_BDTPAGE1 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE1_OFFSET)
-#define KINETIS_USB0_FRMNUML (KINETIS_USB0_BASE+KINETIS_USB_FRMNUML_OFFSET)
-#define KINETIS_USB0_FRMNUMH (KINETIS_USB0_BASE+KINETIS_USB_FRMNUMH_OFFSET)
-#define KINETIS_USB0_TOKEN (KINETIS_USB0_BASE+KINETIS_USB_TOKEN_OFFSET)
-#define KINETIS_USB0_SOFTHLD (KINETIS_USB0_BASE+KINETIS_USB_SOFTHLD_OFFSET)
-#define KINETIS_USB0_BDTPAGE2 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE2_OFFSET)
-#define KINETIS_USB0_BDTPAGE3 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE3_OFFSET)
-
-#define KINETIS_USB0_ENDPT(n) (KINETIS_USB0_BASE+KINETIS_USB_ENDPT_OFFSET(n))
-#define KINETIS_USB0_ENDPT0 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT0_OFFSET)
-#define KINETIS_USB0_ENDPT1 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT1_OFFSET)
-#define KINETIS_USB0_ENDPT2 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT2_OFFSET)
-#define KINETIS_USB0_ENDPT3 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT3_OFFSET)
-#define KINETIS_USB0_ENDPT4 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT4_OFFSET)
-#define KINETIS_USB0_ENDPT5 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT5_OFFSET)
-#define KINETIS_USB0_ENDPT6 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT6_OFFSET)
-#define KINETIS_USB0_ENDPT7 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT7_OFFSET)
-#define KINETIS_USB0_ENDPT8 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT8_OFFSET)
-#define KINETIS_USB0_ENDPT9 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT9_OFFSET)
-#define KINETIS_USB0_ENDPT10 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT10_OFFSET)
-#define KINETIS_USB0_ENDPT11 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT11_OFFSET)
-#define KINETIS_USB0_ENDPT12 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT12_OFFSET)
-#define KINETIS_USB0_ENDPT13 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT13_OFFSET)
-#define KINETIS_USB0_ENDPT14 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT14_OFFSET)
-#define KINETIS_USB0_ENDPT15 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT15_OFFSET)
-
-#define KINETIS_USB0_USBCTRL (KINETIS_USB0_BASE+KINETIS_USB_USBCTRL_OFFSET)
-#define KINETIS_USB0_OBSERVE (KINETIS_USB0_BASE+KINETIS_USB_OBSERVE_OFFSET)
-#define KINETIS_USB0_CONTROL (KINETIS_USB0_BASE+KINETIS_USB_CONTROL_OFFSET)
-#define KINETIS_USB0_USBTRC0 (KINETIS_USB0_BASE+KINETIS_USB_USBTRC0_OFFSET)
-
-/* Register Bit Definitions *****************************************************************/
-
-/* Peripheral ID Register (8-bit) */
- /* Bits 6-7: Reserved */
-#define USB_PERID_MASK (0x3f) /* Bits 0-5: Peripheral identification bits */
-
-/* Peripheral ID Complement Register (8-bit) */
-#define USB_IDCOMP_
- /* Bits 6-7: Reserved */
-#define USB_IDCOMP_MASK (0x3f) /* Bits 0-5: Ones complement of peripheral identification bits */
-
-/* Peripheral Revision Register (8-bit revision number) */
-
-/* Peripheral Additional Info Register (8-bit) */
-
-#define USB_ADDINFO_IEHOST (1 << 0) /* Bit 0: This bit is set if host mode is enabled */
- /* Bits 1-2: Reserved */
-#define USB_ADDINFO_IRQNUM_SHIFT (3) /* Bits 3-7: Assigned Interrupt Request Number */
-#define USB_ADDINFO_IRQNUM_MASK (31 << USB_ADDINFO_IRQNUM_SHIFT)
-
-/* OTG Interrupt Status Register(8-bit) */
-
-#define USB_OTGISTAT_AVBUSCHG (1 << 0) /* Bit 0: Change in VBUS is detected on an A device */
- /* Bit 1: Reserved */
-#define USB_OTGISTAT_B_SESS_CHG (1 << 2) /* Bit 2: Change in VBUS is detected on a B device */
-#define USB_OTGISTAT_SESSVLDCHG (1 << 3) /* Bit 3: Change in VBUS is detected */
- /* Bit 4: Reserved */
-#define USB_OTGISTAT_LINE_STATE_CHG (1 << 5) /* Bit 5: Change USB line state */
-#define USB_OTGISTAT_ONEMSEC (1 << 6) /* Bit 6: Set when the 1 millisecond timer expires */
-#define USB_OTGISTAT_IDCHG (1 << 7) /* Bit 7: Change in ID Signal from the USB connector */
-
-/* OTG Interrupt Control Register (8-bit) */
-
-#define USB_OTGICR_AVBUSEN (1 << 0) /* Bit 0: A VBUS Valid interrupt enable */
- /* Bit 1: Reserved */
-#define USB_OTGICR_BSESSEN (1 << 2) /* Bit 2: B Session END interrupt enable */
-#define USB_OTGICR_SESSVLDEN (1 << 3) /* Bit 3: Session valid interrupt enable */
- /* Bit 4: Reserved */
-#define USB_OTGICR_LINESTATEEN (1 << 5) /* Bit 5: Line State change interrupt enable */
-#define USB_OTGICR_ONEMSECEN (1 << 6) /* Bit 6: 1 millisecond interrupt enable */
-#define USB_OTGICR_IDEN (1 << 7) /* Bit 7: ID interrupt enable */
-
-/* OTG Status Register (8-bit) */
-
-#define USB_OTGSTAT_AVBUSVLD (1 << 0) /* Bit 0: A VBUS Valid */
- /* Bit 1: Reserved */
-#define USB_OTGSTAT_BSESSEND (1 << 2) /* Bit 2: B Session END */
-#define USB_OTGSTAT_SESS_VLD (1 << 3) /* Bit 3: Session valid */
- /* Bit 4: Reserved */
-#define USB_OTGSTAT_LINESTATESTABLE (1 << 5) /* Bit 5: OTGISTAT LINE_STATE_CHG bit stable */
-#define USB_OTGSTAT_ONEMSECEN (1 << 6) /* Bit 6: Reserved for the 1msec count */
-#define USB_OTGSTAT_ID (1 << 7) /* Bit 7: Current state of the ID pin on the USB connector */
-
-/* OTG Control Register (8-bit) */
- /* Bits 0-1: Reserved */
-#define USB_OTGCTL_OTGEN (1 << 2) /* Bit 2: On-The-Go pullup/pulldown resistor enable */
- /* Bit 3: Reserved */
-#define USB_OTGCTL_DMLOW (1 << 4) /* Bit 4: D- Data Line pull-down resistor enable */
-#define USB_OTGCTL_DPLOW (1 << 5) /* Bit 5: D+ Data Line pull-down resistor enable */
- /* Bit 6: Reserved */
-#define USB_OTGCTL_DPHIGH (1 << 7) /* Bit 7: D+ Data Line pullup resistor enable */
-
-/* Interrupt Status Register Interrupt Enable Register (8-bit) */
-
-#define USB_INT_USBRST (1 << 0) /* Bit 0: USB Module has decoded a valid USB reset */
-#define USB_INT_ERROR (1 << 1) /* Bit 1: Any of the error conditions within the ERRSTAT register */
-#define USB_INT_SOFTOK (1 << 2) /* Bit 2: USB Module received a Start Of Frame (SOF) token */
-#define USB_INT_TOKDNE (1 << 3) /* Bit 3: Current token being processed has completed */
-#define USB_INT_SLEEP (1 << 4) /* Bit 4: Constant idle on the USB bus for 3 milliseconds */
-#define USB_INT_RESUME (1 << 5) /* Bit 5: Signal remote wake-up signaling */
-#define USB_INT_ATTACH (1 << 6) /* Bit 6: Attach Interrupt */
-#define USB_INT_STALL (1 << 7) /* Bit 7: Stall Interrupt */
-
-#define USB_INT_ALL 0xFF
-
-/* Error Interrupt Status Register and Error Interrupt Enable Register (8-bit) */
-
-#define USB_ERRSTAT_PIDERR (1 << 0) /* Bit 0: This bit is set when the PID check field fails */
-#define USB_ERRSTAT_CRC5EOF (1 << 1) /* Bit 1: Host data CRC error or End of frame errors */
-#define USB_ERRSTAT_CRC16 (1 << 2) /* Bit 2: Data packet is rejected due to a CRC16 error */
-#define USB_ERRSTAT_DFN8 (1 << 3) /* Bit 3: Data field received was not 8 bits in length */
-#define USB_ERRSTAT_BTOERR (1 << 4) /* Bit 4: Bus turnaround timeout error occurred */
-#define USB_ERRSTAT_DMAERR (1 << 5) /* Bit 5: DMA error */
- /* Bit 6: Reserved */
-#define USB_ERRSTAT_BTSERR (1 << 7) /* Bit 7: Bit stuff error is detected */
-
-#define USB_EINT_ALL 0xBF
-
-/* Status Register (8-bit) */
-
- /* Bits 0-1: Reserved */
-#define USB_STAT_ODD (1 << 2) /* Bit 2: Last Buffer Descriptor was in the odd bank of the BDT */
-#define USB_STAT_TX (1 << 3) /* Bit 3: Transmit Indicator */
-#define USB_STAT_ENDP_SHIFT (4) /* Bits 4-7: Endpoint address that received or transmitted the token */
-#define USB_STAT_ENDP_MASK (15 << USB_STAT_ENDP_SHIFT)
-
-/* Control Register (8-bit) */
-
-#define USB_CTL_USBENSOFEN (1 << 0) /* Bit 0: USB Enable */
-#define USB_CTL_ODDRST (1 << 1) /* Bit 1: Resets all the BDT ODD ping/pong bits to 0 */
-#define USB_CTL_RESUME (1 << 2) /* Bit 2: Enables the USB Module to execute resume signaling */
-#define USB_CTL_HOSTMODEEN (1 << 3) /* Bit 3: Enables the USB Module to operate in Host mode */
-#define USB_CTL_RESET (1 << 4) /* Bit 4: Enables the USB Module to generate USB reset signaling */
-#define USB_CTL_TXSUSPENDTOKENBUSY (1 << 5) /* Bit 5: USB Module is busy executing a USB token */
-#define USB_CTL_SE0 (1 << 6) /* Bit 6: Live USB Single Ended Zero signal */
-#define USB_CTL_JSTATE (1 << 7) /* Bit 7: Live USB differential receiver JSTATE signal */
-
-/* Address Register (8-bit) */
-
-#define USB_ADDR_LSEN (1 << 7) /* Bit 7: Low Speed Enable bit */
-#define USB_ADDR_SHIFT (0) /* Bits 0-6: USB address */
-#define USB_ADDR_MASK (0x7f << USB_ADDR_SHIFT)
-
-/* BDT Page Register 1 (8-bit) */
- /* Bit 0: Reserved */
-#define USB_BDTPAGE1_SHIFT (1) /* Bits 1-7: Address bits 9-15 of the BDT base address */
-#define USB_BDTPAGE1_MASK (0x7f << USB_BDTPAGE1_SHIFT)
-
-/* Frame Number Register Low (8-bit, bits 0-7 of the 11 bit frame number) */
-#define USB_FRMNUML_MASK 0xFF
-/* Frame Number Register High (8-bit) */
- /* Bits 3-7: Reserved */
-#define USB_FRMNUMH_SHIFT (0) /* Bits 0-2: Bits 8-10 of the 11-bit frame number */
-#define USB_FRMNUMH_MASK (7 << USB_FRMNUMH_SHIFT)
-
-/* Token Register (8-bit) */
-
-#define USB_TOKEN_ENDPT_SHIFT (0) /* Bits 0-3: Endpoint address for the token command */
-#define USB_TOKEN_ENDPT_MASK (15 << USB_TOKEN_ENDPT_SHIFT)
-#define USB_TOKEN_PID_SHIFT (4) /* Bits 4-7: Token type executed by the USB Module */
-#define USB_TOKEN_PID_MASK (15 << USB_TOKEN_PID_SHIFT)
-# define USB_TOKEN_PID_OUT (1 << USB_TOKEN_PID_SHIFT) /* OUT Token */
-# define USB_TOKEN_PID_IN (9 << USB_TOKEN_PID_SHIFT) /* IN Token */
-# define USB_TOKEN_PID_SETUP (13 << USB_TOKEN_PID_SHIFT) /* SETUP Token */
-
-/* SOF Threshold Register (8-bit count value) */
-/* BDT Page Register 2/3 (16 bit address in two 8-bit registers) */
-
-/* Endpoint n Control Register (8-bit) */
-
-#define USB_ENDPT_EPHSHK (1 << 0) /* Bit 0: Enable handshaking during a transaction to the endpoint */
-#define USB_ENDPT_EPSTALL (1 << 1) /* Bit 1: Endpoint is stalled */
-#define USB_ENDPT_EPTXEN (1 << 2) /* Bit 2: Enable the endpoint for TX transfers */
-#define USB_ENDPT_EPRXEN (1 << 3) /* Bit 3: Enable the endpoint for RX transfers */
-#define USB_ENDPT_EPCTLDIS (1 << 4) /* Bit 4: Disable control (SETUP) transfers */
- /* Bit 5: Reserved */
-#define USB_ENDPT_RETRYDIS (1 << 6) /* Bit 6: Disable host retry NAK'ed transactions (host EP0) */
-#define USB_ENDPT_HOSTWOHUB (1 << 7) /* Bit 7: Allows the host to communicate to a low speed device (host EP0) */
-
-/* USB Control Register (8-bit) */
- /* Bits 0-5: Reserved */
-#define USB_USBCTRL_PDE (1 << 6) /* Bit 6: Enables the weak pulldowns on the USB transceiver */
-#define USB_USBCTRL_SUSP (1 << 7) /* Bit 7: Places the USB transceiver into the suspend state */
-
-/* USB OTG Observe Register (8-bit) */
- /* Bits 0-3: Reserved */
-#define USB_OBSERVE_DMPD (1 << 4) /* Bit 4: D- Pull Down signal output from the USB OTG module */
- /* Bit 5: Reserved */
-#define USB_OBSERVE_DPPD (1 << 6) /* Bit 6: D+ Pull Down signal output from the USB OTG module */
-#define USB_OBSERVE_DPPU (1 << 7) /* Bit 7: D+ Pull Up signal output from the USB OTG module */
-
-/* USB OTG Control Register (8-bit) */
- /* Bits 0-3: Reserved */
-#define USB_CONTROL_DPPULLUPNONOTG (1 << 4) /* Bit 4: Controls of the DP PULLUP in the USB OTG module */
- /* Bits 5-7: Reserved */
-/* USB Transceiver Control Register 0 (8-bit) */
-
-#define USB_USBTRC0_USBRESET (1 << 7) /* Bit 7: USB reset */
- /* Bit 6: Reserved */
-#define USB_USBTRC0_USBRESMEN (1 << 5) /* Bit 5: Asynchronous Resume Interrupt Enable */
- /* Bits 2-4: Reserved */
-#define USB_USBTRC0_SYNC_DET (1 << 1) /* Bit 1: Synchronous USB Interrupt Detect */
-#define USB_USBTRC0_RESUME_INT (1 << 0) /* Bit 0: USB Asynchronous Interrupt */
-
-/* Buffer Descriptor Table (BDT) ****************************************************/
-/* Offset 0: On write (software->hardware) */
-
-#define USB_BDT_STATUS_MASK 0xfc /* Bits 2-7: Status bits */
-#define USB_BDT_BSTALL (1 << 2) /* Bit 2: Buffer Stall Enable bit */
-#define USB_BDT_DTS (1 << 3) /* Bit 3: Data Toggle Synchronization Enable bit */
-#define USB_BDT_NINC (1 << 4) /* Bit 4: DMA Address Increment Disable bit */
-#define USB_BDT_KEEP (1 << 5) /* Bit 5: BD Keep Enable bit */
-#define USB_BDT_DATA01 (1 << 6) /* Bit 6: Data Toggle Packet bit */
-#define USB_BDT_UOWN (1 << 7) /* Bit 7: USB Own bit */
-#define USB_BDT_BYTECOUNT_SHIFT (16) /* Bits 16-25: Byte Count bits */
-#define USB_BDT_BYTECOUNT_MASK (0x3ff << USB_BDT_BYTECOUNT_SHIFT)
-
-#define USB_BDT_DATA0 0 /* DATA0 packet expected next */
-#define USB_BDT_DATA1 USB_BDT_DATA01 /* DATA1 packet expected next */
-#define USB_BDT_COWN 0 /* CPU owns the descriptor */
-
-/* Offset 0: On read (hardware->software) */
-
-#define USB_BDT_PID_SHIFT (2) /* Bits 2-5: Packet Identifier bits */
-#define USB_BDT_PID_MASK (15 << USB_BDT_PID_SHIFT)
- /* Bit 7: USB Own bit (same) */
- /* Bits 16-25: Byte Count bits (same) */
-
-/* Offset 4: BUFFER_ADDRESS, 32-bit Buffer Address bits */
-
-#define USB_BDT_BYTES_SIZE 8 /* Eight bytes per BDT */
-#define USB_BDT_WORD_SIZE 2 /* Two 32-bit words per BDT */
-#define USB_NBDTS_PER_EP 4 /* Number of BDTS per endpoint: IN/OUT and EVEN/ODD */
+#include "chip/kinetis_usbotg.h"
/************************************************************************************
* Public Types
diff --git a/arch/arm/src/kinetis/kinetis_vectors.S b/arch/arm/src/kinetis/kinetis_vectors.S
index 75c295ae033342bc25f0f64c80aa99beee7e3372..39f07fc000f041f11ddcaaf0293f876aa2b12faa 100644
--- a/arch/arm/src/kinetis/kinetis_vectors.S
+++ b/arch/arm/src/kinetis/kinetis_vectors.S
@@ -42,6 +42,7 @@
#include
+#include "chip.h"
#include "exc_return.h"
/************************************************************************************************
@@ -160,7 +161,7 @@ _vectors:
* K20P64M72SF1RM
*/
-#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
+#if defined(KINETIS_K20)
.word kinetis_dmach0 /* Vector 16: DMA channel 0 transfer complete */
.word kinetis_dmach1 /* Vector 17: DMA channel 1 transfer complete */
.word kinetis_dmach2 /* Vector 18: DMA channel 2 transfer complete */
@@ -263,9 +264,7 @@ _vectors:
* K40P144M100SF2RM
*/
-#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
+#elif defined(KINETIS_K40)
.word kinetis_dmach0 /* Vector 16: DMA channel 0 transfer complete */
.word kinetis_dmach1 /* Vector 17: DMA channel 1 transfer complete */
@@ -369,10 +368,7 @@ _vectors:
* K60P144M100SF2RM
*/
-#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) || defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) || \
- defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK60N256VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK60X256VMD100) || defined(CONFIG_ARCH_CHIP_MK60N512VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK60N512VLL100)
+#elif defined(KINETIS_K60)
.word kinetis_dmach0 /* Vector 16: DMA channel 0 transfer complete */
.word kinetis_dmach1 /* Vector 17: DMA channel 1 transfer complete */
@@ -478,6 +474,102 @@ _vectors:
.word kinetis_reserved /* Vector 117: Reserved */
.word kinetis_reserved /* Vector 118: Reserved */
.word kinetis_reserved /* Vector 119: Reserved */
+
+/* K64 Family ***********************************************************************************
+ *
+ * The memory map for the following parts is defined in Freescale document
+ * MK64FX512VLL12
+ */
+
+#elif defined(KINETIS_K64)
+
+ .word kinetis_dmach0 /* Vector 16: DMA channel 0 transfer complete */
+ .word kinetis_dmach1 /* Vector 17: DMA channel 1 transfer complete */
+ .word kinetis_dmach2 /* Vector 18: DMA channel 2 transfer complete */
+ .word kinetis_dmach3 /* Vector 19: DMA channel 3 transfer complete */
+ .word kinetis_dmach4 /* Vector 20: DMA channel 4 transfer complete */
+ .word kinetis_dmach5 /* Vector 21: DMA channel 5 transfer complete */
+ .word kinetis_dmach6 /* Vector 22: DMA channel 6 transfer complete */
+ .word kinetis_dmach7 /* Vector 23: DMA channel 7 transfer complete */
+ .word kinetis_dmach8 /* Vector 24: DMA channel 8 transfer complete */
+ .word kinetis_dmach9 /* Vector 25: DMA channel 9 transfer complete */
+ .word kinetis_dmach10 /* Vector 26: DMA channel 10 transfer complete */
+ .word kinetis_dmach11 /* Vector 27: DMA channel 11 transfer complete */
+ .word kinetis_dmach12 /* Vector 28: DMA channel 12 transfer complete */
+ .word kinetis_dmach13 /* Vector 29: DMA channel 13 transfer complete */
+ .word kinetis_dmach14 /* Vector 30: DMA channel 14 transfer complete */
+ .word kinetis_dmach15 /* Vector 31: DMA channel 15 transfer complete */
+ .word kinetis_dmaerr /* Vector 32: DMA error interrupt channels 0-15 */
+ .word kinetis_mcm /* Vector 33: MCM Normal interrupt */
+ .word kinetis_flashcc /* Vector 34: Flash memory command complete */
+ .word kinetis_flashrc /* Vector 35: Flash memory read collision */
+ .word kinetis_smclvd /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */
+ .word kinetis_llwu /* Vector 37: LLWU Normal Low Leakage Wakeup */
+ .word kinetis_wdog /* Vector 38: Watchdog */
+ .word kinetis_rngb /* Vector 39: Random number generator */
+ .word kinetis_i2c0 /* Vector 40: I2C0 */
+ .word kinetis_i2c1 /* Vector 41: I2C1 */
+ .word kinetis_spi0 /* Vector 42: SPI0 all sources */
+ .word kinetis_spi1 /* Vector 43: SPI1 all sources */
+ .word kinetis_i2s0 /* Vector 44: Transmit */
+ .word kinetis_i2s1 /* Vector 45: Transmit */
+ .word kinetis_reserved /* Vector 46: Reserved */
+ .word kinetis_uart0s /* Vector 47: UART0 status */
+ .word kinetis_uart0e /* Vector 48: UART0 error */
+ .word kinetis_uart1s /* Vector 49: UART1 status */
+ .word kinetis_uart1e /* Vector 50: UART1 error */
+ .word kinetis_uart2s /* Vector 51: UART2 status */
+ .word kinetis_uart2e /* Vector 52: UART2 error */
+ .word kinetis_uart3s /* Vector 53: UART3 status */
+ .word kinetis_uart3e /* Vector 54: UART3 error */
+ .word kinetis_adc0 /* Vector 55: ADC0 */
+ .word kinetis_cmp0 /* Vector 56: CMP0 */
+ .word kinetis_cmp1 /* Vector 57: CMP1 */
+ .word kinetis_ftm0 /* Vector 58: FTM0 all sources */
+ .word kinetis_ftm1 /* Vector 59: FTM1 all sources */
+ .word kinetis_ftm2 /* Vector 60: FTM2 all sources */
+ .word kinetis_cmt /* Vector 61: CMT */
+ .word kinetis_rtc0 /* Vector 62: RTC alarm interrupt */
+ .word kinetis_rtc1 /* Vector 63: RTC seconds interrupt */
+ .word kinetis_pitch0 /* Vector 64: PIT channel 0 */
+ .word kinetis_pitch1 /* Vector 65: PIT channel 1 */
+ .word kinetis_pitch2 /* Vector 66: PIT channel 2 */
+ .word kinetis_pitch3 /* Vector 67: PIT channel 3 */
+ .word kinetis_pdb /* Vector 68: PDB */
+ .word kinetis_usbotg /* Vector 68: USB OTG */
+ .word kinetis_usbcd /* Vector 70: USB charger detect */
+ .word kinetis_reserved /* Vector 71: Reserved */
+ .word kinetis_dac0 /* Vector 72: DAC0 */
+ .word kinetis_mcg /* Vector 73: MCG */
+ .word kinetis_lpt /* Vector 74: Low power timer */
+ .word kinetis_porta /* Vector 75: Pin detect port A */
+ .word kinetis_portb /* Vector 76: Pin detect port B */
+ .word kinetis_portc /* Vector 77: Pin detect port C */
+ .word kinetis_portd /* Vector 78: Pin detect port D */
+ .word kinetis_porte /* Vector 79: Pin detect port E */
+ .word kinetis_software /* Vector 80: Software interrupt */
+ .word kinetis_spi2 /* Vector 81: SPI2 all sources */
+ .word kinetis_uart4s /* Vector 82: UART4 status */
+ .word kinetis_uart4e /* Vector 83: UART4 error */
+ .word kinetis_uart5s /* Vector 84: UART5 status */
+ .word kinetis_uart5e /* Vector 85: UART5 error */
+ .word kinetis_cmp2 /* Vector 86: CMP2 */
+ .word kinetis_ftm3 /* Vector 87: FTM3 all sources */
+ .word kinetis_dac1 /* Vector 88: DAC1 */
+ .word kinetis_adc1 /* Vector 89: ADC1 */
+ .word kinetis_i2c2 /* Vector 90: I2C2 */
+ .word kinetis_can0mb /* Vector 91: CAN0 ORed Message buffer (0-15) */
+ .word kinetis_can0bo /* Vector 92: CAN0 Bus Off */
+ .word kinetis_can0err /* Vector 93: CAN0 Error */
+ .word kinetis_can0tw /* Vector 94: CAN0 Transmit Warning */
+ .word kinetis_can0rw /* Vector 95: CAN0 Receive Warning */
+ .word kinetis_can0wu /* Vector 96: CAN0 Wake UP */
+ .word kinetis_sdhc /* Vector 97: SDHC */
+ .word kinetis_emactmr /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */
+ .word kinetis_emactx /* Vector 92: Ethernet MAC transmit interrupt */
+ .word kinetis_emacrx /* Vector 93: Ethernet MAC receive interrupt */
+ .word kinetis_emacmisc /* Vector 94: Ethernet MAC error and misc interrupt */
+
#else
# error "No vectors for this Kinetis part"
#endif
@@ -505,13 +597,13 @@ handlers:
HANDLER kinetis_systick, KINETIS_IRQ_SYSTICK /* Vector 15: System tick */
/* External Interrupts **************************************************************************/
-/* K40 Family ***********************************************************************************
+/* K20 Family ***********************************************************************************
*
* The interrupt vectors for the following parts is defined in Freescale document
* K20P64M72SF1RM
*/
-#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
+#if defined(KINETIS_K20)
HANDLER kinetis_dmach0, KINETIS_IRQ_DMACH0 /* Vector 16: DMA channel 0 transfer complete */
HANDLER kinetis_dmach1, KINETIS_IRQ_DMACH1 /* Vector 17: DMA channel 1 transfer complete */
@@ -585,9 +677,7 @@ handlers:
* K40P144M100SF2RM
*/
-#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
+#elif defined(KINETIS_K40)
HANDLER kinetis_dmach0, KINETIS_IRQ_DMACH0 /* Vector 16: DMA channel 0 transfer complete */
HANDLER kinetis_dmach1, KINETIS_IRQ_DMACH1 /* Vector 17: DMA channel 1 transfer complete */
@@ -679,10 +769,7 @@ handlers:
* K60P144M100SF2RM
*/
-#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) || defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) || \
- defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK60N256VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK60X256VMD100) || defined(CONFIG_ARCH_CHIP_MK60N512VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK60N512VLL100)
+#elif defined(KINETIS_K60)
HANDLER kinetis_dmach0, KINETIS_IRQ_DMACH0 /* Vector 16: DMA channel 0 transfer complete */
HANDLER kinetis_dmach1, KINETIS_IRQ_DMACH1 /* Vector 17: DMA channel 1 transfer complete */
@@ -771,6 +858,99 @@ handlers:
HANDLER kinetis_portd, KINETIS_IRQ_PORTD /* Vector 106: Pin detect port D */
HANDLER kinetis_porte, KINETIS_IRQ_PORTE /* Vector 107: Pin detect port E */
+/* K64 Family ***********************************************************************************
+ *
+ * The memory map for the following parts is defined in Freescale document
+ * MK64FX512VLL12
+ */
+
+#elif defined(KINETIS_K64)
+
+ HANDLER kinetis_dmach0, KINETIS_IRQ_DMACH0 /* Vector 16: DMA channel 0 transfer complete */
+ HANDLER kinetis_dmach1, KINETIS_IRQ_DMACH1 /* Vector 17: DMA channel 1 transfer complete */
+ HANDLER kinetis_dmach2, KINETIS_IRQ_DMACH2 /* Vector 18: DMA channel 2 transfer complete */
+ HANDLER kinetis_dmach3, KINETIS_IRQ_DMACH3 /* Vector 19: DMA channel 3 transfer complete */
+ HANDLER kinetis_dmach4, KINETIS_IRQ_DMACH4 /* Vector 20: DMA channel 4 transfer complete */
+ HANDLER kinetis_dmach5, KINETIS_IRQ_DMACH5 /* Vector 21: DMA channel 5 transfer complete */
+ HANDLER kinetis_dmach6, KINETIS_IRQ_DMACH6 /* Vector 22: DMA channel 6 transfer complete */
+ HANDLER kinetis_dmach7, KINETIS_IRQ_DMACH7 /* Vector 23: DMA channel 7 transfer complete */
+ HANDLER kinetis_dmach8, KINETIS_IRQ_DMACH8 /* Vector 24: DMA channel 8 transfer complete */
+ HANDLER kinetis_dmach9, KINETIS_IRQ_DMACH9 /* Vector 25: DMA channel 9 transfer complete */
+ HANDLER kinetis_dmach10, KINETIS_IRQ_DMACH10 /* Vector 26: DMA channel 10 transfer complete */
+ HANDLER kinetis_dmach11, KINETIS_IRQ_DMACH11 /* Vector 27: DMA channel 11 transfer complete */
+ HANDLER kinetis_dmach12, KINETIS_IRQ_DMACH12 /* Vector 28: DMA channel 12 transfer complete */
+ HANDLER kinetis_dmach13, KINETIS_IRQ_DMACH13 /* Vector 29: DMA channel 13 transfer complete */
+ HANDLER kinetis_dmach14, KINETIS_IRQ_DMACH14 /* Vector 30: DMA channel 14 transfer complete */
+ HANDLER kinetis_dmach15, KINETIS_IRQ_DMACH15 /* Vector 31: DMA channel 15 transfer complete */
+ HANDLER kinetis_dmaerr, KINETIS_IRQ_DMAERR /* Vector 32: DMA error interrupt channels 0-15 */
+ HANDLER kinetis_mcm, KINETIS_IRQ_MCM /* Vector 33: MCM Normal interrupt */
+ HANDLER kinetis_flashcc, KINETIS_IRQ_FLASHCC /* Vector 34: Flash memory command complete */
+ HANDLER kinetis_flashrc, KINETIS_IRQ_FLASHRC /* Vector 35: Flash memory read collision */
+ HANDLER kinetis_smclvd, KINETIS_IRQ_SMCLVD /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */
+ HANDLER kinetis_llwu, KINETIS_IRQ_LLWU /* Vector 37: LLWU Normal Low Leakage Wakeup */
+ HANDLER kinetis_wdog, KINETIS_IRQ_WDOG /* Vector 38: Watchdog */
+ HANDLER kinetis_rngb, KINETIS_IRQ_RNGB /* Vector 39: Random number generator */
+ HANDLER kinetis_i2c0, KINETIS_IRQ_I2C0 /* Vector 40: I2C0 */
+ HANDLER kinetis_i2c1, KINETIS_IRQ_I2C1 /* Vector 41: I2C1 */
+ HANDLER kinetis_spi0, KINETIS_IRQ_SPI0 /* Vector 42: SPI0 all sources */
+ HANDLER kinetis_spi1, KINETIS_IRQ_SPI1 /* Vector 43: SPI1 all sources */
+ HANDLER kinetis_i2s0, KINETIS_IRQ_I2S0 /* Vector 44: Transmit */
+ HANDLER kinetis_i2s1, KINETIS_IRQ_I2S1 /* Vector 45: Transmit */
+ HANDLER kinetis_uart0s, KINETIS_IRQ_UART0S /* Vector 47: UART0 status */
+ HANDLER kinetis_uart0e, KINETIS_IRQ_UART0E /* Vector 48: UART0 error */
+ HANDLER kinetis_uart1s, KINETIS_IRQ_UART1S /* Vector 49: UART1 status */
+ HANDLER kinetis_uart1e, KINETIS_IRQ_UART1E /* Vector 50: UART1 error */
+ HANDLER kinetis_uart2s, KINETIS_IRQ_UART2S /* Vector 51: UART2 status */
+ HANDLER kinetis_uart2e, KINETIS_IRQ_UART2E /* Vector 52: UART2 error */
+ HANDLER kinetis_uart3s, KINETIS_IRQ_UART3S /* Vector 53: UART3 status */
+ HANDLER kinetis_uart3e, KINETIS_IRQ_UART3E /* Vector 54: UART3 error */
+ HANDLER kinetis_adc0, KINETIS_IRQ_ADC0 /* Vector 55: ADC0 */
+ HANDLER kinetis_cmp0, KINETIS_IRQ_CMP0 /* Vector 56: CMP0 */
+ HANDLER kinetis_cmp1, KINETIS_IRQ_CMP1 /* Vector 57: CMP1 */
+ HANDLER kinetis_ftm0, KINETIS_IRQ_FTM0 /* Vector 58: FTM0 all sources */
+ HANDLER kinetis_ftm1, KINETIS_IRQ_FTM1 /* Vector 59: FTM1 all sources */
+ HANDLER kinetis_ftm2, KINETIS_IRQ_FTM2 /* Vector 60: FTM2 all sources */
+ HANDLER kinetis_cmt, KINETIS_IRQ_CMT /* Vector 61: CMT */
+ HANDLER kinetis_rtc0, KINETIS_IRQ_RTC0 /* Vector 62: RTC alarm interrupt */
+ HANDLER kinetis_rtc1, KINETIS_IRQ_RTC1 /* Vector 63: RTC seconds interrupt */
+ HANDLER kinetis_pitch0, KINETIS_IRQ_PITCH0 /* Vector 64: PIT channel 0 */
+ HANDLER kinetis_pitch1, KINETIS_IRQ_PITCH1 /* Vector 65: PIT channel 1 */
+ HANDLER kinetis_pitch2, KINETIS_IRQ_PITCH2 /* Vector 66: PIT channel 2 */
+ HANDLER kinetis_pitch3, KINETIS_IRQ_PITCH3 /* Vector 67: PIT channel 3 */
+ HANDLER kinetis_pdb, KINETIS_IRQ_PDB /* Vector 68: PDB */
+ HANDLER kinetis_usbotg, KINETIS_IRQ_USBOTG /* Vector 68: USB OTG */
+ HANDLER kinetis_usbcd, KINETIS_IRQ_USBCD /* Vector 70: USB charger detect */
+ HANDLER kinetis_dac0, KINETIS_IRQ_DAC0 /* Vector 72: DAC0 */
+ HANDLER kinetis_mcg, KINETIS_IRQ_MCG /* Vector 73: MCG */
+ HANDLER kinetis_lpt, KINETIS_IRQ_LPT /* Vector 74: Low power timer */
+ HANDLER kinetis_porta, KINETIS_IRQ_PORTA /* Vector 75: Pin detect port A */
+ HANDLER kinetis_portb, KINETIS_IRQ_PORTB /* Vector 76: Pin detect port B */
+ HANDLER kinetis_portc, KINETIS_IRQ_PORTC /* Vector 77: Pin detect port C */
+ HANDLER kinetis_portd, KINETIS_IRQ_PORTD /* Vector 78: Pin detect port D */
+ HANDLER kinetis_porte, KINETIS_IRQ_PORTE /* Vector 79: Pin detect port E */
+ HANDLER kinetis_software, KINETIS_IRQ_SOFTWARE /* Vector 80: Software interrupt */
+ HANDLER kinetis_spi2, KINETIS_IRQ_SPI2 /* Vector 81: SPI2 all sources */
+ HANDLER kinetis_uart4s, KINETIS_IRQ_UART4S /* Vector 82: UART4 status */
+ HANDLER kinetis_uart4e, KINETIS_IRQ_UART4E /* Vector 83: UART4 error */
+ HANDLER kinetis_uart5s, KINETIS_IRQ_UART5S /* Vector 84: UART5 status */
+ HANDLER kinetis_uart5e, KINETIS_IRQ_UART5E /* Vector 85: UART5 error */
+ HANDLER kinetis_cmp2, KINETIS_IRQ_CMP2 /* Vector 86: CMP2 */
+ HANDLER kinetis_ftm3, KINETIS_IRQ_FTM3 /* Vector 87: FTM3 all sources */
+ HANDLER kinetis_dac1, KINETIS_IRQ_DAC1 /* Vector 88: DAC1 */
+ HANDLER kinetis_adc1, KINETIS_IRQ_ADC1 /* Vector 89: ADC1 */
+ HANDLER kinetis_i2c2, KINETIS_IRQ_I2C2 /* Vector 90: I2C2 */
+ HANDLER kinetis_can0mb, KINETIS_IRQ_CAN0MB /* Vector 91: CAN0 ORed Message buffer (0-15) */
+ HANDLER kinetis_can0bo, KINETIS_IRQ_CAN0BO /* Vector 92: CAN0 Bus Off */
+ HANDLER kinetis_can0err, KINETIS_IRQ_CAN0ERR /* Vector 93: CAN0 Error */
+ HANDLER kinetis_can0tw, KINETIS_IRQ_CAN0TW /* Vector 94: CAN0 Transmit Warning */
+ HANDLER kinetis_can0rw, KINETIS_IRQ_CAN0RW /* Vector 95: CAN0 Receive Warning */
+ HANDLER kinetis_can0wu, KINETIS_IRQ_CAN0WU /* Vector 96: CAN0 Wake UP */
+ HANDLER kinetis_sdhc, KINETIS_IRQ_SDHC /* Vector 97: SDHC */
+ HANDLER kinetis_emactmr, KINETIS_IRQ_EMACTMR /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */
+ HANDLER kinetis_emactx, KINETIS_IRQ_EMACTX /* Vector 92: Ethernet MAC transmit interrupt */
+ HANDLER kinetis_emacrx, KINETIS_IRQ_EMACRX /* Vector 93: Ethernet MAC receive interrupt */
+ HANDLER kinetis_emacmisc, KINETIS_IRQ_EMACMISC /* Vector 94: Ethernet MAC error and misc interrupt */
+
#else
# error "No handlers for this Kinetis part"
#endif
diff --git a/arch/arm/src/kinetis/kinetis_wdog.c b/arch/arm/src/kinetis/kinetis_wdog.c
index 9dc29b80d8963576c400758580b4fa4edecb5945..3beaad8d4bce5d1e0db6153578fe1d9290903f67 100644
--- a/arch/arm/src/kinetis/kinetis_wdog.c
+++ b/arch/arm/src/kinetis/kinetis_wdog.c
@@ -1,6 +1,5 @@
/****************************************************************************
* arch/arm/src/kinetis/kinetis_wdog.c
- * arch/arm/src/chip/kinetis_wdog.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -44,19 +43,7 @@
#include "up_arch.h"
#include "kinetis.h"
-#include "kinetis_wdog.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
+#include "chip/kinetis_wdog.h"
/****************************************************************************
* Private Functions
diff --git a/arch/arm/src/kl/Kconfig b/arch/arm/src/kl/Kconfig
index bfa40491538f8c3300f45d1023645450989ce28e..7dd13a686b9b4dd29e0f28529411e52c40cb07f9 100644
--- a/arch/arm/src/kl/Kconfig
+++ b/arch/arm/src/kl/Kconfig
@@ -345,12 +345,12 @@ config KL_TPM2_CHANNEL
comment "Kinetis GPIO Interrupt Configuration"
-config GPIO_IRQ
+config KL_GPIOIRQ
bool "GPIO pin interrupts"
---help---
Enable support for interrupting GPIO pins
-if GPIO_IRQ
+if KL_GPIOIRQ
config KL_PORTAINTS
bool "GPIOA interrupts"
diff --git a/arch/arm/src/kl/Make.defs b/arch/arm/src/kl/Make.defs
index 105d267a73ac32ea846f1d8b2e12103b7eb02e18..d7712f0983c2a868e54f756ff21d1c2e02cfc830 100644
--- a/arch/arm/src/kl/Make.defs
+++ b/arch/arm/src/kl/Make.defs
@@ -81,7 +81,7 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += kl_userspace.c
endif
-ifeq ($(CONFIG_GPIO_IRQ),y)
+ifeq ($(CONFIG_KL_GPIOIRQ),y)
CHIP_CSRCS += kl_gpioirq.c
endif
diff --git a/arch/arm/src/kl/kl_dumpgpio.c b/arch/arm/src/kl/kl_dumpgpio.c
index 8ca8e15002361720bed568829b383edd2d43a6e7..0e6dadfd8ef0cdacd35a067bfe759828ece1a0e4 100644
--- a/arch/arm/src/kl/kl_dumpgpio.c
+++ b/arch/arm/src/kl/kl_dumpgpio.c
@@ -118,12 +118,12 @@ void kl_dumpgpio(gpio_cfgset_t pinset, const char *msg)
flags = enter_critical_section();
- _llinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
- g_portchar[port], pinset, base, msg);
- _llinfo(" PDOR: %08x PDIR: %08x PDDR: %08x\n",
- getreg32(base + KL_GPIO_PDOR_OFFSET),
- getreg32(base + KL_GPIO_PDIR_OFFSET),
- getreg32(base + KL_GPIO_PDDR_OFFSET));
+ _info("GPIO%c pinset: %08x base: %08x -- %s\n",
+ g_portchar[port], pinset, base, msg);
+ _info(" PDOR: %08x PDIR: %08x PDDR: %08x\n",
+ getreg32(base + KL_GPIO_PDOR_OFFSET),
+ getreg32(base + KL_GPIO_PDIR_OFFSET),
+ getreg32(base + KL_GPIO_PDDR_OFFSET));
leave_critical_section(flags);
}
diff --git a/arch/arm/src/kl/kl_gpio.h b/arch/arm/src/kl/kl_gpio.h
index fc2cd7f37e99e6972ba01504f43146b3fd1f8d90..0024e67608686b7ca892cd80b648054ea7a1a0ea 100644
--- a/arch/arm/src/kl/kl_gpio.h
+++ b/arch/arm/src/kl/kl_gpio.h
@@ -386,7 +386,7 @@ xcpt_t kl_gpioirqattach(uint32_t pinset, xcpt_t pinisr);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KL_GPIOIRQ
void kl_gpioirqenable(uint32_t pinset);
#else
# define kl_gpioirqenable(pinset)
@@ -400,7 +400,7 @@ void kl_gpioirqenable(uint32_t pinset);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KL_GPIOIRQ
void kl_gpioirqdisable(uint32_t pinset);
#else
# define kl_gpioirqdisable(pinset)
diff --git a/arch/arm/src/kl/kl_gpioirq.c b/arch/arm/src/kl/kl_gpioirq.c
index 2b481bce3a22b7a58fe29266fafb824de1ed92f9..61331343ccd404672977b3f8f174967b7947a013 100644
--- a/arch/arm/src/kl/kl_gpioirq.c
+++ b/arch/arm/src/kl/kl_gpioirq.c
@@ -51,7 +51,7 @@
#include "chip/kl_port.h"
#include "kl_gpio.h"
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KL_GPIOIRQ
/****************************************************************************
* Pre-processor Definitions
@@ -396,4 +396,4 @@ void kl_gpioirqdisable(uint32_t pinset)
}
#endif /* HAVE_PORTINTS */
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_KL_GPIOIRQ */
diff --git a/arch/arm/src/kl/kl_idle.c b/arch/arm/src/kl/kl_idle.c
index 1122cf43917ce9556cac99f739be7b0e0dd6ae75..f7db42f276cc89e8a4d64f6ae9c6a08e5db869de 100644
--- a/arch/arm/src/kl/kl_idle.c
+++ b/arch/arm/src/kl/kl_idle.c
@@ -103,7 +103,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
- _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
+ _info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
diff --git a/arch/arm/src/kl/kl_irq.c b/arch/arm/src/kl/kl_irq.c
index b37f7afe1c99aa98cd2c7ad88a5ff247b5b86e01..94628f26bf7179fdd81ea7ca787541749e6ece94 100644
--- a/arch/arm/src/kl/kl_irq.c
+++ b/arch/arm/src/kl/kl_irq.c
@@ -248,7 +248,7 @@ void up_irqinitialize(void)
* configured pin interrupts.
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_KL_GPIOIRQ
kl_gpioirqinitialize();
#endif
diff --git a/arch/arm/src/kl/kl_pwm.c b/arch/arm/src/kl/kl_pwm.c
index 6f3f6e40503b5ae149b55a772db9713e3827182e..a34aa0f8175b08e9130051208edd70ce36301a19 100644
--- a/arch/arm/src/kl/kl_pwm.c
+++ b/arch/arm/src/kl/kl_pwm.c
@@ -48,7 +48,7 @@
#include
#include
-#include
+#include
#include
#include "up_internal.h"
diff --git a/arch/arm/src/kl/kl_pwm.h b/arch/arm/src/kl/kl_pwm.h
index f9afbcd7800e602b7c695fcdb67992d71cff7d5d..5b64e40967be318f3e3e8e639766e9cfac1e1a71 100644
--- a/arch/arm/src/kl/kl_pwm.h
+++ b/arch/arm/src/kl/kl_pwm.h
@@ -90,13 +90,13 @@
# elif CONFIG_KL_TPM0_CHANNEL == 1
# define PWM_TPM0_PINCFG GPIO_TPM0_CH1OUT
# elif CONFIG_KL_TPM0_CHANNEL == 2
-# define PWM_TPM0_PINCFG GPIO_TPM1_CH2OUT
+# define PWM_TPM0_PINCFG GPIO_TPM0_CH2OUT
# elif CONFIG_KL_TPM0_CHANNEL == 3
-# define PWM_TPM0_PINCFG GPIO_TPM1_CH3OUT
+# define PWM_TPM0_PINCFG GPIO_TPM0_CH3OUT
# elif CONFIG_KL_TPM0_CHANNEL == 4
-# define PWM_TPM0_PINCFG GPIO_TPM1_CH4OUT
+# define PWM_TPM0_PINCFG GPIO_TPM0_CH4OUT
# elif CONFIG_KL_TPM0_CHANNEL == 5
-# define PWM_TPM0_PINCFG GPIO_TPM1_CH5OUT
+# define PWM_TPM0_PINCFG GPIO_TPM0_CH5OUT
# else
# error "Unsupported value of CONFIG_KL_TPM1_CHANNEL"
# endif
diff --git a/arch/arm/src/lpc11xx/Kconfig b/arch/arm/src/lpc11xx/Kconfig
index 31a9711cf078a719d6502a45c4f9e19a5f8cd708..33ab254958bb23bb05b65b566c397d0099c3936b 100644
--- a/arch/arm/src/lpc11xx/Kconfig
+++ b/arch/arm/src/lpc11xx/Kconfig
@@ -237,7 +237,7 @@ config CAN_REGDEBUG
endmenu
-config GPIO_IRQ
+config LPC11_GPIOIRQ
bool "GPIO interrupt support"
default n
---help---
diff --git a/arch/arm/src/lpc11xx/Make.defs b/arch/arm/src/lpc11xx/Make.defs
index 041419c2488e42776cb9ed6abd3270ec76e896c7..a347d99946db688d542fd0710eff486accc2a8be 100644
--- a/arch/arm/src/lpc11xx/Make.defs
+++ b/arch/arm/src/lpc11xx/Make.defs
@@ -84,7 +84,7 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += lpc11_userspace.c
endif
-ifeq ($(CONFIG_GPIO_IRQ),y)
+ifeq ($(CONFIG_LPC11_GPIOIRQ),y)
CHIP_CSRCS += lpc11_gpioint.c
endif
diff --git a/arch/arm/src/lpc11xx/lpc111x_gpio.c b/arch/arm/src/lpc11xx/lpc111x_gpio.c
index 6a0718e11d7c176a2a1e08736acf3d4d15746052..cba1ee717349fbb25aa3fce1b712011182aecccc 100644
--- a/arch/arm/src/lpc11xx/lpc111x_gpio.c
+++ b/arch/arm/src/lpc11xx/lpc111x_gpio.c
@@ -79,7 +79,7 @@
* actually set up to interrupt until the interrupt is enabled.
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
uint64_t g_intedge0;
uint64_t g_intedge2;
#endif
@@ -295,7 +295,7 @@ static int lpc11_pullup(lpc11_pinset_t cfgset, unsigned int port,
*
****************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
static void lpc11_setintedge(unsigned int port, unsigned int pin,
unsigned int value)
{
@@ -323,7 +323,7 @@ static void lpc11_setintedge(unsigned int port, unsigned int pin,
*intedge &= ~((uint64_t)3 << shift);
*intedge |= ((uint64_t)value << shift);
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_LPC11_GPIOIRQ */
/****************************************************************************
* Name: lpc11_setopendrain
@@ -453,7 +453,7 @@ static inline int lpc11_configinput(lpc11_pinset_t cfgset, unsigned int port,
/* Forget about any falling/rising edge interrupt enabled */
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
lpc11_setintedge(port, pin, 0);
#endif
}
@@ -495,7 +495,7 @@ static inline int lpc11_configinterrupt(lpc11_pinset_t cfgset, unsigned int port
/* Then just remember the rising/falling edge interrupt enabled */
DEBUGASSERT(port == 0 || port == 2);
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
lpc11_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT);
#endif
return OK;
diff --git a/arch/arm/src/lpc11xx/lpc11_gpio.h b/arch/arm/src/lpc11xx/lpc11_gpio.h
index a0e1c2d8990d8e2dc769ac30a97c71ed03789aaa..f77b748613e938975321bb827c82ad6a7af9c13f 100644
--- a/arch/arm/src/lpc11xx/lpc11_gpio.h
+++ b/arch/arm/src/lpc11xx/lpc11_gpio.h
@@ -88,7 +88,7 @@ extern "C"
* lpc11_gpioint.c, and lpc11_gpiodbg.c
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
EXTERN uint64_t g_intedge0;
EXTERN uint64_t g_intedge2;
#endif
@@ -108,7 +108,7 @@ EXTERN const uint32_t g_intbase[GPIO_NPORTS];
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
void lpc11_gpioirqinitialize(void);
#else
# define lpc11_gpioirqinitialize()
@@ -152,7 +152,7 @@ bool lpc11_gpioread(lpc11_pinset_t pinset);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
void lpc11_gpioirqenable(int irq);
#else
# define lpc11_gpioirqenable(irq)
@@ -166,7 +166,7 @@ void lpc11_gpioirqenable(int irq);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
void lpc11_gpioirqdisable(int irq);
#else
# define lpc11_gpioirqdisable(irq)
diff --git a/arch/arm/src/lpc11xx/lpc11_gpioint.c b/arch/arm/src/lpc11xx/lpc11_gpioint.c
index 4ce6b48c9ed376f9f95b7b47fcbe1cd2a634bba7..8aaefed14978676be72020bd9e9b107d6da46487 100644
--- a/arch/arm/src/lpc11xx/lpc11_gpioint.c
+++ b/arch/arm/src/lpc11xx/lpc11_gpioint.c
@@ -51,7 +51,7 @@
#include "chip.h"
#include "lpc11_gpio.h"
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
/****************************************************************************
* Pre-processor Definitions
@@ -543,5 +543,5 @@ void lpc11_gpioirqdisable(int irq)
}
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_LPC11_GPIOIRQ */
diff --git a/arch/arm/src/lpc11xx/lpc11_irq.c b/arch/arm/src/lpc11xx/lpc11_irq.c
index f861943bc0a111522e571bc9f75b917dde8cc2f0..4399c5820031c8d3e8f85744603e2a0f57d1b939 100644
--- a/arch/arm/src/lpc11xx/lpc11_irq.c
+++ b/arch/arm/src/lpc11xx/lpc11_irq.c
@@ -244,7 +244,7 @@ void up_irqinitialize(void)
* configured pin interrupts.
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC11_GPIOIRQ
lpc11_gpioirqinitialize();
#endif
diff --git a/arch/arm/src/lpc11xx/lpc11_timer.c b/arch/arm/src/lpc11xx/lpc11_timer.c
index e742dc2de0b97ad5690f9d544edc2264769709a2..a9ce65a073a57645e8953559dbad8e060657a096 100644
--- a/arch/arm/src/lpc11xx/lpc11_timer.c
+++ b/arch/arm/src/lpc11xx/lpc11_timer.c
@@ -47,7 +47,7 @@
#include
#include
-#include
+#include
#include
#include "up_internal.h"
diff --git a/arch/arm/src/lpc17xx/Kconfig b/arch/arm/src/lpc17xx/Kconfig
index abfd205fedcbd26c96c252541a1794164a766e33..5038000d8655d0f16303b5aae8fc9491bea0a331 100644
--- a/arch/arm/src/lpc17xx/Kconfig
+++ b/arch/arm/src/lpc17xx/Kconfig
@@ -604,7 +604,7 @@ config LPC17_CAN_REGDEBUG
endmenu
-config GPIO_IRQ
+config LPC17_GPIOIRQ
bool "GPIO interrupt support"
default n
---help---
diff --git a/arch/arm/src/lpc17xx/Make.defs b/arch/arm/src/lpc17xx/Make.defs
index 919f70e75799a37d9fc011c04a80c7136aa74a25..f1dd3cde114f18e6d94e429391c1bf233048cb54 100644
--- a/arch/arm/src/lpc17xx/Make.defs
+++ b/arch/arm/src/lpc17xx/Make.defs
@@ -133,7 +133,7 @@ ifeq ($(CONFIG_LPC17_EMC),y)
CHIP_CSRCS += lpc17_emc.c
endif
-ifeq ($(CONFIG_GPIO_IRQ),y)
+ifeq ($(CONFIG_LPC17_GPIOIRQ),y)
CHIP_CSRCS += lpc17_gpioint.c
endif
diff --git a/arch/arm/src/lpc17xx/lpc176x_gpio.c b/arch/arm/src/lpc17xx/lpc176x_gpio.c
index 7de2fd04bcce93b7001a1a16e54951537170fd97..b2b8e9805ab5cae6da35de2a75d27e61b802e7f4 100644
--- a/arch/arm/src/lpc17xx/lpc176x_gpio.c
+++ b/arch/arm/src/lpc17xx/lpc176x_gpio.c
@@ -78,7 +78,7 @@
* actually set up to interrupt until the interrupt is enabled.
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
uint64_t g_intedge0;
uint64_t g_intedge2;
#endif
@@ -300,7 +300,7 @@ static int lpc17_pullup(lpc17_pinset_t cfgset, unsigned int port,
*
****************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
static void lpc17_setintedge(unsigned int port, unsigned int pin,
unsigned int value)
{
@@ -328,7 +328,7 @@ static void lpc17_setintedge(unsigned int port, unsigned int pin,
*intedge &= ~((uint64_t)3 << shift);
*intedge |= ((uint64_t)value << shift);
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_LPC17_GPIOIRQ */
/****************************************************************************
* Name: lpc17_setopendrain
@@ -412,7 +412,7 @@ static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port, un
/* Forget about any falling/rising edge interrupt enabled */
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
lpc17_setintedge(port, pin, 0);
#endif
}
@@ -453,7 +453,7 @@ static inline int lpc17_configinterrupt(lpc17_pinset_t cfgset, unsigned int port
/* Then just remember the rising/falling edge interrupt enabled */
DEBUGASSERT(port == 0 || port == 2);
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
lpc17_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT);
#endif
return OK;
diff --git a/arch/arm/src/lpc17xx/lpc178x_gpio.c b/arch/arm/src/lpc17xx/lpc178x_gpio.c
index a30b7d425583a47695c00a8dcecb5b6f0cae56e9..a6892d597f6c3be9db6d6bb18156c94d61561159 100644
--- a/arch/arm/src/lpc17xx/lpc178x_gpio.c
+++ b/arch/arm/src/lpc17xx/lpc178x_gpio.c
@@ -79,7 +79,7 @@
* actually set up to interrupt until the interrupt is enabled.
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
uint64_t g_intedge0;
uint64_t g_intedge2;
#endif
@@ -526,7 +526,7 @@ static void lpc17_setpullup(lpc17_pinset_t cfgset, unsigned int port,
*
****************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
static void lpc17_setintedge(unsigned int port, unsigned int pin,
unsigned int value)
{
@@ -554,7 +554,7 @@ static void lpc17_setintedge(unsigned int port, unsigned int pin,
*intedge &= ~((uint64_t)3 << shift);
*intedge |= ((uint64_t)value << shift);
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_LPC17_GPIOIRQ */
/****************************************************************************
* Name: lpc17_configinput
@@ -601,7 +601,7 @@ static inline int lpc17_configinput(lpc17_pinset_t cfgset, unsigned int port,
/* Forget about any falling/rising edge interrupt enabled */
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
lpc17_setintedge(port, pin, 0);
#endif
}
@@ -656,7 +656,7 @@ static inline int lpc17_configinterrupt(lpc17_pinset_t cfgset, unsigned int port
/* Then just remember the rising/falling edge interrupt enabled */
DEBUGASSERT(port == 0 || port == 2);
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
lpc17_setintedge(port, pin, (cfgset & GPIO_EDGE_MASK) >> GPIO_EDGE_SHIFT);
#endif
return OK;
diff --git a/arch/arm/src/lpc17xx/lpc17_can.c b/arch/arm/src/lpc17xx/lpc17_can.c
index 0c2ea65c7ef10137a6c5a182a2b2fed1fafc797b..f961bef5493959da9ebdbd3ee4810e20e2489e17 100644
--- a/arch/arm/src/lpc17xx/lpc17_can.c
+++ b/arch/arm/src/lpc17xx/lpc17_can.c
@@ -57,7 +57,7 @@
#include
#include
#include
-#include
+#include
#include "up_internal.h"
#include "up_arch.h"
@@ -308,7 +308,7 @@ static void can_printreg(uint32_t addr, uint32_t value)
{
if (count == 4)
{
- canllinfo("...\n");
+ caninfo("...\n");
}
return;
@@ -325,7 +325,7 @@ static void can_printreg(uint32_t addr, uint32_t value)
{
/* Yes.. then show how many times the value repeated */
- canllinfo("[repeats %d more times]\n", count-3);
+ caninfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -337,7 +337,7 @@ static void can_printreg(uint32_t addr, uint32_t value)
/* Show the register value read */
- canllinfo("%08x->%08x\n", addr, value);
+ caninfo("%08x->%08x\n", addr, value);
}
#endif
@@ -398,7 +398,7 @@ static void can_putreg(struct up_dev_s *priv, int offset, uint32_t value)
/* Show the register value being written */
- canllinfo("%08x<-%08x\n", addr, value);
+ caninfo("%08x<-%08x\n", addr, value);
/* Write the value */
@@ -458,7 +458,7 @@ static void can_putcommon(uint32_t addr, uint32_t value)
{
/* Show the register value being written */
- canllinfo("%08x<-%08x\n", addr, value);
+ caninfo("%08x<-%08x\n", addr, value);
/* Write the value */
@@ -942,7 +942,7 @@ static void can_interrupt(FAR struct can_dev_s *dev)
/* Read the interrupt and capture register (also clearing most status bits) */
regval = can_getreg(priv, LPC17_CAN_ICR_OFFSET);
- canllinfo("CAN%d ICR: %08x\n", priv->port, regval);
+ caninfo("CAN%d ICR: %08x\n", priv->port, regval);
/* Check for a receive interrupt */
@@ -972,7 +972,7 @@ static void can_interrupt(FAR struct can_dev_s *dev)
if ((rfs & CAN_RFS_FF) != 0)
{
- canllerr("ERROR: Received message with extended identifier. Dropped\n");
+ canerr("ERROR: Received message with extended identifier. Dropped\n");
}
else
#endif
@@ -1049,7 +1049,7 @@ static int can12_interrupt(int irq, void *context)
{
/* Handle CAN1/2 interrupts */
- canllinfo("irq: %d\n", irq);
+ caninfo("irq: %d\n", irq);
#ifdef CONFIG_LPC17_CAN1
can_interrupt(&g_can1dev);
@@ -1126,8 +1126,8 @@ static int can_bittiming(struct up_dev_s *priv)
uint32_t ts2;
uint32_t sjw;
- canllinfo("CAN%d PCLK: %d baud: %d\n", priv->port,
- CAN_CLOCK_FREQUENCY(priv->divisor), priv->baud);
+ caninfo("CAN%d PCLK: %d baud: %d\n", priv->port,
+ CAN_CLOCK_FREQUENCY(priv->divisor), priv->baud);
/* Try to get CAN_BIT_QUANTA quanta in one bit_time.
*
@@ -1179,7 +1179,7 @@ static int can_bittiming(struct up_dev_s *priv)
sjw = 1;
- canllinfo("TS1: %d TS2: %d BRP: %d SJW= %d\n", ts1, ts2, brp, sjw);
+ caninfo("TS1: %d TS2: %d BRP: %d SJW= %d\n", ts1, ts2, brp, sjw);
/* Configure bit timing */
@@ -1196,7 +1196,7 @@ static int can_bittiming(struct up_dev_s *priv)
btr |= CAN_BTR_SAM;
#endif
- canllinfo("Setting CANxBTR= 0x%08x\n", btr);
+ caninfo("Setting CANxBTR= 0x%08x\n", btr);
can_putreg(priv, LPC17_CAN_BTR_OFFSET, btr); /* Set bit timing */
return OK;
}
@@ -1224,7 +1224,7 @@ FAR struct can_dev_s *lpc17_caninitialize(int port)
irqstate_t flags;
uint32_t regval;
- canllinfo("CAN%d\n", port);
+ caninfo("CAN%d\n", port);
flags = enter_critical_section();
diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c
index d3f884b976175cba17c435750da5d08a21c5b985..13730506821648d46e4bcbbd6437d1ebf4a470f5 100644
--- a/arch/arm/src/lpc17xx/lpc17_ethernet.c
+++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c
@@ -837,8 +837,8 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
if ((*rxstat & RXSTAT_INFO_ERROR) != 0)
{
- nllerr("ERROR: considx: %08x prodidx: %08x rxstat: %08x\n",
- considx, prodidx, *rxstat);
+ nerr("ERROR: considx: %08x prodidx: %08x rxstat: %08x\n",
+ considx, prodidx, *rxstat);
NETDEV_RXERRORS(&priv->lp_dev);
}
@@ -850,21 +850,21 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
/* else */ if (pktlen > CONFIG_NET_ETH_MTU + CONFIG_NET_GUARDSIZE)
{
- nllwarn("WARNING: Too big. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
- considx, prodidx, pktlen, *rxstat);
+ nwarn("WARNING: Too big. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
+ considx, prodidx, pktlen, *rxstat);
NETDEV_RXERRORS(&priv->lp_dev);
}
else if ((*rxstat & RXSTAT_INFO_LASTFLAG) == 0)
{
- nllinfo("Fragment. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
- considx, prodidx, pktlen, *rxstat);
+ ninfo("Fragment. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
+ considx, prodidx, pktlen, *rxstat);
NETDEV_RXFRAGMENTS(&priv->lp_dev);
fragment = true;
}
else if (fragment)
{
- nllinfo("Last fragment. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
- considx, prodidx, pktlen, *rxstat);
+ ninfo("Last fragment. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n",
+ considx, prodidx, pktlen, *rxstat);
NETDEV_RXFRAGMENTS(&priv->lp_dev);
fragment = false;
}
@@ -906,7 +906,7 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllinfo("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
NETDEV_RXIPV4(&priv->lp_dev);
/* Handle ARP on input then give the IPv4 packet to the
@@ -948,7 +948,7 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllinfo("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
NETDEV_RXIPV6(&priv->lp_dev);
/* Give the IPv6 packet to the network layer */
@@ -1202,13 +1202,13 @@ static int lpc17_interrupt(int irq, void *context)
{
if ((status & ETH_INT_RXOVR) != 0)
{
- nllerr("ERROR: RX Overrun. status: %08x\n", status);
+ nerr("ERROR: RX Overrun. status: %08x\n", status);
NETDEV_RXERRORS(&priv->lp_dev);
}
if ((status & ETH_INT_TXUNR) != 0)
{
- nllerr("ERROR: TX Underrun. status: %08x\n", status);
+ nerr("ERROR: TX Underrun. status: %08x\n", status);
NETDEV_TXERRORS(&priv->lp_dev);
}
@@ -1229,7 +1229,7 @@ static int lpc17_interrupt(int irq, void *context)
if ((status & ETH_INT_RXERR) != 0)
{
- nllerr("ERROR: RX ERROR: status: %08x\n", status);
+ nerr("ERROR: RX ERROR: status: %08x\n", status);
NETDEV_RXERRORS(&priv->lp_dev);
}
@@ -1281,7 +1281,7 @@ static int lpc17_interrupt(int irq, void *context)
if ((status & ETH_INT_TXERR) != 0)
{
- nllerr("ERROR: TX ERROR: status: %08x\n", status);
+ nerr("ERROR: TX ERROR: status: %08x\n", status);
NETDEV_TXERRORS(&priv->lp_dev);
}
@@ -2145,8 +2145,8 @@ static int lpc17_addmac(struct net_driver_s *dev, const uint8_t *mac)
uint32_t crc;
unsigned int ndx;
- nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Hash function:
*
@@ -2221,8 +2221,8 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac)
uint32_t crc;
unsigned int ndx;
- nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Hash function:
*
@@ -2660,7 +2660,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
* 4-bit revision number).
*/
- if ((phyreg & 0xfff0) == LPC17_PHYID2)
+ if ((phyreg & 0xfff0) == (LPC17_PHYID2 & 0xfff0))
{
break;
}
diff --git a/arch/arm/src/lpc17xx/lpc17_gpio.h b/arch/arm/src/lpc17xx/lpc17_gpio.h
index 1129a26235d02e5ce638b5a5be5bcaa56bbdace0..6aab5b9f84c114afd50c6fef04b83aa69419e475 100644
--- a/arch/arm/src/lpc17xx/lpc17_gpio.h
+++ b/arch/arm/src/lpc17xx/lpc17_gpio.h
@@ -89,7 +89,7 @@ extern "C"
* lpc17_gpioint.c, and lpc17_gpiodbg.c
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
EXTERN uint64_t g_intedge0;
EXTERN uint64_t g_intedge2;
#endif
@@ -109,7 +109,7 @@ EXTERN const uint32_t g_intbase[GPIO_NPORTS];
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
void lpc17_gpioirqinitialize(void);
#else
# define lpc17_gpioirqinitialize()
@@ -153,7 +153,7 @@ bool lpc17_gpioread(lpc17_pinset_t pinset);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
void lpc17_gpioirqenable(int irq);
#else
# define lpc17_gpioirqenable(irq)
@@ -167,7 +167,7 @@ void lpc17_gpioirqenable(int irq);
*
************************************************************************************/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
void lpc17_gpioirqdisable(int irq);
#else
# define lpc17_gpioirqdisable(irq)
diff --git a/arch/arm/src/lpc17xx/lpc17_gpioint.c b/arch/arm/src/lpc17xx/lpc17_gpioint.c
index 46acb05e6fa41ed16932e1b230f216fa449f0d0c..0c1ca613625b2ae110ff0369724eae64253b7c0e 100644
--- a/arch/arm/src/lpc17xx/lpc17_gpioint.c
+++ b/arch/arm/src/lpc17xx/lpc17_gpioint.c
@@ -51,7 +51,7 @@
#include "chip.h"
#include "lpc17_gpio.h"
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
/****************************************************************************
* Pre-processor Definitions
@@ -543,4 +543,4 @@ void lpc17_gpioirqdisable(int irq)
}
}
-#endif /* CONFIG_GPIO_IRQ */
+#endif /* CONFIG_LPC17_GPIOIRQ */
diff --git a/arch/arm/src/lpc17xx/lpc17_irq.c b/arch/arm/src/lpc17xx/lpc17_irq.c
index 44d149c7342f6eb119a55d60e459e753da58972f..ac8fb8855cd54bb14c7e0e8ab7391dfc2990880b 100644
--- a/arch/arm/src/lpc17xx/lpc17_irq.c
+++ b/arch/arm/src/lpc17xx/lpc17_irq.c
@@ -412,7 +412,7 @@ void up_irqinitialize(void)
* GPIO pins.
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
lpc17_gpioirqinitialize();
#endif
@@ -456,7 +456,7 @@ void up_disable_irq(int irq)
putreg32(regval, regaddr);
}
}
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
else if (irq >= LPC17_VALID_FIRST0L)
{
/* Maybe it is a (derived) GPIO IRQ */
@@ -501,7 +501,7 @@ void up_enable_irq(int irq)
putreg32(regval, regaddr);
}
}
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
else if (irq >= LPC17_VALID_FIRST0L)
{
/* Maybe it is a (derived) GPIO IRQ */
diff --git a/arch/arm/src/lpc17xx/lpc17_mcpwm.c b/arch/arm/src/lpc17xx/lpc17_mcpwm.c
index be526964c4a2356a98938a7a4cb107029ef3a750..db0d1a9d67de95932697df6894bc0a8bc6e6ff23 100644
--- a/arch/arm/src/lpc17xx/lpc17_mcpwm.c
+++ b/arch/arm/src/lpc17xx/lpc17_mcpwm.c
@@ -47,7 +47,7 @@
#include
#include
-#include
+#include
#include
#include "up_internal.h"
diff --git a/arch/arm/src/lpc17xx/lpc17_pwm.c b/arch/arm/src/lpc17xx/lpc17_pwm.c
index dc073fc1a73dc36b943e0256eacf61bd42719888..c284934570c5b8bde8741025052ba207cca0d616 100644
--- a/arch/arm/src/lpc17xx/lpc17_pwm.c
+++ b/arch/arm/src/lpc17xx/lpc17_pwm.c
@@ -47,7 +47,7 @@
#include
#include
-#include
+#include
#include
#include "up_internal.h"
diff --git a/arch/arm/src/lpc17xx/lpc17_sdcard.c b/arch/arm/src/lpc17xx/lpc17_sdcard.c
index 15a15c55c60f684af2e92376532da74d3f42e93e..2ea6c17c45cc61c68cbd8751f759a36b88c6787a 100644
--- a/arch/arm/src/lpc17xx/lpc17_sdcard.c
+++ b/arch/arm/src/lpc17xx/lpc17_sdcard.c
@@ -810,7 +810,7 @@ static void lpc17_dmacallback(DMA_HANDLE handle, void *arg, int status)
if (status < 0)
{
- dmallerr("ERROR: DMA error %d, remaining: %d\n", status, priv->remaining);
+ dmaerr("ERROR: DMA error %d, remaining: %d\n", status, priv->remaining);
result = SDIOWAIT_ERROR;
}
else
@@ -1077,7 +1077,7 @@ static void lpc17_eventtimeout(int argc, uint32_t arg)
/* Yes.. wake up any waiting threads */
lpc17_endwait(priv, SDIOWAIT_TIMEOUT);
- mcllerr("ERROR: Timeout: remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Timeout: remaining: %d\n", priv->remaining);
}
}
@@ -1294,7 +1294,7 @@ static int lpc17_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- mcllerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
@@ -1304,7 +1304,7 @@ static int lpc17_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- mcllerr("ERROR: Data timeout, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Data timeout, remaining: %d\n", priv->remaining);
lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT);
}
@@ -1314,7 +1314,7 @@ static int lpc17_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- mcllerr("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining);
lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
@@ -1324,7 +1324,7 @@ static int lpc17_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- mcllerr("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining);
lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
@@ -1334,7 +1334,7 @@ static int lpc17_interrupt(int irq, void *context)
{
/* Terminate the transfer with an error */
- mcllerr("ERROR: Start bit, remaining: %d\n", priv->remaining);
+ mcerr("ERROR: Start bit, remaining: %d\n", priv->remaining);
lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
}
diff --git a/arch/arm/src/lpc17xx/lpc17_timer.c b/arch/arm/src/lpc17xx/lpc17_timer.c
index 9278578b6785d95f8f3f8ede2d760cc50f8165f6..434f416021ffaa6775ce31183ba8ba23eb94528f 100644
--- a/arch/arm/src/lpc17xx/lpc17_timer.c
+++ b/arch/arm/src/lpc17xx/lpc17_timer.c
@@ -47,7 +47,7 @@
#include
#include
-#include
+#include
#include
#include "up_internal.h"
diff --git a/arch/arm/src/lpc17xx/lpc17_usbdev.c b/arch/arm/src/lpc17xx/lpc17_usbdev.c
index 37cc9ab5eb468263c0fc81f57ba69ba680c54888..ca4d5f90d803456e10d95c415d41de0d3ed2eadd 100644
--- a/arch/arm/src/lpc17xx/lpc17_usbdev.c
+++ b/arch/arm/src/lpc17xx/lpc17_usbdev.c
@@ -534,7 +534,7 @@ static struct lpc17_dmadesc_s g_usbddesc[CONFIG_LPC17_USBDEV_NDMADESCRIPTORS];
#ifdef CONFIG_LPC17_USBDEV_REGDEBUG
static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite)
{
- ullinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
+ uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
}
#endif
@@ -584,7 +584,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite)
{
/* No.. More than one. */
- ullinfo("[repeats %d more times]\n", count);
+ uinfo("[repeats %d more times]\n", count);
}
}
@@ -1079,8 +1079,9 @@ static int lpc17_wrrequest(struct lpc17_ep_s *privep)
return OK;
}
- ullinfo("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
- privep->epphy, privreq, privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
+ uinfo("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
+ privep->epphy, privreq, privreq->req.len, privreq->req.xfrd,
+ privep->txnullpkt);
/* Ignore any attempt to send a zero length packet on anything but EP0IN */
@@ -1188,8 +1189,8 @@ static int lpc17_rdrequest(struct lpc17_ep_s *privep)
return OK;
}
- ullinfo("len=%d xfrd=%d nullpkt=%d\n",
- privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
+ uinfo("len=%d xfrd=%d nullpkt=%d\n",
+ privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
/* Ignore any attempt to receive a zero length packet */
@@ -1596,8 +1597,8 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv)
index = GETUINT16(ctrl.index);
len = GETUINT16(ctrl.len);
- ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- ctrl.type, ctrl.req, value, index, len);
+ uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ ctrl.type, ctrl.req, value, index, len);
/* Dispatch any non-standard requests */
@@ -1742,7 +1743,7 @@ static inline void lpc17_ep0setup(struct lpc17_usbdev_s *priv)
if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
value == USB_FEATURE_TESTMODE)
{
- ullinfo("test mode: %d\n", index);
+ uinfo("test mode: %d\n", index);
}
else if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@@ -2324,7 +2325,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context)
}
else
{
- ullinfo("Pending data on OUT endpoint\n");
+ uinfo("Pending data on OUT endpoint\n");
priv->rxpending = 1;
}
}
@@ -2803,7 +2804,8 @@ static int lpc17_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(LPC17_TRACEERR_INVALIDPARMS), 0);
- ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+ uinfo("req=%p callback=%p buf=%p ep=%p\n",
+ req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
diff --git a/arch/arm/src/lpc17xx/lpc17_usbhost.c b/arch/arm/src/lpc17xx/lpc17_usbhost.c
index 269f2de253b4746c53b7cda9aaaff0cfa03cf001..d8d02f629c0ff563d385233701f8adbadc422b8d 100644
--- a/arch/arm/src/lpc17xx/lpc17_usbhost.c
+++ b/arch/arm/src/lpc17xx/lpc17_usbhost.c
@@ -460,7 +460,7 @@ static struct lpc17_xfrinfo_s g_xfrbuffers[CONFIG_LPC17_USBHOST_NPREALLOC];
#ifdef CONFIG_LPC17_USBHOST_REGDEBUG
static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite)
{
- ullinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
+ uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
}
#endif
@@ -510,7 +510,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite)
{
/* No.. More than one. */
- ullinfo("[repeats %d more times]\n", count);
+ uinfo("[repeats %d more times]\n", count);
}
}
@@ -1646,7 +1646,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
intst = lpc17_getreg(LPC17_USBHOST_INTST);
regval = lpc17_getreg(LPC17_USBHOST_INTEN);
- ullinfo("INST: %08x INTEN: %08x\n", intst, regval);
+ uinfo("INST: %08x INTEN: %08x\n", intst, regval);
pending = intst & regval;
if (pending != 0)
@@ -1656,18 +1656,18 @@ static int lpc17_usbinterrupt(int irq, void *context)
if ((pending & OHCI_INT_RHSC) != 0)
{
uint32_t rhportst1 = lpc17_getreg(LPC17_USBHOST_RHPORTST1);
- ullinfo("Root Hub Status Change, RHPORTST1: %08x\n", rhportst1);
+ uinfo("Root Hub Status Change, RHPORTST1: %08x\n", rhportst1);
if ((rhportst1 & OHCI_RHPORTST_CSC) != 0)
{
uint32_t rhstatus = lpc17_getreg(LPC17_USBHOST_RHSTATUS);
- ullinfo("Connect Status Change, RHSTATUS: %08x\n", rhstatus);
+ uinfo("Connect Status Change, RHSTATUS: %08x\n", rhstatus);
/* If DRWE is set, Connect Status Change indicates a remote wake-up event */
if (rhstatus & OHCI_RHSTATUS_DRWE)
{
- ullinfo("DRWE: Remote wake-up\n");
+ uinfo("DRWE: Remote wake-up\n");
}
/* Otherwise... Not a remote wake-up event */
@@ -1684,7 +1684,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
{
/* Yes.. connected. */
- ullinfo("Connected\n");
+ uinfo("Connected\n");
priv->connected = true;
priv->change = true;
@@ -1698,7 +1698,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
}
else
{
- ullwarn("WARNING: Spurious status change (connected)\n");
+ uwarn("WARNING: Spurious status change (connected)\n");
}
/* The LSDA (Low speed device attached) bit is valid
@@ -1714,7 +1714,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
priv->rhport.hport.speed = USB_SPEED_FULL;
}
- ullinfo("Speed:%d\n", priv->rhport.hport.speed);
+ uinfo("Speed:%d\n", priv->rhport.hport.speed);
}
/* Check if we are now disconnected */
@@ -1723,7 +1723,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
{
/* Yes.. disconnect the device */
- ullinfo("Disconnected\n");
+ uinfo("Disconnected\n");
priv->connected = false;
priv->change = true;
@@ -1754,7 +1754,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
}
else
{
- ullwarn("WARNING: Spurious status change (disconnected)\n");
+ uwarn("WARNING: Spurious status change (disconnected)\n");
}
}
@@ -1834,9 +1834,9 @@ static int lpc17_usbinterrupt(int irq, void *context)
{
/* The transfer failed for some reason... dump some diagnostic info. */
- ullerr("ERROR: ED xfrtype:%d TD CTRL:%08x/CC:%d RHPORTST1:%08x\n",
- ed->xfrtype, td->hw.ctrl, xfrinfo->tdstatus,
- lpc17_getreg(LPC17_USBHOST_RHPORTST1));
+ uerr("ERROR: ED xfrtype:%d TD CTRL:%08x/CC:%d RHPORTST1:%08x\n",
+ ed->xfrtype, td->hw.ctrl, xfrinfo->tdstatus,
+ lpc17_getreg(LPC17_USBHOST_RHPORTST1));
}
#endif
@@ -1898,7 +1898,7 @@ static int lpc17_usbinterrupt(int irq, void *context)
#ifdef CONFIG_DEBUG_USB
if ((pending & LPC17_DEBUG_INTS) != 0)
{
- ullerr("ERROR: Unhandled interrupts INTST:%08x\n", intst);
+ uerr("ERROR: Unhandled interrupts INTST:%08x\n", intst);
}
#endif
@@ -3458,7 +3458,7 @@ static int lpc17_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
- ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+ uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */
diff --git a/arch/arm/src/lpc214x/chip.h b/arch/arm/src/lpc214x/chip.h
index c0af01c4475e4fe62e74a518da5bb37f1c0f1031..1e7c8b219bc4890ce1ebb4ff8bb89718c507e57d 100644
--- a/arch/arm/src/lpc214x/chip.h
+++ b/arch/arm/src/lpc214x/chip.h
@@ -33,8 +33,8 @@
*
****************************************************************************************************/
-#ifndef __LPC214X_CHIP_H
-#define __LPC214X_CHIP_H
+#ifndef __ARCH_ARM_SRC_LPC214X_CHIP_H
+#define __ARCH_ARM_SRC_LPC214X_CHIP_H
/****************************************************************************************************
* Included Files
@@ -346,4 +346,4 @@
* Public Function Prototypes
****************************************************************************************************/
-#endif /* __LPC214X_CHIP_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_CHIP_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_apb.h b/arch/arm/src/lpc214x/lpc214x_apb.h
index e76fa5754a635b8604bafe0fcc1459aa6361ee48..93f9ebdf7aed3e2383e44ecc377e411fbd151f07 100644
--- a/arch/arm/src/lpc214x/lpc214x_apb.h
+++ b/arch/arm/src/lpc214x/lpc214x_apb.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC214X_APB_H
-#define _ARCH_ARM_SRC_LPC214X_APB_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_APB_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_APB_H
/************************************************************************************
* Included Files
@@ -69,4 +69,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* _ARCH_ARM_SRC_LPC214X_APB_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_APB_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_decodeirq.c b/arch/arm/src/lpc214x/lpc214x_decodeirq.c
index 382c0bba022a949b9b37ce894b4073f13d821580..331fea560ebcdf2e9434806fc8a4c86d1f1c3bf6 100644
--- a/arch/arm/src/lpc214x/lpc214x_decodeirq.c
+++ b/arch/arm/src/lpc214x/lpc214x_decodeirq.c
@@ -111,8 +111,8 @@ static void lpc214x_decodeirq(uint32_t *regs)
#endif
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
- lowsyslog(LOG_ERR, "Unexpected IRQ\n");
CURRENT_REGS = regs;
+ err("ERROR: Unexpected IRQ\n");
PANIC();
#else
diff --git a/arch/arm/src/lpc214x/lpc214x_i2c.h b/arch/arm/src/lpc214x/lpc214x_i2c.h
index 35fcc00f7ea4e900473ee44c5533fb06f7df4b10..d12f1ff4eec5a0505d63c83228fbd941e0591050 100644
--- a/arch/arm/src/lpc214x/lpc214x_i2c.h
+++ b/arch/arm/src/lpc214x/lpc214x_i2c.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC214X_I2C_H
-#define _ARCH_ARM_SRC_LPC214X_I2C_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_I2C_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_I2C_H
/************************************************************************************
* Included Files
@@ -138,4 +138,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* _ARCH_ARM_SRC_LPC214X_I2C_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_I2C_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_pinsel.h b/arch/arm/src/lpc214x/lpc214x_pinsel.h
index 21c6c2f9db58fed41931f2087fd67d02605853d5..0cb2c58f9bf1ee67fe4c1f6128ee08739008b6aa 100644
--- a/arch/arm/src/lpc214x/lpc214x_pinsel.h
+++ b/arch/arm/src/lpc214x/lpc214x_pinsel.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC214X_PINSEL_H
-#define _ARCH_ARM_SRC_LPC214X_PINSEL_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_PINSEL_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_PINSEL_H
/************************************************************************************
* Included Files
@@ -256,4 +256,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* _ARCH_ARM_SRC_LPC214X_PINSEL_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_PINSEL_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_pll.h b/arch/arm/src/lpc214x/lpc214x_pll.h
index 4e19bcdc11c05a89df0bbff9bc798181fa48a18d..f8f9a25ad8ee44d797c0b3853a0bc9ce5cbb05f0 100644
--- a/arch/arm/src/lpc214x/lpc214x_pll.h
+++ b/arch/arm/src/lpc214x/lpc214x_pll.h
@@ -33,8 +33,8 @@
*
****************************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC214X_PLL_H
-#define _ARCH_ARM_SRC_LPC214X_PLL_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_PLL_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_PLL_H
/****************************************************************************************************
* Included Files
@@ -102,4 +102,4 @@
* Public Function Prototypes
****************************************************************************************************/
-#endif /* _ARCH_ARM_SRC_LPC214X_PLL_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_PLL_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_power.h b/arch/arm/src/lpc214x/lpc214x_power.h
index 699af8d59053d3551edfc0467fc732343238f61b..09d89c92ceaa215e2e09b1b6c00aeca15ec39868 100644
--- a/arch/arm/src/lpc214x/lpc214x_power.h
+++ b/arch/arm/src/lpc214x/lpc214x_power.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC214X_POWER_H
-#define _ARCH_ARM_SRC_LPC214X_POWER_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_POWER_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_POWER_H
/************************************************************************************
* Included Files
@@ -87,4 +87,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* _ARCH_ARM_SRC_LPC214X_POWER_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_POWER_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_spi.h b/arch/arm/src/lpc214x/lpc214x_spi.h
index 97e2fc7a58fce645de655604c7fef40cf0aede53..69c94d89c0fc782290a96290d4c434e7fe0bbbb2 100644
--- a/arch/arm/src/lpc214x/lpc214x_spi.h
+++ b/arch/arm/src/lpc214x/lpc214x_spi.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC214X_SPI_H
-#define _ARCH_ARM_SRC_LPC214X_SPI_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_SPI_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_SPI_H
/************************************************************************************
* Included Files
@@ -181,4 +181,4 @@ struct spi_dev_s; /* Forward reference */
FAR struct spi_dev_s *lpc214x_spibus_initialize(int port);
-#endif /* _ARCH_ARM_SRC_LPC214X_SPI_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_SPI_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_timer.h b/arch/arm/src/lpc214x/lpc214x_timer.h
index 224e608f3e96948a1e402a03ae03df9691411ceb..df0287d4495362da0b75b8b5fd9388b6a613a670 100644
--- a/arch/arm/src/lpc214x/lpc214x_timer.h
+++ b/arch/arm/src/lpc214x/lpc214x_timer.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __LPC214X_TIMER_H
-#define __LPC214X_TIMER_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_TIMER_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_TIMER_H
/************************************************************************************
* Included Files
@@ -149,4 +149,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* __LPC214X_TIMER_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_TIMER_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_uart.h b/arch/arm/src/lpc214x/lpc214x_uart.h
index c4c90c166926ef02998d8128b0d3865ab17d2b6d..3c85c3a065af885bf26e2b7108e56a4825a7fc97 100644
--- a/arch/arm/src/lpc214x/lpc214x_uart.h
+++ b/arch/arm/src/lpc214x/lpc214x_uart.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __LPC214X_UART_H
-#define __LPC214X_UART_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_UART_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_UART_H
/************************************************************************************
* Included Files
@@ -139,4 +139,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* __LPC214X_UART_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_UART_H */
diff --git a/arch/arm/src/lpc214x/lpc214x_usbdev.c b/arch/arm/src/lpc214x/lpc214x_usbdev.c
index 723987814826109fa5fb30ed6205fb12c2a2afaa..636c7391251bb145d0e7a9a68e0e6410fafa8279 100644
--- a/arch/arm/src/lpc214x/lpc214x_usbdev.c
+++ b/arch/arm/src/lpc214x/lpc214x_usbdev.c
@@ -539,7 +539,7 @@ static uint32_t lpc214x_getreg(uint32_t addr)
{
if (count == 4)
{
- ullinfo("...\n");
+ uinfo("...\n");
}
return val;
@@ -556,7 +556,7 @@ static uint32_t lpc214x_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- ullinfo("[repeats %d more times]\n", count-3);
+ uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -568,7 +568,7 @@ static uint32_t lpc214x_getreg(uint32_t addr)
/* Show the register value read */
- ullinfo("%08x->%08x\n", addr, val);
+ uinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@@ -586,7 +586,7 @@ static void lpc214x_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- ullinfo("%08x<-%08x\n", addr, val);
+ uinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@@ -1021,8 +1021,9 @@ static int lpc214x_wrrequest(struct lpc214x_ep_s *privep)
return OK;
}
- ullinfo("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
- privep->epphy, privreq, privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
+ uinfo("epphy=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
+ privep->epphy, privreq, privreq->req.len, privreq->req.xfrd,
+ privep->txnullpkt);
/* Ignore any attempt to send a zero length packet on anything but EP0IN */
@@ -1130,8 +1131,8 @@ static int lpc214x_rdrequest(struct lpc214x_ep_s *privep)
return OK;
}
- ullinfo("len=%d xfrd=%d nullpkt=%d\n",
- privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
+ uinfo("len=%d xfrd=%d nullpkt=%d\n",
+ privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
/* Ignore any attempt to receive a zero length packet */
@@ -1552,8 +1553,8 @@ static inline void lpc214x_ep0setup(struct lpc214x_usbdev_s *priv)
index = GETUINT16(ctrl.index);
len = GETUINT16(ctrl.len);
- ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- ctrl.type, ctrl.req, value, index, len);
+ uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ ctrl.type, ctrl.req, value, index, len);
/* Dispatch any non-standard requests */
@@ -1697,7 +1698,7 @@ static inline void lpc214x_ep0setup(struct lpc214x_usbdev_s *priv)
if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
value == USB_FEATURE_TESTMODE)
{
- ullinfo("test mode: %d\n", index);
+ uinfo("test mode: %d\n", index);
}
else if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@@ -2287,7 +2288,7 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context)
}
else
{
- ullinfo("Pending data on OUT endpoint\n");
+ uinfo("Pending data on OUT endpoint\n");
priv->rxpending = 1;
}
}
@@ -2763,7 +2764,8 @@ static int lpc214x_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(LPC214X_TRACEERR_INVALIDPARMS), 0);
- ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+ uinfo("req=%p callback=%p buf=%p ep=%p\n",
+ req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
diff --git a/arch/arm/src/lpc214x/lpc214x_vic.h b/arch/arm/src/lpc214x/lpc214x_vic.h
index 89a5f7b13f8200175d115bacd5e8fdd71d2528e9..4f3b821a8414c74e9b266e1a77974d74de3f88e5 100644
--- a/arch/arm/src/lpc214x/lpc214x_vic.h
+++ b/arch/arm/src/lpc214x/lpc214x_vic.h
@@ -33,8 +33,8 @@
*
************************************************************************************/
-#ifndef __LPC214X_VIC_H
-#define __LPC214X_VIC_H
+#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_VIC_H
+#define __ARCH_ARM_SRC_LPC214X_LPC214X_VIC_H
/************************************************************************************
* Included Files
@@ -67,4 +67,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* __LPC214X_VIC_H */
+#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_VIC_H */
diff --git a/arch/arm/src/lpc2378/chip.h b/arch/arm/src/lpc2378/chip.h
index b8b8b70c85a38bf51a1d98602ca31f0aad4806d7..1f213eaeabd749d4ae6975860f3047738fcb2ac3 100644
--- a/arch/arm/src/lpc2378/chip.h
+++ b/arch/arm/src/lpc2378/chip.h
@@ -38,8 +38,8 @@
*
****************************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC2378_CHIP_H
-#define _ARCH_ARM_SRC_LPC2378_CHIP_H
+#ifndef __ARCH_ARM_SRC_LPC2378_CHIP_H
+#define __ARCH_ARM_SRC_LPC2378_CHIP_H
/****************************************************************************************************
* Included Files
@@ -1003,4 +1003,4 @@ are for LPC24xx only. */
* Public Function Prototypes
****************************************************************************************************/
-#endif /* _ARCH_ARM_SRC_LPC2378_CHIP_H */
+#endif /* __ARCH_ARM_SRC_LPC2378_CHIP_H */
diff --git a/arch/arm/src/lpc2378/lpc2378.h b/arch/arm/src/lpc2378/lpc2378.h
index 0c7fccede9152d9922905f75ec11ac6ddc87c918..1e40b228d0d591d598f2bb6411ad156b5fc8ce47 100644
--- a/arch/arm/src/lpc2378/lpc2378.h
+++ b/arch/arm/src/lpc2378/lpc2378.h
@@ -38,8 +38,8 @@
*
****************************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC2378_INTERNAL_H
-#define _ARCH_ARM_SRC_LPC2378_INTERNAL_H
+#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_H
+#define __ARCH_ARM_SRC_LPC2378_LPC23XX_H
/****************************************************************************************************
* Included Files
@@ -67,4 +67,4 @@ void lpc2378_statledon(void);
#endif
-#endif /* _ARCH_ARM_SRC_LPC2378_INTERNAL_H */
+#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_H */
diff --git a/arch/arm/src/lpc2378/lpc23xx_decodeirq.c b/arch/arm/src/lpc2378/lpc23xx_decodeirq.c
index aca536e6651cbfdc90d61faea9ef5ff466d99a69..9c0e0b5b76454b495414eede55a329769e396493 100644
--- a/arch/arm/src/lpc2378/lpc23xx_decodeirq.c
+++ b/arch/arm/src/lpc2378/lpc23xx_decodeirq.c
@@ -110,9 +110,9 @@ static void lpc23xx_decodeirq(uint32_t *regs)
#endif
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
- lowsyslog(LOG_ERR, "Unexpected IRQ\n");
- CURRENT_REGS = regs;
PANIC();
+ err("ERROR: Unexpected IRQ\n");
+ CURRENT_REGS = regs;
#else
/* Check which IRQ fires */
diff --git a/arch/arm/src/lpc2378/lpc23xx_gpio.h b/arch/arm/src/lpc2378/lpc23xx_gpio.h
index fc920be4e96528bb6de16c59f8d0d61f8618b05a..b8be69660954a5844efc4b0ce785878db5b3080b 100644
--- a/arch/arm/src/lpc2378/lpc23xx_gpio.h
+++ b/arch/arm/src/lpc2378/lpc23xx_gpio.h
@@ -38,8 +38,8 @@
*
************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
-#define _ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
+#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
+#define __ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
/************************************************************************************
* Included Files
@@ -68,4 +68,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* _ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H */
+#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H */
diff --git a/arch/arm/src/lpc2378/lpc23xx_pinsel.h b/arch/arm/src/lpc2378/lpc23xx_pinsel.h
index 69ad1b749042405b9db94895a2ea233874740ad2..be34810fdc906f6f208a22f93c6365aed16b4138 100644
--- a/arch/arm/src/lpc2378/lpc23xx_pinsel.h
+++ b/arch/arm/src/lpc2378/lpc23xx_pinsel.h
@@ -38,8 +38,8 @@
*
************************************************************************************/
-#ifndef _ARCH_ARM_SRC_LPC23XX_PINSEL_H
-#define _ARCH_ARM_SRC_LPC23XX_PINSEL_H
+#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_PINSEL_H
+#define __ARCH_ARM_SRC_LPC2378_LPC23XX_PINSEL_H
/************************************************************************************
* Included Files
@@ -789,4 +789,4 @@
* Public Function Prototypes
************************************************************************************/
-#endif /* _ARCH_ARM_SRC_LPC23XX_PINSEL_H */
+#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_PINSEL_H */
diff --git a/arch/arm/src/lpc31xx/lpc31_decodeirq.c b/arch/arm/src/lpc31xx/lpc31_decodeirq.c
index 9cfcd3f44353ad25f65f716c4265b823d89e7134..a4f7a11628fa92fc452f77eec4e382c3148e2004 100644
--- a/arch/arm/src/lpc31xx/lpc31_decodeirq.c
+++ b/arch/arm/src/lpc31xx/lpc31_decodeirq.c
@@ -76,8 +76,8 @@
void up_decodeirq(uint32_t *regs)
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
- lowsyslog(LOG_ERR, "Unexpected IRQ\n");
CURRENT_REGS = regs;
+ err("ERROR: Unexpected IRQ\n");
PANIC();
#else
int index;
diff --git a/arch/arm/src/lpc31xx/lpc31_ehci.c b/arch/arm/src/lpc31xx/lpc31_ehci.c
index cc9ffb4c13a0d487daf0dae1c0df64de22956478..e37abe4997f5e3302a668493760845cda9ab2dda 100644
--- a/arch/arm/src/lpc31xx/lpc31_ehci.c
+++ b/arch/arm/src/lpc31xx/lpc31_ehci.c
@@ -826,7 +826,7 @@ static uint32_t lpc31_swap32(uint32_t value)
static void lpc31_printreg(volatile uint32_t *regaddr, uint32_t regval,
bool iswrite)
{
- ullinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
+ uinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
}
#endif
@@ -877,7 +877,7 @@ static void lpc31_checkreg(volatile uint32_t *regaddr, uint32_t regval, bool isw
{
/* No.. More than one. */
- ullinfo("[repeats %d more times]\n", count);
+ uinfo("[repeats %d more times]\n", count);
}
}
@@ -3370,7 +3370,7 @@ static int lpc31_ehci_interrupt(int irq, FAR void *context)
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace1(EHCI_VTRACE1_TOPHALF, usbsts & regval);
#else
- ullinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
+ uinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
#endif
/* Handle all unmasked interrupt sources */
@@ -4680,7 +4680,7 @@ static int lpc31_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
- ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+ uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */
diff --git a/arch/arm/src/lpc31xx/lpc31_spi.c b/arch/arm/src/lpc31xx/lpc31_spi.c
index 88d8ea6c00b70660ce62ea2cd88ee2a6a0eba068..ca2544bc2654d65966bf372cdb66992fdd0bd178 100644
--- a/arch/arm/src/lpc31xx/lpc31_spi.c
+++ b/arch/arm/src/lpc31xx/lpc31_spi.c
@@ -207,7 +207,7 @@ static bool spi_checkreg(bool wr, uint32_t value, uint32_t address)
{
if (g_ntimes > 0)
{
- spillinfo("...[Repeats %d times]...\n", g_ntimes);
+ spiinfo("...[Repeats %d times]...\n", g_ntimes);
}
g_wrlast = wr;
@@ -239,7 +239,7 @@ static void spi_putreg(uint32_t value, uint32_t address)
{
if (spi_checkreg(true, value, address))
{
- spillinfo("%08x<-%08x\n", address, value);
+ spiinfo("%08x<-%08x\n", address, value);
}
putreg32(value, address);
}
@@ -265,7 +265,7 @@ static uint32_t spi_getreg(uint32_t address)
uint32_t value = getreg32(address);
if (spi_checkreg(false, value, address))
{
- spillinfo("%08x->%08x\n", address, value);
+ spiinfo("%08x->%08x\n", address, value);
}
return value;
}
diff --git a/arch/arm/src/lpc31xx/lpc31_usbdev.c b/arch/arm/src/lpc31xx/lpc31_usbdev.c
index a596915536de46137113a850cfc904deac13b6ea..1cc9ec0d38b146be0ac6d260a63aa0b8257bdc8e 100644
--- a/arch/arm/src/lpc31xx/lpc31_usbdev.c
+++ b/arch/arm/src/lpc31xx/lpc31_usbdev.c
@@ -501,7 +501,7 @@ static uint32_t lpc31_getreg(uint32_t addr)
{
if (count == 4)
{
- ullinfo("...\n");
+ uinfo("...\n");
}
return val;
@@ -518,7 +518,7 @@ static uint32_t lpc31_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- ullinfo("[repeats %d more times]\n", count-3);
+ uinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -530,7 +530,7 @@ static uint32_t lpc31_getreg(uint32_t addr)
/* Show the register value read */
- ullinfo("%08x->%08x\n", addr, val);
+ uinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@@ -548,7 +548,7 @@ static void lpc31_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- ullinfo("%08x<-%08x\n", addr, val);
+ uinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@@ -1183,8 +1183,8 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv)
index = GETUINT16(ctrl.index);
len = GETUINT16(ctrl.len);
- ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- ctrl.type, ctrl.req, value, index, len);
+ uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ ctrl.type, ctrl.req, value, index, len);
/* Dispatch any non-standard requests */
if ((ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD)
@@ -1323,7 +1323,7 @@ static inline void lpc31_ep0setup(struct lpc31_usbdev_s *priv)
if (((ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
value == USB_FEATURE_TESTMODE)
{
- ullinfo("test mode: %d\n", index);
+ uinfo("test mode: %d\n", index);
}
else if ((ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@@ -2083,7 +2083,7 @@ static int lpc31_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(LPC31_TRACEERR_INVALIDPARMS), 0);
- ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+ uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
diff --git a/arch/arm/src/lpc43xx/Kconfig b/arch/arm/src/lpc43xx/Kconfig
index e7f830ed2ba5157cebaab467868cfd77e34d7874..80da35c00cac5b0b8c5d05f036938d4bce0502a1 100644
--- a/arch/arm/src/lpc43xx/Kconfig
+++ b/arch/arm/src/lpc43xx/Kconfig
@@ -81,36 +81,43 @@ config ARCH_FAMILY_LPC4320
bool
default y if ARCH_CHIP_LPC4320FBD144 || ARCH_CHIP_LPC4320FET100
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_AHB_SRAM_BANK1
config ARCH_FAMILY_LPC4330
bool
default y if ARCH_CHIP_LPC4330FBD144 || ARCH_CHIP_LPC4330FET100 || ARCH_CHIP_LPC4330FET180 || ARCH_CHIP_LPC4330FET256 || ARCH_CHIP_LPC4337JET100
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_AHB_SRAM_BANK1
config ARCH_FAMILY_LPC4337
bool
default y if ARCH_CHIP_LPC4337JBD144
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_AHB_SRAM_BANK1
config ARCH_FAMILY_LPC4350
bool
default y if ARCH_CHIP_LPC4350FBD208 || ARCH_CHIP_LPC4350FET180 || ARCH_CHIP_LPC4350FET256
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_AHB_SRAM_BANK1
config ARCH_FAMILY_LPC4353
bool
default y if ARCH_CHIP_LPC4353FBD208 || ARCH_CHIP_LPC4353FET180 || ARCH_CHIP_LPC4353FET256
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_AHB_SRAM_BANK1
config ARCH_FAMILY_LPC4357
bool
default y if ARCH_CHIP_LPC4357FET180 || ARCH_CHIP_LPC4357FBD208 || ARCH_CHIP_LPC4357FET256
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_AHB_SRAM_BANK1
config ARCH_FAMILY_LPC4370
bool
default y if ARCH_CHIP_LPC4370FET100
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_AHB_SRAM_BANK1
choice
prompt "LPC43XX Boot Configuration"
@@ -177,9 +184,15 @@ config LPC43_DAC
config LPC43_EMC
bool "External Memory Controller (EMC)"
default n
+ select ARCH_HAVE_EXTSDRAM0
+ select ARCH_HAVE_EXTSDRAM1
+ select ARCH_HAVE_EXTSDRAM2
+ select ARCH_HAVE_EXTSDRAM3
config LPC43_ETHERNET
bool "Ethernet"
+ select NETDEVICES
+ select ARCH_HAVE_PHY
default n
config LPC43_EVNTMNTR
@@ -320,6 +333,158 @@ config LPC43_GPIO_IRQ
---help---
Enable support for GPIO interrupts
+menu "Internal Memory Configuration"
+
+config ARCH_HAVE_AHB_SRAM_BANK1
+ bool
+
+if !LPC43_BOOT_SRAM
+
+config LPC43_USE_LOCSRAM_BANK1
+ bool "Use local SRAM bank 1 memory region"
+ default n
+ ---help---
+ Add local SRAM bank 1 memory region.
+
+endif # LPC43_BOOT_SRAM
+
+config LPC43_USE_AHBSRAM_BANK0
+ bool "Use AHB SRAM bank 0 memory region"
+ default n
+ ---help---
+ Add local AHB SRAM bank 0 memory region.
+
+config LPC43_USE_AHBSRAM_BANK1
+ bool "Use AHB SRAM bank 1 memory region"
+ default n
+ depends on ARCH_HAVE_AHB_SRAM_BANK1
+ ---help---
+ Add local AHB SRAM bank 1 memory region.
+
+config LPC43_HEAP_AHBSRAM_BANK2
+ bool "Use AHB SRAM bank 2 (ETB SRAM) memory region"
+ default n
+ ---help---
+ Add local AHB SRAM bank 2 (ETB SRAM) memory region.
+
+endmenu # LPC43xx Internal Memory Configuration
+
+menu "External Memory Configuration"
+
+config ARCH_HAVE_EXTSDRAM0
+ bool
+
+config ARCH_HAVE_EXTSDRAM1
+ bool
+
+config ARCH_HAVE_EXTSDRAM2
+ bool
+
+config ARCH_HAVE_EXTSDRAM3
+ bool
+
+config LPC43_EXTSDRAM0
+ bool "Configure external SDRAM0 (on DYNCS0)"
+ default n
+ depends on ARCH_HAVE_EXTSDRAM0
+ select ARCH_HAVE_EXTSDRAM
+ ---help---
+ Configure external SDRAM memory and, if applicable, map then external
+ SDRAM into the memory map.
+
+if LPC43_EXTSDRAM0
+
+config LPC43_EXTSDRAM0_SIZE
+ int "External SDRAM0 size"
+ default 0
+ ---help---
+ Size of the external SDRAM on DYNCS0 in bytes.
+
+config LPC43_EXTSDRAM0_HEAP
+ bool "Add external SDRAM on DYNCS0 to the heap"
+ default y
+ ---help---
+ Add the external SDRAM on DYNCS0 into the heap.
+
+endif # LCP43_EXTSDRAM0
+
+config LPC43_EXTSDRAM1
+ bool "Configure external SDRAM1 (on DYNCS1)"
+ default n
+ depends on ARCH_HAVE_EXTSDRAM1
+ select ARCH_HAVE_EXTSDRAM
+ ---help---
+ Configure external SDRAM memoryand, if applicable, map then external
+ SDRAM into the memory map.
+
+if LPC43_EXTSDRAM1
+
+config LPC43_EXTSDRAM1_SIZE
+ int "External SDRAM1 size"
+ default 0
+ ---help---
+ Size of the external SDRAM on DYNCS1 in bytes.
+
+config LPC43_EXTSDRAM1_HEAP
+ bool "Add external SDRAM on DYNCS1 to the heap"
+ default y
+ ---help---
+ Add the external SDRAM on DYNCS1 into the heap.
+
+endif # LCP43_EXTSDRAM1
+
+config LPC43_EXTSDRAM2
+ bool "Configure external SDRAM2 (on DYNCS2)"
+ default n
+ depends on ARCH_HAVE_EXTSDRAM2
+ select ARCH_HAVE_EXTSDRAM
+ ---help---
+ Configure external SDRAM memoryand, if applicable, map then external
+ SDRAM into the memory map.
+
+if LPC43_EXTSDRAM2
+
+config LPC43_EXTSDRAM2_SIZE
+ int "External SDRAM2 size"
+ default 0
+ ---help---
+ Size of the external SDRAM on DYNCS2 in bytes.
+
+config LPC43_EXTSDRAM2_HEAP
+ bool "Add external SDRAM on DYNCS2 to the heap"
+ default y
+ ---help---
+ Add the external SDRAM on DYNCS2 into the heap.
+
+endif # LCP43_EXTSDRAM2
+
+config LPC43_EXTSDRAM3
+ bool "Configure external SDRAM3 (on DYNCS3)"
+ default n
+ depends on ARCH_HAVE_EXTSDRAM3
+ select ARCH_HAVE_EXTSDRAM
+ ---help---
+ Configure external SDRAM memoryand, if applicable, map then external
+ SDRAM into the memory map.
+
+if LPC43_EXTSDRAM3
+
+config LPC43_EXTSDRAM3_SIZE
+ int "External SDRAM3 size"
+ default 0
+ ---help---
+ Size of the external SDRAM in bytes.
+
+config LPC43_EXTSDRAM3_HEAP
+ bool "Add external SDRAM on DYNCS3 to the heap"
+ default y
+ ---help---
+ Add the external SDRAM on DYNCS3 into the heap.
+
+endif # LCP43_EXTSDRAM3
+
+endmenu # External Memory Configuration
+
if LPC43_ETHERNET
menu "Ethernet MAC configuration"
diff --git a/arch/arm/src/lpc43xx/Make.defs b/arch/arm/src/lpc43xx/Make.defs
index 6e5d7ef3a789e822e5243a1608208cb3bb9e5d74..79ddaa4a0226213a2aa473fb097f75b1742852a0 100644
--- a/arch/arm/src/lpc43xx/Make.defs
+++ b/arch/arm/src/lpc43xx/Make.defs
@@ -126,6 +126,10 @@ ifeq ($(CONFIG_LPC43_ETHERNET),y)
CHIP_CSRCS += lpc43_ethernet.c
endif
+ifeq ($(CONFIG_LPC43_EMC),y)
+CHIP_CSRCS += lpc43_emc.c
+endif
+
ifeq ($(CONFIG_LPC43_SPI),y)
CHIP_CSRCS += lpc43_spi.c
else
diff --git a/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h b/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h
index 1b8312c965f79e505f4d7313be9d4b3f84074e89..852bd2a862e63c7a39c8454ae7a50a988d249307 100644
--- a/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h
+++ b/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h
@@ -90,6 +90,8 @@
/* AHB SRAM */
#define LPC43_AHBSRAM_BANK0_BASE (LPC43_AHBSRAM_BASE)
+#define LPC43_AHBSRAM_BANK1_BASE (LPC43_AHBSRAM_BASE + 0x00008000)
+#define LPC43_AHBSRAM_BANK2_BASE (LPC43_AHBSRAM_BASE + 0x0000c000)
#define LPC43_EEPROM_BASE (LPC43_AHBSRAM_BASE + 0x00004000)
#define LPC43_AHBSRAM_BITBAND_BASE (LPC43_AHBSRAM_BASE + 0x02000000)
diff --git a/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h b/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h
index b29722479a33984a1788f0feddd6a04815aa59fa..41a5d939540821ecaeb11f894aede1747f2aa223 100644
--- a/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h
+++ b/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h
@@ -190,86 +190,86 @@
#define PINCONF_CTOUT15_2 (PINCONF_FUNC1|PINCONF_PINSD|PINCONF_PIN_0)
#define PINCONF_CTOUT15_3 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_11)
-#define PINCONF_EMC_A0 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_9)
-#define PINCONF_EMC_A1 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_10)
-#define PINCONF_EMC_A2 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_11)
-#define PINCONF_EMC_A3 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_12)
-#define PINCONF_EMC_A4 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_13)
-#define PINCONF_EMC_A5 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_0)
-#define PINCONF_EMC_A6 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_1)
-#define PINCONF_EMC_A7 (PINCONF_FUNC2|PINCONF_PINS1|PINCONF_PIN_2)
-#define PINCONF_EMC_A8 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_8)
-#define PINCONF_EMC_A9 (PINCONF_FUNC3|PINCONF_PINS2|PINCONF_PIN_7)
-#define PINCONF_EMC_A10 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_6)
-#define PINCONF_EMC_A11 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_2)
-#define PINCONF_EMC_A12 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_1)
-#define PINCONF_EMC_A13 (PINCONF_FUNC2|PINCONF_PINS2|PINCONF_PIN_0)
-#define PINCONF_EMC_A14 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_8)
-#define PINCONF_EMC_A15 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_7)
-#define PINCONF_EMC_A16 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_16)
-#define PINCONF_EMC_A17 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_15)
-#define PINCONF_EMC_A18 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_0)
-#define PINCONF_EMC_A19 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_1)
-#define PINCONF_EMC_A20 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_2)
-#define PINCONF_EMC_A21 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_3)
-#define PINCONF_EMC_A22 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_4)
-#define PINCONF_EMC_A23 (PINCONF_FUNC3|PINCONF_PINSA|PINCONF_PIN_4)
-#define PINCONF_EMC_BLS0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_4)
-#define PINCONF_EMC_BLS1 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_6)
-#define PINCONF_EMC_BLS2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_13)
-#define PINCONF_EMC_BLS3 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_10)
-#define PINCONF_EMC_CAS (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_4)
-#define PINCONF_EMC_CKEOUT0 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_11)
-#define PINCONF_EMC_CKEOUT1 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_2)
-#define PINCONF_EMC_CKEOUT2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_1)
-#define PINCONF_EMC_CKEOUT3 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_15)
-#define PINCONF_EMC_CS0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_5)
-#define PINCONF_EMC_CS1 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_3)
-#define PINCONF_EMC_CS2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_12)
-#define PINCONF_EMC_CS3 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_11)
-#define PINCONF_EMC_D0 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_7)
-#define PINCONF_EMC_D1 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_8)
-#define PINCONF_EMC_D2 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_9)
-#define PINCONF_EMC_D3 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_10)
-#define PINCONF_EMC_D4 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_11)
-#define PINCONF_EMC_D5 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_12)
-#define PINCONF_EMC_D6 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_13)
-#define PINCONF_EMC_D7 (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_14)
-#define PINCONF_EMC_D8 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_4)
-#define PINCONF_EMC_D9 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_5)
-#define PINCONF_EMC_D10 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_6)
-#define PINCONF_EMC_D11 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_7)
-#define PINCONF_EMC_D12 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_0)
-#define PINCONF_EMC_D13 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_1)
-#define PINCONF_EMC_D14 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_2)
-#define PINCONF_EMC_D15 (PINCONF_FUNC2|PINCONF_PINS5|PINCONF_PIN_3)
-#define PINCONF_EMC_D16 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_2)
-#define PINCONF_EMC_D17 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_3)
-#define PINCONF_EMC_D18 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_4)
-#define PINCONF_EMC_D19 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_5)
-#define PINCONF_EMC_D20 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_6)
-#define PINCONF_EMC_D21 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_7)
-#define PINCONF_EMC_D22 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_8)
-#define PINCONF_EMC_D23 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_9)
-#define PINCONF_EMC_D24 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_5)
-#define PINCONF_EMC_D25 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_6)
-#define PINCONF_EMC_D26 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_7)
-#define PINCONF_EMC_D27 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_8)
-#define PINCONF_EMC_D28 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_9)
-#define PINCONF_EMC_D29 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_10)
-#define PINCONF_EMC_D30 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_11)
-#define PINCONF_EMC_D31 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_12)
-#define PINCONF_EMC_DQMOUT0 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_12)
-#define PINCONF_EMC_DQMOUT1 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_10)
-#define PINCONF_EMC_DQMOUT2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_0)
-#define PINCONF_EMC_DQMOUT3 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_13)
-#define PINCONF_EMC_DYCS0 (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_9)
-#define PINCONF_EMC_DYCS1 (PINCONF_FUNC1|PINCONF_PINS6|PINCONF_PIN_1)
-#define PINCONF_EMC_DYCS2 (PINCONF_FUNC2|PINCONF_PINSD|PINCONF_PIN_14)
-#define PINCONF_EMC_DYCS3 (PINCONF_FUNC3|PINCONF_PINSE|PINCONF_PIN_14)
-#define PINCONF_EMC_OE (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_3)
-#define PINCONF_EMC_RAS (PINCONF_FUNC3|PINCONF_PINS6|PINCONF_PIN_5)
-#define PINCONF_EMC_WE (PINCONF_FUNC3|PINCONF_PINS1|PINCONF_PIN_6)
+#define PINCONF_EMC_A0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_9)
+#define PINCONF_EMC_A1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_10)
+#define PINCONF_EMC_A2 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_11)
+#define PINCONF_EMC_A3 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_12)
+#define PINCONF_EMC_A4 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_13)
+#define PINCONF_EMC_A5 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_0)
+#define PINCONF_EMC_A6 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_1)
+#define PINCONF_EMC_A7 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_2)
+#define PINCONF_EMC_A8 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_8)
+#define PINCONF_EMC_A9 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_7)
+#define PINCONF_EMC_A10 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_6)
+#define PINCONF_EMC_A11 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_2)
+#define PINCONF_EMC_A12 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_1)
+#define PINCONF_EMC_A13 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS2|PINCONF_PIN_0)
+#define PINCONF_EMC_A14 (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_8)
+#define PINCONF_EMC_A15 (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_7)
+#define PINCONF_EMC_A16 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_16)
+#define PINCONF_EMC_A17 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_15)
+#define PINCONF_EMC_A18 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_0)
+#define PINCONF_EMC_A19 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_1)
+#define PINCONF_EMC_A20 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_2)
+#define PINCONF_EMC_A21 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_3)
+#define PINCONF_EMC_A22 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_4)
+#define PINCONF_EMC_A23 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSA|PINCONF_PIN_4)
+#define PINCONF_EMC_BLS0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_4)
+#define PINCONF_EMC_BLS1 (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_6)
+#define PINCONF_EMC_BLS2 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_13)
+#define PINCONF_EMC_BLS3 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_10)
+#define PINCONF_EMC_CAS (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_4)
+#define PINCONF_EMC_CKEOUT0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_11)
+#define PINCONF_EMC_CKEOUT1 (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_2)
+#define PINCONF_EMC_CKEOUT2 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_1)
+#define PINCONF_EMC_CKEOUT3 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_15)
+#define PINCONF_EMC_CS0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_5)
+#define PINCONF_EMC_CS1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_3)
+#define PINCONF_EMC_CS2 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_12)
+#define PINCONF_EMC_CS3 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_11)
+#define PINCONF_EMC_D0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_7)
+#define PINCONF_EMC_D1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_8)
+#define PINCONF_EMC_D2 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_9)
+#define PINCONF_EMC_D3 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_10)
+#define PINCONF_EMC_D4 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_11)
+#define PINCONF_EMC_D5 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_12)
+#define PINCONF_EMC_D6 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_13)
+#define PINCONF_EMC_D7 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_14)
+#define PINCONF_EMC_D8 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_4)
+#define PINCONF_EMC_D9 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_5)
+#define PINCONF_EMC_D10 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_6)
+#define PINCONF_EMC_D11 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_7)
+#define PINCONF_EMC_D12 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_0)
+#define PINCONF_EMC_D13 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_1)
+#define PINCONF_EMC_D14 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_2)
+#define PINCONF_EMC_D15 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS5|PINCONF_PIN_3)
+#define PINCONF_EMC_D16 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_2)
+#define PINCONF_EMC_D17 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_3)
+#define PINCONF_EMC_D18 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_4)
+#define PINCONF_EMC_D19 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_5)
+#define PINCONF_EMC_D20 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_6)
+#define PINCONF_EMC_D21 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_7)
+#define PINCONF_EMC_D22 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_8)
+#define PINCONF_EMC_D23 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_9)
+#define PINCONF_EMC_D24 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_5)
+#define PINCONF_EMC_D25 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_6)
+#define PINCONF_EMC_D26 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_7)
+#define PINCONF_EMC_D27 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_8)
+#define PINCONF_EMC_D28 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_9)
+#define PINCONF_EMC_D29 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_10)
+#define PINCONF_EMC_D30 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_11)
+#define PINCONF_EMC_D31 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_12)
+#define PINCONF_EMC_DQMOUT0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_12)
+#define PINCONF_EMC_DQMOUT1 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_10)
+#define PINCONF_EMC_DQMOUT2 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_0)
+#define PINCONF_EMC_DQMOUT3 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_13)
+#define PINCONF_EMC_DYCS0 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_9)
+#define PINCONF_EMC_DYCS1 (PINCONF_FUNC1|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_1)
+#define PINCONF_EMC_DYCS2 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSD|PINCONF_PIN_14)
+#define PINCONF_EMC_DYCS3 (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSE|PINCONF_PIN_14)
+#define PINCONF_EMC_OE (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_3)
+#define PINCONF_EMC_RAS (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS6|PINCONF_PIN_5)
+#define PINCONF_EMC_WE (PINCONF_FUNC3|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_6)
#define PINCONF_ENET_COL_1 (PINCONF_FUNC2|PINCONF_INBUFFER|PINCONF_SLEW_FAST|PINCONF_PINS0|PINCONF_PIN_1)
#define PINCONF_ENET_COL_2 (PINCONF_FUNC5|PINCONF_INBUFFER|PINCONF_SLEW_FAST|PINCONF_PINS9|PINCONF_PIN_6)
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_ccu.h b/arch/arm/src/lpc43xx/chip/lpc43_ccu.h
index a2cb20ca62f67d823682ab60232c816dea209923..51cdcdb9fc90230b1a37901b80f9bdc2b2e91a4b 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_ccu.h
+++ b/arch/arm/src/lpc43xx/chip/lpc43_ccu.h
@@ -1,7 +1,7 @@
/****************************************************************************************************
* arch/arm/src/lpc43xx/chip/lpc43_ccu.h
*
- * Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -45,6 +45,7 @@
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
+
/* Register Offsets *********************************************************************************/
#define LPC43_CCU1_PM_OFFSET 0x0000 /* CCU1 power mode register */
@@ -343,6 +344,23 @@
#define CCU_CLK_STAT_WAKEUP (1 << 2) /* Bit 2: Wake-up mechanism enable status */
/* Bits 3-31: Reserved */
+/* CCU1 Branch Clock EMCDIV Configuration Registers */
+
+#define CCU_CLK_EMCDIV_CFG_RUN (1 << 0) /* Bit 0: Run enable */
+#define CCU_CLK_EMCDIV_CFG_AUTO (1 << 1) /* Bit 1: Auto (AHB disable mechanism) enable */
+#define CCU_CLK_EMCDIV_CFG_WAKEUP (1 << 2) /* Bit 2: Wake-up mechanism enable */
+ /* Bits 3-4: Reserved */
+#define CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT (5) /* Bits 5-7: Clock divider */
+#define CCU_CLK_EMCDIV_CLOCK_DIV_MASK (7 << CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT)
+# define CCU_CLK_EMCDIV_CFG_DIV_FUNC(n) ((n) << CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT)
+# define CCU_CLK_EMCDIV_CFG_DIV_NODIV (0 << CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT) /* Bit 5-7: No division */
+# define CCU_CLK_EMCDIV_CFG_DIV_BY2 (1 << CCU_CLK_EMCDIV_CLOCK_DIV_SHIFT) /* Bit 5-7: Division by 2 */
+ /* Bits 8-26: Reserved */
+#define CCU_CLK_EMCDIV_CLOCK_DIVSTAT_SHIFT (27) /* Bits 27-29: Clock divider status */
+#define CCU_CLK_EMCDIV_CLOCK_DIVSTAT_MASK (7 << CCU_CLK_EMCDIV_CLOCK_DIVSTAT_SHIFT)
+# define CCU_CLK_EMCDIV_CFG_DIVSTAT_NODIV (0 << CCU_CLK_EMCDIV_CLOCK_DIVSTAT_SHIFT) /* Bit 27-29: No division */
+# define CCU_CLK_EMCDIV_CFG_DIVSTAT_BY2 (1 << CCU_CLK_EMCDIV_CLOCK_DIVSTAT_MASK) /* Bit 26-29: Divistion by 2 */
+
/****************************************************************************************************
* Public Types
****************************************************************************************************/
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_emc.h b/arch/arm/src/lpc43xx/chip/lpc43_emc.h
index 4fb3ae38be61f47a15f3a0fae38a11550dbb4bc9..b61cbcbc58523f27b75dc428cd83c4bb55eeb20f 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_emc.h
+++ b/arch/arm/src/lpc43xx/chip/lpc43_emc.h
@@ -1,7 +1,7 @@
/****************************************************************************************************
* arch/arm/src/lpc43xx/chip/lpc43_emc.h
*
- * Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -45,6 +45,7 @@
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
+
/* Register Offsets *********************************************************************************/
#define LPC43_EMC_CONTROL_OFFSET 0x0000 /* EMC Control register */
@@ -213,6 +214,7 @@
#define EMC_CONTROL_LOWPOWER (1 << 2) /* Bit 2: Low-power mode */
/* Bits 3-31: Reserved */
/* EMC Status register */
+
#define EMC__
#define EMC_STATUS_BUSY (1 << 0) /* Bit 0: Busy */
#define EMC_STATUS_WB (1 << 1) /* Bit 1: Write buffer status */
@@ -333,13 +335,64 @@
# define EMC_DYNCONFIG_MD_SDRAM (0 << EMC_DYNCONFIG_MD_SHIFT) /* SDRAM (POR reset value) */
/* Bits 5-6: Reserved */
#define EMC_DYNCONFIG_AM0_SHIFT (7) /* Bits 7-12: AM0 Address mapping (see user manual) */
-#define EMC_DYNCONFIG_AM0_MASK (0x3f << EMC_DYNCONFIG_AM0_SHIFT)
+#define EMC_DYNCONFIG_AM0_MASK (0x3F << EMC_DYNCONFIG_AM0_SHIFT)
/* Bit 13: Reserved */
#define EMC_DYNCONFIG_AM1 (1 << 14) /* Bit 14: AM1 Address mapping (see user manual) */
/* Bits 15-18: Reserved */
-#define EMC_DYNCONFIG_BENA (1 << 10) /* Bit 19: Buffer enable */
+#define EMC_DYNCONFIG_BENA (1 << 19) /* Bit 19: Buffer enable */
#define EMC_DYNCONFIG_WP (1 << 20) /* Bit 20: Write protect. */
/* Bits 21-31: Reserved */
+
+/* Dynamic Memory Configuration register Memory Configuration Values */
+/* TODO: complete configuration */
+
+/* Data Bus Width Value in LPC43_EMC_DYNCONFIG register (bit 14) */
+
+#define EMC_DYNCONFIG_DATA_BUS_16 (0 << 14) /* Data bus width 16 bit */
+#define EMC_DYNCONFIG_DATA_BUS_32 (1 << 14) /* Data bus width 32 bit */
+
+/* Low power SDRAM value in LPC43_EMC_DYNCONFIG register (bit 12) */
+
+#define EMC_DYNCONFIG_LPSDRAM (1 << 12) /* Low power SDRAM value (Bank, Row, Column)*/
+#define EMC_DYNCONFIG_HPSDRAM (0 << 12) /* High performance SDRAM value (Row, Bank, Column)*/
+
+/* Address mapping table for LPC43_EMC_DYNCONFIG register (bits 7-11) */
+
+/* Device size bits in LPC43_EMC_DYNCONFIG register (bits 9-11) */
+
+#define EMC_DYNCONFIG_DEV_SIZE_SHIFT (9)
+#define EMC_DYNCONFIG_DEV_SIZE_MASK (0x7)
+# define EMC_DYNCONFIG_DEV_SIZE_16Mb (0x00 << EMC_DYNCONFIG_DEV_SIZE_SHIFT)
+# define EMC_DYNCONFIG_DEV_SIZE_64Mb (0x01 << EMC_DYNCONFIG_DEV_SIZE_SHIFT)
+# define EMC_DYNCONFIG_DEV_SIZE_128Mb (0x02 << EMC_DYNCONFIG_DEV_SIZE_SHIFT)
+# define EMC_DYNCONFIG_DEV_SIZE_256Mb (0x03 << EMC_DYNCONFIG_DEV_SIZE_SHIFT)
+# define EMC_DYNCONFIG_DEV_SIZE_512Mb (0x04 << EMC_DYNCONFIG_DEV_SIZE_SHIFT)
+
+/* Bus width bits in LPC43_EMC_DYNCONFIG register (bits 7-8) */
+
+#define EMC_DYNCONFIG_DEV_BUS_SHIFT (7)
+#define EMC_DYNCONFIG_DEV_BUS_MASK (0x3)
+# define EMC_DYNCONFIG_DEV_BUS_8 (0x00 << EMC_DYNCONFIG_DEV_BUS_SHIFT)
+# define EMC_DYNCONFIG_DEV_BUS_16 (0x01 << EMC_DYNCONFIG_DEV_BUS_SHIFT)
+# define EMC_DYNCONFIG_DEV_BUS_32 (0x02 << EMC_DYNCONFIG_DEV_BUS_SHIFT)
+
+#define EMC_DYNCONFIG_2Mx8_2BANKS_11ROWS_9COLS ((0x0 << 9) | (0x0 << 7)) /* 16Mb (2Mx8), 2 banks, row length = 11, column length = 9 */
+#define EMC_DYNCONFIG_1Mx16_2BANKS_11ROWS_8COLS ((0x0 << 9) | (0x1 << 7)) /* 16Mb (1Mx16), 2 banks, row length = 11, column length = 8 */
+#define EMC_DYNCONFIG_8Mx8_4BANKS_12ROWS_9COLS ((0x1 << 9) | (0x0 << 7)) /* 64Mb (8Mx8), 4 banks, row length = 12, column length = 9 */
+#define EMC_DYNCONFIG_4Mx16_4BANKS_12ROWS_8COLS ((0x1 << 9) | (0x1 << 7)) /* 64Mb (4Mx16), 4 banks, row length = 12, column length = 8 */
+#define EMC_DYNCONFIG_2Mx32_4BANKS_11ROWS_8COLS ((0x1 << 9) | (0x2 << 7)) /* 64Mb (2Mx32), 4 banks, row length = 11, column length = 8, 32 bit bus only */
+#define EMC_DYNCONFIG_16Mx8_4BANKS_12ROWS_10COLS ((0x2 << 9) | (0x0 << 7)) /* 128Mb (16Mx8), 4 banks, row length = 12, column length = 10 */
+#define EMC_DYNCONFIG_8Mx16_4BANKS_12ROWS_9COLS ((0x2 << 9) | (0x1 << 7)) /* 128Mb (8Mx16), 4 banks, row length = 12, column length = 9 */
+#define EMC_DYNCONFIG_4Mx32_4BANKS_12ROWS_8COLS ((0x2 << 9) | (0x2 << 7)) /* 128Mb (4Mx32), 4 banks, row length = 12, column length = 8 */
+#define EMC_DYNCONFIG_32Mx8_4BANKS_13ROWS_10COLS ((0x3 << 9) | (0x0 << 7)) /* 256Mb (32Mx8), 4 banks, row length = 13, column length = 10, 32 bit bus only */
+#define EMC_DYNCONFIG_16Mx16_4BANKS_13ROWS_9COLS ((0x3 << 9) | (0x1 << 7)) /* 256Mb (16Mx16), 4 banks, row length = 13, column length = 9 */
+#define EMC_DYNCONFIG_8Mx32_4BANKS_13ROWS_8COLS ((0x3 << 9) | (0x2 << 7)) /* 256Mb (8Mx32), 4 banks, row length = 13, column length = 8, 32 bit bus only */
+#define EMC_DYNCONFIG_8Mx32_4BANKS_12ROWS_9COLS ((0x2 << 9) | (0x1 << 7)) /* 256Mb (8Mx32), 4 banks, row length = 12, column length = 9, 32 bit bus only */
+#define EMC_DYNCONFIG_64Mx8_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x0 << 7)) /* 512Mb (64Mx8), 4 banks, row length = 13, column length = 11 */
+#define EMC_DYNCONFIG_32Mx16_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x1 << 7)) /* 512Mb (32Mx16), 4 banks, row length = 13, column length = 10 */
+#define EMC_DYNCONFIG_16Mx32_4BANKS_13ROWS_9COLS ((0x3 << 9) | (0x1 << 7)) /* 512Mb (16Mx32), 4 banks, row length = 13, column length = 9, 32 bit bus only */
+#define EMC_DYNCONFIG_32Mx32_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x1 << 7)) /* 1Gb (32Mx32), 4 banks, row length = 13, column length = 10,32 bit bus only */
+
/* Dynamic Memory RAS & CAS Delay registers */
#define EMC_DYNRASCAS_RAS_SHIFT (0) /* Bits 0-1: RAS latency (active to read/write delay) */
@@ -354,6 +407,35 @@
# define EMC_DYNRASCAS_CAS_2CCLK (2 << EMC_DYNRASCAS_CAS_SHIFT) /* Two CCLK cycles */
# define EMC_DYNRASCAS_CAS_3CCLK (3 << EMC_DYNRASCAS_CAS_SHIFT) /* Three CCLK cycles (POR reset value) */
/* Bits 10-31: Reserved */
+
+/* Dynamic SDRAM mode register definitions */
+
+ /* Bits 0-2: Burst length. All other values are reserved. */
+#define EMC_DYNMODE_BURST_LENGTH_SHIFT (0)
+#define EMC_DYNMODE_BURST_LENGTH_MASK (0x7)
+# define EMC_DYNMODE_BURST_LENGTH_1 (0 << EMC_DYNMODE_BURST_LENGTH_SHIFT)
+# define EMC_DYNMODE_BURST_LENGTH_2 (1 << EMC_DYNMODE_BURST_LENGTH_SHIFT)
+# define EMC_DYNMODE_BURST_LENGTH_4 (2 << EMC_DYNMODE_BURST_LENGTH_SHIFT)
+# define EMC_DYNMODE_BURST_LENGTH_8 (3 << EMC_DYNMODE_BURST_LENGTH_SHIFT)
+ /* Bit 3: Burst mode type */
+#define EMC_DYNMODE_BURST_TYPE_SHIFT (3)
+# define EMC_DYNMODE_BURST_TYPE_SEQUENTIAL (0 << EMC_DYNMODE_BURST_TYPE_SHIFT) /* burst type sequential */
+# define EMC_DYNMODE_BURST_TYPE_INTERLEAVED (1 << EMC_DYNMODE_BURST_TYPE_INTERLEAVED) /* burst type interleaved */
+ /* Bits 4-6: Latency mode. All other values are reserved. */
+#define EMC_DYNMODE_CAS_SHIFT (4)
+#define EMC_DYNMODE_CAS_MASK (0x7)
+# define EMC_DYNMODE_CAS_2 (2 << EMC_DYNMODE_CAS_SHIFT) /* CAS latency of 2 cycles */
+# define EMC_DYNMODE_CAS_3 (3 << EMC_DYNMODE_CAS_SHIFT) /* CAS latency of 3 cycles */
+ /* Bits 7-8: Operating mode. All other values are reserved. */
+#define EMC_DYNMODE_OPMODE_SHIFT (7)
+#define EMC_DYNMODE_OPMODE_MASK (0x3)
+# define EMC_DYNMODE_OPMODE_STANDARD (0 << EMC_DYNMODE_OPMODE_SHIFT) /* dynamic standard operation mode */
+ /* Bit 9: Write burst mode */
+#define EMC_DYNMODE_WBMODE_SHIFT (9)
+# define EMC_DYNMODE_WBMODE_PROGRAMMED (0 << EMC_DYNMODE_WBMODE_SHIFT) /* write burst mode programmed */
+# define EMC_DYNMODE_WBMODE_SINGLE_LOC (1 << EMC_DYNMODE_WBMODE_SHIFT) /* write burst mode single loc */
+ /* Bits 10-11: Reserved */
+
/* Static Memory Configuration registers */
#define EMC_STATCONFIG_MW_SHIFT (0) /* Bits 0-1: Memory width */
diff --git a/arch/arm/src/lpc43xx/lpc43_adc.c b/arch/arm/src/lpc43xx/lpc43_adc.c
index 4286451f11eec9ad60f6691680509b807adcc8c1..2a9db4297d9c121deb015a6db25b21898d1ee3d7 100644
--- a/arch/arm/src/lpc43xx/lpc43_adc.c
+++ b/arch/arm/src/lpc43xx/lpc43_adc.c
@@ -59,7 +59,6 @@
#include
#include
-#include
#include
#include
#include
@@ -80,6 +79,12 @@
#include "lpc43_pinconfig.h"
+/* board.h should be included last because it depends on the previous
+ * inclusions and may need to modify other definitions.
+ */
+
+#include
+
#if defined(CONFIG_LPC43_ADC0) /* TODO ADC1 */
/****************************************************************************
diff --git a/arch/arm/src/lpc43xx/lpc43_allocateheap.c b/arch/arm/src/lpc43xx/lpc43_allocateheap.c
index 70a0bbe5873f4078c5df98f609165d68cb605ac6..b7a947b668ff7550ab8e4c279f6dc51d792006f5 100644
--- a/arch/arm/src/lpc43xx/lpc43_allocateheap.c
+++ b/arch/arm/src/lpc43xx/lpc43_allocateheap.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc43xx/lpc43_allocateheap.c
*
- * Copyright (C) 2012-2013, 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012-2013, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -61,6 +61,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* Get customizations for each supported chip.
*
* SRAM Resources
@@ -95,6 +96,25 @@
* NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span all AHB SRAM
* banks but are treated as two banks of 48 an 16Kb by the NuttX memory
* manager. This gives some symmetry to all of the members of the family.
+ *
+ * ----------------------------------------------------------------------
+ * EMC SDRAM
+ * ----------------------------------------------------------------------
+ * LPC43xx may have dynamic RAM connected on EMC bus. Up to 4 chips can be
+ * connected.
+ *
+ * DYCS0 (0x2800 0000) up to 128MB
+ * DYCS1 (0x3000 0000) up to 256MB
+ * DYCS2 (0x6000 0000) up to 256MB
+ * DYCS3 (0x7000 0000) up to 256MB
+ *
+ * LPC43xx may have static RAM connected on EMC bus.
+ *
+ * CS0 (0x1C00 0000) up to 16MB
+ * CS1 (0x1D00 0000) up to 16MB
+ * CS2 (0x1E00 0000) up to 16MB
+ * CS3 (0x1F00 0000) up to 16MB
+ *
*/
/* Configuration ************************************************************/
@@ -136,58 +156,89 @@
*
* CONFIG_RAM_START = The start of the data RAM region which may be
* either local SRAM bank 0 (Configuration A) or 1 (Configuration B).
- * CONFIG_RAM_START = The size of the data RAM region.
- * CONFIG_RAM_END = The sum of the above
+ * CONFIG_RAM_SIZE = The size of the data RAM region.
+ * CONFIG_RAM_END = The sum of the above.
+ */
+
+/* External Memory Configuration
+ *
+ * Dynamic memory configuration
+ * For dynamic memory configuration at least one of LPC43_EXTSDRAMx
+ * should by defined.
+ * Also, together with LPC43_EXTSDRAMx should be defined:
+ * LPC43_EXTSDRAMxSIZE = External RAM size in bytes.
+ * LPC43_EXTSDRAMxHEAP = Should this RAM be use as heap space?
*/
/* Check for Configuration A. */
+#undef MM_USE_LOCSRAM_BANK0
+#undef MM_USE_LOCSRAM_BANK1
+#undef MM_USE_AHBSRAM_BANK0
+#undef MM_USE_AHBSRAM_BANK1
+#undef MM_USE_AHBSRAM_BANK2
+#undef MM_USE_EXTSDRAM0
+#undef MM_USE_EXTSDRAM1
+#undef MM_USE_EXTSDRAM2
+#undef MM_USE_EXTSDRAM3
+#undef MM_HAVE_REGION
+
#ifndef CONFIG_LPC43_BOOT_SRAM
/* Configuration A */
-/* CONFIG_RAM_START should be set to the base of AHB SRAM, local 0. */
+/* CONFIG_RAM_START shoudl be set to the base of local SRAM, Bank 0. */
# if CONFIG_RAM_START != LPC43_LOCSRAM_BANK0_BASE
-# error "CONFIG_RAM_START must be set to the base address of RAM Bank 0"
+# error "CONFIG_RAM_START must be set to the base address of RAM bank 0"
# endif
-/* The configured RAM size should be equal to the size of local SRAM Bank 0 */
+/* The configured RAM size should be equal to the size of local SRAM Bank 0. */
# if CONFIG_RAM_SIZE != LPC43_LOCSRAM_BANK0_SIZE
-# error "CONFIG_RAM_SIZE must be set to size of AHB SRAM Bank 0"
+# error "CONFIG_RAM_SIZE must be set to size of local SRAM Bank 0"
# endif
-/* Now we can assign all of the memory regions for configuration A */
+/* Local SRAM Bank 0 will be used as main memory region */
+
+# define MM_USE_LOCSRAM_BANK0 0
+
+/* Use local SRAM Bank 1 if configured */
+
+# ifdef CONFIG_LPC43_USE_LOCSRAM_BANK1
+# define MM_USE_LOCSRAM_BANK1 1
+# endif
-# define MM_REGION1_BASE LPC43_LOCSRAM_BANK0_BASE
-# define MM_REGION1_SIZE LPC43_LOCSRAM_BANK0_SIZE
-# define MM_REGION2_BASE LPC43_LOCSRAM_BANK1_BASE
-# define MM_REGION2_SIZE LPC43_LOCSRAM_BANK1_SIZE
-# define MM_REGION3_BASE LPC43_AHBSRAM_BANK0_BASE
-# define MM_REGION3_SIZE LPC43_AHBSRAM_BANK0_SIZE
-#else
+#else /* CONFIG_LPC43_BOOT_SRAM */
/* Configuration B */
-/* CONFIG_RAM_START should be set to the base of local SRAM, bank 1. */
+/* CONFIG_RAM_START should be set to the base of local SRAM, Bank 1. */
# if CONFIG_RAM_START != LPC43_LOCSRAM_BANK1_BASE
-# error "CONFIG_RAM_START must be set to the base address of SRAM Bank 1"
+# error "CONFIG_RAM_START must be set to the base address of RAM bank 1"
# endif
-/* The configured RAM size should be equal to the size of local SRAM Bank 1 */
+/* The configured RAM size should be equal to the size of local SRAM Bank 1. */
# if CONFIG_RAM_SIZE != LPC43_LOCSRAM_BANK1_SIZE
-# error "CONFIG_RAM_SIZE must be set to size of AHB SRAM Bank 1"
+# error "CONFIG_RAM_SIZE must be set to size of local SRAM Bank 1"
# endif
-/* Now we can assign all of the memory regions for configuration B */
+/* Shouldn't use Local SRAM Bank 0 as system use it for code.
+ * Local SRAM Bank1 is used as main memory region.
+ */
+
+# define MM_USE_LOCSRAM_BANK1 0
+
+#endif /* CONFIG_LPC43_BOOT_SRAM */
+
+/* Configure other memory banks */
+
+#ifdef CONFIG_LPC43_AHBSRAM_BANK0
+# define MM_USE_AHBSRAM_BANK0 1
+#endif
-# define MM_REGION1_BASE LPC43_LOCSRAM_BANK1_BASE
-# define MM_REGION1_SIZE LPC43_LOCSRAM_BANK1_SIZE
-# define MM_REGION2_BASE LPC43_AHBSRAM_BANK0_BASE
-# define MM_REGION2_SIZE LPC43_AHBSRAM_BANK0_SIZE
-# undef MM_REGION3_BASE
-# undef MM_REGION3_SIZE
+#ifdef CONFIG_LPC43_AHBSRAM_BANK1
+# define MM_USE_AHBSRAM_BANK1 1
#endif
#define MM_DMAREGION_BASE LPC43_AHBSRAM_BANK2_BASE
@@ -199,8 +250,69 @@
#warning "Missing Logic"
-#define MM_DMAHEAP_BASE MM_DMAREGION_BASE /* For now... use it all */
-#define MM_DMAHEAP_SIZE MM_DMAREGION_SIZE
+#ifdef CONFIG_LPC43_AHBSRAM_BANK2
+# define MM_USE_AHBSRAM_BANK2 1
+# define MM_DMAHEAP_BASE MM_DMAREGION_BASE /* For now... use it all */
+# define MM_DMAHEAP_SIZE MM_DMAREGION_SIZE
+#endif
+
+/* External RAM configuration */
+
+/* Check if external SDRAM is supported and, if so, it is intended to be used
+ * used as heap.
+ */
+
+#if !defined(CONFIG_LPC43_EXTSDRAM0) || !defined(CONFIG_LPC43_EXTSDRAM0_HEAP)
+# undef CONFIG_LPC43_EXTSDRAM0_SIZE
+# define CONFIG_LPC43_EXTSDRAM0_SIZE 0
+#endif
+
+#if !defined(CONFIG_LPC43_EXTSDRAM1) || !defined(CONFIG_LPC43_EXTSDRAM1_HEAP)
+# undef CONFIG_LPC43_EXTSDRAM1_SIZE
+# define CONFIG_LPC43_EXTSDRAM1_SIZE 0
+#endif
+
+#if !defined(CONFIG_LPC43_EXTSDRAM2) || !defined(CONFIG_LPC43_EXTSDRAM2_HEAP)
+# undef CONFIG_LPC43_EXTSDRAM2_SIZE
+# define CONFIG_LPC43_EXTSDRAM2_SIZE 0
+#endif
+
+#if !defined(CONFIG_LPC43_EXTSDRAM3) || !defined(CONFIG_LPC43_EXTSDRAM3_HEAP)
+# undef CONFIG_LPC43_EXTSDRAM3_SIZE
+# define CONFIG_LPC43_EXTSDRAM3_SIZE 0
+#endif
+
+#if CONFIG_LPC43_EXTSDRAM0_SIZE > 0
+# define MM_USE_EXTSDRAM0 1
+# define MM_EXTSDRAM0_REGION LPC43_DYCS0_BASE
+# define MM_EXTSDRAM0_SIZE CONFIG_LPC43_EXTSDRAM0_SIZE
+#endif /* CONFIG_LPC43_EXTSDRAM0_SIZE */
+
+#if CONFIG_LPC43_EXTSDRAM1_SIZE > 0
+# define MM_USE_EXTSDRAM1 1
+# define MM_EXTSDRAM1_REGION LPC43_DYCS1_BASE
+# define MM_EXTSDRAM1_SIZE CONFIG_LPC43_EXTSDRAM1_SIZE
+#endif /* CONFIG_LPC43_EXTSDRAM1_SIZE */
+
+#if CONFIG_LPC43_EXTSDRAM2_SIZE > 0
+# define MM_USE_EXTSDRAM2 1
+# define MM_EXTSDRAM2_REGION LPC43_DYCS2_BASE
+# define MM_EXTSDRAM2_SIZE CONFIG_LPC43_EXTSDRAM2_SIZE
+#endif /* CONFIG_LPC43_EXTSDRAM1_SIZE */
+
+#if CONFIG_LPC43_EXTSDRAM3_SIZE > 0
+# define HAVE_EXTSDRAM3_REGION 1
+# define MM_EXTSDRAM3_REGION LPC43_DYCS3_BASE
+# define MM_EXTSDRAM3_SIZE CONFIG_LPC43_EXTSDRAM3_SIZE
+#endif /* CONFIG_LPC43_EXTSDRAM3_SIZE */
+
+#if CONFIG_MM_REGIONS > 1 && \
+ (defined(MM_USE_LOCSRAM_BANK1) || defined(MM_USE_AHBSRAM_BANK0) || \
+ defined(MM_USE_AHBSRAM_BANK1) || defined(MM_USE_AHBSRAM_BANK2) || \
+ defined(MM_USE_EXTSDRAM0) || defined(MM_USE_EXTSDRAM1) || \
+ defined(MM_USE_EXTSDRAM2) || defined(MM_USE_EXTSDRAM3))
+# define MM_HAVE_REGION 1
+#endif
/****************************************************************************
* Private Data
@@ -216,15 +328,31 @@
* thread is the thread that the system boots on and, eventually, becomes the
* idle, do nothing task that runs only when there is nothing else to run.
* The heap continues from there until the configured end of memory.
- * g_idle_topstack is the beginning of this heap region (not necessarily aligned).
+ * g_idle_topstack is the beginning of this heap region (not necessarily
+ * aligned).
*/
const uint32_t g_idle_topstack = (uint32_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE;
+#ifdef MM_HAVE_REGION
+static uint8_t g_mem_region_next = 0;
+#endif
+
/****************************************************************************
* Private Functions
****************************************************************************/
+#ifdef MM_HAVE_REGION
+static void mem_addregion(FAR void *region_start, size_t region_size)
+{
+ if (g_mem_region_next <= CONFIG_MM_REGIONS)
+ {
+ kmm_addregion(region_start, region_size);
+ g_mem_region_next++;
+ }
+}
+#endif
+
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -265,35 +393,42 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
#if CONFIG_MM_REGIONS > 1
void up_addregion(void)
{
-#if CONFIG_MM_REGIONS > 1
- /* Add the next SRAM region (which should exist) */
-
- kmm_addregion((FAR void *)MM_REGION2_BASE, MM_REGION2_SIZE);
+#ifdef MM_HAVE_REGION
+ /* start from second region */
-#ifdef MM_REGION3_BASE
- /* Add the third SRAM region (which will not exist in configuration B) */
+ g_mem_region_next = 2;
-#if CONFIG_MM_REGIONS > 2
- /* Add the third SRAM region (which may not exist) */
+# ifdef MM_USE_LOCSRAM_BANK1
+ mem_addregion((FAR void *)LPC43_LOCSRAM_BANK1_BASE, LPC43_LOCSRAM_BANK1_SIZE);
+# endif
- kmm_addregion((FAR void *)MM_REGION3_BASE, MM_REGION3_SIZE);
+# ifdef MM_USE_AHBSRAM_BANK0
+ mem_addregion((FAR void *)LPC43_AHBSRAM_BANK0_BASE, LPC43_AHBSRAM_BANK0_SIZE);
+# endif
-#if CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE)
- /* Add the DMA region (which may not be available) */
+# ifdef MM_USE_AHBSRAM_BANK1
+ mem_addregion((FAR void *)LPC43_AHBSRAM_BANK1_BASE, LPC43_AHBSRAM_BANK1_SIZE);
+# endif
- kmm_addregion((FAR void *)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE);
+# ifdef MM_USE_AHBSRAM_BANK2
+ mem_addregion((FAR void *)MM_DMAREGION_BASE, MM_DMAREGION_SIZE);
+# endif
-#endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */
-#endif /* CONFIG_MM_REGIONS > 2 */
-#else /* MM_REGION3_BASE */
+# ifdef MM_USE_EXTSDRAM0
+ mem_addregion((FAR void *)MM_EXTSDRAM0_REGION, MM_EXTSDRAM0_SIZE);
+# endif
-#if CONFIG_MM_REGIONS > 2 && defined(MM_DMAHEAP_BASE)
- /* Add the DMA region (which may not be available) */
+# ifdef MM_USE_EXTSDRAM1
+ mem_addregion((FAR void *)MM_EXTSDRAM1_REGION, MM_EXTSDRAM1_SIZE);
+# endif
- kmm_addregion((FAR void *)MM_DMAHEAP_BASE, MM_DMAHEAP_SIZE);
+# ifdef MM_USE_EXTSDRAM2
+ mem_addregion((FAR void *)MM_EXTSDRAM2_REGION, MM_EXTSDRAM2_SIZE);
+# endif
-#endif /* CONFIG_MM_REGIONS > 3 && defined(MM_DMAHEAP_BASE) */
-#endif /* MM_REGION3_BASE */
-#endif /* CONFIG_MM_REGIONS > 1 */
+# ifdef MM_USE_EXTSDRAM3
+ mem_addregion((FAR void *)MM_EXTSDRAM3_REGION, MM_EXTSDRAM3_SIZE);
+# endif
+#endif
}
#endif
diff --git a/arch/arm/src/lpc43xx/lpc43_ehci.c b/arch/arm/src/lpc43xx/lpc43_ehci.c
index b5ed4414d700b6dd0cceddd3512e6db4b85af322..ae462f80b46ac883fd62c21f1978a3eb2dba1d09 100644
--- a/arch/arm/src/lpc43xx/lpc43_ehci.c
+++ b/arch/arm/src/lpc43xx/lpc43_ehci.c
@@ -817,7 +817,7 @@ static uint32_t lpc43_swap32(uint32_t value)
static void lpc43_printreg(volatile uint32_t *regaddr, uint32_t regval,
bool iswrite)
{
- ullinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
+ uinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval);
}
#endif
@@ -868,7 +868,7 @@ static void lpc43_checkreg(volatile uint32_t *regaddr, uint32_t regval, bool isw
{
/* No.. More than one. */
- ullinfo("[repeats %d more times]\n", count);
+ uinfo("[repeats %d more times]\n", count);
}
}
@@ -3207,7 +3207,7 @@ static int lpc43_ehci_interrupt(int irq, FAR void *context)
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace1(EHCI_VTRACE1_TOPHALF, usbsts & regval);
#else
- ullinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
+ uinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
#endif
/* Handle all unmasked interrupt sources */
@@ -4511,7 +4511,7 @@ static int lpc43_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
- ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+ uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */
diff --git a/arch/arm/src/lpc43xx/lpc43_emc.c b/arch/arm/src/lpc43xx/lpc43_emc.c
new file mode 100644
index 0000000000000000000000000000000000000000..a15ecb5610daccc0bf0641fd37cb3c00f6a5a5b7
--- /dev/null
+++ b/arch/arm/src/lpc43xx/lpc43_emc.c
@@ -0,0 +1,141 @@
+/****************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_emc.c
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+
+/* TODO: add #if defined(CONFIG_LPC43_EMC) */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+
+#include
+#include
+#include
+
+#include "up_internal.h"
+
+#include "chip.h"
+#include "lpc43_pinconfig.h"
+#include "lpc43_emc.h"
+#include "chip/lpc43_creg.h"
+#include "chip/lpc43_cgu.h"
+#include "chip/lpc43_ccu.h"
+#include "lpc43_rgu.h"
+#include "lpc43_gpio.h"
+#include "up_arch.h"
+#include
+
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc43_emcinit
+ *
+ * Description:
+ * Initialize EMC controller. Start in full power
+ * mode.
+ *
+ ****************************************************************************/
+void lpc43_emcinit(uint32_t enable, uint32_t clock_ratio, uint32_t endian_mode)
+{
+ uint32_t regval;
+
+ /* Enable clock for EMC controller. */
+
+ regval = getreg32(LPC43_CCU1_M4_EMC_CFG);
+ regval |= CCU_CLK_CFG_RUN;
+ putreg32(regval, LPC43_CCU1_M4_EMC_CFG);
+
+ /* Configure endian mode and clock ratio. */
+
+ regval = 0;
+ if (endian_mode)
+ regval |= EMC_CONFIG_EM;
+ if (clock_ratio)
+ regval |= EMC_CONFIG_CR;
+
+ putreg32(regval, LPC43_EMC_CONFIG);
+
+ /* Enable EMC 001 normal memory map, no low power mode. */
+
+ putreg32(EMC_CONTROL_ENA, LPC43_EMC_CONTROL);
+}
+
+/****************************************************************************
+ * Name: lpc43_lowpowermode
+ *
+ * Description:
+ * Set EMC lowpower mode.
+ *
+ ****************************************************************************/
+void lpc43_lowpowermode(uint8_t enable)
+{
+ uint32_t regval;
+
+ regval = getreg32(LPC43_EMC_CONTROL);
+ if (enable)
+ {
+ regval |= EMC_CONTROL_LOWPOWER;
+ putreg32(regval, LPC43_EMC_CONTROL);
+ }
+ else
+ {
+ regval &= ~EMC_CONTROL_LOWPOWER;
+ putreg32(regval, LPC43_EMC_CONTROL);
+ }
+}
+
+/****************************************************************************
+ * Name: lpc43_emcenable
+ *
+ * Description:
+ * Enable or disable EMC controller.
+ *
+ ****************************************************************************/
+void lpc43_emcenable(uint8_t enable)
+{
+ uint32_t regval;
+
+ regval = getreg32(LPC43_EMC_CONTROL);
+ if (enable)
+ {
+ regval |= EMC_CONTROL_ENA;
+ putreg32(regval, LPC43_EMC_CONTROL);
+ }
+ else
+ {
+ regval &= ~EMC_CONTROL_ENA;
+ putreg32(regval, LPC43_EMC_CONTROL);
+ }
+}
diff --git a/arch/arm/src/lpc43xx/lpc43_emc.h b/arch/arm/src/lpc43xx/lpc43_emc.h
index 3c2bd2496feacbafc3be8299f70383c2c0ae6324..77b71d8612048818ff88d7a7fe83f190e8df4cd6 100644
--- a/arch/arm/src/lpc43xx/lpc43_emc.h
+++ b/arch/arm/src/lpc43xx/lpc43_emc.h
@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/lpc43xx/lpc43_emc.h
*
- * Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -48,16 +48,22 @@
* Pre-processor Definitions
************************************************************************************/
-/************************************************************************************
- * Public Types
- ************************************************************************************/
+/* Chip select Definitions **********************************************************/
-/************************************************************************************
- * Public Data
- ************************************************************************************/
+#define EMC_CS0 0
+#define EMC_CS1 1
+#define EMC_CS2 2
+#define EMC_CS3 3
+
+#define EMC_DYNCS0 0
+#define EMC_DYNCS1 1
+#define EMC_DYNCS2 2
+#define EMC_DYNCS3 3
/************************************************************************************
- * Public Functions
+ * Public Function Prototypes
************************************************************************************/
+void lpc43_emcinit(uint32_t enable, uint32_t clock_ratio, uint32_t endian_mode);
+
#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_EMC_H */
diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c
index 9c0022b3c4cc1c4c3f52ffa895e7e92826b1dab5..086dd0b8f3eb54f44359d0323b82e6506e2756a9 100644
--- a/arch/arm/src/lpc43xx/lpc43_ethernet.c
+++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c
@@ -704,7 +704,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
{
if (count == 4)
{
- nllinfo("...\n");
+ ninfo("...\n");
}
return val;
@@ -721,7 +721,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- nllinfo("[repeats %d more times]\n", count-3);
+ ninfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -733,7 +733,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
/* Show the register value read */
- nllinfo("%08x->%08x\n", addr, val);
+ ninfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@@ -760,7 +760,7 @@ static void lpc43_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- nllinfo("%08x<-%08x\n", addr, val);
+ ninfo("%08x<-%08x\n", addr, val);
/* Write the value */
@@ -947,8 +947,8 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
txdesc = priv->txhead;
txfirst = txdesc;
- nllinfo("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
- priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0);
+ ninfo("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n",
+ priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0);
DEBUGASSERT(txdesc && (txdesc->tdes0 & ETH_TDES0_OWN) == 0);
@@ -964,7 +964,7 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
bufcount = (priv->dev.d_len + (CONFIG_LPC43_ETH_BUFSIZE-1)) / CONFIG_LPC43_ETH_BUFSIZE;
lastsize = priv->dev.d_len - (bufcount - 1) * CONFIG_LPC43_ETH_BUFSIZE;
- nllinfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
+ ninfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
/* Set the first segment bit in the first TX descriptor */
@@ -1074,8 +1074,8 @@ static int lpc43_transmit(FAR struct lpc43_ethmac_s *priv)
priv->inflight++;
- nllinfo("txhead: %p txtail: %p inflight: %d\n",
- priv->txhead, priv->txtail, priv->inflight);
+ ninfo("txhead: %p txtail: %p inflight: %d\n",
+ priv->txhead, priv->txtail, priv->inflight);
/* If all TX descriptors are in-flight, then we have to disable receive interrupts
* too. This is because receive events can trigger more un-stoppable transmit
@@ -1373,7 +1373,7 @@ static void lpc43_freesegment(FAR struct lpc43_ethmac_s *priv,
struct eth_rxdesc_s *rxdesc;
int i;
- nllinfo("rxfirst: %p segments: %d\n", rxfirst, segments);
+ ninfo("rxfirst: %p segments: %d\n", rxfirst, segments);
/* Set OWN bit in RX descriptors. This gives the buffers back to DMA */
@@ -1431,8 +1431,8 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
uint8_t *buffer;
int i;
- nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
- priv->rxhead, priv->rxcurr, priv->segments);
+ ninfo("rxhead: %p rxcurr: %p segments: %d\n",
+ priv->rxhead, priv->rxcurr, priv->segments);
/* Check if there are free buffers. We cannot receive new frames in this
* design unless there is at least one free buffer.
@@ -1440,7 +1440,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
if (!lpc43_isfreebuffer(priv))
{
- nllerr("ERROR: No free buffers\n");
+ nerr("ERROR: No free buffers\n");
return -ENOMEM;
}
@@ -1497,7 +1497,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
rxcurr = priv->rxcurr;
}
- nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
+ ninfo("rxhead: %p rxcurr: %p segments: %d\n",
priv->rxhead, priv->rxcurr, priv->segments);
/* Check if any errors are reported in the frame */
@@ -1536,8 +1536,8 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
priv->rxhead = (struct eth_rxdesc_s *)rxdesc->rdes3;
lpc43_freesegment(priv, rxcurr, priv->segments);
- nllinfo("rxhead: %p d_buf: %p d_len: %d\n",
- priv->rxhead, dev->d_buf, dev->d_len);
+ ninfo("rxhead: %p d_buf: %p d_len: %d\n",
+ priv->rxhead, dev->d_buf, dev->d_len);
return OK;
}
@@ -1547,7 +1547,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
* scanning logic, and continue scanning with the next frame.
*/
- nllwarn("WARNING: Dropped, RX descriptor errors: %08x\n", rxdesc->rdes0);
+ nwarn("WARNING: Dropped, RX descriptor errors: %08x\n", rxdesc->rdes0);
lpc43_freesegment(priv, rxcurr, priv->segments);
}
}
@@ -1563,8 +1563,8 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv)
priv->rxhead = rxdesc;
- nllinfo("rxhead: %p rxcurr: %p segments: %d\n",
- priv->rxhead, priv->rxcurr, priv->segments);
+ ninfo("rxhead: %p rxcurr: %p segments: %d\n",
+ priv->rxhead, priv->rxcurr, priv->segments);
return -EAGAIN;
}
@@ -1608,7 +1608,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
if (dev->d_len > CONFIG_NET_ETH_MTU)
{
- nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
+ nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
/* Free dropped packet buffer */
if (dev->d_buf)
@@ -1632,7 +1632,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllinfo("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@@ -1672,7 +1672,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllinfo("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@@ -1709,7 +1709,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
- nllinfo("ARP frame\n");
+ ninfo("ARP frame\n");
/* Handle ARP packet */
@@ -1727,7 +1727,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv)
else
#endif
{
- nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
+ nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
}
/* We are finished with the RX buffer. NOTE: If the buffer is
@@ -1768,8 +1768,8 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv)
struct eth_txdesc_s *txdesc;
int i;
- nllinfo("txhead: %p txtail: %p inflight: %d\n",
- priv->txhead, priv->txtail, priv->inflight);
+ ninfo("txhead: %p txtail: %p inflight: %d\n",
+ priv->txhead, priv->txtail, priv->inflight);
/* Scan for "in-flight" descriptors owned by the CPU */
@@ -1784,8 +1784,8 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv)
* TX descriptors.
*/
- nllinfo("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
- txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3);
+ ninfo("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n",
+ txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3);
DEBUGASSERT(txdesc->tdes2 != 0);
@@ -1837,8 +1837,8 @@ static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv)
priv->txtail = txdesc;
- nllinfo("txhead: %p txtail: %p inflight: %d\n",
- priv->txhead, priv->txtail, priv->inflight);
+ ninfo("txhead: %p txtail: %p inflight: %d\n",
+ priv->txhead, priv->txtail, priv->inflight);
}
}
@@ -1975,7 +1975,7 @@ static inline void lpc43_interrupt_process(FAR struct lpc43_ethmac_s *priv)
{
/* Just let the user know what happened */
- nllerr("ERROR: Abnormal event(s): %08x\n", dmasr);
+ nerr("ERROR: Abnormal event(s): %08x\n", dmasr);
/* Clear all pending abnormal events */
@@ -2179,7 +2179,7 @@ static void lpc43_txtimeout_expiry(int argc, uint32_t arg, ...)
{
FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)arg;
- nllinfo("Timeout!\n");
+ ninfo("Timeout!\n");
#ifdef CONFIG_NET_NOINTS
/* Disable further Ethernet interrupts. This will prevent some race
@@ -2647,8 +2647,8 @@ static int lpc43_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
uint32_t temp;
uint32_t registeraddress;
- nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Add the MAC address to the hardware multicast hash table */
@@ -2704,8 +2704,8 @@ static int lpc43_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
uint32_t temp;
uint32_t registeraddress;
- nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Remove the MAC address to the hardware multicast hash table */
@@ -3392,6 +3392,9 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
priv->mbps100 = 1;
}
#endif
+#endif
+
+#else /* Auto-negotion not selected */
#ifdef CONFIG_LPC43_ETHFD
priv->mbps100 = 1;
@@ -3400,11 +3403,9 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv)
#ifdef CONFIG_LPC43_ETH100MBPS
priv->fduplex = 1;
#endif
-#endif
-
- /* However we got here, commit to the hardware */
phyval = 0;
+
if (priv->mbps100)
{
phyval |= MII_MCR_FULLDPLX;
@@ -3718,11 +3719,11 @@ static void lpc43_macaddress(FAR struct lpc43_ethmac_s *priv)
FAR struct net_driver_s *dev = &priv->dev;
uint32_t regval;
- nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- dev->d_ifname,
- dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
- dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
- dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+ ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ dev->d_ifname,
+ dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+ dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+ dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
/* Set the MAC address high register */
@@ -3925,12 +3926,12 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv)
/* Reset the Ethernet block */
- nllinfo("Reset the Ethernet block\n");
+ ninfo("Reset the Ethernet block\n");
lpc43_ethreset(priv);
/* Initialize the PHY */
- nllinfo("Initialize the PHY\n");
+ ninfo("Initialize the PHY\n");
ret = lpc43_phyinit(priv);
if (ret < 0)
{
@@ -3945,7 +3946,7 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv)
/* Initialize the MAC and DMA */
- nllinfo("Initialize the MAC and DMA\n");
+ ninfo("Initialize the MAC and DMA\n");
ret = lpc43_macconfig(priv);
if (ret < 0)
{
@@ -3966,7 +3967,7 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv)
/* Enable normal MAC operation */
- nllinfo("Enable normal operation\n");
+ ninfo("Enable normal operation\n");
return lpc43_macenable(priv);
}
diff --git a/arch/arm/src/lpc43xx/lpc43_idle.c b/arch/arm/src/lpc43xx/lpc43_idle.c
index 89c9d98e8332308141114353aa751843fb99ec26..5cc38b16f5facbdea98eef7a1e239bb284f4de52 100644
--- a/arch/arm/src/lpc43xx/lpc43_idle.c
+++ b/arch/arm/src/lpc43xx/lpc43_idle.c
@@ -98,7 +98,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
- _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
+ _info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c
index 345f63b5c24eb8f639da0c47e9dfe3ed04f1a5d4..09680bd9e9107f3d6e045c52079a42c51694ba6d 100644
--- a/arch/arm/src/lpc43xx/lpc43_irq.c
+++ b/arch/arm/src/lpc43xx/lpc43_irq.c
@@ -91,10 +91,6 @@ volatile uint32_t *g_current_regs[1];
extern uint32_t _vectors[];
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -242,53 +238,17 @@ static inline void lpc43_prioritize_syscall(int priority)
static int lpc43_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
+ int n;
+
DEBUGASSERT(irq >= LPC43_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= LPC43_IRQ_EXTINT)
{
- /* NOTE: We assume that there are at least 32 interrupts */
-
- if (irq < (LPC43_IRQ_EXTINT + 32))
- {
- /* Interrupt in range {0-31} */
-
- *regaddr = (NVIC_IRQ0_31_ENABLE + offset);
- *bit = 1 << (irq - LPC43_IRQ_EXTINT);
- }
-#if LPC43M4_IRQ_NEXTINT > 95
-# error Extension to interrupt logic needed
-#elif LPC43M4_IRQ_NEXTINT > 63
- else if (irq < (LPC43_IRQ_EXTINT + 64))
- {
- /* Interrupt in range {32-63} */
-
- *regaddr = (NVIC_IRQ32_63_ENABLE + offset);
- *bit = 1 << (irq - LPC43_IRQ_EXTINT - 32);
- }
- else if (irq < LPC43M4_IRQ_NIRQS)
- {
- /* Interrupt in range {64-LPC43M4_IRQ_NIRQS}, LPC43M4_IRQ_NIRQS <= 95 */
-
- *regaddr = (NVIC_IRQ64_95_ENABLE + offset);
- *bit = 1 << (irq - LPC43_IRQ_EXTINT - 64);
- }
-#else /* if LPC43M4_IRQ_NEXTINT > 31 */
- else if (irq < LPC43M4_IRQ_NIRQS)
- {
- /* Interrupt in range {32-LPC43M4_IRQ_NIRQS}, LPC43M4_IRQ_NIRQS <= 63 */
-
- *regaddr = (NVIC_IRQ32_63_ENABLE + offset);
- *bit = 1 << (irq - LPC43_IRQ_EXTINT - 32);
- }
-#endif
- else
- {
- /* Interrupt >= LPC43M4_IRQ_NIRQS */
-
- return ERROR; /* Invalid interrupt */
- }
+ n = irq - LPC43_IRQ_EXTINT;
+ *regaddr = NVIC_IRQ_ENABLE(n) + offset;
+ *bit = (uint32_t)1 << (n & 0x1f);
}
/* Handle processor exceptions. Only a few can be disabled */
@@ -342,16 +302,14 @@ void up_irqinitialize(void)
uint32_t regval;
#endif
int num_priority_registers;
+ int i;
/* Disable all interrupts */
- putreg32(0, NVIC_IRQ0_31_ENABLE);
-#if LPC43M4_IRQ_NEXTINT > 31
- putreg32(0, NVIC_IRQ32_63_ENABLE);
-#if LPC43M4_IRQ_NEXTINT > 63
- putreg32(0, NVIC_IRQ64_95_ENABLE);
-#endif
-#endif
+ for (i = 0; i < LPC43M4_IRQ_NEXTINT; i += 32)
+ {
+ putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
+ }
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
diff --git a/arch/arm/src/lpc43xx/lpc43_rit.c b/arch/arm/src/lpc43xx/lpc43_rit.c
index 044aeda1ffc6c4ac0b19e24376168f83737a6336..e42fc7db438a7c12f66cb1002028c8f043e7a9a8 100644
--- a/arch/arm/src/lpc43xx/lpc43_rit.c
+++ b/arch/arm/src/lpc43xx/lpc43_rit.c
@@ -201,8 +201,8 @@ void up_timer_initialize(void)
mask_bits++;
}
- tmrllinfo("mask_bits = %d, mask = %X, ticks_per_int = %d\r\n",
- mask_bits, (0xffffffff << (32 - mask_bits)), ticks_per_int);
+ tmrinfo("mask_bits = %d, mask = %X, ticks_per_int = %d\r\n",
+ mask_bits, (0xffffffff << (32 - mask_bits)), ticks_per_int);
/* Set the mask and compare value so we get interrupts every
* RIT_TIMER_RESOLUTION cycles.
diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c
index 0644622794c11642c468ae2b123cb286153c272b..82ec6d690efa5b8c34554e4b80b03ce8ced035b3 100644
--- a/arch/arm/src/lpc43xx/lpc43_serial.c
+++ b/arch/arm/src/lpc43xx/lpc43_serial.c
@@ -170,7 +170,7 @@ static struct up_dev_s g_uart0priv =
.bits = CONFIG_USART0_BITS,
.stopbits2 = CONFIG_USART0_2STOP,
#if defined(CONFIG_USART0_RS485MODE) && defined(CONFIG_USART0_RS485_DTRDIR)
- .dtrdir = true;
+ .dtrdir = true,
#endif
};
@@ -205,7 +205,7 @@ static struct up_dev_s g_uart1priv =
.bits = CONFIG_UART1_BITS,
.stopbits2 = CONFIG_UART1_2STOP,
#if defined(CONFIG_UART1_RS485MODE) && defined(CONFIG_UART1_RS485_DTRDIR)
- .dtrdir = true;
+ .dtrdir = true,
#endif
};
@@ -240,7 +240,7 @@ static struct up_dev_s g_uart2priv =
.bits = CONFIG_USART2_BITS,
.stopbits2 = CONFIG_USART2_2STOP,
#if defined(CONFIG_USART2_RS485MODE) && defined(CONFIG_USART2_RS485_DTRDIR)
- .dtrdir = true;
+ .dtrdir = true,
#endif
};
@@ -275,7 +275,7 @@ static struct up_dev_s g_uart3priv =
.bits = CONFIG_USART3_BITS,
.stopbits2 = CONFIG_USART3_2STOP,
#if defined(CONFIG_USART3_RS485MODE) && defined(CONFIG_USART3_RS485_DTRDIR)
- .dtrdir = true;
+ .dtrdir = true,
#endif
};
@@ -873,7 +873,7 @@ static int up_interrupt(int irq, void *context)
default:
{
- _llerr("ERROR: Unexpected IIR: %02x\n", status);
+ _err("ERROR: Unexpected IIR: %02x\n", status);
break;
}
}
diff --git a/arch/arm/src/lpc43xx/lpc43_spifi.c b/arch/arm/src/lpc43xx/lpc43_spifi.c
index 71920dc47750290990302ffd9dd6d9670f737df5..57349370c027b401854c2703903c8f09631a79c0 100644
--- a/arch/arm/src/lpc43xx/lpc43_spifi.c
+++ b/arch/arm/src/lpc43xx/lpc43_spifi.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/lpc43/lpc43_spifi.c
*
- * Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -779,12 +779,13 @@ static ssize_t lpc43_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t
lpc43_cachewrite(priv, buffer, startblock, nblocks);
lpc43_dumpbuffer(__func__, buffer, nblocks << SPIFI_512SHIFT)
- return nblocks;
+ return (ssize_t)nblocks;
#else
FAR struct lpc43_dev_s *priv = (FAR struct lpc43_dev_s *)dev;
FAR uint8_t *dest;
+ int ret;
finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
@@ -792,19 +793,17 @@ static ssize_t lpc43_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t
dest = SPIFI_BASE + (startblock << SPIFI_BLKSHIFT);
-#if defined(CONFIG_SPIFI_SECTOR512)
/* Write all of the erase blocks to FLASH */
- ret = lpc43_pagewrite(priv, dest, buffer, nblocks << SPIFI_512SHIFT);
+ ret = lpc43_pagewrite(priv, dest, buffer, nblocks << SPIFI_BLKSHIFT);
if (ret < 0)
{
ferr("ERROR: lpc43_pagewrite failed: %d\n", ret);
return ret;
}
-#endif
- lpc43_dumpbuffer(__func__, buffer, nblocks << SPIFI_BLKSHIFT)
- return nblocks;
+ lpc43_dumpbuffer(__func__, buffer, nblocks << SPIFI_BLKSHIFT);
+ return (ssize_t)nblocks;
#endif
}
diff --git a/arch/arm/src/lpc43xx/lpc43_usb0dev.c b/arch/arm/src/lpc43xx/lpc43_usb0dev.c
index 0b595abe43424fb6bad0ec3388aff62eda63cc79..c583dd30a1854a803bcbd1506dab1fa5121d5bb3 100644
--- a/arch/arm/src/lpc43xx/lpc43_usb0dev.c
+++ b/arch/arm/src/lpc43xx/lpc43_usb0dev.c
@@ -522,7 +522,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
{
if (count == 4)
{
- usbllinfo("...\n");
+ usbinfo("...\n");
}
return val;
@@ -539,7 +539,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
- usbllinfo("[repeats %d more times]\n", count-3);
+ usbinfo("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
@@ -551,7 +551,7 @@ static uint32_t lpc43_getreg(uint32_t addr)
/* Show the register value read */
- usbllinfo("%08x->%08x\n", addr, val);
+ usbinfo("%08x->%08x\n", addr, val);
return val;
}
#endif
@@ -569,7 +569,7 @@ static void lpc43_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
- usbllinfo("%08x<-%08x\n", addr, val);
+ usbinfo("%08x<-%08x\n", addr, val);
/* Write the value */
@@ -1228,8 +1228,8 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
priv->ep0buf_len = len;
- ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- ctrl->type, ctrl->req, value, index, len);
+ uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ ctrl->type, ctrl->req, value, index, len);
/* Starting a control request - update state */
@@ -1393,7 +1393,7 @@ static inline void lpc43_ep0setup(struct lpc43_usbdev_s *priv)
if (((ctrl->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) &&
value == USB_FEATURE_TESTMODE)
{
- ullinfo("test mode: %d\n", index);
+ uinfo("test mode: %d\n", index);
}
else if ((ctrl->type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@@ -2206,7 +2206,7 @@ static int lpc43_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(LPC43_TRACEERR_INVALIDPARMS), 0);
- ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+ uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
diff --git a/arch/arm/src/nuc1xx/nuc_idle.c b/arch/arm/src/nuc1xx/nuc_idle.c
index 7462aa24aa2aeb813b254fc225c0ca5ec890ebd3..791ce2f09188b40822f8a32d8da2b619d9476242 100644
--- a/arch/arm/src/nuc1xx/nuc_idle.c
+++ b/arch/arm/src/nuc1xx/nuc_idle.c
@@ -99,7 +99,7 @@ static void up_idlepm(void)
/* Perform board-specific, state-dependent logic here */
- _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
+ _info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig
index 8e764dff40ee0fef7a3d407386e21cb0c4f6febd..1f1f423e8578ba3c6bf4cad0093316093f8842fd 100644
--- a/arch/arm/src/sam34/Kconfig
+++ b/arch/arm/src/sam34/Kconfig
@@ -1060,7 +1060,6 @@ config SAM34_TC5_TIOB
config SAM34_ONESHOT
bool "TC one-shot wrapper"
- depends on SAM34_FREERUN
default n if !SCHED_TICKLESS
default y if SCHED_TICKLESS
---help---
diff --git a/arch/arm/src/sam34/Make.defs b/arch/arm/src/sam34/Make.defs
index 48c751799ceb2df9e75552386a21ff6c05917eb9..dab10fb45e1b45cc1b7f93178819c5b5287f11e8 100644
--- a/arch/arm/src/sam34/Make.defs
+++ b/arch/arm/src/sam34/Make.defs
@@ -199,7 +199,7 @@ ifeq ($(CONFIG_ARCH_CHIP_SAM4CM),y)
ifeq ($(CONFIG_SAM34_TC),y)
CHIP_CSRCS += sam4cm_tc.c
ifeq ($(CONFIG_SAM34_ONESHOT),y)
-CHIP_CSRCS += sam4cm_oneshot.c
+CHIP_CSRCS += sam4cm_oneshot.c sam4cm_oneshot_lowerhalf.c
endif
ifeq ($(CONFIG_SAM34_FREERUN),y)
CHIP_CSRCS += sam4cm_freerun.c
diff --git a/arch/arm/src/sam34/chip/sam3x_memorymap.h b/arch/arm/src/sam34/chip/sam3x_memorymap.h
index e32e6ec226e60cd99928514b628ca2b945a006e7..ba053d3c3538f4dbe291cf9f34da4100bfd752e5 100644
--- a/arch/arm/src/sam34/chip/sam3x_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam3x_memorymap.h
@@ -91,6 +91,7 @@
# define SAM_TC8_BASE 0x40088080 /* 0x40088080-0x400880bf: Timer Counter 5 */
/* 0x400880c0-0x4008ffff Reserved */
#define SAM_TWI_BASE 0x4008c000 /* 0x4008c000-0x4001ffff: Two-Wire Interface */
+# define SAM_TWIN_BASE(n) (SAM_TWI_BASE + ((n) << 14))
# define SAM_TWI0_BASE 0x4008c000 /* 0x4008c000-0x4008ffff: Two-Wire Interface 0 */
# define SAM_TWI1_BASE 0x40090000 /* 0x40090000-0x40093fff: Two-Wire Interface 1 */
#define SAM_PWM_BASE 0x40094000 /* 0x40020000-0x4003ffff: Pulse Width Modulation */
diff --git a/arch/arm/src/sam34/chip/sam4cm_memorymap.h b/arch/arm/src/sam34/chip/sam4cm_memorymap.h
index 155052388455e3cf26bd1eb135a91006e34323ca..c0b2de041b8bdcbe3cbf544c891de1b3b226b653 100644
--- a/arch/arm/src/sam34/chip/sam4cm_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam4cm_memorymap.h
@@ -77,8 +77,12 @@
#define SAM_TC3_BASE 0x40014000
#define SAM_TC4_BASE 0x40014040
#define SAM_TC5_BASE 0x40014080
+
+#define SAM_TWI_BASE 0x40018000
+#define SAM_TWIN_BASE(n) (SAM_TWI_BASE + ((n) << 14))
#define SAM_TWI0_BASE 0x40018000
#define SAM_TWI1_BASE 0x4001C000
+
#define SAM_USART0_BASE 0x40024000
#define SAM_USART1_BASE 0x40028000
#define SAM_USART2_BASE 0x4002C000
diff --git a/arch/arm/src/sam34/chip/sam4e_memorymap.h b/arch/arm/src/sam34/chip/sam4e_memorymap.h
index 95bfdef2eb719fadef4816b4282709db19742b4d..1cf95993996151bd66fb5d935ec47b5adfcc8a97 100644
--- a/arch/arm/src/sam34/chip/sam4e_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam4e_memorymap.h
@@ -108,6 +108,7 @@
# define SAM_USART0_BASE 0x400a0000 /* 0x400a0000-0x400a3fff: USART0 */
# define SAM_USART1_BASE 0x400a4000 /* 0x400a4000-0x400abfff: USART1 */
#define SAM_TWI_BASE 0x400a8000 /* 0x400a8000-0x400affff: Two-Wire Interface */
+# define SAM_TWIN_BASE(n) (SAM_TWI_BASE + ((n) << 14))
# define SAM_TWI0_BASE 0x400a8000 /* 0x400a8000-0x400abfff: Two-Wire Interface 0 */
# define SAM_TWI1_BASE 0x400ac000 /* 0x400ac000-0x400affff: Two-Wire Interface 1 */
#define SAM_AFEC_BASE 0x400b0000 /* 0x400b0000-0x400b7fff: Analog Front End */
diff --git a/arch/arm/src/sam34/chip/sam4l_memorymap.h b/arch/arm/src/sam34/chip/sam4l_memorymap.h
index 56810fe442cde2fdf5045573e44ba0e5389243c9..62a8c6a0c5c1635f4314d6a2d831c0abb35c8e0f 100644
--- a/arch/arm/src/sam34/chip/sam4l_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam4l_memorymap.h
@@ -82,6 +82,9 @@
/* 0x4000c000-0x4000ffff: Reserved */
#define SAM_TC0_BASE 0x40100000 /* 0x40100000-0x4013ffff: Timer Counter 0 */
#define SAM_TC1_BASE 0x40140000 /* 0x40180000-0x4017ffff: Timer Counter 1 */
+
+#define SAM_TWIMS_BASE 0x40180000 /* 0x40180000-0x401fffff: Two-wire Master/Slave */
+#define SAM_TWIN_BASE(n) (SAM_TWIMS_BASE + ((n) << 14))
#define SAM_TWIMS0_BASE 0x40180000 /* 0x40180000-0x401bffff: Two-wire Master/Slave Interface 0 */
#define SAM_TWIMS1_BASE 0x401c0000 /* 0x401c0000-0x401fffff: Two-wire Master/Slave Interface 1 */
/* 0x40020000-0x40023fff: Reserved */
diff --git a/arch/arm/src/sam34/chip/sam4s_memorymap.h b/arch/arm/src/sam34/chip/sam4s_memorymap.h
index 0ebf658866cc71050d88fd44a62a333f387767ac..45e8a97a3f65644733785ebeba32bd0f0b959f15 100644
--- a/arch/arm/src/sam34/chip/sam4s_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam4s_memorymap.h
@@ -84,6 +84,7 @@
# define SAM_TC5_BASE 0x40014080 /* 0x40014080-0x400140bf: Timer Counter 5 */
#define SAM_TWI_BASE 0x40018000 /* 0x40018000-0x4001ffff: Two-Wire Interface */
+# define SAM_TWIN_BASE(n) (SAM_TWI_BASE + ((n) << 14))
# define SAM_TWI0_BASE 0x40018000 /* 0x40018000-0x4001bfff: Two-Wire Interface 0 */
# define SAM_TWI1_BASE 0x4001c000 /* 0x4001c000-0x4001ffff: Two-Wire Interface 1 */
#define SAM_PWM_BASE 0x40020000 /* 0x40020000-0x4003ffff: Pulse Width Modulation */
diff --git a/arch/arm/src/sam34/chip/sam_dacc.h b/arch/arm/src/sam34/chip/sam_dacc.h
index 4581289edae6b27b4a6f78da6a3868b6718fbf4f..80a61d874a7a20d37ca6ec65aef0813165f8b0eb 100644
--- a/arch/arm/src/sam34/chip/sam_dacc.h
+++ b/arch/arm/src/sam34/chip/sam_dacc.h
@@ -209,7 +209,7 @@
#define DACC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
#define DACC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
#define DACC_WPMR_WPKEY_MASK (0x00ffffff << DACC_WPMR_WPKEY_SHIFT)
-# define DACC_WPMR_WPKEY_MASK (0x00444143 << DACC_WPMR_WPKEY_SHIFT)
+# define DACC_WPMR_WPKEY (0x00444143 << DACC_WPMR_WPKEY_SHIFT)
/* Write Protect Status register */
diff --git a/arch/arm/src/sam34/chip/sam_tc.h b/arch/arm/src/sam34/chip/sam_tc.h
index bb1bd15f0c132d277837a8dedd659e37fbcd6fa1..e5951fcdc9a5c440e63418952b3465a4776491e9 100644
--- a/arch/arm/src/sam34/chip/sam_tc.h
+++ b/arch/arm/src/sam34/chip/sam_tc.h
@@ -2,7 +2,7 @@
* arch/arm/src/sam34/chip/sam_tc.h
* Timer Counter (TC) definitions for the SAM3U, SAM4E, and SAM4S
*
- * Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009, 2013-2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -537,16 +537,10 @@
# define TC_BMR_TC1XC1S_TIOA2 (3 << TC_BMR_TC1XC1S_SHIFT)
#define TC_BMR_TC2XC2S_SHIFT (4) /* Bits 4-5: External Clock Signal 2 Selection */
#define TC_BMR_TC2XC2S_MASK (3 << TC_BMR_TC2XC2S_SHIFT)
-#if defined(CONFIG_ARCH_CHIP_SAM4s) || defined(CONFIG_ARCH_CHIP_SAM4E)
-# define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT)
-# define TC_BMR_TC2XC2S_TIOA1 (2 << TC_BMR_TC2XC2S_SHIFT)
-# define TC_BMR_TC2XC2S_TIOA2 (3 << TC_BMR_TC2XC2S_SHIFT)
-#else
# define TC_BMR_TC2XC2S_TCLK2 (0 << TC_BMR_TC2XC2S_SHIFT)
# define TC_BMR_TC2XC2S_NONE (1 << TC_BMR_TC2XC2S_SHIFT)
# define TC_BMR_TC2XC2S_TIOA0 (2 << TC_BMR_TC2XC2S_SHIFT)
# define TC_BMR_TC2XC2S_TIOA1 (3 << TC_BMR_TC2XC2S_SHIFT)
-#endif
#define TC_BMR_QDEN (1 << 8) /* Bit 8: Quadrature Decoder Enabled */
#define TC_BMR_POSEN (1 << 9) /* Bit 9: Position Enabled */
#define TC_BMR_SPEEDEN (1 << 10) /* Bit 10: Speed Enabled */
diff --git a/arch/arm/src/sam34/chip/sam_twi.h b/arch/arm/src/sam34/chip/sam_twi.h
index 8ad5a0f8aeb79aa5c0e84c090f08515f2d7d8c73..2f843dd07c338655e170de211fcc971e56b84957 100644
--- a/arch/arm/src/sam34/chip/sam_twi.h
+++ b/arch/arm/src/sam34/chip/sam_twi.h
@@ -143,6 +143,7 @@
#define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */
#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-22: Device Address */
#define TWI_MMR_DADR_MASK (0x7f << TWI_MMR_DADR_SHIFT)
+# define TWI_MMR_DADR(n) ((uint32_t)(n) << TWI_MMR_DADR_SHIFT)
/* TWI Slave Mode Register */
@@ -186,6 +187,9 @@
#define TWI_INT_RXBUFF (1 << 14) /* Bit 14: RX Buffer */
#define TWI_INT_TXBUFE (1 << 15) /* Bit 15: TX Buffer Empty */
+#define TWI_INT_ERRORS (0x00000340)
+#define TWI_INT_ALL (0x0000ffff)
+
/* TWI Receive Holding Register */
#define TWI_RHR_RXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Receive Holding Data */
diff --git a/arch/arm/src/sam34/sam4cm_freerun.c b/arch/arm/src/sam34/sam4cm_freerun.c
index a26578e99aca42d11badcada97df4531f05cf244..4b09e1d5e6678cd690abe7fe75aaf3212d782c5d 100644
--- a/arch/arm/src/sam34/sam4cm_freerun.c
+++ b/arch/arm/src/sam34/sam4cm_freerun.c
@@ -59,7 +59,7 @@
#include "sam4cm_freerun.h"
-#ifdef CONFIG_SAM34_ONESHOT
+#ifdef CONFIG_SAM34_FREERUN
/****************************************************************************
* Private Functions
@@ -316,4 +316,4 @@ int sam_freerun_uninitialize(struct sam_freerun_s *freerun)
return OK;
}
-#endif /* CONFIG_SAM34_ONESHOT */
+#endif /* CONFIG_SAM34_FREERUN */
diff --git a/arch/arm/src/sam34/sam4cm_oneshot.c b/arch/arm/src/sam34/sam4cm_oneshot.c
index 402166b2f7a99f76baeaecbbf718774e12a4244a..0bf92d1fea01d48d008b56978390592b1bb50a19 100644
--- a/arch/arm/src/sam34/sam4cm_oneshot.c
+++ b/arch/arm/src/sam34/sam4cm_oneshot.c
@@ -91,7 +91,7 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
oneshot_handler_t oneshot_handler;
void *oneshot_arg;
- tmrllinfo("Expired...\n");
+ tmrinfo("Expired...\n");
DEBUGASSERT(oneshot && oneshot->handler);
/* The clock was stopped, but not disabled when the RC match occurred.
@@ -111,7 +111,9 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
oneshot->handler = NULL;
oneshot_arg = (void *)oneshot->arg;
oneshot->arg = NULL;
+#ifdef CONFIG_SAM34_FREERUN
oneshot->start_count = 0;
+#endif
oneshot_handler(oneshot_arg);
}
@@ -212,7 +214,10 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
+#ifdef CONFIG_SAM34_FREERUN
oneshot->start_count = 0;
+#endif
+
return OK;
}
@@ -251,8 +256,10 @@ int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec)
*
****************************************************************************/
-int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- oneshot_handler_t handler, void *arg, const struct timespec *ts)
+int sam_oneshot_start(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun,
+ oneshot_handler_t handler, void *arg,
+ const struct timespec *ts)
{
uint64_t usec;
uint64_t regval;
@@ -309,6 +316,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
sam_tc_start(oneshot->tch);
+#ifdef CONFIG_SAM34_FREERUN
/* The function sam_tc_start() starts the timer/counter by setting the
* bits TC_CCR_CLKEN and TC_CCR_SWTRG in the channel control register.
* The first one enables the timer/counter the latter performs an
@@ -327,7 +335,11 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* vanishes at least if compiled with no optimisation.
*/
- oneshot->start_count = sam_tc_getcounter(freerun->tch);
+ if (freerun != NULL)
+ {
+ oneshot->start_count = sam_tc_getcounter(freerun->tch);
+ }
+#endif
/* Enable interrupts. We should get the callback when the interrupt
* occurs.
@@ -363,8 +375,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
*
****************************************************************************/
-int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- struct timespec *ts)
+int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun, struct timespec *ts)
{
irqstate_t flags;
uint64_t usec;
@@ -405,16 +417,19 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
count = sam_tc_getcounter(oneshot->tch);
rc = sam_tc_getregister(oneshot->tch, TC_REGC);
+#ifdef CONFIG_SAM34_FREERUN
/* In the case the timer/counter was canceled very short after its start,
* the counter register can hold the wrong value (the value of the last
* run). To prevent this the counter value is set to zero if not at
* least on tick passed since the start of the timer/counter.
*/
- if (count > 0 && sam_tc_getcounter(freerun->tch) == oneshot->start_count)
+ if (count > 0 && freerun != NULL &&
+ sam_tc_getcounter(freerun->tch) == oneshot->start_count)
{
count = 0;
}
+#endif
/* Now we can disable the interrupt and stop the timer. */
diff --git a/arch/arm/src/sam34/sam4cm_oneshot.h b/arch/arm/src/sam34/sam4cm_oneshot.h
index d7dc7a18ee040968f61a73d09fe908a1859fad8f..d46b67b4211d9de78de1f4411eaf815097d1b174 100644
--- a/arch/arm/src/sam34/sam4cm_oneshot.h
+++ b/arch/arm/src/sam34/sam4cm_oneshot.h
@@ -46,7 +46,6 @@
#include
#include "sam4cm_tc.h"
-#include "sam4cm_freerun.h"
#ifdef CONFIG_SAM34_ONESHOT
@@ -83,11 +82,13 @@ struct sam_oneshot_s
volatile oneshot_handler_t handler; /* Oneshot expiration callback */
volatile void *arg; /* The argument that will accompany
* the callback */
+#ifdef CONFIG_SAM34_FREERUN
volatile uint32_t start_count; /* Stores the value of the freerun counter,
* at each start of the onshot timer. Is neccesary
* to find out if the onshot counter was updated
* correctly at the time of the call to
* sam_oneshot_cancel or not. */
+#endif
};
/****************************************************************************
@@ -130,6 +131,14 @@ extern "C"
int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
uint16_t resolution);
+/****************************************************************************
+ * Name: sam_oneshot_max_delay
+ *
+ * Description:
+ * Determine the maximum delay of the one-shot timer (in microseconds)
+ *
+ ****************************************************************************/
+
int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
/****************************************************************************
@@ -144,7 +153,8 @@ int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
- * sam_freerun_initialize();
+ * sam_freerun_initialize(). May be NULL if there is no matching
+ * free-running timer.
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
@@ -155,8 +165,11 @@ int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
*
****************************************************************************/
-int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- oneshot_handler_t handler, void *arg, const struct timespec *ts);
+struct sam_freerun_s;
+int sam_oneshot_start(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun,
+ oneshot_handler_t handler, void *arg,
+ const struct timespec *ts);
/****************************************************************************
* Name: sam_oneshot_cancel
@@ -173,7 +186,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
- * sam_freerun_initialize();
+ * sam_freerun_initialize(). May be NULL if there is no matching
+ * free-running timer.
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
@@ -185,8 +199,9 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
*
****************************************************************************/
-int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- struct timespec *ts);
+struct sam_freerun_s;
+int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun, struct timespec *ts);
#undef EXTERN
#ifdef __cplusplus
diff --git a/arch/arm/src/sam34/sam4cm_oneshot_lowerhalf.c b/arch/arm/src/sam34/sam4cm_oneshot_lowerhalf.c
new file mode 100644
index 0000000000000000000000000000000000000000..cdab331d93ab2cce41169ca8eabf12076bbfdfe9
--- /dev/null
+++ b/arch/arm/src/sam34/sam4cm_oneshot_lowerhalf.c
@@ -0,0 +1,345 @@
+/****************************************************************************
+ * arch/arm/src/sam/sam_oneshot_lowerhalf.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "sam_oneshot.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure describes the state of the oneshot timer lower-half driver */
+
+struct sam_oneshot_lowerhalf_s
+{
+ /* This is the part of the lower half driver that is visible to the upper-
+ * half client of the driver. This must be the first thing in this
+ * structure so that pointers to struct oneshot_lowerhalf_s are cast
+ * compatible to struct sam_oneshot_lowerhalf_s and vice versa.
+ */
+
+ struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */
+
+ /* Private lower half data follows */
+
+ struct sam_oneshot_s oneshot; /* SAM-specific oneshot state */
+ oneshot_callback_t callback; /* internal handler that receives callback */
+ FAR void *arg; /* Argument that is passed to the handler */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static void sam_oneshot_handler(void *arg);
+
+static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts);
+static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback, FAR void *arg,
+ FAR const struct timespec *ts);
+static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Lower half operations */
+
+static const struct oneshot_operations_s g_oneshot_ops =
+{
+ .max_delay = sam_max_delay,
+ .start = sam_start,
+ .cancel = sam_cancel,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_oneshot_handler
+ *
+ * Description:
+ * Timer expiration handler
+ *
+ * Input Parameters:
+ * arg - Should be the same argument provided when sam_oneshot_start()
+ * was called.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void sam_oneshot_handler(void *arg)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)arg;
+ oneshot_callback_t callback;
+ FAR void *cbarg;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Perhaps the callback was nullified in a race condition with
+ * sam_cancel?
+ */
+
+ if (priv->callback)
+ {
+ /* Sample and nullify BEFORE executing callback (in case the callback
+ * restarts the oneshot).
+ */
+
+ callback = priv->callback;
+ cbarg = priv->arg;
+ priv->callback = NULL;
+ priv->arg = NULL;
+
+ /* Then perform the callback */
+
+ callback(&priv->lh, cbarg);
+ }
+}
+
+/****************************************************************************
+ * Name: sam_max_delay
+ *
+ * Description:
+ * Determine the maximum delay of the one-shot timer (in microseconds)
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the maxumum delay.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)lower;
+ uint64_t usecs;
+ int ret;
+
+ DEBUGASSERT(priv != NULL && ts != NULL);
+ ret = sam_oneshot_max_delay(&priv->oneshot, &usecs);
+ if (ret >= 0)
+ {
+ uint64_t sec = usecs / 1000000;
+ usecs -= 1000000 * sec;
+
+ ts->tv_sec = (time_t)sec;
+ ts->tv_nsec = (long)(usecs * 1000);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: sam_start
+ *
+ * Description:
+ * Start the oneshot timer
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * handler The function to call when when the oneshot timer expires.
+ * arg An opaque argument that will accompany the callback.
+ * ts Provides the duration of the one shot timer.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback, FAR void *arg,
+ FAR const struct timespec *ts)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)lower;
+ irqstate_t flags;
+ int ret;
+
+ DEBUGASSERT(priv != NULL && callback != NULL && ts != NULL);
+
+ /* Save the callback information and start the timer */
+
+ flags = enter_critical_section();
+ priv->callback = callback;
+ priv->arg = arg;
+ ret = sam_oneshot_start(&priv->oneshot, NULL,
+ sam_oneshot_handler, priv, ts);
+ leave_critical_section(flags);
+
+ if (ret < 0)
+ {
+ tmrerr("ERROR: sam_oneshot_start failed: %d\n", flags);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: sam_cancel
+ *
+ * Description:
+ * Cancel the oneshot timer and return the time remaining on the timer.
+ *
+ * NOTE: This function may execute at a high rate with no timer running (as
+ * when pre-emption is enabled and disabled).
+ *
+ * Input Parameters:
+ * lower Caller allocated instance of the oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the time remaining on the
+ * oneshot timer. A time of zero is returned if the timer is
+ * not running.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A call to up_timer_cancel() when
+ * the timer is not active should also return success; a negated errno
+ * value is returned on any failure.
+ *
+ ****************************************************************************/
+
+static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)lower;
+ irqstate_t flags;
+ int ret;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Cancel the timer */
+
+ flags = enter_critical_section();
+ ret = sam_oneshot_cancel(&priv->oneshot, NULL, ts);
+ priv->callback = NULL;
+ priv->arg = NULL;
+ leave_critical_section(flags);
+
+ if (ret < 0)
+ {
+ tmrerr("ERROR: sam_oneshot_cancel failed: %d\n", flags);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: oneshot_initialize
+ *
+ * Description:
+ * Initialize the oneshot timer and return a oneshot lower half driver
+ * instance.
+ *
+ * Input Parameters:
+ * chan Timer counter channel to be used.
+ * resolution The required resolution of the timer in units of
+ * microseconds. NOTE that the range is restricted to the
+ * range of uint16_t (excluding zero).
+ *
+ * Returned Value:
+ * On success, a non-NULL instance of the oneshot lower-half driver is
+ * returned. NULL is return on any failure.
+ *
+ ****************************************************************************/
+
+FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
+ uint16_t resolution)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv;
+ int ret;
+
+ /* Allocate an instance of the lower half driver */
+
+ priv = (FAR struct sam_oneshot_lowerhalf_s *)
+ kmm_zalloc(sizeof(struct sam_oneshot_lowerhalf_s));
+
+ if (priv == NULL)
+ {
+ tmrerr("ERROR: Failed to initialized state structure\n");
+ return NULL;
+ }
+
+ /* Initialize the lower-half driver structure */
+
+ priv->lh.ops = &g_oneshot_ops;
+
+ /* Initialize the contained SAM oneshot timer */
+
+ ret = sam_oneshot_initialize(&priv->oneshot, chan, resolution);
+ if (ret < 0)
+ {
+ tmrerr("ERROR: sam_oneshot_initialize failed: %d\n", ret);
+ kmm_free(priv);
+ return NULL;
+ }
+
+ return &priv->lh;
+}
\ No newline at end of file
diff --git a/arch/arm/src/sam34/sam4cm_tickless.c b/arch/arm/src/sam34/sam4cm_tickless.c
index ed6b56dccd0e1dcf073a1143d8342cc9e10750dd..54b6c943af947bec5c4fc5e4005ded68b6755df0 100644
--- a/arch/arm/src/sam34/sam4cm_tickless.c
+++ b/arch/arm/src/sam34/sam4cm_tickless.c
@@ -197,7 +197,7 @@ static struct sam_tickless_s g_tickless;
static void sam_oneshot_handler(void *arg)
{
- tmrllinfo("Expired...\n");
+ tmrinfo("Expired...\n");
sched_timer_expiration();
}
@@ -244,7 +244,7 @@ void up_timer_initialize(void)
CONFIG_USEC_PER_TICK);
if (ret < 0)
{
- tmrllerr("ERROR: sam_oneshot_initialize failed\n");
+ tmrerr("ERROR: sam_oneshot_initialize failed\n");
PANIC();
}
@@ -256,7 +256,7 @@ void up_timer_initialize(void)
ret = sam_oneshot_max_delay(&g_tickless.oneshot, &max_delay);
if (ret < 0)
{
- tmrllerr("ERROR: sam_oneshot_max_delay failed\n");
+ tmrerr("ERROR: sam_oneshot_max_delay failed\n");
PANIC();
}
@@ -280,7 +280,7 @@ void up_timer_initialize(void)
CONFIG_USEC_PER_TICK);
if (ret < 0)
{
- tmrllerr("ERROR: sam_freerun_initialize failed\n");
+ tmrerr("ERROR: sam_freerun_initialize failed\n");
PANIC();
}
diff --git a/arch/arm/src/sam34/sam_dmac.c b/arch/arm/src/sam34/sam_dmac.c
index 01b7f65656a00105ebafca792a8d75dcbc186962..7cf1cff349991acae896bab29e2cf5f9a94ae548 100644
--- a/arch/arm/src/sam34/sam_dmac.c
+++ b/arch/arm/src/sam34/sam_dmac.c
@@ -1354,7 +1354,7 @@ static int sam_dmainterrupt(int irq, void *context)
void weak_function up_dmainitialize(void)
{
- dmallinfo("Initialize DMAC0\n");
+ dmainfo("Initialize DMAC0\n");
/* Enable peripheral clock */
diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c
index b1a665dd9ac83eb821b5efaa653c88ab28880211..a7a9bc2141014c7aedeab6da21c5e89c93e727af 100644
--- a/arch/arm/src/sam34/sam_emac.c
+++ b/arch/arm/src/sam34/sam_emac.c
@@ -207,18 +207,7 @@
#endif
-/* EMAC buffer sizes, number of buffers, and number of descriptors.
- *
- * REVISIT: The CONFIG_NET_MULTIBUFFER might be useful. It might be possible
- * to use this option to send and receive messages directly into the DMA
- * buffers, saving a copy. There might be complications on the receiving
- * side, however, where buffers may wrap and where the size of the received
- * frame will typically be smaller than a full packet.
- */
-
-#ifdef CONFIG_NET_MULTIBUFFER
-# error CONFIG_NET_MULTIBUFFER must not be set
-#endif
+/* EMAC buffer sizes, number of buffers, and number of descriptors. *********/
#define EMAC_RX_UNITSIZE 128 /* Fixed size for RX buffer */
#define EMAC_TX_UNITSIZE CONFIG_NET_ETH_MTU /* MAX size for Ethernet packet */
@@ -312,6 +301,19 @@ struct sam_emac_s
static struct sam_emac_s g_emac;
+#ifdef CONFIG_NET_MULTIBUFFER
+/* A single packet buffer is used
+ *
+ * REVISIT: It might be possible to use this option to send and receive
+ * messages directly into the DMA buffers, saving a copy. There might be
+ * complications on the receiving side, however, where buffers may wrap
+ * and where the size of the received frame will typically be smaller than
+ * a full packet.
+ */
+
+static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE];
+#endif
+
#ifdef CONFIG_SAM34_EMAC_PREALLOCATE
/* Preallocated data */
/* TX descriptors list */
@@ -753,14 +755,14 @@ static int sam_transmit(struct sam_emac_s *priv)
uint32_t regval;
uint32_t status;
- nllinfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
+ ninfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
/* Check parameter */
if (dev->d_len > EMAC_TX_UNITSIZE)
{
- nllerr("ERROR: Packet too big: %d\n", dev->d_len);
+ nerr("ERROR: Packet too big: %d\n", dev->d_len);
return -EINVAL;
}
@@ -772,7 +774,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
- nllerr("ERROR: No free TX descriptors\n");
+ nerr("ERROR: No free TX descriptors\n");
return -EBUSY;
}
@@ -830,7 +832,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
- nllinfo("Disabling RX interrupts\n");
+ ninfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_RCOMP);
}
@@ -1010,7 +1012,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
sam_cmcc_invalidate((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
- nllinfo("rxndx: %d\n", rxndx);
+ ninfo("rxndx: %d\n", rxndx);
while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
{
@@ -1060,7 +1062,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
{
if (rxndx == priv->rxndx)
{
- nllinfo("ERROR: No EOF (Invalid of buffers too small)\n");
+ nerr("ERROR: No EOF (Invalid of buffers too small)\n");
do
{
/* Give ownership back to the EMAC */
@@ -1107,7 +1109,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Frame size from the EMAC */
dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
- nllinfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
+ ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor
@@ -1132,11 +1134,11 @@ static int sam_recvframe(struct sam_emac_s *priv)
* all of the data.
*/
- nllinfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
+ ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
- nllerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
+ nerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
return -E2BIG;
}
@@ -1167,7 +1169,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* No packet was found */
priv->rxndx = rxndx;
- nllinfo("rxndx: %d\n", priv->rxndx);
+ ninfo("rxndx: %d\n", priv->rxndx);
return -EAGAIN;
}
@@ -1207,7 +1209,7 @@ static void sam_receive(struct sam_emac_s *priv)
if (dev->d_len > CONFIG_NET_ETH_MTU)
{
- nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
+ nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
continue;
}
@@ -1222,7 +1224,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllinfo("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@@ -1262,7 +1264,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllinfo("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@@ -1299,7 +1301,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
- nllinfo("ARP frame\n");
+ ninfo("ARP frame\n");
/* Handle ARP packet */
@@ -1317,7 +1319,7 @@ static void sam_receive(struct sam_emac_s *priv)
else
#endif
{
- nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
+ nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
}
}
}
@@ -1442,7 +1444,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
imr = sam_getreg(priv, SAM_EMAC_IMR);
pending = isr & ~(imr | EMAC_INT_UNUSED);
- nllinfo("isr: %08x pending: %08x\n", isr, pending);
+ ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
@@ -1468,7 +1470,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
clrbits = EMAC_TSR_RLE | sam_txinuse(priv);
sam_txreset(priv);
- nllerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
+ nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval |= EMAC_NCR_TXEN;
@@ -1479,7 +1481,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((tsr & EMAC_TSR_COL) != 0)
{
- nllerr("ERROR: Collision occurred TSR: %08x\n", tsr);
+ nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_COL;
}
@@ -1487,7 +1489,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((tsr & EMAC_TSR_TFC) != 0)
{
- nllerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
+ nerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
clrbits |= EMAC_TSR_TFC;
}
@@ -1502,7 +1504,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((tsr & EMAC_TSR_UND) != 0)
{
- nllerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
+ nerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_UND;
}
@@ -1539,7 +1541,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((rsr & EMAC_RSR_RXOVR) != 0)
{
- nllerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
+ nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_RXOVR;
}
@@ -1556,7 +1558,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((rsr & EMAC_RSR_BNA) != 0)
{
- nllerr("ERROR: Buffer not available RSR: %08x\n", rsr);
+ nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_BNA;
}
@@ -1578,7 +1580,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((pending & EMAC_INT_PFNZ) != 0)
{
- nllwarn("WARNING: Pause frame received\n");
+ nwarn("WARNING: Pause frame received\n");
}
/* Check for Pause Time Zero (PTZ)
@@ -1588,7 +1590,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((pending & EMAC_INT_PTZ) != 0)
{
- nllwarn("WARNING: Pause TO!\n");
+ nwarn("WARNING: Pause TO!\n");
}
#endif
}
@@ -1725,7 +1727,7 @@ static int sam_emac_interrupt(int irq, void *context)
static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv)
{
- nllerr("ERROR: Timeout!\n");
+ nerr("ERROR: Timeout!\n");
/* Then reset the hardware. Just take the interface down, then back
* up again.
@@ -3806,6 +3808,9 @@ void up_netinitialize(void)
/* Initialize the driver structure */
memset(priv, 0, sizeof(struct sam_emac_s));
+#ifdef CONFIG_NET_MULTIBUFFER
+ priv->dev.d_buf = g_pktbuf; /* Single packet buffer */
+#endif
priv->dev.d_ifup = sam_ifup; /* I/F up (new IP address) callback */
priv->dev.d_ifdown = sam_ifdown; /* I/F down callback */
priv->dev.d_txavail = sam_txavail; /* New TX data callback */
diff --git a/arch/arm/src/sam34/sam_gpio.c b/arch/arm/src/sam34/sam_gpio.c
index 89461c58369c2fc6fe2ef3e8a311a873c99b6c2f..d1dc1ef64bdb6d9ef2dbd19e1407f1d7711a1f26 100644
--- a/arch/arm/src/sam34/sam_gpio.c
+++ b/arch/arm/src/sam34/sam_gpio.c
@@ -54,6 +54,7 @@
#include "chip.h"
#include "sam_gpio.h"
+#include "sam_periphclks.h"
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
@@ -96,7 +97,7 @@ static inline uintptr_t sam_gpiobase(gpio_pinset_t cfgset)
* Name: sam_gpiopin
*
* Description:
- * Returun the base address of the GPIO register set
+ * Return the base address of the GPIO register set
*
****************************************************************************/
@@ -105,6 +106,67 @@ static inline int sam_gpiopin(gpio_pinset_t cfgset)
return 1 << ((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
}
+/****************************************************************************
+ * Name: sam_gpio_enableclk
+ *
+ * Description:
+ * Enable clocking on the PIO port. Port clocking is required in the
+ * following cases:
+ *
+ * - In order to read values in input pins from the port
+ * - If the port supports interrupting pins
+ * - If glitch filtering is enabled
+ * - If necessary to read the input value on an open drain output (this
+ * may be done in TWI logic to detect hangs on the I2C bus).
+ * - If necessary to read the input value on peripheral pins.
+ *
+ ****************************************************************************/
+
+static inline int sam_gpio_enableclk(gpio_pinset_t cfgset)
+{
+ /* Enable the peripheral clock for the GPIO's port controller. */
+
+ switch (cfgset & GPIO_PORT_MASK)
+ {
+ case GPIO_PORT_PIOA:
+ sam_pioa_enableclk();
+ break;
+
+ case GPIO_PORT_PIOB:
+ sam_piob_enableclk();
+ break;
+
+#ifdef GPIO_PORT_PIOC
+ case GPIO_PORT_PIOC:
+ sam_pioc_enableclk();
+ break;
+#endif
+
+#ifdef GPIO_PORT_PIOD
+ case GPIO_PORT_PIOD:
+ sam_piod_enableclk();
+ break;
+#endif
+
+#ifdef GPIO_PORT_PIOE
+ case GPIO_PORT_PIOE:
+ sam_pioe_enableclk();
+ break;
+#endif
+
+#ifdef GPIO_PORT_PIOF
+ case GPIO_PORT_PIOF:
+ sam_piof_enableclk();
+ break;
+#endif
+
+ default:
+ return -EINVAL;
+ }
+
+ return OK;
+}
+
/****************************************************************************
* Name: sam_configinput
*
@@ -128,6 +190,14 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
if ((cfgset & GPIO_CFG_PULLUP) != 0)
{
+#ifdef GPIO_HAVE_PULLDOWN
+ /* The pull-up on a pin can not be enabled if its pull-down is still
+ * active. Therefore, we need to disable the pull-down first before
+ * enabling the pull-up.
+ */
+
+ putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
+#endif
putreg32(pin, base + SAM_PIO_PUER_OFFSET);
}
else
@@ -140,6 +210,12 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
{
+ /* The pull-down on a pin can not be enabled if its pull-up is still
+ * active. Therefore, we need to disable the pull-up first before
+ * enabling the pull-down.
+ */
+
+ putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
}
else
@@ -171,6 +247,7 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
{
regval &= ~pin;
}
+
putreg32(regval, base + SAM_PIO_SCHMITT_OFFSET);
#endif
@@ -184,7 +261,12 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
* another, new API... perhaps sam_configfilter()
*/
- return OK;
+ /* Enable the peripheral clock for the GPIO's port controller.
+ * A GPIO input value is only sampled if the peripheral clock for its
+ * controller is enabled.
+ */
+
+ return sam_gpio_enableclk(cfgset);
}
/****************************************************************************
@@ -206,6 +288,14 @@ static inline int sam_configoutput(uintptr_t base, uint32_t pin,
if ((cfgset & GPIO_CFG_PULLUP) != 0)
{
+#ifdef GPIO_HAVE_PULLDOWN
+ /* The pull-up on a pin can not be enabled if its pull-down is still
+ * active. Therefore, we need to disable the pull-down first before
+ * enabling the pull-up.
+ */
+
+ putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
+#endif
putreg32(pin, base + SAM_PIO_PUER_OFFSET);
}
else
@@ -218,6 +308,12 @@ static inline int sam_configoutput(uintptr_t base, uint32_t pin,
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
{
+ /* The pull-down on a pin can not be enabled if its pull-up is still
+ * active. Therefore, we need to disable the pull-up first before
+ * enabling the pull-down.
+ */
+
+ putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
}
else
@@ -277,6 +373,14 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
if ((cfgset & GPIO_CFG_PULLUP) != 0)
{
+#ifdef GPIO_HAVE_PULLDOWN
+ /* The pull-up on a pin can not be enabled if its pull-down is still
+ * active. Therefore, we need to disable the pull-down first before
+ * enabling the pull-up.
+ */
+
+ putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
+#endif
putreg32(pin, base + SAM_PIO_PUER_OFFSET);
}
else
@@ -289,6 +393,12 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
{
+ /* The pull-down on a pin can not be enabled if its pull-up is still
+ * active. Therefore, we need to disable the pull-up first before
+ * enabling the pull-down.
+ */
+
+ putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
}
else
diff --git a/arch/arm/src/sam34/sam_hsmci.c b/arch/arm/src/sam34/sam_hsmci.c
index e46ee1c37063045ac252d674e54a96805bcd8c16..fa4073d6a2799c877ef66df8b2fb4d6a6a0365e4 100644
--- a/arch/arm/src/sam34/sam_hsmci.c
+++ b/arch/arm/src/sam34/sam_hsmci.c
@@ -1083,7 +1083,7 @@ static void sam_eventtimeout(int argc, uint32_t arg)
/* Yes.. wake up any waiting threads */
sam_endwait(priv, SDIOWAIT_TIMEOUT);
- mcllerr("ERROR: Timeout\n");
+ mcerr("ERROR: Timeout\n");
}
}
@@ -1278,7 +1278,7 @@ static int sam_interrupt(int irq, void *context)
{
/* Yes.. Was it some kind of timeout error? */
- mcllerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
+ mcerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
if ((pending & HSMCI_DATA_TIMEOUT_ERRORS) != 0)
{
/* Yes.. Terminate with a timeout. */
@@ -1320,8 +1320,8 @@ static int sam_interrupt(int irq, void *context)
{
/* Yes.. Was the error some kind of timeout? */
- mcllinfo("ERROR: events: %08x SR: %08x\n",
- priv->cmdrmask, enabled);
+ mcerr("ERROR: events: %08x SR: %08x\n",
+ priv->cmdrmask, enabled);
if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
{
@@ -2628,7 +2628,7 @@ static void sam_callback(void *arg)
{
/* Yes.. queue it */
- mcllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
+ mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
(void)work_queue(LPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
}
else
@@ -2743,7 +2743,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
priv->cdstatus &= ~SDIO_STATUS_PRESENT;
}
- mcllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
+ mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
/* Perform any requested callback if the status has changed */
diff --git a/arch/arm/src/sam34/sam_rtc.c b/arch/arm/src/sam34/sam_rtc.c
index e6e5d0b6990bf93b57b9a22baa2e15d0c1a1e6eb..c4c548cc9f987152aa3c23e0b31309b89e2d89a7 100644
--- a/arch/arm/src/sam34/sam_rtc.c
+++ b/arch/arm/src/sam34/sam_rtc.c
@@ -274,7 +274,7 @@ static int rtc_interrupt(int irq, void *context)
ret = work_queue(LPWORK, &g_alarmwork, rtc_worker, NULL, 0);
if (ret < 0)
{
- rtcllerr("ERROR: work_queue failed: %d\n", ret);
+ rtcerr("ERROR: work_queue failed: %d\n", ret);
}
/* Disable any further alarm interrupts */
diff --git a/arch/arm/src/sam34/sam_serial.c b/arch/arm/src/sam34/sam_serial.c
index 46df27954a1a3066572132ffbd48397af92b818c..36043e9deb8753611e84f7747b271fd775aeeb09 100644
--- a/arch/arm/src/sam34/sam_serial.c
+++ b/arch/arm/src/sam34/sam_serial.c
@@ -692,8 +692,8 @@ static void up_disableallints(struct up_dev_s *priv, uint32_t *imr)
static int up_setup(struct uart_dev_s *dev)
{
- struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
#ifndef CONFIG_SUPPRESS_UART_CONFIG
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint32_t regval;
uint32_t imr;
diff --git a/arch/arm/src/sam34/sam_twi.c b/arch/arm/src/sam34/sam_twi.c
index af90936b1b9ed4517056b01ffda1a7d3fe267235..74d0e7d6ed337277c2c0a6791a96fed794bced95 100644
--- a/arch/arm/src/sam34/sam_twi.c
+++ b/arch/arm/src/sam34/sam_twi.c
@@ -390,9 +390,9 @@ static int twi_wait(struct twi_dev_s *priv)
do
{
- i2cllinfo("TWI%d Waiting...\n", priv->twi);
+ i2cinfo("TWI%d Waiting...\n", priv->twi);
twi_takesem(&priv->waitsem);
- i2cllinfo("TWI%d Awakened with result: %d\n", priv->twi, priv->result);
+ i2cinfo("TWI%d Awakened with result: %d\n", priv->twi, priv->result);
}
while (priv->result == -EBUSY);
@@ -449,7 +449,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
imr = twi_getrel(priv, SAM_TWI_IMR_OFFSET);
pending = sr & imr;
- i2cllinfo("TWI%d pending: %08x\n", priv->twi, pending);
+ i2cinfo("TWI%d pending: %08x\n", priv->twi, pending);
msg = priv->msg;
@@ -459,7 +459,7 @@ static int twi_interrupt(struct twi_dev_s *priv)
{
/* Wake up the thread with an I/O error indication */
- i2cllerr("ERROR: TWI%d pending: %08x\n", priv->twi, pending);
+ i2cerr("ERROR: TWI%d pending: %08x\n", priv->twi, pending);
twi_wakeup(priv, -EIO);
}
@@ -582,7 +582,7 @@ static void twi_timeout(int argc, uint32_t arg, ...)
{
struct twi_dev_s *priv = (struct twi_dev_s *)arg;
- i2cllerr("ERROR: TWI%d Timeout!\n", priv->twi);
+ i2cerr("ERROR: TWI%d Timeout!\n", priv->twi);
twi_wakeup(priv, -ETIMEDOUT);
}
@@ -666,7 +666,7 @@ static void twi_startwrite(struct twi_dev_s *priv, struct i2c_msg_s *msg)
static void twi_startmessage(struct twi_dev_s *priv, struct i2c_msg_s *msg)
{
- if ((msg->flags & I2C_M_READ) == 0)
+ if ((msg->flags & I2C_M_READ) != 0)
{
twi_startread(priv, msg);
}
diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c
index 8c84fce2f8815842333e4ce583f3c9ff88df08bd..96a521d0ba538272c1877052899a2d258a5f4318 100644
--- a/arch/arm/src/sam34/sam_udp.c
+++ b/arch/arm/src/sam34/sam_udp.c
@@ -305,6 +305,7 @@ struct sam_ep_s
uint8_t zlpneeded:1; /* Zero length packet needed at end of transfer */
uint8_t zlpsent:1; /* Zero length packet has been sent */
uint8_t txbusy:1; /* Write request queue is busy (recursion avoidance kludge) */
+ uint8_t lastbank:1; /* Last bank we read data from */
};
struct sam_usbdev_s
@@ -606,7 +607,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
#ifdef CONFIG_SAM34_UDP_REGDEBUG
static void sam_printreg(uintptr_t regaddr, uint32_t regval, bool iswrite)
{
- _llinfo("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval);
+ _info("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval);
}
#endif
@@ -657,7 +658,7 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite)
{
/* No.. More than one. */
- _llinfo("[repeats %d more times]\n", count);
+ _info("[repeats %d more times]\n", count);
}
}
@@ -737,15 +738,15 @@ static void sam_dumpep(struct sam_usbdev_s *priv, uint8_t epno)
{
/* Global Registers */
- _llinfo("Global Registers:\n");
- _llinfo(" FRMNUM: %08x\n", sam_getreg(SAM_UDP_FRMNUM));
- _llinfo("GLBSTAT: %08x\n", sam_getreg(SAM_UDP_GLBSTAT));
- _llinfo(" FADDR: %08x\n", sam_getreg(SAM_UDP_FADDR));
- _llinfo(" IMR: %08x\n", sam_getreg(SAM_UDP_IMR));
- _llinfo(" ISR: %08x\n", sam_getreg(SAM_UDP_ISR));
- _llinfo(" RSTEP: %08x\n", sam_getreg(SAM_UDP_RSTEP));
- _llinfo(" TXVC: %08x\n", sam_getreg(SAM_UDP_TXVC));
- _llinfo(" CSR[%d]: %08x\n", epno, sam_getreg(SAM_UDPEP_CSR(epno)));
+ _info("Global Registers:\n");
+ _info(" FRMNUM: %08x\n", sam_getreg(SAM_UDP_FRMNUM));
+ _info("GLBSTAT: %08x\n", sam_getreg(SAM_UDP_GLBSTAT));
+ _info(" FADDR: %08x\n", sam_getreg(SAM_UDP_FADDR));
+ _info(" IMR: %08x\n", sam_getreg(SAM_UDP_IMR));
+ _info(" ISR: %08x\n", sam_getreg(SAM_UDP_ISR));
+ _info(" RSTEP: %08x\n", sam_getreg(SAM_UDP_RSTEP));
+ _info(" TXVC: %08x\n", sam_getreg(SAM_UDP_TXVC));
+ _info(" CSR[%d]: %08x\n", epno, sam_getreg(SAM_UDPEP_CSR(epno)));
}
#endif
@@ -968,9 +969,9 @@ static int sam_req_write(struct sam_usbdev_s *priv, struct sam_ep_s *privep)
return -ENOENT;
}
- ullinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
- epno, privreq, privreq->req.len, privreq->req.xfrd,
- privreq->inflight, privep->zlpneeded);
+ uinfo("epno=%d req=%p: len=%d xfrd=%d inflight=%d zlpneeded=%d\n",
+ epno, privreq, privreq->req.len, privreq->req.xfrd,
+ privreq->inflight, privep->zlpneeded);
/* Handle any bytes in flight. */
@@ -1139,8 +1140,8 @@ static int sam_req_read(struct sam_usbdev_s *priv, struct sam_ep_s *privep,
return -ENOENT;
}
- ullinfo("EP%d: len=%d xfrd=%d\n",
- epno, privreq->req.len, privreq->req.xfrd);
+ uinfo("EP%d: len=%d xfrd=%d\n",
+ epno, privreq->req.len, privreq->req.xfrd);
/* Ignore any attempt to receive a zero length packet */
@@ -1188,9 +1189,14 @@ static int sam_req_read(struct sam_usbdev_s *priv, struct sam_ep_s *privep,
/* We get here when an RXDATABK0/1 interrupt occurs. That interrupt
* cannot be cleared until all of the data has been taken from the RX
- * FIFO. But we can
+ * FIFO.
+ *
+ * Also, we need to remember which bank we read last so the interrupt handler
+ * can determine the correct bank read sequence for future reads.
*/
+ privep->lastbank = bank;
+
sam_csr_clrbits(epno, bank ? UDPEP_CSR_RXDATABK1 : UDPEP_CSR_RXDATABK0);
/* Complete the transfer immediately and give the data to the class
@@ -1408,8 +1414,8 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
index.w = GETUINT16(priv->ctrl.index);
len.w = GETUINT16(priv->ctrl.len);
- ullinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
- priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
+ uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+ priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
/* Dispatch any non-standard requests */
@@ -1572,7 +1578,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
{
/* Special case recipient=device test mode */
- ullinfo("test mode: %d\n", index.w);
+ uinfo("test mode: %d\n", index.w);
}
else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT)
{
@@ -1873,7 +1879,6 @@ static void sam_ep_bankinterrupt(struct sam_usbdev_s *priv,
* transferred from the FIFO.
*/
- privep->epstate = UDP_EPSTATE_IDLE;
(void)sam_req_read(priv, privep, pktsize, bank);
}
@@ -1959,6 +1964,8 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno)
struct sam_ep_s *privep;
uintptr_t regaddr;
uint32_t csr;
+ bool bk0;
+ bool bk1;
DEBUGASSERT((unsigned)epno < SAM_UDP_NENDPOINTS);
@@ -2020,33 +2027,81 @@ static void sam_ep_interrupt(struct sam_usbdev_s *priv, int epno)
}
}
- /* OUT packet received in data bank 0 */
- if ((csr & UDPEP_CSR_RXDATABK0) != 0)
- {
- usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK0), (uint16_t)csr);
+ /* OUT packet received.
+ *
+ * OUT packets are received in two banks. The hardware does not provide
+ * information about which bank has been filled last. Therefore we need to
+ * keep track about which bank we read last to figure out which bank(s) we
+ * need to read next.
+ *
+ * When we get here either none, one or both banks can be filled with data.
+ * Depending on which bank we read last and which bank(s) contain data we
+ * need to correctly sequence the FIFO reads:
+ *
+ * case lastbank bk0 bk1 read sequence
+ * 1. 0 0 0 No data to read
+ * 2. 0 1 0 Only read bank 0
+ * 3. 0 0 1 Only read bank 1
+ * 4. 0 1 1 Read bank 1, then read bank 0
+ *
+ * 5. 1 0 0 No data to read
+ * 6. 1 1 0 Only read bank 0
+ * 7. 1 0 1 Only read bank 1 (should not happen)
+ * 8. 1 1 1 Read bank 0, then read bank 1
+ *
+ * lastbank will be updated in sam_req_read() after the FIFO has been read
+ * and clear RXDATABKx.
+ */
- /* Handle data received on Bank 0. sam_ep_bankinterrupt will
- * clear the RXDATABK0 interrupt once that data has been
- * transferred from the FIFO.
- */
+ bk0 = (csr & UDPEP_CSR_RXDATABK0) != 0;
+ bk1 = (csr & UDPEP_CSR_RXDATABK1) != 0;
+
+ /* 2. and 6. - Only read bank 0 */
+ if (bk0 && !bk1)
+ {
+ usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK0), (uint16_t)csr);
sam_ep_bankinterrupt(priv, privep, csr, 0);
}
- /* OUT packet received in data bank 1 */
+ /* 3. and 7. - Only read bank 1*/
- else if ((csr & UDPEP_CSR_RXDATABK1) != 0)
+ else if (!bk0 && bk1)
{
+#ifdef CONFIG_DEBUG_USB_WARN
+ if (privep->lastbank == 1)
+ {
+ uwarn("WARNING: Unexpected USB RX case.\n");
+ }
+#endif
+
usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK1), (uint16_t)csr);
- DEBUGASSERT(SAM_UDP_NBANKS(epno) > 1);
+ sam_ep_bankinterrupt(priv, privep, csr, 1);
+ }
+ else if (bk0 && bk1)
+ {
+ /* 4. - Read bank 1, then read bank 0 */
- /* Handle data received on Bank 1. sam_ep_bankinterrupt will
- * clear the RXDATABK1 interrupt once that data has been
- * transferred from the FIFO.
- */
+ if (privep->lastbank == 0)
+ {
+ usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK1), (uint16_t)csr);
+ sam_ep_bankinterrupt(priv, privep, csr, 1);
- sam_ep_bankinterrupt(priv, privep, csr, 1);
+ usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK0), (uint16_t)csr);
+ sam_ep_bankinterrupt(priv, privep, csr, 0);
+ }
+
+ /* 8. - Read bank 0, then read bank 1 */
+
+ else
+ {
+ usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK0), (uint16_t)csr);
+ sam_ep_bankinterrupt(priv, privep, csr, 0);
+
+ usbtrace(TRACE_INTDECODE(SAM_TRACEINTID_RXDATABK1), (uint16_t)csr);
+ sam_ep_bankinterrupt(priv, privep, csr, 1);
+ }
}
/* STALL sent */
@@ -2510,6 +2565,7 @@ static void sam_ep_reset(struct sam_usbdev_s *priv, uint8_t epno)
privep->zlpneeded = false;
privep->zlpsent = false;
privep->txbusy = false;
+ privep->lastbank = 1;
}
/****************************************************************************
@@ -2946,7 +3002,7 @@ static int sam_ep_disable(struct usbdev_ep_s *ep)
if (!ep)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
- ullerr("ERROR: ep=%p\n", ep);
+ uerr("ERROR: ep=%p\n", ep);
return -EINVAL;
}
#endif
@@ -3079,7 +3135,8 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (!req || !req->callback || !req->buf || !ep)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_INVALIDPARMS), 0);
- ullerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+ uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
+ req, req->callback, req->buf, ep);
return -EINVAL;
}
#endif
@@ -3091,7 +3148,7 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
if (!priv->driver)
{
usbtrace(TRACE_DEVERROR(SAM_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
- ullerr("ERROR: driver=%p\n", priv->driver);
+ uerr("ERROR: driver=%p\n", priv->driver);
return -ESHUTDOWN;
}
#endif
@@ -3119,7 +3176,7 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
* queue. They will stay queuee until the stall is cleared.
*/
- ullinfo("Pending stall clear\n");
+ uinfo("Pending stall clear\n");
sam_req_enqueue(&privep->pendq, privreq);
usbtrace(TRACE_INREQQUEUED(epno), req->len);
ret = OK;
diff --git a/arch/arm/src/sam34/sam_wdt.c b/arch/arm/src/sam34/sam_wdt.c
index cf3d70b1613e66d04fd435a1fbc20d9f8b157904..62075d9a7657392298f57d721fd5bbf1fef90262 100644
--- a/arch/arm/src/sam34/sam_wdt.c
+++ b/arch/arm/src/sam34/sam_wdt.c
@@ -554,7 +554,7 @@ static xcpt_t sam34_capture(FAR struct watchdog_lowerhalf_s *lower,
regval |= WWDG_CFR_EWI;
sam34_putreg(regval, SAM_WDT_CFR);
- up_enable_irq(STM32_IRQ_WWDG);
+ up_enable_irq(SAM_IRQ_WWDG);
}
else
{
@@ -563,7 +563,7 @@ static xcpt_t sam34_capture(FAR struct watchdog_lowerhalf_s *lower,
regval &= ~WWDG_CFR_EWI;
sam34_putreg(regval, SAM_WDT_CFR);
- up_disable_irq(STM32_IRQ_WWDG);
+ up_disable_irq(SAM_IRQ_WWDG);
}
leave_critical_section(flags);
diff --git a/arch/arm/src/sam34/sam_wdt.h b/arch/arm/src/sam34/sam_wdt.h
index 234f4e25204273d54d7344673331afe12e1a3634..77a1fbab40e3dd684031c8ab1e7a459c427cf83c 100644
--- a/arch/arm/src/sam34/sam_wdt.h
+++ b/arch/arm/src/sam34/sam_wdt.h
@@ -95,4 +95,4 @@ void sam_wdtinitialize(FAR const char *devpath);
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_WATCHDOG */
-#endif /* __ARCH_ARM_SRC_STM32_STM32_WDG_H */
+#endif /* __ARCH_ARM_SRC_SAM34_WDT_H */
diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig
index 11aa7179f1f9aff562b9f5c55ca542f093c31f75..121ee991ecca6cc96f910c6e3aec2afdf1882583 100644
--- a/arch/arm/src/sama5/Kconfig
+++ b/arch/arm/src/sama5/Kconfig
@@ -3866,7 +3866,6 @@ endif # SAMA5_TC2
config SAMA5_ONESHOT
bool "TC one-shot wrapper"
- depends on SAMA5_FREERUN
default n if !SCHED_TICKLESS
default y if SCHED_TICKLESS
---help---
diff --git a/arch/arm/src/sama5/Make.defs b/arch/arm/src/sama5/Make.defs
index cfe0d0a3deaf21e098f85003c2fa7aec1d0c25ea..ff8121073052866713bdd54050eaae772b8507aa 100644
--- a/arch/arm/src/sama5/Make.defs
+++ b/arch/arm/src/sama5/Make.defs
@@ -1,7 +1,7 @@
############################################################################
# arch/arm/sama5/Make.defs
#
-# Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
+# Copyright (C) 2013-2014, 2016 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt
#
# Redistribution and use in source and binary forms, with or without
@@ -292,7 +292,7 @@ endif
ifeq ($(CONFIG_SAMA5_HAVE_TC),y)
CHIP_CSRCS += sam_tc.c
ifeq ($(CONFIG_SAMA5_ONESHOT),y)
-CHIP_CSRCS += sam_oneshot.c
+CHIP_CSRCS += sam_oneshot.c sam_oneshot_lowerhalf.c
endif
ifeq ($(CONFIG_SAMA5_FREERUN),y)
CHIP_CSRCS += sam_freerun.c
diff --git a/arch/arm/src/sama5/sam_adc.c b/arch/arm/src/sama5/sam_adc.c
index ad276ff947a0595327f82ccfd5f0a3da350ebaf4..dcf82b1f6d9c5f72bf7f7edd4dac7ead2e629e09 100644
--- a/arch/arm/src/sama5/sam_adc.c
+++ b/arch/arm/src/sama5/sam_adc.c
@@ -729,7 +729,7 @@ static void sam_adc_dmacallback(DMA_HANDLE handle, void *arg, int result)
struct sam_adc_s *priv = (struct sam_adc_s *)arg;
int ret;
- allinfo("ready=%d enabled=%d\n", priv->enabled, priv->ready);
+ ainfo("ready=%d enabled=%d\n", priv->enabled, priv->ready);
DEBUGASSERT(priv->ready);
/* Check of the bottom half is keeping up with us.
@@ -755,7 +755,7 @@ static void sam_adc_dmacallback(DMA_HANDLE handle, void *arg, int result)
ret = work_queue(HPWORK, &priv->work, sam_adc_dmadone, priv, 0);
if (ret != 0)
{
- allerr("ERROR: Failed to queue work: %d\n", ret);
+ aerr("ERROR: Failed to queue work: %d\n", ret);
}
}
@@ -961,7 +961,7 @@ static int sam_adc_interrupt(int irq, void *context)
ret = work_queue(HPWORK, &priv->work, sam_adc_endconversion, priv, 0);
if (ret != 0)
{
- allerr("ERROR: Failed to queue work: %d\n", ret);
+ aerr("ERROR: Failed to queue work: %d\n", ret);
}
pending &= ~ADC_INT_EOCALL;
diff --git a/arch/arm/src/sama5/sam_can.c b/arch/arm/src/sama5/sam_can.c
index 10bb9a4d330ce703fd94f62cea01f991f0e38578..f801e6e8341f9f14908d95b7b4b94152d673c877 100644
--- a/arch/arm/src/sama5/sam_can.c
+++ b/arch/arm/src/sama5/sam_can.c
@@ -60,7 +60,7 @@
#include
#include
-#include
+#include
#include "up_internal.h"
#include "up_arch.h"
@@ -783,7 +783,7 @@ static void can_reset(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
- canllinfo("CAN%d\n", config->port);
+ caninfo("CAN%d\n", config->port);
UNUSED(config);
/* Get exclusive access to the CAN peripheral */
@@ -840,7 +840,7 @@ static int can_setup(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
- canllinfo("CAN%d pid: %d\n", config->port, config->pid);
+ caninfo("CAN%d pid: %d\n", config->port, config->pid);
/* Get exclusive access to the CAN peripheral */
@@ -851,7 +851,7 @@ static int can_setup(FAR struct can_dev_s *dev)
ret = can_hwinitialize(priv);
if (ret < 0)
{
- canllerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret);
+ canerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret);
return ret;
}
@@ -863,7 +863,7 @@ static int can_setup(FAR struct can_dev_s *dev)
ret = irq_attach(config->pid, config->handler);
if (ret < 0)
{
- canllerr("ERROR: Failed to attach CAN%d IRQ (%d)", config->port, config->pid);
+ canerr("ERROR: Failed to attach CAN%d IRQ (%d)", config->port, config->pid);
return ret;
}
@@ -872,7 +872,7 @@ static int can_setup(FAR struct can_dev_s *dev)
ret = can_recvsetup(priv);
if (ret < 0)
{
- canllerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret);
+ canerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret);
return ret;
}
@@ -918,7 +918,7 @@ static void can_shutdown(FAR struct can_dev_s *dev)
config = priv->config;
DEBUGASSERT(config);
- canllinfo("CAN%d\n", config->port);
+ caninfo("CAN%d\n", config->port);
/* Get exclusive access to the CAN peripheral */
@@ -957,7 +957,7 @@ static void can_rxint(FAR struct can_dev_s *dev, bool enable)
FAR struct sam_can_s *priv = dev->cd_priv;
DEBUGASSERT(priv && priv->config);
- canllinfo("CAN%d enable: %d\n", priv->config->port, enable);
+ caninfo("CAN%d enable: %d\n", priv->config->port, enable);
/* Enable/disable the mailbox interrupts from all receive mailboxes */
@@ -990,7 +990,7 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable)
FAR struct sam_can_s *priv = dev->cd_priv;
DEBUGASSERT(priv && priv->config);
- canllinfo("CAN%d enable: %d\n", priv->config->port, enable);
+ caninfo("CAN%d enable: %d\n", priv->config->port, enable);
/* Get exclusive access to the CAN peripheral */
@@ -1091,9 +1091,9 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
priv = dev->cd_priv;
DEBUGASSERT(priv && priv->config);
- canllinfo("CAN%d\n", priv->config->port);
- canllinfo("CAN%d ID: %d DLC: %d\n",
- priv->config->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
+ caninfo("CAN%d\n", priv->config->port);
+ caninfo("CAN%d ID: %d DLC: %d\n",
+ priv->config->port, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
/* Get exclusive access to the CAN peripheral */
@@ -1327,7 +1327,7 @@ static inline void can_rxinterrupt(FAR struct can_dev_s *dev, int mbndx,
ret = can_receive(dev, &hdr, (FAR uint8_t *)md);
if (ret < 0)
{
- canllerr("ERROR: can_receive failed: %d\n", ret);
+ canerr("ERROR: can_receive failed: %d\n", ret);
}
/* Set the MTCR flag in the CAN_MCRx register. This clears the
@@ -1422,9 +1422,9 @@ static inline void can_mbinterrupt(FAR struct can_dev_s *dev, int mbndx)
case CAN_MMR_MOT_CONSUMER: /* Consumer Mailbox */
case CAN_MMR_MOT_PRODUCER: /* Producer Mailbox */
case CAN_MMR_MOT_DISABLED: /* Mailbox is disabled */
- canllerr("ERROR: CAN%d MB%d: Unsupported or invalid mailbox type\n",
- priv->config->port, mbndx);
- canllerr(" MSR: %08x MMR: %08x\n", msr, mmr);
+ canerr("ERROR: CAN%d MB%d: Unsupported or invalid mailbox type\n",
+ priv->config->port, mbndx);
+ canerr(" MSR: %08x MMR: %08x\n", msr, mmr);
break;
}
}
@@ -1515,8 +1515,8 @@ static void can_interrupt(FAR struct can_dev_s *dev)
if ((pending & ~CAN_INT_MBALL) != 0)
{
- canllerr("ERROR: CAN%d system interrupt, SR=%08x IMR=%08x\n",
- priv->config->port, sr, imr);
+ canerr("ERROR: CAN%d system interrupt, SR=%08x IMR=%08x\n",
+ priv->config->port, sr, imr);
}
}
@@ -1773,7 +1773,7 @@ static int can_autobaud(struct sam_can_s *priv)
uint32_t regval;
int ret;
- canllinfo("CAN%d\n", config->port);
+ caninfo("CAN%d\n", config->port);
/* The CAN controller can start listening to the network in Autobaud Mode.
* In this case, the error counters are locked and a mailbox may be
@@ -1843,7 +1843,7 @@ static int can_hwinitialize(struct sam_can_s *priv)
uint32_t mck;
int ret;
- canllinfo("CAN%d\n", config->port);
+ caninfo("CAN%d\n", config->port);
/* Configure CAN pins */
diff --git a/arch/arm/src/sama5/sam_can.h b/arch/arm/src/sama5/sam_can.h
index c18361533f28bfeb54112d83bcc786395f8c00b2..5a26fe83143cd6fa19b78377cf23b1c165253cf4 100644
--- a/arch/arm/src/sama5/sam_can.h
+++ b/arch/arm/src/sama5/sam_can.h
@@ -45,7 +45,7 @@
#include "chip.h"
#include "chip/sam_can.h"
-#include
+#include
#if defined(CONFIG_CAN) && (defined(CONFIG_SAMA5_CAN0) || defined(CONFIG_SAMA5_CAN1))
diff --git a/arch/arm/src/sama5/sam_dmac.c b/arch/arm/src/sama5/sam_dmac.c
index 74bbd3f533ebf2145ee637f9f8944a8b00734d25..e3a813c1b211889c8887ad86766e94e7fadc319b 100644
--- a/arch/arm/src/sama5/sam_dmac.c
+++ b/arch/arm/src/sama5/sam_dmac.c
@@ -1818,7 +1818,7 @@ static int sam_dmac_interrupt(struct sam_dmac_s *dmac)
{
/* Yes... Terminate the transfer with an error? */
- dmallerr("ERROR: DMA failed: %08x\n", regval);
+ dmaerr("ERROR: DMA failed: %08x\n", regval);
sam_dmaterminate(dmach, -EIO);
}
@@ -1920,7 +1920,7 @@ void sam_dmainitialize(struct sam_dmac_s *dmac)
void weak_function up_dmainitialize(void)
{
#ifdef CONFIG_SAMA5_DMAC0
- dmallinfo("Initialize DMAC0\n");
+ dmainfo("Initialize DMAC0\n");
/* Enable peripheral clock */
@@ -1940,7 +1940,7 @@ void weak_function up_dmainitialize(void)
#endif
#ifdef CONFIG_SAMA5_DMAC1
- dmallinfo("Initialize DMAC1\n");
+ dmainfo("Initialize DMAC1\n");
/* Enable peripheral clock */
diff --git a/arch/arm/src/sama5/sam_ehci.c b/arch/arm/src/sama5/sam_ehci.c
index cdd86c208b717d69e4ae76b7bfb60ce53f43cb19..78135e3e8da744b05fddac210d79d1b7aa781732 100644
--- a/arch/arm/src/sama5/sam_ehci.c
+++ b/arch/arm/src/sama5/sam_ehci.c
@@ -3180,7 +3180,7 @@ static int sam_ehci_tophalf(int irq, FAR void *context)
#ifdef CONFIG_USBHOST_TRACE
usbhost_vtrace1(EHCI_VTRACE1_TOPHALF, usbsts & regval);
#else
- ullinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
+ uinfo("USBSTS: %08x USBINTR: %08x\n", usbsts, regval);
#endif
/* Handle all unmasked interrupt sources */
@@ -4493,7 +4493,7 @@ static int sam_connect(FAR struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
- ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+ uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */
diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c
index 553d15f51b96c33a22827dd17d4657de45aad637..672a3efc7fb780faf69772e656849728560da674 100644
--- a/arch/arm/src/sama5/sam_emaca.c
+++ b/arch/arm/src/sama5/sam_emaca.c
@@ -199,18 +199,7 @@
#endif
-/* EMAC buffer sizes, number of buffers, and number of descriptors.
- *
- * REVISIT: The CONFIG_NET_MULTIBUFFER might be useful. It might be possible
- * to use this option to send and receive messages directly into the DMA
- * buffers, saving a copy. There might be complications on the receiving
- * side, however, where buffers may wrap and where the size of the received
- * frame will typically be smaller than a full packet.
- */
-
-#ifdef CONFIG_NET_MULTIBUFFER
-# error CONFIG_NET_MULTIBUFFER must not be set
-#endif
+/* EMAC buffer sizes, number of buffers, and number of descriptors. *********/
#define EMAC_RX_UNITSIZE 128 /* Fixed size for RX buffer */
#define EMAC_TX_UNITSIZE CONFIG_NET_ETH_MTU /* MAX size for Ethernet packet */
@@ -301,6 +290,19 @@ struct sam_emac_s
static struct sam_emac_s g_emac;
+#ifdef CONFIG_NET_MULTIBUFFER
+/* A single packet buffer is used
+ *
+ * REVISIT: It might be possible to use this option to send and receive
+ * messages directly into the DMA buffers, saving a copy. There might be
+ * complications on the receiving side, however, where buffers may wrap
+ * and where the size of the received frame will typically be smaller than
+ * a full packet.
+ */
+
+static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE];
+#endif
+
#ifdef CONFIG_SAMA5_EMACA_PREALLOCATE
/* Preallocated data */
/* TX descriptors list */
@@ -607,7 +609,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->txdesc = (struct emac_txdesc_s *)kmm_memalign(8, allocsize);
if (!priv->txdesc)
{
- nllerr("ERROR: Failed to allocate TX descriptors\n");
+ nerr("ERROR: Failed to allocate TX descriptors\n");
return -ENOMEM;
}
@@ -617,7 +619,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->rxdesc = (struct emac_rxdesc_s *)kmm_memalign(8, allocsize);
if (!priv->rxdesc)
{
- nllerr("ERROR: Failed to allocate RX descriptors\n");
+ nerr("ERROR: Failed to allocate RX descriptors\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -628,7 +630,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->txbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->txbuffer)
{
- nllerr("ERROR: Failed to allocate TX buffer\n");
+ nerr("ERROR: Failed to allocate TX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -637,7 +639,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->rxbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->rxbuffer)
{
- nllerr("ERROR: Failed to allocate RX buffer\n");
+ nerr("ERROR: Failed to allocate RX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -725,14 +727,14 @@ static int sam_transmit(struct sam_emac_s *priv)
uint32_t regval;
uint32_t status;
- nllinfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
+ ninfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
/* Check parameter */
if (dev->d_len > EMAC_TX_UNITSIZE)
{
- nllerr("ERROR: Packet too big: %d\n", dev->d_len);
+ nerr("ERROR: Packet too big: %d\n", dev->d_len);
return -EINVAL;
}
@@ -744,7 +746,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
- nllerr("ERROR: No free TX descriptors\n");
+ nerr("ERROR: No free TX descriptors\n");
return -EBUSY;
}
@@ -806,7 +808,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
- nllinfo("Disabling RX interrupts\n");
+ ninfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_EMAC_IDR, EMAC_INT_RCOMP);
}
@@ -986,7 +988,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
arch_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
- nllinfo("rxndx: %d\n", rxndx);
+ ninfo("rxndx: %d\n", rxndx);
while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
{
@@ -1042,7 +1044,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
{
if (rxndx == priv->rxndx)
{
- nllinfo("ERROR: No EOF (Invalid of buffers too small)\n");
+ nerr("ERROR: No EOF (Invalid of buffers too small)\n");
do
{
/* Give ownership back to the EMAC */
@@ -1097,7 +1099,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Frame size from the EMAC */
dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
- nllinfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
+ ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor
@@ -1128,11 +1130,11 @@ static int sam_recvframe(struct sam_emac_s *priv)
* all of the data.
*/
- nllinfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
+ ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
- nllerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
+ nerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
return -E2BIG;
}
@@ -1172,7 +1174,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* No packet was found */
priv->rxndx = rxndx;
- nllinfo("rxndx: %d\n", priv->rxndx);
+ ninfo("rxndx: %d\n", priv->rxndx);
return -EAGAIN;
}
@@ -1212,7 +1214,7 @@ static void sam_receive(struct sam_emac_s *priv)
if (dev->d_len > CONFIG_NET_ETH_MTU)
{
- nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
+ nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
continue;
}
@@ -1227,7 +1229,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllinfo("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@@ -1267,7 +1269,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllinfo("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@@ -1304,7 +1306,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
- nllinfo("ARP frame\n");
+ ninfo("ARP frame\n");
/* Handle ARP packet */
@@ -1322,7 +1324,7 @@ static void sam_receive(struct sam_emac_s *priv)
else
#endif
{
- nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
+ nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
}
}
}
@@ -1449,7 +1451,7 @@ static int sam_emac_interrupt(int irq, void *context)
imr = sam_getreg(priv, SAM_EMAC_IMR);
pending = isr & ~(imr | EMAC_INT_UNUSED);
- nllinfo("isr: %08x pending: %08x\n", isr, pending);
+ ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
@@ -1475,7 +1477,7 @@ static int sam_emac_interrupt(int irq, void *context)
clrbits = EMAC_TSR_RLES | sam_txinuse(priv);
sam_txreset(priv);
- nllerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
+ nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
regval = sam_getreg(priv, SAM_EMAC_NCR);
regval |= EMAC_NCR_TE;
@@ -1486,7 +1488,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((tsr & EMAC_TSR_COL) != 0)
{
- nllerr("ERROR: Collision occurred TSR: %08x\n", tsr);
+ nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_COL;
}
@@ -1494,7 +1496,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((tsr & EMAC_TSR_BEX) != 0)
{
- nllerr("ERROR: Buffers exhausted mid-frame TSR: %08x\n", tsr);
+ nerr("ERROR: Buffers exhausted mid-frame TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_BEX;
}
@@ -1509,7 +1511,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((tsr & EMAC_TSR_UND) != 0)
{
- nllerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
+ nerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_UND;
}
@@ -1546,7 +1548,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((rsr & EMAC_RSR_OVR) != 0)
{
- nllerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
+ nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_OVR;
}
@@ -1563,7 +1565,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((rsr & EMAC_RSR_BNA) != 0)
{
- nllerr("ERROR: Buffer not available RSR: %08x\n", rsr);
+ nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_BNA;
}
@@ -1584,7 +1586,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((pending & EMAC_INT_PFR) != 0)
{
- nllwarn("WARNING: Pause frame received\n");
+ nwarn("WARNING: Pause frame received\n");
}
/* Check for Pause Time Zero (PTZ)
@@ -1594,7 +1596,7 @@ static int sam_emac_interrupt(int irq, void *context)
if ((pending & EMAC_INT_PTZ) != 0)
{
- nllwarn("WARNING: Pause TO!\n");
+ nwarn("WARNING: Pause TO!\n");
}
#endif
@@ -1624,7 +1626,7 @@ static void sam_txtimeout(int argc, uint32_t arg, ...)
{
struct sam_emac_s *priv = (struct sam_emac_s *)arg;
- nllerr("ERROR: Timeout!\n");
+ nerr("ERROR: Timeout!\n");
/* Then reset the hardware. Just take the interface down, then back
* up again.
@@ -1705,7 +1707,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Configure the EMAC interface for normal operation. */
- nllinfo("Initialize the EMAC\n");
+ ninfo("Initialize the EMAC\n");
sam_emac_configure(priv);
/* Set the MAC address (should have been configured while we were down) */
@@ -1723,7 +1725,7 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_phyinit(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_phyinit failed: %d\n", ret);
+ nerr("ERROR: sam_phyinit failed: %d\n", ret);
return ret;
}
@@ -1732,16 +1734,16 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_autonegotiate(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_autonegotiate failed: %d\n", ret);
+ nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
return ret;
}
while (sam_linkup(priv) == 0);
- nllinfo("Link detected \n");
+ ninfo("Link detected \n");
/* Enable normal MAC operation */
- nllinfo("Enable normal operation\n");
+ ninfo("Enable normal operation\n");
/* Set and activate a timer process */
@@ -1825,7 +1827,7 @@ static int sam_txavail(struct net_driver_s *dev)
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
irqstate_t flags;
- nllinfo("ifup: %d\n", priv->ifup);
+ ninfo("ifup: %d\n", priv->ifup);
/* Disable interrupts because this function may be called from interrupt
* level processing.
@@ -2003,8 +2005,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
- nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@@ -2077,8 +2079,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
- nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@@ -2273,21 +2275,21 @@ static void sam_phydump(struct sam_emac_s *priv)
sam_putreg(priv, SAM_EMAC_NCR, regval);
#ifdef CONFIG_SAMA5_EMAC_RMII
- nllinfo("RMII Registers (Address %02x)\n", priv->phyaddr);
+ ninfo("RMII Registers (Address %02x)\n", priv->phyaddr);
#else /* defined(CONFIG_SAMA5_EMAC_MII) */
- nllinfo("MII Registers (Address %02x)\n", priv->phyaddr);
+ ninfo("MII Registers (Address %02x)\n", priv->phyaddr);
#endif
sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval);
- nllinfo(" MCR: %04x\n", phyval);
+ ninfo(" MCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval);
- nllinfo(" MSR: %04x\n", phyval);
+ ninfo(" MSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval);
- nllinfo(" ADVERTISE: %04x\n", phyval);
+ ninfo(" ADVERTISE: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
- nllinfo(" LPR: %04x\n", phyval);
+ ninfo(" LPR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, CONFIG_SAMA5_EMAC_PHYSR, &phyval);
- nllinfo(" PHYSR: %04x\n", phyval);
+ ninfo(" PHYSR: %04x\n", phyval);
/* Disable management port */
@@ -2410,7 +2412,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int timeout;
int ret;
- nllinfo(" sam_phyreset\n");
+ ninfo(" sam_phyreset\n");
/* Enable management port */
@@ -2423,7 +2425,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, MII_MCR_RESET);
if (ret < 0)
{
- nllerr("ERROR: sam_phywrite failed: %d\n", ret);
+ nerr("ERROR: sam_phywrite failed: %d\n", ret);
}
/* Wait for the PHY reset to complete */
@@ -2435,7 +2437,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int result = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (result < 0)
{
- nllerr("ERROR: Failed to read the MCR register: %d\n", ret);
+ nerr("ERROR: Failed to read the MCR register: %d\n", ret);
ret = result;
}
else if ((mcr & MII_MCR_RESET) == 0)
@@ -2477,7 +2479,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
unsigned int offset;
int ret = -ESRCH;
- nllinfo("Find a valid PHY address\n");
+ ninfo("Find a valid PHY address\n");
/* Enable management port */
@@ -2500,8 +2502,8 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
else
{
- nllerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
- candidate, ret);
+ nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
+ candidate, ret);
for (offset = 0; offset < 32; offset++)
{
@@ -2522,10 +2524,10 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
if (ret == OK)
{
- nllinfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
+ ninfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
*phyaddr = candidate;
sam_phyread(priv, candidate, CONFIG_SAMA5_EMAC_PHYSR, &phyval);
- nllinfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
+ ninfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
}
/* Disable management port */
@@ -2566,7 +2568,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2581,7 +2583,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2621,7 +2623,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2636,7 +2638,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2680,32 +2682,32 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID1, &phyid1);
if (ret < 0)
{
- nllerr("ERROR: Failed to read PHYID1\n");
+ nerr("ERROR: Failed to read PHYID1\n");
goto errout;
}
- nllinfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
+ ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2);
if (ret < 0)
{
- nllerr("ERROR: Failed to read PHYID2\n");
+ nerr("ERROR: Failed to read PHYID2\n");
goto errout;
}
- nllinfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
+ ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == MII_OUI_MSB &&
((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) == MII_OUI_LSB)
{
- nllinfo(" Vendor Model Number: %04x\n",
- (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
- nllinfo(" Model Revision Number: %04x\n",
- (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
+ ninfo(" Vendor Model Number: %04x\n",
+ (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
+ ninfo(" Model Revision Number: %04x\n",
+ (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
}
else
{
- nllerr("ERROR: PHY not recognized\n");
+ nerr("ERROR: PHY not recognized\n");
}
/* Setup control register */
@@ -2713,7 +2715,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
- nllerr("ERROR: Failed to read MCR\n");
+ nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@@ -2724,7 +2726,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nllerr("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@@ -2739,7 +2741,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_ADVERTISE, advertise);
if (ret < 0)
{
- nllerr("ERROR: Failed to write ANAR\n");
+ nerr("ERROR: Failed to write ANAR\n");
goto errout;
}
@@ -2748,7 +2750,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
- nllerr("ERROR: Failed to read MCR\n");
+ nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@@ -2756,7 +2758,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nllerr("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@@ -2768,11 +2770,11 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nllerr("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
- nllinfo(" MCR: %04x\n", mcr);
+ ninfo(" MCR: %04x\n", mcr);
/* Check AutoNegotiate complete */
@@ -2782,7 +2784,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
- nllerr("ERROR: Failed to read MSR\n");
+ nerr("ERROR: Failed to read MSR\n");
goto errout;
}
@@ -2792,7 +2794,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
{
/* Yes.. break out of the loop */
- nllinfo("AutoNegotiate complete\n");
+ ninfo("AutoNegotiate complete\n");
break;
}
@@ -2800,7 +2802,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
if (++timeout >= PHY_RETRY_MAX)
{
- nllerr("ERROR: TimeOut\n");
+ nerr("ERROR: TimeOut\n");
sam_phydump(priv);
ret = -ETIMEDOUT;
goto errout;
@@ -2812,7 +2814,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_LPA, &lpa);
if (ret < 0)
{
- nllerr("ERROR: Failed to read ANLPAR\n");
+ nerr("ERROR: Failed to read ANLPAR\n");
goto errout;
}
@@ -2902,13 +2904,13 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
- nllerr("ERROR: Failed to read MSR: %d\n", ret);
+ nerr("ERROR: Failed to read MSR: %d\n", ret);
goto errout;
}
if ((msr & MII_MSR_LINKSTATUS) == 0)
{
- nllerr("ERROR: MSR LinkStatus: %04x\n", msr);
+ nerr("ERROR: MSR LinkStatus: %04x\n", msr);
goto errout;
}
@@ -2917,7 +2919,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, CONFIG_SAMA5_EMAC_PHYSR, &physr);
if (ret < 0)
{
- nllerr("ERROR: Failed to read PHYSR: %d\n", ret);
+ nerr("ERROR: Failed to read PHYSR: %d\n", ret);
goto errout;
}
@@ -2955,7 +2957,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
/* Start the EMAC transfers */
- nllinfo("Link is up\n");
+ ninfo("Link is up\n");
linkup = true;
errout:
@@ -3024,7 +3026,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
ret = sam_phyfind(priv, &priv->phyaddr);
if (ret < 0)
{
- nllerr("ERROR: sam_phyfind failed: %d\n", ret);
+ nerr("ERROR: sam_phyfind failed: %d\n", ret);
return ret;
}
@@ -3276,11 +3278,11 @@ static void sam_macaddress(struct sam_emac_s *priv)
struct net_driver_s *dev = &priv->dev;
uint32_t regval;
- nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- dev->d_ifname,
- dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
- dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
- dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+ ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ dev->d_ifname,
+ dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+ dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+ dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
/* Set the MAC address */
@@ -3388,7 +3390,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
{
uint32_t regval;
- nllinfo("Entry\n");
+ ninfo("Entry\n");
/* Enable clocking to the EMAC peripheral */
@@ -3484,6 +3486,9 @@ int sam_emac_initialize(void)
/* Initialize the driver structure */
memset(priv, 0, sizeof(struct sam_emac_s));
+#ifdef CONFIG_NET_MULTIBUFFER
+ priv->dev.d_buf = g_pktbuf; /* Single packet buffer */
+#endif
priv->dev.d_ifup = sam_ifup; /* I/F up (new IP address) callback */
priv->dev.d_ifdown = sam_ifdown; /* I/F down callback */
priv->dev.d_txavail = sam_txavail; /* New TX data callback */
diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c
index 6dab62599f48fcfbc4a9c535843df91992d39e14..ba118484e1f9c199c5c215c4279a579ec51117e1 100644
--- a/arch/arm/src/sama5/sam_emacb.c
+++ b/arch/arm/src/sama5/sam_emacb.c
@@ -305,18 +305,7 @@
# define sam_dumppacket(m,a,n)
#endif
-/* EMAC buffer sizes, number of buffers, and number of descriptors **********
- *
- * REVISIT: The CONFIG_NET_MULTIBUFFER might be useful. It might be possible
- * to use this option to send and receive messages directly into the DMA
- * buffers, saving a copy. There might be complications on the receiving
- * side, however, where buffers may wrap and where the size of the received
- * frame will typically be smaller than a full packet.
- */
-
-#ifdef CONFIG_NET_MULTIBUFFER
-# error CONFIG_NET_MULTIBUFFER must not be set
-#endif
+/* EMAC buffer sizes, number of buffers, and number of descriptors **********/
#define EMAC_RX_UNITSIZE 128 /* Fixed size for RX buffer */
#define EMAC_TX_UNITSIZE CONFIG_NET_ETH_MTU /* MAX size for Ethernet packet */
@@ -709,6 +698,21 @@ static const struct sam_emacattr_s g_emac0_attr =
#endif
};
+#ifdef CONFIG_NET_MULTIBUFFER
+/* A single packet buffer is used
+ *
+ * REVISIT: It might be possible to use this option to send and receive
+ * messages directly into the DMA buffers, saving a copy. There might be
+ * complications on the receiving side, however, where buffers may wrap
+ * and where the size of the received frame will typically be smaller than
+ * a full packet.
+ */
+
+static uint8_t g_pktbuf0[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE];
+#endif
+
+/* EMAC0 peripheral state */
+
static struct sam_emac_s g_emac0;
#endif
@@ -777,6 +781,21 @@ static const struct sam_emacattr_s g_emac1_attr =
#endif
};
+#ifdef CONFIG_NET_MULTIBUFFER
+/* A single packet buffer is used
+ *
+ * REVISIT: It might be possible to use this option to send and receive
+ * messages directly into the DMA buffers, saving a copy. There might be
+ * complications on the receiving side, however, where buffers may wrap
+ * and where the size of the received frame will typically be smaller than
+ * a full packet.
+ */
+
+static uint8_t g_pktbuf1[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE];
+#endif
+
+/* EMAC1 peripheral state */
+
static struct sam_emac_s g_emac1;
#endif
@@ -970,7 +989,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->txdesc = (struct emac_txdesc_s *)kmm_memalign(8, allocsize);
if (!priv->txdesc)
{
- nllerr("ERROR: Failed to allocate TX descriptors\n");
+ nerr("ERROR: Failed to allocate TX descriptors\n");
return -ENOMEM;
}
@@ -980,7 +999,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->rxdesc = (struct emac_rxdesc_s *)kmm_memalign(8, allocsize);
if (!priv->rxdesc)
{
- nllerr("ERROR: Failed to allocate RX descriptors\n");
+ nerr("ERROR: Failed to allocate RX descriptors\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -991,7 +1010,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->txbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->txbuffer)
{
- nllerr("ERROR: Failed to allocate TX buffer\n");
+ nerr("ERROR: Failed to allocate TX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -1000,7 +1019,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv)
priv->rxbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->rxbuffer)
{
- nllerr("ERROR: Failed to allocate RX buffer\n");
+ nerr("ERROR: Failed to allocate RX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -1088,14 +1107,14 @@ static int sam_transmit(struct sam_emac_s *priv)
uint32_t regval;
uint32_t status;
- nllinfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
+ ninfo("d_len: %d txhead: %d\n", dev->d_len, priv->txhead);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
/* Check parameter */
if (dev->d_len > EMAC_TX_UNITSIZE)
{
- nllerr("ERROR: Packet too big: %d\n", dev->d_len);
+ nerr("ERROR: Packet too big: %d\n", dev->d_len);
return -EINVAL;
}
@@ -1107,7 +1126,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
- nllerr("ERROR: No free TX descriptors\n");
+ nerr("ERROR: No free TX descriptors\n");
return -EBUSY;
}
@@ -1169,7 +1188,7 @@ static int sam_transmit(struct sam_emac_s *priv)
if (sam_txfree(priv) < 1)
{
- nllinfo("Disabling RX interrupts\n");
+ ninfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_EMAC_IDR_OFFSET, EMAC_INT_RCOMP);
}
@@ -1349,7 +1368,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
arch_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
- nllinfo("rxndx: %d\n", rxndx);
+ ninfo("rxndx: %d\n", rxndx);
while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
{
@@ -1405,7 +1424,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
{
if (rxndx == priv->rxndx)
{
- nllinfo("ERROR: No EOF (Invalid of buffers too small)\n");
+ nerr("ERROR: No EOF (Invalid of buffers too small)\n");
do
{
/* Give ownership back to the EMAC */
@@ -1460,7 +1479,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Frame size from the EMAC */
dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
- nllinfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
+ ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor
@@ -1491,11 +1510,11 @@ static int sam_recvframe(struct sam_emac_s *priv)
* all of the data.
*/
- nllinfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
+ ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
- nllerr("ERROR: Buffer size %d; frame size %d\n",
- dev->d_len, pktlen);
+ nerr("ERROR: Buffer size %d; frame size %d\n",
+ dev->d_len, pktlen);
return -E2BIG;
}
@@ -1535,7 +1554,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* No packet was found */
priv->rxndx = rxndx;
- nllinfo("rxndx: %d\n", priv->rxndx);
+ ninfo("rxndx: %d\n", priv->rxndx);
return -EAGAIN;
}
@@ -1575,7 +1594,7 @@ static void sam_receive(struct sam_emac_s *priv)
if (dev->d_len > CONFIG_NET_ETH_MTU)
{
- nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
+ nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
continue;
}
@@ -1590,7 +1609,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllinfo("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@@ -1630,7 +1649,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllinfo("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@@ -1667,7 +1686,7 @@ static void sam_receive(struct sam_emac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
- nllinfo("ARP frame\n");
+ ninfo("ARP frame\n");
/* Handle ARP packet */
@@ -1685,7 +1704,7 @@ static void sam_receive(struct sam_emac_s *priv)
else
#endif
{
- nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
+ nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
}
}
}
@@ -1836,7 +1855,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
imr = sam_getreg(priv, SAM_EMAC_IMR_OFFSET);
pending = isr & ~(imr | EMAC_INT_UNUSED);
- nllinfo("isr: %08x pending: %08x\n", isr, pending);
+ ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
@@ -1862,7 +1881,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
clrbits = EMAC_TSR_RLE | sam_txinuse(priv);
sam_txreset(priv);
- nllerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
+ nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
regval |= EMAC_NCR_TXEN;
@@ -1873,7 +1892,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((tsr & EMAC_TSR_COL) != 0)
{
- nllerr("ERROR: Collision occurred TSR: %08x\n", tsr);
+ nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_COL;
}
@@ -1881,7 +1900,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((tsr & EMAC_TSR_TFC) != 0)
{
- nllerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
+ nerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", tsr);
clrbits |= EMAC_TSR_TFC;
}
@@ -1896,7 +1915,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((tsr & EMAC_TSR_UND) != 0)
{
- nllerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
+ nerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
clrbits |= EMAC_TSR_UND;
}
@@ -1933,7 +1952,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((rsr & EMAC_RSR_RXOVR) != 0)
{
- nllerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
+ nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_RXOVR;
}
@@ -1950,7 +1969,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((rsr & EMAC_RSR_BNA) != 0)
{
- nllerr("ERROR: Buffer not available RSR: %08x\n", rsr);
+ nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
clrbits |= EMAC_RSR_BNA;
}
@@ -1972,7 +1991,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((pending & EMAC_INT_PFNZ) != 0)
{
- nllwarn("WARNING: Pause frame received\n");
+ nwarn("WARNING: Pause frame received\n");
}
/* Check for Pause Time Zero (PTZ)
@@ -1982,7 +2001,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv)
if ((pending & EMAC_INT_PTZ) != 0)
{
- nllwarn("WARNING: Pause TO!\n");
+ nwarn("WARNING: Pause TO!\n");
}
#endif
}
@@ -2147,7 +2166,7 @@ static int sam_emac1_interrupt(int irq, void *context)
static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv)
{
- nllerr("ERROR: Timeout!\n");
+ nerr("ERROR: Timeout!\n");
/* Reset the hardware. Just take the interface down, then back up again. */
@@ -2390,7 +2409,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Configure the EMAC interface for normal operation. */
- nllinfo("Initialize the EMAC\n");
+ ninfo("Initialize the EMAC\n");
sam_emac_configure(priv);
/* Set the MAC address (should have been configured while we were down) */
@@ -2408,7 +2427,7 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_phyinit(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_phyinit failed: %d\n", ret);
+ nerr("ERROR: sam_phyinit failed: %d\n", ret);
return ret;
}
@@ -2417,16 +2436,16 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_autonegotiate(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_autonegotiate failed: %d\n", ret);
+ nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
return ret;
}
while (sam_linkup(priv) == 0);
- nllinfo("Link detected \n");
+ ninfo("Link detected \n");
/* Enable normal MAC operation */
- nllinfo("Enable normal operation\n");
+ ninfo("Enable normal operation\n");
/* Set and activate a timer process */
@@ -2460,7 +2479,7 @@ static int sam_ifdown(struct net_driver_s *dev)
struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private;
irqstate_t flags;
- nllinfo("Taking the network down\n");
+ ninfo("Taking the network down\n");
/* Disable the EMAC interrupt */
@@ -2505,7 +2524,7 @@ static int sam_ifdown(struct net_driver_s *dev)
static inline void sam_txavail_process(FAR struct sam_emac_s *priv)
{
- nllinfo("ifup: %d\n", priv->ifup);
+ ninfo("ifup: %d\n", priv->ifup);
/* Ignore the notification if the interface is not yet up */
@@ -2758,8 +2777,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int ndx;
unsigned int bit;
- nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@@ -2831,8 +2850,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int ndx;
unsigned int bit;
- nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@@ -3026,19 +3045,19 @@ static void sam_phydump(struct sam_emac_s *priv)
regval |= EMAC_NCR_MPE;
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
- nllinfo("%s Registers (Address %02x)\n",
- priv->attr->rmii ? "RMII" : "MII", priv->phyaddr);
+ ninfo("%s Registers (Address %02x)\n",
+ priv->attr->rmii ? "RMII" : "MII", priv->phyaddr);
sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval);
- nllinfo(" MCR: %04x\n", phyval);
+ ninfo(" MCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval);
- nllinfo(" MSR: %04x\n", phyval);
+ ninfo(" MSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval);
- nllinfo(" ADVERTISE: %04x\n", phyval);
+ ninfo(" ADVERTISE: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval);
- nllinfo(" LPR: %04x\n", phyval);
+ ninfo(" LPR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, priv->attr->physr, &phyval);
- nllinfo(" PHYSR: %04x\n", phyval);
+ ninfo(" PHYSR: %04x\n", phyval);
/* Disable management port */
@@ -3262,7 +3281,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int timeout;
int ret;
- nllinfo(" sam_phyreset\n");
+ ninfo(" sam_phyreset\n");
/* Enable management port */
@@ -3275,7 +3294,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, MII_MCR_RESET);
if (ret < 0)
{
- nllerr("ERROR: sam_phywrite failed: %d\n", ret);
+ nerr("ERROR: sam_phywrite failed: %d\n", ret);
}
/* Wait for the PHY reset to complete */
@@ -3287,7 +3306,7 @@ static int sam_phyreset(struct sam_emac_s *priv)
int result = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (result < 0)
{
- nllerr("ERROR: Failed to read the MCR register: %d\n", ret);
+ nerr("ERROR: Failed to read the MCR register: %d\n", ret);
ret = result;
}
else if ((mcr & MII_MCR_RESET) == 0)
@@ -3329,7 +3348,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
unsigned int offset;
int ret = -ESRCH;
- nllinfo("Find a valid PHY address\n");
+ ninfo("Find a valid PHY address\n");
/* Enable management port */
@@ -3352,8 +3371,8 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
else
{
- nllerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
- candidate, ret);
+ nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
+ candidate, ret);
for (offset = 0; offset < 32; offset++)
{
@@ -3374,10 +3393,10 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
if (ret == OK)
{
- nllinfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
+ ninfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
*phyaddr = candidate;
sam_phyread(priv, candidate, priv->attr->physr, &phyval);
- nllinfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
+ ninfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate);
}
/* Disable management port */
@@ -3418,7 +3437,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -3443,7 +3462,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -3483,7 +3502,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -3508,7 +3527,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -3552,33 +3571,33 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID1, &phyid1);
if (ret < 0)
{
- nllerr("ERROR: Failed to read PHYID1\n");
+ nerr("ERROR: Failed to read PHYID1\n");
goto errout;
}
- nllinfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
+ ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2);
if (ret < 0)
{
- nllerr("ERROR: Failed to read PHYID2\n");
+ nerr("ERROR: Failed to read PHYID2\n");
goto errout;
}
- nllinfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
+ ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == priv->attr->msoui &&
((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) ==
(uint16_t)priv->attr->lsoui)
{
- nllinfo(" Vendor Model Number: %04x\n",
- (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
- nllinfo(" Model Revision Number: %04x\n",
- (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
+ ninfo(" Vendor Model Number: %04x\n",
+ (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
+ ninfo(" Model Revision Number: %04x\n",
+ (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
}
else
{
- nllerr("ERROR: PHY not recognized\n");
+ nerr("ERROR: PHY not recognized\n");
}
/* Setup control register */
@@ -3586,7 +3605,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
- nllerr("ERROR: Failed to read MCR\n");
+ nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@@ -3597,7 +3616,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nllerr("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@@ -3612,7 +3631,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_ADVERTISE, advertise);
if (ret < 0)
{
- nllerr("ERROR: Failed to write ANAR\n");
+ nerr("ERROR: Failed to write ANAR\n");
goto errout;
}
@@ -3621,7 +3640,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr);
if (ret < 0)
{
- nllerr("ERROR: Failed to read MCR\n");
+ nerr("ERROR: Failed to read MCR\n");
goto errout;
}
@@ -3629,7 +3648,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nllerr("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
@@ -3641,11 +3660,11 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr);
if (ret < 0)
{
- nllerr("ERROR: Failed to write MCR\n");
+ nerr("ERROR: Failed to write MCR\n");
goto errout;
}
- nllinfo(" MCR: %04x\n", mcr);
+ ninfo(" MCR: %04x\n", mcr);
/* Check AutoNegotiate complete */
@@ -3655,7 +3674,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
- nllerr("ERROR: Failed to read MSR\n");
+ nerr("ERROR: Failed to read MSR\n");
goto errout;
}
@@ -3665,7 +3684,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
{
/* Yes.. break out of the loop */
- nllinfo("AutoNegotiate complete\n");
+ ninfo("AutoNegotiate complete\n");
break;
}
@@ -3673,7 +3692,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
if (++timeout >= PHY_RETRY_MAX)
{
- nllerr("ERROR: TimeOut\n");
+ nerr("ERROR: TimeOut\n");
sam_phydump(priv);
ret = -ETIMEDOUT;
goto errout;
@@ -3685,7 +3704,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_LPA, &lpa);
if (ret < 0)
{
- nllerr("ERROR: Failed to read ANLPAR\n");
+ nerr("ERROR: Failed to read ANLPAR\n");
goto errout;
}
@@ -3775,13 +3794,13 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr);
if (ret < 0)
{
- nllerr("ERROR: Failed to read MSR: %d\n", ret);
+ nerr("ERROR: Failed to read MSR: %d\n", ret);
goto errout;
}
if ((msr & MII_MSR_LINKSTATUS) == 0)
{
- nllerr("ERROR: MSR LinkStatus: %04x\n", msr);
+ nerr("ERROR: MSR LinkStatus: %04x\n", msr);
goto errout;
}
@@ -3790,7 +3809,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, priv->attr->physr, &physr);
if (ret < 0)
{
- nllerr("ERROR: Failed to read PHYSR: %d\n", ret);
+ nerr("ERROR: Failed to read PHYSR: %d\n", ret);
goto errout;
}
@@ -3828,7 +3847,7 @@ static bool sam_linkup(struct sam_emac_s *priv)
/* Start the EMAC transfers */
- nllinfo("Link is up\n");
+ ninfo("Link is up\n");
linkup = true;
errout:
@@ -3897,7 +3916,7 @@ static int sam_phyinit(struct sam_emac_s *priv)
ret = sam_phyfind(priv, &priv->phyaddr);
if (ret < 0)
{
- nllerr("ERROR: sam_phyfind failed: %d\n", ret);
+ nerr("ERROR: sam_phyfind failed: %d\n", ret);
return ret;
}
@@ -4012,7 +4031,7 @@ static inline void sam_ethgpioconfig(struct sam_emac_s *priv)
else
#endif
{
- ninfo("ERROR: emac=%d\n", priv->attr->emac);
+ nerr("ERROR: emac=%d\n", priv->attr->emac);
}
}
@@ -4311,11 +4330,11 @@ static void sam_macaddress(struct sam_emac_s *priv)
struct net_driver_s *dev = &priv->dev;
uint32_t regval;
- nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- dev->d_ifname,
- dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
- dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
- dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+ ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ dev->d_ifname,
+ dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+ dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+ dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
/* Set the MAC address */
@@ -4423,7 +4442,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
{
uint32_t regval;
- nllinfo("Entry\n");
+ ninfo("Entry\n");
/* Enable clocking to the EMAC peripheral */
@@ -4515,6 +4534,9 @@ int sam_emac_initialize(int intf)
{
struct sam_emac_s *priv;
const struct sam_emacattr_s *attr;
+#ifdef CONFIG_NET_MULTIBUFFER
+ uint8_t *pktbuf;
+#endif
#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
uint8_t phytype;
#endif
@@ -4526,6 +4548,10 @@ int sam_emac_initialize(int intf)
priv = &g_emac0;
attr = &g_emac0_attr;
+#ifdef CONFIG_NET_MULTIBUFFER
+ pktbuf = g_pktbuf0;
+#endif
+
#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
phytype = SAMA5_EMAC0_PHY_TYPE;
#endif
@@ -4538,6 +4564,10 @@ int sam_emac_initialize(int intf)
priv = &g_emac1;
attr = &g_emac1_attr;
+#ifdef CONFIG_NET_MULTIBUFFER
+ pktbuf = g_pktbuf1;
+#endif
+
#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
phytype = SAMA5_EMAC1_PHY_TYPE;
#endif
@@ -4553,6 +4583,9 @@ int sam_emac_initialize(int intf)
memset(priv, 0, sizeof(struct sam_emac_s));
priv->attr = attr; /* Save the constant attributes */
+#ifdef CONFIG_NET_MULTIBUFFER
+ priv->dev.d_buf = pktbuf; /* Single packet buffer */
+#endif
priv->dev.d_ifup = sam_ifup; /* I/F up (new IP address) callback */
priv->dev.d_ifdown = sam_ifdown; /* I/F down callback */
priv->dev.d_txavail = sam_txavail; /* New TX data callback */
diff --git a/arch/arm/src/sama5/sam_ethernet.c b/arch/arm/src/sama5/sam_ethernet.c
index d10f096d2944daf5a8dae55967187ae029fb336c..206af9fc6724e29217516bb54d12c4d3ce0a0f73 100644
--- a/arch/arm/src/sama5/sam_ethernet.c
+++ b/arch/arm/src/sama5/sam_ethernet.c
@@ -88,7 +88,7 @@ static inline void up_gmac_initialize(void)
ret = sam_gmac_initialize();
if (ret < 0)
{
- nllerr("ERROR: sam_gmac_initialize failed: %d\n", ret);
+ nerr("ERROR: sam_gmac_initialize failed: %d\n", ret);
}
}
#else
@@ -119,7 +119,7 @@ static inline void up_emac_initialize(void)
ret = sam_emac_initialize();
if (ret < 0)
{
- nllerr("ERROR: up_emac_initialize failed: %d\n", ret);
+ nerr("ERROR: up_emac_initialize failed: %d\n", ret);
}
}
#elif defined(CONFIG_SAMA5_EMACB)
@@ -133,7 +133,7 @@ static inline void up_emac_initialize(void)
ret = sam_emac_initialize(EMAC0_INTF);
if (ret < 0)
{
- nllerr("ERROR: up_emac_initialize(EMAC0) failed: %d\n", ret);
+ nerr("ERROR: up_emac_initialize(EMAC0) failed: %d\n", ret);
}
#endif
@@ -143,7 +143,7 @@ static inline void up_emac_initialize(void)
ret = sam_emac_initialize(EMAC1_INTF);
if (ret < 0)
{
- nllerr("ERROR: up_emac_initialize(EMAC1) failed: %d\n", ret);
+ nerr("ERROR: up_emac_initialize(EMAC1) failed: %d\n", ret);
}
#endif
}
diff --git a/arch/arm/src/sama5/sam_freerun.c b/arch/arm/src/sama5/sam_freerun.c
index 8870988ce608e5d6997378a99ba7e71e06253761..088cb10a6e82a5e9ad02d84edbbf0b2b107f5508 100644
--- a/arch/arm/src/sama5/sam_freerun.c
+++ b/arch/arm/src/sama5/sam_freerun.c
@@ -60,27 +60,12 @@
#include "sam_freerun.h"
-#ifdef CONFIG_SAMA5_ONESHOT
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
+#ifdef CONFIG_SAMA5_FREERUN
/****************************************************************************
* Private Functions
****************************************************************************/
+
/****************************************************************************
* Name: sam_freerun_handler
*
@@ -333,4 +318,4 @@ int sam_freerun_uninitialize(struct sam_freerun_s *freerun)
return OK;
}
-#endif /* CONFIG_SAMA5_ONESHOT */
+#endif /* CONFIG_SAMA5_FREERUN */
diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c
index 66472d368358bbe818584e55dd1617a19cb68f6d..5442920ee03b31be62ea23bba9a36f9197194215 100644
--- a/arch/arm/src/sama5/sam_gmac.c
+++ b/arch/arm/src/sama5/sam_gmac.c
@@ -118,18 +118,7 @@
# error Unknown PHY
#endif
-/* GMAC buffer sizes, number of buffers, and number of descriptors.
- *
- * REVISIT: The CONFIG_NET_MULTIBUFFER might be useful. It might be possible
- * to use this option to send and receive messages directly into the DMA
- * buffers, saving a copy. There might be complications on the receiving
- * side, however, where buffers may wrap and where the size of the received
- * frame will typically be smaller than a full packet.
- */
-
-#ifdef CONFIG_NET_MULTIBUFFER
-# error CONFIG_NET_MULTIBUFFER must not be set
-#endif
+/* GMAC buffer sizes, number of buffers, and number of descriptors. *********/
#define GMAC_RX_UNITSIZE 128 /* Fixed size for RX buffer */
#define GMAC_TX_UNITSIZE CONFIG_NET_ETH_MTU /* MAX size for Ethernet packet */
@@ -227,6 +216,19 @@ struct sam_gmac_s
static struct sam_gmac_s g_gmac;
+#ifdef CONFIG_NET_MULTIBUFFER
+/* A single packet buffer is used
+ *
+ * REVISIT: It might be possible to use this option to send and receive
+ * messages directly into the DMA buffers, saving a copy. There might be
+ * complications on the receiving side, however, where buffers may wrap
+ * and where the size of the received frame will typically be smaller than
+ * a full packet.
+ */
+
+static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE];
+#endif
+
#ifdef CONFIG_SAMA5_GMAC_PREALLOCATE
/* Preallocated data */
/* TX descriptors list */
@@ -538,7 +540,7 @@ static int sam_buffer_initialize(struct sam_gmac_s *priv)
priv->txdesc = (struct gmac_txdesc_s *)kmm_memalign(8, allocsize);
if (!priv->txdesc)
{
- nllerr("ERROR: Failed to allocate TX descriptors\n");
+ nerr("ERROR: Failed to allocate TX descriptors\n");
return -ENOMEM;
}
@@ -548,7 +550,7 @@ static int sam_buffer_initialize(struct sam_gmac_s *priv)
priv->rxdesc = (struct gmac_rxdesc_s *)kmm_memalign(8, allocsize);
if (!priv->rxdesc)
{
- nllerr("ERROR: Failed to allocate RX descriptors\n");
+ nerr("ERROR: Failed to allocate RX descriptors\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -559,7 +561,7 @@ static int sam_buffer_initialize(struct sam_gmac_s *priv)
priv->txbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->txbuffer)
{
- nllerr("ERROR: Failed to allocate TX buffer\n");
+ nerr("ERROR: Failed to allocate TX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -568,7 +570,7 @@ static int sam_buffer_initialize(struct sam_gmac_s *priv)
priv->rxbuffer = (uint8_t *)kmm_memalign(8, allocsize);
if (!priv->rxbuffer)
{
- nllerr("ERROR: Failed to allocate RX buffer\n");
+ nerr("ERROR: Failed to allocate RX buffer\n");
sam_buffer_free(priv);
return -ENOMEM;
}
@@ -656,15 +658,15 @@ static int sam_transmit(struct sam_gmac_s *priv)
uint32_t regval;
uint32_t status;
- nllinfo("d_len: %d txhead: %d txtail: %d\n",
- dev->d_len, priv->txhead, priv->txtail);
+ ninfo("d_len: %d txhead: %d txtail: %d\n",
+ dev->d_len, priv->txhead, priv->txtail);
sam_dumppacket("Transmit packet", dev->d_buf, dev->d_len);
/* Check parameter */
if (dev->d_len > GMAC_TX_UNITSIZE)
{
- nllerr("ERROR: Packet too big: %d\n", dev->d_len);
+ nerr("ERROR: Packet too big: %d\n", dev->d_len);
return -EINVAL;
}
@@ -676,7 +678,7 @@ static int sam_transmit(struct sam_gmac_s *priv)
if (sam_txfree(priv) < 1)
{
- nllerr("ERROR: No free TX descriptors\n");
+ nerr("ERROR: No free TX descriptors\n");
return -EBUSY;
}
@@ -738,7 +740,7 @@ static int sam_transmit(struct sam_gmac_s *priv)
if (sam_txfree(priv) < 1)
{
- nllinfo("Disabling RX interrupts\n");
+ ninfo("Disabling RX interrupts\n");
sam_putreg(priv, SAM_GMAC_IDR, GMAC_INT_RCOMP);
}
@@ -918,7 +920,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
arch_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct gmac_rxdesc_s));
- nllinfo("rxndx: %d\n", rxndx);
+ ninfo("rxndx: %d\n", rxndx);
while ((rxdesc->addr & GMACRXD_ADDR_OWNER) != 0)
{
@@ -974,7 +976,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
{
if (rxndx == priv->rxndx)
{
- nllinfo("ERROR: No EOF (Invalid of buffers too small)\n");
+ nerr("ERROR: No EOF (Invalid of buffers too small)\n");
do
{
/* Give ownership back to the GMAC */
@@ -1029,7 +1031,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
/* Frame size from the GMAC */
dev->d_len = (rxdesc->status & GMACRXD_STA_FRLEN_MASK);
- nllinfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
+ ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer,
* release the RX descriptor
@@ -1060,11 +1062,11 @@ static int sam_recvframe(struct sam_gmac_s *priv)
* all of the data.
*/
- nllinfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
+ ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len)
{
- nllerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
+ nerr("ERROR: Buffer size %d; frame size %d\n", dev->d_len, pktlen);
return -E2BIG;
}
@@ -1102,7 +1104,7 @@ static int sam_recvframe(struct sam_gmac_s *priv)
/* No packet was found */
priv->rxndx = rxndx;
- nllinfo("rxndx: %d\n", priv->rxndx);
+ ninfo("rxndx: %d\n", priv->rxndx);
return -EAGAIN;
}
@@ -1142,7 +1144,7 @@ static void sam_receive(struct sam_gmac_s *priv)
if (dev->d_len > CONFIG_NET_ETH_MTU)
{
- nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
+ nwarn("WARNING: Dropped, Too big: %d\n", dev->d_len);
continue;
}
@@ -1157,7 +1159,7 @@ static void sam_receive(struct sam_gmac_s *priv)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllinfo("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@@ -1197,7 +1199,7 @@ static void sam_receive(struct sam_gmac_s *priv)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllinfo("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@@ -1234,7 +1236,7 @@ static void sam_receive(struct sam_gmac_s *priv)
#ifdef CONFIG_NET_ARP
if (BUF->type == htons(ETHTYPE_ARP))
{
- nllinfo("ARP frame\n");
+ ninfo("ARP frame\n");
/* Handle ARP packet */
@@ -1252,7 +1254,7 @@ static void sam_receive(struct sam_gmac_s *priv)
else
#endif
{
- nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
+ nwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type);
}
}
}
@@ -1377,7 +1379,7 @@ static int sam_gmac_interrupt(int irq, void *context)
imr = sam_getreg(priv, SAM_GMAC_IMR);
pending = isr & ~(imr | GMAC_INT_UNUSED);
- nllinfo("isr: %08x pending: %08x\n", isr, pending);
+ ninfo("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another transmission
@@ -1403,7 +1405,7 @@ static int sam_gmac_interrupt(int irq, void *context)
clrbits = GMAC_TSR_RLE | sam_txinuse(priv);
sam_txreset(priv);
- nllerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
+ nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr);
regval = sam_getreg(priv, SAM_GMAC_NCR);
regval |= GMAC_NCR_TXEN;
@@ -1414,7 +1416,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((tsr & GMAC_TSR_COL) != 0)
{
- nllerr("ERROR: Collision occurred TSR: %08x\n", tsr);
+ nerr("ERROR: Collision occurred TSR: %08x\n", tsr);
clrbits |= GMAC_TSR_COL;
}
@@ -1422,7 +1424,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((tsr & GMAC_TSR_TFC) != 0)
{
- nllerr("ERROR: Buffers exhausted mid-frame TSR: %08x\n", tsr);
+ nerr("ERROR: Buffers exhausted mid-frame TSR: %08x\n", tsr);
clrbits |= GMAC_TSR_TFC;
}
@@ -1437,7 +1439,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((tsr & GMAC_TSR_UND) != 0)
{
- nllerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
+ nerr("ERROR: Transmit Underrun TSR: %08x\n", tsr);
clrbits |= GMAC_TSR_UND;
}
@@ -1445,7 +1447,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((tsr & GMAC_TSR_HRESP) != 0)
{
- nllerr("ERROR: HRESP not OK: %08x\n", tsr);
+ nerr("ERROR: HRESP not OK: %08x\n", tsr);
clrbits |= GMAC_TSR_HRESP;
}
@@ -1453,7 +1455,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((tsr & GMAC_TSR_LCO) != 0)
{
- nllerr("ERROR: Late collision: %08x\n", tsr);
+ nerr("ERROR: Late collision: %08x\n", tsr);
clrbits |= GMAC_TSR_LCO;
}
@@ -1490,7 +1492,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((rsr & GMAC_RSR_RXOVR) != 0)
{
- nllerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
+ nerr("ERROR: Receiver overrun RSR: %08x\n", rsr);
clrbits |= GMAC_RSR_RXOVR;
}
@@ -1507,7 +1509,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((rsr & GMAC_RSR_BNA) != 0)
{
- nllerr("ERROR: Buffer not available RSR: %08x\n", rsr);
+ nerr("ERROR: Buffer not available RSR: %08x\n", rsr);
clrbits |= GMAC_RSR_BNA;
}
@@ -1515,7 +1517,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((rsr & GMAC_RSR_HNO) != 0)
{
- nllerr("ERROR: HRESP not OK: %08x\n", rsr);
+ nerr("ERROR: HRESP not OK: %08x\n", rsr);
clrbits |= GMAC_RSR_HNO;
}
@@ -1536,7 +1538,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((pending & GMAC_INT_PFNZ) != 0)
{
- nllwarn("WARNING: Pause frame received\n");
+ nwarn("WARNING: Pause frame received\n");
}
/* Check for Pause Time Zero (PTZ)
@@ -1546,7 +1548,7 @@ static int sam_gmac_interrupt(int irq, void *context)
if ((pending & GMAC_INT_PTZ) != 0)
{
- nllwarn("WARNING: Pause TO!\n");
+ nwarn("WARNING: Pause TO!\n");
}
#endif
@@ -1576,7 +1578,7 @@ static void sam_txtimeout(int argc, uint32_t arg, ...)
{
struct sam_gmac_s *priv = (struct sam_gmac_s *)arg;
- nllerr("ERROR: Timeout!\n");
+ nerr("ERROR: Timeout!\n");
/* Then reset the hardware. Just take the interface down, then back
* up again.
@@ -1657,7 +1659,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Configure the GMAC interface for normal operation. */
- nllinfo("Initialize the GMAC\n");
+ ninfo("Initialize the GMAC\n");
sam_gmac_configure(priv);
/* Set the MAC address (should have been configured while we were down) */
@@ -1675,7 +1677,7 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_phyinit(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_phyinit failed: %d\n", ret);
+ nerr("ERROR: sam_phyinit failed: %d\n", ret);
return ret;
}
@@ -1685,7 +1687,7 @@ static int sam_ifup(struct net_driver_s *dev)
ret = sam_autonegotiate(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_autonegotiate failed: %d\n", ret);
+ nerr("ERROR: sam_autonegotiate failed: %d\n", ret);
return ret;
}
#else
@@ -1696,7 +1698,7 @@ static int sam_ifup(struct net_driver_s *dev)
/* Enable normal MAC operation */
- nllinfo("Enable normal operation\n");
+ ninfo("Enable normal operation\n");
/* Set and activate a timer process */
@@ -1780,7 +1782,7 @@ static int sam_txavail(struct net_driver_s *dev)
struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private;
irqstate_t flags;
- nllinfo("ifup: %d\n", priv->ifup);
+ ninfo("ifup: %d\n", priv->ifup);
/* Disable interrupts because this function may be called from interrupt
* level processing.
@@ -1958,8 +1960,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
- nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@@ -2032,8 +2034,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac)
unsigned int bit;
UNUSED(priv);
- nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
/* Calculate the 6-bit has table index */
@@ -2220,21 +2222,21 @@ static void sam_phydump(struct sam_gmac_s *priv)
sam_enablemdio(priv);
- nllinfo("GMII Registers (Address %02x)\n", priv->phyaddr);
+ ninfo("GMII Registers (Address %02x)\n", priv->phyaddr);
sam_phyread(priv, priv->phyaddr, GMII_MCR, &phyval);
- nllinfo(" MCR: %04x\n", phyval);
+ ninfo(" MCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_MSR, &phyval);
- nllinfo(" MSR: %04x\n", phyval);
+ ninfo(" MSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_ADVERTISE, &phyval);
- nllinfo(" ADVERTISE: %04x\n", phyval);
+ ninfo(" ADVERTISE: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_LPA, &phyval);
- nllinfo(" LPR: %04x\n", phyval);
+ ninfo(" LPR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_1000BTCR, &phyval);
- nllinfo(" 1000BTCR: %04x\n", phyval);
+ ninfo(" 1000BTCR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_1000BTSR, &phyval);
- nllinfo(" 1000BTSR: %04x\n", phyval);
+ ninfo(" 1000BTSR: %04x\n", phyval);
sam_phyread(priv, priv->phyaddr, GMII_ESTATUS, &phyval);
- nllinfo(" ESTATUS: %04x\n", phyval);
+ ninfo(" ESTATUS: %04x\n", phyval);
/* Disable management port */
@@ -2418,7 +2420,7 @@ static int sam_phyreset(struct sam_gmac_s *priv)
int timeout;
int ret;
- nllinfo(" sam_phyreset\n");
+ ninfo(" sam_phyreset\n");
/* Enable management port */
@@ -2429,7 +2431,7 @@ static int sam_phyreset(struct sam_gmac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, GMII_MCR, GMII_MCR_RESET);
if (ret < 0)
{
- nllerr("ERROR: sam_phywrite failed: %d\n", ret);
+ nerr("ERROR: sam_phywrite failed: %d\n", ret);
}
/* Wait for the PHY reset to complete */
@@ -2441,7 +2443,7 @@ static int sam_phyreset(struct sam_gmac_s *priv)
int result = sam_phyread(priv, priv->phyaddr, GMII_MCR, &mcr);
if (result < 0)
{
- nllerr("ERROR: Failed to read the MCR register: %d\n", ret);
+ nerr("ERROR: Failed to read the MCR register: %d\n", ret);
ret = result;
}
else if ((mcr & GMII_MCR_RESET) == 0)
@@ -2480,7 +2482,7 @@ static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr)
unsigned int offset;
int ret = -ESRCH;
- nllinfo("Find a valid PHY address\n");
+ ninfo("Find a valid PHY address\n");
/* Enable management port */
@@ -2501,8 +2503,8 @@ static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr)
else
{
- nllerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
- candidate, ret);
+ nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n",
+ candidate, ret);
for (offset = 0; offset < 32; offset++)
{
@@ -2523,7 +2525,7 @@ static int sam_phyfind(struct sam_gmac_s *priv, uint8_t *phyaddr)
if (ret == OK)
{
- nllinfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
+ ninfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate);
*phyaddr = candidate;
}
@@ -2563,7 +2565,7 @@ static int sam_phyread(struct sam_gmac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2578,7 +2580,7 @@ static int sam_phyread(struct sam_gmac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2618,7 +2620,7 @@ static int sam_phywrite(struct sam_gmac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2633,7 +2635,7 @@ static int sam_phywrite(struct sam_gmac_s *priv, uint8_t phyaddr,
ret = sam_phywait(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_phywait failed: %d\n", ret);
+ nerr("ERROR: sam_phywait failed: %d\n", ret);
return ret;
}
@@ -2679,35 +2681,35 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_PHYID1, &phyid1);
if (ret < 0)
{
- nllerr("ERROR: Failed to read PHYID1 register\n");
+ nerr("ERROR: Failed to read PHYID1 register\n");
goto errout;
}
- nllinfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
+ ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr);
/* Read the LS bits of the OUI from Pthe PHYID2 register */
ret = sam_phyread(priv, priv->phyaddr, GMII_PHYID2, &phyid2);
if (ret < 0)
{
- nllerr("ERROR: Failed to read PHYID2 register\n");
+ nerr("ERROR: Failed to read PHYID2 register\n");
goto errout;
}
- nllinfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
+ ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == GMII_OUI_MSB &&
(phyid2 & GMII_PHYID2_OUI_MASK) == GMII_OUI_LSB)
{
- nllinfo(" Vendor Model Number: %04x\n",
- (phyid2 & GMII_PHYID2_MODEL_MASK) >> GMII_PHYID2_MODEL_SHIFT);
- nllinfo(" Model Revision Number: %04x\n",
- (phyid2 & GMII_PHYID2_REV_MASK) >> GMII_PHYID2_REV_SHIFT);
+ ninfo(" Vendor Model Number: %04x\n",
+ (phyid2 & GMII_PHYID2_MODEL_MASK) >> GMII_PHYID2_MODEL_SHIFT);
+ ninfo(" Model Revision Number: %04x\n",
+ (phyid2 & GMII_PHYID2_REV_MASK) >> GMII_PHYID2_REV_SHIFT);
}
else
{
- nllerr("ERROR: PHY not recognized: PHYID1=%04x PHYID2=%04x\n",
- phyid1, phyid2);
+ nerr("ERROR: PHY not recognized: PHYID1=%04x PHYID2=%04x\n",
+ phyid1, phyid2);
}
#ifdef SAMA5_GMAC_PHY_KSZ90x1
@@ -2735,7 +2737,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, GMII_ADVERTISE, advertise);
if (ret < 0)
{
- nllerr("ERROR: Failed to write ADVERTISE register\n");
+ nerr("ERROR: Failed to write ADVERTISE register\n");
goto errout;
}
@@ -2746,7 +2748,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_1000BTCR, &btcr);
if (ret < 0)
{
- nllerr("ERROR: Failed to read 1000BTCR register: %d\n", ret);
+ nerr("ERROR: Failed to read 1000BTCR register: %d\n", ret);
goto errout;
}
@@ -2755,7 +2757,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, GMII_1000BTCR, btcr);
if (ret < 0)
{
- nllerr("ERROR: Failed to write 1000BTCR register: %d\n", ret);
+ nerr("ERROR: Failed to write 1000BTCR register: %d\n", ret);
goto errout;
}
@@ -2764,7 +2766,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_MCR, &phyval);
if (ret < 0)
{
- nllerr("ERROR: Failed to read MCR register: %d\n", ret);
+ nerr("ERROR: Failed to read MCR register: %d\n", ret);
goto errout;
}
@@ -2773,11 +2775,11 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phywrite(priv, priv->phyaddr, GMII_MCR, phyval);
if (ret < 0)
{
- nllerr("ERROR: Failed to write MCR register: %d\n", ret);
+ nerr("ERROR: Failed to write MCR register: %d\n", ret);
goto errout;
}
- nllinfo(" MCR: 0x%X\n", phyval);
+ ninfo(" MCR: 0x%X\n", phyval);
/* Wait for autonegotion to complete */
@@ -2787,7 +2789,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_MSR, &phyval);
if (ret < 0)
{
- nllerr("ERROR: Failed to read MSR register: %d\n", ret);
+ nerr("ERROR: Failed to read MSR register: %d\n", ret);
goto errout;
}
@@ -2797,7 +2799,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
{
/* Yes.. break out of the loop */
- nllinfo("AutoNegotiate complete\n");
+ ninfo("AutoNegotiate complete\n");
break;
}
@@ -2805,7 +2807,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
if (++timeout >= PHY_RETRY_MAX)
{
- nllerr("ERROR: TimeOut\n");
+ nerr("ERROR: TimeOut\n");
sam_phydump(priv);
ret = -ETIMEDOUT;
goto errout;
@@ -2822,7 +2824,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_1000BTSR, &btsr);
if (ret < 0)
{
- nllerr("ERROR: Failed to read 1000BTSR register: %d\n", ret);
+ nerr("ERROR: Failed to read 1000BTSR register: %d\n", ret);
goto errout;
}
@@ -2850,7 +2852,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
ret = sam_phyread(priv, priv->phyaddr, GMII_LPA, &lpa);
if (ret < 0)
{
- nllerr("ERROR: Failed to read LPA register: %d\n", ret);
+ nerr("ERROR: Failed to read LPA register: %d\n", ret);
goto errout;
}
@@ -2892,7 +2894,7 @@ static int sam_autonegotiate(struct sam_gmac_s *priv)
if (++timeout >= PHY_RETRY_MAX)
{
- nllerr("ERROR: TimeOut\n");
+ nerr("ERROR: TimeOut\n");
sam_phydump(priv);
ret = -ETIMEDOUT;
goto errout;
@@ -3065,7 +3067,7 @@ static int sam_phyinit(struct sam_gmac_s *priv)
ret = sam_phyfind(priv, &priv->phyaddr);
if (ret < 0)
{
- nllerr("ERROR: sam_phyfind failed: %d\n", ret);
+ nerr("ERROR: sam_phyfind failed: %d\n", ret);
return ret;
}
@@ -3324,11 +3326,11 @@ static void sam_macaddress(struct sam_gmac_s *priv)
struct net_driver_s *dev = &priv->dev;
uint32_t regval;
- nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
- dev->d_ifname,
- dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
- dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
- dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
+ ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ dev->d_ifname,
+ dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
+ dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
+ dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
/* Set the MAC address */
@@ -3436,7 +3438,7 @@ static int sam_gmac_configure(struct sam_gmac_s *priv)
{
uint32_t regval;
- nllinfo("Entry\n");
+ ninfo("Entry\n");
/* Enable clocking to the GMAC peripheral */
@@ -3556,6 +3558,9 @@ int sam_gmac_initialize(void)
/* Initialize the driver structure */
memset(priv, 0, sizeof(struct sam_gmac_s));
+#ifdef CONFIG_NET_MULTIBUFFER
+ priv->dev.d_buf = g_pktbuf; /* Single packet buffer */
+#endif
priv->dev.d_ifup = sam_ifup; /* I/F up (new IP address) callback */
priv->dev.d_ifdown = sam_ifdown; /* I/F down callback */
priv->dev.d_txavail = sam_txavail; /* New TX data callback */
@@ -3573,7 +3578,7 @@ int sam_gmac_initialize(void)
priv->txpoll = wd_create();
if (!priv->txpoll)
{
- nllerr("ERROR: Failed to create periodic poll timer\n");
+ nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout;
}
@@ -3581,7 +3586,7 @@ int sam_gmac_initialize(void)
priv->txtimeout = wd_create(); /* Create TX timeout timer */
if (!priv->txtimeout)
{
- nllerr("ERROR: Failed to create periodic poll timer\n");
+ nerr("ERROR: Failed to create periodic poll timer\n");
ret = -EAGAIN;
goto errout_with_txpoll;
}
@@ -3595,7 +3600,7 @@ int sam_gmac_initialize(void)
ret = sam_buffer_initialize(priv);
if (ret < 0)
{
- nllerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
+ nerr("ERROR: sam_buffer_initialize failed: %d\n", ret);
goto errout_with_txtimeout;
}
@@ -3606,7 +3611,7 @@ int sam_gmac_initialize(void)
ret = irq_attach(SAM_IRQ_GMAC, sam_gmac_interrupt);
if (ret < 0)
{
- nllerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_GMAC);
+ nerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_GMAC);
goto errout_with_buffers;
}
@@ -3619,7 +3624,7 @@ int sam_gmac_initialize(void)
ret = sam_ifdown(&priv->dev);
if (ret < 0)
{
- nllerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
+ nerr("ERROR: Failed to put the interface in the down state: %d\n", ret);
goto errout_with_buffers;
}
@@ -3631,7 +3636,7 @@ int sam_gmac_initialize(void)
return ret;
}
- nllerr("ERROR: netdev_register() failed: %d\n", ret);
+ nerr("ERROR: netdev_register() failed: %d\n", ret);
errout_with_buffers:
sam_buffer_free(priv);
diff --git a/arch/arm/src/sama5/sam_hsmci.c b/arch/arm/src/sama5/sam_hsmci.c
index db8054fe2d434edc90990bcf39d98f64fb959e69..2b4eb8361a31665ca2aff3c186d90ae3275139f3 100644
--- a/arch/arm/src/sama5/sam_hsmci.c
+++ b/arch/arm/src/sama5/sam_hsmci.c
@@ -1241,7 +1241,7 @@ static void sam_dmacallback(DMA_HANDLE handle, void *arg, int result)
if (result < 0)
{
wkupevent = (result == -ETIMEDOUT ? SDIOWAIT_TIMEOUT : SDIOWAIT_ERROR);
- fllerr("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent);
+ mcerr("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent);
/* sam_endtransfer will terminate the transfer and wait up the waiting
* client in this case.
@@ -1341,7 +1341,7 @@ static void sam_eventtimeout(int argc, uint32_t arg)
/* Yes.. wake up any waiting threads */
sam_endwait(priv, SDIOWAIT_TIMEOUT);
- fllerr("ERROR: Timeout\n");
+ mcerr("ERROR: Timeout\n");
}
}
@@ -1541,7 +1541,7 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv)
{
/* Yes.. Was it some kind of timeout error? */
- fllerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
+ mcerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending);
if ((pending & HSMCI_DATA_TIMEOUT_ERRORS) != 0)
{
/* Yes.. Terminate with a timeout. */
@@ -1613,8 +1613,8 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv)
{
/* Yes.. Was the error some kind of timeout? */
- fllinfo("ERROR: events: %08x SR: %08x\n",
- priv->cmdrmask, enabled);
+ mcerr("ERROR: events: %08x SR: %08x\n",
+ priv->cmdrmask, enabled);
if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
{
@@ -2094,7 +2094,7 @@ static int sam_sendcmd(FAR struct sdio_dev_s *dev,
/* Write the fully decorated command to CMDR */
- finfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
+ mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
sam_putreg(priv, regval, SAM_HSMCI_CMDR_OFFSET);
sam_cmdsample1(priv, SAMPLENDX_AFTER_CMDR);
return OK;
@@ -2816,7 +2816,7 @@ static void sam_callbackenable(FAR struct sdio_dev_s *dev,
{
struct sam_dev_s *priv = (struct sam_dev_s *)dev;
- finfo("eventset: %02x\n", eventset);
+ mcinfo("eventset: %02x\n", eventset);
DEBUGASSERT(priv != NULL);
priv->cbevents = eventset;
@@ -2852,7 +2852,7 @@ static int sam_registercallback(FAR struct sdio_dev_s *dev,
/* Disable callbacks and register this callback and is argument */
- finfo("Register %p(%p)\n", callback, arg);
+ mcinfo("Register %p(%p)\n", callback, arg);
DEBUGASSERT(priv != NULL);
priv->cbevents = 0;
@@ -3099,8 +3099,8 @@ static void sam_callback(void *arg)
/* Is a callback registered? */
DEBUGASSERT(priv != NULL);
- finfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
- priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
+ mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
+ priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
flags = enter_critical_section();
if (priv->callback)
@@ -3157,7 +3157,7 @@ static void sam_callback(void *arg)
lcderr("ERROR: Failed to cancel work: %d\n", ret);
}
- fllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
+ mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
ret = work_queue(LPWORK, &priv->cbwork, (worker_t)priv->callback,
priv->cbarg, 0);
if (ret < 0)
@@ -3327,8 +3327,8 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
return NULL;
}
- finfo("priv: %p base: %08x hsmci: %d dmac: %d pid: %d\n",
- priv, priv->base, priv->hsmci, dmac, pid);
+ mcinfo("priv: %p base: %08x hsmci: %d dmac: %d pid: %d\n",
+ priv, priv->base, priv->hsmci, dmac, pid);
/* Initialize the HSMCI slot structure */
@@ -3397,7 +3397,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
priv->cdstatus &= ~SDIO_STATUS_PRESENT;
}
- fllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
+ mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
/* Perform any requested callback if the status has changed */
@@ -3442,7 +3442,7 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
}
- finfo("cdstatus: %02x\n", priv->cdstatus);
+ mcinfo("cdstatus: %02x\n", priv->cdstatus);
leave_critical_section(flags);
}
diff --git a/arch/arm/src/sama5/sam_nand.c b/arch/arm/src/sama5/sam_nand.c
index f063f22fb2bfb165d39ff38c8604a0a2d21e3ba0..0e6757c073e4eb8a3c37610da101e13fcad48f24 100644
--- a/arch/arm/src/sama5/sam_nand.c
+++ b/arch/arm/src/sama5/sam_nand.c
@@ -999,7 +999,7 @@ static uint32_t nand_nfc_poll(void)
sr = nand_getreg(SAM_HSMC_SR);
#ifndef CONFIG_SAMA5_NAND_REGDEBUG
- // fllinfo("sr=%08x\n", sr);
+ // finfo("sr=%08x\n", sr);
#endif
/* When set to one, this XFRDONE indicates that the NFC has terminated
@@ -1065,7 +1065,7 @@ static int hsmc_interrupt(int irq, void *context)
uint32_t pending = sr & imr;
#ifndef CONFIG_SAMA5_NAND_REGDEBUG
- fllinfo("sr=%08x imr=%08x\n", sr, imr);
+ finfo("sr=%08x imr=%08x\n", sr, imr);
#endif
/* When set to one, this XFRDONE indicates that the NFC has terminated
diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c
index bd3ec0b233b009a4ddafaf29e0510b2c0f402f54..7d4533dca68907b26077edb006d0954b5f6526ac 100644
--- a/arch/arm/src/sama5/sam_ohci.c
+++ b/arch/arm/src/sama5/sam_ohci.c
@@ -3784,7 +3784,7 @@ static int sam_connect(struct usbhost_driver_s *drvr,
/* Set the connected/disconnected flag */
hport->connected = connected;
- ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+ uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
/* Report the connection event */
diff --git a/arch/arm/src/sama5/sam_oneshot.c b/arch/arm/src/sama5/sam_oneshot.c
index fc1985a45cc373e69f66934ba64a5fcb88b6ca9a..b883606982378068bcae46c1b6532106d5f88713 100644
--- a/arch/arm/src/sama5/sam_oneshot.c
+++ b/arch/arm/src/sama5/sam_oneshot.c
@@ -63,22 +63,6 @@
#ifdef CONFIG_SAMA5_ONESHOT
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -108,7 +92,7 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
oneshot_handler_t oneshot_handler;
void *oneshot_arg;
- tmrllinfo("Expired...\n");
+ tmrinfo("Expired...\n");
DEBUGASSERT(oneshot && oneshot->handler);
/* The clock was stopped, but not disabled when the RC match occurred.
@@ -128,7 +112,9 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr)
oneshot->handler = NULL;
oneshot_arg = (void *)oneshot->arg;
oneshot->arg = NULL;
+#ifdef CONFIG_SAMA5_FREERUN
oneshot->start_count = 0;
+#endif
oneshot_handler(oneshot_arg);
}
@@ -229,7 +215,36 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
oneshot->running = false;
oneshot->handler = NULL;
oneshot->arg = NULL;
+#ifdef CONFIG_SAMA5_FREERUN
oneshot->start_count = 0;
+#endif
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: sam_oneshot_max_delay
+ *
+ * Description:
+ * Return the maximum delay supported by the one shot timer (in
+ * microseconds).
+ *
+ * Input Parameters:
+ * oneshot Caller allocated instance of the oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * sam_oneshot_initialize();
+ * usec The location in which to return the maximum delay.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec)
+{
+ DEBUGASSERT(oneshot != NULL && usec != NULL);
+ *usec = (0xffffull * USEC_PER_SEC) / (uint64_t)sam_tc_divfreq(oneshot->tch);
return OK;
}
@@ -253,8 +268,10 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
*
****************************************************************************/
-int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- oneshot_handler_t handler, void *arg, const struct timespec *ts)
+int sam_oneshot_start(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun,
+ oneshot_handler_t handler, void *arg,
+ const struct timespec *ts)
{
uint64_t usec;
uint64_t regval;
@@ -311,6 +328,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
sam_tc_start(oneshot->tch);
+#ifdef CONFIG_SAMA5_FREERUN
/* The function sam_tc_start() starts the timer/counter by setting the
* bits TC_CCR_CLKEN and TC_CCR_SWTRG in the channel control register.
* The first one enables the timer/counter the latter performs an
@@ -329,7 +347,11 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* vanishes at least if compiled with no optimisation.
*/
- oneshot->start_count = sam_tc_getcounter(freerun->tch);
+ if (freerun != NULL)
+ {
+ oneshot->start_count = sam_tc_getcounter(freerun->tch);
+ }
+#endif
/* Enable interrupts. We should get the callback when the interrupt
* occurs.
@@ -365,8 +387,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
*
****************************************************************************/
-int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- struct timespec *ts)
+int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun, struct timespec *ts)
{
irqstate_t flags;
uint64_t usec;
@@ -407,16 +429,19 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free
count = sam_tc_getcounter(oneshot->tch);
rc = sam_tc_getregister(oneshot->tch, TC_REGC);
+#ifdef CONFIG_SAMA5_FREERUN
/* In the case the timer/counter was canceled very short after its start,
* the counter register can hold the wrong value (the value of the last
* run). To prevent this the counter value is set to zero if not at
* least on tick passed since the start of the timer/counter.
*/
- if (count > 0 && sam_tc_getcounter(freerun->tch) == oneshot->start_count)
+ if (count > 0 && freerun != NULL &&
+ sam_tc_getcounter(freerun->tch) == oneshot->start_count)
{
count = 0;
}
+#endif
/* Now we can disable the interrupt and stop the timer. */
diff --git a/arch/arm/src/sama5/sam_oneshot.h b/arch/arm/src/sama5/sam_oneshot.h
index 0443fcd693dbf62592dec20575d66466b814c502..15431882fc048fedb7e228f889d13fb0f5603156 100644
--- a/arch/arm/src/sama5/sam_oneshot.h
+++ b/arch/arm/src/sama5/sam_oneshot.h
@@ -46,7 +46,6 @@
#include
#include "sam_tc.h"
-#include "sam_freerun.h"
#ifdef CONFIG_SAMA5_ONESHOT
@@ -83,11 +82,13 @@ struct sam_oneshot_s
volatile oneshot_handler_t handler; /* Oneshot expiration callback */
volatile void *arg; /* The argument that will accompany
* the callback */
+#ifdef CONFIG_SAMA5_FREERUN
volatile uint32_t start_count; /* Stores the value of the freerun counter,
* at each start of the onshot timer. Is neccesary
* to find out if the onshot counter was updated
* correctly at the time of the call to
* sam_oneshot_cancel or not. */
+#endif
};
/****************************************************************************
@@ -130,6 +131,27 @@ extern "C"
int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
uint16_t resolution);
+/****************************************************************************
+ * Name: sam_oneshot_max_delay
+ *
+ * Description:
+ * Return the maximum delay supported by the one shot timer (in
+ * microseconds).
+ *
+ * Input Parameters:
+ * oneshot Caller allocated instance of the oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * sam_oneshot_initialize();
+ * usec The location in which to return the maximum delay.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec);
+
/****************************************************************************
* Name: sam_oneshot_start
*
@@ -142,7 +164,8 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
- * sam_freerun_initialize();
+ * sam_freerun_initialize(). May be NULL if there is no matching
+ * free-running timer.
* handler The function to call when when the oneshot timer expires.
* arg An opaque argument that will accompany the callback.
* ts Provides the duration of the one shot timer.
@@ -153,8 +176,11 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
*
****************************************************************************/
-int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- oneshot_handler_t handler, void *arg, const struct timespec *ts);
+struct sam_freerun_s;
+int sam_oneshot_start(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun,
+ oneshot_handler_t handler, void *arg,
+ const struct timespec *ts);
/****************************************************************************
* Name: sam_oneshot_cancel
@@ -171,7 +197,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
* sam_oneshot_initialize();
* freerun Caller allocated instance of the freerun state structure. This
* structure must have been previously initialized via a call to
- * sam_freerun_initialize();
+ * sam_freerun_initialize(). May be NULL if there is no matching
+ * free-running timer.
* ts The location in which to return the time remaining on the
* oneshot timer. A time of zero is returned if the timer is
* not running.
@@ -183,8 +210,9 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer
*
****************************************************************************/
-int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freerun,
- struct timespec *ts);
+struct sam_freerun_s;
+int sam_oneshot_cancel(struct sam_oneshot_s *oneshot,
+ struct sam_freerun_s *freerun, struct timespec *ts);
#undef EXTERN
#ifdef __cplusplus
diff --git a/arch/arm/src/sama5/sam_oneshot_lowerhalf.c b/arch/arm/src/sama5/sam_oneshot_lowerhalf.c
new file mode 100644
index 0000000000000000000000000000000000000000..e9737ea167d0c5a42c18ef5435fce5a9caaf7a14
--- /dev/null
+++ b/arch/arm/src/sama5/sam_oneshot_lowerhalf.c
@@ -0,0 +1,347 @@
+/****************************************************************************
+ * arch/arm/src/sam/sam_oneshot_lowerhalf.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "sam_oneshot.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure describes the state of the oneshot timer lower-half driver */
+
+struct sam_oneshot_lowerhalf_s
+{
+ /* This is the part of the lower half driver that is visible to the upper-
+ * half client of the driver. This must be the first thing in this
+ * structure so that pointers to struct oneshot_lowerhalf_s are cast
+ * compatible to struct sam_oneshot_lowerhalf_s and vice versa.
+ */
+
+ struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */
+
+ /* Private lower half data follows */
+
+ struct sam_oneshot_s oneshot; /* SAM-specific oneshot state */
+ oneshot_callback_t callback; /* internal handler that receives callback */
+ FAR void *arg; /* Argument that is passed to the handler */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static void sam_oneshot_handler(void *arg);
+
+static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts);
+static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback, FAR void *arg,
+ FAR const struct timespec *ts);
+static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Lower half operations */
+
+static const struct oneshot_operations_s g_oneshot_ops =
+{
+ .max_delay = sam_max_delay,
+ .start = sam_start,
+ .cancel = sam_cancel,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_oneshot_handler
+ *
+ * Description:
+ * Timer expiration handler
+ *
+ * Input Parameters:
+ * arg - Should be the same argument provided when sam_oneshot_start()
+ * was called.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void sam_oneshot_handler(void *arg)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)arg;
+ oneshot_callback_t callback;
+ FAR void *cbarg;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Perhaps the callback was nullified in a race condition with
+ * sam_cancel?
+ */
+
+ if (priv->callback)
+ {
+ /* Sample and nullify BEFORE executing callback (in case the callback
+ * restarts the oneshot).
+ */
+
+ callback = priv->callback;
+ cbarg = priv->arg;
+ priv->callback = NULL;
+ priv->arg = NULL;
+
+ /* Then perform the callback */
+
+ callback(&priv->lh, cbarg);
+ }
+}
+
+/****************************************************************************
+ * Name: sam_max_delay
+ *
+ * Description:
+ * Determine the maximum delay of the one-shot timer (in microseconds)
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the maxumum delay.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int sam_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)lower;
+ uint64_t usecs;
+ int ret;
+
+ DEBUGASSERT(priv != NULL && ts != NULL);
+ ret = sam_oneshot_max_delay(&priv->oneshot, &usecs);
+ if (ret >= 0)
+ {
+ uint64_t sec = usecs / 1000000;
+ usecs -= 1000000 * sec;
+
+ ts->tv_sec = (time_t)sec;
+ ts->tv_nsec = (long)(usecs * 1000);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: sam_start
+ *
+ * Description:
+ * Start the oneshot timer
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * handler The function to call when when the oneshot timer expires.
+ * arg An opaque argument that will accompany the callback.
+ * ts Provides the duration of the one shot timer.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int sam_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback, FAR void *arg,
+ FAR const struct timespec *ts)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)lower;
+ irqstate_t flags;
+ int ret;
+
+ DEBUGASSERT(priv != NULL && callback != NULL && ts != NULL);
+
+ /* Save the callback information and start the timer */
+
+ flags = enter_critical_section();
+ priv->callback = callback;
+ priv->arg = arg;
+ ret = sam_oneshot_start(&priv->oneshot, NULL,
+ sam_oneshot_handler, priv, ts);
+ leave_critical_section(flags);
+
+ if (ret < 0)
+ {
+ tmrerr("ERROR: sam_oneshot_start failed: %d\n", flags);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: sam_cancel
+ *
+ * Description:
+ * Cancel the oneshot timer and return the time remaining on the timer.
+ *
+ * NOTE: This function may execute at a high rate with no timer running (as
+ * when pre-emption is enabled and disabled).
+ *
+ * Input Parameters:
+ * lower Caller allocated instance of the oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the time remaining on the
+ * oneshot timer. A time of zero is returned if the timer is
+ * not running.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A call to up_timer_cancel() when
+ * the timer is not active should also return success; a negated errno
+ * value is returned on any failure.
+ *
+ ****************************************************************************/
+
+static int sam_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec *ts)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv =
+ (FAR struct sam_oneshot_lowerhalf_s *)lower;
+ irqstate_t flags;
+ int ret;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Cancel the timer */
+
+ flags = enter_critical_section();
+ ret = sam_oneshot_cancel(&priv->oneshot, NULL, ts);
+ priv->callback = NULL;
+ priv->arg = NULL;
+ leave_critical_section(flags);
+
+ if (ret < 0)
+ {
+ tmrerr("ERROR: sam_oneshot_cancel failed: %d\n", flags);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: oneshot_initialize
+ *
+ * Description:
+ * Initialize the oneshot timer and return a oneshot lower half driver
+ * instance.
+ *
+ * Input Parameters:
+ * chan Timer counter channel to be used.
+ * resolution The required resolution of the timer in units of
+ * microseconds. NOTE that the range is restricted to the
+ * range of uint16_t (excluding zero).
+ *
+ * Returned Value:
+ * On success, a non-NULL instance of the oneshot lower-half driver is
+ * returned. NULL is return on any failure.
+ *
+ ****************************************************************************/
+
+FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
+ uint16_t resolution)
+{
+ FAR struct sam_oneshot_lowerhalf_s *priv;
+ int ret;
+
+ /* Allocate an instance of the lower half driver */
+
+ priv = (FAR struct sam_oneshot_lowerhalf_s *)
+ kmm_zalloc(sizeof(struct sam_oneshot_lowerhalf_s));
+
+ if (priv == NULL)
+ {
+ tmrerr("ERROR: Failed to initialized state structure\n");
+ return NULL;
+ }
+
+ /* Initialize the lower-half driver structure */
+
+ priv->lh.ops = &g_oneshot_ops;
+
+ /* Initialize the contained SAM oneshot timer */
+
+ ret = sam_oneshot_initialize(&priv->oneshot, chan, resolution);
+ if (ret < 0)
+ {
+ tmrerr("ERROR: sam_oneshot_initialize failed: %d\n", ret);
+ kmm_free(priv);
+ return NULL;
+ }
+
+ return &priv->lh;
+}
diff --git a/arch/arm/src/sama5/sam_pwm.c b/arch/arm/src/sama5/sam_pwm.c
index 0de1d91dea0b7ac80bd3b585bcc2d7b7e8c206f4..d523da24a1c145da629252ff96ac7d4c66ee7c9a 100644
--- a/arch/arm/src/sama5/sam_pwm.c
+++ b/arch/arm/src/sama5/sam_pwm.c
@@ -47,7 +47,7 @@
#include
#include
-#include
+#include
#include "chip/sam_pinmap.h"
#include
diff --git a/arch/arm/src/sama5/sam_rtc.c b/arch/arm/src/sama5/sam_rtc.c
index d710ff711f62e0c1c05feddf07fcfb4939347fb8..e73e473b706a7f8e25676f08da7e994d883c4b37 100644
--- a/arch/arm/src/sama5/sam_rtc.c
+++ b/arch/arm/src/sama5/sam_rtc.c
@@ -265,7 +265,7 @@ static int rtc_interrupt(int irq, void *context)
ret = work_queue(LPWORK, &g_alarmwork, rtc_worker, NULL, 0);
if (ret < 0)
{
- rtcllerr("ERROR: work_queue failed: %d\n", ret);
+ rtcerr("ERROR: work_queue failed: %d\n", ret);
}
/* Disable any further alarm interrupts */
diff --git a/arch/arm/src/sama5/sam_ssc.c b/arch/arm/src/sama5/sam_ssc.c
index ff50c3988e88c7b7390717a970bece871a72228c..8e4e66a03272ccbd8b076de16787f4f286b75cba 100644
--- a/arch/arm/src/sama5/sam_ssc.c
+++ b/arch/arm/src/sama5/sam_ssc.c
@@ -847,12 +847,12 @@ static void ssc_dump_queue(sq_queue_t *queue)
if (!apb)
{
- i2sllinfo(" %p: No buffer\n", bfcontainer);
+ i2sinfo(" %p: No buffer\n", bfcontainer);
}
else
{
- i2sllinfo(" %p: buffer=%p nmaxbytes=%d nbytes=%d\n",
- bfcontainer, apb, apb->nmaxbytes, apb->nbytes);
+ i2sinfo(" %p: buffer=%p nmaxbytes=%d nbytes=%d\n",
+ bfcontainer, apb, apb->nmaxbytes, apb->nbytes);
}
}
}
@@ -862,12 +862,12 @@ static void ssc_dump_queues(struct sam_transport_s *xpt, const char *msg)
irqstate_t flags;
flags = enter_critical_section();
- i2sllinfo("%s\n", msg);
- i2sllinfo(" Pending:\n");
+ i2sinfo("%s\n", msg);
+ i2sinfo(" Pending:\n");
ssc_dump_queue(&xpt->pend);
- i2sllinfo(" Active:\n");
+ i2sinfo(" Active:\n");
ssc_dump_queue(&xpt->act);
- i2sllinfo(" Done:\n");
+ i2sinfo(" Done:\n");
ssc_dump_queue(&xpt->done);
leave_critical_section(flags);
}
@@ -1377,7 +1377,7 @@ static int ssc_rxdma_setup(struct sam_ssc_s *priv)
if (ret < 0)
{
- i2sllerr("ERROR: wd_start failed: %d\n", errno);
+ i2serr("ERROR: wd_start failed: %d\n", errno);
}
}
@@ -1565,7 +1565,7 @@ static void ssc_rx_schedule(struct sam_ssc_s *priv, int result)
ret = work_queue(HPWORK, &priv->rx.work, ssc_rx_worker, priv, 0);
if (ret != 0)
{
- i2sllerr("ERROR: Failed to queue RX work: %d\n", ret);
+ i2serr("ERROR: Failed to queue RX work: %d\n", ret);
}
}
}
@@ -1790,7 +1790,7 @@ static int ssc_txdma_setup(struct sam_ssc_s *priv)
if (ret < 0)
{
- i2sllerr("ERROR: wd_start failed: %d\n", errno);
+ i2serr("ERROR: wd_start failed: %d\n", errno);
}
}
@@ -1965,7 +1965,7 @@ static void ssc_tx_schedule(struct sam_ssc_s *priv, int result)
ret = work_queue(HPWORK, &priv->tx.work, ssc_tx_worker, priv, 0);
if (ret != 0)
{
- i2sllerr("ERROR: Failed to queue TX work: %d\n", ret);
+ i2serr("ERROR: Failed to queue TX work: %d\n", ret);
}
}
}
diff --git a/arch/arm/src/sama5/sam_tc.c b/arch/arm/src/sama5/sam_tc.c
index fc0bc9c8766e64978ff39f9ea77367dfad1aa365..7d8e19370cc64d87d4d653ade7d888d60055ffcd 100644
--- a/arch/arm/src/sama5/sam_tc.c
+++ b/arch/arm/src/sama5/sam_tc.c
@@ -562,7 +562,7 @@ static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr,
{
/* Yes... show how many times we did it */
- tminfo("...[Repeats %d times]...\n", tc->ntimes);
+ tmrinfo("...[Repeats %d times]...\n", tc->ntimes);
}
/* Save information about the new access */
@@ -597,7 +597,7 @@ static inline uint32_t sam_tc_getreg(struct sam_chan_s *chan,
#ifdef CONFIG_SAMA5_TC_REGDEBUG
if (sam_checkreg(tc, false, regaddr, regval))
{
- tminfo("%08x->%08x\n", regaddr, regval);
+ tmrinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@@ -621,7 +621,7 @@ static inline void sam_tc_putreg(struct sam_chan_s *chan, uint32_t regval,
#ifdef CONFIG_SAMA5_TC_REGDEBUG
if (sam_checkreg(tc, true, regaddr, regval))
{
- tminfo("%08x<-%08x\n", regaddr, regval);
+ tmrinfo("%08x<-%08x\n", regaddr, regval);
}
#endif
@@ -645,7 +645,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan,
#ifdef CONFIG_SAMA5_TC_REGDEBUG
if (sam_checkreg(chan->tc, false, regaddr, regval))
{
- tminfo("%08x->%08x\n", regaddr, regval);
+ tmrinfo("%08x->%08x\n", regaddr, regval);
}
#endif
@@ -668,7 +668,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset,
#ifdef CONFIG_SAMA5_TC_REGDEBUG
if (sam_checkreg(chan->tc, true, regaddr, regval))
{
- tminfo("%08x<-%08x\n", regaddr, regval);
+ tmrinfo("%08x<-%08x\n", regaddr, regval);
}
#endif
diff --git a/arch/arm/src/sama5/sam_tickless.c b/arch/arm/src/sama5/sam_tickless.c
index d3a1d34e011b0f5901cea7ea3ff8c05d3141bfdb..4ae30bf7185d09d66a9fac4afa4fd437b1f4637c 100644
--- a/arch/arm/src/sama5/sam_tickless.c
+++ b/arch/arm/src/sama5/sam_tickless.c
@@ -209,7 +209,7 @@ static struct sam_tickless_s g_tickless;
static void sam_oneshot_handler(void *arg)
{
- tmrllinfo("Expired...\n");
+ tmrinfo("Expired...\n");
sched_timer_expiration();
}
@@ -256,7 +256,7 @@ void up_timer_initialize(void)
CONFIG_USEC_PER_TICK);
if (ret < 0)
{
- tmrllerr("ERROR: sam_oneshot_initialize failed\n");
+ tmrerr("ERROR: sam_oneshot_initialize failed\n");
PANIC();
}
@@ -268,7 +268,7 @@ void up_timer_initialize(void)
ret = sam_oneshot_max_delay(&g_tickless.oneshot, &max_delay);
if (ret < 0)
{
- tmrllerr("ERROR: sam_oneshot_max_delay failed\n");
+ tmrerr("ERROR: sam_oneshot_max_delay failed\n");
PANIC();
}
@@ -292,7 +292,7 @@ void up_timer_initialize(void)
CONFIG_USEC_PER_TICK);
if (ret < 0)
{
- tmrllerr("ERROR: sam_freerun_initialize failed\n");
+ tmrerr("ERROR: sam_freerun_initialize failed\n");
PANIC();
}
diff --git a/arch/arm/src/sama5/sam_trng.c b/arch/arm/src/sama5/sam_trng.c
index a3eb102640e8fa881e727640623deaa61bc5884a..4c0f5ab1bcc6ee212546cbbac38c71da586fba8e 100644
--- a/arch/arm/src/sama5/sam_trng.c
+++ b/arch/arm/src/sama5/sam_trng.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/sama5/sam_trng.c
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Derives, in part, from Max Holtzberg's STM32 RNG Nuttx driver:
@@ -52,6 +52,8 @@
#include |